Hisilicon/PCIe: support multiple MSI target addresses
There might be multiple PCIe associated ITS in the system, so we change
PCD of MSI target address to a feature PCD and specify the addresses in
the code. If ITS is not supported by OS, MSI target address will be set
to GIC distributor.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
index 8659e29..8b10dbc 100644
--- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
@@ -51,9 +51,10 @@
gHisiTokenSpaceGuid.PcdPcieRootBridgeMask
gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P
gHisiTokenSpaceGuid.Pcdsoctype
- gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress
+ gArmTokenSpaceGuid.PcdGicDistributorBase
[FeaturePcd]
+ gHisiTokenSpaceGuid.PcdIsItsSupported
gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable
[depex]
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
index e58d87c..399155c 100644
--- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
@@ -903,12 +903,31 @@
}
}
+VOID SysRegWrite(UINT32 SocType, UINT32 HostBridgeNum, UINT32 Port, UINTN Reg, UINTN Value)
+{
+ if (SocType == 0x1610) {
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value);
+ } else {
+ //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE
+ //in the same hostbridge.
+ RegWrite(PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value);
+ }
+}
+
void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
{
UINT32 Value = 0;
+ UINT64 GicdSetSpiReg = PcdGet64 (PcdGicDistributorBase) + 0x40;
- RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11b4, PcdGet64 (PcdPcieMsiTargetAddress));
- RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c4, 0);
+ if (FeaturePcdGet (PcdIsItsSupported)) {
+ //PCIE_SYS_CTRL24_REG is MSI Low address register
+ //PCIE_SYS_CTRL28_REG is MSI High addres register
+ SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, PCIE_ITS_1610[HostBridgeNum][Port]);
+ SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, PCIE_ITS_1610[HostBridgeNum][Port] >> 32);
+ } else {
+ SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, GicdSetSpiReg);
+ SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, GicdSetSpiReg >> 32);
+ }
RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
Value |= (1 << 12);
RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec
index fca0b70..0faa100 100644
--- a/Chips/Hisilicon/HisiPkg.dec
+++ b/Chips/Hisilicon/HisiPkg.dec
@@ -267,10 +267,10 @@
gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0|UINT64|0x2110005d
gHisiTokenSpaceGuid.Pcdsoctype|0|UINT32|0x00000061
- gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0x0|UINT64|0x00000064
gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|0|UINT32|0x40000056
[PcdsFeatureFlag]
+ gHisiTokenSpaceGuid.PcdIsItsSupported|FALSE|BOOLEAN|0x00000065
gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|FALSE|BOOLEAN|0x00000066
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc
index a8e1995..fcb3ad7 100644
--- a/Platforms/Hisilicon/D03/D03.dsc
+++ b/Platforms/Hisilicon/D03/D03.dsc
@@ -111,6 +111,7 @@
## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
# It could be set FALSE to save size.
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+ gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE
[PcdsFixedAtBuild.common]
@@ -309,7 +310,6 @@
gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x40060000
gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x40060000
- gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0xc6010040
################################################################################
#
