commit e68b9b8bbfcfd47d687d2e460bce12f2877751ef
author Heyi Guo <heyi.guo@linaro.org> Tue Oct 18 14:33:45 2016 +0800
committer Leif Lindholm <leif.lindholm@linaro.org> Tue Nov 29 14:21:00 2016 +0000
tree 1bf0d481b46e8e22b72300f2549d7ce175d0cdf5
parent f578cdac71fa68687dfb8799fca59c29b17767a2

Hisilicon/PCIeInit: Remove unused function PciePortReset

The PciePortReset function is unused, so we remove it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c

diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
index 399155c..bd871d6 100644
--- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
@@ -573,44 +573,6 @@
 }

 

 

-EFI_STATUS PciePortReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)

-{

-    if(Port >= PCIE_MAX_PORT_NUM)

-    {

-        return EFI_INVALID_PARAMETER;

-    }

-

-

-    if(PcieIsLinkUp(soctype, HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])

-    {

-        (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port);

-    }

-

-    mPcieIntCfg.PortIsInitilized[Port] = FALSE;

-    mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;

-    mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;

-    mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;

-    ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));

-

-    if(Port <= 2)

-    {

-        RegWrite(pcie_subctrl_base[HostBridgeNum]+ PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);

-        MicroSecondDelay(0x1000);

-

-        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);

-        MicroSecondDelay(0x1000);

-    }

-    else

-    {

-        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);

-        MicroSecondDelay(0x1000);

-

-        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);

-        MicroSecondDelay(0x1000);

-    }

-    return EFI_SUCCESS;

-}

-

 EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)

 {

     UINT32 PortIndexInSicl;