| /* |
| * Memory setup for XYREF4415 board based on EXYNOS4 |
| * |
| * Copyright (C) 2014 Samsung Electronics |
| * |
| * See file CREDITS for list of people who contributed to this |
| * project. |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| * MA 02111-1307 USA |
| */ |
| |
| #ifndef __CMU_H__
|
| #define __CMU_H__
|
|
|
|
|
| static enum SYSC_CMU_REG
|
| {
|
|
|
| //LEFT 0x10034000
|
| rCLK_SRC_LEFTBUS = 0x10034200,
|
| rCLK_MUX_STAT_LEFTBUS = 0x10034400,
|
| rCLK_DIV_LEFTBUS = 0x10034500,
|
| rCLK_DIV_STAT_LEFTBUS = 0x10034600,
|
| rCLK_GATE_BUS_LEFTBUS = 0x10034700,
|
| rCLK_GATE_BUS_IMAGE = 0x10034730,
|
| rCLK_GATE_IP_LEFTBUS = 0x10034800,
|
| rCLK_GATE_IP_IMAGE = 0x10034930,
|
| rCLKOUT_CMU_LEFTBUS = 0x10034A00,
|
| rCLKOUT_CMU_LEFTBUS_DIV_STAT = 0x10034A04,
|
| rCMU_LEFTBUS_SPARE0 = 0x10036000,
|
| rCMU_LEFTBUS_SPARE1 = 0x10036004,
|
| rCMU_LEFTBUS_SPARE2 = 0x10036008,
|
| rCMU_LEFTBUS_SPARE3 = 0x1003600C,
|
| rCMU_LEFTBUS_SPARE4 = 0x10036010,
|
|
|
| //RIGHT 0x10038000
|
| rCLK_SRC_RIGHTBUS = 0x10038200,
|
| rCLK_MUX_STAT_RIGHTBUS = 0x10038400,
|
| rCLK_DIV_RIGHTBUS = 0x10038500,
|
| rCLK_DIV_STAT_RIGHTBUS = 0x10038600,
|
| rCLK_GATE_BUS_RIGHTBUS = 0x10038700,
|
| rCLK_GATE_BUS_PERIR = 0x10038760,
|
| rCLK_GATE_IP_RIGHTBUS = 0x10038800,
|
| rCLK_GATE_IP_PERIR = 0x10038960,
|
| rCLKOUT_CMU_RIGHTBUS = 0x10038A00,
|
| rCLKOUT_CMU_RIGHTBUS_DIV_STAT = 0x10038A04,
|
| rCMU_RIGHTBUS_SPARE0 = 0x1003A000,
|
| rCMU_RIGHTBUS_SPARE1 = 0x1003A004,
|
| rCMU_RIGHTBUS_SPARE2 = 0x1003A008,
|
| rCMU_RIGHTBUS_SPARE3 = 0x1003A00C,
|
| rCMU_RIGHTBUS_SPARE4 = 0x1003A010,
|
|
|
| //TOP 0x1003C000
|
| rEPLL_LOCK = 0x1003C010,
|
| rG3DPLL_LOCK = 0x1003C020,
|
| rDISPPLL_LOCK = 0x1003C030,
|
| rISPPLL_LOCK = 0x1003C040,
|
|
|
| rEPLL_CON0 = 0x1003C110,
|
| rEPLL_CON1 = 0x1003C114,
|
| rEPLL_CON2 = 0x1003C118,
|
| rG3D_PLL_CON0 = 0x1003C120,
|
| rG3D_PLL_CON1 = 0x1003C124,
|
| rG3D_PLL_CON2 = 0x1003C128,
|
| rISP_PLL_CON0 = 0x1003C130,
|
| rISP_PLL_CON1 = 0x1003C134,
|
| rISP_PLL_CON2 = 0x1003C138,
|
| rDISP_PLL_CON0 = 0x1003C140,
|
| rDISP_PLL_CON1 = 0x1003C144,
|
| rDISP_PLL_CON2 = 0x1003C148,
|
|
|
| rCLK_SRC_TOP0 = 0x1003C210,
|
| rCLK_SRC_TOP1 = 0x1003C214,
|
| rCLK_SRC_CAM0 = 0x1003C220,
|
| rCLK_SRC_TV = 0x1003C224,
|
| rCLK_SRC_MFC = 0x1003C228,
|
| rCLK_SRC_G3D = 0x1003C22C,
|
| rCLK_SRC_LCD = 0x1003C234,
|
| rCLK_SRC_ISP = 0x1003C238,
|
| rCLK_SRC_MAUDIO = 0x1003C23C,
|
| rCLK_SRC_FSYS = 0x1003C240,
|
| rCLK_SRC_PERIL0 = 0x1003C250,
|
| rCLK_SRC_PERIL1 = 0x1003C254,
|
| rCLK_SRC_CAM1 = 0x1003C258,
|
| rCLK_SRC_ISP0_T = 0x1003C25c,
|
| rCLK_SRC_ISP1_T = 0x1003C260,
|
|
|
| rCLK_SRC_MASK_TOP = 0x1003C310,
|
| rCLK_SRC_MASK_CAM0 = 0x1003C320,
|
| rCLK_SRC_MASK_TV = 0x1003C324,
|
| rCLK_SRC_MASK_LCD = 0x1003C334,
|
| rCLK_SRC_MASK_ISP = 0x1003C338,
|
| rCLK_SRC_MASK_MAUDIO = 0x1003C33C,
|
| rCLK_SRC_MASK_FSYS = 0x1003C340,
|
| rCLK_SRC_MASK_PERIL0 = 0x1003C350,
|
| rCLK_SRC_MASK_PERIL1 = 0x1003C354,
|
|
|
| rCLK_MUX_STAT_TOP0 = 0x1003C410,
|
| rCLK_MUX_STAT_TOP1 = 0x1003C414,
|
| rCLK_MUX_STAT_MFC = 0x1003C428,
|
| rCLK_MUX_STAT_G3D = 0x1003C42C,
|
| rCLK_MUX_STAT_CAM1 = 0x1003C458,
|
| rCLK_MUX_STAT_ISP0 = 0x1003C45c,
|
| rCLK_MUX_STAT_ISP1 = 0x1003C460,
|
|
|
| rCLK_DIV_TOP = 0x1003C510,
|
| rCLK_DIV_CAM0 = 0x1003C520,
|
| rCLK_DIV_TV = 0x1003C524,
|
| rCLK_DIV_MFC = 0x1003C528,
|
| rCLK_DIV_G3D = 0x1003C52C,
|
| rCLK_DIV_LCD = 0x1003C534,
|
| rCLK_DIV_ISP = 0x1003C538,
|
| rCLK_DIV_MAUDIO = 0x1003C53C,
|
| rCLK_DIV_FSYS0 = 0x1003C540,
|
| rCLK_DIV_FSYS1 = 0x1003C544,
|
| rCLK_DIV_FSYS2 = 0x1003C548,
|
| rCLK_DIV_FSYS3 = 0x1003C54C,
|
| rCLK_DIV_PERIL0 = 0x1003C550,
|
| rCLK_DIV_PERIL1 = 0x1003C554,
|
| rCLK_DIV_PERIL2 = 0x1003C558,
|
| rCLK_DIV_PERIL3 = 0x1003C55C,
|
| rCLK_DIV_PERIL4 = 0x1003C560,
|
| rCLK_DIV_PERIL5 = 0x1003C564,
|
| rCLK_DIV_CAM1 = 0x1003C568,
|
| rCLK_DIV_ISP1_T = 0x1003C56C,
|
| rCLK_DIV_ISP0_T = 0x1003C570,
|
| rCLKDIV2_RATIO = 0x1003C580,
|
|
|
| rCLK_DIV_STAT_TOP = 0x1003C610,
|
| rCLK_DIV_STAT_CAM0 = 0x1003C620,
|
| rCLK_DIV_STAT_TV = 0x1003C624,
|
| rCLK_DIV_STAT_MFC = 0x1003C628,
|
| rCLK_DIV_STAT_G3D = 0x1003C62C,
|
| rCLK_DIV_STAT_LCD = 0x1003C634,
|
| rCLK_DIV_STAT_ISP = 0x1003C638,
|
| rCLK_DIV_STAT_MAUDIO = 0x1003C63C,
|
| rCLK_DIV_STAT_FSYS0 = 0x1003C640,
|
| rCLK_DIV_STAT_FSYS1 = 0x1003C644,
|
| rCLK_DIV_STAT_FSYS2 = 0x1003C648,
|
| rCLK_DIV_STAT_FSYS3 = 0x1003C64C,
|
| rCLK_DIV_STAT_PERIL0 = 0x1003C650,
|
| rCLK_DIV_STAT_PERIL1 = 0x1003C654,
|
| rCLK_DIV_STAT_PERIL2 = 0x1003C658,
|
| rCLK_DIV_STAT_PERIL3 = 0x1003C65C,
|
| rCLK_DIV_STAT_PERIL4 = 0x1003C660,
|
| rCLK_DIV_STAT_PERIL5 = 0x1003C664,
|
| rCLK_DIV_STAT_CAM1 = 0x1003C668,
|
| rCLK_DIV_STAT_ISP1_T = 0x1003C66c,
|
| rCLK_DIV_STAT_ISP0_T = 0x1003C670,
|
|
|
| rCLKDIV2_STAT = 0x1003C680,
|
|
|
| rCLK_GATE_BUS_CAM0 = 0x1003C720,
|
| rCLK_GATE_BUS_TV = 0x1003C724,
|
| rCLK_GATE_BUS_MFC = 0x1003C728,
|
| rCLK_GATE_BUS_G3D = 0x1003C72C,
|
| rCLK_GATE_BUS_LCD = 0x1003C734,
|
| rCLK_GATE_BUS_CAM1 = 0x1003C738,
|
| rCLK_GATE_BUS_FSYS0 = 0x1003C740,
|
| rCLK_GATE_BUS_FSYS1 = 0x1003C744,
|
| rCLK_GATE_BUS_PERIL = 0x1003C750,
|
| rCLK_GATE_SCLK_CAM0 = 0x1003C820,
|
| rCLK_GATE_SCLK_TV = 0x1003C824,
|
| rCLK_GATE_SCLK_MFC = 0x1003C828,
|
| rCLK_GATE_SCLK_G3D = 0x1003C82C,
|
| rCLK_GATE_SCLK_LCD = 0x1003C834,
|
| rCLK_GATE_SCLK_ISP_T = 0x1003C838, |
| rCLK_GATE_SCLK_MAUDIO = 0x1003C83C,
|
| rCLK_GATE_SCLK_FSYS = 0x1003C840,
|
| rCLK_GATE_SCLK_PERIL = 0x1003C850,
|
| rCLK_GATE_IP_CAM = 0x1003C920,
|
| rCLK_GATE_IP_TV = 0x1003C924,
|
| rCLK_GATE_IP_MFC = 0x1003C928,
|
| rCLK_GATE_IP_G3D = 0x1003C92C,
|
| rCLK_GATE_IP_LCD = 0x1003C934,
|
| rCLK_GATE_IP_ISP = 0x1003C938, |
| rCLK_GATE_IP_MAUDIO = 0x1003C93C,
|
| rCLK_GATE_IP_FSYS = 0x1003C940,
|
| rCLK_GATE_IP_PERIL = 0x1003C950,
|
| rCLK_GATE_BLOCK = 0x1003C970,
|
|
|
| rCLKOUT_CMU_TOP = 0x1003CA00,
|
| rCLKOUT_CMU_TOP_DIV_STAT = 0x1003CA04,
|
| rCMU_TOP_SPARE0 = 0x1003E000,
|
| rCMU_TOP_SPARE1 = 0x1003E004,
|
| rCMU_TOP_SPARE2 = 0x1003E008,
|
| rCMU_TOP_SPARE3 = 0x1003E00C,
|
| rCMU_TOP_SPARE4 = 0x1003E010,
|
|
|
| //CPU 0x10044000
|
| rAPLL_LOCK = 0x10044000,
|
| rAPLL_CON0 = 0x10044100,
|
| rAPLL_CON1 = 0x10044104,
|
| rAPLL_CON2 = 0x10044108,
|
| rCLK_SRC_CPU = 0x10044200,
|
| rCLK_MUX_STAT_CPU = 0x10044400,
|
| rCLK_DIV_CPU0 = 0x10044500,
|
| rCLK_DIV_CPU1 = 0x10044504,
|
| rCLK_DIV_STAT_CPU0 = 0x10044600,
|
| rCLK_DIV_STAT_CPU1 = 0x10044604,
|
| rCLK_GATE_BUS_CPU = 0x10044700,
|
| rCLK_GATE_SCLK_CPU = 0x10044800,
|
| rCLK_GATE_IP_CPU = 0x10044900,
|
| rCLKOUT_CMU_CPU = 0x10044A00,
|
| rCLKOUT_CMU_CPU_DIV_STAT = 0x10044A04,
|
| rARMCLK_STOPCTRL = 0x10045000,
|
| rATCLK_STOPCTRL = 0x10045004,
|
| rARM_EMA_CTRL = 0x10045008,
|
| rARM_EMA_STATUS = 0x1004500C,
|
| rPARITYFAIL_STATUS = 0x10045010,
|
| rPARITYFAIL_CLEAR = 0x10045014,
|
| rPWR_CTRL = 0x10045020,
|
| rPWR_CTRL2 = 0x10045024,
|
| rAPLL_CON0_L8 = 0x10045100,
|
| rAPLL_CON0_L7 = 0x10045104,
|
| rAPLL_CON0_L6 = 0x10045108,
|
| rAPLL_CON0_L5 = 0x1004510C,
|
| rAPLL_CON0_L4 = 0x10045110,
|
| rAPLL_CON0_L3 = 0x10045114,
|
| rAPLL_CON0_L2 = 0x10045118,
|
| rAPLL_CON0_L1 = 0x1004511C,
|
| rIEM_CONTROL = 0x10045120,
|
| rAPLL_CON1_L8 = 0x10045200,
|
| rAPLL_CON1_L7 = 0x10045204,
|
| rAPLL_CON1_L6 = 0x10045208,
|
| rAPLL_CON1_L5 = 0x1004520C,
|
| rAPLL_CON1_L4 = 0x10045210,
|
| rAPLL_CON1_L3 = 0x10045214,
|
| rAPLL_CON1_L2 = 0x10045218,
|
| rAPLL_CON1_L1 = 0x1004521C,
|
| rCLKDIV_IEM_L8 = 0x10045300,
|
| rCLKDIV_IEM_L7 = 0x10045304,
|
| rCLKDIV_IEM_L6 = 0x10045308,
|
| rCLKDIV_IEM_L5 = 0x1004530C,
|
| rCLKDIV_IEM_L4 = 0x10045310,
|
| rCLKDIV_IEM_L3 = 0x10045314,
|
| rCLKDIV_IEM_L2 = 0x10045318,
|
| rCLKDIV_IEM_L1 = 0x1004531C,
|
| rL2_STATUS = 0x10045400,
|
| rCPU_STATUS = 0x10045410,
|
| rPTM_STATUS = 0x10045420,
|
| rCMU_CPU_SPARE0 = 0x10046000,
|
| rCMU_CPU_SPARE1 = 0x10046004,
|
| rCMU_CPU_SPARE2 = 0x10046008,
|
| rCMU_CPU_SPARE3 = 0x1004600C,
|
| rCMU_CPU_SPARE4 = 0x10046010,
|
|
|
| #if 0 //Carmen
|
| //ISP 0x10048000
|
| rCLK_DIV_ISP0 = 0x10048300,
|
| rCLK_DIV_ISP1 = 0x10048304,
|
| rCLK_DIV_STAT_ISP0 = 0x10048400,
|
| rCLK_DIV_STAT_ISP1 = 0x10048404,
|
| rCLK_GATE_BUS_ISP0 = 0x10048700,
|
| rCLK_GATE_BUS_ISP1 = 0x10048704,
|
| rCLK_GATE_BUS_ISP2 = 0x10048708,
|
| rCLK_GATE_BUS_ISP3 = 0x1004870C,
|
| rCLK_GATE_IP_ISP0 = 0x10048800,
|
| rCLK_GATE_IP_ISP1 = 0x10048804,
|
| rCLK_GATE_SCLK_ISP = 0x10048900,
|
| rCLKOUT_CMU_ISP = 0x10048A00,
|
| rCLKOUT_CMU_ISP_DIV_STAT = 0x10048A04,
|
| rCMU_ISP_SPARE0 = 0x10048B00,
|
| rCMU_ISP_SPARE1 = 0x10048B04,
|
| rCMU_ISP_SPARE2 = 0x10048B08,
|
| rCMU_ISP_SPARE3 = 0x10048B0C,
|
| #endif
|
| //ISP0 0x12060000
|
| rCLK_SRC_ISP0 = 0x12060200,
|
| rCLK_SRC_MASK_ISP0 = 0x12060300,
|
| rCLK_SRC_STAT_ISP0 = 0x12060400,
|
| rCLK_DIV_ISP0 = 0x12060500,
|
| rCLK_DIV_ISP0_SUB0 = 0x12060504,
|
| rCLK_DIV_STAT_ISP0 = 0x12060600,
|
| rCLK_DIV_STAT_ISP0_SUB0 = 0x12060604,
|
| rCLK_GATE_ISP0_SUB0 = 0x12060700,
|
| rCLK_GATE_ISP0_SUB1 = 0x12060704,
|
| rCLK_GATE_ISP0_SUB2 = 0x12060708,
|
| rCLK_GATE_ISP0_SUB3 = 0x1206070c,
|
| rCLK_GATE_ISP0_SUB4 = 0x12060710,
|
| rCLK_GATE_SCLK_ISP0_SUB0 = 0x12060800,
|
| rCLK_GATE_SCLK_ISP0_SUB1 = 0x12060804,
|
| rCLK_GATE_IP_ISP0_SUB0 = 0x12060900,
|
| rCLK_GATE_IP_ISP0_SUB1 = 0x12060904,
|
| rCLK_GATE_IP_ISP0_SUB2 = 0x12060908,
|
| rCLK_GATE_IP_ISP0_SUB3 = 0x1206090c,
|
| rCLK_GATE_IP_ISP0_SUB4 = 0x12060910,
|
| rCLKOUT_CMU_ISP0 = 0x12060A00,
|
| rCLKOUT_CMU_ISP0_DIV_STAT = 0x12060A04,
|
| rCMU_ISP0_SPARE0 = 0x12060B00,
|
| rCMU_ISP0_SPARE1 = 0x12060B04,
|
| rCMU_ISP0_SPARE2 = 0x12060B08,
|
| rCMU_ISP0_SPARE3 = 0x12060B0c,
|
|
|
| //ISP1 0x12070000
|
| rCLK_SRC_ISP1 = 0x12070200,
|
| rCLK_SRC_MASK_ISP1 = 0x12070300,
|
| rCLK_SRC_STAT_ISP1 = 0x12070400,
|
| rCLK_DIV_ISP1 = 0x12070500,
|
| rCLK_DIV_STAT_ISP1 = 0x12070600,
|
| rCLK_GATE_ISP1_SUB0 = 0x12070700,
|
| rCLK_GATE_ISP1_SUB1 = 0x12070704,
|
| rCLK_GATE_SCLK_ISP1_SUB0 = 0x12070800,
|
| rCLK_GATE_SCLK_ISP1_SUB1 = 0x12070804,
|
| rCLK_GATE_IP_ISP1_SUB0 = 0x12070900,
|
| rCLK_GATE_IP_ISP1_SUB1 = 0x12070904,
|
| rCLKOUT_CMU_ISP1 = 0x12070A00,
|
| rCLKOUT_CMU_ISP1_DIV_STAT = 0x12070A04,
|
| rCMU_ISP1_SPARE0 = 0x12070B00,
|
| rCMU_ISP1_SPARE1 = 0x12070B04,
|
| rCMU_ISP1_SPARE2 = 0x12070B08,
|
| rCMU_ISP1_SPARE3 = 0x12070B0c,
|
|
|
| //DMC(CORE_L) 0x105C0000
|
| rMPLL_LOCK = 0x105c0008,
|
| rMPLL_CON0 = 0x105c0108,
|
| rMPLL_CON1 = 0x105c010C,
|
| rMPLL_CON2 = 0x105c0110,
|
| rBPLL_LOCK = 0x105c0118,
|
| rBPLL_CON0 = 0x105c0218,
|
| rBPLL_CON1 = 0x105c021C,
|
| rBPLL_CON2 = 0x105c0220,
|
| rCLK_SRC_DMC = 0x105c0300,
|
| rCLK_MUX_STAT_DMC = 0x105c0400,
|
| rCLK_DIV_DYN_FREQ_SCALE = 0x105c0500,
|
| rCLK_DIV_DMC1 = 0x105c0504,
|
| rCLK_DIV_STAT_DMC0 = 0x105c0600,
|
| rCLK_DIV_STAT_DMC1 = 0x105c0604,
|
| rCLK_GATE_BUS_DMC0 = 0x105c0700,
|
| rCLK_GATE_BUS_DMC1 = 0x105c0704,
|
| rCLK_GATE_SCLK_DMC = 0x105c0800,
|
| rCLK_GATE_IP_DMC0 = 0x105c0900,
|
| rCLK_GATE_IP_DMC1 = 0x105c0904,
|
| rCLKOUT_CMU_DMC = 0x105c0A00,
|
| rCLKOUT_CMU_DMC_DIV_STAT = 0x105c0A04,
|
| // rDMC_FREQ_CTRL = 0x105c1090,
|
| rDMC_PAUSE_CTRL = 0x105c1094,
|
| rDDR_PHY_LOCK_CTRL = 0x105c1098,
|
| // rMIF_SEMAPHORE0 = 0x105c2000,
|
| // rMIF_SEMAPHORE1 = 0x105c2004,
|
| // rMIF_SEMAPHORE2 = 0x105c2008,
|
| // rCMU_CORE_SPARE0 = 0x105c200C,
|
| // rCMU_CORE_SPARE1 = 0x105c2010,
|
| rCMU_DMC_SPARE0 = 0x105c2000,
|
| rCMU_DMC_SPARE1 = 0x105c2004,
|
| // rDIVDMC_RATIO_DYN_CLK_GATE_CON = 0x105c3000,
|
|
|
| //ACP(CORE_R) 0x10450000
|
| rCLK_SRC_ACP = 0x10450300,
|
| rCLK_SRC_MASK_ACP = 0x10450304,
|
| rCLK_MUX_STAT_ACP0 = 0x10450400,
|
| rCLK_MUX_STAT_ACP1 = 0x10450404,
|
| rCLK_DIV_ACP0 = 0x10450500,
|
| rCLK_DIV_ACP1 = 0x10450504,
|
| rCLK_DIV_STAT_ACP0 = 0x10450600,
|
| rCLK_DIV_STAT_ACP1 = 0x10450604,
|
| rCLK_GATE_BUS_ACP0 = 0x10450700,
|
| rCLK_GATE_BUS_ACP1 = 0x10450704,
|
| rCLK_GATE_SCLK_ACP = 0x10450800,
|
| rCLK_GATE_IP_ACP0 = 0x10450900,
|
| rCLK_GATE_IP_ACP1 = 0x10450904,
|
| rCLKOUT_CMU_ACP = 0x10450A00,
|
| rCLKOUT_CMU_ACP_DIV_STAT = 0x10450A04,
|
| // rDCGIDX_MAP0 = 0x10451000,
|
| // rDCGIDX_MAP1 = 0x10451004,
|
| // rDCGIDX_MAP2 = 0x10451008,
|
| // rDCGPERF_MAP0 = 0x10451020,
|
| // rDCGPERF_MAP1 = 0x10451024,
|
| // rDVCIDX_MAP = 0x10451040,
|
| // rFREQ_CPU = 0x10451060,
|
| // rFREQ_DPM = 0x10451064,
|
| // rDVSEMCLK_EN = 0x10451080,
|
| // rMAXPERF = 0x10451084,
|
| rCMU_ACP_SPARE0 = 0x10452000,
|
| rCMU_ACP_SPARE1 = 0x10452004,
|
| rCMU_ACP_SPARE2 = 0x10452008,
|
| rCMU_ACP_SPARE3 = 0x1045200C,
|
| rCMU_ACP_SPARE4 = 0x10452010,
|
|
|
| };
|
|
|
| #define rPMU_DEBUG_CLKOUT (SYSC_PMU_BASE + 0x0A00)
|
|
|
|
|
|
|
| void CMU_Init(u32 nARMCLK);
|
| void CMU_InitForMif(u32 uMemClk);
|
|
|
| #endif //__CMU_H__
|
|
|
