| /* |
| * Copyright (c) 2011 Intel Corporation. All Rights Reserved. |
| * Copyright (c) Imagination Technologies Limited, UK |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation the rights to use, copy, modify, merge, publish, |
| * distribute, sub license, and/or sell copies of the Software, and to |
| * permit persons to whom the Software is furnished to do so, subject to |
| * the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial portions |
| * of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| |
| /* Register CR_IMG_MVEA_SRST */ |
| #define MVEA_CR_IMG_MVEA_SRST 0x0000 |
| #define MASK_MVEA_CR_IMG_MVEA_SPE_SOFT_RESET 0x00000001 |
| #define SHIFT_MVEA_CR_IMG_MVEA_SPE_SOFT_RESET 0 |
| #define REGNUM_MVEA_CR_IMG_MVEA_SPE_SOFT_RESET 0x0000 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_IPE_SOFT_RESET 0x00000002 |
| #define SHIFT_MVEA_CR_IMG_MVEA_IPE_SOFT_RESET 1 |
| #define REGNUM_MVEA_CR_IMG_MVEA_IPE_SOFT_RESET 0x0000 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_CMPRS_SOFT_RESET 0x00000004 |
| #define SHIFT_MVEA_CR_IMG_MVEA_CMPRS_SOFT_RESET 2 |
| #define REGNUM_MVEA_CR_IMG_MVEA_CMPRS_SOFT_RESET 0x0000 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_JMCOMP_SOFT_RESET 0x00000008 |
| #define SHIFT_MVEA_CR_IMG_MVEA_JMCOMP_SOFT_RESET 3 |
| #define REGNUM_MVEA_CR_IMG_MVEA_JMCOMP_SOFT_RESET 0x0000 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_CMC_SOFT_RESET 0x00000010 |
| #define SHIFT_MVEA_CR_IMG_MVEA_CMC_SOFT_RESET 4 |
| #define REGNUM_MVEA_CR_IMG_MVEA_CMC_SOFT_RESET 0x0000 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_DCF_SOFT_RESET 0x00000020 |
| #define SHIFT_MVEA_CR_IMG_MVEA_DCF_SOFT_RESET 5 |
| #define REGNUM_MVEA_CR_IMG_MVEA_DCF_SOFT_RESET 0x0000 |
| |
| /* Register CR_IMG_MVEA_INTSTAT */ |
| #define MVEA_CR_IMG_MVEA_INTSTAT 0x0004 |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_SPE_DONE 0x00000001 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_SPE_DONE 0 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_SPE_DONE 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_IPE_DONE 0x00000002 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_IPE_DONE 1 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_IPE_DONE 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_CMPRS_DONE 0x00000004 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_CMPRS_DONE 2 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_CMPRS_DONE 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_JMCOMP_DONE 0x00000008 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_JMCOMP_DONE 3 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_JMCOMP_DONE 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_EDMA_DONE 0x00000010 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_EDMA_DONE 4 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_EDMA_DONE 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_TDMA_DONE 0x00000020 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_TDMA_DONE 5 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_TDMA_DONE 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_DEB_DONE 0x00000040 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_DEB_DONE 6 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_DEB_DONE 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_VLC_DONE 0x00000080 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_VLC_DONE 7 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_VLC_DONE 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_SOFTWARE0 0x00000100 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_SOFTWARE0 8 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_SOFTWARE0 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_SOFTWARE1 0x00000200 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_SOFTWARE1 9 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_SOFTWARE1 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_DCF_EMPTY 0x00000400 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_DCF_EMPTY 10 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_DCF_EMPTY 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_SEQ_START 0x00000800 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_SEQ_START 11 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_SEQ_START 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_SEQ_DONE 0x00001000 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_SEQ_DONE 12 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_SEQ_DONE 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_COMBINED 0x40000000 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_COMBINED 30 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_COMBINED 0x0004 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTS_MASTER 0x80000000 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTS_MASTER 31 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTS_MASTER 0x0004 |
| |
| /* Register CR_IMG_MVEA_INTENAB */ |
| #define MVEA_CR_IMG_MVEA_INTENAB 0x0008 |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_SPE_DONE 0x00000001 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_SPE_DONE 0 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_SPE_DONE 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_IPE_DONE 0x00000002 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_IPE_DONE 1 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_IPE_DONE 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_CMPRS_DONE 0x00000004 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_CMPRS_DONE 2 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_CMPRS_DONE 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_JMCOMP_DONE 0x00000008 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_JMCOMP_DONE 3 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_JMCOMP_DONE 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_EDMA_DONE 0x00000010 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_EDMA_DONE 4 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_EDMA_DONE 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_TDMA_DONE 0x00000020 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_TDMA_DONE 5 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_TDMA_DONE 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_DEB_DONE 0x00000040 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_DEB_DONE 6 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_DEB_DONE 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_VLC_DONE 0x00000080 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_VLC_DONE 7 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_VLC_DONE 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_SOFTWARE0 0x00000100 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_SOFTWARE0 8 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_SOFTWARE0 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_SOFTWARE1 0x00000200 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_SOFTWARE1 9 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_SOFTWARE1 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_DCF_EMPTY 0x00000400 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_DCF_EMPTY 10 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_DCF_EMPTY 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_SEQ_START 0x00000800 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_SEQ_START 11 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_SEQ_START 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_SEQ_DONE 0x00001000 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_SEQ_DONE 12 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_SEQ_DONE 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_COMBINED 0x40000000 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_COMBINED 30 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_COMBINED 0x0008 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTEN_MASTER 0x80000000 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_MASTER 31 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_MASTER 0x0008 |
| |
| /* Register CR_IMG_MVEA_INTCLEAR */ |
| #define MVEA_CR_IMG_MVEA_INTCLEAR 0x000C |
| #define MASK_MVEA_CR_IMG_MVEA_INTCLR_SPE_DONE 0x00000001 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_SPE_DONE 0 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_SPE_DONE 0x000C |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCLR_IPE_DONE 0x00000002 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_IPE_DONE 1 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_IPE_DONE 0x000C |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCLR_CMPRS_DONE 0x00000004 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_CMPRS_DONE 2 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_CMPRS_DONE 0x000C |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCLR_JMCOMP_DONE 0x00000008 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_JMCOMP_DONE 3 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_JMCOMP_DONE 0x000C |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCLR_EDMA_DONE 0x00000010 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_EDMA_DONE 4 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_EDMA_DONE 0x000C |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCLR_TDMA_DONE 0x00000020 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_TDMA_DONE 5 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_TDMA_DONE 0x000C |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCLR_DEB_DONE 0x00000040 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_DEB_DONE 6 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_DEB_DONE 0x000C |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCLR_VLC_DONE 0x00000080 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_VLC_DONE 7 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_VLC_DONE 0x000C |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCLR_SOFTWARE0 0x00000100 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_SOFTWARE0 8 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_SOFTWARE0 0x000C |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCLR_SOFTWARE1 0x00000200 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_SOFTWARE1 9 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_SOFTWARE1 0x000C |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCLR_DCF_EMPTY 0x00000400 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_DCF_EMPTY 10 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_DCF_EMPTY 0x000C |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCLR_SEQ_START 0x00000800 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_SEQ_START 11 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_SEQ_START 0x000C |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCLR_SEQ_DONE 0x00001000 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_SEQ_DONE 12 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_SEQ_DONE 0x000C |
| |
| /* Register CR_IMG_MVEA_INT_COMB_SEL */ |
| #define MVEA_CR_IMG_MVEA_INT_COMB_SEL 0x0010 |
| #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_SPE_DONE 0x00000001 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_SPE_DONE 0 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_SPE_DONE 0x0010 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_IPE_DONE 0x00000002 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_IPE_DONE 1 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_IPE_DONE 0x0010 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_CMPRS_DONE 0x00000004 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_CMPRS_DONE 2 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_CMPRS_DONE 0x0010 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_JMCOMP_DONE 0x00000008 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_JMCOMP_DONE 3 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_JMCOMP_DONE 0x0010 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_EDMA_DONE 0x00000010 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_EDMA_DONE 4 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_EDMA_DONE 0x0010 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_TDMA_DONE 0x00000020 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_TDMA_DONE 5 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_TDMA_DONE 0x0010 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_DEB_DONE 0x00000040 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_DEB_DONE 6 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_DEB_DONE 0x0010 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_VLC_DONE 0x00000080 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_VLC_DONE 7 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_VLC_DONE 0x0010 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_SOFTWARE0 0x00000100 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_SOFTWARE0 8 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_SOFTWARE0 0x0010 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_SOFTWARE1 0x00000200 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_SOFTWARE1 9 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_SOFTWARE1 0x0010 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_DCF_EMPTY 0x00000400 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_DCF_EMPTY 10 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_DCF_EMPTY 0x0010 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_SEQ_START 0x00000800 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_SEQ_START 11 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_SEQ_START 0x0010 |
| |
| #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_SEQ_DONE 0x00001000 |
| #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_SEQ_DONE 12 |
| #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_SEQ_DONE 0x0010 |
| |
| /* Register CR_MVEA_START */ |
| #define MVEA_CR_MVEA_START 0x0014 |
| #define MASK_MVEA_CR_MVEA_SPE_START 0x00000001 |
| #define SHIFT_MVEA_CR_MVEA_SPE_START 0 |
| #define REGNUM_MVEA_CR_MVEA_SPE_START 0x0014 |
| |
| #define MASK_MVEA_CR_MVEA_IPE_START 0x00000002 |
| #define SHIFT_MVEA_CR_MVEA_IPE_START 1 |
| #define REGNUM_MVEA_CR_MVEA_IPE_START 0x0014 |
| |
| #define MASK_MVEA_CR_MVEA_CMPRS_START 0x00000004 |
| #define SHIFT_MVEA_CR_MVEA_CMPRS_START 2 |
| #define REGNUM_MVEA_CR_MVEA_CMPRS_START 0x0014 |
| |
| #define MASK_MVEA_CR_MVEA_JMCOMP_START 0x00000008 |
| #define SHIFT_MVEA_CR_MVEA_JMCOMP_START 3 |
| #define REGNUM_MVEA_CR_MVEA_JMCOMP_START 0x0014 |
| |
| #define MASK_MVEA_CR_MVEA_DEB_START 0x00000040 |
| #define SHIFT_MVEA_CR_MVEA_DEB_START 6 |
| #define REGNUM_MVEA_CR_MVEA_DEB_START 0x0014 |
| |
| #define MASK_MVEA_CR_MVEA_VLC_START 0x00000080 |
| #define SHIFT_MVEA_CR_MVEA_VLC_START 7 |
| #define REGNUM_MVEA_CR_MVEA_VLC_START 0x0014 |
| |
| /* Register CR_MVEA_BUSY */ |
| #define MVEA_CR_MVEA_BUSY 0x0018 |
| #define MASK_MVEA_CR_MVEA_SPE_BUSY 0x00000001 |
| #define SHIFT_MVEA_CR_MVEA_SPE_BUSY 0 |
| #define REGNUM_MVEA_CR_MVEA_SPE_BUSY 0x0018 |
| |
| #define MASK_MVEA_CR_MVEA_IPE_BUSY 0x00000002 |
| #define SHIFT_MVEA_CR_MVEA_IPE_BUSY 1 |
| #define REGNUM_MVEA_CR_MVEA_IPE_BUSY 0x0018 |
| |
| #define MASK_MVEA_CR_MVEA_CMPRS_BUSY 0x00000004 |
| #define SHIFT_MVEA_CR_MVEA_CMPRS_BUSY 2 |
| #define REGNUM_MVEA_CR_MVEA_CMPRS_BUSY 0x0018 |
| |
| #define MASK_MVEA_CR_MVEA_JMCOMP_BUSY 0x00000008 |
| #define SHIFT_MVEA_CR_MVEA_JMCOMP_BUSY 3 |
| #define REGNUM_MVEA_CR_MVEA_JMCOMP_BUSY 0x0018 |
| |
| #define MASK_MVEA_CR_MVEA_EDMA_BUSY 0x00000010 |
| #define SHIFT_MVEA_CR_MVEA_EDMA_BUSY 4 |
| #define REGNUM_MVEA_CR_MVEA_EDMA_BUSY 0x0018 |
| |
| #define MASK_MVEA_CR_MVEA_TDMA_BUSY 0x00000020 |
| #define SHIFT_MVEA_CR_MVEA_TDMA_BUSY 5 |
| #define REGNUM_MVEA_CR_MVEA_TDMA_BUSY 0x0018 |
| |
| #define MASK_MVEA_CR_MVEA_DEB_BUSY 0x00000040 |
| #define SHIFT_MVEA_CR_MVEA_DEB_BUSY 6 |
| #define REGNUM_MVEA_CR_MVEA_DEB_BUSY 0x0018 |
| |
| #define MASK_MVEA_CR_MVEA_VLC_BUSY 0x00000080 |
| #define SHIFT_MVEA_CR_MVEA_VLC_BUSY 7 |
| #define REGNUM_MVEA_CR_MVEA_VLC_BUSY 0x0018 |
| |
| #define MASK_MVEA_CR_MVEA_SPE_LRB_BUSY 0x00000100 |
| #define SHIFT_MVEA_CR_MVEA_SPE_LRB_BUSY 8 |
| #define REGNUM_MVEA_CR_MVEA_SPE_LRB_BUSY 0x0018 |
| |
| /* Register CR_MVEA_DMACMDFIFO_WAIT */ |
| #define MVEA_CR_MVEA_DMACMDFIFO_WAIT 0x001C |
| #define MASK_MVEA_CR_MVEA_DCF_WAIT_SPE 0x00000001 |
| #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_SPE 0 |
| #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_SPE 0x001C |
| |
| #define MASK_MVEA_CR_MVEA_DCF_WAIT_IPE 0x00000002 |
| #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_IPE 1 |
| #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_IPE 0x001C |
| |
| #define MASK_MVEA_CR_MVEA_DCF_WAIT_CMPRS 0x00000004 |
| #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_CMPRS 2 |
| #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_CMPRS 0x001C |
| |
| #define MASK_MVEA_CR_MVEA_DCF_WAIT_JMCOMP 0x00000008 |
| #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_JMCOMP 3 |
| #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_JMCOMP 0x001C |
| |
| #define MASK_MVEA_CR_MVEA_DCF_WAIT_EDMA 0x00000010 |
| #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_EDMA 4 |
| #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_EDMA 0x001C |
| |
| #define MASK_MVEA_CR_MVEA_DCF_WAIT_TDMA 0x00000020 |
| #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_TDMA 5 |
| #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_TDMA 0x001C |
| |
| #define MASK_MVEA_CR_MVEA_DCF_WAIT_SW0 0x00000040 |
| #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_SW0 6 |
| #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_SW0 0x001C |
| |
| #define MASK_MVEA_CR_MVEA_DCF_WAIT_SW1 0x00000080 |
| #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_SW1 7 |
| #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_SW1 0x001C |
| |
| /* Register CR_MVEA_DMACMDFIFO_STATUS */ |
| #define MVEA_CR_MVEA_DMACMDFIFO_STATUS 0x0020 |
| #define MASK_MVEA_CR_MVEA_DCF_SPACE 0x0000001F |
| #define SHIFT_MVEA_CR_MVEA_DCF_SPACE 0 |
| #define REGNUM_MVEA_CR_MVEA_DCF_SPACE 0x0020 |
| |
| #define MASK_MVEA_CR_MVEA_DCF_EMPTY 0x00000100 |
| #define SHIFT_MVEA_CR_MVEA_DCF_EMPTY 8 |
| #define REGNUM_MVEA_CR_MVEA_DCF_EMPTY 0x0020 |
| |
| /* Register CR_MVEA_AUTO_CLOCK_GATING */ |
| #define MVEA_CR_MVEA_AUTO_CLOCK_GATING 0x0024 |
| #define MASK_MVEA_CR_MVEA_SPE_AUTO_CLK_GATE 0x00000001 |
| #define SHIFT_MVEA_CR_MVEA_SPE_AUTO_CLK_GATE 0 |
| #define REGNUM_MVEA_CR_MVEA_SPE_AUTO_CLK_GATE 0x0024 |
| |
| #define MASK_MVEA_CR_MVEA_IPE_AUTO_CLK_GATE 0x00000002 |
| #define SHIFT_MVEA_CR_MVEA_IPE_AUTO_CLK_GATE 1 |
| #define REGNUM_MVEA_CR_MVEA_IPE_AUTO_CLK_GATE 0x0024 |
| |
| #define MASK_MVEA_CR_MVEA_CMPRS_AUTO_CLK_GATE 0x00000004 |
| #define SHIFT_MVEA_CR_MVEA_CMPRS_AUTO_CLK_GATE 2 |
| #define REGNUM_MVEA_CR_MVEA_CMPRS_AUTO_CLK_GATE 0x0024 |
| |
| #define MASK_MVEA_CR_MVEA_JMCOMP_AUTO_CLK_GATE 0x00000008 |
| #define SHIFT_MVEA_CR_MVEA_JMCOMP_AUTO_CLK_GATE 3 |
| #define REGNUM_MVEA_CR_MVEA_JMCOMP_AUTO_CLK_GATE 0x0024 |
| |
| /* Register CR_MVEA_MAN_CLOCK_GATING */ |
| #define MVEA_CR_MVEA_MAN_CLOCK_GATING 0x0028 |
| #define MASK_MVEA_CR_MVEA_SPE_MAN_CLK_GATE 0x00000001 |
| #define SHIFT_MVEA_CR_MVEA_SPE_MAN_CLK_GATE 0 |
| #define REGNUM_MVEA_CR_MVEA_SPE_MAN_CLK_GATE 0x0028 |
| |
| #define MASK_MVEA_CR_MVEA_IPE_MAN_CLK_GATE 0x00000002 |
| #define SHIFT_MVEA_CR_MVEA_IPE_MAN_CLK_GATE 1 |
| #define REGNUM_MVEA_CR_MVEA_IPE_MAN_CLK_GATE 0x0028 |
| |
| #define MASK_MVEA_CR_MVEA_CMPRS_MAN_CLK_GATE 0x00000004 |
| #define SHIFT_MVEA_CR_MVEA_CMPRS_MAN_CLK_GATE 2 |
| #define REGNUM_MVEA_CR_MVEA_CMPRS_MAN_CLK_GATE 0x0028 |
| |
| #define MASK_MVEA_CR_MVEA_JMCOMP_MAN_CLK_GATE 0x00000008 |
| #define SHIFT_MVEA_CR_MVEA_JMCOMP_MAN_CLK_GATE 3 |
| #define REGNUM_MVEA_CR_MVEA_JMCOMP_MAN_CLK_GATE 0x0028 |
| |
| #define MASK_MVEA_CR_MVEA_CMC_MAN_CLK_GATE 0x00000010 |
| #define SHIFT_MVEA_CR_MVEA_CMC_MAN_CLK_GATE 4 |
| #define REGNUM_MVEA_CR_MVEA_CMC_MAN_CLK_GATE 0x0028 |
| |
| /* Register CR_TOPAZ_MB_PERFORMANCE_RESULT */ |
| #define MVEA_CR_TOPAZ_MB_PERFORMANCE_RESULT 0x002C |
| #define MASK_MVEA_CR_TOPAZ_MB_PERFORMANCE_RESULT 0x0000FFFF |
| #define SHIFT_MVEA_CR_TOPAZ_MB_PERFORMANCE_RESULT 0 |
| #define REGNUM_MVEA_CR_TOPAZ_MB_PERFORMANCE_RESULT 0x002C |
| |
| /* Register CR_TOPAZ_MB_PERFORMANCE_MB_NUMBER */ |
| #define MVEA_CR_TOPAZ_MB_PERFORMANCE_MB_NUMBER 0x0030 |
| #define MASK_MVEA_CR_TOPAZ_MB_PERFORMANCE_MB_NUMBER 0x003FFFFF |
| #define SHIFT_MVEA_CR_TOPAZ_MB_PERFORMANCE_MB_NUMBER 0 |
| #define REGNUM_MVEA_CR_TOPAZ_MB_PERFORMANCE_MB_NUMBER 0x0030 |
| |
| /* Register CR_TOPAZ_HW_MB_PERFORMANCE_RESULT */ |
| #define MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_RESULT 0x0034 |
| #define MASK_MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_RESULT 0x0000FFFF |
| #define SHIFT_MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_RESULT 0 |
| #define REGNUM_MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_RESULT 0x0034 |
| |
| /* Register CR_TOPAZ_HW_MB_PERFORMANCE_MB_NUMBER */ |
| #define MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_MB_NUMBER 0x0038 |
| #define MASK_MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_MB_NUMBER 0x003FFFFF |
| #define SHIFT_MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_MB_NUMBER 0 |
| #define REGNUM_MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_MB_NUMBER 0x0038 |
| |
| /* Register CR_CMC_ESB_DIAGNOSTICS */ |
| #define MVEA_CR_CMC_ESB_DIAGNOSTICS 0x0100 |
| #define MASK_MVEA_CR_CMC_ESB_DIAGNOSTICS1 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_CMC_ESB_DIAGNOSTICS1 0 |
| #define REGNUM_MVEA_CR_CMC_ESB_DIAGNOSTICS1 0x0100 |
| |
| /* Register CR_CMC_DMA_DIAGNOSTICS */ |
| #define MVEA_CR_CMC_DMA_DIAGNOSTICS 0x0104 |
| #define MASK_MVEA_CR_CMC_DMA_DIAGNOSTICS 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_CMC_DMA_DIAGNOSTICS 0 |
| #define REGNUM_MVEA_CR_CMC_DMA_DIAGNOSTICS 0x0104 |
| |
| /* Register CR_CMC_SIGNATURE_ENC_MEM_WDATA */ |
| #define MVEA_CR_CMC_SIGNATURE_ENC_MEM_WDATA 0x0108 |
| #define MASK_MVEA_CR_CMC_SIGNATURE_ENC_MEM_WDATA 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_CMC_SIGNATURE_ENC_MEM_WDATA 0 |
| #define REGNUM_MVEA_CR_CMC_SIGNATURE_ENC_MEM_WDATA 0x0108 |
| |
| /* Register CR_CMC_SIGNATURE_ENC_MEM_ADDR */ |
| #define MVEA_CR_CMC_SIGNATURE_ENC_MEM_ADDR 0x010C |
| #define MASK_MVEA_CR_CMC_SIGNATURE_ENC_MEM_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_CMC_SIGNATURE_ENC_MEM_ADDR 0 |
| #define REGNUM_MVEA_CR_CMC_SIGNATURE_ENC_MEM_ADDR 0x010C |
| |
| /* Register CR_CMC_PROC_ESB_ACCESS */ |
| #define MVEA_CR_CMC_PROC_ESB_ACCESS 0x011C |
| #define MASK_MVEA_CR_CMC_PROC_ESB_REGION_NUMBER 0x0000001F |
| #define SHIFT_MVEA_CR_CMC_PROC_ESB_REGION_NUMBER 0 |
| #define REGNUM_MVEA_CR_CMC_PROC_ESB_REGION_NUMBER 0x011C |
| |
| /* Register CR_CMC_LRB_LOGICAL_OFFSET */ |
| #define MVEA_CR_CMC_LRB_LOGICAL_OFFSET 0x012C |
| #define MASK_MVEA_CR_CMC_LRB_LOGICAL_OFFSET 0x0000001F |
| #define SHIFT_MVEA_CR_CMC_LRB_LOGICAL_OFFSET 0 |
| #define REGNUM_MVEA_CR_CMC_LRB_LOGICAL_OFFSET 0x012C |
| |
| /* Register CR_SEQUENCER_SETUP */ |
| #define MVEA_CR_SEQUENCER_SETUP 0x0130 |
| #define MASK_MVEA_CR_FIRMWARE_DONE 0x00000001 |
| #define SHIFT_MVEA_CR_FIRMWARE_DONE 0 |
| #define REGNUM_MVEA_CR_FIRMWARE_DONE 0x0130 |
| |
| #define MASK_MVEA_CR_FIRMWARE_ROW_SETUP_DONE 0x00000010 |
| #define SHIFT_MVEA_CR_FIRMWARE_ROW_SETUP_DONE 4 |
| #define REGNUM_MVEA_CR_FIRMWARE_ROW_SETUP_DONE 0x0130 |
| |
| #define MASK_MVEA_CR_CONTROL_UPDATE 0x00000100 |
| #define SHIFT_MVEA_CR_CONTROL_UPDATE 8 |
| #define REGNUM_MVEA_CR_CONTROL_UPDATE 0x0130 |
| |
| #define MASK_MVEA_CR_STATUS_UPDATE 0x00001000 |
| #define SHIFT_MVEA_CR_STATUS_UPDATE 12 |
| #define REGNUM_MVEA_CR_STATUS_UPDATE 0x0130 |
| |
| /* Register CR_SEQUENCER_CONTROL */ |
| #define MVEA_CR_SEQUENCER_CONTROL 0x0134 |
| #define MASK_MVEA_CR_IPE_ENABLE 0x00000001 |
| #define SHIFT_MVEA_CR_IPE_ENABLE 0 |
| #define REGNUM_MVEA_CR_IPE_ENABLE 0x0134 |
| |
| #define MASK_MVEA_CR_SPE_ENABLE 0x00000002 |
| #define SHIFT_MVEA_CR_SPE_ENABLE 1 |
| #define REGNUM_MVEA_CR_SPE_ENABLE 0x0134 |
| |
| #define MASK_MVEA_CR_CMPRS_ENABLE 0x00000004 |
| #define SHIFT_MVEA_CR_CMPRS_ENABLE 2 |
| #define REGNUM_MVEA_CR_CMPRS_ENABLE 0x0134 |
| |
| #define MASK_MVEA_CR_JMCOMP_ENABLE 0x00000008 |
| #define SHIFT_MVEA_CR_JMCOMP_ENABLE 3 |
| #define REGNUM_MVEA_CR_JMCOMP_ENABLE 0x0134 |
| |
| #define MASK_MVEA_CR_VLC_ENABLE 0x00000010 |
| #define SHIFT_MVEA_CR_VLC_ENABLE 4 |
| #define REGNUM_MVEA_CR_VLC_ENABLE 0x0134 |
| |
| #define MASK_MVEA_CR_DB_ENABLE 0x00000020 |
| #define SHIFT_MVEA_CR_DB_ENABLE 5 |
| #define REGNUM_MVEA_CR_DB_ENABLE 0x0134 |
| |
| #define MASK_MVEA_CR_DMA_ABOVE_PIX_IN_EN 0x00000100 |
| #define SHIFT_MVEA_CR_DMA_ABOVE_PIX_IN_EN 8 |
| #define REGNUM_MVEA_CR_DMA_ABOVE_PIX_IN_EN 0x0134 |
| |
| #define MASK_MVEA_CR_DMA_ABOVE_PIX_OUT_EN 0x00000200 |
| #define SHIFT_MVEA_CR_DMA_ABOVE_PIX_OUT_EN 9 |
| #define REGNUM_MVEA_CR_DMA_ABOVE_PIX_OUT_EN 0x0134 |
| |
| #define MASK_MVEA_CR_DMA_ABOVE_PARAMS_IN_EN 0x00000400 |
| #define SHIFT_MVEA_CR_DMA_ABOVE_PARAMS_IN_EN 10 |
| #define REGNUM_MVEA_CR_DMA_ABOVE_PARAMS_IN_EN 0x0134 |
| |
| #define MASK_MVEA_CR_DMA_ABOVE_PARAMS_OUT_EN 0x00000800 |
| #define SHIFT_MVEA_CR_DMA_ABOVE_PARAMS_OUT_EN 11 |
| #define REGNUM_MVEA_CR_DMA_ABOVE_PARAMS_OUT_EN 0x0134 |
| |
| #define MASK_MVEA_CR_DMA_CURR_MB_IN_EN 0x00001000 |
| #define SHIFT_MVEA_CR_DMA_CURR_MB_IN_EN 12 |
| #define REGNUM_MVEA_CR_DMA_CURR_MB_IN_EN 0x0134 |
| |
| #define MASK_MVEA_CR_DMA_RECON_OUT_EN 0x00002000 |
| #define SHIFT_MVEA_CR_DMA_RECON_OUT_EN 13 |
| #define REGNUM_MVEA_CR_DMA_RECON_OUT_EN 0x0134 |
| |
| #define MASK_MVEA_CR_DMA_BELOW_OUT_EN 0x00004000 |
| #define SHIFT_MVEA_CR_DMA_BELOW_OUT_EN 14 |
| #define REGNUM_MVEA_CR_DMA_BELOW_OUT_EN 0x0134 |
| |
| #define MASK_MVEA_CR_DMA_BELOW1_IN_EN 0x00008000 |
| #define SHIFT_MVEA_CR_DMA_BELOW1_IN_EN 15 |
| #define REGNUM_MVEA_CR_DMA_BELOW1_IN_EN 0x0134 |
| |
| #define MASK_MVEA_CR_DMA_BELOW2_IN_EN 0x00010000 |
| #define SHIFT_MVEA_CR_DMA_BELOW2_IN_EN 16 |
| #define REGNUM_MVEA_CR_DMA_BELOW2_IN_EN 0x0134 |
| |
| #define MASK_MVEA_CR_DMA_CURR_PARAMS_IN_EN 0x00020000 |
| #define SHIFT_MVEA_CR_DMA_CURR_PARAMS_IN_EN 17 |
| #define REGNUM_MVEA_CR_DMA_CURR_PARAMS_IN_EN 0x0134 |
| |
| #define MASK_MVEA_CR_DMA_LRB0 0x00040000 |
| #define SHIFT_MVEA_CR_DMA_LRB0 18 |
| #define REGNUM_MVEA_CR_DMA_LRB0 0x0134 |
| |
| #define MASK_MVEA_CR_DMA_LRB1 0x00080000 |
| #define SHIFT_MVEA_CR_DMA_LRB1 19 |
| #define REGNUM_MVEA_CR_DMA_LRB1 0x0134 |
| |
| #define MASK_MVEA_CR_MB_NO_PER_ROW 0x0FF00000 |
| #define SHIFT_MVEA_CR_MB_NO_PER_ROW 20 |
| #define REGNUM_MVEA_CR_MB_NO_PER_ROW 0x0134 |
| |
| #define MASK_MVEA_CR_CURR_UV_INTERLEAVED 0x10000000 |
| #define SHIFT_MVEA_CR_CURR_UV_INTERLEAVED 28 |
| #define REGNUM_MVEA_CR_CURR_UV_INTERLEAVED 0x0134 |
| |
| #define MASK_MVEA_CR_START_OF_SLICE 0x20000000 |
| #define SHIFT_MVEA_CR_START_OF_SLICE 29 |
| #define REGNUM_MVEA_CR_START_OF_SLICE 0x0134 |
| |
| #define MASK_MVEA_CR_DB_FLUSH 0x40000000 |
| #define SHIFT_MVEA_CR_DB_FLUSH 30 |
| #define REGNUM_MVEA_CR_DB_FLUSH 0x0134 |
| |
| #define MASK_MVEA_CR_SEQUENCER_ENABLE 0x80000000 |
| #define SHIFT_MVEA_CR_SEQUENCER_ENABLE 31 |
| #define REGNUM_MVEA_CR_SEQUENCER_ENABLE 0x0134 |
| |
| /* Register CR_CURR_MB_Y_ROW_ADDR */ |
| #define MVEA_CR_CURR_MB_Y_ROW_ADDR 0x0138 |
| #define MASK_MVEA_CR_CURR_MB_Y_ROW_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_CURR_MB_Y_ROW_ADDR 0 |
| #define REGNUM_MVEA_CR_CURR_MB_Y_ROW_ADDR 0x0138 |
| |
| /* Register CR_CURR_MB_U_ROW_ADDR */ |
| #define MVEA_CR_CURR_MB_U_ROW_ADDR 0x013C |
| #define MASK_MVEA_CR_CURR_MB_U_ROW_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_CURR_MB_U_ROW_ADDR 0 |
| #define REGNUM_MVEA_CR_CURR_MB_U_ROW_ADDR 0x013C |
| |
| /* Register CR_CURR_MB_V_ROW_ADDR */ |
| #define MVEA_CR_CURR_MB_V_ROW_ADDR 0x0140 |
| #define MASK_MVEA_CR_CURR_MB_V_ROW_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_CURR_MB_V_ROW_ADDR 0 |
| #define REGNUM_MVEA_CR_CURR_MB_V_ROW_ADDR 0x0140 |
| |
| /* Register CR_CURR_MB_Y_ROW_STRIDE */ |
| #define MVEA_CR_CURR_MB_Y_ROW_STRIDE 0x0144 |
| #define MASK_MVEA_CR_CURR_MB_Y_ROW_OFFSET 0x0000FFFF |
| #define SHIFT_MVEA_CR_CURR_MB_Y_ROW_OFFSET 0 |
| #define REGNUM_MVEA_CR_CURR_MB_Y_ROW_OFFSET 0x0144 |
| |
| /* Register CR_CURR_MB_UV_ROW_STRIDE */ |
| #define MVEA_CR_CURR_MB_UV_ROW_STRIDE 0x0148 |
| #define MASK_MVEA_CR_CURR_MB_V_ROW_OFFSET 0x0000FFFF |
| #define SHIFT_MVEA_CR_CURR_MB_V_ROW_OFFSET 0 |
| #define REGNUM_MVEA_CR_CURR_MB_V_ROW_OFFSET 0x0148 |
| |
| #define MASK_MVEA_CR_CURR_MB_U_ROW_OFFSET 0xFFFF0000 |
| #define SHIFT_MVEA_CR_CURR_MB_U_ROW_OFFSET 16 |
| #define REGNUM_MVEA_CR_CURR_MB_U_ROW_OFFSET 0x0148 |
| |
| /* Register CR_REF_Y_ROW_ADDR */ |
| #define MVEA_CR_REF_Y_ROW_ADDR 0x014C |
| #define MASK_MVEA_CR_REF_Y_ROW_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_REF_Y_ROW_ADDR 0 |
| #define REGNUM_MVEA_CR_REF_Y_ROW_ADDR 0x014C |
| |
| /* Register CR_REF_UV_ROW_ADDR */ |
| #define MVEA_CR_REF_UV_ROW_ADDR 0x0150 |
| #define MASK_MVEA_CR_REF_UV_ROW_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_REF_UV_ROW_ADDR 0 |
| #define REGNUM_MVEA_CR_REF_UV_ROW_ADDR 0x0150 |
| |
| /* Register CR_REF_ROW_STRIDE */ |
| #define MVEA_CR_REF_ROW_STRIDE 0x0154 |
| #define MASK_MVEA_CR_REF_UV_ROW_OFFSET 0x0000FFFF |
| #define SHIFT_MVEA_CR_REF_UV_ROW_OFFSET 0 |
| #define REGNUM_MVEA_CR_REF_UV_ROW_OFFSET 0x0154 |
| |
| #define MASK_MVEA_CR_REF_Y_ROW_OFFSET 0xFFFF0000 |
| #define SHIFT_MVEA_CR_REF_Y_ROW_OFFSET 16 |
| #define REGNUM_MVEA_CR_REF_Y_ROW_OFFSET 0x0154 |
| |
| /* Register CR_ABOVE_PIX_Y_ROW_IN_ADDR */ |
| #define MVEA_CR_ABOVE_PIX_Y_ROW_IN_ADDR 0x0158 |
| #define MASK_MVEA_CR_ABOVE_PIX_Y_ROW_IN_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_ABOVE_PIX_Y_ROW_IN_ADDR 0 |
| #define REGNUM_MVEA_CR_ABOVE_PIX_Y_ROW_IN_ADDR 0x0158 |
| |
| /* Register CR_ABOVE_PIX_UV_ROW_IN_ADDR */ |
| #define MVEA_CR_ABOVE_PIX_UV_ROW_IN_ADDR 0x015C |
| #define MASK_MVEA_CR_ABOVE_PIX_UV_ROW_IN_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_ABOVE_PIX_UV_ROW_IN_ADDR 0 |
| #define REGNUM_MVEA_CR_ABOVE_PIX_UV_ROW_IN_ADDR 0x015C |
| |
| /* Register CR_RECON_Y_ROW_ADDR */ |
| #define MVEA_CR_RECON_Y_ROW_ADDR 0x0160 |
| #define MASK_MVEA_CR_RECON_Y_ROW_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_RECON_Y_ROW_ADDR 0 |
| #define REGNUM_MVEA_CR_RECON_Y_ROW_ADDR 0x0160 |
| |
| /* Register CR_RECON_UV_ROW_ADDR */ |
| #define MVEA_CR_RECON_UV_ROW_ADDR 0x0164 |
| #define MASK_MVEA_CR_RECON_UV_ROW_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_RECON_UV_ROW_ADDR 0 |
| #define REGNUM_MVEA_CR_RECON_UV_ROW_ADDR 0x0164 |
| |
| /* Register CR_ABOVE_PARAM_ADDR */ |
| #define MVEA_CR_ABOVE_PARAM_ADDR 0x0168 |
| #define MASK_MVEA_CR_ABOVE_PARAM_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_ABOVE_PARAM_ADDR 0 |
| #define REGNUM_MVEA_CR_ABOVE_PARAM_ADDR 0x0168 |
| |
| /* Register CR_CURR_PARAM_ADDR */ |
| #define MVEA_CR_CURR_PARAM_ADDR 0x016C |
| #define MASK_MVEA_CR_CURR_PARAM_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_CURR_PARAM_ADDR 0 |
| #define REGNUM_MVEA_CR_CURR_PARAM_ADDR 0x016C |
| |
| /* Register CR_BELOW_PARAM_IN_ADDR */ |
| #define MVEA_CR_BELOW_PARAM_IN_ADDR 0x0170 |
| #define MASK_MVEA_CR_BELOW_PARAM_IN_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_BELOW_PARAM_IN_ADDR 0 |
| #define REGNUM_MVEA_CR_BELOW_PARAM_IN_ADDR 0x0170 |
| |
| /* Register CR_LRB_LOAD */ |
| #define MVEA_CR_LRB_LOAD 0x0174 |
| #define MASK_MVEA_CR_LRB_LOAD_MB_NO_0 0x0000000F |
| #define SHIFT_MVEA_CR_LRB_LOAD_MB_NO_0 0 |
| #define REGNUM_MVEA_CR_LRB_LOAD_MB_NO_0 0x0174 |
| |
| #define MASK_MVEA_CR_LRB_LOAD_MB_NO_1 0x000000F0 |
| #define SHIFT_MVEA_CR_LRB_LOAD_MB_NO_1 4 |
| #define REGNUM_MVEA_CR_LRB_LOAD_MB_NO_1 0x0174 |
| |
| #define MASK_MVEA_CR_LRB_LOAD_Y_OFFSET 0x00000F00 |
| #define SHIFT_MVEA_CR_LRB_LOAD_Y_OFFSET 8 |
| #define REGNUM_MVEA_CR_LRB_LOAD_Y_OFFSET 0x0174 |
| |
| /* Register CR_BELOW_PARAM_OUT_ADDR */ |
| #define MVEA_CR_BELOW_PARAM_OUT_ADDR 0x0178 |
| #define MASK_MVEA_CR_BELOW_PARAM_OUT_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_BELOW_PARAM_OUT_ADDR 0 |
| #define REGNUM_MVEA_CR_BELOW_PARAM_OUT_ADDR 0x0178 |
| |
| /* Register CR_BUFFER_SIDEBAND */ |
| #define MVEA_CR_BUFFER_SIDEBAND 0x017C |
| #define MASK_MVEA_CR_CURR_MB_SBAND 0x00000003 |
| #define SHIFT_MVEA_CR_CURR_MB_SBAND 0 |
| #define REGNUM_MVEA_CR_CURR_MB_SBAND 0x017C |
| |
| #define MASK_MVEA_CR_ABOVE_PIX_IN_SBAND 0x0000000C |
| #define SHIFT_MVEA_CR_ABOVE_PIX_IN_SBAND 2 |
| #define REGNUM_MVEA_CR_ABOVE_PIX_IN_SBAND 0x017C |
| |
| #define MASK_MVEA_CR_CURR_PARAM_SBAND 0x00000030 |
| #define SHIFT_MVEA_CR_CURR_PARAM_SBAND 4 |
| #define REGNUM_MVEA_CR_CURR_PARAM_SBAND 0x017C |
| |
| #define MASK_MVEA_CR_BELOW_PARAM_IN_SBAND 0x000000C0 |
| #define SHIFT_MVEA_CR_BELOW_PARAM_IN_SBAND 6 |
| #define REGNUM_MVEA_CR_BELOW_PARAM_IN_SBAND 0x017C |
| |
| #define MASK_MVEA_CR_ABOVE_PARAM_IN_SBAND 0x00000300 |
| #define SHIFT_MVEA_CR_ABOVE_PARAM_IN_SBAND 8 |
| #define REGNUM_MVEA_CR_ABOVE_PARAM_IN_SBAND 0x017C |
| |
| #define MASK_MVEA_CR_REF_SBAND 0x00000C00 |
| #define SHIFT_MVEA_CR_REF_SBAND 10 |
| #define REGNUM_MVEA_CR_REF_SBAND 0x017C |
| |
| #define MASK_MVEA_CR_RECON_SBAND 0x00003000 |
| #define SHIFT_MVEA_CR_RECON_SBAND 12 |
| #define REGNUM_MVEA_CR_RECON_SBAND 0x017C |
| |
| #define MASK_MVEA_CR_ABOVE_PIX_OUT_SBAND 0x0000C000 |
| #define SHIFT_MVEA_CR_ABOVE_PIX_OUT_SBAND 14 |
| #define REGNUM_MVEA_CR_ABOVE_PIX_OUT_SBAND 0x017C |
| |
| #define MASK_MVEA_CR_BELOW_PARAM_OUT_SBAND 0x00030000 |
| #define SHIFT_MVEA_CR_BELOW_PARAM_OUT_SBAND 16 |
| #define REGNUM_MVEA_CR_BELOW_PARAM_OUT_SBAND 0x017C |
| |
| #define MASK_MVEA_CR_ABOVE_PARAM_OUT_SBAND 0x000C0000 |
| #define SHIFT_MVEA_CR_ABOVE_PARAM_OUT_SBAND 18 |
| #define REGNUM_MVEA_CR_ABOVE_PARAM_OUT_SBAND 0x017C |
| |
| /* Register CR_CMPRS_ACKNOWLEDGE */ |
| #define MVEA_CR_CMPRS_ACKNOWLEDGE 0x0180 |
| #define MASK_MVEA_CR_CMPRS_ACK 0x00000001 |
| #define SHIFT_MVEA_CR_CMPRS_ACK 0 |
| #define REGNUM_MVEA_CR_CMPRS_ACK 0x0180 |
| |
| /* Register CR_CMPRS_SBLK_THRESHOLD */ |
| #define MVEA_CR_CMPRS_SBLK_THRESHOLD 0x0184 |
| #define MASK_MVEA_CR_CMPRS_SBLK_THRSHLD 0x000001FF |
| #define SHIFT_MVEA_CR_CMPRS_SBLK_THRSHLD 0 |
| #define REGNUM_MVEA_CR_CMPRS_SBLK_THRSHLD 0x0184 |
| |
| /* Register CR_CMPRS_COEFF_COST_H */ |
| #define MVEA_CR_CMPRS_COEFF_COST_H 0x0188 |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST8 0x0000000F |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST8 0 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST8 0x0188 |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST9 0x000000F0 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST9 4 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST9 0x0188 |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST10 0x00000F00 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST10 8 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST10 0x0188 |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST11 0x0000F000 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST11 12 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST11 0x0188 |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST12 0x000F0000 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST12 16 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST12 0x0188 |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST13 0x00F00000 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST13 20 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST13 0x0188 |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST14 0x0F000000 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST14 24 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST14 0x0188 |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST15 0xF0000000 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST15 28 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST15 0x0188 |
| |
| /* Register CR_CMPRS_COEFF_COST_L */ |
| #define MVEA_CR_CMPRS_COEFF_COST_L 0x018C |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST0 0x0000000F |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST0 0 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST0 0x018C |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST1 0x000000F0 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST1 4 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST1 0x018C |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST2 0x00000F00 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST2 8 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST2 0x018C |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST3 0x0000F000 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST3 12 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST3 0x018C |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST4 0x000F0000 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST4 16 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST4 0x018C |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST5 0x00F00000 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST5 20 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST5 0x018C |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST6 0x0F000000 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST6 24 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST6 0x018C |
| |
| #define MASK_MVEA_CR_CMPRS_COEFF_COST7 0xF0000000 |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_COST7 28 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_COST7 0x018C |
| |
| /* Register CR_CMPRS_COEFF_THRESHOLD */ |
| #define MVEA_CR_CMPRS_COEFF_THRESHOLD 0x0190 |
| #define MASK_MVEA_CR_CMPRS_COEFF_THRSHLD 0x0000FFFF |
| #define SHIFT_MVEA_CR_CMPRS_COEFF_THRSHLD 0 |
| #define REGNUM_MVEA_CR_CMPRS_COEFF_THRSHLD 0x0190 |
| |
| /* Register CR_CMPRS_SBLK_RIGHT */ |
| #define MVEA_CR_CMPRS_SBLK_RIGHT 0x0194 |
| #define MASK_MVEA_CR_CMPRS_SBLK_RIGHT 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_CMPRS_SBLK_RIGHT 0 |
| #define REGNUM_MVEA_CR_CMPRS_SBLK_RIGHT 0x0194 |
| |
| /* Register CR_CMPRS_SBLK_BOTTOM */ |
| #define MVEA_CR_CMPRS_SBLK_BOTTOM 0x0198 |
| #define MASK_MVEA_CR_CMPRS_SBLK_BOTTOM 0x00FFFFFF |
| #define SHIFT_MVEA_CR_CMPRS_SBLK_BOTTOM 0 |
| #define REGNUM_MVEA_CR_CMPRS_SBLK_BOTTOM 0x0198 |
| |
| /* Register CR_CMPRS_TRANS_CRC */ |
| #define MVEA_CR_CMPRS_TRANS_CRC 0x019C |
| #define MASK_MVEA_CR_CMPRS_IT_CRC 0x0000FFFF |
| #define SHIFT_MVEA_CR_CMPRS_IT_CRC 0 |
| #define REGNUM_MVEA_CR_CMPRS_IT_CRC 0x019C |
| |
| #define MASK_MVEA_CR_CMPRS_FT_CRC 0xFFFF0000 |
| #define SHIFT_MVEA_CR_CMPRS_FT_CRC 16 |
| #define REGNUM_MVEA_CR_CMPRS_FT_CRC 0x019C |
| |
| /* Register CR_CMPRS_QUANT_CRC */ |
| #define MVEA_CR_CMPRS_QUANT_CRC 0x01A0 |
| #define MASK_MVEA_CR_CMPRS_IQT_CRC 0x0000FFFF |
| #define SHIFT_MVEA_CR_CMPRS_IQT_CRC 0 |
| #define REGNUM_MVEA_CR_CMPRS_IQT_CRC 0x01A0 |
| |
| #define MASK_MVEA_CR_CMPRS_QT_CRC 0xFFFF0000 |
| #define SHIFT_MVEA_CR_CMPRS_QT_CRC 16 |
| #define REGNUM_MVEA_CR_CMPRS_QT_CRC 0x01A0 |
| |
| /* Register CR_CMPRS_DIAGNOSTIC1 */ |
| #define MVEA_CR_CMPRS_DIAGNOSTIC1 0x01A4 |
| #define MASK_MVEA_CR_CMPRS_DIAG1 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_CMPRS_DIAG1 0 |
| #define REGNUM_MVEA_CR_CMPRS_DIAG1 0x01A4 |
| |
| /* Register CR_CMPRS_RLE_CONTROL */ |
| #define MVEA_CR_CMPRS_RLE_CONTROL 0x01A8 |
| #define MASK_MVEA_CR_CMPRS_RLE_ENABLE 0x80000000 |
| #define SHIFT_MVEA_CR_CMPRS_RLE_ENABLE 31 |
| #define REGNUM_MVEA_CR_CMPRS_RLE_ENABLE 0x01A8 |
| |
| /* Register CR_CMPRS_RLE_STATUS */ |
| #define MVEA_CR_CMPRS_RLE_STATUS 0x01AC |
| #define MASK_MVEA_CR_CMPRS_CODED_COUNT 0x000007FF |
| #define SHIFT_MVEA_CR_CMPRS_CODED_COUNT 0 |
| #define REGNUM_MVEA_CR_CMPRS_CODED_COUNT 0x01AC |
| |
| /* Register CR_CMPRS_MAX_CYCLE_COUNT */ |
| #define MVEA_CR_CMPRS_MAX_CYCLE_COUNT 0x01B0 |
| #define MASK_MVEA_CR_CMPRS_MAX_CYCLE_COUNT 0x0000FFFF |
| #define SHIFT_MVEA_CR_CMPRS_MAX_CYCLE_COUNT 0 |
| #define REGNUM_MVEA_CR_CMPRS_MAX_CYCLE_COUNT 0x01B0 |
| |
| /* Register CR_CMPRS_MAX_CYCLE_MB */ |
| #define MVEA_CR_CMPRS_MAX_CYCLE_MB 0x01B4 |
| #define MASK_MVEA_CR_CMPRS_MAX_CYCLE_MB_NUM 0x003FFFFF |
| #define SHIFT_MVEA_CR_CMPRS_MAX_CYCLE_MB_NUM 0 |
| #define REGNUM_MVEA_CR_CMPRS_MAX_CYCLE_MB_NUM 0x01B4 |
| |
| #define MASK_MVEA_CR_CMPRS_MAX_CYCLE_MB_TYPE 0x30000000 |
| #define SHIFT_MVEA_CR_CMPRS_MAX_CYCLE_MB_TYPE 28 |
| #define REGNUM_MVEA_CR_CMPRS_MAX_CYCLE_MB_TYPE 0x01B4 |
| |
| /* Register CR_CMPRS_MAX_CYCLE_RESET */ |
| #define MVEA_CR_CMPRS_MAX_CYCLE_RESET 0x01B8 |
| #define MASK_MVEA_CR_CMPRS_MAX_CYCLE_RESET 0x00000001 |
| #define SHIFT_MVEA_CR_CMPRS_MAX_CYCLE_RESET 0 |
| #define REGNUM_MVEA_CR_CMPRS_MAX_CYCLE_RESET 0x01B8 |
| |
| #define MASK_MVEA_CR_CMPRS_DISABLE_COUNTERS 0x00000002 |
| #define SHIFT_MVEA_CR_CMPRS_DISABLE_COUNTERS 1 |
| #define REGNUM_MVEA_CR_CMPRS_DISABLE_COUNTERS 0x01B8 |
| |
| /* Register CR_CMPRS_VLC_CRC */ |
| #define MVEA_CR_CMPRS_VLC_CRC 0x01BC |
| #define MASK_MVEA_CR_CMPRS_VLC_CRC 0x0000FFFF |
| #define SHIFT_MVEA_CR_CMPRS_VLC_CRC 0 |
| #define REGNUM_MVEA_CR_CMPRS_VLC_CRC 0x01BC |
| |
| /* Register CR_ABOVE_PIX_Y_ROW_OUT_ADDR */ |
| #define MVEA_CR_ABOVE_PIX_Y_ROW_OUT_ADDR 0x01C0 |
| #define MASK_MVEA_CR_ABOVE_PIX_Y_ROW_OUT_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_ABOVE_PIX_Y_ROW_OUT_ADDR 0 |
| #define REGNUM_MVEA_CR_ABOVE_PIX_Y_ROW_OUT_ADDR 0x01C0 |
| |
| /* Register CR_ABOVE_PIX_UV_ROW_OUT_ADDR */ |
| #define MVEA_CR_ABOVE_PIX_UV_ROW_OUT_ADDR 0x01C4 |
| #define MASK_MVEA_CR_ABOVE_PIX_UV_ROW_OUT_ADDR 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_ABOVE_PIX_UV_ROW_OUT_ADDR 0 |
| #define REGNUM_MVEA_CR_ABOVE_PIX_UV_ROW_OUT_ADDR 0x01C4 |
| |
| /* Register CR_IPE_LAMBDA_TABLE */ |
| #define MVEA_CR_IPE_LAMBDA_TABLE 0x01F0 |
| #define MASK_MVEA_CR_IPE_QPC_OR_DC_SCALE_LUMA_TABLE 0x000000FF |
| #define SHIFT_MVEA_CR_IPE_QPC_OR_DC_SCALE_LUMA_TABLE 0 |
| #define REGNUM_MVEA_CR_IPE_QPC_OR_DC_SCALE_LUMA_TABLE 0x01F0 |
| |
| #define MASK_MVEA_CR_IPE_ALPHA_OR_DC_SCALE_CHR_TABLE 0x0000FF00 |
| #define SHIFT_MVEA_CR_IPE_ALPHA_OR_DC_SCALE_CHR_TABLE 8 |
| #define REGNUM_MVEA_CR_IPE_ALPHA_OR_DC_SCALE_CHR_TABLE 0x01F0 |
| |
| #define MASK_MVEA_CR_IPE_LAMBDA_TABLE 0x007F0000 |
| #define SHIFT_MVEA_CR_IPE_LAMBDA_TABLE 16 |
| #define REGNUM_MVEA_CR_IPE_LAMBDA_TABLE 0x01F0 |
| |
| /* Register CR_IPE_MV_BIAS_TABLE */ |
| #define MVEA_CR_IPE_MV_BIAS_TABLE 0x01F4 |
| #define MASK_MVEA_CR_IPE_MV_BIAS_TABLE 0x00007FFF |
| #define SHIFT_MVEA_CR_IPE_MV_BIAS_TABLE 0 |
| #define REGNUM_MVEA_CR_IPE_MV_BIAS_TABLE 0x01F4 |
| |
| /* Register CR_IPE_QP */ |
| #define MVEA_CR_IPE_QP 0x01FC |
| #define MASK_MVEA_CR_IPE_QPY 0x000000FF |
| #define SHIFT_MVEA_CR_IPE_QPY 0 |
| #define REGNUM_MVEA_CR_IPE_QPY 0x01FC |
| |
| /* Register CR_IPE_CONTROL */ |
| #define MVEA_CR_IPE_CONTROL 0x0200 |
| #define MASK_MVEA_CR_IPE_BLOCKSIZE 0x00000003 |
| #define SHIFT_MVEA_CR_IPE_BLOCKSIZE 0 |
| #define REGNUM_MVEA_CR_IPE_BLOCKSIZE 0x0200 |
| |
| #define MASK_MVEA_CR_IPE_Y_CANDIDATE_NUM 0x0000003C |
| #define SHIFT_MVEA_CR_IPE_Y_CANDIDATE_NUM 2 |
| #define REGNUM_MVEA_CR_IPE_Y_CANDIDATE_NUM 0x0200 |
| |
| #define MASK_MVEA_CR_IPE_Y_FINE_SEARCH 0x00000040 |
| #define SHIFT_MVEA_CR_IPE_Y_FINE_SEARCH 6 |
| #define REGNUM_MVEA_CR_IPE_Y_FINE_SEARCH 0x0200 |
| |
| #define MASK_MVEA_CR_IPE_GRID_SEARCH_SIZE 0x00000380 |
| #define SHIFT_MVEA_CR_IPE_GRID_SEARCH_SIZE 7 |
| #define REGNUM_MVEA_CR_IPE_GRID_SEARCH_SIZE 0x0200 |
| |
| #define MASK_MVEA_CR_IPE_GRID_FINE_SEARCH 0x00000C00 |
| #define SHIFT_MVEA_CR_IPE_GRID_FINE_SEARCH 10 |
| #define REGNUM_MVEA_CR_IPE_GRID_FINE_SEARCH 0x0200 |
| |
| #define MASK_MVEA_CR_IPE_ENCODING_FORMAT 0x00003000 |
| #define SHIFT_MVEA_CR_IPE_ENCODING_FORMAT 12 |
| #define REGNUM_MVEA_CR_IPE_ENCODING_FORMAT 0x0200 |
| |
| #define MASK_MVEA_CR_IPE_MV_NUMBER_RESTRICTION 0x00004000 |
| #define SHIFT_MVEA_CR_IPE_MV_NUMBER_RESTRICTION 14 |
| #define REGNUM_MVEA_CR_IPE_MV_NUMBER_RESTRICTION 0x0200 |
| |
| /* Register CR_IPE_SEARCH_STATUS */ |
| #define MVEA_CR_IPE_SEARCH_STATUS 0x0204 |
| #define MASK_MVEA_CR_IPE_SEARCH_STATUS 0x00000007 |
| #define SHIFT_MVEA_CR_IPE_SEARCH_STATUS 0 |
| #define REGNUM_MVEA_CR_IPE_SEARCH_STATUS 0x0204 |
| |
| /* Register CR_IPE_INT_MVCOST */ |
| #define MVEA_CR_IPE_INT_MVCOST 0x0208 |
| #define MASK_MVEA_CR_IPE_INT_MVCOST 0x0000FFFF |
| #define SHIFT_MVEA_CR_IPE_INT_MVCOST 0 |
| #define REGNUM_MVEA_CR_IPE_INT_MVCOST 0x0208 |
| |
| /* Register CR_IPE_MB_SAD */ |
| #define MVEA_CR_IPE_MB_SAD 0x020C |
| #define MASK_MVEA_CR_IPE_MB_SAD 0x0000FFFF |
| #define SHIFT_MVEA_CR_IPE_MB_SAD 0 |
| #define REGNUM_MVEA_CR_IPE_MB_SAD 0x020C |
| |
| /* Register CR_IPE_DIAG1 */ |
| #define MVEA_CR_IPE_DIAG1 0x0210 |
| #define MASK_MVEA_CR_IPE_DIAG1 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_IPE_DIAG1 0 |
| #define REGNUM_MVEA_CR_IPE_DIAG1 0x0210 |
| |
| /* Register CR_IPE_QP_SLICE */ |
| #define MVEA_CR_IPE_QP_SLICE 0x0214 |
| #define MASK_MVEA_CR_IPE_QPY_SLICE 0x000000FF |
| #define SHIFT_MVEA_CR_IPE_QPY_SLICE 0 |
| #define REGNUM_MVEA_CR_IPE_QPY_SLICE 0x0214 |
| |
| #define MASK_MVEA_CR_IPE_QPC_SLICE 0x0000FF00 |
| #define SHIFT_MVEA_CR_IPE_QPC_SLICE 8 |
| #define REGNUM_MVEA_CR_IPE_QPC_SLICE 0x0214 |
| |
| /* Register CR_IPE_JITTER_FACTOR */ |
| #define MVEA_CR_IPE_JITTER_FACTOR 0x0218 |
| #define MASK_MVEA_CR_IPE_JITTER_FACTOR 0x00000003 |
| #define SHIFT_MVEA_CR_IPE_JITTER_FACTOR 0 |
| #define REGNUM_MVEA_CR_IPE_JITTER_FACTOR 0x0218 |
| |
| /* Register CR_IPE_CTRL_CRC */ |
| #define MVEA_CR_IPE_CTRL_CRC 0x0264 |
| #define MASK_MVEA_CR_IPE_CTRL_CRC 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_IPE_CTRL_CRC 0 |
| #define REGNUM_MVEA_CR_IPE_CTRL_CRC 0x0264 |
| |
| /* Register CR_IPE_WDATA_CRC */ |
| #define MVEA_CR_IPE_WDATA_CRC 0x0268 |
| #define MASK_MVEA_CR_IPE_WDATA_CRC 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_IPE_WDATA_CRC 0 |
| #define REGNUM_MVEA_CR_IPE_WDATA_CRC 0x0268 |
| |
| /* Register CR_IPE_MB_PERFORMANCE_CLEAR */ |
| #define MVEA_CR_IPE_MB_PERFORMANCE_CLEAR 0x026C |
| #define MASK_MVEA_CR_IPE_MB_PERFORMANCE_CLEAR 0x00000001 |
| #define SHIFT_MVEA_CR_IPE_MB_PERFORMANCE_CLEAR 0 |
| #define REGNUM_MVEA_CR_IPE_MB_PERFORMANCE_CLEAR 0x026C |
| |
| /* Register CR_IPE_MB_PERFORMANCE_RESULT */ |
| #define MVEA_CR_IPE_MB_PERFORMANCE_RESULT 0x0270 |
| #define MASK_MVEA_CR_IPE_MB_PERFORMANCE_RESULT 0x0000FFFF |
| #define SHIFT_MVEA_CR_IPE_MB_PERFORMANCE_RESULT 0 |
| #define REGNUM_MVEA_CR_IPE_MB_PERFORMANCE_RESULT 0x0270 |
| |
| /* Register CR_IPE_MB_PERFORMANCE_MB_NUMBER */ |
| #define MVEA_CR_IPE_MB_PERFORMANCE_MB_NUMBER 0x0274 |
| #define MASK_MVEA_CR_IPE_MB_PERFORMANCE_MB_NUMBER 0x003FFFFF |
| #define SHIFT_MVEA_CR_IPE_MB_PERFORMANCE_MB_NUMBER 0 |
| #define REGNUM_MVEA_CR_IPE_MB_PERFORMANCE_MB_NUMBER 0x0274 |
| |
| /* Register CR_IPE_VECTOR_CLIPPING */ |
| #define MVEA_CR_IPE_VECTOR_CLIPPING 0x0278 |
| #define MASK_MVEA_CR_IPE_VECTOR_CLIPPING_Y 0x000000FF |
| #define SHIFT_MVEA_CR_IPE_VECTOR_CLIPPING_Y 0 |
| #define REGNUM_MVEA_CR_IPE_VECTOR_CLIPPING_Y 0x0278 |
| |
| #define MASK_MVEA_CR_IPE_VECTOR_CLIPPING_X 0x0000FF00 |
| #define SHIFT_MVEA_CR_IPE_VECTOR_CLIPPING_X 8 |
| #define REGNUM_MVEA_CR_IPE_VECTOR_CLIPPING_X 0x0278 |
| |
| /* Register CR_JMCOMP_CONTROL */ |
| #define MVEA_CR_JMCOMP_CONTROL 0x0280 |
| #define MASK_MVEA_CR_JMCOMP_MODE 0x00000003 |
| #define SHIFT_MVEA_CR_JMCOMP_MODE 0 |
| #define REGNUM_MVEA_CR_JMCOMP_MODE 0x0280 |
| |
| #define MASK_MVEA_CR_JMCOMP_AC_ENABLE 0x00008000 |
| #define SHIFT_MVEA_CR_JMCOMP_AC_ENABLE 15 |
| #define REGNUM_MVEA_CR_JMCOMP_AC_ENABLE 0x0280 |
| |
| #define MASK_MVEA_CR_JMCOMP_JPEG_NUM_BLOCKS 0x00F00000 |
| #define SHIFT_MVEA_CR_JMCOMP_JPEG_NUM_BLOCKS 20 |
| #define REGNUM_MVEA_CR_JMCOMP_JPEG_NUM_BLOCKS 0x0280 |
| |
| #define MASK_MVEA_CR_JMCOMP_DISABLE_QP_PATCH_ON_SKIP 0x01000000 |
| #define SHIFT_MVEA_CR_JMCOMP_DISABLE_QP_PATCH_ON_SKIP 24 |
| #define REGNUM_MVEA_CR_JMCOMP_DISABLE_QP_PATCH_ON_SKIP 0x0280 |
| |
| /* Register CR_JMCOMP_JPEG_BLOCK_TYPES */ |
| #define MVEA_CR_JMCOMP_JPEG_BLOCK_TYPES 0x0284 |
| #define MASK_MVEA_CR_JMCOMP_JPEG_BLOCK_TYPE(i) (0x00000003 << (0 + ((i) * 2))) |
| #define SHIFT_MVEA_CR_JMCOMP_JPEG_BLOCK_TYPE(i) (0 + ((i) * 2)) |
| #define REGNUM_MVEA_CR_JMCOMP_JPEG_BLOCK_TYPE(i) 0x0284 |
| |
| /* Register CR_JMCOMP_JPEG_LUMA_PRED */ |
| #define MVEA_CR_JMCOMP_JPEG_LUMA_PRED 0x0288 |
| #define MASK_MVEA_CR_JMCOMP_JPEG_DC_LUMA_PRED 0x00000FFF |
| #define SHIFT_MVEA_CR_JMCOMP_JPEG_DC_LUMA_PRED 0 |
| #define REGNUM_MVEA_CR_JMCOMP_JPEG_DC_LUMA_PRED 0x0288 |
| |
| /* Register CR_JMCOMP_JPEG_CHROMA_PREDS */ |
| #define MVEA_CR_JMCOMP_JPEG_CHROMA_PREDS 0x028C |
| #define MASK_MVEA_CR_JMCOMP_JPEG_DC_CHROMA_V_PRED 0x0FFF0000 |
| #define SHIFT_MVEA_CR_JMCOMP_JPEG_DC_CHROMA_V_PRED 16 |
| #define REGNUM_MVEA_CR_JMCOMP_JPEG_DC_CHROMA_V_PRED 0x028C |
| |
| #define MASK_MVEA_CR_JMCOMP_JPEG_DC_CHROMA_U_PRED 0x00000FFF |
| #define SHIFT_MVEA_CR_JMCOMP_JPEG_DC_CHROMA_U_PRED 0 |
| #define REGNUM_MVEA_CR_JMCOMP_JPEG_DC_CHROMA_U_PRED 0x028C |
| |
| /* Register CR_JMCOMP_CRC */ |
| #define MVEA_CR_JMCOMP_CRC 0x0314 |
| #define MASK_MVEA_CR_JMCOMP_CRC_OUT 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_JMCOMP_CRC_OUT 0 |
| #define REGNUM_MVEA_CR_JMCOMP_CRC_OUT 0x0314 |
| |
| /* Register CR_JMCOMP_VLC_CRC */ |
| #define MVEA_CR_JMCOMP_VLC_CRC 0x0318 |
| #define MASK_MVEA_CR_JMCOMP_VLC_IF_CRC 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_JMCOMP_VLC_IF_CRC 0 |
| #define REGNUM_MVEA_CR_JMCOMP_VLC_IF_CRC 0x0318 |
| |
| /* Register CR_JMCOMP_PERFORMANCE_0 */ |
| #define MVEA_CR_JMCOMP_PERFORMANCE_0 0x031C |
| #define MASK_MVEA_CR_JMCOMP_WORST_MB_CYCLES 0x0000FFFF |
| #define SHIFT_MVEA_CR_JMCOMP_WORST_MB_CYCLES 0 |
| #define REGNUM_MVEA_CR_JMCOMP_WORST_MB_CYCLES 0x031C |
| |
| #define MASK_MVEA_CR_JMCOMP_WORST_MB_TYPE 0x00030000 |
| #define SHIFT_MVEA_CR_JMCOMP_WORST_MB_TYPE 16 |
| #define REGNUM_MVEA_CR_JMCOMP_WORST_MB_TYPE 0x031C |
| |
| /* Register CR_JMCOMP_PERFORMANCE_1 */ |
| #define MVEA_CR_JMCOMP_PERFORMANCE_1 0x0320 |
| #define MASK_MVEA_CR_JMCOMP_WORST_MB_NUM 0x003FFFFF |
| #define SHIFT_MVEA_CR_JMCOMP_WORST_MB_NUM 0 |
| #define REGNUM_MVEA_CR_JMCOMP_WORST_MB_NUM 0x0320 |
| |
| /* Register CR_JMCOMP_PERFORMANCE_2 */ |
| #define MVEA_CR_JMCOMP_PERFORMANCE_2 0x0324 |
| #define MASK_MVEA_CR_JMCOMP_WORST_MB_RESET 0x00000001 |
| #define SHIFT_MVEA_CR_JMCOMP_WORST_MB_RESET 0 |
| #define REGNUM_MVEA_CR_JMCOMP_WORST_MB_RESET 0x0324 |
| |
| #define MASK_MVEA_CR_JMCOMP_DISABLE_COUNTERS 0x00000002 |
| #define SHIFT_MVEA_CR_JMCOMP_DISABLE_COUNTERS 1 |
| #define REGNUM_MVEA_CR_JMCOMP_DISABLE_COUNTERS 0x0324 |
| |
| /* Register CR_JMCOMP_QP_VALUE */ |
| #define MVEA_CR_JMCOMP_QP_VALUE 0x0348 |
| #define MASK_MVEA_CR_JMCOMP_REAL_QP_LUMA 0x000001FF |
| #define SHIFT_MVEA_CR_JMCOMP_REAL_QP_LUMA 0 |
| #define REGNUM_MVEA_CR_JMCOMP_REAL_QP_LUMA 0x0348 |
| |
| /* Register CR_SPE_ZERO_THRESH */ |
| #define MVEA_CR_SPE_ZERO_THRESH 0x0370 |
| #define MASK_MVEA_CR_SPE_ZERO_THRESH 0x0000001F |
| #define SHIFT_MVEA_CR_SPE_ZERO_THRESH 0 |
| #define REGNUM_MVEA_CR_SPE_ZERO_THRESH 0x0370 |
| |
| /* Register CR_SPE_INTRA16_BIAS_TABLE */ |
| #define MVEA_CR_SPE_INTRA16_BIAS_TABLE 0x0374 |
| #define MASK_MVEA_CR_SPE_INTRA16_BIAS_TABLE 0x0003FFFF |
| #define SHIFT_MVEA_CR_SPE_INTRA16_BIAS_TABLE 0 |
| #define REGNUM_MVEA_CR_SPE_INTRA16_BIAS_TABLE 0x0374 |
| |
| /* Register CR_SPE_INTER_BIAS_TABLE */ |
| #define MVEA_CR_SPE_INTER_BIAS_TABLE 0x0378 |
| #define MASK_MVEA_CR_SPE_INTER_BIAS_TABLE 0x0003FFFF |
| #define SHIFT_MVEA_CR_SPE_INTER_BIAS_TABLE 0 |
| #define REGNUM_MVEA_CR_SPE_INTER_BIAS_TABLE 0x0378 |
| |
| /* Register CR_SPE_PRED_VECTOR_BIAS_TABLE */ |
| #define MVEA_CR_SPE_PRED_VECTOR_BIAS_TABLE 0x037C |
| #define MASK_MVEA_CR_SPE_PRED_VECTOR_BIAS_TABLE 0x00007FFF |
| #define SHIFT_MVEA_CR_SPE_PRED_VECTOR_BIAS_TABLE 0 |
| #define REGNUM_MVEA_CR_SPE_PRED_VECTOR_BIAS_TABLE 0x037C |
| |
| /* Register CR_SPE_CONTROL */ |
| #define MVEA_CR_SPE_CONTROL 0x0380 |
| #define MASK_MVEA_CR_SPE_INTER_ENABLE 0x00000001 |
| #define SHIFT_MVEA_CR_SPE_INTER_ENABLE 0 |
| #define REGNUM_MVEA_CR_SPE_INTER_ENABLE 0x0380 |
| |
| #define MASK_MVEA_CR_SPE_INTRA_ENABLE 0x00000002 |
| #define SHIFT_MVEA_CR_SPE_INTRA_ENABLE 1 |
| #define REGNUM_MVEA_CR_SPE_INTRA_ENABLE 0x0380 |
| |
| #define MASK_MVEA_CR_SPE_MPEG4_ENABLE 0x00000004 |
| #define SHIFT_MVEA_CR_SPE_MPEG4_ENABLE 2 |
| #define REGNUM_MVEA_CR_SPE_MPEG4_ENABLE 0x0380 |
| |
| #define MASK_MVEA_CR_SPE_FORCE_SKIP 0x00000008 |
| #define SHIFT_MVEA_CR_SPE_FORCE_SKIP 3 |
| #define REGNUM_MVEA_CR_SPE_FORCE_SKIP 0x0380 |
| |
| #define MASK_MVEA_CR_SPE_H263_ENABLE 0x00000010 |
| #define SHIFT_MVEA_CR_SPE_H263_ENABLE 4 |
| #define REGNUM_MVEA_CR_SPE_H263_ENABLE 0x0380 |
| |
| /* Register CR_SPE_INTRA_COST */ |
| #define MVEA_CR_SPE_INTRA_COST 0x0384 |
| #define MASK_MVEA_CR_SPE_INTRA_COST 0x0001FFFF |
| #define SHIFT_MVEA_CR_SPE_INTRA_COST 0 |
| #define REGNUM_MVEA_CR_SPE_INTRA_COST 0x0384 |
| |
| /* Register CR_SPE_REQUEST */ |
| #define MVEA_CR_SPE_REQUEST 0x038C |
| #define MASK_MVEA_CR_SPE_REQ 0x00000001 |
| #define SHIFT_MVEA_CR_SPE_REQ 0 |
| #define REGNUM_MVEA_CR_SPE_REQ 0x038C |
| |
| /* Register CR_SPE_INTER_SUM_MIN_SADS */ |
| #define MVEA_CR_SPE_INTER_SUM_MIN_SADS 0x0390 |
| #define MASK_MVEA_CR_SPE_INTER_SUM_MIN_SADS 0x0000FFFF |
| #define SHIFT_MVEA_CR_SPE_INTER_SUM_MIN_SADS 0 |
| #define REGNUM_MVEA_CR_SPE_INTER_SUM_MIN_SADS 0x0390 |
| |
| /* Register CR_SPE_DIAGNOSTIC1 */ |
| #define MVEA_CR_SPE_DIAGNOSTIC1 0x0394 |
| #define MASK_MVEA_CR_SPE_DIAG1 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_SPE_DIAG1 0 |
| #define REGNUM_MVEA_CR_SPE_DIAG1 0x0394 |
| |
| /* Register CR_SPE_INTER_SAD_SIGNATURE */ |
| #define MVEA_CR_SPE_INTER_SAD_SIGNATURE 0x0398 |
| #define MASK_MVEA_CR_SPE_INTER_SAD_SIGNATURE 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_SPE_INTER_SAD_SIGNATURE 0 |
| #define REGNUM_MVEA_CR_SPE_INTER_SAD_SIGNATURE 0x0398 |
| |
| /* Register CR_SPE_INTRA_SAD_SIGNATURE */ |
| #define MVEA_CR_SPE_INTRA_SAD_SIGNATURE 0x039C |
| #define MASK_MVEA_CR_SPE_INTRA_SAD_SIGNATURE 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_SPE_INTRA_SAD_SIGNATURE 0 |
| #define REGNUM_MVEA_CR_SPE_INTRA_SAD_SIGNATURE 0x039C |
| |
| /* Register CR_SPE_MVD_CLIP_RANGE */ |
| #define MVEA_CR_SPE_MVD_CLIP_RANGE 0x03A0 |
| #define MASK_MVEA_CR_SPE_MVD_X_CLIP 0x0000FFFF |
| #define SHIFT_MVEA_CR_SPE_MVD_X_CLIP 0 |
| #define REGNUM_MVEA_CR_SPE_MVD_X_CLIP 0x03A0 |
| |
| #define MASK_MVEA_CR_SPE_MVD_Y_CLIP 0xFFFF0000 |
| #define SHIFT_MVEA_CR_SPE_MVD_Y_CLIP 16 |
| #define REGNUM_MVEA_CR_SPE_MVD_Y_CLIP 0x03A0 |
| |
| /* Register CR_SPE_INT_MVCOST */ |
| #define MVEA_CR_SPE_INT_MVCOST 0x03A4 |
| #define MASK_MVEA_CR_SPE_MVCOST 0x0000FFFF |
| #define SHIFT_MVEA_CR_SPE_MVCOST 0 |
| #define REGNUM_MVEA_CR_SPE_MVCOST 0x03A4 |
| |
| /* Register CR_IMG_MVEA_RSVD0 */ |
| #define MVEA_CR_IMG_MVEA_RSVD0 0x03B0 |
| #define MASK_MVEA_CR_IMG_MVEA_RESERVED0 0xFFFFFFFF |
| #define SHIFT_MVEA_CR_IMG_MVEA_RESERVED0 0 |
| #define REGNUM_MVEA_CR_IMG_MVEA_RESERVED0 0x03B0 |
| |
| /* Register CR_MVEA_CRC_RESET */ |
| #define MVEA_CR_MVEA_CRC_RESET 0x03B4 |
| #define MASK_MVEA_CR_IPE_CRC_RST 0x00000001 |
| #define SHIFT_MVEA_CR_IPE_CRC_RST 0 |
| #define REGNUM_MVEA_CR_IPE_CRC_RST 0x03B4 |
| |
| #define MASK_MVEA_CR_SPE_CRC_RST 0x00000002 |
| #define SHIFT_MVEA_CR_SPE_CRC_RST 1 |
| #define REGNUM_MVEA_CR_SPE_CRC_RST 0x03B4 |
| |
| #define MASK_MVEA_CR_CMC_CRC_RST 0x00000004 |
| #define SHIFT_MVEA_CR_CMC_CRC_RST 2 |
| #define REGNUM_MVEA_CR_CMC_CRC_RST 0x03B4 |
| |
| #define MASK_MVEA_CR_JMCOMP_CRC_RST 0x00000008 |
| #define SHIFT_MVEA_CR_JMCOMP_CRC_RST 3 |
| #define REGNUM_MVEA_CR_JMCOMP_CRC_RST 0x03B4 |
| |
| #define MASK_MVEA_CR_CMPRS_CRC_RST 0x00000010 |
| #define SHIFT_MVEA_CR_CMPRS_CRC_RST 4 |
| #define REGNUM_MVEA_CR_CMPRS_CRC_RST 0x03B4 |
| |
| #define MASK_MVEA_CR_DB_CRC_RST 0x00000020 |
| #define SHIFT_MVEA_CR_DB_CRC_RST 5 |
| #define REGNUM_MVEA_CR_DB_CRC_RST 0x03B4 |
| |
| #define MASK_MVEA_CR_VLC_CRC_RST 0x00000040 |
| #define SHIFT_MVEA_CR_VLC_CRC_RST 6 |
| #define REGNUM_MVEA_CR_VLC_CRC_RST 0x03B4 |
| |
| /* Register CR_SPE_MB_COUNT */ |
| #define MVEA_CR_SPE_MB_COUNT 0x03BC |
| #define MASK_MVEA_CR_SPE_INTER_MB_COUNT 0x03FF0000 |
| #define SHIFT_MVEA_CR_SPE_INTER_MB_COUNT 16 |
| #define REGNUM_MVEA_CR_SPE_INTER_MB_COUNT 0x03BC |
| |
| #define MASK_MVEA_CR_SPE_INTRA_MB_COUNT 0x000003FF |
| #define SHIFT_MVEA_CR_SPE_INTRA_MB_COUNT 0 |
| #define REGNUM_MVEA_CR_SPE_INTRA_MB_COUNT 0x03BC |
| |
| /* Register CR_SPE_PRED_VECTOR */ |
| #define MVEA_CR_SPE_PRED_VECTOR 0x03D4 |
| #define MASK_MVEA_CR_SPE_PRED_VECTOR_Y 0x7FFF0000 |
| #define SHIFT_MVEA_CR_SPE_PRED_VECTOR_Y 16 |
| #define REGNUM_MVEA_CR_SPE_PRED_VECTOR_Y 0x03D4 |
| |
| #define MASK_MVEA_CR_SPE_PRED_VECTOR_X 0x00007FFF |
| #define SHIFT_MVEA_CR_SPE_PRED_VECTOR_X 0 |
| #define REGNUM_MVEA_CR_SPE_PRED_VECTOR_X 0x03D4 |
| |
| /* Register CR_SPE_MAX_CYCLE_COUNT */ |
| #define MVEA_CR_SPE_MAX_CYCLE_COUNT 0x03D8 |
| #define MASK_MVEA_CR_SPE_MAX_CYCLE_COUNT 0x0000FFFF |
| #define SHIFT_MVEA_CR_SPE_MAX_CYCLE_COUNT 0 |
| #define REGNUM_MVEA_CR_SPE_MAX_CYCLE_COUNT 0x03D8 |
| |
| /* Register CR_SPE_MAX_CYCLE_MB */ |
| #define MVEA_CR_SPE_MAX_CYCLE_MB 0x03DC |
| #define MASK_MVEA_CR_SPE_MAX_CYCLE_MB_TYPE 0xC0000000 |
| #define SHIFT_MVEA_CR_SPE_MAX_CYCLE_MB_TYPE 30 |
| #define REGNUM_MVEA_CR_SPE_MAX_CYCLE_MB_TYPE 0x03DC |
| |
| #define MASK_MVEA_CR_SPE_MAX_CYCLE_MB_NUM 0x003FFFFF |
| #define SHIFT_MVEA_CR_SPE_MAX_CYCLE_MB_NUM 0 |
| #define REGNUM_MVEA_CR_SPE_MAX_CYCLE_MB_NUM 0x03DC |
| |
| /* Register CR_SPE_INTRA_SUM_MIN_SADS */ |
| #define MVEA_CR_SPE_INTRA_SUM_MIN_SADS 0x03E0 |
| #define MASK_MVEA_CR_SPE_INTRA_SUM_MIN_SADS 0x0000FFFF |
| #define SHIFT_MVEA_CR_SPE_INTRA_SUM_MIN_SADS 0 |
| #define REGNUM_MVEA_CR_SPE_INTRA_SUM_MIN_SADS 0x03E0 |
| |
| /* Register CR_SPE_MAX_CYCLE_RESET */ |
| #define MVEA_CR_SPE_MAX_CYCLE_RESET 0x03E4 |
| #define MASK_MVEA_CR_SPE_MAX_CYCLE_RESET 0x00000001 |
| #define SHIFT_MVEA_CR_SPE_MAX_CYCLE_RESET 0 |
| #define REGNUM_MVEA_CR_SPE_MAX_CYCLE_RESET 0x03E4 |
| |
| /* Register CR_SEQUENCER_SYNC */ |
| #define MVEA_CR_SEQUENCER_SYNC 0x03E8 |
| #define MASK_MVEA_CR_SYNC_ENABLE 0x0000FFFF |
| #define SHIFT_MVEA_CR_SYNC_ENABLE 0 |
| #define REGNUM_MVEA_CR_SYNC_ENABLE 0x03E8 |
| |
| /* Register CR_IPE_SKIPPED_MV */ |
| #define MVEA_CR_IPE_SKIPPED_MV 0x03EC |
| #define MASK_MVEA_CR_IPE_SKIPPED_MV_X 0x0000FF00 |
| #define SHIFT_MVEA_CR_IPE_SKIPPED_MV_X 8 |
| #define REGNUM_MVEA_CR_IPE_SKIPPED_MV_X 0x03EC |
| |
| #define MASK_MVEA_CR_IPE_SKIPPED_MV_Y 0x000000FF |
| #define SHIFT_MVEA_CR_IPE_SKIPPED_MV_Y 0 |
| #define REGNUM_MVEA_CR_IPE_SKIPPED_MV_Y 0x03EC |
| |
| |
| /* Table CR_JMCOMP_CHROMA_QUANTISER_TABLE */ |
| |
| /* Register CR_JMCOMP_CHROMA_QUANTISER */ |
| #define MVEA_CR_JMCOMP_CHROMA_QUANTISER(X) (0x02D0 + (4 * (X))) |
| #define MASK_MVEA_CR_JMCOMP_CHROMA_QUANT(i) (0x000000FF << (0 + ((i) * 8))) |
| #define SHIFT_MVEA_CR_JMCOMP_CHROMA_QUANT(i) (0 + ((i) * 8)) |
| #define REGNUM_MVEA_CR_JMCOMP_CHROMA_QUANT(X,i) (0x02D0 + (4 * (X))) |
| |
| /* Number of entries in table CR_JMCOMP_CHROMA_QUANTISER_TABLE */ |
| |
| #define MVEA_CR_JMCOMP_CHROMA_QUANTISER_TABLE_SIZE_UINT32 16 |
| #define MVEA_CR_JMCOMP_CHROMA_QUANTISER_TABLE_NUM_ENTRIES 16 |
| |
| |
| /* Table CR_JMCOMP_LUMA_QUANTISER_TABLE */ |
| |
| /* Register CR_JMCOMP_LUMA_QUANTISER */ |
| #define MVEA_CR_JMCOMP_LUMA_QUANTISER(X) (0x0290 + (4 * (X))) |
| #define MASK_MVEA_CR_JMCOMP_LUMA_QUANT(i) (0x000000FF << (0 + ((i) * 8))) |
| #define SHIFT_MVEA_CR_JMCOMP_LUMA_QUANT(i) (0 + ((i) * 8)) |
| #define REGNUM_MVEA_CR_JMCOMP_LUMA_QUANT(X,i) (0x0290 + (4 * (X))) |
| |
| /* Number of entries in table CR_JMCOMP_LUMA_QUANTISER_TABLE */ |
| |
| #define MVEA_CR_JMCOMP_LUMA_QUANTISER_TABLE_SIZE_UINT32 16 |
| #define MVEA_CR_JMCOMP_LUMA_QUANTISER_TABLE_NUM_ENTRIES 16 |
| |
| |
| /* Table CR_CMC_ESB_LOGICAL_REGION_SETUP_TABLE */ |
| |
| /* Register CR_CMC_ESB_LOGICAL_REGION_SETUP */ |
| #define MVEA_CR_CMC_ESB_LOGICAL_REGION_SETUP(X) (0x0080 + (4 * (X))) |
| #define MASK_MVEA_CR_CMC_ESB_REGION_VALID 0x80000000 |
| #define SHIFT_MVEA_CR_CMC_ESB_REGION_VALID 31 |
| #define REGNUM_MVEA_CR_CMC_ESB_REGION_VALID 0x0080 |
| |
| #define MASK_MVEA_CR_CMC_ESB_REGION_TYPE 0x60000000 |
| #define SHIFT_MVEA_CR_CMC_ESB_REGION_TYPE 29 |
| #define REGNUM_MVEA_CR_CMC_ESB_REGION_TYPE 0x0080 |
| |
| #define MASK_MVEA_CR_CMC_ESB_REGION_LOGICAL_WIDTH 0x00F00000 |
| #define SHIFT_MVEA_CR_CMC_ESB_REGION_LOGICAL_WIDTH 20 |
| #define REGNUM_MVEA_CR_CMC_ESB_REGION_LOGICAL_WIDTH 0x0080 |
| |
| #define MASK_MVEA_CR_CMC_ESB_REGION_LOGICAL_OFFSET_X 0x000F0000 |
| #define SHIFT_MVEA_CR_CMC_ESB_REGION_LOGICAL_OFFSET_X 16 |
| #define REGNUM_MVEA_CR_CMC_ESB_REGION_LOGICAL_OFFSET_X 0x0080 |
| |
| #define MASK_MVEA_CR_CMC_ESB_REGION_PHYS_HEIGHT 0x0000F000 |
| #define SHIFT_MVEA_CR_CMC_ESB_REGION_PHYS_HEIGHT 12 |
| #define REGNUM_MVEA_CR_CMC_ESB_REGION_PHYS_HEIGHT 0x0080 |
| |
| #define MASK_MVEA_CR_CMC_ESB_REGION_PHYS_WIDTH 0x00000F00 |
| #define SHIFT_MVEA_CR_CMC_ESB_REGION_PHYS_WIDTH 8 |
| #define REGNUM_MVEA_CR_CMC_ESB_REGION_PHYS_WIDTH 0x0080 |
| |
| #define MASK_MVEA_CR_CMC_ESB_REGION_PHYS_ORIGIN_Y 0x000000F0 |
| #define SHIFT_MVEA_CR_CMC_ESB_REGION_PHYS_ORIGIN_Y 4 |
| #define REGNUM_MVEA_CR_CMC_ESB_REGION_PHYS_ORIGIN_Y 0x0080 |
| |
| #define MASK_MVEA_CR_CMC_ESB_REGION_PHYS_ORIGIN_X 0x0000000F |
| #define SHIFT_MVEA_CR_CMC_ESB_REGION_PHYS_ORIGIN_X 0 |
| #define REGNUM_MVEA_CR_CMC_ESB_REGION_PHYS_ORIGIN_X 0x0080 |
| |
| /* Number of entries in table CR_CMC_ESB_LOGICAL_REGION_SETUP_TABLE */ |
| |
| #define MVEA_CR_CMC_ESB_LOGICAL_REGION_SETUP_TABLE_SIZE_UINT32 32 |
| #define MVEA_CR_CMC_ESB_LOGICAL_REGION_SETUP_TABLE_NUM_ENTRIES 32 |
| |
| /* |
| Byte range covering the group MVEA file |
| */ |
| |
| #define MVEA_MVEA_REGISTERS_START 0x00000000 |
| #define MVEA_MVEA_REGISTERS_END 0x000003EF |
| |
| /* |
| Byte range covering the whole register file |
| */ |
| |
| #define MVEA_REGISTERS_START 0x00000000 |
| #define MVEA_REGISTERS_END 0x000003EF |
| #define MVEA_REG_DEFAULT_TABLE struct {\ |
| IMG_UINT16 uRegOffset;\ |
| IMG_UINT32 uRegDefault;\ |
| IMG_UINT32 uRegMask;\ |
| bool bReadonly;\ |
| char* pszName;\ |
| } MVEA_Defaults[] = {\ |
| {0x0000, 0x00000000, 0x0000003F, 0, "CR_IMG_MVEA_SRST" } ,\ |
| {0x0004, 0x00000000, 0xC0001FFF, 0, "CR_IMG_MVEA_INTSTAT" } ,\ |
| {0x0008, 0x00000000, 0xC0001FFF, 0, "CR_IMG_MVEA_INTENAB" } ,\ |
| {0x000C, 0x00000000, 0x00001FFF, 0, "CR_IMG_MVEA_INTCLEAR" } ,\ |
| {0x0010, 0x00000000, 0x00001FFF, 0, "CR_IMG_MVEA_INT_COMB_SEL" } ,\ |
| {0x0014, 0x00000000, 0x000000CF, 0, "CR_MVEA_START" } ,\ |
| {0x0018, 0x00000000, 0x000001FF, 0, "CR_MVEA_BUSY" } ,\ |
| {0x001C, 0x00000000, 0x000000FF, 0, "CR_MVEA_DMACMDFIFO_WAIT" } ,\ |
| {0x0020, 0x00000000, 0x0000011F, 0, "CR_MVEA_DMACMDFIFO_STATUS" } ,\ |
| {0x0024, 0x00000000, 0x0000000F, 0, "CR_MVEA_AUTO_CLOCK_GATING" } ,\ |
| {0x0028, 0x00000000, 0x0000001F, 0, "CR_MVEA_MAN_CLOCK_GATING" } ,\ |
| {0x002C, 0x00000000, 0x0000FFFF, 0, "CR_TOPAZ_MB_PERFORMANCE_RESULT" } ,\ |
| {0x0030, 0x00000000, 0x003FFFFF, 0, "CR_TOPAZ_MB_PERFORMANCE_MB_NUMBER" } ,\ |
| {0x0034, 0x00000000, 0x0000FFFF, 0, "CR_TOPAZ_HW_MB_PERFORMANCE_RESULT" } ,\ |
| {0x0038, 0x00000000, 0x003FFFFF, 0, "CR_TOPAZ_HW_MB_PERFORMANCE_MB_NUMBER" } ,\ |
| {0x0100, 0x00000000, 0xFFFFFFFF, 0, "CR_CMC_ESB_DIAGNOSTICS" } ,\ |
| {0x0104, 0x00000000, 0xFFFFFFFF, 0, "CR_CMC_DMA_DIAGNOSTICS" } ,\ |
| {0x0108, 0x00000000, 0xFFFFFFFF, 0, "CR_CMC_SIGNATURE_ENC_MEM_WDATA" } ,\ |
| {0x010C, 0x00000000, 0xFFFFFFFF, 0, "CR_CMC_SIGNATURE_ENC_MEM_ADDR" } ,\ |
| {0x011C, 0x00000000, 0x0000001F, 0, "CR_CMC_PROC_ESB_ACCESS" } ,\ |
| {0x012C, 0x00000000, 0x0000001F, 0, "CR_CMC_LRB_LOGICAL_OFFSET" } ,\ |
| {0x0130, 0x00000000, 0x00001111, 0, "CR_SEQUENCER_SETUP" } ,\ |
| {0x0134, 0x00000000, 0xFFFFFF3F, 0, "CR_SEQUENCER_CONTROL" } ,\ |
| {0x0138, 0x00000000, 0xFFFFFFFF, 0, "CR_CURR_MB_Y_ROW_ADDR" } ,\ |
| {0x013C, 0x00000000, 0xFFFFFFFF, 0, "CR_CURR_MB_U_ROW_ADDR" } ,\ |
| {0x0140, 0x00000000, 0xFFFFFFFF, 0, "CR_CURR_MB_V_ROW_ADDR" } ,\ |
| {0x0144, 0x00000000, 0x0000FFFF, 0, "CR_CURR_MB_Y_ROW_STRIDE" } ,\ |
| {0x0148, 0x00000000, 0xFFFFFFFF, 0, "CR_CURR_MB_UV_ROW_STRIDE" } ,\ |
| {0x014C, 0x00000000, 0xFFFFFFFF, 0, "CR_REF_Y_ROW_ADDR" } ,\ |
| {0x0150, 0x00000000, 0xFFFFFFFF, 0, "CR_REF_UV_ROW_ADDR" } ,\ |
| {0x0154, 0x00000000, 0xFFFFFFFF, 0, "CR_REF_ROW_STRIDE" } ,\ |
| {0x0158, 0x00000000, 0xFFFFFFFF, 0, "CR_ABOVE_PIX_Y_ROW_IN_ADDR" } ,\ |
| {0x015C, 0x00000000, 0xFFFFFFFF, 0, "CR_ABOVE_PIX_UV_ROW_IN_ADDR" } ,\ |
| {0x0160, 0x00000000, 0xFFFFFFFF, 0, "CR_RECON_Y_ROW_ADDR" } ,\ |
| {0x0164, 0x00000000, 0xFFFFFFFF, 0, "CR_RECON_UV_ROW_ADDR" } ,\ |
| {0x0168, 0x00000000, 0xFFFFFFFF, 0, "CR_ABOVE_PARAM_ADDR" } ,\ |
| {0x016C, 0x00000000, 0xFFFFFFFF, 0, "CR_CURR_PARAM_ADDR" } ,\ |
| {0x0170, 0x00000000, 0xFFFFFFFF, 0, "CR_BELOW_PARAM_IN_ADDR" } ,\ |
| {0x0174, 0x00000000, 0x00000FFF, 0, "CR_LRB_LOAD" } ,\ |
| {0x0178, 0x00000000, 0xFFFFFFFF, 0, "CR_BELOW_PARAM_OUT_ADDR" } ,\ |
| {0x017C, 0x00000000, 0x000FFFFF, 0, "CR_BUFFER_SIDEBAND" } ,\ |
| {0x0180, 0x00000000, 0x00000001, 0, "CR_CMPRS_ACKNOWLEDGE" } ,\ |
| {0x0184, 0x00000000, 0x000001FF, 0, "CR_CMPRS_SBLK_THRESHOLD" } ,\ |
| {0x0188, 0x00000000, 0xFFFFFFFF, 0, "CR_CMPRS_COEFF_COST_H" } ,\ |
| {0x018C, 0x00000000, 0xFFFFFFFF, 0, "CR_CMPRS_COEFF_COST_L" } ,\ |
| {0x0190, 0x00000000, 0x0000FFFF, 0, "CR_CMPRS_COEFF_THRESHOLD" } ,\ |
| {0x0194, 0x00000000, 0xFFFFFFFF, 0, "CR_CMPRS_SBLK_RIGHT" } ,\ |
| {0x0198, 0x00000000, 0x00FFFFFF, 0, "CR_CMPRS_SBLK_BOTTOM" } ,\ |
| {0x019C, 0x00000000, 0xFFFFFFFF, 0, "CR_CMPRS_TRANS_CRC" } ,\ |
| {0x01A0, 0x00000000, 0xFFFFFFFF, 0, "CR_CMPRS_QUANT_CRC" } ,\ |
| {0x01A4, 0x00000000, 0xFFFFFFFF, 0, "CR_CMPRS_DIAGNOSTIC1" } ,\ |
| {0x01A8, 0x00000000, 0x80000000, 0, "CR_CMPRS_RLE_CONTROL" } ,\ |
| {0x01AC, 0x00000000, 0x000007FF, 0, "CR_CMPRS_RLE_STATUS" } ,\ |
| {0x01B0, 0x00000000, 0x0000FFFF, 0, "CR_CMPRS_MAX_CYCLE_COUNT" } ,\ |
| {0x01B4, 0x00000000, 0x303FFFFF, 0, "CR_CMPRS_MAX_CYCLE_MB" } ,\ |
| {0x01B8, 0x00000000, 0x00000003, 0, "CR_CMPRS_MAX_CYCLE_RESET" } ,\ |
| {0x01BC, 0x00000000, 0x0000FFFF, 0, "CR_CMPRS_VLC_CRC" } ,\ |
| {0x01C0, 0x00000000, 0xFFFFFFFF, 0, "CR_ABOVE_PIX_Y_ROW_OUT_ADDR" } ,\ |
| {0x01C4, 0x00000000, 0xFFFFFFFF, 0, "CR_ABOVE_PIX_UV_ROW_OUT_ADDR" } ,\ |
| {0x01F0, 0x00000000, 0x007FFFFF, 0, "CR_IPE_LAMBDA_TABLE" } ,\ |
| {0x01F4, 0x00000000, 0x00007FFF, 0, "CR_IPE_MV_BIAS_TABLE" } ,\ |
| {0x01FC, 0x00000000, 0x000000FF, 0, "CR_IPE_QP" } ,\ |
| {0x0200, 0x00000000, 0x00007FFF, 0, "CR_IPE_CONTROL" } ,\ |
| {0x0204, 0x00000000, 0x00000007, 0, "CR_IPE_SEARCH_STATUS" } ,\ |
| {0x0208, 0x00000000, 0x0000FFFF, 0, "CR_IPE_INT_MVCOST" } ,\ |
| {0x020C, 0x00000000, 0x0000FFFF, 0, "CR_IPE_MB_SAD" } ,\ |
| {0x0210, 0x00000000, 0xFFFFFFFF, 0, "CR_IPE_DIAG1" } ,\ |
| {0x0214, 0x00000000, 0x0000FFFF, 0, "CR_IPE_QP_SLICE" } ,\ |
| {0x0218, 0x00000000, 0x00000003, 0, "CR_IPE_JITTER_FACTOR" } ,\ |
| {0x0264, 0x00000000, 0xFFFFFFFF, 0, "CR_IPE_CTRL_CRC" } ,\ |
| {0x0268, 0x00000000, 0xFFFFFFFF, 0, "CR_IPE_WDATA_CRC" } ,\ |
| {0x026C, 0x00000000, 0x00000001, 0, "CR_IPE_MB_PERFORMANCE_CLEAR" } ,\ |
| {0x0270, 0x00000000, 0x0000FFFF, 1, "CR_IPE_MB_PERFORMANCE_RESULT" } ,\ |
| {0x0274, 0x00000000, 0x003FFFFF, 1, "CR_IPE_MB_PERFORMANCE_MB_NUMBER" } ,\ |
| {0x0278, 0x00000000, 0x0000FFFF, 0, "CR_IPE_VECTOR_CLIPPING" } ,\ |
| {0x0280, 0x00008000, 0x01F08003, 0, "CR_JMCOMP_CONTROL" } ,\ |
| {0x0284, 0x00000000, 0x000FFFFF, 0, "CR_JMCOMP_JPEG_BLOCK_TYPES" } ,\ |
| {0x0288, 0x00000000, 0x00000FFF, 0, "CR_JMCOMP_JPEG_LUMA_PRED" } ,\ |
| {0x028C, 0x00000000, 0x0FFF0FFF, 0, "CR_JMCOMP_JPEG_CHROMA_PREDS" } ,\ |
| {0x0314, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CRC" } ,\ |
| {0x0318, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_VLC_CRC" } ,\ |
| {0x031C, 0x00000000, 0x0003FFFF, 0, "CR_JMCOMP_PERFORMANCE_0" } ,\ |
| {0x0320, 0x00000000, 0x003FFFFF, 0, "CR_JMCOMP_PERFORMANCE_1" } ,\ |
| {0x0324, 0x00000000, 0x00000003, 0, "CR_JMCOMP_PERFORMANCE_2" } ,\ |
| {0x0348, 0x00000000, 0x000001FF, 0, "CR_JMCOMP_QP_VALUE" } ,\ |
| {0x0370, 0x00000000, 0x0000001F, 0, "CR_SPE_ZERO_THRESH" } ,\ |
| {0x0374, 0x00000000, 0x0003FFFF, 0, "CR_SPE_INTRA16_BIAS_TABLE" } ,\ |
| {0x0378, 0x00000000, 0x0003FFFF, 0, "CR_SPE_INTER_BIAS_TABLE" } ,\ |
| {0x037C, 0x00000000, 0x00007FFF, 0, "CR_SPE_PRED_VECTOR_BIAS_TABLE" } ,\ |
| {0x0380, 0x00000000, 0x0000001F, 0, "CR_SPE_CONTROL" } ,\ |
| {0x0384, 0x00000000, 0x0001FFFF, 0, "CR_SPE_INTRA_COST" } ,\ |
| {0x038C, 0x00000000, 0x00000001, 0, "CR_SPE_REQUEST" } ,\ |
| {0x0390, 0x00000000, 0x0000FFFF, 0, "CR_SPE_INTER_SUM_MIN_SADS" } ,\ |
| {0x0394, 0x00000000, 0xFFFFFFFF, 0, "CR_SPE_DIAGNOSTIC1" } ,\ |
| {0x0398, 0x00000000, 0xFFFFFFFF, 0, "CR_SPE_INTER_SAD_SIGNATURE" } ,\ |
| {0x039C, 0x00000000, 0xFFFFFFFF, 0, "CR_SPE_INTRA_SAD_SIGNATURE" } ,\ |
| {0x03A0, 0x003CFFC2, 0xFFFFFFFF, 0, "CR_SPE_MVD_CLIP_RANGE" } ,\ |
| {0x03A4, 0x00000000, 0x0000FFFF, 1, "CR_SPE_INT_MVCOST" } ,\ |
| {0x03B0, 0x00000000, 0xFFFFFFFF, 0, "CR_IMG_MVEA_RSVD0" } ,\ |
| {0x03B4, 0x00000000, 0x0000007F, 0, "CR_MVEA_CRC_RESET" } ,\ |
| {0x03BC, 0x00000000, 0x03FF03FF, 0, "CR_SPE_MB_COUNT" } ,\ |
| {0x03D4, 0x00000000, 0x7FFF7FFF, 0, "CR_SPE_PRED_VECTOR" } ,\ |
| {0x03D8, 0x00000000, 0x0000FFFF, 0, "CR_SPE_MAX_CYCLE_COUNT" } ,\ |
| {0x03DC, 0x00000000, 0xC03FFFFF, 0, "CR_SPE_MAX_CYCLE_MB" } ,\ |
| {0x03E0, 0x00000000, 0x0000FFFF, 0, "CR_SPE_INTRA_SUM_MIN_SADS" } ,\ |
| {0x03E4, 0x00000000, 0x00000001, 0, "CR_SPE_MAX_CYCLE_RESET" } ,\ |
| {0x03E8, 0x00000000, 0x0000FFFF, 0, "CR_SEQUENCER_SYNC" } ,\ |
| {0x03EC, 0x00000000, 0x0000FFFF, 1, "CR_IPE_SKIPPED_MV" } ,\ |
| {0x02D0, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_0" },\ |
| {0x02D4, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_1" },\ |
| {0x02D8, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_2" },\ |
| {0x02DC, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_3" },\ |
| {0x02E0, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_4" },\ |
| {0x02E4, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_5" },\ |
| {0x02E8, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_6" },\ |
| {0x02EC, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_7" },\ |
| {0x02F0, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_8" },\ |
| {0x02F4, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_9" },\ |
| {0x02F8, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_10" },\ |
| {0x02FC, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_11" },\ |
| {0x0300, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_12" },\ |
| {0x0304, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_13" },\ |
| {0x0308, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_14" },\ |
| {0x030C, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_15" },\ |
| {0x0290, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_0" },\ |
| {0x0294, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_1" },\ |
| {0x0298, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_2" },\ |
| {0x029C, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_3" },\ |
| {0x02A0, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_4" },\ |
| {0x02A4, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_5" },\ |
| {0x02A8, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_6" },\ |
| {0x02AC, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_7" },\ |
| {0x02B0, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_8" },\ |
| {0x02B4, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_9" },\ |
| {0x02B8, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_10" },\ |
| {0x02BC, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_11" },\ |
| {0x02C0, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_12" },\ |
| {0x02C4, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_13" },\ |
| {0x02C8, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_14" },\ |
| {0x02CC, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_15" },\ |
| {0x0080, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_0" },\ |
| {0x0084, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_1" },\ |
| {0x0088, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_2" },\ |
| {0x008C, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_3" },\ |
| {0x0090, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_4" },\ |
| {0x0094, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_5" },\ |
| {0x0098, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_6" },\ |
| {0x009C, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_7" },\ |
| {0x00A0, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_8" },\ |
| {0x00A4, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_9" },\ |
| {0x00A8, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_10" },\ |
| {0x00AC, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_11" },\ |
| {0x00B0, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_12" },\ |
| {0x00B4, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_13" },\ |
| {0x00B8, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_14" },\ |
| {0x00BC, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_15" },\ |
| {0x00C0, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_16" },\ |
| {0x00C4, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_17" },\ |
| {0x00C8, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_18" },\ |
| {0x00CC, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_19" },\ |
| {0x00D0, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_20" },\ |
| {0x00D4, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_21" },\ |
| {0x00D8, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_22" },\ |
| {0x00DC, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_23" },\ |
| {0x00E0, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_24" },\ |
| {0x00E4, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_25" },\ |
| {0x00E8, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_26" },\ |
| {0x00EC, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_27" },\ |
| {0x00F0, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_28" },\ |
| {0x00F4, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_29" },\ |
| {0x00F8, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_30" },\ |
| {0x00FC, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_31" },\ |
| { 0 }} |
| |
| #define MVEA_REGS_INIT(uBase) \ |
| { \ |
| int n;\ |
| MVEA_REG_DEFAULT_TABLE;\ |
| for (n = 0; n < sizeof(MVEA_Defaults)/ sizeof(MVEA_Defaults[0] ) -1; n++)\ |
| {\ |
| RegWriteNoTrap(MVEA_Defaults[n].uRegOffset + uBase, MVEA_Defaults[n].uRegDefault); \ |
| }\ |
| } |
