| /* |
| * Copyright (c) 2011 Intel Corporation. All Rights Reserved. |
| * Copyright (c) Imagination Technologies Limited, UK |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation the rights to use, copy, modify, merge, publish, |
| * distribute, sub license, and/or sell copies of the Software, and to |
| * permit persons to whom the Software is furnished to do so, subject to |
| * the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial portions |
| * of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| |
| /****************************************************************************** |
| |
| @File msvdx_vec_reg_io2.h |
| |
| @Title MSVDX Offsets |
| |
| @Platform </b>\n |
| |
| @Description </b>\n This file contains the MSVDX_VEC_REG_IO2_H Defintions. |
| |
| ******************************************************************************/ |
| #if !defined (__MSVDX_VEC_REG_IO2_H__) |
| #define __MSVDX_VEC_REG_IO2_H__ |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_OFFSET (0x0018) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_STRIDE (12) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_NO_ENTRIES (4) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_CONTROL SR_MASTER_SELECT |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_MASTER_SELECT_MASK (0x00000300) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_MASTER_SELECT_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_MASTER_SELECT_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_CONTROL SR_RBDU_EXTRACT |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_RBDU_EXTRACT_MASK (0x00000008) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_RBDU_EXTRACT_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_RBDU_EXTRACT_SHIFT (3) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_CONTROL SR_READ_MODE |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_READ_MODE_MASK (0x00000004) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_READ_MODE_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_READ_MODE_SHIFT (2) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_CONTROL SR_PREEMPT |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_PREEMPT_MASK (0x00000002) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_PREEMPT_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_PREEMPT_SHIFT (1) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_CONTROL SR_SW_RESET |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_SW_RESET_MASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_SW_RESET_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_CONTROL_SR_SW_RESET_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_BYTE_COUNT_OFFSET (0x001C) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_BYTE_COUNT_STRIDE (12) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_BYTE_COUNT_NO_ENTRIES (4) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_BYTE_COUNT SR_BYTE_COUNT |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_BYTE_COUNT_SR_BYTE_COUNT_MASK (0x00FFFFFF) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_BYTE_COUNT_SR_BYTE_COUNT_LSBMASK (0x00FFFFFF) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_BYTE_COUNT_SR_BYTE_COUNT_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_STREAMIN_OFFSET (0x0020) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_STREAMIN_STRIDE (12) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_STREAMIN_NO_ENTRIES (4) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_STREAMIN SR_STREAMIN |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_STREAMIN_SR_STREAMIN_MASK (0x000000FF) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_STREAMIN_SR_STREAMIN_LSBMASK (0x000000FF) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_STREAMIN_SR_STREAMIN_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_CONTROL_OFFSET (0x0000) |
| |
| // MSVDX_VEC CR_VEC_CONTROL BITPLANE_FETCH_ENABLE |
| #define MSVDX_VEC_CR_VEC_CONTROL_BITPLANE_FETCH_ENABLE_MASK (0x00010000) |
| #define MSVDX_VEC_CR_VEC_CONTROL_BITPLANE_FETCH_ENABLE_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_CONTROL_BITPLANE_FETCH_ENABLE_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_CONTROL ENTDEC_ENABLE_BE |
| #define MSVDX_VEC_CR_VEC_CONTROL_ENTDEC_ENABLE_BE_MASK (0x00000100) |
| #define MSVDX_VEC_CR_VEC_CONTROL_ENTDEC_ENABLE_BE_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_CONTROL_ENTDEC_ENABLE_BE_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_CONTROL ENTDEC_BITPLANE_DECODE_ENABLE |
| #define MSVDX_VEC_CR_VEC_CONTROL_ENTDEC_BITPLANE_DECODE_ENABLE_MASK (0x00000002) |
| #define MSVDX_VEC_CR_VEC_CONTROL_ENTDEC_BITPLANE_DECODE_ENABLE_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_CONTROL_ENTDEC_BITPLANE_DECODE_ENABLE_SHIFT (1) |
| |
| // MSVDX_VEC CR_VEC_CONTROL ENTDEC_ENABLE_FE |
| #define MSVDX_VEC_CR_VEC_CONTROL_ENTDEC_ENABLE_FE_MASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_CONTROL_ENTDEC_ENABLE_FE_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_CONTROL_ENTDEC_ENABLE_FE_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_OFFSET (0x000C) |
| |
| // MSVDX_VEC CR_VEC_ENTDEC_FE_CONTROL VLRIF_DMAC_BURST_LENGTH |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_VLRIF_DMAC_BURST_LENGTH_MASK (0x00000100) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_VLRIF_DMAC_BURST_LENGTH_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_VLRIF_DMAC_BURST_LENGTH_SHIFT (8) |
| |
| // MSVDX_VEC, CR_VEC_ENTDEC_FE_CONTROL, ENTDEC_FE_EXTENDED_MODE |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_ENTDEC_FE_EXTENDED_MODE_MASK (0x00000020) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_ENTDEC_FE_EXTENDED_MODE_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_ENTDEC_FE_EXTENDED_MODE_SHIFT (5) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_ENTDEC_FE_EXTENDED_MODE_SIGNED_FIELD 0 |
| |
| // MSVDX_VEC CR_VEC_ENTDEC_FE_CONTROL ENTDEC_FE_PROFILE |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_ENTDEC_FE_PROFILE_MASK (0x00000018) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_ENTDEC_FE_PROFILE_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_ENTDEC_FE_PROFILE_SHIFT (3) |
| |
| // MSVDX_VEC CR_VEC_ENTDEC_FE_CONTROL ENTDEC_FE_MODE |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_ENTDEC_FE_MODE_MASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_ENTDEC_FE_MODE_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_ENTDEC_FE_MODE_SHIFT (0) |
| |
| // MSVDX_VEC, CR_VEC_ENTDEC_BE_CONTROL, ENTDEC_BE_EXTENDED_MODE |
| #define MSVDX_VEC_CR_VEC_ENTDEC_BE_CONTROL_ENTDEC_BE_EXTENDED_MODE_MASK (0x00000020) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_BE_CONTROL_ENTDEC_BE_EXTENDED_MODE_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_BE_CONTROL_ENTDEC_BE_EXTENDED_MODE_SHIFT (5) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_BE_CONTROL_ENTDEC_BE_EXTENDED_MODE_SIGNED_FIELD IMG_FALSE |
| |
| #define MSVDX_VEC_CR_VEC_ENTDEC_BE_CONTROL_OFFSET (0x0010) |
| |
| // MSVDX_VEC CR_VEC_ENTDEC_BE_CONTROL ENTDEC_BE_PROFILE |
| #define MSVDX_VEC_CR_VEC_ENTDEC_BE_CONTROL_ENTDEC_BE_PROFILE_MASK (0x00000018) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_BE_CONTROL_ENTDEC_BE_PROFILE_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_BE_CONTROL_ENTDEC_BE_PROFILE_SHIFT (3) |
| |
| // MSVDX_VEC CR_VEC_ENTDEC_BE_CONTROL ENTDEC_BE_MODE |
| #define MSVDX_VEC_CR_VEC_ENTDEC_BE_CONTROL_ENTDEC_BE_MODE_MASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_BE_CONTROL_ENTDEC_BE_MODE_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_BE_CONTROL_ENTDEC_BE_MODE_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_SELECT_OFFSET (0x0014) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_SELECT SR_ENTDEC_SELECTOR |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_SELECT_SR_ENTDEC_SELECTOR_MASK (0x00030000) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_SELECT_SR_ENTDEC_SELECTOR_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_SELECT_SR_ENTDEC_SELECTOR_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_SELECT SR_COPRO_SELECTOR |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_SELECT_SR_COPRO_SELECTOR_MASK (0x00000300) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_SELECT_SR_COPRO_SELECTOR_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_SELECT_SR_COPRO_SELECTOR_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_SELECT SR_RESET_METRICS |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_SELECT_SR_RESET_METRICS_MASK (0x00000010) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_SELECT_SR_RESET_METRICS_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_SELECT_SR_RESET_METRICS_SHIFT (4) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_SELECT SR_REGIF_SELECTOR |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_SELECT_SR_REGIF_SELECTOR_MASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_SELECT_SR_REGIF_SELECTOR_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_SELECT_SR_REGIF_SELECTOR_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_OFFSET (0x005C) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_COPRO_RESP_MSWRD SR_RESP_VALID |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_RESP_VALID_MASK (0x80000000) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_RESP_VALID_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_RESP_VALID_SHIFT (31) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_COPRO_RESP_MSWRD SR_BYTE_ALIGNED |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_BYTE_ALIGNED_MASK (0x00000010) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_BYTE_ALIGNED_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_BYTE_ALIGNED_SHIFT (4) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_COPRO_RESP_MSWRD SR_MORE_RBSP |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_MORE_RBSP_MASK (0x00000008) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_MORE_RBSP_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_MORE_RBSP_SHIFT (3) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_COPRO_RESP_MSWRD SR_RESP_EXPG_ERROR |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_RESP_EXPG_ERROR_MASK (0x00000004) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_RESP_EXPG_ERROR_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_RESP_EXPG_ERROR_SHIFT (2) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_COPRO_RESP_MSWRD SR_RESP_SCP_OR_EOD |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_RESP_SCP_OR_EOD_MASK (0x00000002) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_RESP_SCP_OR_EOD_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_RESP_SCP_OR_EOD_SHIFT (1) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_COPRO_RESP_MSWRD SR_RESP_PREEMPTED |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_RESP_PREEMPTED_MASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_RESP_PREEMPTED_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_MSWRD_SR_RESP_PREEMPTED_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_LSWRD_OFFSET (0x0060) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_COPRO_RESP_LSWRD SR_RESP_VALUE |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_LSWRD_SR_RESP_VALUE_MASK (0xFFFFFFFF) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_LSWRD_SR_RESP_VALUE_LSBMASK (0xFFFFFFFF) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_RESP_LSWRD_SR_RESP_VALUE_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_CMD_MSWRD_OFFSET (0x0064) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_COPRO_CMD_MSWRD SR_PRE_FLUSH |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_CMD_MSWRD_SR_PRE_FLUSH_MASK (0x00001F00) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_CMD_MSWRD_SR_PRE_FLUSH_LSBMASK (0x0000001F) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_CMD_MSWRD_SR_PRE_FLUSH_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_COPRO_CMD_MSWRD SR_READ_PEEK |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_CMD_MSWRD_SR_READ_PEEK_MASK (0x000000F8) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_CMD_MSWRD_SR_READ_PEEK_LSBMASK (0x0000001F) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_CMD_MSWRD_SR_READ_PEEK_SHIFT (3) |
| |
| // MSVDX_VEC CR_VEC_SHIFTREG_COPRO_CMD_MSWRD SR_ACCESS_MODE |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_CMD_MSWRD_SR_ACCESS_MODE_MASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_CMD_MSWRD_SR_ACCESS_MODE_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_SHIFTREG_COPRO_CMD_MSWRD_SR_ACCESS_MODE_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_OFFSET (0x0068) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL0 RENDEC_DEC_INITIALISE |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_DEC_INITIALISE_MASK (0x00000040) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_DEC_INITIALISE_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_DEC_INITIALISE_SHIFT (6) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL0 RENDEC_ENC_INITIALISE |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_ENC_INITIALISE_MASK (0x00000020) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_ENC_INITIALISE_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_ENC_INITIALISE_SHIFT (5) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL0 RENDEC_ENC_ERROR_RECOVERY |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_ENC_ERROR_RECOVERY_MASK (0x00000010) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_ENC_ERROR_RECOVERY_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_ENC_ERROR_RECOVERY_SHIFT (4) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL0 RENDEC_MTX_BLOCK_SEARCH |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_MTX_BLOCK_SEARCH_MASK (0x00000008) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_MTX_BLOCK_SEARCH_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_MTX_BLOCK_SEARCH_SHIFT (3) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL0 RENDEC_SLICE_SKIP |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_SLICE_SKIP_MASK (0x00000004) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_SLICE_SKIP_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_SLICE_SKIP_SHIFT (2) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL0 RENDEC_FLUSH |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_FLUSH_MASK (0x00000002) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_FLUSH_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_FLUSH_SHIFT (1) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL0 RENDEC_INITIALISE |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_INITIALISE_MASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_INITIALISE_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL0_RENDEC_INITIALISE_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_OFFSET (0x006C) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL1 RENDEC_DEC_DISABLE |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_DEC_DISABLE_MASK (0x08000000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_DEC_DISABLE_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_DEC_DISABLE_SHIFT (27) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL1 RENDEC_DEC_SLICE_MODE |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_DEC_SLICE_MODE_MASK (0x04000000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_DEC_SLICE_MODE_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_DEC_SLICE_MODE_SHIFT (26) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL1 RENDEC_STREAM_END |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_STREAM_END_MASK (0x02000000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_STREAM_END_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_STREAM_END_SHIFT (25) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL1 RENDEC_EXTERNAL_MEMORY |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_EXTERNAL_MEMORY_MASK (0x01000000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_EXTERNAL_MEMORY_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_EXTERNAL_MEMORY_SHIFT (24) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL1 RENDEC_BURST_SIZE_W |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_BURST_SIZE_W_MASK (0x000C0000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_BURST_SIZE_W_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_BURST_SIZE_W_SHIFT (18) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL1 RENDEC_BURST_SIZE_R |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_BURST_SIZE_R_MASK (0x00030000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_BURST_SIZE_R_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_BURST_SIZE_R_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTROL1 RENDEC_DECODE_START_SIZE |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_DECODE_START_SIZE_MASK (0x000000FF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_DECODE_START_SIZE_LSBMASK (0x000000FF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTROL1_RENDEC_DECODE_START_SIZE_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_BUFFER_SIZE_OFFSET (0x0070) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_BUFFER_SIZE RENDEC_BUFFER_SIZE1 |
| #define MSVDX_VEC_CR_VEC_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE1_MASK (0xFFFF0000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE1_LSBMASK (0x0000FFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE1_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_BUFFER_SIZE RENDEC_BUFFER_SIZE0 |
| #define MSVDX_VEC_CR_VEC_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE0_MASK (0x0000FFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE0_LSBMASK (0x0000FFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE0_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_BASE_ADDR0_OFFSET (0x0074) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_BASE_ADDR0 RENDEC_BASE_ADDR0 |
| #define MSVDX_VEC_CR_VEC_RENDEC_BASE_ADDR0_RENDEC_BASE_ADDR0_MASK (0xFFFFF000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_BASE_ADDR0_RENDEC_BASE_ADDR0_LSBMASK (0x000FFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_BASE_ADDR0_RENDEC_BASE_ADDR0_SHIFT (12) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_BASE_ADDR1_OFFSET (0x0078) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_BASE_ADDR1 RENDEC_BASE_ADDR1 |
| #define MSVDX_VEC_CR_VEC_RENDEC_BASE_ADDR1_RENDEC_BASE_ADDR1_MASK (0xFFFFF000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_BASE_ADDR1_RENDEC_BASE_ADDR1_LSBMASK (0x000FFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_BASE_ADDR1_RENDEC_BASE_ADDR1_SHIFT (12) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_WRITE_ADDR0_OFFSET (0x007C) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_WRITE_ADDR0 RENDEC_WRITE_ADDR0 |
| #define MSVDX_VEC_CR_VEC_RENDEC_WRITE_ADDR0_RENDEC_WRITE_ADDR0_MASK (0x0FFFFFF0) |
| #define MSVDX_VEC_CR_VEC_RENDEC_WRITE_ADDR0_RENDEC_WRITE_ADDR0_LSBMASK (0x00FFFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_WRITE_ADDR0_RENDEC_WRITE_ADDR0_SHIFT (4) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_WRITE_ADDR1_OFFSET (0x0080) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_WRITE_ADDR1 RENDEC_WRITE_ADDR1 |
| #define MSVDX_VEC_CR_VEC_RENDEC_WRITE_ADDR1_RENDEC_WRITE_ADDR1_MASK (0x0FFFFFF0) |
| #define MSVDX_VEC_CR_VEC_RENDEC_WRITE_ADDR1_RENDEC_WRITE_ADDR1_LSBMASK (0x00FFFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_WRITE_ADDR1_RENDEC_WRITE_ADDR1_SHIFT (4) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_READ_ADDR0_OFFSET (0x0084) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_READ_ADDR0 RENDEC_READ_ADDR0 |
| #define MSVDX_VEC_CR_VEC_RENDEC_READ_ADDR0_RENDEC_READ_ADDR0_MASK (0x0FFFFFF0) |
| #define MSVDX_VEC_CR_VEC_RENDEC_READ_ADDR0_RENDEC_READ_ADDR0_LSBMASK (0x00FFFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_READ_ADDR0_RENDEC_READ_ADDR0_SHIFT (4) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_READ_ADDR1_OFFSET (0x0088) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_READ_ADDR1 RENDEC_READ_ADDR1 |
| #define MSVDX_VEC_CR_VEC_RENDEC_READ_ADDR1_RENDEC_READ_ADDR1_MASK (0x0FFFFFF0) |
| #define MSVDX_VEC_CR_VEC_RENDEC_READ_ADDR1_RENDEC_READ_ADDR1_LSBMASK (0x00FFFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_READ_ADDR1_RENDEC_READ_ADDR1_SHIFT (4) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_DATA_SIZE0_OFFSET (0x008C) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_DATA_SIZE0 RENDEC_DATA_SIZE0 |
| #define MSVDX_VEC_CR_VEC_RENDEC_DATA_SIZE0_RENDEC_DATA_SIZE0_MASK (0x0FFFFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_DATA_SIZE0_RENDEC_DATA_SIZE0_LSBMASK (0x0FFFFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_DATA_SIZE0_RENDEC_DATA_SIZE0_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_DATA_SIZE1_OFFSET (0x0090) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_DATA_SIZE1 RENDEC_DATA_SIZE1 |
| #define MSVDX_VEC_CR_VEC_RENDEC_DATA_SIZE1_RENDEC_DATA_SIZE1_MASK (0x0FFFFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_DATA_SIZE1_RENDEC_DATA_SIZE1_LSBMASK (0x0FFFFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_DATA_SIZE1_RENDEC_DATA_SIZE1_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_WRITE_DATA_OFFSET (0x0094) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_WRITE_DATA RENDEC_WRITE_DATA |
| #define MSVDX_VEC_CR_VEC_RENDEC_WRITE_DATA_RENDEC_WRITE_DATA_MASK (0xFFFFFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_WRITE_DATA_RENDEC_WRITE_DATA_LSBMASK (0xFFFFFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_WRITE_DATA_RENDEC_WRITE_DATA_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_READ_DATA_OFFSET (0x0098) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_READ_DATA RENDEC_READ_DATA |
| #define MSVDX_VEC_CR_VEC_RENDEC_READ_DATA_RENDEC_READ_DATA_MASK (0xFFFFFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_READ_DATA_RENDEC_READ_DATA_LSBMASK (0xFFFFFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_READ_DATA_RENDEC_READ_DATA_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_OFFSET (0x009C) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_STATUS RENDEC_DECODED_DATA |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_DECODED_DATA_MASK (0xFFFF0000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_DECODED_DATA_LSBMASK (0x0000FFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_DECODED_DATA_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_STATUS RENDEC_ENC_BUFF_STATUS |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_ENC_BUFF_STATUS_MASK (0x00000800) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_ENC_BUFF_STATUS_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_ENC_BUFF_STATUS_SHIFT (11) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_STATUS RENDEC_ENC_CTRL_STATUS |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_ENC_CTRL_STATUS_MASK (0x00000400) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_ENC_CTRL_STATUS_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_ENC_CTRL_STATUS_SHIFT (10) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_STATUS RENDEC_ERROR_FLAG |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_ERROR_FLAG_MASK (0x00000200) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_ERROR_FLAG_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_ERROR_FLAG_SHIFT (9) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_STATUS RENDEC_HEADER_FLAG |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_HEADER_FLAG_MASK (0x00000100) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_HEADER_FLAG_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_HEADER_FLAG_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_STATUS RENDEC_DFIFO1_STATUS |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_DFIFO1_STATUS_MASK (0x00000008) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_DFIFO1_STATUS_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_DFIFO1_STATUS_SHIFT (3) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_STATUS RENDEC_DFIFO0_STATUS |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_DFIFO0_STATUS_MASK (0x00000004) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_DFIFO0_STATUS_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_DFIFO0_STATUS_SHIFT (2) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_STATUS RENDEC_EFIFO1_STATUS |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_EFIFO1_STATUS_MASK (0x00000002) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_EFIFO1_STATUS_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_EFIFO1_STATUS_SHIFT (1) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_STATUS RENDEC_EFIFO0_STATUS |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_EFIFO0_STATUS_MASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_EFIFO0_STATUS_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_RENDEC_STATUS_RENDEC_EFIFO0_STATUS_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_SLICE_COUNT_OFFSET (0x00A0) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_SLICE_COUNT RENDEC_SLICE_COUNT |
| #define MSVDX_VEC_CR_VEC_RENDEC_SLICE_COUNT_RENDEC_SLICE_COUNT_MASK (0x000FFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_SLICE_COUNT_RENDEC_SLICE_COUNT_LSBMASK (0x000FFFFF) |
| #define MSVDX_VEC_CR_VEC_RENDEC_SLICE_COUNT_RENDEC_SLICE_COUNT_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_ENTDEC_INFORMATION_OFFSET (0x00AC) |
| |
| // MSVDX_VEC CR_VEC_ENTDEC_INFORMATION FE_ENTDEC_LATEST_MB_ADDR_Y |
| #define MSVDX_VEC_CR_VEC_ENTDEC_INFORMATION_FE_ENTDEC_LATEST_MB_ADDR_Y_MASK (0x7F000000) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_INFORMATION_FE_ENTDEC_LATEST_MB_ADDR_Y_LSBMASK (0x0000007F) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_INFORMATION_FE_ENTDEC_LATEST_MB_ADDR_Y_SHIFT (24) |
| |
| // MSVDX_VEC CR_VEC_ENTDEC_INFORMATION FE_ENTDEC_LATEST_MB_ADDR_X |
| #define MSVDX_VEC_CR_VEC_ENTDEC_INFORMATION_FE_ENTDEC_LATEST_MB_ADDR_X_MASK (0x007F0000) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_INFORMATION_FE_ENTDEC_LATEST_MB_ADDR_X_LSBMASK (0x0000007F) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_INFORMATION_FE_ENTDEC_LATEST_MB_ADDR_X_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_ENTDEC_INFORMATION FE_ENTDEC_STATUS |
| #define MSVDX_VEC_CR_VEC_ENTDEC_INFORMATION_FE_ENTDEC_STATUS_MASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_INFORMATION_FE_ENTDEC_STATUS_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_ENTDEC_INFORMATION_FE_ENTDEC_STATUS_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_DIRECT_MODE_CONTROL_OFFSET (0x00B8) |
| |
| // MSVDX_VEC CR_VEC_DIRECT_MODE_CONTROL DIRECT_MODE |
| #define MSVDX_VEC_CR_VEC_DIRECT_MODE_CONTROL_DIRECT_MODE_MASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_DIRECT_MODE_CONTROL_DIRECT_MODE_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_DIRECT_MODE_CONTROL_DIRECT_MODE_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_DIRECT_MODE_DATA0_OFFSET (0x00BC) |
| |
| // MSVDX_VEC CR_VEC_DIRECT_MODE_DATA0 DIRECT_DATA0 |
| #define MSVDX_VEC_CR_VEC_DIRECT_MODE_DATA0_DIRECT_DATA0_MASK (0xFFFFFFFF) |
| #define MSVDX_VEC_CR_VEC_DIRECT_MODE_DATA0_DIRECT_DATA0_LSBMASK (0xFFFFFFFF) |
| #define MSVDX_VEC_CR_VEC_DIRECT_MODE_DATA0_DIRECT_DATA0_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_COMMAND_SIGNATURE_OFFSET (0x00C0) |
| |
| // MSVDX_VEC CR_VEC_COMMAND_SIGNATURE COMMAND_SIGNATURE |
| #define MSVDX_VEC_CR_VEC_COMMAND_SIGNATURE_COMMAND_SIGNATURE_MASK (0xFFFFFFFF) |
| #define MSVDX_VEC_CR_VEC_COMMAND_SIGNATURE_COMMAND_SIGNATURE_LSBMASK (0xFFFFFFFF) |
| #define MSVDX_VEC_CR_VEC_COMMAND_SIGNATURE_COMMAND_SIGNATURE_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_IXFORM_SIGNATURE_OFFSET (0x00C4) |
| |
| // MSVDX_VEC CR_VEC_IXFORM_SIGNATURE IXFORM_SIGNATURE |
| #define MSVDX_VEC_CR_VEC_IXFORM_SIGNATURE_IXFORM_SIGNATURE_MASK (0xFFFFFFFF) |
| #define MSVDX_VEC_CR_VEC_IXFORM_SIGNATURE_IXFORM_SIGNATURE_LSBMASK (0xFFFFFFFF) |
| #define MSVDX_VEC_CR_VEC_IXFORM_SIGNATURE_IXFORM_SIGNATURE_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_ISCAN_MBPARAMS0_OFFSET (0x00C8) |
| |
| // MSVDX_VEC CR_VEC_ISCAN_MBPARAMS0 IS_H264_MB_FIELD_DECODING_FLAG |
| #define MSVDX_VEC_CR_VEC_ISCAN_MBPARAMS0_IS_H264_MB_FIELD_DECODING_FLAG_MASK (0x00000002) |
| #define MSVDX_VEC_CR_VEC_ISCAN_MBPARAMS0_IS_H264_MB_FIELD_DECODING_FLAG_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_ISCAN_MBPARAMS0_IS_H264_MB_FIELD_DECODING_FLAG_SHIFT (1) |
| |
| // MSVDX_VEC CR_VEC_ISCAN_MBPARAMS0 IS_AC_PRED_FLAG |
| #define MSVDX_VEC_CR_VEC_ISCAN_MBPARAMS0_IS_AC_PRED_FLAG_MASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_ISCAN_MBPARAMS0_IS_AC_PRED_FLAG_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_ISCAN_MBPARAMS0_IS_AC_PRED_FLAG_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_OFFSET (0x00CC) |
| |
| // MSVDX_VEC CR_VEC_IQ_MBPARAMS0 IQ_EMPTY_MB_ABOVE_FLAG |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_EMPTY_MB_ABOVE_FLAG_MASK (0x40000000) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_EMPTY_MB_ABOVE_FLAG_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_EMPTY_MB_ABOVE_FLAG_SHIFT (30) |
| |
| // MSVDX_VEC CR_VEC_IQ_MBPARAMS0 IQ_EMPTY_MB_LEFT_FLAG |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_EMPTY_MB_LEFT_FLAG_MASK (0x20000000) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_EMPTY_MB_LEFT_FLAG_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_EMPTY_MB_LEFT_FLAG_SHIFT (29) |
| |
| // MSVDX_VEC CR_VEC_IQ_MBPARAMS0 IQ_EMPTY_MB_ABOVELEFT_FLAG |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_EMPTY_MB_ABOVELEFT_FLAG_MASK (0x10000000) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_EMPTY_MB_ABOVELEFT_FLAG_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_EMPTY_MB_ABOVELEFT_FLAG_SHIFT (28) |
| |
| // MSVDX_VEC CR_VEC_IQ_MBPARAMS0 IQ_AC_PRED_FLAG |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_AC_PRED_FLAG_MASK (0x01000000) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_AC_PRED_FLAG_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_AC_PRED_FLAG_SHIFT (24) |
| |
| // MSVDX_VEC CR_VEC_IQ_MBPARAMS0 IQ_H264_QPCR |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_H264_QPCR_MASK (0x003F0000) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_H264_QPCR_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_H264_QPCR_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_IQ_MBPARAMS0 IQ_H264_QPCB |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_H264_QPCB_MASK (0x00003F00) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_H264_QPCB_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_H264_QPCB_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_IQ_MBPARAMS0 IQ_QUANTISER_SCALE |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_QUANTISER_SCALE_MASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_QUANTISER_SCALE_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS0_IQ_QUANTISER_SCALE_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS1_OFFSET (0x00D0) |
| |
| // MSVDX_VEC CR_VEC_IQ_MBPARAMS1 IQ_VR_ABOVELEFTMB_BASEADDR |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS1_IQ_VR_ABOVELEFTMB_BASEADDR_MASK (0x3FF00000) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS1_IQ_VR_ABOVELEFTMB_BASEADDR_LSBMASK (0x000003FF) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS1_IQ_VR_ABOVELEFTMB_BASEADDR_SHIFT (20) |
| |
| // MSVDX_VEC CR_VEC_IQ_MBPARAMS1 IQ_VR_CURRMB_BASEADDR |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS1_IQ_VR_CURRMB_BASEADDR_MASK (0x000FFC00) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS1_IQ_VR_CURRMB_BASEADDR_LSBMASK (0x000003FF) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS1_IQ_VR_CURRMB_BASEADDR_SHIFT (10) |
| |
| // MSVDX_VEC CR_VEC_IQ_MBPARAMS1 IQ_VR_ABOVEMB_BASEADDR |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS1_IQ_VR_ABOVEMB_BASEADDR_MASK (0x000003FF) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS1_IQ_VR_ABOVEMB_BASEADDR_LSBMASK (0x000003FF) |
| #define MSVDX_VEC_CR_VEC_IQ_MBPARAMS1_IQ_VR_ABOVEMB_BASEADDR_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_BUF_POINTER_OFFSET (0x00D8) |
| |
| // MSVDX_VEC CR_VEC_VLR_COMMANDS_BUF_POINTER VLR_COMMANDS_BUF_POINTER1 |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_BUF_POINTER_VLR_COMMANDS_BUF_POINTER1_MASK (0x003FF000) |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_BUF_POINTER_VLR_COMMANDS_BUF_POINTER1_LSBMASK (0x000003FF) |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_BUF_POINTER_VLR_COMMANDS_BUF_POINTER1_SHIFT (12) |
| |
| // MSVDX_VEC CR_VEC_VLR_COMMANDS_BUF_POINTER VLR_COMMANDS_BUF_POINTER2 |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_BUF_POINTER_VLR_COMMANDS_BUF_POINTER2_MASK (0x00000FFC) |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_BUF_POINTER_VLR_COMMANDS_BUF_POINTER2_LSBMASK (0x000003FF) |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_BUF_POINTER_VLR_COMMANDS_BUF_POINTER2_SHIFT (2) |
| |
| #define MSVDX_VEC_CR_VEC_CIRC_BUFF_BASE_ADDR_OFFSET (0x00DC) |
| |
| // MSVDX_VEC CR_VEC_CIRC_BUFF_BASE_ADDR CIRC_BUFF_BASE_ADDR |
| #define MSVDX_VEC_CR_VEC_CIRC_BUFF_BASE_ADDR_CIRC_BUFF_BASE_ADDR_MASK (0x00000FFC) |
| #define MSVDX_VEC_CR_VEC_CIRC_BUFF_BASE_ADDR_CIRC_BUFF_BASE_ADDR_LSBMASK (0x000003FF) |
| #define MSVDX_VEC_CR_VEC_CIRC_BUFF_BASE_ADDR_CIRC_BUFF_BASE_ADDR_SHIFT (2) |
| |
| #define MSVDX_VEC_CR_VEC_SGM_BITPLANE_BASE_ADDR_OFFSET (0x00E0) |
| |
| // MSVDX_VEC CR_VEC_SGM_BITPLANE_BASE_ADDR SGM_BITPLANE_BASE_ADDR |
| #define MSVDX_VEC_CR_VEC_SGM_BITPLANE_BASE_ADDR_SGM_BITPLANE_BASE_ADDR_MASK (0x00000FFC) |
| #define MSVDX_VEC_CR_VEC_SGM_BITPLANE_BASE_ADDR_SGM_BITPLANE_BASE_ADDR_LSBMASK (0x000003FF) |
| #define MSVDX_VEC_CR_VEC_SGM_BITPLANE_BASE_ADDR_SGM_BITPLANE_BASE_ADDR_SHIFT (2) |
| |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_STORE_OFFSET (0x00E4) |
| |
| // MSVDX_VEC CR_VEC_VLR_COMMANDS_STORE VLR_COMMANDS_STORE_BASE_ADDRESS |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_STORE_VLR_COMMANDS_STORE_BASE_ADDRESS_MASK (0x00000FFC) |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_STORE_VLR_COMMANDS_STORE_BASE_ADDRESS_LSBMASK (0x000003FF) |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_STORE_VLR_COMMANDS_STORE_BASE_ADDRESS_SHIFT (2) |
| |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_NUM_OFFSET (0x00E8) |
| |
| // MSVDX_VEC CR_VEC_VLR_COMMANDS_NUM VLR_COMMANDS_STORE_NUMBER_OF_CMDS |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_NUM_VLR_COMMANDS_STORE_NUMBER_OF_CMDS_MASK (0x0000007F) |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_NUM_VLR_COMMANDS_STORE_NUMBER_OF_CMDS_LSBMASK (0x0000007F) |
| #define MSVDX_VEC_CR_VEC_VLR_COMMANDS_NUM_VLR_COMMANDS_STORE_NUMBER_OF_CMDS_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR0_OFFSET (0x00EC) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR0 VLC_TABLE_ADDR0 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR0_VLC_TABLE_ADDR0_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR0_VLC_TABLE_ADDR0_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR0_VLC_TABLE_ADDR0_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR0 VLC_TABLE_ADDR1 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR0_VLC_TABLE_ADDR1_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR0_VLC_TABLE_ADDR1_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR0_VLC_TABLE_ADDR1_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR1_OFFSET (0x00F0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR1 VLC_TABLE_ADDR2 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR1_VLC_TABLE_ADDR2_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR1_VLC_TABLE_ADDR2_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR1_VLC_TABLE_ADDR2_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR1 VLC_TABLE_ADDR3 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR1_VLC_TABLE_ADDR3_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR1_VLC_TABLE_ADDR3_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR1_VLC_TABLE_ADDR3_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR2_OFFSET (0x00F4) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR2 VLC_TABLE_ADDR4 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR2_VLC_TABLE_ADDR4_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR2_VLC_TABLE_ADDR4_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR2_VLC_TABLE_ADDR4_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR2 VLC_TABLE_ADDR5 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR2_VLC_TABLE_ADDR5_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR2_VLC_TABLE_ADDR5_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR2_VLC_TABLE_ADDR5_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR3_OFFSET (0x00F8) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR3 VLC_TABLE_ADDR6 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR3_VLC_TABLE_ADDR6_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR3_VLC_TABLE_ADDR6_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR3_VLC_TABLE_ADDR6_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR3 VLC_TABLE_ADDR7 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR3_VLC_TABLE_ADDR7_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR3_VLC_TABLE_ADDR7_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR3_VLC_TABLE_ADDR7_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR4_OFFSET (0x00FC) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR4 VLC_TABLE_ADDR8 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR4_VLC_TABLE_ADDR8_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR4_VLC_TABLE_ADDR8_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR4_VLC_TABLE_ADDR8_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR4 VLC_TABLE_ADDR9 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR4_VLC_TABLE_ADDR9_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR4_VLC_TABLE_ADDR9_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR4_VLC_TABLE_ADDR9_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR5_OFFSET (0x0100) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR5 VLC_TABLE_ADDR10 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR5_VLC_TABLE_ADDR10_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR5_VLC_TABLE_ADDR10_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR5_VLC_TABLE_ADDR10_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR5 VLC_TABLE_ADDR11 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR5_VLC_TABLE_ADDR11_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR5_VLC_TABLE_ADDR11_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR5_VLC_TABLE_ADDR11_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR6_OFFSET (0x0104) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR6 VLC_TABLE_ADDR12 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR6_VLC_TABLE_ADDR12_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR6_VLC_TABLE_ADDR12_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR6_VLC_TABLE_ADDR12_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR6 VLC_TABLE_ADDR13 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR6_VLC_TABLE_ADDR13_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR6_VLC_TABLE_ADDR13_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR6_VLC_TABLE_ADDR13_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR7_OFFSET (0x0108) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR7 VLC_TABLE_ADDR14 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR7_VLC_TABLE_ADDR14_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR7_VLC_TABLE_ADDR14_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR7_VLC_TABLE_ADDR14_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR7 VLC_TABLE_ADDR15 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR7_VLC_TABLE_ADDR15_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR7_VLC_TABLE_ADDR15_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR7_VLC_TABLE_ADDR15_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR8_OFFSET (0x010C) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR8 VLC_TABLE_ADDR16 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR8_VLC_TABLE_ADDR16_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR8_VLC_TABLE_ADDR16_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR8_VLC_TABLE_ADDR16_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR8 VLC_TABLE_ADDR17 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR8_VLC_TABLE_ADDR17_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR8_VLC_TABLE_ADDR17_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR8_VLC_TABLE_ADDR17_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR9_OFFSET (0x0110) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR9 VLC_TABLE_ADDR18 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR9_VLC_TABLE_ADDR18_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR9_VLC_TABLE_ADDR18_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR9_VLC_TABLE_ADDR18_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR9 VLC_TABLE_ADDR19 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR9_VLC_TABLE_ADDR19_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR9_VLC_TABLE_ADDR19_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR9_VLC_TABLE_ADDR19_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR10_OFFSET (0x0114) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR10 VLC_TABLE_ADDR20 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR10_VLC_TABLE_ADDR20_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR10_VLC_TABLE_ADDR20_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR10_VLC_TABLE_ADDR20_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR10 VLC_TABLE_ADDR21 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR10_VLC_TABLE_ADDR21_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR10_VLC_TABLE_ADDR21_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR10_VLC_TABLE_ADDR21_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR11_OFFSET (0x0118) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR11 VLC_TABLE_ADDR22 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR11_VLC_TABLE_ADDR22_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR11_VLC_TABLE_ADDR22_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR11_VLC_TABLE_ADDR22_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR11 VLC_TABLE_ADDR23 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR11_VLC_TABLE_ADDR23_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR11_VLC_TABLE_ADDR23_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR11_VLC_TABLE_ADDR23_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR12_OFFSET (0x011C) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR12 VLC_TABLE_ADDR24 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR12_VLC_TABLE_ADDR24_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR12_VLC_TABLE_ADDR24_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR12_VLC_TABLE_ADDR24_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR12 VLC_TABLE_ADDR25 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR12_VLC_TABLE_ADDR25_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR12_VLC_TABLE_ADDR25_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR12_VLC_TABLE_ADDR25_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR13_OFFSET (0x0120) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR13 VLC_TABLE_ADDR26 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR13_VLC_TABLE_ADDR26_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR13_VLC_TABLE_ADDR26_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR13_VLC_TABLE_ADDR26_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR13 VLC_TABLE_ADDR27 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR13_VLC_TABLE_ADDR27_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR13_VLC_TABLE_ADDR27_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR13_VLC_TABLE_ADDR27_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR14_OFFSET (0x0124) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR14 VLC_TABLE_ADDR28 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR14_VLC_TABLE_ADDR28_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR14_VLC_TABLE_ADDR28_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR14_VLC_TABLE_ADDR28_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR14 VLC_TABLE_ADDR29 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR14_VLC_TABLE_ADDR29_MASK (0x003FF800) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR14_VLC_TABLE_ADDR29_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR14_VLC_TABLE_ADDR29_SHIFT (11) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR15_OFFSET (0x0128) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_ADDR15 VLC_TABLE_ADDR30 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR15_VLC_TABLE_ADDR30_MASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR15_VLC_TABLE_ADDR30_LSBMASK (0x000007FF) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_ADDR15_VLC_TABLE_ADDR30_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_OFFSET (0x012C) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH0 VLC_TABLE_INITIAL_WIDTH0 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH0_MASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH0_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH0_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH0 VLC_TABLE_INITIAL_WIDTH1 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH1_MASK (0x00000038) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH1_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH1_SHIFT (3) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH0 VLC_TABLE_INITIAL_WIDTH2 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH2_MASK (0x000001C0) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH2_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH2_SHIFT (6) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH0 VLC_TABLE_INITIAL_WIDTH3 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH3_MASK (0x00000E00) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH3_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH3_SHIFT (9) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH0 VLC_TABLE_INITIAL_WIDTH4 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH4_MASK (0x00007000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH4_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH4_SHIFT (12) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH0 VLC_TABLE_INITIAL_WIDTH5 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH5_MASK (0x00038000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH5_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH5_SHIFT (15) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH0 VLC_TABLE_INITIAL_WIDTH6 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH6_MASK (0x001C0000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH6_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH6_SHIFT (18) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH0 VLC_TABLE_INITIAL_WIDTH7 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH7_MASK (0x00E00000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH7_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH7_SHIFT (21) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH0 VLC_TABLE_INITIAL_WIDTH8 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH8_MASK (0x07000000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH8_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH8_SHIFT (24) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH0 VLC_TABLE_INITIAL_WIDTH9 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH9_MASK (0x38000000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH9_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH0_VLC_TABLE_INITIAL_WIDTH9_SHIFT (27) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_OFFSET (0x0130) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH1 VLC_TABLE_INITIAL_WIDTH10 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH10_MASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH10_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH10_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH1 VLC_TABLE_INITIAL_WIDTH11 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH11_MASK (0x00000038) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH11_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH11_SHIFT (3) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH1 VLC_TABLE_INITIAL_WIDTH12 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH12_MASK (0x000001C0) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH12_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH12_SHIFT (6) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH1 VLC_TABLE_INITIAL_WIDTH13 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH13_MASK (0x00000E00) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH13_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH13_SHIFT (9) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH1 VLC_TABLE_INITIAL_WIDTH14 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH14_MASK (0x00007000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH14_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH14_SHIFT (12) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH1 VLC_TABLE_INITIAL_WIDTH15 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH15_MASK (0x00038000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH15_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH15_SHIFT (15) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH1 VLC_TABLE_INITIAL_WIDTH16 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH16_MASK (0x001C0000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH16_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH16_SHIFT (18) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH1 VLC_TABLE_INITIAL_WIDTH17 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH17_MASK (0x00E00000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH17_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH17_SHIFT (21) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH1 VLC_TABLE_INITIAL_WIDTH18 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH18_MASK (0x07000000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH18_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH18_SHIFT (24) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH1 VLC_TABLE_INITIAL_WIDTH19 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH19_MASK (0x38000000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH19_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH1_VLC_TABLE_INITIAL_WIDTH19_SHIFT (27) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_OFFSET (0x0134) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH2 VLC_TABLE_INITIAL_WIDTH20 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH20_MASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH20_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH20_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH2 VLC_TABLE_INITIAL_WIDTH21 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH21_MASK (0x00000038) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH21_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH21_SHIFT (3) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH2 VLC_TABLE_INITIAL_WIDTH22 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH22_MASK (0x000001C0) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH22_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH22_SHIFT (6) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH2 VLC_TABLE_INITIAL_WIDTH23 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH23_MASK (0x00000E00) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH23_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH23_SHIFT (9) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH2 VLC_TABLE_INITIAL_WIDTH24 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH24_MASK (0x00007000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH24_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH24_SHIFT (12) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH2 VLC_TABLE_INITIAL_WIDTH25 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH25_MASK (0x00038000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH25_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH25_SHIFT (15) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH2 VLC_TABLE_INITIAL_WIDTH26 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH26_MASK (0x001C0000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH26_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH26_SHIFT (18) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH2 VLC_TABLE_INITIAL_WIDTH27 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH27_MASK (0x00E00000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH27_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH27_SHIFT (21) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH2 VLC_TABLE_INITIAL_WIDTH28 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH28_MASK (0x07000000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH28_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH28_SHIFT (24) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH2 VLC_TABLE_INITIAL_WIDTH29 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH29_MASK (0x38000000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH29_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH2_VLC_TABLE_INITIAL_WIDTH29_SHIFT (27) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH3_OFFSET (0x0138) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_WIDTH3 VLC_TABLE_INITIAL_WIDTH30 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH3_VLC_TABLE_INITIAL_WIDTH30_MASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH3_VLC_TABLE_INITIAL_WIDTH30_LSBMASK (0x00000007) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_WIDTH3_VLC_TABLE_INITIAL_WIDTH30_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_OFFSET (0x013C) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE0 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE0_MASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE0_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE0_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE1 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE1_MASK (0x0000000C) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE1_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE1_SHIFT (2) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE2 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE2_MASK (0x00000030) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE2_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE2_SHIFT (4) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE3 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE3_MASK (0x000000C0) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE3_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE3_SHIFT (6) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE4 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE4_MASK (0x00000300) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE4_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE4_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE5 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE5_MASK (0x00000C00) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE5_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE5_SHIFT (10) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE6 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE6_MASK (0x00003000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE6_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE6_SHIFT (12) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE7 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE7_MASK (0x0000C000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE7_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE7_SHIFT (14) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE8 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE8_MASK (0x00030000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE8_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE8_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE9 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE9_MASK (0x000C0000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE9_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE9_SHIFT (18) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE10 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE10_MASK (0x00300000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE10_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE10_SHIFT (20) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE11 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE11_MASK (0x00C00000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE11_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE11_SHIFT (22) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE12 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE12_MASK (0x03000000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE12_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE12_SHIFT (24) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE13 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE13_MASK (0x0C000000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE13_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE13_SHIFT (26) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE14 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE14_MASK (0x30000000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE14_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE14_SHIFT (28) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE0 VLC_TABLE_INITIAL_OPCODE15 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE15_MASK (0xC0000000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE15_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE0_VLC_TABLE_INITIAL_OPCODE15_SHIFT (30) |
| |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_OFFSET (0x0140) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE16 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE16_MASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE16_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE16_SHIFT (0) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE17 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE17_MASK (0x0000000C) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE17_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE17_SHIFT (2) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE18 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE18_MASK (0x00000030) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE18_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE18_SHIFT (4) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE19 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE19_MASK (0x000000C0) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE19_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE19_SHIFT (6) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE20 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE20_MASK (0x00000300) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE20_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE20_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE21 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE21_MASK (0x00000C00) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE21_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE21_SHIFT (10) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE22 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE22_MASK (0x00003000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE22_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE22_SHIFT (12) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE23 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE23_MASK (0x0000C000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE23_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE23_SHIFT (14) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE24 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE24_MASK (0x00030000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE24_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE24_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE25 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE25_MASK (0x000C0000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE25_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE25_SHIFT (18) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE26 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE26_MASK (0x00300000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE26_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE26_SHIFT (20) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE27 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE27_MASK (0x00C00000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE27_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE27_SHIFT (22) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE28 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE28_MASK (0x03000000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE28_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE28_SHIFT (24) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE29 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE29_MASK (0x0C000000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE29_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE29_SHIFT (26) |
| |
| // MSVDX_VEC CR_VEC_VLC_TABLE_INITIAL_OPCODE1 VLC_TABLE_INITIAL_OPCODE30 |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE30_MASK (0x30000000) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE30_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_VLC_TABLE_INITIAL_OPCODE1_VLC_TABLE_INITIAL_OPCODE30_SHIFT (28) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT0_OFFSET (0x0150) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT0 RENDEC_CONTEXT0_2 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT0_RENDEC_CONTEXT0_2_MASK (0x003F0000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT0_RENDEC_CONTEXT0_2_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT0_RENDEC_CONTEXT0_2_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT0 RENDEC_CONTEXT0_1 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT0_RENDEC_CONTEXT0_1_MASK (0x00003F00) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT0_RENDEC_CONTEXT0_1_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT0_RENDEC_CONTEXT0_1_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT0 RENDEC_CONTEXT0_0 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT0_RENDEC_CONTEXT0_0_MASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT0_RENDEC_CONTEXT0_0_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT0_RENDEC_CONTEXT0_0_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT1_OFFSET (0x0154) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT1 RENDEC_CONTEXT1_2 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT1_RENDEC_CONTEXT1_2_MASK (0x003F0000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT1_RENDEC_CONTEXT1_2_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT1_RENDEC_CONTEXT1_2_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT1 RENDEC_CONTEXT1_1 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT1_RENDEC_CONTEXT1_1_MASK (0x00003F00) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT1_RENDEC_CONTEXT1_1_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT1_RENDEC_CONTEXT1_1_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT1 RENDEC_CONTEXT1_0 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT1_RENDEC_CONTEXT1_0_MASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT1_RENDEC_CONTEXT1_0_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT1_RENDEC_CONTEXT1_0_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT2_OFFSET (0x0158) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT2 RENDEC_CONTEXT2_2 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT2_RENDEC_CONTEXT2_2_MASK (0x003F0000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT2_RENDEC_CONTEXT2_2_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT2_RENDEC_CONTEXT2_2_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT2 RENDEC_CONTEXT2_1 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT2_RENDEC_CONTEXT2_1_MASK (0x00003F00) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT2_RENDEC_CONTEXT2_1_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT2_RENDEC_CONTEXT2_1_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT2 RENDEC_CONTEXT2_0 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT2_RENDEC_CONTEXT2_0_MASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT2_RENDEC_CONTEXT2_0_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT2_RENDEC_CONTEXT2_0_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT3_OFFSET (0x015C) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT3 RENDEC_CONTEXT3_2 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT3_RENDEC_CONTEXT3_2_MASK (0x003F0000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT3_RENDEC_CONTEXT3_2_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT3_RENDEC_CONTEXT3_2_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT3 RENDEC_CONTEXT3_1 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT3_RENDEC_CONTEXT3_1_MASK (0x00003F00) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT3_RENDEC_CONTEXT3_1_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT3_RENDEC_CONTEXT3_1_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT3 RENDEC_CONTEXT3_0 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT3_RENDEC_CONTEXT3_0_MASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT3_RENDEC_CONTEXT3_0_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT3_RENDEC_CONTEXT3_0_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT4_OFFSET (0x0160) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT4 RENDEC_CONTEXT4_2 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT4_RENDEC_CONTEXT4_2_MASK (0x003F0000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT4_RENDEC_CONTEXT4_2_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT4_RENDEC_CONTEXT4_2_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT4 RENDEC_CONTEXT4_1 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT4_RENDEC_CONTEXT4_1_MASK (0x00003F00) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT4_RENDEC_CONTEXT4_1_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT4_RENDEC_CONTEXT4_1_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT4 RENDEC_CONTEXT4_0 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT4_RENDEC_CONTEXT4_0_MASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT4_RENDEC_CONTEXT4_0_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT4_RENDEC_CONTEXT4_0_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT5_OFFSET (0x0164) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT5 RENDEC_CONTEXT5_2 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT5_RENDEC_CONTEXT5_2_MASK (0x003F0000) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT5_RENDEC_CONTEXT5_2_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT5_RENDEC_CONTEXT5_2_SHIFT (16) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT5 RENDEC_CONTEXT5_1 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT5_RENDEC_CONTEXT5_1_MASK (0x00003F00) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT5_RENDEC_CONTEXT5_1_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT5_RENDEC_CONTEXT5_1_SHIFT (8) |
| |
| // MSVDX_VEC CR_VEC_RENDEC_CONTEXT5 RENDEC_CONTEXT5_0 |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT5_RENDEC_CONTEXT5_0_MASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT5_RENDEC_CONTEXT5_0_LSBMASK (0x0000003F) |
| #define MSVDX_VEC_CR_VEC_RENDEC_CONTEXT5_RENDEC_CONTEXT5_0_SHIFT (0) |
| |
| |
| // MSVDX_VEC CR_SR_BITS_CONSUMED SR_BITS_CONSUMED |
| #define MSVDX_VEC_CR_SR_BITS_CONSUMED_SR_BITS_CONSUMED_MASK (0x03FFFFFF) |
| #define MSVDX_VEC_CR_SR_BITS_CONSUMED_SR_BITS_CONSUMED_LSBMASK (0x03FFFFFF) |
| #define MSVDX_VEC_CR_SR_BITS_CONSUMED_SR_BITS_CONSUMED_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_BE_ENTDEC_SYNC_OFFSET (0x0180) |
| |
| // MSVDX_VEC CR_VEC_BE_ENTDEC_SYNC BE_ENTDEC_SYNC_FLAG |
| #define MSVDX_VEC_CR_VEC_BE_ENTDEC_SYNC_BE_ENTDEC_SYNC_FLAG_MASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_BE_ENTDEC_SYNC_BE_ENTDEC_SYNC_FLAG_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_BE_ENTDEC_SYNC_BE_ENTDEC_SYNC_FLAG_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_BE_ENTDEC_SYNC_OFFSET (0x0180) |
| |
| // MSVDX_VEC CR_VEC_BE_ENTDEC_SYNC BE_ENTDEC_SYNC_FLAG |
| #define MSVDX_VEC_CR_VEC_BE_ENTDEC_SYNC_BE_ENTDEC_SYNC_FLAG_MASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_BE_ENTDEC_SYNC_BE_ENTDEC_SYNC_FLAG_LSBMASK (0x00000001) |
| #define MSVDX_VEC_CR_VEC_BE_ENTDEC_SYNC_BE_ENTDEC_SYNC_FLAG_SHIFT (0) |
| |
| #define MSVDX_VEC_CR_VEC_BOOL_INIT_OFFSET (0x00A4) |
| |
| // MSVDX_VEC, CR_VEC_BOOL_INIT, BOOL_INIT_RANGE |
| #define MSVDX_VEC_CR_VEC_BOOL_INIT_BOOL_INIT_RANGE_MASK (0x0000FF00) |
| #define MSVDX_VEC_CR_VEC_BOOL_INIT_BOOL_INIT_RANGE_LSBMASK (0x000000FF) |
| #define MSVDX_VEC_CR_VEC_BOOL_INIT_BOOL_INIT_RANGE_SHIFT (8) |
| #define MSVDX_VEC_CR_VEC_BOOL_INIT_BOOL_INIT_RANGE_SIGNED_FIELD 0 |
| |
| // MSVDX_VEC, CR_VEC_BOOL_INIT, BOOL_INIT_VALUE |
| #define MSVDX_VEC_CR_VEC_BOOL_INIT_BOOL_INIT_VALUE_MASK (0x000000FF) |
| #define MSVDX_VEC_CR_VEC_BOOL_INIT_BOOL_INIT_VALUE_LSBMASK (0x000000FF) |
| #define MSVDX_VEC_CR_VEC_BOOL_INIT_BOOL_INIT_VALUE_SHIFT (0) |
| #define MSVDX_VEC_CR_VEC_BOOL_INIT_BOOL_INIT_VALUE_SIGNED_FIELD 0 |
| |
| #define MSVDX_VEC_CR_VEC_BOOL_CTRL_OFFSET (0x00A8) |
| |
| // MSVDX_VEC, CR_VEC_BOOL_CTRL, BOOL_MASTER_SELECT |
| #define MSVDX_VEC_CR_VEC_BOOL_CTRL_BOOL_MASTER_SELECT_MASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_BOOL_CTRL_BOOL_MASTER_SELECT_LSBMASK (0x00000003) |
| #define MSVDX_VEC_CR_VEC_BOOL_CTRL_BOOL_MASTER_SELECT_SHIFT (0) |
| #define MSVDX_VEC_CR_VEC_BOOL_CTRL_BOOL_MASTER_SELECT_SIGNED_FIELD 0 |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| |
| #endif /* __MSVDX_VEC_REG_IO2_H__ */ |
