| /* |
| * Copyright (c) 2011 Intel Corporation. All Rights Reserved. |
| * Copyright (c) Imagination Technologies Limited, UK |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation the rights to use, copy, modify, merge, publish, |
| * distribute, sub license, and/or sell copies of the Software, and to |
| * permit persons to whom the Software is furnished to do so, subject to |
| * the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial portions |
| * of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| #ifndef _REGCONV_H_topazhp_multicore_regs_h |
| #define _REGCONV_H_topazhp_multicore_regs_h |
| |
| #ifdef __cplusplus |
| #include "img_types.h" |
| #include "systemc_utils.h" |
| #endif |
| |
| |
| /* Register CR_MULTICORE_SRST */ |
| #define TOPAZHP_TOP_CR_MULTICORE_SRST 0x0000 |
| #define MASK_TOPAZHP_TOP_CR_IMG_TOPAZ_MTX_SOFT_RESET 0x00000001 |
| #define SHIFT_TOPAZHP_TOP_CR_IMG_TOPAZ_MTX_SOFT_RESET 0 |
| #define REGNUM_TOPAZHP_TOP_CR_IMG_TOPAZ_MTX_SOFT_RESET 0x0000 |
| #define SIGNED_TOPAZHP_TOP_CR_IMG_TOPAZ_MTX_SOFT_RESET 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_IMG_TOPAZ_IO_SOFT_RESET 0x00000002 |
| #define SHIFT_TOPAZHP_TOP_CR_IMG_TOPAZ_IO_SOFT_RESET 1 |
| #define REGNUM_TOPAZHP_TOP_CR_IMG_TOPAZ_IO_SOFT_RESET 0x0000 |
| #define SIGNED_TOPAZHP_TOP_CR_IMG_TOPAZ_IO_SOFT_RESET 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_IMG_TOPAZ_CORE_SOFT_RESET 0x00000004 |
| #define SHIFT_TOPAZHP_TOP_CR_IMG_TOPAZ_CORE_SOFT_RESET 2 |
| #define REGNUM_TOPAZHP_TOP_CR_IMG_TOPAZ_CORE_SOFT_RESET 0x0000 |
| #define SIGNED_TOPAZHP_TOP_CR_IMG_TOPAZ_CORE_SOFT_RESET 0 |
| |
| /* Register CR_MULTICORE_INT_STAT */ |
| #define TOPAZHP_TOP_CR_MULTICORE_INT_STAT 0x0004 |
| #define MASK_TOPAZHP_TOP_CR_INT_STAT_DMAC 0x00000001 |
| #define SHIFT_TOPAZHP_TOP_CR_INT_STAT_DMAC 0 |
| #define REGNUM_TOPAZHP_TOP_CR_INT_STAT_DMAC 0x0004 |
| #define SIGNED_TOPAZHP_TOP_CR_INT_STAT_DMAC 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_INT_STAT_MTX 0x00000002 |
| #define SHIFT_TOPAZHP_TOP_CR_INT_STAT_MTX 1 |
| #define REGNUM_TOPAZHP_TOP_CR_INT_STAT_MTX 0x0004 |
| #define SIGNED_TOPAZHP_TOP_CR_INT_STAT_MTX 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_INT_STAT_MTX_HALT 0x00000004 |
| #define SHIFT_TOPAZHP_TOP_CR_INT_STAT_MTX_HALT 2 |
| #define REGNUM_TOPAZHP_TOP_CR_INT_STAT_MTX_HALT 0x0004 |
| #define SIGNED_TOPAZHP_TOP_CR_INT_STAT_MTX_HALT 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_INT_STAT_MMU_FAULT 0x00000008 |
| #define SHIFT_TOPAZHP_TOP_CR_INT_STAT_MMU_FAULT 3 |
| #define REGNUM_TOPAZHP_TOP_CR_INT_STAT_MMU_FAULT 0x0004 |
| #define SIGNED_TOPAZHP_TOP_CR_INT_STAT_MMU_FAULT 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_INT_STAT_MTX_CORES 0x0000FF00 |
| #define SHIFT_TOPAZHP_TOP_CR_INT_STAT_MTX_CORES 8 |
| #define REGNUM_TOPAZHP_TOP_CR_INT_STAT_MTX_CORES 0x0004 |
| #define SIGNED_TOPAZHP_TOP_CR_INT_STAT_MTX_CORES 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_INT_STAT_HOST_CORES 0x00FF0000 |
| #define SHIFT_TOPAZHP_TOP_CR_INT_STAT_HOST_CORES 16 |
| #define REGNUM_TOPAZHP_TOP_CR_INT_STAT_HOST_CORES 0x0004 |
| #define SIGNED_TOPAZHP_TOP_CR_INT_STAT_HOST_CORES 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MAS_MTX_INTS 0x40000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MAS_MTX_INTS 30 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MAS_MTX_INTS 0x0004 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MAS_MTX_INTS 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MAS_HOST_INTS 0x80000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MAS_HOST_INTS 31 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MAS_HOST_INTS 0x0004 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MAS_HOST_INTS 0 |
| |
| /* Register CR_MULTICORE_MTX_INT_ENAB */ |
| #define TOPAZHP_TOP_CR_MULTICORE_MTX_INT_ENAB 0x0008 |
| #define MASK_TOPAZHP_TOP_CR_MTX_INTEN_DMAC 0x00000001 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_INTEN_DMAC 0 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_INTEN_DMAC 0x0008 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_INTEN_DMAC 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_INTEN_MTX 0x00000002 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_INTEN_MTX 1 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_INTEN_MTX 0x0008 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_INTEN_MTX 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_INTEN_MTX_HALT 0x00000004 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_INTEN_MTX_HALT 2 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_INTEN_MTX_HALT 0x0008 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_INTEN_MTX_HALT 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_INTEN_MMU_FAULT 0x00000008 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_INTEN_MMU_FAULT 3 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_INTEN_MMU_FAULT 0x0008 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_INTEN_MMU_FAULT 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_INTEN_MTX_CORES 0x0000FF00 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_INTEN_MTX_CORES 8 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_INTEN_MTX_CORES 0x0008 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_INTEN_MTX_CORES 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_INTEN_HOST_CORES 0x00FF0000 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_INTEN_HOST_CORES 16 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_INTEN_HOST_CORES 0x0008 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_INTEN_HOST_CORES 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_TOPAZHP_MAS_INTEN 0x40000000 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_TOPAZHP_MAS_INTEN 30 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_TOPAZHP_MAS_INTEN 0x0008 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_TOPAZHP_MAS_INTEN 0 |
| |
| /* Register CR_MULTICORE_HOST_INT_ENAB */ |
| #define TOPAZHP_TOP_CR_MULTICORE_HOST_INT_ENAB 0x000C |
| #define MASK_TOPAZHP_TOP_CR_HOST_INTEN_DMAC 0x00000001 |
| #define SHIFT_TOPAZHP_TOP_CR_HOST_INTEN_DMAC 0 |
| #define REGNUM_TOPAZHP_TOP_CR_HOST_INTEN_DMAC 0x000C |
| #define SIGNED_TOPAZHP_TOP_CR_HOST_INTEN_DMAC 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_HOST_INTEN_MTX 0x00000002 |
| #define SHIFT_TOPAZHP_TOP_CR_HOST_INTEN_MTX 1 |
| #define REGNUM_TOPAZHP_TOP_CR_HOST_INTEN_MTX 0x000C |
| #define SIGNED_TOPAZHP_TOP_CR_HOST_INTEN_MTX 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_HOST_INTEN_MTX_HALT 0x00000004 |
| #define SHIFT_TOPAZHP_TOP_CR_HOST_INTEN_MTX_HALT 2 |
| #define REGNUM_TOPAZHP_TOP_CR_HOST_INTEN_MTX_HALT 0x000C |
| #define SIGNED_TOPAZHP_TOP_CR_HOST_INTEN_MTX_HALT 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_HOST_INTEN_MMU_FAULT 0x00000008 |
| #define SHIFT_TOPAZHP_TOP_CR_HOST_INTEN_MMU_FAULT 3 |
| #define REGNUM_TOPAZHP_TOP_CR_HOST_INTEN_MMU_FAULT 0x000C |
| #define SIGNED_TOPAZHP_TOP_CR_HOST_INTEN_MMU_FAULT 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_HOST_INTEN_MTX_CORES 0x0000FF00 |
| #define SHIFT_TOPAZHP_TOP_CR_HOST_INTEN_MTX_CORES 8 |
| #define REGNUM_TOPAZHP_TOP_CR_HOST_INTEN_MTX_CORES 0x000C |
| #define SIGNED_TOPAZHP_TOP_CR_HOST_INTEN_MTX_CORES 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_HOST_INTEN_HOST_CORES 0x00FF0000 |
| #define SHIFT_TOPAZHP_TOP_CR_HOST_INTEN_HOST_CORES 16 |
| #define REGNUM_TOPAZHP_TOP_CR_HOST_INTEN_HOST_CORES 0x000C |
| #define SIGNED_TOPAZHP_TOP_CR_HOST_INTEN_HOST_CORES 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_HOST_TOPAZHP_MAS_INTEN 0x80000000 |
| #define SHIFT_TOPAZHP_TOP_CR_HOST_TOPAZHP_MAS_INTEN 31 |
| #define REGNUM_TOPAZHP_TOP_CR_HOST_TOPAZHP_MAS_INTEN 0x000C |
| #define SIGNED_TOPAZHP_TOP_CR_HOST_TOPAZHP_MAS_INTEN 0 |
| |
| /* Register CR_MULTICORE_INT_CLEAR */ |
| #define TOPAZHP_TOP_CR_MULTICORE_INT_CLEAR 0x0010 |
| #define MASK_TOPAZHP_TOP_CR_INTCLR_DMAC 0x00000001 |
| #define SHIFT_TOPAZHP_TOP_CR_INTCLR_DMAC 0 |
| #define REGNUM_TOPAZHP_TOP_CR_INTCLR_DMAC 0x0010 |
| #define SIGNED_TOPAZHP_TOP_CR_INTCLR_DMAC 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_INTCLR_MTX 0x00000002 |
| #define SHIFT_TOPAZHP_TOP_CR_INTCLR_MTX 1 |
| #define REGNUM_TOPAZHP_TOP_CR_INTCLR_MTX 0x0010 |
| #define SIGNED_TOPAZHP_TOP_CR_INTCLR_MTX 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_INTCLR_MTX_HALT 0x00000004 |
| #define SHIFT_TOPAZHP_TOP_CR_INTCLR_MTX_HALT 2 |
| #define REGNUM_TOPAZHP_TOP_CR_INTCLR_MTX_HALT 0x0010 |
| #define SIGNED_TOPAZHP_TOP_CR_INTCLR_MTX_HALT 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_INTCLR_MMU_FAULT 0x00000008 |
| #define SHIFT_TOPAZHP_TOP_CR_INTCLR_MMU_FAULT 3 |
| #define REGNUM_TOPAZHP_TOP_CR_INTCLR_MMU_FAULT 0x0010 |
| #define SIGNED_TOPAZHP_TOP_CR_INTCLR_MMU_FAULT 0 |
| |
| /* Register CR_MULTICORE_MAN_CLK_GATE */ |
| #define TOPAZHP_TOP_CR_MULTICORE_MAN_CLK_GATE 0x0014 |
| #define MASK_TOPAZHP_TOP_CR_TOPAZ_MTX_MAN_CLK_GATE 0x00000002 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZ_MTX_MAN_CLK_GATE 1 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZ_MTX_MAN_CLK_GATE 0x0014 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZ_MTX_MAN_CLK_GATE 0 |
| |
| /* Register CR_TOPAZ_MTX_C_RATIO */ |
| #define TOPAZHP_TOP_CR_TOPAZ_MTX_C_RATIO 0x0018 |
| #define MASK_TOPAZHP_TOP_CR_MTX_C_RATIO 0x00000003 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_C_RATIO 0 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_C_RATIO 0x0018 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_C_RATIO 0 |
| |
| /* Register CR_MMU_STATUS */ |
| #define TOPAZHP_TOP_CR_MMU_STATUS 0x001C |
| #define MASK_TOPAZHP_TOP_CR_MMU_PF_N_RW 0x00000001 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_PF_N_RW 0 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_PF_N_RW 0x001C |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_PF_N_RW 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MMU_FAULT_ADDR 0xFFFFF000 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_FAULT_ADDR 12 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_FAULT_ADDR 0x001C |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_FAULT_ADDR 0 |
| |
| /* Register CR_MMU_MEM_REQ */ |
| #define TOPAZHP_TOP_CR_MMU_MEM_REQ 0x0020 |
| #define MASK_TOPAZHP_TOP_CR_MEM_REQ_STAT_READS 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_MEM_REQ_STAT_READS 0 |
| #define REGNUM_TOPAZHP_TOP_CR_MEM_REQ_STAT_READS 0x0020 |
| #define SIGNED_TOPAZHP_TOP_CR_MEM_REQ_STAT_READS 0 |
| |
| /* Register CR_MMU_CONTROL0 */ |
| #define TOPAZHP_TOP_CR_MMU_CONTROL0 0x0024 |
| #define MASK_TOPAZHP_TOP_CR_MMU_NOREORDER 0x00000001 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_NOREORDER 0 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_NOREORDER 0x0024 |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_NOREORDER 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MMU_PAUSE 0x00000002 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_PAUSE 1 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_PAUSE 0x0024 |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_PAUSE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MMU_FLUSH 0x00000004 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_FLUSH 2 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_FLUSH 0x0024 |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_FLUSH 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MMU_INVALDC 0x00000008 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_INVALDC 3 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_INVALDC 0x0024 |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_INVALDC 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_FLOWRATE_TOPAZ 0x00000700 |
| #define SHIFT_TOPAZHP_TOP_CR_FLOWRATE_TOPAZ 8 |
| #define REGNUM_TOPAZHP_TOP_CR_FLOWRATE_TOPAZ 0x0024 |
| #define SIGNED_TOPAZHP_TOP_CR_FLOWRATE_TOPAZ 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MMU_BYPASS_TOPAZ 0x00010000 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_BYPASS_TOPAZ 16 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_BYPASS_TOPAZ 0x0024 |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_BYPASS_TOPAZ 0 |
| |
| /* Register CR_MMU_CONTROL1 */ |
| #define TOPAZHP_TOP_CR_MMU_CONTROL1 0x0028 |
| #define MASK_TOPAZHP_TOP_CR_MMU_TTE_THRESHOLD 0x00000FFF |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_TTE_THRESHOLD 0 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_TTE_THRESHOLD 0x0028 |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_TTE_THRESHOLD 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MMU_ADT_TTE 0x000FF000 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_ADT_TTE 12 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_ADT_TTE 0x0028 |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_ADT_TTE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MMU_BEST_COUNT 0x0FF00000 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_BEST_COUNT 20 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_BEST_COUNT 0x0028 |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_BEST_COUNT 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MMU_PAGE_SIZE 0xF0000000 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_PAGE_SIZE 28 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_PAGE_SIZE 0x0028 |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_PAGE_SIZE 0 |
| |
| /* Register CR_MMU_CONTROL2 */ |
| #define TOPAZHP_TOP_CR_MMU_CONTROL2 0x002C |
| #define MASK_TOPAZHP_TOP_CR_MMU_ENABLE_36BIT_ADDRESSING 0x00000001 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_ENABLE_36BIT_ADDRESSING 0 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_ENABLE_36BIT_ADDRESSING 0x002C |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_ENABLE_36BIT_ADDRESSING 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MMU_TILING_SCHEME 0x00000008 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_TILING_SCHEME 3 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_TILING_SCHEME 0x002C |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_TILING_SCHEME 0 |
| |
| /* Register CR_MMU_DIR_LIST_BASE_0 */ |
| #define TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_0 0x0030 |
| #define MASK_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR_00 0xFFFFFFF0 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR_00 4 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR_00 0x0030 |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR_00 0 |
| |
| /* Register CR_MMU_TILE_0 */ |
| #define TOPAZHP_TOP_CR_MMU_TILE_0 0x0038 |
| #define MASK_TOPAZHP_TOP_CR_TILE_MIN_ADDR_00 0x00000FFF |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_MIN_ADDR_00 0 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_MIN_ADDR_00 0x0038 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_MIN_ADDR_00 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TILE_MAX_ADDR_00 0x00FFF000 |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_MAX_ADDR_00 12 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_MAX_ADDR_00 0x0038 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_MAX_ADDR_00 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TILE_STRIDE_00 0x07000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_STRIDE_00 24 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_STRIDE_00 0x0038 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_STRIDE_00 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TILE_ENABLE_00 0x10000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_ENABLE_00 28 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_ENABLE_00 0x0038 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_ENABLE_00 0 |
| |
| /* Register CR_MMU_TILE_1 */ |
| #define TOPAZHP_TOP_CR_MMU_TILE_1 0x003C |
| #define MASK_TOPAZHP_TOP_CR_TILE_MIN_ADDR_01 0x00000FFF |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_MIN_ADDR_01 0 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_MIN_ADDR_01 0x003C |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_MIN_ADDR_01 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TILE_MAX_ADDR_01 0x00FFF000 |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_MAX_ADDR_01 12 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_MAX_ADDR_01 0x003C |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_MAX_ADDR_01 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TILE_STRIDE_01 0x07000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_STRIDE_01 24 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_STRIDE_01 0x003C |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_STRIDE_01 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TILE_ENABLE_01 0x10000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_ENABLE_01 28 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_ENABLE_01 0x003C |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_ENABLE_01 0 |
| |
| /* Register CR_MTX_DEBUG_MSTR */ |
| #define TOPAZHP_TOP_CR_MTX_DEBUG_MSTR 0x0044 |
| #define MASK_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_IN 0x00000003 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_IN 0 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_IN 0x0044 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_IN 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_MSTR_DBG_IS_SLAVE 0x00000004 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_MSTR_DBG_IS_SLAVE 2 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_MSTR_DBG_IS_SLAVE 0x0044 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_MSTR_DBG_IS_SLAVE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_OUT 0x00000018 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_OUT 3 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_OUT 0x0044 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_OUT 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANKS 0x00000F00 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANKS 8 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANKS 0x0044 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANKS 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANK_SIZE 0x000F0000 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANK_SIZE 16 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANK_SIZE 0x0044 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANK_SIZE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_MSTR_LAST_RAM_BANK_SIZE 0x0F000000 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_MSTR_LAST_RAM_BANK_SIZE 24 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_MSTR_LAST_RAM_BANK_SIZE 0x0044 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_MSTR_LAST_RAM_BANK_SIZE 0 |
| |
| /* Register CR_MTX_DEBUG_SLV */ |
| #define TOPAZHP_TOP_CR_MTX_DEBUG_SLV 0x0048 |
| #define MASK_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_IN 0x00000003 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_IN 0 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_IN 0x0048 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_IN 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_SLV_DBG_IS_SLAVE 0x00000004 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_SLV_DBG_IS_SLAVE 2 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_SLV_DBG_IS_SLAVE 0x0048 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_SLV_DBG_IS_SLAVE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_OUT 0x00000018 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_OUT 3 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_OUT 0x0048 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_OUT 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANKS 0x00000F00 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANKS 8 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANKS 0x0048 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANKS 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANK_SIZE 0x000F0000 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANK_SIZE 16 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANK_SIZE 0x0048 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANK_SIZE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_MTX_SLV_LAST_RAM_BANK_SIZE 0x0F000000 |
| #define SHIFT_TOPAZHP_TOP_CR_MTX_SLV_LAST_RAM_BANK_SIZE 24 |
| #define REGNUM_TOPAZHP_TOP_CR_MTX_SLV_LAST_RAM_BANK_SIZE 0x0048 |
| #define SIGNED_TOPAZHP_TOP_CR_MTX_SLV_LAST_RAM_BANK_SIZE 0 |
| |
| /* Register CR_MULTICORE_CORE_SEL_0 */ |
| #define TOPAZHP_TOP_CR_MULTICORE_CORE_SEL_0 0x0050 |
| #define MASK_TOPAZHP_TOP_CR_DMAC_MTX_SELECT 0x00000007 |
| #define SHIFT_TOPAZHP_TOP_CR_DMAC_MTX_SELECT 0 |
| #define REGNUM_TOPAZHP_TOP_CR_DMAC_MTX_SELECT 0x0050 |
| #define SIGNED_TOPAZHP_TOP_CR_DMAC_MTX_SELECT 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_WRITES_MTX_ALL 0x40000000 |
| #define SHIFT_TOPAZHP_TOP_CR_WRITES_MTX_ALL 30 |
| #define REGNUM_TOPAZHP_TOP_CR_WRITES_MTX_ALL 0x0050 |
| #define SIGNED_TOPAZHP_TOP_CR_WRITES_MTX_ALL 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_WRITES_CORE_ALL 0x80000000 |
| #define SHIFT_TOPAZHP_TOP_CR_WRITES_CORE_ALL 31 |
| #define REGNUM_TOPAZHP_TOP_CR_WRITES_CORE_ALL 0x0050 |
| #define SIGNED_TOPAZHP_TOP_CR_WRITES_CORE_ALL 0 |
| |
| /* Register CR_MULTICORE_CORE_SEL_1 */ |
| #define TOPAZHP_TOP_CR_MULTICORE_CORE_SEL_1 0x0054 |
| #define MASK_TOPAZHP_TOP_CR_RTM_PORT_CORE_SELECT 0x0000001F |
| #define SHIFT_TOPAZHP_TOP_CR_RTM_PORT_CORE_SELECT 0 |
| #define REGNUM_TOPAZHP_TOP_CR_RTM_PORT_CORE_SELECT 0x0054 |
| #define SIGNED_TOPAZHP_TOP_CR_RTM_PORT_CORE_SELECT 0 |
| |
| /* Register CR_MULTICORE_HW_CFG */ |
| #define TOPAZHP_TOP_CR_MULTICORE_HW_CFG 0x0058 |
| #define MASK_TOPAZHP_TOP_CR_NUM_CORES_SUPPORTED 0x0000001F |
| #define SHIFT_TOPAZHP_TOP_CR_NUM_CORES_SUPPORTED 0 |
| #define REGNUM_TOPAZHP_TOP_CR_NUM_CORES_SUPPORTED 0x0058 |
| #define SIGNED_TOPAZHP_TOP_CR_NUM_CORES_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_NUM_MTX_SUPPORTED 0x00000700 |
| #define SHIFT_TOPAZHP_TOP_CR_NUM_MTX_SUPPORTED 8 |
| #define REGNUM_TOPAZHP_TOP_CR_NUM_MTX_SUPPORTED 0x0058 |
| #define SIGNED_TOPAZHP_TOP_CR_NUM_MTX_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_NUM_CORES_PER_MTX 0x00070000 |
| #define SHIFT_TOPAZHP_TOP_CR_NUM_CORES_PER_MTX 16 |
| #define REGNUM_TOPAZHP_TOP_CR_NUM_CORES_PER_MTX 0x0058 |
| #define SIGNED_TOPAZHP_TOP_CR_NUM_CORES_PER_MTX 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_EXTENDED_ADDR_RANGE 0x0F000000 |
| #define SHIFT_TOPAZHP_TOP_CR_EXTENDED_ADDR_RANGE 24 |
| #define REGNUM_TOPAZHP_TOP_CR_EXTENDED_ADDR_RANGE 0x0058 |
| #define SIGNED_TOPAZHP_TOP_CR_EXTENDED_ADDR_RANGE 0 |
| |
| /* Register CR_MULTICORE_CMD_FIFO_WRITE */ |
| #define TOPAZHP_TOP_CR_MULTICORE_CMD_FIFO_WRITE 0x0060 |
| #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_WDATA 0xFFFFFFFF |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_WDATA 0 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_WDATA 0x0060 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_WDATA 0 |
| |
| /* Register CR_MULTICORE_CMD_FIFO_WRITE_SPACE */ |
| #define TOPAZHP_TOP_CR_MULTICORE_CMD_FIFO_WRITE_SPACE 0x0064 |
| #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_SPACE 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_SPACE 0 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_SPACE 0x0064 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_SPACE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_FULL 0x00000100 |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_FULL 8 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_FULL 0x0064 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_FULL 0 |
| |
| /* Register CR_TOPAZ_CMD_FIFO_READ */ |
| #define TOPAZHP_TOP_CR_TOPAZ_CMD_FIFO_READ 0x0070 |
| #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_RDATA 0xFFFFFFFF |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_RDATA 0 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_RDATA 0x0070 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_RDATA 0 |
| |
| /* Register CR_TOPAZ_CMD_FIFO_READ_AVAILABLE */ |
| #define TOPAZHP_TOP_CR_TOPAZ_CMD_FIFO_READ_AVAILABLE 0x0074 |
| #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_QUANTITY 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_QUANTITY 0 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_QUANTITY 0x0074 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_QUANTITY 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_NOTEMPTY 0x00000100 |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_NOTEMPTY 8 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_NOTEMPTY 0x0074 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_NOTEMPTY 0 |
| |
| /* Register CR_TOPAZ_CMD_FIFO_FLUSH */ |
| #define TOPAZHP_TOP_CR_TOPAZ_CMD_FIFO_FLUSH 0x0078 |
| #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_FLUSH 0x00000001 |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_FLUSH 0 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_FLUSH 0x0078 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_FLUSH 0 |
| |
| /* Register CR_MMU_TILE_EXT_0 */ |
| #define TOPAZHP_TOP_CR_MMU_TILE_EXT_0 0x0080 |
| #define MASK_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_00 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_00 0 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_00 0x0080 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_00 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_00 0x0000FF00 |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_00 8 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_00 0x0080 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_00 0 |
| |
| /* Register CR_MMU_TILE_EXT_1 */ |
| #define TOPAZHP_TOP_CR_MMU_TILE_EXT_1 0x0084 |
| #define MASK_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_01 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_01 0 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_01 0x0084 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_01 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_01 0x0000FF00 |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_01 8 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_01 0x0084 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_01 0 |
| |
| /* Register CR_TOPAZHP_CMD_PRIORITY_ENABLE */ |
| #define TOPAZHP_TOP_CR_TOPAZHP_CMD_PRIORITY_ENABLE 0x0090 |
| #define MASK_TOPAZHP_TOP_CR_CMD_PRI_BIF 0x00000001 |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_BIF 0 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_BIF 0x0090 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_BIF 0 |
| #define TOPAZHP_TOP_CR_CMD_PRI_BIF_PRI_ENABLE 0x00000001 /* Enable setting of mem_cmd_priority for BIF memory transactions */ |
| #define TOPAZHP_TOP_CR_CMD_PRI_BIF_PRI_DISABLE 0x00000000 /* Disable setting of mem_cmd_priority for BIF memory transactions */ |
| |
| #define MASK_TOPAZHP_TOP_CR_CMD_PRI_LRITC0 0x00000002 |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_LRITC0 1 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_LRITC0 0x0090 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_LRITC0 0 |
| #define TOPAZHP_TOP_CR_CMD_PRI_LRITC0_PRI_ENABLE 0x00000001 /* Enable setting of mem_cmd_priority for LRITC0 memory transactions */ |
| #define TOPAZHP_TOP_CR_CMD_PRI_LRITC0_PRI_DISABLE 0x00000000 /* Disable setting of mem_cmd_priority for LRITC0 memory transactions |
| */ |
| |
| #define MASK_TOPAZHP_TOP_CR_CMD_PRI_SEQ0_VLC0_DMAC 0x00000004 |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_SEQ0_VLC0_DMAC 2 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_SEQ0_VLC0_DMAC 0x0090 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_SEQ0_VLC0_DMAC 0 |
| #define TOPAZHP_TOP_CR_CMD_PRI_SEQ0_VLC0_DMAC_PRI_ENABLE 0x00000001 /* Enable setting of mem_cmd_priority for SEQ0 / VLC0 / DMAC memory |
| transactions */ |
| #define TOPAZHP_TOP_CR_CMD_PRI_SEQ0_VLC0_DMAC_PRI_DISABLE 0x00000000 /* Disable setting of mem_cmd_priority for SEQ0 / VLC0 / DMAC |
| memory transactions */ |
| |
| #define MASK_TOPAZHP_TOP_CR_CMD_PRI_LRITC1 0x00000008 |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_LRITC1 3 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_LRITC1 0x0090 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_LRITC1 0 |
| #define TOPAZHP_TOP_CR_CMD_PRI_LRITC1_PRI_ENABLE 0x00000001 /* Enable setting of mem_cmd_priority for LRITC1 memory transactions */ |
| #define TOPAZHP_TOP_CR_CMD_PRI_LRITC1_PRI_DISABLE 0x00000000 /* Disable setting of mem_cmd_priority for LRITC1 memory transactions |
| */ |
| |
| #define MASK_TOPAZHP_TOP_CR_CMD_PRI_SEQ1_VLC1 0x00000010 |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_SEQ1_VLC1 4 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_SEQ1_VLC1 0x0090 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_SEQ1_VLC1 0 |
| #define TOPAZHP_TOP_CR_CMD_PRI_SEQ1_VLC1_PRI_ENABLE 0x00000001 /* Enable setting of mem_cmd_priority for SEQ1 / VLC1 memory transactions |
| */ |
| #define TOPAZHP_TOP_CR_CMD_PRI_SEQ1_VLC1_PRI_DISABLE 0x00000000 /* Disable setting of mem_cmd_priority for SEQ1 / VLC1 memory transactions |
| */ |
| |
| #define MASK_TOPAZHP_TOP_CR_CMD_PRI_LRITC2 0x00000020 |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_LRITC2 5 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_LRITC2 0x0090 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_LRITC2 0 |
| #define TOPAZHP_TOP_CR_CMD_PRI_LRITC2_PRI_ENABLE 0x00000001 /* Enable setting of mem_cmd_priority for LRITC2 memory transactions */ |
| #define TOPAZHP_TOP_CR_CMD_PRI_LRITC2_PRI_DISABLE 0x00000000 /* Disable setting of mem_cmd_priority for LRITC2 memory transactions |
| */ |
| |
| #define MASK_TOPAZHP_TOP_CR_CMD_PRI_SEQ2_VLC2 0x00000040 |
| #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_SEQ2_VLC2 6 |
| #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_SEQ2_VLC2 0x0090 |
| #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_SEQ2_VLC2 0 |
| #define TOPAZHP_TOP_CR_CMD_PRI_SEQ2_VLC2_PRI_ENABLE 0x00000001 /* Enable setting of mem_cmd_priority for SEQ2 / VLC2 memory transactions |
| */ |
| #define TOPAZHP_TOP_CR_CMD_PRI_SEQ2_VLC2_PRI_DISABLE 0x00000000 /* Disable setting of mem_cmd_priority for SEQ2 / VLC2 memory transactions |
| */ |
| |
| /* Register CR_TOPAZHP_LIMITED_THROUGHPUT */ |
| #define TOPAZHP_TOP_CR_TOPAZHP_LIMITED_THROUGHPUT 0x0094 |
| #define MASK_TOPAZHP_TOP_CR_LIMITED_WORDS 0x000003FF |
| #define SHIFT_TOPAZHP_TOP_CR_LIMITED_WORDS 0 |
| #define REGNUM_TOPAZHP_TOP_CR_LIMITED_WORDS 0x0094 |
| #define SIGNED_TOPAZHP_TOP_CR_LIMITED_WORDS 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_REQUEST_GAP 0x0FFF0000 |
| #define SHIFT_TOPAZHP_TOP_CR_REQUEST_GAP 16 |
| #define REGNUM_TOPAZHP_TOP_CR_REQUEST_GAP 0x0094 |
| #define SIGNED_TOPAZHP_TOP_CR_REQUEST_GAP 0 |
| |
| /* Register CR_FIRMWARE_REG_1 */ |
| #define TOPAZHP_TOP_CR_FIRMWARE_REG_1 0x0100 |
| #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_1 0xFFFFFFFF |
| #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_1 0 |
| #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_1 0x0100 |
| #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_1 0 |
| |
| /* Register CR_FIRMWARE_REG_2 */ |
| #define TOPAZHP_TOP_CR_FIRMWARE_REG_2 0x0104 |
| #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_2 0xFFFFFFFF |
| #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_2 0 |
| #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_2 0x0104 |
| #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_2 0 |
| |
| /* Register CR_FIRMWARE_REG_3 */ |
| #define TOPAZHP_TOP_CR_FIRMWARE_REG_3 0x0108 |
| #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_3 0xFFFFFFFF |
| #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_3 0 |
| #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_3 0x0108 |
| #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_3 0 |
| |
| /* Register CR_CYCLE_COUNTER */ |
| #define TOPAZHP_TOP_CR_CYCLE_COUNTER 0x0110 |
| #define MASK_TOPAZHP_TOP_CR_CYCLE_COUNTER 0xFFFFFFFF |
| #define SHIFT_TOPAZHP_TOP_CR_CYCLE_COUNTER 0 |
| #define REGNUM_TOPAZHP_TOP_CR_CYCLE_COUNTER 0x0110 |
| #define SIGNED_TOPAZHP_TOP_CR_CYCLE_COUNTER 0 |
| |
| /* Register CR_CYCLE_COUNTER_CTRL */ |
| #define TOPAZHP_TOP_CR_CYCLE_COUNTER_CTRL 0x0114 |
| #define MASK_TOPAZHP_TOP_CR_CYCLE_COUNTER_ENABLE 0x00000001 |
| #define SHIFT_TOPAZHP_TOP_CR_CYCLE_COUNTER_ENABLE 0 |
| #define REGNUM_TOPAZHP_TOP_CR_CYCLE_COUNTER_ENABLE 0x0114 |
| #define SIGNED_TOPAZHP_TOP_CR_CYCLE_COUNTER_ENABLE 0 |
| |
| /* Register CR_MULTICORE_IDLE_PWR_MAN */ |
| #define TOPAZHP_TOP_CR_MULTICORE_IDLE_PWR_MAN 0x0118 |
| #define MASK_TOPAZHP_TOP_CR_TOPAZ_IDLE_DISABLE 0x00000001 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZ_IDLE_DISABLE 0 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZ_IDLE_DISABLE 0x0118 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZ_IDLE_DISABLE 0 |
| |
| /* Register CR_DIRECT_BIAS_TABLE */ |
| #define TOPAZHP_TOP_CR_DIRECT_BIAS_TABLE 0x0124 |
| #define MASK_TOPAZHP_TOP_CR_DIRECT_BIAS_TABLE 0x00007FFF |
| #define SHIFT_TOPAZHP_TOP_CR_DIRECT_BIAS_TABLE 0 |
| #define REGNUM_TOPAZHP_TOP_CR_DIRECT_BIAS_TABLE 0x0124 |
| #define SIGNED_TOPAZHP_TOP_CR_DIRECT_BIAS_TABLE 0 |
| |
| /* Register CR_INTRA_BIAS_TABLE */ |
| #define TOPAZHP_TOP_CR_INTRA_BIAS_TABLE 0x0128 |
| #define MASK_TOPAZHP_TOP_CR_INTRA8_BIAS_TABLE 0xFFFF0000 |
| #define SHIFT_TOPAZHP_TOP_CR_INTRA8_BIAS_TABLE 16 |
| #define REGNUM_TOPAZHP_TOP_CR_INTRA8_BIAS_TABLE 0x0128 |
| #define SIGNED_TOPAZHP_TOP_CR_INTRA8_BIAS_TABLE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_INTRA16_BIAS_TABLE 0x0000FFFF |
| #define SHIFT_TOPAZHP_TOP_CR_INTRA16_BIAS_TABLE 0 |
| #define REGNUM_TOPAZHP_TOP_CR_INTRA16_BIAS_TABLE 0x0128 |
| #define SIGNED_TOPAZHP_TOP_CR_INTRA16_BIAS_TABLE 0 |
| |
| /* Register CR_INTER_BIAS_TABLE */ |
| #define TOPAZHP_TOP_CR_INTER_BIAS_TABLE 0x012C |
| #define MASK_TOPAZHP_TOP_CR_INTER_BIAS_TABLE 0x0000FFFF |
| #define SHIFT_TOPAZHP_TOP_CR_INTER_BIAS_TABLE 0 |
| #define REGNUM_TOPAZHP_TOP_CR_INTER_BIAS_TABLE 0x012C |
| #define SIGNED_TOPAZHP_TOP_CR_INTER_BIAS_TABLE 0 |
| |
| /* Register CR_INTRA_SCALE_TABLE */ |
| #define TOPAZHP_TOP_CR_INTRA_SCALE_TABLE 0x0130 |
| #define MASK_TOPAZHP_TOP_CR_INTRA8_SCALE_TABLE 0x00000007 |
| #define SHIFT_TOPAZHP_TOP_CR_INTRA8_SCALE_TABLE 0 |
| #define REGNUM_TOPAZHP_TOP_CR_INTRA8_SCALE_TABLE 0x0130 |
| #define SIGNED_TOPAZHP_TOP_CR_INTRA8_SCALE_TABLE 0 |
| |
| /* Register CR_QPCB_QPCR_OFFSET */ |
| #define TOPAZHP_TOP_CR_QPCB_QPCR_OFFSET 0x0134 |
| #define MASK_TOPAZHP_TOP_CR_QPCB_OFFSET 0x0000001F |
| #define SHIFT_TOPAZHP_TOP_CR_QPCB_OFFSET 0 |
| #define REGNUM_TOPAZHP_TOP_CR_QPCB_OFFSET 0x0134 |
| #define SIGNED_TOPAZHP_TOP_CR_QPCB_OFFSET 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_QPCR_OFFSET 0x00001F00 |
| #define SHIFT_TOPAZHP_TOP_CR_QPCR_OFFSET 8 |
| #define REGNUM_TOPAZHP_TOP_CR_QPCR_OFFSET 0x0134 |
| #define SIGNED_TOPAZHP_TOP_CR_QPCR_OFFSET 0 |
| |
| /* Register CR_INTER_INTRA_SCALE_TABLE */ |
| #define TOPAZHP_TOP_CR_INTER_INTRA_SCALE_TABLE 0x0140 |
| #define MASK_TOPAZHP_TOP_CR_INTRA_SCALING_TABLE 0x0000FF00 |
| #define SHIFT_TOPAZHP_TOP_CR_INTRA_SCALING_TABLE 8 |
| #define REGNUM_TOPAZHP_TOP_CR_INTRA_SCALING_TABLE 0x0140 |
| #define SIGNED_TOPAZHP_TOP_CR_INTRA_SCALING_TABLE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_INTER_SCALING_TABLE 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_INTER_SCALING_TABLE 0 |
| #define REGNUM_TOPAZHP_TOP_CR_INTER_SCALING_TABLE 0x0140 |
| #define SIGNED_TOPAZHP_TOP_CR_INTER_SCALING_TABLE 0 |
| |
| /* Register CR_SKIPPED_CODED_SCALE_TABLE */ |
| #define TOPAZHP_TOP_CR_SKIPPED_CODED_SCALE_TABLE 0x0144 |
| #define MASK_TOPAZHP_TOP_CR_CODED_SCALING_TABLE 0x0000FF00 |
| #define SHIFT_TOPAZHP_TOP_CR_CODED_SCALING_TABLE 8 |
| #define REGNUM_TOPAZHP_TOP_CR_CODED_SCALING_TABLE 0x0144 |
| #define SIGNED_TOPAZHP_TOP_CR_CODED_SCALING_TABLE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_SKIPPED_SCALING_TABLE 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_SKIPPED_SCALING_TABLE 0 |
| #define REGNUM_TOPAZHP_TOP_CR_SKIPPED_SCALING_TABLE 0x0144 |
| #define SIGNED_TOPAZHP_TOP_CR_SKIPPED_SCALING_TABLE 0 |
| |
| /* Register CR_POLYNOM_ALPHA_COEFF_CORE_0 */ |
| #define TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_0 0x0148 |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_00 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_00 0 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_00 0x0148 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_00 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_00 0x007FFF00 |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_00 8 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_00 0x0148 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_00 1 |
| |
| /* Register CR_POLYNOM_GAMMA_COEFF_CORE_0 */ |
| #define TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_0 0x014C |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_00 0x0003FFFF |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_00 0 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_00 0x014C |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_00 0 |
| |
| /* Register CR_POLYNOM_CUTOFF_CORE_0 */ |
| #define TOPAZHP_TOP_CR_POLYNOM_CUTOFF_CORE_0 0x0150 |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_00 0x0000003F |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_00 0 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_00 0x0150 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_00 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_00 0x00000FC0 |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_00 6 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_00 0x0150 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_00 0 |
| |
| /* Register CR_POLYNOM_ALPHA_COEFF_CORE_1 */ |
| #define TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_1 0x0154 |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_01 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_01 0 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_01 0x0154 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_01 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_01 0x007FFF00 |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_01 8 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_01 0x0154 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_01 1 |
| |
| /* Register CR_POLYNOM_GAMMA_COEFF_CORE_1 */ |
| #define TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_1 0x0158 |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_01 0x0003FFFF |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_01 0 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_01 0x0158 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_01 0 |
| |
| /* Register CR_POLYNOM_CUTOFF_CORE_1 */ |
| #define TOPAZHP_TOP_CR_POLYNOM_CUTOFF_CORE_1 0x015C |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_01 0x0000003F |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_01 0 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_01 0x015C |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_01 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_01 0x00000FC0 |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_01 6 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_01 0x015C |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_01 0 |
| |
| /* Register CR_POLYNOM_ALPHA_COEFF_CORE_2 */ |
| #define TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_2 0x0160 |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_02 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_02 0 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_02 0x0160 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_02 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_02 0x007FFF00 |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_02 8 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_02 0x0160 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_02 1 |
| |
| /* Register CR_POLYNOM_GAMMA_COEFF_CORE_2 */ |
| #define TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_2 0x0164 |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_02 0x0003FFFF |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_02 0 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_02 0x0164 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_02 0 |
| |
| /* Register CR_POLYNOM_CUTOFF_CORE_2 */ |
| #define TOPAZHP_TOP_CR_POLYNOM_CUTOFF_CORE_2 0x0168 |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_02 0x0000003F |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_02 0 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_02 0x0168 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_02 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_02 0x00000FC0 |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_02 6 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_02 0x0168 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_02 0 |
| |
| /* Register CR_FIRMWARE_REG_4 */ |
| #define TOPAZHP_TOP_CR_FIRMWARE_REG_4 0x0300 |
| #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_4 0xFFFFFFFF |
| #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_4 0 |
| #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_4 0x0300 |
| #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_4 0 |
| |
| /* Register CR_FIRMWARE_REG_5 */ |
| #define TOPAZHP_TOP_CR_FIRMWARE_REG_5 0x0304 |
| #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_5 0xFFFFFFFF |
| #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_5 0 |
| #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_5 0x0304 |
| #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_5 0 |
| |
| /* Register CR_FIRMWARE_REG_6 */ |
| #define TOPAZHP_TOP_CR_FIRMWARE_REG_6 0x0308 |
| #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_6 0xFFFFFFFF |
| #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_6 0 |
| #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_6 0x0308 |
| #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_6 0 |
| |
| /* Register CR_FIRMWARE_REG_7 */ |
| #define TOPAZHP_TOP_CR_FIRMWARE_REG_7 0x030C |
| #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_7 0xFFFFFFFF |
| #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_7 0 |
| #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_7 0x030C |
| #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_7 0 |
| |
| /* Register CR_MULTICORE_RSVD0 */ |
| #define TOPAZHP_TOP_CR_MULTICORE_RSVD0 0x03B0 |
| #define MASK_TOPAZHP_TOP_CR_RESERVED0 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_RESERVED0 0 |
| #define REGNUM_TOPAZHP_TOP_CR_RESERVED0 0x03B0 |
| #define SIGNED_TOPAZHP_TOP_CR_RESERVED0 0 |
| |
| /* Register CR_TOPAZHP_CORE_ID */ |
| #define TOPAZHP_TOP_CR_TOPAZHP_CORE_ID 0x03C0 |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_CORE_CONFIG 0x0000FFFF |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_CORE_CONFIG 0 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_CORE_CONFIG 0x03C0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_CORE_CONFIG 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_CORE_ID 0x00FF0000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_CORE_ID 16 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_CORE_ID 0x03C0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_CORE_ID 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_GROUP_ID 0xFF000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_GROUP_ID 24 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_GROUP_ID 0x03C0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_GROUP_ID 0 |
| |
| /* Register CR_TOPAZHP_CORE_REV */ |
| #define TOPAZHP_TOP_CR_TOPAZHP_CORE_REV 0x03D0 |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MAINT_REV 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MAINT_REV 0 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MAINT_REV 0x03D0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MAINT_REV 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MINOR_REV 0x0000FF00 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MINOR_REV 8 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MINOR_REV 0x03D0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MINOR_REV 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MAJOR_REV 0x00FF0000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MAJOR_REV 16 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MAJOR_REV 0x03D0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MAJOR_REV 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER 0xFF000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER 24 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER 0x03D0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER 0 |
| |
| /* Register CR_TOPAZHP_CORE_DES1 */ |
| #define TOPAZHP_TOP_CR_TOPAZHP_CORE_DES1 0x03E0 |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_SCALER_SUPPORTED 0x00000080 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_SCALER_SUPPORTED 7 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_SCALER_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_SCALER_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_GENERATE_PERFORMANCE_STORE 0x00000100 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_GENERATE_PERFORMANCE_STORE 8 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_GENERATE_PERFORMANCE_STORE 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_GENERATE_PERFORMANCE_STORE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_LOSSLESS_SUPPORTED 0x00000200 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_LOSSLESS_SUPPORTED 9 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_LOSSLESS_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_LOSSLESS_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_CUSTOM_QUANT_SUPPORTED 0x00000400 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_CUSTOM_QUANT_SUPPORTED 10 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_CUSTOM_QUANT_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_CUSTOM_QUANT_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MPEG2_SUPPORTED 0x00000800 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MPEG2_SUPPORTED 11 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MPEG2_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MPEG2_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_SUBSET 0x00001000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_SUBSET 12 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_SUBSET 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_SUBSET 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_ALL 0x00002000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_ALL 13 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_ALL 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_ALL 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_ME_SUPPORTED 0x00004000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_ME_SUPPORTED 14 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_ME_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_ME_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_SUPPORTED 0x00008000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_SUPPORTED 15 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_2_REF_ON_P_PIC_SUPPORTED 0x00010000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_2_REF_ON_P_PIC_SUPPORTED 16 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_2_REF_ON_P_PIC_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_2_REF_ON_P_PIC_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_SPATIAL_DIRECT_SUPPORTED 0x00020000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_SPATIAL_DIRECT_SUPPORTED 17 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_SPATIAL_DIRECT_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_SPATIAL_DIRECT_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_MULTIPASS_SUPPORTED 0x00040000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_MULTIPASS_SUPPORTED 18 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_MULTIPASS_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_MULTIPASS_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_DEFAULT_TABLES_SUPPORTED 0x00080000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_DEFAULT_TABLES_SUPPORTED 19 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_DEFAULT_TABLES_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_DEFAULT_TABLES_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_8X8_TRANSFORM_SUPPORTED 0x00100000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_8X8_TRANSFORM_SUPPORTED 20 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_8X8_TRANSFORM_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_8X8_TRANSFORM_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_INTERLACED_SUPPORTED 0x00200000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_INTERLACED_SUPPORTED 21 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_INTERLACED_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_INTERLACED_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_B_PIC_SUPPORTED 0x00400000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_B_PIC_SUPPORTED 22 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_B_PIC_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_B_PIC_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_16X8_8X16_SUPPORTED 0x00800000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_16X8_8X16_SUPPORTED 23 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_16X8_8X16_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_16X8_8X16_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_CABAC_SUPPORTED 0x01000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_CABAC_SUPPORTED 24 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_CABAC_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_CABAC_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_SLAVE_JPEG_SUPPORTED 0x02000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_SLAVE_JPEG_SUPPORTED 25 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_SLAVE_JPEG_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_SLAVE_JPEG_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_JPEG_SUPPORTED 0x04000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_JPEG_SUPPORTED 26 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_JPEG_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_JPEG_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H263_SUPPORTED 0x08000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H263_SUPPORTED 27 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H263_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H263_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MPEG4_SUPPORTED 0x10000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MPEG4_SUPPORTED 28 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MPEG4_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MPEG4_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_SUPPORTED 0x20000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_SUPPORTED 29 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_DMAC_SUPPORTED 0x40000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_DMAC_SUPPORTED 30 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_DMAC_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_DMAC_SUPPORTED 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MMU_SUPPORTED 0x80000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MMU_SUPPORTED 31 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MMU_SUPPORTED 0x03E0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MMU_SUPPORTED 0 |
| |
| /* Register CR_TOPAZHP_CORE_DES2 */ |
| #define TOPAZHP_TOP_CR_TOPAZHP_CORE_DES2 0x03F0 |
| #define MASK_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER2 0xFFFFFFFF |
| #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER2 0 |
| #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER2 0x03F0 |
| #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER2 0 |
| |
| |
| /* Table MMU_DIR_LIST_BASE */ |
| |
| /* Register CR_MMU_DIR_LIST_BASE */ |
| #define TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE(X) (0x0030 + (4 * (X))) |
| #define MASK_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR 0xFFFFFFF0 |
| #define SHIFT_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR 4 |
| #define REGNUM_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR 0x0030 |
| #define SIGNED_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR 0 |
| |
| /* Number of entries in table MMU_DIR_LIST_BASE */ |
| |
| #define TOPAZHP_TOP_MMU_DIR_LIST_BASE_SIZE_UINT32 1 |
| #define TOPAZHP_TOP_MMU_DIR_LIST_BASE_NUM_ENTRIES 1 |
| |
| |
| /* Table MMU_TILE */ |
| |
| /* Register CR_MMU_TILE */ |
| #define TOPAZHP_TOP_CR_MMU_TILE(X) (0x0038 + (4 * (X))) |
| #define MASK_TOPAZHP_TOP_CR_TILE_MIN_ADDR 0x00000FFF |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_MIN_ADDR 0 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_MIN_ADDR 0x0038 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_MIN_ADDR 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TILE_MAX_ADDR 0x00FFF000 |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_MAX_ADDR 12 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_MAX_ADDR 0x0038 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_MAX_ADDR 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TILE_STRIDE 0x07000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_STRIDE 24 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_STRIDE 0x0038 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_STRIDE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TILE_ENABLE 0x10000000 |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_ENABLE 28 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_ENABLE 0x0038 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_ENABLE 0 |
| |
| /* Number of entries in table MMU_TILE */ |
| |
| #define TOPAZHP_TOP_MMU_TILE_SIZE_UINT32 2 |
| #define TOPAZHP_TOP_MMU_TILE_NUM_ENTRIES 2 |
| |
| |
| /* Table MMU_TILE_EXT */ |
| |
| /* Register CR_MMU_TILE_EXT */ |
| #define TOPAZHP_TOP_CR_MMU_TILE_EXT(X) (0x0080 + (4 * (X))) |
| #define MASK_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT 0 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT 0x0080 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT 0x0000FF00 |
| #define SHIFT_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT 8 |
| #define REGNUM_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT 0x0080 |
| #define SIGNED_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT 0 |
| |
| /* Number of entries in table MMU_TILE_EXT */ |
| |
| #define TOPAZHP_TOP_MMU_TILE_EXT_SIZE_UINT32 2 |
| #define TOPAZHP_TOP_MMU_TILE_EXT_NUM_ENTRIES 2 |
| |
| |
| /* Table TABLES_POLYNOM_TABLE */ |
| |
| /* Register CR_POLYNOM_ALPHA_COEFF_CORE */ |
| #define TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE(X) (0x0148 + (12 * (X))) |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE 0x000000FF |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE 0 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE 0x0148 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE 0x007FFF00 |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE 8 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE 0x0148 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE 1 |
| |
| /* Register CR_POLYNOM_GAMMA_COEFF_CORE */ |
| #define TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE(X) (0x014C + (12 * (X))) |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE 0x0003FFFF |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE 0 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE 0x014C |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE 0 |
| |
| /* Register CR_POLYNOM_CUTOFF_CORE */ |
| #define TOPAZHP_TOP_CR_POLYNOM_CUTOFF_CORE(X) (0x0150 + (12 * (X))) |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE 0x0000003F |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE 0 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE 0x0150 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE 0 |
| |
| #define MASK_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE 0x00000FC0 |
| #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE 6 |
| #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE 0x0150 |
| #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE 0 |
| |
| /* Number of entries in table TABLES_POLYNOM_TABLE */ |
| |
| #define TOPAZHP_TOP_TABLES_POLYNOM_TABLE_SIZE_UINT32 9 |
| #define TOPAZHP_TOP_TABLES_POLYNOM_TABLE_NUM_ENTRIES 3 |
| |
| /* |
| Byte range covering the group TOPAZHP_MULTICORE file |
| */ |
| |
| #define TOPAZHP_TOP_TOPAZHP_MULTICORE_REGISTERS_START 0x00000000 |
| #define TOPAZHP_TOP_TOPAZHP_MULTICORE_REGISTERS_END 0x000003F3 |
| |
| /* |
| Byte range covering the whole register file |
| */ |
| |
| #define TOPAZHP_TOP_REGISTERS_START 0x00000000 |
| #define TOPAZHP_TOP_REGISTERS_END 0x000003F3 |
| #define TOPAZHP_TOP_REG_DEFAULT_TABLE struct {\ |
| IMG_UINT16 uRegOffset;\ |
| IMG_UINT32 uRegDefault;\ |
| IMG_UINT32 uRegMask;\ |
| bool bReadonly;\ |
| const char* pszName;\ |
| } TOPAZHP_TOP_Defaults[] = {\ |
| {0x0000, 0x00000000, 0x00000007, 0, "CR_MULTICORE_SRST" } ,\ |
| {0x0004, 0x00000000, 0xC0FFFF0F, 0, "CR_MULTICORE_INT_STAT" } ,\ |
| {0x0008, 0x00000000, 0x40FFFF0F, 0, "CR_MULTICORE_MTX_INT_ENAB" } ,\ |
| {0x000C, 0x00000000, 0x80FFFF0F, 0, "CR_MULTICORE_HOST_INT_ENAB" } ,\ |
| {0x0010, 0x00000000, 0x0000000F, 0, "CR_MULTICORE_INT_CLEAR" } ,\ |
| {0x0014, 0x00000000, 0x00000002, 0, "CR_MULTICORE_MAN_CLK_GATE" } ,\ |
| {0x0018, 0x00000000, 0x00000003, 0, "CR_TOPAZ_MTX_C_RATIO" } ,\ |
| {0x001C, 0x00000000, 0xFFFFF001, 1, "CR_MMU_STATUS" } ,\ |
| {0x0020, 0x00000000, 0x000000FF, 1, "CR_MMU_MEM_REQ" } ,\ |
| {0x0024, 0x00010000, 0x0001070F, 0, "CR_MMU_CONTROL0" } ,\ |
| {0x0028, 0xC000000C, 0xFFFFFFFF, 0, "CR_MMU_CONTROL1" } ,\ |
| {0x002C, 0x00000000, 0x00000009, 0, "CR_MMU_CONTROL2" } ,\ |
| {0x0030, 0x00000000, 0xFFFFFFF0, 0, "CR_MMU_DIR_LIST_BASE_0" } ,\ |
| {0x0038, 0x00000000, 0x17FFFFFF, 0, "CR_MMU_TILE_0" } ,\ |
| {0x003C, 0x00000000, 0x17FFFFFF, 0, "CR_MMU_TILE_1" } ,\ |
| {0x0044, 0x00010004, 0x0F0F0F1F, 0, "CR_MTX_DEBUG_MSTR" } ,\ |
| {0x0048, 0x00000000, 0x0F0F0F1F, 0, "CR_MTX_DEBUG_SLV" } ,\ |
| {0x0050, 0x00000000, 0xC0000007, 0, "CR_MULTICORE_CORE_SEL_0" } ,\ |
| {0x0054, 0x00000000, 0x0000001F, 0, "CR_MULTICORE_CORE_SEL_1" } ,\ |
| {0x0058, 0x08020102, 0x0F07071F, 1, "CR_MULTICORE_HW_CFG" } ,\ |
| {0x0060, 0x00000000, 0xFFFFFFFF, 0, "CR_MULTICORE_CMD_FIFO_WRITE" } ,\ |
| {0x0064, 0x00000020, 0x000001FF, 1, "CR_MULTICORE_CMD_FIFO_WRITE_SPACE" } ,\ |
| {0x0070, 0x00000000, 0xFFFFFFFF, 0, "CR_TOPAZ_CMD_FIFO_READ" } ,\ |
| {0x0074, 0x00000000, 0x000001FF, 1, "CR_TOPAZ_CMD_FIFO_READ_AVAILABLE" } ,\ |
| {0x0078, 0x00000000, 0x00000001, 0, "CR_TOPAZ_CMD_FIFO_FLUSH" } ,\ |
| {0x0080, 0x00000000, 0x0000FFFF, 0, "CR_MMU_TILE_EXT_0" } ,\ |
| {0x0084, 0x00000000, 0x0000FFFF, 0, "CR_MMU_TILE_EXT_1" } ,\ |
| {0x0090, 0x00000001, 0x0000007F, 0, "CR_TOPAZHP_CMD_PRIORITY_ENABLE" } ,\ |
| {0x0094, 0x00000000, 0x0FFF03FF, 0, "CR_TOPAZHP_LIMITED_THROUGHPUT" } ,\ |
| {0x0100, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_1" } ,\ |
| {0x0104, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_2" } ,\ |
| {0x0108, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_3" } ,\ |
| {0x0110, 0x00000000, 0xFFFFFFFF, 0, "CR_CYCLE_COUNTER" } ,\ |
| {0x0114, 0x00000000, 0x00000001, 0, "CR_CYCLE_COUNTER_CTRL" } ,\ |
| {0x0118, 0x00000000, 0x00000001, 0, "CR_MULTICORE_IDLE_PWR_MAN" } ,\ |
| {0x0124, 0x00000000, 0x00007FFF, 0, "CR_DIRECT_BIAS_TABLE" } ,\ |
| {0x0128, 0x00000000, 0xFFFFFFFF, 0, "CR_INTRA_BIAS_TABLE" } ,\ |
| {0x012C, 0x00000000, 0x0000FFFF, 0, "CR_INTER_BIAS_TABLE" } ,\ |
| {0x0130, 0x00000000, 0x00000007, 0, "CR_INTRA_SCALE_TABLE" } ,\ |
| {0x0134, 0x00000000, 0x00001F1F, 0, "CR_QPCB_QPCR_OFFSET" } ,\ |
| {0x0140, 0x00000000, 0x0000FFFF, 0, "CR_INTER_INTRA_SCALE_TABLE" } ,\ |
| {0x0144, 0x00000000, 0x0000FFFF, 0, "CR_SKIPPED_CODED_SCALE_TABLE" } ,\ |
| {0x0148, 0x00000000, 0x007FFFFF, 0, "CR_POLYNOM_ALPHA_COEFF_CORE_0" } ,\ |
| {0x014C, 0x00000000, 0x0003FFFF, 0, "CR_POLYNOM_GAMMA_COEFF_CORE_0" } ,\ |
| {0x0150, 0x0000071C, 0x00000FFF, 0, "CR_POLYNOM_CUTOFF_CORE_0" } ,\ |
| {0x0154, 0x00000000, 0x007FFFFF, 0, "CR_POLYNOM_ALPHA_COEFF_CORE_1" } ,\ |
| {0x0158, 0x00000000, 0x0003FFFF, 0, "CR_POLYNOM_GAMMA_COEFF_CORE_1" } ,\ |
| {0x015C, 0x0000071C, 0x00000FFF, 0, "CR_POLYNOM_CUTOFF_CORE_1" } ,\ |
| {0x0160, 0x00000000, 0x007FFFFF, 0, "CR_POLYNOM_ALPHA_COEFF_CORE_2" } ,\ |
| {0x0164, 0x00000000, 0x0003FFFF, 0, "CR_POLYNOM_GAMMA_COEFF_CORE_2" } ,\ |
| {0x0168, 0x0000071C, 0x00000FFF, 0, "CR_POLYNOM_CUTOFF_CORE_2" } ,\ |
| {0x0300, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_4" } ,\ |
| {0x0304, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_5" } ,\ |
| {0x0308, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_6" } ,\ |
| {0x030C, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_7" } ,\ |
| {0x03B0, 0x00000000, 0x000000FF, 0, "CR_MULTICORE_RSVD0" } ,\ |
| {0x03C0, 0x04070000, 0xFFFFFFFF, 1, "CR_TOPAZHP_CORE_ID" } ,\ |
| {0x03D0, 0x00030203, 0xFFFFFFFF, 1, "CR_TOPAZHP_CORE_REV" } ,\ |
| {0x03E0, 0xFFFFFF00, 0xFFFFFF80, 1, "CR_TOPAZHP_CORE_DES1" } ,\ |
| {0x03F0, 0x00000000, 0xFFFFFFFF, 1, "CR_TOPAZHP_CORE_DES2" } ,\ |
| { 0 }} |
| |
| #define TOPAZHP_TOP_REGS_INIT(uBase) \ |
| { \ |
| int n;\ |
| TOPAZHP_TOP_REG_DEFAULT_TABLE;\ |
| for (n = 0; n < sizeof(TOPAZHP_TOP_Defaults)/ sizeof(TOPAZHP_TOP_Defaults[0] ) -1; n++)\ |
| {\ |
| RegWriteNoTrap(TOPAZHP_TOP_Defaults[n].uRegOffset + uBase, TOPAZHP_TOP_Defaults[n].uRegDefault); \ |
| }\ |
| } |
| #endif |
