| //===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // Interface definition for SIInstrInfo. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| |
| #ifndef SIINSTRINFO_H |
| #define SIINSTRINFO_H |
| |
| #include "AMDGPUInstrInfo.h" |
| #include "SIRegisterInfo.h" |
| |
| namespace llvm { |
| |
| class SIInstrInfo : public AMDGPUInstrInfo { |
| private: |
| const SIRegisterInfo RI; |
| AMDGPUTargetMachine &TM; |
| |
| public: |
| explicit SIInstrInfo(AMDGPUTargetMachine &tm); |
| |
| const SIRegisterInfo &getRegisterInfo() const; |
| |
| virtual void copyPhysReg(MachineBasicBlock &MBB, |
| MachineBasicBlock::iterator MI, DebugLoc DL, |
| unsigned DestReg, unsigned SrcReg, |
| bool KillSrc) const; |
| |
| /// getEncodingType - Returns the encoding type of this instruction. |
| unsigned getEncodingType(const MachineInstr &MI) const; |
| |
| /// getEncodingBytes - Returns the size of this instructions encoding in |
| /// number of bytes. |
| unsigned getEncodingBytes(const MachineInstr &MI) const; |
| |
| virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg, |
| int64_t Imm) const; |
| |
| virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;} |
| virtual bool isMov(unsigned Opcode) const; |
| |
| }; |
| |
| } // End namespace llvm |
| |
| namespace SIInstrFlags { |
| enum Flags { |
| // First 4 bits are the instruction encoding |
| NEED_WAIT = 1 << 4 |
| }; |
| } |
| |
| #endif //SIINSTRINFO_H |