| //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // SI Implementation of TargetInstrInfo. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| |
| #include "SIInstrInfo.h" |
| #include "AMDGPUTargetMachine.h" |
| #include "llvm/CodeGen/MachineInstrBuilder.h" |
| #include "llvm/CodeGen/MachineRegisterInfo.h" |
| #include "llvm/MC/MCInstrDesc.h" |
| |
| #include <stdio.h> |
| |
| using namespace llvm; |
| |
| SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm) |
| : AMDGPUInstrInfo(tm), |
| RI(tm, *this), |
| TM(tm) |
| { } |
| |
| const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const |
| { |
| return RI; |
| } |
| |
| void |
| SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, |
| MachineBasicBlock::iterator MI, DebugLoc DL, |
| unsigned DestReg, unsigned SrcReg, |
| bool KillSrc) const |
| { |
| |
| // If we are trying to copy to or from SCC, there is a bug somewhere else in |
| // the backend. While it may be theoretically possible to do this, it should |
| // never be necessary. |
| assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); |
| |
| BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) |
| .addReg(SrcReg, getKillRegState(KillSrc)); |
| } |
| |
| MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, |
| int64_t Imm) const |
| { |
| MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc()); |
| MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); |
| MachineInstrBuilder(MI).addImm(Imm); |
| |
| return MI; |
| |
| } |
| |
| bool SIInstrInfo::isMov(unsigned Opcode) const |
| { |
| switch(Opcode) { |
| default: return false; |
| case AMDGPU::S_MOV_B32: |
| case AMDGPU::S_MOV_B64: |
| case AMDGPU::V_MOV_B32_e32: |
| case AMDGPU::V_MOV_B32_e64: |
| case AMDGPU::V_MOV_IMM_F32: |
| case AMDGPU::V_MOV_IMM_I32: |
| case AMDGPU::S_MOV_IMM_I32: |
| return true; |
| } |
| } |