hardware/arduino/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3a4_sram.icf

/*-  SRAM0 memory region -*/
define symbol __region_RAM0_size__          = 0x8000 ;
define symbol __region_RAM0_start__         = 0x20000000 ;
define symbol __region_RAM0_end__           = __region_RAM0_start__+__region_RAM0_size__-1 ;

export symbol __region_RAM0_size__ ;
export symbol __region_RAM0_start__ ;
export symbol __region_RAM0_end__ ;

/*-  SRAM1 memory region -*/
define symbol __region_RAM1_size__          = 0x8000 ;
define symbol __region_RAM1_start__         = 0x20080000 ;
define symbol __region_RAM1_end__           = __region_RAM1_start__+__region_RAM1_size__-1 ;

export symbol __region_RAM1_size__ ;
export symbol __region_RAM1_start__ ;
export symbol __region_RAM1_end__ ;

/*- Continous SRAM region (SRAM0 is mirrored) -*/
define symbol __region_RAM_size__           = __region_RAM0_size__+__region_RAM1_size__ ;
define symbol __region_RAM_start__          = __region_RAM1_start__-__region_RAM0_size__ ;
define symbol __region_RAM_end__            = __region_RAM1_end__ ;

export symbol __region_RAM_size__ ;
export symbol __region_RAM_start__ ;
export symbol __region_RAM_end__ ;

/*- NFC SRAM region -*/
define symbol __region_NFC_RAM_start__      = 0x20100000 ;
define symbol __region_NFC_RAM_end__        = 0x20100FFF ;

export symbol __region_NFC_RAM_start__ ;
export symbol __region_NFC_RAM_end__ ;

/*-Vector table start*/
define symbol __vector_start__              = __region_RAM_start__ ;

/*-Sizes-*/
define symbol __size_cstack__               = 0x2000 ;
define symbol __size_heap__                 = 0x2000 ;

define memory mem with size                 = 4G ;
define region RAM_region                    = mem:[from __region_RAM_start__ to __region_RAM_end__];

define block CSTACK    with alignment = 8, size = __size_cstack__   { };
define block HEAP      with alignment = 8, size = __size_heap__     { };

initialize by copy with packing=none { readwrite };
do not initialize  { section .noinit };

place at address mem:__vector_start__ { readonly section .intvec };
place in RAM_region          { readonly };
place in RAM_region          { readwrite, block CSTACK, block HEAP };