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android / platform / external / arduino-ide / f876b2abdebd02acfa4ba21e607327be4f9668d4 / . / hardware / arduino / sam / system / CMSIS / Device / ATMEL / sam3xa / html / UOTGHS.html
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8" />
<title>SAM3XA UOTGHS</title>
<link rel="stylesheet" type="text/css" href="css/html.css" media="all" />
</head>
<body id="abstract">
<div id="container">
<div id="content">
<a id="UOTGHS"></a>
<h1>SAM3XA UOTGHS</h1>
<a id="UOTGHS__User_Interface"></a>
<h2>USB On-The-Go Interface (UOTGHS) User Interface</h2>
<!--As per 11016B programmer datasheet.-->
<h3>Registers</h3>
<table class="registers">
<caption>Register Mapping</caption>
<thead>
<tr>
<th class="address">Address</th>
<th class="description">Register</th>
<th class="name">Name</th>
<th class="access">Access</th>
<th class="reset">Reset</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="address" id="address_0x400AC000">0x400AC000</td>
<td class="description">Device General Control Register</td>
<td class="name">
<a href="#UOTGHS_DEVCTRL" title="Device General Control Register" class="one_click_away">UOTGHS_DEVCTRL</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000100</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC004">0x400AC004</td>
<td class="description">Device Global Interrupt Status Register</td>
<td class="name">
<a href="#UOTGHS_DEVISR" title="Device Global Interrupt Status Register" class="one_click_away">UOTGHS_DEVISR</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC008">0x400AC008</td>
<td class="description">Device Global Interrupt Clear Register</td>
<td class="name">
<a href="#UOTGHS_DEVICR" title="Device Global Interrupt Clear Register" class="one_click_away">UOTGHS_DEVICR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC00C">0x400AC00C</td>
<td class="description">Device Global Interrupt Set Register</td>
<td class="name">
<a href="#UOTGHS_DEVIFR" title="Device Global Interrupt Set Register" class="one_click_away">UOTGHS_DEVIFR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC010">0x400AC010</td>
<td class="description">Device Global Interrupt Mask Register</td>
<td class="name">
<a href="#UOTGHS_DEVIMR" title="Device Global Interrupt Mask Register" class="one_click_away">UOTGHS_DEVIMR</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC014">0x400AC014</td>
<td class="description">Device Global Interrupt Disable Register</td>
<td class="name">
<a href="#UOTGHS_DEVIDR" title="Device Global Interrupt Disable Register" class="one_click_away">UOTGHS_DEVIDR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC018">0x400AC018</td>
<td class="description">Device Global Interrupt Enable Register</td>
<td class="name">
<a href="#UOTGHS_DEVIER" title="Device Global Interrupt Enable Register" class="one_click_away">UOTGHS_DEVIER</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC01C">0x400AC01C</td>
<td class="description">Device Endpoint Register</td>
<td class="name">
<a href="#UOTGHS_DEVEPT" title="Device Endpoint Register" class="one_click_away">UOTGHS_DEVEPT</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC020">0x400AC020</td>
<td class="description">Device Frame Number Register</td>
<td class="name">
<a href="#UOTGHS_DEVFNUM" title="Device Frame Number Register" class="one_click_away">UOTGHS_DEVFNUM</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC100">0x400AC100</td>
<td class="description">Device Endpoint Configuration Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_DEVEPTCFG" title="Device Endpoint Configuration Register (n = 0)" class="one_click_away">UOTGHS_DEVEPTCFG[10]</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00002000000020000000200000002000000020000000200000002000000020000000200000002000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC130">0x400AC130</td>
<td class="description">Device Endpoint Status Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_DEVEPTISR" title="Device Endpoint Status Register (n = 0)" class="one_click_away">UOTGHS_DEVEPTISR[10]</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000100000001000000010000000100000001000000010000000100000001000000010000000100</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC160">0x400AC160</td>
<td class="description">Device Endpoint Clear Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_DEVEPTICR" title="Device Endpoint Clear Register (n = 0)" class="one_click_away">UOTGHS_DEVEPTICR[10]</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC190">0x400AC190</td>
<td class="description">Device Endpoint Set Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_DEVEPTIFR" title="Device Endpoint Set Register (n = 0)" class="one_click_away">UOTGHS_DEVEPTIFR[10]</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC1C0">0x400AC1C0</td>
<td class="description">Device Endpoint Mask Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_DEVEPTIMR" title="Device Endpoint Mask Register (n = 0)" class="one_click_away">UOTGHS_DEVEPTIMR[10]</a>
</td>
<td class="access">read-only</td>
<td class="address">0x0</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC1F0">0x400AC1F0</td>
<td class="description">Device Endpoint Enable Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_DEVEPTIER" title="Device Endpoint Enable Register (n = 0)" class="one_click_away">UOTGHS_DEVEPTIER[10]</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC220">0x400AC220</td>
<td class="description">Device Endpoint Disable Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_DEVEPTIDR" title="Device Endpoint Disable Register (n = 0)" class="one_click_away">UOTGHS_DEVEPTIDR[10]</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC310">0x400AC310</td>
<td class="description">Device DMA Channel Next Descriptor Address Register (n = 1)</td>
<td class="name">
<a href="#UOTGHS_DEVDMANXTDSC1" title="Device DMA Channel Next Descriptor Address Register (n = 1)" class="one_click_away">UOTGHS_DEVDMANXTDSC1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC314">0x400AC314</td>
<td class="description">Device DMA Channel Address Register (n = 1)</td>
<td class="name">
<a href="#UOTGHS_DEVDMAADDRESS1" title="Device DMA Channel Address Register (n = 1)" class="one_click_away">UOTGHS_DEVDMAADDRESS1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC318">0x400AC318</td>
<td class="description">Device DMA Channel Control Register (n = 1)</td>
<td class="name">
<a href="#UOTGHS_DEVDMACONTROL1" title="Device DMA Channel Control Register (n = 1)" class="one_click_away">UOTGHS_DEVDMACONTROL1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC31C">0x400AC31C</td>
<td class="description">Device DMA Channel Status Register (n = 1)</td>
<td class="name">
<a href="#UOTGHS_DEVDMASTATUS1" title="Device DMA Channel Status Register (n = 1)" class="one_click_away">UOTGHS_DEVDMASTATUS1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC320">0x400AC320</td>
<td class="description">Device DMA Channel Next Descriptor Address Register (n = 2)</td>
<td class="name">
<a href="#UOTGHS_DEVDMANXTDSC2" title="Device DMA Channel Next Descriptor Address Register (n = 2)" class="one_click_away">UOTGHS_DEVDMANXTDSC2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC324">0x400AC324</td>
<td class="description">Device DMA Channel Address Register (n = 2)</td>
<td class="name">
<a href="#UOTGHS_DEVDMAADDRESS2" title="Device DMA Channel Address Register (n = 2)" class="one_click_away">UOTGHS_DEVDMAADDRESS2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC328">0x400AC328</td>
<td class="description">Device DMA Channel Control Register (n = 2)</td>
<td class="name">
<a href="#UOTGHS_DEVDMACONTROL2" title="Device DMA Channel Control Register (n = 2)" class="one_click_away">UOTGHS_DEVDMACONTROL2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC32C">0x400AC32C</td>
<td class="description">Device DMA Channel Status Register (n = 2)</td>
<td class="name">
<a href="#UOTGHS_DEVDMASTATUS2" title="Device DMA Channel Status Register (n = 2)" class="one_click_away">UOTGHS_DEVDMASTATUS2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC330">0x400AC330</td>
<td class="description">Device DMA Channel Next Descriptor Address Register (n = 3)</td>
<td class="name">
<a href="#UOTGHS_DEVDMANXTDSC3" title="Device DMA Channel Next Descriptor Address Register (n = 3)" class="one_click_away">UOTGHS_DEVDMANXTDSC3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC334">0x400AC334</td>
<td class="description">Device DMA Channel Address Register (n = 3)</td>
<td class="name">
<a href="#UOTGHS_DEVDMAADDRESS3" title="Device DMA Channel Address Register (n = 3)" class="one_click_away">UOTGHS_DEVDMAADDRESS3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC338">0x400AC338</td>
<td class="description">Device DMA Channel Control Register (n = 3)</td>
<td class="name">
<a href="#UOTGHS_DEVDMACONTROL3" title="Device DMA Channel Control Register (n = 3)" class="one_click_away">UOTGHS_DEVDMACONTROL3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC33C">0x400AC33C</td>
<td class="description">Device DMA Channel Status Register (n = 3)</td>
<td class="name">
<a href="#UOTGHS_DEVDMASTATUS3" title="Device DMA Channel Status Register (n = 3)" class="one_click_away">UOTGHS_DEVDMASTATUS3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC340">0x400AC340</td>
<td class="description">Device DMA Channel Next Descriptor Address Register (n = 4)</td>
<td class="name">
<a href="#UOTGHS_DEVDMANXTDSC4" title="Device DMA Channel Next Descriptor Address Register (n = 4)" class="one_click_away">UOTGHS_DEVDMANXTDSC4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC344">0x400AC344</td>
<td class="description">Device DMA Channel Address Register (n = 4)</td>
<td class="name">
<a href="#UOTGHS_DEVDMAADDRESS4" title="Device DMA Channel Address Register (n = 4)" class="one_click_away">UOTGHS_DEVDMAADDRESS4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC348">0x400AC348</td>
<td class="description">Device DMA Channel Control Register (n = 4)</td>
<td class="name">
<a href="#UOTGHS_DEVDMACONTROL4" title="Device DMA Channel Control Register (n = 4)" class="one_click_away">UOTGHS_DEVDMACONTROL4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC34C">0x400AC34C</td>
<td class="description">Device DMA Channel Status Register (n = 4)</td>
<td class="name">
<a href="#UOTGHS_DEVDMASTATUS4" title="Device DMA Channel Status Register (n = 4)" class="one_click_away">UOTGHS_DEVDMASTATUS4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC350">0x400AC350</td>
<td class="description">Device DMA Channel Next Descriptor Address Register (n = 5)</td>
<td class="name">
<a href="#UOTGHS_DEVDMANXTDSC5" title="Device DMA Channel Next Descriptor Address Register (n = 5)" class="one_click_away">UOTGHS_DEVDMANXTDSC5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC354">0x400AC354</td>
<td class="description">Device DMA Channel Address Register (n = 5)</td>
<td class="name">
<a href="#UOTGHS_DEVDMAADDRESS5" title="Device DMA Channel Address Register (n = 5)" class="one_click_away">UOTGHS_DEVDMAADDRESS5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC358">0x400AC358</td>
<td class="description">Device DMA Channel Control Register (n = 5)</td>
<td class="name">
<a href="#UOTGHS_DEVDMACONTROL5" title="Device DMA Channel Control Register (n = 5)" class="one_click_away">UOTGHS_DEVDMACONTROL5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC35C">0x400AC35C</td>
<td class="description">Device DMA Channel Status Register (n = 5)</td>
<td class="name">
<a href="#UOTGHS_DEVDMASTATUS5" title="Device DMA Channel Status Register (n = 5)" class="one_click_away">UOTGHS_DEVDMASTATUS5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC360">0x400AC360</td>
<td class="description">Device DMA Channel Next Descriptor Address Register (n = 6)</td>
<td class="name">
<a href="#UOTGHS_DEVDMANXTDSC6" title="Device DMA Channel Next Descriptor Address Register (n = 6)" class="one_click_away">UOTGHS_DEVDMANXTDSC6</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC364">0x400AC364</td>
<td class="description">Device DMA Channel Address Register (n = 6)</td>
<td class="name">
<a href="#UOTGHS_DEVDMAADDRESS6" title="Device DMA Channel Address Register (n = 6)" class="one_click_away">UOTGHS_DEVDMAADDRESS6</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC368">0x400AC368</td>
<td class="description">Device DMA Channel Control Register (n = 6)</td>
<td class="name">
<a href="#UOTGHS_DEVDMACONTROL6" title="Device DMA Channel Control Register (n = 6)" class="one_click_away">UOTGHS_DEVDMACONTROL6</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC36C">0x400AC36C</td>
<td class="description">Device DMA Channel Status Register (n = 6)</td>
<td class="name">
<a href="#UOTGHS_DEVDMASTATUS6" title="Device DMA Channel Status Register (n = 6)" class="one_click_away">UOTGHS_DEVDMASTATUS6</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC370">0x400AC370</td>
<td class="description">Device DMA Channel Next Descriptor Address Register (n = 7)</td>
<td class="name">
<a href="#UOTGHS_DEVDMANXTDSC7" title="Device DMA Channel Next Descriptor Address Register (n = 7)" class="one_click_away">UOTGHS_DEVDMANXTDSC7</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC374">0x400AC374</td>
<td class="description">Device DMA Channel Address Register (n = 7)</td>
<td class="name">
<a href="#UOTGHS_DEVDMAADDRESS7" title="Device DMA Channel Address Register (n = 7)" class="one_click_away">UOTGHS_DEVDMAADDRESS7</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC378">0x400AC378</td>
<td class="description">Device DMA Channel Control Register (n = 7)</td>
<td class="name">
<a href="#UOTGHS_DEVDMACONTROL7" title="Device DMA Channel Control Register (n = 7)" class="one_click_away">UOTGHS_DEVDMACONTROL7</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC37C">0x400AC37C</td>
<td class="description">Device DMA Channel Status Register (n = 7)</td>
<td class="name">
<a href="#UOTGHS_DEVDMASTATUS7" title="Device DMA Channel Status Register (n = 7)" class="one_click_away">UOTGHS_DEVDMASTATUS7</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC400">0x400AC400</td>
<td class="description">Host General Control Register</td>
<td class="name">
<a href="#UOTGHS_HSTCTRL" title="Host General Control Register" class="one_click_away">UOTGHS_HSTCTRL</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC404">0x400AC404</td>
<td class="description">Host Global Interrupt Status Register</td>
<td class="name">
<a href="#UOTGHS_HSTISR" title="Host Global Interrupt Status Register" class="one_click_away">UOTGHS_HSTISR</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC408">0x400AC408</td>
<td class="description">Host Global Interrupt Clear Register</td>
<td class="name">
<a href="#UOTGHS_HSTICR" title="Host Global Interrupt Clear Register" class="one_click_away">UOTGHS_HSTICR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC40C">0x400AC40C</td>
<td class="description">Host Global Interrupt Set Register</td>
<td class="name">
<a href="#UOTGHS_HSTIFR" title="Host Global Interrupt Set Register" class="one_click_away">UOTGHS_HSTIFR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC410">0x400AC410</td>
<td class="description">Host Global Interrupt Mask Register</td>
<td class="name">
<a href="#UOTGHS_HSTIMR" title="Host Global Interrupt Mask Register" class="one_click_away">UOTGHS_HSTIMR</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC414">0x400AC414</td>
<td class="description">Host Global Interrupt Disable Register</td>
<td class="name">
<a href="#UOTGHS_HSTIDR" title="Host Global Interrupt Disable Register" class="one_click_away">UOTGHS_HSTIDR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC418">0x400AC418</td>
<td class="description">Host Global Interrupt Enable Register</td>
<td class="name">
<a href="#UOTGHS_HSTIER" title="Host Global Interrupt Enable Register" class="one_click_away">UOTGHS_HSTIER</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC41C">0x400AC41C</td>
<td class="description">Host Pipe Register</td>
<td class="name">
<a href="#UOTGHS_HSTPIP" title="Host Pipe Register" class="one_click_away">UOTGHS_HSTPIP</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC420">0x400AC420</td>
<td class="description">Host Frame Number Register</td>
<td class="name">
<a href="#UOTGHS_HSTFNUM" title="Host Frame Number Register" class="one_click_away">UOTGHS_HSTFNUM</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC424">0x400AC424</td>
<td class="description">Host Address 1 Register</td>
<td class="name">
<a href="#UOTGHS_HSTADDR1" title="Host Address 1 Register" class="one_click_away">UOTGHS_HSTADDR1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC428">0x400AC428</td>
<td class="description">Host Address 2 Register</td>
<td class="name">
<a href="#UOTGHS_HSTADDR2" title="Host Address 2 Register" class="one_click_away">UOTGHS_HSTADDR2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC42C">0x400AC42C</td>
<td class="description">Host Address 3 Register</td>
<td class="name">
<a href="#UOTGHS_HSTADDR3" title="Host Address 3 Register" class="one_click_away">UOTGHS_HSTADDR3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC500">0x400AC500</td>
<td class="description">Host Pipe Configuration Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_HSTPIPCFG" title="Host Pipe Configuration Register (n = 0)" class="one_click_away">UOTGHS_HSTPIPCFG[10]</a>
</td>
<td class="access">read-write</td>
<td class="address">0x0</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC530">0x400AC530</td>
<td class="description">Host Pipe Status Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_HSTPIPISR" title="Host Pipe Status Register (n = 0)" class="one_click_away">UOTGHS_HSTPIPISR[10]</a>
</td>
<td class="access">read-only</td>
<td class="address">0x0</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC560">0x400AC560</td>
<td class="description">Host Pipe Clear Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_HSTPIPICR" title="Host Pipe Clear Register (n = 0)" class="one_click_away">UOTGHS_HSTPIPICR[10]</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC590">0x400AC590</td>
<td class="description">Host Pipe Set Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_HSTPIPIFR" title="Host Pipe Set Register (n = 0)" class="one_click_away">UOTGHS_HSTPIPIFR[10]</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC5C0">0x400AC5C0</td>
<td class="description">Host Pipe Mask Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_HSTPIPIMR" title="Host Pipe Mask Register (n = 0)" class="one_click_away">UOTGHS_HSTPIPIMR[10]</a>
</td>
<td class="access">read-only</td>
<td class="address">0x0</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC5F0">0x400AC5F0</td>
<td class="description">Host Pipe Enable Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_HSTPIPIER" title="Host Pipe Enable Register (n = 0)" class="one_click_away">UOTGHS_HSTPIPIER[10]</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC620">0x400AC620</td>
<td class="description">Host Pipe Disable Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_HSTPIPIDR" title="Host Pipe Disable Register (n = 0)" class="one_click_away">UOTGHS_HSTPIPIDR[10]</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC650">0x400AC650</td>
<td class="description">Host Pipe IN Request Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_HSTPIPINRQ" title="Host Pipe IN Request Register (n = 0)" class="one_click_away">UOTGHS_HSTPIPINRQ[10]</a>
</td>
<td class="access">read-write</td>
<td class="address">0x0</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC680">0x400AC680</td>
<td class="description">Host Pipe Error Register (n = 0)</td>
<td class="name">
<a href="#UOTGHS_HSTPIPERR" title="Host Pipe Error Register (n = 0)" class="one_click_away">UOTGHS_HSTPIPERR[10]</a>
</td>
<td class="access">read-write</td>
<td class="address">0x0</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC710">0x400AC710</td>
<td class="description">Host DMA Channel Next Descriptor Address Register (n = 1)</td>
<td class="name">
<a href="#UOTGHS_HSTDMANXTDSC1" title="Host DMA Channel Next Descriptor Address Register (n = 1)" class="one_click_away">UOTGHS_HSTDMANXTDSC1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC714">0x400AC714</td>
<td class="description">Host DMA Channel Address Register (n = 1)</td>
<td class="name">
<a href="#UOTGHS_HSTDMAADDRESS1" title="Host DMA Channel Address Register (n = 1)" class="one_click_away">UOTGHS_HSTDMAADDRESS1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC718">0x400AC718</td>
<td class="description">Host DMA Channel Control Register (n = 1)</td>
<td class="name">
<a href="#UOTGHS_HSTDMACONTROL1" title="Host DMA Channel Control Register (n = 1)" class="one_click_away">UOTGHS_HSTDMACONTROL1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC71C">0x400AC71C</td>
<td class="description">Host DMA Channel Status Register (n = 1)</td>
<td class="name">
<a href="#UOTGHS_HSTDMASTATUS1" title="Host DMA Channel Status Register (n = 1)" class="one_click_away">UOTGHS_HSTDMASTATUS1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC720">0x400AC720</td>
<td class="description">Host DMA Channel Next Descriptor Address Register (n = 2)</td>
<td class="name">
<a href="#UOTGHS_HSTDMANXTDSC2" title="Host DMA Channel Next Descriptor Address Register (n = 2)" class="one_click_away">UOTGHS_HSTDMANXTDSC2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC724">0x400AC724</td>
<td class="description">Host DMA Channel Address Register (n = 2)</td>
<td class="name">
<a href="#UOTGHS_HSTDMAADDRESS2" title="Host DMA Channel Address Register (n = 2)" class="one_click_away">UOTGHS_HSTDMAADDRESS2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC728">0x400AC728</td>
<td class="description">Host DMA Channel Control Register (n = 2)</td>
<td class="name">
<a href="#UOTGHS_HSTDMACONTROL2" title="Host DMA Channel Control Register (n = 2)" class="one_click_away">UOTGHS_HSTDMACONTROL2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC72C">0x400AC72C</td>
<td class="description">Host DMA Channel Status Register (n = 2)</td>
<td class="name">
<a href="#UOTGHS_HSTDMASTATUS2" title="Host DMA Channel Status Register (n = 2)" class="one_click_away">UOTGHS_HSTDMASTATUS2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC730">0x400AC730</td>
<td class="description">Host DMA Channel Next Descriptor Address Register (n = 3)</td>
<td class="name">
<a href="#UOTGHS_HSTDMANXTDSC3" title="Host DMA Channel Next Descriptor Address Register (n = 3)" class="one_click_away">UOTGHS_HSTDMANXTDSC3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC734">0x400AC734</td>
<td class="description">Host DMA Channel Address Register (n = 3)</td>
<td class="name">
<a href="#UOTGHS_HSTDMAADDRESS3" title="Host DMA Channel Address Register (n = 3)" class="one_click_away">UOTGHS_HSTDMAADDRESS3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC738">0x400AC738</td>
<td class="description">Host DMA Channel Control Register (n = 3)</td>
<td class="name">
<a href="#UOTGHS_HSTDMACONTROL3" title="Host DMA Channel Control Register (n = 3)" class="one_click_away">UOTGHS_HSTDMACONTROL3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC73C">0x400AC73C</td>
<td class="description">Host DMA Channel Status Register (n = 3)</td>
<td class="name">
<a href="#UOTGHS_HSTDMASTATUS3" title="Host DMA Channel Status Register (n = 3)" class="one_click_away">UOTGHS_HSTDMASTATUS3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC740">0x400AC740</td>
<td class="description">Host DMA Channel Next Descriptor Address Register (n = 4)</td>
<td class="name">
<a href="#UOTGHS_HSTDMANXTDSC4" title="Host DMA Channel Next Descriptor Address Register (n = 4)" class="one_click_away">UOTGHS_HSTDMANXTDSC4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC744">0x400AC744</td>
<td class="description">Host DMA Channel Address Register (n = 4)</td>
<td class="name">
<a href="#UOTGHS_HSTDMAADDRESS4" title="Host DMA Channel Address Register (n = 4)" class="one_click_away">UOTGHS_HSTDMAADDRESS4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC748">0x400AC748</td>
<td class="description">Host DMA Channel Control Register (n = 4)</td>
<td class="name">
<a href="#UOTGHS_HSTDMACONTROL4" title="Host DMA Channel Control Register (n = 4)" class="one_click_away">UOTGHS_HSTDMACONTROL4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC74C">0x400AC74C</td>
<td class="description">Host DMA Channel Status Register (n = 4)</td>
<td class="name">
<a href="#UOTGHS_HSTDMASTATUS4" title="Host DMA Channel Status Register (n = 4)" class="one_click_away">UOTGHS_HSTDMASTATUS4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC750">0x400AC750</td>
<td class="description">Host DMA Channel Next Descriptor Address Register (n = 5)</td>
<td class="name">
<a href="#UOTGHS_HSTDMANXTDSC5" title="Host DMA Channel Next Descriptor Address Register (n = 5)" class="one_click_away">UOTGHS_HSTDMANXTDSC5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC754">0x400AC754</td>
<td class="description">Host DMA Channel Address Register (n = 5)</td>
<td class="name">
<a href="#UOTGHS_HSTDMAADDRESS5" title="Host DMA Channel Address Register (n = 5)" class="one_click_away">UOTGHS_HSTDMAADDRESS5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC758">0x400AC758</td>
<td class="description">Host DMA Channel Control Register (n = 5)</td>
<td class="name">
<a href="#UOTGHS_HSTDMACONTROL5" title="Host DMA Channel Control Register (n = 5)" class="one_click_away">UOTGHS_HSTDMACONTROL5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC75C">0x400AC75C</td>
<td class="description">Host DMA Channel Status Register (n = 5)</td>
<td class="name">
<a href="#UOTGHS_HSTDMASTATUS5" title="Host DMA Channel Status Register (n = 5)" class="one_click_away">UOTGHS_HSTDMASTATUS5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC760">0x400AC760</td>
<td class="description">Host DMA Channel Next Descriptor Address Register (n = 6)</td>
<td class="name">
<a href="#UOTGHS_HSTDMANXTDSC6" title="Host DMA Channel Next Descriptor Address Register (n = 6)" class="one_click_away">UOTGHS_HSTDMANXTDSC6</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC764">0x400AC764</td>
<td class="description">Host DMA Channel Address Register (n = 6)</td>
<td class="name">
<a href="#UOTGHS_HSTDMAADDRESS6" title="Host DMA Channel Address Register (n = 6)" class="one_click_away">UOTGHS_HSTDMAADDRESS6</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC768">0x400AC768</td>
<td class="description">Host DMA Channel Control Register (n = 6)</td>
<td class="name">
<a href="#UOTGHS_HSTDMACONTROL6" title="Host DMA Channel Control Register (n = 6)" class="one_click_away">UOTGHS_HSTDMACONTROL6</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC76C">0x400AC76C</td>
<td class="description">Host DMA Channel Status Register (n = 6)</td>
<td class="name">
<a href="#UOTGHS_HSTDMASTATUS6" title="Host DMA Channel Status Register (n = 6)" class="one_click_away">UOTGHS_HSTDMASTATUS6</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC770">0x400AC770</td>
<td class="description">Host DMA Channel Next Descriptor Address Register (n = 7)</td>
<td class="name">
<a href="#UOTGHS_HSTDMANXTDSC7" title="Host DMA Channel Next Descriptor Address Register (n = 7)" class="one_click_away">UOTGHS_HSTDMANXTDSC7</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC774">0x400AC774</td>
<td class="description">Host DMA Channel Address Register (n = 7)</td>
<td class="name">
<a href="#UOTGHS_HSTDMAADDRESS7" title="Host DMA Channel Address Register (n = 7)" class="one_click_away">UOTGHS_HSTDMAADDRESS7</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC778">0x400AC778</td>
<td class="description">Host DMA Channel Control Register (n = 7)</td>
<td class="name">
<a href="#UOTGHS_HSTDMACONTROL7" title="Host DMA Channel Control Register (n = 7)" class="one_click_away">UOTGHS_HSTDMACONTROL7</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC77C">0x400AC77C</td>
<td class="description">Host DMA Channel Status Register (n = 7)</td>
<td class="name">
<a href="#UOTGHS_HSTDMASTATUS7" title="Host DMA Channel Status Register (n = 7)" class="one_click_away">UOTGHS_HSTDMASTATUS7</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC800">0x400AC800</td>
<td class="description">General Control Register</td>
<td class="name">
<a href="#UOTGHS_CTRL" title="General Control Register" class="one_click_away">UOTGHS_CTRL</a>
</td>
<td class="access">read-write</td>
<td class="address">0x03004000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC804">0x400AC804</td>
<td class="description">General Status Register</td>
<td class="name">
<a href="#UOTGHS_SR" title="General Status Register" class="one_click_away">UOTGHS_SR</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000400</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC808">0x400AC808</td>
<td class="description">General Status Clear Register</td>
<td class="name">
<a href="#UOTGHS_SCR" title="General Status Clear Register" class="one_click_away">UOTGHS_SCR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400AC80C">0x400AC80C</td>
<td class="description">General Status Set Register</td>
<td class="name">
<a href="#UOTGHS_SFR" title="General Status Set Register" class="one_click_away">UOTGHS_SFR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400AC82C">0x400AC82C</td>
<td class="description">General Finite State Machine Register</td>
<td class="name">
<a href="#UOTGHS_FSM" title="General Finite State Machine Register" class="one_click_away">UOTGHS_FSM</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000009</td>
</tr>
</tbody>
</table>
<h3>Register Fields</h3>
<h4 id="UOTGHS_DEVCTRL">UOTGHS Device General Control Register</h4>
<p><strong>Name</strong>: UOTGHS_DEVCTRL</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC000</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVCTRL__OPMODE2" title="Specific Operational mode">OPMODE2</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVCTRL__TSTPCKT" title="Test packet mode">TSTPCKT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVCTRL__TSTK" title="Test mode K">TSTK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVCTRL__TSTJ" title="Test mode J">TSTJ</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVCTRL__LS" title="Low-Speed Mode Force">LS</a>
</td>
<td colspan="2">
<a href="#UOTGHS_DEVCTRL__SPDCONF" title="Mode Configuration">SPDCONF</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVCTRL__RMWKUP" title="Remote Wake-Up">RMWKUP</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVCTRL__DETACH" title="Detach">DETACH</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVCTRL__ADDEN" title="Address Enable">ADDEN</a>
</td>
<td colspan="7">
<a href="#UOTGHS_DEVCTRL__UADD" title="USB Address">UADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVCTRL__UADD"><strong>UADD</strong>: USB Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVCTRL__ADDEN"><strong>ADDEN</strong>: Address Enable</li>
<p>-</p>
<li id="UOTGHS_DEVCTRL__DETACH"><strong>DETACH</strong>: Detach</li>
<p>-</p>
<li id="UOTGHS_DEVCTRL__RMWKUP"><strong>RMWKUP</strong>: Remote Wake-Up</li>
<p>-</p>
<li id="UOTGHS_DEVCTRL__SPDCONF"><strong>SPDCONF</strong>: Mode Configuration<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">NORMAL</td><td class="description">The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable.</td></tr><tr class="even"><td class="value">0x1</td><td class="name">LOW_POWER</td><td class="description">For a better consumption, if high-speed is not needed.</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">HIGH_SPEED</td><td class="description">Forced high speed.</td></tr><tr class="even"><td class="value">0x3</td><td class="name">FORCED_FS</td><td class="description">The peripheral remains in full-speed mode whatever the host speed capability.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVCTRL__LS"><strong>LS</strong>: Low-Speed Mode Force<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The full-speed mode is active.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The low-speed mode is active.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVCTRL__TSTJ"><strong>TSTJ</strong>: Test mode J<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The UTMI transceiver is in normal operation mode.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The UTMI transceiver generates high-speed J state for test purpose.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVCTRL__TSTK"><strong>TSTK</strong>: Test mode K<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The UTMI transceiver is in normal operation mode.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The UTMI transceiver generates high-speed K state for test purpose.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVCTRL__TSTPCKT"><strong>TSTPCKT</strong>: Test packet mode<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The UTMI transceiver is in normal operation mode.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The UTMI transceiver generates test packets for test purpose.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVCTRL__OPMODE2"><strong>OPMODE2</strong>: Specific Operational mode<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The UTMI transceiver is in normal operation mode.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The UTMI transceiver is in the \xc7 disable bit stuffing and NRZI encoding\xc8 operational mode for test purpose.</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVISR">UOTGHS Device Global Interrupt Status Register</h4>
<p><strong>Name</strong>: UOTGHS_DEVISR</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400AC004</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__DMA_6" title="DMA Channel 6 Interrupt">DMA_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__DMA_5" title="DMA Channel 5 Interrupt">DMA_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__DMA_4" title="DMA Channel 4 Interrupt">DMA_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__DMA_3" title="DMA Channel 3 Interrupt">DMA_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__DMA_2" title="DMA Channel 2 Interrupt">DMA_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__DMA_1" title="DMA Channel 1 Interrupt">DMA_1</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__PEP_9" title="Endpoint 9 Interrupt">PEP_9</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__PEP_8" title="Endpoint 8 Interrupt">PEP_8</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__PEP_7" title="Endpoint 7 Interrupt">PEP_7</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__PEP_6" title="Endpoint 6 Interrupt">PEP_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__PEP_5" title="Endpoint 5 Interrupt">PEP_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__PEP_4" title="Endpoint 4 Interrupt">PEP_4</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVISR__PEP_3" title="Endpoint 3 Interrupt">PEP_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__PEP_2" title="Endpoint 2 Interrupt">PEP_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__PEP_1" title="Endpoint 1 Interrupt">PEP_1</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__PEP_0" title="Endpoint 0 Interrupt">PEP_0</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__UPRSM" title="Upstream Resume Interrupt">UPRSM</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__EORSM" title="End of Resume Interrupt">EORSM</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__WAKEUP" title="Wake-Up Interrupt">WAKEUP</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__EORST" title="End of Reset Interrupt">EORST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__SOF" title="Start of Frame Interrupt">SOF</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__MSOF" title="Micro Start of Frame Interrupt">MSOF</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVISR__SUSP" title="Suspend Interrupt">SUSP</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVISR__SUSP"><strong>SUSP</strong>: Suspend Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVISR__MSOF"><strong>MSOF</strong>: Micro Start of Frame Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__SOF"><strong>SOF</strong>: Start of Frame Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__EORST"><strong>EORST</strong>: End of Reset Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__WAKEUP"><strong>WAKEUP</strong>: Wake-Up Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__EORSM"><strong>EORSM</strong>: End of Resume Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__UPRSM"><strong>UPRSM</strong>: Upstream Resume Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__PEP_0"><strong>PEP_0</strong>: Endpoint 0 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__PEP_1"><strong>PEP_1</strong>: Endpoint 1 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__PEP_2"><strong>PEP_2</strong>: Endpoint 2 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__PEP_3"><strong>PEP_3</strong>: Endpoint 3 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__PEP_4"><strong>PEP_4</strong>: Endpoint 4 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__PEP_5"><strong>PEP_5</strong>: Endpoint 5 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__PEP_6"><strong>PEP_6</strong>: Endpoint 6 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__PEP_7"><strong>PEP_7</strong>: Endpoint 7 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__PEP_8"><strong>PEP_8</strong>: Endpoint 8 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__PEP_9"><strong>PEP_9</strong>: Endpoint 9 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__DMA_1"><strong>DMA_1</strong>: DMA Channel 1 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__DMA_2"><strong>DMA_2</strong>: DMA Channel 2 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__DMA_3"><strong>DMA_3</strong>: DMA Channel 3 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__DMA_4"><strong>DMA_4</strong>: DMA Channel 4 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__DMA_5"><strong>DMA_5</strong>: DMA Channel 5 Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVISR__DMA_6"><strong>DMA_6</strong>: DMA Channel 6 Interrupt</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVICR">UOTGHS Device Global Interrupt Clear Register</h4>
<p><strong>Name</strong>: UOTGHS_DEVICR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC008</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVICR__UPRSMC" title="Upstream Resume Interrupt Clear">UPRSMC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVICR__EORSMC" title="End of Resume Interrupt Clear">EORSMC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVICR__WAKEUPC" title="Wake-Up Interrupt Clear">WAKEUPC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVICR__EORSTC" title="End of Reset Interrupt Clear">EORSTC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVICR__SOFC" title="Start of Frame Interrupt Clear">SOFC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVICR__MSOFC" title="Micro Start of Frame Interrupt Clear">MSOFC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVICR__SUSPC" title="Suspend Interrupt Clear">SUSPC</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVICR__SUSPC"><strong>SUSPC</strong>: Suspend Interrupt Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVICR__MSOFC"><strong>MSOFC</strong>: Micro Start of Frame Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVICR__SOFC"><strong>SOFC</strong>: Start of Frame Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVICR__EORSTC"><strong>EORSTC</strong>: End of Reset Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVICR__WAKEUPC"><strong>WAKEUPC</strong>: Wake-Up Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVICR__EORSMC"><strong>EORSMC</strong>: End of Resume Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVICR__UPRSMC"><strong>UPRSMC</strong>: Upstream Resume Interrupt Clear</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVIFR">UOTGHS Device Global Interrupt Set Register</h4>
<p><strong>Name</strong>: UOTGHS_DEVIFR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC00C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVIFR__DMA_6" title="DMA Channel 6 Interrupt Set">DMA_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIFR__DMA_5" title="DMA Channel 5 Interrupt Set">DMA_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIFR__DMA_4" title="DMA Channel 4 Interrupt Set">DMA_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIFR__DMA_3" title="DMA Channel 3 Interrupt Set">DMA_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIFR__DMA_2" title="DMA Channel 2 Interrupt Set">DMA_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIFR__DMA_1" title="DMA Channel 1 Interrupt Set">DMA_1</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVIFR__UPRSMS" title="Upstream Resume Interrupt Set">UPRSMS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIFR__EORSMS" title="End of Resume Interrupt Set">EORSMS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIFR__WAKEUPS" title="Wake-Up Interrupt Set">WAKEUPS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIFR__EORSTS" title="End of Reset Interrupt Set">EORSTS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIFR__SOFS" title="Start of Frame Interrupt Set">SOFS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIFR__MSOFS" title="Micro Start of Frame Interrupt Set">MSOFS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIFR__SUSPS" title="Suspend Interrupt Set">SUSPS</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVIFR__SUSPS"><strong>SUSPS</strong>: Suspend Interrupt Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIFR__MSOFS"><strong>MSOFS</strong>: Micro Start of Frame Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVIFR__SOFS"><strong>SOFS</strong>: Start of Frame Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVIFR__EORSTS"><strong>EORSTS</strong>: End of Reset Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVIFR__WAKEUPS"><strong>WAKEUPS</strong>: Wake-Up Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVIFR__EORSMS"><strong>EORSMS</strong>: End of Resume Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVIFR__UPRSMS"><strong>UPRSMS</strong>: Upstream Resume Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVIFR__DMA_1"><strong>DMA_1</strong>: DMA Channel 1 Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVIFR__DMA_2"><strong>DMA_2</strong>: DMA Channel 2 Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVIFR__DMA_3"><strong>DMA_3</strong>: DMA Channel 3 Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVIFR__DMA_4"><strong>DMA_4</strong>: DMA Channel 4 Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVIFR__DMA_5"><strong>DMA_5</strong>: DMA Channel 5 Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVIFR__DMA_6"><strong>DMA_6</strong>: DMA Channel 6 Interrupt Set</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVIMR">UOTGHS Device Global Interrupt Mask Register</h4>
<p><strong>Name</strong>: UOTGHS_DEVIMR</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400AC010</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__DMA_6" title="DMA Channel 6 Interrupt Mask">DMA_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__DMA_5" title="DMA Channel 5 Interrupt Mask">DMA_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__DMA_4" title="DMA Channel 4 Interrupt Mask">DMA_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__DMA_3" title="DMA Channel 3 Interrupt Mask">DMA_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__DMA_2" title="DMA Channel 2 Interrupt Mask">DMA_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__DMA_1" title="DMA Channel 1 Interrupt Mask">DMA_1</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__PEP_9" title="Endpoint 9 Interrupt Mask">PEP_9</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__PEP_8" title="Endpoint 8 Interrupt Mask">PEP_8</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__PEP_7" title="Endpoint 7 Interrupt Mask">PEP_7</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__PEP_6" title="Endpoint 6 Interrupt Mask">PEP_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__PEP_5" title="Endpoint 5 Interrupt Mask">PEP_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__PEP_4" title="Endpoint 4 Interrupt Mask">PEP_4</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVIMR__PEP_3" title="Endpoint 3 Interrupt Mask">PEP_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__PEP_2" title="Endpoint 2 Interrupt Mask">PEP_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__PEP_1" title="Endpoint 1 Interrupt Mask">PEP_1</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__PEP_0" title="Endpoint 0 Interrupt Mask">PEP_0</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__UPRSME" title="Upstream Resume Interrupt Mask">UPRSME</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__EORSME" title="End of Resume Interrupt Mask">EORSME</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__WAKEUPE" title="Wake-Up Interrupt Mask">WAKEUPE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__EORSTE" title="End of Reset Interrupt Mask">EORSTE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__SOFE" title="Start of Frame Interrupt Mask">SOFE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__MSOFE" title="Micro Start of Frame Interrupt Mask">MSOFE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIMR__SUSPE" title="Suspend Interrupt Mask">SUSPE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVIMR__SUSPE"><strong>SUSPE</strong>: Suspend Interrupt Mask</li>
<p>-</p>
<li id="UOTGHS_DEVIMR__MSOFE"><strong>MSOFE</strong>: Micro Start of Frame Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__SOFE"><strong>SOFE</strong>: Start of Frame Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__EORSTE"><strong>EORSTE</strong>: End of Reset Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__WAKEUPE"><strong>WAKEUPE</strong>: Wake-Up Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__EORSME"><strong>EORSME</strong>: End of Resume Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__UPRSME"><strong>UPRSME</strong>: Upstream Resume Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__PEP_0"><strong>PEP_0</strong>: Endpoint 0 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__PEP_1"><strong>PEP_1</strong>: Endpoint 1 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__PEP_2"><strong>PEP_2</strong>: Endpoint 2 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__PEP_3"><strong>PEP_3</strong>: Endpoint 3 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__PEP_4"><strong>PEP_4</strong>: Endpoint 4 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__PEP_5"><strong>PEP_5</strong>: Endpoint 5 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__PEP_6"><strong>PEP_6</strong>: Endpoint 6 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__PEP_7"><strong>PEP_7</strong>: Endpoint 7 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__PEP_8"><strong>PEP_8</strong>: Endpoint 8 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__PEP_9"><strong>PEP_9</strong>: Endpoint 9 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__DMA_1"><strong>DMA_1</strong>: DMA Channel 1 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__DMA_2"><strong>DMA_2</strong>: DMA Channel 2 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__DMA_3"><strong>DMA_3</strong>: DMA Channel 3 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__DMA_4"><strong>DMA_4</strong>: DMA Channel 4 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__DMA_5"><strong>DMA_5</strong>: DMA Channel 5 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIMR__DMA_6"><strong>DMA_6</strong>: DMA Channel 6 Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The interrupt is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The interrupt is enabled.</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVIDR">UOTGHS Device Global Interrupt Disable Register</h4>
<p><strong>Name</strong>: UOTGHS_DEVIDR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC014</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__DMA_6" title="DMA Channel 6 Interrupt Disable">DMA_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__DMA_5" title="DMA Channel 5 Interrupt Disable">DMA_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__DMA_4" title="DMA Channel 4 Interrupt Disable">DMA_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__DMA_3" title="DMA Channel 3 Interrupt Disable">DMA_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__DMA_2" title="DMA Channel 2 Interrupt Disable">DMA_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__DMA_1" title="DMA Channel 1 Interrupt Disable">DMA_1</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__PEP_9" title="Endpoint 9 Interrupt Disable">PEP_9</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__PEP_8" title="Endpoint 8 Interrupt Disable">PEP_8</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__PEP_7" title="Endpoint 7 Interrupt Disable">PEP_7</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__PEP_6" title="Endpoint 6 Interrupt Disable">PEP_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__PEP_5" title="Endpoint 5 Interrupt Disable">PEP_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__PEP_4" title="Endpoint 4 Interrupt Disable">PEP_4</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVIDR__PEP_3" title="Endpoint 3 Interrupt Disable">PEP_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__PEP_2" title="Endpoint 2 Interrupt Disable">PEP_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__PEP_1" title="Endpoint 1 Interrupt Disable">PEP_1</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__PEP_0" title="Endpoint 0 Interrupt Disable">PEP_0</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__UPRSMEC" title="Upstream Resume Interrupt Disable">UPRSMEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__EORSMEC" title="End of Resume Interrupt Disable">EORSMEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__WAKEUPEC" title="Wake-Up Interrupt Disable">WAKEUPEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__EORSTEC" title="End of Reset Interrupt Disable">EORSTEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__SOFEC" title="Start of Frame Interrupt Disable">SOFEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__MSOFEC" title="Micro Start of Frame Interrupt Disable">MSOFEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIDR__SUSPEC" title="Suspend Interrupt Disable">SUSPEC</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVIDR__SUSPEC"><strong>SUSPEC</strong>: Suspend Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIDR__MSOFEC"><strong>MSOFEC</strong>: Micro Start of Frame Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__SOFEC"><strong>SOFEC</strong>: Start of Frame Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__EORSTEC"><strong>EORSTEC</strong>: End of Reset Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__WAKEUPEC"><strong>WAKEUPEC</strong>: Wake-Up Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__EORSMEC"><strong>EORSMEC</strong>: End of Resume Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__UPRSMEC"><strong>UPRSMEC</strong>: Upstream Resume Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__PEP_0"><strong>PEP_0</strong>: Endpoint 0 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__PEP_1"><strong>PEP_1</strong>: Endpoint 1 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__PEP_2"><strong>PEP_2</strong>: Endpoint 2 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__PEP_3"><strong>PEP_3</strong>: Endpoint 3 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__PEP_4"><strong>PEP_4</strong>: Endpoint 4 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__PEP_5"><strong>PEP_5</strong>: Endpoint 5 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__PEP_6"><strong>PEP_6</strong>: Endpoint 6 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__PEP_7"><strong>PEP_7</strong>: Endpoint 7 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__PEP_8"><strong>PEP_8</strong>: Endpoint 8 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__PEP_9"><strong>PEP_9</strong>: Endpoint 9 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__DMA_1"><strong>DMA_1</strong>: DMA Channel 1 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__DMA_2"><strong>DMA_2</strong>: DMA Channel 2 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__DMA_3"><strong>DMA_3</strong>: DMA Channel 3 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__DMA_4"><strong>DMA_4</strong>: DMA Channel 4 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__DMA_5"><strong>DMA_5</strong>: DMA Channel 5 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_DEVIDR__DMA_6"><strong>DMA_6</strong>: DMA Channel 6 Interrupt Disable</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVIER">UOTGHS Device Global Interrupt Enable Register</h4>
<p><strong>Name</strong>: UOTGHS_DEVIER</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC018</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__DMA_6" title="DMA Channel 6 Interrupt Enable">DMA_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__DMA_5" title="DMA Channel 5 Interrupt Enable">DMA_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__DMA_4" title="DMA Channel 4 Interrupt Enable">DMA_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__DMA_3" title="DMA Channel 3 Interrupt Enable">DMA_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__DMA_2" title="DMA Channel 2 Interrupt Enable">DMA_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__DMA_1" title="DMA Channel 1 Interrupt Enable">DMA_1</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__PEP_9" title="Endpoint 9 Interrupt Enable">PEP_9</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__PEP_8" title="Endpoint 8 Interrupt Enable">PEP_8</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__PEP_7" title="Endpoint 7 Interrupt Enable">PEP_7</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__PEP_6" title="Endpoint 6 Interrupt Enable">PEP_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__PEP_5" title="Endpoint 5 Interrupt Enable">PEP_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__PEP_4" title="Endpoint 4 Interrupt Enable">PEP_4</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVIER__PEP_3" title="Endpoint 3 Interrupt Enable">PEP_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__PEP_2" title="Endpoint 2 Interrupt Enable">PEP_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__PEP_1" title="Endpoint 1 Interrupt Enable">PEP_1</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__PEP_0" title="Endpoint 0 Interrupt Enable">PEP_0</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__UPRSMES" title="Upstream Resume Interrupt Enable">UPRSMES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__EORSMES" title="End of Resume Interrupt Enable">EORSMES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__WAKEUPES" title="Wake-Up Interrupt Enable">WAKEUPES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__EORSTES" title="End of Reset Interrupt Enable">EORSTES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__SOFES" title="Start of Frame Interrupt Enable">SOFES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__MSOFES" title="Micro Start of Frame Interrupt Enable">MSOFES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVIER__SUSPES" title="Suspend Interrupt Enable">SUSPES</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVIER__SUSPES"><strong>SUSPES</strong>: Suspend Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVIER__MSOFES"><strong>MSOFES</strong>: Micro Start of Frame Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__SOFES"><strong>SOFES</strong>: Start of Frame Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__EORSTES"><strong>EORSTES</strong>: End of Reset Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__WAKEUPES"><strong>WAKEUPES</strong>: Wake-Up Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__EORSMES"><strong>EORSMES</strong>: End of Resume Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__UPRSMES"><strong>UPRSMES</strong>: Upstream Resume Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__PEP_0"><strong>PEP_0</strong>: Endpoint 0 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__PEP_1"><strong>PEP_1</strong>: Endpoint 1 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__PEP_2"><strong>PEP_2</strong>: Endpoint 2 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__PEP_3"><strong>PEP_3</strong>: Endpoint 3 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__PEP_4"><strong>PEP_4</strong>: Endpoint 4 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__PEP_5"><strong>PEP_5</strong>: Endpoint 5 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__PEP_6"><strong>PEP_6</strong>: Endpoint 6 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__PEP_7"><strong>PEP_7</strong>: Endpoint 7 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__PEP_8"><strong>PEP_8</strong>: Endpoint 8 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__PEP_9"><strong>PEP_9</strong>: Endpoint 9 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__DMA_1"><strong>DMA_1</strong>: DMA Channel 1 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__DMA_2"><strong>DMA_2</strong>: DMA Channel 2 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__DMA_3"><strong>DMA_3</strong>: DMA Channel 3 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__DMA_4"><strong>DMA_4</strong>: DMA Channel 4 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__DMA_5"><strong>DMA_5</strong>: DMA Channel 5 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVIER__DMA_6"><strong>DMA_6</strong>: DMA Channel 6 Interrupt Enable</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVEPT">UOTGHS Device Endpoint Register</h4>
<p><strong>Name</strong>: UOTGHS_DEVEPT</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC01C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPRST8" title="Endpoint 8 Reset">EPRST8</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPRST7" title="Endpoint 7 Reset">EPRST7</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPRST6" title="Endpoint 6 Reset">EPRST6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPRST5" title="Endpoint 5 Reset">EPRST5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPRST4" title="Endpoint 4 Reset">EPRST4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPRST3" title="Endpoint 3 Reset">EPRST3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPRST2" title="Endpoint 2 Reset">EPRST2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPRST1" title="Endpoint 1 Reset">EPRST1</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPRST0" title="Endpoint 0 Reset">EPRST0</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPEN8" title="Endpoint 8 Enable">EPEN8</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPEN7" title="Endpoint 7 Enable">EPEN7</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPEN6" title="Endpoint 6 Enable">EPEN6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPEN5" title="Endpoint 5 Enable">EPEN5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPEN4" title="Endpoint 4 Enable">EPEN4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPEN3" title="Endpoint 3 Enable">EPEN3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPEN2" title="Endpoint 2 Enable">EPEN2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPEN1" title="Endpoint 1 Enable">EPEN1</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPT__EPEN0" title="Endpoint 0 Enable">EPEN0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVEPT__EPEN0"><strong>EPEN0</strong>: Endpoint 0 Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPEN1"><strong>EPEN1</strong>: Endpoint 1 Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPEN2"><strong>EPEN2</strong>: Endpoint 2 Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPEN3"><strong>EPEN3</strong>: Endpoint 3 Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPEN4"><strong>EPEN4</strong>: Endpoint 4 Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPEN5"><strong>EPEN5</strong>: Endpoint 5 Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPEN6"><strong>EPEN6</strong>: Endpoint 6 Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPEN7"><strong>EPEN7</strong>: Endpoint 7 Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPEN8"><strong>EPEN8</strong>: Endpoint 8 Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPRST0"><strong>EPRST0</strong>: Endpoint 0 Reset</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPRST1"><strong>EPRST1</strong>: Endpoint 1 Reset</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPRST2"><strong>EPRST2</strong>: Endpoint 2 Reset</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPRST3"><strong>EPRST3</strong>: Endpoint 3 Reset</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPRST4"><strong>EPRST4</strong>: Endpoint 4 Reset</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPRST5"><strong>EPRST5</strong>: Endpoint 5 Reset</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPRST6"><strong>EPRST6</strong>: Endpoint 6 Reset</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPRST7"><strong>EPRST7</strong>: Endpoint 7 Reset</li>
<p>-</p>
<li id="UOTGHS_DEVEPT__EPRST8"><strong>EPRST8</strong>: Endpoint 8 Reset</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVFNUM">UOTGHS Device Frame Number Register</h4>
<p><strong>Name</strong>: UOTGHS_DEVFNUM</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400AC020</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVFNUM__FNCERR" title="Frame Number CRC Error">FNCERR</a>
</td>
<td>-</td>
<td colspan="6">
<a href="#UOTGHS_DEVFNUM__FNUM" title="Frame Number">FNUM</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="5">
<a href="#UOTGHS_DEVFNUM__FNUM" title="Frame Number">FNUM</a>
</td>
<td colspan="3">
<a href="#UOTGHS_DEVFNUM__MFNUM" title="Micro Frame Number">MFNUM</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVFNUM__MFNUM"><strong>MFNUM</strong>: Micro Frame Number<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVFNUM__FNUM"><strong>FNUM</strong>: Frame Number</li>
<p>-</p>
<li id="UOTGHS_DEVFNUM__FNCERR"><strong>FNCERR</strong>: Frame Number CRC Error</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVEPTCFG">UOTGHS Device Endpoint Configuration Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_DEVEPTCFG[0:9]</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC100</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="2">
<a href="#UOTGHS_DEVEPTCFG__NBTRANS" title="Number of transaction per microframe for isochronous endpoint">NBTRANS</a>
</td>
<td colspan="2">
<a href="#UOTGHS_DEVEPTCFG__EPTYPE" title="Endpoint Type">EPTYPE</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTCFG__AUTOSW" title="Automatic Switch">AUTOSW</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTCFG__EPDIR" title="Endpoint Direction">EPDIR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="3">
<a href="#UOTGHS_DEVEPTCFG__EPSIZE" title="Endpoint Size">EPSIZE</a>
</td>
<td colspan="2">
<a href="#UOTGHS_DEVEPTCFG__EPBK" title="Endpoint Banks">EPBK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTCFG__ALLOC" title="Endpoint Memory Allocate">ALLOC</a>
</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVEPTCFG__ALLOC"><strong>ALLOC</strong>: Endpoint Memory Allocate<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTCFG__EPBK"><strong>EPBK</strong>: Endpoint Banks<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">1_BANK</td><td class="description">Single-bank endpoint</td></tr><tr class="even"><td class="value">0x1</td><td class="name">2_BANK</td><td class="description">Double-bank endpoint</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">3_BANK</td><td class="description">Triple-bank endpoint</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTCFG__EPSIZE"><strong>EPSIZE</strong>: Endpoint Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">8_BYTE</td><td class="description">8 bytes</td></tr><tr class="even"><td class="value">0x1</td><td class="name">16_BYTE</td><td class="description">16 bytes</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">32_BYTE</td><td class="description">32 bytes</td></tr><tr class="even"><td class="value">0x3</td><td class="name">64_BYTE</td><td class="description">64 bytes</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">128_BYTE</td><td class="description">128 bytes</td></tr><tr class="even"><td class="value">0x5</td><td class="name">256_BYTE</td><td class="description">256 bytes</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">512_BYTE</td><td class="description">512 bytes</td></tr><tr class="even"><td class="value">0x7</td><td class="name">1024_BYTE</td><td class="description">1024 bytes</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTCFG__EPDIR"><strong>EPDIR</strong>: Endpoint Direction<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">OUT</td><td class="description">The endpoint direction is OUT.</td></tr><tr class="even"><td class="value">1</td><td class="name">IN</td><td class="description">The endpoint direction is IN (nor for control endpoints).</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTCFG__AUTOSW"><strong>AUTOSW</strong>: Automatic Switch<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The automatic bank switching is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The automatic bank switching is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTCFG__EPTYPE"><strong>EPTYPE</strong>: Endpoint Type<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CTRL</td><td class="description">Control</td></tr><tr class="even"><td class="value">0x1</td><td class="name">ISO</td><td class="description">Isochronous</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">BLK</td><td class="description">Bulk</td></tr><tr class="even"><td class="value">0x3</td><td class="name">INTRPT</td><td class="description">Interrupt</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTCFG__NBTRANS"><strong>NBTRANS</strong>: Number of transaction per microframe for isochronous endpoint<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">0_TRANS</td><td class="description">reserved to endpoint that does not have the high-bandwidth isochronous capability.</td></tr><tr class="even"><td class="value">0x1</td><td class="name">1_TRANS</td><td class="description">default value: one transaction per micro-frame.</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">2_TRANS</td><td class="description">2 transactions per micro-frame. This endpoint should be configured as double-bank.</td></tr><tr class="even"><td class="value">0x3</td><td class="name">3_TRANS</td><td class="description">3 transactions per micro-frame. This endpoint should be configured as triple-bank.</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVEPTISR">UOTGHS Device Endpoint Status Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_DEVEPTISR[0:9]</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400AC130</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="7">
<a href="#UOTGHS_DEVEPTISR__BYCT" title="Byte Count">BYCT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#UOTGHS_DEVEPTISR__BYCT" title="Byte Count">BYCT</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTISR__CFGOK" title="Configuration OK Status">CFGOK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTISR__CTRLDIR" title="Control Direction">CTRLDIR</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTISR__RWALL" title="Read-write Allowed">RWALL</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UOTGHS_DEVEPTISR__CURRBK" title="Current Bank">CURRBK</a>
</td>
<td colspan="2">
<a href="#UOTGHS_DEVEPTISR__NBUSYBK" title="Number of Busy Banks">NBUSYBK</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTISR__ERRORTRANS" title="High-bandwidth isochronous OUT endpoint transaction error Interrupt">ERRORTRANS</a>
</td>
<td colspan="2">
<a href="#UOTGHS_DEVEPTISR__DTSEQ" title="Data Toggle Sequence">DTSEQ</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVEPTISR__SHORTPACKET" title="Short Packet Interrupt">SHORTPACKET</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTISR__STALLEDI" title="STALLed Interrupt">STALLEDI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTISR__OVERFI" title="Overflow Interrupt">OVERFI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTISR__NAKINI" title="NAKed IN Interrupt">NAKINI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTISR__NAKOUTI" title="NAKed OUT Interrupt">NAKOUTI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTISR__RXSTPI" title="Received SETUP Interrupt">RXSTPI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTISR__RXOUTI" title="Received OUT Data Interrupt">RXOUTI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTISR__TXINI" title="Transmitted IN Data Interrupt">TXINI</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVEPTISR__TXINI"><strong>TXINI</strong>: Transmitted IN Data Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTISR__RXOUTI"><strong>RXOUTI</strong>: Received OUT Data Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__RXSTPI"><strong>RXSTPI</strong>: Received SETUP Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__UNDERFI"><strong>UNDERFI</strong>: Underflow Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__NAKOUTI"><strong>NAKOUTI</strong>: NAKed OUT Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__HBISOINERRI"><strong>HBISOINERRI</strong>: High bandwidth isochronous IN Underflow Error Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__NAKINI"><strong>NAKINI</strong>: NAKed IN Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__HBISOFLUSHI"><strong>HBISOFLUSHI</strong>: High Bandwidth Isochronous IN Flush Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__OVERFI"><strong>OVERFI</strong>: Overflow Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__STALLEDI"><strong>STALLEDI</strong>: STALLed Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__CRCERRI"><strong>CRCERRI</strong>: CRC Error Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__SHORTPACKET"><strong>SHORTPACKET</strong>: Short Packet Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__DTSEQ"><strong>DTSEQ</strong>: Data Toggle Sequence<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">DATA0</td><td class="description">Data0 toggle sequence</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DATA1</td><td class="description">Data1 toggle sequence</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">DATA2</td><td class="description">Data2 toggle sequence (for high-bandwidth isochronous endpoint)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">MDATA</td><td class="description">MData toggle sequence (for high-bandwidth isochronous endpoint)</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTISR__ERRORTRANS"><strong>ERRORTRANS</strong>: High-bandwidth isochronous OUT endpoint transaction error Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__NBUSYBK"><strong>NBUSYBK</strong>: Number of Busy Banks<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">0_BUSY</td><td class="description">0 busy bank (all banks free)</td></tr><tr class="even"><td class="value">0x1</td><td class="name">1_BUSY</td><td class="description">1 busy bank</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">2_BUSY</td><td class="description">2 busy banks</td></tr><tr class="even"><td class="value">0x3</td><td class="name">3_BUSY</td><td class="description">3 busy banks</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTISR__CURRBK"><strong>CURRBK</strong>: Current Bank<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BANK0</td><td class="description">Current bank is bank0</td></tr><tr class="even"><td class="value">0x1</td><td class="name">BANK1</td><td class="description">Current bank is bank1</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">BANK2</td><td class="description">Current bank is bank2</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTISR__RWALL"><strong>RWALL</strong>: Read-write Allowed</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__CTRLDIR"><strong>CTRLDIR</strong>: Control Direction</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__CFGOK"><strong>CFGOK</strong>: Configuration OK Status</li>
<p>-</p>
<li id="UOTGHS_DEVEPTISR__BYCT"><strong>BYCT</strong>: Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVEPTICR">UOTGHS Device Endpoint Clear Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_DEVEPTICR[0:9]</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC160</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVEPTICR__SHORTPACKETC" title="Short Packet Interrupt Clear">SHORTPACKETC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTICR__STALLEDIC" title="STALLed Interrupt Clear">STALLEDIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTICR__OVERFIC" title="Overflow Interrupt Clear">OVERFIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTICR__NAKINIC" title="NAKed IN Interrupt Clear">NAKINIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTICR__NAKOUTIC" title="NAKed OUT Interrupt Clear">NAKOUTIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTICR__RXSTPIC" title="Received SETUP Interrupt Clear">RXSTPIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTICR__RXOUTIC" title="Received OUT Data Interrupt Clear">RXOUTIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTICR__TXINIC" title="Transmitted IN Data Interrupt Clear">TXINIC</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVEPTICR__TXINIC"><strong>TXINIC</strong>: Transmitted IN Data Interrupt Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTICR__RXOUTIC"><strong>RXOUTIC</strong>: Received OUT Data Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTICR__RXSTPIC"><strong>RXSTPIC</strong>: Received SETUP Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTICR__UNDERFIC"><strong>UNDERFIC</strong>: Underflow Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTICR__NAKOUTIC"><strong>NAKOUTIC</strong>: NAKed OUT Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTICR__HBISOINERRIC"><strong>HBISOINERRIC</strong>: High bandwidth isochronous IN Underflow Error Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTICR__NAKINIC"><strong>NAKINIC</strong>: NAKed IN Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTICR__HBISOFLUSHIC"><strong>HBISOFLUSHIC</strong>: High Bandwidth Isochronous IN Flush Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTICR__OVERFIC"><strong>OVERFIC</strong>: Overflow Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTICR__STALLEDIC"><strong>STALLEDIC</strong>: STALLed Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTICR__CRCERRIC"><strong>CRCERRIC</strong>: CRC Error Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTICR__SHORTPACKETC"><strong>SHORTPACKETC</strong>: Short Packet Interrupt Clear</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVEPTIFR">UOTGHS Device Endpoint Set Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_DEVEPTIFR[0:9]</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC190</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIFR__NBUSYBKS" title="Number of Busy Banks Interrupt Set">NBUSYBKS</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVEPTIFR__SHORTPACKETS" title="Short Packet Interrupt Set">SHORTPACKETS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIFR__STALLEDIS" title="STALLed Interrupt Set">STALLEDIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIFR__OVERFIS" title="Overflow Interrupt Set">OVERFIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIFR__NAKINIS" title="NAKed IN Interrupt Set">NAKINIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIFR__NAKOUTIS" title="NAKed OUT Interrupt Set">NAKOUTIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIFR__RXSTPIS" title="Received SETUP Interrupt Set">RXSTPIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIFR__RXOUTIS" title="Received OUT Data Interrupt Set">RXOUTIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIFR__TXINIS" title="Transmitted IN Data Interrupt Set">TXINIS</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVEPTIFR__TXINIS"><strong>TXINIS</strong>: Transmitted IN Data Interrupt Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTIFR__RXOUTIS"><strong>RXOUTIS</strong>: Received OUT Data Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIFR__RXSTPIS"><strong>RXSTPIS</strong>: Received SETUP Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIFR__UNDERFIS"><strong>UNDERFIS</strong>: Underflow Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIFR__NAKOUTIS"><strong>NAKOUTIS</strong>: NAKed OUT Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIFR__HBISOINERRIS"><strong>HBISOINERRIS</strong>: High bandwidth isochronous IN Underflow Error Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIFR__NAKINIS"><strong>NAKINIS</strong>: NAKed IN Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIFR__HBISOFLUSHIS"><strong>HBISOFLUSHIS</strong>: High Bandwidth Isochronous IN Flush Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIFR__OVERFIS"><strong>OVERFIS</strong>: Overflow Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIFR__STALLEDIS"><strong>STALLEDIS</strong>: STALLed Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIFR__CRCERRIS"><strong>CRCERRIS</strong>: CRC Error Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIFR__SHORTPACKETS"><strong>SHORTPACKETS</strong>: Short Packet Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIFR__NBUSYBKS"><strong>NBUSYBKS</strong>: Number of Busy Banks Interrupt Set</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVEPTIMR">UOTGHS Device Endpoint Mask Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_DEVEPTIMR[0:9]</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400AC1C0</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__STALLRQ" title="STALL Request">STALLRQ</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__RSTDT" title="Reset Data Toggle">RSTDT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__NYETDIS" title="NYET Token Disable">NYETDIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__EPDISHDMA" title="Endpoint Interrupts Disable HDMA Request">EPDISHDMA</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__FIFOCON" title="FIFO Control">FIFOCON</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__KILLBK" title="Kill IN Bank">KILLBK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__NBUSYBKE" title="Number of Busy Banks Interrupt">NBUSYBKE</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__ERRORTRANSE" title="Transaction Error Interrupt">ERRORTRANSE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__DATAXE" title="DataX Interrupt">DATAXE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__MDATAE" title="MData Interrupt">MDATAE</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__SHORTPACKETE" title="Short Packet Interrupt">SHORTPACKETE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__STALLEDE" title="STALLed Interrupt">STALLEDE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__OVERFE" title="Overflow Interrupt">OVERFE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__NAKINE" title="NAKed IN Interrupt">NAKINE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__NAKOUTE" title="NAKed OUT Interrupt">NAKOUTE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__RXSTPE" title="Received SETUP Interrupt">RXSTPE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__RXOUTE" title="Received OUT Data Interrupt">RXOUTE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIMR__TXINE" title="Transmitted IN Data Interrupt">TXINE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVEPTIMR__TXINE"><strong>TXINE</strong>: Transmitted IN Data Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTIMR__RXOUTE"><strong>RXOUTE</strong>: Received OUT Data Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__RXSTPE"><strong>RXSTPE</strong>: Received SETUP Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__UNDERFE"><strong>UNDERFE</strong>: Underflow Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__NAKOUTE"><strong>NAKOUTE</strong>: NAKed OUT Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__HBISOINERRE"><strong>HBISOINERRE</strong>: High Bandwidth Isochronous IN Error Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__NAKINE"><strong>NAKINE</strong>: NAKed IN Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__HBISOFLUSHE"><strong>HBISOFLUSHE</strong>: High Bandwidth Isochronous IN Flush Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__OVERFE"><strong>OVERFE</strong>: Overflow Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__STALLEDE"><strong>STALLEDE</strong>: STALLed Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__CRCERRE"><strong>CRCERRE</strong>: CRC Error Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__SHORTPACKETE"><strong>SHORTPACKETE</strong>: Short Packet Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__MDATAE"><strong>MDATAE</strong>: MData Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__DATAXE"><strong>DATAXE</strong>: DataX Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__ERRORTRANSE"><strong>ERRORTRANSE</strong>: Transaction Error Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__NBUSYBKE"><strong>NBUSYBKE</strong>: Number of Busy Banks Interrupt</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__KILLBK"><strong>KILLBK</strong>: Kill IN Bank</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__FIFOCON"><strong>FIFOCON</strong>: FIFO Control</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__EPDISHDMA"><strong>EPDISHDMA</strong>: Endpoint Interrupts Disable HDMA Request</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__NYETDIS"><strong>NYETDIS</strong>: NYET Token Disable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__RSTDT"><strong>RSTDT</strong>: Reset Data Toggle</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIMR__STALLRQ"><strong>STALLRQ</strong>: STALL Request</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVEPTIER">UOTGHS Device Endpoint Enable Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_DEVEPTIER[0:9]</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC1F0</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__STALLRQS" title="STALL Request Enable">STALLRQS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__RSTDTS" title="Reset Data Toggle Enable">RSTDTS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__NYETDISS" title="NYET Token Disable Enable">NYETDISS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__EPDISHDMAS" title="Endpoint Interrupts Disable HDMA Request Enable">EPDISHDMAS</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__KILLBKS" title="Kill IN Bank">KILLBKS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__NBUSYBKES" title="Number of Busy Banks Interrupt Enable">NBUSYBKES</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__ERRORTRANSES" title="Transaction Error Interrupt Enable">ERRORTRANSES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__DATAXES" title="DataX Interrupt Enable">DATAXES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__MDATAES" title="MData Interrupt Enable">MDATAES</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__SHORTPACKETES" title="Short Packet Interrupt Enable">SHORTPACKETES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__STALLEDES" title="STALLed Interrupt Enable">STALLEDES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__OVERFES" title="Overflow Interrupt Enable">OVERFES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__NAKINES" title="NAKed IN Interrupt Enable">NAKINES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__NAKOUTES" title="NAKed OUT Interrupt Enable">NAKOUTES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__RXSTPES" title="Received SETUP Interrupt Enable">RXSTPES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__RXOUTES" title="Received OUT Data Interrupt Enable">RXOUTES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIER__TXINES" title="Transmitted IN Data Interrupt Enable">TXINES</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVEPTIER__TXINES"><strong>TXINES</strong>: Transmitted IN Data Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTIER__RXOUTES"><strong>RXOUTES</strong>: Received OUT Data Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__RXSTPES"><strong>RXSTPES</strong>: Received SETUP Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__UNDERFES"><strong>UNDERFES</strong>: Underflow Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__NAKOUTES"><strong>NAKOUTES</strong>: NAKed OUT Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__HBISOINERRES"><strong>HBISOINERRES</strong>: High Bandwidth Isochronous IN Error Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__NAKINES"><strong>NAKINES</strong>: NAKed IN Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__HBISOFLUSHES"><strong>HBISOFLUSHES</strong>: High Bandwidth Isochronous IN Flush Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__OVERFES"><strong>OVERFES</strong>: Overflow Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__STALLEDES"><strong>STALLEDES</strong>: STALLed Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__CRCERRES"><strong>CRCERRES</strong>: CRC Error Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__SHORTPACKETES"><strong>SHORTPACKETES</strong>: Short Packet Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__MDATAES"><strong>MDATAES</strong>: MData Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__DATAXES"><strong>DATAXES</strong>: DataX Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__ERRORTRANSES"><strong>ERRORTRANSES</strong>: Transaction Error Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__NBUSYBKES"><strong>NBUSYBKES</strong>: Number of Busy Banks Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__KILLBKS"><strong>KILLBKS</strong>: Kill IN Bank</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__EPDISHDMAS"><strong>EPDISHDMAS</strong>: Endpoint Interrupts Disable HDMA Request Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__NYETDISS"><strong>NYETDISS</strong>: NYET Token Disable Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__RSTDTS"><strong>RSTDTS</strong>: Reset Data Toggle Enable</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIER__STALLRQS"><strong>STALLRQS</strong>: STALL Request Enable</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVEPTIDR">UOTGHS Device Endpoint Disable Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_DEVEPTIDR[0:9]</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC220</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__STALLRQC" title="STALL Request Clear">STALLRQC</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__NYETDISC" title="NYET Token Disable Clear">NYETDISC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__EPDISHDMAC" title="Endpoint Interrupts Disable HDMA Request Clear">EPDISHDMAC</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__FIFOCONC" title="FIFO Control Clear">FIFOCONC</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__NBUSYBKEC" title="Number of Busy Banks Interrupt Clear">NBUSYBKEC</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__ERRORTRANSEC" title="Transaction Error Interrupt Clear">ERRORTRANSEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__DATAXEC" title="DataX Interrupt Clear">DATAXEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__MDATEC" title="MData Interrupt Clear">MDATEC</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__SHORTPACKETEC" title="Shortpacket Interrupt Clear">SHORTPACKETEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__STALLEDEC" title="STALLed Interrupt Clear">STALLEDEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__OVERFEC" title="Overflow Interrupt Clear">OVERFEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__NAKINEC" title="NAKed IN Interrupt Clear">NAKINEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__NAKOUTEC" title="NAKed OUT Interrupt Clear">NAKOUTEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__RXSTPEC" title="Received SETUP Interrupt Clear">RXSTPEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__RXOUTEC" title="Received OUT Data Interrupt Clear">RXOUTEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVEPTIDR__TXINEC" title="Transmitted IN Interrupt Clear">TXINEC</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVEPTIDR__TXINEC"><strong>TXINEC</strong>: Transmitted IN Interrupt Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_DEVEPTIDR__RXOUTEC"><strong>RXOUTEC</strong>: Received OUT Data Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__RXSTPEC"><strong>RXSTPEC</strong>: Received SETUP Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__UNDERFEC"><strong>UNDERFEC</strong>: Underflow Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__NAKOUTEC"><strong>NAKOUTEC</strong>: NAKed OUT Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__HBISOINERREC"><strong>HBISOINERREC</strong>: High Bandwidth Isochronous IN Error Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__NAKINEC"><strong>NAKINEC</strong>: NAKed IN Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__HBISOFLUSHEC"><strong>HBISOFLUSHEC</strong>: High Bandwidth Isochronous IN Flush Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__OVERFEC"><strong>OVERFEC</strong>: Overflow Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__STALLEDEC"><strong>STALLEDEC</strong>: STALLed Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__CRCERREC"><strong>CRCERREC</strong>: CRC Error Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__SHORTPACKETEC"><strong>SHORTPACKETEC</strong>: Shortpacket Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__MDATEC"><strong>MDATEC</strong>: MData Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__DATAXEC"><strong>DATAXEC</strong>: DataX Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__ERRORTRANSEC"><strong>ERRORTRANSEC</strong>: Transaction Error Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__NBUSYBKEC"><strong>NBUSYBKEC</strong>: Number of Busy Banks Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__FIFOCONC"><strong>FIFOCONC</strong>: FIFO Control Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__EPDISHDMAC"><strong>EPDISHDMAC</strong>: Endpoint Interrupts Disable HDMA Request Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__NYETDISC"><strong>NYETDISC</strong>: NYET Token Disable Clear</li>
<p>-</p>
<li id="UOTGHS_DEVEPTIDR__STALLRQC"><strong>STALLRQC</strong>: STALL Request Clear</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVDMANXTDSC1">UOTGHS Device DMA Channel Next Descriptor Address Register (n = 1)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMANXTDSC1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC310</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC1__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC1__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC1__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC1__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMANXTDSC1__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMAADDRESS1">UOTGHS Device DMA Channel Address Register (n = 1)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMAADDRESS1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC314</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS1__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS1__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS1__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS1__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMAADDRESS1__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMACONTROL1">UOTGHS Device DMA Channel Control Register (n = 1)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMACONTROL1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC318</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL1__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL1__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL1__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL1__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL1__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL1__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL1__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL1__END_TR_EN" title="End of Transfer Enable Control">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL1__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL1__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMACONTROL1__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL1__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL1__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL1__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL1__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL1__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL1__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL1__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL1__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMASTATUS1">UOTGHS Device DMA Channel Status Register (n = 1)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMASTATUS1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC31C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS1__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS1__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS1__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS1__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS1__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS1__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS1__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMASTATUS1__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS1__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS1__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS1__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS1__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS1__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVDMANXTDSC2">UOTGHS Device DMA Channel Next Descriptor Address Register (n = 2)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMANXTDSC2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC320</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC2__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC2__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC2__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC2__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMANXTDSC2__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMAADDRESS2">UOTGHS Device DMA Channel Address Register (n = 2)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMAADDRESS2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC324</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS2__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS2__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS2__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS2__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMAADDRESS2__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMACONTROL2">UOTGHS Device DMA Channel Control Register (n = 2)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMACONTROL2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC328</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL2__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL2__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL2__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL2__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL2__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL2__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL2__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL2__END_TR_EN" title="End of Transfer Enable Control">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL2__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL2__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMACONTROL2__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL2__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL2__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL2__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL2__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL2__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL2__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL2__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL2__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMASTATUS2">UOTGHS Device DMA Channel Status Register (n = 2)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMASTATUS2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC32C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS2__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS2__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS2__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS2__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS2__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS2__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS2__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMASTATUS2__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS2__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS2__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS2__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS2__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS2__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVDMANXTDSC3">UOTGHS Device DMA Channel Next Descriptor Address Register (n = 3)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMANXTDSC3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC330</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC3__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC3__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC3__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC3__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMANXTDSC3__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMAADDRESS3">UOTGHS Device DMA Channel Address Register (n = 3)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMAADDRESS3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC334</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS3__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS3__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS3__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS3__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMAADDRESS3__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMACONTROL3">UOTGHS Device DMA Channel Control Register (n = 3)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMACONTROL3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC338</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL3__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL3__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL3__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL3__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL3__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL3__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL3__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL3__END_TR_EN" title="End of Transfer Enable Control">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL3__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL3__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMACONTROL3__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL3__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL3__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL3__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL3__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL3__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL3__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL3__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL3__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMASTATUS3">UOTGHS Device DMA Channel Status Register (n = 3)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMASTATUS3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC33C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS3__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS3__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS3__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS3__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS3__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS3__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS3__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMASTATUS3__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS3__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS3__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS3__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS3__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS3__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVDMANXTDSC4">UOTGHS Device DMA Channel Next Descriptor Address Register (n = 4)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMANXTDSC4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC340</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC4__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC4__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC4__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC4__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMANXTDSC4__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMAADDRESS4">UOTGHS Device DMA Channel Address Register (n = 4)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMAADDRESS4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC344</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS4__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS4__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS4__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS4__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMAADDRESS4__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMACONTROL4">UOTGHS Device DMA Channel Control Register (n = 4)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMACONTROL4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC348</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL4__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL4__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL4__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL4__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL4__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL4__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL4__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL4__END_TR_EN" title="End of Transfer Enable Control">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL4__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL4__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMACONTROL4__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL4__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL4__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL4__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL4__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL4__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL4__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL4__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL4__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMASTATUS4">UOTGHS Device DMA Channel Status Register (n = 4)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMASTATUS4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC34C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS4__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS4__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS4__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS4__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS4__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS4__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS4__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMASTATUS4__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS4__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS4__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS4__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS4__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS4__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVDMANXTDSC5">UOTGHS Device DMA Channel Next Descriptor Address Register (n = 5)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMANXTDSC5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC350</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC5__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC5__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC5__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC5__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMANXTDSC5__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMAADDRESS5">UOTGHS Device DMA Channel Address Register (n = 5)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMAADDRESS5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC354</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS5__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS5__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS5__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS5__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMAADDRESS5__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMACONTROL5">UOTGHS Device DMA Channel Control Register (n = 5)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMACONTROL5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC358</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL5__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL5__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL5__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL5__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL5__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL5__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL5__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL5__END_TR_EN" title="End of Transfer Enable Control">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL5__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL5__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMACONTROL5__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL5__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL5__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL5__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL5__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL5__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL5__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL5__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL5__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMASTATUS5">UOTGHS Device DMA Channel Status Register (n = 5)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMASTATUS5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC35C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS5__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS5__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS5__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS5__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS5__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS5__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS5__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMASTATUS5__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS5__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS5__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS5__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS5__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS5__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVDMANXTDSC6">UOTGHS Device DMA Channel Next Descriptor Address Register (n = 6)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMANXTDSC6</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC360</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC6__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC6__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC6__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC6__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMANXTDSC6__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMAADDRESS6">UOTGHS Device DMA Channel Address Register (n = 6)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMAADDRESS6</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC364</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS6__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS6__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS6__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS6__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMAADDRESS6__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMACONTROL6">UOTGHS Device DMA Channel Control Register (n = 6)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMACONTROL6</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC368</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL6__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL6__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL6__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL6__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL6__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL6__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL6__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL6__END_TR_EN" title="End of Transfer Enable Control">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL6__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL6__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMACONTROL6__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL6__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL6__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL6__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL6__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL6__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL6__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL6__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL6__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMASTATUS6">UOTGHS Device DMA Channel Status Register (n = 6)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMASTATUS6</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC36C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS6__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS6__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS6__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS6__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS6__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS6__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS6__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMASTATUS6__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS6__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS6__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS6__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS6__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS6__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_DEVDMANXTDSC7">UOTGHS Device DMA Channel Next Descriptor Address Register (n = 7)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMANXTDSC7</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC370</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC7__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC7__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC7__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMANXTDSC7__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMANXTDSC7__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMAADDRESS7">UOTGHS Device DMA Channel Address Register (n = 7)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMAADDRESS7</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC374</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS7__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS7__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS7__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMAADDRESS7__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMAADDRESS7__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMACONTROL7">UOTGHS Device DMA Channel Control Register (n = 7)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMACONTROL7</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC378</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL7__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMACONTROL7__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL7__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL7__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL7__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL7__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL7__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL7__END_TR_EN" title="End of Transfer Enable Control">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL7__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMACONTROL7__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMACONTROL7__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL7__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_DEVDMACONTROL7__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL7__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL7__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL7__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL7__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL7__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMACONTROL7__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_DEVDMASTATUS7">UOTGHS Device DMA Channel Status Register (n = 7)</h4>
<p><strong>Name</strong>: UOTGHS_DEVDMASTATUS7</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC37C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS7__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_DEVDMASTATUS7__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS7__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS7__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS7__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS7__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_DEVDMASTATUS7__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_DEVDMASTATUS7__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS7__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS7__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS7__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS7__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_DEVDMASTATUS7__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTCTRL">UOTGHS Host General Control Register</h4>
<p><strong>Name</strong>: UOTGHS_HSTCTRL</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC400</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#UOTGHS_HSTCTRL__SPDCONF" title="Mode Configuration">SPDCONF</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTCTRL__RESUME" title="Send USB Resume">RESUME</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTCTRL__RESET" title="Send USB Reset">RESET</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTCTRL__SOFE" title="Start of Frame Generation Enable">SOFE</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTCTRL__SOFE"><strong>SOFE</strong>: Start of Frame Generation Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTCTRL__RESET"><strong>RESET</strong>: Send USB Reset</li>
<p>-</p>
<li id="UOTGHS_HSTCTRL__RESUME"><strong>RESUME</strong>: Send USB Resume</li>
<p>-</p>
<li id="UOTGHS_HSTCTRL__SPDCONF"><strong>SPDCONF</strong>: Mode Configuration<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">NORMAL</td><td class="description">The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable.</td></tr><tr class="even"><td class="value">0x1</td><td class="name">LOW_POWER</td><td class="description">For a better consumption, if high-speed is not needed.</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">HIGH_SPEED</td><td class="description">Forced high speed.</td></tr><tr class="even"><td class="value">0x3</td><td class="name">FORCED_FS</td><td class="description">The host remains to full-speed mode whatever the peripheral speed capability.</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTISR">UOTGHS Host Global Interrupt Status Register</h4>
<p><strong>Name</strong>: UOTGHS_HSTISR</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400AC404</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__DMA_6" title="DMA Channel 6 Interrupt">DMA_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__DMA_5" title="DMA Channel 5 Interrupt">DMA_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__DMA_4" title="DMA Channel 4 Interrupt">DMA_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__DMA_3" title="DMA Channel 3 Interrupt">DMA_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__DMA_2" title="DMA Channel 2 Interrupt">DMA_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__DMA_1" title="DMA Channel 1 Interrupt">DMA_1</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__PEP_9" title="Pipe 9 Interrupt">PEP_9</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__PEP_8" title="Pipe 8 Interrupt">PEP_8</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTISR__PEP_7" title="Pipe 7 Interrupt">PEP_7</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__PEP_6" title="Pipe 6 Interrupt">PEP_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__PEP_5" title="Pipe 5 Interrupt">PEP_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__PEP_4" title="Pipe 4 Interrupt">PEP_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__PEP_3" title="Pipe 3 Interrupt">PEP_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__PEP_2" title="Pipe 2 Interrupt">PEP_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__PEP_1" title="Pipe 1 Interrupt">PEP_1</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__PEP_0" title="Pipe 0 Interrupt">PEP_0</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__HWUPI" title="Host Wake-Up Interrupt">HWUPI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__HSOFI" title="Host Start of Frame Interrupt">HSOFI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__RXRSMI" title="Upstream Resume Received Interrupt">RXRSMI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__RSMEDI" title="Downstream Resume Sent Interrupt">RSMEDI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__RSTI" title="USB Reset Sent Interrupt">RSTI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__DDISCI" title="Device Disconnection Interrupt">DDISCI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTISR__DCONNI" title="Device Connection Interrupt">DCONNI</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTISR__DCONNI"><strong>DCONNI</strong>: Device Connection Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTISR__DDISCI"><strong>DDISCI</strong>: Device Disconnection Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__RSTI"><strong>RSTI</strong>: USB Reset Sent Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__RSMEDI"><strong>RSMEDI</strong>: Downstream Resume Sent Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__RXRSMI"><strong>RXRSMI</strong>: Upstream Resume Received Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__HSOFI"><strong>HSOFI</strong>: Host Start of Frame Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__HWUPI"><strong>HWUPI</strong>: Host Wake-Up Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__PEP_0"><strong>PEP_0</strong>: Pipe 0 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__PEP_1"><strong>PEP_1</strong>: Pipe 1 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__PEP_2"><strong>PEP_2</strong>: Pipe 2 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__PEP_3"><strong>PEP_3</strong>: Pipe 3 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__PEP_4"><strong>PEP_4</strong>: Pipe 4 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__PEP_5"><strong>PEP_5</strong>: Pipe 5 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__PEP_6"><strong>PEP_6</strong>: Pipe 6 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__PEP_7"><strong>PEP_7</strong>: Pipe 7 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__PEP_8"><strong>PEP_8</strong>: Pipe 8 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__PEP_9"><strong>PEP_9</strong>: Pipe 9 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__DMA_1"><strong>DMA_1</strong>: DMA Channel 1 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__DMA_2"><strong>DMA_2</strong>: DMA Channel 2 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__DMA_3"><strong>DMA_3</strong>: DMA Channel 3 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__DMA_4"><strong>DMA_4</strong>: DMA Channel 4 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__DMA_5"><strong>DMA_5</strong>: DMA Channel 5 Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTISR__DMA_6"><strong>DMA_6</strong>: DMA Channel 6 Interrupt</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTICR">UOTGHS Host Global Interrupt Clear Register</h4>
<p><strong>Name</strong>: UOTGHS_HSTICR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC408</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTICR__HWUPIC" title="Host Wake-Up Interrupt Clear">HWUPIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTICR__HSOFIC" title="Host Start of Frame Interrupt Clear">HSOFIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTICR__RXRSMIC" title="Upstream Resume Received Interrupt Clear">RXRSMIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTICR__RSMEDIC" title="Downstream Resume Sent Interrupt Clear">RSMEDIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTICR__RSTIC" title="USB Reset Sent Interrupt Clear">RSTIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTICR__DDISCIC" title="Device Disconnection Interrupt Clear">DDISCIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTICR__DCONNIC" title="Device Connection Interrupt Clear">DCONNIC</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTICR__DCONNIC"><strong>DCONNIC</strong>: Device Connection Interrupt Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTICR__DDISCIC"><strong>DDISCIC</strong>: Device Disconnection Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_HSTICR__RSTIC"><strong>RSTIC</strong>: USB Reset Sent Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_HSTICR__RSMEDIC"><strong>RSMEDIC</strong>: Downstream Resume Sent Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_HSTICR__RXRSMIC"><strong>RXRSMIC</strong>: Upstream Resume Received Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_HSTICR__HSOFIC"><strong>HSOFIC</strong>: Host Start of Frame Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_HSTICR__HWUPIC"><strong>HWUPIC</strong>: Host Wake-Up Interrupt Clear</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTIFR">UOTGHS Host Global Interrupt Set Register</h4>
<p><strong>Name</strong>: UOTGHS_HSTIFR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC40C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTIFR__DMA_6" title="DMA Channel 6 Interrupt Set">DMA_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIFR__DMA_5" title="DMA Channel 5 Interrupt Set">DMA_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIFR__DMA_4" title="DMA Channel 4 Interrupt Set">DMA_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIFR__DMA_3" title="DMA Channel 3 Interrupt Set">DMA_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIFR__DMA_2" title="DMA Channel 2 Interrupt Set">DMA_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIFR__DMA_1" title="DMA Channel 1 Interrupt Set">DMA_1</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTIFR__HWUPIS" title="Host Wake-Up Interrupt Set">HWUPIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIFR__HSOFIS" title="Host Start of Frame Interrupt Set">HSOFIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIFR__RXRSMIS" title="Upstream Resume Received Interrupt Set">RXRSMIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIFR__RSMEDIS" title="Downstream Resume Sent Interrupt Set">RSMEDIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIFR__RSTIS" title="USB Reset Sent Interrupt Set">RSTIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIFR__DDISCIS" title="Device Disconnection Interrupt Set">DDISCIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIFR__DCONNIS" title="Device Connection Interrupt Set">DCONNIS</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTIFR__DCONNIS"><strong>DCONNIS</strong>: Device Connection Interrupt Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTIFR__DDISCIS"><strong>DDISCIS</strong>: Device Disconnection Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTIFR__RSTIS"><strong>RSTIS</strong>: USB Reset Sent Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTIFR__RSMEDIS"><strong>RSMEDIS</strong>: Downstream Resume Sent Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTIFR__RXRSMIS"><strong>RXRSMIS</strong>: Upstream Resume Received Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTIFR__HSOFIS"><strong>HSOFIS</strong>: Host Start of Frame Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTIFR__HWUPIS"><strong>HWUPIS</strong>: Host Wake-Up Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTIFR__DMA_1"><strong>DMA_1</strong>: DMA Channel 1 Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTIFR__DMA_2"><strong>DMA_2</strong>: DMA Channel 2 Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTIFR__DMA_3"><strong>DMA_3</strong>: DMA Channel 3 Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTIFR__DMA_4"><strong>DMA_4</strong>: DMA Channel 4 Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTIFR__DMA_5"><strong>DMA_5</strong>: DMA Channel 5 Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTIFR__DMA_6"><strong>DMA_6</strong>: DMA Channel 6 Interrupt Set</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTIMR">UOTGHS Host Global Interrupt Mask Register</h4>
<p><strong>Name</strong>: UOTGHS_HSTIMR</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400AC410</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__DMA_6" title="DMA Channel 6 Interrupt Enable">DMA_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__DMA_5" title="DMA Channel 5 Interrupt Enable">DMA_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__DMA_4" title="DMA Channel 4 Interrupt Enable">DMA_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__DMA_3" title="DMA Channel 3 Interrupt Enable">DMA_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__DMA_2" title="DMA Channel 2 Interrupt Enable">DMA_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__DMA_1" title="DMA Channel 1 Interrupt Enable">DMA_1</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__PEP_9" title="Pipe 9 Interrupt Enable">PEP_9</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__PEP_8" title="Pipe 8 Interrupt Enable">PEP_8</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTIMR__PEP_7" title="Pipe 7 Interrupt Enable">PEP_7</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__PEP_6" title="Pipe 6 Interrupt Enable">PEP_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__PEP_5" title="Pipe 5 Interrupt Enable">PEP_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__PEP_4" title="Pipe 4 Interrupt Enable">PEP_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__PEP_3" title="Pipe 3 Interrupt Enable">PEP_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__PEP_2" title="Pipe 2 Interrupt Enable">PEP_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__PEP_1" title="Pipe 1 Interrupt Enable">PEP_1</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__PEP_0" title="Pipe 0 Interrupt Enable">PEP_0</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__HWUPIE" title="Host Wake-Up Interrupt Enable">HWUPIE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__HSOFIE" title="Host Start of Frame Interrupt Enable">HSOFIE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__RXRSMIE" title="Upstream Resume Received Interrupt Enable">RXRSMIE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__RSMEDIE" title="Downstream Resume Sent Interrupt Enable">RSMEDIE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__RSTIE" title="USB Reset Sent Interrupt Enable">RSTIE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__DDISCIE" title="Device Disconnection Interrupt Enable">DDISCIE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIMR__DCONNIE" title="Device Connection Interrupt Enable">DCONNIE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTIMR__DCONNIE"><strong>DCONNIE</strong>: Device Connection Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTIMR__DDISCIE"><strong>DDISCIE</strong>: Device Disconnection Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__RSTIE"><strong>RSTIE</strong>: USB Reset Sent Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__RSMEDIE"><strong>RSMEDIE</strong>: Downstream Resume Sent Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__RXRSMIE"><strong>RXRSMIE</strong>: Upstream Resume Received Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__HSOFIE"><strong>HSOFIE</strong>: Host Start of Frame Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__HWUPIE"><strong>HWUPIE</strong>: Host Wake-Up Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__PEP_0"><strong>PEP_0</strong>: Pipe 0 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__PEP_1"><strong>PEP_1</strong>: Pipe 1 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__PEP_2"><strong>PEP_2</strong>: Pipe 2 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__PEP_3"><strong>PEP_3</strong>: Pipe 3 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__PEP_4"><strong>PEP_4</strong>: Pipe 4 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__PEP_5"><strong>PEP_5</strong>: Pipe 5 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__PEP_6"><strong>PEP_6</strong>: Pipe 6 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__PEP_7"><strong>PEP_7</strong>: Pipe 7 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__PEP_8"><strong>PEP_8</strong>: Pipe 8 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__PEP_9"><strong>PEP_9</strong>: Pipe 9 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__DMA_1"><strong>DMA_1</strong>: DMA Channel 1 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__DMA_2"><strong>DMA_2</strong>: DMA Channel 2 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__DMA_3"><strong>DMA_3</strong>: DMA Channel 3 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__DMA_4"><strong>DMA_4</strong>: DMA Channel 4 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__DMA_5"><strong>DMA_5</strong>: DMA Channel 5 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIMR__DMA_6"><strong>DMA_6</strong>: DMA Channel 6 Interrupt Enable</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTIDR">UOTGHS Host Global Interrupt Disable Register</h4>
<p><strong>Name</strong>: UOTGHS_HSTIDR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC414</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__DMA_6" title="DMA Channel 6 Interrupt Disable">DMA_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__DMA_5" title="DMA Channel 5 Interrupt Disable">DMA_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__DMA_4" title="DMA Channel 4 Interrupt Disable">DMA_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__DMA_3" title="DMA Channel 3 Interrupt Disable">DMA_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__DMA_2" title="DMA Channel 2 Interrupt Disable">DMA_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__DMA_1" title="DMA Channel 1 Interrupt Disable">DMA_1</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__PEP_9" title="Pipe 9 Interrupt Disable">PEP_9</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__PEP_8" title="Pipe 8 Interrupt Disable">PEP_8</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTIDR__PEP_7" title="Pipe 7 Interrupt Disable">PEP_7</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__PEP_6" title="Pipe 6 Interrupt Disable">PEP_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__PEP_5" title="Pipe 5 Interrupt Disable">PEP_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__PEP_4" title="Pipe 4 Interrupt Disable">PEP_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__PEP_3" title="Pipe 3 Interrupt Disable">PEP_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__PEP_2" title="Pipe 2 Interrupt Disable">PEP_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__PEP_1" title="Pipe 1 Interrupt Disable">PEP_1</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__PEP_0" title="Pipe 0 Interrupt Disable">PEP_0</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__HWUPIEC" title="Host Wake-Up Interrupt Disable">HWUPIEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__HSOFIEC" title="Host Start of Frame Interrupt Disable">HSOFIEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__RXRSMIEC" title="Upstream Resume Received Interrupt Disable">RXRSMIEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__RSMEDIEC" title="Downstream Resume Sent Interrupt Disable">RSMEDIEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__RSTIEC" title="USB Reset Sent Interrupt Disable">RSTIEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__DDISCIEC" title="Device Disconnection Interrupt Disable">DDISCIEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIDR__DCONNIEC" title="Device Connection Interrupt Disable">DCONNIEC</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTIDR__DCONNIEC"><strong>DCONNIEC</strong>: Device Connection Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTIDR__DDISCIEC"><strong>DDISCIEC</strong>: Device Disconnection Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__RSTIEC"><strong>RSTIEC</strong>: USB Reset Sent Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__RSMEDIEC"><strong>RSMEDIEC</strong>: Downstream Resume Sent Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__RXRSMIEC"><strong>RXRSMIEC</strong>: Upstream Resume Received Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__HSOFIEC"><strong>HSOFIEC</strong>: Host Start of Frame Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__HWUPIEC"><strong>HWUPIEC</strong>: Host Wake-Up Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__PEP_0"><strong>PEP_0</strong>: Pipe 0 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__PEP_1"><strong>PEP_1</strong>: Pipe 1 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__PEP_2"><strong>PEP_2</strong>: Pipe 2 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__PEP_3"><strong>PEP_3</strong>: Pipe 3 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__PEP_4"><strong>PEP_4</strong>: Pipe 4 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__PEP_5"><strong>PEP_5</strong>: Pipe 5 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__PEP_6"><strong>PEP_6</strong>: Pipe 6 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__PEP_7"><strong>PEP_7</strong>: Pipe 7 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__PEP_8"><strong>PEP_8</strong>: Pipe 8 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__PEP_9"><strong>PEP_9</strong>: Pipe 9 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__DMA_1"><strong>DMA_1</strong>: DMA Channel 1 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__DMA_2"><strong>DMA_2</strong>: DMA Channel 2 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__DMA_3"><strong>DMA_3</strong>: DMA Channel 3 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__DMA_4"><strong>DMA_4</strong>: DMA Channel 4 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__DMA_5"><strong>DMA_5</strong>: DMA Channel 5 Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTIDR__DMA_6"><strong>DMA_6</strong>: DMA Channel 6 Interrupt Disable</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTIER">UOTGHS Host Global Interrupt Enable Register</h4>
<p><strong>Name</strong>: UOTGHS_HSTIER</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC418</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__DMA_6" title="DMA Channel 6 Interrupt Enable">DMA_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__DMA_5" title="DMA Channel 5 Interrupt Enable">DMA_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__DMA_4" title="DMA Channel 4 Interrupt Enable">DMA_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__DMA_3" title="DMA Channel 3 Interrupt Enable">DMA_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__DMA_2" title="DMA Channel 2 Interrupt Enable">DMA_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__DMA_1" title="DMA Channel 1 Interrupt Enable">DMA_1</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__PEP_9" title="Pipe 9 Interrupt Enable">PEP_9</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__PEP_8" title="Pipe 8 Interrupt Enable">PEP_8</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTIER__PEP_7" title="Pipe 7 Interrupt Enable">PEP_7</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__PEP_6" title="Pipe 6 Interrupt Enable">PEP_6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__PEP_5" title="Pipe 5 Interrupt Enable">PEP_5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__PEP_4" title="Pipe 4 Interrupt Enable">PEP_4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__PEP_3" title="Pipe 3 Interrupt Enable">PEP_3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__PEP_2" title="Pipe 2 Interrupt Enable">PEP_2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__PEP_1" title="Pipe 1 Interrupt Enable">PEP_1</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__PEP_0" title="Pipe 0 Interrupt Enable">PEP_0</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__HWUPIES" title="Host Wake-Up Interrupt Enable">HWUPIES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__HSOFIES" title="Host Start of Frame Interrupt Enable">HSOFIES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__RXRSMIES" title="Upstream Resume Received Interrupt Enable">RXRSMIES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__RSMEDIES" title="Downstream Resume Sent Interrupt Enable">RSMEDIES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__RSTIES" title="USB Reset Sent Interrupt Enable">RSTIES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__DDISCIES" title="Device Disconnection Interrupt Enable">DDISCIES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTIER__DCONNIES" title="Device Connection Interrupt Enable">DCONNIES</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTIER__DCONNIES"><strong>DCONNIES</strong>: Device Connection Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTIER__DDISCIES"><strong>DDISCIES</strong>: Device Disconnection Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__RSTIES"><strong>RSTIES</strong>: USB Reset Sent Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__RSMEDIES"><strong>RSMEDIES</strong>: Downstream Resume Sent Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__RXRSMIES"><strong>RXRSMIES</strong>: Upstream Resume Received Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__HSOFIES"><strong>HSOFIES</strong>: Host Start of Frame Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__HWUPIES"><strong>HWUPIES</strong>: Host Wake-Up Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__PEP_0"><strong>PEP_0</strong>: Pipe 0 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__PEP_1"><strong>PEP_1</strong>: Pipe 1 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__PEP_2"><strong>PEP_2</strong>: Pipe 2 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__PEP_3"><strong>PEP_3</strong>: Pipe 3 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__PEP_4"><strong>PEP_4</strong>: Pipe 4 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__PEP_5"><strong>PEP_5</strong>: Pipe 5 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__PEP_6"><strong>PEP_6</strong>: Pipe 6 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__PEP_7"><strong>PEP_7</strong>: Pipe 7 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__PEP_8"><strong>PEP_8</strong>: Pipe 8 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__PEP_9"><strong>PEP_9</strong>: Pipe 9 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__DMA_1"><strong>DMA_1</strong>: DMA Channel 1 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__DMA_2"><strong>DMA_2</strong>: DMA Channel 2 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__DMA_3"><strong>DMA_3</strong>: DMA Channel 3 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__DMA_4"><strong>DMA_4</strong>: DMA Channel 4 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__DMA_5"><strong>DMA_5</strong>: DMA Channel 5 Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTIER__DMA_6"><strong>DMA_6</strong>: DMA Channel 6 Interrupt Enable</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTPIP">UOTGHS Host Pipe Register</h4>
<p><strong>Name</strong>: UOTGHS_HSTPIP</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC41C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PRST8" title="Pipe 8 Reset">PRST8</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PRST7" title="Pipe 7 Reset">PRST7</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PRST6" title="Pipe 6 Reset">PRST6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PRST5" title="Pipe 5 Reset">PRST5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PRST4" title="Pipe 4 Reset">PRST4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PRST3" title="Pipe 3 Reset">PRST3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PRST2" title="Pipe 2 Reset">PRST2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PRST1" title="Pipe 1 Reset">PRST1</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PRST0" title="Pipe 0 Reset">PRST0</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PEN8" title="Pipe 8 Enable">PEN8</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PEN7" title="Pipe 7 Enable">PEN7</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PEN6" title="Pipe 6 Enable">PEN6</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PEN5" title="Pipe 5 Enable">PEN5</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PEN4" title="Pipe 4 Enable">PEN4</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PEN3" title="Pipe 3 Enable">PEN3</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PEN2" title="Pipe 2 Enable">PEN2</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PEN1" title="Pipe 1 Enable">PEN1</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIP__PEN0" title="Pipe 0 Enable">PEN0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTPIP__PEN0"><strong>PEN0</strong>: Pipe 0 Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIP__PEN1"><strong>PEN1</strong>: Pipe 1 Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIP__PEN2"><strong>PEN2</strong>: Pipe 2 Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIP__PEN3"><strong>PEN3</strong>: Pipe 3 Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIP__PEN4"><strong>PEN4</strong>: Pipe 4 Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIP__PEN5"><strong>PEN5</strong>: Pipe 5 Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIP__PEN6"><strong>PEN6</strong>: Pipe 6 Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIP__PEN7"><strong>PEN7</strong>: Pipe 7 Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIP__PEN8"><strong>PEN8</strong>: Pipe 8 Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIP__PRST0"><strong>PRST0</strong>: Pipe 0 Reset</li>
<p>-</p>
<li id="UOTGHS_HSTPIP__PRST1"><strong>PRST1</strong>: Pipe 1 Reset</li>
<p>-</p>
<li id="UOTGHS_HSTPIP__PRST2"><strong>PRST2</strong>: Pipe 2 Reset</li>
<p>-</p>
<li id="UOTGHS_HSTPIP__PRST3"><strong>PRST3</strong>: Pipe 3 Reset</li>
<p>-</p>
<li id="UOTGHS_HSTPIP__PRST4"><strong>PRST4</strong>: Pipe 4 Reset</li>
<p>-</p>
<li id="UOTGHS_HSTPIP__PRST5"><strong>PRST5</strong>: Pipe 5 Reset</li>
<p>-</p>
<li id="UOTGHS_HSTPIP__PRST6"><strong>PRST6</strong>: Pipe 6 Reset</li>
<p>-</p>
<li id="UOTGHS_HSTPIP__PRST7"><strong>PRST7</strong>: Pipe 7 Reset</li>
<p>-</p>
<li id="UOTGHS_HSTPIP__PRST8"><strong>PRST8</strong>: Pipe 8 Reset</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTFNUM">UOTGHS Host Frame Number Register</h4>
<p><strong>Name</strong>: UOTGHS_HSTFNUM</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC420</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTFNUM__FLENHIGH" title="Frame Length">FLENHIGH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="6">
<a href="#UOTGHS_HSTFNUM__FNUM" title="Frame Number">FNUM</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="5">
<a href="#UOTGHS_HSTFNUM__FNUM" title="Frame Number">FNUM</a>
</td>
<td colspan="3">
<a href="#UOTGHS_HSTFNUM__MFNUM" title="Micro Frame Number">MFNUM</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTFNUM__MFNUM"><strong>MFNUM</strong>: Micro Frame Number<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTFNUM__FNUM"><strong>FNUM</strong>: Frame Number</li>
<p>-</p>
<li id="UOTGHS_HSTFNUM__FLENHIGH"><strong>FLENHIGH</strong>: Frame Length</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTADDR1">UOTGHS Host Address 1 Register</h4>
<p><strong>Name</strong>: UOTGHS_HSTADDR1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC424</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="7">
<a href="#UOTGHS_HSTADDR1__HSTADDRP3" title="USB Host Address">HSTADDRP3</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="7">
<a href="#UOTGHS_HSTADDR1__HSTADDRP2" title="USB Host Address">HSTADDRP2</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="7">
<a href="#UOTGHS_HSTADDR1__HSTADDRP1" title="USB Host Address">HSTADDRP1</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="7">
<a href="#UOTGHS_HSTADDR1__HSTADDRP0" title="USB Host Address">HSTADDRP0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTADDR1__HSTADDRP0"><strong>HSTADDRP0</strong>: USB Host Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTADDR1__HSTADDRP1"><strong>HSTADDRP1</strong>: USB Host Address</li>
<p>-</p>
<li id="UOTGHS_HSTADDR1__HSTADDRP2"><strong>HSTADDRP2</strong>: USB Host Address</li>
<p>-</p>
<li id="UOTGHS_HSTADDR1__HSTADDRP3"><strong>HSTADDRP3</strong>: USB Host Address</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTADDR2">UOTGHS Host Address 2 Register</h4>
<p><strong>Name</strong>: UOTGHS_HSTADDR2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC428</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="7">
<a href="#UOTGHS_HSTADDR2__HSTADDRP7" title="USB Host Address">HSTADDRP7</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="7">
<a href="#UOTGHS_HSTADDR2__HSTADDRP6" title="USB Host Address">HSTADDRP6</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="7">
<a href="#UOTGHS_HSTADDR2__HSTADDRP5" title="USB Host Address">HSTADDRP5</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="7">
<a href="#UOTGHS_HSTADDR2__HSTADDRP4" title="USB Host Address">HSTADDRP4</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTADDR2__HSTADDRP4"><strong>HSTADDRP4</strong>: USB Host Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTADDR2__HSTADDRP5"><strong>HSTADDRP5</strong>: USB Host Address</li>
<p>-</p>
<li id="UOTGHS_HSTADDR2__HSTADDRP6"><strong>HSTADDRP6</strong>: USB Host Address</li>
<p>-</p>
<li id="UOTGHS_HSTADDR2__HSTADDRP7"><strong>HSTADDRP7</strong>: USB Host Address</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTADDR3">UOTGHS Host Address 3 Register</h4>
<p><strong>Name</strong>: UOTGHS_HSTADDR3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC42C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="7">
<a href="#UOTGHS_HSTADDR3__HSTADDRP9" title="USB Host Address">HSTADDRP9</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="7">
<a href="#UOTGHS_HSTADDR3__HSTADDRP8" title="USB Host Address">HSTADDRP8</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTADDR3__HSTADDRP8"><strong>HSTADDRP8</strong>: USB Host Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTADDR3__HSTADDRP9"><strong>HSTADDRP9</strong>: USB Host Address</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTPIPCFG">UOTGHS Host Pipe Configuration Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_HSTPIPCFG[0:9]</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC500</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTPIPCFG__INTFRQ" title="Pipe Interrupt Request Frequency">INTFRQ</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPCFG__PINGEN" title="Ping Enable">PINGEN</a>
</td>
<td colspan="4">
<a href="#UOTGHS_HSTPIPCFG__PEPNUM" title="Pipe Endpoint Number">PEPNUM</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#UOTGHS_HSTPIPCFG__PTYPE" title="Pipe Type">PTYPE</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPCFG__AUTOSW" title="Automatic Switch">AUTOSW</a>
</td>
<td colspan="2">
<a href="#UOTGHS_HSTPIPCFG__PTOKEN" title="Pipe Token">PTOKEN</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="3">
<a href="#UOTGHS_HSTPIPCFG__PSIZE" title="Pipe Size">PSIZE</a>
</td>
<td colspan="2">
<a href="#UOTGHS_HSTPIPCFG__PBK" title="Pipe Banks">PBK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPCFG__ALLOC" title="Pipe Memory Allocate">ALLOC</a>
</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTPIPCFG__ALLOC"><strong>ALLOC</strong>: Pipe Memory Allocate<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPCFG__PBK"><strong>PBK</strong>: Pipe Banks<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">1_BANK</td><td class="description">Single-bank pipe</td></tr><tr class="even"><td class="value">0x1</td><td class="name">2_BANK</td><td class="description">Double-bank pipe</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">3_BANK</td><td class="description">Triple-bank pipe</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPCFG__PSIZE"><strong>PSIZE</strong>: Pipe Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">8_BYTE</td><td class="description">8 bytes</td></tr><tr class="even"><td class="value">0x1</td><td class="name">16_BYTE</td><td class="description">16 bytes</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">32_BYTE</td><td class="description">32 bytes</td></tr><tr class="even"><td class="value">0x3</td><td class="name">64_BYTE</td><td class="description">64 bytes</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">128_BYTE</td><td class="description">128 bytes</td></tr><tr class="even"><td class="value">0x5</td><td class="name">256_BYTE</td><td class="description">256 bytes</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">512_BYTE</td><td class="description">512 bytes</td></tr><tr class="even"><td class="value">0x7</td><td class="name">1024_BYTE</td><td class="description">1024 bytes</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPCFG__PTOKEN"><strong>PTOKEN</strong>: Pipe Token<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">SETUP</td><td class="description">SETUP</td></tr><tr class="even"><td class="value">0x1</td><td class="name">IN</td><td class="description">IN</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">OUT</td><td class="description">OUT</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPCFG__AUTOSW"><strong>AUTOSW</strong>: Automatic Switch<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The automatic bank switching is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The automatic bank switching is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPCFG__PTYPE"><strong>PTYPE</strong>: Pipe Type<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CTRL</td><td class="description">Control</td></tr><tr class="even"><td class="value">0x1</td><td class="name">ISO</td><td class="description">Isochronous</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">BLK</td><td class="description">Bulk</td></tr><tr class="even"><td class="value">0x3</td><td class="name">INTRPT</td><td class="description">Interrupt</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPCFG__PEPNUM"><strong>PEPNUM</strong>: Pipe Endpoint Number</li>
<p>-</p>
<li id="UOTGHS_HSTPIPCFG__PINGEN"><strong>PINGEN</strong>: Ping Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPCFG__INTFRQ"><strong>INTFRQ</strong>: Pipe Interrupt Request Frequency</li>
<p>-</p>
<li id="UOTGHS_HSTPIPCFG__BINTERVAL"><strong>BINTERVAL</strong>: bInterval parameter for the Bulk-Out/Ping transaction</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTPIPISR">UOTGHS Host Pipe Status Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_HSTPIPISR[0:9]</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400AC530</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="7">
<a href="#UOTGHS_HSTPIPISR__PBYCT" title="Pipe Byte Count">PBYCT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#UOTGHS_HSTPIPISR__PBYCT" title="Pipe Byte Count">PBYCT</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPISR__CFGOK" title="Configuration OK Status">CFGOK</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPISR__RWALL" title="Read-write Allowed">RWALL</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UOTGHS_HSTPIPISR__CURRBK" title="Current Bank">CURRBK</a>
</td>
<td colspan="2">
<a href="#UOTGHS_HSTPIPISR__NBUSYBK" title="Number of Busy Banks">NBUSYBK</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#UOTGHS_HSTPIPISR__DTSEQ" title="Data Toggle Sequence">DTSEQ</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTPIPISR__SHORTPACKETI" title="Short Packet Interrupt">SHORTPACKETI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPISR__RXSTALLDI" title="Received STALLed Interrupt">RXSTALLDI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPISR__OVERFI" title="Overflow Interrupt">OVERFI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPISR__NAKEDI" title="NAKed Interrupt">NAKEDI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPISR__PERRI" title="Pipe Error Interrupt">PERRI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPISR__TXSTPI" title="Transmitted SETUP Interrupt">TXSTPI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPISR__TXOUTI" title="Transmitted OUT Data Interrupt">TXOUTI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPISR__RXINI" title="Received IN Data Interrupt">RXINI</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTPIPISR__RXINI"><strong>RXINI</strong>: Received IN Data Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPISR__TXOUTI"><strong>TXOUTI</strong>: Transmitted OUT Data Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTPIPISR__TXSTPI"><strong>TXSTPI</strong>: Transmitted SETUP Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTPIPISR__UNDERFI"><strong>UNDERFI</strong>: Underflow Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTPIPISR__PERRI"><strong>PERRI</strong>: Pipe Error Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTPIPISR__NAKEDI"><strong>NAKEDI</strong>: NAKed Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTPIPISR__OVERFI"><strong>OVERFI</strong>: Overflow Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTPIPISR__RXSTALLDI"><strong>RXSTALLDI</strong>: Received STALLed Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTPIPISR__CRCERRI"><strong>CRCERRI</strong>: CRC Error Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTPIPISR__SHORTPACKETI"><strong>SHORTPACKETI</strong>: Short Packet Interrupt</li>
<p>-</p>
<li id="UOTGHS_HSTPIPISR__DTSEQ"><strong>DTSEQ</strong>: Data Toggle Sequence<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DATA0</td><td class="description">Data0 toggle sequence</td></tr><tr class="even"><td class="value">1</td><td class="name">DATA1</td><td class="description">Data1 toggle sequence</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPISR__NBUSYBK"><strong>NBUSYBK</strong>: Number of Busy Banks<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">0_BUSY</td><td class="description">0 busy bank (all banks free)</td></tr><tr class="even"><td class="value">0x1</td><td class="name">1_BUSY</td><td class="description">1 busy bank</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">2_BUSY</td><td class="description">2 busy banks</td></tr><tr class="even"><td class="value">0x3</td><td class="name">3_BUSY</td><td class="description">3 busy banks</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPISR__CURRBK"><strong>CURRBK</strong>: Current Bank<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BANK0</td><td class="description">Current bank is bank0</td></tr><tr class="even"><td class="value">0x1</td><td class="name">BANK1</td><td class="description">Current bank is bank1</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">BANK2</td><td class="description">Current bank is bank2</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPISR__RWALL"><strong>RWALL</strong>: Read-write Allowed</li>
<p>-</p>
<li id="UOTGHS_HSTPIPISR__CFGOK"><strong>CFGOK</strong>: Configuration OK Status</li>
<p>-</p>
<li id="UOTGHS_HSTPIPISR__PBYCT"><strong>PBYCT</strong>: Pipe Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTPIPICR">UOTGHS Host Pipe Clear Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_HSTPIPICR[0:9]</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC560</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTPIPICR__SHORTPACKETIC" title="Short Packet Interrupt Clear">SHORTPACKETIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPICR__RXSTALLDIC" title="Received STALLed Interrupt Clear">RXSTALLDIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPICR__OVERFIC" title="Overflow Interrupt Clear">OVERFIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPICR__NAKEDIC" title="NAKed Interrupt Clear">NAKEDIC</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPICR__TXSTPIC" title="Transmitted SETUP Interrupt Clear">TXSTPIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPICR__TXOUTIC" title="Transmitted OUT Data Interrupt Clear">TXOUTIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPICR__RXINIC" title="Received IN Data Interrupt Clear">RXINIC</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTPIPICR__RXINIC"><strong>RXINIC</strong>: Received IN Data Interrupt Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPICR__TXOUTIC"><strong>TXOUTIC</strong>: Transmitted OUT Data Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_HSTPIPICR__TXSTPIC"><strong>TXSTPIC</strong>: Transmitted SETUP Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_HSTPIPICR__UNDERFIC"><strong>UNDERFIC</strong>: Underflow Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_HSTPIPICR__NAKEDIC"><strong>NAKEDIC</strong>: NAKed Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_HSTPIPICR__OVERFIC"><strong>OVERFIC</strong>: Overflow Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_HSTPIPICR__RXSTALLDIC"><strong>RXSTALLDIC</strong>: Received STALLed Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_HSTPIPICR__CRCERRIC"><strong>CRCERRIC</strong>: CRC Error Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_HSTPIPICR__SHORTPACKETIC"><strong>SHORTPACKETIC</strong>: Short Packet Interrupt Clear</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTPIPIFR">UOTGHS Host Pipe Set Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_HSTPIPIFR[0:9]</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC590</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIFR__NBUSYBKS" title="Number of Busy Banks Set">NBUSYBKS</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTPIPIFR__SHORTPACKETIS" title="Short Packet Interrupt Set">SHORTPACKETIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIFR__RXSTALLDIS" title="Received STALLed Interrupt Set">RXSTALLDIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIFR__OVERFIS" title="Overflow Interrupt Set">OVERFIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIFR__NAKEDIS" title="NAKed Interrupt Set">NAKEDIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIFR__PERRIS" title="Pipe Error Interrupt Set">PERRIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIFR__TXSTPIS" title="Transmitted SETUP Interrupt Set">TXSTPIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIFR__TXOUTIS" title="Transmitted OUT Data Interrupt Set">TXOUTIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIFR__RXINIS" title="Received IN Data Interrupt Set">RXINIS</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTPIPIFR__RXINIS"><strong>RXINIS</strong>: Received IN Data Interrupt Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPIFR__TXOUTIS"><strong>TXOUTIS</strong>: Transmitted OUT Data Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIFR__TXSTPIS"><strong>TXSTPIS</strong>: Transmitted SETUP Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIFR__UNDERFIS"><strong>UNDERFIS</strong>: Underflow Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIFR__PERRIS"><strong>PERRIS</strong>: Pipe Error Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIFR__NAKEDIS"><strong>NAKEDIS</strong>: NAKed Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIFR__OVERFIS"><strong>OVERFIS</strong>: Overflow Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIFR__RXSTALLDIS"><strong>RXSTALLDIS</strong>: Received STALLed Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIFR__CRCERRIS"><strong>CRCERRIS</strong>: CRC Error Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIFR__SHORTPACKETIS"><strong>SHORTPACKETIS</strong>: Short Packet Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIFR__NBUSYBKS"><strong>NBUSYBKS</strong>: Number of Busy Banks Set</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTPIPIMR">UOTGHS Host Pipe Mask Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_HSTPIPIMR[0:9]</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400AC5C0</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIMR__RSTDT" title="Reset Data Toggle">RSTDT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIMR__PFREEZE" title="Pipe Freeze">PFREEZE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIMR__PDISHDMA" title="Pipe Interrupts Disable HDMA Request Enable">PDISHDMA</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIMR__FIFOCON" title="FIFO Control">FIFOCON</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIMR__NBUSYBKE" title="Number of Busy Banks Interrupt Enable">NBUSYBKE</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTPIPIMR__SHORTPACKETIE" title="Short Packet Interrupt Enable">SHORTPACKETIE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIMR__RXSTALLDE" title="Received STALLed Interrupt Enable">RXSTALLDE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIMR__OVERFIE" title="Overflow Interrupt Enable">OVERFIE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIMR__NAKEDE" title="NAKed Interrupt Enable">NAKEDE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIMR__PERRE" title="Pipe Error Interrupt Enable">PERRE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIMR__TXSTPE" title="Transmitted SETUP Interrupt Enable">TXSTPE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIMR__TXOUTE" title="Transmitted OUT Data Interrupt Enable">TXOUTE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIMR__RXINE" title="Received IN Data Interrupt Enable">RXINE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTPIPIMR__RXINE"><strong>RXINE</strong>: Received IN Data Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPIMR__TXOUTE"><strong>TXOUTE</strong>: Transmitted OUT Data Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIMR__TXSTPE"><strong>TXSTPE</strong>: Transmitted SETUP Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIMR__UNDERFIE"><strong>UNDERFIE</strong>: Underflow Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIMR__PERRE"><strong>PERRE</strong>: Pipe Error Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIMR__NAKEDE"><strong>NAKEDE</strong>: NAKed Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIMR__OVERFIE"><strong>OVERFIE</strong>: Overflow Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIMR__RXSTALLDE"><strong>RXSTALLDE</strong>: Received STALLed Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIMR__CRCERRE"><strong>CRCERRE</strong>: CRC Error Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIMR__SHORTPACKETIE"><strong>SHORTPACKETIE</strong>: Short Packet Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIMR__NBUSYBKE"><strong>NBUSYBKE</strong>: Number of Busy Banks Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIMR__FIFOCON"><strong>FIFOCON</strong>: FIFO Control</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIMR__PDISHDMA"><strong>PDISHDMA</strong>: Pipe Interrupts Disable HDMA Request Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIMR__PFREEZE"><strong>PFREEZE</strong>: Pipe Freeze</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIMR__RSTDT"><strong>RSTDT</strong>: Reset Data Toggle</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTPIPIER">UOTGHS Host Pipe Enable Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_HSTPIPIER[0:9]</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC5F0</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIER__RSTDTS" title="Reset Data Toggle Enable">RSTDTS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIER__PFREEZES" title="Pipe Freeze Enable">PFREEZES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIER__PDISHDMAS" title="Pipe Interrupts Disable HDMA Request Enable">PDISHDMAS</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIER__NBUSYBKES" title="Number of Busy Banks Enable">NBUSYBKES</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTPIPIER__SHORTPACKETIES" title="Short Packet Interrupt Enable">SHORTPACKETIES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIER__RXSTALLDES" title="Received STALLed Interrupt Enable">RXSTALLDES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIER__OVERFIES" title="Overflow Interrupt Enable">OVERFIES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIER__NAKEDES" title="NAKed Interrupt Enable">NAKEDES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIER__PERRES" title="Pipe Error Interrupt Enable">PERRES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIER__TXSTPES" title="Transmitted SETUP Interrupt Enable">TXSTPES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIER__TXOUTES" title="Transmitted OUT Data Interrupt Enable">TXOUTES</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIER__RXINES" title="Received IN Data Interrupt Enable">RXINES</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTPIPIER__RXINES"><strong>RXINES</strong>: Received IN Data Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPIER__TXOUTES"><strong>TXOUTES</strong>: Transmitted OUT Data Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIER__TXSTPES"><strong>TXSTPES</strong>: Transmitted SETUP Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIER__UNDERFIES"><strong>UNDERFIES</strong>: Underflow Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIER__PERRES"><strong>PERRES</strong>: Pipe Error Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIER__NAKEDES"><strong>NAKEDES</strong>: NAKed Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIER__OVERFIES"><strong>OVERFIES</strong>: Overflow Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIER__RXSTALLDES"><strong>RXSTALLDES</strong>: Received STALLed Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIER__CRCERRES"><strong>CRCERRES</strong>: CRC Error Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIER__SHORTPACKETIES"><strong>SHORTPACKETIES</strong>: Short Packet Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIER__NBUSYBKES"><strong>NBUSYBKES</strong>: Number of Busy Banks Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIER__PDISHDMAS"><strong>PDISHDMAS</strong>: Pipe Interrupts Disable HDMA Request Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIER__PFREEZES"><strong>PFREEZES</strong>: Pipe Freeze Enable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIER__RSTDTS"><strong>RSTDTS</strong>: Reset Data Toggle Enable</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTPIPIDR">UOTGHS Host Pipe Disable Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_HSTPIPIDR[0:9]</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC620</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIDR__PFREEZEC" title="Pipe Freeze Disable">PFREEZEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIDR__PDISHDMAC" title="Pipe Interrupts Disable HDMA Request Disable">PDISHDMAC</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIDR__FIFOCONC" title="FIFO Control Disable">FIFOCONC</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIDR__NBUSYBKEC" title="Number of Busy Banks Disable">NBUSYBKEC</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTPIPIDR__SHORTPACKETIEC" title="Short Packet Interrupt Disable">SHORTPACKETIEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIDR__RXSTALLDEC" title="Received STALLed Interrupt Disable">RXSTALLDEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIDR__OVERFIEC" title="Overflow Interrupt Disable">OVERFIEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIDR__NAKEDEC" title="NAKed Interrupt Disable">NAKEDEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIDR__PERREC" title="Pipe Error Interrupt Disable">PERREC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIDR__TXSTPEC" title="Transmitted SETUP Interrupt Disable">TXSTPEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIDR__TXOUTEC" title="Transmitted OUT Data Interrupt Disable">TXOUTEC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPIDR__RXINEC" title="Received IN Data Interrupt Disable">RXINEC</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTPIPIDR__RXINEC"><strong>RXINEC</strong>: Received IN Data Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPIDR__TXOUTEC"><strong>TXOUTEC</strong>: Transmitted OUT Data Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIDR__TXSTPEC"><strong>TXSTPEC</strong>: Transmitted SETUP Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIDR__UNDERFIEC"><strong>UNDERFIEC</strong>: Underflow Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIDR__PERREC"><strong>PERREC</strong>: Pipe Error Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIDR__NAKEDEC"><strong>NAKEDEC</strong>: NAKed Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIDR__OVERFIEC"><strong>OVERFIEC</strong>: Overflow Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIDR__RXSTALLDEC"><strong>RXSTALLDEC</strong>: Received STALLed Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIDR__CRCERREC"><strong>CRCERREC</strong>: CRC Error Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIDR__SHORTPACKETIEC"><strong>SHORTPACKETIEC</strong>: Short Packet Interrupt Disable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIDR__NBUSYBKEC"><strong>NBUSYBKEC</strong>: Number of Busy Banks Disable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIDR__FIFOCONC"><strong>FIFOCONC</strong>: FIFO Control Disable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIDR__PDISHDMAC"><strong>PDISHDMAC</strong>: Pipe Interrupts Disable HDMA Request Disable</li>
<p>-</p>
<li id="UOTGHS_HSTPIPIDR__PFREEZEC"><strong>PFREEZEC</strong>: Pipe Freeze Disable</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTPIPINRQ">UOTGHS Host Pipe IN Request Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_HSTPIPINRQ[0:9]</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC650</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPINRQ__INMODE" title="IN Request Mode">INMODE</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTPIPINRQ__INRQ" title="IN Request Number before Freeze">INRQ</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTPIPINRQ__INRQ"><strong>INRQ</strong>: IN Request Number before Freeze<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPINRQ__INMODE"><strong>INMODE</strong>: IN Request Mode</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTPIPERR">UOTGHS Host Pipe Error Register (n = 0)</h4>
<p><strong>Name</strong>: UOTGHS_HSTPIPERR[0:9]</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC680</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="2">
<a href="#UOTGHS_HSTPIPERR__COUNTER" title="Error Counter">COUNTER</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPERR__CRC16" title="CRC16 Error">CRC16</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPERR__TIMEOUT" title="Time-Out Error">TIMEOUT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPERR__PID" title="PID Error">PID</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPERR__DATAPID" title="Data PID Error">DATAPID</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTPIPERR__DATATGL" title="Data Toggle Error">DATATGL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTPIPERR__DATATGL"><strong>DATATGL</strong>: Data Toggle Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_HSTPIPERR__DATAPID"><strong>DATAPID</strong>: Data PID Error</li>
<p>-</p>
<li id="UOTGHS_HSTPIPERR__PID"><strong>PID</strong>: PID Error</li>
<p>-</p>
<li id="UOTGHS_HSTPIPERR__TIMEOUT"><strong>TIMEOUT</strong>: Time-Out Error</li>
<p>-</p>
<li id="UOTGHS_HSTPIPERR__CRC16"><strong>CRC16</strong>: CRC16 Error</li>
<p>-</p>
<li id="UOTGHS_HSTPIPERR__COUNTER"><strong>COUNTER</strong>: Error Counter</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTDMANXTDSC1">UOTGHS Host DMA Channel Next Descriptor Address Register (n = 1)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMANXTDSC1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC710</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC1__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC1__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC1__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC1__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMANXTDSC1__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMAADDRESS1">UOTGHS Host DMA Channel Address Register (n = 1)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMAADDRESS1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC714</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS1__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS1__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS1__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS1__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMAADDRESS1__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMACONTROL1">UOTGHS Host DMA Channel Control Register (n = 1)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMACONTROL1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC718</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL1__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL1__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL1__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL1__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL1__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL1__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL1__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL1__END_TR_EN" title="End of Transfer Enable (Control)">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL1__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL1__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMACONTROL1__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL1__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL1__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL1__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL1__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL1__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL1__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL1__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks the bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL1__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMASTATUS1">UOTGHS Host DMA Channel Status Register (n = 1)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMASTATUS1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC71C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS1__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS1__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS1__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS1__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS1__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS1__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS1__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMASTATUS1__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS1__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS1__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS1__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS1__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS1__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTDMANXTDSC2">UOTGHS Host DMA Channel Next Descriptor Address Register (n = 2)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMANXTDSC2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC720</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC2__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC2__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC2__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC2__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMANXTDSC2__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMAADDRESS2">UOTGHS Host DMA Channel Address Register (n = 2)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMAADDRESS2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC724</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS2__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS2__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS2__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS2__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMAADDRESS2__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMACONTROL2">UOTGHS Host DMA Channel Control Register (n = 2)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMACONTROL2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC728</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL2__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL2__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL2__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL2__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL2__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL2__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL2__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL2__END_TR_EN" title="End of Transfer Enable (Control)">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL2__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL2__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMACONTROL2__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL2__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL2__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL2__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL2__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL2__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL2__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL2__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks the bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL2__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMASTATUS2">UOTGHS Host DMA Channel Status Register (n = 2)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMASTATUS2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC72C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS2__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS2__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS2__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS2__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS2__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS2__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS2__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMASTATUS2__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS2__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS2__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS2__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS2__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS2__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTDMANXTDSC3">UOTGHS Host DMA Channel Next Descriptor Address Register (n = 3)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMANXTDSC3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC730</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC3__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC3__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC3__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC3__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMANXTDSC3__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMAADDRESS3">UOTGHS Host DMA Channel Address Register (n = 3)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMAADDRESS3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC734</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS3__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS3__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS3__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS3__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMAADDRESS3__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMACONTROL3">UOTGHS Host DMA Channel Control Register (n = 3)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMACONTROL3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC738</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL3__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL3__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL3__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL3__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL3__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL3__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL3__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL3__END_TR_EN" title="End of Transfer Enable (Control)">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL3__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL3__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMACONTROL3__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL3__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL3__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL3__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL3__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL3__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL3__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL3__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks the bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL3__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMASTATUS3">UOTGHS Host DMA Channel Status Register (n = 3)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMASTATUS3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC73C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS3__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS3__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS3__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS3__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS3__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS3__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS3__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMASTATUS3__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS3__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS3__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS3__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS3__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS3__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTDMANXTDSC4">UOTGHS Host DMA Channel Next Descriptor Address Register (n = 4)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMANXTDSC4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC740</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC4__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC4__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC4__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC4__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMANXTDSC4__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMAADDRESS4">UOTGHS Host DMA Channel Address Register (n = 4)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMAADDRESS4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC744</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS4__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS4__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS4__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS4__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMAADDRESS4__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMACONTROL4">UOTGHS Host DMA Channel Control Register (n = 4)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMACONTROL4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC748</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL4__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL4__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL4__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL4__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL4__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL4__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL4__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL4__END_TR_EN" title="End of Transfer Enable (Control)">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL4__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL4__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMACONTROL4__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL4__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL4__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL4__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL4__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL4__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL4__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL4__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks the bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL4__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMASTATUS4">UOTGHS Host DMA Channel Status Register (n = 4)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMASTATUS4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC74C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS4__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS4__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS4__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS4__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS4__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS4__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS4__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMASTATUS4__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS4__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS4__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS4__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS4__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS4__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTDMANXTDSC5">UOTGHS Host DMA Channel Next Descriptor Address Register (n = 5)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMANXTDSC5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC750</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC5__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC5__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC5__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC5__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMANXTDSC5__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMAADDRESS5">UOTGHS Host DMA Channel Address Register (n = 5)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMAADDRESS5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC754</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS5__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS5__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS5__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS5__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMAADDRESS5__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMACONTROL5">UOTGHS Host DMA Channel Control Register (n = 5)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMACONTROL5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC758</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL5__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL5__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL5__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL5__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL5__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL5__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL5__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL5__END_TR_EN" title="End of Transfer Enable (Control)">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL5__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL5__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMACONTROL5__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL5__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL5__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL5__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL5__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL5__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL5__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL5__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks the bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL5__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMASTATUS5">UOTGHS Host DMA Channel Status Register (n = 5)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMASTATUS5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC75C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS5__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS5__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS5__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS5__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS5__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS5__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS5__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMASTATUS5__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS5__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS5__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS5__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS5__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS5__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTDMANXTDSC6">UOTGHS Host DMA Channel Next Descriptor Address Register (n = 6)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMANXTDSC6</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC760</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC6__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC6__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC6__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC6__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMANXTDSC6__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMAADDRESS6">UOTGHS Host DMA Channel Address Register (n = 6)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMAADDRESS6</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC764</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS6__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS6__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS6__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS6__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMAADDRESS6__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMACONTROL6">UOTGHS Host DMA Channel Control Register (n = 6)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMACONTROL6</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC768</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL6__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL6__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL6__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL6__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL6__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL6__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL6__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL6__END_TR_EN" title="End of Transfer Enable (Control)">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL6__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL6__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMACONTROL6__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL6__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL6__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL6__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL6__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL6__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL6__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL6__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks the bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL6__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMASTATUS6">UOTGHS Host DMA Channel Status Register (n = 6)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMASTATUS6</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC76C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS6__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS6__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS6__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS6__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS6__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS6__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS6__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMASTATUS6__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS6__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS6__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS6__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS6__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS6__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_HSTDMANXTDSC7">UOTGHS Host DMA Channel Next Descriptor Address Register (n = 7)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMANXTDSC7</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC770</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC7__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC7__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC7__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMANXTDSC7__NXT_DSC_ADD" title="Next Descriptor Address">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMANXTDSC7__NXT_DSC_ADD"><strong>NXT_DSC_ADD</strong>: Next Descriptor Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMAADDRESS7">UOTGHS Host DMA Channel Address Register (n = 7)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMAADDRESS7</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC774</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS7__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS7__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS7__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMAADDRESS7__BUFF_ADD" title="Buffer Address">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMAADDRESS7__BUFF_ADD"><strong>BUFF_ADD</strong>: Buffer Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMACONTROL7">UOTGHS Host DMA Channel Control Register (n = 7)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMACONTROL7</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC778</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL7__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMACONTROL7__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL7__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL7__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL7__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL7__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL7__END_B_EN" title="End of Buffer Enable Control">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL7__END_TR_EN" title="End of Transfer Enable (Control)">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL7__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable Command">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMACONTROL7__CHANN_ENB" title="Channel Enable Command">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMACONTROL7__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL7__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable Command</li>
<p>-</p>
<li id="UOTGHS_HSTDMACONTROL7__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UOTGHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL7__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL7__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL7__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL7__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL7__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks the bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMACONTROL7__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_HSTDMASTATUS7">UOTGHS Host DMA Channel Status Register (n = 7)</h4>
<p><strong>Name</strong>: UOTGHS_HSTDMASTATUS7</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC77C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS7__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UOTGHS_HSTDMASTATUS7__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS7__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS7__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS7__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS7__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UOTGHS_HSTDMASTATUS7__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_HSTDMASTATUS7__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS7__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS7__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS7__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when BUFF_COUNT count-down reaches zero.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS7__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UOTGHS_HSTDMASTATUS7__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_CTRL">UOTGHS General Control Register</h4>
<p><strong>Name</strong>: UOTGHS_CTRL</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400AC800</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__UIMOD" title="UOTGHS Mode">UIMOD</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__UIDE" title="UOTGID Pin Enable">UIDE</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__UNLOCK" title="Timer Access Unlock">UNLOCK</a>
</td>
<td colspan="2">
<a href="#UOTGHS_CTRL__TIMPAGE" title="Timer Page">TIMPAGE</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#UOTGHS_CTRL__TIMVALUE" title="Timer Value">TIMVALUE</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_CTRL__USBE" title="UOTGHS Enable">USBE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__FRZCLK" title="Freeze USB Clock">FRZCLK</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__VBUSPO" title="VBus Polarity Off">VBUSPO</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__OTGPADE" title="OTG Pad Enable">OTGPADE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__HNPREQ" title="HNP Request">HNPREQ</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__SRPREQ" title="SRP Request">SRPREQ</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__SRPSEL" title="SRP Selection">SRPSEL</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__VBUSHWC" title="VBus Hardware Control">VBUSHWC</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_CTRL__STOE" title="Suspend Time-Out Interrupt Enable">STOE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__HNPERRE" title="HNP Error Interrupt Enable">HNPERRE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__ROLEEXE" title="Role Exchange Interrupt Enable">ROLEEXE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__BCERRE" title="B-Connection Error Interrupt Enable">BCERRE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__VBERRE" title="VBus Error Interrupt Enable">VBERRE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__SRPE" title="SRP Interrupt Enable">SRPE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__VBUSTE" title="VBus Transition Interrupt Enable">VBUSTE</a>
</td>
<td colspan="1">
<a href="#UOTGHS_CTRL__IDTE" title="ID Transition Interrupt Enable">IDTE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_CTRL__IDTE"><strong>IDTE</strong>: ID Transition Interrupt Enable</li>
<p>-</p>
<li id="UOTGHS_CTRL__VBUSTE"><strong>VBUSTE</strong>: VBus Transition Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The VBus Transition Interrupt (UOTGHS_SR.VBUSTI) is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The VBus Transition Interrupt (UOTGHS_SR.VBUSTI) is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__SRPE"><strong>SRPE</strong>: SRP Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The SRP Interrupt (UOTGHS_SR.SRPI) is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The SRP Interrupt (UOTGHS_SR.SRPI) is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__VBERRE"><strong>VBERRE</strong>: VBus Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The VBus Error Interrupt (UOTGHS_SR.VBERRI) is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The VBus Error Interrupt (UOTGHS_SR.VBERRI) is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__BCERRE"><strong>BCERRE</strong>: B-Connection Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The B-Connection Error Interrupt (UOTGHS_SR.BCERRI) is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The B-Connection Error Interrupt (UOTGHS_SR.BCERRI) is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__ROLEEXE"><strong>ROLEEXE</strong>: Role Exchange Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The Role Exchange Interrupt (UOTGHS_SR.ROLEEXI) is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The Role Exchange Interrupt (UOTGHS_SR.ROLEEXI) is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__HNPERRE"><strong>HNPERRE</strong>: HNP Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The HNP Error Interrupt (UOTGHS_SR.HNPERRI) is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The HNP Error Interrupt (UOTGHS_SR.HNPERRI) is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__STOE"><strong>STOE</strong>: Suspend Time-Out Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The Suspend Time-Out Interrupt (UOTGHS_SR.STOI) is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The Suspend Time-Out Interrupt (UOTGHS_SR.STOI) is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__VBUSHWC"><strong>VBUSHWC</strong>: VBus Hardware Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The hardware control over the UOTGVBOF output pin is enabled. The UOTGHS resets the UOTGVBOF output pin when a VBUS problem occurs.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The hardware control over the UOTGVBOF output pin is disabled.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__SRPSEL"><strong>SRPSEL</strong>: SRP Selection<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Data line pulsing is selected as an SRP method.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">VBus pulsing is selected as an SRP method.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__SRPREQ"><strong>SRPREQ</strong>: SRP Request</li>
<p>-</p>
<li id="UOTGHS_CTRL__HNPREQ"><strong>HNPREQ</strong>: HNP Request</li>
<p>-</p>
<li id="UOTGHS_CTRL__OTGPADE"><strong>OTGPADE</strong>: OTG Pad Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The OTG pad is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The OTG pad is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__VBUSPO"><strong>VBUSPO</strong>: VBus Polarity Off<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The UOTGVBOF output signal is in its default mode (active high).</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The UOTGVBOF output signal is inverted (active low).</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__FRZCLK"><strong>FRZCLK</strong>: Freeze USB Clock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The clock inputs are enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The clock inputs are disabled (the resume detection is still active).This reduces the power consumption. Unless explicitly stated, all registers then become read-only.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__USBE"><strong>USBE</strong>: UOTGHS Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The UOTGHS is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The UOTGHS is enabled.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__TIMVALUE"><strong>TIMVALUE</strong>: Timer Value</li>
<p>-</p>
<li id="UOTGHS_CTRL__TIMPAGE"><strong>TIMPAGE</strong>: Timer Page</li>
<p>-</p>
<li id="UOTGHS_CTRL__UNLOCK"><strong>UNLOCK</strong>: Timer Access Unlock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The TIMPAGE and TIMVALUE fields are locked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The TIMPAGE and TIMVALUE fields are unlocked.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__UIDE"><strong>UIDE</strong>: UOTGID Pin Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">UIMOD</td><td class="description">The USB mode (device/host) is selected from the UIMOD bit.</td></tr><tr class="even"><td class="value">1</td><td class="name">UOTGID</td><td class="description">The USB mode (device/host) is selected from the UOTGID input pin.</td></tr></tbody></table></li>
<li id="UOTGHS_CTRL__UIMOD"><strong>UIMOD</strong>: UOTGHS Mode<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">Host</td><td class="description">The module is in USB host mode.</td></tr><tr class="even"><td class="value">1</td><td class="name">Device</td><td class="description">The module is in USB device mode.</td></tr></tbody></table></li>
</ul>
<h4 id="UOTGHS_SR">UOTGHS General Status Register</h4>
<p><strong>Name</strong>: UOTGHS_SR</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400AC804</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_SR__CLKUSABLE" title="UTMI Clock Usable">CLKUSABLE</a>
</td>
<td colspan="2">
<a href="#UOTGHS_SR__SPEED" title="Speed Status">SPEED</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SR__VBUS" title="VBus Level">VBUS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SR__ID" title="UOTGID Pin State">ID</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SR__VBUSRQ" title="VBus Request">VBUSRQ</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_SR__STOI" title="Suspend Time-Out Interrupt">STOI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SR__HNPERRI" title="HNP Error Interrupt">HNPERRI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SR__ROLEEXI" title="Role Exchange Interrupt">ROLEEXI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SR__BCERRI" title="B-Connection Error Interrupt">BCERRI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SR__VBERRI" title="VBus Error Interrupt">VBERRI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SR__SRPI" title="SRP Interrupt">SRPI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SR__VBUSTI" title="VBus Transition Interrupt">VBUSTI</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SR__IDTI" title="ID Transition Interrupt">IDTI</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_SR__IDTI"><strong>IDTI</strong>: ID Transition Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_SR__VBUSTI"><strong>VBUSTI</strong>: VBus Transition Interrupt</li>
<p>-</p>
<li id="UOTGHS_SR__SRPI"><strong>SRPI</strong>: SRP Interrupt</li>
<p>-</p>
<li id="UOTGHS_SR__VBERRI"><strong>VBERRI</strong>: VBus Error Interrupt</li>
<p>-</p>
<li id="UOTGHS_SR__BCERRI"><strong>BCERRI</strong>: B-Connection Error Interrupt</li>
<p>-</p>
<li id="UOTGHS_SR__ROLEEXI"><strong>ROLEEXI</strong>: Role Exchange Interrupt</li>
<p>-</p>
<li id="UOTGHS_SR__HNPERRI"><strong>HNPERRI</strong>: HNP Error Interrupt</li>
<p>-</p>
<li id="UOTGHS_SR__STOI"><strong>STOI</strong>: Suspend Time-Out Interrupt</li>
<p>-</p>
<li id="UOTGHS_SR__VBUSRQ"><strong>VBUSRQ</strong>: VBus Request<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The UOTGVBOF output pin is driven low to disable the VBUS power supply generation.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The UOTGVBOF output pin is driven high to enable the VBUS power supply generation.</td></tr></tbody></table></li>
<li id="UOTGHS_SR__ID"><strong>ID</strong>: UOTGID Pin State</li>
<p>-</p>
<li id="UOTGHS_SR__VBUS"><strong>VBUS</strong>: VBus Level</li>
<p>-</p>
<li id="UOTGHS_SR__SPEED"><strong>SPEED</strong>: Speed Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">FULL_SPEED</td><td class="description">Full-Speed mode</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HIGH_SPEED</td><td class="description">High-Speed mode</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">LOW_SPEED</td><td class="description">Low-Speed mode</td></tr></tbody></table></li>
<li id="UOTGHS_SR__CLKUSABLE"><strong>CLKUSABLE</strong>: UTMI Clock Usable</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_SCR">UOTGHS General Status Clear Register</h4>
<p><strong>Name</strong>: UOTGHS_SCR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC808</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_SCR__VBUSRQC" title="VBus Request Clear">VBUSRQC</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_SCR__STOIC" title="Suspend Time-Out Interrupt Clear">STOIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SCR__HNPERRIC" title="HNP Error Interrupt Clear">HNPERRIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SCR__ROLEEXIC" title="Role Exchange Interrupt Clear">ROLEEXIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SCR__BCERRIC" title="B-Connection Error Interrupt Clear">BCERRIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SCR__VBERRIC" title="VBus Error Interrupt Clear">VBERRIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SCR__SRPIC" title="SRP Interrupt Clear">SRPIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SCR__VBUSTIC" title="VBus Transition Interrupt Clear">VBUSTIC</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SCR__IDTIC" title="ID Transition Interrupt Clear">IDTIC</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_SCR__IDTIC"><strong>IDTIC</strong>: ID Transition Interrupt Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_SCR__VBUSTIC"><strong>VBUSTIC</strong>: VBus Transition Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_SCR__SRPIC"><strong>SRPIC</strong>: SRP Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_SCR__VBERRIC"><strong>VBERRIC</strong>: VBus Error Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_SCR__BCERRIC"><strong>BCERRIC</strong>: B-Connection Error Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_SCR__ROLEEXIC"><strong>ROLEEXIC</strong>: Role Exchange Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_SCR__HNPERRIC"><strong>HNPERRIC</strong>: HNP Error Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_SCR__STOIC"><strong>STOIC</strong>: Suspend Time-Out Interrupt Clear</li>
<p>-</p>
<li id="UOTGHS_SCR__VBUSRQC"><strong>VBUSRQC</strong>: VBus Request Clear</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_SFR">UOTGHS General Status Set Register</h4>
<p><strong>Name</strong>: UOTGHS_SFR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400AC80C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UOTGHS_SFR__VBUSRQS" title="VBus Request Set">VBUSRQS</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UOTGHS_SFR__STOIS" title="Suspend Time-Out Interrupt Set">STOIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SFR__HNPERRIS" title="HNP Error Interrupt Set">HNPERRIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SFR__ROLEEXIS" title="Role Exchange Interrupt Set">ROLEEXIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SFR__BCERRIS" title="B-Connection Error Interrupt Set">BCERRIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SFR__VBERRIS" title="VBus Error Interrupt Set">VBERRIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SFR__SRPIS" title="SRP Interrupt Set">SRPIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SFR__VBUSTIS" title="VBus Transition Interrupt Set">VBUSTIS</a>
</td>
<td colspan="1">
<a href="#UOTGHS_SFR__IDTIS" title="ID Transition Interrupt Set">IDTIS</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_SFR__IDTIS"><strong>IDTIS</strong>: ID Transition Interrupt Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x74CBB1</td><td class="name">-</td><td class="description">0</td></tr><tr class="even"><td class="value">0x1608940C365</td><td class="name">-</td><td class="description">8</td></tr><tr class="odd"><td class="value">0x151ED2399749</td><td class="name">-</td><td class="description">16</td></tr><tr class="even"><td class="value">0x1C7847EB8CF1</td><td class="name">-</td><td class="description">24</td></tr></tbody></table></li>
<li id="UOTGHS_SFR__VBUSTIS"><strong>VBUSTIS</strong>: VBus Transition Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_SFR__SRPIS"><strong>SRPIS</strong>: SRP Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_SFR__VBERRIS"><strong>VBERRIS</strong>: VBus Error Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_SFR__BCERRIS"><strong>BCERRIS</strong>: B-Connection Error Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_SFR__ROLEEXIS"><strong>ROLEEXIS</strong>: Role Exchange Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_SFR__HNPERRIS"><strong>HNPERRIS</strong>: HNP Error Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_SFR__STOIS"><strong>STOIS</strong>: Suspend Time-Out Interrupt Set</li>
<p>-</p>
<li id="UOTGHS_SFR__VBUSRQS"><strong>VBUSRQS</strong>: VBus Request Set</li>
<p>-</p>
</ul>
<h4 id="UOTGHS_FSM">UOTGHS General Finite State Machine Register</h4>
<p><strong>Name</strong>: UOTGHS_FSM</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400AC82C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="4">
<a href="#UOTGHS_FSM__DRDSTATE" title="">DRDSTATE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UOTGHS_FSM__DRDSTATE">
<strong>DRDSTATE</strong>
<table class="values">
<thead>
<tr>
<th>Value</th>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="value">0x0</td>
<td class="name">A_IDLESTATE</td>
<td class="description">This is the start state for A-devices (when the ID pin is 0)</td>
</tr>
<tr class="even">
<td class="value">0x1</td>
<td class="name">A_WAIT_VRISE</td>
<td class="description">In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V).</td>
</tr>
<tr class="odd">
<td class="value">0x2</td>
<td class="name">A_WAIT_BCON</td>
<td class="description">In this state, the A-device waits for the B-device to signal a connection.</td>
</tr>
<tr class="even">
<td class="value">0x3</td>
<td class="name">A_HOST</td>
<td class="description">In this state, the A-device that operates in Host mode is operational.</td>
</tr>
<tr class="odd">
<td class="value">0x4</td>
<td class="name">A_SUSPEND</td>
<td class="description">The A-device operating as a host is in the suspend mode.</td>
</tr>
<tr class="even">
<td class="value">0x5</td>
<td class="name">A_PERIPHERAL</td>
<td class="description">The A-device operates as a peripheral.</td>
</tr>
<tr class="odd">
<td class="value">0x6</td>
<td class="name">A_WAIT_VFALL</td>
<td class="description">In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V).</td>
</tr>
<tr class="even">
<td class="value">0x7</td>
<td class="name">A_VBUS_ERR</td>
<td class="description">In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state.</td>
</tr>
<tr class="odd">
<td class="value">0x8</td>
<td class="name">A_WAIT_DISCHARGE</td>
<td class="description">In this state, the A-device waits for the data USB line to discharge (100 us).</td>
</tr>
<tr class="even">
<td class="value">0x9</td>
<td class="name">B_IDLE</td>
<td class="description">This is the start state for B-device (when the ID pin is 1).</td>
</tr>
<tr class="odd">
<td class="value">0xA</td>
<td class="name">B_PERIPHERAL</td>
<td class="description">In this state, the B-device acts as the peripheral.</td>
</tr>
<tr class="even">
<td class="value">0xB</td>
<td class="name">B_WAIT_BEGIN_HNP</td>
<td class="description">In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested.</td>
</tr>
<tr class="odd">
<td class="value">0xC</td>
<td class="name">B_WAIT_DISCHARGE</td>
<td class="description">In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host.</td>
</tr>
<tr class="even">
<td class="value">0xD</td>
<td class="name">B_WAIT_ACON</td>
<td class="description">In this state, the B-device waits for the A-device to signal a connect before becoming B-Host.</td>
</tr>
<tr class="odd">
<td class="value">0xE</td>
<td class="name">B_HOST</td>
<td class="description">In this state, the B-device acts as the Host.</td>
</tr>
<tr class="even">
<td class="value">0xF</td>
<td class="name">B_SRP_INIT</td>
<td class="description">In this state, the B-device attempts to start a session using the SRP protocol.</td>
</tr>
</tbody>
</table>
</li>
</ul>
</div>
</div>
</body>
</html>