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| <title>SAM3XA SPI0</title> |
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| </head> |
| <body id="abstract"> |
| <div id="container"> |
| <div id="content"> |
| <a id="SPI0"></a> |
| <h1>SAM3XA SPI0</h1> |
| <a id="SPI0__User_Interface"></a> |
| <h2>Serial Peripheral Interface (SPI0) User Interface</h2> |
| <!--As per 6088R programmer datasheet.--> |
| <h3>Registers</h3> |
| <table class="registers"> |
| <caption>Register Mapping</caption> |
| <thead> |
| <tr> |
| <th class="address">Address</th> |
| <th class="description">Register</th> |
| <th class="name">Name</th> |
| <th class="access">Access</th> |
| <th class="reset">Reset</th> |
| </tr> |
| </thead> |
| <tbody> |
| <tr class="odd"> |
| <td class="address" id="address_0x40008000">0x40008000</td> |
| <td class="description">Control Register</td> |
| <td class="name"> |
| <a href="#SPI0_CR" title="Control Register" class="one_click_away">SPI0_CR</a> |
| </td> |
| <td class="access">write-only</td> |
| <td class="address">-</td> |
| </tr> |
| <tr class="even"> |
| <td class="address" id="address_0x40008004">0x40008004</td> |
| <td class="description">Mode Register</td> |
| <td class="name"> |
| <a href="#SPI0_MR" title="Mode Register" class="one_click_away">SPI0_MR</a> |
| </td> |
| <td class="access">read-write</td> |
| <td class="address">0x00000000</td> |
| </tr> |
| <tr class="odd"> |
| <td class="address" id="address_0x40008008">0x40008008</td> |
| <td class="description">Receive Data Register</td> |
| <td class="name"> |
| <a href="#SPI0_RDR" title="Receive Data Register" class="one_click_away">SPI0_RDR</a> |
| </td> |
| <td class="access">read-only</td> |
| <td class="address">0x00000000</td> |
| </tr> |
| <tr class="even"> |
| <td class="address" id="address_0x4000800C">0x4000800C</td> |
| <td class="description">Transmit Data Register</td> |
| <td class="name"> |
| <a href="#SPI0_TDR" title="Transmit Data Register" class="one_click_away">SPI0_TDR</a> |
| </td> |
| <td class="access">write-only</td> |
| <td class="address">-</td> |
| </tr> |
| <tr class="odd"> |
| <td class="address" id="address_0x40008010">0x40008010</td> |
| <td class="description">Status Register</td> |
| <td class="name"> |
| <a href="#SPI0_SR" title="Status Register" class="one_click_away">SPI0_SR</a> |
| </td> |
| <td class="access">read-only</td> |
| <td class="address">0x000000F0</td> |
| </tr> |
| <tr class="even"> |
| <td class="address" id="address_0x40008014">0x40008014</td> |
| <td class="description">Interrupt Enable Register</td> |
| <td class="name"> |
| <a href="#SPI0_IER" title="Interrupt Enable Register" class="one_click_away">SPI0_IER</a> |
| </td> |
| <td class="access">write-only</td> |
| <td class="address">-</td> |
| </tr> |
| <tr class="odd"> |
| <td class="address" id="address_0x40008018">0x40008018</td> |
| <td class="description">Interrupt Disable Register</td> |
| <td class="name"> |
| <a href="#SPI0_IDR" title="Interrupt Disable Register" class="one_click_away">SPI0_IDR</a> |
| </td> |
| <td class="access">write-only</td> |
| <td class="address">-</td> |
| </tr> |
| <tr class="even"> |
| <td class="address" id="address_0x4000801C">0x4000801C</td> |
| <td class="description">Interrupt Mask Register</td> |
| <td class="name"> |
| <a href="#SPI0_IMR" title="Interrupt Mask Register" class="one_click_away">SPI0_IMR</a> |
| </td> |
| <td class="access">read-only</td> |
| <td class="address">0x00000000</td> |
| </tr> |
| <tr class="odd"> |
| <td class="address" id="address_0x40008030">0x40008030</td> |
| <td class="description">Chip Select Register</td> |
| <td class="name"> |
| <a href="#SPI0_CSR" title="Chip Select Register" class="one_click_away">SPI0_CSR[4]</a> |
| </td> |
| <td class="access">read-write</td> |
| <td class="address">0x0</td> |
| </tr> |
| <tr class="even"> |
| <td class="address" id="address_0x400080E4">0x400080E4</td> |
| <td class="description">Write Protection Control Register</td> |
| <td class="name"> |
| <a href="#SPI0_WPMR" title="Write Protection Control Register" class="one_click_away">SPI0_WPMR</a> |
| </td> |
| <td class="access">read-write</td> |
| <td class="address">0x00000000</td> |
| </tr> |
| <tr class="odd"> |
| <td class="address" id="address_0x400080E8">0x400080E8</td> |
| <td class="description">Write Protection Status Register</td> |
| <td class="name"> |
| <a href="#SPI0_WPSR" title="Write Protection Status Register" class="one_click_away">SPI0_WPSR</a> |
| </td> |
| <td class="access">read-only</td> |
| <td class="address">0x00000000</td> |
| </tr> |
| </tbody> |
| </table> |
| <h3>Register Fields</h3> |
| <h4 id="SPI0_CR">SPI0 Control Register</h4> |
| <p><strong>Name</strong>: SPI0_CR</p> |
| <p><strong>Access</strong>: write-only</p> |
| <p><strong>Address</strong>: 0x40008000</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_CR__LASTXFER" title="Last Transfer">LASTXFER</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="1"> |
| <a href="#SPI0_CR__SWRST" title="SPI Software Reset">SWRST</a> |
| </td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_CR__SPIDIS" title="SPI Disable">SPIDIS</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_CR__SPIEN" title="SPI Enable">SPIEN</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="SPI0_CR__SPIEN"><strong>SPIEN</strong>: SPI Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the SPI to transfer and receive data.</td></tr></tbody></table></li> |
| <li id="SPI0_CR__SPIDIS"><strong>SPIDIS</strong>: SPI Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the SPI.</td></tr></tbody></table></li> |
| <li id="SPI0_CR__SWRST"><strong>SWRST</strong>: SPI Software Reset<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.</td></tr></tbody></table></li> |
| <li id="SPI0_CR__LASTXFER"><strong>LASTXFER</strong>: Last Transfer<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.</td></tr></tbody></table></li> |
| </ul> |
| <h4 id="SPI0_MR">SPI0 Mode Register</h4> |
| <p><strong>Name</strong>: SPI0_MR</p> |
| <p><strong>Access</strong>: read-write</p> |
| <p><strong>Address</strong>: 0x40008004</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#SPI0_MR__DLYBCS" title="Delay Between Chip Selects">DLYBCS</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="4"> |
| <a href="#SPI0_MR__PCS" title="Peripheral Chip Select">PCS</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="1"> |
| <a href="#SPI0_MR__LLB" title="Local Loopback Enable">LLB</a> |
| </td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_MR__WDRBT" title="Wait Data Read Before Transfer">WDRBT</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_MR__MODFDIS" title="Mode Fault Detection">MODFDIS</a> |
| </td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_MR__PCSDEC" title="Chip Select Decode">PCSDEC</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_MR__PS" title="Peripheral Select">PS</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_MR__MSTR" title="Master/Slave Mode">MSTR</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="SPI0_MR__MSTR"><strong>MSTR</strong>: Master/Slave Mode<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">SPI is in Slave mode.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">SPI is in Master mode.</td></tr></tbody></table></li> |
| <li id="SPI0_MR__PS"><strong>PS</strong>: Peripheral Select<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Fixed Peripheral Select.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Variable Peripheral Select.</td></tr></tbody></table></li> |
| <li id="SPI0_MR__PCSDEC"><strong>PCSDEC</strong>: Chip Select Decode<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The chip selects are directly connected to a peripheral device.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The four chip select lines are connected to a 4- to 16-bit decoder.</td></tr></tbody></table></li> |
| <li id="SPI0_MR__MODFDIS"><strong>MODFDIS</strong>: Mode Fault Detection<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Mode fault detection is enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Mode fault detection is disabled.</td></tr></tbody></table></li> |
| <li id="SPI0_MR__WDRBT"><strong>WDRBT</strong>: Wait Data Read Before Transfer<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No Effect. In master mode, a transfer can be initiated whatever the state of the Receive Data Register is.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">In Master Mode, a transfer can start only if the Receive Data Register is empty, i.e. does not contain any unread data. This mode prevents overrun error in reception.</td></tr></tbody></table></li> |
| <li id="SPI0_MR__LLB"><strong>LLB</strong>: Local Loopback Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Local loopback path disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Local loopback path enabled</td></tr></tbody></table></li> |
| <li id="SPI0_MR__PCS"><strong>PCS</strong>: Peripheral Chip Select</li> |
| <p>-</p> |
| <li id="SPI0_MR__DLYBCS"><strong>DLYBCS</strong>: Delay Between Chip Selects</li> |
| <p>-</p> |
| </ul> |
| <h4 id="SPI0_RDR">SPI0 Receive Data Register</h4> |
| <p><strong>Name</strong>: SPI0_RDR</p> |
| <p><strong>Access</strong>: read-only</p> |
| <p><strong>Address</strong>: 0x40008008</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="4"> |
| <a href="#SPI0_RDR__PCS" title="Peripheral Chip Select">PCS</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#SPI0_RDR__RD" title="Receive Data">RD</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#SPI0_RDR__RD" title="Receive Data">RD</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="SPI0_RDR__RD"><strong>RD</strong>: Receive Data</li> |
| <p>-</p> |
| <li id="SPI0_RDR__PCS"><strong>PCS</strong>: Peripheral Chip Select</li> |
| <p>-</p> |
| </ul> |
| <h4 id="SPI0_TDR">SPI0 Transmit Data Register</h4> |
| <p><strong>Name</strong>: SPI0_TDR</p> |
| <p><strong>Access</strong>: write-only</p> |
| <p><strong>Address</strong>: 0x4000800C</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_TDR__LASTXFER" title="Last Transfer">LASTXFER</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="4"> |
| <a href="#SPI0_TDR__PCS" title="Peripheral Chip Select">PCS</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#SPI0_TDR__TD" title="Transmit Data">TD</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#SPI0_TDR__TD" title="Transmit Data">TD</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="SPI0_TDR__TD"><strong>TD</strong>: Transmit Data</li> |
| <p>-</p> |
| <li id="SPI0_TDR__PCS"><strong>PCS</strong>: Peripheral Chip Select</li> |
| <p>-</p> |
| <li id="SPI0_TDR__LASTXFER"><strong>LASTXFER</strong>: Last Transfer<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.</td></tr></tbody></table></li> |
| </ul> |
| <h4 id="SPI0_SR">SPI0 Status Register</h4> |
| <p><strong>Name</strong>: SPI0_SR</p> |
| <p><strong>Access</strong>: read-only</p> |
| <p><strong>Address</strong>: 0x40008010</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_SR__SPIENS" title="SPI Enable Status">SPIENS</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_SR__UNDES" title="Underrun Error Status (Slave Mode Only)">UNDES</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_SR__TXEMPTY" title="Transmission Registers Empty">TXEMPTY</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_SR__NSSR" title="NSS Rising">NSSR</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_SR__OVRES" title="Overrun Error Status">OVRES</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_SR__MODF" title="Mode Fault Error">MODF</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_SR__TDRE" title="Transmit Data Register Empty">TDRE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_SR__RDRF" title="Receive Data Register Full">RDRF</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="SPI0_SR__RDRF"><strong>RDRF</strong>: Receive Data Register Full<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No data has been received since the last read of SPI_RDR</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR.</td></tr></tbody></table></li> |
| <li id="SPI0_SR__TDRE"><strong>TDRE</strong>: Transmit Data Register Empty<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Data has been written to SPI_TDR and not yet transferred to the serializer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The last data written in the Transmit Data Register has been transferred to the serializer.</td></tr></tbody></table></li> |
| <li id="SPI0_SR__MODF"><strong>MODF</strong>: Mode Fault Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No Mode Fault has been detected since the last read of SPI_SR.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">A Mode Fault occurred since the last read of the SPI_SR.</td></tr></tbody></table></li> |
| <li id="SPI0_SR__OVRES"><strong>OVRES</strong>: Overrun Error Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No overrun has been detected since the last read of SPI_SR.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">An overrun has occurred since the last read of SPI_SR.</td></tr></tbody></table></li> |
| <li id="SPI0_SR__NSSR"><strong>NSSR</strong>: NSS Rising<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No rising edge detected on NSS pin since last read.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">A rising edge occurred on NSS pin since last read.</td></tr></tbody></table></li> |
| <li id="SPI0_SR__TXEMPTY"><strong>TXEMPTY</strong>: Transmission Registers Empty<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">As soon as data is written in SPI_TDR.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.</td></tr></tbody></table></li> |
| <li id="SPI0_SR__UNDES"><strong>UNDES</strong>: Underrun Error Status (Slave Mode Only)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No underrun has been detected since the last read of SPI_SR.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">A transfer begins whereas no data has been loaded in the Transmit Data Register.</td></tr></tbody></table></li> |
| <li id="SPI0_SR__SPIENS"><strong>SPIENS</strong>: SPI Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">SPI is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">SPI is enabled.</td></tr></tbody></table></li> |
| </ul> |
| <h4 id="SPI0_IER">SPI0 Interrupt Enable Register</h4> |
| <p><strong>Name</strong>: SPI0_IER</p> |
| <p><strong>Access</strong>: write-only</p> |
| <p><strong>Address</strong>: 0x40008014</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_IER__UNDES" title="Underrun Error Interrupt Enable">UNDES</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IER__TXEMPTY" title="Transmission Registers Empty Enable">TXEMPTY</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IER__NSSR" title="NSS Rising Interrupt Enable">NSSR</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_IER__OVRES" title="Overrun Error Interrupt Enable">OVRES</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IER__MODF" title="Mode Fault Error Interrupt Enable">MODF</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IER__TDRE" title="SPI Transmit Data Register Empty Interrupt Enable">TDRE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IER__RDRF" title="Receive Data Register Full Interrupt Enable">RDRF</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="SPI0_IER__RDRF"><strong>RDRF</strong>: Receive Data Register Full Interrupt Enable</li> |
| <p>-</p> |
| <li id="SPI0_IER__TDRE"><strong>TDRE</strong>: SPI Transmit Data Register Empty Interrupt Enable</li> |
| <p>-</p> |
| <li id="SPI0_IER__MODF"><strong>MODF</strong>: Mode Fault Error Interrupt Enable</li> |
| <p>-</p> |
| <li id="SPI0_IER__OVRES"><strong>OVRES</strong>: Overrun Error Interrupt Enable</li> |
| <p>-</p> |
| <li id="SPI0_IER__NSSR"><strong>NSSR</strong>: NSS Rising Interrupt Enable</li> |
| <p>-</p> |
| <li id="SPI0_IER__TXEMPTY"><strong>TXEMPTY</strong>: Transmission Registers Empty Enable</li> |
| <p>-</p> |
| <li id="SPI0_IER__UNDES"><strong>UNDES</strong>: Underrun Error Interrupt Enable</li> |
| <p>-</p> |
| </ul> |
| <h4 id="SPI0_IDR">SPI0 Interrupt Disable Register</h4> |
| <p><strong>Name</strong>: SPI0_IDR</p> |
| <p><strong>Access</strong>: write-only</p> |
| <p><strong>Address</strong>: 0x40008018</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_IDR__UNDES" title="Underrun Error Interrupt Disable">UNDES</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IDR__TXEMPTY" title="Transmission Registers Empty Disable">TXEMPTY</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IDR__NSSR" title="NSS Rising Interrupt Disable">NSSR</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_IDR__OVRES" title="Overrun Error Interrupt Disable">OVRES</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IDR__MODF" title="Mode Fault Error Interrupt Disable">MODF</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IDR__TDRE" title="SPI Transmit Data Register Empty Interrupt Disable">TDRE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IDR__RDRF" title="Receive Data Register Full Interrupt Disable">RDRF</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="SPI0_IDR__RDRF"><strong>RDRF</strong>: Receive Data Register Full Interrupt Disable</li> |
| <p>-</p> |
| <li id="SPI0_IDR__TDRE"><strong>TDRE</strong>: SPI Transmit Data Register Empty Interrupt Disable</li> |
| <p>-</p> |
| <li id="SPI0_IDR__MODF"><strong>MODF</strong>: Mode Fault Error Interrupt Disable</li> |
| <p>-</p> |
| <li id="SPI0_IDR__OVRES"><strong>OVRES</strong>: Overrun Error Interrupt Disable</li> |
| <p>-</p> |
| <li id="SPI0_IDR__NSSR"><strong>NSSR</strong>: NSS Rising Interrupt Disable</li> |
| <p>-</p> |
| <li id="SPI0_IDR__TXEMPTY"><strong>TXEMPTY</strong>: Transmission Registers Empty Disable</li> |
| <p>-</p> |
| <li id="SPI0_IDR__UNDES"><strong>UNDES</strong>: Underrun Error Interrupt Disable</li> |
| <p>-</p> |
| </ul> |
| <h4 id="SPI0_IMR">SPI0 Interrupt Mask Register</h4> |
| <p><strong>Name</strong>: SPI0_IMR</p> |
| <p><strong>Access</strong>: read-only</p> |
| <p><strong>Address</strong>: 0x4000801C</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_IMR__UNDES" title="Underrun Error Interrupt Mask">UNDES</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IMR__TXEMPTY" title="Transmission Registers Empty Mask">TXEMPTY</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IMR__NSSR" title="NSS Rising Interrupt Mask">NSSR</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_IMR__OVRES" title="Overrun Error Interrupt Mask">OVRES</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IMR__MODF" title="Mode Fault Error Interrupt Mask">MODF</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IMR__TDRE" title="SPI Transmit Data Register Empty Interrupt Mask">TDRE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_IMR__RDRF" title="Receive Data Register Full Interrupt Mask">RDRF</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="SPI0_IMR__RDRF"><strong>RDRF</strong>: Receive Data Register Full Interrupt Mask</li> |
| <p>-</p> |
| <li id="SPI0_IMR__TDRE"><strong>TDRE</strong>: SPI Transmit Data Register Empty Interrupt Mask</li> |
| <p>-</p> |
| <li id="SPI0_IMR__MODF"><strong>MODF</strong>: Mode Fault Error Interrupt Mask</li> |
| <p>-</p> |
| <li id="SPI0_IMR__OVRES"><strong>OVRES</strong>: Overrun Error Interrupt Mask</li> |
| <p>-</p> |
| <li id="SPI0_IMR__NSSR"><strong>NSSR</strong>: NSS Rising Interrupt Mask</li> |
| <p>-</p> |
| <li id="SPI0_IMR__TXEMPTY"><strong>TXEMPTY</strong>: Transmission Registers Empty Mask</li> |
| <p>-</p> |
| <li id="SPI0_IMR__UNDES"><strong>UNDES</strong>: Underrun Error Interrupt Mask</li> |
| <p>-</p> |
| </ul> |
| <h4 id="SPI0_CSR">SPI0 Chip Select Register</h4> |
| <p><strong>Name</strong>: SPI0_CSR[0:3]</p> |
| <p><strong>Access</strong>: read-write</p> |
| <p><strong>Address</strong>: 0x40008030</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#SPI0_CSR__DLYBCT" title="Delay Between Consecutive Transfers">DLYBCT</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#SPI0_CSR__DLYBS" title="Delay Before SPCK">DLYBS</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#SPI0_CSR__SCBR" title="Serial Clock Baud Rate">SCBR</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="4"> |
| <a href="#SPI0_CSR__BITS" title="Bits Per Transfer">BITS</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_CSR__CSAAT" title="Chip Select Not Active After Transfer (Ignored if CSAAT = 1)">CSAAT</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_CSR__CSNAAT" title="Chip Select Not Active After Transfer (Ignored if CSAAT = 1)">CSNAAT</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_CSR__NCPHA" title="Clock Phase">NCPHA</a> |
| </td> |
| <td colspan="1"> |
| <a href="#SPI0_CSR__CPOL" title="Clock Polarity">CPOL</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="SPI0_CSR__CPOL"><strong>CPOL</strong>: Clock Polarity<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The inactive state value of SPCK is logic level zero.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The inactive state value of SPCK is logic level one.</td></tr></tbody></table></li> |
| <li id="SPI0_CSR__NCPHA"><strong>NCPHA</strong>: Clock Phase<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.</td></tr></tbody></table></li> |
| <li id="SPI0_CSR__CSNAAT"><strong>CSNAAT</strong>: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The Peripheral Chip Select rises systematically after each transfer performed on the same slave. It remains active after the end of transfer for a minimal duration of:</td></tr></tbody></table></li> |
| <li id="SPI0_CSR__CSAAT"><strong>CSAAT</strong>: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The Peripheral Chip Select rises systematically after each transfer performed on the same slave. It remains active after the end of transfer for a minimal duration of:</td></tr></tbody></table></li> |
| <li id="SPI0_CSR__BITS"><strong>BITS</strong>: Bits Per Transfer<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">8_BIT</td><td class="description">8 bits for transfer</td></tr><tr class="even"><td class="value">0x1</td><td class="name">9_BIT</td><td class="description">9 bits for transfer</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">10_BIT</td><td class="description">10 bits for transfer</td></tr><tr class="even"><td class="value">0x3</td><td class="name">11_BIT</td><td class="description">11 bits for transfer</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">12_BIT</td><td class="description">12 bits for transfer</td></tr><tr class="even"><td class="value">0x5</td><td class="name">13_BIT</td><td class="description">13 bits for transfer</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">14_BIT</td><td class="description">14 bits for transfer</td></tr><tr class="even"><td class="value">0x7</td><td class="name">15_BIT</td><td class="description">15 bits for transfer</td></tr><tr class="odd"><td class="value">0x8</td><td class="name">16_BIT</td><td class="description">16 bits for transfer</td></tr></tbody></table></li> |
| <li id="SPI0_CSR__SCBR"><strong>SCBR</strong>: Serial Clock Baud Rate</li> |
| <p>-</p> |
| <li id="SPI0_CSR__DLYBS"><strong>DLYBS</strong>: Delay Before SPCK</li> |
| <p>-</p> |
| <li id="SPI0_CSR__DLYBCT"><strong>DLYBCT</strong>: Delay Between Consecutive Transfers</li> |
| <p>-</p> |
| </ul> |
| <h4 id="SPI0_WPMR">SPI0 Write Protection Control Register</h4> |
| <p><strong>Name</strong>: SPI0_WPMR</p> |
| <p><strong>Access</strong>: read-write</p> |
| <p><strong>Address</strong>: 0x400080E4</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#SPI0_WPMR__WPKEY" title="Write Protection Key Password">WPKEY</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#SPI0_WPMR__WPKEY" title="Write Protection Key Password">WPKEY</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#SPI0_WPMR__WPKEY" title="Write Protection Key Password">WPKEY</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_WPMR__WPEN" title="Write Protection Enable">WPEN</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="SPI0_WPMR__WPEN"><strong>WPEN</strong>: Write Protection Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The Write Protection is Disabled</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The Write Protection is Enabled</td></tr></tbody></table></li> |
| <li id="SPI0_WPMR__WPKEY"><strong>WPKEY</strong>: Write Protection Key Password</li> |
| <p>-</p> |
| </ul> |
| <h4 id="SPI0_WPSR">SPI0 Write Protection Status Register</h4> |
| <p><strong>Name</strong>: SPI0_WPSR</p> |
| <p><strong>Access</strong>: read-only</p> |
| <p><strong>Address</strong>: 0x400080E8</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#SPI0_WPSR__WPVSRC" title="Write Protection Violation Source">WPVSRC</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#SPI0_WPSR__WPVS" title="Write Protection Violation Status">WPVS</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="SPI0_WPSR__WPVS"><strong>WPVS</strong>: Write Protection Violation Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No Write Protect Violation has occurred since the last read of the SPI_WPSR register.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">A Write Protect Violation has occurred since the last read of the SPI_WPSR register. If this violation is an unauthorized</td></tr></tbody></table></li> |
| <li id="SPI0_WPSR__WPVSRC"><strong>WPVSRC</strong>: Write Protection Violation Source</li> |
| <p>-</p> |
| </ul> |
| </div> |
| </div> |
| </body> |
| </html> |
