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android / platform / external / arduino-ide / f876b2abdebd02acfa4ba21e607327be4f9668d4 / . / hardware / arduino / sam / system / CMSIS / Device / ATMEL / sam3xa / html / DMAC.html
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8" />
<title>SAM3XA DMAC</title>
<link rel="stylesheet" type="text/css" href="css/html.css" media="all" />
</head>
<body id="abstract">
<div id="container">
<div id="content">
<a id="DMAC"></a>
<h1>SAM3XA DMAC</h1>
<a id="DMAC__User_Interface"></a>
<h2>DMA Controller (DMAC) User Interface</h2>
<!--As per 6233L programmer datasheet.-->
<h3>Registers</h3>
<table class="registers">
<caption>Register Mapping</caption>
<thead>
<tr>
<th class="address">Address</th>
<th class="description">Register</th>
<th class="name">Name</th>
<th class="access">Access</th>
<th class="reset">Reset</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="address" id="address_0x400C4000">0x400C4000</td>
<td class="description">DMAC Global Configuration Register</td>
<td class="name">
<a href="#DMAC_GCFG" title="DMAC Global Configuration Register" class="one_click_away">DMAC_GCFG</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000010</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4004">0x400C4004</td>
<td class="description">DMAC Enable Register</td>
<td class="name">
<a href="#DMAC_EN" title="DMAC Enable Register" class="one_click_away">DMAC_EN</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C4008">0x400C4008</td>
<td class="description">DMAC Software Single Request Register</td>
<td class="name">
<a href="#DMAC_SREQ" title="DMAC Software Single Request Register" class="one_click_away">DMAC_SREQ</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C400C">0x400C400C</td>
<td class="description">DMAC Software Chunk Transfer Request Register</td>
<td class="name">
<a href="#DMAC_CREQ" title="DMAC Software Chunk Transfer Request Register" class="one_click_away">DMAC_CREQ</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C4010">0x400C4010</td>
<td class="description">DMAC Software Last Transfer Flag Register</td>
<td class="name">
<a href="#DMAC_LAST" title="DMAC Software Last Transfer Flag Register" class="one_click_away">DMAC_LAST</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4018">0x400C4018</td>
<td class="description">DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.</td>
<td class="name">
<a href="#DMAC_EBCIER" title="DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register." class="one_click_away">DMAC_EBCIER</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C401C">0x400C401C</td>
<td class="description">DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.</td>
<td class="name">
<a href="#DMAC_EBCIDR" title="DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register." class="one_click_away">DMAC_EBCIDR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4020">0x400C4020</td>
<td class="description">DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.</td>
<td class="name">
<a href="#DMAC_EBCIMR" title="DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register." class="one_click_away">DMAC_EBCIMR</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C4024">0x400C4024</td>
<td class="description">DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.</td>
<td class="name">
<a href="#DMAC_EBCISR" title="DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register." class="one_click_away">DMAC_EBCISR</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4028">0x400C4028</td>
<td class="description">DMAC Channel Handler Enable Register</td>
<td class="name">
<a href="#DMAC_CHER" title="DMAC Channel Handler Enable Register" class="one_click_away">DMAC_CHER</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C402C">0x400C402C</td>
<td class="description">DMAC Channel Handler Disable Register</td>
<td class="name">
<a href="#DMAC_CHDR" title="DMAC Channel Handler Disable Register" class="one_click_away">DMAC_CHDR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4030">0x400C4030</td>
<td class="description">DMAC Channel Handler Status Register</td>
<td class="name">
<a href="#DMAC_CHSR" title="DMAC Channel Handler Status Register" class="one_click_away">DMAC_CHSR</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00FF0000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C403C">0x400C403C</td>
<td class="description">DMAC Channel Source Address Register (ch_num = 0)</td>
<td class="name">
<a href="#DMAC_SADDR0" title="DMAC Channel Source Address Register (ch_num = 0)" class="one_click_away">DMAC_SADDR0</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4040">0x400C4040</td>
<td class="description">DMAC Channel Destination Address Register (ch_num = 0)</td>
<td class="name">
<a href="#DMAC_DADDR0" title="DMAC Channel Destination Address Register (ch_num = 0)" class="one_click_away">DMAC_DADDR0</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C4044">0x400C4044</td>
<td class="description">DMAC Channel Descriptor Address Register (ch_num = 0)</td>
<td class="name">
<a href="#DMAC_DSCR0" title="DMAC Channel Descriptor Address Register (ch_num = 0)" class="one_click_away">DMAC_DSCR0</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4048">0x400C4048</td>
<td class="description">DMAC Channel Control A Register (ch_num = 0)</td>
<td class="name">
<a href="#DMAC_CTRLA0" title="DMAC Channel Control A Register (ch_num = 0)" class="one_click_away">DMAC_CTRLA0</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C404C">0x400C404C</td>
<td class="description">DMAC Channel Control B Register (ch_num = 0)</td>
<td class="name">
<a href="#DMAC_CTRLB0" title="DMAC Channel Control B Register (ch_num = 0)" class="one_click_away">DMAC_CTRLB0</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4050">0x400C4050</td>
<td class="description">DMAC Channel Configuration Register (ch_num = 0)</td>
<td class="name">
<a href="#DMAC_CFG0" title="DMAC Channel Configuration Register (ch_num = 0)" class="one_click_away">DMAC_CFG0</a>
</td>
<td class="access">read-write</td>
<td class="address">0x01000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C4064">0x400C4064</td>
<td class="description">DMAC Channel Source Address Register (ch_num = 1)</td>
<td class="name">
<a href="#DMAC_SADDR1" title="DMAC Channel Source Address Register (ch_num = 1)" class="one_click_away">DMAC_SADDR1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4068">0x400C4068</td>
<td class="description">DMAC Channel Destination Address Register (ch_num = 1)</td>
<td class="name">
<a href="#DMAC_DADDR1" title="DMAC Channel Destination Address Register (ch_num = 1)" class="one_click_away">DMAC_DADDR1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C406C">0x400C406C</td>
<td class="description">DMAC Channel Descriptor Address Register (ch_num = 1)</td>
<td class="name">
<a href="#DMAC_DSCR1" title="DMAC Channel Descriptor Address Register (ch_num = 1)" class="one_click_away">DMAC_DSCR1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4070">0x400C4070</td>
<td class="description">DMAC Channel Control A Register (ch_num = 1)</td>
<td class="name">
<a href="#DMAC_CTRLA1" title="DMAC Channel Control A Register (ch_num = 1)" class="one_click_away">DMAC_CTRLA1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C4074">0x400C4074</td>
<td class="description">DMAC Channel Control B Register (ch_num = 1)</td>
<td class="name">
<a href="#DMAC_CTRLB1" title="DMAC Channel Control B Register (ch_num = 1)" class="one_click_away">DMAC_CTRLB1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4078">0x400C4078</td>
<td class="description">DMAC Channel Configuration Register (ch_num = 1)</td>
<td class="name">
<a href="#DMAC_CFG1" title="DMAC Channel Configuration Register (ch_num = 1)" class="one_click_away">DMAC_CFG1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x01000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C408C">0x400C408C</td>
<td class="description">DMAC Channel Source Address Register (ch_num = 2)</td>
<td class="name">
<a href="#DMAC_SADDR2" title="DMAC Channel Source Address Register (ch_num = 2)" class="one_click_away">DMAC_SADDR2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4090">0x400C4090</td>
<td class="description">DMAC Channel Destination Address Register (ch_num = 2)</td>
<td class="name">
<a href="#DMAC_DADDR2" title="DMAC Channel Destination Address Register (ch_num = 2)" class="one_click_away">DMAC_DADDR2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C4094">0x400C4094</td>
<td class="description">DMAC Channel Descriptor Address Register (ch_num = 2)</td>
<td class="name">
<a href="#DMAC_DSCR2" title="DMAC Channel Descriptor Address Register (ch_num = 2)" class="one_click_away">DMAC_DSCR2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4098">0x400C4098</td>
<td class="description">DMAC Channel Control A Register (ch_num = 2)</td>
<td class="name">
<a href="#DMAC_CTRLA2" title="DMAC Channel Control A Register (ch_num = 2)" class="one_click_away">DMAC_CTRLA2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C409C">0x400C409C</td>
<td class="description">DMAC Channel Control B Register (ch_num = 2)</td>
<td class="name">
<a href="#DMAC_CTRLB2" title="DMAC Channel Control B Register (ch_num = 2)" class="one_click_away">DMAC_CTRLB2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C40A0">0x400C40A0</td>
<td class="description">DMAC Channel Configuration Register (ch_num = 2)</td>
<td class="name">
<a href="#DMAC_CFG2" title="DMAC Channel Configuration Register (ch_num = 2)" class="one_click_away">DMAC_CFG2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x01000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C40B4">0x400C40B4</td>
<td class="description">DMAC Channel Source Address Register (ch_num = 3)</td>
<td class="name">
<a href="#DMAC_SADDR3" title="DMAC Channel Source Address Register (ch_num = 3)" class="one_click_away">DMAC_SADDR3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C40B8">0x400C40B8</td>
<td class="description">DMAC Channel Destination Address Register (ch_num = 3)</td>
<td class="name">
<a href="#DMAC_DADDR3" title="DMAC Channel Destination Address Register (ch_num = 3)" class="one_click_away">DMAC_DADDR3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C40BC">0x400C40BC</td>
<td class="description">DMAC Channel Descriptor Address Register (ch_num = 3)</td>
<td class="name">
<a href="#DMAC_DSCR3" title="DMAC Channel Descriptor Address Register (ch_num = 3)" class="one_click_away">DMAC_DSCR3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C40C0">0x400C40C0</td>
<td class="description">DMAC Channel Control A Register (ch_num = 3)</td>
<td class="name">
<a href="#DMAC_CTRLA3" title="DMAC Channel Control A Register (ch_num = 3)" class="one_click_away">DMAC_CTRLA3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C40C4">0x400C40C4</td>
<td class="description">DMAC Channel Control B Register (ch_num = 3)</td>
<td class="name">
<a href="#DMAC_CTRLB3" title="DMAC Channel Control B Register (ch_num = 3)" class="one_click_away">DMAC_CTRLB3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C40C8">0x400C40C8</td>
<td class="description">DMAC Channel Configuration Register (ch_num = 3)</td>
<td class="name">
<a href="#DMAC_CFG3" title="DMAC Channel Configuration Register (ch_num = 3)" class="one_click_away">DMAC_CFG3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x01000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C40DC">0x400C40DC</td>
<td class="description">DMAC Channel Source Address Register (ch_num = 4)</td>
<td class="name">
<a href="#DMAC_SADDR4" title="DMAC Channel Source Address Register (ch_num = 4)" class="one_click_away">DMAC_SADDR4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C40E0">0x400C40E0</td>
<td class="description">DMAC Channel Destination Address Register (ch_num = 4)</td>
<td class="name">
<a href="#DMAC_DADDR4" title="DMAC Channel Destination Address Register (ch_num = 4)" class="one_click_away">DMAC_DADDR4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C40E4">0x400C40E4</td>
<td class="description">DMAC Channel Descriptor Address Register (ch_num = 4)</td>
<td class="name">
<a href="#DMAC_DSCR4" title="DMAC Channel Descriptor Address Register (ch_num = 4)" class="one_click_away">DMAC_DSCR4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C40E8">0x400C40E8</td>
<td class="description">DMAC Channel Control A Register (ch_num = 4)</td>
<td class="name">
<a href="#DMAC_CTRLA4" title="DMAC Channel Control A Register (ch_num = 4)" class="one_click_away">DMAC_CTRLA4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C40EC">0x400C40EC</td>
<td class="description">DMAC Channel Control B Register (ch_num = 4)</td>
<td class="name">
<a href="#DMAC_CTRLB4" title="DMAC Channel Control B Register (ch_num = 4)" class="one_click_away">DMAC_CTRLB4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C40F0">0x400C40F0</td>
<td class="description">DMAC Channel Configuration Register (ch_num = 4)</td>
<td class="name">
<a href="#DMAC_CFG4" title="DMAC Channel Configuration Register (ch_num = 4)" class="one_click_away">DMAC_CFG4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x01000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C4104">0x400C4104</td>
<td class="description">DMAC Channel Source Address Register (ch_num = 5)</td>
<td class="name">
<a href="#DMAC_SADDR5" title="DMAC Channel Source Address Register (ch_num = 5)" class="one_click_away">DMAC_SADDR5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4108">0x400C4108</td>
<td class="description">DMAC Channel Destination Address Register (ch_num = 5)</td>
<td class="name">
<a href="#DMAC_DADDR5" title="DMAC Channel Destination Address Register (ch_num = 5)" class="one_click_away">DMAC_DADDR5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C410C">0x400C410C</td>
<td class="description">DMAC Channel Descriptor Address Register (ch_num = 5)</td>
<td class="name">
<a href="#DMAC_DSCR5" title="DMAC Channel Descriptor Address Register (ch_num = 5)" class="one_click_away">DMAC_DSCR5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4110">0x400C4110</td>
<td class="description">DMAC Channel Control A Register (ch_num = 5)</td>
<td class="name">
<a href="#DMAC_CTRLA5" title="DMAC Channel Control A Register (ch_num = 5)" class="one_click_away">DMAC_CTRLA5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C4114">0x400C4114</td>
<td class="description">DMAC Channel Control B Register (ch_num = 5)</td>
<td class="name">
<a href="#DMAC_CTRLB5" title="DMAC Channel Control B Register (ch_num = 5)" class="one_click_away">DMAC_CTRLB5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C4118">0x400C4118</td>
<td class="description">DMAC Channel Configuration Register (ch_num = 5)</td>
<td class="name">
<a href="#DMAC_CFG5" title="DMAC Channel Configuration Register (ch_num = 5)" class="one_click_away">DMAC_CFG5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x01000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400C41E4">0x400C41E4</td>
<td class="description">DMAC Write Protect Mode Register</td>
<td class="name">
<a href="#DMAC_WPMR" title="DMAC Write Protect Mode Register" class="one_click_away">DMAC_WPMR</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400C41E8">0x400C41E8</td>
<td class="description">DMAC Write Protect Status Register</td>
<td class="name">
<a href="#DMAC_WPSR" title="DMAC Write Protect Status Register" class="one_click_away">DMAC_WPSR</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
</tbody>
</table>
<h3>Register Fields</h3>
<h4 id="DMAC_GCFG">DMAC DMAC Global Configuration Register</h4>
<p><strong>Name</strong>: DMAC_GCFG</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4000</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_GCFG__ARB_CFG" title="Arbiter Configuration">ARB_CFG</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_GCFG__ARB_CFG"><strong>ARB_CFG</strong>: Arbiter Configuration<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">FIXED</td><td class="description">Fixed priority arbiter.</td></tr><tr class="even"><td class="value">1</td><td class="name">ROUND_ROBIN</td><td class="description">Modified round robin arbiter.</td></tr></tbody></table></li>
</ul>
<h4 id="DMAC_EN">DMAC DMAC Enable Register</h4>
<p><strong>Name</strong>: DMAC_EN</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4004</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_EN__ENABLE" title="">ENABLE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_EN__ENABLE">
<strong>ENABLE</strong>
<table class="values">
<thead>
<tr>
<th>Value</th>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="value">0</td>
<td class="name">-</td>
<td class="description">DMA Controller is disabled.</td>
</tr>
<tr class="even">
<td class="value">1</td>
<td class="name">-</td>
<td class="description">DMA Controller is enabled.</td>
</tr>
</tbody>
</table>
</li>
</ul>
<h4 id="DMAC_SREQ">DMAC DMAC Software Single Request Register</h4>
<p><strong>Name</strong>: DMAC_SREQ</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4008</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_SREQ__DSREQ5" title="Destination Request">DSREQ5</a>
</td>
<td colspan="1">
<a href="#DMAC_SREQ__SSREQ5" title="Source Request">SSREQ5</a>
</td>
<td colspan="1">
<a href="#DMAC_SREQ__DSREQ4" title="Destination Request">DSREQ4</a>
</td>
<td colspan="1">
<a href="#DMAC_SREQ__SSREQ4" title="Source Request">SSREQ4</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#DMAC_SREQ__DSREQ3" title="Destination Request">DSREQ3</a>
</td>
<td colspan="1">
<a href="#DMAC_SREQ__SSREQ3" title="Source Request">SSREQ3</a>
</td>
<td colspan="1">
<a href="#DMAC_SREQ__DSREQ2" title="Destination Request">DSREQ2</a>
</td>
<td colspan="1">
<a href="#DMAC_SREQ__SSREQ2" title="Source Request">SSREQ2</a>
</td>
<td colspan="1">
<a href="#DMAC_SREQ__DSREQ1" title="Destination Request">DSREQ1</a>
</td>
<td colspan="1">
<a href="#DMAC_SREQ__SSREQ1" title="Source Request">SSREQ1</a>
</td>
<td colspan="1">
<a href="#DMAC_SREQ__DSREQ0" title="Destination Request">DSREQ0</a>
</td>
<td colspan="1">
<a href="#DMAC_SREQ__SSREQ0" title="Source Request">SSREQ0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_SREQ__SSREQ0"><strong>SSREQ0</strong>: Source Request</li>
<p>-</p>
<li id="DMAC_SREQ__DSREQ0"><strong>DSREQ0</strong>: Destination Request</li>
<p>-</p>
<li id="DMAC_SREQ__SSREQ1"><strong>SSREQ1</strong>: Source Request</li>
<p>-</p>
<li id="DMAC_SREQ__DSREQ1"><strong>DSREQ1</strong>: Destination Request</li>
<p>-</p>
<li id="DMAC_SREQ__SSREQ2"><strong>SSREQ2</strong>: Source Request</li>
<p>-</p>
<li id="DMAC_SREQ__DSREQ2"><strong>DSREQ2</strong>: Destination Request</li>
<p>-</p>
<li id="DMAC_SREQ__SSREQ3"><strong>SSREQ3</strong>: Source Request</li>
<p>-</p>
<li id="DMAC_SREQ__DSREQ3"><strong>DSREQ3</strong>: Destination Request</li>
<p>-</p>
<li id="DMAC_SREQ__SSREQ4"><strong>SSREQ4</strong>: Source Request</li>
<p>-</p>
<li id="DMAC_SREQ__DSREQ4"><strong>DSREQ4</strong>: Destination Request</li>
<p>-</p>
<li id="DMAC_SREQ__SSREQ5"><strong>SSREQ5</strong>: Source Request</li>
<p>-</p>
<li id="DMAC_SREQ__DSREQ5"><strong>DSREQ5</strong>: Destination Request</li>
<p>-</p>
</ul>
<h4 id="DMAC_CREQ">DMAC DMAC Software Chunk Transfer Request Register</h4>
<p><strong>Name</strong>: DMAC_CREQ</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C400C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CREQ__DCREQ5" title="Destination Chunk Request">DCREQ5</a>
</td>
<td colspan="1">
<a href="#DMAC_CREQ__SCREQ5" title="Source Chunk Request">SCREQ5</a>
</td>
<td colspan="1">
<a href="#DMAC_CREQ__DCREQ4" title="Destination Chunk Request">DCREQ4</a>
</td>
<td colspan="1">
<a href="#DMAC_CREQ__SCREQ4" title="Source Chunk Request">SCREQ4</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#DMAC_CREQ__DCREQ3" title="Destination Chunk Request">DCREQ3</a>
</td>
<td colspan="1">
<a href="#DMAC_CREQ__SCREQ3" title="Source Chunk Request">SCREQ3</a>
</td>
<td colspan="1">
<a href="#DMAC_CREQ__DCREQ2" title="Destination Chunk Request">DCREQ2</a>
</td>
<td colspan="1">
<a href="#DMAC_CREQ__SCREQ2" title="Source Chunk Request">SCREQ2</a>
</td>
<td colspan="1">
<a href="#DMAC_CREQ__DCREQ1" title="Destination Chunk Request">DCREQ1</a>
</td>
<td colspan="1">
<a href="#DMAC_CREQ__SCREQ1" title="Source Chunk Request">SCREQ1</a>
</td>
<td colspan="1">
<a href="#DMAC_CREQ__DCREQ0" title="Destination Chunk Request">DCREQ0</a>
</td>
<td colspan="1">
<a href="#DMAC_CREQ__SCREQ0" title="Source Chunk Request">SCREQ0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CREQ__SCREQ0"><strong>SCREQ0</strong>: Source Chunk Request</li>
<p>-</p>
<li id="DMAC_CREQ__DCREQ0"><strong>DCREQ0</strong>: Destination Chunk Request</li>
<p>-</p>
<li id="DMAC_CREQ__SCREQ1"><strong>SCREQ1</strong>: Source Chunk Request</li>
<p>-</p>
<li id="DMAC_CREQ__DCREQ1"><strong>DCREQ1</strong>: Destination Chunk Request</li>
<p>-</p>
<li id="DMAC_CREQ__SCREQ2"><strong>SCREQ2</strong>: Source Chunk Request</li>
<p>-</p>
<li id="DMAC_CREQ__DCREQ2"><strong>DCREQ2</strong>: Destination Chunk Request</li>
<p>-</p>
<li id="DMAC_CREQ__SCREQ3"><strong>SCREQ3</strong>: Source Chunk Request</li>
<p>-</p>
<li id="DMAC_CREQ__DCREQ3"><strong>DCREQ3</strong>: Destination Chunk Request</li>
<p>-</p>
<li id="DMAC_CREQ__SCREQ4"><strong>SCREQ4</strong>: Source Chunk Request</li>
<p>-</p>
<li id="DMAC_CREQ__DCREQ4"><strong>DCREQ4</strong>: Destination Chunk Request</li>
<p>-</p>
<li id="DMAC_CREQ__SCREQ5"><strong>SCREQ5</strong>: Source Chunk Request</li>
<p>-</p>
<li id="DMAC_CREQ__DCREQ5"><strong>DCREQ5</strong>: Destination Chunk Request</li>
<p>-</p>
</ul>
<h4 id="DMAC_LAST">DMAC DMAC Software Last Transfer Flag Register</h4>
<p><strong>Name</strong>: DMAC_LAST</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4010</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_LAST__DLAST5" title="Destination Last">DLAST5</a>
</td>
<td colspan="1">
<a href="#DMAC_LAST__SLAST5" title="Source Last">SLAST5</a>
</td>
<td colspan="1">
<a href="#DMAC_LAST__DLAST4" title="Destination Last">DLAST4</a>
</td>
<td colspan="1">
<a href="#DMAC_LAST__SLAST4" title="Source Last">SLAST4</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#DMAC_LAST__DLAST3" title="Destination Last">DLAST3</a>
</td>
<td colspan="1">
<a href="#DMAC_LAST__SLAST3" title="Source Last">SLAST3</a>
</td>
<td colspan="1">
<a href="#DMAC_LAST__DLAST2" title="Destination Last">DLAST2</a>
</td>
<td colspan="1">
<a href="#DMAC_LAST__SLAST2" title="Source Last">SLAST2</a>
</td>
<td colspan="1">
<a href="#DMAC_LAST__DLAST1" title="Destination Last">DLAST1</a>
</td>
<td colspan="1">
<a href="#DMAC_LAST__SLAST1" title="Source Last">SLAST1</a>
</td>
<td colspan="1">
<a href="#DMAC_LAST__DLAST0" title="Destination Last">DLAST0</a>
</td>
<td colspan="1">
<a href="#DMAC_LAST__SLAST0" title="Source Last">SLAST0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_LAST__SLAST0"><strong>SLAST0</strong>: Source Last</li>
<p>-</p>
<li id="DMAC_LAST__DLAST0"><strong>DLAST0</strong>: Destination Last</li>
<p>-</p>
<li id="DMAC_LAST__SLAST1"><strong>SLAST1</strong>: Source Last</li>
<p>-</p>
<li id="DMAC_LAST__DLAST1"><strong>DLAST1</strong>: Destination Last</li>
<p>-</p>
<li id="DMAC_LAST__SLAST2"><strong>SLAST2</strong>: Source Last</li>
<p>-</p>
<li id="DMAC_LAST__DLAST2"><strong>DLAST2</strong>: Destination Last</li>
<p>-</p>
<li id="DMAC_LAST__SLAST3"><strong>SLAST3</strong>: Source Last</li>
<p>-</p>
<li id="DMAC_LAST__DLAST3"><strong>DLAST3</strong>: Destination Last</li>
<p>-</p>
<li id="DMAC_LAST__SLAST4"><strong>SLAST4</strong>: Source Last</li>
<p>-</p>
<li id="DMAC_LAST__DLAST4"><strong>DLAST4</strong>: Destination Last</li>
<p>-</p>
<li id="DMAC_LAST__SLAST5"><strong>SLAST5</strong>: Source Last</li>
<p>-</p>
<li id="DMAC_LAST__DLAST5"><strong>DLAST5</strong>: Destination Last</li>
<p>-</p>
</ul>
<h4 id="DMAC_EBCIER">DMAC DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.</h4>
<p><strong>Name</strong>: DMAC_EBCIER</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400C4018</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_EBCIER__ERR5" title="Access Error [5:0]">ERR5</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__ERR4" title="Access Error [5:0]">ERR4</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__ERR3" title="Access Error [5:0]">ERR3</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__ERR2" title="Access Error [5:0]">ERR2</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__ERR1" title="Access Error [5:0]">ERR1</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__ERR0" title="Access Error [5:0]">ERR0</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_EBCIER__CBTC5" title="Chained Buffer Transfer Completed [5:0]">CBTC5</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__CBTC4" title="Chained Buffer Transfer Completed [5:0]">CBTC4</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__CBTC3" title="Chained Buffer Transfer Completed [5:0]">CBTC3</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__CBTC2" title="Chained Buffer Transfer Completed [5:0]">CBTC2</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__CBTC1" title="Chained Buffer Transfer Completed [5:0]">CBTC1</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__CBTC0" title="Chained Buffer Transfer Completed [5:0]">CBTC0</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_EBCIER__BTC5" title="Buffer Transfer Completed [5:0]">BTC5</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__BTC4" title="Buffer Transfer Completed [5:0]">BTC4</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__BTC3" title="Buffer Transfer Completed [5:0]">BTC3</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__BTC2" title="Buffer Transfer Completed [5:0]">BTC2</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__BTC1" title="Buffer Transfer Completed [5:0]">BTC1</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIER__BTC0" title="Buffer Transfer Completed [5:0]">BTC0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_EBCIER__BTC0"><strong>BTC0</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__BTC1"><strong>BTC1</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__BTC2"><strong>BTC2</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__BTC3"><strong>BTC3</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__BTC4"><strong>BTC4</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__BTC5"><strong>BTC5</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__CBTC0"><strong>CBTC0</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__CBTC1"><strong>CBTC1</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__CBTC2"><strong>CBTC2</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__CBTC3"><strong>CBTC3</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__CBTC4"><strong>CBTC4</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__CBTC5"><strong>CBTC5</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__ERR0"><strong>ERR0</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__ERR1"><strong>ERR1</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__ERR2"><strong>ERR2</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__ERR3"><strong>ERR3</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__ERR4"><strong>ERR4</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIER__ERR5"><strong>ERR5</strong>: Access Error [5:0]</li>
<p>-</p>
</ul>
<h4 id="DMAC_EBCIDR">DMAC DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.</h4>
<p><strong>Name</strong>: DMAC_EBCIDR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400C401C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__ERR5" title="Access Error [5:0]">ERR5</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__ERR4" title="Access Error [5:0]">ERR4</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__ERR3" title="Access Error [5:0]">ERR3</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__ERR2" title="Access Error [5:0]">ERR2</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__ERR1" title="Access Error [5:0]">ERR1</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__ERR0" title="Access Error [5:0]">ERR0</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__CBTC5" title="Chained Buffer Transfer Completed [5:0]">CBTC5</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__CBTC4" title="Chained Buffer Transfer Completed [5:0]">CBTC4</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__CBTC3" title="Chained Buffer Transfer Completed [5:0]">CBTC3</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__CBTC2" title="Chained Buffer Transfer Completed [5:0]">CBTC2</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__CBTC1" title="Chained Buffer Transfer Completed [5:0]">CBTC1</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__CBTC0" title="Chained Buffer Transfer Completed [5:0]">CBTC0</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__BTC5" title="Buffer Transfer Completed [5:0]">BTC5</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__BTC4" title="Buffer Transfer Completed [5:0]">BTC4</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__BTC3" title="Buffer Transfer Completed [5:0]">BTC3</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__BTC2" title="Buffer Transfer Completed [5:0]">BTC2</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__BTC1" title="Buffer Transfer Completed [5:0]">BTC1</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIDR__BTC0" title="Buffer Transfer Completed [5:0]">BTC0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_EBCIDR__BTC0"><strong>BTC0</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__BTC1"><strong>BTC1</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__BTC2"><strong>BTC2</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__BTC3"><strong>BTC3</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__BTC4"><strong>BTC4</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__BTC5"><strong>BTC5</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__CBTC0"><strong>CBTC0</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__CBTC1"><strong>CBTC1</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__CBTC2"><strong>CBTC2</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__CBTC3"><strong>CBTC3</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__CBTC4"><strong>CBTC4</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__CBTC5"><strong>CBTC5</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__ERR0"><strong>ERR0</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__ERR1"><strong>ERR1</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__ERR2"><strong>ERR2</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__ERR3"><strong>ERR3</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__ERR4"><strong>ERR4</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCIDR__ERR5"><strong>ERR5</strong>: Access Error [5:0]</li>
<p>-</p>
</ul>
<h4 id="DMAC_EBCIMR">DMAC DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.</h4>
<p><strong>Name</strong>: DMAC_EBCIMR</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400C4020</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__ERR5" title="Access Error [5:0]">ERR5</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__ERR4" title="Access Error [5:0]">ERR4</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__ERR3" title="Access Error [5:0]">ERR3</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__ERR2" title="Access Error [5:0]">ERR2</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__ERR1" title="Access Error [5:0]">ERR1</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__ERR0" title="Access Error [5:0]">ERR0</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__CBTC5" title="Chained Buffer Transfer Completed [5:0]">CBTC5</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__CBTC4" title="Chained Buffer Transfer Completed [5:0]">CBTC4</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__CBTC3" title="Chained Buffer Transfer Completed [5:0]">CBTC3</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__CBTC2" title="Chained Buffer Transfer Completed [5:0]">CBTC2</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__CBTC1" title="Chained Buffer Transfer Completed [5:0]">CBTC1</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__CBTC0" title="Chained Buffer Transfer Completed [5:0]">CBTC0</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__BTC5" title="Buffer Transfer Completed [5:0]">BTC5</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__BTC4" title="Buffer Transfer Completed [5:0]">BTC4</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__BTC3" title="Buffer Transfer Completed [5:0]">BTC3</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__BTC2" title="Buffer Transfer Completed [5:0]">BTC2</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__BTC1" title="Buffer Transfer Completed [5:0]">BTC1</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCIMR__BTC0" title="Buffer Transfer Completed [5:0]">BTC0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_EBCIMR__BTC0"><strong>BTC0</strong>: Buffer Transfer Completed [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Buffer Transfer Completed Interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Buffer Transfer Completed Interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__BTC1"><strong>BTC1</strong>: Buffer Transfer Completed [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Buffer Transfer Completed Interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Buffer Transfer Completed Interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__BTC2"><strong>BTC2</strong>: Buffer Transfer Completed [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Buffer Transfer Completed Interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Buffer Transfer Completed Interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__BTC3"><strong>BTC3</strong>: Buffer Transfer Completed [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Buffer Transfer Completed Interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Buffer Transfer Completed Interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__BTC4"><strong>BTC4</strong>: Buffer Transfer Completed [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Buffer Transfer Completed Interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Buffer Transfer Completed Interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__BTC5"><strong>BTC5</strong>: Buffer Transfer Completed [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Buffer Transfer Completed Interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Buffer Transfer Completed Interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__CBTC0"><strong>CBTC0</strong>: Chained Buffer Transfer Completed [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Chained Buffer Transfer interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Chained Buffer Transfer interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__CBTC1"><strong>CBTC1</strong>: Chained Buffer Transfer Completed [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Chained Buffer Transfer interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Chained Buffer Transfer interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__CBTC2"><strong>CBTC2</strong>: Chained Buffer Transfer Completed [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Chained Buffer Transfer interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Chained Buffer Transfer interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__CBTC3"><strong>CBTC3</strong>: Chained Buffer Transfer Completed [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Chained Buffer Transfer interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Chained Buffer Transfer interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__CBTC4"><strong>CBTC4</strong>: Chained Buffer Transfer Completed [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Chained Buffer Transfer interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Chained Buffer Transfer interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__CBTC5"><strong>CBTC5</strong>: Chained Buffer Transfer Completed [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Chained Buffer Transfer interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Chained Buffer Transfer interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__ERR0"><strong>ERR0</strong>: Access Error [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Transfer Error Interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Transfer Error Interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__ERR1"><strong>ERR1</strong>: Access Error [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Transfer Error Interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Transfer Error Interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__ERR2"><strong>ERR2</strong>: Access Error [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Transfer Error Interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Transfer Error Interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__ERR3"><strong>ERR3</strong>: Access Error [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Transfer Error Interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Transfer Error Interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__ERR4"><strong>ERR4</strong>: Access Error [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Transfer Error Interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Transfer Error Interrupt is enabled for channel i.</td></tr></tbody></table></li>
<li id="DMAC_EBCIMR__ERR5"><strong>ERR5</strong>: Access Error [5:0]<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Transfer Error Interrupt is disabled for channel i.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Transfer Error Interrupt is enabled for channel i.</td></tr></tbody></table></li>
</ul>
<h4 id="DMAC_EBCISR">DMAC DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.</h4>
<p><strong>Name</strong>: DMAC_EBCISR</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400C4024</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_EBCISR__ERR5" title="Access Error [5:0]">ERR5</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__ERR4" title="Access Error [5:0]">ERR4</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__ERR3" title="Access Error [5:0]">ERR3</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__ERR2" title="Access Error [5:0]">ERR2</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__ERR1" title="Access Error [5:0]">ERR1</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__ERR0" title="Access Error [5:0]">ERR0</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_EBCISR__CBTC5" title="Chained Buffer Transfer Completed [5:0]">CBTC5</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__CBTC4" title="Chained Buffer Transfer Completed [5:0]">CBTC4</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__CBTC3" title="Chained Buffer Transfer Completed [5:0]">CBTC3</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__CBTC2" title="Chained Buffer Transfer Completed [5:0]">CBTC2</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__CBTC1" title="Chained Buffer Transfer Completed [5:0]">CBTC1</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__CBTC0" title="Chained Buffer Transfer Completed [5:0]">CBTC0</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_EBCISR__BTC5" title="Buffer Transfer Completed [5:0]">BTC5</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__BTC4" title="Buffer Transfer Completed [5:0]">BTC4</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__BTC3" title="Buffer Transfer Completed [5:0]">BTC3</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__BTC2" title="Buffer Transfer Completed [5:0]">BTC2</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__BTC1" title="Buffer Transfer Completed [5:0]">BTC1</a>
</td>
<td colspan="1">
<a href="#DMAC_EBCISR__BTC0" title="Buffer Transfer Completed [5:0]">BTC0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_EBCISR__BTC0"><strong>BTC0</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__BTC1"><strong>BTC1</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__BTC2"><strong>BTC2</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__BTC3"><strong>BTC3</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__BTC4"><strong>BTC4</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__BTC5"><strong>BTC5</strong>: Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__CBTC0"><strong>CBTC0</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__CBTC1"><strong>CBTC1</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__CBTC2"><strong>CBTC2</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__CBTC3"><strong>CBTC3</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__CBTC4"><strong>CBTC4</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__CBTC5"><strong>CBTC5</strong>: Chained Buffer Transfer Completed [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__ERR0"><strong>ERR0</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__ERR1"><strong>ERR1</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__ERR2"><strong>ERR2</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__ERR3"><strong>ERR3</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__ERR4"><strong>ERR4</strong>: Access Error [5:0]</li>
<p>-</p>
<li id="DMAC_EBCISR__ERR5"><strong>ERR5</strong>: Access Error [5:0]</li>
<p>-</p>
</ul>
<h4 id="DMAC_CHER">DMAC DMAC Channel Handler Enable Register</h4>
<p><strong>Name</strong>: DMAC_CHER</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400C4028</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CHER__KEEP5" title="Keep on [5:0]">KEEP5</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__KEEP4" title="Keep on [5:0]">KEEP4</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__KEEP3" title="Keep on [5:0]">KEEP3</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__KEEP2" title="Keep on [5:0]">KEEP2</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__KEEP1" title="Keep on [5:0]">KEEP1</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__KEEP0" title="Keep on [5:0]">KEEP0</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CHER__SUSP5" title="Suspend [5:0]">SUSP5</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__SUSP4" title="Suspend [5:0]">SUSP4</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__SUSP3" title="Suspend [5:0]">SUSP3</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__SUSP2" title="Suspend [5:0]">SUSP2</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__SUSP1" title="Suspend [5:0]">SUSP1</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__SUSP0" title="Suspend [5:0]">SUSP0</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CHER__ENA5" title="Enable [5:0]">ENA5</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__ENA4" title="Enable [5:0]">ENA4</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__ENA3" title="Enable [5:0]">ENA3</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__ENA2" title="Enable [5:0]">ENA2</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__ENA1" title="Enable [5:0]">ENA1</a>
</td>
<td colspan="1">
<a href="#DMAC_CHER__ENA0" title="Enable [5:0]">ENA0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CHER__ENA0"><strong>ENA0</strong>: Enable [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__ENA1"><strong>ENA1</strong>: Enable [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__ENA2"><strong>ENA2</strong>: Enable [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__ENA3"><strong>ENA3</strong>: Enable [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__ENA4"><strong>ENA4</strong>: Enable [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__ENA5"><strong>ENA5</strong>: Enable [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__SUSP0"><strong>SUSP0</strong>: Suspend [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__SUSP1"><strong>SUSP1</strong>: Suspend [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__SUSP2"><strong>SUSP2</strong>: Suspend [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__SUSP3"><strong>SUSP3</strong>: Suspend [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__SUSP4"><strong>SUSP4</strong>: Suspend [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__SUSP5"><strong>SUSP5</strong>: Suspend [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__KEEP0"><strong>KEEP0</strong>: Keep on [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__KEEP1"><strong>KEEP1</strong>: Keep on [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__KEEP2"><strong>KEEP2</strong>: Keep on [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__KEEP3"><strong>KEEP3</strong>: Keep on [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__KEEP4"><strong>KEEP4</strong>: Keep on [5:0]</li>
<p>-</p>
<li id="DMAC_CHER__KEEP5"><strong>KEEP5</strong>: Keep on [5:0]</li>
<p>-</p>
</ul>
<h4 id="DMAC_CHDR">DMAC DMAC Channel Handler Disable Register</h4>
<p><strong>Name</strong>: DMAC_CHDR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400C402C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CHDR__RES5" title="Resume [5:0]">RES5</a>
</td>
<td colspan="1">
<a href="#DMAC_CHDR__RES4" title="Resume [5:0]">RES4</a>
</td>
<td colspan="1">
<a href="#DMAC_CHDR__RES3" title="Resume [5:0]">RES3</a>
</td>
<td colspan="1">
<a href="#DMAC_CHDR__RES2" title="Resume [5:0]">RES2</a>
</td>
<td colspan="1">
<a href="#DMAC_CHDR__RES1" title="Resume [5:0]">RES1</a>
</td>
<td colspan="1">
<a href="#DMAC_CHDR__RES0" title="Resume [5:0]">RES0</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CHDR__DIS5" title="Disable [5:0]">DIS5</a>
</td>
<td colspan="1">
<a href="#DMAC_CHDR__DIS4" title="Disable [5:0]">DIS4</a>
</td>
<td colspan="1">
<a href="#DMAC_CHDR__DIS3" title="Disable [5:0]">DIS3</a>
</td>
<td colspan="1">
<a href="#DMAC_CHDR__DIS2" title="Disable [5:0]">DIS2</a>
</td>
<td colspan="1">
<a href="#DMAC_CHDR__DIS1" title="Disable [5:0]">DIS1</a>
</td>
<td colspan="1">
<a href="#DMAC_CHDR__DIS0" title="Disable [5:0]">DIS0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CHDR__DIS0"><strong>DIS0</strong>: Disable [5:0]</li>
<p>-</p>
<li id="DMAC_CHDR__DIS1"><strong>DIS1</strong>: Disable [5:0]</li>
<p>-</p>
<li id="DMAC_CHDR__DIS2"><strong>DIS2</strong>: Disable [5:0]</li>
<p>-</p>
<li id="DMAC_CHDR__DIS3"><strong>DIS3</strong>: Disable [5:0]</li>
<p>-</p>
<li id="DMAC_CHDR__DIS4"><strong>DIS4</strong>: Disable [5:0]</li>
<p>-</p>
<li id="DMAC_CHDR__DIS5"><strong>DIS5</strong>: Disable [5:0]</li>
<p>-</p>
<li id="DMAC_CHDR__RES0"><strong>RES0</strong>: Resume [5:0]</li>
<p>-</p>
<li id="DMAC_CHDR__RES1"><strong>RES1</strong>: Resume [5:0]</li>
<p>-</p>
<li id="DMAC_CHDR__RES2"><strong>RES2</strong>: Resume [5:0]</li>
<p>-</p>
<li id="DMAC_CHDR__RES3"><strong>RES3</strong>: Resume [5:0]</li>
<p>-</p>
<li id="DMAC_CHDR__RES4"><strong>RES4</strong>: Resume [5:0]</li>
<p>-</p>
<li id="DMAC_CHDR__RES5"><strong>RES5</strong>: Resume [5:0]</li>
<p>-</p>
</ul>
<h4 id="DMAC_CHSR">DMAC DMAC Channel Handler Status Register</h4>
<p><strong>Name</strong>: DMAC_CHSR</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400C4030</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CHSR__STAL5" title="Stalled [5:0]">STAL5</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__STAL4" title="Stalled [5:0]">STAL4</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__STAL3" title="Stalled [5:0]">STAL3</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__STAL2" title="Stalled [5:0]">STAL2</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__STAL1" title="Stalled [5:0]">STAL1</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__STAL0" title="Stalled [5:0]">STAL0</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CHSR__EMPT5" title="Empty [5:0]">EMPT5</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__EMPT4" title="Empty [5:0]">EMPT4</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__EMPT3" title="Empty [5:0]">EMPT3</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__EMPT2" title="Empty [5:0]">EMPT2</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__EMPT1" title="Empty [5:0]">EMPT1</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__EMPT0" title="Empty [5:0]">EMPT0</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CHSR__SUSP5" title="Suspend [5:0]">SUSP5</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__SUSP4" title="Suspend [5:0]">SUSP4</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__SUSP3" title="Suspend [5:0]">SUSP3</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__SUSP2" title="Suspend [5:0]">SUSP2</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__SUSP1" title="Suspend [5:0]">SUSP1</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__SUSP0" title="Suspend [5:0]">SUSP0</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CHSR__ENA5" title="Enable [5:0]">ENA5</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__ENA4" title="Enable [5:0]">ENA4</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__ENA3" title="Enable [5:0]">ENA3</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__ENA2" title="Enable [5:0]">ENA2</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__ENA1" title="Enable [5:0]">ENA1</a>
</td>
<td colspan="1">
<a href="#DMAC_CHSR__ENA0" title="Enable [5:0]">ENA0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CHSR__ENA0"><strong>ENA0</strong>: Enable [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__ENA1"><strong>ENA1</strong>: Enable [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__ENA2"><strong>ENA2</strong>: Enable [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__ENA3"><strong>ENA3</strong>: Enable [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__ENA4"><strong>ENA4</strong>: Enable [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__ENA5"><strong>ENA5</strong>: Enable [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__SUSP0"><strong>SUSP0</strong>: Suspend [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__SUSP1"><strong>SUSP1</strong>: Suspend [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__SUSP2"><strong>SUSP2</strong>: Suspend [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__SUSP3"><strong>SUSP3</strong>: Suspend [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__SUSP4"><strong>SUSP4</strong>: Suspend [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__SUSP5"><strong>SUSP5</strong>: Suspend [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__EMPT0"><strong>EMPT0</strong>: Empty [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__EMPT1"><strong>EMPT1</strong>: Empty [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__EMPT2"><strong>EMPT2</strong>: Empty [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__EMPT3"><strong>EMPT3</strong>: Empty [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__EMPT4"><strong>EMPT4</strong>: Empty [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__EMPT5"><strong>EMPT5</strong>: Empty [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__STAL0"><strong>STAL0</strong>: Stalled [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__STAL1"><strong>STAL1</strong>: Stalled [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__STAL2"><strong>STAL2</strong>: Stalled [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__STAL3"><strong>STAL3</strong>: Stalled [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__STAL4"><strong>STAL4</strong>: Stalled [5:0]</li>
<p>-</p>
<li id="DMAC_CHSR__STAL5"><strong>STAL5</strong>: Stalled [5:0]</li>
<p>-</p>
</ul>
<h4 id="DMAC_SADDR0">DMAC DMAC Channel Source Address Register (ch_num = 0)</h4>
<p><strong>Name</strong>: DMAC_SADDR0</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C403C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR0__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR0__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR0__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR0__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_SADDR0__SADDR"><strong>SADDR</strong>: Channel x Source Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_DADDR0">DMAC DMAC Channel Destination Address Register (ch_num = 0)</h4>
<p><strong>Name</strong>: DMAC_DADDR0</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4040</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR0__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR0__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR0__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR0__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_DADDR0__DADDR"><strong>DADDR</strong>: Channel x Destination Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_DSCR0">DMAC DMAC Channel Descriptor Address Register (ch_num = 0)</h4>
<p><strong>Name</strong>: DMAC_DSCR0</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4044</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR0__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR0__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR0__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="6">
<a href="#DMAC_DSCR0__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_DSCR0__DSCR"><strong>DSCR</strong>: Buffer Transfer Descriptor Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_CTRLA0">DMAC DMAC Channel Control A Register (ch_num = 0)</h4>
<p><strong>Name</strong>: DMAC_CTRLA0</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4048</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#DMAC_CTRLA0__DONE" title="">DONE</a>
</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLA0__DST_WIDTH" title="Transfer Width for the Destination">DST_WIDTH</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLA0__SRC_WIDTH" title="Transfer Width for the Source">SRC_WIDTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="3">
<a href="#DMAC_CTRLA0__DCSIZE" title="Destination Chunk Transfer Size">DCSIZE</a>
</td>
<td>-</td>
<td colspan="3">
<a href="#DMAC_CTRLA0__SCSIZE" title="Source Chunk Transfer Size.">SCSIZE</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_CTRLA0__BTSIZE" title="Buffer Transfer Size">BTSIZE</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_CTRLA0__BTSIZE" title="Buffer Transfer Size">BTSIZE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CTRLA0__BTSIZE"><strong>BTSIZE</strong>: Buffer Transfer Size</li>
<p>-</p>
<li id="DMAC_CTRLA0__SCSIZE"><strong>SCSIZE</strong>: Source Chunk Transfer Size.<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CHK_1</td><td class="description">1 data transferred</td></tr><tr class="even"><td class="value">0x1</td><td class="name">CHK_4</td><td class="description">4 data transferred</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">CHK_8</td><td class="description">8 data transferred</td></tr><tr class="even"><td class="value">0x3</td><td class="name">CHK_16</td><td class="description">16 data transferred</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">CHK_32</td><td class="description">32 data transferred</td></tr><tr class="even"><td class="value">0x5</td><td class="name">CHK_64</td><td class="description">64 data transferred</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">CHK_128</td><td class="description">128 data transferred</td></tr><tr class="even"><td class="value">0x7</td><td class="name">CHK_256</td><td class="description">256 data transferred</td></tr></tbody></table></li>
<li id="DMAC_CTRLA0__DCSIZE"><strong>DCSIZE</strong>: Destination Chunk Transfer Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CHK_1</td><td class="description">1 data transferred</td></tr><tr class="even"><td class="value">0x1</td><td class="name">CHK_4</td><td class="description">4 data transferred</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">CHK_8</td><td class="description">8 data transferred</td></tr><tr class="even"><td class="value">0x3</td><td class="name">CHK_16</td><td class="description">16 data transferred</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">CHK_32</td><td class="description">32 data transferred</td></tr><tr class="even"><td class="value">0x5</td><td class="name">CHK_64</td><td class="description">64 data transferred</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">CHK_128</td><td class="description">128 data transferred</td></tr><tr class="even"><td class="value">0x7</td><td class="name">CHK_256</td><td class="description">256 data transferred</td></tr></tbody></table></li>
<li id="DMAC_CTRLA0__SRC_WIDTH"><strong>SRC_WIDTH</strong>: Transfer Width for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BYTE</td><td class="description">the transfer size is set to 8-bit width</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_WORD</td><td class="description">the transfer size is set to 16-bit width</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">WORD</td><td class="description">the transfer size is set to 32-bit width</td></tr></tbody></table></li>
<li id="DMAC_CTRLA0__DST_WIDTH"><strong>DST_WIDTH</strong>: Transfer Width for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BYTE</td><td class="description">the transfer size is set to 8-bit width</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_WORD</td><td class="description">the transfer size is set to 16-bit width</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">WORD</td><td class="description">the transfer size is set to 32-bit width</td></tr></tbody></table></li>
<li id="DMAC_CTRLA0__DONE">
<strong>DONE</strong>
<table class="values">
<thead>
<tr>
<th>Value</th>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="value">0</td>
<td class="name">-</td>
<td class="description">The transfer is performed.</td>
</tr>
<tr class="even">
<td class="value">1</td>
<td class="name">-</td>
<td class="description">If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con-tent of this register.</td>
</tr>
</tbody>
</table>
</li>
</ul>
<h4 id="DMAC_CTRLB0">DMAC DMAC Channel Control B Register (ch_num = 0)</h4>
<p><strong>Name</strong>: DMAC_CTRLB0</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C404C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#DMAC_CTRLB0__IEN" title="">IEN</a>
</td>
<td colspan="2">
<a href="#DMAC_CTRLB0__DST_INCR" title="Incrementing, Decrementing or Fixed Address for the Destination">DST_INCR</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLB0__SRC_INCR" title="Incrementing, Decrementing or Fixed Address for the Source">SRC_INCR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="3">
<a href="#DMAC_CTRLB0__FC" title="Flow Control">FC</a>
</td>
<td colspan="1">
<a href="#DMAC_CTRLB0__DST_DSCR" title="Destination Address Descriptor">DST_DSCR</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CTRLB0__SRC_DSCR" title="Source Address Descriptor">SRC_DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CTRLB0__SRC_DSCR"><strong>SRC_DSCR</strong>: Source Address Descriptor<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">FETCH_FROM_MEM</td><td class="description">Source address is updated when the descriptor is fetched from the memory.</td></tr><tr class="even"><td class="value">1</td><td class="name">FETCH_DISABLE</td><td class="description">Buffer Descriptor Fetch operation is disabled for the source.</td></tr></tbody></table></li>
<li id="DMAC_CTRLB0__DST_DSCR"><strong>DST_DSCR</strong>: Destination Address Descriptor<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">FETCH_FROM_MEM</td><td class="description">Destination address is updated when the descriptor is fetched from the memory.</td></tr><tr class="even"><td class="value">1</td><td class="name">FETCH_DISABLE</td><td class="description">Buffer Descriptor Fetch operation is disabled for the destination.</td></tr></tbody></table></li>
<li id="DMAC_CTRLB0__FC"><strong>FC</strong>: Flow Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">MEM2MEM_DMA_FC</td><td class="description">Memory-to-Memory Transfer DMAC is flow controller</td></tr><tr class="even"><td class="value">0x1</td><td class="name">MEM2PER_DMA_FC</td><td class="description">Memory-to-Peripheral Transfer DMAC is flow controller</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">PER2MEM_DMA_FC</td><td class="description">Peripheral-to-Memory Transfer DMAC is flow controller</td></tr><tr class="even"><td class="value">0x3</td><td class="name">PER2PER_DMA_FC</td><td class="description">Peripheral-to-Peripheral Transfer DMAC is flow controller</td></tr></tbody></table></li>
<li id="DMAC_CTRLB0__SRC_INCR"><strong>SRC_INCR</strong>: Incrementing, Decrementing or Fixed Address for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">INCREMENTING</td><td class="description">The source address is incremented</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DECREMENTING</td><td class="description">The source address is decremented</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">FIXED</td><td class="description">The source address remains unchanged</td></tr></tbody></table></li>
<li id="DMAC_CTRLB0__DST_INCR"><strong>DST_INCR</strong>: Incrementing, Decrementing or Fixed Address for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">INCREMENTING</td><td class="description">The destination address is incremented</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DECREMENTING</td><td class="description">The destination address is decremented</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">FIXED</td><td class="description">The destination address remains unchanged</td></tr></tbody></table></li>
<li id="DMAC_CTRLB0__IEN">
<strong>IEN</strong>
</li>
<p>-</p>
</ul>
<h4 id="DMAC_CFG0">DMAC DMAC Channel Configuration Register (ch_num = 0)</h4>
<p><strong>Name</strong>: DMAC_CFG0</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4050</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CFG0__FIFOCFG" title="FIFO Configuration">FIFOCFG</a>
</td>
<td>-</td>
<td colspan="3">
<a href="#DMAC_CFG0__AHB_PROT" title="AHB Protection">AHB_PROT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG0__LOCK_IF_L" title="Master Interface Arbiter Lock">LOCK_IF_L</a>
</td>
<td colspan="1">
<a href="#DMAC_CFG0__LOCK_B" title="Bus Lock">LOCK_B</a>
</td>
<td colspan="1">
<a href="#DMAC_CFG0__LOCK_IF" title="Interface Lock">LOCK_IF</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG0__SOD" title="Stop On Done">SOD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG0__DST_H2SEL" title="Software or Hardware Selection for the Destination">DST_H2SEL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG0__SRC_H2SEL" title="Software or Hardware Selection for the Source">SRC_H2SEL</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#DMAC_CFG0__DST_PER" title="Destination with Peripheral identifier">DST_PER</a>
</td>
<td colspan="4">
<a href="#DMAC_CFG0__SRC_PER" title="Source with Peripheral identifier">SRC_PER</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CFG0__SRC_PER"><strong>SRC_PER</strong>: Source with Peripheral identifier</li>
<p>-</p>
<li id="DMAC_CFG0__DST_PER"><strong>DST_PER</strong>: Destination with Peripheral identifier</li>
<p>-</p>
<li id="DMAC_CFG0__SRC_H2SEL"><strong>SRC_H2SEL</strong>: Software or Hardware Selection for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">SW</td><td class="description">Software handshaking interface is used to trigger a transfer request.</td></tr><tr class="even"><td class="value">1</td><td class="name">HW</td><td class="description">Hardware handshaking interface is used to trigger a transfer request.</td></tr></tbody></table></li>
<li id="DMAC_CFG0__DST_H2SEL"><strong>DST_H2SEL</strong>: Software or Hardware Selection for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">SW</td><td class="description">Software handshaking interface is used to trigger a transfer request.</td></tr><tr class="even"><td class="value">1</td><td class="name">HW</td><td class="description">Hardware handshaking interface is used to trigger a transfer request.</td></tr></tbody></table></li>
<li id="DMAC_CFG0__SOD"><strong>SOD</strong>: Stop On Done<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.</td></tr><tr class="even"><td class="value">1</td><td class="name">ENABLE</td><td class="description">STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.</td></tr></tbody></table></li>
<li id="DMAC_CFG0__LOCK_IF"><strong>LOCK_IF</strong>: Interface Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">Interface Lock capability is disabled</td></tr><tr class="even"><td class="value">1</td><td class="name">ENABLE</td><td class="description">Interface Lock capability is enabled</td></tr></tbody></table></li>
<li id="DMAC_CFG0__LOCK_B"><strong>LOCK_B</strong>: Bus Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">AHB Bus Locking capability is disabled.</td></tr></tbody></table></li>
<li id="DMAC_CFG0__LOCK_IF_L"><strong>LOCK_IF_L</strong>: Master Interface Arbiter Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">CHUNK</td><td class="description">The Master Interface Arbiter is locked by the channel x for a chunk transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">BUFFER</td><td class="description">The Master Interface Arbiter is locked by the channel x for a buffer transfer.</td></tr></tbody></table></li>
<li id="DMAC_CFG0__AHB_PROT"><strong>AHB_PROT</strong>: AHB Protection<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">1</td><td class="name">-</td><td class="description">Data access</td></tr></tbody></table></li>
<li id="DMAC_CFG0__FIFOCFG"><strong>FIFOCFG</strong>: FIFO Configuration<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">ALAP_CFG</td><td class="description">The largest defined length AHB burst is performed on the destination AHB interface.</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_CFG</td><td class="description">When half FIFO size is available/filled, a source/destination request is serviced.</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">ASAP_CFG</td><td class="description">When there is enough space/data available to perform a single AHB access, then the request is serviced.</td></tr></tbody></table></li>
</ul>
<h4 id="DMAC_SADDR1">DMAC DMAC Channel Source Address Register (ch_num = 1)</h4>
<p><strong>Name</strong>: DMAC_SADDR1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4064</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR1__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR1__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR1__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR1__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_SADDR1__SADDR"><strong>SADDR</strong>: Channel x Source Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_DADDR1">DMAC DMAC Channel Destination Address Register (ch_num = 1)</h4>
<p><strong>Name</strong>: DMAC_DADDR1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4068</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR1__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR1__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR1__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR1__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_DADDR1__DADDR"><strong>DADDR</strong>: Channel x Destination Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_DSCR1">DMAC DMAC Channel Descriptor Address Register (ch_num = 1)</h4>
<p><strong>Name</strong>: DMAC_DSCR1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C406C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR1__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR1__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR1__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="6">
<a href="#DMAC_DSCR1__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_DSCR1__DSCR"><strong>DSCR</strong>: Buffer Transfer Descriptor Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_CTRLA1">DMAC DMAC Channel Control A Register (ch_num = 1)</h4>
<p><strong>Name</strong>: DMAC_CTRLA1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4070</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#DMAC_CTRLA1__DONE" title="">DONE</a>
</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLA1__DST_WIDTH" title="Transfer Width for the Destination">DST_WIDTH</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLA1__SRC_WIDTH" title="Transfer Width for the Source">SRC_WIDTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="3">
<a href="#DMAC_CTRLA1__DCSIZE" title="Destination Chunk Transfer Size">DCSIZE</a>
</td>
<td>-</td>
<td colspan="3">
<a href="#DMAC_CTRLA1__SCSIZE" title="Source Chunk Transfer Size.">SCSIZE</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_CTRLA1__BTSIZE" title="Buffer Transfer Size">BTSIZE</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_CTRLA1__BTSIZE" title="Buffer Transfer Size">BTSIZE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CTRLA1__BTSIZE"><strong>BTSIZE</strong>: Buffer Transfer Size</li>
<p>-</p>
<li id="DMAC_CTRLA1__SCSIZE"><strong>SCSIZE</strong>: Source Chunk Transfer Size.<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CHK_1</td><td class="description">1 data transferred</td></tr><tr class="even"><td class="value">0x1</td><td class="name">CHK_4</td><td class="description">4 data transferred</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">CHK_8</td><td class="description">8 data transferred</td></tr><tr class="even"><td class="value">0x3</td><td class="name">CHK_16</td><td class="description">16 data transferred</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">CHK_32</td><td class="description">32 data transferred</td></tr><tr class="even"><td class="value">0x5</td><td class="name">CHK_64</td><td class="description">64 data transferred</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">CHK_128</td><td class="description">128 data transferred</td></tr><tr class="even"><td class="value">0x7</td><td class="name">CHK_256</td><td class="description">256 data transferred</td></tr></tbody></table></li>
<li id="DMAC_CTRLA1__DCSIZE"><strong>DCSIZE</strong>: Destination Chunk Transfer Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CHK_1</td><td class="description">1 data transferred</td></tr><tr class="even"><td class="value">0x1</td><td class="name">CHK_4</td><td class="description">4 data transferred</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">CHK_8</td><td class="description">8 data transferred</td></tr><tr class="even"><td class="value">0x3</td><td class="name">CHK_16</td><td class="description">16 data transferred</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">CHK_32</td><td class="description">32 data transferred</td></tr><tr class="even"><td class="value">0x5</td><td class="name">CHK_64</td><td class="description">64 data transferred</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">CHK_128</td><td class="description">128 data transferred</td></tr><tr class="even"><td class="value">0x7</td><td class="name">CHK_256</td><td class="description">256 data transferred</td></tr></tbody></table></li>
<li id="DMAC_CTRLA1__SRC_WIDTH"><strong>SRC_WIDTH</strong>: Transfer Width for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BYTE</td><td class="description">the transfer size is set to 8-bit width</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_WORD</td><td class="description">the transfer size is set to 16-bit width</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">WORD</td><td class="description">the transfer size is set to 32-bit width</td></tr></tbody></table></li>
<li id="DMAC_CTRLA1__DST_WIDTH"><strong>DST_WIDTH</strong>: Transfer Width for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BYTE</td><td class="description">the transfer size is set to 8-bit width</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_WORD</td><td class="description">the transfer size is set to 16-bit width</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">WORD</td><td class="description">the transfer size is set to 32-bit width</td></tr></tbody></table></li>
<li id="DMAC_CTRLA1__DONE">
<strong>DONE</strong>
<table class="values">
<thead>
<tr>
<th>Value</th>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="value">0</td>
<td class="name">-</td>
<td class="description">The transfer is performed.</td>
</tr>
<tr class="even">
<td class="value">1</td>
<td class="name">-</td>
<td class="description">If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con-tent of this register.</td>
</tr>
</tbody>
</table>
</li>
</ul>
<h4 id="DMAC_CTRLB1">DMAC DMAC Channel Control B Register (ch_num = 1)</h4>
<p><strong>Name</strong>: DMAC_CTRLB1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4074</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#DMAC_CTRLB1__IEN" title="">IEN</a>
</td>
<td colspan="2">
<a href="#DMAC_CTRLB1__DST_INCR" title="Incrementing, Decrementing or Fixed Address for the Destination">DST_INCR</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLB1__SRC_INCR" title="Incrementing, Decrementing or Fixed Address for the Source">SRC_INCR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="3">
<a href="#DMAC_CTRLB1__FC" title="Flow Control">FC</a>
</td>
<td colspan="1">
<a href="#DMAC_CTRLB1__DST_DSCR" title="Destination Address Descriptor">DST_DSCR</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CTRLB1__SRC_DSCR" title="Source Address Descriptor">SRC_DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CTRLB1__SRC_DSCR"><strong>SRC_DSCR</strong>: Source Address Descriptor<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">FETCH_FROM_MEM</td><td class="description">Source address is updated when the descriptor is fetched from the memory.</td></tr><tr class="even"><td class="value">1</td><td class="name">FETCH_DISABLE</td><td class="description">Buffer Descriptor Fetch operation is disabled for the source.</td></tr></tbody></table></li>
<li id="DMAC_CTRLB1__DST_DSCR"><strong>DST_DSCR</strong>: Destination Address Descriptor<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">FETCH_FROM_MEM</td><td class="description">Destination address is updated when the descriptor is fetched from the memory.</td></tr><tr class="even"><td class="value">1</td><td class="name">FETCH_DISABLE</td><td class="description">Buffer Descriptor Fetch operation is disabled for the destination.</td></tr></tbody></table></li>
<li id="DMAC_CTRLB1__FC"><strong>FC</strong>: Flow Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">MEM2MEM_DMA_FC</td><td class="description">Memory-to-Memory Transfer DMAC is flow controller</td></tr><tr class="even"><td class="value">0x1</td><td class="name">MEM2PER_DMA_FC</td><td class="description">Memory-to-Peripheral Transfer DMAC is flow controller</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">PER2MEM_DMA_FC</td><td class="description">Peripheral-to-Memory Transfer DMAC is flow controller</td></tr><tr class="even"><td class="value">0x3</td><td class="name">PER2PER_DMA_FC</td><td class="description">Peripheral-to-Peripheral Transfer DMAC is flow controller</td></tr></tbody></table></li>
<li id="DMAC_CTRLB1__SRC_INCR"><strong>SRC_INCR</strong>: Incrementing, Decrementing or Fixed Address for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">INCREMENTING</td><td class="description">The source address is incremented</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DECREMENTING</td><td class="description">The source address is decremented</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">FIXED</td><td class="description">The source address remains unchanged</td></tr></tbody></table></li>
<li id="DMAC_CTRLB1__DST_INCR"><strong>DST_INCR</strong>: Incrementing, Decrementing or Fixed Address for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">INCREMENTING</td><td class="description">The destination address is incremented</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DECREMENTING</td><td class="description">The destination address is decremented</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">FIXED</td><td class="description">The destination address remains unchanged</td></tr></tbody></table></li>
<li id="DMAC_CTRLB1__IEN">
<strong>IEN</strong>
</li>
<p>-</p>
</ul>
<h4 id="DMAC_CFG1">DMAC DMAC Channel Configuration Register (ch_num = 1)</h4>
<p><strong>Name</strong>: DMAC_CFG1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4078</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CFG1__FIFOCFG" title="FIFO Configuration">FIFOCFG</a>
</td>
<td>-</td>
<td colspan="3">
<a href="#DMAC_CFG1__AHB_PROT" title="AHB Protection">AHB_PROT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG1__LOCK_IF_L" title="Master Interface Arbiter Lock">LOCK_IF_L</a>
</td>
<td colspan="1">
<a href="#DMAC_CFG1__LOCK_B" title="Bus Lock">LOCK_B</a>
</td>
<td colspan="1">
<a href="#DMAC_CFG1__LOCK_IF" title="Interface Lock">LOCK_IF</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG1__SOD" title="Stop On Done">SOD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG1__DST_H2SEL" title="Software or Hardware Selection for the Destination">DST_H2SEL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG1__SRC_H2SEL" title="Software or Hardware Selection for the Source">SRC_H2SEL</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#DMAC_CFG1__DST_PER" title="Destination with Peripheral identifier">DST_PER</a>
</td>
<td colspan="4">
<a href="#DMAC_CFG1__SRC_PER" title="Source with Peripheral identifier">SRC_PER</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CFG1__SRC_PER"><strong>SRC_PER</strong>: Source with Peripheral identifier</li>
<p>-</p>
<li id="DMAC_CFG1__DST_PER"><strong>DST_PER</strong>: Destination with Peripheral identifier</li>
<p>-</p>
<li id="DMAC_CFG1__SRC_H2SEL"><strong>SRC_H2SEL</strong>: Software or Hardware Selection for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">SW</td><td class="description">Software handshaking interface is used to trigger a transfer request.</td></tr><tr class="even"><td class="value">1</td><td class="name">HW</td><td class="description">Hardware handshaking interface is used to trigger a transfer request.</td></tr></tbody></table></li>
<li id="DMAC_CFG1__DST_H2SEL"><strong>DST_H2SEL</strong>: Software or Hardware Selection for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">SW</td><td class="description">Software handshaking interface is used to trigger a transfer request.</td></tr><tr class="even"><td class="value">1</td><td class="name">HW</td><td class="description">Hardware handshaking interface is used to trigger a transfer request.</td></tr></tbody></table></li>
<li id="DMAC_CFG1__SOD"><strong>SOD</strong>: Stop On Done<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.</td></tr><tr class="even"><td class="value">1</td><td class="name">ENABLE</td><td class="description">STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.</td></tr></tbody></table></li>
<li id="DMAC_CFG1__LOCK_IF"><strong>LOCK_IF</strong>: Interface Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">Interface Lock capability is disabled</td></tr><tr class="even"><td class="value">1</td><td class="name">ENABLE</td><td class="description">Interface Lock capability is enabled</td></tr></tbody></table></li>
<li id="DMAC_CFG1__LOCK_B"><strong>LOCK_B</strong>: Bus Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">AHB Bus Locking capability is disabled.</td></tr></tbody></table></li>
<li id="DMAC_CFG1__LOCK_IF_L"><strong>LOCK_IF_L</strong>: Master Interface Arbiter Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">CHUNK</td><td class="description">The Master Interface Arbiter is locked by the channel x for a chunk transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">BUFFER</td><td class="description">The Master Interface Arbiter is locked by the channel x for a buffer transfer.</td></tr></tbody></table></li>
<li id="DMAC_CFG1__AHB_PROT"><strong>AHB_PROT</strong>: AHB Protection<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">1</td><td class="name">-</td><td class="description">Data access</td></tr></tbody></table></li>
<li id="DMAC_CFG1__FIFOCFG"><strong>FIFOCFG</strong>: FIFO Configuration<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">ALAP_CFG</td><td class="description">The largest defined length AHB burst is performed on the destination AHB interface.</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_CFG</td><td class="description">When half FIFO size is available/filled, a source/destination request is serviced.</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">ASAP_CFG</td><td class="description">When there is enough space/data available to perform a single AHB access, then the request is serviced.</td></tr></tbody></table></li>
</ul>
<h4 id="DMAC_SADDR2">DMAC DMAC Channel Source Address Register (ch_num = 2)</h4>
<p><strong>Name</strong>: DMAC_SADDR2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C408C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR2__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR2__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR2__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR2__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_SADDR2__SADDR"><strong>SADDR</strong>: Channel x Source Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_DADDR2">DMAC DMAC Channel Destination Address Register (ch_num = 2)</h4>
<p><strong>Name</strong>: DMAC_DADDR2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4090</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR2__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR2__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR2__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR2__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_DADDR2__DADDR"><strong>DADDR</strong>: Channel x Destination Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_DSCR2">DMAC DMAC Channel Descriptor Address Register (ch_num = 2)</h4>
<p><strong>Name</strong>: DMAC_DSCR2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4094</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR2__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR2__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR2__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="6">
<a href="#DMAC_DSCR2__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_DSCR2__DSCR"><strong>DSCR</strong>: Buffer Transfer Descriptor Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_CTRLA2">DMAC DMAC Channel Control A Register (ch_num = 2)</h4>
<p><strong>Name</strong>: DMAC_CTRLA2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4098</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#DMAC_CTRLA2__DONE" title="">DONE</a>
</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLA2__DST_WIDTH" title="Transfer Width for the Destination">DST_WIDTH</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLA2__SRC_WIDTH" title="Transfer Width for the Source">SRC_WIDTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="3">
<a href="#DMAC_CTRLA2__DCSIZE" title="Destination Chunk Transfer Size">DCSIZE</a>
</td>
<td>-</td>
<td colspan="3">
<a href="#DMAC_CTRLA2__SCSIZE" title="Source Chunk Transfer Size.">SCSIZE</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_CTRLA2__BTSIZE" title="Buffer Transfer Size">BTSIZE</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_CTRLA2__BTSIZE" title="Buffer Transfer Size">BTSIZE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CTRLA2__BTSIZE"><strong>BTSIZE</strong>: Buffer Transfer Size</li>
<p>-</p>
<li id="DMAC_CTRLA2__SCSIZE"><strong>SCSIZE</strong>: Source Chunk Transfer Size.<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CHK_1</td><td class="description">1 data transferred</td></tr><tr class="even"><td class="value">0x1</td><td class="name">CHK_4</td><td class="description">4 data transferred</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">CHK_8</td><td class="description">8 data transferred</td></tr><tr class="even"><td class="value">0x3</td><td class="name">CHK_16</td><td class="description">16 data transferred</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">CHK_32</td><td class="description">32 data transferred</td></tr><tr class="even"><td class="value">0x5</td><td class="name">CHK_64</td><td class="description">64 data transferred</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">CHK_128</td><td class="description">128 data transferred</td></tr><tr class="even"><td class="value">0x7</td><td class="name">CHK_256</td><td class="description">256 data transferred</td></tr></tbody></table></li>
<li id="DMAC_CTRLA2__DCSIZE"><strong>DCSIZE</strong>: Destination Chunk Transfer Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CHK_1</td><td class="description">1 data transferred</td></tr><tr class="even"><td class="value">0x1</td><td class="name">CHK_4</td><td class="description">4 data transferred</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">CHK_8</td><td class="description">8 data transferred</td></tr><tr class="even"><td class="value">0x3</td><td class="name">CHK_16</td><td class="description">16 data transferred</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">CHK_32</td><td class="description">32 data transferred</td></tr><tr class="even"><td class="value">0x5</td><td class="name">CHK_64</td><td class="description">64 data transferred</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">CHK_128</td><td class="description">128 data transferred</td></tr><tr class="even"><td class="value">0x7</td><td class="name">CHK_256</td><td class="description">256 data transferred</td></tr></tbody></table></li>
<li id="DMAC_CTRLA2__SRC_WIDTH"><strong>SRC_WIDTH</strong>: Transfer Width for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BYTE</td><td class="description">the transfer size is set to 8-bit width</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_WORD</td><td class="description">the transfer size is set to 16-bit width</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">WORD</td><td class="description">the transfer size is set to 32-bit width</td></tr></tbody></table></li>
<li id="DMAC_CTRLA2__DST_WIDTH"><strong>DST_WIDTH</strong>: Transfer Width for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BYTE</td><td class="description">the transfer size is set to 8-bit width</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_WORD</td><td class="description">the transfer size is set to 16-bit width</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">WORD</td><td class="description">the transfer size is set to 32-bit width</td></tr></tbody></table></li>
<li id="DMAC_CTRLA2__DONE">
<strong>DONE</strong>
<table class="values">
<thead>
<tr>
<th>Value</th>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="value">0</td>
<td class="name">-</td>
<td class="description">The transfer is performed.</td>
</tr>
<tr class="even">
<td class="value">1</td>
<td class="name">-</td>
<td class="description">If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con-tent of this register.</td>
</tr>
</tbody>
</table>
</li>
</ul>
<h4 id="DMAC_CTRLB2">DMAC DMAC Channel Control B Register (ch_num = 2)</h4>
<p><strong>Name</strong>: DMAC_CTRLB2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C409C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#DMAC_CTRLB2__IEN" title="">IEN</a>
</td>
<td colspan="2">
<a href="#DMAC_CTRLB2__DST_INCR" title="Incrementing, Decrementing or Fixed Address for the Destination">DST_INCR</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLB2__SRC_INCR" title="Incrementing, Decrementing or Fixed Address for the Source">SRC_INCR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="3">
<a href="#DMAC_CTRLB2__FC" title="Flow Control">FC</a>
</td>
<td colspan="1">
<a href="#DMAC_CTRLB2__DST_DSCR" title="Destination Address Descriptor">DST_DSCR</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CTRLB2__SRC_DSCR" title="Source Address Descriptor">SRC_DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CTRLB2__SRC_DSCR"><strong>SRC_DSCR</strong>: Source Address Descriptor<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">FETCH_FROM_MEM</td><td class="description">Source address is updated when the descriptor is fetched from the memory.</td></tr><tr class="even"><td class="value">1</td><td class="name">FETCH_DISABLE</td><td class="description">Buffer Descriptor Fetch operation is disabled for the source.</td></tr></tbody></table></li>
<li id="DMAC_CTRLB2__DST_DSCR"><strong>DST_DSCR</strong>: Destination Address Descriptor<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">FETCH_FROM_MEM</td><td class="description">Destination address is updated when the descriptor is fetched from the memory.</td></tr><tr class="even"><td class="value">1</td><td class="name">FETCH_DISABLE</td><td class="description">Buffer Descriptor Fetch operation is disabled for the destination.</td></tr></tbody></table></li>
<li id="DMAC_CTRLB2__FC"><strong>FC</strong>: Flow Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">MEM2MEM_DMA_FC</td><td class="description">Memory-to-Memory Transfer DMAC is flow controller</td></tr><tr class="even"><td class="value">0x1</td><td class="name">MEM2PER_DMA_FC</td><td class="description">Memory-to-Peripheral Transfer DMAC is flow controller</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">PER2MEM_DMA_FC</td><td class="description">Peripheral-to-Memory Transfer DMAC is flow controller</td></tr><tr class="even"><td class="value">0x3</td><td class="name">PER2PER_DMA_FC</td><td class="description">Peripheral-to-Peripheral Transfer DMAC is flow controller</td></tr></tbody></table></li>
<li id="DMAC_CTRLB2__SRC_INCR"><strong>SRC_INCR</strong>: Incrementing, Decrementing or Fixed Address for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">INCREMENTING</td><td class="description">The source address is incremented</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DECREMENTING</td><td class="description">The source address is decremented</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">FIXED</td><td class="description">The source address remains unchanged</td></tr></tbody></table></li>
<li id="DMAC_CTRLB2__DST_INCR"><strong>DST_INCR</strong>: Incrementing, Decrementing or Fixed Address for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">INCREMENTING</td><td class="description">The destination address is incremented</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DECREMENTING</td><td class="description">The destination address is decremented</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">FIXED</td><td class="description">The destination address remains unchanged</td></tr></tbody></table></li>
<li id="DMAC_CTRLB2__IEN">
<strong>IEN</strong>
</li>
<p>-</p>
</ul>
<h4 id="DMAC_CFG2">DMAC DMAC Channel Configuration Register (ch_num = 2)</h4>
<p><strong>Name</strong>: DMAC_CFG2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C40A0</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CFG2__FIFOCFG" title="FIFO Configuration">FIFOCFG</a>
</td>
<td>-</td>
<td colspan="3">
<a href="#DMAC_CFG2__AHB_PROT" title="AHB Protection">AHB_PROT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG2__LOCK_IF_L" title="Master Interface Arbiter Lock">LOCK_IF_L</a>
</td>
<td colspan="1">
<a href="#DMAC_CFG2__LOCK_B" title="Bus Lock">LOCK_B</a>
</td>
<td colspan="1">
<a href="#DMAC_CFG2__LOCK_IF" title="Interface Lock">LOCK_IF</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG2__SOD" title="Stop On Done">SOD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG2__DST_H2SEL" title="Software or Hardware Selection for the Destination">DST_H2SEL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG2__SRC_H2SEL" title="Software or Hardware Selection for the Source">SRC_H2SEL</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#DMAC_CFG2__DST_PER" title="Destination with Peripheral identifier">DST_PER</a>
</td>
<td colspan="4">
<a href="#DMAC_CFG2__SRC_PER" title="Source with Peripheral identifier">SRC_PER</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CFG2__SRC_PER"><strong>SRC_PER</strong>: Source with Peripheral identifier</li>
<p>-</p>
<li id="DMAC_CFG2__DST_PER"><strong>DST_PER</strong>: Destination with Peripheral identifier</li>
<p>-</p>
<li id="DMAC_CFG2__SRC_H2SEL"><strong>SRC_H2SEL</strong>: Software or Hardware Selection for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">SW</td><td class="description">Software handshaking interface is used to trigger a transfer request.</td></tr><tr class="even"><td class="value">1</td><td class="name">HW</td><td class="description">Hardware handshaking interface is used to trigger a transfer request.</td></tr></tbody></table></li>
<li id="DMAC_CFG2__DST_H2SEL"><strong>DST_H2SEL</strong>: Software or Hardware Selection for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">SW</td><td class="description">Software handshaking interface is used to trigger a transfer request.</td></tr><tr class="even"><td class="value">1</td><td class="name">HW</td><td class="description">Hardware handshaking interface is used to trigger a transfer request.</td></tr></tbody></table></li>
<li id="DMAC_CFG2__SOD"><strong>SOD</strong>: Stop On Done<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.</td></tr><tr class="even"><td class="value">1</td><td class="name">ENABLE</td><td class="description">STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.</td></tr></tbody></table></li>
<li id="DMAC_CFG2__LOCK_IF"><strong>LOCK_IF</strong>: Interface Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">Interface Lock capability is disabled</td></tr><tr class="even"><td class="value">1</td><td class="name">ENABLE</td><td class="description">Interface Lock capability is enabled</td></tr></tbody></table></li>
<li id="DMAC_CFG2__LOCK_B"><strong>LOCK_B</strong>: Bus Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">AHB Bus Locking capability is disabled.</td></tr></tbody></table></li>
<li id="DMAC_CFG2__LOCK_IF_L"><strong>LOCK_IF_L</strong>: Master Interface Arbiter Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">CHUNK</td><td class="description">The Master Interface Arbiter is locked by the channel x for a chunk transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">BUFFER</td><td class="description">The Master Interface Arbiter is locked by the channel x for a buffer transfer.</td></tr></tbody></table></li>
<li id="DMAC_CFG2__AHB_PROT"><strong>AHB_PROT</strong>: AHB Protection<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">1</td><td class="name">-</td><td class="description">Data access</td></tr></tbody></table></li>
<li id="DMAC_CFG2__FIFOCFG"><strong>FIFOCFG</strong>: FIFO Configuration<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">ALAP_CFG</td><td class="description">The largest defined length AHB burst is performed on the destination AHB interface.</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_CFG</td><td class="description">When half FIFO size is available/filled, a source/destination request is serviced.</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">ASAP_CFG</td><td class="description">When there is enough space/data available to perform a single AHB access, then the request is serviced.</td></tr></tbody></table></li>
</ul>
<h4 id="DMAC_SADDR3">DMAC DMAC Channel Source Address Register (ch_num = 3)</h4>
<p><strong>Name</strong>: DMAC_SADDR3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C40B4</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR3__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR3__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR3__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR3__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_SADDR3__SADDR"><strong>SADDR</strong>: Channel x Source Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_DADDR3">DMAC DMAC Channel Destination Address Register (ch_num = 3)</h4>
<p><strong>Name</strong>: DMAC_DADDR3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C40B8</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR3__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR3__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR3__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR3__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_DADDR3__DADDR"><strong>DADDR</strong>: Channel x Destination Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_DSCR3">DMAC DMAC Channel Descriptor Address Register (ch_num = 3)</h4>
<p><strong>Name</strong>: DMAC_DSCR3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C40BC</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR3__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR3__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR3__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="6">
<a href="#DMAC_DSCR3__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_DSCR3__DSCR"><strong>DSCR</strong>: Buffer Transfer Descriptor Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_CTRLA3">DMAC DMAC Channel Control A Register (ch_num = 3)</h4>
<p><strong>Name</strong>: DMAC_CTRLA3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C40C0</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#DMAC_CTRLA3__DONE" title="">DONE</a>
</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLA3__DST_WIDTH" title="Transfer Width for the Destination">DST_WIDTH</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLA3__SRC_WIDTH" title="Transfer Width for the Source">SRC_WIDTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="3">
<a href="#DMAC_CTRLA3__DCSIZE" title="Destination Chunk Transfer Size">DCSIZE</a>
</td>
<td>-</td>
<td colspan="3">
<a href="#DMAC_CTRLA3__SCSIZE" title="Source Chunk Transfer Size.">SCSIZE</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_CTRLA3__BTSIZE" title="Buffer Transfer Size">BTSIZE</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_CTRLA3__BTSIZE" title="Buffer Transfer Size">BTSIZE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CTRLA3__BTSIZE"><strong>BTSIZE</strong>: Buffer Transfer Size</li>
<p>-</p>
<li id="DMAC_CTRLA3__SCSIZE"><strong>SCSIZE</strong>: Source Chunk Transfer Size.<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CHK_1</td><td class="description">1 data transferred</td></tr><tr class="even"><td class="value">0x1</td><td class="name">CHK_4</td><td class="description">4 data transferred</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">CHK_8</td><td class="description">8 data transferred</td></tr><tr class="even"><td class="value">0x3</td><td class="name">CHK_16</td><td class="description">16 data transferred</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">CHK_32</td><td class="description">32 data transferred</td></tr><tr class="even"><td class="value">0x5</td><td class="name">CHK_64</td><td class="description">64 data transferred</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">CHK_128</td><td class="description">128 data transferred</td></tr><tr class="even"><td class="value">0x7</td><td class="name">CHK_256</td><td class="description">256 data transferred</td></tr></tbody></table></li>
<li id="DMAC_CTRLA3__DCSIZE"><strong>DCSIZE</strong>: Destination Chunk Transfer Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CHK_1</td><td class="description">1 data transferred</td></tr><tr class="even"><td class="value">0x1</td><td class="name">CHK_4</td><td class="description">4 data transferred</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">CHK_8</td><td class="description">8 data transferred</td></tr><tr class="even"><td class="value">0x3</td><td class="name">CHK_16</td><td class="description">16 data transferred</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">CHK_32</td><td class="description">32 data transferred</td></tr><tr class="even"><td class="value">0x5</td><td class="name">CHK_64</td><td class="description">64 data transferred</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">CHK_128</td><td class="description">128 data transferred</td></tr><tr class="even"><td class="value">0x7</td><td class="name">CHK_256</td><td class="description">256 data transferred</td></tr></tbody></table></li>
<li id="DMAC_CTRLA3__SRC_WIDTH"><strong>SRC_WIDTH</strong>: Transfer Width for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BYTE</td><td class="description">the transfer size is set to 8-bit width</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_WORD</td><td class="description">the transfer size is set to 16-bit width</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">WORD</td><td class="description">the transfer size is set to 32-bit width</td></tr></tbody></table></li>
<li id="DMAC_CTRLA3__DST_WIDTH"><strong>DST_WIDTH</strong>: Transfer Width for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BYTE</td><td class="description">the transfer size is set to 8-bit width</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_WORD</td><td class="description">the transfer size is set to 16-bit width</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">WORD</td><td class="description">the transfer size is set to 32-bit width</td></tr></tbody></table></li>
<li id="DMAC_CTRLA3__DONE">
<strong>DONE</strong>
<table class="values">
<thead>
<tr>
<th>Value</th>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="value">0</td>
<td class="name">-</td>
<td class="description">The transfer is performed.</td>
</tr>
<tr class="even">
<td class="value">1</td>
<td class="name">-</td>
<td class="description">If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con-tent of this register.</td>
</tr>
</tbody>
</table>
</li>
</ul>
<h4 id="DMAC_CTRLB3">DMAC DMAC Channel Control B Register (ch_num = 3)</h4>
<p><strong>Name</strong>: DMAC_CTRLB3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C40C4</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#DMAC_CTRLB3__IEN" title="">IEN</a>
</td>
<td colspan="2">
<a href="#DMAC_CTRLB3__DST_INCR" title="Incrementing, Decrementing or Fixed Address for the Destination">DST_INCR</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLB3__SRC_INCR" title="Incrementing, Decrementing or Fixed Address for the Source">SRC_INCR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="3">
<a href="#DMAC_CTRLB3__FC" title="Flow Control">FC</a>
</td>
<td colspan="1">
<a href="#DMAC_CTRLB3__DST_DSCR" title="Destination Address Descriptor">DST_DSCR</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CTRLB3__SRC_DSCR" title="Source Address Descriptor">SRC_DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CTRLB3__SRC_DSCR"><strong>SRC_DSCR</strong>: Source Address Descriptor<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">FETCH_FROM_MEM</td><td class="description">Source address is updated when the descriptor is fetched from the memory.</td></tr><tr class="even"><td class="value">1</td><td class="name">FETCH_DISABLE</td><td class="description">Buffer Descriptor Fetch operation is disabled for the source.</td></tr></tbody></table></li>
<li id="DMAC_CTRLB3__DST_DSCR"><strong>DST_DSCR</strong>: Destination Address Descriptor<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">FETCH_FROM_MEM</td><td class="description">Destination address is updated when the descriptor is fetched from the memory.</td></tr><tr class="even"><td class="value">1</td><td class="name">FETCH_DISABLE</td><td class="description">Buffer Descriptor Fetch operation is disabled for the destination.</td></tr></tbody></table></li>
<li id="DMAC_CTRLB3__FC"><strong>FC</strong>: Flow Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">MEM2MEM_DMA_FC</td><td class="description">Memory-to-Memory Transfer DMAC is flow controller</td></tr><tr class="even"><td class="value">0x1</td><td class="name">MEM2PER_DMA_FC</td><td class="description">Memory-to-Peripheral Transfer DMAC is flow controller</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">PER2MEM_DMA_FC</td><td class="description">Peripheral-to-Memory Transfer DMAC is flow controller</td></tr><tr class="even"><td class="value">0x3</td><td class="name">PER2PER_DMA_FC</td><td class="description">Peripheral-to-Peripheral Transfer DMAC is flow controller</td></tr></tbody></table></li>
<li id="DMAC_CTRLB3__SRC_INCR"><strong>SRC_INCR</strong>: Incrementing, Decrementing or Fixed Address for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">INCREMENTING</td><td class="description">The source address is incremented</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DECREMENTING</td><td class="description">The source address is decremented</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">FIXED</td><td class="description">The source address remains unchanged</td></tr></tbody></table></li>
<li id="DMAC_CTRLB3__DST_INCR"><strong>DST_INCR</strong>: Incrementing, Decrementing or Fixed Address for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">INCREMENTING</td><td class="description">The destination address is incremented</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DECREMENTING</td><td class="description">The destination address is decremented</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">FIXED</td><td class="description">The destination address remains unchanged</td></tr></tbody></table></li>
<li id="DMAC_CTRLB3__IEN">
<strong>IEN</strong>
</li>
<p>-</p>
</ul>
<h4 id="DMAC_CFG3">DMAC DMAC Channel Configuration Register (ch_num = 3)</h4>
<p><strong>Name</strong>: DMAC_CFG3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C40C8</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CFG3__FIFOCFG" title="FIFO Configuration">FIFOCFG</a>
</td>
<td>-</td>
<td colspan="3">
<a href="#DMAC_CFG3__AHB_PROT" title="AHB Protection">AHB_PROT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG3__LOCK_IF_L" title="Master Interface Arbiter Lock">LOCK_IF_L</a>
</td>
<td colspan="1">
<a href="#DMAC_CFG3__LOCK_B" title="Bus Lock">LOCK_B</a>
</td>
<td colspan="1">
<a href="#DMAC_CFG3__LOCK_IF" title="Interface Lock">LOCK_IF</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG3__SOD" title="Stop On Done">SOD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG3__DST_H2SEL" title="Software or Hardware Selection for the Destination">DST_H2SEL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG3__SRC_H2SEL" title="Software or Hardware Selection for the Source">SRC_H2SEL</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#DMAC_CFG3__DST_PER" title="Destination with Peripheral identifier">DST_PER</a>
</td>
<td colspan="4">
<a href="#DMAC_CFG3__SRC_PER" title="Source with Peripheral identifier">SRC_PER</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CFG3__SRC_PER"><strong>SRC_PER</strong>: Source with Peripheral identifier</li>
<p>-</p>
<li id="DMAC_CFG3__DST_PER"><strong>DST_PER</strong>: Destination with Peripheral identifier</li>
<p>-</p>
<li id="DMAC_CFG3__SRC_H2SEL"><strong>SRC_H2SEL</strong>: Software or Hardware Selection for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">SW</td><td class="description">Software handshaking interface is used to trigger a transfer request.</td></tr><tr class="even"><td class="value">1</td><td class="name">HW</td><td class="description">Hardware handshaking interface is used to trigger a transfer request.</td></tr></tbody></table></li>
<li id="DMAC_CFG3__DST_H2SEL"><strong>DST_H2SEL</strong>: Software or Hardware Selection for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">SW</td><td class="description">Software handshaking interface is used to trigger a transfer request.</td></tr><tr class="even"><td class="value">1</td><td class="name">HW</td><td class="description">Hardware handshaking interface is used to trigger a transfer request.</td></tr></tbody></table></li>
<li id="DMAC_CFG3__SOD"><strong>SOD</strong>: Stop On Done<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.</td></tr><tr class="even"><td class="value">1</td><td class="name">ENABLE</td><td class="description">STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.</td></tr></tbody></table></li>
<li id="DMAC_CFG3__LOCK_IF"><strong>LOCK_IF</strong>: Interface Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">Interface Lock capability is disabled</td></tr><tr class="even"><td class="value">1</td><td class="name">ENABLE</td><td class="description">Interface Lock capability is enabled</td></tr></tbody></table></li>
<li id="DMAC_CFG3__LOCK_B"><strong>LOCK_B</strong>: Bus Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">AHB Bus Locking capability is disabled.</td></tr></tbody></table></li>
<li id="DMAC_CFG3__LOCK_IF_L"><strong>LOCK_IF_L</strong>: Master Interface Arbiter Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">CHUNK</td><td class="description">The Master Interface Arbiter is locked by the channel x for a chunk transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">BUFFER</td><td class="description">The Master Interface Arbiter is locked by the channel x for a buffer transfer.</td></tr></tbody></table></li>
<li id="DMAC_CFG3__AHB_PROT"><strong>AHB_PROT</strong>: AHB Protection<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">1</td><td class="name">-</td><td class="description">Data access</td></tr></tbody></table></li>
<li id="DMAC_CFG3__FIFOCFG"><strong>FIFOCFG</strong>: FIFO Configuration<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">ALAP_CFG</td><td class="description">The largest defined length AHB burst is performed on the destination AHB interface.</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_CFG</td><td class="description">When half FIFO size is available/filled, a source/destination request is serviced.</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">ASAP_CFG</td><td class="description">When there is enough space/data available to perform a single AHB access, then the request is serviced.</td></tr></tbody></table></li>
</ul>
<h4 id="DMAC_SADDR4">DMAC DMAC Channel Source Address Register (ch_num = 4)</h4>
<p><strong>Name</strong>: DMAC_SADDR4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C40DC</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR4__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR4__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR4__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR4__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_SADDR4__SADDR"><strong>SADDR</strong>: Channel x Source Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_DADDR4">DMAC DMAC Channel Destination Address Register (ch_num = 4)</h4>
<p><strong>Name</strong>: DMAC_DADDR4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C40E0</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR4__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR4__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR4__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR4__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_DADDR4__DADDR"><strong>DADDR</strong>: Channel x Destination Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_DSCR4">DMAC DMAC Channel Descriptor Address Register (ch_num = 4)</h4>
<p><strong>Name</strong>: DMAC_DSCR4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C40E4</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR4__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR4__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR4__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="6">
<a href="#DMAC_DSCR4__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_DSCR4__DSCR"><strong>DSCR</strong>: Buffer Transfer Descriptor Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_CTRLA4">DMAC DMAC Channel Control A Register (ch_num = 4)</h4>
<p><strong>Name</strong>: DMAC_CTRLA4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C40E8</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#DMAC_CTRLA4__DONE" title="">DONE</a>
</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLA4__DST_WIDTH" title="Transfer Width for the Destination">DST_WIDTH</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLA4__SRC_WIDTH" title="Transfer Width for the Source">SRC_WIDTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="3">
<a href="#DMAC_CTRLA4__DCSIZE" title="Destination Chunk Transfer Size">DCSIZE</a>
</td>
<td>-</td>
<td colspan="3">
<a href="#DMAC_CTRLA4__SCSIZE" title="Source Chunk Transfer Size.">SCSIZE</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_CTRLA4__BTSIZE" title="Buffer Transfer Size">BTSIZE</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_CTRLA4__BTSIZE" title="Buffer Transfer Size">BTSIZE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CTRLA4__BTSIZE"><strong>BTSIZE</strong>: Buffer Transfer Size</li>
<p>-</p>
<li id="DMAC_CTRLA4__SCSIZE"><strong>SCSIZE</strong>: Source Chunk Transfer Size.<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CHK_1</td><td class="description">1 data transferred</td></tr><tr class="even"><td class="value">0x1</td><td class="name">CHK_4</td><td class="description">4 data transferred</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">CHK_8</td><td class="description">8 data transferred</td></tr><tr class="even"><td class="value">0x3</td><td class="name">CHK_16</td><td class="description">16 data transferred</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">CHK_32</td><td class="description">32 data transferred</td></tr><tr class="even"><td class="value">0x5</td><td class="name">CHK_64</td><td class="description">64 data transferred</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">CHK_128</td><td class="description">128 data transferred</td></tr><tr class="even"><td class="value">0x7</td><td class="name">CHK_256</td><td class="description">256 data transferred</td></tr></tbody></table></li>
<li id="DMAC_CTRLA4__DCSIZE"><strong>DCSIZE</strong>: Destination Chunk Transfer Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CHK_1</td><td class="description">1 data transferred</td></tr><tr class="even"><td class="value">0x1</td><td class="name">CHK_4</td><td class="description">4 data transferred</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">CHK_8</td><td class="description">8 data transferred</td></tr><tr class="even"><td class="value">0x3</td><td class="name">CHK_16</td><td class="description">16 data transferred</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">CHK_32</td><td class="description">32 data transferred</td></tr><tr class="even"><td class="value">0x5</td><td class="name">CHK_64</td><td class="description">64 data transferred</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">CHK_128</td><td class="description">128 data transferred</td></tr><tr class="even"><td class="value">0x7</td><td class="name">CHK_256</td><td class="description">256 data transferred</td></tr></tbody></table></li>
<li id="DMAC_CTRLA4__SRC_WIDTH"><strong>SRC_WIDTH</strong>: Transfer Width for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BYTE</td><td class="description">the transfer size is set to 8-bit width</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_WORD</td><td class="description">the transfer size is set to 16-bit width</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">WORD</td><td class="description">the transfer size is set to 32-bit width</td></tr></tbody></table></li>
<li id="DMAC_CTRLA4__DST_WIDTH"><strong>DST_WIDTH</strong>: Transfer Width for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BYTE</td><td class="description">the transfer size is set to 8-bit width</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_WORD</td><td class="description">the transfer size is set to 16-bit width</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">WORD</td><td class="description">the transfer size is set to 32-bit width</td></tr></tbody></table></li>
<li id="DMAC_CTRLA4__DONE">
<strong>DONE</strong>
<table class="values">
<thead>
<tr>
<th>Value</th>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="value">0</td>
<td class="name">-</td>
<td class="description">The transfer is performed.</td>
</tr>
<tr class="even">
<td class="value">1</td>
<td class="name">-</td>
<td class="description">If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con-tent of this register.</td>
</tr>
</tbody>
</table>
</li>
</ul>
<h4 id="DMAC_CTRLB4">DMAC DMAC Channel Control B Register (ch_num = 4)</h4>
<p><strong>Name</strong>: DMAC_CTRLB4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C40EC</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#DMAC_CTRLB4__IEN" title="">IEN</a>
</td>
<td colspan="2">
<a href="#DMAC_CTRLB4__DST_INCR" title="Incrementing, Decrementing or Fixed Address for the Destination">DST_INCR</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLB4__SRC_INCR" title="Incrementing, Decrementing or Fixed Address for the Source">SRC_INCR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="3">
<a href="#DMAC_CTRLB4__FC" title="Flow Control">FC</a>
</td>
<td colspan="1">
<a href="#DMAC_CTRLB4__DST_DSCR" title="Destination Address Descriptor">DST_DSCR</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CTRLB4__SRC_DSCR" title="Source Address Descriptor">SRC_DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CTRLB4__SRC_DSCR"><strong>SRC_DSCR</strong>: Source Address Descriptor<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">FETCH_FROM_MEM</td><td class="description">Source address is updated when the descriptor is fetched from the memory.</td></tr><tr class="even"><td class="value">1</td><td class="name">FETCH_DISABLE</td><td class="description">Buffer Descriptor Fetch operation is disabled for the source.</td></tr></tbody></table></li>
<li id="DMAC_CTRLB4__DST_DSCR"><strong>DST_DSCR</strong>: Destination Address Descriptor<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">FETCH_FROM_MEM</td><td class="description">Destination address is updated when the descriptor is fetched from the memory.</td></tr><tr class="even"><td class="value">1</td><td class="name">FETCH_DISABLE</td><td class="description">Buffer Descriptor Fetch operation is disabled for the destination.</td></tr></tbody></table></li>
<li id="DMAC_CTRLB4__FC"><strong>FC</strong>: Flow Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">MEM2MEM_DMA_FC</td><td class="description">Memory-to-Memory Transfer DMAC is flow controller</td></tr><tr class="even"><td class="value">0x1</td><td class="name">MEM2PER_DMA_FC</td><td class="description">Memory-to-Peripheral Transfer DMAC is flow controller</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">PER2MEM_DMA_FC</td><td class="description">Peripheral-to-Memory Transfer DMAC is flow controller</td></tr><tr class="even"><td class="value">0x3</td><td class="name">PER2PER_DMA_FC</td><td class="description">Peripheral-to-Peripheral Transfer DMAC is flow controller</td></tr></tbody></table></li>
<li id="DMAC_CTRLB4__SRC_INCR"><strong>SRC_INCR</strong>: Incrementing, Decrementing or Fixed Address for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">INCREMENTING</td><td class="description">The source address is incremented</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DECREMENTING</td><td class="description">The source address is decremented</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">FIXED</td><td class="description">The source address remains unchanged</td></tr></tbody></table></li>
<li id="DMAC_CTRLB4__DST_INCR"><strong>DST_INCR</strong>: Incrementing, Decrementing or Fixed Address for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">INCREMENTING</td><td class="description">The destination address is incremented</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DECREMENTING</td><td class="description">The destination address is decremented</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">FIXED</td><td class="description">The destination address remains unchanged</td></tr></tbody></table></li>
<li id="DMAC_CTRLB4__IEN">
<strong>IEN</strong>
</li>
<p>-</p>
</ul>
<h4 id="DMAC_CFG4">DMAC DMAC Channel Configuration Register (ch_num = 4)</h4>
<p><strong>Name</strong>: DMAC_CFG4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C40F0</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CFG4__FIFOCFG" title="FIFO Configuration">FIFOCFG</a>
</td>
<td>-</td>
<td colspan="3">
<a href="#DMAC_CFG4__AHB_PROT" title="AHB Protection">AHB_PROT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG4__LOCK_IF_L" title="Master Interface Arbiter Lock">LOCK_IF_L</a>
</td>
<td colspan="1">
<a href="#DMAC_CFG4__LOCK_B" title="Bus Lock">LOCK_B</a>
</td>
<td colspan="1">
<a href="#DMAC_CFG4__LOCK_IF" title="Interface Lock">LOCK_IF</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG4__SOD" title="Stop On Done">SOD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG4__DST_H2SEL" title="Software or Hardware Selection for the Destination">DST_H2SEL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG4__SRC_H2SEL" title="Software or Hardware Selection for the Source">SRC_H2SEL</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#DMAC_CFG4__DST_PER" title="Destination with Peripheral identifier">DST_PER</a>
</td>
<td colspan="4">
<a href="#DMAC_CFG4__SRC_PER" title="Source with Peripheral identifier">SRC_PER</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CFG4__SRC_PER"><strong>SRC_PER</strong>: Source with Peripheral identifier</li>
<p>-</p>
<li id="DMAC_CFG4__DST_PER"><strong>DST_PER</strong>: Destination with Peripheral identifier</li>
<p>-</p>
<li id="DMAC_CFG4__SRC_H2SEL"><strong>SRC_H2SEL</strong>: Software or Hardware Selection for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">SW</td><td class="description">Software handshaking interface is used to trigger a transfer request.</td></tr><tr class="even"><td class="value">1</td><td class="name">HW</td><td class="description">Hardware handshaking interface is used to trigger a transfer request.</td></tr></tbody></table></li>
<li id="DMAC_CFG4__DST_H2SEL"><strong>DST_H2SEL</strong>: Software or Hardware Selection for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">SW</td><td class="description">Software handshaking interface is used to trigger a transfer request.</td></tr><tr class="even"><td class="value">1</td><td class="name">HW</td><td class="description">Hardware handshaking interface is used to trigger a transfer request.</td></tr></tbody></table></li>
<li id="DMAC_CFG4__SOD"><strong>SOD</strong>: Stop On Done<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.</td></tr><tr class="even"><td class="value">1</td><td class="name">ENABLE</td><td class="description">STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.</td></tr></tbody></table></li>
<li id="DMAC_CFG4__LOCK_IF"><strong>LOCK_IF</strong>: Interface Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">Interface Lock capability is disabled</td></tr><tr class="even"><td class="value">1</td><td class="name">ENABLE</td><td class="description">Interface Lock capability is enabled</td></tr></tbody></table></li>
<li id="DMAC_CFG4__LOCK_B"><strong>LOCK_B</strong>: Bus Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">AHB Bus Locking capability is disabled.</td></tr></tbody></table></li>
<li id="DMAC_CFG4__LOCK_IF_L"><strong>LOCK_IF_L</strong>: Master Interface Arbiter Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">CHUNK</td><td class="description">The Master Interface Arbiter is locked by the channel x for a chunk transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">BUFFER</td><td class="description">The Master Interface Arbiter is locked by the channel x for a buffer transfer.</td></tr></tbody></table></li>
<li id="DMAC_CFG4__AHB_PROT"><strong>AHB_PROT</strong>: AHB Protection<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">1</td><td class="name">-</td><td class="description">Data access</td></tr></tbody></table></li>
<li id="DMAC_CFG4__FIFOCFG"><strong>FIFOCFG</strong>: FIFO Configuration<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">ALAP_CFG</td><td class="description">The largest defined length AHB burst is performed on the destination AHB interface.</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_CFG</td><td class="description">When half FIFO size is available/filled, a source/destination request is serviced.</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">ASAP_CFG</td><td class="description">When there is enough space/data available to perform a single AHB access, then the request is serviced.</td></tr></tbody></table></li>
</ul>
<h4 id="DMAC_SADDR5">DMAC DMAC Channel Source Address Register (ch_num = 5)</h4>
<p><strong>Name</strong>: DMAC_SADDR5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4104</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR5__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR5__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR5__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_SADDR5__SADDR" title="Channel x Source Address">SADDR</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_SADDR5__SADDR"><strong>SADDR</strong>: Channel x Source Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_DADDR5">DMAC DMAC Channel Destination Address Register (ch_num = 5)</h4>
<p><strong>Name</strong>: DMAC_DADDR5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4108</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR5__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR5__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR5__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DADDR5__DADDR" title="Channel x Destination Address">DADDR</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_DADDR5__DADDR"><strong>DADDR</strong>: Channel x Destination Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_DSCR5">DMAC DMAC Channel Descriptor Address Register (ch_num = 5)</h4>
<p><strong>Name</strong>: DMAC_DSCR5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C410C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR5__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR5__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_DSCR5__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="6">
<a href="#DMAC_DSCR5__DSCR" title="Buffer Transfer Descriptor Address">DSCR</a>
</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_DSCR5__DSCR"><strong>DSCR</strong>: Buffer Transfer Descriptor Address</li>
<p>-</p>
</ul>
<h4 id="DMAC_CTRLA5">DMAC DMAC Channel Control A Register (ch_num = 5)</h4>
<p><strong>Name</strong>: DMAC_CTRLA5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4110</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#DMAC_CTRLA5__DONE" title="">DONE</a>
</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLA5__DST_WIDTH" title="Transfer Width for the Destination">DST_WIDTH</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLA5__SRC_WIDTH" title="Transfer Width for the Source">SRC_WIDTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="3">
<a href="#DMAC_CTRLA5__DCSIZE" title="Destination Chunk Transfer Size">DCSIZE</a>
</td>
<td>-</td>
<td colspan="3">
<a href="#DMAC_CTRLA5__SCSIZE" title="Source Chunk Transfer Size.">SCSIZE</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_CTRLA5__BTSIZE" title="Buffer Transfer Size">BTSIZE</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_CTRLA5__BTSIZE" title="Buffer Transfer Size">BTSIZE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CTRLA5__BTSIZE"><strong>BTSIZE</strong>: Buffer Transfer Size</li>
<p>-</p>
<li id="DMAC_CTRLA5__SCSIZE"><strong>SCSIZE</strong>: Source Chunk Transfer Size.<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CHK_1</td><td class="description">1 data transferred</td></tr><tr class="even"><td class="value">0x1</td><td class="name">CHK_4</td><td class="description">4 data transferred</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">CHK_8</td><td class="description">8 data transferred</td></tr><tr class="even"><td class="value">0x3</td><td class="name">CHK_16</td><td class="description">16 data transferred</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">CHK_32</td><td class="description">32 data transferred</td></tr><tr class="even"><td class="value">0x5</td><td class="name">CHK_64</td><td class="description">64 data transferred</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">CHK_128</td><td class="description">128 data transferred</td></tr><tr class="even"><td class="value">0x7</td><td class="name">CHK_256</td><td class="description">256 data transferred</td></tr></tbody></table></li>
<li id="DMAC_CTRLA5__DCSIZE"><strong>DCSIZE</strong>: Destination Chunk Transfer Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CHK_1</td><td class="description">1 data transferred</td></tr><tr class="even"><td class="value">0x1</td><td class="name">CHK_4</td><td class="description">4 data transferred</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">CHK_8</td><td class="description">8 data transferred</td></tr><tr class="even"><td class="value">0x3</td><td class="name">CHK_16</td><td class="description">16 data transferred</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">CHK_32</td><td class="description">32 data transferred</td></tr><tr class="even"><td class="value">0x5</td><td class="name">CHK_64</td><td class="description">64 data transferred</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">CHK_128</td><td class="description">128 data transferred</td></tr><tr class="even"><td class="value">0x7</td><td class="name">CHK_256</td><td class="description">256 data transferred</td></tr></tbody></table></li>
<li id="DMAC_CTRLA5__SRC_WIDTH"><strong>SRC_WIDTH</strong>: Transfer Width for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BYTE</td><td class="description">the transfer size is set to 8-bit width</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_WORD</td><td class="description">the transfer size is set to 16-bit width</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">WORD</td><td class="description">the transfer size is set to 32-bit width</td></tr></tbody></table></li>
<li id="DMAC_CTRLA5__DST_WIDTH"><strong>DST_WIDTH</strong>: Transfer Width for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">BYTE</td><td class="description">the transfer size is set to 8-bit width</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_WORD</td><td class="description">the transfer size is set to 16-bit width</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">WORD</td><td class="description">the transfer size is set to 32-bit width</td></tr></tbody></table></li>
<li id="DMAC_CTRLA5__DONE">
<strong>DONE</strong>
<table class="values">
<thead>
<tr>
<th>Value</th>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="value">0</td>
<td class="name">-</td>
<td class="description">The transfer is performed.</td>
</tr>
<tr class="even">
<td class="value">1</td>
<td class="name">-</td>
<td class="description">If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con-tent of this register.</td>
</tr>
</tbody>
</table>
</li>
</ul>
<h4 id="DMAC_CTRLB5">DMAC DMAC Channel Control B Register (ch_num = 5)</h4>
<p><strong>Name</strong>: DMAC_CTRLB5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4114</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#DMAC_CTRLB5__IEN" title="">IEN</a>
</td>
<td colspan="2">
<a href="#DMAC_CTRLB5__DST_INCR" title="Incrementing, Decrementing or Fixed Address for the Destination">DST_INCR</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CTRLB5__SRC_INCR" title="Incrementing, Decrementing or Fixed Address for the Source">SRC_INCR</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="3">
<a href="#DMAC_CTRLB5__FC" title="Flow Control">FC</a>
</td>
<td colspan="1">
<a href="#DMAC_CTRLB5__DST_DSCR" title="Destination Address Descriptor">DST_DSCR</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CTRLB5__SRC_DSCR" title="Source Address Descriptor">SRC_DSCR</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CTRLB5__SRC_DSCR"><strong>SRC_DSCR</strong>: Source Address Descriptor<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">FETCH_FROM_MEM</td><td class="description">Source address is updated when the descriptor is fetched from the memory.</td></tr><tr class="even"><td class="value">1</td><td class="name">FETCH_DISABLE</td><td class="description">Buffer Descriptor Fetch operation is disabled for the source.</td></tr></tbody></table></li>
<li id="DMAC_CTRLB5__DST_DSCR"><strong>DST_DSCR</strong>: Destination Address Descriptor<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">FETCH_FROM_MEM</td><td class="description">Destination address is updated when the descriptor is fetched from the memory.</td></tr><tr class="even"><td class="value">1</td><td class="name">FETCH_DISABLE</td><td class="description">Buffer Descriptor Fetch operation is disabled for the destination.</td></tr></tbody></table></li>
<li id="DMAC_CTRLB5__FC"><strong>FC</strong>: Flow Control<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">MEM2MEM_DMA_FC</td><td class="description">Memory-to-Memory Transfer DMAC is flow controller</td></tr><tr class="even"><td class="value">0x1</td><td class="name">MEM2PER_DMA_FC</td><td class="description">Memory-to-Peripheral Transfer DMAC is flow controller</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">PER2MEM_DMA_FC</td><td class="description">Peripheral-to-Memory Transfer DMAC is flow controller</td></tr><tr class="even"><td class="value">0x3</td><td class="name">PER2PER_DMA_FC</td><td class="description">Peripheral-to-Peripheral Transfer DMAC is flow controller</td></tr></tbody></table></li>
<li id="DMAC_CTRLB5__SRC_INCR"><strong>SRC_INCR</strong>: Incrementing, Decrementing or Fixed Address for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">INCREMENTING</td><td class="description">The source address is incremented</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DECREMENTING</td><td class="description">The source address is decremented</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">FIXED</td><td class="description">The source address remains unchanged</td></tr></tbody></table></li>
<li id="DMAC_CTRLB5__DST_INCR"><strong>DST_INCR</strong>: Incrementing, Decrementing or Fixed Address for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">INCREMENTING</td><td class="description">The destination address is incremented</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DECREMENTING</td><td class="description">The destination address is decremented</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">FIXED</td><td class="description">The destination address remains unchanged</td></tr></tbody></table></li>
<li id="DMAC_CTRLB5__IEN">
<strong>IEN</strong>
</li>
<p>-</p>
</ul>
<h4 id="DMAC_CFG5">DMAC DMAC Channel Configuration Register (ch_num = 5)</h4>
<p><strong>Name</strong>: DMAC_CFG5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C4118</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#DMAC_CFG5__FIFOCFG" title="FIFO Configuration">FIFOCFG</a>
</td>
<td>-</td>
<td colspan="3">
<a href="#DMAC_CFG5__AHB_PROT" title="AHB Protection">AHB_PROT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG5__LOCK_IF_L" title="Master Interface Arbiter Lock">LOCK_IF_L</a>
</td>
<td colspan="1">
<a href="#DMAC_CFG5__LOCK_B" title="Bus Lock">LOCK_B</a>
</td>
<td colspan="1">
<a href="#DMAC_CFG5__LOCK_IF" title="Interface Lock">LOCK_IF</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG5__SOD" title="Stop On Done">SOD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG5__DST_H2SEL" title="Software or Hardware Selection for the Destination">DST_H2SEL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_CFG5__SRC_H2SEL" title="Software or Hardware Selection for the Source">SRC_H2SEL</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#DMAC_CFG5__DST_PER" title="Destination with Peripheral identifier">DST_PER</a>
</td>
<td colspan="4">
<a href="#DMAC_CFG5__SRC_PER" title="Source with Peripheral identifier">SRC_PER</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_CFG5__SRC_PER"><strong>SRC_PER</strong>: Source with Peripheral identifier</li>
<p>-</p>
<li id="DMAC_CFG5__DST_PER"><strong>DST_PER</strong>: Destination with Peripheral identifier</li>
<p>-</p>
<li id="DMAC_CFG5__SRC_H2SEL"><strong>SRC_H2SEL</strong>: Software or Hardware Selection for the Source<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">SW</td><td class="description">Software handshaking interface is used to trigger a transfer request.</td></tr><tr class="even"><td class="value">1</td><td class="name">HW</td><td class="description">Hardware handshaking interface is used to trigger a transfer request.</td></tr></tbody></table></li>
<li id="DMAC_CFG5__DST_H2SEL"><strong>DST_H2SEL</strong>: Software or Hardware Selection for the Destination<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">SW</td><td class="description">Software handshaking interface is used to trigger a transfer request.</td></tr><tr class="even"><td class="value">1</td><td class="name">HW</td><td class="description">Hardware handshaking interface is used to trigger a transfer request.</td></tr></tbody></table></li>
<li id="DMAC_CFG5__SOD"><strong>SOD</strong>: Stop On Done<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.</td></tr><tr class="even"><td class="value">1</td><td class="name">ENABLE</td><td class="description">STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.</td></tr></tbody></table></li>
<li id="DMAC_CFG5__LOCK_IF"><strong>LOCK_IF</strong>: Interface Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">Interface Lock capability is disabled</td></tr><tr class="even"><td class="value">1</td><td class="name">ENABLE</td><td class="description">Interface Lock capability is enabled</td></tr></tbody></table></li>
<li id="DMAC_CFG5__LOCK_B"><strong>LOCK_B</strong>: Bus Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">DISABLE</td><td class="description">AHB Bus Locking capability is disabled.</td></tr></tbody></table></li>
<li id="DMAC_CFG5__LOCK_IF_L"><strong>LOCK_IF_L</strong>: Master Interface Arbiter Lock<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">CHUNK</td><td class="description">The Master Interface Arbiter is locked by the channel x for a chunk transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">BUFFER</td><td class="description">The Master Interface Arbiter is locked by the channel x for a buffer transfer.</td></tr></tbody></table></li>
<li id="DMAC_CFG5__AHB_PROT"><strong>AHB_PROT</strong>: AHB Protection<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">1</td><td class="name">-</td><td class="description">Data access</td></tr></tbody></table></li>
<li id="DMAC_CFG5__FIFOCFG"><strong>FIFOCFG</strong>: FIFO Configuration<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">ALAP_CFG</td><td class="description">The largest defined length AHB burst is performed on the destination AHB interface.</td></tr><tr class="even"><td class="value">0x1</td><td class="name">HALF_CFG</td><td class="description">When half FIFO size is available/filled, a source/destination request is serviced.</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">ASAP_CFG</td><td class="description">When there is enough space/data available to perform a single AHB access, then the request is serviced.</td></tr></tbody></table></li>
</ul>
<h4 id="DMAC_WPMR">DMAC DMAC Write Protect Mode Register</h4>
<p><strong>Name</strong>: DMAC_WPMR</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400C41E4</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_WPMR__WPKEY" title="Write Protect KEY">WPKEY</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_WPMR__WPKEY" title="Write Protect KEY">WPKEY</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_WPMR__WPKEY" title="Write Protect KEY">WPKEY</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_WPMR__WPEN" title="Write Protect Enable">WPEN</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_WPMR__WPEN"><strong>WPEN</strong>: Write Protect Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Disables the Write Protect if WPKEY corresponds to 0x444D4143 ("DMAC" in ASCII).</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the Write Protect if WPKEY corresponds to 0x444D4143 ("DMAC" in ASCII).</td></tr></tbody></table></li>
<li id="DMAC_WPMR__WPKEY"><strong>WPKEY</strong>: Write Protect KEY</li>
<p>-</p>
</ul>
<h4 id="DMAC_WPSR">DMAC DMAC Write Protect Status Register</h4>
<p><strong>Name</strong>: DMAC_WPSR</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400C41E8</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_WPSR__WPVSRC" title="Write Protect Violation Source">WPVSRC</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#DMAC_WPSR__WPVSRC" title="Write Protect Violation Source">WPVSRC</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#DMAC_WPSR__WPVS" title="Write Protect Violation Status">WPVS</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="DMAC_WPSR__WPVS"><strong>WPVS</strong>: Write Protect Violation Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No Write Protect Violation has occurred since the last read of the DMAC_WPSR register.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">A Write Protect Violation has occurred since the last read of the DMAC_WPSR register. If this violation is an unauthor-ized attempt to write a protected register, the associated violation is reported into field WPVSRC.</td></tr></tbody></table></li>
<li id="DMAC_WPSR__WPVSRC"><strong>WPVSRC</strong>: Write Protect Violation Source</li>
<p>-</p>
</ul>
</div>
</div>
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