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android / platform / external / arduino-ide / f876b2abdebd02acfa4ba21e607327be4f9668d4 / . / hardware / arduino / sam / system / CMSIS / Device / ATMEL / sam3u / html / UDPHS.html
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8" />
<title>SAM3U UDPHS</title>
<link rel="stylesheet" type="text/css" href="css/html.css" media="all" />
</head>
<body id="abstract">
<div id="container">
<div id="content">
<a id="UDPHS"></a>
<h1>SAM3U UDPHS</h1>
<a id="UDPHS__User_Interface"></a>
<h2>USB High Speed Device Port (UDPHS) User Interface</h2>
<!--As per 6227N programmer datasheet.-->
<h3>Registers</h3>
<table class="registers">
<caption>Register Mapping</caption>
<thead>
<tr>
<th class="address">Address</th>
<th class="description">Register</th>
<th class="name">Name</th>
<th class="access">Access</th>
<th class="reset">Reset</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="address" id="address_0x400A4000">0x400A4000</td>
<td class="description">UDPHS Control Register</td>
<td class="name">
<a href="#UDPHS_CTRL" title="UDPHS Control Register" class="one_click_away">UDPHS_CTRL</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000200</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4004">0x400A4004</td>
<td class="description">UDPHS Frame Number Register</td>
<td class="name">
<a href="#UDPHS_FNUM" title="UDPHS Frame Number Register" class="one_click_away">UDPHS_FNUM</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4010">0x400A4010</td>
<td class="description">UDPHS Interrupt Enable Register</td>
<td class="name">
<a href="#UDPHS_IEN" title="UDPHS Interrupt Enable Register" class="one_click_away">UDPHS_IEN</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000010</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4014">0x400A4014</td>
<td class="description">UDPHS Interrupt Status Register</td>
<td class="name">
<a href="#UDPHS_INTSTA" title="UDPHS Interrupt Status Register" class="one_click_away">UDPHS_INTSTA</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4018">0x400A4018</td>
<td class="description">UDPHS Clear Interrupt Register</td>
<td class="name">
<a href="#UDPHS_CLRINT" title="UDPHS Clear Interrupt Register" class="one_click_away">UDPHS_CLRINT</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A401C">0x400A401C</td>
<td class="description">UDPHS Endpoints Reset Register</td>
<td class="name">
<a href="#UDPHS_EPTRST" title="UDPHS Endpoints Reset Register" class="one_click_away">UDPHS_EPTRST</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A40E0">0x400A40E0</td>
<td class="description">UDPHS Test Register</td>
<td class="name">
<a href="#UDPHS_TST" title="UDPHS Test Register" class="one_click_away">UDPHS_TST</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A40F0">0x400A40F0</td>
<td class="description">UDPHS Name1 Register</td>
<td class="name">
<a href="#UDPHS_IPNAME1" title="UDPHS Name1 Register" class="one_click_away">UDPHS_IPNAME1</a>
</td>
<td class="access">read-only</td>
<td class="address">0x48555342</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A40F4">0x400A40F4</td>
<td class="description">UDPHS Name2 Register</td>
<td class="name">
<a href="#UDPHS_IPNAME2" title="UDPHS Name2 Register" class="one_click_away">UDPHS_IPNAME2</a>
</td>
<td class="access">read-only</td>
<td class="address">0x32444556</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A40F8">0x400A40F8</td>
<td class="description">UDPHS Features Register</td>
<td class="name">
<a href="#UDPHS_IPFEATURES" title="UDPHS Features Register" class="one_click_away">UDPHS_IPFEATURES</a>
</td>
<td class="access">read-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4100">0x400A4100</td>
<td class="description">UDPHS Endpoint Configuration Register (endpoint = 0)</td>
<td class="name">
<a href="#UDPHS_EPTCFG0" title="UDPHS Endpoint Configuration Register (endpoint = 0)" class="one_click_away">UDPHS_EPTCFG0</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4104">0x400A4104</td>
<td class="description">UDPHS Endpoint Control Enable Register (endpoint = 0)</td>
<td class="name">
<a href="#UDPHS_EPTCTLENB0" title="UDPHS Endpoint Control Enable Register (endpoint = 0)" class="one_click_away">UDPHS_EPTCTLENB0</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4108">0x400A4108</td>
<td class="description">UDPHS Endpoint Control Disable Register (endpoint = 0)</td>
<td class="name">
<a href="#UDPHS_EPTCTLDIS0" title="UDPHS Endpoint Control Disable Register (endpoint = 0)" class="one_click_away">UDPHS_EPTCTLDIS0</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A410C">0x400A410C</td>
<td class="description">UDPHS Endpoint Control Register (endpoint = 0)</td>
<td class="name">
<a href="#UDPHS_EPTCTL0" title="UDPHS Endpoint Control Register (endpoint = 0)" class="one_click_away">UDPHS_EPTCTL0</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4114">0x400A4114</td>
<td class="description">UDPHS Endpoint Set Status Register (endpoint = 0)</td>
<td class="name">
<a href="#UDPHS_EPTSETSTA0" title="UDPHS Endpoint Set Status Register (endpoint = 0)" class="one_click_away">UDPHS_EPTSETSTA0</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4118">0x400A4118</td>
<td class="description">UDPHS Endpoint Clear Status Register (endpoint = 0)</td>
<td class="name">
<a href="#UDPHS_EPTCLRSTA0" title="UDPHS Endpoint Clear Status Register (endpoint = 0)" class="one_click_away">UDPHS_EPTCLRSTA0</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A411C">0x400A411C</td>
<td class="description">UDPHS Endpoint Status Register (endpoint = 0)</td>
<td class="name">
<a href="#UDPHS_EPTSTA0" title="UDPHS Endpoint Status Register (endpoint = 0)" class="one_click_away">UDPHS_EPTSTA0</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000040</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4120">0x400A4120</td>
<td class="description">UDPHS Endpoint Configuration Register (endpoint = 1)</td>
<td class="name">
<a href="#UDPHS_EPTCFG1" title="UDPHS Endpoint Configuration Register (endpoint = 1)" class="one_click_away">UDPHS_EPTCFG1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4124">0x400A4124</td>
<td class="description">UDPHS Endpoint Control Enable Register (endpoint = 1)</td>
<td class="name">
<a href="#UDPHS_EPTCTLENB1" title="UDPHS Endpoint Control Enable Register (endpoint = 1)" class="one_click_away">UDPHS_EPTCTLENB1</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4128">0x400A4128</td>
<td class="description">UDPHS Endpoint Control Disable Register (endpoint = 1)</td>
<td class="name">
<a href="#UDPHS_EPTCTLDIS1" title="UDPHS Endpoint Control Disable Register (endpoint = 1)" class="one_click_away">UDPHS_EPTCTLDIS1</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A412C">0x400A412C</td>
<td class="description">UDPHS Endpoint Control Register (endpoint = 1)</td>
<td class="name">
<a href="#UDPHS_EPTCTL1" title="UDPHS Endpoint Control Register (endpoint = 1)" class="one_click_away">UDPHS_EPTCTL1</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4134">0x400A4134</td>
<td class="description">UDPHS Endpoint Set Status Register (endpoint = 1)</td>
<td class="name">
<a href="#UDPHS_EPTSETSTA1" title="UDPHS Endpoint Set Status Register (endpoint = 1)" class="one_click_away">UDPHS_EPTSETSTA1</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4138">0x400A4138</td>
<td class="description">UDPHS Endpoint Clear Status Register (endpoint = 1)</td>
<td class="name">
<a href="#UDPHS_EPTCLRSTA1" title="UDPHS Endpoint Clear Status Register (endpoint = 1)" class="one_click_away">UDPHS_EPTCLRSTA1</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A413C">0x400A413C</td>
<td class="description">UDPHS Endpoint Status Register (endpoint = 1)</td>
<td class="name">
<a href="#UDPHS_EPTSTA1" title="UDPHS Endpoint Status Register (endpoint = 1)" class="one_click_away">UDPHS_EPTSTA1</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000040</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4140">0x400A4140</td>
<td class="description">UDPHS Endpoint Configuration Register (endpoint = 2)</td>
<td class="name">
<a href="#UDPHS_EPTCFG2" title="UDPHS Endpoint Configuration Register (endpoint = 2)" class="one_click_away">UDPHS_EPTCFG2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4144">0x400A4144</td>
<td class="description">UDPHS Endpoint Control Enable Register (endpoint = 2)</td>
<td class="name">
<a href="#UDPHS_EPTCTLENB2" title="UDPHS Endpoint Control Enable Register (endpoint = 2)" class="one_click_away">UDPHS_EPTCTLENB2</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4148">0x400A4148</td>
<td class="description">UDPHS Endpoint Control Disable Register (endpoint = 2)</td>
<td class="name">
<a href="#UDPHS_EPTCTLDIS2" title="UDPHS Endpoint Control Disable Register (endpoint = 2)" class="one_click_away">UDPHS_EPTCTLDIS2</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A414C">0x400A414C</td>
<td class="description">UDPHS Endpoint Control Register (endpoint = 2)</td>
<td class="name">
<a href="#UDPHS_EPTCTL2" title="UDPHS Endpoint Control Register (endpoint = 2)" class="one_click_away">UDPHS_EPTCTL2</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4154">0x400A4154</td>
<td class="description">UDPHS Endpoint Set Status Register (endpoint = 2)</td>
<td class="name">
<a href="#UDPHS_EPTSETSTA2" title="UDPHS Endpoint Set Status Register (endpoint = 2)" class="one_click_away">UDPHS_EPTSETSTA2</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4158">0x400A4158</td>
<td class="description">UDPHS Endpoint Clear Status Register (endpoint = 2)</td>
<td class="name">
<a href="#UDPHS_EPTCLRSTA2" title="UDPHS Endpoint Clear Status Register (endpoint = 2)" class="one_click_away">UDPHS_EPTCLRSTA2</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A415C">0x400A415C</td>
<td class="description">UDPHS Endpoint Status Register (endpoint = 2)</td>
<td class="name">
<a href="#UDPHS_EPTSTA2" title="UDPHS Endpoint Status Register (endpoint = 2)" class="one_click_away">UDPHS_EPTSTA2</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000040</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4160">0x400A4160</td>
<td class="description">UDPHS Endpoint Configuration Register (endpoint = 3)</td>
<td class="name">
<a href="#UDPHS_EPTCFG3" title="UDPHS Endpoint Configuration Register (endpoint = 3)" class="one_click_away">UDPHS_EPTCFG3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4164">0x400A4164</td>
<td class="description">UDPHS Endpoint Control Enable Register (endpoint = 3)</td>
<td class="name">
<a href="#UDPHS_EPTCTLENB3" title="UDPHS Endpoint Control Enable Register (endpoint = 3)" class="one_click_away">UDPHS_EPTCTLENB3</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4168">0x400A4168</td>
<td class="description">UDPHS Endpoint Control Disable Register (endpoint = 3)</td>
<td class="name">
<a href="#UDPHS_EPTCTLDIS3" title="UDPHS Endpoint Control Disable Register (endpoint = 3)" class="one_click_away">UDPHS_EPTCTLDIS3</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A416C">0x400A416C</td>
<td class="description">UDPHS Endpoint Control Register (endpoint = 3)</td>
<td class="name">
<a href="#UDPHS_EPTCTL3" title="UDPHS Endpoint Control Register (endpoint = 3)" class="one_click_away">UDPHS_EPTCTL3</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4174">0x400A4174</td>
<td class="description">UDPHS Endpoint Set Status Register (endpoint = 3)</td>
<td class="name">
<a href="#UDPHS_EPTSETSTA3" title="UDPHS Endpoint Set Status Register (endpoint = 3)" class="one_click_away">UDPHS_EPTSETSTA3</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4178">0x400A4178</td>
<td class="description">UDPHS Endpoint Clear Status Register (endpoint = 3)</td>
<td class="name">
<a href="#UDPHS_EPTCLRSTA3" title="UDPHS Endpoint Clear Status Register (endpoint = 3)" class="one_click_away">UDPHS_EPTCLRSTA3</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A417C">0x400A417C</td>
<td class="description">UDPHS Endpoint Status Register (endpoint = 3)</td>
<td class="name">
<a href="#UDPHS_EPTSTA3" title="UDPHS Endpoint Status Register (endpoint = 3)" class="one_click_away">UDPHS_EPTSTA3</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000040</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4180">0x400A4180</td>
<td class="description">UDPHS Endpoint Configuration Register (endpoint = 4)</td>
<td class="name">
<a href="#UDPHS_EPTCFG4" title="UDPHS Endpoint Configuration Register (endpoint = 4)" class="one_click_away">UDPHS_EPTCFG4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4184">0x400A4184</td>
<td class="description">UDPHS Endpoint Control Enable Register (endpoint = 4)</td>
<td class="name">
<a href="#UDPHS_EPTCTLENB4" title="UDPHS Endpoint Control Enable Register (endpoint = 4)" class="one_click_away">UDPHS_EPTCTLENB4</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4188">0x400A4188</td>
<td class="description">UDPHS Endpoint Control Disable Register (endpoint = 4)</td>
<td class="name">
<a href="#UDPHS_EPTCTLDIS4" title="UDPHS Endpoint Control Disable Register (endpoint = 4)" class="one_click_away">UDPHS_EPTCTLDIS4</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A418C">0x400A418C</td>
<td class="description">UDPHS Endpoint Control Register (endpoint = 4)</td>
<td class="name">
<a href="#UDPHS_EPTCTL4" title="UDPHS Endpoint Control Register (endpoint = 4)" class="one_click_away">UDPHS_EPTCTL4</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4194">0x400A4194</td>
<td class="description">UDPHS Endpoint Set Status Register (endpoint = 4)</td>
<td class="name">
<a href="#UDPHS_EPTSETSTA4" title="UDPHS Endpoint Set Status Register (endpoint = 4)" class="one_click_away">UDPHS_EPTSETSTA4</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4198">0x400A4198</td>
<td class="description">UDPHS Endpoint Clear Status Register (endpoint = 4)</td>
<td class="name">
<a href="#UDPHS_EPTCLRSTA4" title="UDPHS Endpoint Clear Status Register (endpoint = 4)" class="one_click_away">UDPHS_EPTCLRSTA4</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A419C">0x400A419C</td>
<td class="description">UDPHS Endpoint Status Register (endpoint = 4)</td>
<td class="name">
<a href="#UDPHS_EPTSTA4" title="UDPHS Endpoint Status Register (endpoint = 4)" class="one_click_away">UDPHS_EPTSTA4</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000040</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A41A0">0x400A41A0</td>
<td class="description">UDPHS Endpoint Configuration Register (endpoint = 5)</td>
<td class="name">
<a href="#UDPHS_EPTCFG5" title="UDPHS Endpoint Configuration Register (endpoint = 5)" class="one_click_away">UDPHS_EPTCFG5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A41A4">0x400A41A4</td>
<td class="description">UDPHS Endpoint Control Enable Register (endpoint = 5)</td>
<td class="name">
<a href="#UDPHS_EPTCTLENB5" title="UDPHS Endpoint Control Enable Register (endpoint = 5)" class="one_click_away">UDPHS_EPTCTLENB5</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A41A8">0x400A41A8</td>
<td class="description">UDPHS Endpoint Control Disable Register (endpoint = 5)</td>
<td class="name">
<a href="#UDPHS_EPTCTLDIS5" title="UDPHS Endpoint Control Disable Register (endpoint = 5)" class="one_click_away">UDPHS_EPTCTLDIS5</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A41AC">0x400A41AC</td>
<td class="description">UDPHS Endpoint Control Register (endpoint = 5)</td>
<td class="name">
<a href="#UDPHS_EPTCTL5" title="UDPHS Endpoint Control Register (endpoint = 5)" class="one_click_away">UDPHS_EPTCTL5</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A41B4">0x400A41B4</td>
<td class="description">UDPHS Endpoint Set Status Register (endpoint = 5)</td>
<td class="name">
<a href="#UDPHS_EPTSETSTA5" title="UDPHS Endpoint Set Status Register (endpoint = 5)" class="one_click_away">UDPHS_EPTSETSTA5</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A41B8">0x400A41B8</td>
<td class="description">UDPHS Endpoint Clear Status Register (endpoint = 5)</td>
<td class="name">
<a href="#UDPHS_EPTCLRSTA5" title="UDPHS Endpoint Clear Status Register (endpoint = 5)" class="one_click_away">UDPHS_EPTCLRSTA5</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A41BC">0x400A41BC</td>
<td class="description">UDPHS Endpoint Status Register (endpoint = 5)</td>
<td class="name">
<a href="#UDPHS_EPTSTA5" title="UDPHS Endpoint Status Register (endpoint = 5)" class="one_click_away">UDPHS_EPTSTA5</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000040</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A41C0">0x400A41C0</td>
<td class="description">UDPHS Endpoint Configuration Register (endpoint = 6)</td>
<td class="name">
<a href="#UDPHS_EPTCFG6" title="UDPHS Endpoint Configuration Register (endpoint = 6)" class="one_click_away">UDPHS_EPTCFG6</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A41C4">0x400A41C4</td>
<td class="description">UDPHS Endpoint Control Enable Register (endpoint = 6)</td>
<td class="name">
<a href="#UDPHS_EPTCTLENB6" title="UDPHS Endpoint Control Enable Register (endpoint = 6)" class="one_click_away">UDPHS_EPTCTLENB6</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A41C8">0x400A41C8</td>
<td class="description">UDPHS Endpoint Control Disable Register (endpoint = 6)</td>
<td class="name">
<a href="#UDPHS_EPTCTLDIS6" title="UDPHS Endpoint Control Disable Register (endpoint = 6)" class="one_click_away">UDPHS_EPTCTLDIS6</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A41CC">0x400A41CC</td>
<td class="description">UDPHS Endpoint Control Register (endpoint = 6)</td>
<td class="name">
<a href="#UDPHS_EPTCTL6" title="UDPHS Endpoint Control Register (endpoint = 6)" class="one_click_away">UDPHS_EPTCTL6</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A41D4">0x400A41D4</td>
<td class="description">UDPHS Endpoint Set Status Register (endpoint = 6)</td>
<td class="name">
<a href="#UDPHS_EPTSETSTA6" title="UDPHS Endpoint Set Status Register (endpoint = 6)" class="one_click_away">UDPHS_EPTSETSTA6</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A41D8">0x400A41D8</td>
<td class="description">UDPHS Endpoint Clear Status Register (endpoint = 6)</td>
<td class="name">
<a href="#UDPHS_EPTCLRSTA6" title="UDPHS Endpoint Clear Status Register (endpoint = 6)" class="one_click_away">UDPHS_EPTCLRSTA6</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A41DC">0x400A41DC</td>
<td class="description">UDPHS Endpoint Status Register (endpoint = 6)</td>
<td class="name">
<a href="#UDPHS_EPTSTA6" title="UDPHS Endpoint Status Register (endpoint = 6)" class="one_click_away">UDPHS_EPTSTA6</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000040</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4300">0x400A4300</td>
<td class="description">UDPHS DMA Next Descriptor Address Register (channel = 0)</td>
<td class="name">
<a href="#UDPHS_DMANXTDSC0" title="UDPHS DMA Next Descriptor Address Register (channel = 0)" class="one_click_away">UDPHS_DMANXTDSC0</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4304">0x400A4304</td>
<td class="description">UDPHS DMA Channel Address Register (channel = 0)</td>
<td class="name">
<a href="#UDPHS_DMAADDRESS0" title="UDPHS DMA Channel Address Register (channel = 0)" class="one_click_away">UDPHS_DMAADDRESS0</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4308">0x400A4308</td>
<td class="description">UDPHS DMA Channel Control Register (channel = 0)</td>
<td class="name">
<a href="#UDPHS_DMACONTROL0" title="UDPHS DMA Channel Control Register (channel = 0)" class="one_click_away">UDPHS_DMACONTROL0</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A430C">0x400A430C</td>
<td class="description">UDPHS DMA Channel Status Register (channel = 0)</td>
<td class="name">
<a href="#UDPHS_DMASTATUS0" title="UDPHS DMA Channel Status Register (channel = 0)" class="one_click_away">UDPHS_DMASTATUS0</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4310">0x400A4310</td>
<td class="description">UDPHS DMA Next Descriptor Address Register (channel = 1)</td>
<td class="name">
<a href="#UDPHS_DMANXTDSC1" title="UDPHS DMA Next Descriptor Address Register (channel = 1)" class="one_click_away">UDPHS_DMANXTDSC1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4314">0x400A4314</td>
<td class="description">UDPHS DMA Channel Address Register (channel = 1)</td>
<td class="name">
<a href="#UDPHS_DMAADDRESS1" title="UDPHS DMA Channel Address Register (channel = 1)" class="one_click_away">UDPHS_DMAADDRESS1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4318">0x400A4318</td>
<td class="description">UDPHS DMA Channel Control Register (channel = 1)</td>
<td class="name">
<a href="#UDPHS_DMACONTROL1" title="UDPHS DMA Channel Control Register (channel = 1)" class="one_click_away">UDPHS_DMACONTROL1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A431C">0x400A431C</td>
<td class="description">UDPHS DMA Channel Status Register (channel = 1)</td>
<td class="name">
<a href="#UDPHS_DMASTATUS1" title="UDPHS DMA Channel Status Register (channel = 1)" class="one_click_away">UDPHS_DMASTATUS1</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4320">0x400A4320</td>
<td class="description">UDPHS DMA Next Descriptor Address Register (channel = 2)</td>
<td class="name">
<a href="#UDPHS_DMANXTDSC2" title="UDPHS DMA Next Descriptor Address Register (channel = 2)" class="one_click_away">UDPHS_DMANXTDSC2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4324">0x400A4324</td>
<td class="description">UDPHS DMA Channel Address Register (channel = 2)</td>
<td class="name">
<a href="#UDPHS_DMAADDRESS2" title="UDPHS DMA Channel Address Register (channel = 2)" class="one_click_away">UDPHS_DMAADDRESS2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4328">0x400A4328</td>
<td class="description">UDPHS DMA Channel Control Register (channel = 2)</td>
<td class="name">
<a href="#UDPHS_DMACONTROL2" title="UDPHS DMA Channel Control Register (channel = 2)" class="one_click_away">UDPHS_DMACONTROL2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A432C">0x400A432C</td>
<td class="description">UDPHS DMA Channel Status Register (channel = 2)</td>
<td class="name">
<a href="#UDPHS_DMASTATUS2" title="UDPHS DMA Channel Status Register (channel = 2)" class="one_click_away">UDPHS_DMASTATUS2</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4330">0x400A4330</td>
<td class="description">UDPHS DMA Next Descriptor Address Register (channel = 3)</td>
<td class="name">
<a href="#UDPHS_DMANXTDSC3" title="UDPHS DMA Next Descriptor Address Register (channel = 3)" class="one_click_away">UDPHS_DMANXTDSC3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4334">0x400A4334</td>
<td class="description">UDPHS DMA Channel Address Register (channel = 3)</td>
<td class="name">
<a href="#UDPHS_DMAADDRESS3" title="UDPHS DMA Channel Address Register (channel = 3)" class="one_click_away">UDPHS_DMAADDRESS3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4338">0x400A4338</td>
<td class="description">UDPHS DMA Channel Control Register (channel = 3)</td>
<td class="name">
<a href="#UDPHS_DMACONTROL3" title="UDPHS DMA Channel Control Register (channel = 3)" class="one_click_away">UDPHS_DMACONTROL3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A433C">0x400A433C</td>
<td class="description">UDPHS DMA Channel Status Register (channel = 3)</td>
<td class="name">
<a href="#UDPHS_DMASTATUS3" title="UDPHS DMA Channel Status Register (channel = 3)" class="one_click_away">UDPHS_DMASTATUS3</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4340">0x400A4340</td>
<td class="description">UDPHS DMA Next Descriptor Address Register (channel = 4)</td>
<td class="name">
<a href="#UDPHS_DMANXTDSC4" title="UDPHS DMA Next Descriptor Address Register (channel = 4)" class="one_click_away">UDPHS_DMANXTDSC4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4344">0x400A4344</td>
<td class="description">UDPHS DMA Channel Address Register (channel = 4)</td>
<td class="name">
<a href="#UDPHS_DMAADDRESS4" title="UDPHS DMA Channel Address Register (channel = 4)" class="one_click_away">UDPHS_DMAADDRESS4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4348">0x400A4348</td>
<td class="description">UDPHS DMA Channel Control Register (channel = 4)</td>
<td class="name">
<a href="#UDPHS_DMACONTROL4" title="UDPHS DMA Channel Control Register (channel = 4)" class="one_click_away">UDPHS_DMACONTROL4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A434C">0x400A434C</td>
<td class="description">UDPHS DMA Channel Status Register (channel = 4)</td>
<td class="name">
<a href="#UDPHS_DMASTATUS4" title="UDPHS DMA Channel Status Register (channel = 4)" class="one_click_away">UDPHS_DMASTATUS4</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4350">0x400A4350</td>
<td class="description">UDPHS DMA Next Descriptor Address Register (channel = 5)</td>
<td class="name">
<a href="#UDPHS_DMANXTDSC5" title="UDPHS DMA Next Descriptor Address Register (channel = 5)" class="one_click_away">UDPHS_DMANXTDSC5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A4354">0x400A4354</td>
<td class="description">UDPHS DMA Channel Address Register (channel = 5)</td>
<td class="name">
<a href="#UDPHS_DMAADDRESS5" title="UDPHS DMA Channel Address Register (channel = 5)" class="one_click_away">UDPHS_DMAADDRESS5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400A4358">0x400A4358</td>
<td class="description">UDPHS DMA Channel Control Register (channel = 5)</td>
<td class="name">
<a href="#UDPHS_DMACONTROL5" title="UDPHS DMA Channel Control Register (channel = 5)" class="one_click_away">UDPHS_DMACONTROL5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400A435C">0x400A435C</td>
<td class="description">UDPHS DMA Channel Status Register (channel = 5)</td>
<td class="name">
<a href="#UDPHS_DMASTATUS5" title="UDPHS DMA Channel Status Register (channel = 5)" class="one_click_away">UDPHS_DMASTATUS5</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
</tbody>
</table>
<h3>Register Fields</h3>
<h4 id="UDPHS_CTRL">UDPHS UDPHS Control Register</h4>
<p><strong>Name</strong>: UDPHS_CTRL</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4000</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_CTRL__PULLD_DIS" title="Pull-Down Disable">PULLD_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_CTRL__REWAKEUP" title="Send Remote Wake Up">REWAKEUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_CTRL__DETACH" title="Detach Command">DETACH</a>
</td>
<td colspan="1">
<a href="#UDPHS_CTRL__EN_UDPHS" title="UDPHS Enable">EN_UDPHS</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_CTRL__FADDR_EN" title="Function Address Enable">FADDR_EN</a>
</td>
<td colspan="7">
<a href="#UDPHS_CTRL__DEV_ADDR" title="UDPHS Address">DEV_ADDR</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_CTRL__DEV_ADDR"><strong>DEV_ADDR</strong>: UDPHS Address</li>
<p>-</p>
<li id="UDPHS_CTRL__FADDR_EN"><strong>FADDR_EN</strong>: Function Address Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Device is not in address state (read), or only the default function address is used (write).</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Device is in address state (read), or this bit is set by the device firmware after a successful status phase of a SET_ADDRESS transaction (write). When set, the only address accepted by the UDPHS controller is the one stored in the UDPHS Address field. It will not be cleared afterwards by the device firmware. It is cleared by hardware on hardware reset, or when UDPHS bus reset is received.</td></tr></tbody></table></li>
<li id="UDPHS_CTRL__EN_UDPHS"><strong>EN_UDPHS</strong>: UDPHS Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS is disabled (read), or this bit disables and resets the UDPHS controller (write). Disable the UTMI transceiver. The UTMI may disable the pull-up.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UDPHS is enabled (read), or this bit enables the UDPHS controller (write).</td></tr></tbody></table></li>
<li id="UDPHS_CTRL__DETACH"><strong>DETACH</strong>: Detach Command<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS is attached (read), or this bit pulls up the DP line (attach command) (write).</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UDPHS is detached, UTMI transceiver is suspended (read), or this bit simulates a detach on the UDPHS line and forces the UTMI transceiver into suspend state (Suspend M = 0) (write).</td></tr></tbody></table></li>
<li id="UDPHS_CTRL__REWAKEUP"><strong>REWAKEUP</strong>: Send Remote Wake Up<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Remote Wake Up is disabled (read), or this bit has no effect (write).</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Remote Wake Up is enabled (read), or this bit forces an external interrupt on the UDPHS controller for Remote Wake UP purposes.</td></tr></tbody></table></li>
<li id="UDPHS_CTRL__PULLD_DIS"><strong>PULLD_DIS</strong>: Pull-Down Disable</li>
<p>-</p>
</ul>
<h4 id="UDPHS_FNUM">UDPHS UDPHS Frame Number Register</h4>
<p><strong>Name</strong>: UDPHS_FNUM</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A4004</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_FNUM__FNUM_ERR" title="Frame Number CRC Error">FNUM_ERR</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="6">
<a href="#UDPHS_FNUM__FRAME_NUMBER" title="Frame Number as defined in the Packet Field Formats">FRAME_NUMBER</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="5">
<a href="#UDPHS_FNUM__FRAME_NUMBER" title="Frame Number as defined in the Packet Field Formats">FRAME_NUMBER</a>
</td>
<td colspan="3">
<a href="#UDPHS_FNUM__MICRO_FRAME_NUM" title="Microframe Number">MICRO_FRAME_NUM</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_FNUM__MICRO_FRAME_NUM"><strong>MICRO_FRAME_NUM</strong>: Microframe Number</li>
<p>-</p>
<li id="UDPHS_FNUM__FRAME_NUMBER"><strong>FRAME_NUMBER</strong>: Frame Number as defined in the Packet Field Formats</li>
<p>-</p>
<li id="UDPHS_FNUM__FNUM_ERR"><strong>FNUM_ERR</strong>: Frame Number CRC Error</li>
<p>-</p>
</ul>
<h4 id="UDPHS_IEN">UDPHS UDPHS Interrupt Enable Register</h4>
<p><strong>Name</strong>: UDPHS_IEN</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4010</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_IEN__DMA_6" title="DMA Channel 6 Interrupt Enable">DMA_6</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__DMA_5" title="DMA Channel 5 Interrupt Enable">DMA_5</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__DMA_4" title="DMA Channel 4 Interrupt Enable">DMA_4</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__DMA_3" title="DMA Channel 3 Interrupt Enable">DMA_3</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__DMA_2" title="DMA Channel 2 Interrupt Enable">DMA_2</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__DMA_1" title="DMA Channel 1 Interrupt Enable">DMA_1</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_IEN__EPT_6" title="Endpoint 6 Interrupt Enable">EPT_6</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__EPT_5" title="Endpoint 5 Interrupt Enable">EPT_5</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__EPT_4" title="Endpoint 4 Interrupt Enable">EPT_4</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__EPT_3" title="Endpoint 3 Interrupt Enable">EPT_3</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__EPT_2" title="Endpoint 2 Interrupt Enable">EPT_2</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__EPT_1" title="Endpoint 1 Interrupt Enable">EPT_1</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__EPT_0" title="Endpoint 0 Interrupt Enable">EPT_0</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_IEN__UPSTR_RES" title="Upstream Resume Interrupt Enable">UPSTR_RES</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__ENDOFRSM" title="End Of Resume Interrupt Enable">ENDOFRSM</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__WAKE_UP" title="Wake Up CPU Interrupt Enable">WAKE_UP</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__ENDRESET" title="End Of Reset Interrupt Enable">ENDRESET</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__INT_SOF" title="SOF Interrupt Enable">INT_SOF</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__MICRO_SOF" title="Micro-SOF Interrupt Enable">MICRO_SOF</a>
</td>
<td colspan="1">
<a href="#UDPHS_IEN__DET_SUSPD" title="Suspend Interrupt Enable">DET_SUSPD</a>
</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_IEN__DET_SUSPD"><strong>DET_SUSPD</strong>: Suspend Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable Suspend Interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Suspend Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__MICRO_SOF"><strong>MICRO_SOF</strong>: Micro-SOF Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable Micro-SOF Interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Micro-SOF Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__INT_SOF"><strong>INT_SOF</strong>: SOF Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable SOF Interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable SOF Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__ENDRESET"><strong>ENDRESET</strong>: End Of Reset Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable End Of Reset Interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable End Of Reset Interrupt. Automatically enabled after USB reset.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__WAKE_UP"><strong>WAKE_UP</strong>: Wake Up CPU Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable Wake Up CPU Interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Wake Up CPU Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__ENDOFRSM"><strong>ENDOFRSM</strong>: End Of Resume Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable Resume Interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Resume Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__UPSTR_RES"><strong>UPSTR_RES</strong>: Upstream Resume Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable Upstream Resume Interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Upstream Resume Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__EPT_0"><strong>EPT_0</strong>: Endpoint 0 Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable the interrupts for this endpoint.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable the interrupts for this endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__EPT_1"><strong>EPT_1</strong>: Endpoint 1 Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable the interrupts for this endpoint.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable the interrupts for this endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__EPT_2"><strong>EPT_2</strong>: Endpoint 2 Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable the interrupts for this endpoint.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable the interrupts for this endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__EPT_3"><strong>EPT_3</strong>: Endpoint 3 Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable the interrupts for this endpoint.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable the interrupts for this endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__EPT_4"><strong>EPT_4</strong>: Endpoint 4 Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable the interrupts for this endpoint.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable the interrupts for this endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__EPT_5"><strong>EPT_5</strong>: Endpoint 5 Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable the interrupts for this endpoint.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable the interrupts for this endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__EPT_6"><strong>EPT_6</strong>: Endpoint 6 Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable the interrupts for this endpoint.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable the interrupts for this endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__DMA_1"><strong>DMA_1</strong>: DMA Channel 1 Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable the interrupts for this channel.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable the interrupts for this channel.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__DMA_2"><strong>DMA_2</strong>: DMA Channel 2 Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable the interrupts for this channel.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable the interrupts for this channel.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__DMA_3"><strong>DMA_3</strong>: DMA Channel 3 Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable the interrupts for this channel.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable the interrupts for this channel.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__DMA_4"><strong>DMA_4</strong>: DMA Channel 4 Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable the interrupts for this channel.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable the interrupts for this channel.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__DMA_5"><strong>DMA_5</strong>: DMA Channel 5 Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable the interrupts for this channel.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable the interrupts for this channel.</td></tr></tbody></table></li>
<li id="UDPHS_IEN__DMA_6"><strong>DMA_6</strong>: DMA Channel 6 Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">disable the interrupts for this channel.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable the interrupts for this channel.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_INTSTA">UDPHS UDPHS Interrupt Status Register</h4>
<p><strong>Name</strong>: UDPHS_INTSTA</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A4014</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__DMA_6" title="DMA Channel 6 Interrupt">DMA_6</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__DMA_5" title="DMA Channel 5 Interrupt">DMA_5</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__DMA_4" title="DMA Channel 4 Interrupt">DMA_4</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__DMA_3" title="DMA Channel 3 Interrupt">DMA_3</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__DMA_2" title="DMA Channel 2 Interrupt">DMA_2</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__DMA_1" title="DMA Channel 1 Interrupt">DMA_1</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__EPT_6" title="Endpoint 6 Interrupt">EPT_6</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__EPT_5" title="Endpoint 5 Interrupt">EPT_5</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__EPT_4" title="Endpoint 4 Interrupt">EPT_4</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__EPT_3" title="Endpoint 3 Interrupt">EPT_3</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__EPT_2" title="Endpoint 2 Interrupt">EPT_2</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__EPT_1" title="Endpoint 1 Interrupt">EPT_1</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__EPT_0" title="Endpoint 0 Interrupt">EPT_0</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_INTSTA__UPSTR_RES" title="Upstream Resume Interrupt">UPSTR_RES</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__ENDOFRSM" title="End Of Resume Interrupt">ENDOFRSM</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__WAKE_UP" title="Wake Up CPU Interrupt">WAKE_UP</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__ENDRESET" title="End Of Reset Interrupt">ENDRESET</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__INT_SOF" title="Start Of Frame Interrupt">INT_SOF</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__MICRO_SOF" title="Micro Start Of Frame Interrupt">MICRO_SOF</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__DET_SUSPD" title="Suspend Interrupt">DET_SUSPD</a>
</td>
<td colspan="1">
<a href="#UDPHS_INTSTA__SPEED" title="Speed Status">SPEED</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_INTSTA__SPEED"><strong>SPEED</strong>: Speed Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset by hardware when the hardware is in Full Speed mode.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the hardware is in High Speed mode</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__DET_SUSPD"><strong>DET_SUSPD</strong>: Suspend Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared by setting the DET_SUSPD bit in UDPHS_CLRINT register</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a UDPHS Suspend (Idle bus for three frame periods, a J state for 3 ms) is detected. This triggers a UDPHS interrupt when the DET_SUSPD bit is set in UDPHS_IEN register.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__MICRO_SOF"><strong>MICRO_SOF</strong>: Micro Start Of Frame Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared by setting the MICRO_SOF bit in UDPHS_CLRINT register.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an UDPHS micro start of frame PID (SOF) has been detected (every 125 us) or synthesized by the macro. This triggers a UDPHS interrupt when the MICRO_SOF bit is set in UDPHS_IEN. In case of detected SOF, the MICRO_FRAME_NUM field in UDPHS_FNUM register is incremented and the FRAME_NUMBER field doesn't change.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__INT_SOF"><strong>INT_SOF</strong>: Start Of Frame Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared by setting the INT_SOF bit in UDPHS_CLRINT.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an UDPHS Start Of Frame PID (SOF) has been detected (every 1 ms) or synthesized by the macro. This triggers a UDPHS interrupt when the INT_SOF bit is set in UDPHS_IEN register. In case of detected SOF, in High Speed mode, the MICRO_FRAME_NUMBER field is cleared in UDPHS_FNUM register and the FRAME_NUMBER field is updated.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__ENDRESET"><strong>ENDRESET</strong>: End Of Reset Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared by setting the ENDRESET bit in UDPHS_CLRINT.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an End Of Reset has been detected by the UDPHS controller. This triggers a UDPHS interrupt when the ENDRESET bit is set in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__WAKE_UP"><strong>WAKE_UP</strong>: Wake Up CPU Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared by setting the WAKE_UP bit in UDPHS_CLRINT.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered non-idle signal from the UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when the WAKE_UP bit is set in UDPHS_IEN register. When receiving this interrupt, the user has to enable the device controller clock prior to operation.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__ENDOFRSM"><strong>ENDOFRSM</strong>: End Of Resume Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared by setting the ENDOFRSM bit in UDPHS_CLRINT.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the UDPHS controller detects a good end of resume signal initiated by the host. This triggers a UDPHS interrupt when the ENDOFRSM bit is set in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__UPSTR_RES"><strong>UPSTR_RES</strong>: Upstream Resume Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared by setting the UPSTR_RES bit in UDPHS_CLRINT.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the UDPHS controller is sending a resume signal called "upstream resume". This triggers a UDPHS interrupt when the UPSTR_RES bit is set in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__EPT_0"><strong>EPT_0</strong>: Endpoint 0 Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset when the UDPHS_EPTSTAx interrupt source is cleared.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__EPT_1"><strong>EPT_1</strong>: Endpoint 1 Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset when the UDPHS_EPTSTAx interrupt source is cleared.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__EPT_2"><strong>EPT_2</strong>: Endpoint 2 Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset when the UDPHS_EPTSTAx interrupt source is cleared.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__EPT_3"><strong>EPT_3</strong>: Endpoint 3 Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset when the UDPHS_EPTSTAx interrupt source is cleared.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__EPT_4"><strong>EPT_4</strong>: Endpoint 4 Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset when the UDPHS_EPTSTAx interrupt source is cleared.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__EPT_5"><strong>EPT_5</strong>: Endpoint 5 Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset when the UDPHS_EPTSTAx interrupt source is cleared.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__EPT_6"><strong>EPT_6</strong>: Endpoint 6 Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset when the UDPHS_EPTSTAx interrupt source is cleared.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__DMA_1"><strong>DMA_1</strong>: DMA Channel 1 Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset when the UDPHS_DMASTATUSx interrupt source is cleared.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__DMA_2"><strong>DMA_2</strong>: DMA Channel 2 Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset when the UDPHS_DMASTATUSx interrupt source is cleared.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__DMA_3"><strong>DMA_3</strong>: DMA Channel 3 Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset when the UDPHS_DMASTATUSx interrupt source is cleared.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__DMA_4"><strong>DMA_4</strong>: DMA Channel 4 Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset when the UDPHS_DMASTATUSx interrupt source is cleared.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__DMA_5"><strong>DMA_5</strong>: DMA Channel 5 Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset when the UDPHS_DMASTATUSx interrupt source is cleared.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN.</td></tr></tbody></table></li>
<li id="UDPHS_INTSTA__DMA_6"><strong>DMA_6</strong>: DMA Channel 6 Interrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">reset when the UDPHS_DMASTATUSx interrupt source is cleared.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_CLRINT">UDPHS UDPHS Clear Interrupt Register</h4>
<p><strong>Name</strong>: UDPHS_CLRINT</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4018</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_CLRINT__UPSTR_RES" title="Upstream Resume Interrupt Clear">UPSTR_RES</a>
</td>
<td colspan="1">
<a href="#UDPHS_CLRINT__ENDOFRSM" title="End Of Resume Interrupt Clear">ENDOFRSM</a>
</td>
<td colspan="1">
<a href="#UDPHS_CLRINT__WAKE_UP" title="Wake Up CPU Interrupt Clear">WAKE_UP</a>
</td>
<td colspan="1">
<a href="#UDPHS_CLRINT__ENDRESET" title="End Of Reset Interrupt Clear">ENDRESET</a>
</td>
<td colspan="1">
<a href="#UDPHS_CLRINT__INT_SOF" title="Start Of Frame Interrupt Clear">INT_SOF</a>
</td>
<td colspan="1">
<a href="#UDPHS_CLRINT__MICRO_SOF" title="Micro Start Of Frame Interrupt Clear">MICRO_SOF</a>
</td>
<td colspan="1">
<a href="#UDPHS_CLRINT__DET_SUSPD" title="Suspend Interrupt Clear">DET_SUSPD</a>
</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_CLRINT__DET_SUSPD"><strong>DET_SUSPD</strong>: Suspend Interrupt Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the DET_SUSPD bit in UDPHS_INTSTA.</td></tr></tbody></table></li>
<li id="UDPHS_CLRINT__MICRO_SOF"><strong>MICRO_SOF</strong>: Micro Start Of Frame Interrupt Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the MICRO_SOF bit in UDPHS_INTSTA.</td></tr></tbody></table></li>
<li id="UDPHS_CLRINT__INT_SOF"><strong>INT_SOF</strong>: Start Of Frame Interrupt Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the INT_SOF bit in UDPHS_INTSTA.</td></tr></tbody></table></li>
<li id="UDPHS_CLRINT__ENDRESET"><strong>ENDRESET</strong>: End Of Reset Interrupt Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the ENDRESET bit in UDPHS_INTSTA.</td></tr></tbody></table></li>
<li id="UDPHS_CLRINT__WAKE_UP"><strong>WAKE_UP</strong>: Wake Up CPU Interrupt Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the WAKE_UP bit in UDPHS_INTSTA.</td></tr></tbody></table></li>
<li id="UDPHS_CLRINT__ENDOFRSM"><strong>ENDOFRSM</strong>: End Of Resume Interrupt Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the ENDOFRSM bit in UDPHS_INTSTA.</td></tr></tbody></table></li>
<li id="UDPHS_CLRINT__UPSTR_RES"><strong>UPSTR_RES</strong>: Upstream Resume Interrupt Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the UPSTR_RES bit in UDPHS_INTSTA.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTRST">UDPHS UDPHS Endpoints Reset Register</h4>
<p><strong>Name</strong>: UDPHS_EPTRST</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A401C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTRST__EPT_6" title="Endpoint 6 Reset">EPT_6</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTRST__EPT_5" title="Endpoint 5 Reset">EPT_5</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTRST__EPT_4" title="Endpoint 4 Reset">EPT_4</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTRST__EPT_3" title="Endpoint 3 Reset">EPT_3</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTRST__EPT_2" title="Endpoint 2 Reset">EPT_2</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTRST__EPT_1" title="Endpoint 1 Reset">EPT_1</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTRST__EPT_0" title="Endpoint 0 Reset">EPT_0</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTRST__EPT_0"><strong>EPT_0</strong>: Endpoint 0 Reset<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">reset the Endpointx state.</td></tr></tbody></table></li>
<li id="UDPHS_EPTRST__EPT_1"><strong>EPT_1</strong>: Endpoint 1 Reset<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">reset the Endpointx state.</td></tr></tbody></table></li>
<li id="UDPHS_EPTRST__EPT_2"><strong>EPT_2</strong>: Endpoint 2 Reset<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">reset the Endpointx state.</td></tr></tbody></table></li>
<li id="UDPHS_EPTRST__EPT_3"><strong>EPT_3</strong>: Endpoint 3 Reset<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">reset the Endpointx state.</td></tr></tbody></table></li>
<li id="UDPHS_EPTRST__EPT_4"><strong>EPT_4</strong>: Endpoint 4 Reset<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">reset the Endpointx state.</td></tr></tbody></table></li>
<li id="UDPHS_EPTRST__EPT_5"><strong>EPT_5</strong>: Endpoint 5 Reset<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">reset the Endpointx state.</td></tr></tbody></table></li>
<li id="UDPHS_EPTRST__EPT_6"><strong>EPT_6</strong>: Endpoint 6 Reset<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">reset the Endpointx state.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_TST">UDPHS UDPHS Test Register</h4>
<p><strong>Name</strong>: UDPHS_TST</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A40E0</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_TST__OPMODE2" title="OpMode2">OPMODE2</a>
</td>
<td colspan="1">
<a href="#UDPHS_TST__TST_PKT" title="Test Packet Mode">TST_PKT</a>
</td>
<td colspan="1">
<a href="#UDPHS_TST__TST_K" title="Test K Mode">TST_K</a>
</td>
<td colspan="1">
<a href="#UDPHS_TST__TST_J" title="Test J Mode">TST_J</a>
</td>
<td colspan="2">
<a href="#UDPHS_TST__SPEED_CFG" title="Speed Configuration">SPEED_CFG</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_TST__SPEED_CFG"><strong>SPEED_CFG</strong>: Speed Configuration<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">NORMAL</td><td class="description">Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode</td></tr><tr class="even"><td class="value">0x2</td><td class="name">HIGH_SPEED</td><td class="description">Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose.</td></tr><tr class="odd"><td class="value">0x3</td><td class="name">FULL_SPEED</td><td class="description">Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake.</td></tr></tbody></table></li>
<li id="UDPHS_TST__TST_J"><strong>TST_J</strong>: Test J Mode<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set to send the J state on the UDPHS line. This enables the testing of the high output drive level on the D+ line.</td></tr></tbody></table></li>
<li id="UDPHS_TST__TST_K"><strong>TST_K</strong>: Test K Mode<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set to send the K state on the UDPHS line. This enables the testing of the high output drive level on the D- line.</td></tr></tbody></table></li>
<li id="UDPHS_TST__TST_PKT"><strong>TST_PKT</strong>: Test Packet Mode<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set to repetitively transmit the packet stored in the current bank. This enables the testing of rise and fall times, eye pat-terns, jitter, and any other dynamic waveform specifications.</td></tr></tbody></table></li>
<li id="UDPHS_TST__OPMODE2"><strong>OPMODE2</strong>: OpMode2<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set to force the OpMode signal (UTMI interface) to "10", to disable the bit-stuffing and the NRZI encoding.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_IPNAME1">UDPHS UDPHS Name1 Register</h4>
<p><strong>Name</strong>: UDPHS_IPNAME1</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A40F0</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_IPNAME1__IP_NAME1" title="">IP_NAME1</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_IPNAME1__IP_NAME1" title="">IP_NAME1</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_IPNAME1__IP_NAME1" title="">IP_NAME1</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_IPNAME1__IP_NAME1" title="">IP_NAME1</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_IPNAME1__IP_NAME1">
<strong>IP_NAME1</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_IPNAME2">UDPHS UDPHS Name2 Register</h4>
<p><strong>Name</strong>: UDPHS_IPNAME2</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A40F4</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_IPNAME2__IP_NAME2" title="">IP_NAME2</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_IPNAME2__IP_NAME2" title="">IP_NAME2</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_IPNAME2__IP_NAME2" title="">IP_NAME2</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_IPNAME2__IP_NAME2" title="">IP_NAME2</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_IPNAME2__IP_NAME2">
<strong>IP_NAME2</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_IPFEATURES">UDPHS UDPHS Features Register</h4>
<p><strong>Name</strong>: UDPHS_IPFEATURES</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A40F8</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_15" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_15</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_14" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_14</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_13" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_13</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_12" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_12</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_11" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_11</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_10" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_10</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_9" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_9</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_8" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_8</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_7" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_7</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_6" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_6</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_5" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_5</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_4" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_4</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_3" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_3</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_2" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_2</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__ISO_EPT_1" title="Endpointx High Bandwidth Isochronous Capability">ISO_EPT_1</a>
</td>
<td colspan="1">
<a href="#UDPHS_IPFEATURES__DATAB16_8" title="UTMI DataBus16_8">DATAB16_8</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_IPFEATURES__BW_DPRAM" title="DPRAM Byte Write Capability">BW_DPRAM</a>
</td>
<td colspan="3">
<a href="#UDPHS_IPFEATURES__FIFO_MAX_SIZE" title="DPRAM Size">FIFO_MAX_SIZE</a>
</td>
<td colspan="4">
<a href="#UDPHS_IPFEATURES__DMA_FIFO_WORD_DEPTH" title="DMA FIFO Depth in Words">DMA_FIFO_WORD_DEPTH</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_IPFEATURES__DMA_B_SIZ" title="DMA Buffer Size">DMA_B_SIZ</a>
</td>
<td colspan="3">
<a href="#UDPHS_IPFEATURES__DMA_CHANNEL_NBR" title="Number of DMA Channels">DMA_CHANNEL_NBR</a>
</td>
<td colspan="4">
<a href="#UDPHS_IPFEATURES__EPT_NBR_MAX" title="Max Number of Endpoints">EPT_NBR_MAX</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_IPFEATURES__EPT_NBR_MAX"><strong>EPT_NBR_MAX</strong>: Max Number of Endpoints</li>
<p>-</p>
<li id="UDPHS_IPFEATURES__DMA_CHANNEL_NBR"><strong>DMA_CHANNEL_NBR</strong>: Number of DMA Channels</li>
<p>-</p>
<li id="UDPHS_IPFEATURES__DMA_B_SIZ"><strong>DMA_B_SIZ</strong>: DMA Buffer Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the DMA Buffer size is 16 bits.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the DMA Buffer size is 24 bits.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__DMA_FIFO_WORD_DEPTH"><strong>DMA_FIFO_WORD_DEPTH</strong>: DMA FIFO Depth in Words</li>
<p>-</p>
<li id="UDPHS_IPFEATURES__FIFO_MAX_SIZE"><strong>FIFO_MAX_SIZE</strong>: DPRAM Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">-</td><td class="description">if DPRAM is 128 bytes deep.</td></tr><tr class="even"><td class="value">0x1</td><td class="name">-</td><td class="description">if DPRAM is 256 bytes deep.</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">-</td><td class="description">if DPRAM is 512 bytes deep.</td></tr><tr class="even"><td class="value">0x3</td><td class="name">-</td><td class="description">if DPRAM is 1024 bytes deep.</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">-</td><td class="description">if DPRAM is 2048 bytes deep.</td></tr><tr class="even"><td class="value">0x5</td><td class="name">-</td><td class="description">if DPRAM is 4096 bytes deep.</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">-</td><td class="description">if DPRAM is 8192 bytes deep.</td></tr><tr class="even"><td class="value">0x7</td><td class="name">-</td><td class="description">if DPRAM is 16384 bytes deep.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__BW_DPRAM"><strong>BW_DPRAM</strong>: DPRAM Byte Write Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if DPRAM Write Data Shadow logic is implemented.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if DPRAM is byte write capable.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__DATAB16_8"><strong>DATAB16_8</strong>: UTMI DataBus16_8<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the UTMI uses an 8-bit parallel data interface (60 MHz, unidirectional).</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the UTMI uses a 16-bit parallel data interface (30 MHz, bidirectional).</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_1"><strong>ISO_EPT_1</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_2"><strong>ISO_EPT_2</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_3"><strong>ISO_EPT_3</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_4"><strong>ISO_EPT_4</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_5"><strong>ISO_EPT_5</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_6"><strong>ISO_EPT_6</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_7"><strong>ISO_EPT_7</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_8"><strong>ISO_EPT_8</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_9"><strong>ISO_EPT_9</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_10"><strong>ISO_EPT_10</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_11"><strong>ISO_EPT_11</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_12"><strong>ISO_EPT_12</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_13"><strong>ISO_EPT_13</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_14"><strong>ISO_EPT_14</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
<li id="UDPHS_IPFEATURES__ISO_EPT_15"><strong>ISO_EPT_15</strong>: Endpointx High Bandwidth Isochronous Capability<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if the endpoint does not have isochronous High Bandwidth Capability.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if the endpoint has isochronous High Bandwidth Capability.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCFG0">UDPHS UDPHS Endpoint Configuration Register (endpoint = 0)</h4>
<p><strong>Name</strong>: UDPHS_EPTCFG0</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4100</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCFG0__EPT_MAPD" title="Endpoint Mapped">EPT_MAPD</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG0__NB_TRANS" title="Number Of Transaction per Microframe">NB_TRANS</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTCFG0__BK_NUMBER" title="Number of Banks">BK_NUMBER</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG0__EPT_TYPE" title="Endpoint Type">EPT_TYPE</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCFG0__EPT_DIR" title="Endpoint Direction">EPT_DIR</a>
</td>
<td colspan="3">
<a href="#UDPHS_EPTCFG0__EPT_SIZE" title="Endpoint Size">EPT_SIZE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCFG0__EPT_SIZE"><strong>EPT_SIZE</strong>: Endpoint Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">8</td><td class="description">8 bytes</td></tr><tr class="even"><td class="value">0x1</td><td class="name">16</td><td class="description">16 bytes</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">32</td><td class="description">32 bytes</td></tr><tr class="even"><td class="value">0x3</td><td class="name">64</td><td class="description">64 bytes</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">128</td><td class="description">128 bytes</td></tr><tr class="even"><td class="value">0x5</td><td class="name">256</td><td class="description">256 bytes</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">512</td><td class="description">512 bytes</td></tr><tr class="even"><td class="value">0x7</td><td class="name">1024</td><td class="description">1024 bytes</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG0__EPT_DIR"><strong>EPT_DIR</strong>: Endpoint Direction<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG0__EPT_TYPE"><strong>EPT_TYPE</strong>: Endpoint Type<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CTRL8</td><td class="description">Control endpoint</td></tr><tr class="even"><td class="value">0x1</td><td class="name">ISO</td><td class="description">Isochronous endpoint</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">BULK</td><td class="description">Bulk endpoint</td></tr><tr class="even"><td class="value">0x3</td><td class="name">INT</td><td class="description">Interrupt endpoint</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG0__BK_NUMBER"><strong>BK_NUMBER</strong>: Number of Banks<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">0</td><td class="description">Zero bank, the endpoint is not mapped in memory</td></tr><tr class="even"><td class="value">0x1</td><td class="name">1</td><td class="description">One bank (bank 0)</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">2</td><td class="description">Double bank (Ping-Pong: bank0/bank1)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">3</td><td class="description">Triple bank (bank0/bank1/bank2)</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG0__NB_TRANS"><strong>NB_TRANS</strong>: Number Of Transaction per Microframe</li>
<p>-</p>
<li id="UDPHS_EPTCFG0__EPT_MAPD"><strong>EPT_MAPD</strong>: Endpoint Mapped<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the user should reprogram the register with correct values.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLENB0">UDPHS UDPHS Endpoint Control Enable Register (endpoint = 0)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLENB0</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4104</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__SHRT_PCKT" title="Short Packet Send/Short Packet Interrupt Enable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__BUSY_BANK" title="Busy Bank Interrupt Enable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__NAK_OUT" title="NAKOUT Interrupt Enable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__STALL_SNT" title="Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__RX_BK_RDY" title="Received OUT Data Interrupt Enable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__ERR_OVFLW" title="Overflow Error Interrupt Enable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__MDATA_RX" title="MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__DATAX_RX" title="DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__AUTO_VALID" title="Packet Auto-Valid Enable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB0__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLENB0__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable endpoint according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB0__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Send/Short Packet Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLDIS0">UDPHS UDPHS Endpoint Control Disable Register (endpoint = 0)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLDIS0</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4108</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__SHRT_PCKT" title="Short Packet Interrupt Disable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__BUSY_BANK" title="Busy Bank Interrupt Disable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__NAK_OUT" title="NAKOUT Interrupt Disable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__NAK_IN" title="NAKIN/bank flush error Interrupt Disable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__RX_SETUP" title="Received SETUP/Error Flow Interrupt Disable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Disable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Disable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__RX_BK_RDY" title="Received OUT Data Interrupt Disable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__ERR_OVFLW" title="Overflow Error Interrupt Disable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__MDATA_RX" title="MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__DATAX_RX" title="DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__NYET_DIS" title="NYET Enable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__AUTO_VALID" title="Packet Auto-Valid Disable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS0__EPT_DISABL" title="Endpoint Disable">EPT_DISABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLDIS0__EPT_DISABL"><strong>EPT_DISABL</strong>: Endpoint Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable this bit to not automatically validate the current packet.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable the "Interrupts Disable DMA".</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__NYET_DIS"><strong>NYET_DIS</strong>: NYET Enable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">let the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__NAK_IN"><strong>NAK_IN</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS0__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTL0">UDPHS UDPHS Endpoint Control Register (endpoint = 0)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTL0</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A410C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL0__SHRT_PCKT" title="Short Packet Interrupt Enabled">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL0__BUSY_BANK" title="Busy Bank Interrupt Enabled">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL0__NAK_OUT" title="NAKOUT Interrupt Enabled">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL0__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enabled">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL0__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL0__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enabled">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL0__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enabled">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL0__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enabled">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL0__RX_BK_RDY" title="Received OUT Data Interrupt Enabled">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL0__ERR_OVFLW" title="Overflow Error Interrupt Enabled">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL0__MDATA_RX" title="MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL0__DATAX_RX" title="DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL0__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL0__INTDIS_DMA" title="Interrupt Disables DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL0__AUTO_VALID" title="Packet Auto-Valid Enabled (Not for CONTROL Endpoints)">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL0__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTL0__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, the endpoint is enabled according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)</li>
<p>-</p>
<li id="UDPHS_EPTCTL0__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupt Disables DMA</li>
<p>-</p>
<li id="UDPHS_EPTCTL0__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Overflow Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Overflow Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKOUT Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKOUT Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL0__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Short Packet Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Short Packet Interrupt is enabled.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSETSTA0">UDPHS UDPHS Endpoint Set Status Register (endpoint = 0)</h4>
<p><strong>Name</strong>: UDPHS_EPTSETSTA0</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4114</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA0__TX_PK_RDY" title="TX Packet Ready Set">TX_PK_RDY</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA0__KILL_BANK" title="KILL Bank Set (for IN Endpoint)">KILL_BANK</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA0__FRCESTALL" title="Stall Handshake Request Set">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSETSTA0__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to request a STALL answer to the host for the next handshake</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA0__KILL_BANK"><strong>KILL_BANK</strong>: KILL Bank Set (for IN Endpoint)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">kill the last written bank.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA0__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit after a packet has been written into the endpoint FIFO for IN data transfers</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCLRSTA0">UDPHS UDPHS Endpoint Clear Status Register (endpoint = 0)</h4>
<p><strong>Name</strong>: UDPHS_EPTCLRSTA0</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4118</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA0__NAK_OUT" title="NAKOUT Clear">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA0__NAK_IN" title="NAKIN/Bank Flush Error Clear">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA0__STALL_SNT" title="Stall Sent/Number of Transaction Error Clear">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA0__RX_SETUP" title="Received SETUP/Error Flow Clear">RX_SETUP</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA0__TX_COMPLT" title="Transmitted IN Data Complete Clear">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA0__RX_BK_RDY" title="Received OUT Data Clear">RX_BK_RDY</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA0__TOGGLESQ" title="Data Toggle Clear">TOGGLESQ</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA0__FRCESTALL" title="Stall Handshake Request Clear">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCLRSTA0__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL request. The next packets from host will not be STALLed.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA0__TOGGLESQ"><strong>TOGGLESQ</strong>: Data Toggle Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the PID data of the current bank</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA0__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_BK_RDY flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA0__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the TX_COMPLT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA0__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA0__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA0__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA0__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA0__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA0__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA0__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_OUT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSTA0">UDPHS UDPHS Endpoint Status Register (endpoint = 0)</h4>
<p><strong>Name</strong>: UDPHS_EPTSTA0</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A411C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA0__SHRT_PCKT" title="Short Packet">SHRT_PCKT</a>
</td>
<td colspan="7">
<a href="#UDPHS_EPTSTA0__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#UDPHS_EPTSTA0__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA0__BUSY_BANK_STA" title="Busy Bank Number">BUSY_BANK_STA</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA0__CURRENT_BANK" title="Current Bank/Control Direction">CURRENT_BANK</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA0__NAK_OUT" title="NAK OUT">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA0__NAK_IN" title="NAK IN/Bank Flush Error">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA0__STALL_SNT" title="Stall Sent/CRC ISO Error/Number of Transaction Error">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA0__RX_SETUP" title="Received SETUP/Error Flow">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA0__TX_PK_RDY" title="TX Packet Ready/Transaction Error">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA0__TX_COMPLT" title="Transmitted IN Data Complete">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA0__RX_BK_RDY" title="Received OUT Data/KILL Bank">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA0__ERR_OVFLW" title="Overflow Error">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTSTA0__TOGGLESQ_STA" title="Toggle Sequencing">TOGGLESQ_STA</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA0__FRCESTALL" title="Stall Handshake Request">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSTA0__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set a STALL answer will be done to the host for the next handshake.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA0__TOGGLESQ_STA"><strong>TOGGLESQ_STA</strong>: Toggle Sequencing<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">DATA0</td><td class="description">DATA0</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DATA1</td><td class="description">DATA1</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">DATA2</td><td class="description">Data2 (only for High Bandwidth Isochronous Endpoint)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">MDATA</td><td class="description">MData (only for High Bandwidth Isochronous Endpoint)</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA0__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__KILL_BANK"><strong>KILL_BANK</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__NAK_IN"><strong>NAK_IN</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__NAK_OUT"><strong>NAK_OUT</strong>: NAK OUT</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__CURRENT_BANK"><strong>CURRENT_BANK</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__CONTROL_DIR"><strong>CONTROL_DIR</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__BUSY_BANK_STA"><strong>BUSY_BANK_STA</strong>: Busy Bank Number<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">1BUSYBANK</td><td class="description">1 busy bank</td></tr><tr class="even"><td class="value">0x1</td><td class="name">2BUSYBANKS</td><td class="description">2 busy banks</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">3BUSYBANKS</td><td class="description">3 busy banks</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA0__BYTE_COUNT"><strong>BYTE_COUNT</strong>: UDPHS Byte Count</li>
<p>-</p>
<li id="UDPHS_EPTSTA0__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet</li>
<p>-</p>
</ul>
<h4 id="UDPHS_EPTCFG1">UDPHS UDPHS Endpoint Configuration Register (endpoint = 1)</h4>
<p><strong>Name</strong>: UDPHS_EPTCFG1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4120</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCFG1__EPT_MAPD" title="Endpoint Mapped">EPT_MAPD</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG1__NB_TRANS" title="Number Of Transaction per Microframe">NB_TRANS</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTCFG1__BK_NUMBER" title="Number of Banks">BK_NUMBER</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG1__EPT_TYPE" title="Endpoint Type">EPT_TYPE</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCFG1__EPT_DIR" title="Endpoint Direction">EPT_DIR</a>
</td>
<td colspan="3">
<a href="#UDPHS_EPTCFG1__EPT_SIZE" title="Endpoint Size">EPT_SIZE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCFG1__EPT_SIZE"><strong>EPT_SIZE</strong>: Endpoint Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">8</td><td class="description">8 bytes</td></tr><tr class="even"><td class="value">0x1</td><td class="name">16</td><td class="description">16 bytes</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">32</td><td class="description">32 bytes</td></tr><tr class="even"><td class="value">0x3</td><td class="name">64</td><td class="description">64 bytes</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">128</td><td class="description">128 bytes</td></tr><tr class="even"><td class="value">0x5</td><td class="name">256</td><td class="description">256 bytes</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">512</td><td class="description">512 bytes</td></tr><tr class="even"><td class="value">0x7</td><td class="name">1024</td><td class="description">1024 bytes</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG1__EPT_DIR"><strong>EPT_DIR</strong>: Endpoint Direction<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG1__EPT_TYPE"><strong>EPT_TYPE</strong>: Endpoint Type<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CTRL8</td><td class="description">Control endpoint</td></tr><tr class="even"><td class="value">0x1</td><td class="name">ISO</td><td class="description">Isochronous endpoint</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">BULK</td><td class="description">Bulk endpoint</td></tr><tr class="even"><td class="value">0x3</td><td class="name">INT</td><td class="description">Interrupt endpoint</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG1__BK_NUMBER"><strong>BK_NUMBER</strong>: Number of Banks<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">0</td><td class="description">Zero bank, the endpoint is not mapped in memory</td></tr><tr class="even"><td class="value">0x1</td><td class="name">1</td><td class="description">One bank (bank 0)</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">2</td><td class="description">Double bank (Ping-Pong: bank0/bank1)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">3</td><td class="description">Triple bank (bank0/bank1/bank2)</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG1__NB_TRANS"><strong>NB_TRANS</strong>: Number Of Transaction per Microframe</li>
<p>-</p>
<li id="UDPHS_EPTCFG1__EPT_MAPD"><strong>EPT_MAPD</strong>: Endpoint Mapped<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the user should reprogram the register with correct values.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLENB1">UDPHS UDPHS Endpoint Control Enable Register (endpoint = 1)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLENB1</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4124</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__SHRT_PCKT" title="Short Packet Send/Short Packet Interrupt Enable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__BUSY_BANK" title="Busy Bank Interrupt Enable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__NAK_OUT" title="NAKOUT Interrupt Enable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__STALL_SNT" title="Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__RX_BK_RDY" title="Received OUT Data Interrupt Enable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__ERR_OVFLW" title="Overflow Error Interrupt Enable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__MDATA_RX" title="MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__DATAX_RX" title="DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__AUTO_VALID" title="Packet Auto-Valid Enable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB1__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLENB1__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable endpoint according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB1__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Send/Short Packet Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLDIS1">UDPHS UDPHS Endpoint Control Disable Register (endpoint = 1)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLDIS1</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4128</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__SHRT_PCKT" title="Short Packet Interrupt Disable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__BUSY_BANK" title="Busy Bank Interrupt Disable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__NAK_OUT" title="NAKOUT Interrupt Disable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__NAK_IN" title="NAKIN/bank flush error Interrupt Disable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__RX_SETUP" title="Received SETUP/Error Flow Interrupt Disable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Disable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Disable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__RX_BK_RDY" title="Received OUT Data Interrupt Disable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__ERR_OVFLW" title="Overflow Error Interrupt Disable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__MDATA_RX" title="MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__DATAX_RX" title="DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__NYET_DIS" title="NYET Enable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__AUTO_VALID" title="Packet Auto-Valid Disable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS1__EPT_DISABL" title="Endpoint Disable">EPT_DISABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLDIS1__EPT_DISABL"><strong>EPT_DISABL</strong>: Endpoint Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable this bit to not automatically validate the current packet.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable the "Interrupts Disable DMA".</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__NYET_DIS"><strong>NYET_DIS</strong>: NYET Enable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">let the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__NAK_IN"><strong>NAK_IN</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS1__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTL1">UDPHS UDPHS Endpoint Control Register (endpoint = 1)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTL1</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A412C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL1__SHRT_PCKT" title="Short Packet Interrupt Enabled">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL1__BUSY_BANK" title="Busy Bank Interrupt Enabled">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL1__NAK_OUT" title="NAKOUT Interrupt Enabled">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL1__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enabled">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL1__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL1__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enabled">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL1__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enabled">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL1__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enabled">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL1__RX_BK_RDY" title="Received OUT Data Interrupt Enabled">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL1__ERR_OVFLW" title="Overflow Error Interrupt Enabled">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL1__MDATA_RX" title="MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL1__DATAX_RX" title="DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL1__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL1__INTDIS_DMA" title="Interrupt Disables DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL1__AUTO_VALID" title="Packet Auto-Valid Enabled (Not for CONTROL Endpoints)">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL1__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTL1__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, the endpoint is enabled according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)</li>
<p>-</p>
<li id="UDPHS_EPTCTL1__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupt Disables DMA</li>
<p>-</p>
<li id="UDPHS_EPTCTL1__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Overflow Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Overflow Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKOUT Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKOUT Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL1__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Short Packet Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Short Packet Interrupt is enabled.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSETSTA1">UDPHS UDPHS Endpoint Set Status Register (endpoint = 1)</h4>
<p><strong>Name</strong>: UDPHS_EPTSETSTA1</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4134</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA1__TX_PK_RDY" title="TX Packet Ready Set">TX_PK_RDY</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA1__KILL_BANK" title="KILL Bank Set (for IN Endpoint)">KILL_BANK</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA1__FRCESTALL" title="Stall Handshake Request Set">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSETSTA1__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to request a STALL answer to the host for the next handshake</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA1__KILL_BANK"><strong>KILL_BANK</strong>: KILL Bank Set (for IN Endpoint)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">kill the last written bank.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA1__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit after a packet has been written into the endpoint FIFO for IN data transfers</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCLRSTA1">UDPHS UDPHS Endpoint Clear Status Register (endpoint = 1)</h4>
<p><strong>Name</strong>: UDPHS_EPTCLRSTA1</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4138</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA1__NAK_OUT" title="NAKOUT Clear">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA1__NAK_IN" title="NAKIN/Bank Flush Error Clear">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA1__STALL_SNT" title="Stall Sent/Number of Transaction Error Clear">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA1__RX_SETUP" title="Received SETUP/Error Flow Clear">RX_SETUP</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA1__TX_COMPLT" title="Transmitted IN Data Complete Clear">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA1__RX_BK_RDY" title="Received OUT Data Clear">RX_BK_RDY</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA1__TOGGLESQ" title="Data Toggle Clear">TOGGLESQ</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA1__FRCESTALL" title="Stall Handshake Request Clear">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCLRSTA1__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL request. The next packets from host will not be STALLed.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA1__TOGGLESQ"><strong>TOGGLESQ</strong>: Data Toggle Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the PID data of the current bank</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA1__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_BK_RDY flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA1__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the TX_COMPLT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA1__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA1__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA1__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA1__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA1__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA1__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA1__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_OUT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSTA1">UDPHS UDPHS Endpoint Status Register (endpoint = 1)</h4>
<p><strong>Name</strong>: UDPHS_EPTSTA1</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A413C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA1__SHRT_PCKT" title="Short Packet">SHRT_PCKT</a>
</td>
<td colspan="7">
<a href="#UDPHS_EPTSTA1__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#UDPHS_EPTSTA1__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA1__BUSY_BANK_STA" title="Busy Bank Number">BUSY_BANK_STA</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA1__CURRENT_BANK" title="Current Bank/Control Direction">CURRENT_BANK</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA1__NAK_OUT" title="NAK OUT">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA1__NAK_IN" title="NAK IN/Bank Flush Error">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA1__STALL_SNT" title="Stall Sent/CRC ISO Error/Number of Transaction Error">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA1__RX_SETUP" title="Received SETUP/Error Flow">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA1__TX_PK_RDY" title="TX Packet Ready/Transaction Error">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA1__TX_COMPLT" title="Transmitted IN Data Complete">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA1__RX_BK_RDY" title="Received OUT Data/KILL Bank">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA1__ERR_OVFLW" title="Overflow Error">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTSTA1__TOGGLESQ_STA" title="Toggle Sequencing">TOGGLESQ_STA</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA1__FRCESTALL" title="Stall Handshake Request">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSTA1__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set a STALL answer will be done to the host for the next handshake.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA1__TOGGLESQ_STA"><strong>TOGGLESQ_STA</strong>: Toggle Sequencing<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">DATA0</td><td class="description">DATA0</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DATA1</td><td class="description">DATA1</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">DATA2</td><td class="description">Data2 (only for High Bandwidth Isochronous Endpoint)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">MDATA</td><td class="description">MData (only for High Bandwidth Isochronous Endpoint)</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA1__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__KILL_BANK"><strong>KILL_BANK</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__NAK_IN"><strong>NAK_IN</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__NAK_OUT"><strong>NAK_OUT</strong>: NAK OUT</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__CURRENT_BANK"><strong>CURRENT_BANK</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__CONTROL_DIR"><strong>CONTROL_DIR</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__BUSY_BANK_STA"><strong>BUSY_BANK_STA</strong>: Busy Bank Number<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">1BUSYBANK</td><td class="description">1 busy bank</td></tr><tr class="even"><td class="value">0x1</td><td class="name">2BUSYBANKS</td><td class="description">2 busy banks</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">3BUSYBANKS</td><td class="description">3 busy banks</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA1__BYTE_COUNT"><strong>BYTE_COUNT</strong>: UDPHS Byte Count</li>
<p>-</p>
<li id="UDPHS_EPTSTA1__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet</li>
<p>-</p>
</ul>
<h4 id="UDPHS_EPTCFG2">UDPHS UDPHS Endpoint Configuration Register (endpoint = 2)</h4>
<p><strong>Name</strong>: UDPHS_EPTCFG2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4140</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCFG2__EPT_MAPD" title="Endpoint Mapped">EPT_MAPD</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG2__NB_TRANS" title="Number Of Transaction per Microframe">NB_TRANS</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTCFG2__BK_NUMBER" title="Number of Banks">BK_NUMBER</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG2__EPT_TYPE" title="Endpoint Type">EPT_TYPE</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCFG2__EPT_DIR" title="Endpoint Direction">EPT_DIR</a>
</td>
<td colspan="3">
<a href="#UDPHS_EPTCFG2__EPT_SIZE" title="Endpoint Size">EPT_SIZE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCFG2__EPT_SIZE"><strong>EPT_SIZE</strong>: Endpoint Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">8</td><td class="description">8 bytes</td></tr><tr class="even"><td class="value">0x1</td><td class="name">16</td><td class="description">16 bytes</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">32</td><td class="description">32 bytes</td></tr><tr class="even"><td class="value">0x3</td><td class="name">64</td><td class="description">64 bytes</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">128</td><td class="description">128 bytes</td></tr><tr class="even"><td class="value">0x5</td><td class="name">256</td><td class="description">256 bytes</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">512</td><td class="description">512 bytes</td></tr><tr class="even"><td class="value">0x7</td><td class="name">1024</td><td class="description">1024 bytes</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG2__EPT_DIR"><strong>EPT_DIR</strong>: Endpoint Direction<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG2__EPT_TYPE"><strong>EPT_TYPE</strong>: Endpoint Type<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CTRL8</td><td class="description">Control endpoint</td></tr><tr class="even"><td class="value">0x1</td><td class="name">ISO</td><td class="description">Isochronous endpoint</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">BULK</td><td class="description">Bulk endpoint</td></tr><tr class="even"><td class="value">0x3</td><td class="name">INT</td><td class="description">Interrupt endpoint</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG2__BK_NUMBER"><strong>BK_NUMBER</strong>: Number of Banks<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">0</td><td class="description">Zero bank, the endpoint is not mapped in memory</td></tr><tr class="even"><td class="value">0x1</td><td class="name">1</td><td class="description">One bank (bank 0)</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">2</td><td class="description">Double bank (Ping-Pong: bank0/bank1)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">3</td><td class="description">Triple bank (bank0/bank1/bank2)</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG2__NB_TRANS"><strong>NB_TRANS</strong>: Number Of Transaction per Microframe</li>
<p>-</p>
<li id="UDPHS_EPTCFG2__EPT_MAPD"><strong>EPT_MAPD</strong>: Endpoint Mapped<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the user should reprogram the register with correct values.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLENB2">UDPHS UDPHS Endpoint Control Enable Register (endpoint = 2)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLENB2</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4144</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__SHRT_PCKT" title="Short Packet Send/Short Packet Interrupt Enable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__BUSY_BANK" title="Busy Bank Interrupt Enable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__NAK_OUT" title="NAKOUT Interrupt Enable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__STALL_SNT" title="Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__RX_BK_RDY" title="Received OUT Data Interrupt Enable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__ERR_OVFLW" title="Overflow Error Interrupt Enable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__MDATA_RX" title="MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__DATAX_RX" title="DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__AUTO_VALID" title="Packet Auto-Valid Enable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB2__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLENB2__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable endpoint according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB2__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Send/Short Packet Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLDIS2">UDPHS UDPHS Endpoint Control Disable Register (endpoint = 2)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLDIS2</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4148</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__SHRT_PCKT" title="Short Packet Interrupt Disable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__BUSY_BANK" title="Busy Bank Interrupt Disable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__NAK_OUT" title="NAKOUT Interrupt Disable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__NAK_IN" title="NAKIN/bank flush error Interrupt Disable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__RX_SETUP" title="Received SETUP/Error Flow Interrupt Disable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Disable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Disable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__RX_BK_RDY" title="Received OUT Data Interrupt Disable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__ERR_OVFLW" title="Overflow Error Interrupt Disable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__MDATA_RX" title="MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__DATAX_RX" title="DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__NYET_DIS" title="NYET Enable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__AUTO_VALID" title="Packet Auto-Valid Disable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS2__EPT_DISABL" title="Endpoint Disable">EPT_DISABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLDIS2__EPT_DISABL"><strong>EPT_DISABL</strong>: Endpoint Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable this bit to not automatically validate the current packet.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable the "Interrupts Disable DMA".</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__NYET_DIS"><strong>NYET_DIS</strong>: NYET Enable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">let the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__NAK_IN"><strong>NAK_IN</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS2__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTL2">UDPHS UDPHS Endpoint Control Register (endpoint = 2)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTL2</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A414C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL2__SHRT_PCKT" title="Short Packet Interrupt Enabled">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL2__BUSY_BANK" title="Busy Bank Interrupt Enabled">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL2__NAK_OUT" title="NAKOUT Interrupt Enabled">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL2__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enabled">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL2__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL2__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enabled">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL2__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enabled">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL2__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enabled">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL2__RX_BK_RDY" title="Received OUT Data Interrupt Enabled">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL2__ERR_OVFLW" title="Overflow Error Interrupt Enabled">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL2__MDATA_RX" title="MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL2__DATAX_RX" title="DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL2__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL2__INTDIS_DMA" title="Interrupt Disables DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL2__AUTO_VALID" title="Packet Auto-Valid Enabled (Not for CONTROL Endpoints)">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL2__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTL2__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, the endpoint is enabled according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)</li>
<p>-</p>
<li id="UDPHS_EPTCTL2__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupt Disables DMA</li>
<p>-</p>
<li id="UDPHS_EPTCTL2__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Overflow Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Overflow Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKOUT Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKOUT Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL2__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Short Packet Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Short Packet Interrupt is enabled.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSETSTA2">UDPHS UDPHS Endpoint Set Status Register (endpoint = 2)</h4>
<p><strong>Name</strong>: UDPHS_EPTSETSTA2</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4154</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA2__TX_PK_RDY" title="TX Packet Ready Set">TX_PK_RDY</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA2__KILL_BANK" title="KILL Bank Set (for IN Endpoint)">KILL_BANK</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA2__FRCESTALL" title="Stall Handshake Request Set">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSETSTA2__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to request a STALL answer to the host for the next handshake</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA2__KILL_BANK"><strong>KILL_BANK</strong>: KILL Bank Set (for IN Endpoint)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">kill the last written bank.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA2__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit after a packet has been written into the endpoint FIFO for IN data transfers</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCLRSTA2">UDPHS UDPHS Endpoint Clear Status Register (endpoint = 2)</h4>
<p><strong>Name</strong>: UDPHS_EPTCLRSTA2</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4158</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA2__NAK_OUT" title="NAKOUT Clear">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA2__NAK_IN" title="NAKIN/Bank Flush Error Clear">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA2__STALL_SNT" title="Stall Sent/Number of Transaction Error Clear">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA2__RX_SETUP" title="Received SETUP/Error Flow Clear">RX_SETUP</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA2__TX_COMPLT" title="Transmitted IN Data Complete Clear">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA2__RX_BK_RDY" title="Received OUT Data Clear">RX_BK_RDY</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA2__TOGGLESQ" title="Data Toggle Clear">TOGGLESQ</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA2__FRCESTALL" title="Stall Handshake Request Clear">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCLRSTA2__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL request. The next packets from host will not be STALLed.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA2__TOGGLESQ"><strong>TOGGLESQ</strong>: Data Toggle Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the PID data of the current bank</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA2__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_BK_RDY flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA2__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the TX_COMPLT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA2__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA2__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA2__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA2__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA2__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA2__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA2__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_OUT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSTA2">UDPHS UDPHS Endpoint Status Register (endpoint = 2)</h4>
<p><strong>Name</strong>: UDPHS_EPTSTA2</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A415C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA2__SHRT_PCKT" title="Short Packet">SHRT_PCKT</a>
</td>
<td colspan="7">
<a href="#UDPHS_EPTSTA2__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#UDPHS_EPTSTA2__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA2__BUSY_BANK_STA" title="Busy Bank Number">BUSY_BANK_STA</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA2__CURRENT_BANK" title="Current Bank/Control Direction">CURRENT_BANK</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA2__NAK_OUT" title="NAK OUT">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA2__NAK_IN" title="NAK IN/Bank Flush Error">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA2__STALL_SNT" title="Stall Sent/CRC ISO Error/Number of Transaction Error">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA2__RX_SETUP" title="Received SETUP/Error Flow">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA2__TX_PK_RDY" title="TX Packet Ready/Transaction Error">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA2__TX_COMPLT" title="Transmitted IN Data Complete">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA2__RX_BK_RDY" title="Received OUT Data/KILL Bank">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA2__ERR_OVFLW" title="Overflow Error">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTSTA2__TOGGLESQ_STA" title="Toggle Sequencing">TOGGLESQ_STA</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA2__FRCESTALL" title="Stall Handshake Request">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSTA2__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set a STALL answer will be done to the host for the next handshake.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA2__TOGGLESQ_STA"><strong>TOGGLESQ_STA</strong>: Toggle Sequencing<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">DATA0</td><td class="description">DATA0</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DATA1</td><td class="description">DATA1</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">DATA2</td><td class="description">Data2 (only for High Bandwidth Isochronous Endpoint)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">MDATA</td><td class="description">MData (only for High Bandwidth Isochronous Endpoint)</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA2__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__KILL_BANK"><strong>KILL_BANK</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__NAK_IN"><strong>NAK_IN</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__NAK_OUT"><strong>NAK_OUT</strong>: NAK OUT</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__CURRENT_BANK"><strong>CURRENT_BANK</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__CONTROL_DIR"><strong>CONTROL_DIR</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__BUSY_BANK_STA"><strong>BUSY_BANK_STA</strong>: Busy Bank Number<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">1BUSYBANK</td><td class="description">1 busy bank</td></tr><tr class="even"><td class="value">0x1</td><td class="name">2BUSYBANKS</td><td class="description">2 busy banks</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">3BUSYBANKS</td><td class="description">3 busy banks</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA2__BYTE_COUNT"><strong>BYTE_COUNT</strong>: UDPHS Byte Count</li>
<p>-</p>
<li id="UDPHS_EPTSTA2__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet</li>
<p>-</p>
</ul>
<h4 id="UDPHS_EPTCFG3">UDPHS UDPHS Endpoint Configuration Register (endpoint = 3)</h4>
<p><strong>Name</strong>: UDPHS_EPTCFG3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4160</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCFG3__EPT_MAPD" title="Endpoint Mapped">EPT_MAPD</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG3__NB_TRANS" title="Number Of Transaction per Microframe">NB_TRANS</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTCFG3__BK_NUMBER" title="Number of Banks">BK_NUMBER</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG3__EPT_TYPE" title="Endpoint Type">EPT_TYPE</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCFG3__EPT_DIR" title="Endpoint Direction">EPT_DIR</a>
</td>
<td colspan="3">
<a href="#UDPHS_EPTCFG3__EPT_SIZE" title="Endpoint Size">EPT_SIZE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCFG3__EPT_SIZE"><strong>EPT_SIZE</strong>: Endpoint Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">8</td><td class="description">8 bytes</td></tr><tr class="even"><td class="value">0x1</td><td class="name">16</td><td class="description">16 bytes</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">32</td><td class="description">32 bytes</td></tr><tr class="even"><td class="value">0x3</td><td class="name">64</td><td class="description">64 bytes</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">128</td><td class="description">128 bytes</td></tr><tr class="even"><td class="value">0x5</td><td class="name">256</td><td class="description">256 bytes</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">512</td><td class="description">512 bytes</td></tr><tr class="even"><td class="value">0x7</td><td class="name">1024</td><td class="description">1024 bytes</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG3__EPT_DIR"><strong>EPT_DIR</strong>: Endpoint Direction<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG3__EPT_TYPE"><strong>EPT_TYPE</strong>: Endpoint Type<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CTRL8</td><td class="description">Control endpoint</td></tr><tr class="even"><td class="value">0x1</td><td class="name">ISO</td><td class="description">Isochronous endpoint</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">BULK</td><td class="description">Bulk endpoint</td></tr><tr class="even"><td class="value">0x3</td><td class="name">INT</td><td class="description">Interrupt endpoint</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG3__BK_NUMBER"><strong>BK_NUMBER</strong>: Number of Banks<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">0</td><td class="description">Zero bank, the endpoint is not mapped in memory</td></tr><tr class="even"><td class="value">0x1</td><td class="name">1</td><td class="description">One bank (bank 0)</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">2</td><td class="description">Double bank (Ping-Pong: bank0/bank1)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">3</td><td class="description">Triple bank (bank0/bank1/bank2)</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG3__NB_TRANS"><strong>NB_TRANS</strong>: Number Of Transaction per Microframe</li>
<p>-</p>
<li id="UDPHS_EPTCFG3__EPT_MAPD"><strong>EPT_MAPD</strong>: Endpoint Mapped<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the user should reprogram the register with correct values.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLENB3">UDPHS UDPHS Endpoint Control Enable Register (endpoint = 3)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLENB3</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4164</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__SHRT_PCKT" title="Short Packet Send/Short Packet Interrupt Enable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__BUSY_BANK" title="Busy Bank Interrupt Enable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__NAK_OUT" title="NAKOUT Interrupt Enable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__STALL_SNT" title="Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__RX_BK_RDY" title="Received OUT Data Interrupt Enable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__ERR_OVFLW" title="Overflow Error Interrupt Enable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__MDATA_RX" title="MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__DATAX_RX" title="DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__AUTO_VALID" title="Packet Auto-Valid Enable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB3__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLENB3__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable endpoint according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB3__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Send/Short Packet Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLDIS3">UDPHS UDPHS Endpoint Control Disable Register (endpoint = 3)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLDIS3</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4168</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__SHRT_PCKT" title="Short Packet Interrupt Disable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__BUSY_BANK" title="Busy Bank Interrupt Disable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__NAK_OUT" title="NAKOUT Interrupt Disable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__NAK_IN" title="NAKIN/bank flush error Interrupt Disable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__RX_SETUP" title="Received SETUP/Error Flow Interrupt Disable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Disable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Disable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__RX_BK_RDY" title="Received OUT Data Interrupt Disable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__ERR_OVFLW" title="Overflow Error Interrupt Disable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__MDATA_RX" title="MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__DATAX_RX" title="DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__NYET_DIS" title="NYET Enable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__AUTO_VALID" title="Packet Auto-Valid Disable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS3__EPT_DISABL" title="Endpoint Disable">EPT_DISABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLDIS3__EPT_DISABL"><strong>EPT_DISABL</strong>: Endpoint Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable this bit to not automatically validate the current packet.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable the "Interrupts Disable DMA".</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__NYET_DIS"><strong>NYET_DIS</strong>: NYET Enable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">let the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__NAK_IN"><strong>NAK_IN</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS3__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTL3">UDPHS UDPHS Endpoint Control Register (endpoint = 3)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTL3</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A416C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL3__SHRT_PCKT" title="Short Packet Interrupt Enabled">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL3__BUSY_BANK" title="Busy Bank Interrupt Enabled">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL3__NAK_OUT" title="NAKOUT Interrupt Enabled">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL3__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enabled">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL3__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL3__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enabled">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL3__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enabled">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL3__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enabled">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL3__RX_BK_RDY" title="Received OUT Data Interrupt Enabled">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL3__ERR_OVFLW" title="Overflow Error Interrupt Enabled">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL3__MDATA_RX" title="MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL3__DATAX_RX" title="DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL3__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL3__INTDIS_DMA" title="Interrupt Disables DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL3__AUTO_VALID" title="Packet Auto-Valid Enabled (Not for CONTROL Endpoints)">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL3__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTL3__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, the endpoint is enabled according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)</li>
<p>-</p>
<li id="UDPHS_EPTCTL3__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupt Disables DMA</li>
<p>-</p>
<li id="UDPHS_EPTCTL3__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Overflow Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Overflow Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKOUT Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKOUT Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL3__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Short Packet Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Short Packet Interrupt is enabled.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSETSTA3">UDPHS UDPHS Endpoint Set Status Register (endpoint = 3)</h4>
<p><strong>Name</strong>: UDPHS_EPTSETSTA3</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4174</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA3__TX_PK_RDY" title="TX Packet Ready Set">TX_PK_RDY</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA3__KILL_BANK" title="KILL Bank Set (for IN Endpoint)">KILL_BANK</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA3__FRCESTALL" title="Stall Handshake Request Set">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSETSTA3__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to request a STALL answer to the host for the next handshake</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA3__KILL_BANK"><strong>KILL_BANK</strong>: KILL Bank Set (for IN Endpoint)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">kill the last written bank.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA3__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit after a packet has been written into the endpoint FIFO for IN data transfers</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCLRSTA3">UDPHS UDPHS Endpoint Clear Status Register (endpoint = 3)</h4>
<p><strong>Name</strong>: UDPHS_EPTCLRSTA3</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4178</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA3__NAK_OUT" title="NAKOUT Clear">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA3__NAK_IN" title="NAKIN/Bank Flush Error Clear">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA3__STALL_SNT" title="Stall Sent/Number of Transaction Error Clear">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA3__RX_SETUP" title="Received SETUP/Error Flow Clear">RX_SETUP</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA3__TX_COMPLT" title="Transmitted IN Data Complete Clear">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA3__RX_BK_RDY" title="Received OUT Data Clear">RX_BK_RDY</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA3__TOGGLESQ" title="Data Toggle Clear">TOGGLESQ</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA3__FRCESTALL" title="Stall Handshake Request Clear">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCLRSTA3__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL request. The next packets from host will not be STALLed.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA3__TOGGLESQ"><strong>TOGGLESQ</strong>: Data Toggle Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the PID data of the current bank</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA3__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_BK_RDY flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA3__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the TX_COMPLT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA3__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA3__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA3__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA3__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA3__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA3__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA3__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_OUT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSTA3">UDPHS UDPHS Endpoint Status Register (endpoint = 3)</h4>
<p><strong>Name</strong>: UDPHS_EPTSTA3</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A417C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA3__SHRT_PCKT" title="Short Packet">SHRT_PCKT</a>
</td>
<td colspan="7">
<a href="#UDPHS_EPTSTA3__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#UDPHS_EPTSTA3__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA3__BUSY_BANK_STA" title="Busy Bank Number">BUSY_BANK_STA</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA3__CURRENT_BANK" title="Current Bank/Control Direction">CURRENT_BANK</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA3__NAK_OUT" title="NAK OUT">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA3__NAK_IN" title="NAK IN/Bank Flush Error">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA3__STALL_SNT" title="Stall Sent/CRC ISO Error/Number of Transaction Error">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA3__RX_SETUP" title="Received SETUP/Error Flow">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA3__TX_PK_RDY" title="TX Packet Ready/Transaction Error">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA3__TX_COMPLT" title="Transmitted IN Data Complete">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA3__RX_BK_RDY" title="Received OUT Data/KILL Bank">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA3__ERR_OVFLW" title="Overflow Error">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTSTA3__TOGGLESQ_STA" title="Toggle Sequencing">TOGGLESQ_STA</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA3__FRCESTALL" title="Stall Handshake Request">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSTA3__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set a STALL answer will be done to the host for the next handshake.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA3__TOGGLESQ_STA"><strong>TOGGLESQ_STA</strong>: Toggle Sequencing<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">DATA0</td><td class="description">DATA0</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DATA1</td><td class="description">DATA1</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">DATA2</td><td class="description">Data2 (only for High Bandwidth Isochronous Endpoint)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">MDATA</td><td class="description">MData (only for High Bandwidth Isochronous Endpoint)</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA3__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__KILL_BANK"><strong>KILL_BANK</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__NAK_IN"><strong>NAK_IN</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__NAK_OUT"><strong>NAK_OUT</strong>: NAK OUT</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__CURRENT_BANK"><strong>CURRENT_BANK</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__CONTROL_DIR"><strong>CONTROL_DIR</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__BUSY_BANK_STA"><strong>BUSY_BANK_STA</strong>: Busy Bank Number<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">1BUSYBANK</td><td class="description">1 busy bank</td></tr><tr class="even"><td class="value">0x1</td><td class="name">2BUSYBANKS</td><td class="description">2 busy banks</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">3BUSYBANKS</td><td class="description">3 busy banks</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA3__BYTE_COUNT"><strong>BYTE_COUNT</strong>: UDPHS Byte Count</li>
<p>-</p>
<li id="UDPHS_EPTSTA3__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet</li>
<p>-</p>
</ul>
<h4 id="UDPHS_EPTCFG4">UDPHS UDPHS Endpoint Configuration Register (endpoint = 4)</h4>
<p><strong>Name</strong>: UDPHS_EPTCFG4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4180</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCFG4__EPT_MAPD" title="Endpoint Mapped">EPT_MAPD</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG4__NB_TRANS" title="Number Of Transaction per Microframe">NB_TRANS</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTCFG4__BK_NUMBER" title="Number of Banks">BK_NUMBER</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG4__EPT_TYPE" title="Endpoint Type">EPT_TYPE</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCFG4__EPT_DIR" title="Endpoint Direction">EPT_DIR</a>
</td>
<td colspan="3">
<a href="#UDPHS_EPTCFG4__EPT_SIZE" title="Endpoint Size">EPT_SIZE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCFG4__EPT_SIZE"><strong>EPT_SIZE</strong>: Endpoint Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">8</td><td class="description">8 bytes</td></tr><tr class="even"><td class="value">0x1</td><td class="name">16</td><td class="description">16 bytes</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">32</td><td class="description">32 bytes</td></tr><tr class="even"><td class="value">0x3</td><td class="name">64</td><td class="description">64 bytes</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">128</td><td class="description">128 bytes</td></tr><tr class="even"><td class="value">0x5</td><td class="name">256</td><td class="description">256 bytes</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">512</td><td class="description">512 bytes</td></tr><tr class="even"><td class="value">0x7</td><td class="name">1024</td><td class="description">1024 bytes</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG4__EPT_DIR"><strong>EPT_DIR</strong>: Endpoint Direction<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG4__EPT_TYPE"><strong>EPT_TYPE</strong>: Endpoint Type<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CTRL8</td><td class="description">Control endpoint</td></tr><tr class="even"><td class="value">0x1</td><td class="name">ISO</td><td class="description">Isochronous endpoint</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">BULK</td><td class="description">Bulk endpoint</td></tr><tr class="even"><td class="value">0x3</td><td class="name">INT</td><td class="description">Interrupt endpoint</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG4__BK_NUMBER"><strong>BK_NUMBER</strong>: Number of Banks<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">0</td><td class="description">Zero bank, the endpoint is not mapped in memory</td></tr><tr class="even"><td class="value">0x1</td><td class="name">1</td><td class="description">One bank (bank 0)</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">2</td><td class="description">Double bank (Ping-Pong: bank0/bank1)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">3</td><td class="description">Triple bank (bank0/bank1/bank2)</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG4__NB_TRANS"><strong>NB_TRANS</strong>: Number Of Transaction per Microframe</li>
<p>-</p>
<li id="UDPHS_EPTCFG4__EPT_MAPD"><strong>EPT_MAPD</strong>: Endpoint Mapped<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the user should reprogram the register with correct values.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLENB4">UDPHS UDPHS Endpoint Control Enable Register (endpoint = 4)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLENB4</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4184</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__SHRT_PCKT" title="Short Packet Send/Short Packet Interrupt Enable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__BUSY_BANK" title="Busy Bank Interrupt Enable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__NAK_OUT" title="NAKOUT Interrupt Enable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__STALL_SNT" title="Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__RX_BK_RDY" title="Received OUT Data Interrupt Enable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__ERR_OVFLW" title="Overflow Error Interrupt Enable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__MDATA_RX" title="MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__DATAX_RX" title="DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__AUTO_VALID" title="Packet Auto-Valid Enable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB4__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLENB4__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable endpoint according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB4__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Send/Short Packet Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLDIS4">UDPHS UDPHS Endpoint Control Disable Register (endpoint = 4)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLDIS4</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4188</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__SHRT_PCKT" title="Short Packet Interrupt Disable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__BUSY_BANK" title="Busy Bank Interrupt Disable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__NAK_OUT" title="NAKOUT Interrupt Disable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__NAK_IN" title="NAKIN/bank flush error Interrupt Disable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__RX_SETUP" title="Received SETUP/Error Flow Interrupt Disable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Disable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Disable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__RX_BK_RDY" title="Received OUT Data Interrupt Disable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__ERR_OVFLW" title="Overflow Error Interrupt Disable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__MDATA_RX" title="MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__DATAX_RX" title="DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__NYET_DIS" title="NYET Enable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__AUTO_VALID" title="Packet Auto-Valid Disable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS4__EPT_DISABL" title="Endpoint Disable">EPT_DISABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLDIS4__EPT_DISABL"><strong>EPT_DISABL</strong>: Endpoint Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable this bit to not automatically validate the current packet.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable the "Interrupts Disable DMA".</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__NYET_DIS"><strong>NYET_DIS</strong>: NYET Enable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">let the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__NAK_IN"><strong>NAK_IN</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS4__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTL4">UDPHS UDPHS Endpoint Control Register (endpoint = 4)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTL4</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A418C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL4__SHRT_PCKT" title="Short Packet Interrupt Enabled">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL4__BUSY_BANK" title="Busy Bank Interrupt Enabled">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL4__NAK_OUT" title="NAKOUT Interrupt Enabled">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL4__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enabled">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL4__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL4__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enabled">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL4__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enabled">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL4__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enabled">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL4__RX_BK_RDY" title="Received OUT Data Interrupt Enabled">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL4__ERR_OVFLW" title="Overflow Error Interrupt Enabled">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL4__MDATA_RX" title="MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL4__DATAX_RX" title="DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL4__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL4__INTDIS_DMA" title="Interrupt Disables DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL4__AUTO_VALID" title="Packet Auto-Valid Enabled (Not for CONTROL Endpoints)">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL4__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTL4__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, the endpoint is enabled according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)</li>
<p>-</p>
<li id="UDPHS_EPTCTL4__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupt Disables DMA</li>
<p>-</p>
<li id="UDPHS_EPTCTL4__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Overflow Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Overflow Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKOUT Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKOUT Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL4__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Short Packet Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Short Packet Interrupt is enabled.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSETSTA4">UDPHS UDPHS Endpoint Set Status Register (endpoint = 4)</h4>
<p><strong>Name</strong>: UDPHS_EPTSETSTA4</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4194</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA4__TX_PK_RDY" title="TX Packet Ready Set">TX_PK_RDY</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA4__KILL_BANK" title="KILL Bank Set (for IN Endpoint)">KILL_BANK</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA4__FRCESTALL" title="Stall Handshake Request Set">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSETSTA4__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to request a STALL answer to the host for the next handshake</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA4__KILL_BANK"><strong>KILL_BANK</strong>: KILL Bank Set (for IN Endpoint)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">kill the last written bank.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA4__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit after a packet has been written into the endpoint FIFO for IN data transfers</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCLRSTA4">UDPHS UDPHS Endpoint Clear Status Register (endpoint = 4)</h4>
<p><strong>Name</strong>: UDPHS_EPTCLRSTA4</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A4198</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA4__NAK_OUT" title="NAKOUT Clear">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA4__NAK_IN" title="NAKIN/Bank Flush Error Clear">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA4__STALL_SNT" title="Stall Sent/Number of Transaction Error Clear">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA4__RX_SETUP" title="Received SETUP/Error Flow Clear">RX_SETUP</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA4__TX_COMPLT" title="Transmitted IN Data Complete Clear">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA4__RX_BK_RDY" title="Received OUT Data Clear">RX_BK_RDY</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA4__TOGGLESQ" title="Data Toggle Clear">TOGGLESQ</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA4__FRCESTALL" title="Stall Handshake Request Clear">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCLRSTA4__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL request. The next packets from host will not be STALLed.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA4__TOGGLESQ"><strong>TOGGLESQ</strong>: Data Toggle Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the PID data of the current bank</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA4__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_BK_RDY flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA4__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the TX_COMPLT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA4__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA4__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA4__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA4__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA4__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA4__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA4__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_OUT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSTA4">UDPHS UDPHS Endpoint Status Register (endpoint = 4)</h4>
<p><strong>Name</strong>: UDPHS_EPTSTA4</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A419C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA4__SHRT_PCKT" title="Short Packet">SHRT_PCKT</a>
</td>
<td colspan="7">
<a href="#UDPHS_EPTSTA4__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#UDPHS_EPTSTA4__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA4__BUSY_BANK_STA" title="Busy Bank Number">BUSY_BANK_STA</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA4__CURRENT_BANK" title="Current Bank/Control Direction">CURRENT_BANK</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA4__NAK_OUT" title="NAK OUT">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA4__NAK_IN" title="NAK IN/Bank Flush Error">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA4__STALL_SNT" title="Stall Sent/CRC ISO Error/Number of Transaction Error">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA4__RX_SETUP" title="Received SETUP/Error Flow">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA4__TX_PK_RDY" title="TX Packet Ready/Transaction Error">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA4__TX_COMPLT" title="Transmitted IN Data Complete">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA4__RX_BK_RDY" title="Received OUT Data/KILL Bank">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA4__ERR_OVFLW" title="Overflow Error">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTSTA4__TOGGLESQ_STA" title="Toggle Sequencing">TOGGLESQ_STA</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA4__FRCESTALL" title="Stall Handshake Request">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSTA4__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set a STALL answer will be done to the host for the next handshake.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA4__TOGGLESQ_STA"><strong>TOGGLESQ_STA</strong>: Toggle Sequencing<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">DATA0</td><td class="description">DATA0</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DATA1</td><td class="description">DATA1</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">DATA2</td><td class="description">Data2 (only for High Bandwidth Isochronous Endpoint)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">MDATA</td><td class="description">MData (only for High Bandwidth Isochronous Endpoint)</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA4__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__KILL_BANK"><strong>KILL_BANK</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__NAK_IN"><strong>NAK_IN</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__NAK_OUT"><strong>NAK_OUT</strong>: NAK OUT</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__CURRENT_BANK"><strong>CURRENT_BANK</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__CONTROL_DIR"><strong>CONTROL_DIR</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__BUSY_BANK_STA"><strong>BUSY_BANK_STA</strong>: Busy Bank Number<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">1BUSYBANK</td><td class="description">1 busy bank</td></tr><tr class="even"><td class="value">0x1</td><td class="name">2BUSYBANKS</td><td class="description">2 busy banks</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">3BUSYBANKS</td><td class="description">3 busy banks</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA4__BYTE_COUNT"><strong>BYTE_COUNT</strong>: UDPHS Byte Count</li>
<p>-</p>
<li id="UDPHS_EPTSTA4__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet</li>
<p>-</p>
</ul>
<h4 id="UDPHS_EPTCFG5">UDPHS UDPHS Endpoint Configuration Register (endpoint = 5)</h4>
<p><strong>Name</strong>: UDPHS_EPTCFG5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A41A0</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCFG5__EPT_MAPD" title="Endpoint Mapped">EPT_MAPD</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG5__NB_TRANS" title="Number Of Transaction per Microframe">NB_TRANS</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTCFG5__BK_NUMBER" title="Number of Banks">BK_NUMBER</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG5__EPT_TYPE" title="Endpoint Type">EPT_TYPE</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCFG5__EPT_DIR" title="Endpoint Direction">EPT_DIR</a>
</td>
<td colspan="3">
<a href="#UDPHS_EPTCFG5__EPT_SIZE" title="Endpoint Size">EPT_SIZE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCFG5__EPT_SIZE"><strong>EPT_SIZE</strong>: Endpoint Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">8</td><td class="description">8 bytes</td></tr><tr class="even"><td class="value">0x1</td><td class="name">16</td><td class="description">16 bytes</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">32</td><td class="description">32 bytes</td></tr><tr class="even"><td class="value">0x3</td><td class="name">64</td><td class="description">64 bytes</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">128</td><td class="description">128 bytes</td></tr><tr class="even"><td class="value">0x5</td><td class="name">256</td><td class="description">256 bytes</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">512</td><td class="description">512 bytes</td></tr><tr class="even"><td class="value">0x7</td><td class="name">1024</td><td class="description">1024 bytes</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG5__EPT_DIR"><strong>EPT_DIR</strong>: Endpoint Direction<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG5__EPT_TYPE"><strong>EPT_TYPE</strong>: Endpoint Type<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CTRL8</td><td class="description">Control endpoint</td></tr><tr class="even"><td class="value">0x1</td><td class="name">ISO</td><td class="description">Isochronous endpoint</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">BULK</td><td class="description">Bulk endpoint</td></tr><tr class="even"><td class="value">0x3</td><td class="name">INT</td><td class="description">Interrupt endpoint</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG5__BK_NUMBER"><strong>BK_NUMBER</strong>: Number of Banks<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">0</td><td class="description">Zero bank, the endpoint is not mapped in memory</td></tr><tr class="even"><td class="value">0x1</td><td class="name">1</td><td class="description">One bank (bank 0)</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">2</td><td class="description">Double bank (Ping-Pong: bank0/bank1)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">3</td><td class="description">Triple bank (bank0/bank1/bank2)</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG5__NB_TRANS"><strong>NB_TRANS</strong>: Number Of Transaction per Microframe</li>
<p>-</p>
<li id="UDPHS_EPTCFG5__EPT_MAPD"><strong>EPT_MAPD</strong>: Endpoint Mapped<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the user should reprogram the register with correct values.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLENB5">UDPHS UDPHS Endpoint Control Enable Register (endpoint = 5)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLENB5</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A41A4</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__SHRT_PCKT" title="Short Packet Send/Short Packet Interrupt Enable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__BUSY_BANK" title="Busy Bank Interrupt Enable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__NAK_OUT" title="NAKOUT Interrupt Enable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__STALL_SNT" title="Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__RX_BK_RDY" title="Received OUT Data Interrupt Enable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__ERR_OVFLW" title="Overflow Error Interrupt Enable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__MDATA_RX" title="MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__DATAX_RX" title="DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__AUTO_VALID" title="Packet Auto-Valid Enable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB5__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLENB5__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable endpoint according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB5__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Send/Short Packet Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLDIS5">UDPHS UDPHS Endpoint Control Disable Register (endpoint = 5)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLDIS5</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A41A8</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__SHRT_PCKT" title="Short Packet Interrupt Disable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__BUSY_BANK" title="Busy Bank Interrupt Disable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__NAK_OUT" title="NAKOUT Interrupt Disable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__NAK_IN" title="NAKIN/bank flush error Interrupt Disable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__RX_SETUP" title="Received SETUP/Error Flow Interrupt Disable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Disable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Disable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__RX_BK_RDY" title="Received OUT Data Interrupt Disable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__ERR_OVFLW" title="Overflow Error Interrupt Disable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__MDATA_RX" title="MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__DATAX_RX" title="DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__NYET_DIS" title="NYET Enable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__AUTO_VALID" title="Packet Auto-Valid Disable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS5__EPT_DISABL" title="Endpoint Disable">EPT_DISABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLDIS5__EPT_DISABL"><strong>EPT_DISABL</strong>: Endpoint Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable this bit to not automatically validate the current packet.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable the "Interrupts Disable DMA".</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__NYET_DIS"><strong>NYET_DIS</strong>: NYET Enable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">let the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__NAK_IN"><strong>NAK_IN</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS5__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTL5">UDPHS UDPHS Endpoint Control Register (endpoint = 5)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTL5</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A41AC</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL5__SHRT_PCKT" title="Short Packet Interrupt Enabled">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL5__BUSY_BANK" title="Busy Bank Interrupt Enabled">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL5__NAK_OUT" title="NAKOUT Interrupt Enabled">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL5__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enabled">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL5__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL5__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enabled">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL5__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enabled">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL5__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enabled">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL5__RX_BK_RDY" title="Received OUT Data Interrupt Enabled">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL5__ERR_OVFLW" title="Overflow Error Interrupt Enabled">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL5__MDATA_RX" title="MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL5__DATAX_RX" title="DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL5__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL5__INTDIS_DMA" title="Interrupt Disables DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL5__AUTO_VALID" title="Packet Auto-Valid Enabled (Not for CONTROL Endpoints)">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL5__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTL5__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, the endpoint is enabled according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)</li>
<p>-</p>
<li id="UDPHS_EPTCTL5__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupt Disables DMA</li>
<p>-</p>
<li id="UDPHS_EPTCTL5__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Overflow Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Overflow Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKOUT Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKOUT Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL5__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Short Packet Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Short Packet Interrupt is enabled.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSETSTA5">UDPHS UDPHS Endpoint Set Status Register (endpoint = 5)</h4>
<p><strong>Name</strong>: UDPHS_EPTSETSTA5</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A41B4</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA5__TX_PK_RDY" title="TX Packet Ready Set">TX_PK_RDY</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA5__KILL_BANK" title="KILL Bank Set (for IN Endpoint)">KILL_BANK</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA5__FRCESTALL" title="Stall Handshake Request Set">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSETSTA5__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to request a STALL answer to the host for the next handshake</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA5__KILL_BANK"><strong>KILL_BANK</strong>: KILL Bank Set (for IN Endpoint)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">kill the last written bank.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA5__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit after a packet has been written into the endpoint FIFO for IN data transfers</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCLRSTA5">UDPHS UDPHS Endpoint Clear Status Register (endpoint = 5)</h4>
<p><strong>Name</strong>: UDPHS_EPTCLRSTA5</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A41B8</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA5__NAK_OUT" title="NAKOUT Clear">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA5__NAK_IN" title="NAKIN/Bank Flush Error Clear">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA5__STALL_SNT" title="Stall Sent/Number of Transaction Error Clear">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA5__RX_SETUP" title="Received SETUP/Error Flow Clear">RX_SETUP</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA5__TX_COMPLT" title="Transmitted IN Data Complete Clear">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA5__RX_BK_RDY" title="Received OUT Data Clear">RX_BK_RDY</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA5__TOGGLESQ" title="Data Toggle Clear">TOGGLESQ</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA5__FRCESTALL" title="Stall Handshake Request Clear">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCLRSTA5__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL request. The next packets from host will not be STALLed.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA5__TOGGLESQ"><strong>TOGGLESQ</strong>: Data Toggle Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the PID data of the current bank</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA5__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_BK_RDY flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA5__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the TX_COMPLT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA5__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA5__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA5__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA5__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA5__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA5__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA5__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_OUT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSTA5">UDPHS UDPHS Endpoint Status Register (endpoint = 5)</h4>
<p><strong>Name</strong>: UDPHS_EPTSTA5</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A41BC</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA5__SHRT_PCKT" title="Short Packet">SHRT_PCKT</a>
</td>
<td colspan="7">
<a href="#UDPHS_EPTSTA5__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#UDPHS_EPTSTA5__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA5__BUSY_BANK_STA" title="Busy Bank Number">BUSY_BANK_STA</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA5__CURRENT_BANK" title="Current Bank/Control Direction">CURRENT_BANK</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA5__NAK_OUT" title="NAK OUT">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA5__NAK_IN" title="NAK IN/Bank Flush Error">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA5__STALL_SNT" title="Stall Sent/CRC ISO Error/Number of Transaction Error">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA5__RX_SETUP" title="Received SETUP/Error Flow">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA5__TX_PK_RDY" title="TX Packet Ready/Transaction Error">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA5__TX_COMPLT" title="Transmitted IN Data Complete">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA5__RX_BK_RDY" title="Received OUT Data/KILL Bank">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA5__ERR_OVFLW" title="Overflow Error">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTSTA5__TOGGLESQ_STA" title="Toggle Sequencing">TOGGLESQ_STA</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA5__FRCESTALL" title="Stall Handshake Request">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSTA5__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set a STALL answer will be done to the host for the next handshake.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA5__TOGGLESQ_STA"><strong>TOGGLESQ_STA</strong>: Toggle Sequencing<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">DATA0</td><td class="description">DATA0</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DATA1</td><td class="description">DATA1</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">DATA2</td><td class="description">Data2 (only for High Bandwidth Isochronous Endpoint)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">MDATA</td><td class="description">MData (only for High Bandwidth Isochronous Endpoint)</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA5__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__KILL_BANK"><strong>KILL_BANK</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__NAK_IN"><strong>NAK_IN</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__NAK_OUT"><strong>NAK_OUT</strong>: NAK OUT</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__CURRENT_BANK"><strong>CURRENT_BANK</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__CONTROL_DIR"><strong>CONTROL_DIR</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__BUSY_BANK_STA"><strong>BUSY_BANK_STA</strong>: Busy Bank Number<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">1BUSYBANK</td><td class="description">1 busy bank</td></tr><tr class="even"><td class="value">0x1</td><td class="name">2BUSYBANKS</td><td class="description">2 busy banks</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">3BUSYBANKS</td><td class="description">3 busy banks</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA5__BYTE_COUNT"><strong>BYTE_COUNT</strong>: UDPHS Byte Count</li>
<p>-</p>
<li id="UDPHS_EPTSTA5__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet</li>
<p>-</p>
</ul>
<h4 id="UDPHS_EPTCFG6">UDPHS UDPHS Endpoint Configuration Register (endpoint = 6)</h4>
<p><strong>Name</strong>: UDPHS_EPTCFG6</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A41C0</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCFG6__EPT_MAPD" title="Endpoint Mapped">EPT_MAPD</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG6__NB_TRANS" title="Number Of Transaction per Microframe">NB_TRANS</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTCFG6__BK_NUMBER" title="Number of Banks">BK_NUMBER</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTCFG6__EPT_TYPE" title="Endpoint Type">EPT_TYPE</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCFG6__EPT_DIR" title="Endpoint Direction">EPT_DIR</a>
</td>
<td colspan="3">
<a href="#UDPHS_EPTCFG6__EPT_SIZE" title="Endpoint Size">EPT_SIZE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCFG6__EPT_SIZE"><strong>EPT_SIZE</strong>: Endpoint Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">8</td><td class="description">8 bytes</td></tr><tr class="even"><td class="value">0x1</td><td class="name">16</td><td class="description">16 bytes</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">32</td><td class="description">32 bytes</td></tr><tr class="even"><td class="value">0x3</td><td class="name">64</td><td class="description">64 bytes</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">128</td><td class="description">128 bytes</td></tr><tr class="even"><td class="value">0x5</td><td class="name">256</td><td class="description">256 bytes</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">512</td><td class="description">512 bytes</td></tr><tr class="even"><td class="value">0x7</td><td class="name">1024</td><td class="description">1024 bytes</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG6__EPT_DIR"><strong>EPT_DIR</strong>: Endpoint Direction<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG6__EPT_TYPE"><strong>EPT_TYPE</strong>: Endpoint Type<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">CTRL8</td><td class="description">Control endpoint</td></tr><tr class="even"><td class="value">0x1</td><td class="name">ISO</td><td class="description">Isochronous endpoint</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">BULK</td><td class="description">Bulk endpoint</td></tr><tr class="even"><td class="value">0x3</td><td class="name">INT</td><td class="description">Interrupt endpoint</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG6__BK_NUMBER"><strong>BK_NUMBER</strong>: Number of Banks<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">0</td><td class="description">Zero bank, the endpoint is not mapped in memory</td></tr><tr class="even"><td class="value">0x1</td><td class="name">1</td><td class="description">One bank (bank 0)</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">2</td><td class="description">Double bank (Ping-Pong: bank0/bank1)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">3</td><td class="description">Triple bank (bank0/bank1/bank2)</td></tr></tbody></table></li>
<li id="UDPHS_EPTCFG6__NB_TRANS"><strong>NB_TRANS</strong>: Number Of Transaction per Microframe</li>
<p>-</p>
<li id="UDPHS_EPTCFG6__EPT_MAPD"><strong>EPT_MAPD</strong>: Endpoint Mapped<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the user should reprogram the register with correct values.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLENB6">UDPHS UDPHS Endpoint Control Enable Register (endpoint = 6)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLENB6</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A41C4</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__SHRT_PCKT" title="Short Packet Send/Short Packet Interrupt Enable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__BUSY_BANK" title="Busy Bank Interrupt Enable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__NAK_OUT" title="NAKOUT Interrupt Enable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__STALL_SNT" title="Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__RX_BK_RDY" title="Received OUT Data Interrupt Enable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__ERR_OVFLW" title="Overflow Error Interrupt Enable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__MDATA_RX" title="MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__DATAX_RX" title="DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__AUTO_VALID" title="Packet Auto-Valid Enable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLENB6__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLENB6__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable endpoint according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKIN/Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLENB6__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Send/Short Packet Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">enable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTLDIS6">UDPHS UDPHS Endpoint Control Disable Register (endpoint = 6)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTLDIS6</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A41C8</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__SHRT_PCKT" title="Short Packet Interrupt Disable">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__BUSY_BANK" title="Busy Bank Interrupt Disable">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__NAK_OUT" title="NAKOUT Interrupt Disable">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__NAK_IN" title="NAKIN/bank flush error Interrupt Disable">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__RX_SETUP" title="Received SETUP/Error Flow Interrupt Disable">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Disable">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Disable">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__RX_BK_RDY" title="Received OUT Data Interrupt Disable">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__ERR_OVFLW" title="Overflow Error Interrupt Disable">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__MDATA_RX" title="MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__DATAX_RX" title="DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__NYET_DIS" title="NYET Enable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__INTDIS_DMA" title="Interrupts Disable DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__AUTO_VALID" title="Packet Auto-Valid Disable">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTLDIS6__EPT_DISABL" title="Endpoint Disable">EPT_DISABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTLDIS6__EPT_DISABL"><strong>EPT_DISABL</strong>: Endpoint Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable endpoint.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable this bit to not automatically validate the current packet.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupts Disable DMA<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable the "Interrupts Disable DMA".</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__NYET_DIS"><strong>NYET_DIS</strong>: NYET Enable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">let the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable DATAx Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable MDATA Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Overflow Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Received OUT Data Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Transmitted IN Data Complete Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable TX Packet Ready/Transaction Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable RX_SETUP/Error Flow ISO Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__NAK_IN"><strong>NAK_IN</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/bank flush error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKIN/ Bank Flush Error Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable NAKOUT Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Busy Bank Interrupt.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTLDIS6__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">disable Short Packet Interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCTL6">UDPHS UDPHS Endpoint Control Register (endpoint = 6)</h4>
<p><strong>Name</strong>: UDPHS_EPTCTL6</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A41CC</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL6__SHRT_PCKT" title="Short Packet Interrupt Enabled">SHRT_PCKT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL6__BUSY_BANK" title="Busy Bank Interrupt Enabled">BUSY_BANK</a>
</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL6__NAK_OUT" title="NAKOUT Interrupt Enabled">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL6__NAK_IN" title="NAKIN/Bank Flush Error Interrupt Enabled">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL6__STALL_SNT" title="Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL6__RX_SETUP" title="Received SETUP/Error Flow Interrupt Enabled">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL6__TX_PK_RDY" title="TX Packet Ready/Transaction Error Interrupt Enabled">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL6__TX_COMPLT" title="Transmitted IN Data Complete Interrupt Enabled">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL6__RX_BK_RDY" title="Received OUT Data Interrupt Enabled">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL6__ERR_OVFLW" title="Overflow Error Interrupt Enabled">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCTL6__MDATA_RX" title="MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">MDATA_RX</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL6__DATAX_RX" title="DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)">DATAX_RX</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL6__NYET_DIS" title="NYET Disable (Only for High Speed Bulk OUT endpoints)">NYET_DIS</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL6__INTDIS_DMA" title="Interrupt Disables DMA">INTDIS_DMA</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL6__AUTO_VALID" title="Packet Auto-Valid Enabled (Not for CONTROL Endpoints)">AUTO_VALID</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCTL6__EPT_ENABL" title="Endpoint Enable">EPT_ENABL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCTL6__EPT_ENABL"><strong>EPT_ENABL</strong>: Endpoint Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, the endpoint is enabled according to the device configuration.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__AUTO_VALID"><strong>AUTO_VALID</strong>: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)</li>
<p>-</p>
<li id="UDPHS_EPTCTL6__INTDIS_DMA"><strong>INTDIS_DMA</strong>: Interrupt Disables DMA</li>
<p>-</p>
<li id="UDPHS_EPTCTL6__NYET_DIS"><strong>NYET_DIS</strong>: NYET Disable (Only for High Speed Bulk OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__DATAX_RX"><strong>DATAX_RX</strong>: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__MDATA_RX"><strong>MDATA_RX</strong>: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Overflow Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Overflow Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received OUT Data Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Transmitted IN Data Complete Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">TX Packet Ready/Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Received SETUP/Error Flow Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKIN Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKIN/Bank Flush Error Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NAKOUT Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">NAKOUT Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__BUSY_BANK"><strong>BUSY_BANK</strong>: Busy Bank Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">BUSY_BANK Interrupt is enabled.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCTL6__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet Interrupt Enabled<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Short Packet Interrupt is masked.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Short Packet Interrupt is enabled.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSETSTA6">UDPHS UDPHS Endpoint Set Status Register (endpoint = 6)</h4>
<p><strong>Name</strong>: UDPHS_EPTSETSTA6</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A41D4</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA6__TX_PK_RDY" title="TX Packet Ready Set">TX_PK_RDY</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA6__KILL_BANK" title="KILL Bank Set (for IN Endpoint)">KILL_BANK</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTSETSTA6__FRCESTALL" title="Stall Handshake Request Set">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSETSTA6__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit to request a STALL answer to the host for the next handshake</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA6__KILL_BANK"><strong>KILL_BANK</strong>: KILL Bank Set (for IN Endpoint)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">kill the last written bank.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSETSTA6__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready Set<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set this bit after a packet has been written into the endpoint FIFO for IN data transfers</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTCLRSTA6">UDPHS UDPHS Endpoint Clear Status Register (endpoint = 6)</h4>
<p><strong>Name</strong>: UDPHS_EPTCLRSTA6</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x400A41D8</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA6__NAK_OUT" title="NAKOUT Clear">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA6__NAK_IN" title="NAKIN/Bank Flush Error Clear">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA6__STALL_SNT" title="Stall Sent/Number of Transaction Error Clear">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA6__RX_SETUP" title="Received SETUP/Error Flow Clear">RX_SETUP</a>
</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA6__TX_COMPLT" title="Transmitted IN Data Complete Clear">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA6__RX_BK_RDY" title="Received OUT Data Clear">RX_BK_RDY</a>
</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA6__TOGGLESQ" title="Data Toggle Clear">TOGGLESQ</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTCLRSTA6__FRCESTALL" title="Stall Handshake Request Clear">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTCLRSTA6__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL request. The next packets from host will not be STALLed.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA6__TOGGLESQ"><strong>TOGGLESQ</strong>: Data Toggle Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the PID data of the current bank</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA6__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_BK_RDY flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA6__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the TX_COMPLT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA6__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA6__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA6__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA6__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/Number of Transaction Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA6__NAK_IN"><strong>NAK_IN</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA6__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAKIN/Bank Flush Error Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
<li id="UDPHS_EPTCLRSTA6__NAK_OUT"><strong>NAK_OUT</strong>: NAKOUT Clear<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">clear the NAK_OUT flag of UDPHS_EPTSTAx.</td></tr></tbody></table></li>
</ul>
<h4 id="UDPHS_EPTSTA6">UDPHS UDPHS Endpoint Status Register (endpoint = 6)</h4>
<p><strong>Name</strong>: UDPHS_EPTSTA6</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400A41DC</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA6__SHRT_PCKT" title="Short Packet">SHRT_PCKT</a>
</td>
<td colspan="7">
<a href="#UDPHS_EPTSTA6__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="4">
<a href="#UDPHS_EPTSTA6__BYTE_COUNT" title="UDPHS Byte Count">BYTE_COUNT</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA6__BUSY_BANK_STA" title="Busy Bank Number">BUSY_BANK_STA</a>
</td>
<td colspan="2">
<a href="#UDPHS_EPTSTA6__CURRENT_BANK" title="Current Bank/Control Direction">CURRENT_BANK</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_EPTSTA6__NAK_OUT" title="NAK OUT">NAK_OUT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA6__NAK_IN" title="NAK IN/Bank Flush Error">NAK_IN</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA6__STALL_SNT" title="Stall Sent/CRC ISO Error/Number of Transaction Error">STALL_SNT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA6__RX_SETUP" title="Received SETUP/Error Flow">RX_SETUP</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA6__TX_PK_RDY" title="TX Packet Ready/Transaction Error">TX_PK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA6__TX_COMPLT" title="Transmitted IN Data Complete">TX_COMPLT</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA6__RX_BK_RDY" title="Received OUT Data/KILL Bank">RX_BK_RDY</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA6__ERR_OVFLW" title="Overflow Error">ERR_OVFLW</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#UDPHS_EPTSTA6__TOGGLESQ_STA" title="Toggle Sequencing">TOGGLESQ_STA</a>
</td>
<td colspan="1">
<a href="#UDPHS_EPTSTA6__FRCESTALL" title="Stall Handshake Request">FRCESTALL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_EPTSTA6__FRCESTALL"><strong>FRCESTALL</strong>: Stall Handshake Request<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">no effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set a STALL answer will be done to the host for the next handshake.</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA6__TOGGLESQ_STA"><strong>TOGGLESQ_STA</strong>: Toggle Sequencing<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">DATA0</td><td class="description">DATA0</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DATA1</td><td class="description">DATA1</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">DATA2</td><td class="description">Data2 (only for High Bandwidth Isochronous Endpoint)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">MDATA</td><td class="description">MData (only for High Bandwidth Isochronous Endpoint)</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA6__ERR_OVFLW"><strong>ERR_OVFLW</strong>: Overflow Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__RX_BK_RDY"><strong>RX_BK_RDY</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__KILL_BANK"><strong>KILL_BANK</strong>: Received OUT Data/KILL Bank</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__TX_COMPLT"><strong>TX_COMPLT</strong>: Transmitted IN Data Complete</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__TX_PK_RDY"><strong>TX_PK_RDY</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__ERR_TRANS"><strong>ERR_TRANS</strong>: TX Packet Ready/Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__RX_SETUP"><strong>RX_SETUP</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__ERR_FL_ISO"><strong>ERR_FL_ISO</strong>: Received SETUP/Error Flow</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__STALL_SNT"><strong>STALL_SNT</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__ERR_CRISO"><strong>ERR_CRISO</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__ERR_NBTRA"><strong>ERR_NBTRA</strong>: Stall Sent/CRC ISO Error/Number of Transaction Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__NAK_IN"><strong>NAK_IN</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__ERR_FLUSH"><strong>ERR_FLUSH</strong>: NAK IN/Bank Flush Error</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__NAK_OUT"><strong>NAK_OUT</strong>: NAK OUT</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__CURRENT_BANK"><strong>CURRENT_BANK</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__CONTROL_DIR"><strong>CONTROL_DIR</strong>: Current Bank/Control Direction</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__BUSY_BANK_STA"><strong>BUSY_BANK_STA</strong>: Busy Bank Number<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">1BUSYBANK</td><td class="description">1 busy bank</td></tr><tr class="even"><td class="value">0x1</td><td class="name">2BUSYBANKS</td><td class="description">2 busy banks</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">3BUSYBANKS</td><td class="description">3 busy banks</td></tr></tbody></table></li>
<li id="UDPHS_EPTSTA6__BYTE_COUNT"><strong>BYTE_COUNT</strong>: UDPHS Byte Count</li>
<p>-</p>
<li id="UDPHS_EPTSTA6__SHRT_PCKT"><strong>SHRT_PCKT</strong>: Short Packet</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMANXTDSC0">UDPHS UDPHS DMA Next Descriptor Address Register (channel = 0)</h4>
<p><strong>Name</strong>: UDPHS_DMANXTDSC0</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4300</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC0__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC0__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC0__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC0__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMANXTDSC0__NXT_DSC_ADD">
<strong>NXT_DSC_ADD</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMAADDRESS0">UDPHS UDPHS DMA Channel Address Register (channel = 0)</h4>
<p><strong>Name</strong>: UDPHS_DMAADDRESS0</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4304</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS0__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS0__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS0__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS0__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMAADDRESS0__BUFF_ADD">
<strong>BUFF_ADD</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMACONTROL0">UDPHS UDPHS DMA Channel Control Register (channel = 0)</h4>
<p><strong>Name</strong>: UDPHS_DMACONTROL0</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4308</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMACONTROL0__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMACONTROL0__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_DMACONTROL0__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL0__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL0__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL0__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL0__END_B_EN" title="End of Buffer Enable (Control)">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL0__END_TR_EN" title="End of Transfer Enable (Control)">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL0__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable (Command)">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL0__CHANN_ENB" title="">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMACONTROL0__CHANN_ENB">
<strong>CHANN_ENB</strong>
</li>
<p>-</p>
<li id="UDPHS_DMACONTROL0__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable (Command)</li>
<p>-</p>
<li id="UDPHS_DMACONTROL0__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UDPHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL0__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL0__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL0__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL0__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL0__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL0__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMASTATUS0">UDPHS UDPHS DMA Channel Status Register (channel = 0)</h4>
<p><strong>Name</strong>: UDPHS_DMASTATUS0</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A430C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMASTATUS0__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMASTATUS0__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS0__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS0__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS0__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS0__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS0__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMASTATUS0__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS0__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS0__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS0__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the BUFF_COUNT downcount reach zero.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS0__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS0__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMANXTDSC1">UDPHS UDPHS DMA Next Descriptor Address Register (channel = 1)</h4>
<p><strong>Name</strong>: UDPHS_DMANXTDSC1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4310</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC1__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC1__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC1__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC1__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMANXTDSC1__NXT_DSC_ADD">
<strong>NXT_DSC_ADD</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMAADDRESS1">UDPHS UDPHS DMA Channel Address Register (channel = 1)</h4>
<p><strong>Name</strong>: UDPHS_DMAADDRESS1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4314</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS1__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS1__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS1__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS1__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMAADDRESS1__BUFF_ADD">
<strong>BUFF_ADD</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMACONTROL1">UDPHS UDPHS DMA Channel Control Register (channel = 1)</h4>
<p><strong>Name</strong>: UDPHS_DMACONTROL1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4318</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMACONTROL1__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMACONTROL1__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_DMACONTROL1__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL1__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL1__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL1__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL1__END_B_EN" title="End of Buffer Enable (Control)">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL1__END_TR_EN" title="End of Transfer Enable (Control)">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL1__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable (Command)">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL1__CHANN_ENB" title="">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMACONTROL1__CHANN_ENB">
<strong>CHANN_ENB</strong>
</li>
<p>-</p>
<li id="UDPHS_DMACONTROL1__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable (Command)</li>
<p>-</p>
<li id="UDPHS_DMACONTROL1__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UDPHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL1__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL1__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL1__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL1__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL1__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL1__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMASTATUS1">UDPHS UDPHS DMA Channel Status Register (channel = 1)</h4>
<p><strong>Name</strong>: UDPHS_DMASTATUS1</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A431C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMASTATUS1__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMASTATUS1__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS1__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS1__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS1__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS1__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS1__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMASTATUS1__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS1__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS1__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS1__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the BUFF_COUNT downcount reach zero.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS1__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS1__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMANXTDSC2">UDPHS UDPHS DMA Next Descriptor Address Register (channel = 2)</h4>
<p><strong>Name</strong>: UDPHS_DMANXTDSC2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4320</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC2__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC2__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC2__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC2__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMANXTDSC2__NXT_DSC_ADD">
<strong>NXT_DSC_ADD</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMAADDRESS2">UDPHS UDPHS DMA Channel Address Register (channel = 2)</h4>
<p><strong>Name</strong>: UDPHS_DMAADDRESS2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4324</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS2__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS2__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS2__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS2__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMAADDRESS2__BUFF_ADD">
<strong>BUFF_ADD</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMACONTROL2">UDPHS UDPHS DMA Channel Control Register (channel = 2)</h4>
<p><strong>Name</strong>: UDPHS_DMACONTROL2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4328</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMACONTROL2__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMACONTROL2__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_DMACONTROL2__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL2__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL2__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL2__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL2__END_B_EN" title="End of Buffer Enable (Control)">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL2__END_TR_EN" title="End of Transfer Enable (Control)">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL2__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable (Command)">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL2__CHANN_ENB" title="">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMACONTROL2__CHANN_ENB">
<strong>CHANN_ENB</strong>
</li>
<p>-</p>
<li id="UDPHS_DMACONTROL2__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable (Command)</li>
<p>-</p>
<li id="UDPHS_DMACONTROL2__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UDPHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL2__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL2__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL2__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL2__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL2__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL2__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMASTATUS2">UDPHS UDPHS DMA Channel Status Register (channel = 2)</h4>
<p><strong>Name</strong>: UDPHS_DMASTATUS2</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A432C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMASTATUS2__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMASTATUS2__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS2__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS2__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS2__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS2__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS2__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMASTATUS2__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS2__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS2__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS2__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the BUFF_COUNT downcount reach zero.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS2__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS2__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMANXTDSC3">UDPHS UDPHS DMA Next Descriptor Address Register (channel = 3)</h4>
<p><strong>Name</strong>: UDPHS_DMANXTDSC3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4330</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC3__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC3__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC3__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC3__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMANXTDSC3__NXT_DSC_ADD">
<strong>NXT_DSC_ADD</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMAADDRESS3">UDPHS UDPHS DMA Channel Address Register (channel = 3)</h4>
<p><strong>Name</strong>: UDPHS_DMAADDRESS3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4334</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS3__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS3__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS3__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS3__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMAADDRESS3__BUFF_ADD">
<strong>BUFF_ADD</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMACONTROL3">UDPHS UDPHS DMA Channel Control Register (channel = 3)</h4>
<p><strong>Name</strong>: UDPHS_DMACONTROL3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4338</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMACONTROL3__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMACONTROL3__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_DMACONTROL3__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL3__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL3__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL3__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL3__END_B_EN" title="End of Buffer Enable (Control)">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL3__END_TR_EN" title="End of Transfer Enable (Control)">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL3__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable (Command)">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL3__CHANN_ENB" title="">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMACONTROL3__CHANN_ENB">
<strong>CHANN_ENB</strong>
</li>
<p>-</p>
<li id="UDPHS_DMACONTROL3__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable (Command)</li>
<p>-</p>
<li id="UDPHS_DMACONTROL3__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UDPHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL3__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL3__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL3__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL3__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL3__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL3__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMASTATUS3">UDPHS UDPHS DMA Channel Status Register (channel = 3)</h4>
<p><strong>Name</strong>: UDPHS_DMASTATUS3</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A433C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMASTATUS3__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMASTATUS3__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS3__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS3__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS3__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS3__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS3__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMASTATUS3__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS3__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS3__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS3__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the BUFF_COUNT downcount reach zero.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS3__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS3__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMANXTDSC4">UDPHS UDPHS DMA Next Descriptor Address Register (channel = 4)</h4>
<p><strong>Name</strong>: UDPHS_DMANXTDSC4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4340</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC4__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC4__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC4__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC4__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMANXTDSC4__NXT_DSC_ADD">
<strong>NXT_DSC_ADD</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMAADDRESS4">UDPHS UDPHS DMA Channel Address Register (channel = 4)</h4>
<p><strong>Name</strong>: UDPHS_DMAADDRESS4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4344</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS4__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS4__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS4__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS4__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMAADDRESS4__BUFF_ADD">
<strong>BUFF_ADD</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMACONTROL4">UDPHS UDPHS DMA Channel Control Register (channel = 4)</h4>
<p><strong>Name</strong>: UDPHS_DMACONTROL4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4348</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMACONTROL4__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMACONTROL4__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_DMACONTROL4__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL4__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL4__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL4__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL4__END_B_EN" title="End of Buffer Enable (Control)">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL4__END_TR_EN" title="End of Transfer Enable (Control)">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL4__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable (Command)">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL4__CHANN_ENB" title="">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMACONTROL4__CHANN_ENB">
<strong>CHANN_ENB</strong>
</li>
<p>-</p>
<li id="UDPHS_DMACONTROL4__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable (Command)</li>
<p>-</p>
<li id="UDPHS_DMACONTROL4__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UDPHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL4__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL4__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL4__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL4__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL4__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL4__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMASTATUS4">UDPHS UDPHS DMA Channel Status Register (channel = 4)</h4>
<p><strong>Name</strong>: UDPHS_DMASTATUS4</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A434C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMASTATUS4__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMASTATUS4__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS4__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS4__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS4__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS4__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS4__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMASTATUS4__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS4__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS4__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS4__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the BUFF_COUNT downcount reach zero.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS4__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS4__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMANXTDSC5">UDPHS UDPHS DMA Next Descriptor Address Register (channel = 5)</h4>
<p><strong>Name</strong>: UDPHS_DMANXTDSC5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4350</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC5__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC5__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC5__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMANXTDSC5__NXT_DSC_ADD" title="">NXT_DSC_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMANXTDSC5__NXT_DSC_ADD">
<strong>NXT_DSC_ADD</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMAADDRESS5">UDPHS UDPHS DMA Channel Address Register (channel = 5)</h4>
<p><strong>Name</strong>: UDPHS_DMAADDRESS5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4354</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS5__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS5__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS5__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMAADDRESS5__BUFF_ADD" title="">BUFF_ADD</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMAADDRESS5__BUFF_ADD">
<strong>BUFF_ADD</strong>
</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMACONTROL5">UDPHS UDPHS DMA Channel Control Register (channel = 5)</h4>
<p><strong>Name</strong>: UDPHS_DMACONTROL5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A4358</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMACONTROL5__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMACONTROL5__BUFF_LENGTH" title="Buffer Byte Length (Write-only)">BUFF_LENGTH</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#UDPHS_DMACONTROL5__BURST_LCK" title="Burst Lock Enable">BURST_LCK</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL5__DESC_LD_IT" title="Descriptor Loaded Interrupt Enable">DESC_LD_IT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL5__END_BUFFIT" title="End of Buffer Interrupt Enable">END_BUFFIT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL5__END_TR_IT" title="End of Transfer Interrupt Enable">END_TR_IT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL5__END_B_EN" title="End of Buffer Enable (Control)">END_B_EN</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL5__END_TR_EN" title="End of Transfer Enable (Control)">END_TR_EN</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL5__LDNXT_DSC" title="Load Next Channel Transfer Descriptor Enable (Command)">LDNXT_DSC</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMACONTROL5__CHANN_ENB" title="">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMACONTROL5__CHANN_ENB">
<strong>CHANN_ENB</strong>
</li>
<p>-</p>
<li id="UDPHS_DMACONTROL5__LDNXT_DSC"><strong>LDNXT_DSC</strong>: Load Next Channel Transfer Descriptor Enable (Command)</li>
<p>-</p>
<li id="UDPHS_DMACONTROL5__END_TR_EN"><strong>END_TR_EN</strong>: End of Transfer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USB end of transfer is ignored.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">UDPHS device can put an end to the current buffer transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL5__END_B_EN"><strong>END_B_EN</strong>: End of Buffer Enable (Control)<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA Buffer End has no impact on USB packet transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL5__END_TR_IT"><strong>END_TR_IT</strong>: End of Transfer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL5__END_BUFFIT"><strong>END_BUFFIT</strong>: End of Buffer Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL5__DESC_LD_IT"><strong>DESC_LD_IT</strong>: Descriptor Loaded Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">an interrupt is generated when a descriptor has been loaded from the bus.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL5__BURST_LCK"><strong>BURST_LCK</strong>: Burst Lock Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA never locks bus access.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.</td></tr></tbody></table></li>
<li id="UDPHS_DMACONTROL5__BUFF_LENGTH"><strong>BUFF_LENGTH</strong>: Buffer Byte Length (Write-only)</li>
<p>-</p>
</ul>
<h4 id="UDPHS_DMASTATUS5">UDPHS UDPHS DMA Channel Status Register (channel = 5)</h4>
<p><strong>Name</strong>: UDPHS_DMASTATUS5</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400A435C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMASTATUS5__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#UDPHS_DMASTATUS5__BUFF_COUNT" title="Buffer Byte Count">BUFF_COUNT</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS5__DESC_LDST" title="Descriptor Loaded Status">DESC_LDST</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS5__END_BF_ST" title="End of Channel Buffer Status">END_BF_ST</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS5__END_TR_ST" title="End of Channel Transfer Status">END_TR_ST</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS5__CHANN_ACT" title="Channel Active Status">CHANN_ACT</a>
</td>
<td colspan="1">
<a href="#UDPHS_DMASTATUS5__CHANN_ENB" title="Channel Enable Status">CHANN_ENB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="UDPHS_DMASTATUS5__CHANN_ENB"><strong>CHANN_ENB</strong>: Channel Enable Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">if set, the DMA channel is currently enabled and transfers data upon request.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS5__CHANN_ACT"><strong>CHANN_ACT</strong>: Channel Active Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">the DMA channel is no longer trying to source the packet data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS5__END_TR_ST"><strong>END_TR_ST</strong>: End of Channel Transfer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS5__END_BF_ST"><strong>END_BF_ST</strong>: End of Channel Buffer Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when the BUFF_COUNT downcount reach zero.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS5__DESC_LDST"><strong>DESC_LDST</strong>: Descriptor Loaded Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">cleared automatically when read by software.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">set by hardware when a descriptor has been loaded from the system bus.</td></tr></tbody></table></li>
<li id="UDPHS_DMASTATUS5__BUFF_COUNT"><strong>BUFF_COUNT</strong>: Buffer Byte Count</li>
<p>-</p>
</ul>
</div>
</div>
</body>
</html>