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<title>SAM3U HSMCI</title>
<link rel="stylesheet" type="text/css" href="css/html.css" media="all" />
</head>
<body id="abstract">
<div id="container">
<div id="content">
<a id="HSMCI"></a>
<h1>SAM3U HSMCI</h1>
<a id="HSMCI__User_Interface"></a>
<h2>High Speed MultiMedia Card Interface (HSMCI) User Interface</h2>
<!--As per 6449H programmer datasheet.-->
<h3>Registers</h3>
<table class="registers">
<caption>Register Mapping</caption>
<thead>
<tr>
<th class="address">Address</th>
<th class="description">Register</th>
<th class="name">Name</th>
<th class="access">Access</th>
<th class="reset">Reset</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="address" id="address_0x40000000">0x40000000</td>
<td class="description">Control Register</td>
<td class="name">
<a href="#HSMCI_CR" title="Control Register" class="one_click_away">HSMCI_CR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x40000004">0x40000004</td>
<td class="description">Mode Register</td>
<td class="name">
<a href="#HSMCI_MR" title="Mode Register" class="one_click_away">HSMCI_MR</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x40000008">0x40000008</td>
<td class="description">Data Timeout Register</td>
<td class="name">
<a href="#HSMCI_DTOR" title="Data Timeout Register" class="one_click_away">HSMCI_DTOR</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x4000000C">0x4000000C</td>
<td class="description">SD/SDIO Card Register</td>
<td class="name">
<a href="#HSMCI_SDCR" title="SD/SDIO Card Register" class="one_click_away">HSMCI_SDCR</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x40000010">0x40000010</td>
<td class="description">Argument Register</td>
<td class="name">
<a href="#HSMCI_ARGR" title="Argument Register" class="one_click_away">HSMCI_ARGR</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x40000014">0x40000014</td>
<td class="description">Command Register</td>
<td class="name">
<a href="#HSMCI_CMDR" title="Command Register" class="one_click_away">HSMCI_CMDR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x40000018">0x40000018</td>
<td class="description">Block Register</td>
<td class="name">
<a href="#HSMCI_BLKR" title="Block Register" class="one_click_away">HSMCI_BLKR</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x4000001C">0x4000001C</td>
<td class="description">Completion Signal Timeout Register</td>
<td class="name">
<a href="#HSMCI_CSTOR" title="Completion Signal Timeout Register" class="one_click_away">HSMCI_CSTOR</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x40000020">0x40000020</td>
<td class="description">Response Register</td>
<td class="name">
<a href="#HSMCI_RSPR" title="Response Register" class="one_click_away">HSMCI_RSPR[4]</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x40000030">0x40000030</td>
<td class="description">Receive Data Register</td>
<td class="name">
<a href="#HSMCI_RDR" title="Receive Data Register" class="one_click_away">HSMCI_RDR</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x40000034">0x40000034</td>
<td class="description">Transmit Data Register</td>
<td class="name">
<a href="#HSMCI_TDR" title="Transmit Data Register" class="one_click_away">HSMCI_TDR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x40000040">0x40000040</td>
<td class="description">Status Register</td>
<td class="name">
<a href="#HSMCI_SR" title="Status Register" class="one_click_away">HSMCI_SR</a>
</td>
<td class="access">read-only</td>
<td class="address">0x0000C0E5</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x40000044">0x40000044</td>
<td class="description">Interrupt Enable Register</td>
<td class="name">
<a href="#HSMCI_IER" title="Interrupt Enable Register" class="one_click_away">HSMCI_IER</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x40000048">0x40000048</td>
<td class="description">Interrupt Disable Register</td>
<td class="name">
<a href="#HSMCI_IDR" title="Interrupt Disable Register" class="one_click_away">HSMCI_IDR</a>
</td>
<td class="access">write-only</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x4000004C">0x4000004C</td>
<td class="description">Interrupt Mask Register</td>
<td class="name">
<a href="#HSMCI_IMR" title="Interrupt Mask Register" class="one_click_away">HSMCI_IMR</a>
</td>
<td class="access">read-only</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x40000050">0x40000050</td>
<td class="description">DMA Configuration Register</td>
<td class="name">
<a href="#HSMCI_DMA" title="DMA Configuration Register" class="one_click_away">HSMCI_DMA</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x40000054">0x40000054</td>
<td class="description">Configuration Register</td>
<td class="name">
<a href="#HSMCI_CFG" title="Configuration Register" class="one_click_away">HSMCI_CFG</a>
</td>
<td class="access">read-write</td>
<td class="address">0x00000000</td>
</tr>
<tr class="even">
<td class="address" id="address_0x400000E4">0x400000E4</td>
<td class="description">Write Protection Mode Register</td>
<td class="name">
<a href="#HSMCI_WPMR" title="Write Protection Mode Register" class="one_click_away">HSMCI_WPMR</a>
</td>
<td class="access">read-write</td>
<td class="address">-</td>
</tr>
<tr class="odd">
<td class="address" id="address_0x400000E8">0x400000E8</td>
<td class="description">Write Protection Status Register</td>
<td class="name">
<a href="#HSMCI_WPSR" title="Write Protection Status Register" class="one_click_away">HSMCI_WPSR</a>
</td>
<td class="access">read-only</td>
<td class="address">-</td>
</tr>
<tr class="even">
<td class="address" id="address_0x40000200">0x40000200</td>
<td class="description">FIFO Memory Aperture0</td>
<td class="name">
<a href="#HSMCI_FIFO" title="FIFO Memory Aperture0" class="one_click_away">HSMCI_FIFO[256]</a>
</td>
<td class="access">read-write</td>
<td class="address">0x0</td>
</tr>
</tbody>
</table>
<h3>Register Fields</h3>
<h4 id="HSMCI_CR">HSMCI Control Register</h4>
<p><strong>Name</strong>: HSMCI_CR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x40000000</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#HSMCI_CR__SWRST" title="Software Reset">SWRST</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_CR__PWSDIS" title="Power Save Mode Disable">PWSDIS</a>
</td>
<td colspan="1">
<a href="#HSMCI_CR__PWSEN" title="Power Save Mode Enable">PWSEN</a>
</td>
<td colspan="1">
<a href="#HSMCI_CR__MCIDIS" title="Multi-Media Interface Disable">MCIDIS</a>
</td>
<td colspan="1">
<a href="#HSMCI_CR__MCIEN" title="Multi-Media Interface Enable">MCIEN</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_CR__MCIEN"><strong>MCIEN</strong>: Multi-Media Interface Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the Multi-Media Interface if MCDIS is 0.</td></tr></tbody></table></li>
<li id="HSMCI_CR__MCIDIS"><strong>MCIDIS</strong>: Multi-Media Interface Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the Multi-Media Interface.</td></tr></tbody></table></li>
<li id="HSMCI_CR__PWSEN"><strong>PWSEN</strong>: Power Save Mode Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the Power Saving Mode if PWSDIS is 0.</td></tr></tbody></table></li>
<li id="HSMCI_CR__PWSDIS"><strong>PWSDIS</strong>: Power Save Mode Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the Power Saving Mode.</td></tr></tbody></table></li>
<li id="HSMCI_CR__SWRST"><strong>SWRST</strong>: Software Reset<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Resets the HSMCI. A software triggered hardware reset of the HSMCI interface is performed.</td></tr></tbody></table></li>
</ul>
<h4 id="HSMCI_MR">HSMCI Mode Register</h4>
<p><strong>Name</strong>: HSMCI_MR</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x40000004</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="1">
<a href="#HSMCI_MR__PADV" title="Padding Value">PADV</a>
</td>
<td colspan="1">
<a href="#HSMCI_MR__FBYTE" title="Force Byte Transfer">FBYTE</a>
</td>
<td colspan="1">
<a href="#HSMCI_MR__WRPROOF" title="">WRPROOF</a>
</td>
<td colspan="1">
<a href="#HSMCI_MR__RDPROOF" title="">RDPROOF</a>
</td>
<td colspan="3">
<a href="#HSMCI_MR__PWSDIV" title="Power Saving Divider">PWSDIV</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_MR__CLKDIV" title="Clock Divider">CLKDIV</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_MR__CLKDIV"><strong>CLKDIV</strong>: Clock Divider</li>
<p>-</p>
<li id="HSMCI_MR__PWSDIV"><strong>PWSDIV</strong>: Power Saving Divider</li>
<p>-</p>
<li id="HSMCI_MR__RDPROOF">
<strong>RDPROOF</strong>
<table class="values">
<thead>
<tr>
<th>Value</th>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="value">0</td>
<td class="name">-</td>
<td class="description">Disables Read Proof.</td>
</tr>
<tr class="even">
<td class="value">1</td>
<td class="name">-</td>
<td class="description">Enables Read Proof.</td>
</tr>
</tbody>
</table>
</li>
<li id="HSMCI_MR__WRPROOF">
<strong>WRPROOF</strong>
<table class="values">
<thead>
<tr>
<th>Value</th>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td class="value">0</td>
<td class="name">-</td>
<td class="description">Disables Write Proof.</td>
</tr>
<tr class="even">
<td class="value">1</td>
<td class="name">-</td>
<td class="description">Enables Write Proof.</td>
</tr>
</tbody>
</table>
</li>
<li id="HSMCI_MR__FBYTE"><strong>FBYTE</strong>: Force Byte Transfer<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Disables Force Byte Transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables Force Byte Transfer.</td></tr></tbody></table></li>
<li id="HSMCI_MR__PADV"><strong>PADV</strong>: Padding Value<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">0x00 value is used when padding data in write transfer.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">0xFF value is used when padding data in write transfer.</td></tr></tbody></table></li>
</ul>
<h4 id="HSMCI_DTOR">HSMCI Data Timeout Register</h4>
<p><strong>Name</strong>: HSMCI_DTOR</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x40000008</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="3">
<a href="#HSMCI_DTOR__DTOMUL" title="Data Timeout Multiplier">DTOMUL</a>
</td>
<td colspan="4">
<a href="#HSMCI_DTOR__DTOCYC" title="Data Timeout Cycle Number">DTOCYC</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_DTOR__DTOCYC"><strong>DTOCYC</strong>: Data Timeout Cycle Number</li>
<p>-</p>
<li id="HSMCI_DTOR__DTOMUL"><strong>DTOMUL</strong>: Data Timeout Multiplier<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">1</td><td class="description">DTOCYC</td></tr><tr class="even"><td class="value">0x1</td><td class="name">16</td><td class="description">DTOCYC x 16</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">128</td><td class="description">DTOCYC x 128</td></tr><tr class="even"><td class="value">0x3</td><td class="name">256</td><td class="description">DTOCYC x 256</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">1024</td><td class="description">DTOCYC x 1024</td></tr><tr class="even"><td class="value">0x5</td><td class="name">4096</td><td class="description">DTOCYC x 4096</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">65536</td><td class="description">DTOCYC x 65536</td></tr><tr class="even"><td class="value">0x7</td><td class="name">1048576</td><td class="description">DTOCYC x 1048576</td></tr></tbody></table></li>
</ul>
<h4 id="HSMCI_SDCR">HSMCI SD/SDIO Card Register</h4>
<p><strong>Name</strong>: HSMCI_SDCR</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x4000000C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#HSMCI_SDCR__SDCBUS" title="SDCard/SDIO Bus Width">SDCBUS</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#HSMCI_SDCR__SDCSEL" title="SDCard/SDIO Slot">SDCSEL</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_SDCR__SDCSEL"><strong>SDCSEL</strong>: SDCard/SDIO Slot<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">SLOTA</td><td class="description">Slot A is selected.</td></tr><tr class="even"><td class="value">0x1</td><td class="name">SLOTB</td><td class="description">-</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">SLOTC</td><td class="description">-</td></tr><tr class="even"><td class="value">0x3</td><td class="name">SLOTD</td><td class="description">-</td></tr></tbody></table></li>
<li id="HSMCI_SDCR__SDCBUS"><strong>SDCBUS</strong>: SDCard/SDIO Bus Width<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">1</td><td class="description">1 bit</td></tr><tr class="even"><td class="value">0x2</td><td class="name">4</td><td class="description">4 bit</td></tr><tr class="odd"><td class="value">0x3</td><td class="name">8</td><td class="description">8 bit</td></tr></tbody></table></li>
</ul>
<h4 id="HSMCI_ARGR">HSMCI Argument Register</h4>
<p><strong>Name</strong>: HSMCI_ARGR</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x40000010</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_ARGR__ARG" title="Command Argument">ARG</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_ARGR__ARG" title="Command Argument">ARG</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_ARGR__ARG" title="Command Argument">ARG</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_ARGR__ARG" title="Command Argument">ARG</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_ARGR__ARG"><strong>ARG</strong>: Command Argument</li>
<p>-</p>
</ul>
<h4 id="HSMCI_CMDR">HSMCI Command Register</h4>
<p><strong>Name</strong>: HSMCI_CMDR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x40000014</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_CMDR__BOOT_ACK" title="Boot Operation Acknowledge.">BOOT_ACK</a>
</td>
<td colspan="1">
<a href="#HSMCI_CMDR__ATACS" title="ATA with Command Completion Signal">ATACS</a>
</td>
<td colspan="2">
<a href="#HSMCI_CMDR__IOSPCMD" title="SDIO Special Command">IOSPCMD</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="3">
<a href="#HSMCI_CMDR__TRTYP" title="Transfer Type">TRTYP</a>
</td>
<td colspan="1">
<a href="#HSMCI_CMDR__TRDIR" title="Transfer Direction">TRDIR</a>
</td>
<td colspan="2">
<a href="#HSMCI_CMDR__TRCMD" title="Transfer Command">TRCMD</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_CMDR__MAXLAT" title="Max Latency for Command to Response">MAXLAT</a>
</td>
<td colspan="1">
<a href="#HSMCI_CMDR__OPDCMD" title="Open Drain Command">OPDCMD</a>
</td>
<td colspan="3">
<a href="#HSMCI_CMDR__SPCMD" title="Special Command">SPCMD</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="2">
<a href="#HSMCI_CMDR__RSPTYP" title="Response Type">RSPTYP</a>
</td>
<td colspan="6">
<a href="#HSMCI_CMDR__CMDNB" title="Command Number">CMDNB</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_CMDR__CMDNB"><strong>CMDNB</strong>: Command Number</li>
<p>-</p>
<li id="HSMCI_CMDR__RSPTYP"><strong>RSPTYP</strong>: Response Type<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">NORESP</td><td class="description">No response.</td></tr><tr class="even"><td class="value">0x1</td><td class="name">48_BIT</td><td class="description">48-bit response.</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">136_BIT</td><td class="description">136-bit response.</td></tr><tr class="even"><td class="value">0x3</td><td class="name">R1B</td><td class="description">R1b response type</td></tr></tbody></table></li>
<li id="HSMCI_CMDR__SPCMD"><strong>SPCMD</strong>: Special Command<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">STD</td><td class="description">Not a special CMD.</td></tr><tr class="even"><td class="value">0x1</td><td class="name">INIT</td><td class="description">Initialization CMD: 74 clock cycles for initialization sequence.</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">SYNC</td><td class="description">Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command.</td></tr><tr class="even"><td class="value">0x3</td><td class="name">CE_ATA</td><td class="description">CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line.</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">IT_CMD</td><td class="description">Interrupt command: Corresponds to the Interrupt Mode (CMD40).</td></tr><tr class="even"><td class="value">0x5</td><td class="name">IT_RESP</td><td class="description">Interrupt response: Corresponds to the Interrupt Mode (CMD40).</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">BOR</td><td class="description">Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly.</td></tr><tr class="even"><td class="value">0x7</td><td class="name">EBO</td><td class="description">End Boot Operation. This command allows the host processor to terminate the boot operation mode.</td></tr></tbody></table></li>
<li id="HSMCI_CMDR__OPDCMD"><strong>OPDCMD</strong>: Open Drain Command<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">PUSHPULL</td><td class="description">Push pull command.</td></tr><tr class="even"><td class="value">1</td><td class="name">OPENDRAIN</td><td class="description">Open drain command.</td></tr></tbody></table></li>
<li id="HSMCI_CMDR__MAXLAT"><strong>MAXLAT</strong>: Max Latency for Command to Response<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">5</td><td class="description">5-cycle max latency.</td></tr><tr class="even"><td class="value">1</td><td class="name">64</td><td class="description">64-cycle max latency.</td></tr></tbody></table></li>
<li id="HSMCI_CMDR__TRCMD"><strong>TRCMD</strong>: Transfer Command<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">NO_DATA</td><td class="description">No data transfer</td></tr><tr class="even"><td class="value">0x1</td><td class="name">START_DATA</td><td class="description">Start data transfer</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">STOP_DATA</td><td class="description">Stop data transfer</td></tr></tbody></table></li>
<li id="HSMCI_CMDR__TRDIR"><strong>TRDIR</strong>: Transfer Direction<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">WRITE</td><td class="description">Write.</td></tr><tr class="even"><td class="value">1</td><td class="name">READ</td><td class="description">Read.</td></tr></tbody></table></li>
<li id="HSMCI_CMDR__TRTYP"><strong>TRTYP</strong>: Transfer Type<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">SINGLE</td><td class="description">MMC/SDCard Single Block</td></tr><tr class="even"><td class="value">0x1</td><td class="name">MULTIPLE</td><td class="description">MMC/SDCard Multiple Block</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">STREAM</td><td class="description">MMC Stream</td></tr><tr class="even"><td class="value">0x4</td><td class="name">BYTE</td><td class="description">SDIO Byte</td></tr><tr class="odd"><td class="value">0x5</td><td class="name">BLOCK</td><td class="description">SDIO Block</td></tr></tbody></table></li>
<li id="HSMCI_CMDR__IOSPCMD"><strong>IOSPCMD</strong>: SDIO Special Command<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">STD</td><td class="description">Not an SDIO Special Command</td></tr><tr class="even"><td class="value">0x1</td><td class="name">SUSPEND</td><td class="description">SDIO Suspend Command</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">RESUME</td><td class="description">SDIO Resume Command</td></tr></tbody></table></li>
<li id="HSMCI_CMDR__ATACS"><strong>ATACS</strong>: ATA with Command Completion Signal<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">NORMAL</td><td class="description">Normal operation mode.</td></tr><tr class="even"><td class="value">1</td><td class="name">COMPLETION</td><td class="description">This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR).</td></tr></tbody></table></li>
<li id="HSMCI_CMDR__BOOT_ACK"><strong>BOOT_ACK</strong>: Boot Operation Acknowledge.</li>
<p>-</p>
</ul>
<h4 id="HSMCI_BLKR">HSMCI Block Register</h4>
<p><strong>Name</strong>: HSMCI_BLKR</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x40000018</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_BLKR__BLKLEN" title="Data Block Length">BLKLEN</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_BLKR__BLKLEN" title="Data Block Length">BLKLEN</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_BLKR__BCNT" title="MMC/SDIO Block Count - SDIO Byte Count">BCNT</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_BLKR__BCNT" title="MMC/SDIO Block Count - SDIO Byte Count">BCNT</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_BLKR__BCNT"><strong>BCNT</strong>: MMC/SDIO Block Count - SDIO Byte Count<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">MULTIPLE</td><td class="description">MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer.</td></tr><tr class="even"><td class="value">0x4</td><td class="name">BYTE</td><td class="description">SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden.</td></tr><tr class="odd"><td class="value">0x5</td><td class="name">BLOCK</td><td class="description">SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden.</td></tr></tbody></table></li>
<li id="HSMCI_BLKR__BLKLEN"><strong>BLKLEN</strong>: Data Block Length</li>
<p>-</p>
</ul>
<h4 id="HSMCI_CSTOR">HSMCI Completion Signal Timeout Register</h4>
<p><strong>Name</strong>: HSMCI_CSTOR</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x4000001C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td colspan="3">
<a href="#HSMCI_CSTOR__CSTOMUL" title="Completion Signal Timeout Multiplier">CSTOMUL</a>
</td>
<td colspan="4">
<a href="#HSMCI_CSTOR__CSTOCYC" title="Completion Signal Timeout Cycle Number">CSTOCYC</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_CSTOR__CSTOCYC"><strong>CSTOCYC</strong>: Completion Signal Timeout Cycle Number</li>
<p>-</p>
<li id="HSMCI_CSTOR__CSTOMUL"><strong>CSTOMUL</strong>: Completion Signal Timeout Multiplier<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">1</td><td class="description">CSTOCYC x 1</td></tr><tr class="even"><td class="value">0x1</td><td class="name">16</td><td class="description">CSTOCYC x 16</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">128</td><td class="description">CSTOCYC x 128</td></tr><tr class="even"><td class="value">0x3</td><td class="name">256</td><td class="description">CSTOCYC x 256</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">1024</td><td class="description">CSTOCYC x 1024</td></tr><tr class="even"><td class="value">0x5</td><td class="name">4096</td><td class="description">CSTOCYC x 4096</td></tr><tr class="odd"><td class="value">0x6</td><td class="name">65536</td><td class="description">CSTOCYC x 65536</td></tr><tr class="even"><td class="value">0x7</td><td class="name">1048576</td><td class="description">CSTOCYC x 1048576</td></tr></tbody></table></li>
</ul>
<h4 id="HSMCI_RSPR">HSMCI Response Register</h4>
<p><strong>Name</strong>: HSMCI_RSPR[0:3]</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x40000020</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_RSPR__RSP" title="Response">RSP</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_RSPR__RSP" title="Response">RSP</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_RSPR__RSP" title="Response">RSP</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_RSPR__RSP" title="Response">RSP</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_RSPR__RSP"><strong>RSP</strong>: Response</li>
<p>-</p>
</ul>
<h4 id="HSMCI_RDR">HSMCI Receive Data Register</h4>
<p><strong>Name</strong>: HSMCI_RDR</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x40000030</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_RDR__DATA" title="Data to Read">DATA</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_RDR__DATA" title="Data to Read">DATA</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_RDR__DATA" title="Data to Read">DATA</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_RDR__DATA" title="Data to Read">DATA</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_RDR__DATA"><strong>DATA</strong>: Data to Read</li>
<p>-</p>
</ul>
<h4 id="HSMCI_TDR">HSMCI Transmit Data Register</h4>
<p><strong>Name</strong>: HSMCI_TDR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x40000034</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_TDR__DATA" title="Data to Write">DATA</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_TDR__DATA" title="Data to Write">DATA</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_TDR__DATA" title="Data to Write">DATA</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_TDR__DATA" title="Data to Write">DATA</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_TDR__DATA"><strong>DATA</strong>: Data to Write</li>
<p>-</p>
</ul>
<h4 id="HSMCI_SR">HSMCI Status Register</h4>
<p><strong>Name</strong>: HSMCI_SR</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x40000040</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#HSMCI_SR__UNRE" title="Underrun">UNRE</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__OVRE" title="Overrun">OVRE</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__ACKRCVE" title="Boot Operation Acknowledge Error">ACKRCVE</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__ACKRCV" title="Boot Operation Acknowledge Received">ACKRCV</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__XFRDONE" title="Transfer Done flag">XFRDONE</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__FIFOEMPTY" title="FIFO empty flag">FIFOEMPTY</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__DMADONE" title="DMA Transfer done">DMADONE</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__BLKOVRE" title="DMA Block Overrun Error">BLKOVRE</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#HSMCI_SR__CSTOE" title="Completion Signal Time-out Error">CSTOE</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__DTOE" title="Data Time-out Error">DTOE</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__DCRCE" title="Data CRC Error">DCRCE</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__RTOE" title="Response Time-out Error">RTOE</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__RENDE" title="Response End Bit Error">RENDE</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__RCRCE" title="Response CRC Error">RCRCE</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__RDIRE" title="Response Direction Error">RDIRE</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__RINDE" title="Response Index Error">RINDE</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_SR__CSRCV" title="CE-ATA Completion Signal Received">CSRCV</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__SDIOWAIT" title="SDIO Read Wait Operation Status">SDIOWAIT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_SR__MCI_SDIOIRQA">MCI_SDIOIRQA</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_SR__NOTBUSY" title="HSMCI Not Busy">NOTBUSY</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__DTIP" title="Data Transfer in Progress">DTIP</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__BLKE" title="Data Block Ended">BLKE</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__TXRDY" title="Transmit Ready">TXRDY</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__RXRDY" title="Receiver Ready">RXRDY</a>
</td>
<td colspan="1">
<a href="#HSMCI_SR__CMDRDY" title="Command Ready">CMDRDY</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_SR__CMDRDY"><strong>CMDRDY</strong>: Command Ready<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">A command is in progress.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The last command has been sent. Cleared when writing in the HSMCI_CMDR.</td></tr></tbody></table></li>
<li id="HSMCI_SR__RXRDY"><strong>RXRDY</strong>: Receiver Ready<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Data has not yet been received since the last read of HSMCI_RDR.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Data has been received since the last read of HSMCI_RDR.</td></tr></tbody></table></li>
<li id="HSMCI_SR__TXRDY"><strong>TXRDY</strong>: Transmit Ready<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The last data written in HSMCI_TDR has not yet been transferred in the Shift Register.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The last data written in HSMCI_TDR has been transferred in the Shift Register.</td></tr></tbody></table></li>
<li id="HSMCI_SR__BLKE"><strong>BLKE</strong>: Data Block Ended<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">A data block transfer is not yet finished. Cleared when reading the HSMCI_SR.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">A data block transfer has ended, including the CRC16 Status transmission. the flag is set for each transmitted CRC Status.</td></tr></tbody></table></li>
<li id="HSMCI_SR__DTIP"><strong>DTIP</strong>: Data Transfer in Progress<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No data transfer in progress.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The current data transfer is still in progress, including CRC16 calculation. Cleared at the end of the CRC16 calculation.</td></tr></tbody></table></li>
<li id="HSMCI_SR__NOTBUSY"><strong>NOTBUSY</strong>: HSMCI Not Busy<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The HSMCI is not ready for new data transfer. Cleared at the end of the card response.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data receive buffer of the card.</td></tr></tbody></table></li>
<li id="HSMCI_SR__MCI_SDIOIRQA">
<strong>MCI_SDIOIRQA</strong>
</li>
<p>-</p>
<li id="HSMCI_SR__SDIOWAIT"><strong>SDIOWAIT</strong>: SDIO Read Wait Operation Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Normal Bus operation.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The data bus has entered IO wait state.</td></tr></tbody></table></li>
<li id="HSMCI_SR__CSRCV"><strong>CSRCV</strong>: CE-ATA Completion Signal Received<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No completion signal received since last status read operation.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The device has issued a command completion signal on the command line. Cleared by reading in the HSMCI_SR register.</td></tr></tbody></table></li>
<li id="HSMCI_SR__RINDE"><strong>RINDE</strong>: Response Index Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No error.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">A mismatch is detected between the command index sent and the response index received. Cleared when writing in the HSMCI_CMDR.</td></tr></tbody></table></li>
<li id="HSMCI_SR__RDIRE"><strong>RDIRE</strong>: Response Direction Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No error.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The direction bit from card to host in the response has not been detected.</td></tr></tbody></table></li>
<li id="HSMCI_SR__RCRCE"><strong>RCRCE</strong>: Response CRC Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No error.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">A CRC7 error has been detected in the response. Cleared when writing in the HSMCI_CMDR.</td></tr></tbody></table></li>
<li id="HSMCI_SR__RENDE"><strong>RENDE</strong>: Response End Bit Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No error.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The end bit of the response has not been detected. Cleared when writing in the HSMCI_CMDR.</td></tr></tbody></table></li>
<li id="HSMCI_SR__RTOE"><strong>RTOE</strong>: Response Time-out Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No error.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The response time-out set by MAXLAT in the HSMCI_CMDR has been exceeded. Cleared when writing in the HSMCI_CMDR.</td></tr></tbody></table></li>
<li id="HSMCI_SR__DCRCE"><strong>DCRCE</strong>: Data CRC Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No error.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">A CRC16 error has been detected in the last data block. Cleared by reading in the HSMCI_SR register.</td></tr></tbody></table></li>
<li id="HSMCI_SR__DTOE"><strong>DTOE</strong>: Data Time-out Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No error.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded. Cleared by reading in the HSMCI_SR register.</td></tr></tbody></table></li>
<li id="HSMCI_SR__CSTOE"><strong>CSTOE</strong>: Completion Signal Time-out Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No error.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The completion signal time-out set by CSTOCYC and CSTOMUL in HSMCI_CSTOR has been exceeded. Cleared by reading in the HSMCI_SR register. Cleared by reading in the HSMCI_SR register.</td></tr></tbody></table></li>
<li id="HSMCI_SR__BLKOVRE"><strong>BLKOVRE</strong>: DMA Block Overrun Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No error.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">A new block of data is received and the DMA controller has not started to move the current pending block, a block over-run is raised. Cleared by reading in the HSMCI_SR register.</td></tr></tbody></table></li>
<li id="HSMCI_SR__DMADONE"><strong>DMADONE</strong>: DMA Transfer done<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA buffer transfer has not completed since the last read of HSMCI_SR register.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">DMA buffer transfer has completed.</td></tr></tbody></table></li>
<li id="HSMCI_SR__FIFOEMPTY"><strong>FIFOEMPTY</strong>: FIFO empty flag<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">FIFO contains at least one byte.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">FIFO is empty.</td></tr></tbody></table></li>
<li id="HSMCI_SR__XFRDONE"><strong>XFRDONE</strong>: Transfer Done flag<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">A transfer is in progress.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Command register is ready to operate and the data bus is in the idle state.</td></tr></tbody></table></li>
<li id="HSMCI_SR__ACKRCV"><strong>ACKRCV</strong>: Boot Operation Acknowledge Received<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No Boot acknowledge received since the last read of the status register.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">A Boot acknowledge signal has been received. Cleared by reading the HSMCI_SR register.</td></tr></tbody></table></li>
<li id="HSMCI_SR__ACKRCVE"><strong>ACKRCVE</strong>: Boot Operation Acknowledge Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No error</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Corrupted Boot Acknowledge signal received.</td></tr></tbody></table></li>
<li id="HSMCI_SR__OVRE"><strong>OVRE</strong>: Overrun<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No error.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command.</td></tr></tbody></table></li>
<li id="HSMCI_SR__UNRE"><strong>UNRE</strong>: Underrun<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No error.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">At least one 8-bit data has been sent without valid information (not written). Cleared when sending a new data transfer command or when setting FERRCTRL in HSMCI_CFG to 1.</td></tr></tbody></table></li>
</ul>
<h4 id="HSMCI_IER">HSMCI Interrupt Enable Register</h4>
<p><strong>Name</strong>: HSMCI_IER</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x40000044</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#HSMCI_IER__UNRE" title="Underrun Interrupt Enable">UNRE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__OVRE" title="Overrun Interrupt Enable">OVRE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__ACKRCVE" title="Boot Acknowledge Error Interrupt Enable">ACKRCVE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__ACKRCV" title="Boot Acknowledge Interrupt Enable">ACKRCV</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__XFRDONE" title="Transfer Done Interrupt enable">XFRDONE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__FIFOEMPTY" title="FIFO empty Interrupt enable">FIFOEMPTY</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__DMADONE" title="DMA Transfer completed Interrupt Enable">DMADONE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__BLKOVRE" title="DMA Block Overrun Error Interrupt Enable">BLKOVRE</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#HSMCI_IER__CSTOE" title="Completion Signal Timeout Error Interrupt Enable">CSTOE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__DTOE" title="Data Time-out Error Interrupt Enable">DTOE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__DCRCE" title="Data CRC Error Interrupt Enable">DCRCE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__RTOE" title="Response Time-out Error Interrupt Enable">RTOE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__RENDE" title="Response End Bit Error Interrupt Enable">RENDE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__RCRCE" title="Response CRC Error Interrupt Enable">RCRCE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__RDIRE" title="Response Direction Error Interrupt Enable">RDIRE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__RINDE" title="Response Index Error Interrupt Enable">RINDE</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_IER__CSRCV" title="Completion Signal Received Interrupt Enable">CSRCV</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__SDIOWAIT" title="SDIO Read Wait Operation Status Interrupt Enable">SDIOWAIT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_IER__MCI_SDIOIRQA">MCI_SDIOIRQA</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_IER__NOTBUSY" title="Data Not Busy Interrupt Enable">NOTBUSY</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__DTIP" title="Data Transfer in Progress Interrupt Enable">DTIP</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__BLKE" title="Data Block Ended Interrupt Enable">BLKE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__TXRDY" title="Transmit Ready Interrupt Enable">TXRDY</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__RXRDY" title="Receiver Ready Interrupt Enable">RXRDY</a>
</td>
<td colspan="1">
<a href="#HSMCI_IER__CMDRDY" title="Command Ready Interrupt Enable">CMDRDY</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_IER__CMDRDY"><strong>CMDRDY</strong>: Command Ready Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__RXRDY"><strong>RXRDY</strong>: Receiver Ready Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__TXRDY"><strong>TXRDY</strong>: Transmit Ready Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__BLKE"><strong>BLKE</strong>: Data Block Ended Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__DTIP"><strong>DTIP</strong>: Data Transfer in Progress Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__NOTBUSY"><strong>NOTBUSY</strong>: Data Not Busy Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__MCI_SDIOIRQA">
<strong>MCI_SDIOIRQA</strong>
</li>
<p>-</p>
<li id="HSMCI_IER__SDIOWAIT"><strong>SDIOWAIT</strong>: SDIO Read Wait Operation Status Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__CSRCV"><strong>CSRCV</strong>: Completion Signal Received Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__RINDE"><strong>RINDE</strong>: Response Index Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__RDIRE"><strong>RDIRE</strong>: Response Direction Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__RCRCE"><strong>RCRCE</strong>: Response CRC Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__RENDE"><strong>RENDE</strong>: Response End Bit Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__RTOE"><strong>RTOE</strong>: Response Time-out Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__DCRCE"><strong>DCRCE</strong>: Data CRC Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__DTOE"><strong>DTOE</strong>: Data Time-out Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__CSTOE"><strong>CSTOE</strong>: Completion Signal Timeout Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__BLKOVRE"><strong>BLKOVRE</strong>: DMA Block Overrun Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__DMADONE"><strong>DMADONE</strong>: DMA Transfer completed Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__FIFOEMPTY"><strong>FIFOEMPTY</strong>: FIFO empty Interrupt enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__XFRDONE"><strong>XFRDONE</strong>: Transfer Done Interrupt enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__ACKRCV"><strong>ACKRCV</strong>: Boot Acknowledge Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__ACKRCVE"><strong>ACKRCVE</strong>: Boot Acknowledge Error Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__OVRE"><strong>OVRE</strong>: Overrun Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IER__UNRE"><strong>UNRE</strong>: Underrun Interrupt Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the corresponding interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="HSMCI_IDR">HSMCI Interrupt Disable Register</h4>
<p><strong>Name</strong>: HSMCI_IDR</p>
<p><strong>Access</strong>: write-only</p>
<p><strong>Address</strong>: 0x40000048</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#HSMCI_IDR__UNRE" title="Underrun Interrupt Disable">UNRE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__OVRE" title="Overrun Interrupt Disable">OVRE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__ACKRCVE" title="Boot Acknowledge Error Interrupt Disable">ACKRCVE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__ACKRCV" title="Boot Acknowledge Interrupt Disable">ACKRCV</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__XFRDONE" title="Transfer Done Interrupt Disable">XFRDONE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__FIFOEMPTY" title="FIFO empty Interrupt Disable">FIFOEMPTY</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__DMADONE" title="DMA Transfer completed Interrupt Disable">DMADONE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__BLKOVRE" title="DMA Block Overrun Error Interrupt Disable">BLKOVRE</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#HSMCI_IDR__CSTOE" title="Completion Signal Time out Error Interrupt Disable">CSTOE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__DTOE" title="Data Time-out Error Interrupt Disable">DTOE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__DCRCE" title="Data CRC Error Interrupt Disable">DCRCE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__RTOE" title="Response Time-out Error Interrupt Disable">RTOE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__RENDE" title="Response End Bit Error Interrupt Disable">RENDE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__RCRCE" title="Response CRC Error Interrupt Disable">RCRCE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__RDIRE" title="Response Direction Error Interrupt Disable">RDIRE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__RINDE" title="Response Index Error Interrupt Disable">RINDE</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_IDR__CSRCV" title="Completion Signal received interrupt Disable">CSRCV</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__SDIOWAIT" title="SDIO Read Wait Operation Status Interrupt Disable">SDIOWAIT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_IDR__MCI_SDIOIRQA">MCI_SDIOIRQA</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_IDR__NOTBUSY" title="Data Not Busy Interrupt Disable">NOTBUSY</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__DTIP" title="Data Transfer in Progress Interrupt Disable">DTIP</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__BLKE" title="Data Block Ended Interrupt Disable">BLKE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__TXRDY" title="Transmit Ready Interrupt Disable">TXRDY</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__RXRDY" title="Receiver Ready Interrupt Disable">RXRDY</a>
</td>
<td colspan="1">
<a href="#HSMCI_IDR__CMDRDY" title="Command Ready Interrupt Disable">CMDRDY</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_IDR__CMDRDY"><strong>CMDRDY</strong>: Command Ready Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__RXRDY"><strong>RXRDY</strong>: Receiver Ready Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__TXRDY"><strong>TXRDY</strong>: Transmit Ready Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__BLKE"><strong>BLKE</strong>: Data Block Ended Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__DTIP"><strong>DTIP</strong>: Data Transfer in Progress Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__NOTBUSY"><strong>NOTBUSY</strong>: Data Not Busy Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__MCI_SDIOIRQA">
<strong>MCI_SDIOIRQA</strong>
</li>
<p>-</p>
<li id="HSMCI_IDR__SDIOWAIT"><strong>SDIOWAIT</strong>: SDIO Read Wait Operation Status Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__CSRCV"><strong>CSRCV</strong>: Completion Signal received interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__RINDE"><strong>RINDE</strong>: Response Index Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__RDIRE"><strong>RDIRE</strong>: Response Direction Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__RCRCE"><strong>RCRCE</strong>: Response CRC Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__RENDE"><strong>RENDE</strong>: Response End Bit Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__RTOE"><strong>RTOE</strong>: Response Time-out Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__DCRCE"><strong>DCRCE</strong>: Data CRC Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__DTOE"><strong>DTOE</strong>: Data Time-out Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__CSTOE"><strong>CSTOE</strong>: Completion Signal Time out Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__BLKOVRE"><strong>BLKOVRE</strong>: DMA Block Overrun Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__DMADONE"><strong>DMADONE</strong>: DMA Transfer completed Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__FIFOEMPTY"><strong>FIFOEMPTY</strong>: FIFO empty Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__XFRDONE"><strong>XFRDONE</strong>: Transfer Done Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__ACKRCV"><strong>ACKRCV</strong>: Boot Acknowledge Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__ACKRCVE"><strong>ACKRCVE</strong>: Boot Acknowledge Error Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__OVRE"><strong>OVRE</strong>: Overrun Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
<li id="HSMCI_IDR__UNRE"><strong>UNRE</strong>: Underrun Interrupt Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the corresponding interrupt.</td></tr></tbody></table></li>
</ul>
<h4 id="HSMCI_IMR">HSMCI Interrupt Mask Register</h4>
<p><strong>Name</strong>: HSMCI_IMR</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x4000004C</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#HSMCI_IMR__UNRE" title="Underrun Interrupt Mask">UNRE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__OVRE" title="Overrun Interrupt Mask">OVRE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__ACKRCVE" title="Boot Operation Acknowledge Error Interrupt Mask">ACKRCVE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__ACKRCV" title="Boot Operation Acknowledge Received Interrupt Mask">ACKRCV</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__XFRDONE" title="Transfer Done Interrupt Mask">XFRDONE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__FIFOEMPTY" title="FIFO Empty Interrupt Mask">FIFOEMPTY</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__DMADONE" title="DMA Transfer Completed Interrupt Mask">DMADONE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__BLKOVRE" title="DMA Block Overrun Error Interrupt Mask">BLKOVRE</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="1">
<a href="#HSMCI_IMR__CSTOE" title="Completion Signal Time-out Error Interrupt Mask">CSTOE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__DTOE" title="Data Time-out Error Interrupt Mask">DTOE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__DCRCE" title="Data CRC Error Interrupt Mask">DCRCE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__RTOE" title="Response Time-out Error Interrupt Mask">RTOE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__RENDE" title="Response End Bit Error Interrupt Mask">RENDE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__RCRCE" title="Response CRC Error Interrupt Mask">RCRCE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__RDIRE" title="Response Direction Error Interrupt Mask">RDIRE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__RINDE" title="Response Index Error Interrupt Mask">RINDE</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_IMR__CSRCV" title="Completion Signal Received Interrupt Mask">CSRCV</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__SDIOWAIT" title="SDIO Read Wait Operation Status Interrupt Mask">SDIOWAIT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_IMR__MCI_SDIOIRQA">MCI_SDIOIRQA</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_IMR__NOTBUSY" title="Data Not Busy Interrupt Mask">NOTBUSY</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__DTIP" title="Data Transfer in Progress Interrupt Mask">DTIP</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__BLKE" title="Data Block Ended Interrupt Mask">BLKE</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__TXRDY" title="Transmit Ready Interrupt Mask">TXRDY</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__RXRDY" title="Receiver Ready Interrupt Mask">RXRDY</a>
</td>
<td colspan="1">
<a href="#HSMCI_IMR__CMDRDY" title="Command Ready Interrupt Mask">CMDRDY</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_IMR__CMDRDY"><strong>CMDRDY</strong>: Command Ready Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__RXRDY"><strong>RXRDY</strong>: Receiver Ready Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__TXRDY"><strong>TXRDY</strong>: Transmit Ready Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__BLKE"><strong>BLKE</strong>: Data Block Ended Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__DTIP"><strong>DTIP</strong>: Data Transfer in Progress Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__NOTBUSY"><strong>NOTBUSY</strong>: Data Not Busy Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__MCI_SDIOIRQA">
<strong>MCI_SDIOIRQA</strong>
</li>
<p>-</p>
<li id="HSMCI_IMR__SDIOWAIT"><strong>SDIOWAIT</strong>: SDIO Read Wait Operation Status Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__CSRCV"><strong>CSRCV</strong>: Completion Signal Received Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__RINDE"><strong>RINDE</strong>: Response Index Error Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__RDIRE"><strong>RDIRE</strong>: Response Direction Error Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__RCRCE"><strong>RCRCE</strong>: Response CRC Error Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__RENDE"><strong>RENDE</strong>: Response End Bit Error Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__RTOE"><strong>RTOE</strong>: Response Time-out Error Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__DCRCE"><strong>DCRCE</strong>: Data CRC Error Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__DTOE"><strong>DTOE</strong>: Data Time-out Error Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__CSTOE"><strong>CSTOE</strong>: Completion Signal Time-out Error Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__BLKOVRE"><strong>BLKOVRE</strong>: DMA Block Overrun Error Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__DMADONE"><strong>DMADONE</strong>: DMA Transfer Completed Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__FIFOEMPTY"><strong>FIFOEMPTY</strong>: FIFO Empty Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__XFRDONE"><strong>XFRDONE</strong>: Transfer Done Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__ACKRCV"><strong>ACKRCV</strong>: Boot Operation Acknowledge Received Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__ACKRCVE"><strong>ACKRCVE</strong>: Boot Operation Acknowledge Error Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__OVRE"><strong>OVRE</strong>: Overrun Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_IMR__UNRE"><strong>UNRE</strong>: Underrun Interrupt Mask<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The corresponding interrupt is not enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The corresponding interrupt is enabled.</td></tr></tbody></table></li>
</ul>
<h4 id="HSMCI_DMA">HSMCI DMA Configuration Register</h4>
<p><strong>Name</strong>: HSMCI_DMA</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x40000050</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_DMA__ROPT" title="Read Optimization with padding">ROPT</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_DMA__DMAEN" title="DMA Hardware Handshaking Enable">DMAEN</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_DMA__CHKSIZE" title="DMA Channel Read and Write Chunk Size">CHKSIZE</a>
</td>
<td>-</td>
<td>-</td>
<td colspan="2">
<a href="#HSMCI_DMA__OFFSET" title="DMA Write Buffer Offset">OFFSET</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_DMA__OFFSET"><strong>OFFSET</strong>: DMA Write Buffer Offset</li>
<p>-</p>
<li id="HSMCI_DMA__CHKSIZE"><strong>CHKSIZE</strong>: DMA Channel Read and Write Chunk Size<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">1</td><td class="description">1 data available</td></tr><tr class="even"><td class="value">1</td><td class="name">4</td><td class="description">4 data available</td></tr></tbody></table></li>
<li id="HSMCI_DMA__DMAEN"><strong>DMAEN</strong>: DMA Hardware Handshaking Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">DMA interface is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">DMA Interface is enabled.</td></tr></tbody></table></li>
<li id="HSMCI_DMA__ROPT"><strong>ROPT</strong>: Read Optimization with padding<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">BLKLEN bytes are moved from the Memory Card to the system memory, two DMA descriptors are used when the trans-fer size is not a multiple of 4.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Ceiling(BLKLEN/4) * 4 bytes are moved from the Memory Card to the system memory, only one DMA descriptor is used.</td></tr></tbody></table></li>
</ul>
<h4 id="HSMCI_CFG">HSMCI Configuration Register</h4>
<p><strong>Name</strong>: HSMCI_CFG</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x40000054</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_CFG__LSYNC" title="Synchronize on the last block">LSYNC</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_CFG__HSMODE" title="High Speed Mode">HSMODE</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_CFG__FERRCTRL" title="Flow Error flag reset control mode">FERRCTRL</a>
</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_CFG__FIFOMODE" title="HSMCI Internal FIFO control mode">FIFOMODE</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_CFG__FIFOMODE"><strong>FIFOMODE</strong>: HSMCI Internal FIFO control mode</li>
<p>-</p>
<li id="HSMCI_CFG__FERRCTRL"><strong>FERRCTRL</strong>: Flow Error flag reset control mode<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">When an underflow/overflow condition flag is set, a read status resets the flag.</td></tr></tbody></table></li>
<li id="HSMCI_CFG__HSMODE"><strong>HSMODE</strong>: High Speed Mode<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Default bus timing mode.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">If set to one, the host controller outputs command line and data lines on the rising edge of the card clock. The Host driver shall check the high speed support in the card registers.</td></tr></tbody></table></li>
<li id="HSMCI_CFG__LSYNC"><strong>LSYNC</strong>: Synchronize on the last block<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The pending command is sent at the end of the current data block.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The pending command is sent at the end of the block transfer when the transfer length is not infinite. (block count shall be different from zero)</td></tr></tbody></table></li>
</ul>
<h4 id="HSMCI_WPMR">HSMCI Write Protection Mode Register</h4>
<p><strong>Name</strong>: HSMCI_WPMR</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x400000E4</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_WPMR__WP_KEY" title="Write Protection Key password">WP_KEY</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_WPMR__WP_KEY" title="Write Protection Key password">WP_KEY</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_WPMR__WP_KEY" title="Write Protection Key password">WP_KEY</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="1">
<a href="#HSMCI_WPMR__WP_EN" title="Write Protection Enable">WP_EN</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_WPMR__WP_EN"><strong>WP_EN</strong>: Write Protection Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Disables the Write Protection if WP_KEY corresponds to 0x4D4349 ("MCI' in ASCII).</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the Write Protection if WP_KEY corresponds to 0x4D4349 ("MCI' in ASCII).</td></tr></tbody></table></li>
<li id="HSMCI_WPMR__WP_KEY"><strong>WP_KEY</strong>: Write Protection Key password</li>
<p>-</p>
</ul>
<h4 id="HSMCI_WPSR">HSMCI Write Protection Status Register</h4>
<p><strong>Name</strong>: HSMCI_WPSR</p>
<p><strong>Access</strong>: read-only</p>
<p><strong>Address</strong>: 0x400000E8</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_WPSR__WP_VSRC" title="Write Protection Violation SouRCe">WP_VSRC</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_WPSR__WP_VSRC" title="Write Protection Violation SouRCe">WP_VSRC</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td colspan="4">
<a href="#HSMCI_WPSR__WP_VS" title="Write Protection Violation Status">WP_VS</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_WPSR__WP_VS"><strong>WP_VS</strong>: Write Protection Violation Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">NONE</td><td class="description">No Write Protection Violation occurred since the last read of this register (WP_SR)</td></tr><tr class="even"><td class="value">0x1</td><td class="name">WRITE</td><td class="description">Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.)</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">RESET</td><td class="description">Software reset had been performed while Write Protection was enabled (since the last read).</td></tr><tr class="even"><td class="value">0x3</td><td class="name">BOTH</td><td class="description">Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read.</td></tr></tbody></table></li>
<li id="HSMCI_WPSR__WP_VSRC"><strong>WP_VSRC</strong>: Write Protection Violation SouRCe</li>
<p>-</p>
</ul>
<h4 id="HSMCI_FIFO">HSMCI FIFO Memory Aperture0</h4>
<p><strong>Name</strong>: HSMCI_FIFO[0:255]</p>
<p><strong>Access</strong>: read-write</p>
<p><strong>Address</strong>: 0x40000200</p>
<table class="fields">
<tbody>
<tr class="offsets">
<td>31</td>
<td>30</td>
<td>29</td>
<td>28</td>
<td>27</td>
<td>26</td>
<td>25</td>
<td>24</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_FIFO__DATA" title="Data to Read or Data to Write">DATA</a>
</td>
</tr>
<tr class="offsets">
<td>23</td>
<td>22</td>
<td>21</td>
<td>20</td>
<td>19</td>
<td>18</td>
<td>17</td>
<td>16</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_FIFO__DATA" title="Data to Read or Data to Write">DATA</a>
</td>
</tr>
<tr class="offsets">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>9</td>
<td>8</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_FIFO__DATA" title="Data to Read or Data to Write">DATA</a>
</td>
</tr>
<tr class="offsets">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr class="fields">
<td colspan="8">
<a href="#HSMCI_FIFO__DATA" title="Data to Read or Data to Write">DATA</a>
</td>
</tr>
</tbody>
</table>
<ul class="values">
<li id="HSMCI_FIFO__DATA"><strong>DATA</strong>: Data to Read or Data to Write</li>
<p>-</p>
</ul>
</div>
</div>
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