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| <title>SAM3N USART1</title> |
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| <body id="abstract"> |
| <div id="container"> |
| <div id="content"> |
| <a id="USART1"></a> |
| <h1>SAM3N USART1</h1> |
| <a id="USART1__User_Interface"></a> |
| <h2>Universal Synchronous Asynchronous Receiver Transmitter (USART1) User Interface</h2> |
| <!--As per 6089W programmer datasheet.--> |
| <h3>Registers</h3> |
| <table class="registers"> |
| <caption>Register Mapping</caption> |
| <thead> |
| <tr> |
| <th class="address">Address</th> |
| <th class="description">Register</th> |
| <th class="name">Name</th> |
| <th class="access">Access</th> |
| <th class="reset">Reset</th> |
| </tr> |
| </thead> |
| <tbody> |
| <tr class="odd"> |
| <td class="address" id="address_0x40028000">0x40028000</td> |
| <td class="description">Control Register</td> |
| <td class="name"> |
| <a href="#USART1_CR" title="Control Register" class="one_click_away">USART1_CR</a> |
| </td> |
| <td class="access">write-only</td> |
| <td class="address">-</td> |
| </tr> |
| <tr class="even"> |
| <td class="address" id="address_0x40028004">0x40028004</td> |
| <td class="description">Mode Register</td> |
| <td class="name"> |
| <a href="#USART1_MR" title="Mode Register" class="one_click_away">USART1_MR</a> |
| </td> |
| <td class="access">read-write</td> |
| <td class="address">-</td> |
| </tr> |
| <tr class="odd"> |
| <td class="address" id="address_0x40028008">0x40028008</td> |
| <td class="description">Interrupt Enable Register</td> |
| <td class="name"> |
| <a href="#USART1_IER" title="Interrupt Enable Register" class="one_click_away">USART1_IER</a> |
| </td> |
| <td class="access">write-only</td> |
| <td class="address">-</td> |
| </tr> |
| <tr class="even"> |
| <td class="address" id="address_0x4002800C">0x4002800C</td> |
| <td class="description">Interrupt Disable Register</td> |
| <td class="name"> |
| <a href="#USART1_IDR" title="Interrupt Disable Register" class="one_click_away">USART1_IDR</a> |
| </td> |
| <td class="access">write-only</td> |
| <td class="address">-</td> |
| </tr> |
| <tr class="odd"> |
| <td class="address" id="address_0x40028010">0x40028010</td> |
| <td class="description">Interrupt Mask Register</td> |
| <td class="name"> |
| <a href="#USART1_IMR" title="Interrupt Mask Register" class="one_click_away">USART1_IMR</a> |
| </td> |
| <td class="access">read-only</td> |
| <td class="address">0x00000000</td> |
| </tr> |
| <tr class="even"> |
| <td class="address" id="address_0x40028014">0x40028014</td> |
| <td class="description">Channel Status Register</td> |
| <td class="name"> |
| <a href="#USART1_CSR" title="Channel Status Register" class="one_click_away">USART1_CSR</a> |
| </td> |
| <td class="access">read-only</td> |
| <td class="address">-</td> |
| </tr> |
| <tr class="odd"> |
| <td class="address" id="address_0x40028018">0x40028018</td> |
| <td class="description">Receiver Holding Register</td> |
| <td class="name"> |
| <a href="#USART1_RHR" title="Receiver Holding Register" class="one_click_away">USART1_RHR</a> |
| </td> |
| <td class="access">read-only</td> |
| <td class="address">0x00000000</td> |
| </tr> |
| <tr class="even"> |
| <td class="address" id="address_0x4002801C">0x4002801C</td> |
| <td class="description">Transmitter Holding Register</td> |
| <td class="name"> |
| <a href="#USART1_THR" title="Transmitter Holding Register" class="one_click_away">USART1_THR</a> |
| </td> |
| <td class="access">write-only</td> |
| <td class="address">-</td> |
| </tr> |
| <tr class="odd"> |
| <td class="address" id="address_0x40028020">0x40028020</td> |
| <td class="description">Baud Rate Generator Register</td> |
| <td class="name"> |
| <a href="#USART1_BRGR" title="Baud Rate Generator Register" class="one_click_away">USART1_BRGR</a> |
| </td> |
| <td class="access">read-write</td> |
| <td class="address">0x00000000</td> |
| </tr> |
| <tr class="even"> |
| <td class="address" id="address_0x40028024">0x40028024</td> |
| <td class="description">Receiver Time-out Register</td> |
| <td class="name"> |
| <a href="#USART1_RTOR" title="Receiver Time-out Register" class="one_click_away">USART1_RTOR</a> |
| </td> |
| <td class="access">read-write</td> |
| <td class="address">0x00000000</td> |
| </tr> |
| <tr class="odd"> |
| <td class="address" id="address_0x40028028">0x40028028</td> |
| <td class="description">Transmitter Timeguard Register</td> |
| <td class="name"> |
| <a href="#USART1_TTGR" title="Transmitter Timeguard Register" class="one_click_away">USART1_TTGR</a> |
| </td> |
| <td class="access">read-write</td> |
| <td class="address">0x00000000</td> |
| </tr> |
| <tr class="even"> |
| <td class="address" id="address_0x40028040">0x40028040</td> |
| <td class="description">FI DI Ratio Register</td> |
| <td class="name"> |
| <a href="#USART1_FIDI" title="FI DI Ratio Register" class="one_click_away">USART1_FIDI</a> |
| </td> |
| <td class="access">read-write</td> |
| <td class="address">0x00000174</td> |
| </tr> |
| <tr class="odd"> |
| <td class="address" id="address_0x40028044">0x40028044</td> |
| <td class="description">Number of Errors Register</td> |
| <td class="name"> |
| <a href="#USART1_NER" title="Number of Errors Register" class="one_click_away">USART1_NER</a> |
| </td> |
| <td class="access">read-only</td> |
| <td class="address">-</td> |
| </tr> |
| <tr class="even"> |
| <td class="address" id="address_0x4002804C">0x4002804C</td> |
| <td class="description">IrDA Filter Register</td> |
| <td class="name"> |
| <a href="#USART1_IF" title="IrDA Filter Register" class="one_click_away">USART1_IF</a> |
| </td> |
| <td class="access">read-write</td> |
| <td class="address">0x00000000</td> |
| </tr> |
| <tr class="odd"> |
| <td class="address" id="address_0x400280E4">0x400280E4</td> |
| <td class="description">Write Protect Mode Register</td> |
| <td class="name"> |
| <a href="#USART1_WPMR" title="Write Protect Mode Register" class="one_click_away">USART1_WPMR</a> |
| </td> |
| <td class="access">read-write</td> |
| <td class="address">0x00000000</td> |
| </tr> |
| <tr class="even"> |
| <td class="address" id="address_0x400280E8">0x400280E8</td> |
| <td class="description">Write Protect Status Register</td> |
| <td class="name"> |
| <a href="#USART1_WPSR" title="Write Protect Status Register" class="one_click_away">USART1_WPSR</a> |
| </td> |
| <td class="access">read-only</td> |
| <td class="address">0x00000000</td> |
| </tr> |
| </tbody> |
| </table> |
| <h3>Register Fields</h3> |
| <h4 id="USART1_CR">USART1 Control Register</h4> |
| <p><strong>Name</strong>: USART1_CR</p> |
| <p><strong>Access</strong>: write-only</p> |
| <p><strong>Address</strong>: 0x40028000</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_CR__RTSDIS" title="Request to Send Disable">RTSDIS</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CR__RTSEN" title="Request to Send Enable">RTSEN</a> |
| </td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="1"> |
| <a href="#USART1_CR__RETTO" title="Rearm Time-out">RETTO</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CR__RSTNACK" title="Reset Non Acknowledge">RSTNACK</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CR__RSTIT" title="Reset Iterations">RSTIT</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CR__SENDA" title="Send Address">SENDA</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CR__STTTO" title="Start Time-out">STTTO</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CR__STPBRK" title="Stop Break">STPBRK</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CR__STTBRK" title="Start Break">STTBRK</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CR__RSTSTA" title="Reset Status Bits">RSTSTA</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="1"> |
| <a href="#USART1_CR__TXDIS" title="Transmitter Disable">TXDIS</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CR__TXEN" title="Transmitter Enable">TXEN</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CR__RXDIS" title="Receiver Disable">RXDIS</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CR__RXEN" title="Receiver Enable">RXEN</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CR__RSTTX" title="Reset Transmitter">RSTTX</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CR__RSTRX" title="Reset Receiver">RSTRX</a> |
| </td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_CR__RSTRX"><strong>RSTRX</strong>: Reset Receiver<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Resets the receiver.</td></tr></tbody></table></li> |
| <li id="USART1_CR__RSTTX"><strong>RSTTX</strong>: Reset Transmitter<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Resets the transmitter.</td></tr></tbody></table></li> |
| <li id="USART1_CR__RXEN"><strong>RXEN</strong>: Receiver Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the receiver, if RXDIS is 0.</td></tr></tbody></table></li> |
| <li id="USART1_CR__RXDIS"><strong>RXDIS</strong>: Receiver Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the receiver.</td></tr></tbody></table></li> |
| <li id="USART1_CR__TXEN"><strong>TXEN</strong>: Transmitter Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the transmitter if TXDIS is 0.</td></tr></tbody></table></li> |
| <li id="USART1_CR__TXDIS"><strong>TXDIS</strong>: Transmitter Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Disables the transmitter.</td></tr></tbody></table></li> |
| <li id="USART1_CR__RSTSTA"><strong>RSTSTA</strong>: Reset Status Bits<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Resets the status bits PARE, FRAME, OVRE, UNRE and RXBRK in US_CSR.</td></tr></tbody></table></li> |
| <li id="USART1_CR__STTBRK"><strong>STTBRK</strong>: Start Break<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been trans-mitted. No effect if a break is already being transmitted.</td></tr></tbody></table></li> |
| <li id="USART1_CR__STPBRK"><strong>STPBRK</strong>: Stop Break<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted.</td></tr></tbody></table></li> |
| <li id="USART1_CR__STTTO"><strong>STTTO</strong>: Start Time-out<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.</td></tr></tbody></table></li> |
| <li id="USART1_CR__SENDA"><strong>SENDA</strong>: Send Address<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.</td></tr></tbody></table></li> |
| <li id="USART1_CR__RSTIT"><strong>RSTIT</strong>: Reset Iterations<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.</td></tr></tbody></table></li> |
| <li id="USART1_CR__RSTNACK"><strong>RSTNACK</strong>: Reset Non Acknowledge<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Resets NACK in US_CSR.</td></tr></tbody></table></li> |
| <li id="USART1_CR__RETTO"><strong>RETTO</strong>: Rearm Time-out<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Restart Time-out</td></tr></tbody></table></li> |
| <li id="USART1_CR__RTSEN"><strong>RTSEN</strong>: Request to Send Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Drives the pin RTS to 0.</td></tr></tbody></table></li> |
| <li id="USART1_CR__FCS"><strong>FCS</strong>: Force SPI Chip Select</li> |
| <p>-</p> |
| <li id="USART1_CR__RTSDIS"><strong>RTSDIS</strong>: Request to Send Disable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No effect.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Drives the pin RTS to 1.</td></tr></tbody></table></li> |
| <li id="USART1_CR__RCS"><strong>RCS</strong>: Release SPI Chip Select</li> |
| <p>-</p> |
| </ul> |
| <h4 id="USART1_MR">USART1 Mode Register</h4> |
| <p><strong>Name</strong>: USART1_MR</p> |
| <p><strong>Access</strong>: read-write</p> |
| <p><strong>Address</strong>: 0x40028004</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_MR__FILTER" title="Infrared Receive Line Filter">FILTER</a> |
| </td> |
| <td>-</td> |
| <td colspan="3"> |
| <a href="#USART1_MR__MAX_ITERATION" title="">MAX_ITERATION</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="1"> |
| <a href="#USART1_MR__INVDATA" title="INverted Data">INVDATA</a> |
| </td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_MR__DSNACK" title="Disable Successive NACK">DSNACK</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_MR__INACK" title="Inhibit Non Acknowledge">INACK</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_MR__OVER" title="Oversampling Mode">OVER</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_MR__CLKO" title="Clock Output Select">CLKO</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_MR__MODE9" title="9-bit Character Length">MODE9</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_MR__MSBF" title="Bit Order">MSBF</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="2"> |
| <a href="#USART1_MR__CHMODE" title="Channel Mode">CHMODE</a> |
| </td> |
| <td colspan="2"> |
| <a href="#USART1_MR__NBSTOP" title="Number of Stop Bits">NBSTOP</a> |
| </td> |
| <td colspan="3"> |
| <a href="#USART1_MR__PAR" title="Parity Type">PAR</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_MR__SYNC" title="Synchronous Mode Select">SYNC</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="2"> |
| <a href="#USART1_MR__CHRL" title="Character Length.">CHRL</a> |
| </td> |
| <td colspan="2"> |
| <a href="#USART1_MR__USCLKS" title="Clock Selection">USCLKS</a> |
| </td> |
| <td colspan="4"> |
| <a href="#USART1_MR__USART_MODE" title="">USART_MODE</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_MR__USART_MODE"> |
| <strong>USART_MODE</strong> |
| <table class="values"> |
| <thead> |
| <tr> |
| <th>Value</th> |
| <th>Name</th> |
| <th>Description</th> |
| </tr> |
| </thead> |
| <tbody> |
| <tr class="odd"> |
| <td class="value">0x0</td> |
| <td class="name">NORMAL</td> |
| <td class="description">Normal mode</td> |
| </tr> |
| <tr class="even"> |
| <td class="value">0x1</td> |
| <td class="name">RS485</td> |
| <td class="description">RS485</td> |
| </tr> |
| <tr class="odd"> |
| <td class="value">0x2</td> |
| <td class="name">HW_HANDSHAKING</td> |
| <td class="description">Hardware Handshaking</td> |
| </tr> |
| <tr class="even"> |
| <td class="value">0x4</td> |
| <td class="name">IS07816_T_0</td> |
| <td class="description">IS07816 Protocol: T = 0</td> |
| </tr> |
| <tr class="odd"> |
| <td class="value">0x6</td> |
| <td class="name">IS07816_T_1</td> |
| <td class="description">IS07816 Protocol: T = 1</td> |
| </tr> |
| <tr class="even"> |
| <td class="value">0x8</td> |
| <td class="name">IRDA</td> |
| <td class="description">IrDA</td> |
| </tr> |
| <tr class="odd"> |
| <td class="value">0xE</td> |
| <td class="name">SPI_MASTER</td> |
| <td class="description">SPI Master</td> |
| </tr> |
| <tr class="even"> |
| <td class="value">0xF</td> |
| <td class="name">SPI_SLAVE</td> |
| <td class="description">SPI Slave</td> |
| </tr> |
| </tbody> |
| </table> |
| </li> |
| <li id="USART1_MR__USCLKS"><strong>USCLKS</strong>: Clock Selection<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">MCK</td><td class="description">Master Clock MCK is selected</td></tr><tr class="even"><td class="value">0x1</td><td class="name">DIV</td><td class="description">Internal Clock Divided MCK/DIV (DIV=8) is selected</td></tr><tr class="odd"><td class="value">0x3</td><td class="name">SCK</td><td class="description">Serial Clock SLK is selected</td></tr></tbody></table></li> |
| <li id="USART1_MR__CHRL"><strong>CHRL</strong>: Character Length.<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">5_BIT</td><td class="description">Character length is 5 bits</td></tr><tr class="even"><td class="value">0x1</td><td class="name">6_BIT</td><td class="description">Character length is 6 bits</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">7_BIT</td><td class="description">Character length is 7 bits</td></tr><tr class="even"><td class="value">0x3</td><td class="name">8_BIT</td><td class="description">Character length is 8 bits</td></tr></tbody></table></li> |
| <li id="USART1_MR__SYNC"><strong>SYNC</strong>: Synchronous Mode Select<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">USART operates in Asynchronous Mode.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">USART operates in Synchronous Mode.</td></tr></tbody></table></li> |
| <li id="USART1_MR__CPHA"><strong>CPHA</strong>: SPI Clock Phase</li> |
| <p>-</p> |
| <li id="USART1_MR__PAR"><strong>PAR</strong>: Parity Type<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">EVEN</td><td class="description">Even parity</td></tr><tr class="even"><td class="value">0x1</td><td class="name">ODD</td><td class="description">Odd parity</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">SPACE</td><td class="description">Parity forced to 0 (Space)</td></tr><tr class="even"><td class="value">0x3</td><td class="name">MARK</td><td class="description">Parity forced to 1 (Mark)</td></tr><tr class="odd"><td class="value">0x4</td><td class="name">NO</td><td class="description">No parity</td></tr><tr class="even"><td class="value">0x6</td><td class="name">MULTIDROP</td><td class="description">Multidrop mode</td></tr></tbody></table></li> |
| <li id="USART1_MR__NBSTOP"><strong>NBSTOP</strong>: Number of Stop Bits<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">1_BIT</td><td class="description">1 stop bit</td></tr><tr class="even"><td class="value">0x1</td><td class="name">1_5_BIT</td><td class="description">1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">2_BIT</td><td class="description">2 stop bits</td></tr></tbody></table></li> |
| <li id="USART1_MR__CHMODE"><strong>CHMODE</strong>: Channel Mode<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0x0</td><td class="name">NORMAL</td><td class="description">Normal Mode</td></tr><tr class="even"><td class="value">0x1</td><td class="name">AUTOMATIC</td><td class="description">Automatic Echo. Receiver input is connected to the TXD pin.</td></tr><tr class="odd"><td class="value">0x2</td><td class="name">LOCAL_LOOPBACK</td><td class="description">Local Loopback. Transmitter output is connected to the Receiver Input.</td></tr><tr class="even"><td class="value">0x3</td><td class="name">REMOTE_LOOPBACK</td><td class="description">Remote Loopback. RXD pin is internally connected to the TXD pin.</td></tr></tbody></table></li> |
| <li id="USART1_MR__MSBF"><strong>MSBF</strong>: Bit Order<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Least Significant Bit is sent/received first.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Most Significant Bit is sent/received first.</td></tr></tbody></table></li> |
| <li id="USART1_MR__CPOL"><strong>CPOL</strong>: SPI Clock Polarity</li> |
| <p>-</p> |
| <li id="USART1_MR__MODE9"><strong>MODE9</strong>: 9-bit Character Length<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">CHRL defines character length.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">9-bit character length.</td></tr></tbody></table></li> |
| <li id="USART1_MR__CLKO"><strong>CLKO</strong>: Clock Output Select<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The USART does not drive the SCK pin.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The USART drives the SCK pin if USCLKS does not select the external clock SCK.</td></tr></tbody></table></li> |
| <li id="USART1_MR__OVER"><strong>OVER</strong>: Oversampling Mode<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">16x Oversampling.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">8x Oversampling.</td></tr></tbody></table></li> |
| <li id="USART1_MR__INACK"><strong>INACK</strong>: Inhibit Non Acknowledge<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The NACK is generated.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The NACK is not generated.</td></tr></tbody></table></li> |
| <li id="USART1_MR__DSNACK"><strong>DSNACK</strong>: Disable Successive NACK<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener-ate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted.</td></tr></tbody></table></li> |
| <li id="USART1_MR__INVDATA"><strong>INVDATA</strong>: INverted Data<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The data field transmitted on TXD line is the same as the one written in US_THR register or the content read in US_RHR is the same as RXD line. Normal mode of operation.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The data field transmitted on TXD line is inverted (voltage polarity only) compared to the value written on US_THR regis-ter or the content read in US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line). Inverted Mode of operation, useful for contactless card application. To be used with configuration bit MSBF.</td></tr></tbody></table></li> |
| <li id="USART1_MR__MAX_ITERATION"> |
| <strong>MAX_ITERATION</strong> |
| </li> |
| <p>-</p> |
| <li id="USART1_MR__FILTER"><strong>FILTER</strong>: Infrared Receive Line Filter<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The USART does not filter the receive line.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).</td></tr></tbody></table></li> |
| </ul> |
| <h4 id="USART1_IER">USART1 Interrupt Enable Register</h4> |
| <p><strong>Name</strong>: USART1_IER</p> |
| <p><strong>Access</strong>: write-only</p> |
| <p><strong>Address</strong>: 0x40028008</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_IER__CTSIC" title="Clear to Send Input Change Interrupt Enable">CTSIC</a> |
| </td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_IER__NACK" title="Non AcknowledgeInterrupt Enable">NACK</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IER__RXBUFF" title="Buffer Full Interrupt Enable">RXBUFF</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IER__TXBUFE" title="Buffer Empty Interrupt Enable">TXBUFE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IER__ITER" title="Max number of Repetitions Reached">ITER</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IER__TXEMPTY" title="TXEMPTY Interrupt Enable">TXEMPTY</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IER__TIMEOUT" title="Time-out Interrupt Enable">TIMEOUT</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="1"> |
| <a href="#USART1_IER__PARE" title="Parity Error Interrupt Enable">PARE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IER__FRAME" title="Framing Error Interrupt Enable">FRAME</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IER__OVRE" title="Overrun Error Interrupt Enable">OVRE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IER__ENDTX" title="End of Transmit Interrupt Enable">ENDTX</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IER__ENDRX" title="End of Receive Transfer Interrupt Enable">ENDRX</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IER__RXBRK" title="Receiver Break Interrupt Enable">RXBRK</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IER__TXRDY" title="TXRDY Interrupt Enable">TXRDY</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IER__RXRDY" title="RXRDY Interrupt Enable">RXRDY</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_IER__RXRDY"><strong>RXRDY</strong>: RXRDY Interrupt Enable</li> |
| <p>-</p> |
| <li id="USART1_IER__TXRDY"><strong>TXRDY</strong>: TXRDY Interrupt Enable</li> |
| <p>-</p> |
| <li id="USART1_IER__RXBRK"><strong>RXBRK</strong>: Receiver Break Interrupt Enable</li> |
| <p>-</p> |
| <li id="USART1_IER__ENDRX"><strong>ENDRX</strong>: End of Receive Transfer Interrupt Enable</li> |
| <p>-</p> |
| <li id="USART1_IER__ENDTX"><strong>ENDTX</strong>: End of Transmit Interrupt Enable</li> |
| <p>-</p> |
| <li id="USART1_IER__OVRE"><strong>OVRE</strong>: Overrun Error Interrupt Enable</li> |
| <p>-</p> |
| <li id="USART1_IER__FRAME"><strong>FRAME</strong>: Framing Error Interrupt Enable</li> |
| <p>-</p> |
| <li id="USART1_IER__PARE"><strong>PARE</strong>: Parity Error Interrupt Enable</li> |
| <p>-</p> |
| <li id="USART1_IER__TIMEOUT"><strong>TIMEOUT</strong>: Time-out Interrupt Enable</li> |
| <p>-</p> |
| <li id="USART1_IER__TXEMPTY"><strong>TXEMPTY</strong>: TXEMPTY Interrupt Enable</li> |
| <p>-</p> |
| <li id="USART1_IER__ITER"><strong>ITER</strong>: Max number of Repetitions Reached</li> |
| <p>-</p> |
| <li id="USART1_IER__UNRE"><strong>UNRE</strong>: SPI Underrun Error</li> |
| <p>-</p> |
| <li id="USART1_IER__TXBUFE"><strong>TXBUFE</strong>: Buffer Empty Interrupt Enable</li> |
| <p>-</p> |
| <li id="USART1_IER__RXBUFF"><strong>RXBUFF</strong>: Buffer Full Interrupt Enable</li> |
| <p>-</p> |
| <li id="USART1_IER__NACK"><strong>NACK</strong>: Non AcknowledgeInterrupt Enable</li> |
| <p>-</p> |
| <li id="USART1_IER__CTSIC"><strong>CTSIC</strong>: Clear to Send Input Change Interrupt Enable</li> |
| <p>-</p> |
| </ul> |
| <h4 id="USART1_IDR">USART1 Interrupt Disable Register</h4> |
| <p><strong>Name</strong>: USART1_IDR</p> |
| <p><strong>Access</strong>: write-only</p> |
| <p><strong>Address</strong>: 0x4002800C</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__CTSIC" title="Clear to Send Input Change Interrupt Disable">CTSIC</a> |
| </td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__NACK" title="Non AcknowledgeInterrupt Disable">NACK</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__RXBUFF" title="Buffer Full Interrupt Disable">RXBUFF</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__TXBUFE" title="Buffer Empty Interrupt Disable">TXBUFE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__ITER" title="Max number of Repetitions Reached Disable">ITER</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__TXEMPTY" title="TXEMPTY Interrupt Disable">TXEMPTY</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__TIMEOUT" title="Time-out Interrupt Disable">TIMEOUT</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="1"> |
| <a href="#USART1_IDR__PARE" title="Parity Error Interrupt Disable">PARE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__FRAME" title="Framing Error Interrupt Disable">FRAME</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__OVRE" title="Overrun Error Interrupt Disable">OVRE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__ENDTX" title="End of Transmit Interrupt Disable">ENDTX</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__ENDRX" title="End of Receive Transfer Interrupt Disable">ENDRX</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__RXBRK" title="Receiver Break Interrupt Disable">RXBRK</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__TXRDY" title="TXRDY Interrupt Disable">TXRDY</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IDR__RXRDY" title="RXRDY Interrupt Disable">RXRDY</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_IDR__RXRDY"><strong>RXRDY</strong>: RXRDY Interrupt Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__TXRDY"><strong>TXRDY</strong>: TXRDY Interrupt Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__RXBRK"><strong>RXBRK</strong>: Receiver Break Interrupt Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__ENDRX"><strong>ENDRX</strong>: End of Receive Transfer Interrupt Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__ENDTX"><strong>ENDTX</strong>: End of Transmit Interrupt Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__OVRE"><strong>OVRE</strong>: Overrun Error Interrupt Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__FRAME"><strong>FRAME</strong>: Framing Error Interrupt Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__PARE"><strong>PARE</strong>: Parity Error Interrupt Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__TIMEOUT"><strong>TIMEOUT</strong>: Time-out Interrupt Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__TXEMPTY"><strong>TXEMPTY</strong>: TXEMPTY Interrupt Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__ITER"><strong>ITER</strong>: Max number of Repetitions Reached Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__UNRE"><strong>UNRE</strong>: SPI Underrun Error Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__TXBUFE"><strong>TXBUFE</strong>: Buffer Empty Interrupt Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__RXBUFF"><strong>RXBUFF</strong>: Buffer Full Interrupt Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__NACK"><strong>NACK</strong>: Non AcknowledgeInterrupt Disable</li> |
| <p>-</p> |
| <li id="USART1_IDR__CTSIC"><strong>CTSIC</strong>: Clear to Send Input Change Interrupt Disable</li> |
| <p>-</p> |
| </ul> |
| <h4 id="USART1_IMR">USART1 Interrupt Mask Register</h4> |
| <p><strong>Name</strong>: USART1_IMR</p> |
| <p><strong>Access</strong>: read-only</p> |
| <p><strong>Address</strong>: 0x40028010</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__CTSIC" title="Clear to Send Input Change Interrupt Mask">CTSIC</a> |
| </td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__NACK" title="Non AcknowledgeInterrupt Mask">NACK</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__RXBUFF" title="Buffer Full Interrupt Mask">RXBUFF</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__TXBUFE" title="Buffer Empty Interrupt Mask">TXBUFE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__ITER" title="Max number of Repetitions Reached Mask">ITER</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__TXEMPTY" title="TXEMPTY Interrupt Mask">TXEMPTY</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__TIMEOUT" title="Time-out Interrupt Mask">TIMEOUT</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="1"> |
| <a href="#USART1_IMR__PARE" title="Parity Error Interrupt Mask">PARE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__FRAME" title="Framing Error Interrupt Mask">FRAME</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__OVRE" title="Overrun Error Interrupt Mask">OVRE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__ENDTX" title="End of Transmit Interrupt Mask">ENDTX</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__ENDRX" title="End of Receive Transfer Interrupt Mask">ENDRX</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__RXBRK" title="Receiver Break Interrupt Mask">RXBRK</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__TXRDY" title="TXRDY Interrupt Mask">TXRDY</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_IMR__RXRDY" title="RXRDY Interrupt Mask">RXRDY</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_IMR__RXRDY"><strong>RXRDY</strong>: RXRDY Interrupt Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__TXRDY"><strong>TXRDY</strong>: TXRDY Interrupt Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__RXBRK"><strong>RXBRK</strong>: Receiver Break Interrupt Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__ENDRX"><strong>ENDRX</strong>: End of Receive Transfer Interrupt Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__ENDTX"><strong>ENDTX</strong>: End of Transmit Interrupt Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__OVRE"><strong>OVRE</strong>: Overrun Error Interrupt Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__FRAME"><strong>FRAME</strong>: Framing Error Interrupt Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__PARE"><strong>PARE</strong>: Parity Error Interrupt Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__TIMEOUT"><strong>TIMEOUT</strong>: Time-out Interrupt Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__TXEMPTY"><strong>TXEMPTY</strong>: TXEMPTY Interrupt Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__ITER"><strong>ITER</strong>: Max number of Repetitions Reached Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__UNRE"><strong>UNRE</strong>: SPI Underrun Error Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__TXBUFE"><strong>TXBUFE</strong>: Buffer Empty Interrupt Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__RXBUFF"><strong>RXBUFF</strong>: Buffer Full Interrupt Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__NACK"><strong>NACK</strong>: Non AcknowledgeInterrupt Mask</li> |
| <p>-</p> |
| <li id="USART1_IMR__CTSIC"><strong>CTSIC</strong>: Clear to Send Input Change Interrupt Mask</li> |
| <p>-</p> |
| </ul> |
| <h4 id="USART1_CSR">USART1 Channel Status Register</h4> |
| <p><strong>Name</strong>: USART1_CSR</p> |
| <p><strong>Access</strong>: read-only</p> |
| <p><strong>Address</strong>: 0x40028014</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="1"> |
| <a href="#USART1_CSR__CTS" title="Image of CTS Input">CTS</a> |
| </td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__CTSIC" title="Clear to Send Input Change Flag">CTSIC</a> |
| </td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__NACK" title="Non AcknowledgeInterrupt">NACK</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__RXBUFF" title="Reception Buffer Full">RXBUFF</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__TXBUFE" title="Transmission Buffer Empty">TXBUFE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__ITER" title="Max number of Repetitions Reached">ITER</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__TXEMPTY" title="Transmitter Empty">TXEMPTY</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__TIMEOUT" title="Receiver Time-out">TIMEOUT</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="1"> |
| <a href="#USART1_CSR__PARE" title="Parity Error">PARE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__FRAME" title="Framing Error">FRAME</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__OVRE" title="Overrun Error">OVRE</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__ENDTX" title="End of Transmitter Transfer">ENDTX</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__ENDRX" title="End of Receiver Transfer">ENDRX</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__RXBRK" title="Break Received/End of Break">RXBRK</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__TXRDY" title="Transmitter Ready">TXRDY</a> |
| </td> |
| <td colspan="1"> |
| <a href="#USART1_CSR__RXRDY" title="Receiver Ready">RXRDY</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_CSR__RXRDY"><strong>RXRDY</strong>: Receiver Ready<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">At least one complete character has been received and US_RHR has not yet been read.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__TXRDY"><strong>TXRDY</strong>: Transmitter Ready<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">There is no character in the US_THR.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__RXBRK"><strong>RXBRK</strong>: Break Received/End of Break<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No Break received or End of Break detected since the last RSTSTA.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Break Received or End of Break detected since the last RSTSTA.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__ENDRX"><strong>ENDRX</strong>: End of Receiver Transfer<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The End of Transfer signal from the Receive PDC channel is inactive.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The End of Transfer signal from the Receive PDC channel is active.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__ENDTX"><strong>ENDTX</strong>: End of Transmitter Transfer<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The End of Transfer signal from the Transmit PDC channel is inactive.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The End of Transfer signal from the Transmit PDC channel is active.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__OVRE"><strong>OVRE</strong>: Overrun Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No overrun error has occurred since the last RSTSTA.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">At least one overrun error has occurred since the last RSTSTA.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__FRAME"><strong>FRAME</strong>: Framing Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No stop bit has been detected low since the last RSTSTA.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">At least one stop bit has been detected low since the last RSTSTA.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__PARE"><strong>PARE</strong>: Parity Error<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No parity error has been detected since the last RSTSTA.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">At least one parity error has been detected since the last RSTSTA.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__TIMEOUT"><strong>TIMEOUT</strong>: Receiver Time-out<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">There has been a time-out since the last Start Time-out command (STTTO in US_CR).</td></tr></tbody></table></li> |
| <li id="USART1_CSR__TXEMPTY"><strong>TXEMPTY</strong>: Transmitter Empty<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">There are no characters in US_THR, nor in the Transmit Shift Register.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__ITER"><strong>ITER</strong>: Max number of Repetitions Reached<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Maximum number of repetitions has not been reached since the last RSTSTA.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Maximum number of repetitions has been reached since the last RSTSTA.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__UNRE"><strong>UNRE</strong>: SPI Underrun Error</li> |
| <p>-</p> |
| <li id="USART1_CSR__TXBUFE"><strong>TXBUFE</strong>: Transmission Buffer Empty<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The signal Buffer Empty from the Transmit PDC channel is inactive.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The signal Buffer Empty from the Transmit PDC channel is active.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__RXBUFF"><strong>RXBUFF</strong>: Reception Buffer Full<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The signal Buffer Full from the Receive PDC channel is inactive.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The signal Buffer Full from the Receive PDC channel is active.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__NACK"><strong>NACK</strong>: Non AcknowledgeInterrupt<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Non Acknowledge has not been detected since the last RSTNACK.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">At least one Non Acknowledge has been detected since the last RSTNACK.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__CTSIC"><strong>CTSIC</strong>: Clear to Send Input Change Flag<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No input change has been detected on the CTS pin since the last read of US_CSR.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">At least one input change has been detected on the CTS pin since the last read of US_CSR.</td></tr></tbody></table></li> |
| <li id="USART1_CSR__CTS"><strong>CTS</strong>: Image of CTS Input<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">CTS is set to 0.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">CTS is set to 1.</td></tr></tbody></table></li> |
| </ul> |
| <h4 id="USART1_RHR">USART1 Receiver Holding Register</h4> |
| <p><strong>Name</strong>: USART1_RHR</p> |
| <p><strong>Access</strong>: read-only</p> |
| <p><strong>Address</strong>: 0x40028018</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="1"> |
| <a href="#USART1_RHR__RXSYNH" title="Received Sync">RXSYNH</a> |
| </td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_RHR__RXCHR" title="Received Character">RXCHR</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_RHR__RXCHR" title="Received Character">RXCHR</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_RHR__RXCHR"><strong>RXCHR</strong>: Received Character</li> |
| <p>-</p> |
| <li id="USART1_RHR__RXSYNH"><strong>RXSYNH</strong>: Received Sync<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Last Character received is a Data.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Last Character received is a Command.</td></tr></tbody></table></li> |
| </ul> |
| <h4 id="USART1_THR">USART1 Transmitter Holding Register</h4> |
| <p><strong>Name</strong>: USART1_THR</p> |
| <p><strong>Access</strong>: write-only</p> |
| <p><strong>Address</strong>: 0x4002801C</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="1"> |
| <a href="#USART1_THR__TXSYNH" title="Sync Field to be transmitted">TXSYNH</a> |
| </td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_THR__TXCHR" title="Character to be Transmitted">TXCHR</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_THR__TXCHR" title="Character to be Transmitted">TXCHR</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_THR__TXCHR"><strong>TXCHR</strong>: Character to be Transmitted</li> |
| <p>-</p> |
| <li id="USART1_THR__TXSYNH"><strong>TXSYNH</strong>: Sync Field to be transmitted<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.</td></tr></tbody></table></li> |
| </ul> |
| <h4 id="USART1_BRGR">USART1 Baud Rate Generator Register</h4> |
| <p><strong>Name</strong>: USART1_BRGR</p> |
| <p><strong>Access</strong>: read-write</p> |
| <p><strong>Address</strong>: 0x40028020</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="3"> |
| <a href="#USART1_BRGR__FP" title="Fractional Part">FP</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_BRGR__CD" title="Clock Divider">CD</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_BRGR__CD" title="Clock Divider">CD</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_BRGR__CD"><strong>CD</strong>: Clock Divider</li> |
| <p>-</p> |
| <li id="USART1_BRGR__FP"><strong>FP</strong>: Fractional Part</li> |
| <p>-</p> |
| </ul> |
| <h4 id="USART1_RTOR">USART1 Receiver Time-out Register</h4> |
| <p><strong>Name</strong>: USART1_RTOR</p> |
| <p><strong>Access</strong>: read-write</p> |
| <p><strong>Address</strong>: 0x40028024</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_RTOR__TO" title="Time-out Value">TO</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_RTOR__TO" title="Time-out Value">TO</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_RTOR__TO"><strong>TO</strong>: Time-out Value</li> |
| <p>-</p> |
| </ul> |
| <h4 id="USART1_TTGR">USART1 Transmitter Timeguard Register</h4> |
| <p><strong>Name</strong>: USART1_TTGR</p> |
| <p><strong>Access</strong>: read-write</p> |
| <p><strong>Address</strong>: 0x40028028</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_TTGR__TG" title="Timeguard Value">TG</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_TTGR__TG"><strong>TG</strong>: Timeguard Value</li> |
| <p>-</p> |
| </ul> |
| <h4 id="USART1_FIDI">USART1 FI DI Ratio Register</h4> |
| <p><strong>Name</strong>: USART1_FIDI</p> |
| <p><strong>Access</strong>: read-write</p> |
| <p><strong>Address</strong>: 0x40028040</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="3"> |
| <a href="#USART1_FIDI__FI_DI_RATIO" title="FI Over DI Ratio Value">FI_DI_RATIO</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_FIDI__FI_DI_RATIO" title="FI Over DI Ratio Value">FI_DI_RATIO</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_FIDI__FI_DI_RATIO"><strong>FI_DI_RATIO</strong>: FI Over DI Ratio Value</li> |
| <p>-</p> |
| </ul> |
| <h4 id="USART1_NER">USART1 Number of Errors Register</h4> |
| <p><strong>Name</strong>: USART1_NER</p> |
| <p><strong>Access</strong>: read-only</p> |
| <p><strong>Address</strong>: 0x40028044</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_NER__NB_ERRORS" title="Number of Errors">NB_ERRORS</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_NER__NB_ERRORS"><strong>NB_ERRORS</strong>: Number of Errors</li> |
| <p>-</p> |
| </ul> |
| <h4 id="USART1_IF">USART1 IrDA Filter Register</h4> |
| <p><strong>Name</strong>: USART1_IF</p> |
| <p><strong>Access</strong>: read-write</p> |
| <p><strong>Address</strong>: 0x4002804C</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_IF__IRDA_FILTER" title="IrDA Filter">IRDA_FILTER</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_IF__IRDA_FILTER"><strong>IRDA_FILTER</strong>: IrDA Filter</li> |
| <p>-</p> |
| </ul> |
| <h4 id="USART1_WPMR">USART1 Write Protect Mode Register</h4> |
| <p><strong>Name</strong>: USART1_WPMR</p> |
| <p><strong>Access</strong>: read-write</p> |
| <p><strong>Address</strong>: 0x400280E4</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_WPMR__WPKEY" title="Write Protect KEY">WPKEY</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_WPMR__WPKEY" title="Write Protect KEY">WPKEY</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_WPMR__WPKEY" title="Write Protect KEY">WPKEY</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_WPMR__WPEN" title="Write Protect Enable">WPEN</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_WPMR__WPEN"><strong>WPEN</strong>: Write Protect Enable<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">Disables the Write Protect if WPKEY corresponds to 0x555341 ("USA" in ASCII).</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">Enables the Write Protect if WPKEY corresponds to 0x555341 ("USA" in ASCII).</td></tr></tbody></table></li> |
| <li id="USART1_WPMR__WPKEY"><strong>WPKEY</strong>: Write Protect KEY</li> |
| <p>-</p> |
| </ul> |
| <h4 id="USART1_WPSR">USART1 Write Protect Status Register</h4> |
| <p><strong>Name</strong>: USART1_WPSR</p> |
| <p><strong>Access</strong>: read-only</p> |
| <p><strong>Address</strong>: 0x400280E8</p> |
| <table class="fields"> |
| <tbody> |
| <tr class="offsets"> |
| <td>31</td> |
| <td>30</td> |
| <td>29</td> |
| <td>28</td> |
| <td>27</td> |
| <td>26</td> |
| <td>25</td> |
| <td>24</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| </tr> |
| <tr class="offsets"> |
| <td>23</td> |
| <td>22</td> |
| <td>21</td> |
| <td>20</td> |
| <td>19</td> |
| <td>18</td> |
| <td>17</td> |
| <td>16</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_WPSR__WPVSRC" title="Write Protect Violation Source">WPVSRC</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>15</td> |
| <td>14</td> |
| <td>13</td> |
| <td>12</td> |
| <td>11</td> |
| <td>10</td> |
| <td>9</td> |
| <td>8</td> |
| </tr> |
| <tr class="fields"> |
| <td colspan="8"> |
| <a href="#USART1_WPSR__WPVSRC" title="Write Protect Violation Source">WPVSRC</a> |
| </td> |
| </tr> |
| <tr class="offsets"> |
| <td>7</td> |
| <td>6</td> |
| <td>5</td> |
| <td>4</td> |
| <td>3</td> |
| <td>2</td> |
| <td>1</td> |
| <td>0</td> |
| </tr> |
| <tr class="fields"> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td>-</td> |
| <td colspan="1"> |
| <a href="#USART1_WPSR__WPVS" title="Write Protect Violation Status">WPVS</a> |
| </td> |
| </tr> |
| </tbody> |
| </table> |
| <ul class="values"> |
| <li id="USART1_WPSR__WPVS"><strong>WPVS</strong>: Write Protect Violation Status<table class="values"><thead><tr><th>Value</th><th>Name</th><th>Description</th></tr></thead><tbody><tr class="odd"><td class="value">0</td><td class="name">-</td><td class="description">No Write Protect Violation has occurred since the last read of the US_WPSR register.</td></tr><tr class="even"><td class="value">1</td><td class="name">-</td><td class="description">A Write Protect Violation has occurred since the last read of the US_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.</td></tr></tbody></table></li> |
| <li id="USART1_WPSR__WPVSRC"><strong>WPVSRC</strong>: Write Protect Violation Source</li> |
| <p>-</p> |
| </ul> |
| </div> |
| </div> |
| </body> |
| </html> |
