| /**************************************************************************//** |
| * @file core_cm0.h |
| * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File |
| * @version V2.10 |
| * @date 19. July 2011 |
| * |
| * @note |
| * Copyright (C) 2009-2011 ARM Limited. All rights reserved. |
| * |
| * @par |
| * ARM Limited (ARM) is supplying this software for use with Cortex-M |
| * processor based microcontrollers. This file can be freely distributed |
| * within development tools that are supporting such ARM based processors. |
| * |
| * @par |
| * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
| * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
| * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
| * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
| * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| * |
| ******************************************************************************/ |
| #if defined ( __ICCARM__ ) |
| #pragma system_include /* treat file as system include file for MISRA check */ |
| #endif |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| #ifndef __CORE_CM0_H_GENERIC |
| #define __CORE_CM0_H_GENERIC |
| |
| |
| /** \mainpage CMSIS Cortex-M0 |
| |
| This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. |
| It consists of: |
| |
| - Cortex-M Core Register Definitions |
| - Cortex-M functions |
| - Cortex-M instructions |
| |
| The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease |
| access to the Cortex-M Core |
| */ |
| |
| /** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions |
| CMSIS violates following MISRA-C2004 Rules: |
| |
| - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br> |
| Function definitions in header files are used to allow 'inlining'. |
| |
| - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
| Unions are used for effective representation of core registers. |
| |
| - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br> |
| Function-like macros are used to allow more efficient code. |
| |
| */ |
| |
| |
| /******************************************************************************* |
| * CMSIS definitions |
| ******************************************************************************/ |
| /** \defgroup CMSIS_core_definitions CMSIS Core Definitions |
| This file defines all structures and symbols for CMSIS core: |
| - CMSIS version number |
| - Cortex-M core |
| - Cortex-M core Revision Number |
| @{ |
| */ |
| |
| /* CMSIS CM0 definitions */ |
| #define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ |
| #define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ |
| #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ |
| |
| #define __CORTEX_M (0x00) /*!< Cortex core */ |
| |
| |
| #if defined ( __CC_ARM ) |
| #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
| #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
| |
| #elif defined ( __ICCARM__ ) |
| #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
| #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
| |
| #elif defined ( __GNUC__ ) |
| #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
| #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
| |
| #elif defined ( __TASKING__ ) |
| #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
| #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
| |
| #endif |
| |
| /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ |
| #define __FPU_USED 0 |
| |
| #if defined ( __CC_ARM ) |
| #if defined __TARGET_FPU_VFP |
| #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| #endif |
| #elif defined ( __ICCARM__ ) |
| #if defined __ARMVFP__ |
| #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| #endif |
| |
| #elif defined ( __GNUC__ ) |
| #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
| #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| #endif |
| |
| #elif defined ( __TASKING__ ) |
| /* add preprocessor checks */ |
| #endif |
| |
| #include <stdint.h> /*!< standard types definitions */ |
| #include "core_cmInstr.h" /*!< Core Instruction Access */ |
| #include "core_cmFunc.h" /*!< Core Function Access */ |
| |
| #endif /* __CORE_CM0_H_GENERIC */ |
| |
| #ifndef __CMSIS_GENERIC |
| |
| #ifndef __CORE_CM0_H_DEPENDANT |
| #define __CORE_CM0_H_DEPENDANT |
| |
| /* check device defines and use defaults */ |
| #if defined __CHECK_DEVICE_DEFINES |
| #ifndef __CM0_REV |
| #define __CM0_REV 0x0000 |
| #warning "__CM0_REV not defined in device header file; using default!" |
| #endif |
| |
| #ifndef __NVIC_PRIO_BITS |
| #define __NVIC_PRIO_BITS 2 |
| #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
| #endif |
| |
| #ifndef __Vendor_SysTickConfig |
| #define __Vendor_SysTickConfig 0 |
| #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
| #endif |
| #endif |
| |
| /* IO definitions (access restrictions to peripheral registers) */ |
| #ifdef __cplusplus |
| #define __I volatile /*!< defines 'read only' permissions */ |
| #else |
| #define __I volatile const /*!< defines 'read only' permissions */ |
| #endif |
| #define __O volatile /*!< defines 'write only' permissions */ |
| #define __IO volatile /*!< defines 'read / write' permissions */ |
| |
| /*@} end of group CMSIS_core_definitions */ |
| |
| |
| |
| /******************************************************************************* |
| * Register Abstraction |
| ******************************************************************************/ |
| /** \defgroup CMSIS_core_register CMSIS Core Register |
| Core Register contain: |
| - Core Register |
| - Core NVIC Register |
| - Core SCB Register |
| - Core SysTick Register |
| */ |
| |
| /** \ingroup CMSIS_core_register |
| \defgroup CMSIS_CORE CMSIS Core |
| Type definitions for the Cortex-M Core Registers |
| @{ |
| */ |
| |
| /** \brief Union type to access the Application Program Status Register (APSR). |
| */ |
| typedef union |
| { |
| struct |
| { |
| #if (__CORTEX_M != 0x04) |
| uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ |
| #else |
| uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ |
| uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
| uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ |
| #endif |
| uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
| uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| } b; /*!< Structure used for bit access */ |
| uint32_t w; /*!< Type used for word access */ |
| } APSR_Type; |
| |
| |
| /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
| */ |
| typedef union |
| { |
| struct |
| { |
| uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
| } b; /*!< Structure used for bit access */ |
| uint32_t w; /*!< Type used for word access */ |
| } IPSR_Type; |
| |
| |
| /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
| */ |
| typedef union |
| { |
| struct |
| { |
| uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| #if (__CORTEX_M != 0x04) |
| uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
| #else |
| uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ |
| uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
| uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ |
| #endif |
| uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
| uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ |
| uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
| uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| } b; /*!< Structure used for bit access */ |
| uint32_t w; /*!< Type used for word access */ |
| } xPSR_Type; |
| |
| |
| /** \brief Union type to access the Control Registers (CONTROL). |
| */ |
| typedef union |
| { |
| struct |
| { |
| uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
| uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
| uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ |
| uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ |
| } b; /*!< Structure used for bit access */ |
| uint32_t w; /*!< Type used for word access */ |
| } CONTROL_Type; |
| |
| /*@} end of group CMSIS_CORE */ |
| |
| |
| /** \ingroup CMSIS_core_register |
| \defgroup CMSIS_NVIC CMSIS NVIC |
| Type definitions for the Cortex-M NVIC Registers |
| @{ |
| */ |
| |
| /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
| */ |
| typedef struct |
| { |
| __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
| uint32_t RESERVED0[31]; |
| __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
| uint32_t RSERVED1[31]; |
| __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
| uint32_t RESERVED2[31]; |
| __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
| uint32_t RESERVED3[31]; |
| uint32_t RESERVED4[64]; |
| __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
| } NVIC_Type; |
| |
| /*@} end of group CMSIS_NVIC */ |
| |
| |
| /** \ingroup CMSIS_core_register |
| \defgroup CMSIS_SCB CMSIS SCB |
| Type definitions for the Cortex-M System Control Block Registers |
| @{ |
| */ |
| |
| /** \brief Structure type to access the System Control Block (SCB). |
| */ |
| typedef struct |
| { |
| __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
| __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
| uint32_t RESERVED0; |
| __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
| __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
| __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
| uint32_t RESERVED1; |
| __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
| __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
| } SCB_Type; |
| |
| /* SCB CPUID Register Definitions */ |
| #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
| |
| #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
| |
| #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
| |
| #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
| |
| #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
| #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ |
| |
| /* SCB Interrupt Control State Register Definitions */ |
| #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
| |
| #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
| |
| #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
| |
| #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
| |
| #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
| |
| #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
| |
| #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
| |
| #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
| |
| #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ |
| |
| /* SCB Application Interrupt and Reset Control Register Definitions */ |
| #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
| |
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
| |
| #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
| |
| #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
| |
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
| |
| /* SCB System Control Register Definitions */ |
| #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
| |
| #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
| |
| #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
| |
| /* SCB Configuration Control Register Definitions */ |
| #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
| |
| #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
| |
| /* SCB System Handler Control and State Register Definitions */ |
| #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
| |
| /*@} end of group CMSIS_SCB */ |
| |
| |
| /** \ingroup CMSIS_core_register |
| \defgroup CMSIS_SysTick CMSIS SysTick |
| Type definitions for the Cortex-M System Timer Registers |
| @{ |
| */ |
| |
| /** \brief Structure type to access the System Timer (SysTick). |
| */ |
| typedef struct |
| { |
| __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
| __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
| __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
| __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
| } SysTick_Type; |
| |
| /* SysTick Control / Status Register Definitions */ |
| #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
| |
| #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
| |
| #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
| |
| #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
| #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ |
| |
| /* SysTick Reload Register Definitions */ |
| #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ |
| |
| /* SysTick Current Register Definitions */ |
| #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ |
| |
| /* SysTick Calibration Register Definitions */ |
| #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
| |
| #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
| |
| #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ |
| |
| /*@} end of group CMSIS_SysTick */ |
| |
| |
| /** \ingroup CMSIS_core_register |
| \defgroup CMSIS_CoreDebug CMSIS Core Debug |
| Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP |
| and not via processor. Therefore they are not covered by the Cortex-M0 header file. |
| @{ |
| */ |
| /*@} end of group CMSIS_CoreDebug */ |
| |
| |
| /** \ingroup CMSIS_core_register |
| @{ |
| */ |
| |
| /* Memory mapping of Cortex-M0 Hardware */ |
| #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
| #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ |
| #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
| #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
| #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
| |
| #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
| #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
| #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
| |
| |
| /*@} */ |
| |
| |
| |
| /******************************************************************************* |
| * Hardware Abstraction Layer |
| ******************************************************************************/ |
| /** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface |
| Core Function Interface contains: |
| - Core NVIC Functions |
| - Core SysTick Functions |
| - Core Register Access Functions |
| */ |
| |
| |
| |
| /* ########################## NVIC functions #################################### */ |
| /** \ingroup CMSIS_Core_FunctionInterface |
| \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions |
| @{ |
| */ |
| |
| /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
| /* The following MACROS handle generation of the register offset and byte masks */ |
| #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) |
| #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) |
| #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) |
| |
| |
| /** \brief Enable External Interrupt |
| |
| This function enables a device specific interrupt in the NVIC interrupt controller. |
| The interrupt number cannot be a negative value. |
| |
| \param [in] IRQn Number of the external interrupt to enable |
| */ |
| static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
| { |
| NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); |
| } |
| |
| |
| /** \brief Disable External Interrupt |
| |
| This function disables a device specific interrupt in the NVIC interrupt controller. |
| The interrupt number cannot be a negative value. |
| |
| \param [in] IRQn Number of the external interrupt to disable |
| */ |
| static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
| { |
| NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); |
| } |
| |
| |
| /** \brief Get Pending Interrupt |
| |
| This function reads the pending register in the NVIC and returns the pending bit |
| for the specified interrupt. |
| |
| \param [in] IRQn Number of the interrupt for get pending |
| \return 0 Interrupt status is not pending |
| \return 1 Interrupt status is pending |
| */ |
| static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
| { |
| return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); |
| } |
| |
| |
| /** \brief Set Pending Interrupt |
| |
| This function sets the pending bit for the specified interrupt. |
| The interrupt number cannot be a negative value. |
| |
| \param [in] IRQn Number of the interrupt for set pending |
| */ |
| static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
| { |
| NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); |
| } |
| |
| |
| /** \brief Clear Pending Interrupt |
| |
| This function clears the pending bit for the specified interrupt. |
| The interrupt number cannot be a negative value. |
| |
| \param [in] IRQn Number of the interrupt for clear pending |
| */ |
| static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
| { |
| NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ |
| } |
| |
| |
| /** \brief Set Interrupt Priority |
| |
| This function sets the priority for the specified interrupt. The interrupt |
| number can be positive to specify an external (device specific) |
| interrupt, or negative to specify an internal (core) interrupt. |
| |
| Note: The priority cannot be set for every core interrupt. |
| |
| \param [in] IRQn Number of the interrupt for set priority |
| \param [in] priority Priority to set |
| */ |
| static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
| { |
| if(IRQn < 0) { |
| SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | |
| (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } |
| else { |
| NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | |
| (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } |
| } |
| |
| |
| /** \brief Get Interrupt Priority |
| |
| This function reads the priority for the specified interrupt. The interrupt |
| number can be positive to specify an external (device specific) |
| interrupt, or negative to specify an internal (core) interrupt. |
| |
| The returned priority value is automatically aligned to the implemented |
| priority bits of the microcontroller. |
| |
| \param [in] IRQn Number of the interrupt for get priority |
| \return Interrupt Priority |
| */ |
| static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
| { |
| |
| if(IRQn < 0) { |
| return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ |
| else { |
| return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ |
| } |
| |
| |
| /** \brief System Reset |
| |
| This function initiate a system reset request to reset the MCU. |
| */ |
| static __INLINE void NVIC_SystemReset(void) |
| { |
| __DSB(); /* Ensure all outstanding memory accesses included |
| buffered write are completed before reset */ |
| SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
| SCB_AIRCR_SYSRESETREQ_Msk); |
| __DSB(); /* Ensure completion of memory access */ |
| while(1); /* wait until reset */ |
| } |
| |
| /*@} end of CMSIS_Core_NVICFunctions */ |
| |
| |
| |
| /* ################################## SysTick function ############################################ */ |
| /** \ingroup CMSIS_Core_FunctionInterface |
| \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions |
| @{ |
| */ |
| |
| #if (__Vendor_SysTickConfig == 0) |
| |
| /** \brief System Tick Configuration |
| |
| This function initialises the system tick timer and its interrupt and start the system tick timer. |
| Counter is in free running mode to generate periodical interrupts. |
| |
| \param [in] ticks Number of ticks between two interrupts |
| \return 0 Function succeeded |
| \return 1 Function failed |
| */ |
| static __INLINE uint32_t SysTick_Config(uint32_t ticks) |
| { |
| if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ |
| |
| SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ |
| NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ |
| SysTick->VAL = 0; /* Load the SysTick Counter Value */ |
| SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
| SysTick_CTRL_TICKINT_Msk | |
| SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
| return (0); /* Function successful */ |
| } |
| |
| #endif |
| |
| /*@} end of CMSIS_Core_SysTickFunctions */ |
| |
| |
| |
| |
| #endif /* __CORE_CM0_H_DEPENDANT */ |
| |
| #endif /* __CMSIS_GENERIC */ |
| |
| #ifdef __cplusplus |
| } |
| #endif |