Factory Build
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..14e4dd1
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,5 @@
+*.swp
+*~
+TAGS
+tags
+cscope.out
diff --git a/COPYING b/COPYING
new file mode 100644
index 0000000..9692d21
--- /dev/null
+++ b/COPYING
@@ -0,0 +1,119 @@
+
+
+
+
+This product includes software from ChaN:
+*---------------------------------------------------------------------------/
+/ FatFs - FAT file system module include file R0.08b (C)ChaN, 2011
+/----------------------------------------------------------------------------/
+/ FatFs module is a generic FAT file system module for small embedded systems.
+/ This is a free software that opened for education, research and commercial
+/ developments under license policy of following trems.
+/
+/ Copyright (C) 2011, ChaN, all right reserved.
+/
+/ * The FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/----------------------------------------------------------------------------*/
+
+
+This product includes software from Dmitry Grinberg:
+/*
+Copyright (c) 2011, Dmitry Grinberg (as published for DGOS on http://dgosblog.blogspot.com)
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following condition is met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+This product includes software from Atmel Corporation:
+/* Copyright (c) 2011, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+
+This product includes TREMOR software from the Xiph.org Foundation:
+Copyright (c) 2002, Xiph.org Foundation
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+- Redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer.
+
+- Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in the
+documentation and/or other materials provided with the distribution.
+
+- Neither the name of the Xiph.org Foundation nor the names of its
+contributors may be used to endorse or promote products derived from
+this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION
+OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+This product includes software from the Android Open-Source Project:
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
diff --git a/library/ADK2/ADK.cpp b/library/ADK2/ADK.cpp
new file mode 100644
index 0000000..29b1140
--- /dev/null
+++ b/library/ADK2/ADK.cpp
@@ -0,0 +1,665 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+extern "C"{
+ #include "fwk.h"
+ #include "LEDs.h"
+ #include "Audio.h"
+ #include "dbg.h"
+ #include "coop.h"
+ #include "BT.h"
+ #include "HCI.h"
+ #include "btL2CAP.h"
+ #include "btRFCOMM.h"
+ #include "btSDP.h"
+ #include "btA2DP.h"
+ #include "I2C.h"
+ #include "hygro.h"
+ #include "baro.h"
+ #include "capsense.h"
+ #include "als.h"
+ #include "accel.h"
+ #include "hygro.h"
+ #include "capsense.h"
+ #include "als.h"
+ #include "accel.h"
+ #include "mag.h"
+ #include "f_ff.h"
+ #include "simpleOgg.h"
+ #include "RTC.h"
+ #include "sgBuf.h"
+ void eliza(void);
+}
+#include "usbh.h"
+#include "ADK.h"
+
+static adkBtConnectionRequestF bt_crF = 0;
+static adkBtLinkKeyRequestF bt_krF = 0;
+static adkBtLinkKeyCreatedF bt_kcF = 0;
+static adkBtPinRequestF bt_prF = 0;
+static adkBtDiscoveryResultF bt_drF = 0;
+static adkBtSspDisplayF bt_pdF = 0;
+static FATFS fs;
+
+static char btLinkKeyRequest(void* userData, const uint8_t* mac, uint8_t* buf){
+
+ if(bt_krF) return bt_krF(mac, buf);
+
+ dbgPrintf("BT Link key request from %02x:%02x:%02x:%02x:%02x:%02x -> denied due to lack of handler", mac[5], mac[4], mac[3], mac[2], mac[1], mac[0]);
+ return 0;
+}
+static uint8_t btPinRequestF(void* userData, const uint8_t* mac, uint8_t* buf){ //fill buff with PIN code, return num bytes used (16 max) return 0 to decline
+
+ if(bt_prF) return bt_prF(mac, buf);
+
+ dbgPrintf("BT PIN request from %02x:%02x:%02x:%02x:%02x:%02x -> '0000' due to lack of handler", mac[5], mac[4], mac[3], mac[2], mac[1], mac[0]);
+
+ buf[0] = buf[1] = buf[2] = buf[3] = '0';
+ return 4;
+}
+
+static void btLinkKeyCreated(void* userData, const uint8_t* mac, const uint8_t* buf){
+
+ if(bt_kcF) bt_kcF(mac, buf);
+}
+
+static char btConnReqF(void* userData, const uint8_t* mac, uint32_t devClass, uint8_t linkType){ //return 1 to accept
+
+ if(bt_crF) return bt_crF(mac, devClass, linkType);
+
+ dbgPrintf("BT connection request: %s connection from %02x:%02x:%02x:%02x:%02x:%02x (class %06X) -> accepted due to lack of handler\n", linkType ? "ACL" : "SCO", mac[5], mac[4], mac[3], mac[2], mac[1], mac[0], devClass);
+ return 1;
+}
+
+static void btConnStartF(void* userData, uint16_t conn, const uint8_t* mac, uint8_t linkType, uint8_t encrMode){
+
+ dbgPrintf("BT %s connection up with handle %d to %02x:%02x:%02x:%02x:%02x:%02x encryption type %d\n",
+ linkType ? "ACL" : "SCO", conn, mac[5], mac[4], mac[3], mac[2], mac[1], mac[0], encrMode);
+ l2capAclLinkUp(conn);
+}
+
+static void btConnEndF(void* userData, uint16_t conn, uint8_t reason){
+
+ dbgPrintf("BT connection with handle %d down for reason %d\n", conn, reason);
+ l2capAclLinkDown(conn);
+}
+
+static void btAclDataRxF(void* userData, uint16_t conn, char first, uint8_t bcastType, const uint8_t* data, uint16_t sz){
+
+ l2capAclLinkDataRx(conn, first, data, sz);
+}
+
+static void btSspShowF(void* userData, const uint8_t* mac, uint32_t val){
+
+ if(val == BT_SSP_DONE_VAL) val = ADK_BT_SSP_DONE_VAL;
+
+ if(bt_pdF) bt_pdF(mac, val);
+}
+
+static char btVerboseScanCbkF(void* userData, BtDiscoveryResult* dr){
+
+ if(bt_drF) return bt_drF(dr->mac, dr->PSRM, dr->PSPM, dr->PSM, dr->co, dr->dc);
+
+ dbgPrintf("BT: no callback for scan makes the scan useless, no?");
+ return 0;
+}
+
+void ADK::adkInit(void){
+
+ //board init
+ ::fwkInit();
+ ::coopInit();
+ ::ledsInit();
+ ::i2cInit(1, 400000);
+ ::rtcInit();
+ ::rtcSet(2012, 3, 28, 19, 8, 50);
+ ::audioInit();
+ ::usbh_init();
+
+ //bt init
+ static const BtFuncs myBtFuncs = {this, btVerboseScanCbkF, btConnReqF, btConnStartF, btConnEndF, btPinRequestF, btLinkKeyRequest, btLinkKeyCreated, btAclDataRxF, btSspShowF};
+ btInit(&myBtFuncs); //BT UART & HCI driver
+ btSdpRegisterL2capService(); //SDP daemon
+ btRfcommRegisterL2capService(); //RFCOMM framework
+ eliza(); //easter egg
+ btA2dpRegister(); //A2DP profile
+
+
+ uint8_t mac[BT_MAC_SIZE];
+
+ if(::btLocalMac(mac)) dbgPrintf("BT MAC: %02X:%02X:%02X:%02X:%02X:%02X\n", mac[5], mac[4], mac[3], mac[2], mac[1], mac[0]);
+
+ //i2c devices init
+ if(!hygroInit()) dbgPrintf("ADK i2c init failure: hygrometer\n");
+ if(!baroInit()) dbgPrintf("ADK i2c init failure: barometer\n");
+ if(!capSenseInit()) dbgPrintf("ADK i2c init failure: capsense\n");
+ if(!alsInit()) dbgPrintf("ADK i2c init failure: ALS\n");
+ if(!accelInit()) dbgPrintf("ADK i2c init failure: accelerometer\n");
+ if(!magInit()) dbgPrintf("ADK i2c init failure: magnetometer\n");
+}
+
+void ADK::adkEventProcess(void){
+ ::coopYield();
+}
+
+void ADK::getUniqueId(uint32_t* ID){
+
+ ::cpuGetUniqId(ID);
+}
+
+uint64_t ADK::getUptime(void){ //in ms
+
+ return ::fwkGetUptime();
+}
+
+void ADK::adkSetPutchar(adkPutcharF f){
+
+ ::dbgSetPutchar(f);
+}
+
+void ADK::ledWrite(uint8_t led_id, uint8_t r, uint8_t g, uint8_t b){
+
+ ::ledWrite(led_id, r, g, b);
+}
+
+void ADK::ledDrawIcon(uint8_t offset, uint8_t r, uint8_t g, uint8_t b){
+
+ ::ledDrawIcon(offset, r, g, b);
+}
+
+void ADK::ledDrawLetter(char letter, uint8_t val, uint8_t r, uint8_t g, uint8_t b){
+
+ ::ledDrawLetter(letter, val, r, g, b);
+}
+
+void ADK::ledUpdate(void){
+
+ ::ledUpdate();
+}
+
+void ADK::ledDbgState(char on){
+
+ ::ledDbgState(on);
+}
+
+void ADK::audioOn(int source, uint32_t samplerate){
+
+ ::audioOn(source, samplerate);
+}
+
+void ADK::audioOff(int source){
+
+ ::audioOff(source);
+}
+
+void ADK::audioAddBuffer(int source, const uint16_t* samples, uint32_t numSamples){
+
+ ::audioAddBuffer(source, samples, numSamples);
+}
+
+int ADK::audioTryAddBuffer(int source, const uint16_t* samples, uint32_t numSamples){
+
+ return ::audioTryAddBuffer(source, samples, numSamples);
+}
+
+void ADK::btEnable(adkBtConnectionRequestF crF, adkBtLinkKeyRequestF krF, adkBtLinkKeyCreatedF kcF, adkBtPinRequestF prF, adkBtDiscoveryResultF drF){
+
+ bt_crF = crF;
+ bt_krF = krF;
+ bt_kcF = kcF;
+ bt_prF = prF;
+ bt_drF = drF;
+}
+
+void ADK::btSetSspCallback(adkBtSspDisplayF pdF){
+
+ bt_pdF = pdF;
+}
+
+char ADK::btSetLocalName(const char* name){
+
+ return ::btSetLocalName(name);
+}
+
+char ADK::btGetRemoteName(const uint8_t* mac, uint8_t PSRM, uint8_t PSM, uint16_t co, char* nameBuf){
+
+ return ::btGetRemoteName(mac, PSRM, PSM, co, nameBuf);
+}
+
+void ADK::btScan(void){
+
+ ::btScan();
+}
+
+char ADK::btDiscoverable(char on){
+
+ return ::btDiscoverable(on);
+}
+
+char ADK::btConnectable(char on){
+
+ return ::btConnectable(on);
+}
+
+char ADK::btSetDeviceClass(uint32_t cls){
+
+ return ::btSetDeviceClass(cls);
+}
+
+char ADK::hygroRead(int32_t *temp, int32_t *humidity){
+
+ return ::hygroRead(temp, humidity);
+}
+
+void ADK::baroRead(uint8_t oss, long *kPa, long* decicelcius){
+
+ return ::baroRead(oss, kPa, decicelcius);
+}
+
+uint8_t ADK::capSenseSlider(void){
+
+ return ::capSenseSlider();
+}
+
+uint16_t ADK::capSenseButtons(void){
+
+ return ::capSenseButtons();
+}
+
+uint16_t ADK::capSenseIcons(void){
+
+ return ::capSenseIcons();
+}
+
+void ADK::capSenseDump(void){
+
+ return ::capSenseDump();
+}
+
+void ADK::alsRead(uint16_t* prox, uint16_t* clear, uint16_t* R, uint16_t* G, uint16_t* B, uint16_t* IR, uint16_t* temp){
+
+ return ::alsRead(prox, clear, R, G, B, IR, temp);
+}
+
+void ADK::accelRead(int16_t* x, int16_t* y, int16_t* z){
+
+ ::accelRead(x, y, z);
+}
+
+void ADK::magRead(int16_t* x, int16_t* y, int16_t* z){
+
+ ::magRead(x, y, z);
+}
+
+void ADK::playOgg(const char* path){
+
+ ::playOgg(path);
+}
+
+void ADK::playOggBackground(const char* path, char *complete, char *abort) {
+
+ ::playOggBackground(path, complete, abort);
+}
+
+void ADK::setVolume(uint8_t vol){
+
+ ::setVolume(vol);
+}
+
+uint8_t ADK::getVolume(void){
+
+ return ::getVolume();
+}
+
+void ADK::rtcGet(uint16_t* yearP, uint8_t* monthP, uint8_t* dayP, uint8_t* hourP, uint8_t* minuteP, uint8_t* secondP){
+
+ ::rtcGet(yearP, monthP, dayP, hourP, minuteP, secondP);
+}
+
+void ADK::rtcSet(uint16_t year, uint8_t month, uint8_t day, uint8_t hour, uint8_t minute, uint8_t second){
+
+ ::rtcSet(year, month, day, hour, minute, second);
+}
+
+
+char ADK::fatfsMount(void){ // Mount/Unmount a logical drive
+
+ return f_mount (0, &fs);
+}
+
+char ADK::fatfsOpen(struct FatFile** fPP, const char* path, uint8_t mode){ // Open or create a file
+
+ FIL f;
+ FIL* fP;
+ char ret;
+ uint8_t flg = 0;
+
+ if(mode & FATFS_READ) flg |= FA_READ;
+ if(mode & FATFS_WRITE) flg |= FA_WRITE;
+ if(mode & FATFS_CREATE) flg |= FA_CREATE_NEW | FA_OPEN_ALWAYS;
+ if(mode & FATFS_TRUNCATE) flg |= FA_CREATE_ALWAYS | FA_OPEN_ALWAYS;
+
+ ret = f_open(&f, path, flg);
+ if(ret != FR_OK) return ret;
+
+ fP = (FIL*)malloc(sizeof(FIL));
+ if(!fP){
+ f_close(&f);
+ return -1;
+ }
+ *fP = f;
+ *fPP = (struct FatFile*)fP;
+ return FR_OK;
+}
+
+char ADK::fatfsRead(struct FatFile* f, void* buf, uint32_t num, uint32_t* numDone){ // Read data from a file
+
+ return f_read((FIL*)f, buf, num, numDone);
+}
+
+char ADK::fatfsWrite(struct FatFile* f, void* buf, uint32_t num, uint32_t* numDone){ // Write data to a file
+
+ return f_write((FIL*)f, buf, num, numDone);
+}
+
+char ADK::fatfsSeek(struct FatFile* f_, uint8_t whence, int32_t ofst){ // Move file pointer of a file object
+
+ FIL* f = (FIL*)f_;
+ uint32_t pos;
+
+ pos = f->fptr;
+ switch(pos){
+ case FATFS_START: pos = ofst; break;
+ case FATFS_CUR: pos += ofst; break;
+ case FATFS_END: pos = f->fsize + ofst; break;
+ default: return -1;
+ }
+
+ return f_lseek(f, pos);
+}
+
+char ADK::fatfsClose(struct FatFile* f){ // Close an open file object
+
+ char ret;
+
+ ret = f_close((FIL*)f);
+ free(f);
+ return ret;
+}
+
+char ADK::fatfsTruncate(struct FatFile* f){ // Truncate file
+
+ return f_truncate((FIL*)f);
+}
+
+char ADK::fatfsSync(struct FatFile* f){ // Flush cached data of a writing file
+
+ return f_sync((FIL*)f);
+}
+
+char ADK::fatfsOpenDir(struct FatDir** dPP, const char* path){ // Open an existing directory
+
+ DIR d;
+ DIR* dP;
+ char ret;
+
+ ret = f_opendir(&d, path);
+ if(ret != FR_OK) return ret;
+
+ dP = (DIR*)malloc(sizeof(DIR));
+ if(!dP) return -1;
+
+ *dP = d;
+ *dPP = (struct FatDir*)dP;
+ return FR_OK;
+}
+
+static void fatfsfileInfoToFileInfo(FILINFO* fat, FatFileInfo* fatfs, char before){
+
+ if(before){
+ fat->lfname = fatfs->longName;
+ fat->lfsize = fatfs->nameSz;
+ }
+ else{
+ int i;
+
+ fatfs->longName = fat->lfname;
+ fatfs->nameSz = fat->lfsize;
+ fatfs->fsize = fat->fsize;
+ fatfs->attrib = fat->fattrib;
+ for(i = 0 ;i < 13; i++) fatfs->name[i] = fat->fname[i];
+ }
+}
+
+char ADK::fatfsReadDir(struct FatDir* d, FatFileInfo* i){ // Read a directory item
+
+ FILINFO fi;
+ char ret;
+
+ fatfsfileInfoToFileInfo(&fi, i, 1);
+ ret = f_readdir((DIR*)d, &fi);
+ if(ret == FR_OK) fatfsfileInfoToFileInfo(&fi, i, 0);
+ return ret;
+}
+
+char ADK::fatfsCloseDir(struct FatDir* d){ // Close a directory
+
+ free(d);
+}
+
+char ADK::fatfsStat(const char* path, FatFileInfo* i){ // Get file status
+
+ FILINFO fi;
+ char ret;
+
+ fatfsfileInfoToFileInfo(&fi, i, 1);
+ ret = f_stat(path, &fi);
+ fatfsfileInfoToFileInfo(&fi, i, 0);
+ return ret;
+}
+
+char ADK::fatfsGetFree(const char* path, uint64_t* freeSize){ // Get number of free space on the drive
+
+ char ret;
+ DWORD clus;
+ FATFS* fsP = &fs;
+
+ ret = f_getfree("/", &clus, &fsP);
+ if(freeSize) *freeSize = ((uint64_t)clus * (uint64_t)fs.csize) << 9;
+ return ret;
+}
+
+char ADK::fatfsUnlink(const char* path){ // Delete an existing file or directory
+
+ return f_unlink(path);
+}
+
+char ADK::fatfsMkdir(const char* path){ // Create a new directory
+
+ return f_mkdir(path);
+}
+
+char ADK::fatfsChmod(const char* path, uint8_t val, uint8_t mask){ // Change attributes of the file/dir
+
+ return f_chmod(path, val, mask);
+}
+
+char ADK::fatfsRename(const char* path, const char* newPath){ // Rename/Move a file or directory
+
+ return f_rename(path, newPath);
+}
+
+char ADK::fatfsMkfs(void){ // Create a file system on the drive
+
+ return f_mkfs(0, 0, 0);
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+void ADK::l2capServiceTx(uint16_t conn, uint16_t remChan, const uint8_t* data, uint32_t size){ //send data over L2CAP
+
+ sg_buf* buf = ::sg_alloc();
+
+ if(!buf) return;
+ if(::sg_add_back(buf, data, size, SG_FLAG_MAKE_A_COPY)) ::l2capServiceTx(conn, remChan, buf);
+ else ::sg_free(buf);
+}
+
+void ADK::l2capServiceCloseConn(uint16_t conn, uint16_t chan){
+
+ ::l2capServiceCloseConn(conn, chan);
+}
+
+char ADK::l2capServiceRegister(uint16_t PSM, const L2capService* svcData){
+
+ return::l2capServiceRegister(PSM, svcData);
+}
+
+char ADK::l2capServiceUnregister(uint16_t PSM){
+
+ return ::l2capServiceUnregister(PSM);
+}
+
+void ADK::btSdpServiceDescriptorAdd(const uint8_t* descriptor, uint16_t descrLen){
+
+ ::btSdpServiceDescriptorAdd(descriptor, descrLen);
+}
+
+void ADK::btSdpServiceDescriptorDel(const uint8_t* descriptor){
+
+ ::btSdpServiceDescriptorDel(descriptor);
+}
+
+void ADK::btRfcommRegisterPort(uint8_t dlci, BtRfcommPortOpenF oF, BtRfcommPortCloseF cF, BtRfcommPortRxF rF){
+
+ ::btRfcommRegisterPort(dlci, oF, cF, rF);
+}
+
+void ADK::btRfcommPortTx(void* port, uint8_t dlci, const uint8_t* data, uint16_t size){
+
+ ::btRfcommPortTx(port, dlci, data, size);
+}
+
+uint8_t ADK::btRfcommReserveDlci(uint8_t preference){
+
+ return ::btRfcommReserveDlci(preference);
+}
+
+void ADK::btRfcommReleaseDlci(uint8_t dlci){
+
+ ::btRfcommReleaseDlci(dlci);
+}
+
+// USB
+void ADK::usbStart()
+{
+ ::usbh_start();
+}
+
+void ADK::usbSetAccessoryStringVendor(const char *str)
+{
+ ::usbh_set_accessory_string_vendor(str);
+}
+
+void ADK::usbSetAccessoryStringName(const char *str)
+{
+ ::usbh_set_accessory_string_name(str);
+}
+
+void ADK::usbSetAccessoryStringLongname(const char *str)
+{
+ ::usbh_set_accessory_string_longname(str);
+}
+
+void ADK::usbSetAccessoryStringVersion(const char *str)
+{
+ ::usbh_set_accessory_string_version(str);
+}
+
+void ADK::usbSetAccessoryStringUrl(const char *str)
+{
+ ::usbh_set_accessory_string_url(str);
+}
+
+void ADK::usbSetAccessoryStringSerial(const char *str)
+{
+ ::usbh_set_accessory_string_serial(str);
+}
+
+int ADK::accessoryConnected()
+{
+ return ::usbh_accessory_connected();
+}
+
+int ADK::accessorySend(const void *buf, unsigned int len)
+{
+ return ::accessory_send(buf, len);
+}
+
+int ADK::accessoryReceive(void *buf, unsigned int len)
+{
+ return ::accessory_receive(buf, len);
+}
+
+
+
+extern "C"{
+void logHardFault(unsigned long* auto_pushed, unsigned long* self_pushed)
+{
+ unsigned long r[16], sr;
+ int i;
+
+ for(i = 0; i < 4; i++) r[i] = auto_pushed[i];
+ r[12] = auto_pushed[4];
+ r[13] = ((unsigned long)auto_pushed) - 32;
+ r[14] = auto_pushed[5];
+ r[15] = auto_pushed[6];
+ sr = auto_pushed[7];
+
+ for(i = 4; i < 11; i++) r[i] = self_pushed[i - 4];
+
+ dbgPrintf ("\n\n[Cortex-M3 HARD FAULT]\n");
+ for(i = 0 ;i < 16; i++) dbgPrintf ("R%2d = 0x%08X\n", i, r[i]);
+ dbgPrintf ("SR = 0x%08X\n", sr);
+ while (1);
+}
+
+void __attribute__((naked)) HardFault_Handler(){
+ asm(
+ "tst lr, #4 \n\t"
+ "ite eq \n\t"
+ "mrseq r0, msp \n\t"
+ "mrsne r0, psp \n\t"
+ "push {r4-r11} \n\t"
+ "mov r1, sp \n\t"
+ "B logHardFault \n\t"
+ );
+}
+}
+
+
diff --git a/library/ADK2/ADK.h b/library/ADK2/ADK.h
new file mode 100644
index 0000000..0aca2c8
--- /dev/null
+++ b/library/ADK2/ADK.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef _ADK_H_
+#define _ADK_H_
+
+#include <stdint.h>
+#include "btL2CAP.h"
+#include "btSDP.h"
+#include "btRFCOMM.h"
+
+#define NUM_LEDS 64
+#define NUM_DIGITS 6
+#define NUM_ICONS 8
+
+#define DMA_CHANNEL_LEDS 0 //we use channel 0
+
+typedef void (*adkPutcharF)(char c);
+
+typedef char (*adkBtConnectionRequestF)(const uint8_t* mac, uint32_t devClass, uint8_t linkType); //return 1 to accept
+typedef char (*adkBtLinkKeyRequestF)(const uint8_t* mac, uint8_t* buf); //retrieve link key, fill buffer with it, return 1. if no key -> return 0
+typedef void (*adkBtLinkKeyCreatedF)(const uint8_t* mac, const uint8_t* buf); //link key was just created, save it if you want it later
+typedef char (*adkBtPinRequestF)(const uint8_t* mac, uint8_t* buf); //fill buff with PIN code, return num bytes used (16 max) return 0 to decline
+typedef char (*adkBtDiscoveryResultF)(const uint8_t* mac, uint8_t PSRM, uint8_t PSPM, uint8_t PSM, uint16_t CO, uint32_t devClass); //return 0 to stop scan immediately
+typedef void (*adkBtSspDisplayF)(const uint8_t* mac, uint32_t val);
+
+#define ADK_BT_SSP_DONE_VAL 0x0FF00000
+
+#define BLUETOOTH_MAC_SIZE 6 //bytes
+#define BLUETOOTH_LINK_KEY_SIZE 16 //bytes
+#define BLUETOOTH_MAX_PIN_SIZE 16 //bytes
+#define BLUETOOTH_MAX_NAME_LEN 248 //bytes
+#define ADK_UNIQUE_ID_LEN 4 //4 32-bit values
+
+/* keep in sync with Audio.h */
+#define AUDIO_NULL 0
+#define AUDIO_USB 1
+#define AUDIO_BT 2
+#define AUDIO_ALARM 3
+
+#define AUDIO_MAX_SOURCE 4
+
+/* --- structure(s) and types reference ---
+
+typedef struct{
+
+ uint8_t flags;
+
+ void* (*serviceInstanceAllocate)(uint16_t conn, uint16_t chan, uint16_t remChan);
+ void (*serviceInstanceFree)(void* service);
+
+ void (*serviceRx)(void* service, const uint8_t* data, uint16_t size);
+
+}L2capService;
+
+
+typedef void (*BtRfcommPortOpenF)(void* port, uint8_t dlci);
+typedef void (*BtRfcommPortCloseF)(void* port, uint8_t dlci);
+typedef void (*BtRfcommPortRxF)(void* port, uint8_t dlci, const uint8_t* buf, uint16_t sz);
+
+
+*/
+
+struct FatFile;
+struct FatDir;
+typedef struct FatFile* FatFileP;
+typedef struct FatDir* FatDirP;
+#define FATFS_READ 1
+#define FATFS_WRITE 2
+#define FATFS_CREATE 4
+#define FATFS_TRUNCATE 8
+
+#define FATFS_START 0
+#define FATFS_CUR 1
+#define FATFS_END 2
+
+typedef struct{
+
+ uint32_t fsize;
+ uint8_t attrib;
+ char name[13]; //short name
+ char* longName; //you make this point somewhere
+ uint32_t nameSz;
+
+}FatFileInfo;
+
+class ADK {
+public:
+
+ //generic
+ void adkInit(void);
+ void adkSetPutchar(adkPutcharF f);
+ void adkEventProcess(void); //call this often
+ void getUniqueId(uint32_t* id);
+ uint64_t getUptime(void); //in ms
+
+ //LEDS
+ //raw LED write
+ void ledWrite(uint8_t led_id, uint8_t r, uint8_t g, uint8_t b);
+ //draw an icon
+ void ledDrawIcon(uint8_t icon, uint8_t r, uint8_t g, uint8_t b);
+ //draw a letter
+ void ledDrawLetter(char letter, uint8_t val, uint8_t r, uint8_t g, uint8_t b);
+ //flush the backbuffer to the display (call often)
+ void ledUpdate(void);
+ //on-board debug led
+ void ledDbgState(char on);
+
+ //RAW Audio
+ void audioOn(int source, uint32_t samplerate);
+ void audioOff(int source);
+ void audioAddBuffer(int source, const uint16_t* samples, uint32_t numSamples); //if buffers full, will block until they arent...
+ int audioTryAddBuffer(int source, const uint16_t* samples, uint32_t numSamples); //0 if failed
+
+ //OGG Audio
+ void playOgg(const char* path);
+ void playOggBackground(const char* path, char *complete, char *abort);
+ void setVolume(uint8_t vol);
+ uint8_t getVolume(void);
+
+ //BT
+ void btEnable(adkBtConnectionRequestF crF, adkBtLinkKeyRequestF krF, adkBtLinkKeyCreatedF kcF, adkBtPinRequestF prF, adkBtDiscoveryResultF drF);
+ char btSetLocalName(const char* name);
+ char btGetRemoteName(const uint8_t* mac, uint8_t PSRM, uint8_t PSM, uint16_t co, char* nameBuf);
+ void btScan(void);
+ char btDiscoverable(char on);
+ char btConnectable(char on);
+ char btSetDeviceClass(uint32_t cls);
+
+ //advanced BT
+ //ACL
+ void l2capServiceTx(uint16_t conn, uint16_t remChan, const uint8_t* data, uint32_t size); //send data over L2CAP
+ void l2capServiceCloseConn(uint16_t conn, uint16_t chan);
+ char l2capServiceRegister(uint16_t PSM, const L2capService* svcData);
+ char l2capServiceUnregister(uint16_t PSM);
+
+ //SDP
+ void btSdpServiceDescriptorAdd(const uint8_t* descriptor, uint16_t descrLen); //a copy will NOT be made do not include handle
+ void btSdpServiceDescriptorDel(const uint8_t* descriptor);
+
+ //RFCOMM
+ void btRfcommRegisterPort(uint8_t dlci, BtRfcommPortOpenF oF, BtRfcommPortCloseF cF, BtRfcommPortRxF rF);
+ void btRfcommPortTx(void* port, uint8_t dlci, const uint8_t* data, uint16_t size); //makes a copy of your buffer
+ uint8_t btRfcommReserveDlci(uint8_t preference); //return dlci if success, zero if fail
+ void btRfcommReleaseDlci(uint8_t dlci);
+
+ //SSP
+ void btSetSspCallback(adkBtSspDisplayF pdF);
+
+
+ //Sensors
+ char hygroRead(int32_t *temp, int32_t *humidity); //return 0 on failure
+ void baroRead(uint8_t oss, long* kPa, long* decicelcius);
+ uint8_t capSenseSlider(void);
+ uint16_t capSenseButtons(void);
+ uint16_t capSenseIcons(void);
+ void capSenseDump(void);
+ void alsRead(uint16_t* prox, uint16_t* clear, uint16_t* R, uint16_t* G, uint16_t* B, uint16_t* IR, uint16_t* temp);
+ void accelRead(int16_t* x, int16_t* y, int16_t* z);
+ void magRead(int16_t* x, int16_t* y, int16_t* z);
+
+ //RTC
+ void rtcGet(uint16_t* yearP, uint8_t* monthP, uint8_t* dayP, uint8_t* hourP, uint8_t* minuteP, uint8_t* secondP);
+ void rtcSet(uint16_t year, uint8_t month, uint8_t day, uint8_t hour, uint8_t minute, uint8_t second);
+
+ //FATFS (retrn 0 on success)
+ char fatfsMount(void); // Mount/Unmount a logical drive
+ char fatfsOpen(struct FatFile**, const char* path, uint8_t mode); // Open or create a file
+ char fatfsRead(struct FatFile*, void* buf, uint32_t num, uint32_t* numDone); // Read data from a file
+ char fatfsWrite(struct FatFile*, void* buf, uint32_t num, uint32_t* numDone); // Write data to a file
+ char fatfsSeek(struct FatFile*, uint8_t whence, int32_t pos); // Move file pointer of a file object
+ char fatfsClose(struct FatFile*); // Close an open file object
+ char fatfsTruncate(struct FatFile*); // Truncate file
+ char fatfsSync(struct FatFile*); // Flush cached data of a writing file
+
+ char fatfsOpenDir(struct FatDir**, const char* path); // Open an existing directory
+ char fatfsReadDir(struct FatDir*, FatFileInfo*); // Read a directory item
+ char fatfsCloseDir(struct FatDir*); // Close a directory
+
+ char fatfsStat(const char* path, FatFileInfo*); // Get file status
+ char fatfsGetFree(const char* path, uint64_t* freeSize); // Get number of free space on the drive
+ char fatfsUnlink(const char* path); // Delete an existing file or directory
+ char fatfsMkdir(const char* path); // Create a new directory
+ char fatfsChmod(const char* path, uint8_t val, uint8_t mask); // Change attributes of the file/dir
+ char fatfsRename(const char* path, const char* newPath); // Rename/Move a file or directory
+ char fatfsMkfs(void); // Create a file system on the drive
+
+ //USB
+ void usbStart();
+ void usbSetAccessoryStringVendor(const char *str);
+ void usbSetAccessoryStringName(const char *str);
+ void usbSetAccessoryStringLongname(const char *str);
+ void usbSetAccessoryStringVersion(const char *str);
+ void usbSetAccessoryStringUrl(const char *str);
+ void usbSetAccessoryStringSerial(const char *str);
+
+ //USB accessory
+ int accessoryConnected();
+ int accessorySend(const void *buf, unsigned int len);
+ int accessoryReceive(void *buf, unsigned int len);
+};
+
+
+
+#endif
+
+
diff --git a/library/ADK2/Audio.c b/library/ADK2/Audio.c
new file mode 100644
index 0000000..062efac
--- /dev/null
+++ b/library/ADK2/Audio.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "Audio.h"
+#include "coop.h"
+
+#define DEFAULT_AUDIO_SAMPLERATE 44100
+
+static uint32_t sampleRates[AUDIO_MAX_SOURCE];
+static uint32_t audioActive; // bitmap of active audio sources
+
+static int highestPriAudio(void)
+{
+ int i;
+
+ if (audioActive == 0)
+ return -1;
+
+ return (31 - __builtin_clz(audioActive));
+}
+
+void audioInit(void)
+{
+ PMC_EnablePeripheral(ID_PWM);
+ PWMC_ConfigureClocks(0, 0, BOARD_MCK);
+ PWMC_ConfigureChannel(PWM, 0, PWM_CMR_CPRE_MCK, 0, 0);
+ PWMC_ConfigureEventLineMode(PWM, 0, 1);
+
+ audioSetSample(AUDIO_NULL, DEFAULT_AUDIO_SAMPLERATE);
+
+ PWMC_EnableChannel(PWM, 0);
+ PMC_EnablePeripheral(ID_DACC);
+ DACC_Initialize(DACC, ID_DACC, 1, 4, 0, 0, BOARD_MCK, 8, DACC_CHANNEL_0, 0, 16 );
+ DACC_EnableChannel(DACC, DACC_CHANNEL_0);
+}
+
+void audioOn(int source, uint32_t samplerate)
+{
+ audioActive |= (1 << source);
+
+ audioSetSample(source, samplerate);
+}
+
+void audioOff(int source)
+{
+ int resetsample = 0;
+ if (source == highestPriAudio())
+ resetsample = 1;
+
+ audioActive &= ~(1 << source);
+
+ // switch to the new highest priority audio's sample rate
+ int highest = highestPriAudio();
+ if (resetsample && highest >= 0) {
+ audioSetSample(highest, sampleRates[highest]);
+ }
+}
+
+void audioSetSample(int source, uint32_t samplerate)
+{
+ sampleRates[source] = samplerate;
+
+ // if we're not the highest priority audio source, dont set it
+ if (source != highestPriAudio())
+ return;
+
+ samplerate = (BOARD_MCK + samplerate - 1) / samplerate; //err on the side of slower audio
+
+ PWMC_SetPeriod(PWM, 0, samplerate);
+ PWMC_ConfigureComparisonUnit(PWM, 0, (samplerate + 1) >> 1, 1);
+}
+
+void audioAddBuffer(int source, const uint16_t* samples, uint32_t numSamples)
+{
+ // see if we're the highest priority audio, drop on the floor if we're not
+ if (source != highestPriAudio())
+ return;
+
+ while(!DACC_WriteBuffer(DACC, samples, numSamples)) coopYield();
+}
+
+int audioTryAddBuffer(int source, const uint16_t* samples, uint32_t numSamples)
+{
+ // see if we're the highest priority audio, drop on the floor if we're not
+ if (source != highestPriAudio())
+ return 1; // pretend we queued
+
+ int first_free = (DACC->DACC_TCR == 0) && (DACC->DACC_TNCR == 0);
+
+ uint32_t res = DACC_WriteBuffer(DACC, samples, numSamples);
+
+ if (!res)
+ return 0;
+
+ if (first_free)
+ return 1;
+ else
+ return DACC->DACC_TCR;
+}
+
diff --git a/library/ADK2/Audio.h b/library/ADK2/Audio.h
new file mode 100644
index 0000000..132fc5a
--- /dev/null
+++ b/library/ADK2/Audio.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _AUDIO_H_
+#define _AUDIO_H_
+
+#define AUDIO_NULL 0
+#define AUDIO_USB 1
+#define AUDIO_BT 2
+#define AUDIO_ALARM 3
+
+#define AUDIO_MAX_SOURCE 3
+
+void audioInit(void);
+void audioOn(int source, uint32_t samplerate);
+void audioOff(int source);
+void audioSetSample(int source, uint32_t samplerate);
+
+void audioAddBuffer(int source, const uint16_t* samples, uint32_t numSamples); //if buffers full, will block until they arent...
+int audioTryAddBuffer(int source, const uint16_t* samples, uint32_t numSamples); //0 if failed, positive number of existing queued samples
+
+#define AUDIO_BITS 12
+
+
+
+#endif
+#endif
+
diff --git a/library/ADK2/BT.c b/library/ADK2/BT.c
new file mode 100644
index 0000000..bddbfcc
--- /dev/null
+++ b/library/ADK2/BT.c
@@ -0,0 +1,1742 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "BT.h"
+#include "HCI.h"
+#include "dbg.h"
+#include "coop.h"
+#include "sgBuf.h"
+
+#define BT_VERBOSE 0
+
+#define PACKET_RX_BACKLOG_SZ 4
+
+extern const uint8_t cc256x_init_script[];
+
+static uint8_t* backlog[PACKET_RX_BACKLOG_SZ] = {0, };
+static uint8_t btThreadDie;
+static BtFuncs cbks;
+
+#define RESET PORTA(0)
+#define TX PORTA(10)
+#define RX PORTA(11)
+#define RTS PORTB(25)
+#define CTS PORTB(26)
+
+
+static uint32_t packetStore[(BT_RX_BUF_SZ + 3) >> 2];
+static uint8_t* packet = (uint8_t*)packetStore;
+static uint8_t pageState;
+static uint16_t gAclPacketsCanSend = 0;
+
+typedef struct BtEnqueuedNode{
+
+ struct BtEnqueuedNode* next;
+
+ sg_buf* buf;
+ uint16_t conn;
+ char first;
+ uint8_t bcastType
+
+}BtEnqueuedNode;
+
+BtEnqueuedNode* enqueuedPackets = NULL;
+
+static char btDiscoverableConnectable(void);
+
+static void initBtUart(char initial){
+
+ uint32_t speed = initial ? 115200 : BT_BAUDRATE;
+ if(initial){
+
+ PMC_EnablePeripheral(ID_USART0);
+
+ gpioSetFun(RESET, GPIO_FUNC_GPIO);
+ gpioSetDir(RESET, 0);
+ gpioSetVal(RESET, 0);
+
+ gpioSetFun(RX, GPIO_FUNC_A);
+ gpioSetFun(TX, GPIO_FUNC_A);
+ gpioSetFun(RTS, GPIO_FUNC_A);
+ gpioSetFun(CTS, GPIO_FUNC_A);
+ }
+ USART0->US_CR = US_CR_RSTRX | US_CR_RSTTX | US_CR_RXDIS | US_CR_TXDIS;
+ USART0->US_MR = US_MR_USART_MODE_HW_HANDSHAKING | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL;
+ USART0->US_BRGR = (BOARD_MCK >> 4) / speed;
+ USART0->US_CR = US_CR_RSTRX | US_CR_RSTTX | US_CR_TXDIS | US_CR_RXDIS | US_CR_RSTSTA | US_CR_RTSEN;
+ USART0->US_CR = US_CR_TXEN;
+ USART0->US_CR = US_CR_RXEN;
+}
+
+static void btUartSend(const uint8_t* buf, uint32_t sz){
+
+ while (sz--){
+ while (!(USART0->US_CSR & US_CSR_TXRDY));
+ USART0->US_THR = *buf++;
+ }
+}
+
+static void btUartRecv(uint8_t* buf, uint32_t num){ //recv..hang until we have what we wanted
+
+ USART0->US_RPR = (uint32_t)buf;
+ USART0->US_RCR = num;
+ USART0->US_PTCR = US_PTCR_RXTEN;
+ while(USART0->US_RCR) coopYield();
+}
+
+static uint8_t* hciCmdPacketStart(uint16_t ogf, uint16_t ocf){ //start a packet in "packet", return "state" pointer
+
+ HCI_Cmd* cmd = (HCI_Cmd*)packetStore;
+
+ cmd->opcode = HCI_OPCODE(ogf, ocf);
+ return packet + 3;
+}
+
+static uint8_t* hciCmdPacketAddU32(uint8_t* state, uint32_t val){ //add a uint32 to packet, update state
+
+ *state++ = val;
+ *state++ = val >> 8;
+ *state++ = val >> 16;
+ *state++ = val >> 24;
+
+ return state;
+}
+
+static uint8_t* hciCmdPacketAddU24(uint8_t* state, uint32_t val){ //add a uint24 to packet, update state
+
+ *state++ = val;
+ *state++ = val >> 8;
+ *state++ = val >> 16;
+
+ return state;
+}
+
+static uint8_t* hciCmdPacketAddU16(uint8_t* state, uint16_t val){ //add a uint32 to packet, update state
+
+ *state++ = val;
+ *state++ = val >> 8;
+
+ return state;
+}
+
+static uint8_t* hciCmdPacketAddU8(uint8_t* state, uint8_t val){ //add a uint32 to packet, update state
+
+ *state++ = val;
+
+ return state;
+}
+
+static uint32_t hciCmdPacketFinish(uint8_t* state){ //finish, return size to send
+
+ HCI_Cmd* cmd = (HCI_Cmd*)packetStore;
+ uint32_t paramLen = state - packet - 3;
+
+ cmd->totalParamLen = paramLen;
+ return paramLen + 3;
+}
+
+static void btTxCmdPacketEx(const HCI_Cmd* cmd){
+
+ uint8_t typ = UART_PKT_TYP_CMD;
+
+ btUartSend(&typ, 1);
+ btUartSend((uint8_t*)cmd, 3 + cmd->totalParamLen); //cannot use sizeof thanks to gcc
+}
+
+static void btTxCmdPacket(void){
+
+ btTxCmdPacketEx((HCI_Cmd*)packetStore);
+}
+
+static void btAclDataTxBuf(uint16_t conn, char first, uint8_t bcastType, const uint8_t* data, uint16_t sz){
+
+ uint8_t typ = UART_PKT_TYP_ACL;
+ HCI_ACL_Data* acl = (HCI_ACL_Data*)packetStore;
+ acl->info = conn | (first ? 0x2000 : 0x1000) | ((uint32_t)bcastType) << 14;
+ acl->totalDataLen = sz;
+
+ btUartSend(&typ, 1);
+ btUartSend((uint8_t*)acl, 4);
+ btUartSend(data, sz);
+}
+
+static void btAclDoDataTx(uint16_t conn, char first, uint8_t bcastType, sg_buf* buf){
+
+ sg_iter iter;
+ uint8_t typ = UART_PKT_TYP_ACL;
+ HCI_ACL_Data* acl = (HCI_ACL_Data*)packetStore;
+ const uint8_t* data;
+ uint32_t len;
+
+ gAclPacketsCanSend --;
+ acl->info = conn | (first ? 0x2000 : 0x1000) | ((uint32_t)bcastType) << 14;
+ acl->totalDataLen = sg_length(buf);
+
+ btUartSend(&typ, 1);
+ btUartSend((uint8_t*)acl, 4);
+ iter = sg_iter_start(buf);
+ while(sg_iter_next(&iter, &data, &len)) btUartSend(data, len);
+
+ sg_free(buf);
+ free(buf);
+}
+
+void btAclDataTx(uint16_t conn, char first, uint8_t bcastType, sg_buf* buf){
+
+ if(gAclPacketsCanSend){
+
+ btAclDoDataTx(conn, first, bcastType, buf);
+ }
+ else{
+
+ BtEnqueuedNode *q = enqueuedPackets, *n = malloc(sizeof(BtEnqueuedNode));
+ if(!n){
+
+ //packet dropped due to lack of memory...sorry
+ sg_free(buf);
+ free(buf);
+ return;
+ }
+ n->buf = buf;
+ n->conn = conn;
+ n->first = first;
+ n->bcastType = bcastType;
+ n->next = NULL;
+
+ while(q && q->next) q = q->next;
+ if(q) q->next = n;
+ else enqueuedPackets = n;
+ }
+}
+
+static void btEnqueuePacket(uint8_t typ){ //we got a packet but it's not for us - enqueue it for someone else to use
+
+ uint8_t* copy;
+ unsigned sz, i;
+
+ switch(typ){
+ case UART_PKT_TYP_ACL:
+ sz = ((HCI_ACL_Data*)packetStore)->totalDataLen + 4L;
+ break;
+
+ case UART_PKT_TYP_SCO:
+ sz = ((HCI_SCO_Data*)packetStore)->totalDataLen + 3L;
+ break;
+
+ case UART_PKT_TYP_EVT:
+ sz = ((HCI_Event*)packetStore)->totalParamLen + 2L;
+ break;
+
+ default:
+ //no idea what it is...drop it on the floor
+ return;
+ }
+
+ copy = malloc(sz + 1);
+ if(!copy) return; //cannot alloc -> fail
+
+ copy[0] = typ;
+ for(i = 0; i < sz; i++) copy[i + 1] = packet[i];
+ for(i = 0; i < PACKET_RX_BACKLOG_SZ; i++) if(!backlog[i]) break;
+ if(i == PACKET_RX_BACKLOG_SZ){ //we have to drop something
+
+ #if BT_VERBOSE
+
+ dbgPrintf("BT: dropping backlog item: %d, 0x%x\n", backlog[0][0], backlog[0][1]);
+
+ #endif
+ free(backlog[0]);
+ for(i = 0; i < PACKET_RX_BACKLOG_SZ - 1; i++) backlog[i] = backlog[i + 1];
+ }
+ backlog[i] = copy;
+}
+
+static uint8_t btRxPacket(void){ //return type
+
+ uint8_t typ;
+ uint8_t* dst;
+ unsigned sz;
+
+ btUartRecv(&typ, 1); //get H4 packet type
+ switch(typ){
+ case UART_PKT_TYP_ACL:
+ sz = 4L;
+ break;
+
+ case UART_PKT_TYP_SCO:
+ sz = 3L;
+ break;
+
+ case UART_PKT_TYP_EVT:
+ sz = 2L;
+ break;
+
+ default:
+ //no idea what it is...drop it on the floor
+ return 0;
+ }
+
+ dst = packet + sz;
+ btUartRecv(packet, sz);
+
+ switch(typ){
+ case UART_PKT_TYP_ACL:
+ sz = ((HCI_ACL_Data*)packetStore)->totalDataLen;
+ break;
+
+ case UART_PKT_TYP_SCO:
+ sz = ((HCI_SCO_Data*)packetStore)->totalDataLen;
+ break;
+
+ case UART_PKT_TYP_EVT:
+ sz = ((HCI_Event*)packetStore)->totalParamLen;
+ break;
+
+ default:
+ //no idea what it is...drop it on the floor
+ return 0;
+ }
+
+ if(dst + sz > packet + BT_RX_BUF_SZ){
+
+ dbgPrintf("BT: Incoming packet too big. Dropping\n");
+ while(sz--) btUartRecv(dst, 1);
+ return 0;
+ }
+ else btUartRecv(dst, sz);
+
+ #if BT_VERBOSE
+ {
+ uint8_t *start = packet, *end = dst + sz;
+
+ dbgPrintf("RX: %02X", typ);
+ while(start < end) dbgPrintf(" %02X", *start++);
+ dbgPrintf("\n");
+ }
+ #endif
+
+ return typ;
+}
+
+static void btTaskF(void* ptr){
+
+ HCI_Event* e = (HCI_Event*)packetStore;
+ HCI_ACL_Data* acl = (HCI_ACL_Data*)packetStore;
+ uint8_t* packetState;
+ uint16_t conn;
+ uint8_t mac[6];
+ uint8_t buf[16];
+ unsigned i, j;
+
+
+ while(!btThreadDie){
+
+ uint8_t typ;
+
+ if((typ = btRxPacket())){
+
+ if(typ == UART_PKT_TYP_ACL){
+
+ cbks.BtAclDataRxF(cbks.userData, acl->info & 0x0FFF, ((acl->info >> 12) & 3) == 2, acl->info >> 14, acl->data, acl->totalDataLen);
+ }
+ else if(typ == UART_PKT_TYP_EVT && e->eventCode == HCI_EVT_Connection_Request_Event){
+
+ uint32_t dc = e->params[6] + (((uint32_t)e->params[7]) << 8) + (((uint32_t)e->params[8]) << 16);
+
+ for(i = 0; i < sizeof(mac); i++) mac[i] = e->params[i];
+
+ if(cbks.BtConnReqF(cbks.userData, mac, dc, e->params[9])){ //accept it
+
+ packetState = hciCmdPacketStart(HCI_OGF_Link_Control, HCI_CMD_Accept_Connection_Request);
+ i = 1;
+ }
+ else{ //reject it
+
+ packetState = hciCmdPacketStart(HCI_OGF_Link_Control, HCI_CMD_Reject_Connection_Request);
+ i = 0x0F; //rejected...
+ }
+ packetState = hciCmdPacketAddU8(packetState, mac[0]);
+ packetState = hciCmdPacketAddU8(packetState, mac[1]);
+ packetState = hciCmdPacketAddU8(packetState, mac[2]);
+ packetState = hciCmdPacketAddU8(packetState, mac[3]);
+ packetState = hciCmdPacketAddU8(packetState, mac[4]);
+ packetState = hciCmdPacketAddU8(packetState, mac[5]);
+ packetState = hciCmdPacketAddU8(packetState, i); //we'll be the slave on the connection...for now
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+ }
+ else if(typ == UART_PKT_TYP_EVT && e->eventCode == HCI_EVT_Connection_Complete_Event && !e->params[0]){
+
+ conn = e->params[1] + (((uint32_t)e->params[2]) << 8);
+
+ cbks.BtConnStartF(cbks.userData, conn, e->params + 3, e->params[9], e->params[10]);
+ }
+ else if(typ == UART_PKT_TYP_EVT && e->eventCode == HCI_EVT_Disconnection_Complete_Event){
+
+ BtEnqueuedNode *t, *n = enqueuedPackets, *p = NULL;
+ conn = e->params[1] + (((uint32_t)e->params[2]) << 8);
+
+ cbks.BtConnEndF(cbks.userData, conn, e->params[3]);
+
+ while(n){
+
+ if(n->conn == conn){
+
+ if(p) p->next = n->next;
+ else enqueuedPackets = n->next;
+ t = n;
+ n = n->next;
+ sg_free(t->buf);
+ free(t->buf);
+ free(t);
+ }
+ else{
+
+ p = n;
+ n = n->next;
+ }
+ }
+ }
+ else if(typ == UART_PKT_TYP_EVT && e->eventCode == HCI_EVT_PIN_Code_Request_Event){
+
+ for(i = 0; i < sizeof(mac); i++) mac[i] = e->params[i];
+ i = cbks.BtPinRequestF(cbks.userData, mac, buf);
+ packetState = hciCmdPacketStart(HCI_OGF_Link_Control, i ? HCI_CMD_PIN_Code_Request_Reply : HCI_CMD_PIN_Code_Request_Negative_Reply);
+ packetState = hciCmdPacketAddU8(packetState, mac[0]);
+ packetState = hciCmdPacketAddU8(packetState, mac[1]);
+ packetState = hciCmdPacketAddU8(packetState, mac[2]);
+ packetState = hciCmdPacketAddU8(packetState, mac[3]);
+ packetState = hciCmdPacketAddU8(packetState, mac[4]);
+ packetState = hciCmdPacketAddU8(packetState, mac[5]);
+
+ if(i){ //accept
+
+ packetState = hciCmdPacketAddU8(packetState, i);
+ for(j = 0; j < 16; j++) packetState = hciCmdPacketAddU8(packetState, buf[j]);
+ }
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+ }
+ else if(typ == UART_PKT_TYP_EVT && e->eventCode == HCI_EVT_Number_Of_Completed_Packets_Event){
+
+ uint8_t numHandles = e->params[0];
+
+ for(i = 0; i < numHandles; i++) gAclPacketsCanSend += (((uint16_t)e->params[1 + i * 4 + 3]) << 8) | e->params[1 + i * 4 + 2];
+
+ while(gAclPacketsCanSend && enqueuedPackets){
+
+ BtEnqueuedNode* n = enqueuedPackets;
+
+ enqueuedPackets = n->next;
+ btAclDoDataTx(n->conn, n->first, n->bcastType, n->buf);
+ free(n);
+ }
+ }
+ else if(typ == UART_PKT_TYP_EVT && e->eventCode == HCI_EVT_Link_Key_Request_Event){
+
+ for(i = 0; i < sizeof(mac); i++) mac[i] = e->params[i];
+ i = cbks.BtLinkKeyRequestF(cbks.userData, mac, buf);
+ packetState = hciCmdPacketStart(HCI_OGF_Link_Control, i ? HCI_CMD_Link_Key_Request_Reply : HCI_CMD_Link_Key_Request_Negative_Reply);
+ packetState = hciCmdPacketAddU8(packetState, mac[0]);
+ packetState = hciCmdPacketAddU8(packetState, mac[1]);
+ packetState = hciCmdPacketAddU8(packetState, mac[2]);
+ packetState = hciCmdPacketAddU8(packetState, mac[3]);
+ packetState = hciCmdPacketAddU8(packetState, mac[4]);
+ packetState = hciCmdPacketAddU8(packetState, mac[5]);
+
+ if(i){ //link key given to us
+
+ for(j = 0; j < 16; j++) packetState = hciCmdPacketAddU8(packetState, buf[j]);
+ }
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+ }
+ else if(typ == UART_PKT_TYP_EVT && e->eventCode == HCI_EVT_Link_Key_Notification_Event){
+
+ for(i = 0; i < sizeof(mac); i++) mac[i] = e->params[i];
+ for(i = 0; i < 16; i++) buf[i] = e->params[i + sizeof(mac)];
+
+ cbks.BtLinkKeyCreatedF(cbks.userData, mac, buf);
+ }
+ #if SUPORT_SSP //this was done last minute, but should work :) -DG
+
+ else if(typ == UART_PKT_TYP_EVT && e->eventCode == HCI_EVT_IO_Capability_Request_Event){
+
+ for(i = 0; i < sizeof(mac); i++) mac[i] = e->params[i];
+
+ packetState = hciCmdPacketStart(HCI_OGF_Link_Control, HCI_CMD_IO_Capability_Request_Reply);
+ packetState = hciCmdPacketAddU8(packetState, mac[0]);
+ packetState = hciCmdPacketAddU8(packetState, mac[1]);
+ packetState = hciCmdPacketAddU8(packetState, mac[2]);
+ packetState = hciCmdPacketAddU8(packetState, mac[3]);
+ packetState = hciCmdPacketAddU8(packetState, mac[4]);
+ packetState = hciCmdPacketAddU8(packetState, mac[5]);
+
+ packetState = hciCmdPacketAddU8(packetState, 0); //we claim to be display-only - it works for us
+ packetState = hciCmdPacketAddU8(packetState, 0); //we do not support OOB
+ packetState = hciCmdPacketAddU8(packetState, 2); //we don't care about MITM and like Dedicated Bonding
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+ }
+ else if(typ == UART_PKT_TYP_EVT && e->eventCode == HCI_EVT_User_Confirmation_Request_Event){
+
+ for(i = 0; i < sizeof(mac); i++) mac[i] = e->params[i];
+ uint32_t val = 0;
+
+ for(i = 0; i < 4; i++) val = (val << 8) | e->params[sizeof(mac) + 3 - i];
+
+ //we are disaply-only so accept it unconditionally
+ packetState = hciCmdPacketStart(HCI_OGF_Link_Control, HCI_CMD_User_Confirmation_Request_Reply);
+ packetState = hciCmdPacketAddU8(packetState, mac[0]);
+ packetState = hciCmdPacketAddU8(packetState, mac[1]);
+ packetState = hciCmdPacketAddU8(packetState, mac[2]);
+ packetState = hciCmdPacketAddU8(packetState, mac[3]);
+ packetState = hciCmdPacketAddU8(packetState, mac[4]);
+ packetState = hciCmdPacketAddU8(packetState, mac[5]);
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+
+ cbks.BtSspShow(cbks.userData, mac, val);
+ }
+ else if(typ == UART_PKT_TYP_EVT && e->eventCode == HCI_EVT_Simple_Pairing_Complete_Event){
+
+ for(i = 0; i < sizeof(mac); i++) mac[i] = e->params[i];
+ uint32_t val = 0;
+
+ for(i = 0; i < 4; i++) val = (val << 8) | e->params[sizeof(mac) + 3 - i];
+
+ cbks.BtSspShow(cbks.userData, mac, BT_SSP_DONE_VAL);
+ }
+
+ #endif
+ else{
+
+ btEnqueuePacket(typ);
+ }
+ }
+ }
+ btThreadDie = 0;
+}
+
+static char btTryRxEventPacket(uint8_t wantedType){
+
+ uint8_t i, j;
+
+ for(i = 0; i < PACKET_RX_BACKLOG_SZ; i++){
+
+ if(backlog[i] && backlog[i][0] == UART_PKT_TYP_EVT && (!wantedType || backlog[i][1] == wantedType)){
+
+ for(j = 0; j < 2; j++) packet[j] = backlog[i][j + 1]; //copy packet header
+ for(j = 0; j < ((HCI_Event*)packetStore)->totalParamLen; j++) packet[j + 2] = backlog[i][j + 3];
+ free(backlog[i]);
+ for(; i < PACKET_RX_BACKLOG_SZ - 1; i++) backlog[i] = backlog[i + 1];
+ backlog[i] = NULL;
+ return 1;
+ }
+ }
+ return 0;
+}
+
+static void btRxEventPacket(uint8_t wantedType){
+
+ while(!btTryRxEventPacket(wantedType)) coopYield();
+}
+
+char btInit(const BtFuncs* btf){
+
+ HCI_Cmd* cmd;
+ HCI_Event* evt = (HCI_Event*)packetStore;
+ int num = 0;
+ const uint8_t* script = cc256x_init_script;
+ uint8_t* packetState;
+ int i;
+
+dbgPrintf("inBtInit\n");
+
+ NVIC_DisableIRQ(USART0_IRQn);
+
+ initBtUart(1);
+ gpioSetVal(RESET, 0);
+ delay_ms(15);
+ gpioSetVal(RESET, 1);
+ delay_ms(70);
+ //set speed
+ packetState = hciCmdPacketStart(0x3f, 0x336);
+ packetState = hciCmdPacketAddU32(packetState, BT_BAUDRATE);
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+ btRxPacket(); //it responds at old speed
+ delay_ms(100);
+ initBtUart(0);
+ btThreadDie = 0;
+ if(!coopSpawn(btTaskF, NULL, 2048)){
+ dbgPrintf("Failed to start BT task\n");
+ return 0;
+ }
+ dbgPrintf("Bt initing...\n");
+
+ //init script
+ while(*script++){
+
+ dbgPrintf("\r%d", num++);
+ cmd = (HCI_Cmd*)script;
+ btTxCmdPacketEx(cmd);
+ script += 3 + cmd->totalParamLen;
+ btRxEventPacket(0);
+ #if BT_VERBOSE
+ dbgPrintf(" -> %d, %d:", evt->eventCode ,evt->totalParamLen);
+ for(i = 0; i < evt->totalParamLen; i++) dbgPrintf(" %02X", evt->params[i]);
+ dbgPrintf("\n");
+ #endif
+ }
+
+ //get buffer size
+ packetState = hciCmdPacketStart(HCI_OGF_Informational, HCI_CMD_Read_Buffer_Size);
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+ do{
+ btRxEventPacket(HCI_EVT_Command_Complete_Event);
+ }while(evt->params[1] != (HCI_OPCODE(HCI_OGF_Informational, HCI_CMD_Read_Buffer_Size) & 0xFF) ||
+ evt->params[2] != (HCI_OPCODE(HCI_OGF_Informational, HCI_CMD_Read_Buffer_Size) >> 8));
+
+ uint16_t aclLen, aclNum, scoNum;
+ uint8_t scoLen;
+
+ aclLen = (((uint16_t)evt->params[5]) << 8) | evt->params[4];
+ scoLen = evt->params[6];
+ aclNum = (((uint16_t)evt->params[8]) << 8) | evt->params[7];
+ scoNum = (((uint16_t)evt->params[10]) << 8) | evt->params[9];
+
+ #if BT_VERBOSE
+ dbgPrintf("BT chip buffers: %ux%ub ACL, %ux%ub SCO\n", aclNum, aclLen, scoNum, scoLen);
+ #endif
+
+ gAclPacketsCanSend = aclNum;
+
+ //set connectibility/discoverability
+ pageState = 0;
+ btDiscoverableConnectable();
+
+ //enable simple passcodes
+ if(SUPORT_SSP){
+ packetState = hciCmdPacketStart(HCI_OGF_Controller_and_Baseband, HCI_CMD_Write_Simple_Pairing_Mode);
+ packetState = hciCmdPacketAddU8(packetState, 1); //enable it
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+ do{
+ btRxEventPacket(HCI_EVT_Command_Complete_Event);
+ }while(evt->params[1] != (HCI_OPCODE(HCI_OGF_Controller_and_Baseband, HCI_CMD_Write_Simple_Pairing_Mode) & 0xFF) ||
+ evt->params[2] != (HCI_OPCODE(HCI_OGF_Controller_and_Baseband, HCI_CMD_Write_Simple_Pairing_Mode) >> 8));
+ }
+
+ cbks = *btf;
+
+ dbgPrintf("\nBT up\n");
+
+ return 1;
+}
+
+void btDeinit(void){
+
+ int i;
+
+ btThreadDie = 1;
+ while(btThreadDie) coopYield();
+
+ for(i = 0; i < PACKET_RX_BACKLOG_SZ; i++) if(backlog[i]) free(backlog[i]);
+}
+
+char btLocalMac(uint8_t* buf){
+
+ int i;
+ HCI_Event* evt = (HCI_Event*)packetStore;
+ uint8_t* packetState;
+
+ packetState = hciCmdPacketStart(HCI_OGF_Informational, HCI_CMD_Read_BD_ADDR);
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+ btRxEventPacket(HCI_EVT_Command_Complete_Event);
+ if(evt->totalParamLen != 10 ||
+ evt->params[1] != (HCI_OPCODE(HCI_OGF_Informational, HCI_CMD_Read_BD_ADDR) & 0xFF) ||
+ evt->params[2] != (HCI_OPCODE(HCI_OGF_Informational, HCI_CMD_Read_BD_ADDR) >> 8) || evt->params[3] != 0){
+ return 0;
+ }
+
+ for(i = 0; i < 6; i++) buf[i] = evt->params[4 + i];
+ return 1;
+}
+
+char btSetLocalName(const char* name){
+
+ HCI_Cmd* cmd = (HCI_Cmd*)packetStore;
+ HCI_Event* evt = (HCI_Event*)packetStore;
+ uint8_t* packetState;
+
+ packetState = hciCmdPacketStart(HCI_OGF_Controller_and_Baseband, HCI_CMD_Change_Local_Name);
+ while(name && *name) packetState = hciCmdPacketAddU8(packetState, *name++);
+ packetState = hciCmdPacketAddU8(packetState, 0);
+ hciCmdPacketFinish(packetState);
+ if(cmd->totalParamLen > 248) return 0; //too long
+ cmd->totalParamLen = 248;
+ btTxCmdPacket();
+ btRxEventPacket(HCI_EVT_Command_Complete_Event);
+
+ if(evt->totalParamLen != 4 ||
+ evt->params[1] != (HCI_OPCODE(HCI_OGF_Controller_and_Baseband, HCI_CMD_Change_Local_Name) & 0xFF) ||
+ evt->params[2] != (HCI_OPCODE(HCI_OGF_Controller_and_Baseband, HCI_CMD_Change_Local_Name) >> 8) || evt->params[3] != 0){
+ return 0;
+ }
+ return 1;
+}
+
+void btScan(void){
+
+ //HCI_Cmd* cmd = (HCI_Cmd*)packet;
+ HCI_Event* evt = (HCI_Event*)packet;
+ uint8_t* packetState;
+ int i, done = 0;
+
+ packetState = hciCmdPacketStart(HCI_OGF_Link_Control, HCI_CMD_Inquiry);
+ packetState = hciCmdPacketAddU24(packetState, HCI_LAP_Unlimited_Inquiry);
+ packetState = hciCmdPacketAddU8(packetState, 0x30);
+ packetState = hciCmdPacketAddU8(packetState, 0);
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+
+ while(1){
+ coopYield();
+ if(!done && btTryRxEventPacket(HCI_EVT_Inquiry_Result_Event)){
+
+ uint8_t* MACs = evt->params + evt->params[0]*0 + 1;
+ uint8_t* PSRMs = evt->params + evt->params[0]*6 + 1;
+ uint8_t* PSPMs = evt->params + evt->params[0]*7 + 1;
+ uint8_t* PSMs = evt->params + evt->params[0]*8 + 1;
+ uint8_t* DCs = evt->params + evt->params[0]*9 + 1;
+ uint8_t* COs = evt->params + evt->params[0]*12 + 1;
+
+ for(i = 0; i < evt->params[0]; i++){
+
+ BtDiscoveryResult dr;
+
+ dr.dc = DCs[0] + (((uint32_t)DCs[1]) << 8) + (((uint32_t)DCs[2]) << 16) ;
+ dr.mac[0] = *MACs++;
+ dr.mac[1] = *MACs++;
+ dr.mac[2] = *MACs++;
+ dr.mac[3] = *MACs++;
+ dr.mac[4] = *MACs++;
+ dr.mac[5] = *MACs++;
+ dr.PSRM = *PSRMs++;
+ dr.PSPM = *PSPMs++;
+ dr.PSM = *PSMs++;
+ dr.co = (((uint16_t)COs[1]) << 8) + COs[0];
+
+ if(!cbks.BtDiscoveryF(cbks.userData, &dr)){
+
+ packetState = hciCmdPacketStart(HCI_OGF_Link_Control, HCI_CMD_Inquiry_Cancel);
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+ done = 1;
+ break;
+ }
+ COs += 2;
+ DCs += 3;
+ }
+ }
+ if(btTryRxEventPacket(HCI_EVT_Inquiry_Complete_Event)) break;
+ if(btTryRxEventPacket(HCI_EVT_Command_Complete_Event)) break;
+ }
+}
+
+char btGetRemoteName(const uint8_t* mac, uint8_t PSRM, uint8_t PSM, uint16_t co, char* nameBuf){
+
+ HCI_Event* evt = (HCI_Event*)packet;
+ uint8_t* packetState;
+ int i = 0;
+
+ packetState = hciCmdPacketStart(HCI_OGF_Link_Control, HCI_CMD_Remote_Name_Request);
+ packetState = hciCmdPacketAddU8(packetState, mac[0]);
+ packetState = hciCmdPacketAddU8(packetState, mac[1]);
+ packetState = hciCmdPacketAddU8(packetState, mac[2]);
+ packetState = hciCmdPacketAddU8(packetState, mac[3]);
+ packetState = hciCmdPacketAddU8(packetState, mac[4]);
+ packetState = hciCmdPacketAddU8(packetState, mac[5]);
+ packetState = hciCmdPacketAddU8(packetState, PSRM);
+ packetState = hciCmdPacketAddU8(packetState, PSM);
+ packetState = hciCmdPacketAddU16(packetState, co);
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+
+ btRxEventPacket(HCI_EVT_Remote_Name_Request_Complete_Event);
+
+ if(evt->params[0] == 0){
+
+ while(i < 248 && evt->params[7 + i]){
+ nameBuf[i] = evt->params[7 + i];
+ i++;
+ }
+ nameBuf[i] = 0;
+ return 1;
+ }
+ else return 0;
+}
+
+static char btDiscoverableConnectable(void){
+
+ HCI_Event* evt = (HCI_Event*)packet;
+ uint8_t* packetState;
+
+ packetState = hciCmdPacketStart(HCI_OGF_Controller_and_Baseband, HCI_CMD_Write_Scan_Enable);
+ packetState = hciCmdPacketAddU8(packetState, pageState);
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+ btRxEventPacket(HCI_EVT_Command_Complete_Event);
+ if(evt->totalParamLen != 4 ||
+ evt->params[1] != (HCI_OPCODE(HCI_OGF_Controller_and_Baseband, HCI_CMD_Write_Scan_Enable) & 0xFF) ||
+ evt->params[2] != (HCI_OPCODE(HCI_OGF_Controller_and_Baseband, HCI_CMD_Write_Scan_Enable) >> 8) || evt->params[3] != 0){
+ return 0;
+ }
+
+ return 1;
+}
+
+char btDiscoverable(char on){
+
+ uint8_t nv = (pageState &~ PAGE_STATE_INQUIRY) | (on ? PAGE_STATE_INQUIRY : 0);
+ if(nv == pageState) return 1;
+ pageState = nv;
+
+ return btDiscoverableConnectable();
+}
+
+char btConnectable(char on){
+
+ uint8_t nv = (pageState &~ PAGE_STATE_PAGE) | (on ? PAGE_STATE_PAGE : 0);
+ if(nv == pageState) return 1;
+ pageState = nv;
+
+ return btDiscoverableConnectable();
+}
+
+char btSetDeviceClass(uint32_t cls){
+
+ HCI_Event* evt = (HCI_Event*)packet;
+ uint8_t* packetState;
+
+ packetState = hciCmdPacketStart(HCI_OGF_Controller_and_Baseband, HCI_CMD_Write_Class_Of_Device);
+ packetState = hciCmdPacketAddU24(packetState, cls);
+ hciCmdPacketFinish(packetState);
+ btTxCmdPacket();
+ btRxEventPacket(HCI_EVT_Command_Complete_Event);
+ if(evt->totalParamLen != 4 ||
+ evt->params[1] != (HCI_OPCODE(HCI_OGF_Controller_and_Baseband, HCI_CMD_Write_Class_Of_Device) & 0xFF) ||
+ evt->params[2] != (HCI_OPCODE(HCI_OGF_Controller_and_Baseband, HCI_CMD_Write_Class_Of_Device) >> 8) || evt->params[3] != 0){
+ return 0;
+ }
+
+ return 1;
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+const uint8_t cc256x_init_script[] = {
+ // #--------------------------------------------------------------------------------
+ // # Description : Trio Orca 5500 L ROM Initialization Script
+ // #
+ // # Compatibility: Trio/Orca/5500, 6.0.15 ROM
+ // #
+ // # Last Updated: 09-Aug-2011 10:06:07.86
+ // #
+ // # Version : TI_P6_15.41
+ // #
+ // #
+ // #
+ // # Trio LMP Subversion: 1f29
+ // # Orca LMP Subversion: 1b29
+ // #
+ // # Notes : Use this script on Trio, Orca or 5500, 6.0.15 ROM device only (FW v6.0.15)
+ // #--------------------------------------------------------------------------------
+ //
+ // #################################################################
+ // ## START of Panasonic Adds-On
+ // #################################################################
+ //
+ // ## Change UART baudrate
+ //
+ //
+ // #################################################################
+ // ## END of Panasonic Adds-On
+ // #################################################################
+ //
+ 0x01, 0x37, 0xfe, 0x02, 0x06, 0x0f,
+
+ //
+ //
+ 0x01, 0x05, 0xff, 0xff, 0xa0, 0x62, 0x08, 0x00, 0xfa, 0x06, 0x0f, 0x3d, 0x29, 0x05, 0xc0,
+ 0x03, 0xc0, 0x1e, 0x08, 0x05, 0x00, 0x04, 0xc0, 0x03, 0xc0, 0x1e, 0x08, 0x3d, 0x01, 0x04,
+ 0xc0, 0x03, 0xc0, 0x1e, 0x08, 0x76, 0x02, 0x04, 0xc0, 0x03, 0xc0, 0x1e, 0x08, 0xae, 0x03,
+ 0x04, 0xc0, 0x03, 0xc0, 0x1e, 0x08, 0xae, 0x0b, 0x01, 0x00, 0x34, 0x30, 0x41, 0x02, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xb9, 0x58, 0x00, 0x00, 0x1b, 0x59, 0x00, 0x00, 0x40, 0x59,
+ 0x00, 0x00, 0x41, 0x59, 0x00, 0x00, 0x65, 0x59, 0x00, 0x00, 0xdc, 0x74, 0x00, 0x00, 0xdd,
+ 0x74, 0x00, 0x00, 0x4b, 0xf4, 0x00, 0x00, 0x5c, 0xf4, 0x00, 0x00, 0x5d, 0xf4, 0x00, 0x00,
+ 0xcb, 0xf4, 0x00, 0x00, 0xdc, 0xf4, 0x00, 0x00, 0xdd, 0xf4, 0x00, 0x00, 0x40, 0x19, 0x02,
+ 0x00, 0x48, 0x19, 0x02, 0x00, 0xdb, 0x48, 0x02, 0x00, 0x1c, 0x49, 0x02, 0x00, 0x40, 0x49,
+ 0x02, 0x00, 0x41, 0x49, 0x02, 0x00, 0x45, 0x49, 0x02, 0x00, 0xb9, 0x50, 0x02, 0x00, 0x45,
+ 0x51, 0x02, 0x00, 0x1b, 0x58, 0x02, 0x00, 0x1c, 0x58, 0x02, 0x00, 0x38, 0x58, 0x02, 0x00,
+ 0x41, 0x58, 0x02, 0x00, 0x98, 0x58, 0x02, 0x00, 0xb8, 0x58, 0x02, 0x00, 0xb9, 0x58, 0x02,
+ 0x00, 0xdb, 0x58, 0x02, 0x00, 0xdc, 0x58, 0x02, 0x00, 0x01, 0x59, 0x02, 0x00, 0x05, 0x59,
+ 0x02, 0x00, 0x18, 0x59, 0x02, 0x00, 0x19, 0x59, 0x02, 0x00, 0x1b, 0x59, 0x02, 0x00, 0x1c,
+ 0x59, 0x02, 0x00, 0x40, 0x59, 0x02, 0x00, 0x41, 0x59, 0x02, 0x00, 0x42, 0x59, 0x02, 0x00,
+ 0x45, 0x59, 0x02, 0x00, 0x47, 0x59, 0x02, 0x00, 0x48, 0x59, 0x02, 0x00, 0x56, 0x59, 0x02,
+ 0x00, 0x57, 0x59, 0x02, 0x00, 0x60, 0x59, 0x02, 0x00, 0x62, 0x59, 0x02, 0x00, 0x63, 0x59,
+ 0x02, 0x00, 0x64, 0x59,
+
+ 0x01, 0x05, 0xff, 0xff, 0x9a, 0x63, 0x08, 0x00, 0xfa, 0x02, 0x00, 0x65, 0x59, 0x02, 0x00,
+ 0x84, 0x59, 0x02, 0x00, 0x8c, 0x59, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xb5, 0x43, 0x4d, 0xae, 0x7f, 0x01, 0x24, 0xa6,
+ 0x46, 0x3f, 0x48, 0xfe, 0x44, 0x00, 0x47, 0xb0, 0x42, 0xf8, 0xd1, 0x03, 0x20, 0x17, 0x21,
+ 0x89, 0x01, 0xa6, 0x46, 0x3b, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0xad, 0x7f, 0xa6, 0x46, 0x38,
+ 0x48, 0xfe, 0x44, 0x00, 0x47, 0xa8, 0x42, 0xf9, 0xd1, 0xfe, 0xe7, 0xf0, 0xb5, 0x37, 0x49,
+ 0x4f, 0x68, 0x33, 0x20, 0xc0, 0x5d, 0xc0, 0x06, 0xc0, 0x0f, 0x84, 0x46, 0x08, 0x78, 0x02,
+ 0x28, 0x3e, 0xd1, 0x33, 0x48, 0x06, 0x78, 0x00, 0x24, 0x25, 0x1c, 0x22, 0x1c, 0x1b, 0xe0,
+ 0x11, 0x20, 0x40, 0x01, 0x50, 0x43, 0x30, 0x49, 0x0b, 0x18, 0x38, 0x20, 0xc0, 0x5c, 0x00,
+ 0x28, 0x0f, 0xd0, 0x18, 0x78, 0xa8, 0x21, 0x41, 0x43, 0x2d, 0x48, 0x41, 0x30, 0x40, 0x5c,
+ 0x01, 0x28, 0x07, 0xd0, 0xff, 0x20, 0x1e, 0x30, 0xc0, 0x5c, 0x01, 0x28, 0x01, 0xd1, 0x01,
+ 0x25, 0x00, 0xe0, 0x01, 0x24, 0x50, 0x1c, 0x02, 0x06, 0x12, 0x0e, 0xb2, 0x42, 0xe1, 0xdb,
+ 0x00, 0x20, 0x00, 0x2d,
+
+ 0x01, 0x05, 0xff, 0xff, 0x94, 0x64, 0x08, 0x00, 0xfa, 0x02, 0xd0, 0x00, 0x2c, 0x00, 0xd1,
+ 0x01, 0x20, 0x22, 0x49, 0x0a, 0x78, 0x60, 0x45, 0x10, 0xd0, 0x33, 0x21, 0xcb, 0x19, 0x10,
+ 0x24, 0x19, 0x78, 0xa1, 0x43, 0x04, 0x01, 0x10, 0x20, 0x20, 0x40, 0x08, 0x43, 0x18, 0x70,
+ 0x19, 0x48, 0x01, 0x2a, 0x00, 0xd1, 0x2c, 0x38, 0x01, 0x21, 0x49, 0x02, 0x01, 0x80, 0xf0,
+ 0xbd, 0x70, 0xb5, 0x07, 0x26, 0x15, 0x4d, 0x40, 0x20, 0x40, 0x5d, 0x02, 0x28, 0x0c, 0xd1,
+ 0x45, 0x20, 0x40, 0x5d, 0x14, 0x49, 0x08, 0x18, 0x40, 0x00, 0x02, 0x21, 0x01, 0x24, 0xa6,
+ 0x46, 0x12, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x00, 0x28, 0x03, 0xd1, 0xa8, 0x35, 0x01, 0x3e,
+ 0xeb, 0xd1, 0x70, 0xbd, 0x0e, 0x48, 0x09, 0x21, 0xa6, 0x46, 0x0e, 0x4a, 0xfe, 0x44, 0x10,
+ 0x47, 0x70, 0xbd, 0xc0, 0x46, 0x8b, 0x05, 0x05, 0x00, 0xf5, 0xd3, 0x04, 0x00, 0x8c, 0x4f,
+ 0x08, 0x00, 0xe4, 0x21, 0x08, 0x00, 0x83, 0x50, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x70,
+ 0x7c, 0x1a, 0x00, 0x60, 0x19, 0x08, 0x00, 0xe8, 0x57, 0x08, 0x00, 0x11, 0x01, 0x0d, 0x00,
+ 0x57, 0x4a, 0x05, 0x00, 0x46, 0x7f, 0x1a, 0x00, 0x61, 0x48, 0x05, 0x00, 0x70, 0xb5, 0x9f,
+ 0x48, 0x00, 0x78, 0x01, 0x28, 0x27, 0xd0, 0x00, 0x28, 0x12, 0xd1, 0x9d, 0x4d, 0x28, 0x1c,
+ 0x04, 0x21, 0x01, 0x24, 0xa6, 0x46, 0x9b, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x00, 0x28, 0x2d,
+ 0xd1, 0x03, 0x21, 0xc9, 0x01, 0x28, 0x1c, 0x0a, 0x1c, 0xa6, 0x46, 0x97, 0x4b, 0xfe, 0x44,
+ 0x18, 0x47, 0x70, 0xbd, 0x02, 0x28, 0x22, 0xd1, 0x95, 0x48, 0x41, 0x88, 0x09, 0x09, 0x1e,
+ 0xd2, 0x41, 0x88, 0x49, 0x08, 0x1b, 0xd2, 0x42, 0x88, 0x10, 0x21, 0x11, 0x43, 0x41, 0x80,
+ 0x02, 0x88, 0x01, 0x21,
+
+ 0x01, 0x05, 0xff, 0xff, 0x8e, 0x65, 0x08, 0x00, 0xfa, 0x89, 0x03, 0x11, 0x43, 0x01, 0x80,
+ 0x70, 0xbd, 0xe4, 0x4e, 0x30, 0x1c, 0x00, 0x25, 0x29, 0x1c, 0x01, 0x24, 0xa6, 0x46, 0xe3,
+ 0x4a, 0xfe, 0x44, 0x10, 0x47, 0xe0, 0x49, 0x08, 0x80, 0x30, 0x1c, 0x1c, 0x21, 0x2a, 0x1c,
+ 0xa6, 0x46, 0xdf, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x70, 0xbd, 0x30, 0xb5, 0xdb, 0x4d, 0x28,
+ 0x1c, 0x01, 0x88, 0x7d, 0x48, 0x00, 0x78, 0x01, 0x28, 0x26, 0xd0, 0x00, 0x28, 0x12, 0xd1,
+ 0x7b, 0x4d, 0x28, 0x1c, 0x04, 0x21, 0x01, 0x24, 0xa6, 0x46, 0x7a, 0x4a, 0xfe, 0x44, 0x10,
+ 0x47, 0x00, 0x28, 0x26, 0xd1, 0x28, 0x1c, 0x00, 0x21, 0x03, 0x22, 0xd2, 0x01, 0xa6, 0x46,
+ 0x76, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x30, 0xbd, 0x02, 0x28, 0x1b, 0xd1, 0x74, 0x48, 0x41,
+ 0x88, 0x09, 0x09, 0x17, 0xd2, 0x41, 0x88, 0x49, 0x08, 0x14, 0xd2, 0x10, 0x22, 0x41, 0x88,
+ 0x91, 0x43, 0x41, 0x80, 0x01, 0x21, 0x89, 0x03, 0x04, 0x88, 0x8c, 0x43, 0x0a, 0xe0, 0xd7,
+ 0x4c, 0xa1, 0x42, 0x08, 0xd0, 0xc1, 0x48, 0x00, 0x22, 0x01, 0x23, 0x9e, 0x46, 0xc2, 0x4b,
+ 0xfe, 0x44, 0x18, 0x47, 0x28, 0x1c, 0x04, 0x80, 0x30, 0xbd, 0x00, 0xb5, 0x61, 0x49, 0x09,
+ 0x78, 0x01, 0x29, 0x08, 0xd1, 0x40, 0x69, 0x00, 0x7a, 0x15, 0x28, 0x04, 0xd1, 0x01, 0x20,
+ 0x86, 0x46, 0xe0, 0x48, 0xfe, 0x44, 0x00, 0x47, 0x00, 0xbd, 0xf0, 0xb5, 0x04, 0x69, 0xc7,
+ 0x26, 0x30, 0x5d, 0x04, 0x28, 0x24, 0xd1, 0xc8, 0x25, 0x28, 0x5d, 0x18, 0x28, 0x03, 0xd1,
+ 0x6a, 0x20, 0x00, 0x5d, 0x04, 0x28, 0x16, 0xd0, 0x28, 0x5d, 0x19, 0x28, 0x19, 0xd1, 0xce,
+ 0x20, 0x00, 0x5d, 0x16, 0x28, 0x15, 0xd1, 0xb5, 0x27, 0x38, 0x5d, 0x01, 0x21, 0x8e, 0x46,
+ 0xea, 0x4a, 0xfe, 0x44,
+
+ 0x01, 0x05, 0xff, 0xff, 0x88, 0x66, 0x08, 0x00, 0xfa, 0x10, 0x47, 0x00, 0x22, 0x38, 0x5d,
+ 0x60, 0x21, 0x41, 0x43, 0xe8, 0x48, 0x42, 0x54, 0x32, 0x55, 0x2a, 0x55, 0xf0, 0xbd, 0x20,
+ 0x1c, 0x01, 0x21, 0x8e, 0x46, 0xe5, 0x49, 0xfe, 0x44, 0x08, 0x47, 0xf0, 0xbd, 0xf0, 0xb5,
+ 0x06, 0x1c, 0xb5, 0x69, 0xb4, 0x8a, 0x42, 0x48, 0x02, 0x78, 0x00, 0x27, 0xe0, 0x49, 0xe1,
+ 0x48, 0x8c, 0x42, 0x0e, 0xdc, 0xe0, 0x4a, 0x8c, 0x42, 0x51, 0xd0, 0x71, 0x39, 0x61, 0x1a,
+ 0x57, 0xd0, 0x01, 0x39, 0x4c, 0xd0, 0x43, 0x39, 0x34, 0xd0, 0x29, 0x39, 0x51, 0xd0, 0x01,
+ 0x39, 0x57, 0xd0, 0xf0, 0xbd, 0x48, 0x31, 0x61, 0x1a, 0x23, 0xd0, 0x0b, 0x39, 0x34, 0xd0,
+ 0x01, 0x39, 0x14, 0xd0, 0x01, 0x39, 0x64, 0xd1, 0xe1, 0x48, 0x00, 0x78, 0x02, 0x28, 0x2a,
+ 0xd1, 0xe8, 0x7a, 0x00, 0x07, 0x00, 0x0f, 0xdf, 0x49, 0x0a, 0x1c, 0xb6, 0x3a, 0x10, 0x70,
+ 0x02, 0x01, 0x02, 0x43, 0x12, 0x01, 0x02, 0x43, 0x12, 0x01, 0x02, 0x43, 0x0a, 0x80, 0x20,
+ 0xe0, 0x01, 0x2a, 0x01, 0xd0, 0x04, 0x2a, 0x1c, 0xd1, 0x28, 0x1c, 0x01, 0x21, 0x8e, 0x46,
+ 0xe8, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x15, 0xe0, 0x0e, 0x21, 0x01, 0x22, 0x96, 0x46, 0xe6,
+ 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x01, 0x28, 0x08, 0xd0, 0xf0, 0xbd, 0x0d, 0x21, 0x01, 0x22,
+ 0x96, 0x46, 0xe1, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x01, 0x28, 0x35, 0xd1, 0x0c, 0x27, 0x02,
+ 0xe0, 0xe8, 0x7a, 0xde, 0x49, 0x08, 0x70, 0x28, 0x1c, 0x21, 0x1c, 0x3a, 0x1c, 0x01, 0x23,
+ 0x9e, 0x46, 0xdc, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x24, 0xe0, 0x10, 0x1c, 0x39, 0x1c, 0x06,
+ 0x22, 0x01, 0x23, 0x9e, 0x46, 0xf0, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0xf0, 0xbd, 0x10, 0x1c,
+ 0x03, 0x21, 0x06, 0x22,
+
+ 0x01, 0x05, 0xff, 0xff, 0x82, 0x67, 0x08, 0x00, 0xfa, 0x01, 0x23, 0x9e, 0x46, 0xec, 0x4b,
+ 0xfe, 0x44, 0x18, 0x47, 0xeb, 0x48, 0x00, 0x68, 0x00, 0x28, 0x12, 0xd0, 0x04, 0x20, 0x01,
+ 0x24, 0xa6, 0x46, 0xe9, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x47, 0x21, 0x09, 0x02, 0x01, 0x80,
+ 0x85, 0x80, 0x29, 0x0c, 0xc1, 0x80, 0xa6, 0x46, 0xe5, 0x49, 0xfe, 0x44, 0x08, 0x47, 0xdf,
+ 0x48, 0x9e, 0x30, 0x30, 0x62, 0xf0, 0xbd, 0xe8, 0x57, 0x08, 0x00, 0x7e, 0x7c, 0x1a, 0x00,
+ 0x43, 0x4a, 0x05, 0x00, 0xdb, 0x4a, 0x05, 0x00, 0x60, 0x7a, 0x1a, 0x00, 0xf8, 0xb5, 0x06,
+ 0x1c, 0xb5, 0x69, 0xb0, 0x8a, 0xdb, 0x49, 0x40, 0x1a, 0x00, 0xd1, 0x99, 0xe0, 0x65, 0x49,
+ 0x89, 0x09, 0x40, 0x1a, 0x69, 0xd0, 0xd8, 0x49, 0x40, 0x1a, 0xa2, 0x49, 0x25, 0xd0, 0x07,
+ 0x38, 0x00, 0xd0, 0x96, 0xe0, 0x0e, 0x20, 0x40, 0x19, 0x06, 0x22, 0xaa, 0x80, 0x08, 0x22,
+ 0x6a, 0x80, 0x09, 0x78, 0x02, 0x29, 0x0c, 0xd1, 0xd1, 0x49, 0x01, 0x24, 0xa6, 0x46, 0xd1,
+ 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x00, 0x21, 0xa6, 0x46, 0xce, 0x4a, 0xfe, 0x44, 0x10, 0x47,
+ 0x00, 0x22, 0x00, 0xe0, 0x0c, 0x22, 0x28, 0x1c, 0x87, 0x21, 0x89, 0x00, 0x01, 0x23, 0x9e,
+ 0x46, 0xca, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0xc9, 0x48, 0xfa, 0x30, 0x30, 0x62, 0xf8, 0xbd,
+ 0x08, 0x78, 0x02, 0x28, 0x33, 0xd1, 0x0b, 0x20, 0x40, 0x19, 0x01, 0x24, 0xa6, 0x46, 0xef,
+ 0x49, 0xfe, 0x44, 0x08, 0x47, 0x00, 0x90, 0xa6, 0x46, 0xc2, 0x49, 0xfe, 0x44, 0x08, 0x47,
+ 0x00, 0x06, 0x00, 0x0e, 0xa6, 0x46, 0xc0, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x07, 0x1c, 0x0e,
+ 0x20, 0x40, 0x19, 0x00, 0x99, 0xa6, 0x46, 0xed, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x06, 0x21,
+ 0xa9, 0x80, 0x07, 0x21,
+
+ 0x01, 0x05, 0xff, 0xff, 0x7c, 0x68, 0x08, 0x00, 0xfa, 0x69, 0x80, 0x00, 0x2f, 0x0b, 0xd0,
+ 0x00, 0x99, 0xc9, 0x0a, 0x08, 0xd3, 0x3a, 0x21, 0xc9, 0x19, 0x05, 0x22, 0xa6, 0x46, 0xe6,
+ 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x00, 0x22, 0x08, 0xe0, 0x00, 0x21, 0x05, 0x22, 0xa6, 0x46,
+ 0xe3, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x02, 0x22, 0x00, 0xe0, 0x0c, 0x22, 0x28, 0x1c, 0xe1,
+ 0x49, 0x01, 0x23, 0x9e, 0x46, 0xe0, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0xbb, 0xe7, 0x2f, 0x1c,
+ 0x06, 0x20, 0xa8, 0x80, 0x0e, 0x20, 0x40, 0x19, 0x40, 0x21, 0x01, 0x24, 0xa6, 0x46, 0xea,
+ 0x4a, 0xfe, 0x44, 0x10, 0x47, 0xea, 0x48, 0x01, 0x1c, 0xcf, 0x22, 0x0a, 0x72, 0x08, 0x31,
+ 0x61, 0x22, 0x0a, 0x74, 0x19, 0x21, 0x02, 0x78, 0xba, 0x73, 0x01, 0x37, 0x01, 0x30, 0x01,
+ 0x39, 0xf9, 0xd1, 0x04, 0x20, 0xe3, 0x49, 0x0a, 0x78, 0xba, 0x73, 0x01, 0x37, 0x01, 0x31,
+ 0x01, 0x38, 0xf9, 0xd1, 0x40, 0x20, 0x68, 0x80, 0x28, 0x1c, 0x81, 0x21, 0x49, 0x00, 0x00,
+ 0x22, 0xa6, 0x46, 0x92, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x8f, 0xe7, 0x4b, 0x48, 0x00, 0x21,
+ 0x06, 0x22, 0x01, 0x23, 0x9e, 0x46, 0x86, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0xf8, 0xbd, 0xc0,
+ 0x46, 0x58, 0x74, 0x1a, 0x00, 0xb0, 0x63, 0x08, 0x00, 0x6b, 0x4a, 0x05, 0x00, 0x15, 0x49,
+ 0x05, 0x00, 0x30, 0xb5, 0x05, 0x1c, 0xeb, 0x48, 0x00, 0x78, 0x00, 0x28, 0x17, 0xd1, 0x01,
+ 0x24, 0xa6, 0x46, 0xe9, 0x48, 0xfe, 0x44, 0x00, 0x47, 0x00, 0x28, 0x0b, 0xd1, 0xa6, 0x46,
+ 0xe7, 0x48, 0xfe, 0x44, 0x00, 0x47, 0x01, 0x28, 0x05, 0xd0, 0xa6, 0x46, 0xe5, 0x48, 0xfe,
+ 0x44, 0x00, 0x47, 0x01, 0x28, 0x04, 0xd1, 0x00, 0x20, 0x28, 0x60, 0xe3, 0x48, 0x52, 0x30,
+ 0x28, 0x62, 0x30, 0xbd,
+
+ 0x01, 0x05, 0xff, 0xff, 0x76, 0x69, 0x08, 0x00, 0xfa, 0xc0, 0x46, 0xff, 0xff, 0x00, 0x00,
+ 0x70, 0xb5, 0xe9, 0x49, 0x80, 0x8a, 0x88, 0x42, 0x20, 0xd1, 0xe8, 0x4b, 0xe8, 0x4a, 0x00,
+ 0x21, 0x40, 0x20, 0x80, 0x5c, 0x00, 0x28, 0x0e, 0xd0, 0x18, 0x78, 0xe6, 0x4e, 0x8c, 0x00,
+ 0xe6, 0x4d, 0x2c, 0x19, 0x25, 0x6a, 0xb5, 0x42, 0x0b, 0xd8, 0x64, 0x68, 0xb4, 0x42, 0x08,
+ 0xd8, 0x01, 0x24, 0x8c, 0x40, 0xa0, 0x43, 0x18, 0x70, 0xa8, 0x32, 0x01, 0x31, 0x07, 0x29,
+ 0xe8, 0xdb, 0x70, 0xbd, 0x0a, 0x06, 0x12, 0x0e, 0x01, 0x21, 0x91, 0x40, 0x01, 0x43, 0x19,
+ 0x70, 0x70, 0xbd, 0xc0, 0x46, 0xe7, 0x46, 0x04, 0x00, 0x70, 0xb5, 0x05, 0x1c, 0xae, 0x69,
+ 0x47, 0x20, 0x00, 0x02, 0x31, 0x88, 0x09, 0x12, 0x09, 0x02, 0x81, 0x42, 0x23, 0xd1, 0x55,
+ 0x48, 0x00, 0x68, 0x00, 0x28, 0x0e, 0xd1, 0xf0, 0x88, 0x00, 0x04, 0xb1, 0x88, 0x08, 0x43,
+ 0x01, 0x24, 0xa6, 0x46, 0x4e, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x30, 0x1c, 0xa6, 0x46, 0xcd,
+ 0x49, 0xfe, 0x44, 0x08, 0x47, 0x0b, 0xe0, 0x7d, 0x20, 0xc0, 0x00, 0x01, 0x24, 0xa6, 0x46,
+ 0xcb, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x30, 0x1c, 0xa6, 0x46, 0x49, 0x49, 0xfe, 0x44, 0x08,
+ 0x47, 0xc6, 0x49, 0x05, 0x20, 0x00, 0x02, 0x40, 0x18, 0x28, 0x62, 0x70, 0xbd, 0xc0, 0x46,
+ 0xc9, 0xa2, 0x00, 0x00, 0x76, 0xa0, 0x1b, 0x00, 0x6d, 0x97, 0x00, 0x00, 0x88, 0xfd, 0x00,
+ 0x00, 0xc0, 0x61, 0x1a, 0x00, 0x6a, 0x0a, 0x1a, 0x00, 0x70, 0xb5, 0x05, 0x1c, 0x6e, 0x69,
+ 0x20, 0x48, 0x00, 0x78, 0x01, 0x28, 0x0f, 0xd1, 0x03, 0x20, 0xbb, 0x49, 0x03, 0x39, 0x01,
+ 0x24, 0xa6, 0x46, 0xba, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x30, 0x1c, 0xa6, 0x46, 0xb3, 0x49,
+ 0xfe, 0x44, 0x08, 0x47,
+
+ 0x01, 0x05, 0xff, 0xff, 0x70, 0x6a, 0x08, 0x00, 0xfa, 0xb4, 0x48, 0x1a, 0x30, 0x28, 0x62,
+ 0x70, 0xbd, 0x41, 0x10, 0x08, 0x00, 0x4c, 0xa6, 0x1b, 0x00, 0x30, 0xb5, 0x04, 0x1c, 0xa1,
+ 0x69, 0x00, 0x29, 0x1c, 0xd0, 0x20, 0x69, 0x02, 0x78, 0xff, 0x2a, 0x18, 0xd0, 0x8a, 0x88,
+ 0x89, 0x18, 0x08, 0x22, 0xca, 0x42, 0x13, 0xd0, 0x39, 0x22, 0x12, 0x5c, 0x0a, 0x2a, 0x0f,
+ 0xd1, 0x09, 0x7a, 0x4a, 0x08, 0x0f, 0x2a, 0x0b, 0xd1, 0xc9, 0x07, 0xc9, 0x0f, 0x0f, 0x22,
+ 0x2a, 0x23, 0x01, 0x25, 0xae, 0x46, 0xa5, 0x4d, 0xfe, 0x44, 0x28, 0x47, 0xa5, 0x48, 0xf0,
+ 0x30, 0x20, 0x62, 0x30, 0xbd, 0xc0, 0x46, 0x81, 0x08, 0x18, 0x00, 0x2f, 0x4a, 0x05, 0x00,
+ 0xfb, 0x63, 0x08, 0x00, 0x99, 0x77, 0x05, 0x00, 0x70, 0xb5, 0x85, 0xb0, 0x05, 0x1c, 0x68,
+ 0x69, 0x9d, 0x4e, 0x01, 0x24, 0x34, 0x70, 0x01, 0x7a, 0x89, 0x06, 0x09, 0x0e, 0x9b, 0x4a,
+ 0x52, 0x58, 0x69, 0x46, 0xa6, 0x46, 0xfe, 0x44, 0x10, 0x47, 0x00, 0x20, 0x30, 0x70, 0x68,
+ 0x46, 0x01, 0x7c, 0x6e, 0x46, 0x72, 0x7c, 0x14, 0x20, 0xa6, 0x46, 0x95, 0x4b, 0xfe, 0x44,
+ 0x18, 0x47, 0x68, 0x46, 0x01, 0x7c, 0x06, 0x29, 0x04, 0xd0, 0xa6, 0x46, 0x92, 0x49, 0xfe,
+ 0x44, 0x08, 0x47, 0x04, 0xe0, 0x91, 0x4a, 0x34, 0x21, 0x88, 0x5c, 0x01, 0x30, 0x88, 0x54,
+ 0x90, 0x48, 0x4e, 0x30, 0x28, 0x62, 0x05, 0xb0, 0x70, 0xbd, 0x81, 0x60, 0x00, 0x00, 0x91,
+ 0x48, 0x05, 0x00, 0x2c, 0x51, 0x08, 0x00, 0x9b, 0x60, 0x04, 0x00, 0xe9, 0x3f, 0x05, 0x00,
+ 0x03, 0x0c, 0x00, 0x00, 0x13, 0x10, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, 0x53, 0x2c, 0x00,
+ 0x00, 0xc1, 0x50, 0x02, 0x00, 0x25, 0x00, 0x00, 0x00, 0x71, 0x8b, 0x04, 0x00, 0x9b, 0x8b,
+ 0x04, 0x00, 0xf0, 0xb5,
+
+ 0x01, 0x05, 0xff, 0xff, 0x6a, 0x6b, 0x08, 0x00, 0xfa, 0x05, 0x1c, 0x6c, 0x69, 0x2e, 0x69,
+ 0x28, 0x7f, 0x17, 0x21, 0x40, 0x1a, 0x0f, 0xd0, 0x0d, 0x38, 0x53, 0xd1, 0x01, 0x24, 0xa6,
+ 0x46, 0x7b, 0x48, 0xfe, 0x44, 0x00, 0x47, 0xa6, 0x46, 0x7a, 0x49, 0xfe, 0x44, 0x08, 0x47,
+ 0x00, 0x28, 0x48, 0xd0, 0x7a, 0x48, 0xb2, 0x38, 0x42, 0xe0, 0xff, 0x20, 0x7d, 0x30, 0x07,
+ 0x19, 0x30, 0x78, 0x38, 0x70, 0x39, 0x78, 0x02, 0x20, 0x08, 0x40, 0x38, 0x70, 0x01, 0x36,
+ 0x30, 0x1c, 0x01, 0x21, 0x8e, 0x46, 0x15, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x78, 0x80, 0x02,
+ 0x36, 0x30, 0x1c, 0x01, 0x21, 0x8e, 0x46, 0x11, 0x49, 0xfe, 0x44, 0x08, 0x47, 0xb8, 0x80,
+ 0xff, 0x20, 0x83, 0x30, 0x04, 0x19, 0x02, 0x36, 0x30, 0x1c, 0x01, 0x21, 0x8e, 0x46, 0x0b,
+ 0x49, 0xfe, 0x44, 0x08, 0x47, 0x20, 0x80, 0x02, 0x36, 0x30, 0x1c, 0x01, 0x21, 0x8e, 0x46,
+ 0x07, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x60, 0x80, 0xb8, 0x88, 0x79, 0x88, 0x01, 0x43, 0x49,
+ 0x08, 0x10, 0xd2, 0x21, 0x88, 0x00, 0x29, 0x0d, 0xd0, 0x42, 0x08, 0x91, 0x42, 0x0a, 0xdc,
+ 0x01, 0xe0, 0x73, 0x2c, 0x00, 0x00, 0x08, 0x28, 0x02, 0xda, 0xff, 0xe7, 0x5a, 0x48, 0x03,
+ 0xe0, 0x59, 0x48, 0x12, 0x30, 0x00, 0xe0, 0x58, 0x48, 0x56, 0x49, 0x40, 0x18, 0x28, 0x62,
+ 0xf0, 0xbd, 0xc0, 0x46, 0x69, 0x2c, 0x00, 0x00, 0x21, 0xa7, 0x05, 0x00, 0xc1, 0xad, 0x05,
+ 0x00, 0x15, 0x20, 0x00, 0x00, 0xa7, 0x50, 0x02, 0x00, 0x10, 0xb5, 0x56, 0x48, 0x00, 0x78,
+ 0x01, 0x28, 0x01, 0xd0, 0x04, 0x28, 0x08, 0xd1, 0x01, 0x24, 0xa6, 0x46, 0x4d, 0x48, 0xfe,
+ 0x44, 0x00, 0x47, 0xa6, 0x46, 0x4c, 0x48, 0xfe, 0x44, 0x00, 0x47, 0x01, 0x24, 0xa6, 0x46,
+ 0x4a, 0x48, 0xfe, 0x44,
+
+ 0x01, 0x05, 0xff, 0xff, 0x64, 0x6c, 0x08, 0x00, 0xfa, 0x00, 0x47, 0xa6, 0x46, 0x49, 0x48,
+ 0xfe, 0x44, 0x00, 0x47, 0xa6, 0x46, 0x48, 0x48, 0xfe, 0x44, 0x00, 0x47, 0x10, 0xbd, 0x91,
+ 0x1c, 0x04, 0x00, 0xb3, 0x11, 0x08, 0x00, 0xf0, 0x63, 0x08, 0x00, 0x10, 0xb5, 0x45, 0x4c,
+ 0x45, 0x48, 0x00, 0x78, 0x21, 0x78, 0x81, 0x42, 0x0d, 0xdd, 0x07, 0x21, 0x43, 0x48, 0x00,
+ 0x22, 0x40, 0x23, 0x1b, 0x5c, 0x00, 0x2b, 0x02, 0xd0, 0x52, 0x1c, 0x12, 0x06, 0x12, 0x0e,
+ 0xa8, 0x30, 0x01, 0x39, 0xf5, 0xd1, 0x22, 0x70, 0x10, 0xbd, 0xf0, 0xb5, 0x01, 0x24, 0xa6,
+ 0x46, 0x2e, 0x48, 0xfe, 0x44, 0x00, 0x47, 0xa6, 0x46, 0x2d, 0x49, 0xfe, 0x44, 0x08, 0x47,
+ 0x00, 0x28, 0x10, 0xd0, 0x11, 0x27, 0x09, 0x26, 0x36, 0x4d, 0x3e, 0x20, 0x40, 0x5d, 0xff,
+ 0x28, 0x06, 0xd0, 0x3b, 0x20, 0x47, 0x55, 0x28, 0x1c, 0xa6, 0x46, 0x33, 0x49, 0xfe, 0x44,
+ 0x08, 0x47, 0x50, 0x35, 0x01, 0x3e, 0xf1, 0xd1, 0xf0, 0xbd, 0xef, 0x22, 0x08, 0x00, 0x5d,
+ 0x8b, 0x04, 0x00, 0x7b, 0x5f, 0x03, 0x00, 0xab, 0xb9, 0x03, 0x00, 0xbf, 0x70, 0x05, 0x00,
+ 0x00, 0xb5, 0x2b, 0x48, 0x00, 0x88, 0x02, 0x28, 0x01, 0xda, 0x01, 0x21, 0x02, 0xe0, 0x40,
+ 0x1e, 0x01, 0x04, 0x09, 0x0c, 0x27, 0x48, 0x00, 0x22, 0x01, 0x23, 0x9e, 0x46, 0x26, 0x4b,
+ 0xfe, 0x44, 0x18, 0x47, 0x00, 0xbd, 0x76, 0x81, 0x00, 0x00, 0xb5, 0x63, 0x08, 0x00, 0x60,
+ 0x19, 0x08, 0x00, 0x10, 0x27, 0x00, 0x00, 0xcc, 0x24, 0x08, 0x00, 0x2d, 0x61, 0x04, 0x00,
+ 0xd5, 0xb4, 0x02, 0x00, 0xbb, 0x16, 0x04, 0x00, 0x5d, 0xf0, 0x03, 0x00, 0xae, 0x05, 0x00,
+ 0x00, 0xf5, 0xd3, 0x04, 0x00, 0x55, 0xf6, 0x00, 0x00, 0x5b, 0xf5, 0x00, 0x00, 0xfc, 0x63,
+ 0x08, 0x00, 0xb4, 0x8a,
+
+ 0x01, 0x05, 0xff, 0xff, 0x5e, 0x6d, 0x08, 0x00, 0xfa, 0x06, 0x00, 0xa9, 0xd3, 0x04, 0x00,
+ 0x61, 0x97, 0x04, 0x00, 0x28, 0x19, 0x08, 0x00, 0x57, 0x98, 0x04, 0x00, 0x37, 0x98, 0x01,
+ 0x00, 0x37, 0x9b, 0x01, 0x00, 0x0d, 0xe2, 0x00, 0x00, 0xca, 0x0c, 0x00, 0x00, 0x3a, 0x0e,
+ 0x00, 0x00, 0x33, 0x64, 0x08, 0x00, 0xc9, 0x64, 0x08, 0x00, 0xb1, 0x6c, 0x08, 0x00, 0x01,
+ 0x6d, 0x08, 0x00, 0x85, 0x6c, 0x08, 0x00, 0xe8, 0x57, 0x08, 0x00, 0xbf, 0x0f, 0x08, 0x00,
+ 0x83, 0x50, 0x08, 0x00, 0x60, 0x19, 0x08, 0x00, 0xf4, 0x46, 0x08, 0x00, 0xa5, 0x1e, 0x02,
+ 0x00, 0x8c, 0x18, 0x08, 0x00, 0x36, 0x02, 0x1a, 0x00, 0x15, 0x49, 0x05, 0x00, 0xf0, 0xb5,
+ 0x87, 0xb0, 0x06, 0x1c, 0xf0, 0x4d, 0x28, 0x78, 0x01, 0x28, 0x02, 0xd1, 0x01, 0x27, 0xff,
+ 0x03, 0x01, 0xe0, 0x7d, 0x27, 0x3f, 0x02, 0xed, 0x48, 0x00, 0x21, 0x01, 0x24, 0xa6, 0x46,
+ 0xd5, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0xe9, 0x49, 0x48, 0x43, 0x39, 0x1c, 0xa6, 0x46, 0xe9,
+ 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x01, 0x91, 0x28, 0x78, 0x01, 0x28, 0x02, 0xd1, 0x01, 0x21,
+ 0xc9, 0x03, 0x01, 0xe0, 0x7d, 0x21, 0x09, 0x02, 0xee, 0x48, 0xa6, 0x46, 0xe2, 0x4a, 0xfe,
+ 0x44, 0x10, 0x47, 0x02, 0x91, 0x76, 0x69, 0xf0, 0x7a, 0x03, 0x90, 0x30, 0x1c, 0x21, 0x1c,
+ 0xa6, 0x46, 0xf2, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x04, 0x90, 0x30, 0x1c, 0x05, 0x21, 0xa6,
+ 0x46, 0xee, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x05, 0x90, 0x30, 0x7f, 0x06, 0x90, 0xf7, 0x7e,
+ 0x00, 0x97, 0x06, 0x9b, 0x03, 0x20, 0xf1, 0x49, 0xde, 0x31, 0x04, 0x9a, 0xa6, 0x46, 0xe8,
+ 0x4e, 0xfe, 0x44, 0x30, 0x47, 0x03, 0x98, 0xff, 0x28, 0x04, 0xd0, 0x03, 0x98, 0xa6, 0x46,
+ 0xe5, 0x49, 0xfe, 0x44,
+
+ 0x01, 0x05, 0xff, 0xff, 0x58, 0x6e, 0x08, 0x00, 0xfa, 0x08, 0x47, 0x04, 0x98, 0x40, 0x1c,
+ 0x07, 0xd0, 0x04, 0x98, 0x03, 0x99, 0x06, 0x9a, 0x3b, 0x1c, 0xa6, 0x46, 0xe1, 0x4e, 0xfe,
+ 0x44, 0x30, 0x47, 0xe5, 0x48, 0x00, 0x78, 0x02, 0x28, 0x00, 0xd0, 0xb2, 0xe0, 0x28, 0x78,
+ 0xdd, 0x4e, 0x01, 0x2f, 0x52, 0xd0, 0xb1, 0x89, 0x01, 0x28, 0x02, 0xd1, 0x01, 0x20, 0xc0,
+ 0x03, 0x01, 0xe0, 0x7d, 0x20, 0x00, 0x02, 0x04, 0x99, 0x48, 0x43, 0xd8, 0x49, 0x08, 0x18,
+ 0xbb, 0x49, 0xa6, 0x46, 0xd7, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0xb1, 0x81, 0x28, 0x78, 0x01,
+ 0x28, 0x02, 0xd1, 0x01, 0x20, 0xc0, 0x03, 0x01, 0xe0, 0x7d, 0x20, 0x00, 0x02, 0xd2, 0x4d,
+ 0x0f, 0x27, 0x29, 0x88, 0x39, 0x40, 0x2a, 0x88, 0x12, 0x09, 0x3a, 0x40, 0x8a, 0x42, 0x04,
+ 0xdd, 0x29, 0x88, 0x09, 0x11, 0x09, 0x07, 0x0f, 0x0f, 0x01, 0xe0, 0x29, 0x88, 0x0f, 0x40,
+ 0x04, 0x99, 0x41, 0x43, 0xc7, 0x48, 0x40, 0x18, 0xaa, 0x49, 0xa6, 0x46, 0xc6, 0x4a, 0xfe,
+ 0x44, 0x10, 0x47, 0x30, 0x1c, 0x9c, 0x30, 0x00, 0x88, 0x1f, 0x22, 0x10, 0x40, 0x40, 0x18,
+ 0xa9, 0x89, 0x11, 0x40, 0x08, 0x18, 0x31, 0x8a, 0x08, 0x18, 0xe4, 0x49, 0x09, 0x88, 0x09,
+ 0x0a, 0x08, 0x18, 0xe2, 0x49, 0x09, 0x89, 0x09, 0x0a, 0x08, 0x18, 0x39, 0x18, 0x06, 0x98,
+ 0x40, 0x18, 0x05, 0x30, 0x01, 0x04, 0x09, 0x0c, 0x9c, 0x48, 0x00, 0x22, 0xa6, 0x46, 0xed,
+ 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x50, 0xe0, 0x31, 0x88, 0x01, 0x28, 0x02, 0xd1, 0x01, 0x20,
+ 0xc0, 0x03, 0x01, 0xe0, 0x7d, 0x20, 0x00, 0x02, 0x04, 0x99, 0x48, 0x43, 0xae, 0x49, 0x08,
+ 0x18, 0x91, 0x49, 0xa6, 0x46, 0xad, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x31, 0x80, 0x28, 0x78,
+ 0x01, 0x28, 0x02, 0xd1,
+
+ 0x01, 0x05, 0xff, 0xff, 0x52, 0x6f, 0x08, 0x00, 0xfa, 0x01, 0x20, 0xc0, 0x03, 0x01, 0xe0,
+ 0x7d, 0x20, 0x00, 0x02, 0xa8, 0x4d, 0x0f, 0x27, 0xa9, 0x88, 0x09, 0x09, 0x39, 0x40, 0xaa,
+ 0x88, 0x3a, 0x40, 0x8a, 0x42, 0x03, 0xdd, 0xa9, 0x88, 0x09, 0x07, 0x0f, 0x0f, 0x02, 0xe0,
+ 0xa9, 0x88, 0x09, 0x09, 0x0f, 0x40, 0x04, 0x99, 0x41, 0x43, 0x9d, 0x48, 0x40, 0x18, 0x80,
+ 0x49, 0xa6, 0x46, 0x9c, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x30, 0x89, 0x1f, 0x22, 0x10, 0x40,
+ 0x40, 0x18, 0xb1, 0x88, 0x11, 0x40, 0x08, 0x18, 0x29, 0x89, 0x11, 0x40, 0x08, 0x18, 0xbb,
+ 0x49, 0x09, 0x88, 0x09, 0x0a, 0x08, 0x18, 0xb9, 0x49, 0x09, 0x89, 0x09, 0x0a, 0x08, 0x18,
+ 0x39, 0x18, 0x06, 0x98, 0x40, 0x18, 0x05, 0x30, 0x01, 0x04, 0x09, 0x0c, 0x73, 0x48, 0x00,
+ 0x22, 0xa6, 0x46, 0xc4, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x01, 0x98, 0x02, 0x99, 0x41, 0x18,
+ 0x8c, 0x48, 0x40, 0x18, 0xde, 0x49, 0xa6, 0x46, 0x88, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x07,
+ 0xe0, 0x88, 0x48, 0x01, 0x99, 0x40, 0x18, 0xda, 0x49, 0xa6, 0x46, 0x84, 0x4a, 0xfe, 0x44,
+ 0x10, 0x47, 0xc8, 0x1c, 0xd6, 0x49, 0x08, 0x80, 0xd7, 0x48, 0x05, 0x99, 0x49, 0x1c, 0x01,
+ 0xd0, 0x59, 0x30, 0x00, 0xe0, 0x61, 0x30, 0x07, 0xb0, 0xf0, 0xbd, 0x70, 0xb5, 0x06, 0x1c,
+ 0x01, 0x25, 0xae, 0x46, 0xeb, 0x48, 0xfe, 0x44, 0x00, 0x47, 0xeb, 0x48, 0xae, 0x46, 0xeb,
+ 0x49, 0xfe, 0x44, 0x08, 0x47, 0xea, 0x48, 0x00, 0x78, 0xea, 0x4c, 0x00, 0x28, 0x04, 0xd1,
+ 0xae, 0x46, 0xe9, 0x48, 0xfe, 0x44, 0x00, 0x47, 0x03, 0xe0, 0xae, 0x46, 0xe8, 0x49, 0xfe,
+ 0x44, 0x08, 0x47, 0x60, 0x62, 0x74, 0x61, 0x60, 0x6a, 0x70, 0x60, 0xe5, 0x48, 0x4f, 0x30,
+ 0x70, 0xbd, 0xc0, 0x1e,
+
+ 0x01, 0x05, 0xff, 0xff, 0x4c, 0x70, 0x08, 0x00, 0xfa, 0x02, 0xd0, 0x02, 0x38, 0x02, 0xd0,
+ 0x03, 0xe0, 0xe2, 0x48, 0xf7, 0x46, 0xe2, 0x48, 0xf7, 0x46, 0x00, 0x20, 0xc0, 0x43, 0xf7,
+ 0x46, 0xf0, 0xb5, 0xc2, 0x69, 0x11, 0x06, 0x09, 0x0e, 0xd9, 0x4c, 0x27, 0x68, 0x66, 0x4b,
+ 0x1b, 0x78, 0xdd, 0x4e, 0x02, 0x2b, 0x03, 0xd0, 0x42, 0x60, 0x30, 0x1c, 0x51, 0x30, 0xf0,
+ 0xbd, 0x08, 0x1c, 0x01, 0x25, 0xae, 0x46, 0xea, 0x49, 0xfe, 0x44, 0x08, 0x47, 0xe1, 0x69,
+ 0xd4, 0x48, 0x02, 0x1c, 0x52, 0x00, 0x91, 0x42, 0x01, 0xd0, 0x81, 0x42, 0x1e, 0xd1, 0xa0,
+ 0x6a, 0xeb, 0x49, 0x88, 0x42, 0x04, 0xd0, 0xea, 0x49, 0x88, 0x42, 0x03, 0xd1, 0xea, 0x48,
+ 0x00, 0xe0, 0xea, 0x48, 0x20, 0x60, 0x36, 0x48, 0x1a, 0x30, 0x0c, 0x21, 0xae, 0x46, 0xe9,
+ 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x41, 0x1c, 0x20, 0x68, 0xae, 0x46, 0x4d, 0x4a, 0xfe, 0x44,
+ 0x10, 0x47, 0x21, 0x61, 0xae, 0x46, 0xe2, 0x48, 0xfe, 0x44, 0x00, 0x47, 0x27, 0x60, 0x03,
+ 0xe0, 0xae, 0x46, 0xdf, 0x48, 0xfe, 0x44, 0x00, 0x47, 0x30, 0x1c, 0x59, 0x30, 0xf0, 0xbd,
+ 0x40, 0x1e, 0x80, 0x00, 0xde, 0x4b, 0x19, 0x50, 0xdc, 0x49, 0x0a, 0x50, 0xf7, 0x46, 0x80,
+ 0x69, 0xb8, 0x21, 0x09, 0x5c, 0x01, 0x29, 0x06, 0xd0, 0xb5, 0x21, 0x08, 0x5c, 0x60, 0x21,
+ 0x41, 0x43, 0xd8, 0x4a, 0x00, 0x20, 0x50, 0x54, 0xd8, 0x48, 0x1b, 0x30, 0xf7, 0x46, 0x10,
+ 0xb5, 0x04, 0x1c, 0xd6, 0x48, 0x00, 0x68, 0x01, 0x21, 0x8e, 0x46, 0xd5, 0x49, 0xfe, 0x44,
+ 0x08, 0x47, 0xe0, 0x68, 0x0c, 0x30, 0xe0, 0x60, 0xd3, 0x48, 0xff, 0x30, 0x02, 0x30, 0x10,
+ 0xbd, 0xa7, 0x4a, 0x05, 0x00, 0x30, 0xb5, 0x42, 0x69, 0x11, 0x88, 0x09, 0x06, 0x0b, 0x0e,
+ 0xcf, 0x49, 0x02, 0x2b,
+
+ 0x01, 0x05, 0xff, 0xff, 0x46, 0x71, 0x08, 0x00, 0xfa, 0x1a, 0xd1, 0xca, 0x4b, 0x1b, 0x6b,
+ 0x9b, 0x68, 0xdb, 0x88, 0x01, 0x24, 0xa4, 0x02, 0x1d, 0x05, 0xad, 0x0f, 0xad, 0x02, 0xa5,
+ 0x42, 0x06, 0xdb, 0x05, 0x24, 0x24, 0x02, 0x1b, 0x05, 0x1b, 0x0f, 0x1b, 0x02, 0xa3, 0x42,
+ 0x02, 0xdb, 0xd2, 0x88, 0x52, 0x1d, 0x01, 0xe0, 0x52, 0x88, 0x52, 0x1c, 0x42, 0x60, 0x08,
+ 0x1c, 0x9f, 0x30, 0x30, 0xbd, 0x08, 0x1c, 0x87, 0x30, 0x30, 0xbd, 0x5e, 0x56, 0x08, 0x00,
+ 0x40, 0x42, 0x0f, 0x00, 0x04, 0x60, 0x1a, 0x00, 0x6d, 0x94, 0x05, 0x00, 0x00, 0xb5, 0x01,
+ 0x1c, 0x48, 0x68, 0xc9, 0x69, 0xb5, 0x22, 0x51, 0x5c, 0xdc, 0x22, 0x4a, 0x43, 0xea, 0x49,
+ 0x89, 0x18, 0x08, 0x22, 0x01, 0x23, 0x9e, 0x46, 0xe9, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0xe8,
+ 0x48, 0x3f, 0x30, 0x00, 0xbd, 0xc0, 0x46, 0x80, 0xc3, 0xc9, 0x01, 0x40, 0x69, 0x01, 0x8f,
+ 0xc0, 0x8e, 0x40, 0x1a, 0x00, 0x04, 0x02, 0x0c, 0xe9, 0x49, 0x49, 0x0a, 0x0c, 0x48, 0x8a,
+ 0x42, 0x01, 0xd3, 0xfa, 0x38, 0x00, 0xe0, 0xa2, 0x30, 0xe4, 0x49, 0x40, 0x18, 0xf7, 0x46,
+ 0xc0, 0x46, 0xe5, 0x2b, 0x00, 0x00, 0x19, 0xd4, 0x04, 0x00, 0x81, 0x42, 0x02, 0x00, 0x55,
+ 0x3f, 0x02, 0x00, 0xc0, 0x79, 0x1a, 0x00, 0x3f, 0x42, 0x0f, 0x00, 0x05, 0x9a, 0x05, 0x00,
+ 0x28, 0x79, 0x1a, 0x00, 0xe1, 0x04, 0x00, 0x00, 0xe8, 0x57, 0x08, 0x00, 0xf8, 0xb5, 0x81,
+ 0x69, 0x08, 0x04, 0x00, 0x0c, 0x00, 0x90, 0xd9, 0x4d, 0xda, 0x4c, 0xc8, 0x08, 0x2a, 0xd3,
+ 0xd6, 0x48, 0xff, 0x21, 0x3d, 0x31, 0x0f, 0x18, 0x29, 0x5c, 0x00, 0x26, 0x21, 0xe0, 0xa8,
+ 0x00, 0x30, 0x58, 0xc2, 0x22, 0x12, 0x5c, 0x00, 0x2a, 0x0a, 0xd0, 0xb5, 0x21, 0x08, 0x5c,
+ 0x0a, 0x30, 0x00, 0x06,
+
+ 0x01, 0x05, 0xff, 0xff, 0x40, 0x72, 0x08, 0x00, 0xfa, 0x00, 0x0e, 0x01, 0x21, 0x8e, 0x46,
+ 0xce, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x21, 0x78, 0x01, 0x35, 0x19, 0xe0, 0xb0, 0x00, 0x38,
+ 0x58, 0xc2, 0x22, 0x12, 0x5c, 0x00, 0x2a, 0x07, 0xd0, 0xb5, 0x21, 0x08, 0x5c, 0x01, 0x21,
+ 0x8e, 0x46, 0xc6, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x21, 0x78, 0x01, 0x36, 0x8e, 0x42, 0xee,
+ 0xd3, 0x00, 0x98, 0x00, 0x09, 0x07, 0xd3, 0xbf, 0x48, 0xff, 0x21, 0x3d, 0x31, 0x0e, 0x18,
+ 0x29, 0x5c, 0x00, 0x25, 0x8d, 0x42, 0xd0, 0xd3, 0xbf, 0x48, 0x87, 0x30, 0xf8, 0xbd, 0x2c,
+ 0x7a, 0x1a, 0x00, 0x70, 0xb5, 0x06, 0x1c, 0xb0, 0x68, 0xbc, 0x4d, 0x00, 0x28, 0x02, 0xd1,
+ 0x28, 0x1c, 0xdf, 0x30, 0x70, 0xbd, 0x73, 0x4c, 0x04, 0x3c, 0x20, 0x7a, 0x02, 0x28, 0x08,
+ 0xd0, 0xb7, 0x49, 0x08, 0x5c, 0x01, 0x21, 0x8e, 0x46, 0xb6, 0x49, 0xfe, 0x44, 0x08, 0x47,
+ 0x00, 0x28, 0x02, 0xd0, 0x28, 0x1c, 0xcf, 0x30, 0x70, 0xbd, 0x00, 0x20, 0x20, 0x60, 0x70,
+ 0x60, 0x28, 0x1c, 0xff, 0x30, 0x20, 0x30, 0x70, 0xbd, 0xc0, 0x46, 0xc9, 0x49, 0x05, 0x00,
+ 0x10, 0xb5, 0x9c, 0x49, 0x11, 0x31, 0x06, 0x22, 0x00, 0x23, 0x0c, 0x78, 0xff, 0x2c, 0x02,
+ 0xd1, 0x5b, 0x1c, 0x1b, 0x06, 0x1b, 0x0e, 0xdc, 0x31, 0x01, 0x3a, 0xf6, 0xd1, 0x43, 0x60,
+ 0xa7, 0x48, 0x19, 0x30, 0x10, 0xbd, 0x01, 0x1c, 0xa7, 0x4b, 0x1a, 0x78, 0xa5, 0x48, 0x05,
+ 0x2a, 0x04, 0xd1, 0xa5, 0x4a, 0x12, 0x68, 0x12, 0x78, 0x01, 0x2a, 0x02, 0xd0, 0x4b, 0x60,
+ 0x5b, 0x30, 0xf7, 0x46, 0x7d, 0x30, 0xf7, 0x46, 0x10, 0xb5, 0x01, 0x1c, 0xa0, 0x48, 0x00,
+ 0x68, 0xa1, 0x4c, 0x00, 0x28, 0x0b, 0xd0, 0x88, 0x69, 0x09, 0x7a, 0x01, 0x22, 0x96, 0x46,
+ 0x9d, 0x4a, 0xfe, 0x44,
+
+ 0x01, 0x05, 0xff, 0xff, 0x3a, 0x73, 0x08, 0x00, 0xfa, 0x10, 0x47, 0x00, 0x28, 0x02, 0xd0,
+ 0x20, 0x1c, 0x21, 0x30, 0x10, 0xbd, 0x20, 0x1c, 0x33, 0x30, 0x10, 0xbd, 0x48, 0x53, 0x08,
+ 0x00, 0xe2, 0x04, 0x00, 0x00, 0x71, 0x55, 0x00, 0x00, 0xf8, 0xb5, 0x81, 0x69, 0x00, 0x91,
+ 0x92, 0x4c, 0x25, 0x1c, 0x0c, 0x3d, 0xe9, 0x68, 0x08, 0x22, 0x57, 0x18, 0x40, 0x69, 0x90,
+ 0x4a, 0x00, 0x28, 0x02, 0xd0, 0x10, 0x1c, 0xd3, 0x30, 0xf8, 0xbd, 0x00, 0x26, 0x04, 0xe0,
+ 0x70, 0x1c, 0x06, 0x06, 0x36, 0x0e, 0x06, 0x37, 0x21, 0x68, 0x48, 0x88, 0x86, 0x42, 0x14,
+ 0xda, 0x38, 0x1c, 0x00, 0x99, 0x01, 0x22, 0x96, 0x46, 0x87, 0x4a, 0xfe, 0x44, 0x10, 0x47,
+ 0x00, 0x28, 0xee, 0xd1, 0x0c, 0x34, 0xe8, 0x68, 0x41, 0x88, 0x01, 0x20, 0x88, 0x40, 0xe1,
+ 0x6f, 0x81, 0x43, 0xe1, 0x67, 0xe9, 0x68, 0x48, 0x88, 0x01, 0x38, 0x48, 0x80, 0x7e, 0x48,
+ 0xff, 0x30, 0x14, 0x30, 0xf8, 0xbd, 0xc0, 0x46, 0xc1, 0x0b, 0x04, 0x00, 0x98, 0x3a, 0x00,
+ 0x00, 0xbb, 0x16, 0x04, 0x00, 0xc2, 0x4f, 0x08, 0x00, 0x24, 0x56, 0x08, 0x00, 0x6d, 0x0b,
+ 0x04, 0x00, 0x4b, 0x70, 0x08, 0x00, 0xc9, 0x4c, 0x02, 0x00, 0x00, 0x59, 0x00, 0x01, 0x40,
+ 0x31, 0xf7, 0x00, 0xdd, 0xd6, 0x02, 0x00, 0x70, 0xb5, 0x72, 0x48, 0x05, 0x78, 0x00, 0x24,
+ 0x71, 0x48, 0x00, 0x88, 0x80, 0x09, 0x10, 0xd3, 0x01, 0x20, 0x06, 0x1c, 0x86, 0x46, 0x6f,
+ 0x49, 0xfe, 0x44, 0x08, 0x47, 0x00, 0x28, 0x08, 0xd0, 0x3f, 0x22, 0x6d, 0x49, 0x08, 0x78,
+ 0x02, 0x28, 0x03, 0xd1, 0x50, 0x5c, 0x00, 0x28, 0x00, 0xd0, 0x34, 0x1c, 0x6a, 0x48, 0xff,
+ 0x2d, 0x01, 0xd0, 0x00, 0x2c, 0x01, 0xd0, 0x41, 0x30, 0x70, 0xbd, 0x0d, 0x30, 0x70, 0xbd,
+ 0xd1, 0xcd, 0x02, 0x00,
+
+ 0x01, 0x05, 0xff, 0xff, 0x34, 0x74, 0x08, 0x00, 0xfa, 0x01, 0x1c, 0x66, 0x48, 0x02, 0x78,
+ 0x64, 0x48, 0x00, 0x2a, 0x01, 0xd0, 0xed, 0x30, 0xf7, 0x46, 0x41, 0x22, 0x4a, 0x60, 0x39,
+ 0x30, 0xf7, 0x46, 0x00, 0x5a, 0x62, 0x02, 0x00, 0x6c, 0xdc, 0x02, 0x38, 0x58, 0xdb, 0x02,
+ 0xcc, 0xb5, 0x62, 0x02, 0x99, 0x29, 0x03, 0x00, 0x57, 0x4a, 0x05, 0x00, 0x04, 0xf3, 0x1a,
+ 0x00, 0x80, 0x7b, 0x08, 0x00, 0x76, 0xa0, 0x1b, 0x00, 0x6d, 0x97, 0x00, 0x00, 0x6c, 0x55,
+ 0x08, 0x00, 0x4f, 0x61, 0x04, 0x00, 0x39, 0xc1, 0x02, 0x00, 0x7d, 0xc4, 0x02, 0x00, 0xf8,
+ 0xb5, 0x06, 0x1c, 0x75, 0x69, 0xb7, 0x69, 0x31, 0x6a, 0x30, 0x7f, 0x00, 0x28, 0x2d, 0xd1,
+ 0x01, 0x21, 0xa8, 0x8d, 0x18, 0x28, 0x27, 0xdc, 0x50, 0x48, 0x00, 0x78, 0x00, 0x90, 0x00,
+ 0x24, 0x01, 0x22, 0xa2, 0x40, 0x00, 0x98, 0x10, 0x42, 0x1b, 0xd0, 0x49, 0x48, 0x20, 0x5c,
+ 0x11, 0x21, 0x49, 0x01, 0x41, 0x43, 0x47, 0x48, 0x41, 0x18, 0xff, 0x20, 0x1e, 0x30, 0x40,
+ 0x5c, 0x01, 0x28, 0x01, 0xd1, 0x02, 0x20, 0x00, 0xe0, 0x00, 0x20, 0xc9, 0x78, 0x08, 0x18,
+ 0x44, 0x49, 0x08, 0x5c, 0xa9, 0x8d, 0x01, 0x22, 0x96, 0x46, 0x43, 0x4a, 0xfe, 0x44, 0x10,
+ 0x47, 0x48, 0x1c, 0x01, 0x06, 0x09, 0x0e, 0x01, 0x34, 0x07, 0x2c, 0xdb, 0xdb, 0xa8, 0x8d,
+ 0x01, 0xe0, 0x48, 0x7d, 0xa9, 0x8d, 0x48, 0x43, 0x39, 0x68, 0x40, 0x18, 0x80, 0x01, 0x80,
+ 0x09, 0x38, 0x60, 0x70, 0x60, 0x36, 0x48, 0x5d, 0x30, 0xf8, 0xbd, 0x01, 0x1c, 0x4a, 0x68,
+ 0x13, 0x06, 0x1b, 0x0e, 0x36, 0x48, 0x03, 0xd1, 0x22, 0x4b, 0x1b, 0x78, 0x03, 0x2b, 0x05,
+ 0xd0, 0x00, 0x2a, 0x01, 0xd0, 0x1d, 0x30, 0xf7, 0x46, 0xff, 0x30, 0xf7, 0x46, 0x13, 0x4a,
+ 0x30, 0x23, 0x9b, 0x5c,
+
+ 0x01, 0x05, 0xff, 0xff, 0x2e, 0x75, 0x08, 0x00, 0xfa, 0x00, 0x2b, 0x07, 0xd1, 0x30, 0x4b,
+ 0x92, 0x88, 0x9a, 0x42, 0x03, 0xd1, 0x2d, 0x4a, 0x12, 0x78, 0x00, 0x2a, 0x01, 0xd0, 0x00,
+ 0x22, 0x00, 0xe0, 0x07, 0x22, 0x4a, 0x60, 0xff, 0x30, 0xa2, 0x30, 0xf7, 0x46, 0x5c, 0x27,
+ 0x08, 0x00, 0x4b, 0x1e, 0x04, 0x00, 0x05, 0x5e, 0x02, 0x00, 0x40, 0x69, 0x78, 0x21, 0x09,
+ 0x5a, 0x25, 0x48, 0xac, 0x29, 0x01, 0xda, 0x3b, 0x30, 0xf7, 0x46, 0x89, 0x30, 0xf7, 0x46,
+ 0xc9, 0x98, 0x00, 0x00, 0xf0, 0xff, 0xff, 0x00, 0x48, 0x25, 0x08, 0x00, 0x6a, 0x0a, 0x00,
+ 0x00, 0x47, 0x93, 0x02, 0x00, 0xb2, 0x2f, 0x08, 0x00, 0x49, 0xa0, 0x02, 0x00, 0x25, 0x6e,
+ 0x03, 0x00, 0x3c, 0x91, 0x06, 0x00, 0x17, 0x62, 0x04, 0x00, 0xef, 0x8a, 0x04, 0x00, 0xd9,
+ 0xae, 0x02, 0x00, 0x41, 0x10, 0x08, 0x00, 0xa8, 0x63, 0x08, 0x00, 0xec, 0x0e, 0x08, 0x00,
+ 0x5d, 0x86, 0x01, 0x00, 0xdd, 0xf8, 0x03, 0x00, 0x79, 0x1c, 0x04, 0x00, 0xc2, 0x22, 0x08,
+ 0x00, 0x7a, 0x7f, 0x1a, 0x00, 0x93, 0x68, 0x04, 0x00, 0xe4, 0x21, 0x08, 0x00, 0xe9, 0xcb,
+ 0x01, 0x00, 0xdd, 0x84, 0x01, 0x00, 0xfc, 0x63, 0x08, 0x00, 0x00, 0x16, 0x08, 0x00, 0x00,
+ 0x00, 0x08, 0x00, 0x09, 0x82, 0x01, 0x00, 0xb5, 0x63, 0x08, 0x00, 0xac, 0x63, 0x08, 0x00,
+ 0x6d, 0x94, 0x05, 0x00, 0xbd, 0x7b, 0x03, 0x00, 0xf5, 0x50, 0x08, 0x00, 0xff, 0xff, 0x00,
+ 0x00, 0xe5, 0x85, 0x00, 0x00, 0xff, 0xb5, 0x68, 0x46, 0xff, 0xf7, 0x3e, 0xfa, 0xff, 0xbd,
+ 0xff, 0xb5, 0x68, 0x46, 0xff, 0xf7, 0x1d, 0xfa, 0xff, 0xbd, 0xff, 0xb5, 0x68, 0x46, 0xff,
+ 0xf7, 0xb2, 0xf9, 0xff, 0xbd, 0xff, 0xb5, 0x68, 0x46, 0xff, 0xf7, 0x0d, 0xfb, 0xff, 0xbd,
+ 0xff, 0xb5, 0x68, 0x46,
+
+ 0x01, 0x05, 0xff, 0x65, 0x28, 0x76, 0x08, 0x00, 0x60, 0xff, 0xf7, 0x9e, 0xfa, 0xff, 0xbd,
+ 0xff, 0xb5, 0x68, 0x46, 0xff, 0xf7, 0x51, 0xfa, 0xff, 0xbd, 0xff, 0xb5, 0x68, 0x46, 0xfe,
+ 0xf7, 0xfa, 0xff, 0xff, 0xbd, 0xff, 0xb5, 0x68, 0x46, 0xff, 0xf7, 0x04, 0xf8, 0xff, 0xbd,
+ 0xff, 0xb5, 0x68, 0x46, 0xfe, 0xf7, 0x74, 0xff, 0xff, 0xbd, 0xff, 0xb5, 0x68, 0x46, 0xfe,
+ 0xf7, 0xaf, 0xff, 0xff, 0xbd, 0xff, 0xb5, 0x68, 0x46, 0xff, 0xf7, 0x68, 0xf9, 0xff, 0xbd,
+ 0xff, 0xb5, 0x68, 0x46, 0xff, 0xf7, 0xaf, 0xf9, 0xff, 0xbd, 0xff, 0xb5, 0x68, 0x46, 0xff,
+ 0xf7, 0x17, 0xf8, 0xff, 0xbd, 0xff, 0xb5, 0x68, 0x46, 0xff, 0xf7, 0xa5, 0xf8, 0xff, 0xbd,
+
+
+ 0x01, 0x05, 0xff, 0x8d, 0x78, 0x7b, 0x08, 0x00, 0x88, 0x00, 0xb5, 0xf8, 0xf0, 0x31, 0xfd,
+ 0x00, 0xbd, 0x95, 0x71, 0x08, 0x00, 0x15, 0x71, 0x08, 0x00, 0x39, 0x71, 0x08, 0x00, 0xc1,
+ 0x71, 0x08, 0x00, 0xc1, 0x71, 0x08, 0x00, 0xf5, 0x06, 0x18, 0x00, 0xf7, 0x70, 0x08, 0x00,
+ 0x0d, 0x72, 0x08, 0x00, 0x95, 0x72, 0x08, 0x00, 0xdd, 0x72, 0x08, 0x00, 0x01, 0x73, 0x08,
+ 0x00, 0x21, 0x73, 0x08, 0x00, 0xed, 0x73, 0x08, 0x00, 0xbd, 0x6d, 0x08, 0x00, 0x59, 0x07,
+ 0x18, 0x00, 0x35, 0x74, 0x08, 0x00, 0x85, 0x74, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x59,
+ 0x73, 0x08, 0x00, 0x09, 0x75, 0x08, 0x00, 0x63, 0x70, 0x08, 0x00, 0x5d, 0x75, 0x08, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ 0x01, 0x05, 0xff, 0x85, 0x04, 0xf3, 0x1a, 0x00, 0x80, 0x36, 0x5e, 0x02, 0x00, 0x38, 0xc2,
+ 0x02, 0x00, 0x00, 0xc5, 0x02, 0x00, 0x9c, 0x9c, 0x00, 0x00, 0x08, 0x9c, 0x00, 0x00, 0x02,
+ 0x69, 0x00, 0x00, 0x84, 0x97, 0x00, 0x00, 0x6a, 0xa0, 0x02, 0x00, 0xf0, 0x6e, 0x03, 0x00,
+ 0xf0, 0x8a, 0x04, 0x00, 0x32, 0xaf, 0x02, 0x00, 0xf4, 0xf8, 0x03, 0x00, 0xf4, 0xcb, 0x01,
+ 0x00, 0xa8, 0x55, 0x00, 0x00, 0x00, 0x16, 0x04, 0x00, 0x14, 0x85, 0x01, 0x00, 0x54, 0x82,
+ 0x01, 0x00, 0xff, 0xff, 0xff, 0xff, 0xac, 0xf9, 0x03, 0x00, 0xd6, 0x7b, 0x03, 0x00, 0x2c,
+ 0xd7, 0x02, 0x00, 0x1c, 0x86, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff,
+
+ 0x01, 0x05, 0xff, 0xff, 0x00, 0x00, 0x18, 0x00, 0xfa, 0xf0, 0xb5, 0x8c, 0xb0, 0xad, 0x48,
+ 0x06, 0xc8, 0x6f, 0x46, 0x68, 0x46, 0x06, 0xc0, 0xac, 0x48, 0x06, 0xc8, 0x02, 0xa8, 0x06,
+ 0xc0, 0xfb, 0x48, 0x06, 0xc8, 0x04, 0xa8, 0x06, 0xc0, 0xfa, 0x48, 0x06, 0xc8, 0x06, 0xa8,
+ 0x06, 0xc0, 0xf9, 0x48, 0x06, 0xc8, 0x08, 0xa8, 0x06, 0xc0, 0xf8, 0x48, 0x06, 0xc8, 0x0a,
+ 0xa8, 0x06, 0xc0, 0x0c, 0x26, 0xf1, 0x48, 0x48, 0x30, 0x31, 0x1c, 0x01, 0x24, 0xa6, 0x46,
+ 0xf4, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x9e, 0x4d, 0xa8, 0x78, 0x00, 0x28, 0x19, 0xd1, 0x03,
+ 0x20, 0x01, 0x1c, 0xf0, 0x48, 0xa6, 0x46, 0xee, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0xef, 0x48,
+ 0x03, 0x21, 0xa6, 0x46, 0xeb, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0xed, 0x48, 0x00, 0x21, 0x32,
+ 0x1c, 0xa6, 0x46, 0xec, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0xe8, 0x48, 0x02, 0x21, 0xa6, 0x46,
+ 0xea, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0xde, 0x48, 0x04, 0x21, 0xa6, 0x46, 0xe7, 0x4a, 0xfe,
+ 0x44, 0x10, 0x47, 0xea, 0x4e, 0x30, 0x1c, 0x4c, 0x38, 0x02, 0x21, 0xa6, 0x46, 0xde, 0x4a,
+ 0xfe, 0x44, 0x10, 0x47, 0xe2, 0x48, 0x0a, 0x99, 0x01, 0x60, 0xb9, 0x8d, 0x81, 0x80, 0x27,
+ 0x1c, 0x21, 0x1c, 0xe0, 0x48, 0x98, 0x30, 0x8e, 0x46, 0xd7, 0x4a, 0xfe, 0x44, 0x10, 0x47,
+ 0xdd, 0x48, 0x00, 0x99, 0x01, 0x60, 0x01, 0x99, 0x41, 0x60, 0x02, 0x99, 0x01, 0x62, 0x03,
+ 0x99, 0x41, 0x62, 0x04, 0x99, 0x01, 0x63, 0x05, 0x99, 0x41, 0x63, 0x06, 0x99, 0x81, 0x64,
+ 0x07, 0x99, 0xc1, 0x64, 0x08, 0x99, 0x01, 0x66, 0x09, 0x99, 0x41, 0x66, 0x9c, 0x30, 0x21,
+ 0x1c, 0x8e, 0x46, 0xca, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0xd0, 0x48, 0x00, 0x78, 0x01, 0x28,
+ 0x00, 0xd1, 0xa3, 0xe0,
+
+ 0x01, 0x05, 0xff, 0xff, 0xfa, 0x00, 0x18, 0x00, 0xfa, 0x00, 0x28, 0x00, 0xd1, 0xda, 0xe0,
+ 0x02, 0x28, 0x00, 0xd0, 0xd7, 0xe0, 0x30, 0x1c, 0x05, 0x21, 0xbe, 0x46, 0xf9, 0x4a, 0xfe,
+ 0x44, 0x10, 0x47, 0x01, 0x1c, 0xc8, 0x48, 0x00, 0x22, 0xbe, 0x46, 0xc2, 0x4b, 0xfe, 0x44,
+ 0x18, 0x47, 0xa8, 0x78, 0x00, 0x28, 0x16, 0xd1, 0x13, 0x20, 0xc5, 0x49, 0x08, 0x80, 0x03,
+ 0x25, 0x29, 0x1c, 0x20, 0x1c, 0xa6, 0x46, 0xc3, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0xb8, 0x48,
+ 0x29, 0x1c, 0xbe, 0x46, 0xb4, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0xb6, 0x48, 0x00, 0x21, 0x0c,
+ 0x22, 0xbe, 0x46, 0xb5, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0xaa, 0x4e, 0x06, 0x3e, 0x30, 0x1c,
+ 0x02, 0x21, 0x00, 0x22, 0xbe, 0x46, 0xb9, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0xa6, 0x4d, 0x04,
+ 0x3d, 0xb8, 0x4f, 0x38, 0x1c, 0xc8, 0x38, 0x28, 0x60, 0x30, 0x1c, 0x03, 0x21, 0x00, 0x22,
+ 0xa6, 0x46, 0xb3, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x2f, 0x60, 0x30, 0x1c, 0x04, 0x21, 0x00,
+ 0x22, 0xa6, 0x46, 0xaf, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0xaf, 0x4f, 0x38, 0x1c, 0xd1, 0x38,
+ 0x28, 0x60, 0x30, 0x1c, 0x05, 0x21, 0x00, 0x22, 0xa6, 0x46, 0xa9, 0x4b, 0xfe, 0x44, 0x18,
+ 0x47, 0x2f, 0x60, 0x30, 0x1c, 0x06, 0x21, 0x00, 0x22, 0xa6, 0x46, 0xa5, 0x4b, 0xfe, 0x44,
+ 0x18, 0x47, 0x38, 0x1c, 0x32, 0x30, 0x28, 0x60, 0x30, 0x1c, 0x07, 0x21, 0x00, 0x22, 0xa6,
+ 0x46, 0xa0, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x38, 0x1c, 0x62, 0x30, 0x28, 0x60, 0x30, 0x1c,
+ 0x08, 0x21, 0x00, 0x22, 0xa6, 0x46, 0x9b, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0xc2, 0x37, 0x2f,
+ 0x60, 0x30, 0x1c, 0x09, 0x21, 0x00, 0x22, 0xa6, 0x46, 0x97, 0x4b, 0xfe, 0x44, 0x18, 0x47,
+ 0xea, 0x48, 0x28, 0x60,
+
+ 0x01, 0x05, 0xff, 0xff, 0xf4, 0x01, 0x18, 0x00, 0xfa, 0x30, 0x1c, 0x0a, 0x21, 0x00, 0x22,
+ 0xa6, 0x46, 0x92, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0xe7, 0x48, 0x28, 0x60, 0x30, 0x1c, 0x0b,
+ 0x21, 0x00, 0x22, 0xa6, 0x46, 0x8e, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0xe3, 0x48, 0x28, 0x60,
+ 0xe3, 0x48, 0x00, 0x88, 0x80, 0x0b, 0x4a, 0xd3, 0x00, 0x22, 0x10, 0x1c, 0xc3, 0x00, 0x82,
+ 0x49, 0x06, 0x39, 0xc9, 0x18, 0x0c, 0x88, 0x24, 0x06, 0x24, 0x0e, 0x0c, 0x80, 0x7e, 0x49,
+ 0x04, 0x39, 0xca, 0x52, 0x01, 0x30, 0x14, 0x28, 0xf1, 0xdb, 0x39, 0xe0, 0xbe, 0x46, 0xd9,
+ 0x48, 0xfe, 0x44, 0x00, 0x47, 0xbe, 0x46, 0xda, 0x48, 0xfe, 0x44, 0x00, 0x47, 0xc0, 0x06,
+ 0xc0, 0x0e, 0x81, 0x02, 0xd6, 0x48, 0x00, 0x78, 0x40, 0x06, 0x40, 0x0e, 0x08, 0x43, 0x03,
+ 0x21, 0x09, 0x02, 0x01, 0x43, 0xd1, 0x48, 0x00, 0x68, 0x81, 0x86, 0xd3, 0x48, 0x04, 0x70,
+ 0xd4, 0x48, 0xd2, 0x49, 0x08, 0x80, 0xd3, 0x4d, 0x28, 0x1c, 0x08, 0x38, 0x02, 0x21, 0xbe,
+ 0x46, 0x64, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x28, 0x1c, 0x07, 0x21, 0x0c, 0x22, 0xbe, 0x46,
+ 0xce, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x00, 0x26, 0x32, 0x1c, 0xce, 0x4d, 0x28, 0x1c, 0x04,
+ 0x38, 0x37, 0x21, 0xbe, 0x46, 0xca, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x28, 0x1c, 0x31, 0x1c,
+ 0xbe, 0x46, 0x58, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x0c, 0xb0, 0xf0, 0xbd, 0xc0, 0x46, 0xa4,
+ 0x62, 0x08, 0x00, 0xac, 0x62, 0x08, 0x00, 0x60, 0x56, 0x08, 0x00, 0xf0, 0xb5, 0x5a, 0x48,
+ 0x00, 0x78, 0x01, 0x28, 0x44, 0xd0, 0x00, 0x28, 0x34, 0xd0, 0x02, 0x28, 0x00, 0xd0, 0x90,
+ 0xe0, 0xbe, 0x49, 0x48, 0x20, 0x40, 0x18, 0x03, 0x88, 0x01, 0x22, 0x1a, 0x43, 0x02, 0x80,
+ 0xaf, 0x4a, 0x70, 0x3a,
+
+ 0x01, 0x05, 0xff, 0xff, 0xee, 0x02, 0x18, 0x00, 0xfa, 0x13, 0x88, 0x9b, 0x10, 0x9b, 0x00,
+ 0x13, 0x80, 0x7c, 0x23, 0x82, 0x8e, 0x9a, 0x43, 0x32, 0x23, 0x13, 0x43, 0x83, 0x86, 0xb6,
+ 0x48, 0x7a, 0x30, 0x02, 0x88, 0x52, 0x09, 0x53, 0x01, 0x08, 0x22, 0x1a, 0x43, 0x02, 0x80,
+ 0x08, 0x88, 0x40, 0x10, 0x40, 0x00, 0x08, 0x80, 0xf3, 0x4b, 0xff, 0x24, 0x18, 0x88, 0x20,
+ 0x40, 0x03, 0x22, 0x12, 0x02, 0x02, 0x43, 0x1a, 0x80, 0x18, 0x89, 0x20, 0x40, 0xff, 0x22,
+ 0x01, 0x32, 0x02, 0x43, 0x1a, 0x81, 0x02, 0x22, 0x08, 0x88, 0x90, 0x43, 0x08, 0x80, 0xf0,
+ 0xbd, 0x07, 0x21, 0x09, 0x02, 0xea, 0x48, 0xc2, 0x38, 0x0a, 0x1c, 0x01, 0x24, 0xa6, 0x46,
+ 0xe7, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x99, 0x48, 0x01, 0x38, 0x04, 0x70, 0xf0, 0xbd, 0x00,
+ 0x26, 0xe4, 0x48, 0x31, 0x1c, 0x02, 0x22, 0x01, 0x24, 0xa6, 0x46, 0xe0, 0x4b, 0xfe, 0x44,
+ 0x18, 0x47, 0x96, 0x4d, 0x28, 0x1c, 0x08, 0x38, 0x02, 0x21, 0xa6, 0x46, 0x26, 0x4a, 0xfe,
+ 0x44, 0x10, 0x47, 0x02, 0x35, 0x28, 0x1c, 0x07, 0x27, 0x31, 0x1c, 0x0a, 0x1c, 0x39, 0x1c,
+ 0xa6, 0x46, 0x8f, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x28, 0x1c, 0x39, 0x1c, 0x03, 0x22, 0xa6,
+ 0x46, 0x8c, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x8c, 0x4d, 0x28, 0x1c, 0x04, 0x38, 0x08, 0x21,
+ 0x3a, 0x1c, 0xa6, 0x46, 0xec, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x28, 0x1c, 0x02, 0x38, 0x04,
+ 0x21, 0xa6, 0x46, 0xea, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x28, 0x1c, 0x31, 0x1c, 0xa6, 0x46,
+ 0x13, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x0c, 0x49, 0x58, 0x31, 0x0e, 0x80, 0x0c, 0x25, 0x29,
+ 0x1c, 0x81, 0x48, 0xa6, 0x46, 0x13, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0xc3, 0x48, 0xa6, 0x38,
+ 0x31, 0x1c, 0x0a, 0x1c,
+
+ 0x01, 0x05, 0xff, 0xff, 0xe8, 0x03, 0x18, 0x00, 0xfa, 0xa6, 0x46, 0x79, 0x4b, 0xfe, 0x44,
+ 0x18, 0x47, 0xbf, 0x48, 0x64, 0x38, 0x29, 0x1c, 0xa6, 0x46, 0x06, 0x4a, 0xfe, 0x44, 0x10,
+ 0x47, 0xf0, 0xbd, 0x10, 0x60, 0x1a, 0x00, 0xb4, 0x62, 0x08, 0x00, 0xbc, 0x62, 0x08, 0x00,
+ 0xc4, 0x62, 0x08, 0x00, 0xcc, 0x62, 0x08, 0x00, 0x61, 0x48, 0x05, 0x00, 0x08, 0xf0, 0x1a,
+ 0x00, 0x1e, 0xf6, 0x1a, 0x00, 0x14, 0xf6, 0x1a, 0x00, 0xd3, 0x48, 0x05, 0x00, 0x79, 0x48,
+ 0x05, 0x00, 0x98, 0x0b, 0x1a, 0x00, 0x08, 0x09, 0x1a, 0x00, 0xe8, 0x57, 0x08, 0x00, 0x6a,
+ 0x31, 0x19, 0x00, 0xc4, 0x61, 0x1a, 0x00, 0x9e, 0x13, 0x08, 0x00, 0x21, 0x99, 0x05, 0x00,
+ 0xff, 0x48, 0x05, 0x00, 0xdc, 0x09, 0x04, 0x00, 0x25, 0x0d, 0x04, 0x00, 0xf0, 0xb5, 0xba,
+ 0xb0, 0xa5, 0x4d, 0x2e, 0x1c, 0x56, 0x36, 0x30, 0x1c, 0x08, 0x21, 0x01, 0x24, 0xa6, 0x46,
+ 0xc0, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x00, 0x06, 0x00, 0x0e, 0x37, 0x90, 0x30, 0x1c, 0x00,
+ 0x21, 0xa6, 0x46, 0xbc, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x06, 0x04, 0x28, 0x1c, 0x54, 0x30,
+ 0x00, 0x88, 0x06, 0x43, 0x2f, 0x1c, 0x52, 0x37, 0x38, 0x1c, 0x08, 0x21, 0xa6, 0x46, 0xb7,
+ 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x00, 0x06, 0x00, 0x0e, 0x38, 0x90, 0x50, 0x35, 0x28, 0x1c,
+ 0x00, 0x21, 0xa6, 0x46, 0xb3, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x39, 0x90, 0x28, 0x1c, 0x0c,
+ 0x21, 0xa6, 0x46, 0x0f, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x05, 0x1c, 0x38, 0x1c, 0x00, 0x21,
+ 0xa6, 0x46, 0xaa, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x00, 0x01, 0x28, 0x43, 0x05, 0x04, 0x2d,
+ 0x0c, 0x02, 0xa8, 0xa9, 0x49, 0xd4, 0x22, 0xa6, 0x46, 0xa8, 0x4b, 0xfe, 0x44, 0x18, 0x47,
+ 0x37, 0x98, 0x08, 0x28,
+
+ 0x01, 0x05, 0xff, 0xff, 0xe2, 0x04, 0x18, 0x00, 0xfa, 0x58, 0xd1, 0xa6, 0x48, 0xa7, 0x49,
+ 0x42, 0x79, 0x0b, 0x78, 0x93, 0x42, 0x52, 0xd1, 0x02, 0xe0, 0xc0, 0x46, 0x57, 0x4a, 0x05,
+ 0x00, 0x02, 0x79, 0x4b, 0x78, 0x93, 0x42, 0x4a, 0xd1, 0xc2, 0x78, 0x8b, 0x78, 0x93, 0x42,
+ 0x46, 0xd1, 0xff, 0xe7, 0x82, 0x78, 0xcb, 0x78, 0x93, 0x42, 0x41, 0xd1, 0x42, 0x78, 0x0b,
+ 0x79, 0x93, 0x42, 0x3d, 0xd1, 0x00, 0x78, 0x49, 0x79, 0x81, 0x42, 0x39, 0xd1, 0x00, 0x21,
+ 0x08, 0x1c, 0x0b, 0xe0, 0x35, 0x28, 0x34, 0xda, 0x82, 0x00, 0x02, 0xab, 0x9a, 0x58, 0x96,
+ 0x42, 0x03, 0xd0, 0x40, 0x1c, 0x00, 0x06, 0x00, 0x0e, 0x00, 0xe0, 0x21, 0x1c, 0x00, 0x29,
+ 0xf1, 0xd0, 0x78, 0x22, 0x69, 0x46, 0x0a, 0x70, 0xde, 0x22, 0x4a, 0x70, 0xe4, 0x22, 0x8a,
+ 0x70, 0x42, 0x01, 0x38, 0x98, 0x02, 0x43, 0x90, 0x01, 0x28, 0x43, 0x80, 0x01, 0x39, 0x9a,
+ 0x10, 0x43, 0x02, 0x0c, 0xca, 0x70, 0x02, 0x0a, 0x0a, 0x71, 0x48, 0x71, 0x86, 0x48, 0x05,
+ 0x1c, 0xa6, 0x46, 0x86, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x1f, 0x20, 0xa6, 0x46, 0x84, 0x49,
+ 0xfe, 0x44, 0x08, 0x47, 0x84, 0x48, 0x00, 0x78, 0x02, 0x28, 0x05, 0xd1, 0x28, 0x1c, 0x00,
+ 0x21, 0xa6, 0x46, 0x81, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x3a, 0xb0, 0xf0, 0xbd, 0xc0, 0x46,
+ 0x2f, 0x0e, 0x04, 0x00, 0x6a, 0x12, 0x40, 0x00, 0x85, 0x12, 0x00, 0x00, 0x5c, 0x7b, 0x1a,
+ 0x00, 0x55, 0x04, 0x18, 0x00, 0xe8, 0x21, 0x08, 0x00, 0x0f, 0x51, 0x08, 0x00, 0x4f, 0x76,
+ 0x04, 0x00, 0x09, 0x51, 0x08, 0x00, 0xb0, 0x63, 0x08, 0x00, 0xff, 0xff, 0x00, 0x00, 0x0a,
+ 0x30, 0x1a, 0x00, 0xa7, 0x48, 0x05, 0x00, 0x15, 0x49, 0x05, 0x00, 0x08, 0x0f, 0x1a, 0x00,
+ 0x24, 0x79, 0x1a, 0x00,
+
+ 0x01, 0x05, 0xff, 0xff, 0xdc, 0x05, 0x18, 0x00, 0xfa, 0xda, 0x7c, 0x1a, 0x00, 0xf0, 0xb5,
+ 0x6e, 0x4e, 0x06, 0x25, 0x35, 0x70, 0x0f, 0x23, 0x73, 0x70, 0x3d, 0x20, 0xb0, 0x70, 0x29,
+ 0x20, 0xf0, 0x70, 0x03, 0x20, 0x2a, 0x1c, 0x7d, 0x49, 0xe4, 0x31, 0x01, 0x24, 0xa6, 0x46,
+ 0x67, 0x4f, 0xfe, 0x44, 0x38, 0x47, 0xb2, 0x78, 0xf3, 0x78, 0x03, 0x20, 0x78, 0x49, 0xe5,
+ 0x31, 0xa6, 0x46, 0x63, 0x4e, 0xfe, 0x44, 0x30, 0x47, 0x03, 0x20, 0x75, 0x49, 0xe6, 0x31,
+ 0xa6, 0x46, 0x60, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0xa6, 0x46, 0x5f, 0x48, 0xfe, 0x44, 0x00,
+ 0x47, 0x5f, 0x4a, 0x00, 0x21, 0x08, 0x1c, 0x13, 0x68, 0x00, 0x2b, 0x04, 0xd0, 0x03, 0x07,
+ 0x1e, 0x0f, 0x23, 0x1c, 0xb3, 0x40, 0x19, 0x43, 0x03, 0x07, 0x1b, 0x0f, 0x0f, 0x2b, 0x05,
+ 0xd1, 0xc6, 0x08, 0x2b, 0x1c, 0x33, 0x40, 0x57, 0x4e, 0xf1, 0x52, 0x00, 0x21, 0x04, 0x32,
+ 0x01, 0x30, 0x20, 0x28, 0xe9, 0xd3, 0x00, 0x27, 0x54, 0x48, 0x07, 0x70, 0x19, 0x20, 0x40,
+ 0x01, 0x53, 0x49, 0x08, 0x80, 0xff, 0x20, 0x52, 0x49, 0x08, 0x70, 0x52, 0x49, 0x08, 0x70,
+ 0x52, 0x48, 0x07, 0x70, 0x53, 0x48, 0x52, 0x49, 0x08, 0x60, 0x53, 0x48, 0x24, 0x21, 0x01,
+ 0x70, 0x18, 0x21, 0x41, 0x70, 0x20, 0x21, 0x81, 0x70, 0x10, 0x21, 0xc1, 0x70, 0x57, 0x48,
+ 0x4f, 0x49, 0x08, 0x80, 0xa6, 0x46, 0x4e, 0x48, 0xfe, 0x44, 0x00, 0x47, 0x4e, 0x4e, 0x4e,
+ 0x4d, 0xa6, 0x46, 0x4e, 0x48, 0xfe, 0x44, 0x00, 0x47, 0x31, 0x88, 0x01, 0x40, 0x48, 0x08,
+ 0x04, 0xd0, 0x00, 0x20, 0xc0, 0x43, 0x45, 0x19, 0x85, 0x42, 0xf2, 0xd1, 0xa6, 0x46, 0x48,
+ 0x48, 0xfe, 0x44, 0x00, 0x47, 0x31, 0x88, 0x01, 0x40, 0x48, 0x08, 0x04, 0xd0, 0x5c, 0x20,
+ 0xa6, 0x46, 0x44, 0x49,
+
+ 0x01, 0x05, 0xff, 0xff, 0xd6, 0x06, 0x18, 0x00, 0xfa, 0xfe, 0x44, 0x08, 0x47, 0xa6, 0x46,
+ 0x43, 0x48, 0xfe, 0x44, 0x00, 0x47, 0x37, 0x80, 0xf0, 0xbd, 0xc0, 0x46, 0x2c, 0x7a, 0x1a,
+ 0x00, 0xdb, 0x4a, 0x05, 0x00, 0xc2, 0x74, 0x1a, 0x00, 0x10, 0xb5, 0x43, 0x69, 0x31, 0x49,
+ 0x09, 0x78, 0x3e, 0x4a, 0x12, 0x78, 0x01, 0x2a, 0x04, 0xd1, 0x1c, 0x78, 0x00, 0x2c, 0x01,
+ 0xd1, 0x2c, 0x49, 0x09, 0x78, 0x3e, 0x4c, 0x24, 0x78, 0x00, 0x2c, 0x1b, 0xd0, 0xff, 0x29,
+ 0x19, 0xd0, 0x01, 0x2a, 0x08, 0xd0, 0x37, 0x4a, 0x12, 0x78, 0x01, 0x2a, 0x13, 0xd0, 0x1a,
+ 0x78, 0x01, 0x2a, 0x01, 0xd0, 0x02, 0x2a, 0x0e, 0xd1, 0x10, 0x22, 0xd4, 0x56, 0x8c, 0x42,
+ 0x0a, 0xdd, 0x61, 0x1a, 0x09, 0x06, 0x09, 0x0e, 0x5b, 0x1c, 0x00, 0x24, 0x1c, 0x57, 0x64,
+ 0x1a, 0x1c, 0x70, 0x01, 0x33, 0x01, 0x3a, 0xf8, 0xd1, 0x2c, 0x49, 0x81, 0x60, 0x2c, 0x48,
+ 0x15, 0x30, 0x10, 0xbd, 0x2c, 0x48, 0x15, 0x30, 0xf7, 0x46, 0xc0, 0x46, 0x2b, 0x49, 0x05,
+ 0x00, 0x41, 0x49, 0x05, 0x00, 0x61, 0x4a, 0x05, 0x00, 0x7f, 0x4a, 0x05, 0x00, 0x6b, 0x4a,
+ 0x05, 0x00, 0xa7, 0x4a, 0x05, 0x00, 0xd4, 0x62, 0x08, 0x00, 0x21, 0xa7, 0x05, 0x00, 0x22,
+ 0x17, 0x08, 0x00, 0x12, 0x56, 0x08, 0x00, 0x79, 0x10, 0x08, 0x00, 0x87, 0x1c, 0x04, 0x00,
+ 0x9d, 0x31, 0x05, 0x00, 0x41, 0x10, 0x08, 0x00, 0xc3, 0x7a, 0x03, 0x00, 0x0c, 0x51, 0x08,
+ 0x00, 0x0b, 0xd4, 0x04, 0x00, 0xf5, 0xd3, 0x04, 0x00, 0x8d, 0x0a, 0x18, 0x00, 0x80, 0x7b,
+ 0x08, 0x00, 0x84, 0xf3, 0x1a, 0x00, 0xb5, 0x63, 0x08, 0x00, 0xcc, 0x24, 0x08, 0x00, 0xf4,
+ 0x63, 0x08, 0x00, 0xf5, 0x63, 0x08, 0x00, 0xfc, 0x63, 0x08, 0x00, 0xa8, 0x63, 0x08, 0x00,
+ 0x36, 0xa0, 0x1b, 0x00,
+
+ 0x01, 0x05, 0xff, 0xff, 0xd0, 0x07, 0x18, 0x00, 0xfa, 0xac, 0x63, 0x08, 0x00, 0x4c, 0x25,
+ 0x08, 0x00, 0x01, 0x00, 0x18, 0x00, 0x00, 0x7c, 0x1a, 0x00, 0xf0, 0xff, 0xff, 0x00, 0x07,
+ 0xff, 0x03, 0x00, 0xd7, 0xd3, 0x04, 0x00, 0xc9, 0x02, 0x18, 0x00, 0xe1, 0x04, 0x00, 0x00,
+ 0xff, 0xff, 0x00, 0x00, 0xfa, 0x63, 0x08, 0x00, 0xf7, 0x63, 0x08, 0x00, 0x10, 0x30, 0x19,
+ 0x00, 0xef, 0x68, 0x00, 0x00, 0xe8, 0x57, 0x08, 0x00, 0xff, 0x15, 0x04, 0x00, 0xf0, 0xb5,
+ 0xc3, 0x49, 0x0c, 0x78, 0x0e, 0x2c, 0x2c, 0xda, 0xc2, 0x4e, 0x3f, 0x20, 0x85, 0x19, 0x60,
+ 0x1c, 0x00, 0x06, 0x00, 0x0e, 0x28, 0x70, 0xbf, 0x4b, 0xa2, 0x00, 0xbf, 0x4f, 0x9f, 0x50,
+ 0x0e, 0x28, 0x18, 0xda, 0xa2, 0x1c, 0x12, 0x06, 0x12, 0x0e, 0x6a, 0x70, 0x80, 0x00, 0xbc,
+ 0x4d, 0x1d, 0x50, 0x0e, 0x2a, 0x08, 0xda, 0xe0, 0x1c, 0x70, 0x72, 0x90, 0x00, 0xb9, 0x4a,
+ 0x1a, 0x50, 0x08, 0x78, 0x03, 0x30, 0x08, 0x70, 0xf0, 0xbd, 0x0a, 0x70, 0x01, 0x20, 0x86,
+ 0x46, 0xb6, 0x48, 0xfe, 0x44, 0x00, 0x47, 0xfe, 0xe7, 0x08, 0x70, 0x01, 0x20, 0x86, 0x46,
+ 0xb2, 0x48, 0xfe, 0x44, 0x00, 0x47, 0xfe, 0xe7, 0x01, 0x20, 0x86, 0x46, 0xaf, 0x48, 0xfe,
+ 0x44, 0x00, 0x47, 0xfe, 0xe7, 0xf8, 0xb5, 0x07, 0x1c, 0xfb, 0x7a, 0xad, 0x48, 0x03, 0x70,
+ 0x3a, 0x7b, 0xac, 0x48, 0x02, 0x70, 0xac, 0x49, 0x7c, 0x7b, 0x0c, 0x70, 0xac, 0x48, 0xbd,
+ 0x7b, 0x05, 0x70, 0xb3, 0x4e, 0x00, 0x2b, 0x00, 0xd0, 0xbe, 0xe0, 0xad, 0x4a, 0x15, 0x1c,
+ 0x8c, 0x3d, 0xb6, 0x4e, 0xb6, 0x0b, 0x01, 0x24, 0xa6, 0x46, 0xa6, 0x48, 0xfe, 0x44, 0x00,
+ 0x47, 0x29, 0x88, 0x01, 0x40, 0x48, 0x08, 0x05, 0xd0, 0x30, 0x1c, 0x41, 0x1e, 0x0e, 0x04,
+ 0x36, 0x0c, 0x00, 0x28,
+
+ 0x01, 0x05, 0xff, 0xff, 0xca, 0x08, 0x18, 0x00, 0xfa, 0xf0, 0xd1, 0xa6, 0x46, 0x9f, 0x48,
+ 0xfe, 0x44, 0x00, 0x47, 0x29, 0x88, 0x01, 0x40, 0x48, 0x08, 0x04, 0xd0, 0x58, 0x20, 0xa6,
+ 0x46, 0x9b, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x98, 0x48, 0x00, 0x78, 0x9a, 0x4e, 0x01, 0x28,
+ 0x34, 0xd0, 0x00, 0x20, 0x01, 0x1c, 0x0c, 0x20, 0x02, 0x1c, 0x30, 0x1c, 0xa6, 0x46, 0x96,
+ 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x96, 0x48, 0x00, 0x21, 0x08, 0x22, 0xa6, 0x46, 0x95, 0x4b,
+ 0xfe, 0x44, 0x18, 0x47, 0x92, 0x4e, 0x24, 0x36, 0x30, 0x1c, 0x21, 0x1c, 0x0c, 0x22, 0xa6,
+ 0x46, 0x9a, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x07, 0x20, 0x01, 0x1c, 0x20, 0x1c, 0xa6, 0x46,
+ 0x8e, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x14, 0x20, 0xa6, 0x46, 0x8c, 0x49, 0xfe, 0x44, 0x08,
+ 0x47, 0x07, 0x20, 0xa6, 0x46, 0x8c, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x89, 0x49, 0x08, 0x70,
+ 0x30, 0x1c, 0x00, 0x21, 0x0c, 0x22, 0xa6, 0x46, 0x8d, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x85,
+ 0x4e, 0x5b, 0xe0, 0x30, 0x1c, 0x00, 0x21, 0x08, 0x22, 0xa6, 0x46, 0x7d, 0x4b, 0xfe, 0x44,
+ 0x18, 0x47, 0x30, 0x1c, 0x00, 0x21, 0x0c, 0x22, 0xa6, 0x46, 0x79, 0x4b, 0xfe, 0x44, 0x18,
+ 0x47, 0x79, 0x48, 0x00, 0x21, 0x0a, 0x1c, 0xa6, 0x46, 0x78, 0x4b, 0xfe, 0x44, 0x18, 0x47,
+ 0x75, 0x48, 0x00, 0x21, 0x08, 0x22, 0xa6, 0x46, 0x74, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x03,
+ 0x20, 0x02, 0x1c, 0x71, 0x48, 0x02, 0x21, 0xa6, 0x46, 0x7a, 0x4b, 0xfe, 0x44, 0x18, 0x47,
+ 0x0b, 0x20, 0x02, 0x1c, 0x6d, 0x48, 0x21, 0x1c, 0x8e, 0x46, 0x76, 0x4b, 0xfe, 0x44, 0x18,
+ 0x47, 0x20, 0x1c, 0x06, 0x21, 0xa6, 0x46, 0x6a, 0x4a, 0xfe, 0x44, 0x10, 0x47, 0x07, 0x20,
+ 0x01, 0x1c, 0x20, 0x1c,
+
+ 0x01, 0x05, 0xff, 0xff, 0xc4, 0x09, 0x18, 0x00, 0xfa, 0xa6, 0x46, 0x67, 0x4a, 0xfe, 0x44,
+ 0x10, 0x47, 0x14, 0x20, 0xa6, 0x46, 0x65, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x65, 0x4e, 0x07,
+ 0x20, 0xa6, 0x46, 0x64, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x00, 0x90, 0x06, 0x20, 0xa6, 0x46,
+ 0x61, 0x49, 0xfe, 0x44, 0x08, 0x47, 0x41, 0x00, 0x00, 0x98, 0x01, 0x43, 0x31, 0x70, 0x59,
+ 0x48, 0x00, 0x21, 0x03, 0x22, 0xa6, 0x46, 0x62, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x55, 0x48,
+ 0x00, 0x21, 0x0b, 0x22, 0xa6, 0x46, 0x5e, 0x4b, 0xfe, 0x44, 0x18, 0x47, 0x00, 0x20, 0x28,
+ 0x80, 0x4b, 0x48, 0x04, 0x78, 0x4b, 0x48, 0x05, 0x78, 0x32, 0x78, 0x01, 0xe0, 0x30, 0x1c,
+ 0x02, 0x70, 0xfb, 0x7b, 0x01, 0x2d, 0x25, 0xd1, 0x00, 0x2c, 0x0d, 0xd1, 0x10, 0x1c, 0x09,
+ 0xd0, 0x01, 0x38, 0x05, 0xd0, 0x01, 0x38, 0x01, 0xd0, 0x06, 0x20, 0x16, 0xe0, 0x04, 0x20,
+ 0x14, 0xe0, 0x02, 0x20, 0x12, 0xe0, 0x00, 0x20, 0x10, 0xe0, 0x10, 0x1c, 0x0d, 0xd0, 0x01,
+ 0x38, 0x09, 0xd0, 0x01, 0x38, 0x05, 0xd0, 0x01, 0x38, 0x01, 0xd0, 0x10, 0x20, 0x06, 0xe0,
+ 0x0e, 0x20, 0x04, 0xe0, 0x0c, 0x20, 0x02, 0xe0, 0x0a, 0x20, 0x00, 0xe0, 0x08, 0x20, 0xc0,
+ 0x19, 0xc1, 0x7b, 0x40, 0x4b, 0x19, 0x70, 0x03, 0x7c, 0x3f, 0x48, 0x03, 0x70, 0x03, 0x20,
+ 0x3f, 0x49, 0x01, 0x24, 0xa6, 0x46, 0x3e, 0x4c, 0xfe, 0x44, 0x20, 0x47, 0xf8, 0xbd, 0x30,
+ 0xb5, 0x00, 0x20, 0x4c, 0x49, 0x08, 0x70, 0x4c, 0x48, 0xf7, 0x21, 0x01, 0x70, 0xff, 0x21,
+ 0x41, 0x70, 0x81, 0x70, 0x7f, 0x21, 0xc1, 0x70, 0x20, 0x4a, 0x10, 0x1f, 0x38, 0x49, 0x08,
+ 0x60, 0x1d, 0x4b, 0x01, 0x21, 0x19, 0x70, 0x37, 0x48, 0x10, 0x60, 0x02, 0x25, 0x38, 0x48,
+ 0x04, 0x1c, 0x33, 0x34,
+
+ 0x01, 0x05, 0xff, 0xff, 0xbe, 0x0a, 0x18, 0x00, 0xfa, 0x25, 0x70, 0x34, 0x4c, 0x54, 0x60,
+ 0x03, 0x24, 0x1c, 0x71, 0x33, 0x4c, 0x94, 0x60, 0x04, 0x24, 0x04, 0x70, 0x33, 0x4c, 0xd4,
+ 0x60, 0x05, 0x24, 0xc4, 0x73, 0x32, 0x4c, 0x14, 0x61, 0x06, 0x24, 0x9c, 0x71, 0x31, 0x4c,
+ 0x54, 0x61, 0x07, 0x24, 0xdc, 0x71, 0xdc, 0x1d, 0x30, 0x4d, 0x95, 0x61, 0x08, 0x25, 0x15,
+ 0x38, 0x05, 0x70, 0x2e, 0x48, 0xd0, 0x61, 0x09, 0x20, 0x60, 0x77, 0x2d, 0x48, 0x10, 0x62,
+ 0x0a, 0x20, 0xc3, 0x18, 0x18, 0x70, 0x2c, 0x48, 0x50, 0x62, 0x0b, 0x20, 0xd8, 0x75, 0x2b,
+ 0x4b, 0x93, 0x62, 0x03, 0x4a, 0x10, 0x70, 0x8e, 0x46, 0x29, 0x48, 0xfe, 0x44, 0x00, 0x47,
+ 0x30, 0xbd, 0xb4, 0x63, 0x08, 0x00, 0x8c, 0x53, 0x08, 0x00, 0xb8, 0x63, 0x08, 0x00, 0x4d,
+ 0x76, 0x08, 0x00, 0x57, 0x76, 0x08, 0x00, 0x39, 0x76, 0x08, 0x00, 0x01, 0x64, 0x08, 0x00,
+ 0xf6, 0x63, 0x08, 0x00, 0xf9, 0x63, 0x08, 0x00, 0xf8, 0x63, 0x08, 0x00, 0xfa, 0x63, 0x08,
+ 0x00, 0x07, 0xff, 0x03, 0x00, 0xd7, 0xd3, 0x04, 0x00, 0x16, 0xf6, 0x1a, 0x00, 0xd3, 0x48,
+ 0x05, 0x00, 0x8c, 0x7c, 0x1a, 0x00, 0xa7, 0x48, 0x05, 0x00, 0x21, 0x99, 0x05, 0x00, 0xbb,
+ 0x16, 0x04, 0x00, 0xf7, 0x63, 0x08, 0x00, 0x67, 0x99, 0x05, 0x00, 0xf4, 0x63, 0x08, 0x00,
+ 0xf5, 0x63, 0x08, 0x00, 0xae, 0x05, 0x00, 0x00, 0x0b, 0xd4, 0x04, 0x00, 0xff, 0xff, 0xff,
+ 0x1f, 0x91, 0x48, 0x05, 0x00, 0x88, 0x53, 0x08, 0x00, 0x1b, 0x76, 0x08, 0x00, 0x43, 0x76,
+ 0x08, 0x00, 0x75, 0x76, 0x08, 0x00, 0xca, 0x53, 0x08, 0x00, 0x7f, 0x76, 0x08, 0x00, 0x61,
+ 0x76, 0x08, 0x00, 0x6b, 0x76, 0x08, 0x00, 0x11, 0x76, 0x08, 0x00, 0x07, 0x76, 0x08, 0x00,
+ 0xfd, 0x75, 0x08, 0x00,
+
+ 0x01, 0x05, 0xff, 0x19, 0xb8, 0x0b, 0x18, 0x00, 0x14, 0x2f, 0x76, 0x08, 0x00, 0x25, 0x76,
+ 0x08, 0x00, 0x11, 0x08, 0x18, 0x00, 0xfb, 0x63, 0x08, 0x00, 0xf0, 0x63, 0x08, 0x00,
+
+ 0x01, 0x83, 0xff, 0x14, 0x79, 0x7b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ //
+ //
+ 0x01, 0xdc, 0xfd, 0x05, 0x00, 0x00, 0x00, 0x00, 0x12,
+
+ 0x01, 0x0f, 0xfd, 0x01, 0x01,
+
+ //
+ //
+ // ##--------------------------------------------------------------------------------
+ // ## Description: QRCA_L_TRIOL PHY FW Initialization Script
+ // ## Version: 3.17_3 (based on ROM version)
+ // ##--------------------------------------------------------------------------------
+ 0x01, 0x01, 0xff, 0x06, 0xc6, 0x32, 0x19, 0x00, 0x10, 0x10,
+
+ 0x01, 0x01, 0xff, 0x06, 0x60, 0x32, 0x19, 0x00, 0x32, 0x10,
+
+ 0x01, 0x82, 0xfd, 0x14, 0x00, 0x9c, 0x18, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xdc,
+ 0xe6, 0xf0, 0xfa, 0x04, 0x0e, 0x18, 0xff, 0x00, 0x00,
+
+ 0x01, 0x82, 0xfd, 0x14, 0x01, 0x9c, 0xce, 0xce, 0xce, 0xce, 0xce, 0xce, 0xce, 0xce, 0xd8,
+ 0xe2, 0xec, 0xf6, 0x00, 0x0a, 0x14, 0xff, 0x00, 0x00,
+
+ 0x01, 0x82, 0xfd, 0x14, 0x02, 0x9c, 0xce, 0xce, 0xce, 0xce, 0xce, 0xce, 0xce, 0xce, 0xd8,
+ 0xe2, 0xec, 0xf6, 0x00, 0x0a, 0x14, 0xff, 0x00, 0x00,
+
+ 0x01, 0x87, 0xfd, 0x03, 0x0d, 0x0d, 0x0d,
+
+ 0x01, 0x76, 0xfd, 0x31, 0x01, 0x21, 0x54, 0x00, 0x00, 0x61, 0x57, 0x00, 0x00, 0x14, 0x05,
+ 0x0a, 0x05, 0x00, 0x07, 0x06, 0x0a, 0x04, 0x05, 0x08, 0x09, 0x0b, 0x0c, 0x0d, 0x0e, 0x10,
+ 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
+
+ 0x01, 0x80, 0xfd, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
+
+ 0x01, 0x80, 0xfd, 0x06, 0x3c, 0xf0, 0x5f, 0x00, 0x00, 0x00,
+
+ //
+ //
+ //
+ 0x01, 0x38, 0xfe, 0x00,
+
+ //
+ // # BLE
+ // #--------------------------------------------------------------------------------
+ // # Description: BRF6450 WB FW Initialization Script
+ // #
+ // # Compatibility: BRF6450 PG1 ROM
+ // #
+ // # Last Updated: 07-Oct-2010 15:19:44.57
+ // #
+ // # Version: 1.0
+ // #
+ // #--------------------------------------------------------------------------------
+ //
+ //
+ // #BLE Enable
+ 0x01, 0x5b, 0xfd, 0x02, 0x01, 0x01,
+
+ //
+ // # Disable Cortex Sleep
+ 0x01, 0xa8, 0xfd, 0x01, 0x01,
+
+ //
+ //
+ // # Cortex Reset (hold in reset while loading IMEM)
+ 0x01, 0x09, 0xfd, 0x08, 0x00, 0xc0, 0x1b, 0x00, 0x01, 0x00, 0x01, 0x00,
+
+ // ########################
+ // # Patch Start
+ // ########################
+ //
+ 0x01, 0x05, 0xff, 0x41, 0x60, 0x5c, 0x1b, 0x00, 0x3c, 0x01, 0x68, 0xb1, 0xf1, 0xff, 0x3f,
+ 0x1c, 0xbf, 0x49, 0x1c, 0x01, 0x60, 0x13, 0xd1, 0x41, 0x68, 0x00, 0x23, 0x03, 0x60, 0x01,
+ 0xf0, 0x7f, 0x02, 0x7f, 0x2a, 0x04, 0xbf, 0x21, 0xf0, 0x7f, 0x01, 0x41, 0x60, 0x4f, 0xea,
+ 0x41, 0x62, 0x06, 0xd0, 0x02, 0xf1, 0x00, 0x72, 0x21, 0xf0, 0x7f, 0x01, 0x41, 0xea, 0x52,
+ 0x61, 0x41, 0x60, 0x70, 0x47, 0x00, 0x00, 0xf0, 0xb5,
+
+ 0x01, 0x05, 0xff, 0xcd, 0x8c, 0x6e, 0x1b, 0x00, 0xc8, 0x40, 0xf2, 0x00, 0x04, 0xc2, 0xf2,
+ 0x00, 0x04, 0xd4, 0xf8, 0x8c, 0x25, 0x40, 0xf2, 0x00, 0x05, 0x01, 0x78, 0x6f, 0xf3, 0x1f,
+ 0x42, 0xc2, 0xf2, 0x30, 0x05, 0x15, 0x43, 0x42, 0xf2, 0x6c, 0x4b, 0x29, 0x80, 0x43, 0xf2,
+ 0x00, 0x02, 0xc4, 0xf2, 0x00, 0x0b, 0x00, 0x23, 0xab, 0xf8, 0x00, 0x30, 0x4f, 0xf4, 0x20,
+ 0x63, 0xc2, 0xf2, 0x31, 0x02, 0x01, 0x21, 0x41, 0xf2, 0x08, 0x46, 0x40, 0x27, 0x4f, 0xf0,
+ 0x78, 0x0c, 0x53, 0x80, 0x16, 0x80, 0xd7, 0x83, 0xa2, 0xf8, 0x1c, 0xc0, 0x91, 0x80, 0x11,
+ 0x84, 0x02, 0x78, 0x10, 0x2a, 0x80, 0xf2, 0xbf, 0x80, 0x13, 0x46, 0x00, 0x2b, 0x05, 0xf1,
+ 0x02, 0x05, 0x2b, 0xd0, 0x5b, 0x1e, 0x1d, 0xd0, 0x5b, 0x1e, 0x0e, 0xd0, 0x5b, 0x1e, 0x30,
+ 0xd1, 0x42, 0xf2, 0x46, 0x42, 0xc2, 0xf2, 0x31, 0x02, 0x00, 0x23, 0x93, 0x80, 0x11, 0x80,
+ 0x02, 0x78, 0x4f, 0xf4, 0x80, 0x7a, 0x41, 0xf2, 0x11, 0x08, 0x23, 0xe0, 0x42, 0xf2, 0x46,
+ 0x42, 0xc2, 0xf2, 0x31, 0x02, 0x02, 0x23, 0x93, 0x80, 0x11, 0x80, 0x02, 0x78, 0x4f, 0xf4,
+ 0x80, 0x7a, 0x41, 0xf2, 0x11, 0x08, 0x16, 0xe0, 0x42, 0xf2, 0x46, 0x42, 0xc2, 0xf2, 0x31,
+ 0x02, 0x02, 0x23, 0x93, 0x80, 0x11, 0x80, 0x02, 0x78, 0x8a, 0x46, 0x41, 0xf2, 0x01, 0x18,
+ 0x0a, 0xe0, 0x42, 0xf2, 0x46, 0x42, 0xc2, 0xf2, 0x31, 0x02, 0x00, 0x23, 0x93, 0x80,
+
+ 0x01, 0x05, 0xff, 0xcd, 0x54, 0x6f, 0x1b, 0x00, 0xc8, 0x11, 0x80, 0x41, 0xf2, 0x10, 0x18,
+ 0x8a, 0x46, 0x02, 0x78, 0x42, 0xf2, 0x48, 0x49, 0x4f, 0xf2, 0x04, 0x07, 0x10, 0x2a, 0x7c,
+ 0xda, 0xc2, 0xf2, 0x31, 0x09, 0xc2, 0xf2, 0x32, 0x07, 0x00, 0x20, 0x00, 0x26, 0xab, 0xf8,
+ 0x00, 0x00, 0x25, 0xf8, 0x02, 0x6b, 0x4f, 0xf0, 0x15, 0x0e, 0xa9, 0xf8, 0x00, 0xe0, 0x94,
+ 0xf8, 0x05, 0x26, 0x10, 0x2a, 0x04, 0xda, 0x39, 0x88, 0x01, 0x20, 0x90, 0x40, 0x08, 0x43,
+ 0x38, 0x80, 0xc6, 0xf1, 0xfa, 0x00, 0x80, 0xb2, 0xfe, 0xf7, 0xb7, 0xfb, 0x11, 0x20, 0xa9,
+ 0xf8, 0x00, 0x00, 0x94, 0xf8, 0x10, 0x26, 0x10, 0x2a, 0x04, 0xda, 0x39, 0x88, 0x01, 0x20,
+ 0x90, 0x40, 0x08, 0x43, 0x38, 0x80, 0xfa, 0x20, 0xfe, 0xf7, 0xa8, 0xfb, 0xbb, 0xf8, 0x00,
+ 0x00, 0x1a, 0xea, 0x00, 0x0f, 0x25, 0xf8, 0x02, 0x0b, 0x02, 0xd0, 0x18, 0xea, 0x00, 0x0f,
+ 0x09, 0xd0, 0x94, 0xf8, 0x49, 0x06, 0x40, 0xf0, 0x04, 0x00, 0x84, 0xf8, 0x49, 0x06, 0x4f,
+ 0xf4, 0xfa, 0x70, 0xfe, 0xf7, 0x94, 0xfb, 0x10, 0x20, 0xa9, 0xf8, 0x00, 0x00, 0x94, 0xf8,
+ 0x10, 0x26, 0x38, 0x46, 0x10, 0x2a, 0x08, 0xda, 0x01, 0x88, 0x4f, 0xf0, 0x01, 0x0e, 0x0e,
+ 0xfa, 0x02, 0xf0, 0x81, 0x43, 0xbc, 0x46, 0xac, 0xf8, 0x00, 0x10, 0x32, 0x20, 0xfe, 0xf7,
+ 0x80, 0xfb, 0x14, 0x20, 0xa9, 0xf8, 0x00, 0x00, 0x94, 0xf8, 0x05, 0x26, 0x38, 0x46,
+
+ 0x01, 0x05, 0xff, 0xcd, 0x1c, 0x70, 0x1b, 0x00, 0xc8, 0x10, 0x2a, 0x08, 0xda, 0x01, 0x88,
+ 0x4f, 0xf0, 0x01, 0x0e, 0x0e, 0xfa, 0x02, 0xf0, 0x81, 0x43, 0xbc, 0x46, 0xac, 0xf8, 0x00,
+ 0x10, 0x32, 0x20, 0xfe, 0xf7, 0x6c, 0xfb, 0xbb, 0xf8, 0x00, 0x00, 0x41, 0xf2, 0x11, 0x11,
+ 0x25, 0xf8, 0x02, 0x0b, 0x01, 0x42, 0x1e, 0xbf, 0x94, 0xf8, 0x49, 0x06, 0x40, 0xf0, 0x08,
+ 0x00, 0x84, 0xf8, 0x49, 0x06, 0xc8, 0x20, 0xfe, 0xf7, 0x5b, 0xfb, 0x76, 0x1c, 0xfa, 0x2e,
+ 0x4f, 0xf0, 0x00, 0x00, 0x88, 0xd3, 0x94, 0xf8, 0x49, 0x06, 0x00, 0xf0, 0x7f, 0x00, 0x84,
+ 0xf8, 0x49, 0x06, 0xbd, 0xe8, 0xf0, 0x8f, 0x30, 0xb5, 0x41, 0xf6, 0x48, 0x44, 0x41, 0xf6,
+ 0x30, 0x45, 0x00, 0x21, 0x03, 0x20, 0xc2, 0xf2, 0x00, 0x04, 0xc2, 0xf2, 0x00, 0x05, 0x0a,
+ 0x46, 0x63, 0x7a, 0xe8, 0x75, 0xf9, 0xf7, 0x57, 0xfb, 0x63, 0x7a, 0xe8, 0x7d, 0x00, 0x22,
+ 0x01, 0x21, 0xf9, 0xf7, 0x51, 0xfb, 0x40, 0xf6, 0x6a, 0x20, 0x07, 0x21, 0xc2, 0xf2, 0x32,
+ 0x00, 0xff, 0xf7, 0xbc, 0xfa, 0x00, 0x21, 0x22, 0x7a, 0x31, 0x20, 0xff, 0xf7, 0x0d, 0xfa,
+ 0x43, 0xf2, 0x5c, 0x10, 0x00, 0x21, 0xc2, 0xf2, 0x31, 0x00, 0xff, 0xf7, 0xb0, 0xfa, 0x20,
+ 0x7a, 0x10, 0xb9, 0x00, 0xf0, 0x79, 0xff, 0x30, 0xbd, 0x00, 0xf0, 0xdf, 0xfe, 0x30, 0xbd,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ 0x01, 0x05, 0xff, 0xcd, 0xe4, 0x70, 0x1b, 0x00, 0xc8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ 0x01, 0x05, 0xff, 0x11, 0xac, 0x71, 0x1b, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ 0x01, 0x05, 0xff, 0x15, 0x0c, 0x7f, 0x1b, 0x00, 0x10, 0x10, 0xbd, 0x00, 0xb5, 0x41, 0xf6,
+ 0x50, 0x40, 0xc2, 0xf2, 0x00, 0x00, 0x00, 0x21, 0x02, 0x78,
+
+ 0x01, 0x05, 0xff, 0x15, 0x30, 0x7f, 0x1b, 0x00, 0x10, 0xff, 0xf7, 0xa0, 0xf8, 0x00, 0xbd,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ //
+ // ########################
+ // # Patch End
+ // ########################
+ //
+ // #release Cortex Reset
+ 0x01, 0x09, 0xfd, 0x08, 0x00, 0xc0, 0x1b, 0x00, 0x00, 0x00, 0x01, 0x00,
+
+ //
+ // # Enable Cortex Sleep
+ 0x01, 0xa8, 0xfd, 0x01, 0x00,
+
+ //
+ // #RESET BLE
+ 0x01, 0x5b, 0xfd, 0x02, 0x01, 0x00,
+
+ //
+ 0x01, 0xdd, 0xfd, 0x01, 0x01,
+
+ //
+ // #################################################################
+ // ## START of Panasonic Adds-On
+ // #################################################################
+ //
+ // ## Enable fast clock XTAL support
+ 0x01, 0x1c, 0xfd, 0x14, 0x01, 0x88, 0x13, 0x00, 0x00, 0xd0, 0x07, 0x00, 0x00, 0xff, 0xff,
+ 0x04, 0xff, 0xff, 0xff, 0xfa, 0x00, 0x00, 0x00, 0x00,
+
+ //
+ // ## Enable LPS
+ 0x01, 0x2e, 0xfd, 0x0d, 0x01, 0x58, 0x02, 0x06, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00,
+
+ //
+ // ## Enable eHCILL
+// 0x01, 0x2b, 0xfd, 0x05, 0x10, 0x00, 0x50, 0x00, 0x96,
+
+//DGV: disable eHCILL
+ 0x01, 0x0c, 0xfd, 0x09 , 0x01, 0, 0, 0xff, 0xff, 0xff, 0xff, 100, 0,
+
+ //
+ // 0x01, 0x0c, 0xfd, 0x09, 0x01, 0x01, 0x00, 0xff, 0xff, 0xff, 0xff, 0x64, 0x00,
+
+ //
+ // #################################################################
+ // ## END of Panasonic Adds-On
+ // #################################################################
+
+
+ //terminate
+ 0x00
+};
+
diff --git a/library/ADK2/BT.h b/library/ADK2/BT.h
new file mode 100644
index 0000000..52b24cf
--- /dev/null
+++ b/library/ADK2/BT.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _BT_H_
+#define _BT_H_
+
+#include "sgBuf.h"
+
+typedef struct{
+
+ uint8_t mac[6];
+ uint8_t PSRM, PSPM, PSM;
+ uint16_t co; //clock offset
+ uint32_t dc; //class
+
+}BtDiscoveryResult;
+
+#define SUPORT_SSP 1
+
+#define BT_CONN_LINK_TYPE_SCO 0
+#define BT_CONN_LINK_TYPE_ACL 1
+
+#define BT_BCAST_NONE 0 //point to point
+#define BT_BCAST_ACTIVE 1 //to all active slaves
+#define BT_BCAST_PICONET 2 //to all slaves (even parked)
+
+#define BT_RX_BUF_SZ 1024
+#define BT_BAUDRATE 1750000
+
+
+#define BT_LINK_KEY_SIZE 16
+#define BT_MAC_SIZE 6
+
+
+#define BT_SSP_DONE_VAL 0x0FF00000
+
+typedef struct{
+
+ void* userData;
+
+ char (*BtDiscoveryF)(void* userData, BtDiscoveryResult* r);
+ char (*BtConnReqF)(void* userData, const uint8_t* mac, uint32_t devClass, uint8_t linkType); //return 1 to accept
+ void (*BtConnStartF)(void* userData, uint16_t conn, const uint8_t* mac, uint8_t linkType, uint8_t encrMode);
+ void (*BtConnEndF)(void* userData, uint16_t conn, uint8_t reason);
+ uint8_t (*BtPinRequestF)(void* userData, const uint8_t* mac, uint8_t* buf); //fill buff with PIN code, return num bytes used (16 max) return 0 to decline
+
+ char (*BtLinkKeyRequestF)(void* userData, const uint8_t* mac, uint8_t* buf); //fill buff with the 16-byte link key if known. return 1 if yes, 0 if no
+ void (*BtLinkKeyCreatedF)(void* userData, const uint8_t* mac, const uint8_t* key); //save the key, if you want to...
+
+ void (*BtAclDataRxF)(void* userData, uint16_t conn, char first, uint8_t bcastType, const uint8_t* data, uint16_t sz);
+
+ void (*BtSspShow)(void* userData, const uint8_t* mac, uint32_t sspVal);
+
+}BtFuncs;
+
+char btInit(const BtFuncs* btf);
+
+char btLocalMac(uint8_t* buf);
+char btSetLocalName(const char* name);
+char btGetRemoteName(const uint8_t* mac, uint8_t PSRM, uint8_t PSM, uint16_t co, char* nameBuf);
+void btScan(void);
+char btDiscoverable(char on);
+char btConnectable(char on);
+char btSetDeviceClass(uint32_t cls);
+void btDeinit(void);
+
+void btAclDataTx(uint16_t conn, char first, uint8_t bcastType, sg_buf* buf);
+
+#endif
+#endif
+
diff --git a/library/ADK2/HCI.h b/library/ADK2/HCI.h
new file mode 100644
index 0000000..cfb2cd7
--- /dev/null
+++ b/library/ADK2/HCI.h
@@ -0,0 +1,359 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef _HCI_H_
+#define _HCI_H_
+
+
+//http://webee.technion.ac.il/labs/comnet/projects/winter02/cn08w02/HCI_spec.pdf
+
+
+#define HCI_OPCODE(ogf, ocf) ((((unsigned short)(ogf)) << 10) | (ocf))
+
+typedef struct{
+
+ unsigned short opcode;
+ unsigned char totalParamLen;
+ unsigned char params[];
+
+}HCI_Cmd;
+
+typedef struct{
+
+ unsigned char eventCode;
+ unsigned char totalParamLen;
+ unsigned char params[];
+
+}HCI_Event;
+
+#define HCI_DATA_INFO(conn, pbf, bcf) (((conn & 0xEFF) | (((unsigned short)(pbf)) << 12) | (((unsigned short)(bcf)) << 14))
+#define HCI_CONN(info) ((info) & 0xEFF)
+#define HCI_PBF(info) (((info) >> 12) & 3)
+#define HCI_BCF(info) (((info) >> 14) & 3)
+
+#define HCI_PBF_First_Message 2
+#define HCI_PBF_Continuing_Message 1
+
+//BCF Common
+#define HCI_BCF_Point_To_Point 0
+
+//BCF from host to controller
+#define HCI_BCF_Active_Broadcast 1
+#define HCI_BCF_Piconet_Broadcast 2
+
+//BCF from controller
+#define HCI_BCF_RXed_In_Active_State 1
+#define HCI_BCF_RXed_In_Parked_State 2
+
+typedef struct{
+
+ unsigned short info; //connection handle & flags
+ unsigned short totalDataLen;
+ unsigned char data[];
+
+}HCI_ACL_Data;
+
+
+typedef struct{
+
+ unsigned short info; //connection handle & flags [reserved]
+ unsigned char totalDataLen;
+ unsigned char data[];
+
+}HCI_SCO_Data;
+
+
+#define HCI_LAP_Unlimited_Inquiry 0x9E8B33
+#define HCI_LAP_Limited_Inquiry 0x9E8B00
+
+#define UART_PKT_TYP_CMD 1
+#define UART_PKT_TYP_ACL 2
+#define UART_PKT_TYP_SCO 3
+#define UART_PKT_TYP_EVT 4
+
+#define PAGE_STATE_INQUIRY 1
+#define PAGE_STATE_PAGE 2
+
+#define DEVICE_CLASS_SERVICE_POSITIONING 0x010000 //GPS
+#define DEVICE_CLASS_SERVICE_NETWORKING 0x020000 //LAN
+#define DEVICE_CLASS_SERVICE_RENDERING 0x040000 //PRINTER, SPEAKER
+#define DEVICE_CLASS_SERVICE_CAPTURING 0x080000 //SCANNER, MICROPHONE
+#define DEVICE_CLASS_SERVICE_OBEX 0x100000 //v-Inbox, v-Folder, v-$WORD
+#define DEVICE_CLASS_SERVICE_AUDIO 0x200000 //SPEAKER, MIC, HEADSET
+#define DEVICE_CLASS_SERVICE_TELEPHONY 0x400000 //MODEM, HEADSET
+#define DEVICE_CLASS_SERVICE_INFORMATION 0x800000 //WEB-server, WAP-server
+
+#define DEVICE_CLASS_MAJOR_SHIFT 8
+#define DEVICE_CLASS_MAJOR_MASK 0x001F00
+
+#define DEVICE_CLASS_MAJOR_MISC 0
+#define DEVICE_CLASS_MAJOR_COMPUTER 1
+#define DEVICE_CLASS_MAJOR_PHONE 2
+#define DEVICE_CLASS_MAJOR_LAN 3
+#define DEVICE_CLASS_MAJOR_AV 4
+#define DEVICE_CLASS_MAJOR_PERIPH 5
+#define DEVICE_CLASS_MAJOR_IMAGING 6
+#define DEVICE_CLASS_MAJOR_WEARABLE 7
+#define DEVICE_CLASS_MAJOR_TOY 8
+#define DEVICE_CLASS_MAJOR_HEALTH 9
+#define DEVICE_CLASS_MAJOR_UNCATEGORIZED 31
+
+#define DEVICE_CLASS_MINOR_COMPUTER_SHIFT 2
+#define DEVICE_CLASS_MINOR_COMPUTER_MASK 0xFC
+#define DEVICE_CLASS_MINOR_COMPUTER_UNCATEG 0
+#define DEVICE_CLASS_MINOR_COMPUTER_DESKTOP 1
+#define DEVICE_CLASS_MINOR_COMPUTER_SERVER 2
+#define DEVICE_CLASS_MINOR_COMPUTER_LAPTOP 3
+#define DEVICE_CLASS_MINOR_COMPUTER_CLAM_PDA 4
+#define DEVICE_CLASS_MINOR_COMPUTER_PALM_PDA 5
+#define DEVICE_CLASS_MINOR_COMPUTER_WEARABLE 6
+
+#define DEVICE_CLASS_MINOR_PHONE_SHIFT 2
+#define DEVICE_CLASS_MINOR_PHONE_MASK 0xFC
+#define DEVICE_CLASS_MINOR_PHONE_UNCATEG 0
+#define DEVICE_CLASS_MINOR_PHONE_CELL 1
+#define DEVICE_CLASS_MINOR_PHONE_CORDLESS 2
+#define DEVICE_CLASS_MINOR_PHONE_SMART 3
+#define DEVICE_CLASS_MINOR_PHONE_MODEM 4
+#define DEVICE_CLASS_MINOR_PHONE_ISDN 5
+
+#define DEVICE_CLASS_MINOR_AV_SHIFT 2
+#define DEVICE_CLASS_MINOR_AV_MASK 0xFC
+#define DEVICE_CLASS_MINOR_AV_UNCATEG 0
+#define DEVICE_CLASS_MINOR_AV_HEADSET 1
+#define DEVICE_CLASS_MINOR_AV_HANDSFREE 2
+#define DEVICE_CLASS_MINOR_AV_MIC 4
+#define DEVICE_CLASS_MINOR_AV_LOUDSPEAKER 5
+#define DEVICE_CLASS_MINOR_AV_HEADPHONES 6
+#define DEVICE_CLASS_MINOR_AV_PORTBL_AUDIO 7
+#define DEVICE_CLASS_MINOR_AV_CAR_AUDIO 8
+#define DEVICE_CLASS_MINOR_AV_SET_TOP_BOX 9
+#define DEVICE_CLASS_MINOR_AV_HIFI 10
+#define DEVICE_CLASS_MINOR_AV_VCR 11
+#define DEVICE_CLASS_MINOR_AV_VID_CAM 12
+#define DEVICE_CLASS_MINOR_AV_CAMCORDER 13
+#define DEVICE_CLASS_MINOR_AV_VID_MONITOR 14
+#define DEVICE_CLASS_MINOR_AV_DISPLAY_AND_SPKR 15
+#define DEVICE_CLASS_MINOR_AV_VC 16
+#define DEVICE_CLASS_MINOR_AV_TOY 18
+
+
+//COMMANDS
+
+#define HCI_OGF_Link_Control 1
+
+#define HCI_CMD_Inquiry 0x0001 //enter Inquiry mode where it discovers other Bluetooth devices.
+#define HCI_CMD_Inquiry_Cancel 0x0002 //cancel the Inquiry mode in which the Bluetooth device is in.
+#define HCI_CMD_Periodic_Inquiry_Mode 0x0003 //set the device to enter Inquiry modes periodically according to the time interval set.
+#define HCI_CMD_Exit_Periodic_Inquiry_Mode 0x0004 //exit the periodic Inquiry mode
+#define HCI_CMD_Create_Connection 0x0005 //create an ACL connection to the device specified by the BD_ADDR in the parameters.
+#define HCI_CMD_Disconnect 0x0006 //terminate the existing connection to a device
+#define HCI_CMD_Add_SCO_Connection 0x0007 //Create an SCO connection defined by the connection handle parameters.
+#define HCI_CMD_Accept_Connection_Request 0x0009 //accept a new connection request
+#define HCI_CMD_Reject_Connection_Request 0x000A //reject a new connection request
+#define HCI_CMD_Link_Key_Request_Reply 0x000B //Reply to a link key request event sent from controller to the host
+#define HCI_CMD_Link_Key_Request_Negative_Reply 0x000C //Reply to a link key request event from the controller to the host if there is no link key associated with the connection.
+#define HCI_CMD_PIN_Code_Request_Reply 0x000D //Reply to a PIN code request event sent from a controller to the host.
+#define HCI_CMD_PIN_Code_Request_Negative_Reply 0x000E //Reply to a PIN code request event sent from the controller to the host if there is no PIN associated with the connection.
+#define HCI_CMD_Change_Connection_Packet_Type 0x000F //change the type of packets to be sent for an existing connection.
+#define HCI_CMD_Authentication_Requested 0x0011 //establish authentication between two devices specified by the connection handle.
+#define HCI_CMD_Set_Connection_Encryption 0x0013 //enable or disable the link level encryption.
+#define HCI_CMD_Change_Connection_Link_Key 0x0015 //force the change of a link key to a new one between two connected devices.
+#define HCI_CMD_Master_Link_Key 0x0017 //force two devices to use the master's link key temporarily.
+#define HCI_CMD_Remote_Name_Request 0x0019 //determine the user friendly name of the connected device.
+#define HCI_CMD_Read_Remote_Supported_Features 0x001B //determine the features supported by the connected device.
+#define HCI_CMD_Read_Remote_Version_Information 0x001D //determine the version information of the connected device.
+#define HCI_CMD_Read_Clock_Offset 0x001F //read the clock offset of the remote device.
+//BT2.1 SSP
+#define HCI_CMD_IO_Capability_Request_Reply 0x002B
+#define HCI_CMD_User_Confirmation_Request_Reply 0x002C
+#define HCI_CMD_User_Confirmation_Request_Negative_Reply 0x002D
+#define HCI_CMD_User_Passkey_Request_Reply 0x002E
+#define HCI_CMD_User_Passkey_Request_Negative_Reply 0x002F
+#define HCI_CMD_Remote_OOB_Data_Request_Reply 0x0030
+#define HCI_CMD_Remote_OOB_Data_Request_Negative_Reply 0x0033
+#define HCI_CMD_IO_Capability_Request_Negative_Reply 0x0034
+
+#define HCI_OGF_Policy 2
+
+#define HCI_CMD_Hold_Mode 0x0001 //place the current or remote device into the Hold mode state.
+#define HCI_CMD_Sniff_Mode 0x0003 //place the current or remote device into the Sniff mode state.
+#define HCI_CMD_Exit_Sniff_Mode 0x0004 //exit the current or remote device from the Sniff mode state.
+#define HCI_CMD_Park_Mode 0x0005 //place the current or remote device into the Park mode state.
+#define HCI_CMD_Exit_Park_Mode 0x0006 //exit the current or remote device from the Park mode state.
+#define HCI_CMD_QoS_Setup 0x0007 //setup the Quality of Service parameters of the device.
+#define HCI_CMD_Role_Discovery 0x0009 //determine the role of the device for a particular connection.
+#define HCI_CMD_Switch_Role 0x000B //allow the device to switch roles for a particular connection.
+#define HCI_CMD_Read_Link_Policy_Settings 0x000C //determine the link policy that the LM can use to establish connections.
+#define HCI_CMD_Write_Link_Policy_Settings 0x000D //set the link policy that the LM can use for a particular connection.
+
+
+#define HCI_OGF_Controller_and_Baseband 3
+
+#define HCI_CMD_Set_Event_Mask 0x0001 //set which events are generated by the HCI for the host.
+#define HCI_CMD_Reset 0x0003 //reset the host controller, link manager and the radio module.
+#define HCI_CMD_Set_Event_Filter 0x0005 //used by host to set the different types of event filters that the host needs to receive.
+#define HCI_CMD_Flush 0x0008 //flush all pending data packets for transmission for a particular connection handle.
+#define HCI_CMD_Read_PIN_Type 0x0009 //used by host to determine if the link manager assumes that the host requires a variable PIN type or fixed PIN code. PIN is used during pairing.
+#define HCI_CMD_Write_PIN_Type 0x000A //used by host to write to the host controller on the PIN type supported by the host.
+#define HCI_CMD_Create_New_Unit_Key 0x000B //create a new unit key.
+#define HCI_CMD_Read_Stored_Link_Key 0x000D //read the link key stored in the host controller.
+#define HCI_CMD_Write_Stored_Link_Key 0x0011 //write the link key to the host controller.
+#define HCI_CMD_Delete_Stored_Link_Key 0x0012 //delete a stored link key in the host controller.
+#define HCI_CMD_Change_Local_Name 0x0013 //modify the user friendly name of the device.
+#define HCI_CMD_Read_Local_Name 0x0014 //read the user friendly name of the device.
+#define HCI_CMD_Read_Connection_Accept_Timeout 0x0015 //determine the timeout session before the host denies and rejects a new connection request.
+#define HCI_CMD_Write_Connection_Accept_Timeout 0x0016 //set the timeout session before a device can deny or reject a connection request.
+#define HCI_CMD_Read_Page_Timeout 0x0017 //read the timeout value where a device will wait for a connection acceptance before sending a connection failure is returned.
+#define HCI_CMD_Write_Page_Timeout 0x0018 //write the timeout value where a device will wait for a connection acceptance before sending a connection failure is returned.
+#define HCI_CMD_Read_Scan_Enable 0x0019 //read the status of the Scan_Enable configuration.
+#define HCI_CMD_Write_Scan_Enable 0x001A //set the status of the Scan_Enable configuration.
+#define HCI_CMD_Read_Page_Scan_Activity 0x001B //read the value of the Page_Scan_Interval and Page_Scan_Window configurations.
+#define HCI_CMD_Write_Page_Scan_Activity 0x001C //write the value of the Page_Scan_Interval and Page_Scan_Window configurations.
+#define HCI_CMD_Read_Inquiry_Scan_Activity 0x001D //read the value of the Inquiry_Scan_Interval and Inquiry_Scan_Window configurations.
+#define HCI_CMD_Write_Inquiry_Scan_Activity 0x001E //set the value of the Inquiry_Scan_Interval and Inquiry_Scan_Window configurations.
+#define HCI_CMD_Authentication_Enable 0x001F //read the Authentication_Enable parameter.
+#define HCI_CMD_Write_Authentication_Enable 0x0020 //set the Authentication_Enable parameter.
+#define HCI_CMD_Read_Encryption_Mode 0x0021 //read the Encryption_Mode parameter.
+#define HCI_CMD_Write_Encryption_Mode 0x0022 //write the Encryption_Mode parameter.
+#define HCI_CMD_Read_Class_Of_Device 0x0023 //read the Class_Of_Device parameter.
+#define HCI_CMD_Write_Class_Of_Device 0x0024 //set the Class_Of_Device parameter.
+#define HCI_CMD_Read_Voice_Setting 0x0025 //read the Voice_Setting parameter. Used for voice connections.
+#define HCI_CMD_Voice_Setting 0x0026 //set the Voice_Setting parameter. Used for voice connections.
+#define HCI_CMD_Read_Automatic_Flush_Timeout 0x0027 //read the Flush_Timeout parameter. Used for ACL connections only.
+#define HCI_CMD_Write_Automatic_Flush_Timeout 0x0028 //set the Flush_Timeout parameter. Used for ACL connections only.
+#define HCI_CMD_Read_Num_Broadcast_Retransmissions 0x0029 //read the number of time a broadcast message is retransmitted.
+#define HCI_CMD_Write_Num_Broadcast_Retransmissions 0x002A //set the number of time a broadcast message is retransmitted.
+#define HCI_CMD_Read_Hold_Mode_Activity 0x002B //set the Hold_Mode activity to instruct the device to perform an activity during hold mode.
+#define HCI_CMD_Write_Hold_Mode_Activity 0x002C //set the Hold_Mode_Activity parameter.
+#define HCI_CMD_Transmit_Power_Level 0x002D //read the power level required for transmission for a connection handle.
+#define HCI_CMD_Read_SCO_Flow_Control_Enable 0x002E //check the current status of the flow control for the SCO connection.
+#define HCI_CMD_SCO_Flow_Control_Enable 0x002F //set the status of the flow control for a connection handle.
+#define HCI_CMD_Set_Host_Controller_To_Host_Flow_Control 0x0031 //set the flow control from the host controller to host in on or off state.
+#define HCI_CMD_Host_Buffer_Size 0x0033 //set by host to inform the host controller of the buffer size of the host for ACL and SCO connections.
+#define HCI_CMD_Host_Number_Of_Completed_Packets 0x0035 //set from host to host controller when it is ready to receive more data packets.
+#define HCI_CMD_Read_Link_Supervision_Timeout 0x0036 //read the timeout for monitoring link losses.
+#define HCI_CMD_Write_Link_Supervision_Timeout 0x0037 //set the timeout for monitoring link losses.
+#define HCI_CMD_Read_Number_Of_Supported_IAC 0x0038 //read the number of IACs that the device can listen on during Inquiry access.
+#define HCI_CMD_Read_Current_IAC_LAP 0x0039 //read the LAP for the current IAC.
+#define HCI_CMD_Write_Current_IAC_LAP 0x003A //set the LAP for the current IAC.
+#define HCI_CMD_Read_Page_Scan_Period_Mode 0x003B //read the timeout session of a page scan.
+#define HCI_CMD_Write_Page_Scan_Period_Mode 0x003C //set the timeout session of a page scan.
+#define HCI_CMD_Read_Page_Scan_Mode 0x003D //read the default Page scan mode.
+#define HCI_CMD_Write_Page_Scan_Mode 0x003E //set the default page scan mode.
+//BT2.1 SSP
+#define HCI_CMD_Write_Simple_Pairing_Mode 0x0056
+
+
+#define HCI_OGF_Informational 4
+
+#define HCI_CMD_Read_Local_Version_Information 0x0001
+#define HCI_CMD_Read_Local_Supported_Features 0x0003
+#define HCI_CMD_Read_Buffer_Size 0x0005
+#define HCI_CMD_Read_Country_Code 0x0007
+#define HCI_CMD_Read_BD_ADDR 0x0009
+
+
+//EVENTS
+
+#define HCI_EVT_Inquiry_Complete_Event 0x01 //Indicates the Inquiry has finished.
+#define HCI_EVT_Inquiry_Result_Event 0x02 //Indicates that Bluetooth device(s) have responded for the inquiry.
+#define HCI_EVT_Connection_Complete_Event 0x03 //Indicates to both hosts that the new connection has been formed.
+#define HCI_EVT_Connection_Request_Event 0x04 //Indicates that a new connection is trying to be established.
+#define HCI_EVT_Disconnection_Complete_Event 0x05 //Occurs when a connection has been disconnected.
+#define HCI_EVT_Authentication_Complete_Event 0x06 //Occurs when an authentication has been completed.
+#define HCI_EVT_Remote_Name_Request_Complete_Event 0x07 //Indicates that the request for the remote name has been completed.
+#define HCI_EVT_Encryption_Change_Event 0x08 //Indicates that a change in the encryption has been completed.
+#define HCI_EVT_Change_Connection_Link_Key_Complete_Event 0x09 //Indicates that the change in the link key has been completed.
+#define HCI_EVT_Master_Link_Key_Complete_Event 0x0A //Indicates that the change in the temporary link key or semi permanent link key on the master device is complete.
+#define HCI_EVT_Read_Remote_Supported_Features_Complete_Event 0x0B //Indicates that the reading of the supported features on the remote device is complete.
+#define HCI_EVT_Read_Remote_Version_Complete_Event 0x0C //Indicates that the version number on the remote device has been read and completed.
+#define HCI_EVT_QOS_Setup_Complete_Event 0x0D //Indicates that the Quality of Service setup has been complete.
+#define HCI_EVT_Command_Complete_Event 0x0E //Used by controller to send status and event parameters to the host for the particular command.
+#define HCI_EVT_Command_Status_Event 0x0F //Indicates that the command has been received and is being processed in the host controller.
+#define HCI_EVT_Hardware_Error_Event 0x10 //Indicates a hardware failure of the Bluetooth device.
+#define HCI_EVT_Flush_Occured_event 0x11 //Indicates that the data has been flushed for a particular connection.
+#define HCI_EVT_Role_Change_Event 0x12 //Indicates that the current bluetooth role for a connection has been changed.
+#define HCI_EVT_Number_Of_Completed_Packets_Event 0x13 //Indicates to the host the number of data packets sent compared to the last time the same event was sent.
+#define HCI_EVT_Mode_Change_Event 0x14 //Indicates the change in mode from hold, sniff, park or active to another mode.
+#define HCI_EVT_Return_Link_Keys_Event 0x15 //Used to return stored link keys after a Read_Stored_Link_Key command was issued.
+#define HCI_EVT_PIN_Code_Request_Event 0x16 //Indicates the a PIN code is required for a new connection.
+#define HCI_EVT_Link_Key_Request_Event 0x17 //Indicates that a link key is required for the connection.
+#define HCI_EVT_Link_Key_Notification_Event 0x18 //Indicates to the host that a new link key has been created.
+#define HCI_EVT_Loopback_Command_Event 0x19 //Indicates that command sent from the host will be looped back.
+#define HCI_EVT_Data_Buffer_Overflow_Event 0x1A //Indicates that the data buffers on the host has overflowed.
+#define HCI_EVT_Max_Slots_Change_Event 0x1B //Informs the host when the LMP_Max_Slots parameter changes.
+#define HCI_EVT_Read_Clock_Offset_Complete_Event 0x1C //Indicates the completion of reading the clock offset information.
+#define HCI_EVT_Connection_Packet_Type_Changed_Event 0x1D //Indicate the completion of the packet type change for a connection.
+#define HCI_EVT_QoS_Violation_Event 0x1E //Indicates that the link manager is unable to provide the required Quality of Service.
+#define HCI_EVT_Page_Scan_Mode_Change_Event 0x1F //Indicates that the remote device has successfully changed the Page Scan mode.
+#define HCI_EVT_Page_Scan_Repetition_Mode_Change_Event 0x20 //Indicates that the remote device has successfully changed the Page Scan Repetition mode.
+//BT2.1 SSP
+#define HCI_EVT_IO_Capability_Request_Event 0x31
+#define HCI_EVT_IO_Capability_Response_Event 0x32
+#define HCI_EVT_User_Confirmation_Request_Event 0x33
+#define HCI_EVT_User_Passkey_Request_Event 0x34
+#define HCI_EVT_Remote_OOB Data_Request_Event 0x35
+#define HCI_EVT_Simple_Pairing_Complete_Event 0x36
+#define HCI_EVT_User_Passkey_Notification_Event 0x3B
+
+
+
+
+//ERRORS
+
+#define HCI_ERR_Unknown_HCI_Command 0x01
+#define HCI_ERR_No_Connection 0x02
+#define HCI_ERR_Hardware_Failure 0x03
+#define HCI_ERR_Page_Timeout 0x04
+#define HCI_ERR_Authentication_Failure 0x05
+#define HCI_ERR_Key_Missing 0x06
+#define HCI_ERR_Memory_Full 0x07
+#define HCI_ERR_Connection_Timeout 0x08
+#define HCI_ERR_Max_Number_Of_Connections 0x09
+#define HCI_ERR_Max_Number_Of_SCO_Connections_To_A_Device 0x0A
+#define HCI_ERR_ACL_Connection_Already_Exists 0x0B
+#define HCI_ERR_Command_Disallowed 0x0C
+#define HCI_ERR_Host_Rejected_Due_To_Limited_Resources 0x0D
+#define HCI_ERR_Host_Rejected_Due_To_Security_Reasons 0x0E
+#define HCI_ERR_Host_Rejected_Due_To_A_Remote_Device_Only_A_Personal_Device 0x0F
+#define HCI_ERR_Host_Timeout 0x10
+#define HCI_ERR_Unsupported_Feature_Or_Parameter_Value 0x11
+#define HCI_ERR_Invalid_HCI_Command_Parameters 0x12
+#define HCI_ERR_Other_End_Terminated_Connection_User_Ended_Connection 0x13
+#define HCI_ERR_Other_End_Terminated_Connection_Low_Resources 0x14
+#define HCI_ERR_Other_End_Terminated_Connection_About_To_Power_Off 0x15
+#define HCI_ERR_Connection_Terminated_By_Local_Host 0x16
+#define HCI_ERR_Repeated_Attempts 0x17
+#define HCI_ERR_Pairing_Not_Allowed 0x18
+#define HCI_ERR_Unknown_LMP_PDU 0x19
+#define HCI_ERR_Unsupported_Remote_Feature 0x1A
+#define HCI_ERR_SCO_Offset_Rejected 0x1B
+#define HCI_ERR_SCO_Interval_Rejected 0x1C
+#define HCI_ERR_SCO_Air_Mode_Rejected 0x1D
+#define HCI_ERR_Invalid_LMP_Parameters 0x1E
+#define HCI_ERR_Unspecified_Error 0x1F
+#define HCI_ERR_Unsupported_LMP_Parameter 0x20
+#define HCI_ERR_Role_Change_Not_Allowed 0x21
+#define HCI_ERR_LMP_Response_Timeout 0x22
+#define HCI_ERR_LMP_Error_Transaction_Collision 0x23
+#define HCI_ERR_LMP_PDU_Not_Allowed 0x24
+#define HCI_ERR_Encryption_Mode_Not_Acceptable 0x25
+#define HCI_ERR_Unit_Key_Used 0x26
+#define HCI_ERR_QoS_Not_Supported 0x27
+#define HCI_ERR_Instant_Passed 0x28
+#define HCI_ERR_Pairing_With_Unit_Key_Not_Supported 0x29
+
+#endif
diff --git a/library/ADK2/I2C.c b/library/ADK2/I2C.c
new file mode 100644
index 0000000..be730a3
--- /dev/null
+++ b/library/ADK2/I2C.c
@@ -0,0 +1,602 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "I2C.h"
+#include "coop.h"
+#include "dbg.h"
+
+// the hardware interface in this chip is as pleasant to use as cuddling a pirahna, hence the bit-bang solution.
+// to use the hardware, set I2C_BITBANG to 0.
+// to use the peripheral DMA with the I2C hardware, set I2C_PDC to 1.
+#define I2C_BITBANG 0
+#define I2C_PDC 1
+#define I2C_INT_PDC 1
+
+#define I2C_STAT_DONE 0
+#define I2C_STAT_LASTREAD 2
+#define I2C_STAT_BUSY 1
+#define I2C_STAT_NACK 3
+
+typedef struct _i2cInst
+{
+ Twi *pTwi;
+ volatile uint8_t status;
+ uint8_t *lastByte;
+} i2c_i;
+
+static i2c_i i2cInst[I2C_NUM_INSTANCES] = { { TWI0, 0, 0 }, { TWI1, 0, 0 } };
+
+static char sdaRd(uint8_t instance);
+static void sdaLo(uint8_t instance);
+static void sdaHi(uint8_t instance);
+static void sclLo(uint8_t instance);
+static void sclHi(uint8_t instance);
+static void i2cBitTx(uint8_t instance, char bit);
+static void i2cStop(uint8_t instance);
+static void i2cPdcDisable(Twi *pTwi);
+
+ //sda first please
+static const uint8_t pins[I2C_NUM_INSTANCES][2] = { { PORTA(17), PORTA(18) }, { PORTB(12), PORTB(13) } };
+static uint32_t delayTicks[I2C_NUM_INSTANCES];
+
+
+static void i2cDelay(uint8_t instance){
+
+ fwkDelay(delayTicks[instance]);
+}
+
+void i2cClock(uint8_t instance, uint32_t clock){
+#if I2C_BITBANG
+ delayTicks[instance] = (TICKS_PER_MS * 1000) / (8 * clock * 2);
+#else
+ Twi *pTwi;
+ uint32_t dwCkDiv = 0;
+ uint32_t dwClDiv;
+ uint32_t dwOk = 0;
+ if (instance == 0)
+ pTwi = TWI0;
+ else
+ pTwi = TWI1;
+
+ while (!dwOk) {
+ dwClDiv = ((BOARD_MCK / (2 * clock)) - 4) / (1 << dwCkDiv);
+ if (dwClDiv <= 255)
+ dwOk = 1;
+ else
+ dwCkDiv++;
+ }
+ pTwi->TWI_CWGR = 0;
+ pTwi->TWI_CWGR = (dwCkDiv << 16) | (dwClDiv << 8) | dwClDiv;
+#endif
+}
+
+// i2c interrupt handler used only for PDC mode
+// to prevent runaway operations caused by not responding
+// fast enough and setting the stop bit.
+void i2c_handler( i2c_i *pInst )
+{
+ uint32_t status;
+ Twi *pTwi = pInst->pTwi;
+
+ status = pTwi->TWI_SR & pTwi->TWI_IMR; // Masked status
+
+ if (TWI_SR_TXBUFE & status) { // Transmit has completed.
+ i2cPdcDisable(pTwi);
+ pTwi->TWI_CR = TWI_CR_STOP;
+ pTwi->TWI_IDR = TWI_IDR_TXBUFE;
+ pTwi->TWI_IER = TWI_IER_TXCOMP;
+ } else if (TWI_SR_RXBUFF & status) { // Receive has completed
+ if (pInst->status == I2C_STAT_LASTREAD) {
+ i2cPdcDisable(pTwi);
+ pTwi->TWI_IDR = TWI_IDR_RXBUFF;
+ pTwi->TWI_IER = TWI_IER_TXCOMP;
+ } else {
+ pInst->status = I2C_STAT_LASTREAD;
+ i2cPdcDisable(pTwi);
+ pTwi->TWI_CR = TWI_CR_STOP;
+ pTwi->TWI_RPR = pInst->lastByte;
+ pTwi->TWI_RCR = 1;
+ pTwi->TWI_PTCR = TWI_PTCR_RXTEN;
+ }
+ } else if (TWI_SR_TXCOMP & status) {
+ pInst->status = I2C_STAT_DONE;
+ pTwi->TWI_IDR = TWI_IDR_TXCOMP;
+ } else if (TWI_SR_NACK & status) {
+ pInst->status = I2C_STAT_NACK;
+ i2cPdcDisable(pTwi);
+ }
+}
+
+void TWI0_Handler(void)
+{
+ i2c_handler(&i2cInst[0]);
+}
+
+void TWI1_Handler(void)
+{
+ i2c_handler(&i2cInst[1]);
+}
+
+uint8_t i2cInit(uint8_t instance, uint32_t clock){
+ uint8_t i;
+
+ if(instance >= I2C_NUM_INSTANCES) return I2C_ERR_INVAL;
+
+ gpioSetFun(pins[instance][0], GPIO_FUNC_GPIO);
+ gpioSetFun(pins[instance][1], GPIO_FUNC_GPIO);
+ gpioSetPullup(pins[instance][0], 1);
+ gpioSetPullup(pins[instance][1], 1);
+ gpioSetDir(pins[instance][0], 0);
+ gpioSetDir(pins[instance][1], 0);
+ gpioSetVal(pins[instance][0], 0);
+ gpioSetVal(pins[instance][1], 0);
+ sdaHi(instance);
+ sclHi(instance);
+ delayTicks[instance] = (TICKS_PER_MS * 1000) / (8 * clock * 2);
+ i2cDelay(instance);
+ i2cDelay(instance);
+ for (i = 0; i < 100; i++) // Try to reset the bus
+ i2cBitTx(instance, 1);
+ i2cStop(instance);
+
+#if !I2C_BITBANG
+ PMC_EnablePeripheral(instance ? ID_TWI1 : ID_TWI0);
+ gpioSetFun(pins[instance][0], GPIO_FUNC_A);
+ gpioSetFun(pins[instance][1], GPIO_FUNC_A);
+ TWI_ConfigureMaster(instance ? TWI1 : TWI0, clock, BOARD_MCK);
+
+#if I2C_INT_PDC
+ NVIC_EnableIRQ(instance ? TWI1_IRQn : TWI0_IRQn);
+ if (instance)
+ TWI1->TWI_IDR = 0x00F77;
+ else
+ TWI0->TWI_IDR = 0x00F77;
+#endif
+
+#endif
+
+
+ return I2C_ALL_OK;
+}
+
+static void i2cStart(uint8_t instance){
+
+ sdaHi(instance);
+ sclHi(instance);
+ i2cDelay(instance);
+ sdaLo(instance);
+ i2cDelay(instance);
+ sclLo(instance);
+ i2cDelay(instance);
+}
+
+static void i2cStop(uint8_t instance){
+
+ i2cDelay(instance);
+ sdaLo(instance);
+ i2cDelay(instance);
+ sclHi(instance);
+ i2cDelay(instance);
+ sdaHi(instance);
+}
+
+static char i2cBitRx(uint8_t instance){
+
+ char ret;
+
+ sdaHi(instance);
+ i2cDelay(instance);
+ sclHi(instance);
+ i2cDelay(instance);
+ ret = sdaRd(instance);
+ sclLo(instance);
+
+ return ret;
+}
+
+static void i2cBitTx(uint8_t instance, char bit){
+
+ if(bit) sdaHi(instance);
+ else sdaLo(instance);
+ i2cDelay(instance);
+ sclHi(instance);
+ i2cDelay(instance);
+ sclLo(instance);
+}
+
+static char i2cSend(uint8_t instance, uint8_t val){ //return 1 -> ack, 0->nak
+
+ uint8_t i;
+
+ for(i = 0; i < 8; i++){
+ i2cBitTx(instance, !!(val & 0x80));
+ val <<= 1;
+ }
+ return !i2cBitRx(instance);
+}
+
+static uint8_t i2cRecv(uint8_t instance, char ack){
+
+ uint8_t i, v = 0;
+
+ for(i = 0; i < 8; i++){
+
+ v <<= 1;
+ if(i2cBitRx(instance)) v |= 1;
+ }
+ i2cBitTx(instance, !ack);
+ return v;
+}
+
+
+static void i2cWaitComplete(Twi *pTwi)
+{
+ while(!(pTwi->TWI_SR & TWI_SR_TXCOMP)) coopYield();
+}
+
+static uint32_t i2cWaitRx(Twi *pTwi)
+{
+ uint32_t stat;
+ do {
+ coopYield();
+ stat = pTwi->TWI_SR;
+ if (stat & TWI_SR_NACK) {
+ return stat;
+ }
+ } while (!(stat & TWI_SR_RXRDY));
+}
+
+static uint32_t i2cWaitTx(Twi *pTwi)
+{
+ uint32_t stat;
+ do {
+ coopYield();
+ stat = pTwi->TWI_SR;
+ if (stat & TWI_SR_NACK) {
+ return stat;
+ }
+ } while (!(stat & TWI_SR_TXRDY));
+ return 0;
+}
+
+static void i2cPdcDisable(Twi *pTwi)
+{
+ pTwi->TWI_PTCR = TWI_PTCR_RXTDIS;
+ pTwi->TWI_PTCR = TWI_PTCR_TXTDIS;
+ pTwi->TWI_RPR = 0;
+ pTwi->TWI_RCR = 0;
+ pTwi->TWI_TPR = 0;
+ pTwi->TWI_TCR = 0;
+}
+
+static uint32_t i2cWaitPdcTx(Twi *pTwi)
+{
+ uint32_t stat;
+ do {
+ coopYield();
+ stat = pTwi->TWI_SR;
+ if (stat & TWI_SR_NACK) {
+ return stat;
+ }
+ } while (!(stat & TWI_SR_TXBUFE));
+ return stat;
+}
+
+static uint32_t i2cWaitPdcRx(Twi *pTwi)
+{
+ uint32_t stat;
+ do {
+ coopYield();
+ stat = pTwi->TWI_SR;
+ if ((stat & TWI_SR_NACK) || ((stat & TWI_SR_TXCOMP) && !(stat & TWI_SR_RXBUFF))) {
+ return stat;
+ }
+ } while(!(stat & TWI_SR_RXBUFF));
+ return stat;
+}
+
+uint8_t i2cOp(uint8_t instance, uint8_t addr, const uint8_t* sendData, uint8_t sendSz, uint8_t* recvData, uint8_t recvSz){
+
+ uint8_t ret = I2C_ERR_NAK;
+ uint32_t stat;
+
+#if I2C_PDC
+ uint8_t dat[256];
+ uint8_t i;
+ uint32_t tmp;
+ if (sendData != NULL && (uint32_t)sendData < 0x20000000) { /* Undocumented feature: PDC can't read from flash */
+ if (sendSz > 256)
+ return I2C_ERR_INVAL;
+ for (i = 0; i < sendSz; i++)
+ dat[i] = *sendData++;
+ sendData = dat;
+ }
+#endif
+
+#if !I2C_BITBANG
+ Twi *pTwi;
+#endif
+
+ if(instance >= I2C_NUM_INSTANCES) return I2C_ERR_INVAL;
+
+#if !I2C_BITBANG
+ pTwi = (instance == 0) ? TWI0 : TWI1;
+#endif
+
+#if I2C_BITBANG
+ addr <<= 1;
+
+ if(sendSz || !recvSz){ //if neither send nor recv requested, do a single send -> this is for a scan
+
+ i2cStart(instance);
+
+ if(!i2cSend(instance, addr)) goto out;
+ while(sendSz--) if(!i2cSend(instance, *sendData++)) goto out;
+ }
+ if(recvSz){
+
+ i2cStart(instance); //if we already sent something, restart
+
+ if(!i2cSend(instance, addr | 1)) goto out;
+ while(recvSz){
+ recvSz--;
+ *recvData++ = i2cRecv(instance, !!recvSz);
+ }
+ }
+
+ ret = I2C_ALL_OK;
+#else
+
+ if (sendSz == 0 && recvSz == 0) { // Quick (for a scan)
+ pTwi->TWI_MMR = 0;
+ pTwi->TWI_MMR = (addr << 16);
+ pTwi->TWI_CR = TWI_CR_QUICK;
+ if (TWI_SR_NACK & i2cWaitTx(pTwi)) {
+ i2cWaitComplete(pTwi);
+ ret = I2C_ERR_NAK;
+ goto out;
+ }
+ i2cWaitComplete(pTwi);
+ }
+
+#if I2C_PDC
+ if (sendSz != 0) {
+ pTwi->TWI_TPR = (uint32_t)sendData;
+ pTwi->TWI_TCR = sendSz;
+ pTwi->TWI_MMR = 0;
+ pTwi->TWI_MMR = (addr << 16);
+ pTwi->TWI_IADR = 0;
+ pTwi->TWI_IADR = 0;
+ pTwi->TWI_PTCR = TWI_PTCR_TXTEN;
+#if I2C_INT_PDC
+ i2cInst[instance].status = I2C_STAT_BUSY;
+ pTwi->TWI_IER = TWI_IER_TXBUFE | TWI_IER_NACK;
+ while((i2cInst[instance].status != I2C_STAT_DONE) &&
+ (i2cInst[instance].status != I2C_STAT_NACK))
+ coopYield();
+ if (i2cInst[instance].status == I2C_STAT_NACK) {
+ ret = I2C_ERR_NAK;
+ goto out;
+ }
+#else
+
+ if (TWI_SR_NACK & i2cWaitPdcTx(pTwi)) {
+ i2cPdcDisable(pTwi);
+ i2cWaitComplete(pTwi);
+ ret = I2C_ERR_NAK;
+ goto out;
+ }
+ i2cPdcDisable(pTwi);
+ pTwi->TWI_CR = TWI_CR_STOP;
+ i2cWaitComplete(pTwi);
+#endif
+ }
+
+ if (recvSz == 1) { // We are forced to do the one byte reads manually.
+ pTwi->TWI_RPR = (uint32_t)recvData;
+ pTwi->TWI_RCR = 1;
+ pTwi->TWI_MMR = 0;
+ pTwi->TWI_MMR = TWI_MMR_MREAD | (addr << 16);
+ pTwi->TWI_CR = TWI_CR_START | TWI_CR_STOP;
+ pTwi->TWI_PTCR = TWI_PTCR_RXTEN;
+#if I2C_INT_PDC
+ i2cInst[instance].status = I2C_STAT_LASTREAD;
+ pTwi->TWI_IER = TWI_IER_RXBUFF | TWI_IER_NACK;
+ while((i2cInst[instance].status != I2C_STAT_DONE) &&
+ (i2cInst[instance].status != I2C_STAT_NACK))
+ coopYield();
+ if (i2cInst[instance].status == I2C_STAT_NACK) {
+ ret = I2C_ERR_NAK;
+ goto out;
+ }
+#else
+
+ if (TWI_SR_NACK & i2cWaitPdcRx(pTwi)) {
+ i2cPdcDisable(pTwi);
+ i2cWaitComplete(pTwi);
+ ret = I2C_ERR_NAK;
+ goto out;
+ }
+ i2cPdcDisable(pTwi);
+ i2cWaitComplete(pTwi);
+#endif
+ }
+
+ if (recvSz > 1) {
+ pTwi->TWI_RPR = (uint32_t)recvData;
+ pTwi->TWI_RCR = recvSz - 1; // Last byte read is handled manually
+ pTwi->TWI_MMR = 0;
+ pTwi->TWI_MMR = TWI_MMR_MREAD | (addr << 16);
+ pTwi->TWI_CR = TWI_CR_START;
+ pTwi->TWI_PTCR = TWI_PTCR_RXTEN;
+
+#if I2C_INT_PDC
+ i2cInst[instance].lastByte = recvData + recvSz - 1;
+ i2cInst[instance].status = I2C_STAT_BUSY;
+ pTwi->TWI_IER = TWI_IER_RXBUFF | TWI_IER_NACK;
+ while((i2cInst[instance].status != I2C_STAT_DONE) &&
+ (i2cInst[instance].status != I2C_STAT_NACK))
+ coopYield();
+ if (i2cInst[instance].status == I2C_STAT_NACK) {
+ ret = I2C_ERR_NAK;
+ goto out;
+ }
+#else
+ if (TWI_SR_NACK & i2cWaitPdcRx(pTwi)) {
+ i2cPdcDisable(pTwi);
+ i2cWaitComplete(pTwi);
+ ret = I2C_ERR_NAK;
+ goto out;
+ }
+ i2cPdcDisable(pTwi);
+ pTwi->TWI_CR = TWI_CR_STOP;
+ pTwi->TWI_RPR = (uint32_t)(recvData + recvSz - 1);
+ pTwi->TWI_RCR = 1;
+ pTwi->TWI_PTCR = TWI_PTCR_RXTEN;
+ if (TWI_SR_NACK & i2cWaitPdcRx(pTwi)) {
+ i2cPdcDisable(pTwi);
+ i2cWaitComplete(pTwi);
+ ret = I2C_ERR_NAK;
+ goto out;
+ }
+ i2cPdcDisable(pTwi);
+ i2cWaitComplete(pTwi);
+#endif
+ }
+ ret = I2C_ALL_OK;
+#else
+ if (sendSz != 0) {
+ pTwi->TWI_MMR = 0;
+ pTwi->TWI_MMR = (addr << 16);
+ pTwi->TWI_IADR = 0;
+ pTwi->TWI_IADR = 0;
+ while (sendSz--) {
+ pTwi->TWI_THR = *sendData++;
+ stat = i2cWaitTx(pTwi);
+ if (stat & TWI_SR_NACK) {
+ ret = I2C_ERR_NAK;
+ goto out;
+ }
+ }
+ pTwi->TWI_CR = TWI_CR_STOP;
+ i2cWaitComplete(pTwi);
+ }
+
+ if (recvSz == 1) {
+ pTwi->TWI_MMR = 0;
+ pTwi->TWI_MMR = TWI_MMR_MREAD | (addr << 16);
+ pTwi->TWI_IADR = 0;
+ pTwi->TWI_IADR = 0;
+ pTwi->TWI_CR = TWI_CR_START | TWI_CR_STOP;
+ if (TWI_SR_NACK & i2cWaitRx(pTwi)) {
+ ret = I2C_ERR_NAK;
+ goto out;
+ }
+ *recvData = pTwi->TWI_RHR;
+ i2cWaitComplete(pTwi);
+ } else if (recvSz >= 1) {
+ pTwi->TWI_MMR = 0;
+ pTwi->TWI_MMR = TWI_MMR_MREAD | (addr << 16);
+ pTwi->TWI_IADR = 0;
+ pTwi->TWI_IADR = 0;
+ pTwi->TWI_CR = TWI_CR_START;
+ while (recvSz--) {
+ if (TWI_SR_NACK & i2cWaitRx(pTwi)) {
+ ret = I2C_ERR_NAK;
+ goto out;
+ }
+ dbgPrintf("\0");
+ *recvData++ = pTwi->TWI_RHR;
+ if (recvSz == 1) pTwi->TWI_CR = TWI_CR_STOP;
+ }
+ i2cWaitComplete(pTwi);
+ }
+
+ ret = I2C_ALL_OK;
+#endif
+#endif
+
+out:
+
+#if I2C_BITBANG
+ i2cStop(instance);
+#else
+ if (ret != I2C_ALL_OK) {
+ pTwi->TWI_CR = TWI_CR_STOP;
+ i2cWaitComplete(pTwi);
+ }
+#endif
+
+ return ret;
+}
+
+uint8_t i2cSingleWrite(uint8_t instance, uint8_t addr, uint8_t reg, uint8_t val){
+
+ unsigned char data[2] = {reg, val};
+
+ return i2cOp(instance, addr, data, 2, NULL, 0);
+}
+
+uint8_t i2cSingleRead(uint8_t instance, uint8_t addr, uint8_t reg){
+
+ uint8_t ret, val;
+
+ ret = i2cOp(instance, addr, ®, 1, &val, 1);
+
+ if(ret != I2C_ALL_OK) val = 0xFF;
+
+ return val;
+}
+
+uint8_t i2cQuick(uint8_t instance, uint8_t addr, uint8_t byte){
+
+ return i2cOp(instance, addr, &byte, 1, NULL, 0);
+}
+
+uint8_t i2cScan(uint8_t instance, uint8_t addr){
+
+ return i2cOp(instance, addr, NULL, 0, NULL, 0);
+}
+
+static char sdaRd(uint8_t instance){
+
+ return gpioGetVal(pins[instance][0]);
+}
+
+static void sdaLo(uint8_t instance){
+
+ gpioSetDir(pins[instance][0], 0);
+}
+
+static void sdaHi(uint8_t instance){
+
+ gpioSetDir(pins[instance][0], 1);
+}
+
+static void sclLo(uint8_t instance){
+
+ gpioSetDir(pins[instance][1], 0);
+}
+
+static void sclHi(uint8_t instance){
+
+ gpioSetDir(pins[instance][1], 1);
+ while(!gpioGetVal(pins[instance][1]));
+}
+
+
+
diff --git a/library/ADK2/I2C.h b/library/ADK2/I2C.h
new file mode 100644
index 0000000..bf1a917
--- /dev/null
+++ b/library/ADK2/I2C.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _I2C_H_
+#define _I2C_H_
+
+
+#define I2C_ALL_OK 0 //all OK
+#define I2C_ERR_NAK 1 //got a NAK
+#define I2C_ERR_INVAL 2 //invalid command given
+
+#define I2C_NUM_INSTANCES 2
+
+//basic interface
+uint8_t i2cInit(uint8_t instance, uint32_t clock);
+void i2cClock(uint8_t instance, uint32_t clock);
+uint8_t i2cOp(uint8_t instance, uint8_t addr, const uint8_t* sendData, uint8_t sendSz, uint8_t* recvData, uint8_t recvSz);
+
+//convenience
+uint8_t i2cSingleWrite(uint8_t instance, uint8_t addr, uint8_t reg, uint8_t val);
+uint8_t i2cSingleRead(uint8_t instance, uint8_t addr, uint8_t reg);
+uint8_t i2cQuick(uint8_t instance, uint8_t addr, uint8_t byte);
+uint8_t i2cScan(uint8_t instance, uint8_t addr);
+
+#endif
+#endif
+
diff --git a/library/ADK2/LEDs.c b/library/ADK2/LEDs.c
new file mode 100644
index 0000000..8c35088
--- /dev/null
+++ b/library/ADK2/LEDs.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "LEDs.h"
+#include "fwk.h"
+
+
+static const uint8_t blanks[] = {PORTB(8), PORTC(25), PORTC(26), PORTC(27)};
+#define MISO PORTA(25)
+#define MOSI PORTA(26)
+#define SCLK PORTA(27)
+#define XLAT PORTA(28)
+#define DBGLED PORTC(9)
+
+static const uint16_t led_gamma[256] =
+{
+ 0, 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 17, 19,
+ 21, 23, 25, 27, 29, 32, 34, 37, 40, 43, 46, 49, 52, 55, 59, 62, 66, 70, 73,
+ 77, 82, 86, 90, 95, 99, 104, 109, 114, 119, 124, 129, 135, 140, 146, 152,
+ 158, 164, 170, 176, 182, 189, 196, 202, 209, 216, 224, 231, 238, 246, 254,
+ 261, 269, 277, 286, 294, 302, 311, 320, 328, 337, 347, 356, 365, 375, 384,
+ 394, 404, 414, 424, 435, 445, 456, 467, 477, 488, 500, 511, 522, 534, 545,
+ 557, 569, 581, 594, 606, 619, 631, 644, 657, 670, 683, 697, 710, 724, 738,
+ 752, 766, 780, 794, 809, 823, 838, 853, 868, 884, 899, 914, 930, 946, 962,
+ 978, 994, 1011, 1027, 1044, 1061, 1078, 1095, 1112, 1130, 1147, 1165, 1183,
+ 1201, 1219, 1237, 1256, 1274, 1293, 1312, 1331, 1350, 1370, 1389, 1409,
+ 1429, 1449, 1469, 1489, 1509, 1530, 1551, 1572, 1593, 1614, 1635, 1657,
+ 1678, 1700, 1722, 1744, 1766, 1789, 1811, 1834, 1857, 1880, 1903, 1926,
+ 1950, 1974, 1997, 2021, 2045, 2070, 2094, 2119, 2143, 2168, 2193, 2219,
+ 2244, 2270, 2295, 2321, 2347, 2373, 2400, 2426, 2453, 2479, 2506, 2534,
+ 2561, 2588, 2616, 2644, 2671, 2700, 2728, 2756, 2785, 2813, 2842, 2871,
+ 2900, 2930, 2959, 2989, 3019, 3049, 3079, 3109, 3140, 3170, 3201, 3232,
+ 3263, 3295, 3326, 3358, 3390, 3421, 3454, 3486, 3518, 3551, 3584, 3617,
+ 3650, 3683, 3716, 3750, 3784, 3818, 3852, 3886, 3920, 3955, 3990, 4025,
+ 4060, 4095
+};
+
+
+#define NUM_ROWS 4
+#define XFERS_PER_LED 3
+#define XFERS_PER_ROW ((NUM_LEDS) * (XFERS_PER_LED) / (NUM_ROWS))
+
+
+
+const uint8_t digit_table[6] = {57, 41, 25, 50, 34, 18};
+const uint8_t icon_table[8] = {49, 33, 17, 1, 48, 32, 16, 0};
+const uint8_t seg_table[128] =
+ {
+ /* 0x00 - 0x0F */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0x10 - 0x1F */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0x20 - 0x2F */ 0x00, 0x6B, 0x22, 0x56, 0x64, 0x2D, 0x64, 0x02, 0x31, 0x07, 0x40, 0x40, 0x08, 0x40, 0x08, 0x52,
+ /* 0x30 - 0x3F */ 0x3F, 0x06, 0x5B, 0x4F, 0x66, 0x6D, 0x7D, 0x07, 0x7F, 0x6F, 0x08, 0x08, 0x58, 0x48, 0x4C, 0x0B,
+ /* 0x40 - 0x4F */ 0x63, 0x77, 0x7C, 0x58, 0x5E, 0x79, 0x71, 0x6F, 0x74, 0x10, 0x0E, 0x70, 0x38, 0x55, 0x54, 0x5C,
+ /* 0x50 - 0x5F */ 0x73, 0x67, 0x50, 0x6D, 0x78, 0x3E, 0x1C, 0x1D, 0x76, 0x6E, 0x5B, 0x59, 0x0F, 0x64, 0x23, 0x08,
+ /* 0x60 - 0x6F */ 0x20, 0x77, 0x7C, 0x58, 0x5E, 0x79, 0x71, 0x6F, 0x74, 0x10, 0x0E, 0x70, 0x38, 0x55, 0x54, 0x5C,
+ /* 0x70 - 0x7F */ 0x73, 0x67, 0x50, 0x6D, 0x78, 0x3E, 0x1C, 0x1D, 0x76, 0x6E, 0x5B, 0x46, 0x30, 0x70, 0x40, 0x00
+ };
+
+
+static uint8_t row = 0;
+static uint16_t led_buffer[192]={0,};
+
+
+
+void SPI0_Handler(void){
+
+ //disable the interrupt
+ gpioSetVal(XLAT, 1);
+ SPI0->SPI_IDR = SPI_IER_TXEMPTY;
+ gpioSetVal(XLAT, 0);
+ gpioSetVal(blanks[row], 0);
+}
+
+void ledsInit(void){
+
+ uint8_t i;
+
+ //init SPI
+ SPI_Configure(SPI0, ID_SPI0, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PCS(0));
+ SPI_ConfigureNPCS(SPI0, 0 , SPI_CSR_NCPHA | SPI_CSR_BITS_12_BIT | SPI_CSR_SCBR(3) | SPI_CSR_DLYBS(2) | SPI_CSR_DLYBCT(0)); //30MHz spi speed
+ SPI_Enable(SPI0);
+ SPI0->SPI_IDR = 0xFFFFFFFF;
+ NVIC_EnableIRQ(SPI0_IRQn);
+
+ //init pins: SPI
+ gpioSetFun(MISO, GPIO_FUNC_A);
+ gpioSetFun(MOSI, GPIO_FUNC_A);
+ gpioSetFun(SCLK, GPIO_FUNC_A);
+
+ //init pins: debug LED
+ gpioSetFun(DBGLED, GPIO_FUNC_GPIO);
+ gpioSetDir(DBGLED, 0);
+ gpioSetVal(DBGLED, 0);
+
+ //init pins: latch
+ gpioSetFun(XLAT, GPIO_FUNC_GPIO);
+ gpioSetDir(XLAT, 0);
+ gpioSetVal(XLAT, 0);
+
+ //init pins: blanking
+ for(i = 0; i < sizeof(blanks); i++){
+ gpioSetFun(blanks[i], GPIO_FUNC_GPIO);
+ gpioSetDir(blanks[i], 0);
+ gpioSetVal(blanks[i], 1);
+ }
+
+ periodicAdd(ledUpdate, 0, 4);
+}
+
+void ledWrite(uint8_t led_id, uint8_t r, uint8_t g, uint8_t b){
+
+ if(led_id >= NUM_LEDS) return;
+
+ led_id += led_id << 1;
+
+ led_buffer[led_id++] = led_gamma[b];
+ led_buffer[led_id++] = led_gamma[g];
+ led_buffer[led_id++] = led_gamma[r];
+}
+
+void ledDrawIcon(uint8_t offset, uint8_t r, uint8_t g, uint8_t b){
+
+ ledWrite(icon_table[offset], r, g, b);
+}
+
+void ledDrawLetter(char letter, uint8_t val, uint8_t r, uint8_t g, uint8_t b){
+
+ uint8_t i;
+ uint8_t seg = seg_table[val];
+ uint8_t offset = digit_table[letter];
+
+ for (i = 0; i < 7; i++, seg <<= 1) ledWrite(i + offset, (seg & 64) ? r : 0, (seg & 64) ? g : 0, (seg & 64) ? b : 0);
+}
+
+void ledUpdate(void){
+
+ volatile uint16_t* row_data;
+ unsigned i;
+
+ gpioSetVal(blanks[row], 1);
+
+ if(++row == NUM_ROWS) row = 0;
+ row_data = led_buffer + XFERS_PER_ROW * row;
+
+ DMAC->DMAC_CH_NUM[DMA_CHANNEL_LEDS].DMAC_SADDR = (uint32_t)row_data;
+ DMAC->DMAC_CH_NUM[DMA_CHANNEL_LEDS].DMAC_DADDR = (uint32_t)&SPI0->SPI_TDR;
+ DMAC->DMAC_CH_NUM[DMA_CHANNEL_LEDS].DMAC_DSCR = 0;
+ DMAC->DMAC_CH_NUM[DMA_CHANNEL_LEDS].DMAC_CTRLA = DMAC_CTRLA_BTSIZE(XFERS_PER_ROW) | DMAC_CTRLA_SCSIZE_CHK_16 | DMAC_CTRLA_DCSIZE_CHK_1 | DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
+ DMAC->DMAC_CH_NUM[DMA_CHANNEL_LEDS].DMAC_CTRLB = DMAC_CTRLB_FC_MEM2PER_DMA_FC | DMAC_CTRLB_SRC_INCR_INCREMENTING | DMAC_CTRLB_DST_INCR_FIXED;
+ DMAC->DMAC_CH_NUM[DMA_CHANNEL_LEDS].DMAC_CFG = DMAC_CFG_DST_PER(1) | DMAC_CFG_SRC_PER(1) | DMAC_CFG_DST_H2SEL_HW | DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG;
+ DMAC->DMAC_CHER = (1 << DMA_CHANNEL_LEDS);
+
+ //wait for transfer to start
+ while(SPI0->SPI_SR & SPI_SR_TXEMPTY);
+ SPI0->SPI_IER = SPI_IER_TXEMPTY;
+}
+
+void ledDbgState(char on){
+
+ gpioSetVal(DBGLED, on);
+}
+
+
diff --git a/library/ADK2/LEDs.h b/library/ADK2/LEDs.h
new file mode 100644
index 0000000..0e45f06
--- /dev/null
+++ b/library/ADK2/LEDs.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _LEDS_H_
+#define _LEDS_H_
+
+#include <stdint.h>
+
+
+
+
+#define NUM_LEDS 64
+
+#define NUM_DIGITS 6
+#define NUM_ICONS 8
+
+extern const uint8_t seg_table[]; //7-segment difits: 0-9a-z_-.()
+extern const uint8_t digit_table[NUM_DIGITS]; //"offset" values to each of the 6 digits
+extern const uint8_t icon_table[NUM_ICONS]; //"offset" values to each of the 8 icons
+
+void ledsInit(void);
+
+//front LED display
+
+ //draw to the backbuffer
+ void ledWrite(uint8_t led_id, uint8_t r, uint8_t g, uint8_t b);
+ void ledDrawIcon(uint8_t icon, uint8_t r, uint8_t g, uint8_t b);
+ void ledDrawLetter(char letter, uint8_t val, uint8_t r, uint8_t g, uint8_t b);
+
+ //flush the backbuffer to the display
+ void ledUpdate(void);
+
+//onboard debug LED
+
+ void ledDbgState(char on);
+
+#endif
+#endif
+
diff --git a/library/ADK2/RTC.c b/library/ADK2/RTC.c
new file mode 100644
index 0000000..c7d8433
--- /dev/null
+++ b/library/ADK2/RTC.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "coop.h"
+#include "RTC.h"
+
+
+
+static volatile uint16_t gYear = 2012;
+static volatile uint8_t gMonth = 2, gDay = 27, gHour = 19, gMinute = 8, gSecond = 8;
+
+
+void rtcInit(void){
+
+ SUPC->SUPC_CR = SUPC_CR_KEY(0xA5) | SUPC_CR_XTALSEL_CRYSTAL_SEL; //enable oscillator
+ RTC->RTC_IDR = 0x1f;
+ RTC->RTC_IER = RTC_IER_SECEN; //enable interrupt
+ NVIC_EnableIRQ(RTC_IRQn);
+}
+
+void RTC_Handler(void){
+
+ static const uint8_t days_per_month[2][12] = {
+ {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31},
+ {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31},
+ };
+
+ RTC->RTC_SCCR = RTC_SCCR_SECCLR;
+ if(++gSecond < 60) return;
+ gSecond = 0;
+ if(++gMinute < 60) return;
+ gMinute = 0;
+ if(++gHour < 24) return;
+ gHour = 0;
+ if(++gDay < days_per_month[!(gYear & 3)][gMonth]) return;
+ gDay = 0;
+ if(gMonth++ < 12) return;
+ gMonth = 0;
+ gYear++;
+}
+
+void rtcGet(uint16_t* yearP, uint8_t* monthP, uint8_t* dayP, uint8_t* hourP, uint8_t* minuteP, uint8_t* secondP){
+
+ uint16_t mYear;
+ uint8_t mMonth, mDay, mHour, mMinute, mSecond;
+
+ //read
+ do{
+
+ mSecond = gSecond;
+ mMinute = gMinute;
+ mHour = gHour;
+ mDay = gDay;
+ mMonth = gMonth;
+ mYear = gYear;
+
+ }while(mSecond != gSecond);
+
+ if(yearP) *yearP = mYear;
+ if(monthP) *monthP = mMonth + 1;
+ if(dayP) *dayP = mDay + 1;
+ if(hourP) *hourP = mHour;
+ if(minuteP) *minuteP = mMinute;
+ if(secondP) *secondP = mSecond;
+}
+
+void rtcSet(uint16_t year, uint8_t month, uint8_t day, uint8_t hour, uint8_t minute, uint8_t second){
+
+ //disable hardware update
+ RTC->RTC_IDR = RTC_IDR_SECDIS;
+
+ //write
+ gYear = year;
+ gMonth = month - 1;
+ gDay = day - 1;
+ gHour = hour;
+ gMinute = minute;
+ gSecond = second;
+
+ //re-enable hardware RTC counting
+ RTC->RTC_IER = RTC_IER_SECEN;
+}
+
+
+
diff --git a/library/ADK2/RTC.h b/library/ADK2/RTC.h
new file mode 100644
index 0000000..6635fac
--- /dev/null
+++ b/library/ADK2/RTC.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _RTC_H_
+#define _RTH_H_
+
+void rtcInit(void);
+void rtcGet(uint16_t* yearP, uint8_t* monthP, uint8_t* dayP, uint8_t* hourP, uint8_t* minuteP, uint8_t* secondP);
+void rtcSet(uint16_t year, uint8_t month, uint8_t day, uint8_t hour, uint8_t minute, uint8_t second);
+
+
+#endif
+#endif
+
diff --git a/library/ADK2/SAM3XA.h b/library/ADK2/SAM3XA.h
new file mode 100644
index 0000000..2de4745
--- /dev/null
+++ b/library/ADK2/SAM3XA.h
@@ -0,0 +1,12328 @@
+#ifdef ADK_INTERNAL
+
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2011, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+/* */
+/* File Name : SAM3XA.h */
+/* Object : SAM3XA definitions */
+/* Generated by : AT91 SW Application Group */
+/* Generated on : 2011-03-29 */
+
+#ifndef SAM3XA_H
+#define SAM3XA_H
+
+/** \addtogroup SAM3XA_definitions SAM3XA definitions
+ This file defines all structures and symbols for SAM3XA:
+ - registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __ASSEMBLY__
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type*) (value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/* CMSIS DEFINITIONS FOR SAM3XA */
+/* ************************************************************************** */
+/** \addtogroup SAM3XA_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
+/****** SAM3XA specific Interrupt Numbers *********************************/
+
+ SUPC_IRQn = 0, /**< 0 SAM3XA Supply Controller (SUPC) */
+ RSTC_IRQn = 1, /**< 1 SAM3XA Reset Controller (RSTC) */
+ RTC_IRQn = 2, /**< 2 SAM3XA Real Time Clock (RTC) */
+ RTT_IRQn = 3, /**< 3 SAM3XA Real Time Timer (RTT) */
+ WDT_IRQn = 4, /**< 4 SAM3XA Watchdog Timer (WDT) */
+ PMC_IRQn = 5, /**< 5 SAM3XA Power Management Controller (PMC) */
+ EFC0_IRQn = 6, /**< 6 SAM3XA Enhanced Flash Controller 0 (EFC0) */
+ EFC1_IRQn = 7, /**< 7 SAM3XA Enhanced Flash Controller 1 (EFC1) */
+ UART_IRQn = 8, /**< 8 SAM3XA Universal Asynchronous Receiver Transceiver (UART) */
+ SMC_IRQn = 9, /**< 9 SAM3XA Static Memory Controller (SMC) */
+ SDRAMC_IRQn = 10, /**< 10 SAM3XA Synchronous Dynamic RAM Controller (SDRAMC) */
+ PIOA_IRQn = 11, /**< 11 SAM3XA Parallel I/O Controller A, (PIOA) */
+ PIOB_IRQn = 12, /**< 12 SAM3XA Parallel I/O Controller B (PIOB) */
+ PIOC_IRQn = 13, /**< 13 SAM3XA Parallel I/O Controller C (PIOC) */
+ PIOD_IRQn = 14, /**< 14 SAM3XA Parallel I/O Controller D (PIOD) */
+ PIOE_IRQn = 15, /**< 15 SAM3XA Parallel I/O Controller E (PIOE) */
+ PIOF_IRQn = 16, /**< 16 SAM3XA Parallel I/O Controller F (PIOF) */
+ USART0_IRQn = 17, /**< 17 SAM3XA USART 0 (USART0) */
+ USART1_IRQn = 18, /**< 18 SAM3XA USART 1 (USART1) */
+ USART2_IRQn = 19, /**< 19 SAM3XA USART 2 (USART2) */
+ USART3_IRQn = 20, /**< 20 SAM3XA USART 3 (USART3) */
+ HSMCI_IRQn = 21, /**< 21 SAM3XA Multimedia Card Interface (HSMCI) */
+ TWI0_IRQn = 22, /**< 22 SAM3XA Two-Wire Interface 0 (TWI0) */
+ TWI1_IRQn = 23, /**< 23 SAM3XA Two-Wire Interface 1 (TWI1) */
+ SPI0_IRQn = 24, /**< 24 SAM3XA Serial Peripheral Interface (SPI0) */
+ SPI1_IRQn = 25, /**< 25 SAM3XA Serial Peripheral Interface (SPI1) */
+ SSC_IRQn = 26, /**< 26 SAM3XA Synchronous Serial Controller (SSC) */
+ TC0_IRQn = 27, /**< 27 SAM3XA Timer Counter 0 (TC0) */
+ TC1_IRQn = 28, /**< 28 SAM3XA Timer Counter 1 (TC1) */
+ TC2_IRQn = 29, /**< 29 SAM3XA Timer Counter 2 (TC2) */
+ TC3_IRQn = 30, /**< 30 SAM3XA Timer Counter 3 (TC3) */
+ TC4_IRQn = 31, /**< 31 SAM3XA Timer Counter 4 (TC4) */
+ TC5_IRQn = 32, /**< 32 SAM3XA Timer Counter 5 (TC5) */
+ TC6_IRQn = 33, /**< 33 SAM3XA Timer Counter 6 (TC6) */
+ TC7_IRQn = 34, /**< 34 SAM3XA Timer Counter 7 (TC7) */
+ TC8_IRQn = 35, /**< 35 SAM3XA Timer Counter 8 (TC8) */
+ PWM_IRQn = 36, /**< 36 SAM3XA Pulse Width Modulation Controller (PWM) */
+ ADC_IRQn = 37, /**< 37 SAM3XA ADC Controller (ADC) */
+ DACC_IRQn = 38, /**< 38 SAM3XA DAC Controller (DACC) */
+ DMAC_IRQn = 39, /**< 39 SAM3XA DMA Controller (DMAC) */
+ UOTGHS_IRQn = 40, /**< 40 SAM3XA USB OTG High Speed (UOTGHS) */
+ TRNG_IRQn = 41, /**< 41 SAM3XA True Random Number Generator (TRNG) */
+ EMAC_IRQn = 42, /**< 42 SAM3XA Ethernet MAC (EMAC) */
+ CAN0_IRQn = 43, /**< 43 SAM3XA CAN Controller 0 (CAN0) */
+ CAN1_IRQn = 44 /**< 44 SAM3XA CAN Controller 1 (CAN1) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __MPU_PRESENT 1 /**< SAM3XA does provide a MPU */
+#define __NVIC_PRIO_BITS 4 /**< SAM3XA uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V1.30
+ * @date 30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CM3_CORE_H__
+#define __CM3_CORE_H__
+
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
+ *
+ * List of Lint messages which will be suppressed and not shown:
+ * - Error 10: \n
+ * register uint32_t __regBasePri __asm("basepri"); \n
+ * Error 10: Expecting ';'
+ * .
+ * - Error 530: \n
+ * return(__regBasePri); \n
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized
+ * .
+ * - Error 550: \n
+ * __regBasePri = (basePri & 0x1ff); \n
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed
+ * .
+ * - Error 754: \n
+ * uint32_t RESERVED0[24]; \n
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
+ * .
+ * - Error 750: \n
+ * #define __CM3_CORE_H__ \n
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
+ * .
+ * - Error 528: \n
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
+ * .
+ * - Error 751: \n
+ * } InterruptType_Type; \n
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
+ * .
+ * Note: To re-enable a Message, insert a space before 'lint' *
+ *
+ */
+
+/*lint -save */
+/*lint -e10 */
+/*lint -e530 */
+/*lint -e550 */
+/*lint -e754 */
+/*lint -e750 */
+/*lint -e528 */
+/*lint -e751 */
+
+
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
+ This file defines all structures and symbols for CMSIS core:
+ - CMSIS version number
+ - Cortex-M core registers and bitfields
+ - Cortex-M core peripheral base address
+ @{
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+#include <stdint.h> /* Include standard types */
+
+#if defined (__ICCARM__)
+ #include <intrinsics.h> /* IAR Intrinsics */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
+#endif
+
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#ifdef __cplusplus
+ #define __I volatile /*!< defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< defines 'read only' permissions */
+#endif
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ ******************************************************************************/
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
+ @{
+*/
+
+
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
+ memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
+ @{
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
+} NVIC_Type;
+/*@}*/ /* end of group CMSIS_CM3_NVIC */
+
+
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
+ memory mapped structure for System Control Block (SCB)
+ @{
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (0x1ul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+/*@}*/ /* end of group CMSIS_CM3_SCB */
+
+
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
+ memory mapped structure for SysTick
+ @{
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+/*@}*/ /* end of group CMSIS_CM3_SysTick */
+
+
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
+ memory mapped structure for Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
+ __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
+ __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+/*@}*/ /* end of group CMSIS_CM3_ITM */
+
+
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
+ memory mapped structure for Interrupt Type
+ @{
+ */
+typedef struct
+{
+ uint32_t RESERVED0;
+ __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
+#else
+ uint32_t RESERVED1;
+#endif
+} InterruptType_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
+#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
+
+#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+
+#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
+ memory mapped structure for Memory Protection Unit (MPU)
+ @{
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
+#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
+#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
+#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
+#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
+#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
+#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@}*/ /* end of group CMSIS_CM3_MPU */
+#endif
+
+
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
+ memory mapped structure for Core Debug Register
+ @{
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
+
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
+
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
+#endif
+
+/*@}*/ /* end of group CMSIS_CM3_core_register */
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#define __enable_fault_irq __enable_fiq
+#define __disable_fault_irq __disable_fiq
+
+#define __NOP __nop
+#define __WFI __wfi
+#define __WFE __wfe
+#define __SEV __sev
+#define __ISB() __isb(0)
+#define __DSB() __dsb(0)
+#define __DMB() __dmb(0)
+#define __REV __rev
+#define __RBIT __rbit
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
+#define __STREXB(value, ptr) __strex(value, ptr)
+#define __STREXH(value, ptr) __strex(value, ptr)
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+extern void __CLREX(void);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param basePri BasePriority
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param priMask PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param control Control value
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+#else /* (__ARMCC_VERSION >= 400000) */
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+#define __CLREX __clrex
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+static __INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param basePri BasePriority
+ *
+ * Set the base priority register
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param priMask PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & 1);
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param control Control value
+ *
+ * Set the control register
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+#endif /* __ARMCC_VERSION */
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
+
+static __INLINE void __enable_fault_irq( void ) { __ASM ("cpsie f"); }
+static __INLINE void __disable_fault_irq( void ) { __ASM ("cpsid f"); }
+
+#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
+static __INLINE void __WFI( void ) { __ASM ("wfi"); }
+static __INLINE void __WFE( void ) { __ASM ("wfe"); }
+static __INLINE void __SEV( void ) { __ASM ("sev"); }
+static __INLINE void __CLREX( void ) { __ASM ("clrex"); }
+
+/* intrinsic void __ISB(void) */
+/* intrinsic void __DSB(void) */
+/* intrinsic void __DMB(void) */
+/* intrinsic void __set_PRIMASK(); */
+/* intrinsic void __get_PRIMASK(); */
+/* intrinsic void __set_FAULTMASK(); */
+/* intrinsic void __get_FAULTMASK(); */
+/* intrinsic uint32_t __REV(uint32_t value); */
+/* intrinsic uint32_t __REVSH(uint32_t value); */
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
+/* intrinsic unsigned long __LDREX(unsigned long *); */
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive (8 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive (16 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive (32 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive (8 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive (16 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive (32 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); }
+static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); }
+
+static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); }
+static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); }
+
+static __INLINE void __NOP(void) { __ASM volatile ("nop"); }
+static __INLINE void __WFI(void) { __ASM volatile ("wfi"); }
+static __INLINE void __WFE(void) { __ASM volatile ("wfe"); }
+static __INLINE void __SEV(void) { __ASM volatile ("sev"); }
+static __INLINE void __ISB(void) { __ASM volatile ("isb"); }
+static __INLINE void __DSB(void) { __ASM volatile ("dsb"); }
+static __INLINE void __DMB(void) { __ASM volatile ("dmb"); }
+static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); }
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param basePri BasePriority
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param priMask PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+*
+* @return Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param control Control value
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+/**
+ * @brief Reverse byte order in integer value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in integer value
+ */
+extern uint32_t __REV(uint32_t value);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive (8 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive (16 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive (32 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive (8 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive (16 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive (32 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
+ Core Function Interface containing:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Reset Functions
+*/
+/*@{*/
+
+/* ########################## NVIC functions #################################### */
+
+/**
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller
+ *
+ * @param PriorityGroup is priority grouping field
+ *
+ * Set the priority grouping field using the required unlock sequence.
+ * The parameter priority_grouping is assigned to the field
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+/**
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller
+ *
+ * @return priority grouping field
+ *
+ * Get the priority grouping from NVIC Interrupt Controller.
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+/**
+ * @brief Enable Interrupt in NVIC Interrupt Controller
+ *
+ * @param IRQn The positive number of the external interrupt to enable
+ *
+ * Enable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+/**
+ * @brief Disable the interrupt line for external interrupt specified
+ *
+ * @param IRQn The positive number of the external interrupt to disable
+ *
+ * Disable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+/**
+ * @brief Read the interrupt pending bit for a device specific interrupt source
+ *
+ * @param IRQn The number of the device specifc interrupt
+ * @return 1 = interrupt pending, 0 = interrupt not pending
+ *
+ * Read the pending register in NVIC and return 1 if its status is pending,
+ * otherwise it returns 0
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+/**
+ * @brief Set the pending bit for an external interrupt
+ *
+ * @param IRQn The number of the interrupt for set pending
+ *
+ * Set the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+/**
+ * @brief Clear the pending bit for an external interrupt
+ *
+ * @param IRQn The number of the interrupt for clear pending
+ *
+ * Clear the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+/**
+ * @brief Read the active bit for an external interrupt
+ *
+ * @param IRQn The number of the interrupt for read active bit
+ * @return 1 = interrupt active, 0 = interrupt not active
+ *
+ * Read the active register in NVIC and returns 1 if its status is active,
+ * otherwise it returns 0.
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+/**
+ * @brief Set the priority for an interrupt
+ *
+ * @param IRQn The number of the interrupt for set priority
+ * @param priority The priority to set
+ *
+ * Set the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+/**
+ * @brief Read the priority for an interrupt
+ *
+ * @param IRQn The number of the interrupt for get priority
+ * @return The priority for the interrupt
+ *
+ * Read the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * The returned priority value is automatically aligned to the implemented
+ * priority bits of the microcontroller.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/**
+ * @brief Encode the priority for an interrupt
+ *
+ * @param PriorityGroup The used priority group
+ * @param PreemptPriority The preemptive priority value (starting from 0)
+ * @param SubPriority The sub priority value (starting from 0)
+ * @return The encoded priority for the interrupt
+ *
+ * Encode the priority for an interrupt with the given priority group,
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The returned priority value can be used for NVIC_SetPriority(...) function
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/**
+ * @brief Decode the priority of an interrupt
+ *
+ * @param Priority The priority for the interrupt
+ * @param PriorityGroup The used priority group
+ * @param pPreemptPriority The preemptive priority value (starting from 0)
+ * @param pSubPriority The sub priority value (starting from 0)
+ *
+ * Decode an interrupt priority value with the given priority group to
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The priority value can be retrieved with NVIC_GetPriority(...) function
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+
+/* ################################## SysTick function ############################################ */
+
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
+
+/**
+ * @brief Initialize and start the SysTick counter and its interrupt.
+ *
+ * @param ticks number of ticks between two interrupts
+ * @return 1 = failed, 0 = successful
+ *
+ * Initialise the system tick timer and its interrupt and start the
+ * system tick timer / counter in free running mode to generate
+ * periodical interrupts.
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+
+
+
+/* ################################## Reset function ############################################ */
+
+/**
+ * @brief Initiate a system reset request.
+ *
+ * Initiate a system reset request to reset the MCU
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
+ Core Debug Interface containing:
+ - Core Debug Receive / Transmit Functions
+ - Core Debug Defines
+ - Core Debug Variables
+*/
+/*@{*/
+
+extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/**
+ * @brief Outputs a character via the ITM channel 0
+ *
+ * @param ch character to output
+ * @return character to output
+ *
+ * The function outputs a character via the ITM channel 0.
+ * The function returns when no debugger is connected that has booked the output.
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/**
+ * @brief Inputs a character via variable ITM_RxBuffer
+ *
+ * @return received character, -1 = no character received
+ *
+ * The function inputs a character via variable ITM_RxBuffer.
+ * The function returns when no debugger is connected that has booked the output.
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ */
+static __INLINE int ITM_ReceiveChar (void) {
+ int ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ * @brief Check if a character via variable ITM_RxBuffer is available
+ *
+ * @return 1 = character available, 0 = no character available
+ *
+ * The function checks variable ITM_RxBuffer whether a character is available or not.
+ * The function returns '1' if a character is available and '0' if no character is available.
+ */
+static __INLINE int ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */
+
+#endif /* __CM3_CORE_H__ */
+
+/*lint -restore */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3XA */
+/* ************************************************************************** */
+/** \addtogroup SAM3XA_api Peripheral Software API */
+/*@{*/
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_ADC Analog-to-digital Converter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Adc hardware registers */
+typedef struct {
+ WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */
+ RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */
+ RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
+ RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
+ WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+ WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+ RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */
+ RoReg Reserved1[1];
+ RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+ WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+ WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+ RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+ RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
+ RoReg Reserved2[2];
+ RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
+ RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */
+ RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */
+ RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */
+ RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
+ RoReg ADC_CDR[16]; /**< \brief (Adc Offset: 0x50) Channel Data Register */
+ RoReg Reserved3[1];
+ RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */
+ RoReg Reserved4[19];
+ RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
+ RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
+ RoReg Reserved5[5];
+ RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+ RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+ RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */
+ RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */
+ RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+ RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+ RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */
+ RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */
+ WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+ RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* __ASSEMBLY__ */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External : ADCTRG */
+#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 0 */
+#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 1 */
+#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 2 */
+#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
+#define ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */
+#define ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
+#define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
+#define ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
+#define ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */
+#define ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */
+#define ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */
+#define ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */
+#define ADC_MR_SETTLING_Pos 20
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */
+#define ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */
+#define ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */
+#define ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */
+#define ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */
+#define ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */
+#define ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */
+#define ADC_MR_TRACKTIM_Pos 24
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
+#define ADC_MR_TRANSFER_Pos 28
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
+#define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */
+#define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
+#define ADC_SEQR1_USCH1_Pos 0
+#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
+#define ADC_SEQR1_USCH2_Pos 4
+#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
+#define ADC_SEQR1_USCH3_Pos 8
+#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
+#define ADC_SEQR1_USCH4_Pos 12
+#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
+#define ADC_SEQR1_USCH5_Pos 16
+#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
+#define ADC_SEQR1_USCH6_Pos 20
+#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
+#define ADC_SEQR1_USCH7_Pos 24
+#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
+#define ADC_SEQR1_USCH8_Pos 28
+#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
+#define ADC_SEQR2_USCH9_Pos 0
+#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
+#define ADC_SEQR2_USCH10_Pos 4
+#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
+#define ADC_SEQR2_USCH11_Pos 8
+#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
+#define ADC_SEQR2_USCH12_Pos 12
+#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
+#define ADC_SEQR2_USCH13_Pos 16
+#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
+#define ADC_SEQR2_USCH14_Pos 20
+#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
+#define ADC_SEQR2_USCH15_Pos 24
+#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
+#define ADC_SEQR2_USCH16_Pos 28
+#define ADC_SEQR2_USCH16_Msk (0xfu << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+#define ADC_LCDR_CHNB_Pos 12
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
+#define ADC_EMR_CMPMODE_Pos 0
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
+#define ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
+#define ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
+#define ADC_EMR_CMPSEL_Pos 4
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
+#define ADC_EMR_CMPFILTER_Pos 12
+#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */
+#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos)))
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
+#define ADC_CWR_LOWTHRES_Pos 0
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
+#define ADC_CWR_HIGHTHRES_Pos 16
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
+#define ADC_CGR_GAIN0_Pos 0
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))
+#define ADC_CGR_GAIN1_Pos 2
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))
+#define ADC_CGR_GAIN2_Pos 4
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))
+#define ADC_CGR_GAIN3_Pos 6
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))
+#define ADC_CGR_GAIN4_Pos 8
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))
+#define ADC_CGR_GAIN5_Pos 10
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))
+#define ADC_CGR_GAIN6_Pos 12
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))
+#define ADC_CGR_GAIN7_Pos 14
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))
+#define ADC_CGR_GAIN8_Pos 16
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))
+#define ADC_CGR_GAIN9_Pos 18
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))
+#define ADC_CGR_GAIN10_Pos 20
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))
+#define ADC_CGR_GAIN11_Pos 22
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))
+#define ADC_CGR_GAIN12_Pos 24
+#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */
+#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))
+#define ADC_CGR_GAIN13_Pos 26
+#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */
+#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))
+#define ADC_CGR_GAIN14_Pos 28
+#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */
+
+#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))
+#define ADC_CGR_GAIN15_Pos 30
+#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */
+#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */
+#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */
+#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */
+#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */
+#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */
+#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */
+#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */
+#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */
+#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */
+/* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[16]) Converted Data */
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
+#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */
+#define ADC_ACR_IBCTL_Pos 8
+#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */
+#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
+#define ADC_WPMR_WPKEY_Pos 8
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
+#define ADC_WPSR_WPVSRC_Pos 8
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */
+#define ADC_TPR_TXPTR_Pos 0
+#define ADC_TPR_TXPTR_Msk (0xffffffffu << ADC_TPR_TXPTR_Pos) /**< \brief (ADC_TPR) Transmit Counter Register */
+#define ADC_TPR_TXPTR(value) ((ADC_TPR_TXPTR_Msk & ((value) << ADC_TPR_TXPTR_Pos)))
+/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */
+#define ADC_TCR_TXCTR_Pos 0
+#define ADC_TCR_TXCTR_Msk (0xffffu << ADC_TCR_TXCTR_Pos) /**< \brief (ADC_TCR) Transmit Counter Register */
+#define ADC_TCR_TXCTR(value) ((ADC_TCR_TXCTR_Msk & ((value) << ADC_TCR_TXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define ADC_TNPR_TXNPTR_Pos 0
+#define ADC_TNPR_TXNPTR_Msk (0xffffffffu << ADC_TNPR_TXNPTR_Pos) /**< \brief (ADC_TNPR) Transmit Next Pointer */
+#define ADC_TNPR_TXNPTR(value) ((ADC_TNPR_TXNPTR_Msk & ((value) << ADC_TNPR_TXNPTR_Pos)))
+/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define ADC_TNCR_TXNCTR_Pos 0
+#define ADC_TNCR_TXNCTR_Msk (0xffffu << ADC_TNCR_TXNCTR_Pos) /**< \brief (ADC_TNCR) Transmit Counter Next */
+#define ADC_TNCR_TXNCTR(value) ((ADC_TNCR_TXNCTR_Msk & ((value) << ADC_TNCR_TXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Controller Area Network */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_CAN Controller Area Network */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+#define CAN_MB_NUMBER 8
+/** \brief CanMb hardware registers */
+typedef struct {
+ RwReg CAN_MMR; /**< \brief (CanMb Offset: 0x0) Mailbox Mode Register */
+ RwReg CAN_MAM; /**< \brief (CanMb Offset: 0x4) Mailbox Acceptance Mask Register */
+ RwReg CAN_MID; /**< \brief (CanMb Offset: 0x8) Mailbox ID Register */
+ RwReg CAN_MFID; /**< \brief (CanMb Offset: 0xC) Mailbox Family ID Register */
+ RwReg CAN_MSR; /**< \brief (CanMb Offset: 0x10) Mailbox Status Register */
+ RwReg CAN_MDL; /**< \brief (CanMb Offset: 0x14) Mailbox Data Low Register */
+ RwReg CAN_MDH; /**< \brief (CanMb Offset: 0x18) Mailbox Data High Register */
+ RwReg CAN_MCR; /**< \brief (CanMb Offset: 0x1C) Mailbox Control Register */
+} CanMb;
+/** \brief Can hardware registers */
+typedef struct {
+ RwReg CAN_MR; /**< \brief (Can Offset: 0x0000) Mode Register */
+ WoReg CAN_IER; /**< \brief (Can Offset: 0x0004) Interrupt Enable Register */
+ WoReg CAN_IDR; /**< \brief (Can Offset: 0x0008) Interrupt Disable Register */
+ RoReg CAN_IMR; /**< \brief (Can Offset: 0x000C) Interrupt Mask Register */
+ RoReg CAN_SR; /**< \brief (Can Offset: 0x0010) Status Register */
+ RwReg CAN_BR; /**< \brief (Can Offset: 0x0014) Baudrate Register */
+ RoReg CAN_TIM; /**< \brief (Can Offset: 0x0018) Timer Register */
+ RoReg CAN_TIMESTP; /**< \brief (Can Offset: 0x001C) Timestamp Register */
+ RoReg CAN_ECR; /**< \brief (Can Offset: 0x0020) Error Counter Register */
+ WoReg CAN_TCR; /**< \brief (Can Offset: 0x0024) Transfer Command Register */
+ WoReg CAN_ACR; /**< \brief (Can Offset: 0x0028) Abort Command Register */
+ RoReg Reserved1[117];
+ CanMb CAN_MB[CAN_MB_NUMBER]; /**< \brief (Can Offset: 0x200) MB = 0 .. 7 */
+} Can;
+#endif /* __ASSEMBLY__ */
+/* -------- CAN_MR : (CAN Offset: 0x0000) Mode Register -------- */
+#define CAN_MR_CANEN (0x1u << 0) /**< \brief (CAN_MR) CAN Controller Enable */
+#define CAN_MR_LPM (0x1u << 1) /**< \brief (CAN_MR) Disable/Enable Low Power Mode */
+#define CAN_MR_ABM (0x1u << 2) /**< \brief (CAN_MR) Disable/Enable Autobaud/Listen mode */
+#define CAN_MR_OVL (0x1u << 3) /**< \brief (CAN_MR) Disable/Enable Overload Frame */
+#define CAN_MR_TEOF (0x1u << 4) /**< \brief (CAN_MR) Timestamp messages at each end of Frame */
+#define CAN_MR_TTM (0x1u << 5) /**< \brief (CAN_MR) Disable/Enable Time Triggered Mode */
+#define CAN_MR_TIMFRZ (0x1u << 6) /**< \brief (CAN_MR) Enable Timer Freeze */
+#define CAN_MR_DRPT (0x1u << 7) /**< \brief (CAN_MR) Disable Repeat */
+#define CAN_MR_RXSYNC_Pos 24
+#define CAN_MR_RXSYNC_Msk (0x7u << CAN_MR_RXSYNC_Pos) /**< \brief (CAN_MR) Reception Synchronization Stage (not readable) */
+#define CAN_MR_RXSYNC_DOUBLE_PP (0x0u << 24) /**< \brief (CAN_MR) Rx Signal with Double Synchro Stages (2 Positive Edges) */
+#define CAN_MR_RXSYNC_DOUBLE_PN (0x1u << 24) /**< \brief (CAN_MR) Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge) */
+#define CAN_MR_RXSYNC_SINGLE_P (0x2u << 24) /**< \brief (CAN_MR) Rx Signal with Single Synchro Stage (Positive Edge) */
+#define CAN_MR_RXSYNC_NONE (0x3u << 24) /**< \brief (CAN_MR) Rx Signal with No Synchro Stage */
+/* -------- CAN_IER : (CAN Offset: 0x0004) Interrupt Enable Register -------- */
+#define CAN_IER_MB0 (0x1u << 0) /**< \brief (CAN_IER) Mailbox 0 Interrupt Enable */
+#define CAN_IER_MB1 (0x1u << 1) /**< \brief (CAN_IER) Mailbox 1 Interrupt Enable */
+#define CAN_IER_MB2 (0x1u << 2) /**< \brief (CAN_IER) Mailbox 2 Interrupt Enable */
+#define CAN_IER_MB3 (0x1u << 3) /**< \brief (CAN_IER) Mailbox 3 Interrupt Enable */
+#define CAN_IER_MB4 (0x1u << 4) /**< \brief (CAN_IER) Mailbox 4 Interrupt Enable */
+#define CAN_IER_MB5 (0x1u << 5) /**< \brief (CAN_IER) Mailbox 5 Interrupt Enable */
+#define CAN_IER_MB6 (0x1u << 6) /**< \brief (CAN_IER) Mailbox 6 Interrupt Enable */
+#define CAN_IER_MB7 (0x1u << 7) /**< \brief (CAN_IER) Mailbox 7 Interrupt Enable */
+#define CAN_IER_ERRA (0x1u << 16) /**< \brief (CAN_IER) Error Active Mode Interrupt Enable */
+#define CAN_IER_WARN (0x1u << 17) /**< \brief (CAN_IER) Warning Limit Interrupt Enable */
+#define CAN_IER_ERRP (0x1u << 18) /**< \brief (CAN_IER) Error Passive Mode Interrupt Enable */
+#define CAN_IER_BOFF (0x1u << 19) /**< \brief (CAN_IER) Bus Off Mode Interrupt Enable */
+#define CAN_IER_SLEEP (0x1u << 20) /**< \brief (CAN_IER) Sleep Interrupt Enable */
+#define CAN_IER_WAKEUP (0x1u << 21) /**< \brief (CAN_IER) Wakeup Interrupt Enable */
+#define CAN_IER_TOVF (0x1u << 22) /**< \brief (CAN_IER) Timer Overflow Interrupt Enable */
+#define CAN_IER_TSTP (0x1u << 23) /**< \brief (CAN_IER) TimeStamp Interrupt Enable */
+#define CAN_IER_CERR (0x1u << 24) /**< \brief (CAN_IER) CRC Error Interrupt Enable */
+#define CAN_IER_SERR (0x1u << 25) /**< \brief (CAN_IER) Stuffing Error Interrupt Enable */
+#define CAN_IER_AERR (0x1u << 26) /**< \brief (CAN_IER) Acknowledgment Error Interrupt Enable */
+#define CAN_IER_FERR (0x1u << 27) /**< \brief (CAN_IER) Form Error Interrupt Enable */
+#define CAN_IER_BERR (0x1u << 28) /**< \brief (CAN_IER) Bit Error Interrupt Enable */
+/* -------- CAN_IDR : (CAN Offset: 0x0008) Interrupt Disable Register -------- */
+#define CAN_IDR_MB0 (0x1u << 0) /**< \brief (CAN_IDR) Mailbox 0 Interrupt Disable */
+#define CAN_IDR_MB1 (0x1u << 1) /**< \brief (CAN_IDR) Mailbox 1 Interrupt Disable */
+#define CAN_IDR_MB2 (0x1u << 2) /**< \brief (CAN_IDR) Mailbox 2 Interrupt Disable */
+#define CAN_IDR_MB3 (0x1u << 3) /**< \brief (CAN_IDR) Mailbox 3 Interrupt Disable */
+#define CAN_IDR_MB4 (0x1u << 4) /**< \brief (CAN_IDR) Mailbox 4 Interrupt Disable */
+#define CAN_IDR_MB5 (0x1u << 5) /**< \brief (CAN_IDR) Mailbox 5 Interrupt Disable */
+#define CAN_IDR_MB6 (0x1u << 6) /**< \brief (CAN_IDR) Mailbox 6 Interrupt Disable */
+#define CAN_IDR_MB7 (0x1u << 7) /**< \brief (CAN_IDR) Mailbox 7 Interrupt Disable */
+#define CAN_IDR_ERRA (0x1u << 16) /**< \brief (CAN_IDR) Error Active Mode Interrupt Disable */
+#define CAN_IDR_WARN (0x1u << 17) /**< \brief (CAN_IDR) Warning Limit Interrupt Disable */
+#define CAN_IDR_ERRP (0x1u << 18) /**< \brief (CAN_IDR) Error Passive Mode Interrupt Disable */
+#define CAN_IDR_BOFF (0x1u << 19) /**< \brief (CAN_IDR) Bus Off Mode Interrupt Disable */
+#define CAN_IDR_SLEEP (0x1u << 20) /**< \brief (CAN_IDR) Sleep Interrupt Disable */
+#define CAN_IDR_WAKEUP (0x1u << 21) /**< \brief (CAN_IDR) Wakeup Interrupt Disable */
+#define CAN_IDR_TOVF (0x1u << 22) /**< \brief (CAN_IDR) Timer Overflow Interrupt */
+#define CAN_IDR_TSTP (0x1u << 23) /**< \brief (CAN_IDR) TimeStamp Interrupt Disable */
+#define CAN_IDR_CERR (0x1u << 24) /**< \brief (CAN_IDR) CRC Error Interrupt Disable */
+#define CAN_IDR_SERR (0x1u << 25) /**< \brief (CAN_IDR) Stuffing Error Interrupt Disable */
+#define CAN_IDR_AERR (0x1u << 26) /**< \brief (CAN_IDR) Acknowledgment Error Interrupt Disable */
+#define CAN_IDR_FERR (0x1u << 27) /**< \brief (CAN_IDR) Form Error Interrupt Disable */
+#define CAN_IDR_BERR (0x1u << 28) /**< \brief (CAN_IDR) Bit Error Interrupt Disable */
+/* -------- CAN_IMR : (CAN Offset: 0x000C) Interrupt Mask Register -------- */
+#define CAN_IMR_MB0 (0x1u << 0) /**< \brief (CAN_IMR) Mailbox 0 Interrupt Mask */
+#define CAN_IMR_MB1 (0x1u << 1) /**< \brief (CAN_IMR) Mailbox 1 Interrupt Mask */
+#define CAN_IMR_MB2 (0x1u << 2) /**< \brief (CAN_IMR) Mailbox 2 Interrupt Mask */
+#define CAN_IMR_MB3 (0x1u << 3) /**< \brief (CAN_IMR) Mailbox 3 Interrupt Mask */
+#define CAN_IMR_MB4 (0x1u << 4) /**< \brief (CAN_IMR) Mailbox 4 Interrupt Mask */
+#define CAN_IMR_MB5 (0x1u << 5) /**< \brief (CAN_IMR) Mailbox 5 Interrupt Mask */
+#define CAN_IMR_MB6 (0x1u << 6) /**< \brief (CAN_IMR) Mailbox 6 Interrupt Mask */
+#define CAN_IMR_MB7 (0x1u << 7) /**< \brief (CAN_IMR) Mailbox 7 Interrupt Mask */
+#define CAN_IMR_ERRA (0x1u << 16) /**< \brief (CAN_IMR) Error Active Mode Interrupt Mask */
+#define CAN_IMR_WARN (0x1u << 17) /**< \brief (CAN_IMR) Warning Limit Interrupt Mask */
+#define CAN_IMR_ERRP (0x1u << 18) /**< \brief (CAN_IMR) Error Passive Mode Interrupt Mask */
+#define CAN_IMR_BOFF (0x1u << 19) /**< \brief (CAN_IMR) Bus Off Mode Interrupt Mask */
+#define CAN_IMR_SLEEP (0x1u << 20) /**< \brief (CAN_IMR) Sleep Interrupt Mask */
+#define CAN_IMR_WAKEUP (0x1u << 21) /**< \brief (CAN_IMR) Wakeup Interrupt Mask */
+#define CAN_IMR_TOVF (0x1u << 22) /**< \brief (CAN_IMR) Timer Overflow Interrupt Mask */
+#define CAN_IMR_TSTP (0x1u << 23) /**< \brief (CAN_IMR) Timestamp Interrupt Mask */
+#define CAN_IMR_CERR (0x1u << 24) /**< \brief (CAN_IMR) CRC Error Interrupt Mask */
+#define CAN_IMR_SERR (0x1u << 25) /**< \brief (CAN_IMR) Stuffing Error Interrupt Mask */
+#define CAN_IMR_AERR (0x1u << 26) /**< \brief (CAN_IMR) Acknowledgment Error Interrupt Mask */
+#define CAN_IMR_FERR (0x1u << 27) /**< \brief (CAN_IMR) Form Error Interrupt Mask */
+#define CAN_IMR_BERR (0x1u << 28) /**< \brief (CAN_IMR) Bit Error Interrupt Mask */
+/* -------- CAN_SR : (CAN Offset: 0x0010) Status Register -------- */
+#define CAN_SR_MB0 (0x1u << 0) /**< \brief (CAN_SR) Mailbox 0 Event */
+#define CAN_SR_MB1 (0x1u << 1) /**< \brief (CAN_SR) Mailbox 1 Event */
+#define CAN_SR_MB2 (0x1u << 2) /**< \brief (CAN_SR) Mailbox 2 Event */
+#define CAN_SR_MB3 (0x1u << 3) /**< \brief (CAN_SR) Mailbox 3 Event */
+#define CAN_SR_MB4 (0x1u << 4) /**< \brief (CAN_SR) Mailbox 4 Event */
+#define CAN_SR_MB5 (0x1u << 5) /**< \brief (CAN_SR) Mailbox 5 Event */
+#define CAN_SR_MB6 (0x1u << 6) /**< \brief (CAN_SR) Mailbox 6 Event */
+#define CAN_SR_MB7 (0x1u << 7) /**< \brief (CAN_SR) Mailbox 7 Event */
+#define CAN_SR_ERRA (0x1u << 16) /**< \brief (CAN_SR) Error Active Mode */
+#define CAN_SR_WARN (0x1u << 17) /**< \brief (CAN_SR) Warning Limit */
+#define CAN_SR_ERRP (0x1u << 18) /**< \brief (CAN_SR) Error Passive Mode */
+#define CAN_SR_BOFF (0x1u << 19) /**< \brief (CAN_SR) Bus Off Mode */
+#define CAN_SR_SLEEP (0x1u << 20) /**< \brief (CAN_SR) CAN controller in Low power Mode */
+#define CAN_SR_WAKEUP (0x1u << 21) /**< \brief (CAN_SR) CAN controller is not in Low power Mode */
+#define CAN_SR_TOVF (0x1u << 22) /**< \brief (CAN_SR) Timer Overflow */
+#define CAN_SR_TSTP (0x1u << 23) /**< \brief (CAN_SR) */
+#define CAN_SR_CERR (0x1u << 24) /**< \brief (CAN_SR) Mailbox CRC Error */
+#define CAN_SR_SERR (0x1u << 25) /**< \brief (CAN_SR) Mailbox Stuffing Error */
+#define CAN_SR_AERR (0x1u << 26) /**< \brief (CAN_SR) Acknowledgment Error */
+#define CAN_SR_FERR (0x1u << 27) /**< \brief (CAN_SR) Form Error */
+#define CAN_SR_BERR (0x1u << 28) /**< \brief (CAN_SR) Bit Error */
+#define CAN_SR_RBSY (0x1u << 29) /**< \brief (CAN_SR) Receiver busy */
+#define CAN_SR_TBSY (0x1u << 30) /**< \brief (CAN_SR) Transmitter busy */
+#define CAN_SR_OVLSY (0x1u << 31) /**< \brief (CAN_SR) Overload busy */
+/* -------- CAN_BR : (CAN Offset: 0x0014) Baudrate Register -------- */
+#define CAN_BR_PHASE2_Pos 0
+#define CAN_BR_PHASE2_Msk (0x7u << CAN_BR_PHASE2_Pos) /**< \brief (CAN_BR) Phase 2 segment */
+#define CAN_BR_PHASE2(value) ((CAN_BR_PHASE2_Msk & ((value) << CAN_BR_PHASE2_Pos)))
+#define CAN_BR_PHASE1_Pos 4
+#define CAN_BR_PHASE1_Msk (0x7u << CAN_BR_PHASE1_Pos) /**< \brief (CAN_BR) Phase 1 segment */
+#define CAN_BR_PHASE1(value) ((CAN_BR_PHASE1_Msk & ((value) << CAN_BR_PHASE1_Pos)))
+#define CAN_BR_PROPAG_Pos 8
+#define CAN_BR_PROPAG_Msk (0x7u << CAN_BR_PROPAG_Pos) /**< \brief (CAN_BR) Programming time segment */
+#define CAN_BR_PROPAG(value) ((CAN_BR_PROPAG_Msk & ((value) << CAN_BR_PROPAG_Pos)))
+#define CAN_BR_SJW_Pos 12
+#define CAN_BR_SJW_Msk (0x3u << CAN_BR_SJW_Pos) /**< \brief (CAN_BR) Re-synchronization jump width */
+#define CAN_BR_SJW(value) ((CAN_BR_SJW_Msk & ((value) << CAN_BR_SJW_Pos)))
+#define CAN_BR_BRP_Pos 16
+#define CAN_BR_BRP_Msk (0x7fu << CAN_BR_BRP_Pos) /**< \brief (CAN_BR) Baudrate Prescaler. */
+#define CAN_BR_BRP(value) ((CAN_BR_BRP_Msk & ((value) << CAN_BR_BRP_Pos)))
+#define CAN_BR_SMP (0x1u << 24) /**< \brief (CAN_BR) Sampling Mode */
+#define CAN_BR_SMP_ONCE (0x0u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled once at sample point. */
+#define CAN_BR_SMP_THREE (0x1u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. */
+/* -------- CAN_TIM : (CAN Offset: 0x0018) Timer Register -------- */
+#define CAN_TIM_TIMER0 (0x1u << 0) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER1 (0x1u << 1) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER2 (0x1u << 2) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER3 (0x1u << 3) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER4 (0x1u << 4) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER5 (0x1u << 5) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER6 (0x1u << 6) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER7 (0x1u << 7) /**< \brief (CAN_TIM) Timer */
+/* -------- CAN_TIMESTP : (CAN Offset: 0x001C) Timestamp Register -------- */
+#define CAN_TIMESTP_MTIMESTAMP0 (0x1u << 0) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP1 (0x1u << 1) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP2 (0x1u << 2) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP3 (0x1u << 3) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP4 (0x1u << 4) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP5 (0x1u << 5) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP6 (0x1u << 6) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP7 (0x1u << 7) /**< \brief (CAN_TIMESTP) Timestamp */
+/* -------- CAN_ECR : (CAN Offset: 0x0020) Error Counter Register -------- */
+#define CAN_ECR_REC_Pos 0
+#define CAN_ECR_REC_Msk (0xffu << CAN_ECR_REC_Pos) /**< \brief (CAN_ECR) Receive Error Counter */
+#define CAN_ECR_TEC_Pos 16
+#define CAN_ECR_TEC_Msk (0xffu << CAN_ECR_TEC_Pos) /**< \brief (CAN_ECR) Transmit Error Counter */
+/* -------- CAN_TCR : (CAN Offset: 0x0024) Transfer Command Register -------- */
+#define CAN_TCR_MB0 (0x1u << 0) /**< \brief (CAN_TCR) Transfer Request for Mailbox 0 */
+#define CAN_TCR_MB1 (0x1u << 1) /**< \brief (CAN_TCR) Transfer Request for Mailbox 1 */
+#define CAN_TCR_MB2 (0x1u << 2) /**< \brief (CAN_TCR) Transfer Request for Mailbox 2 */
+#define CAN_TCR_MB3 (0x1u << 3) /**< \brief (CAN_TCR) Transfer Request for Mailbox 3 */
+#define CAN_TCR_MB4 (0x1u << 4) /**< \brief (CAN_TCR) Transfer Request for Mailbox 4 */
+#define CAN_TCR_MB5 (0x1u << 5) /**< \brief (CAN_TCR) Transfer Request for Mailbox 5 */
+#define CAN_TCR_MB6 (0x1u << 6) /**< \brief (CAN_TCR) Transfer Request for Mailbox 6 */
+#define CAN_TCR_MB7 (0x1u << 7) /**< \brief (CAN_TCR) Transfer Request for Mailbox 7 */
+#define CAN_TCR_TIMRST (0x1u << 31) /**< \brief (CAN_TCR) Timer Reset */
+/* -------- CAN_ACR : (CAN Offset: 0x0028) Abort Command Register -------- */
+#define CAN_ACR_MB0 (0x1u << 0) /**< \brief (CAN_ACR) Abort Request for Mailbox 0 */
+#define CAN_ACR_MB1 (0x1u << 1) /**< \brief (CAN_ACR) Abort Request for Mailbox 1 */
+#define CAN_ACR_MB2 (0x1u << 2) /**< \brief (CAN_ACR) Abort Request for Mailbox 2 */
+#define CAN_ACR_MB3 (0x1u << 3) /**< \brief (CAN_ACR) Abort Request for Mailbox 3 */
+#define CAN_ACR_MB4 (0x1u << 4) /**< \brief (CAN_ACR) Abort Request for Mailbox 4 */
+#define CAN_ACR_MB5 (0x1u << 5) /**< \brief (CAN_ACR) Abort Request for Mailbox 5 */
+#define CAN_ACR_MB6 (0x1u << 6) /**< \brief (CAN_ACR) Abort Request for Mailbox 6 */
+#define CAN_ACR_MB7 (0x1u << 7) /**< \brief (CAN_ACR) Abort Request for Mailbox 7 */
+/* -------- CAN_MMR : (CAN Offset: N/A) Mailbox Mode Register -------- */
+#define CAN_MMR_MTIMEMARK0 (0x1u << 0) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK1 (0x1u << 1) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK2 (0x1u << 2) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK3 (0x1u << 3) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK4 (0x1u << 4) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK5 (0x1u << 5) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK6 (0x1u << 6) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK7 (0x1u << 7) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_PRIOR_Pos 16
+#define CAN_MMR_PRIOR_Msk (0xfu << CAN_MMR_PRIOR_Pos) /**< \brief (CAN_MMR) Mailbox Priority */
+#define CAN_MMR_PRIOR(value) ((CAN_MMR_PRIOR_Msk & ((value) << CAN_MMR_PRIOR_Pos)))
+#define CAN_MMR_MOT_Pos 24
+#define CAN_MMR_MOT_Msk (0x7u << CAN_MMR_MOT_Pos) /**< \brief (CAN_MMR) Mailbox Object Type */
+#define CAN_MMR_MOT_MB_DISABLED (0x0u << 24) /**< \brief (CAN_MMR) Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. */
+#define CAN_MMR_MOT_MB_RX (0x1u << 24) /**< \brief (CAN_MMR) Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. */
+#define CAN_MMR_MOT_MB_RX_OVERWRITE (0x2u << 24) /**< \brief (CAN_MMR) Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. */
+#define CAN_MMR_MOT_MB_TX (0x3u << 24) /**< \brief (CAN_MMR) Transmit mailbox. Mailbox is configured for transmission. */
+#define CAN_MMR_MOT_MB_CONSUMER (0x4u << 24) /**< \brief (CAN_MMR) Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. */
+#define CAN_MMR_MOT_MB_PRODUCER (0x5u << 24) /**< \brief (CAN_MMR) Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. */
+/* -------- CAN_MAM : (CAN Offset: N/A) Mailbox Acceptance Mask Register -------- */
+#define CAN_MAM_MIDvB_Pos 0
+#define CAN_MAM_MIDvB_Msk (0x3ffffu << CAN_MAM_MIDvB_Pos) /**< \brief (CAN_MAM) Complementary bits for identifier in extended frame mode */
+#define CAN_MAM_MIDvB(value) ((CAN_MAM_MIDvB_Msk & ((value) << CAN_MAM_MIDvB_Pos)))
+#define CAN_MAM_MIDvA_Pos 18
+#define CAN_MAM_MIDvA_Msk (0x7ffu << CAN_MAM_MIDvA_Pos) /**< \brief (CAN_MAM) Identifier for standard frame mode */
+#define CAN_MAM_MIDvA(value) ((CAN_MAM_MIDvA_Msk & ((value) << CAN_MAM_MIDvA_Pos)))
+#define CAN_MAM_MIDE (0x1u << 29) /**< \brief (CAN_MAM) Identifier Version */
+/* -------- CAN_MID : (CAN Offset: N/A) Mailbox ID Register -------- */
+#define CAN_MID_MIDvB_Pos 0
+#define CAN_MID_MIDvB_Msk (0x3ffffu << CAN_MID_MIDvB_Pos) /**< \brief (CAN_MID) Complementary bits for identifier in extended frame mode */
+#define CAN_MID_MIDvB(value) ((CAN_MID_MIDvB_Msk & ((value) << CAN_MID_MIDvB_Pos)))
+#define CAN_MID_MIDvA_Pos 18
+#define CAN_MID_MIDvA_Msk (0x7ffu << CAN_MID_MIDvA_Pos) /**< \brief (CAN_MID) Identifier for standard frame mode */
+#define CAN_MID_MIDvA(value) ((CAN_MID_MIDvA_Msk & ((value) << CAN_MID_MIDvA_Pos)))
+#define CAN_MID_MIDE (0x1u << 29) /**< \brief (CAN_MID) Identifier Version */
+/* -------- CAN_MFID : (CAN Offset: N/A) Mailbox Family ID Register -------- */
+#define CAN_MFID_MFID_Pos 0
+#define CAN_MFID_MFID_Msk (0x1fffffffu << CAN_MFID_MFID_Pos) /**< \brief (CAN_MFID) Family ID */
+/* -------- CAN_MSR : (CAN Offset: N/A) Mailbox Status Register -------- */
+#define CAN_MSR_MTIMESTAMP0 (0x1u << 0) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP1 (0x1u << 1) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP2 (0x1u << 2) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP3 (0x1u << 3) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP4 (0x1u << 4) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP5 (0x1u << 5) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP6 (0x1u << 6) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP7 (0x1u << 7) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MDLC_Pos 16
+#define CAN_MSR_MDLC_Msk (0xfu << CAN_MSR_MDLC_Pos) /**< \brief (CAN_MSR) Mailbox Data Length Code */
+#define CAN_MSR_MRTR (0x1u << 20) /**< \brief (CAN_MSR) Mailbox Remote Transmission Request */
+#define CAN_MSR_MABT (0x1u << 22) /**< \brief (CAN_MSR) Mailbox Message Abort */
+#define CAN_MSR_MRDY (0x1u << 23) /**< \brief (CAN_MSR) Mailbox Ready */
+#define CAN_MSR_MMI (0x1u << 24) /**< \brief (CAN_MSR) Mailbox Message Ignored */
+/* -------- CAN_MDL : (CAN Offset: N/A) Mailbox Data Low Register -------- */
+#define CAN_MDL_MDL_Pos 0
+#define CAN_MDL_MDL_Msk (0xffffffffu << CAN_MDL_MDL_Pos) /**< \brief (CAN_MDL) Message Data Low Value */
+#define CAN_MDL_MDL(value) ((CAN_MDL_MDL_Msk & ((value) << CAN_MDL_MDL_Pos)))
+/* -------- CAN_MDH : (CAN Offset: N/A) Mailbox Data High Register -------- */
+#define CAN_MDH_MDH_Pos 0
+#define CAN_MDH_MDH_Msk (0xffffffffu << CAN_MDH_MDH_Pos) /**< \brief (CAN_MDH) Message Data High Value */
+#define CAN_MDH_MDH(value) ((CAN_MDH_MDH_Msk & ((value) << CAN_MDH_MDH_Pos)))
+/* -------- CAN_MCR : (CAN Offset: N/A) Mailbox Control Register -------- */
+#define CAN_MCR_MDLC_Pos 16
+#define CAN_MCR_MDLC_Msk (0xfu << CAN_MCR_MDLC_Pos) /**< \brief (CAN_MCR) Mailbox Data Length Code */
+#define CAN_MCR_MDLC(value) ((CAN_MCR_MDLC_Msk & ((value) << CAN_MCR_MDLC_Pos)))
+#define CAN_MCR_MRTR (0x1u << 20) /**< \brief (CAN_MCR) Mailbox Remote Transmission Request */
+#define CAN_MCR_MACR (0x1u << 22) /**< \brief (CAN_MCR) Abort Request for Mailbox x */
+#define CAN_MCR_MTCR (0x1u << 23) /**< \brief (CAN_MCR) Mailbox Transfer Command */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_CHIPID Chip Identifier */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Chipid hardware registers */
+typedef struct {
+ RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+ RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* __ASSEMBLY__ */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) */
+#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxA Series (48-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3SDxA (0x98u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxA Series (48-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */
+#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_DACC Digital-to-Analog Converter Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Dacc hardware registers */
+typedef struct {
+ WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */
+ RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */
+ RoReg Reserved1[2];
+ WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
+ WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
+ RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */
+ RoReg Reserved2[1];
+ WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */
+ WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
+ WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
+ RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
+ RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
+ RoReg Reserved3[24];
+ RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */
+ RoReg Reserved4[19];
+ RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */
+ RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */
+ RoReg Reserved5[5];
+ RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */
+ RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */
+ RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
+ RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
+ RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */
+ RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */
+ RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
+ RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
+ WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
+ RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
+} Dacc;
+#endif /* __ASSEMBLY__ */
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
+#define DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */
+#define DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */
+#define DACC_MR_TRGSEL_Pos 1
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */
+#define DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */
+#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */
+#define DACC_MR_REFRESH_Pos 8
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
+#define DACC_MR_USER_SEL_Pos 16
+#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */
+#define DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */
+#define DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */
+#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */
+#define DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */
+#define DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */
+#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */
+#define DACC_MR_STARTUP_Pos 24
+#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
+#define DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */
+#define DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */
+#define DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */
+#define DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */
+#define DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */
+#define DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */
+#define DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */
+#define DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */
+#define DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */
+#define DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */
+#define DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */
+#define DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */
+#define DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */
+#define DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */
+#define DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */
+#define DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */
+#define DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */
+#define DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */
+#define DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */
+#define DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */
+#define DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */
+#define DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */
+#define DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */
+#define DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */
+#define DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */
+#define DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */
+#define DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */
+#define DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */
+#define DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */
+#define DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */
+#define DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */
+#define DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
+/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */
+#define DACC_CDR_DATA_Pos 0
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */
+#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */
+#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */
+#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */
+#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */
+#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */
+#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */
+#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */
+#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */
+#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */
+#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */
+#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */
+#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
+#define DACC_ACR_IBCTLCH0_Pos 0
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
+#define DACC_ACR_IBCTLCH1_Pos 2
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
+#define DACC_ACR_IBCTLDACCORE_Pos 8
+#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */
+#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
+#define DACC_WPMR_WPKEY_Pos 8
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
+#define DACC_WPSR_WPROTADDR_Pos 8
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
+/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */
+#define DACC_RPR_RXPTR_Pos 0
+#define DACC_RPR_RXPTR_Msk (0xffffffffu << DACC_RPR_RXPTR_Pos) /**< \brief (DACC_RPR) Receive Pointer Register */
+#define DACC_RPR_RXPTR(value) ((DACC_RPR_RXPTR_Msk & ((value) << DACC_RPR_RXPTR_Pos)))
+/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */
+#define DACC_RCR_RXCTR_Pos 0
+#define DACC_RCR_RXCTR_Msk (0xffffu << DACC_RCR_RXCTR_Pos) /**< \brief (DACC_RCR) Receive Counter Register */
+#define DACC_RCR_RXCTR(value) ((DACC_RCR_RXCTR_Msk & ((value) << DACC_RCR_RXCTR_Pos)))
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
+#define DACC_TPR_TXPTR_Pos 0
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
+#define DACC_TCR_TXCTR_Pos 0
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
+/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */
+#define DACC_RNPR_RXNPTR_Pos 0
+#define DACC_RNPR_RXNPTR_Msk (0xffffffffu << DACC_RNPR_RXNPTR_Pos) /**< \brief (DACC_RNPR) Receive Next Pointer */
+#define DACC_RNPR_RXNPTR(value) ((DACC_RNPR_RXNPTR_Msk & ((value) << DACC_RNPR_RXNPTR_Pos)))
+/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */
+#define DACC_RNCR_RXNCTR_Pos 0
+#define DACC_RNCR_RXNCTR_Msk (0xffffu << DACC_RNCR_RXNCTR_Pos) /**< \brief (DACC_RNCR) Receive Next Counter */
+#define DACC_RNCR_RXNCTR(value) ((DACC_RNCR_RXNCTR_Msk & ((value) << DACC_RNCR_RXNCTR_Pos)))
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define DACC_TNPR_TXNPTR_Pos 0
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define DACC_TNCR_TXNCTR_Pos 0
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_DMAC DMA Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief DmacCh_num hardware registers */
+typedef struct {
+ RwReg DMAC_SADDR; /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */
+ RwReg DMAC_DADDR; /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */
+ RwReg DMAC_DSCR; /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */
+ RwReg DMAC_CTRLA; /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */
+ RwReg DMAC_CTRLB; /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */
+ RwReg DMAC_CFG; /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */
+ RoReg Reserved1[4];
+} DmacCh_num;
+/** \brief Dmac hardware registers */
+#define DMACCH_NUM_NUMBER 6
+typedef struct {
+ RwReg DMAC_GCFG; /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */
+ RwReg DMAC_EN; /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */
+ RwReg DMAC_SREQ; /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */
+ RwReg DMAC_CREQ; /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */
+ RwReg DMAC_LAST; /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */
+ RoReg Reserved1[1];
+ WoReg DMAC_EBCIER; /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+ WoReg DMAC_EBCIDR; /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+ RoReg DMAC_EBCIMR; /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+ RoReg DMAC_EBCISR; /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+ WoReg DMAC_CHER; /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */
+ WoReg DMAC_CHDR; /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */
+ RoReg DMAC_CHSR; /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */
+ RoReg Reserved2[2];
+ DmacCh_num DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 5 */
+ RoReg Reserved3[46];
+ RwReg DMAC_WPMR; /**< \brief (Dmac Offset: 0x1E4) DMAC Write Protect Mode Register */
+ RoReg DMAC_WPSR; /**< \brief (Dmac Offset: 0x1E8) DMAC Write Protect Status Register */
+} Dmac;
+#endif /* __ASSEMBLY__ */
+/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */
+#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) Arbiter Configuration */
+#define DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) /**< \brief (DMAC_GCFG) Fixed priority arbiter. */
+#define DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) /**< \brief (DMAC_GCFG) Modified round robin arbiter. */
+/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */
+#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN) */
+/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */
+#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ4 (0x1u << 8) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ4 (0x1u << 9) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ5 (0x1u << 10) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ5 (0x1u << 11) /**< \brief (DMAC_SREQ) Destination Request */
+/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */
+#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ4 (0x1u << 8) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ4 (0x1u << 9) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ5 (0x1u << 10) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ5 (0x1u << 11) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */
+#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST4 (0x1u << 8) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST4 (0x1u << 9) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST5 (0x1u << 10) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST5 (0x1u << 11) /**< \brief (DMAC_LAST) Destination Last */
+/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */
+#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */
+#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */
+#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */
+#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */
+#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA4 (0x1u << 4) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA5 (0x1u << 5) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP4 (0x1u << 28) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP5 (0x1u << 29) /**< \brief (DMAC_CHER) Keep on [5:0] */
+/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */
+#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS4 (0x1u << 4) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS5 (0x1u << 5) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES4 (0x1u << 12) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES5 (0x1u << 13) /**< \brief (DMAC_CHDR) Resume [5:0] */
+/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */
+#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA4 (0x1u << 4) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA5 (0x1u << 5) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT4 (0x1u << 20) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT5 (0x1u << 21) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL4 (0x1u << 28) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL5 (0x1u << 29) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */
+#define DMAC_SADDR_SADDR_Pos 0
+#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) /**< \brief (DMAC_SADDR) Channel x Source Address */
+#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos)))
+/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */
+#define DMAC_DADDR_DADDR_Pos 0
+#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) /**< \brief (DMAC_DADDR) Channel x Destination Address */
+#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos)))
+/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */
+#define DMAC_DSCR_DSCR_Pos 2
+#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) /**< \brief (DMAC_DSCR) Buffer Transfer Descriptor Address */
+#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos)))
+/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */
+#define DMAC_CTRLA_BTSIZE_Pos 0
+#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) Buffer Transfer Size */
+#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))
+#define DMAC_CTRLA_SCSIZE_Pos 16
+#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA) Source Chunk Transfer Size. */
+#define DMAC_CTRLA_SCSIZE_CHK_1 (0x0u << 16) /**< \brief (DMAC_CTRLA) 1 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_4 (0x1u << 16) /**< \brief (DMAC_CTRLA) 4 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_8 (0x2u << 16) /**< \brief (DMAC_CTRLA) 8 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_16 (0x3u << 16) /**< \brief (DMAC_CTRLA) 16 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_32 (0x4u << 16) /**< \brief (DMAC_CTRLA) 32 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_64 (0x5u << 16) /**< \brief (DMAC_CTRLA) 64 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_128 (0x6u << 16) /**< \brief (DMAC_CTRLA) 128 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_256 (0x7u << 16) /**< \brief (DMAC_CTRLA) 256 data transferred */
+#define DMAC_CTRLA_DCSIZE_Pos 20
+#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA) Destination Chunk Transfer Size */
+#define DMAC_CTRLA_DCSIZE_CHK_1 (0x0u << 20) /**< \brief (DMAC_CTRLA) 1 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_4 (0x1u << 20) /**< \brief (DMAC_CTRLA) 4 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_8 (0x2u << 20) /**< \brief (DMAC_CTRLA) 8 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_16 (0x3u << 20) /**< \brief (DMAC_CTRLA) 16 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_32 (0x4u << 20) /**< \brief (DMAC_CTRLA) 32 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_64 (0x5u << 20) /**< \brief (DMAC_CTRLA) 64 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_128 (0x6u << 20) /**< \brief (DMAC_CTRLA) 128 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_256 (0x7u << 20) /**< \brief (DMAC_CTRLA) 256 data transferred */
+#define DMAC_CTRLA_SRC_WIDTH_Pos 24
+#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Source */
+#define DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
+#define DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
+#define DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
+#define DMAC_CTRLA_DST_WIDTH_Pos 28
+#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Destination */
+#define DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
+#define DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
+#define DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
+#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA) */
+/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */
+#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) Source Address Descriptor */
+#define DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) /**< \brief (DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory. */
+#define DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source. */
+#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) Destination Address Descriptor */
+#define DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) /**< \brief (DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory. */
+#define DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination. */
+#define DMAC_CTRLB_FC_Pos 21
+#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) Flow Control */
+#define DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller */
+#define DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller */
+#define DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller */
+#define DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller */
+#define DMAC_CTRLB_SRC_INCR_Pos 24
+#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source */
+#define DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) /**< \brief (DMAC_CTRLB) The source address is incremented */
+#define DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) /**< \brief (DMAC_CTRLB) The source address is decremented */
+#define DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) /**< \brief (DMAC_CTRLB) The source address remains unchanged */
+#define DMAC_CTRLB_DST_INCR_Pos 28
+#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination */
+#define DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) /**< \brief (DMAC_CTRLB) The destination address is incremented */
+#define DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) /**< \brief (DMAC_CTRLB) The destination address is decremented */
+#define DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) /**< \brief (DMAC_CTRLB) The destination address remains unchanged */
+#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB) */
+/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */
+#define DMAC_CFG_SRC_PER_Pos 0
+#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) Source with Peripheral identifier */
+#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))
+#define DMAC_CFG_DST_PER_Pos 4
+#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) Destination with Peripheral identifier */
+#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))
+#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Source */
+#define DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Destination */
+#define DMAC_CFG_DST_H2SEL_SW (0x0u << 13) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_DST_H2SEL_HW (0x1u << 13) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) Stop On Done */
+#define DMAC_CFG_SOD_DISABLE (0x0u << 16) /**< \brief (DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. */
+#define DMAC_CFG_SOD_ENABLE (0x1u << 16) /**< \brief (DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. */
+#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock */
+#define DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is disabled */
+#define DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is enabled */
+#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) Bus Lock */
+#define DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) /**< \brief (DMAC_CFG) AHB Bus Locking capability is disabled. */
+#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) Master Interface Arbiter Lock */
+#define DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer. */
+#define DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer. */
+#define DMAC_CFG_AHB_PROT_Pos 24
+#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) AHB Protection */
+#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))
+#define DMAC_CFG_FIFOCFG_Pos 28
+#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) FIFO Configuration */
+#define DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) /**< \brief (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface. */
+#define DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) /**< \brief (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced. */
+#define DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) /**< \brief (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced. */
+/* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */
+#define DMAC_WPMR_WPEN (0x1u << 0) /**< \brief (DMAC_WPMR) Write Protect Enable */
+#define DMAC_WPMR_WPKEY_Pos 8
+#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) /**< \brief (DMAC_WPMR) Write Protect KEY */
+#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos)))
+/* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */
+#define DMAC_WPSR_WPVS (0x1u << 0) /**< \brief (DMAC_WPSR) Write Protect Violation Status */
+#define DMAC_WPSR_WPVSRC_Pos 8
+#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) /**< \brief (DMAC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_EFC Embedded Flash Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Efc hardware registers */
+typedef struct {
+ RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+ WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+ RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+ RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* __ASSEMBLY__ */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_EMAC Ethernet MAC 10/100 */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief EmacSa hardware registers */
+typedef struct {
+ RwReg EMAC_SAxB; /**< \brief (EmacSa Offset: 0x0) Specific Address 1 Bottom Register */
+ RwReg EMAC_SAxT; /**< \brief (EmacSa Offset: 0x4) Specific Address 1 Top Register */
+} EmacSa;
+/** \brief Emac hardware registers */
+#define EMACSA_NUMBER 4
+typedef struct {
+ RwReg EMAC_NCR; /**< \brief (Emac Offset: 0x00) Network Control Register */
+ RwReg EMAC_NCFGR; /**< \brief (Emac Offset: 0x04) Network Configuration Register */
+ RoReg EMAC_NSR; /**< \brief (Emac Offset: 0x08) Network Status Register */
+ RoReg Reserved1[2];
+ RwReg EMAC_TSR; /**< \brief (Emac Offset: 0x14) Transmit Status Register */
+ RwReg EMAC_RBQP; /**< \brief (Emac Offset: 0x18) Receive Buffer Queue Pointer Register */
+ RwReg EMAC_TBQP; /**< \brief (Emac Offset: 0x1C) Transmit Buffer Queue Pointer Register */
+ RwReg EMAC_RSR; /**< \brief (Emac Offset: 0x20) Receive Status Register */
+ RwReg EMAC_ISR; /**< \brief (Emac Offset: 0x24) Interrupt Status Register */
+ WoReg EMAC_IER; /**< \brief (Emac Offset: 0x28) Interrupt Enable Register */
+ WoReg EMAC_IDR; /**< \brief (Emac Offset: 0x2C) Interrupt Disable Register */
+ RoReg EMAC_IMR; /**< \brief (Emac Offset: 0x30) Interrupt Mask Register */
+ RwReg EMAC_MAN; /**< \brief (Emac Offset: 0x34) Phy Maintenance Register */
+ RwReg EMAC_PTR; /**< \brief (Emac Offset: 0x38) Pause Time Register */
+ RwReg EMAC_PFR; /**< \brief (Emac Offset: 0x3C) Pause Frames Received Register */
+ RwReg EMAC_FTO; /**< \brief (Emac Offset: 0x40) Frames Transmitted Ok Register */
+ RwReg EMAC_SCF; /**< \brief (Emac Offset: 0x44) Single Collision Frames Register */
+ RwReg EMAC_MCF; /**< \brief (Emac Offset: 0x48) Multiple Collision Frames Register */
+ RwReg EMAC_FRO; /**< \brief (Emac Offset: 0x4C) Frames Received Ok Register */
+ RwReg EMAC_FCSE; /**< \brief (Emac Offset: 0x50) Frame Check Sequence Errors Register */
+ RwReg EMAC_ALE; /**< \brief (Emac Offset: 0x54) Alignment Errors Register */
+ RwReg EMAC_DTF; /**< \brief (Emac Offset: 0x58) Deferred Transmission Frames Register */
+ RwReg EMAC_LCOL; /**< \brief (Emac Offset: 0x5C) Late Collisions Register */
+ RwReg EMAC_ECOL; /**< \brief (Emac Offset: 0x60) Excessive Collisions Register */
+ RwReg EMAC_TUND; /**< \brief (Emac Offset: 0x64) Transmit Underrun Errors Register */
+ RwReg EMAC_CSE; /**< \brief (Emac Offset: 0x68) Carrier Sense Errors Register */
+ RwReg EMAC_RRE; /**< \brief (Emac Offset: 0x6C) Receive Resource Errors Register */
+ RwReg EMAC_ROV; /**< \brief (Emac Offset: 0x70) Receive Overrun Errors Register */
+ RwReg EMAC_RSE; /**< \brief (Emac Offset: 0x74) Receive Symbol Errors Register */
+ RwReg EMAC_ELE; /**< \brief (Emac Offset: 0x78) Excessive Length Errors Register */
+ RwReg EMAC_RJA; /**< \brief (Emac Offset: 0x7C) Receive Jabbers Register */
+ RwReg EMAC_USF; /**< \brief (Emac Offset: 0x80) Undersize Frames Register */
+ RwReg EMAC_STE; /**< \brief (Emac Offset: 0x84) SQE Test Errors Register */
+ RwReg EMAC_RLE; /**< \brief (Emac Offset: 0x88) Received Length Field Mismatch Register */
+ RoReg Reserved2[1];
+ RwReg EMAC_HRB; /**< \brief (Emac Offset: 0x90) Hash Register Bottom [31:0] Register */
+ RwReg EMAC_HRT; /**< \brief (Emac Offset: 0x94) Hash Register Top [63:32] Register */
+ EmacSa EMAC_SA[EMACSA_NUMBER]; /**< \brief (Emac Offset: 0x98) sa = 1 .. 4 */
+ RwReg EMAC_TID; /**< \brief (Emac Offset: 0xB8) Type ID Checking Register */
+ RoReg Reserved3[1];
+ RwReg EMAC_USRIO; /**< \brief (Emac Offset: 0xC0) User Input/Output Register */
+} Emac;
+#endif /* __ASSEMBLY__ */
+/* -------- EMAC_NCR : (EMAC Offset: 0x00) Network Control Register -------- */
+#define EMAC_NCR_LB (0x1u << 0) /**< \brief (EMAC_NCR) LoopBack */
+#define EMAC_NCR_LLB (0x1u << 1) /**< \brief (EMAC_NCR) Loopback local */
+#define EMAC_NCR_RE (0x1u << 2) /**< \brief (EMAC_NCR) Receive enable */
+#define EMAC_NCR_TE (0x1u << 3) /**< \brief (EMAC_NCR) Transmit enable */
+#define EMAC_NCR_MPE (0x1u << 4) /**< \brief (EMAC_NCR) Management port enable */
+#define EMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (EMAC_NCR) Clear statistics registers */
+#define EMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (EMAC_NCR) Increment statistics registers */
+#define EMAC_NCR_WESTAT (0x1u << 7) /**< \brief (EMAC_NCR) Write enable for statistics registers */
+#define EMAC_NCR_BP (0x1u << 8) /**< \brief (EMAC_NCR) Back pressure */
+#define EMAC_NCR_TSTART (0x1u << 9) /**< \brief (EMAC_NCR) Start transmission */
+#define EMAC_NCR_THALT (0x1u << 10) /**< \brief (EMAC_NCR) Transmit halt */
+/* -------- EMAC_NCFGR : (EMAC Offset: 0x04) Network Configuration Register -------- */
+#define EMAC_NCFGR_SPD (0x1u << 0) /**< \brief (EMAC_NCFGR) Speed */
+#define EMAC_NCFGR_FD (0x1u << 1) /**< \brief (EMAC_NCFGR) Full Duplex */
+#define EMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (EMAC_NCFGR) Jumbo Frames */
+#define EMAC_NCFGR_CAF (0x1u << 4) /**< \brief (EMAC_NCFGR) Copy All Frames */
+#define EMAC_NCFGR_NBC (0x1u << 5) /**< \brief (EMAC_NCFGR) No Broadcast */
+#define EMAC_NCFGR_MTI (0x1u << 6) /**< \brief (EMAC_NCFGR) Multicast Hash Enable */
+#define EMAC_NCFGR_UNI (0x1u << 7) /**< \brief (EMAC_NCFGR) Unicast Hash Enable */
+#define EMAC_NCFGR_BIG (0x1u << 8) /**< \brief (EMAC_NCFGR) Receive 1536 bytes frames */
+#define EMAC_NCFGR_CLK_Pos 10
+#define EMAC_NCFGR_CLK_Msk (0x3u << EMAC_NCFGR_CLK_Pos) /**< \brief (EMAC_NCFGR) MDC clock divider */
+#define EMAC_NCFGR_CLK_MCK_8 (0x0u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz). */
+#define EMAC_NCFGR_CLK_MCK_16 (0x1u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz). */
+#define EMAC_NCFGR_CLK_MCK_32 (0x2u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz). */
+#define EMAC_NCFGR_CLK_MCK_64 (0x3u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz). */
+#define EMAC_NCFGR_RTY (0x1u << 12) /**< \brief (EMAC_NCFGR) Retry test */
+#define EMAC_NCFGR_PAE (0x1u << 13) /**< \brief (EMAC_NCFGR) Pause Enable */
+#define EMAC_NCFGR_RBOF_Pos 14
+#define EMAC_NCFGR_RBOF_Msk (0x3u << EMAC_NCFGR_RBOF_Pos) /**< \brief (EMAC_NCFGR) Receive Buffer Offset */
+#define EMAC_NCFGR_RBOF_OFFSET_0 (0x0u << 14) /**< \brief (EMAC_NCFGR) No offset from start of receive buffer. */
+#define EMAC_NCFGR_RBOF_OFFSET_1 (0x1u << 14) /**< \brief (EMAC_NCFGR) One-byte offset from start of receive buffer. */
+#define EMAC_NCFGR_RBOF_OFFSET_2 (0x2u << 14) /**< \brief (EMAC_NCFGR) Two-byte offset from start of receive buffer. */
+#define EMAC_NCFGR_RBOF_OFFSET_3 (0x3u << 14) /**< \brief (EMAC_NCFGR) Three-byte offset from start of receive buffer. */
+#define EMAC_NCFGR_RLCE (0x1u << 16) /**< \brief (EMAC_NCFGR) Receive Length field Checking Enable */
+#define EMAC_NCFGR_DRFCS (0x1u << 17) /**< \brief (EMAC_NCFGR) Discard Receive FCS */
+#define EMAC_NCFGR_EFRHD (0x1u << 18) /**< \brief (EMAC_NCFGR) */
+#define EMAC_NCFGR_IRXFCS (0x1u << 19) /**< \brief (EMAC_NCFGR) Ignore RX FCS */
+/* -------- EMAC_NSR : (EMAC Offset: 0x08) Network Status Register -------- */
+#define EMAC_NSR_MDIO (0x1u << 1) /**< \brief (EMAC_NSR) */
+#define EMAC_NSR_IDLE (0x1u << 2) /**< \brief (EMAC_NSR) */
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
+#define EMAC_TSR_UBR (0x1u << 0) /**< \brief (EMAC_TSR) Used Bit Read */
+#define EMAC_TSR_COL (0x1u << 1) /**< \brief (EMAC_TSR) Collision Occurred */
+#define EMAC_TSR_RLES (0x1u << 2) /**< \brief (EMAC_TSR) Retry Limit exceeded */
+#define EMAC_TSR_TGO (0x1u << 3) /**< \brief (EMAC_TSR) Transmit Go */
+#define EMAC_TSR_BEX (0x1u << 4) /**< \brief (EMAC_TSR) Buffers exhausted mid frame */
+#define EMAC_TSR_COMP (0x1u << 5) /**< \brief (EMAC_TSR) Transmit Complete */
+#define EMAC_TSR_UND (0x1u << 6) /**< \brief (EMAC_TSR) Transmit Underrun */
+/* -------- EMAC_RBQP : (EMAC Offset: 0x18) Receive Buffer Queue Pointer Register -------- */
+#define EMAC_RBQP_ADDR_Pos 2
+#define EMAC_RBQP_ADDR_Msk (0x3fffffffu << EMAC_RBQP_ADDR_Pos) /**< \brief (EMAC_RBQP) Receive buffer queue pointer address */
+#define EMAC_RBQP_ADDR(value) ((EMAC_RBQP_ADDR_Msk & ((value) << EMAC_RBQP_ADDR_Pos)))
+/* -------- EMAC_TBQP : (EMAC Offset: 0x1C) Transmit Buffer Queue Pointer Register -------- */
+#define EMAC_TBQP_ADDR_Pos 2
+#define EMAC_TBQP_ADDR_Msk (0x3fffffffu << EMAC_TBQP_ADDR_Pos) /**< \brief (EMAC_TBQP) Transmit buffer queue pointer address */
+#define EMAC_TBQP_ADDR(value) ((EMAC_TBQP_ADDR_Msk & ((value) << EMAC_TBQP_ADDR_Pos)))
+/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
+#define EMAC_RSR_BNA (0x1u << 0) /**< \brief (EMAC_RSR) Buffer Not Available */
+#define EMAC_RSR_REC (0x1u << 1) /**< \brief (EMAC_RSR) Frame Received */
+#define EMAC_RSR_OVR (0x1u << 2) /**< \brief (EMAC_RSR) Receive Overrun */
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+#define EMAC_ISR_MFD (0x1u << 0) /**< \brief (EMAC_ISR) Management Frame Done */
+#define EMAC_ISR_RCOMP (0x1u << 1) /**< \brief (EMAC_ISR) Receive Complete */
+#define EMAC_ISR_RXUBR (0x1u << 2) /**< \brief (EMAC_ISR) Receive Used Bit Read */
+#define EMAC_ISR_TXUBR (0x1u << 3) /**< \brief (EMAC_ISR) Transmit Used Bit Read */
+#define EMAC_ISR_TUND (0x1u << 4) /**< \brief (EMAC_ISR) Ethernet Transmit Buffer Underrun */
+#define EMAC_ISR_RLEX (0x1u << 5) /**< \brief (EMAC_ISR) Retry Limit Exceeded */
+#define EMAC_ISR_TXERR (0x1u << 6) /**< \brief (EMAC_ISR) Transmit Error */
+#define EMAC_ISR_TCOMP (0x1u << 7) /**< \brief (EMAC_ISR) Transmit Complete */
+#define EMAC_ISR_ROVR (0x1u << 10) /**< \brief (EMAC_ISR) Receive Overrun */
+#define EMAC_ISR_HRESP (0x1u << 11) /**< \brief (EMAC_ISR) Hresp not OK */
+#define EMAC_ISR_PFRE (0x1u << 12) /**< \brief (EMAC_ISR) Pause Frame Received */
+#define EMAC_ISR_PTZ (0x1u << 13) /**< \brief (EMAC_ISR) Pause Time Zero */
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
+#define EMAC_IER_MFD (0x1u << 0) /**< \brief (EMAC_IER) Management Frame sent */
+#define EMAC_IER_RCOMP (0x1u << 1) /**< \brief (EMAC_IER) Receive Complete */
+#define EMAC_IER_RXUBR (0x1u << 2) /**< \brief (EMAC_IER) Receive Used Bit Read */
+#define EMAC_IER_TXUBR (0x1u << 3) /**< \brief (EMAC_IER) Transmit Used Bit Read */
+#define EMAC_IER_TUND (0x1u << 4) /**< \brief (EMAC_IER) Ethernet Transmit Buffer Underrun */
+#define EMAC_IER_RLE (0x1u << 5) /**< \brief (EMAC_IER) Retry Limit Exceeded */
+#define EMAC_IER_TXERR (0x1u << 6) /**< \brief (EMAC_IER) */
+#define EMAC_IER_TCOMP (0x1u << 7) /**< \brief (EMAC_IER) Transmit Complete */
+#define EMAC_IER_ROVR (0x1u << 10) /**< \brief (EMAC_IER) Receive Overrun */
+#define EMAC_IER_HRESP (0x1u << 11) /**< \brief (EMAC_IER) Hresp not OK */
+#define EMAC_IER_PFR (0x1u << 12) /**< \brief (EMAC_IER) Pause Frame Received */
+#define EMAC_IER_PTZ (0x1u << 13) /**< \brief (EMAC_IER) Pause Time Zero */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2C) Interrupt Disable Register -------- */
+#define EMAC_IDR_MFD (0x1u << 0) /**< \brief (EMAC_IDR) Management Frame sent */
+#define EMAC_IDR_RCOMP (0x1u << 1) /**< \brief (EMAC_IDR) Receive Complete */
+#define EMAC_IDR_RXUBR (0x1u << 2) /**< \brief (EMAC_IDR) Receive Used Bit Read */
+#define EMAC_IDR_TXUBR (0x1u << 3) /**< \brief (EMAC_IDR) Transmit Used Bit Read */
+#define EMAC_IDR_TUND (0x1u << 4) /**< \brief (EMAC_IDR) Ethernet Transmit Buffer Underrun */
+#define EMAC_IDR_RLE (0x1u << 5) /**< \brief (EMAC_IDR) Retry Limit Exceeded */
+#define EMAC_IDR_TXERR (0x1u << 6) /**< \brief (EMAC_IDR) */
+#define EMAC_IDR_TCOMP (0x1u << 7) /**< \brief (EMAC_IDR) Transmit Complete */
+#define EMAC_IDR_ROVR (0x1u << 10) /**< \brief (EMAC_IDR) Receive Overrun */
+#define EMAC_IDR_HRESP (0x1u << 11) /**< \brief (EMAC_IDR) Hresp not OK */
+#define EMAC_IDR_PFR (0x1u << 12) /**< \brief (EMAC_IDR) Pause Frame Received */
+#define EMAC_IDR_PTZ (0x1u << 13) /**< \brief (EMAC_IDR) Pause Time Zero */
+/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
+#define EMAC_IMR_MFD (0x1u << 0) /**< \brief (EMAC_IMR) Management Frame sent */
+#define EMAC_IMR_RCOMP (0x1u << 1) /**< \brief (EMAC_IMR) Receive Complete */
+#define EMAC_IMR_RXUBR (0x1u << 2) /**< \brief (EMAC_IMR) Receive Used Bit Read */
+#define EMAC_IMR_TXUBR (0x1u << 3) /**< \brief (EMAC_IMR) Transmit Used Bit Read */
+#define EMAC_IMR_TUND (0x1u << 4) /**< \brief (EMAC_IMR) Ethernet Transmit Buffer Underrun */
+#define EMAC_IMR_RLE (0x1u << 5) /**< \brief (EMAC_IMR) Retry Limit Exceeded */
+#define EMAC_IMR_TXERR (0x1u << 6) /**< \brief (EMAC_IMR) */
+#define EMAC_IMR_TCOMP (0x1u << 7) /**< \brief (EMAC_IMR) Transmit Complete */
+#define EMAC_IMR_ROVR (0x1u << 10) /**< \brief (EMAC_IMR) Receive Overrun */
+#define EMAC_IMR_HRESP (0x1u << 11) /**< \brief (EMAC_IMR) Hresp not OK */
+#define EMAC_IMR_PFR (0x1u << 12) /**< \brief (EMAC_IMR) Pause Frame Received */
+#define EMAC_IMR_PTZ (0x1u << 13) /**< \brief (EMAC_IMR) Pause Time Zero */
+/* -------- EMAC_MAN : (EMAC Offset: 0x34) Phy Maintenance Register -------- */
+#define EMAC_MAN_DATA_Pos 0
+#define EMAC_MAN_DATA_Msk (0xffffu << EMAC_MAN_DATA_Pos) /**< \brief (EMAC_MAN) */
+#define EMAC_MAN_DATA(value) ((EMAC_MAN_DATA_Msk & ((value) << EMAC_MAN_DATA_Pos)))
+#define EMAC_MAN_CODE_Pos 16
+#define EMAC_MAN_CODE_Msk (0x3u << EMAC_MAN_CODE_Pos) /**< \brief (EMAC_MAN) */
+#define EMAC_MAN_CODE(value) ((EMAC_MAN_CODE_Msk & ((value) << EMAC_MAN_CODE_Pos)))
+#define EMAC_MAN_REGA_Pos 18
+#define EMAC_MAN_REGA_Msk (0x1fu << EMAC_MAN_REGA_Pos) /**< \brief (EMAC_MAN) Register Address */
+#define EMAC_MAN_REGA(value) ((EMAC_MAN_REGA_Msk & ((value) << EMAC_MAN_REGA_Pos)))
+#define EMAC_MAN_PHYA_Pos 23
+#define EMAC_MAN_PHYA_Msk (0x1fu << EMAC_MAN_PHYA_Pos) /**< \brief (EMAC_MAN) PHY Address */
+#define EMAC_MAN_PHYA(value) ((EMAC_MAN_PHYA_Msk & ((value) << EMAC_MAN_PHYA_Pos)))
+#define EMAC_MAN_RW_Pos 28
+#define EMAC_MAN_RW_Msk (0x3u << EMAC_MAN_RW_Pos) /**< \brief (EMAC_MAN) Read-write */
+#define EMAC_MAN_RW(value) ((EMAC_MAN_RW_Msk & ((value) << EMAC_MAN_RW_Pos)))
+#define EMAC_MAN_SOF_Pos 30
+#define EMAC_MAN_SOF_Msk (0x3u << EMAC_MAN_SOF_Pos) /**< \brief (EMAC_MAN) Start of frame */
+#define EMAC_MAN_SOF(value) ((EMAC_MAN_SOF_Msk & ((value) << EMAC_MAN_SOF_Pos)))
+/* -------- EMAC_PTR : (EMAC Offset: 0x38) Pause Time Register -------- */
+#define EMAC_PTR_PTIME_Pos 0
+#define EMAC_PTR_PTIME_Msk (0xffffu << EMAC_PTR_PTIME_Pos) /**< \brief (EMAC_PTR) Pause Time */
+#define EMAC_PTR_PTIME(value) ((EMAC_PTR_PTIME_Msk & ((value) << EMAC_PTR_PTIME_Pos)))
+/* -------- EMAC_PFR : (EMAC Offset: 0x3C) Pause Frames Received Register -------- */
+#define EMAC_PFR_FROK_Pos 0
+#define EMAC_PFR_FROK_Msk (0xffffu << EMAC_PFR_FROK_Pos) /**< \brief (EMAC_PFR) Pause Frames received OK */
+#define EMAC_PFR_FROK(value) ((EMAC_PFR_FROK_Msk & ((value) << EMAC_PFR_FROK_Pos)))
+/* -------- EMAC_FTO : (EMAC Offset: 0x40) Frames Transmitted Ok Register -------- */
+#define EMAC_FTO_FTOK_Pos 0
+#define EMAC_FTO_FTOK_Msk (0xffffffu << EMAC_FTO_FTOK_Pos) /**< \brief (EMAC_FTO) Frames Transmitted OK */
+#define EMAC_FTO_FTOK(value) ((EMAC_FTO_FTOK_Msk & ((value) << EMAC_FTO_FTOK_Pos)))
+/* -------- EMAC_SCF : (EMAC Offset: 0x44) Single Collision Frames Register -------- */
+#define EMAC_SCF_SCF_Pos 0
+#define EMAC_SCF_SCF_Msk (0xffffu << EMAC_SCF_SCF_Pos) /**< \brief (EMAC_SCF) Single Collision Frames */
+#define EMAC_SCF_SCF(value) ((EMAC_SCF_SCF_Msk & ((value) << EMAC_SCF_SCF_Pos)))
+/* -------- EMAC_MCF : (EMAC Offset: 0x48) Multiple Collision Frames Register -------- */
+#define EMAC_MCF_MCF_Pos 0
+#define EMAC_MCF_MCF_Msk (0xffffu << EMAC_MCF_MCF_Pos) /**< \brief (EMAC_MCF) Multicollision Frames */
+#define EMAC_MCF_MCF(value) ((EMAC_MCF_MCF_Msk & ((value) << EMAC_MCF_MCF_Pos)))
+/* -------- EMAC_FRO : (EMAC Offset: 0x4C) Frames Received Ok Register -------- */
+#define EMAC_FRO_FROK_Pos 0
+#define EMAC_FRO_FROK_Msk (0xffffffu << EMAC_FRO_FROK_Pos) /**< \brief (EMAC_FRO) Frames Received OK */
+#define EMAC_FRO_FROK(value) ((EMAC_FRO_FROK_Msk & ((value) << EMAC_FRO_FROK_Pos)))
+/* -------- EMAC_FCSE : (EMAC Offset: 0x50) Frame Check Sequence Errors Register -------- */
+#define EMAC_FCSE_FCSE_Pos 0
+#define EMAC_FCSE_FCSE_Msk (0xffu << EMAC_FCSE_FCSE_Pos) /**< \brief (EMAC_FCSE) Frame Check Sequence Errors */
+#define EMAC_FCSE_FCSE(value) ((EMAC_FCSE_FCSE_Msk & ((value) << EMAC_FCSE_FCSE_Pos)))
+/* -------- EMAC_ALE : (EMAC Offset: 0x54) Alignment Errors Register -------- */
+#define EMAC_ALE_ALE_Pos 0
+#define EMAC_ALE_ALE_Msk (0xffu << EMAC_ALE_ALE_Pos) /**< \brief (EMAC_ALE) Alignment Errors */
+#define EMAC_ALE_ALE(value) ((EMAC_ALE_ALE_Msk & ((value) << EMAC_ALE_ALE_Pos)))
+/* -------- EMAC_DTF : (EMAC Offset: 0x58) Deferred Transmission Frames Register -------- */
+#define EMAC_DTF_DTF_Pos 0
+#define EMAC_DTF_DTF_Msk (0xffffu << EMAC_DTF_DTF_Pos) /**< \brief (EMAC_DTF) Deferred Transmission Frames */
+#define EMAC_DTF_DTF(value) ((EMAC_DTF_DTF_Msk & ((value) << EMAC_DTF_DTF_Pos)))
+/* -------- EMAC_LCOL : (EMAC Offset: 0x5C) Late Collisions Register -------- */
+#define EMAC_LCOL_LCOL_Pos 0
+#define EMAC_LCOL_LCOL_Msk (0xffu << EMAC_LCOL_LCOL_Pos) /**< \brief (EMAC_LCOL) Late Collisions */
+#define EMAC_LCOL_LCOL(value) ((EMAC_LCOL_LCOL_Msk & ((value) << EMAC_LCOL_LCOL_Pos)))
+/* -------- EMAC_ECOL : (EMAC Offset: 0x60) Excessive Collisions Register -------- */
+#define EMAC_ECOL_EXCOL_Pos 0
+#define EMAC_ECOL_EXCOL_Msk (0xffu << EMAC_ECOL_EXCOL_Pos) /**< \brief (EMAC_ECOL) Excessive Collisions */
+#define EMAC_ECOL_EXCOL(value) ((EMAC_ECOL_EXCOL_Msk & ((value) << EMAC_ECOL_EXCOL_Pos)))
+/* -------- EMAC_TUND : (EMAC Offset: 0x64) Transmit Underrun Errors Register -------- */
+#define EMAC_TUND_TUND_Pos 0
+#define EMAC_TUND_TUND_Msk (0xffu << EMAC_TUND_TUND_Pos) /**< \brief (EMAC_TUND) Transmit Underruns */
+#define EMAC_TUND_TUND(value) ((EMAC_TUND_TUND_Msk & ((value) << EMAC_TUND_TUND_Pos)))
+/* -------- EMAC_CSE : (EMAC Offset: 0x68) Carrier Sense Errors Register -------- */
+#define EMAC_CSE_CSE_Pos 0
+#define EMAC_CSE_CSE_Msk (0xffu << EMAC_CSE_CSE_Pos) /**< \brief (EMAC_CSE) Carrier Sense Errors */
+#define EMAC_CSE_CSE(value) ((EMAC_CSE_CSE_Msk & ((value) << EMAC_CSE_CSE_Pos)))
+/* -------- EMAC_RRE : (EMAC Offset: 0x6C) Receive Resource Errors Register -------- */
+#define EMAC_RRE_RRE_Pos 0
+#define EMAC_RRE_RRE_Msk (0xffffu << EMAC_RRE_RRE_Pos) /**< \brief (EMAC_RRE) Receive Resource Errors */
+#define EMAC_RRE_RRE(value) ((EMAC_RRE_RRE_Msk & ((value) << EMAC_RRE_RRE_Pos)))
+/* -------- EMAC_ROV : (EMAC Offset: 0x70) Receive Overrun Errors Register -------- */
+#define EMAC_ROV_ROVR_Pos 0
+#define EMAC_ROV_ROVR_Msk (0xffu << EMAC_ROV_ROVR_Pos) /**< \brief (EMAC_ROV) Receive Overrun */
+#define EMAC_ROV_ROVR(value) ((EMAC_ROV_ROVR_Msk & ((value) << EMAC_ROV_ROVR_Pos)))
+/* -------- EMAC_RSE : (EMAC Offset: 0x74) Receive Symbol Errors Register -------- */
+#define EMAC_RSE_RSE_Pos 0
+#define EMAC_RSE_RSE_Msk (0xffu << EMAC_RSE_RSE_Pos) /**< \brief (EMAC_RSE) Receive Symbol Errors */
+#define EMAC_RSE_RSE(value) ((EMAC_RSE_RSE_Msk & ((value) << EMAC_RSE_RSE_Pos)))
+/* -------- EMAC_ELE : (EMAC Offset: 0x78) Excessive Length Errors Register -------- */
+#define EMAC_ELE_EXL_Pos 0
+#define EMAC_ELE_EXL_Msk (0xffu << EMAC_ELE_EXL_Pos) /**< \brief (EMAC_ELE) Excessive Length Errors */
+#define EMAC_ELE_EXL(value) ((EMAC_ELE_EXL_Msk & ((value) << EMAC_ELE_EXL_Pos)))
+/* -------- EMAC_RJA : (EMAC Offset: 0x7C) Receive Jabbers Register -------- */
+#define EMAC_RJA_RJB_Pos 0
+#define EMAC_RJA_RJB_Msk (0xffu << EMAC_RJA_RJB_Pos) /**< \brief (EMAC_RJA) Receive Jabbers */
+#define EMAC_RJA_RJB(value) ((EMAC_RJA_RJB_Msk & ((value) << EMAC_RJA_RJB_Pos)))
+/* -------- EMAC_USF : (EMAC Offset: 0x80) Undersize Frames Register -------- */
+#define EMAC_USF_USF_Pos 0
+#define EMAC_USF_USF_Msk (0xffu << EMAC_USF_USF_Pos) /**< \brief (EMAC_USF) Undersize frames */
+#define EMAC_USF_USF(value) ((EMAC_USF_USF_Msk & ((value) << EMAC_USF_USF_Pos)))
+/* -------- EMAC_STE : (EMAC Offset: 0x84) SQE Test Errors Register -------- */
+#define EMAC_STE_SQER_Pos 0
+#define EMAC_STE_SQER_Msk (0xffu << EMAC_STE_SQER_Pos) /**< \brief (EMAC_STE) SQE test errors */
+#define EMAC_STE_SQER(value) ((EMAC_STE_SQER_Msk & ((value) << EMAC_STE_SQER_Pos)))
+/* -------- EMAC_RLE : (EMAC Offset: 0x88) Received Length Field Mismatch Register -------- */
+#define EMAC_RLE_RLFM_Pos 0
+#define EMAC_RLE_RLFM_Msk (0xffu << EMAC_RLE_RLFM_Pos) /**< \brief (EMAC_RLE) Receive Length Field Mismatch */
+#define EMAC_RLE_RLFM(value) ((EMAC_RLE_RLFM_Msk & ((value) << EMAC_RLE_RLFM_Pos)))
+/* -------- EMAC_HRB : (EMAC Offset: 0x90) Hash Register Bottom [31:0] Register -------- */
+#define EMAC_HRB_ADDR_Pos 0
+#define EMAC_HRB_ADDR_Msk (0xffffffffu << EMAC_HRB_ADDR_Pos) /**< \brief (EMAC_HRB) */
+#define EMAC_HRB_ADDR(value) ((EMAC_HRB_ADDR_Msk & ((value) << EMAC_HRB_ADDR_Pos)))
+/* -------- EMAC_HRT : (EMAC Offset: 0x94) Hash Register Top [63:32] Register -------- */
+#define EMAC_HRT_ADDR_Pos 0
+#define EMAC_HRT_ADDR_Msk (0xffffffffu << EMAC_HRT_ADDR_Pos) /**< \brief (EMAC_HRT) */
+#define EMAC_HRT_ADDR(value) ((EMAC_HRT_ADDR_Msk & ((value) << EMAC_HRT_ADDR_Pos)))
+/* -------- EMAC_SAxB : (EMAC Offset: N/A) Specific Address 1 Bottom Register -------- */
+#define EMAC_SAxB_ADDR_Pos 0
+#define EMAC_SAxB_ADDR_Msk (0xffffffffu << EMAC_SAxB_ADDR_Pos) /**< \brief (EMAC_SAxB) */
+#define EMAC_SAxB_ADDR(value) ((EMAC_SAxB_ADDR_Msk & ((value) << EMAC_SAxB_ADDR_Pos)))
+/* -------- EMAC_SAxT : (EMAC Offset: N/A) Specific Address 1 Top Register -------- */
+#define EMAC_SAxT_ADDR_Pos 0
+#define EMAC_SAxT_ADDR_Msk (0xffffu << EMAC_SAxT_ADDR_Pos) /**< \brief (EMAC_SAxT) */
+#define EMAC_SAxT_ADDR(value) ((EMAC_SAxT_ADDR_Msk & ((value) << EMAC_SAxT_ADDR_Pos)))
+/* -------- EMAC_TID : (EMAC Offset: 0xB8) Type ID Checking Register -------- */
+#define EMAC_TID_TID_Pos 0
+#define EMAC_TID_TID_Msk (0xffffu << EMAC_TID_TID_Pos) /**< \brief (EMAC_TID) Type ID checking */
+#define EMAC_TID_TID(value) ((EMAC_TID_TID_Msk & ((value) << EMAC_TID_TID_Pos)))
+/* -------- EMAC_USRIO : (EMAC Offset: 0xC0) User Input/Output Register -------- */
+#define EMAC_USRIO_RMII (0x1u << 0) /**< \brief (EMAC_USRIO) Reduce MII */
+#define EMAC_USRIO_CLKEN (0x1u << 1) /**< \brief (EMAC_USRIO) Clock Enable */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_GPBR General Purpose Backup Register */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Gpbr hardware registers */
+typedef struct {
+ RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */
+ RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */
+ RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */
+ RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */
+ RwReg SYS_GPBR4; /**< \brief (Gpbr Offset: 0x10) General Purpose Backup Register 4 */
+ RwReg SYS_GPBR5; /**< \brief (Gpbr Offset: 0x14) General Purpose Backup Register 5 */
+ RwReg SYS_GPBR6; /**< \brief (Gpbr Offset: 0x18) General Purpose Backup Register 6 */
+ RwReg SYS_GPBR7; /**< \brief (Gpbr Offset: 0x1C) General Purpose Backup Register 7 */
+} Gpbr;
+#endif /* __ASSEMBLY__ */
+/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */
+#define SYS_GPBR0_GPBR_VALUE0_Pos 0
+#define SYS_GPBR0_GPBR_VALUE0_Msk (0xffffffffu << SYS_GPBR0_GPBR_VALUE0_Pos) /**< \brief (SYS_GPBR0) Value of GPBR x */
+#define SYS_GPBR0_GPBR_VALUE0(value) ((SYS_GPBR0_GPBR_VALUE0_Msk & ((value) << SYS_GPBR0_GPBR_VALUE0_Pos)))
+/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */
+#define SYS_GPBR1_GPBR_VALUE1_Pos 0
+#define SYS_GPBR1_GPBR_VALUE1_Msk (0xffffffffu << SYS_GPBR1_GPBR_VALUE1_Pos) /**< \brief (SYS_GPBR1) Value of GPBR x */
+#define SYS_GPBR1_GPBR_VALUE1(value) ((SYS_GPBR1_GPBR_VALUE1_Msk & ((value) << SYS_GPBR1_GPBR_VALUE1_Pos)))
+/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */
+#define SYS_GPBR2_GPBR_VALUE2_Pos 0
+#define SYS_GPBR2_GPBR_VALUE2_Msk (0xffffffffu << SYS_GPBR2_GPBR_VALUE2_Pos) /**< \brief (SYS_GPBR2) Value of GPBR x */
+#define SYS_GPBR2_GPBR_VALUE2(value) ((SYS_GPBR2_GPBR_VALUE2_Msk & ((value) << SYS_GPBR2_GPBR_VALUE2_Pos)))
+/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */
+#define SYS_GPBR3_GPBR_VALUE3_Pos 0
+#define SYS_GPBR3_GPBR_VALUE3_Msk (0xffffffffu << SYS_GPBR3_GPBR_VALUE3_Pos) /**< \brief (SYS_GPBR3) Value of GPBR x */
+#define SYS_GPBR3_GPBR_VALUE3(value) ((SYS_GPBR3_GPBR_VALUE3_Msk & ((value) << SYS_GPBR3_GPBR_VALUE3_Pos)))
+/* -------- SYS_GPBR4 : (GPBR Offset: 0x10) General Purpose Backup Register 4 -------- */
+#define SYS_GPBR4_GPBR_VALUE4_Pos 0
+#define SYS_GPBR4_GPBR_VALUE4_Msk (0xffffffffu << SYS_GPBR4_GPBR_VALUE4_Pos) /**< \brief (SYS_GPBR4) Value of GPBR x */
+#define SYS_GPBR4_GPBR_VALUE4(value) ((SYS_GPBR4_GPBR_VALUE4_Msk & ((value) << SYS_GPBR4_GPBR_VALUE4_Pos)))
+/* -------- SYS_GPBR5 : (GPBR Offset: 0x14) General Purpose Backup Register 5 -------- */
+#define SYS_GPBR5_GPBR_VALUE5_Pos 0
+#define SYS_GPBR5_GPBR_VALUE5_Msk (0xffffffffu << SYS_GPBR5_GPBR_VALUE5_Pos) /**< \brief (SYS_GPBR5) Value of GPBR x */
+#define SYS_GPBR5_GPBR_VALUE5(value) ((SYS_GPBR5_GPBR_VALUE5_Msk & ((value) << SYS_GPBR5_GPBR_VALUE5_Pos)))
+/* -------- SYS_GPBR6 : (GPBR Offset: 0x18) General Purpose Backup Register 6 -------- */
+#define SYS_GPBR6_GPBR_VALUE6_Pos 0
+#define SYS_GPBR6_GPBR_VALUE6_Msk (0xffffffffu << SYS_GPBR6_GPBR_VALUE6_Pos) /**< \brief (SYS_GPBR6) Value of GPBR x */
+#define SYS_GPBR6_GPBR_VALUE6(value) ((SYS_GPBR6_GPBR_VALUE6_Msk & ((value) << SYS_GPBR6_GPBR_VALUE6_Pos)))
+/* -------- SYS_GPBR7 : (GPBR Offset: 0x1C) General Purpose Backup Register 7 -------- */
+#define SYS_GPBR7_GPBR_VALUE7_Pos 0
+#define SYS_GPBR7_GPBR_VALUE7_Msk (0xffffffffu << SYS_GPBR7_GPBR_VALUE7_Pos) /**< \brief (SYS_GPBR7) Value of GPBR x */
+#define SYS_GPBR7_GPBR_VALUE7(value) ((SYS_GPBR7_GPBR_VALUE7_Msk & ((value) << SYS_GPBR7_GPBR_VALUE7_Pos)))
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_HSMCI High Speed MultiMedia Card Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Hsmci hardware registers */
+typedef struct {
+ WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */
+ RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */
+ RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
+ RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
+ RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */
+ WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */
+ RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */
+ RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
+ RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */
+ RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
+ WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
+ RoReg Reserved1[2];
+ RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */
+ WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
+ WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
+ RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
+ RwReg HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */
+ RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */
+ RoReg Reserved2[35];
+ RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
+ RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
+ RoReg Reserved3[69];
+ RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
+} Hsmci;
+#endif /* __ASSEMBLY__ */
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
+#define HSMCI_MR_CLKDIV_Pos 0
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
+#define HSMCI_MR_PWSDIV_Pos 8
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
+#define HSMCI_MR_BLKLEN_Pos 16
+#define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */
+#define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos)))
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
+#define HSMCI_DTOR_DTOCYC_Pos 0
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
+#define HSMCI_DTOR_DTOMUL_Pos 4
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
+#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
+#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
+#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
+#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
+#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
+#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
+#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
+#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
+#define HSMCI_SDCR_SDCSEL_Pos 0
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
+#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
+#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) SDCARD/SDIO Slot B selected */
+#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCBUS_Pos 6
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
+#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
+#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
+#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
+#define HSMCI_ARGR_ARG_Pos 0
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
+#define HSMCI_CMDR_CMDNB_Pos 0
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
+#define HSMCI_CMDR_RSPTYP_Pos 6
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
+#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
+#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
+#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
+#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
+#define HSMCI_CMDR_SPCMD_Pos 8
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
+#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
+#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
+#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
+#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
+#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
+#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
+#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
+#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
+#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
+#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
+#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
+#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
+#define HSMCI_CMDR_TRCMD_Pos 16
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
+#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
+#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
+#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
+#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
+#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
+#define HSMCI_CMDR_TRTYP_Pos 19
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
+#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
+#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
+#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
+#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
+#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
+#define HSMCI_CMDR_IOSPCMD_Pos 24
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
+#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
+#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
+#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
+#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
+#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
+#define HSMCI_BLKR_BCNT_Pos 0
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
+#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
+#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BLKLEN_Pos 16
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
+#define HSMCI_CSTOR_CSTOCYC_Pos 0
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
+#define HSMCI_CSTOR_CSTOMUL_Pos 4
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
+#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
+#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
+#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
+#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
+#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
+#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
+#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
+#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
+#define HSMCI_RSPR_RSP_Pos 0
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
+#define HSMCI_RDR_DATA_Pos 0
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
+#define HSMCI_TDR_DATA_Pos 0
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
+#define HSMCI_SR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_SR) */
+#define HSMCI_SR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_SR) */
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
+#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */
+#define HSMCI_SR_DMADONE (0x1u << 25) /**< \brief (HSMCI_SR) DMA Transfer done */
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
+#define HSMCI_IER_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IER) */
+#define HSMCI_IER_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IER) */
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
+#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */
+#define HSMCI_IER_DMADONE (0x1u << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
+#define HSMCI_IDR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IDR) */
+#define HSMCI_IDR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IDR) */
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
+#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */
+#define HSMCI_IDR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
+#define HSMCI_IMR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IMR) */
+#define HSMCI_IMR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IMR) */
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
+#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */
+#define HSMCI_IMR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
+/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
+#define HSMCI_DMA_OFFSET_Pos 0
+#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */
+#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos)))
+#define HSMCI_DMA_CHKSIZE (0x1u << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */
+#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */
+#define HSMCI_DMA_CHKSIZE_4 (0x1u << 4) /**< \brief (HSMCI_DMA) 4 data available */
+#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */
+#define HSMCI_DMA_ROPT (0x1u << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
+#define HSMCI_WPMR_WP_KEY_Pos 8
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
+#define HSMCI_WPSR_WP_VS_Pos 0
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
+#define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
+#define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
+#define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
+#define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
+#define HSMCI_WPSR_WP_VSRC_Pos 8
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
+/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
+#define HSMCI_FIFO_DATA_Pos 0
+#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */
+#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Matrix hardware registers */
+typedef struct {
+ RwReg MATRIX_MCFG[6]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+ RoReg Reserved1[10];
+ RwReg MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+ RoReg Reserved2[7];
+ RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+ RoReg Reserved3[1];
+ RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+ RoReg Reserved4[1];
+ RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+ RoReg Reserved5[1];
+ RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+ RoReg Reserved6[1];
+ RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
+ RoReg Reserved7[1];
+ RwReg MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */
+ RoReg Reserved8[1];
+ RwReg MATRIX_PRAS6; /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */
+ RoReg Reserved9[1];
+ RwReg MATRIX_PRAS7; /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */
+ RoReg Reserved10[1];
+ RwReg MATRIX_PRAS8; /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */
+ RoReg Reserved11[1];
+ RoReg Reserved12[14];
+ RwReg MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */
+ RoReg Reserved13[4];
+ RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */
+ RoReg Reserved14[51];
+ RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+ RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* __ASSEMBLY__ */
+/* -------- MATRIX_MCFG[6] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[6]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[9]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+#define MATRIX_PRAS0_M4PR_Pos 16
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
+#define MATRIX_PRAS0_M5PR_Pos 20
+#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) /**< \brief (MATRIX_PRAS0) Master 5 Priority */
+#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+#define MATRIX_PRAS1_M4PR_Pos 16
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
+#define MATRIX_PRAS1_M5PR_Pos 20
+#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) /**< \brief (MATRIX_PRAS1) Master 5 Priority */
+#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+#define MATRIX_PRAS2_M4PR_Pos 16
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
+#define MATRIX_PRAS2_M5PR_Pos 20
+#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) /**< \brief (MATRIX_PRAS2) Master 5 Priority */
+#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+#define MATRIX_PRAS3_M4PR_Pos 16
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
+#define MATRIX_PRAS3_M5PR_Pos 20
+#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) /**< \brief (MATRIX_PRAS3) Master 5 Priority */
+#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos)))
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
+#define MATRIX_PRAS4_M0PR_Pos 0
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
+#define MATRIX_PRAS4_M1PR_Pos 4
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
+#define MATRIX_PRAS4_M2PR_Pos 8
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
+#define MATRIX_PRAS4_M3PR_Pos 12
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
+#define MATRIX_PRAS4_M4PR_Pos 16
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
+#define MATRIX_PRAS4_M5PR_Pos 20
+#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) /**< \brief (MATRIX_PRAS4) Master 5 Priority */
+#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos)))
+/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
+#define MATRIX_PRAS5_M0PR_Pos 0
+#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */
+#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))
+#define MATRIX_PRAS5_M1PR_Pos 4
+#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */
+#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))
+#define MATRIX_PRAS5_M2PR_Pos 8
+#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */
+#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))
+#define MATRIX_PRAS5_M3PR_Pos 12
+#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */
+#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))
+#define MATRIX_PRAS5_M4PR_Pos 16
+#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */
+#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))
+#define MATRIX_PRAS5_M5PR_Pos 20
+#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) /**< \brief (MATRIX_PRAS5) Master 5 Priority */
+#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos)))
+/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
+#define MATRIX_PRAS6_M0PR_Pos 0
+#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */
+#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))
+#define MATRIX_PRAS6_M1PR_Pos 4
+#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */
+#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))
+#define MATRIX_PRAS6_M2PR_Pos 8
+#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */
+#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))
+#define MATRIX_PRAS6_M3PR_Pos 12
+#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */
+#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))
+#define MATRIX_PRAS6_M4PR_Pos 16
+#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */
+#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))
+#define MATRIX_PRAS6_M5PR_Pos 20
+#define MATRIX_PRAS6_M5PR_Msk (0x3u << MATRIX_PRAS6_M5PR_Pos) /**< \brief (MATRIX_PRAS6) Master 5 Priority */
+#define MATRIX_PRAS6_M5PR(value) ((MATRIX_PRAS6_M5PR_Msk & ((value) << MATRIX_PRAS6_M5PR_Pos)))
+/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
+#define MATRIX_PRAS7_M0PR_Pos 0
+#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */
+#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))
+#define MATRIX_PRAS7_M1PR_Pos 4
+#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */
+#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))
+#define MATRIX_PRAS7_M2PR_Pos 8
+#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */
+#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))
+#define MATRIX_PRAS7_M3PR_Pos 12
+#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */
+#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))
+#define MATRIX_PRAS7_M4PR_Pos 16
+#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */
+#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))
+#define MATRIX_PRAS7_M5PR_Pos 20
+#define MATRIX_PRAS7_M5PR_Msk (0x3u << MATRIX_PRAS7_M5PR_Pos) /**< \brief (MATRIX_PRAS7) Master 5 Priority */
+#define MATRIX_PRAS7_M5PR(value) ((MATRIX_PRAS7_M5PR_Msk & ((value) << MATRIX_PRAS7_M5PR_Pos)))
+/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
+#define MATRIX_PRAS8_M0PR_Pos 0
+#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */
+#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))
+#define MATRIX_PRAS8_M1PR_Pos 4
+#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */
+#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))
+#define MATRIX_PRAS8_M2PR_Pos 8
+#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */
+#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))
+#define MATRIX_PRAS8_M3PR_Pos 12
+#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */
+#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))
+#define MATRIX_PRAS8_M4PR_Pos 16
+#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */
+#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))
+#define MATRIX_PRAS8_M5PR_Pos 20
+#define MATRIX_PRAS8_M5PR_Msk (0x3u << MATRIX_PRAS8_M5PR_Pos) /**< \brief (MATRIX_PRAS8) Master 5 Priority */
+#define MATRIX_PRAS8_M5PR(value) ((MATRIX_PRAS8_M5PR_Msk & ((value) << MATRIX_PRAS8_M5PR_Pos)))
+/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
+#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */
+#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */
+#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */
+#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */
+#define MATRIX_MRCR_RCB4_Pos 4
+#define MATRIX_MRCR_RCB4_Msk (0x3u << MATRIX_MRCR_RCB4_Pos) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */
+#define MATRIX_MRCR_RCB4(value) ((MATRIX_MRCR_RCB4_Msk & ((value) << MATRIX_MRCR_RCB4_Pos)))
+#define MATRIX_MRCR_RCB5 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 5 */
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PC0 or ERASE Assignment */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PDC Peripheral DMA Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pdc hardware registers */
+typedef struct {
+ RoReg Reserved1[64];
+ RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */
+ RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */
+ RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */
+ RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */
+ RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */
+ RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */
+ RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */
+ RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */
+ WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */
+ RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */
+} Pdc;
+#endif /* __ASSEMBLY__ */
+/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pio hardware registers */
+typedef struct {
+ WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+ WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+ RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+ RoReg Reserved1[1];
+ WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+ WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+ RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */
+ RoReg Reserved2[1];
+ WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+ WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+ RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+ RoReg Reserved3[1];
+ WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+ WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+ RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+ RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+ WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+ WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+ RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+ RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+ WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+ WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+ RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+ RoReg Reserved4[1];
+ WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+ WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+ RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+ RoReg Reserved5[1];
+ RwReg PIO_ABSR; /**< \brief (Pio Offset: 0x0070) Peripheral AB Select Register */
+ RoReg Reserved6[3];
+ WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */
+ WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */
+ RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */
+ RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+ RoReg Reserved7[4];
+ WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+ WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+ RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+ RoReg Reserved8[1];
+ WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+ WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
+ RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+ RoReg Reserved9[1];
+ WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+ WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+ RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+ RoReg Reserved10[1];
+ WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
+ WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
+ RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+ RoReg Reserved11[1];
+ RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */
+ RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
+ RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
+} Pio;
+#endif /* __ASSEMBLY__ */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
+/* -------- PIO_ABSR : (PIO Offset: 0x0070) Peripheral AB Select Register -------- */
+#define PIO_ABSR_P0 (0x1u << 0) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P1 (0x1u << 1) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P2 (0x1u << 2) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P3 (0x1u << 3) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P4 (0x1u << 4) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P5 (0x1u << 5) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P6 (0x1u << 6) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P7 (0x1u << 7) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P8 (0x1u << 8) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P9 (0x1u << 9) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P10 (0x1u << 10) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P11 (0x1u << 11) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P12 (0x1u << 12) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P13 (0x1u << 13) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P14 (0x1u << 14) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P15 (0x1u << 15) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P16 (0x1u << 16) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P17 (0x1u << 17) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P18 (0x1u << 18) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P19 (0x1u << 19) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P20 (0x1u << 20) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P21 (0x1u << 21) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P22 (0x1u << 22) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P23 (0x1u << 23) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P24 (0x1u << 24) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P25 (0x1u << 25) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P26 (0x1u << 26) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P27 (0x1u << 27) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P28 (0x1u << 28) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P29 (0x1u << 29) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P30 (0x1u << 30) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P31 (0x1u << 31) /**< \brief (PIO_ABSR) Peripheral A Select. */
+/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */
+#define PIO_SCIFSR_P0 (0x1u << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P1 (0x1u << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P2 (0x1u << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P3 (0x1u << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P4 (0x1u << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P5 (0x1u << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P6 (0x1u << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P7 (0x1u << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P8 (0x1u << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P9 (0x1u << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P10 (0x1u << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P11 (0x1u << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P12 (0x1u << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P13 (0x1u << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P14 (0x1u << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P15 (0x1u << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P16 (0x1u << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P17 (0x1u << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P18 (0x1u << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P19 (0x1u << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P20 (0x1u << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P21 (0x1u << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P22 (0x1u << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P23 (0x1u << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P24 (0x1u << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P25 (0x1u << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P26 (0x1u << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P27 (0x1u << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P28 (0x1u << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P29 (0x1u << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P30 (0x1u << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P31 (0x1u << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */
+#define PIO_DIFSR_P0 (0x1u << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P1 (0x1u << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P2 (0x1u << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P3 (0x1u << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P4 (0x1u << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P5 (0x1u << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P6 (0x1u << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P7 (0x1u << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P8 (0x1u << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P9 (0x1u << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P10 (0x1u << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P11 (0x1u << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P12 (0x1u << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P13 (0x1u << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P14 (0x1u << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P15 (0x1u << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P16 (0x1u << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P17 (0x1u << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P18 (0x1u << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P19 (0x1u << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P20 (0x1u << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P21 (0x1u << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P22 (0x1u << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P23 (0x1u << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P24 (0x1u << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P25 (0x1u << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P26 (0x1u << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P27 (0x1u << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P28 (0x1u << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P29 (0x1u << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P30 (0x1u << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P31 (0x1u << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */
+#define PIO_IFDGSR_P0 (0x1u << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P1 (0x1u << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P2 (0x1u << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P3 (0x1u << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P4 (0x1u << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P5 (0x1u << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P6 (0x1u << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P7 (0x1u << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P8 (0x1u << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P9 (0x1u << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P10 (0x1u << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P11 (0x1u << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P12 (0x1u << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P13 (0x1u << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P14 (0x1u << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P15 (0x1u << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P16 (0x1u << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P17 (0x1u << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P18 (0x1u << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P19 (0x1u << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P20 (0x1u << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P21 (0x1u << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P22 (0x1u << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P23 (0x1u << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P24 (0x1u << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P25 (0x1u << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P26 (0x1u << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P27 (0x1u << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P28 (0x1u << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P29 (0x1u << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P30 (0x1u << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P31 (0x1u << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PMC Power Management Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pmc hardware registers */
+typedef struct {
+ WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+ WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+ RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+ RoReg Reserved1[1];
+ WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+ WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+ RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+ RwReg CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */
+ RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+ RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+ RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+ RoReg Reserved2[1];
+ RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+ RoReg Reserved3[1];
+ RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
+ RoReg Reserved4[1];
+ RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+ RoReg Reserved5[5];
+ WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+ WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+ RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */
+ RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+ RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+ RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+ WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+ RoReg Reserved6[26];
+ RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+ RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+ RoReg Reserved7[5];
+ WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
+ WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
+ RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
+ RwReg PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */
+} Pmc;
+#endif /* __ASSEMBLY__ */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_UOTGCK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB OTG Clock (48 MHz, USB_48M) for UTMI */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_UOTGCK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB OTG Clock (48 MHz, USB_48M) for UTMI */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_UOTGCK (0x1u << 5) /**< \brief (PMC_SCSR) USB OTG Clock (48 MHz, USB_48M) for UTMI */
+#define PMC_SCSR_UOTGCK_DISABLE (0x0u << 5) /**< \brief (PMC_SCSR) USB_48M is disabled in normal operation mode. */
+#define PMC_SCSR_UOTGCK_ENABLE (0x1u << 5) /**< \brief (PMC_SCSR) Enable USB_48M (to use if SPDCONF =1). */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
+#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
+#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
+#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
+/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
+#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */
+#define CKGR_UCKR_UPLLCOUNT_Pos 20
+#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */
+#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define CKGR_MOR_MOSCRCF_4MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define CKGR_MOR_MOSCRCF_8MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define CKGR_MOR_MOSCRCF_12MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_STUCKTO1 (0x1u << 29) /**< \brief (CKGR_PLLAR) */
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLL/2 Clock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_UPLLDIV (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divider */
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
+#define PMC_USB_USBDIV_Pos 8
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL/2 Clock is selected */
+#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLL A Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLL A Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLL A Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLL A Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
+#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */
+#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */
+#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */
+#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */
+#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */
+#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */
+#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */
+#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */
+#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */
+#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
+#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */
+#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */
+#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */
+#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */
+#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */
+#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */
+#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */
+#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */
+#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */
+#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
+#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */
+#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */
+#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */
+#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */
+#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */
+#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */
+#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */
+#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */
+#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */
+#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */
+/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */
+#define PMC_PCR_PID_Pos 0
+#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */
+#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
+#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */
+#define PMC_PCR_DIV_Pos 16
+#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */
+#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */
+#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */
+#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */
+#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+ RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+ RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+ RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
+ RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
+ RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
+ RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
+ RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
+ RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
+} PwmCh_num;
+/** \brief PwmCmp hardware registers */
+typedef struct {
+ RwReg PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
+ RwReg PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
+ RwReg PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
+ RwReg PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
+} PwmCmp;
+/** \brief Pwm hardware registers */
+#define PWMCMP_NUMBER 8
+#define PWMCH_NUM_NUMBER 8
+typedef struct {
+ RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
+ WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+ WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+ RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+ WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
+ WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
+ RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
+ RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
+ RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
+ RoReg Reserved1[1];
+ RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
+ RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
+ WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
+ WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
+ WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
+ RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
+ RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
+ RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
+ RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
+ WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
+ WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
+ WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
+ WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
+ RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
+ RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
+ WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
+ RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
+ RwReg PWM_FPE1; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register 1 */
+ RwReg PWM_FPE2; /**< \brief (Pwm Offset: 0x70) PWM Fault Protection Enable Register 2 */
+ RoReg Reserved2[2];
+ RwReg PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
+ RoReg Reserved3[11];
+ RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
+ RoReg Reserved4[12];
+ WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
+ RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
+ RoReg Reserved5[5];
+ RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */
+ RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */
+ RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
+ RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
+ RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */
+ RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */
+ RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
+ RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
+ WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
+ RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
+ RoReg Reserved6[2];
+ PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
+ RoReg Reserved7[20];
+ PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 7 */
+} Pwm;
+#endif /* __ASSEMBLY__ */
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
+#define PWM_CLK_DIVA_Pos 0
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
+#define PWM_CLK_PREA_Pos 8
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
+#define PWM_CLK_DIVB_Pos 16
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
+#define PWM_CLK_PREB_Pos 24
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID4 (0x1u << 4) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID5 (0x1u << 5) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID6 (0x1u << 6) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID7 (0x1u << 7) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID4 (0x1u << 4) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID5 (0x1u << 5) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID6 (0x1u << 6) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID7 (0x1u << 7) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID4 (0x1u << 4) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID5 (0x1u << 5) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID6 (0x1u << 6) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID7 (0x1u << 7) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
+#define PWM_IER1_CHID4 (0x1u << 4) /**< \brief (PWM_IER1) Counter Event on Channel 4 Interrupt Enable */
+#define PWM_IER1_CHID5 (0x1u << 5) /**< \brief (PWM_IER1) Counter Event on Channel 5 Interrupt Enable */
+#define PWM_IER1_CHID6 (0x1u << 6) /**< \brief (PWM_IER1) Counter Event on Channel 6 Interrupt Enable */
+#define PWM_IER1_CHID7 (0x1u << 7) /**< \brief (PWM_IER1) Counter Event on Channel 7 Interrupt Enable */
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
+#define PWM_IER1_FCHID4 (0x1u << 20) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 4 Interrupt Enable */
+#define PWM_IER1_FCHID5 (0x1u << 21) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 5 Interrupt Enable */
+#define PWM_IER1_FCHID6 (0x1u << 22) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 6 Interrupt Enable */
+#define PWM_IER1_FCHID7 (0x1u << 23) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 7 Interrupt Enable */
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
+#define PWM_IDR1_CHID4 (0x1u << 4) /**< \brief (PWM_IDR1) Counter Event on Channel 4 Interrupt Disable */
+#define PWM_IDR1_CHID5 (0x1u << 5) /**< \brief (PWM_IDR1) Counter Event on Channel 5 Interrupt Disable */
+#define PWM_IDR1_CHID6 (0x1u << 6) /**< \brief (PWM_IDR1) Counter Event on Channel 6 Interrupt Disable */
+#define PWM_IDR1_CHID7 (0x1u << 7) /**< \brief (PWM_IDR1) Counter Event on Channel 7 Interrupt Disable */
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
+#define PWM_IDR1_FCHID4 (0x1u << 20) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 4 Interrupt Disable */
+#define PWM_IDR1_FCHID5 (0x1u << 21) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 5 Interrupt Disable */
+#define PWM_IDR1_FCHID6 (0x1u << 22) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 6 Interrupt Disable */
+#define PWM_IDR1_FCHID7 (0x1u << 23) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 7 Interrupt Disable */
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
+#define PWM_IMR1_CHID4 (0x1u << 4) /**< \brief (PWM_IMR1) Counter Event on Channel 4 Interrupt Mask */
+#define PWM_IMR1_CHID5 (0x1u << 5) /**< \brief (PWM_IMR1) Counter Event on Channel 5 Interrupt Mask */
+#define PWM_IMR1_CHID6 (0x1u << 6) /**< \brief (PWM_IMR1) Counter Event on Channel 6 Interrupt Mask */
+#define PWM_IMR1_CHID7 (0x1u << 7) /**< \brief (PWM_IMR1) Counter Event on Channel 7 Interrupt Mask */
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
+#define PWM_IMR1_FCHID4 (0x1u << 20) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 4 Interrupt Mask */
+#define PWM_IMR1_FCHID5 (0x1u << 21) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 5 Interrupt Mask */
+#define PWM_IMR1_FCHID6 (0x1u << 22) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 6 Interrupt Mask */
+#define PWM_IMR1_FCHID7 (0x1u << 23) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 7 Interrupt Mask */
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
+#define PWM_ISR1_CHID4 (0x1u << 4) /**< \brief (PWM_ISR1) Counter Event on Channel 4 */
+#define PWM_ISR1_CHID5 (0x1u << 5) /**< \brief (PWM_ISR1) Counter Event on Channel 5 */
+#define PWM_ISR1_CHID6 (0x1u << 6) /**< \brief (PWM_ISR1) Counter Event on Channel 6 */
+#define PWM_ISR1_CHID7 (0x1u << 7) /**< \brief (PWM_ISR1) Counter Event on Channel 7 */
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
+#define PWM_ISR1_FCHID4 (0x1u << 20) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 4 */
+#define PWM_ISR1_FCHID5 (0x1u << 21) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 5 */
+#define PWM_ISR1_FCHID6 (0x1u << 22) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 6 */
+#define PWM_ISR1_FCHID7 (0x1u << 23) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 7 */
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
+#define PWM_SCM_SYNC4 (0x1u << 4) /**< \brief (PWM_SCM) Synchronous Channel 4 */
+#define PWM_SCM_SYNC5 (0x1u << 5) /**< \brief (PWM_SCM) Synchronous Channel 5 */
+#define PWM_SCM_SYNC6 (0x1u << 6) /**< \brief (PWM_SCM) Synchronous Channel 6 */
+#define PWM_SCM_SYNC7 (0x1u << 7) /**< \brief (PWM_SCM) Synchronous Channel 7 */
+#define PWM_SCM_UPDM_Pos 16
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
+#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
+#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
+#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
+#define PWM_SCM_PTRCS_Pos 21
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
+#define PWM_SCUP_UPR_Pos 0
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
+#define PWM_SCUP_UPRCNT_Pos 4
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
+#define PWM_SCUPUPD_UPRUPD_Pos 0
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
+#define PWM_OOV_OOVH4 (0x1u << 4) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 4 */
+#define PWM_OOV_OOVH5 (0x1u << 5) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 5 */
+#define PWM_OOV_OOVH6 (0x1u << 6) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 6 */
+#define PWM_OOV_OOVH7 (0x1u << 7) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 7 */
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
+#define PWM_OOV_OOVL4 (0x1u << 20) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 4 */
+#define PWM_OOV_OOVL5 (0x1u << 21) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 5 */
+#define PWM_OOV_OOVL6 (0x1u << 22) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 6 */
+#define PWM_OOV_OOVL7 (0x1u << 23) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 7 */
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
+#define PWM_OS_OSH4 (0x1u << 4) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 4 */
+#define PWM_OS_OSH5 (0x1u << 5) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 5 */
+#define PWM_OS_OSH6 (0x1u << 6) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 6 */
+#define PWM_OS_OSH7 (0x1u << 7) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 7 */
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
+#define PWM_OS_OSL4 (0x1u << 20) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 4 */
+#define PWM_OS_OSL5 (0x1u << 21) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 5 */
+#define PWM_OS_OSL6 (0x1u << 22) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 6 */
+#define PWM_OS_OSL7 (0x1u << 23) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 7 */
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSS_OSSH4 (0x1u << 4) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 4 */
+#define PWM_OSS_OSSH5 (0x1u << 5) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 5 */
+#define PWM_OSS_OSSH6 (0x1u << 6) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 6 */
+#define PWM_OSS_OSSH7 (0x1u << 7) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 7 */
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
+#define PWM_OSS_OSSL4 (0x1u << 20) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 4 */
+#define PWM_OSS_OSSL5 (0x1u << 21) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 5 */
+#define PWM_OSS_OSSL6 (0x1u << 22) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 6 */
+#define PWM_OSS_OSSL7 (0x1u << 23) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 7 */
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSC_OSCH4 (0x1u << 4) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 4 */
+#define PWM_OSC_OSCH5 (0x1u << 5) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 5 */
+#define PWM_OSC_OSCH6 (0x1u << 6) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 6 */
+#define PWM_OSC_OSCH7 (0x1u << 7) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 7 */
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
+#define PWM_OSC_OSCL4 (0x1u << 20) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 4 */
+#define PWM_OSC_OSCL5 (0x1u << 21) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 5 */
+#define PWM_OSC_OSCL6 (0x1u << 22) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 6 */
+#define PWM_OSC_OSCL7 (0x1u << 23) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 7 */
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSSUPD_OSSUPH4 (0x1u << 4) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 4 */
+#define PWM_OSSUPD_OSSUPH5 (0x1u << 5) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 5 */
+#define PWM_OSSUPD_OSSUPH6 (0x1u << 6) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 6 */
+#define PWM_OSSUPD_OSSUPH7 (0x1u << 7) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 7 */
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
+#define PWM_OSSUPD_OSSUPL4 (0x1u << 20) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 4 */
+#define PWM_OSSUPD_OSSUPL5 (0x1u << 21) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 5 */
+#define PWM_OSSUPD_OSSUPL6 (0x1u << 22) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 6 */
+#define PWM_OSSUPD_OSSUPL7 (0x1u << 23) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 7 */
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSCUPD_OSCUPH4 (0x1u << 4) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 4 */
+#define PWM_OSCUPD_OSCUPH5 (0x1u << 5) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 5 */
+#define PWM_OSCUPD_OSCUPH6 (0x1u << 6) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 6 */
+#define PWM_OSCUPD_OSCUPH7 (0x1u << 7) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 7 */
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
+#define PWM_OSCUPD_OSCUPL4 (0x1u << 20) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 4 */
+#define PWM_OSCUPD_OSCUPL5 (0x1u << 21) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 5 */
+#define PWM_OSCUPD_OSCUPDL6 (0x1u << 22) /**< \brief (PWM_OSCUPD) */
+#define PWM_OSCUPD_OSCUPL7 (0x1u << 23) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 7 */
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
+#define PWM_FMR_FPOL_Pos 0
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
+#define PWM_FMR_FMOD_Pos 8
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
+#define PWM_FMR_FFIL_Pos 16
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
+#define PWM_FSR_FIV_Pos 0
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */
+#define PWM_FSR_FS_Pos 8
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
+#define PWM_FCR_FCLR_Pos 0
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
+#define PWM_FPV_FPVH4 (0x1u << 4) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 4 */
+#define PWM_FPV_FPVH5 (0x1u << 5) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 5 */
+#define PWM_FPV_FPVH6 (0x1u << 6) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 6 */
+#define PWM_FPV_FPVH7 (0x1u << 7) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 7 */
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
+#define PWM_FPV_FPVL4 (0x1u << 20) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 4 */
+#define PWM_FPV_FPVL5 (0x1u << 21) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 5 */
+#define PWM_FPV_FPVL6 (0x1u << 22) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 6 */
+#define PWM_FPV_FPVL7 (0x1u << 23) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 7 */
+/* -------- PWM_FPE1 : (PWM Offset: 0x6C) PWM Fault Protection Enable Register 1 -------- */
+#define PWM_FPE1_FPE0_Pos 0
+#define PWM_FPE1_FPE0_Msk (0xffu << PWM_FPE1_FPE0_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE0(value) ((PWM_FPE1_FPE0_Msk & ((value) << PWM_FPE1_FPE0_Pos)))
+#define PWM_FPE1_FPE1_Pos 8
+#define PWM_FPE1_FPE1_Msk (0xffu << PWM_FPE1_FPE1_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE1(value) ((PWM_FPE1_FPE1_Msk & ((value) << PWM_FPE1_FPE1_Pos)))
+#define PWM_FPE1_FPE2_Pos 16
+#define PWM_FPE1_FPE2_Msk (0xffu << PWM_FPE1_FPE2_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE2(value) ((PWM_FPE1_FPE2_Msk & ((value) << PWM_FPE1_FPE2_Pos)))
+#define PWM_FPE1_FPE3_Pos 24
+#define PWM_FPE1_FPE3_Msk (0xffu << PWM_FPE1_FPE3_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE3(value) ((PWM_FPE1_FPE3_Msk & ((value) << PWM_FPE1_FPE3_Pos)))
+/* -------- PWM_FPE2 : (PWM Offset: 0x70) PWM Fault Protection Enable Register 2 -------- */
+#define PWM_FPE2_FPE4_Pos 0
+#define PWM_FPE2_FPE4_Msk (0xffu << PWM_FPE2_FPE4_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 4 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE4(value) ((PWM_FPE2_FPE4_Msk & ((value) << PWM_FPE2_FPE4_Pos)))
+#define PWM_FPE2_FPE5_Pos 8
+#define PWM_FPE2_FPE5_Msk (0xffu << PWM_FPE2_FPE5_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 5 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE5(value) ((PWM_FPE2_FPE5_Msk & ((value) << PWM_FPE2_FPE5_Pos)))
+#define PWM_FPE2_FPE6_Pos 16
+#define PWM_FPE2_FPE6_Msk (0xffu << PWM_FPE2_FPE6_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 6 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE6(value) ((PWM_FPE2_FPE6_Msk & ((value) << PWM_FPE2_FPE6_Pos)))
+#define PWM_FPE2_FPE7_Pos 24
+#define PWM_FPE2_FPE7_Msk (0xffu << PWM_FPE2_FPE7_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 7 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE7(value) ((PWM_FPE2_FPE7_Msk & ((value) << PWM_FPE2_FPE7_Pos)))
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN2 (0x1u << 2) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN3 (0x1u << 3) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN2 (0x1u << 18) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN3 (0x1u << 19) /**< \brief (PWM_SMMR) DOWN Count */
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
+#define PWM_WPCR_WPCMD_Pos 0
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
+#define PWM_WPCR_WPKEY_Pos 8
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPVSRC_Pos 16
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
+/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */
+#define PWM_RPR_RXPTR_Pos 0
+#define PWM_RPR_RXPTR_Msk (0xffffffffu << PWM_RPR_RXPTR_Pos) /**< \brief (PWM_RPR) Receive Pointer Register */
+#define PWM_RPR_RXPTR(value) ((PWM_RPR_RXPTR_Msk & ((value) << PWM_RPR_RXPTR_Pos)))
+/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */
+#define PWM_RCR_RXCTR_Pos 0
+#define PWM_RCR_RXCTR_Msk (0xffffu << PWM_RCR_RXCTR_Pos) /**< \brief (PWM_RCR) Receive Counter Register */
+#define PWM_RCR_RXCTR(value) ((PWM_RCR_RXCTR_Msk & ((value) << PWM_RCR_RXCTR_Pos)))
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
+#define PWM_TPR_TXPTR_Pos 0
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
+#define PWM_TCR_TXCTR_Pos 0
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
+/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */
+#define PWM_RNPR_RXNPTR_Pos 0
+#define PWM_RNPR_RXNPTR_Msk (0xffffffffu << PWM_RNPR_RXNPTR_Pos) /**< \brief (PWM_RNPR) Receive Next Pointer */
+#define PWM_RNPR_RXNPTR(value) ((PWM_RNPR_RXNPTR_Msk & ((value) << PWM_RNPR_RXNPTR_Pos)))
+/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */
+#define PWM_RNCR_RXNCTR_Pos 0
+#define PWM_RNCR_RXNCTR_Msk (0xffffu << PWM_RNCR_RXNCTR_Pos) /**< \brief (PWM_RNCR) Receive Next Counter */
+#define PWM_RNCR_RXNCTR(value) ((PWM_RNCR_RXNCTR_Msk & ((value) << PWM_RNCR_RXNCTR_Pos)))
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
+#define PWM_TNPR_TXNPTR_Pos 0
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
+#define PWM_TNCR_TXNCTR_Pos 0
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
+#define PWM_CMPV_CV_Pos 0
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
+#define PWM_CMPVUPD_CVUPD_Pos 0
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
+#define PWM_CMPM_CTR_Pos 4
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
+#define PWM_CMPM_CPR_Pos 8
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
+#define PWM_CMPM_CPRCNT_Pos 12
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
+#define PWM_CMPM_CUPR_Pos 16
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
+#define PWM_CMPM_CUPRCNT_Pos 20
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
+#define PWM_CMPMUPD_CTRUPD_Pos 4
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
+#define PWM_CMPMUPD_CPRUPD_Pos 8
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
+#define PWM_CMPMUPD_CUPRUPD_Pos 16
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
+#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
+#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
+#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
+#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
+#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
+#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
+#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
+#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
+#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
+#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
+#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
+#define PWM_CDTYUPD_CDTYUPD_Pos 0
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
+#define PWM_CPRDUPD_CPRDUPD_Pos 0
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
+#define PWM_DT_DTH_Pos 0
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
+#define PWM_DT_DTL_Pos 16
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
+#define PWM_DTUPD_DTHUPD_Pos 0
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
+#define PWM_DTUPD_DTLUPD_Pos 16
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_RSTC Reset Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rstc hardware registers */
+typedef struct {
+ WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+ RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+ RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* __ASSEMBLY__ */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_RTC Real-time Clock */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rtc hardware registers */
+typedef struct {
+ RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */
+ RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */
+ RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */
+ RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+ RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+ RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+ RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */
+ WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+ WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+ WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+ RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+ RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+ RoReg Reserved1[45];
+ RwReg RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */
+} Rtc;
+#endif /* __ASSEMBLY__ */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */
+#define RTC_WPMR_WPKEY_Pos 8
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) */
+#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_RTT Real-time Timer */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rtt hardware registers */
+typedef struct {
+ RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+ RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+ RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+ RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* __ASSEMBLY__ */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR SDRAM Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SDRAMC SDRAM Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Sdramc hardware registers */
+typedef struct {
+ RwReg SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */
+ RwReg SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */
+ RwReg SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */
+ RoReg Reserved1[1];
+ RwReg SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */
+ WoReg SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */
+ WoReg SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */
+ RoReg SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */
+ RoReg SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */
+ RwReg SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */
+ RwReg SDRAMC_CR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */
+ RwReg SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register 1 */
+} Sdramc;
+#endif /* __ASSEMBLY__ */
+/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */
+#define SDRAMC_MR_MODE_Pos 0
+#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */
+#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */
+#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
+#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
+#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
+#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */
+#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */
+#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */
+/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */
+#define SDRAMC_TR_COUNT_Pos 0
+#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */
+#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)))
+/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */
+#define SDRAMC_CR_NC_Pos 0
+#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */
+#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */
+#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */
+#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */
+#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */
+#define SDRAMC_CR_NR_Pos 2
+#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */
+#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */
+#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */
+#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */
+#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */
+#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */
+#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */
+#define SDRAMC_CR_CAS_Pos 5
+#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */
+#define SDRAMC_CR_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */
+#define SDRAMC_CR_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */
+#define SDRAMC_CR_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */
+#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */
+#define SDRAMC_CR_TWR_Pos 8
+#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */
+#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)))
+#define SDRAMC_CR_TRC_TRFC_Pos 12
+#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */
+#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)))
+#define SDRAMC_CR_TRP_Pos 16
+#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */
+#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)))
+#define SDRAMC_CR_TRCD_Pos 20
+#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */
+#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)))
+#define SDRAMC_CR_TRAS_Pos 24
+#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */
+#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)))
+#define SDRAMC_CR_TXSR_Pos 28
+#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */
+#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)))
+/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */
+#define SDRAMC_LPR_LPCB_Pos 0
+#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */
+#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */
+#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */
+#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */
+#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */
+#define SDRAMC_LPR_PASR_Pos 4
+#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */
+#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)))
+#define SDRAMC_LPR_TCSR_Pos 8
+#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */
+#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)))
+#define SDRAMC_LPR_DS_Pos 10
+#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */
+#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)))
+#define SDRAMC_LPR_TIMEOUT_Pos 12
+#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to define when low-power mode is enable */
+#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. */
+#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */
+#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */
+/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */
+#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */
+/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */
+#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */
+/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */
+#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */
+/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */
+#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status */
+/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */
+#define SDRAMC_MDR_MD_Pos 0
+#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */
+#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */
+#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */
+/* -------- SDRAMC_CR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */
+#define SDRAMC_CR1_NC_Pos 0
+#define SDRAMC_CR1_NC_Msk (0x3u << SDRAMC_CR1_NC_Pos) /**< \brief (SDRAMC_CR1) Number of Column Bits */
+#define SDRAMC_CR1_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR1) 8 column bits */
+#define SDRAMC_CR1_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR1) 9 column bits */
+#define SDRAMC_CR1_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR1) 10 column bits */
+#define SDRAMC_CR1_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR1) 11 column bits */
+#define SDRAMC_CR1_NR_Pos 2
+#define SDRAMC_CR1_NR_Msk (0x3u << SDRAMC_CR1_NR_Pos) /**< \brief (SDRAMC_CR1) Number of Row Bits */
+#define SDRAMC_CR1_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR1) 11 row bits */
+#define SDRAMC_CR1_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR1) 12 row bits */
+#define SDRAMC_CR1_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR1) 13 row bits */
+#define SDRAMC_CR1_NB (0x1u << 4) /**< \brief (SDRAMC_CR1) Number of Banks */
+#define SDRAMC_CR1_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR1) 2 banks */
+#define SDRAMC_CR1_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR1) 4 banks */
+#define SDRAMC_CR1_CAS_Pos 5
+#define SDRAMC_CR1_CAS_Msk (0x3u << SDRAMC_CR1_CAS_Pos) /**< \brief (SDRAMC_CR1) CAS Latency */
+#define SDRAMC_CR1_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR1) 1 cycle CAS latency */
+#define SDRAMC_CR1_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR1) 2 cycle CAS latency */
+#define SDRAMC_CR1_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR1) 3 cycle CAS latency */
+#define SDRAMC_CR1_DBW (0x1u << 7) /**< \brief (SDRAMC_CR1) Data Bus Width */
+#define SDRAMC_CR1_TWR_Pos 8
+#define SDRAMC_CR1_TWR_Msk (0xfu << SDRAMC_CR1_TWR_Pos) /**< \brief (SDRAMC_CR1) Write Recovery Delay */
+#define SDRAMC_CR1_TWR(value) ((SDRAMC_CR1_TWR_Msk & ((value) << SDRAMC_CR1_TWR_Pos)))
+#define SDRAMC_CR1_TRC_TRFC_Pos 12
+#define SDRAMC_CR1_TRC_TRFC_Msk (0xfu << SDRAMC_CR1_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR1) Row Cycle Delay and Row Refresh Cycle */
+#define SDRAMC_CR1_TRC_TRFC(value) ((SDRAMC_CR1_TRC_TRFC_Msk & ((value) << SDRAMC_CR1_TRC_TRFC_Pos)))
+#define SDRAMC_CR1_TRP_Pos 16
+#define SDRAMC_CR1_TRP_Msk (0xfu << SDRAMC_CR1_TRP_Pos) /**< \brief (SDRAMC_CR1) Row Precharge Delay */
+#define SDRAMC_CR1_TRP(value) ((SDRAMC_CR1_TRP_Msk & ((value) << SDRAMC_CR1_TRP_Pos)))
+#define SDRAMC_CR1_TRCD_Pos 20
+#define SDRAMC_CR1_TRCD_Msk (0xfu << SDRAMC_CR1_TRCD_Pos) /**< \brief (SDRAMC_CR1) Row to Column Delay */
+#define SDRAMC_CR1_TRCD(value) ((SDRAMC_CR1_TRCD_Msk & ((value) << SDRAMC_CR1_TRCD_Pos)))
+#define SDRAMC_CR1_TRAS_Pos 24
+#define SDRAMC_CR1_TRAS_Msk (0xfu << SDRAMC_CR1_TRAS_Pos) /**< \brief (SDRAMC_CR1) Active to Precharge Delay */
+#define SDRAMC_CR1_TRAS(value) ((SDRAMC_CR1_TRAS_Msk & ((value) << SDRAMC_CR1_TRAS_Pos)))
+#define SDRAMC_CR1_TXSR_Pos 28
+#define SDRAMC_CR1_TXSR_Msk (0xfu << SDRAMC_CR1_TXSR_Pos) /**< \brief (SDRAMC_CR1) Exit Self Refresh to Active Delay */
+#define SDRAMC_CR1_TXSR(value) ((SDRAMC_CR1_TXSR_Msk & ((value) << SDRAMC_CR1_TXSR_Pos)))
+/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register 1 -------- */
+#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Static Memory Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SMC Static Memory Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief SmcCs_number hardware registers */
+typedef struct {
+ RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
+ RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
+ RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
+ RwReg SMC_TIMINGS; /**< \brief (SmcCs_number Offset: 0xC) SMC Timings Register */
+ RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0x10) SMC Mode Register */
+} SmcCs_number;
+/** \brief Smc hardware registers */
+#define SMCCS_NUMBER_NUMBER 8
+typedef struct {
+ RwReg SMC_CFG; /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */
+ WoReg SMC_CTRL; /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */
+ RoReg SMC_SR; /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */
+ WoReg SMC_IER; /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */
+ WoReg SMC_IDR; /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */
+ RoReg SMC_IMR; /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */
+ RwReg SMC_ADDR; /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */
+ RwReg SMC_BANK; /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */
+ WoReg SMC_ECC_CTRL; /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */
+ RwReg SMC_ECC_MD; /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */
+ RoReg SMC_ECC_SR1; /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */
+ RoReg SMC_ECC_PR0; /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */
+ RoReg SMC_ECC_PR1; /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */
+ RoReg SMC_ECC_SR2; /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */
+ RoReg SMC_ECC_PR2; /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */
+ RoReg SMC_ECC_PR3; /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */
+ RoReg SMC_ECC_PR4; /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */
+ RoReg SMC_ECC_PR5; /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */
+ RoReg SMC_ECC_PR6; /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */
+ RoReg SMC_ECC_PR7; /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */
+ RoReg SMC_ECC_PR8; /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */
+ RoReg SMC_ECC_PR9; /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */
+ RoReg SMC_ECC_PR10; /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */
+ RoReg SMC_ECC_PR11; /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */
+ RoReg SMC_ECC_PR12; /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */
+ RoReg SMC_ECC_PR13; /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */
+ RoReg SMC_ECC_PR14; /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */
+ RoReg SMC_ECC_PR15; /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */
+ SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 7 */
+ RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x110) SMC OCMS Register */
+ WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x114) SMC OCMS KEY1 Register */
+ WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x118) SMC OCMS KEY2 Register */
+ RoReg Reserved1[50];
+ WoReg SMC_WPCR; /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */
+ RoReg SMC_WPSR; /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */
+} Smc;
+#endif /* __ASSEMBLY__ */
+/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */
+#define SMC_CFG_PAGESIZE_Pos 0
+#define SMC_CFG_PAGESIZE_Msk (0x3u << SMC_CFG_PAGESIZE_Pos) /**< \brief (SMC_CFG) */
+#define SMC_CFG_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_CFG) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define SMC_CFG_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_CFG) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define SMC_CFG_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_CFG) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define SMC_CFG_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_CFG) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_CFG_WSPARE (0x1u << 8) /**< \brief (SMC_CFG) Write Spare Area */
+#define SMC_CFG_RSPARE (0x1u << 9) /**< \brief (SMC_CFG) Read Spare Area */
+#define SMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */
+#define SMC_CFG_RBEDGE (0x1u << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */
+#define SMC_CFG_DTOCYC_Pos 16
+#define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) /**< \brief (SMC_CFG) Data Timeout Cycle Number */
+#define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos)))
+#define SMC_CFG_DTOMUL_Pos 20
+#define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) /**< \brief (SMC_CFG) Data Timeout Multiplier */
+#define SMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (SMC_CFG) DTOCYC */
+#define SMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (SMC_CFG) DTOCYC x 16 */
+#define SMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (SMC_CFG) DTOCYC x 128 */
+#define SMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (SMC_CFG) DTOCYC x 256 */
+#define SMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (SMC_CFG) DTOCYC x 1024 */
+
+
+#define SMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (SMC_CFG) DTOCYC x 4096 */
+#define SMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (SMC_CFG) DTOCYC x 65536 */
+#define SMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (SMC_CFG) DTOCYC x 1048576 */
+/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */
+#define SMC_CTRL_NFCEN (0x1u << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */
+#define SMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */
+/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */
+#define SMC_SR_SMCSTS (0x1u << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */
+#define SMC_SR_RB_RISE (0x1u << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */
+#define SMC_SR_RB_FALL (0x1u << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */
+#define SMC_SR_NFCBUSY (0x1u << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */
+#define SMC_SR_NFCWR (0x1u << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */
+#define SMC_SR_NFCSID_Pos 12
+#define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */
+#define SMC_SR_XFRDONE (0x1u << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */
+#define SMC_SR_CMDDONE (0x1u << 17) /**< \brief (SMC_SR) Command Done */
+#define SMC_SR_DTOE (0x1u << 20) /**< \brief (SMC_SR) Data Timeout Error */
+#define SMC_SR_UNDEF (0x1u << 21) /**< \brief (SMC_SR) Undefined Area Error */
+#define SMC_SR_AWB (0x1u << 22) /**< \brief (SMC_SR) Accessing While Busy */
+#define SMC_SR_NFCASE (0x1u << 23) /**< \brief (SMC_SR) NFC Access Size Error */
+#define SMC_SR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */
+/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */
+#define SMC_IER_RB_RISE (0x1u << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */
+#define SMC_IER_RB_FALL (0x1u << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */
+#define SMC_IER_XFRDONE (0x1u << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */
+#define SMC_IER_CMDDONE (0x1u << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */
+#define SMC_IER_DTOE (0x1u << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */
+#define SMC_IER_UNDEF (0x1u << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */
+#define SMC_IER_AWB (0x1u << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */
+#define SMC_IER_NFCASE (0x1u << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */
+#define SMC_IER_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */
+/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */
+#define SMC_IDR_RB_RISE (0x1u << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */
+#define SMC_IDR_RB_FALL (0x1u << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */
+#define SMC_IDR_XFRDONE (0x1u << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */
+#define SMC_IDR_CMDDONE (0x1u << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */
+#define SMC_IDR_DTOE (0x1u << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */
+#define SMC_IDR_UNDEF (0x1u << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */
+#define SMC_IDR_AWB (0x1u << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */
+#define SMC_IDR_NFCASE (0x1u << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */
+#define SMC_IDR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */
+/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */
+#define SMC_IMR_RB_RISE (0x1u << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */
+#define SMC_IMR_RB_FALL (0x1u << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */
+#define SMC_IMR_XFRDONE (0x1u << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */
+#define SMC_IMR_CMDDONE (0x1u << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */
+#define SMC_IMR_DTOE (0x1u << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */
+#define SMC_IMR_UNDEF (0x1u << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */
+#define SMC_IMR_AWB (0x1u << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */
+#define SMC_IMR_NFCASE (0x1u << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */
+#define SMC_IMR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */
+/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */
+#define SMC_ADDR_ADDR_CYCLE0_Pos 0
+#define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */
+#define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos)))
+/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */
+#define SMC_BANK_BANK_Pos 0
+#define SMC_BANK_BANK_Msk (0x7u << SMC_BANK_BANK_Pos) /**< \brief (SMC_BANK) Bank Identifier */
+#define SMC_BANK_BANK(value) ((SMC_BANK_BANK_Msk & ((value) << SMC_BANK_BANK_Pos)))
+/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */
+#define SMC_ECC_CTRL_RST (0x1u << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */
+#define SMC_ECC_CTRL_SWRST (0x1u << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */
+/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */
+#define SMC_ECC_MD_ECC_PAGESIZE_Pos 0
+#define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) /**< \brief (SMC_ECC_MD) ECC Page Size */
+#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_ECC_MD) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_ECC_MD) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_ECC_MD) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_ECC_MD) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_ECC_MD_TYPCORREC_Pos 4
+#define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) /**< \brief (SMC_ECC_MD) Type of Correction */
+#define SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash) */
+#define SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+#define SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */
+#define SMC_ECC_SR1_RECERR0 (0x1u << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */
+#define SMC_ECC_SR1_ECCERR0_Pos 1
+#define SMC_ECC_SR1_ECCERR0_Msk (0x3u << SMC_ECC_SR1_ECCERR0_Pos) /**< \brief (SMC_ECC_SR1) ECC Error */
+#define SMC_ECC_SR1_RECERR1 (0x1u << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_ECCERR1 (0x1u << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_MULERR1 (0x1u << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_RECERR2 (0x1u << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_ECCERR2 (0x1u << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_MULERR2 (0x1u << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_RECERR3 (0x1u << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_ECCERR3 (0x1u << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_MULERR3 (0x1u << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_RECERR4 (0x1u << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_ECCERR4_Pos 17
+#define SMC_ECC_SR1_ECCERR4_Msk (0x3u << SMC_ECC_SR1_ECCERR4_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_RECERR5 (0x1u << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_ECCERR5_Pos 21
+#define SMC_ECC_SR1_ECCERR5_Msk (0x3u << SMC_ECC_SR1_ECCERR5_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_RECERR6 (0x1u << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_ECCERR6_Pos 25
+#define SMC_ECC_SR1_ECCERR6_Msk (0x3u << SMC_ECC_SR1_ECCERR6_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_RECERR7 (0x1u << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+#define SMC_ECC_SR1_ECCERR7_Pos 29
+#define SMC_ECC_SR1_ECCERR7_Msk (0x3u << SMC_ECC_SR1_ECCERR7_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */
+#define SMC_ECC_PR0_BITADDR_Pos 0
+#define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) /**< \brief (SMC_ECC_PR0) Bit Address */
+#define SMC_ECC_PR0_WORDADDR_Pos 4
+#define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) /**< \brief (SMC_ECC_PR0) Word Address */
+#define SMC_ECC_PR0_BITADDR_W9BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W9BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Msk (0x1ffu << SMC_ECC_PR0_WORDADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_Pos 12
+#define SMC_ECC_PR0_NPARITY_Msk (0xfffu << SMC_ECC_PR0_NPARITY_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+#define SMC_ECC_PR0_BITADDR_W8BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W8BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR0_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR0_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR0_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */
+#define SMC_ECC_PR1_NPARITY_Pos 0
+#define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_BITADDR_Pos 0
+#define SMC_ECC_PR1_BITADDR_Msk (0x7u << SMC_ECC_PR1_BITADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_WORDADDR_Pos 3
+#define SMC_ECC_PR1_WORDADDR_Msk (0x1ffu << SMC_ECC_PR1_WORDADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W9BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W9BIT_Msk (0xfffu << SMC_ECC_PR1_NPARITY_W9BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR1_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR1_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */
+#define SMC_ECC_SR2_RECERR8 (0x1u << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_ECCERR8_Pos 1
+#define SMC_ECC_SR2_ECCERR8_Msk (0x3u << SMC_ECC_SR2_ECCERR8_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_RECERR9 (0x1u << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_ECCERR9 (0x1u << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_MULERR9 (0x1u << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_RECERR10 (0x1u << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_ECCERR10 (0x1u << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_MULERR10 (0x1u << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_RECERR11 (0x1u << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_ECCERR11 (0x1u << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_MULERR11 (0x1u << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_RECERR12 (0x1u << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_ECCERR12_Pos 17
+#define SMC_ECC_SR2_ECCERR12_Msk (0x3u << SMC_ECC_SR2_ECCERR12_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_RECERR13 (0x1u << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_ECCERR13_Pos 21
+#define SMC_ECC_SR2_ECCERR13_Msk (0x3u << SMC_ECC_SR2_ECCERR13_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_RECERR14 (0x1u << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_ECCERR14_Pos 25
+#define SMC_ECC_SR2_ECCERR14_Msk (0x3u << SMC_ECC_SR2_ECCERR14_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_RECERR15 (0x1u << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */
+#define SMC_ECC_SR2_ECCERR15_Pos 29
+#define SMC_ECC_SR2_ECCERR15_Msk (0x3u << SMC_ECC_SR2_ECCERR15_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */
+/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */
+#define SMC_ECC_PR2_BITADDR_Pos 0
+#define SMC_ECC_PR2_BITADDR_Msk (0x7u << SMC_ECC_PR2_BITADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_WORDADDR_Pos 3
+#define SMC_ECC_PR2_WORDADDR_Msk (0x1ffu << SMC_ECC_PR2_WORDADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_Pos 12
+#define SMC_ECC_PR2_NPARITY_Msk (0xfffu << SMC_ECC_PR2_NPARITY_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR2_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR2_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR2_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */
+#define SMC_ECC_PR3_BITADDR_Pos 0
+#define SMC_ECC_PR3_BITADDR_Msk (0x7u << SMC_ECC_PR3_BITADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_WORDADDR_Pos 3
+#define SMC_ECC_PR3_WORDADDR_Msk (0x1ffu << SMC_ECC_PR3_WORDADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_Pos 12
+#define SMC_ECC_PR3_NPARITY_Msk (0xfffu << SMC_ECC_PR3_NPARITY_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR3_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR3_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR3_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */
+#define SMC_ECC_PR4_BITADDR_Pos 0
+#define SMC_ECC_PR4_BITADDR_Msk (0x7u << SMC_ECC_PR4_BITADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_WORDADDR_Pos 3
+#define SMC_ECC_PR4_WORDADDR_Msk (0x1ffu << SMC_ECC_PR4_WORDADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_Pos 12
+#define SMC_ECC_PR4_NPARITY_Msk (0xfffu << SMC_ECC_PR4_NPARITY_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR4_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR4_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR4_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */
+#define SMC_ECC_PR5_BITADDR_Pos 0
+#define SMC_ECC_PR5_BITADDR_Msk (0x7u << SMC_ECC_PR5_BITADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_WORDADDR_Pos 3
+#define SMC_ECC_PR5_WORDADDR_Msk (0x1ffu << SMC_ECC_PR5_WORDADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_Pos 12
+#define SMC_ECC_PR5_NPARITY_Msk (0xfffu << SMC_ECC_PR5_NPARITY_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR5_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR5_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR5_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */
+#define SMC_ECC_PR6_BITADDR_Pos 0
+#define SMC_ECC_PR6_BITADDR_Msk (0x7u << SMC_ECC_PR6_BITADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_WORDADDR_Pos 3
+#define SMC_ECC_PR6_WORDADDR_Msk (0x1ffu << SMC_ECC_PR6_WORDADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_Pos 12
+#define SMC_ECC_PR6_NPARITY_Msk (0xfffu << SMC_ECC_PR6_NPARITY_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR6_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR6_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR6_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */
+#define SMC_ECC_PR7_BITADDR_Pos 0
+#define SMC_ECC_PR7_BITADDR_Msk (0x7u << SMC_ECC_PR7_BITADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_WORDADDR_Pos 3
+#define SMC_ECC_PR7_WORDADDR_Msk (0x1ffu << SMC_ECC_PR7_WORDADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_Pos 12
+#define SMC_ECC_PR7_NPARITY_Msk (0xfffu << SMC_ECC_PR7_NPARITY_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR7_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR7_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR7_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */
+#define SMC_ECC_PR8_BITADDR_Pos 0
+#define SMC_ECC_PR8_BITADDR_Msk (0x7u << SMC_ECC_PR8_BITADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_WORDADDR_Pos 3
+#define SMC_ECC_PR8_WORDADDR_Msk (0xffu << SMC_ECC_PR8_WORDADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_NPARITY_Pos 12
+#define SMC_ECC_PR8_NPARITY_Msk (0x7ffu << SMC_ECC_PR8_NPARITY_Pos) /**< \brief (SMC_ECC_PR8) Parity N */
+/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */
+#define SMC_ECC_PR9_BITADDR_Pos 0
+#define SMC_ECC_PR9_BITADDR_Msk (0x7u << SMC_ECC_PR9_BITADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_WORDADDR_Pos 3
+#define SMC_ECC_PR9_WORDADDR_Msk (0xffu << SMC_ECC_PR9_WORDADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_NPARITY_Pos 12
+#define SMC_ECC_PR9_NPARITY_Msk (0x7ffu << SMC_ECC_PR9_NPARITY_Pos) /**< \brief (SMC_ECC_PR9) Parity N */
+/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */
+#define SMC_ECC_PR10_BITADDR_Pos 0
+#define SMC_ECC_PR10_BITADDR_Msk (0x7u << SMC_ECC_PR10_BITADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_WORDADDR_Pos 3
+#define SMC_ECC_PR10_WORDADDR_Msk (0xffu << SMC_ECC_PR10_WORDADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_NPARITY_Pos 12
+#define SMC_ECC_PR10_NPARITY_Msk (0x7ffu << SMC_ECC_PR10_NPARITY_Pos) /**< \brief (SMC_ECC_PR10) Parity N */
+/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */
+#define SMC_ECC_PR11_BITADDR_Pos 0
+#define SMC_ECC_PR11_BITADDR_Msk (0x7u << SMC_ECC_PR11_BITADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_WORDADDR_Pos 3
+#define SMC_ECC_PR11_WORDADDR_Msk (0xffu << SMC_ECC_PR11_WORDADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_NPARITY_Pos 12
+#define SMC_ECC_PR11_NPARITY_Msk (0x7ffu << SMC_ECC_PR11_NPARITY_Pos) /**< \brief (SMC_ECC_PR11) Parity N */
+/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */
+#define SMC_ECC_PR12_BITADDR_Pos 0
+#define SMC_ECC_PR12_BITADDR_Msk (0x7u << SMC_ECC_PR12_BITADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_WORDADDR_Pos 3
+#define SMC_ECC_PR12_WORDADDR_Msk (0xffu << SMC_ECC_PR12_WORDADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_NPARITY_Pos 12
+#define SMC_ECC_PR12_NPARITY_Msk (0x7ffu << SMC_ECC_PR12_NPARITY_Pos) /**< \brief (SMC_ECC_PR12) Parity N */
+/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */
+#define SMC_ECC_PR13_BITADDR_Pos 0
+#define SMC_ECC_PR13_BITADDR_Msk (0x7u << SMC_ECC_PR13_BITADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_WORDADDR_Pos 3
+#define SMC_ECC_PR13_WORDADDR_Msk (0xffu << SMC_ECC_PR13_WORDADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_NPARITY_Pos 12
+#define SMC_ECC_PR13_NPARITY_Msk (0x7ffu << SMC_ECC_PR13_NPARITY_Pos) /**< \brief (SMC_ECC_PR13) Parity N */
+/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */
+#define SMC_ECC_PR14_BITADDR_Pos 0
+#define SMC_ECC_PR14_BITADDR_Msk (0x7u << SMC_ECC_PR14_BITADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_WORDADDR_Pos 3
+#define SMC_ECC_PR14_WORDADDR_Msk (0xffu << SMC_ECC_PR14_WORDADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_NPARITY_Pos 12
+#define SMC_ECC_PR14_NPARITY_Msk (0x7ffu << SMC_ECC_PR14_NPARITY_Pos) /**< \brief (SMC_ECC_PR14) Parity N */
+/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */
+#define SMC_ECC_PR15_BITADDR_Pos 0
+#define SMC_ECC_PR15_BITADDR_Msk (0x7u << SMC_ECC_PR15_BITADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_WORDADDR_Pos 3
+#define SMC_ECC_PR15_WORDADDR_Msk (0xffu << SMC_ECC_PR15_WORDADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_NPARITY_Pos 12
+#define SMC_ECC_PR15_NPARITY_Msk (0x7ffu << SMC_ECC_PR15_NPARITY_Pos) /**< \brief (SMC_ECC_PR15) Parity N */
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
+#define SMC_SETUP_NWE_SETUP_Pos 0
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Write Access */
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
+#define SMC_SETUP_NRD_SETUP_Pos 16
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Read Access */
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
+#define SMC_PULSE_NWE_PULSE_Pos 0
+#define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
+#define SMC_PULSE_NRD_PULSE_Pos 16
+#define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
+#define SMC_CYCLE_NWE_CYCLE_Pos 0
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
+#define SMC_CYCLE_NRD_CYCLE_Pos 16
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
+/* -------- SMC_TIMINGS : (SMC Offset: N/A) SMC Timings Register -------- */
+#define SMC_TIMINGS_TCLR_Pos 0
+#define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) /**< \brief (SMC_TIMINGS) CLE to REN Low Delay */
+#define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos)))
+#define SMC_TIMINGS_TADL_Pos 4
+#define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) /**< \brief (SMC_TIMINGS) ALE to Data Start */
+#define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos)))
+#define SMC_TIMINGS_TAR_Pos 8
+#define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) /**< \brief (SMC_TIMINGS) ALE to REN Low Delay */
+#define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos)))
+#define SMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (SMC_TIMINGS) Off Chip Memory Scrambling Enable */
+#define SMC_TIMINGS_TRR_Pos 16
+#define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) /**< \brief (SMC_TIMINGS) Ready to REN Low Delay */
+#define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos)))
+#define SMC_TIMINGS_TWB_Pos 24
+#define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) /**< \brief (SMC_TIMINGS) WEN High to REN to Busy */
+#define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos)))
+#define SMC_TIMINGS_RBNSEL_Pos 28
+#define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) /**< \brief (SMC_TIMINGS) Ready/Busy Line Selection */
+#define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos)))
+#define SMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (SMC_TIMINGS) NAND Flash Selection */
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */
+#define SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NCS signal. */
+#define SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NRD signal. */
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */
+#define SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (SMC_MODE) The Write operation is controller by the NCS signal. */
+#define SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (SMC_MODE) The Write operation is controlled by the NWE signal. */
+#define SMC_MODE_EXNW_MODE_Pos 4
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
+#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
+#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
+#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
+#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */
+#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */
+#define SMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
+#define SMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
+#define SMC_MODE_TDF_CYCLES_Pos 16
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
+/* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS Register -------- */
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
+#define SMC_OCMS_SRSE (0x1u << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */
+/* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC OCMS KEY1 Register -------- */
+#define SMC_KEY1_KEY1_Pos 0
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
+/* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC OCMS KEY2 Register -------- */
+#define SMC_KEY2_KEY2_Pos 0
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
+/* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */
+#define SMC_WPCR_WP_EN (0x1u << 0) /**< \brief (SMC_WPCR) Write Protection Enable */
+#define SMC_WPCR_WP_KEY_Pos 8
+#define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) /**< \brief (SMC_WPCR) Write Protection KEY password */
+#define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos)))
+/* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */
+#define SMC_WPSR_WP_VS_Pos 0
+#define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Status */
+#define SMC_WPSR_WP_VSRC_Pos 8
+#define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */
+/* -------- NFCADDR_CMD : NFC Address Command -------- */
+#define NFCADDR_CMD_CMD1 (0xFFu << 2) /* Command Register Value for Cycle 1 */
+#define NFCADDR_CMD_CMD2 (0xFFu << 10) /* Command Register Value for Cycle 2 */
+#define NFCADDR_CMD_VCMD2 (0x1u << 18) /* Valid Cycle 2 Command */
+#define NFCADDR_CMD_ACYCLE (0x7u << 19) /* Number of Address required for the current command */
+#define NFCADDR_CMD_ACYCLE_NONE (0x0u << 19) /* No address cycle */
+#define NFCADDR_CMD_ACYCLE_ONE (0x1u << 19) /* One address cycle */
+#define NFCADDR_CMD_ACYCLE_TWO (0x2u << 19) /* Two address cycles */
+#define NFCADDR_CMD_ACYCLE_THREE (0x3u << 19) /* Three address cycles */
+#define NFCADDR_CMD_ACYCLE_FOUR (0x4u << 19) /* Four address cycles */
+#define NFCADDR_CMD_ACYCLE_FIVE (0x5u << 19) /* Five address cycles */
+#define NFCADDR_CMD_CSID (0x7u << 22) /* Chip Select Identifier */
+#define NFCADDR_CMD_CSID_0 (0x0u << 22) /* CS0 */
+#define NFCADDR_CMD_CSID_1 (0x1u << 22) /* CS1 */
+#define NFCADDR_CMD_CSID_2 (0x2u << 22) /* CS2 */
+#define NFCADDR_CMD_CSID_3 (0x3u << 22) /* CS3 */
+#define NFCADDR_CMD_CSID_4 (0x4u << 22) /* CS4 */
+#define NFCADDR_CMD_CSID_5 (0x5u << 22) /* CS5 */
+#define NFCADDR_CMD_CSID_6 (0x6u << 22) /* CS6 */
+#define NFCADDR_CMD_CSID_7 (0x7u << 22) /* CS7 */
+#define NFCADDR_CMD_NFCEN (0x1u << 25) /* NFC Enable */
+#define NFCADDR_CMD_NFCWR (0x1u << 26) /* NFC Write Enable */
+#define NFCADDR_CMD_NFCCMD (0x1u << 27) /* NFC Command Enable */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SPI Serial Peripheral Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Spi hardware registers */
+typedef struct {
+ WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */
+ RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */
+ RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */
+ WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+ RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */
+ WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+ WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+ RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+ RoReg Reserved1[4];
+ RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */
+ RoReg Reserved2[41];
+ RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+ RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+} Spi;
+#endif /* __ASSEMBLY__ */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_SPIWPEN (0x1u << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */
+#define SPI_WPMR_SPIWPKEY_Pos 8
+#define SPI_WPMR_SPIWPKEY_Msk (0xffffffu << SPI_WPMR_SPIWPKEY_Pos) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */
+#define SPI_WPMR_SPIWPKEY(value) ((SPI_WPMR_SPIWPKEY_Msk & ((value) << SPI_WPMR_SPIWPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_SPIWPVS_Pos 0
+#define SPI_WPSR_SPIWPVS_Msk (0x7u << SPI_WPSR_SPIWPVS_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */
+#define SPI_WPSR_SPIWPVSRC_Pos 8
+#define SPI_WPSR_SPIWPVSRC_Msk (0xffu << SPI_WPSR_SPIWPVSRC_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SSC Synchronous Serial Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Ssc hardware registers */
+typedef struct {
+ WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */
+ RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
+ RoReg Reserved1[2];
+ RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
+ RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
+ RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
+ RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
+ RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
+ WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
+ RoReg Reserved2[2];
+ RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
+ RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
+ RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
+ RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
+ RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */
+ WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
+ WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
+ RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
+ RoReg Reserved3[37];
+ RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
+ RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
+} Ssc;
+#endif /* __ASSEMBLY__ */
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
+#define SSC_CMR_DIV_Pos 0
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
+#define SSC_RCMR_CKS_Pos 0
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
+#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
+#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
+#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
+#define SSC_RCMR_CKO_Pos 2
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
+#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
+#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
+#define SSC_RCMR_CKG_Pos 6
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
+#define SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
+#define SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_START_Pos 8
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
+#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
+#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
+#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
+#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
+#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
+#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
+#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
+#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
+#define SSC_RCMR_STTDLY_Pos 16
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
+#define SSC_RCMR_PERIOD_Pos 24
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
+#define SSC_RFMR_DATLEN_Pos 0
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
+#define SSC_RFMR_DATNB_Pos 8
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
+#define SSC_RFMR_FSLEN_Pos 16
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
+#define SSC_RFMR_FSOS_Pos 20
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
+#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
+#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
+#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
+#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
+#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
+#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
+#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
+#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
+#define SSC_RFMR_FSLEN_EXT_Pos 28
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
+#define SSC_TCMR_CKS_Pos 0
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
+#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
+#define SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
+#define SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
+#define SSC_TCMR_CKO_Pos 2
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
+#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
+#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
+#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
+#define SSC_TCMR_CKG_Pos 6
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
+#define SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
+#define SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
+#define SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
+#define SSC_TCMR_START_Pos 8
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
+#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
+#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
+#define SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
+#define SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
+#define SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
+#define SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
+#define SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
+#define SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
+#define SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
+#define SSC_TCMR_STTDLY_Pos 16
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
+#define SSC_TCMR_PERIOD_Pos 24
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
+#define SSC_TFMR_DATLEN_Pos 0
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
+#define SSC_TFMR_DATNB_Pos 8
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
+#define SSC_TFMR_FSLEN_Pos 16
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
+#define SSC_TFMR_FSOS_Pos 20
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
+#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
+#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
+#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
+#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
+#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
+#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
+#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
+#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
+#define SSC_TFMR_FSLEN_EXT_Pos 28
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
+#define SSC_RHR_RDAT_Pos 0
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
+#define SSC_THR_TDAT_Pos 0
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
+#define SSC_RSHR_RSDAT_Pos 0
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
+#define SSC_TSHR_TSDAT_Pos 0
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
+#define SSC_RC0R_CP0_Pos 0
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
+#define SSC_RC1R_CP1_Pos 0
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
+#define SSC_WPMR_WPKEY_Pos 8
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
+#define SSC_WPSR_WPVSRC_Pos 8
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SUPC Supply Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Supc hardware registers */
+typedef struct {
+ WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+ RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+ RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+ RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+ RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+ RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* __ASSEMBLY__ */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_VDDIORDYONREG (0x1u << 14) /**< \brief (SUPC_MR) */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_FWUPEN (0x1u << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */
+#define SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */
+#define SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_FWUPDBC_Pos 8
+#define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer Period */
+#define SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */
+#define SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */
+#define SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */
+#define SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */
+#define SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
+#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
+#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
+#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
+#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
+#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
+#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
+#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
+#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
+#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
+#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
+#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
+#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
+#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
+#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
+#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
+#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_FWUPS (0x1u << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */
+#define SUPC_SR_FWUPS_NO (0x0u << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_FWUPS_PRESENT (0x1u << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */
+#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_FWUPIS (0x1u << 12) /**< \brief (SUPC_SR) FWUP Input Status */
+#define SUPC_SR_FWUPIS_LOW (0x0u << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */
+#define SUPC_SR_FWUPIS_HIGH (0x1u << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_TC Timer Counter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief TcChannel hardware registers */
+typedef struct {
+ RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+ RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+ RwReg TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
+ RoReg Reserved1[1];
+ RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */
+ RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */
+ RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */
+ RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */
+ RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */
+ RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+ RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+ RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+ RoReg Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+ TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+ WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */
+ RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+ WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+ WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+ RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+ RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+ RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
+ RoReg Reserved1[2];
+ RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
+} Tc;
+#endif /* __ASSEMBLY__ */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Selection */
+#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Selection */
+#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
+#define TC_WPMR_WPKEY_Pos 8
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR True Random Number Generator */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_TRNG True Random Number Generator */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Trng hardware registers */
+typedef struct {
+ WoReg TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */
+ RoReg Reserved1[3];
+ WoReg TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */
+ WoReg TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */
+ RoReg TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */
+ RoReg TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */
+ RoReg Reserved2[12];
+ RoReg TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */
+} Trng;
+#endif /* __ASSEMBLY__ */
+/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */
+#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */
+#define TRNG_CR_KEY_Pos 8
+#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */
+#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)))
+/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */
+#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */
+/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */
+#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */
+/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */
+#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */
+/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */
+#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */
+/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */
+#define TRNG_ODATA_ODATA_Pos 0
+#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_TWI Two-wire Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Twi hardware registers */
+typedef struct {
+ WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */
+ RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */
+ RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+ RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+ RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+ RoReg Reserved1[3];
+ RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */
+ WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+ WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+ RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+ RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+ WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+ RoReg Reserved2[50];
+ RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+ RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+ RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+ RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+ RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+ RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+ RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+ RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+ WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+ RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* __ASSEMBLY__ */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Uart hardware registers */
+typedef struct {
+ WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */
+ RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */
+ WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+ WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+ RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+ RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */
+ RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+ WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+ RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+ RoReg Reserved1[55];
+ RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+ RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+ RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+ RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+ RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+ RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+ RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+ RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+ WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+ RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* __ASSEMBLY__ */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR USB On-The-Go Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_UOTGHS USB On-The-Go Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief UotghsDevdma hardware registers */
+typedef struct {
+ RwReg UOTGHS_DEVDMANXTDSC; /**< \brief (UotghsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */
+ RwReg UOTGHS_DEVDMAADDRESS; /**< \brief (UotghsDevdma Offset: 0x4) Device DMA Channel Address Register */
+ RwReg UOTGHS_DEVDMACONTROL; /**< \brief (UotghsDevdma Offset: 0x8) Device DMA Channel Control Register */
+ RwReg UOTGHS_DEVDMASTATUS; /**< \brief (UotghsDevdma Offset: 0xC) Device DMA Channel Status Register */
+} UotghsDevdma;
+/** \brief UotghsHstdma hardware registers */
+typedef struct {
+ RwReg UOTGHS_HSTDMANXTDSC; /**< \brief (UotghsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */
+ RwReg UOTGHS_HSTDMAADDRESS; /**< \brief (UotghsHstdma Offset: 0x4) Host DMA Channel Address Register */
+ RwReg UOTGHS_HSTDMACONTROL; /**< \brief (UotghsHstdma Offset: 0x8) Host DMA Channel Control Register */
+ RwReg UOTGHS_HSTDMASTATUS; /**< \brief (UotghsHstdma Offset: 0xC) Host DMA Channel Status Register */
+} UotghsHstdma;
+/** \brief Uotghs hardware registers */
+#define UOTGHSDEVDMA_NUMBER 7
+#define UOTGHSHSTDMA_NUMBER 7
+typedef struct {
+ RwReg UOTGHS_DEVCTRL; /**< \brief (Uotghs Offset: 0x0000) Device General Control Register */
+ RoReg UOTGHS_DEVISR; /**< \brief (Uotghs Offset: 0x0004) Device Global Interrupt Status Register */
+ WoReg UOTGHS_DEVICR; /**< \brief (Uotghs Offset: 0x0008) Device Global Interrupt Clear Register */
+ WoReg UOTGHS_DEVIFR; /**< \brief (Uotghs Offset: 0x000C) Device Global Interrupt Set Register */
+ RoReg UOTGHS_DEVIMR; /**< \brief (Uotghs Offset: 0x0010) Device Global Interrupt Mask Register */
+ WoReg UOTGHS_DEVIDR; /**< \brief (Uotghs Offset: 0x0014) Device Global Interrupt Disable Register */
+ WoReg UOTGHS_DEVIER; /**< \brief (Uotghs Offset: 0x0018) Device Global Interrupt Enable Register */
+ RwReg UOTGHS_DEVEPT; /**< \brief (Uotghs Offset: 0x001C) Device Endpoint Register */
+ RoReg UOTGHS_DEVFNUM; /**< \brief (Uotghs Offset: 0x0020) Device Frame Number Register */
+ RoReg Reserved1[55];
+ RwReg UOTGHS_DEVEPTCFG[10]; /**< \brief (Uotghs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */
+ RoReg Reserved2[2];
+ RoReg UOTGHS_DEVEPTISR[10]; /**< \brief (Uotghs Offset: 0x130) Device Endpoint Status Register (n = 0) */
+ RoReg Reserved3[2];
+ WoReg UOTGHS_DEVEPTICR[10]; /**< \brief (Uotghs Offset: 0x160) Device Endpoint Clear Register (n = 0) */
+ RoReg Reserved4[2];
+ WoReg UOTGHS_DEVEPTIFR[10]; /**< \brief (Uotghs Offset: 0x190) Device Endpoint Set Register (n = 0) */
+ RoReg Reserved5[2];
+ RoReg UOTGHS_DEVEPTIMR[10]; /**< \brief (Uotghs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */
+ RoReg Reserved6[2];
+ WoReg UOTGHS_DEVEPTIER[10]; /**< \brief (Uotghs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */
+ RoReg Reserved7[2];
+ WoReg UOTGHS_DEVEPTIDR[10]; /**< \brief (Uotghs Offset: 0x220) Device Endpoint Disable Register (n = 0) */
+ RoReg Reserved8[50];
+ UotghsDevdma UOTGHS_DEVDMA[UOTGHSDEVDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x310) n = 1 .. 7 */
+ RoReg Reserved9[32];
+ RwReg UOTGHS_HSTCTRL; /**< \brief (Uotghs Offset: 0x0400) Host General Control Register */
+ RoReg UOTGHS_HSTISR; /**< \brief (Uotghs Offset: 0x0404) Host Global Interrupt Status Register */
+ WoReg UOTGHS_HSTICR; /**< \brief (Uotghs Offset: 0x0408) Host Global Interrupt Clear Register */
+ WoReg UOTGHS_HSTIFR; /**< \brief (Uotghs Offset: 0x040C) Host Global Interrupt Set Register */
+ RoReg UOTGHS_HSTIMR; /**< \brief (Uotghs Offset: 0x0410) Host Global Interrupt Mask Register */
+ WoReg UOTGHS_HSTIDR; /**< \brief (Uotghs Offset: 0x0414) Host Global Interrupt Disable Register */
+ WoReg UOTGHS_HSTIER; /**< \brief (Uotghs Offset: 0x0418) Host Global Interrupt Enable Register */
+ RwReg UOTGHS_HSTPIP; /**< \brief (Uotghs Offset: 0x0041C) Host Pipe Register */
+ RwReg UOTGHS_HSTFNUM; /**< \brief (Uotghs Offset: 0x0420) Host Frame Number Register */
+ RwReg UOTGHS_HSTADDR1; /**< \brief (Uotghs Offset: 0x0424) Host Address 1 Register */
+ RwReg UOTGHS_HSTADDR2; /**< \brief (Uotghs Offset: 0x0428) Host Address 2 Register */
+ RwReg UOTGHS_HSTADDR3; /**< \brief (Uotghs Offset: 0x042C) Host Address 3 Register */
+ RoReg Reserved10[52];
+ RwReg UOTGHS_HSTPIPCFG[10]; /**< \brief (Uotghs Offset: 0x500) Host Pipe Configuration Register (n = 0) */
+ RoReg Reserved11[2];
+ RoReg UOTGHS_HSTPIPISR[10]; /**< \brief (Uotghs Offset: 0x530) Host Pipe Status Register (n = 0) */
+ RoReg Reserved12[2];
+ WoReg UOTGHS_HSTPIPICR[10]; /**< \brief (Uotghs Offset: 0x560) Host Pipe Clear Register (n = 0) */
+ RoReg Reserved13[2];
+ WoReg UOTGHS_HSTPIPIFR[10]; /**< \brief (Uotghs Offset: 0x590) Host Pipe Set Register (n = 0) */
+ RoReg Reserved14[2];
+ RoReg UOTGHS_HSTPIPIMR[10]; /**< \brief (Uotghs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */
+ RoReg Reserved15[2];
+ WoReg UOTGHS_HSTPIPIER[10]; /**< \brief (Uotghs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */
+ RoReg Reserved16[2];
+ WoReg UOTGHS_HSTPIPIDR[10]; /**< \brief (Uotghs Offset: 0x620) Host Pipe Disable Register (n = 0) */
+ RoReg Reserved17[2];
+ RwReg UOTGHS_HSTPIPINRQ[10]; /**< \brief (Uotghs Offset: 0x650) Host Pipe IN Request Register (n = 0) */
+ RoReg Reserved18[2];
+ RwReg UOTGHS_HSTPIPERR[10]; /**< \brief (Uotghs Offset: 0x680) Host Pipe Error Register (n = 0) */
+ RoReg Reserved19[26];
+ UotghsHstdma UOTGHS_HSTDMA[UOTGHSHSTDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x710) n = 1 .. 7 */
+ RoReg Reserved20[32];
+ RwReg UOTGHS_CTRL; /**< \brief (Uotghs Offset: 0x0800) General Control Register */
+ RoReg UOTGHS_SR; /**< \brief (Uotghs Offset: 0x0804) General Status Register */
+ WoReg UOTGHS_SCR; /**< \brief (Uotghs Offset: 0x0808) General Status Clear Register */
+ WoReg UOTGHS_SFR; /**< \brief (Uotghs Offset: 0x080C) General Status Set Register */
+ RoReg Reserved21[7];
+ RoReg UOTGHS_FSM; /**< \brief (Uotghs Offset: 0x082C) General Finite State Machine Register */
+} Uotghs;
+#endif /* __ASSEMBLY__ */
+/* -------- UOTGHS_DEVCTRL : (UOTGHS Offset: 0x0000) Device General Control Register -------- */
+#define UOTGHS_DEVCTRL_UADD_Pos 0
+#define UOTGHS_DEVCTRL_UADD_Msk (0x7fu << UOTGHS_DEVCTRL_UADD_Pos) /**< \brief (UOTGHS_DEVCTRL) USB Address */
+#define UOTGHS_DEVCTRL_UADD(value) ((UOTGHS_DEVCTRL_UADD_Msk & ((value) << UOTGHS_DEVCTRL_UADD_Pos)))
+#define UOTGHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (UOTGHS_DEVCTRL) Address Enable */
+#define UOTGHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (UOTGHS_DEVCTRL) Detach */
+#define UOTGHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (UOTGHS_DEVCTRL) Remote Wake-Up */
+#define UOTGHS_DEVCTRL_SPDCONF_Pos 10
+#define UOTGHS_DEVCTRL_SPDCONF_Msk (0x3u << UOTGHS_DEVCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_DEVCTRL) Mode Configuration */
+#define UOTGHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. */
+#define UOTGHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (UOTGHS_DEVCTRL) For a better consumption, if high-speed is not needed. */
+#define UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (UOTGHS_DEVCTRL) Forced high speed. */
+#define UOTGHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral remains in full-speed mode whatever the host speed capability. */
+#define UOTGHS_DEVCTRL_LS (0x1u << 12) /**< \brief (UOTGHS_DEVCTRL) Low-Speed Mode Force */
+#define UOTGHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (UOTGHS_DEVCTRL) Test mode J */
+#define UOTGHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (UOTGHS_DEVCTRL) Test mode K */
+#define UOTGHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (UOTGHS_DEVCTRL) Test packet mode */
+#define UOTGHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (UOTGHS_DEVCTRL) Specific Operational mode */
+/* -------- UOTGHS_DEVISR : (UOTGHS Offset: 0x0004) Device Global Interrupt Status Register -------- */
+#define UOTGHS_DEVISR_SUSP (0x1u << 0) /**< \brief (UOTGHS_DEVISR) Suspend Interrupt */
+#define UOTGHS_DEVISR_MSOF (0x1u << 1) /**< \brief (UOTGHS_DEVISR) Micro Start of Frame Interrupt */
+#define UOTGHS_DEVISR_SOF (0x1u << 2) /**< \brief (UOTGHS_DEVISR) Start of Frame Interrupt */
+#define UOTGHS_DEVISR_EORST (0x1u << 3) /**< \brief (UOTGHS_DEVISR) End of Reset Interrupt */
+#define UOTGHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (UOTGHS_DEVISR) Wake-Up Interrupt */
+#define UOTGHS_DEVISR_EORSM (0x1u << 5) /**< \brief (UOTGHS_DEVISR) End of Resume Interrupt */
+#define UOTGHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (UOTGHS_DEVISR) Upstream Resume Interrupt */
+#define UOTGHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVISR) Endpoint 0 Interrupt */
+#define UOTGHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVISR) Endpoint 1 Interrupt */
+#define UOTGHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVISR) Endpoint 2 Interrupt */
+#define UOTGHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVISR) Endpoint 3 Interrupt */
+#define UOTGHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVISR) Endpoint 4 Interrupt */
+#define UOTGHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVISR) Endpoint 5 Interrupt */
+#define UOTGHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVISR) Endpoint 6 Interrupt */
+#define UOTGHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVISR) Endpoint 7 Interrupt */
+#define UOTGHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVISR) Endpoint 8 Interrupt */
+#define UOTGHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVISR) Endpoint 9 Interrupt */
+#define UOTGHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVISR) DMA Channel 1 Interrupt */
+#define UOTGHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVISR) DMA Channel 2 Interrupt */
+#define UOTGHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVISR) DMA Channel 3 Interrupt */
+#define UOTGHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVISR) DMA Channel 4 Interrupt */
+#define UOTGHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVISR) DMA Channel 5 Interrupt */
+#define UOTGHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVISR) DMA Channel 6 Interrupt */
+/* -------- UOTGHS_DEVICR : (UOTGHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */
+#define UOTGHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (UOTGHS_DEVICR) Suspend Interrupt Clear */
+#define UOTGHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (UOTGHS_DEVICR) Micro Start of Frame Interrupt Clear */
+#define UOTGHS_DEVICR_SOFC (0x1u << 2) /**< \brief (UOTGHS_DEVICR) Start of Frame Interrupt Clear */
+#define UOTGHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (UOTGHS_DEVICR) End of Reset Interrupt Clear */
+#define UOTGHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (UOTGHS_DEVICR) Wake-Up Interrupt Clear */
+#define UOTGHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (UOTGHS_DEVICR) End of Resume Interrupt Clear */
+#define UOTGHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (UOTGHS_DEVICR) Upstream Resume Interrupt Clear */
+/* -------- UOTGHS_DEVIFR : (UOTGHS Offset: 0x000C) Device Global Interrupt Set Register -------- */
+#define UOTGHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (UOTGHS_DEVIFR) Suspend Interrupt Set */
+#define UOTGHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (UOTGHS_DEVIFR) Micro Start of Frame Interrupt Set */
+#define UOTGHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (UOTGHS_DEVIFR) Start of Frame Interrupt Set */
+#define UOTGHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (UOTGHS_DEVIFR) End of Reset Interrupt Set */
+#define UOTGHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (UOTGHS_DEVIFR) Wake-Up Interrupt Set */
+#define UOTGHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (UOTGHS_DEVIFR) End of Resume Interrupt Set */
+#define UOTGHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (UOTGHS_DEVIFR) Upstream Resume Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIFR) DMA Channel 1 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIFR) DMA Channel 2 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIFR) DMA Channel 3 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIFR) DMA Channel 4 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIFR) DMA Channel 5 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIFR) DMA Channel 6 Interrupt Set */
+/* -------- UOTGHS_DEVIMR : (UOTGHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */
+#define UOTGHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (UOTGHS_DEVIMR) Suspend Interrupt Mask */
+#define UOTGHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (UOTGHS_DEVIMR) Micro Start of Frame Interrupt Mask */
+#define UOTGHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (UOTGHS_DEVIMR) Start of Frame Interrupt Mask */
+#define UOTGHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (UOTGHS_DEVIMR) End of Reset Interrupt Mask */
+#define UOTGHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (UOTGHS_DEVIMR) Wake-Up Interrupt Mask */
+#define UOTGHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (UOTGHS_DEVIMR) End of Resume Interrupt Mask */
+#define UOTGHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (UOTGHS_DEVIMR) Upstream Resume Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIMR) Endpoint 0 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIMR) Endpoint 1 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIMR) Endpoint 2 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIMR) Endpoint 3 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIMR) Endpoint 4 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIMR) Endpoint 5 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIMR) Endpoint 6 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIMR) Endpoint 7 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIMR) Endpoint 8 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIMR) Endpoint 9 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIMR) DMA Channel 1 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIMR) DMA Channel 2 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIMR) DMA Channel 3 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIMR) DMA Channel 4 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIMR) DMA Channel 5 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIMR) DMA Channel 6 Interrupt Mask */
+/* -------- UOTGHS_DEVIDR : (UOTGHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */
+#define UOTGHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (UOTGHS_DEVIDR) Suspend Interrupt Disable */
+#define UOTGHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (UOTGHS_DEVIDR) Micro Start of Frame Interrupt Disable */
+#define UOTGHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (UOTGHS_DEVIDR) Start of Frame Interrupt Disable */
+#define UOTGHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (UOTGHS_DEVIDR) End of Reset Interrupt Disable */
+#define UOTGHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (UOTGHS_DEVIDR) Wake-Up Interrupt Disable */
+#define UOTGHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (UOTGHS_DEVIDR) End of Resume Interrupt Disable */
+#define UOTGHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (UOTGHS_DEVIDR) Upstream Resume Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIDR) Endpoint 0 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIDR) Endpoint 1 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIDR) Endpoint 2 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIDR) Endpoint 3 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIDR) Endpoint 4 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIDR) Endpoint 5 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIDR) Endpoint 6 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIDR) Endpoint 7 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIDR) Endpoint 8 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIDR) Endpoint 9 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIDR) DMA Channel 1 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIDR) DMA Channel 2 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIDR) DMA Channel 3 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIDR) DMA Channel 4 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIDR) DMA Channel 5 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIDR) DMA Channel 6 Interrupt Disable */
+/* -------- UOTGHS_DEVIER : (UOTGHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */
+#define UOTGHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (UOTGHS_DEVIER) Suspend Interrupt Enable */
+#define UOTGHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (UOTGHS_DEVIER) Micro Start of Frame Interrupt Enable */
+#define UOTGHS_DEVIER_SOFES (0x1u << 2) /**< \brief (UOTGHS_DEVIER) Start of Frame Interrupt Enable */
+#define UOTGHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (UOTGHS_DEVIER) End of Reset Interrupt Enable */
+#define UOTGHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (UOTGHS_DEVIER) Wake-Up Interrupt Enable */
+#define UOTGHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (UOTGHS_DEVIER) End of Resume Interrupt Enable */
+#define UOTGHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (UOTGHS_DEVIER) Upstream Resume Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIER) Endpoint 0 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIER) Endpoint 1 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIER) Endpoint 2 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIER) Endpoint 3 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIER) Endpoint 4 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIER) Endpoint 5 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIER) Endpoint 6 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIER) Endpoint 7 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIER) Endpoint 8 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIER) Endpoint 9 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIER) DMA Channel 1 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIER) DMA Channel 2 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIER) DMA Channel 3 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIER) DMA Channel 4 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIER) DMA Channel 5 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIER) DMA Channel 6 Interrupt Enable */
+/* -------- UOTGHS_DEVEPT : (UOTGHS Offset: 0x001C) Device Endpoint Register -------- */
+#define UOTGHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Enable */
+#define UOTGHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Enable */
+#define UOTGHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Enable */
+#define UOTGHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Enable */
+#define UOTGHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Enable */
+#define UOTGHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Enable */
+#define UOTGHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Enable */
+#define UOTGHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Enable */
+#define UOTGHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Enable */
+#define UOTGHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Reset */
+#define UOTGHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Reset */
+#define UOTGHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Reset */
+#define UOTGHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Reset */
+#define UOTGHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Reset */
+#define UOTGHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Reset */
+#define UOTGHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Reset */
+#define UOTGHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Reset */
+#define UOTGHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Reset */
+/* -------- UOTGHS_DEVFNUM : (UOTGHS Offset: 0x0020) Device Frame Number Register -------- */
+#define UOTGHS_DEVFNUM_MFNUM_Pos 0
+#define UOTGHS_DEVFNUM_MFNUM_Msk (0x7u << UOTGHS_DEVFNUM_MFNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Micro Frame Number */
+#define UOTGHS_DEVFNUM_FNUM_Pos 3
+#define UOTGHS_DEVFNUM_FNUM_Msk (0x7ffu << UOTGHS_DEVFNUM_FNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Frame Number */
+#define UOTGHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (UOTGHS_DEVFNUM) Frame Number CRC Error */
+/* -------- UOTGHS_DEVEPTCFG[10] : (UOTGHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */
+#define UOTGHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Memory Allocate */
+#define UOTGHS_DEVEPTCFG_EPBK_Pos 2
+#define UOTGHS_DEVEPTCFG_EPBK_Msk (0x3u << UOTGHS_DEVEPTCFG_EPBK_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Banks */
+#define UOTGHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Single-bank endpoint */
+#define UOTGHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Double-bank endpoint */
+#define UOTGHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Triple-bank endpoint */
+#define UOTGHS_DEVEPTCFG_EPSIZE_Pos 4
+#define UOTGHS_DEVEPTCFG_EPSIZE_Msk (0x7u << UOTGHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Size */
+#define UOTGHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 8 bytes */
+#define UOTGHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 16 bytes */
+#define UOTGHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 32 bytes */
+#define UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 64 bytes */
+#define UOTGHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 128 bytes */
+#define UOTGHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 256 bytes */
+#define UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 512 bytes */
+#define UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 1024 bytes */
+#define UOTGHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Direction */
+#define UOTGHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) The endpoint direction is OUT. */
+#define UOTGHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */
+#define UOTGHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (UOTGHS_DEVEPTCFG[10]) Automatic Switch */
+#define UOTGHS_DEVEPTCFG_EPTYPE_Pos 11
+#define UOTGHS_DEVEPTCFG_EPTYPE_Msk (0x3u << UOTGHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Type */
+#define UOTGHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Control */
+#define UOTGHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Isochronous */
+#define UOTGHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Bulk */
+#define UOTGHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Interrupt */
+#define UOTGHS_DEVEPTCFG_NBTRANS_Pos 13
+#define UOTGHS_DEVEPTCFG_NBTRANS_Msk (0x3u << UOTGHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Number of transaction per microframe for isochronous endpoint */
+#define UOTGHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) reserved to endpoint that does not have the high-bandwidth isochronous capability. */
+#define UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) default value: one transaction per micro-frame. */
+#define UOTGHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) 2 transactions per micro-frame. This endpoint should be configured as double-bank. */
+#define UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) 3 transactions per micro-frame. This endpoint should be configured as triple-bank. */
+/* -------- UOTGHS_DEVEPTISR[10] : (UOTGHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */
+#define UOTGHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (UOTGHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */
+#define UOTGHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (UOTGHS_DEVEPTISR[10]) Received OUT Data Interrupt */
+#define UOTGHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[10]) Received SETUP Interrupt */
+#define UOTGHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[10]) Underflow Interrupt */
+#define UOTGHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[10]) NAKed OUT Interrupt */
+#define UOTGHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[10]) High bandwidth isochronous IN Underflow Error Interrupt */
+#define UOTGHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[10]) NAKed IN Interrupt */
+#define UOTGHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */
+#define UOTGHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_DEVEPTISR[10]) Overflow Interrupt */
+#define UOTGHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[10]) STALLed Interrupt */
+#define UOTGHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[10]) CRC Error Interrupt */
+#define UOTGHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (UOTGHS_DEVEPTISR[10]) Short Packet Interrupt */
+#define UOTGHS_DEVEPTISR_DTSEQ_Pos 8
+#define UOTGHS_DEVEPTISR_DTSEQ_Msk (0x3u << UOTGHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Data Toggle Sequence */
+#define UOTGHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data0 toggle sequence */
+#define UOTGHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data1 toggle sequence */
+#define UOTGHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data2 toggle sequence (for high-bandwidth isochronous endpoint) */
+#define UOTGHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) MData toggle sequence (for high-bandwidth isochronous endpoint) */
+#define UOTGHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (UOTGHS_DEVEPTISR[10]) High-bandwidth isochronous OUT endpoint transaction error Interrupt */
+#define UOTGHS_DEVEPTISR_NBUSYBK_Pos 12
+#define UOTGHS_DEVEPTISR_NBUSYBK_Msk (0x3u << UOTGHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Number of Busy Banks */
+#define UOTGHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 0 busy bank (all banks free) */
+#define UOTGHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 1 busy bank */
+#define UOTGHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 2 busy banks */
+#define UOTGHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 3 busy banks */
+#define UOTGHS_DEVEPTISR_CURRBK_Pos 14
+#define UOTGHS_DEVEPTISR_CURRBK_Msk (0x3u << UOTGHS_DEVEPTISR_CURRBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Current Bank */
+#define UOTGHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank0 */
+#define UOTGHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank1 */
+#define UOTGHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank2 */
+#define UOTGHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_DEVEPTISR[10]) Read-write Allowed */
+#define UOTGHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (UOTGHS_DEVEPTISR[10]) Control Direction */
+#define UOTGHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_DEVEPTISR[10]) Configuration OK Status */
+#define UOTGHS_DEVEPTISR_BYCT_Pos 20
+#define UOTGHS_DEVEPTISR_BYCT_Msk (0x7ffu << UOTGHS_DEVEPTISR_BYCT_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Byte Count */
+/* -------- UOTGHS_DEVEPTICR[10] : (UOTGHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */
+#define UOTGHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */
+#define UOTGHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */
+#define UOTGHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */
+#define UOTGHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[10]) Underflow Interrupt Clear */
+#define UOTGHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */
+#define UOTGHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[10]) High bandwidth isochronous IN Underflow Error Interrupt Clear */
+#define UOTGHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */
+#define UOTGHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
+#define UOTGHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTICR[10]) Overflow Interrupt Clear */
+#define UOTGHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[10]) STALLed Interrupt Clear */
+#define UOTGHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[10]) CRC Error Interrupt Clear */
+#define UOTGHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTICR[10]) Short Packet Interrupt Clear */
+/* -------- UOTGHS_DEVEPTIFR[10] : (UOTGHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */
+#define UOTGHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */
+#define UOTGHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */
+#define UOTGHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[10]) Underflow Interrupt Set */
+#define UOTGHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */
+#define UOTGHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[10]) High bandwidth isochronous IN Underflow Error Interrupt Set */
+#define UOTGHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */
+#define UOTGHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */
+#define UOTGHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIFR[10]) Overflow Interrupt Set */
+#define UOTGHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[10]) STALLed Interrupt Set */
+#define UOTGHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[10]) CRC Error Interrupt Set */
+#define UOTGHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIFR[10]) Short Packet Interrupt Set */
+#define UOTGHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */
+/* -------- UOTGHS_DEVEPTIMR[10] : (UOTGHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */
+#define UOTGHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIMR[10]) Received OUT Data Interrupt */
+#define UOTGHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[10]) Received SETUP Interrupt */
+#define UOTGHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[10]) Underflow Interrupt */
+#define UOTGHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[10]) NAKed OUT Interrupt */
+#define UOTGHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */
+#define UOTGHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[10]) NAKed IN Interrupt */
+#define UOTGHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */
+#define UOTGHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIMR[10]) Overflow Interrupt */
+#define UOTGHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[10]) STALLed Interrupt */
+#define UOTGHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[10]) CRC Error Interrupt */
+#define UOTGHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIMR[10]) Short Packet Interrupt */
+#define UOTGHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIMR[10]) MData Interrupt */
+#define UOTGHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIMR[10]) DataX Interrupt */
+#define UOTGHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIMR[10]) Transaction Error Interrupt */
+#define UOTGHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */
+#define UOTGHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIMR[10]) Kill IN Bank */
+#define UOTGHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIMR[10]) FIFO Control */
+#define UOTGHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */
+#define UOTGHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIMR[10]) NYET Token Disable */
+#define UOTGHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIMR[10]) Reset Data Toggle */
+#define UOTGHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIMR[10]) STALL Request */
+/* -------- UOTGHS_DEVEPTIER[10] : (UOTGHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */
+#define UOTGHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */
+#define UOTGHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */
+#define UOTGHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[10]) Underflow Interrupt Enable */
+#define UOTGHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */
+#define UOTGHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */
+#define UOTGHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */
+#define UOTGHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */
+#define UOTGHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIER[10]) Overflow Interrupt Enable */
+#define UOTGHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[10]) STALLed Interrupt Enable */
+#define UOTGHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[10]) CRC Error Interrupt Enable */
+#define UOTGHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIER[10]) Short Packet Interrupt Enable */
+#define UOTGHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIER[10]) MData Interrupt Enable */
+#define UOTGHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIER[10]) DataX Interrupt Enable */
+#define UOTGHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */
+#define UOTGHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */
+#define UOTGHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIER[10]) Kill IN Bank */
+#define UOTGHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */
+#define UOTGHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIER[10]) NYET Token Disable Enable */
+#define UOTGHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIER[10]) Reset Data Toggle Enable */
+#define UOTGHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIER[10]) STALL Request Enable */
+/* -------- UOTGHS_DEVEPTIDR[10] : (UOTGHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[10]) Underflow Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIDR[10]) Overflow Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[10]) STALLed Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIDR[10]) MData Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIDR[10]) DataX Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIDR[10]) FIFO Control Clear */
+#define UOTGHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */
+#define UOTGHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIDR[10]) NYET Token Disable Clear */
+#define UOTGHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIDR[10]) STALL Request Clear */
+/* -------- UOTGHS_DEVDMANXTDSC : (UOTGHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_DEVDMANXTDSC) Next Descriptor Address */
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))
+/* -------- UOTGHS_DEVDMAADDRESS : (UOTGHS Offset: N/A) Device DMA Channel Address Register -------- */
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos 0
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_DEVDMAADDRESS) Buffer Address */
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD(value) ((UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos)))
+/* -------- UOTGHS_DEVDMACONTROL : (UOTGHS Offset: N/A) Device DMA Channel Control Register -------- */
+#define UOTGHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMACONTROL) Channel Enable Command */
+#define UOTGHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
+#define UOTGHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Enable Control */
+#define UOTGHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Enable Control */
+#define UOTGHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Interrupt Enable */
+#define UOTGHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Interrupt Enable */
+#define UOTGHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */
+#define UOTGHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_DEVDMACONTROL) Burst Lock Enable */
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))
+/* -------- UOTGHS_DEVDMASTATUS : (UOTGHS Offset: N/A) Device DMA Channel Status Register -------- */
+#define UOTGHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Enable Status */
+#define UOTGHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Active Status */
+#define UOTGHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Transfer Status */
+#define UOTGHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Buffer Status */
+#define UOTGHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_DEVDMASTATUS) Descriptor Loaded Status */
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos 16
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_DEVDMASTATUS) Buffer Byte Count */
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT(value) ((UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos)))
+/* -------- UOTGHS_HSTCTRL : (UOTGHS Offset: 0x0400) Host General Control Register -------- */
+#define UOTGHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (UOTGHS_HSTCTRL) Start of Frame Generation Enable */
+#define UOTGHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (UOTGHS_HSTCTRL) Send USB Reset */
+#define UOTGHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (UOTGHS_HSTCTRL) Send USB Resume */
+#define UOTGHS_HSTCTRL_SPDCONF_Pos 12
+#define UOTGHS_HSTCTRL_SPDCONF_Msk (0x3u << UOTGHS_HSTCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_HSTCTRL) Mode Configuration */
+#define UOTGHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (UOTGHS_HSTCTRL) The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. */
+#define UOTGHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (UOTGHS_HSTCTRL) For a better consumption, if high-speed is not needed. */
+#define UOTGHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (UOTGHS_HSTCTRL) Forced high speed. */
+#define UOTGHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (UOTGHS_HSTCTRL) The host remains to full-speed mode whatever the peripheral speed capability. */
+/* -------- UOTGHS_HSTISR : (UOTGHS Offset: 0x0404) Host Global Interrupt Status Register -------- */
+#define UOTGHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (UOTGHS_HSTISR) Device Connection Interrupt */
+#define UOTGHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (UOTGHS_HSTISR) Device Disconnection Interrupt */
+#define UOTGHS_HSTISR_RSTI (0x1u << 2) /**< \brief (UOTGHS_HSTISR) USB Reset Sent Interrupt */
+#define UOTGHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (UOTGHS_HSTISR) Downstream Resume Sent Interrupt */
+#define UOTGHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (UOTGHS_HSTISR) Upstream Resume Received Interrupt */
+#define UOTGHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (UOTGHS_HSTISR) Host Start of Frame Interrupt */
+#define UOTGHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (UOTGHS_HSTISR) Host Wake-Up Interrupt */
+#define UOTGHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTISR) Pipe 0 Interrupt */
+#define UOTGHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTISR) Pipe 1 Interrupt */
+#define UOTGHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTISR) Pipe 2 Interrupt */
+#define UOTGHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTISR) Pipe 3 Interrupt */
+#define UOTGHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTISR) Pipe 4 Interrupt */
+#define UOTGHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTISR) Pipe 5 Interrupt */
+#define UOTGHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTISR) Pipe 6 Interrupt */
+#define UOTGHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTISR) Pipe 7 Interrupt */
+#define UOTGHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTISR) Pipe 8 Interrupt */
+#define UOTGHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTISR) Pipe 9 Interrupt */
+#define UOTGHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTISR) DMA Channel 1 Interrupt */
+#define UOTGHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTISR) DMA Channel 2 Interrupt */
+#define UOTGHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTISR) DMA Channel 3 Interrupt */
+#define UOTGHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTISR) DMA Channel 4 Interrupt */
+#define UOTGHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTISR) DMA Channel 5 Interrupt */
+#define UOTGHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTISR) DMA Channel 6 Interrupt */
+/* -------- UOTGHS_HSTICR : (UOTGHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */
+#define UOTGHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (UOTGHS_HSTICR) Device Connection Interrupt Clear */
+#define UOTGHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (UOTGHS_HSTICR) Device Disconnection Interrupt Clear */
+#define UOTGHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (UOTGHS_HSTICR) USB Reset Sent Interrupt Clear */
+#define UOTGHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (UOTGHS_HSTICR) Downstream Resume Sent Interrupt Clear */
+#define UOTGHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (UOTGHS_HSTICR) Upstream Resume Received Interrupt Clear */
+#define UOTGHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (UOTGHS_HSTICR) Host Start of Frame Interrupt Clear */
+#define UOTGHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (UOTGHS_HSTICR) Host Wake-Up Interrupt Clear */
+/* -------- UOTGHS_HSTIFR : (UOTGHS Offset: 0x040C) Host Global Interrupt Set Register -------- */
+#define UOTGHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (UOTGHS_HSTIFR) Device Connection Interrupt Set */
+#define UOTGHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (UOTGHS_HSTIFR) Device Disconnection Interrupt Set */
+#define UOTGHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (UOTGHS_HSTIFR) USB Reset Sent Interrupt Set */
+#define UOTGHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (UOTGHS_HSTIFR) Downstream Resume Sent Interrupt Set */
+#define UOTGHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (UOTGHS_HSTIFR) Upstream Resume Received Interrupt Set */
+#define UOTGHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (UOTGHS_HSTIFR) Host Start of Frame Interrupt Set */
+#define UOTGHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (UOTGHS_HSTIFR) Host Wake-Up Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIFR) DMA Channel 1 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIFR) DMA Channel 2 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIFR) DMA Channel 3 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIFR) DMA Channel 4 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIFR) DMA Channel 5 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIFR) DMA Channel 6 Interrupt Set */
+/* -------- UOTGHS_HSTIMR : (UOTGHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */
+#define UOTGHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (UOTGHS_HSTIMR) Device Connection Interrupt Enable */
+#define UOTGHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (UOTGHS_HSTIMR) Device Disconnection Interrupt Enable */
+#define UOTGHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (UOTGHS_HSTIMR) USB Reset Sent Interrupt Enable */
+#define UOTGHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (UOTGHS_HSTIMR) Downstream Resume Sent Interrupt Enable */
+#define UOTGHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (UOTGHS_HSTIMR) Upstream Resume Received Interrupt Enable */
+#define UOTGHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (UOTGHS_HSTIMR) Host Start of Frame Interrupt Enable */
+#define UOTGHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (UOTGHS_HSTIMR) Host Wake-Up Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIMR) Pipe 0 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIMR) Pipe 1 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIMR) Pipe 2 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIMR) Pipe 3 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIMR) Pipe 4 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIMR) Pipe 5 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIMR) Pipe 6 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIMR) Pipe 7 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIMR) Pipe 8 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIMR) Pipe 9 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIMR) DMA Channel 1 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIMR) DMA Channel 2 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIMR) DMA Channel 3 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIMR) DMA Channel 4 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIMR) DMA Channel 5 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIMR) DMA Channel 6 Interrupt Enable */
+/* -------- UOTGHS_HSTIDR : (UOTGHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */
+#define UOTGHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (UOTGHS_HSTIDR) Device Connection Interrupt Disable */
+#define UOTGHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (UOTGHS_HSTIDR) Device Disconnection Interrupt Disable */
+#define UOTGHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (UOTGHS_HSTIDR) USB Reset Sent Interrupt Disable */
+#define UOTGHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (UOTGHS_HSTIDR) Downstream Resume Sent Interrupt Disable */
+#define UOTGHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (UOTGHS_HSTIDR) Upstream Resume Received Interrupt Disable */
+#define UOTGHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTIDR) Host Start of Frame Interrupt Disable */
+#define UOTGHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (UOTGHS_HSTIDR) Host Wake-Up Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIDR) Pipe 0 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIDR) Pipe 1 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIDR) Pipe 2 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIDR) Pipe 3 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIDR) Pipe 4 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIDR) Pipe 5 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIDR) Pipe 6 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIDR) Pipe 7 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIDR) Pipe 8 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIDR) Pipe 9 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIDR) DMA Channel 1 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIDR) DMA Channel 2 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIDR) DMA Channel 3 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIDR) DMA Channel 4 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIDR) DMA Channel 5 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIDR) DMA Channel 6 Interrupt Disable */
+/* -------- UOTGHS_HSTIER : (UOTGHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */
+#define UOTGHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (UOTGHS_HSTIER) Device Connection Interrupt Enable */
+#define UOTGHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (UOTGHS_HSTIER) Device Disconnection Interrupt Enable */
+#define UOTGHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (UOTGHS_HSTIER) USB Reset Sent Interrupt Enable */
+#define UOTGHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (UOTGHS_HSTIER) Downstream Resume Sent Interrupt Enable */
+#define UOTGHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (UOTGHS_HSTIER) Upstream Resume Received Interrupt Enable */
+#define UOTGHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (UOTGHS_HSTIER) Host Start of Frame Interrupt Enable */
+#define UOTGHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (UOTGHS_HSTIER) Host Wake-Up Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIER) Pipe 0 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIER) Pipe 1 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIER) Pipe 2 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIER) Pipe 3 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIER) Pipe 4 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIER) Pipe 5 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIER) Pipe 6 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIER) Pipe 7 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIER) Pipe 8 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIER) Pipe 9 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIER) DMA Channel 1 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIER) DMA Channel 2 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIER) DMA Channel 3 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIER) DMA Channel 4 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIER) DMA Channel 5 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIER) DMA Channel 6 Interrupt Enable */
+/* -------- UOTGHS_HSTPIP : (UOTGHS Offset: 0x0041C) Host Pipe Register -------- */
+#define UOTGHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Enable */
+#define UOTGHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Enable */
+#define UOTGHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Enable */
+#define UOTGHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Enable */
+#define UOTGHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Enable */
+#define UOTGHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Enable */
+#define UOTGHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Enable */
+#define UOTGHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Enable */
+#define UOTGHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Enable */
+#define UOTGHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Reset */
+#define UOTGHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Reset */
+#define UOTGHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Reset */
+#define UOTGHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Reset */
+#define UOTGHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Reset */
+#define UOTGHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Reset */
+#define UOTGHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Reset */
+#define UOTGHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Reset */
+#define UOTGHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Reset */
+/* -------- UOTGHS_HSTFNUM : (UOTGHS Offset: 0x0420) Host Frame Number Register -------- */
+#define UOTGHS_HSTFNUM_MFNUM_Pos 0
+#define UOTGHS_HSTFNUM_MFNUM_Msk (0x7u << UOTGHS_HSTFNUM_MFNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Micro Frame Number */
+#define UOTGHS_HSTFNUM_MFNUM(value) ((UOTGHS_HSTFNUM_MFNUM_Msk & ((value) << UOTGHS_HSTFNUM_MFNUM_Pos)))
+#define UOTGHS_HSTFNUM_FNUM_Pos 3
+#define UOTGHS_HSTFNUM_FNUM_Msk (0x7ffu << UOTGHS_HSTFNUM_FNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Number */
+#define UOTGHS_HSTFNUM_FNUM(value) ((UOTGHS_HSTFNUM_FNUM_Msk & ((value) << UOTGHS_HSTFNUM_FNUM_Pos)))
+#define UOTGHS_HSTFNUM_FLENHIGH_Pos 16
+#define UOTGHS_HSTFNUM_FLENHIGH_Msk (0xffu << UOTGHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Length */
+#define UOTGHS_HSTFNUM_FLENHIGH(value) ((UOTGHS_HSTFNUM_FLENHIGH_Msk & ((value) << UOTGHS_HSTFNUM_FLENHIGH_Pos)))
+/* -------- UOTGHS_HSTADDR1 : (UOTGHS Offset: 0x0424) Host Address 1 Register -------- */
+#define UOTGHS_HSTADDR1_HSTADDRP0_Pos 0
+#define UOTGHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP0(value) ((UOTGHS_HSTADDR1_HSTADDRP0_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP0_Pos)))
+#define UOTGHS_HSTADDR1_HSTADDRP1_Pos 8
+#define UOTGHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP1(value) ((UOTGHS_HSTADDR1_HSTADDRP1_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP1_Pos)))
+#define UOTGHS_HSTADDR1_HSTADDRP2_Pos 16
+#define UOTGHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP2(value) ((UOTGHS_HSTADDR1_HSTADDRP2_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP2_Pos)))
+#define UOTGHS_HSTADDR1_HSTADDRP3_Pos 24
+#define UOTGHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP3(value) ((UOTGHS_HSTADDR1_HSTADDRP3_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP3_Pos)))
+/* -------- UOTGHS_HSTADDR2 : (UOTGHS Offset: 0x0428) Host Address 2 Register -------- */
+#define UOTGHS_HSTADDR2_HSTADDRP4_Pos 0
+#define UOTGHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP4(value) ((UOTGHS_HSTADDR2_HSTADDRP4_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP4_Pos)))
+#define UOTGHS_HSTADDR2_HSTADDRP5_Pos 8
+#define UOTGHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP5(value) ((UOTGHS_HSTADDR2_HSTADDRP5_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP5_Pos)))
+#define UOTGHS_HSTADDR2_HSTADDRP6_Pos 16
+#define UOTGHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP6(value) ((UOTGHS_HSTADDR2_HSTADDRP6_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP6_Pos)))
+#define UOTGHS_HSTADDR2_HSTADDRP7_Pos 24
+#define UOTGHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP7(value) ((UOTGHS_HSTADDR2_HSTADDRP7_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP7_Pos)))
+/* -------- UOTGHS_HSTADDR3 : (UOTGHS Offset: 0x042C) Host Address 3 Register -------- */
+#define UOTGHS_HSTADDR3_HSTADDRP8_Pos 0
+#define UOTGHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */
+#define UOTGHS_HSTADDR3_HSTADDRP8(value) ((UOTGHS_HSTADDR3_HSTADDRP8_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP8_Pos)))
+#define UOTGHS_HSTADDR3_HSTADDRP9_Pos 8
+#define UOTGHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */
+#define UOTGHS_HSTADDR3_HSTADDRP9(value) ((UOTGHS_HSTADDR3_HSTADDRP9_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP9_Pos)))
+/* -------- UOTGHS_HSTPIPCFG[10] : (UOTGHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */
+#define UOTGHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Memory Allocate */
+#define UOTGHS_HSTPIPCFG_PBK_Pos 2
+#define UOTGHS_HSTPIPCFG_PBK_Msk (0x3u << UOTGHS_HSTPIPCFG_PBK_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Banks */
+#define UOTGHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Single-bank pipe */
+#define UOTGHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Double-bank pipe */
+#define UOTGHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Triple-bank pipe */
+#define UOTGHS_HSTPIPCFG_PSIZE_Pos 4
+#define UOTGHS_HSTPIPCFG_PSIZE_Msk (0x7u << UOTGHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Size */
+#define UOTGHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 8 bytes */
+#define UOTGHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 16 bytes */
+#define UOTGHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 32 bytes */
+#define UOTGHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 64 bytes */
+#define UOTGHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 128 bytes */
+#define UOTGHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 256 bytes */
+#define UOTGHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 512 bytes */
+#define UOTGHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 1024 bytes */
+#define UOTGHS_HSTPIPCFG_PTOKEN_Pos 8
+#define UOTGHS_HSTPIPCFG_PTOKEN_Msk (0x3u << UOTGHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Token */
+#define UOTGHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) SETUP */
+#define UOTGHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) IN */
+#define UOTGHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) OUT */
+#define UOTGHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (UOTGHS_HSTPIPCFG[10]) Automatic Switch */
+#define UOTGHS_HSTPIPCFG_PTYPE_Pos 12
+#define UOTGHS_HSTPIPCFG_PTYPE_Msk (0x3u << UOTGHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Type */
+#define UOTGHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Control */
+#define UOTGHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Isochronous */
+#define UOTGHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Bulk */
+#define UOTGHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Interrupt */
+#define UOTGHS_HSTPIPCFG_PEPNUM_Pos 16
+#define UOTGHS_HSTPIPCFG_PEPNUM_Msk (0xfu << UOTGHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Endpoint Number */
+#define UOTGHS_HSTPIPCFG_PEPNUM(value) ((UOTGHS_HSTPIPCFG_PEPNUM_Msk & ((value) << UOTGHS_HSTPIPCFG_PEPNUM_Pos)))
+#define UOTGHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (UOTGHS_HSTPIPCFG[10]) Ping Enable */
+#define UOTGHS_HSTPIPCFG_INTFRQ_Pos 24
+#define UOTGHS_HSTPIPCFG_INTFRQ_Msk (0xffu << UOTGHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */
+#define UOTGHS_HSTPIPCFG_INTFRQ(value) ((UOTGHS_HSTPIPCFG_INTFRQ_Msk & ((value) << UOTGHS_HSTPIPCFG_INTFRQ_Pos)))
+#define UOTGHS_HSTPIPCFG_BINTERVAL_Pos 24
+#define UOTGHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << UOTGHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) bInterval parameter for the Bulk-Out/Ping transaction */
+#define UOTGHS_HSTPIPCFG_BINTERVAL(value) ((UOTGHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << UOTGHS_HSTPIPCFG_BINTERVAL_Pos)))
+/* -------- UOTGHS_HSTPIPISR[10] : (UOTGHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */
+#define UOTGHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (UOTGHS_HSTPIPISR[10]) Received IN Data Interrupt */
+#define UOTGHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (UOTGHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */
+#define UOTGHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */
+#define UOTGHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[10]) Underflow Interrupt */
+#define UOTGHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (UOTGHS_HSTPIPISR[10]) Pipe Error Interrupt */
+#define UOTGHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (UOTGHS_HSTPIPISR[10]) NAKed Interrupt */
+#define UOTGHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_HSTPIPISR[10]) Overflow Interrupt */
+#define UOTGHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[10]) Received STALLed Interrupt */
+#define UOTGHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[10]) CRC Error Interrupt */
+#define UOTGHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (UOTGHS_HSTPIPISR[10]) Short Packet Interrupt */
+#define UOTGHS_HSTPIPISR_DTSEQ_Pos 8
+#define UOTGHS_HSTPIPISR_DTSEQ_Msk (0x3u << UOTGHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Data Toggle Sequence */
+#define UOTGHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_HSTPIPISR[10]) Data0 toggle sequence */
+#define UOTGHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_HSTPIPISR[10]) Data1 toggle sequence */
+#define UOTGHS_HSTPIPISR_NBUSYBK_Pos 12
+#define UOTGHS_HSTPIPISR_NBUSYBK_Msk (0x3u << UOTGHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Number of Busy Banks */
+#define UOTGHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 0 busy bank (all banks free) */
+#define UOTGHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 1 busy bank */
+#define UOTGHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 2 busy banks */
+#define UOTGHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 3 busy banks */
+#define UOTGHS_HSTPIPISR_CURRBK_Pos 14
+#define UOTGHS_HSTPIPISR_CURRBK_Msk (0x3u << UOTGHS_HSTPIPISR_CURRBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Current Bank */
+#define UOTGHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank0 */
+#define UOTGHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank1 */
+#define UOTGHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank2 */
+#define UOTGHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_HSTPIPISR[10]) Read-write Allowed */
+#define UOTGHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_HSTPIPISR[10]) Configuration OK Status */
+#define UOTGHS_HSTPIPISR_PBYCT_Pos 20
+#define UOTGHS_HSTPIPISR_PBYCT_Msk (0x7ffu << UOTGHS_HSTPIPISR_PBYCT_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Pipe Byte Count */
+/* -------- UOTGHS_HSTPIPICR[10] : (UOTGHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */
+#define UOTGHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */
+#define UOTGHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */
+#define UOTGHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */
+#define UOTGHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[10]) Underflow Interrupt Clear */
+#define UOTGHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPICR[10]) NAKed Interrupt Clear */
+#define UOTGHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPICR[10]) Overflow Interrupt Clear */
+#define UOTGHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */
+#define UOTGHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[10]) CRC Error Interrupt Clear */
+#define UOTGHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPICR[10]) Short Packet Interrupt Clear */
+/* -------- UOTGHS_HSTPIPIFR[10] : (UOTGHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */
+#define UOTGHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */
+#define UOTGHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */
+#define UOTGHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[10]) Underflow Interrupt Set */
+#define UOTGHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */
+#define UOTGHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIFR[10]) NAKed Interrupt Set */
+#define UOTGHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIFR[10]) Overflow Interrupt Set */
+#define UOTGHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */
+#define UOTGHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[10]) CRC Error Interrupt Set */
+#define UOTGHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIFR[10]) Short Packet Interrupt Set */
+#define UOTGHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIFR[10]) Number of Busy Banks Set */
+/* -------- UOTGHS_HSTPIPIMR[10] : (UOTGHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[10]) Underflow Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIMR[10]) NAKed Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIMR[10]) Overflow Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIMR[10]) FIFO Control */
+#define UOTGHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */
+#define UOTGHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Freeze */
+#define UOTGHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIMR[10]) Reset Data Toggle */
+/* -------- UOTGHS_HSTPIPIER[10] : (UOTGHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */
+#define UOTGHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */
+#define UOTGHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */
+#define UOTGHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[10]) Underflow Interrupt Enable */
+#define UOTGHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */
+#define UOTGHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIER[10]) NAKed Interrupt Enable */
+#define UOTGHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIER[10]) Overflow Interrupt Enable */
+#define UOTGHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */
+#define UOTGHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[10]) CRC Error Interrupt Enable */
+#define UOTGHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIER[10]) Short Packet Interrupt Enable */
+#define UOTGHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIER[10]) Number of Busy Banks Enable */
+#define UOTGHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */
+#define UOTGHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Freeze Enable */
+#define UOTGHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIER[10]) Reset Data Toggle Enable */
+/* -------- UOTGHS_HSTPIPIDR[10] : (UOTGHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[10]) Underflow Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIDR[10]) NAKed Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIDR[10]) Overflow Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIDR[10]) Number of Busy Banks Disable */
+#define UOTGHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIDR[10]) FIFO Control Disable */
+#define UOTGHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */
+#define UOTGHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Freeze Disable */
+/* -------- UOTGHS_HSTPIPINRQ[10] : (UOTGHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */
+#define UOTGHS_HSTPIPINRQ_INRQ_Pos 0
+#define UOTGHS_HSTPIPINRQ_INRQ_Msk (0xffu << UOTGHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (UOTGHS_HSTPIPINRQ[10]) IN Request Number before Freeze */
+#define UOTGHS_HSTPIPINRQ_INRQ(value) ((UOTGHS_HSTPIPINRQ_INRQ_Msk & ((value) << UOTGHS_HSTPIPINRQ_INRQ_Pos)))
+#define UOTGHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (UOTGHS_HSTPIPINRQ[10]) IN Request Mode */
+/* -------- UOTGHS_HSTPIPERR[10] : (UOTGHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */
+#define UOTGHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (UOTGHS_HSTPIPERR[10]) Data Toggle Error */
+#define UOTGHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (UOTGHS_HSTPIPERR[10]) Data PID Error */
+#define UOTGHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (UOTGHS_HSTPIPERR[10]) PID Error */
+#define UOTGHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (UOTGHS_HSTPIPERR[10]) Time-Out Error */
+#define UOTGHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (UOTGHS_HSTPIPERR[10]) CRC16 Error */
+#define UOTGHS_HSTPIPERR_COUNTER_Pos 5
+#define UOTGHS_HSTPIPERR_COUNTER_Msk (0x3u << UOTGHS_HSTPIPERR_COUNTER_Pos) /**< \brief (UOTGHS_HSTPIPERR[10]) Error Counter */
+#define UOTGHS_HSTPIPERR_COUNTER(value) ((UOTGHS_HSTPIPERR_COUNTER_Msk & ((value) << UOTGHS_HSTPIPERR_COUNTER_Pos)))
+/* -------- UOTGHS_HSTDMANXTDSC : (UOTGHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_HSTDMANXTDSC) Next Descriptor Address */
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))
+/* -------- UOTGHS_HSTDMAADDRESS : (UOTGHS Offset: N/A) Host DMA Channel Address Register -------- */
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos 0
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_HSTDMAADDRESS) Buffer Address */
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD(value) ((UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos)))
+/* -------- UOTGHS_HSTDMACONTROL : (UOTGHS Offset: N/A) Host DMA Channel Control Register -------- */
+#define UOTGHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMACONTROL) Channel Enable Command */
+#define UOTGHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
+#define UOTGHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Enable (Control) */
+#define UOTGHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Enable Control */
+#define UOTGHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Interrupt Enable */
+#define UOTGHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Interrupt Enable */
+#define UOTGHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */
+#define UOTGHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_HSTDMACONTROL) Burst Lock Enable */
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))
+/* -------- UOTGHS_HSTDMASTATUS : (UOTGHS Offset: N/A) Host DMA Channel Status Register -------- */
+#define UOTGHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Enable Status */
+#define UOTGHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Active Status */
+#define UOTGHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Transfer Status */
+#define UOTGHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Buffer Status */
+#define UOTGHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_HSTDMASTATUS) Descriptor Loaded Status */
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos 16
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_HSTDMASTATUS) Buffer Byte Count */
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT(value) ((UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos)))
+/* -------- UOTGHS_CTRL : (UOTGHS Offset: 0x0800) General Control Register -------- */
+#define UOTGHS_CTRL_IDTE (0x1u << 0) /**< \brief (UOTGHS_CTRL) ID Transition Interrupt Enable */
+#define UOTGHS_CTRL_VBUSTE (0x1u << 1) /**< \brief (UOTGHS_CTRL) VBus Transition Interrupt Enable */
+#define UOTGHS_CTRL_SRPE (0x1u << 2) /**< \brief (UOTGHS_CTRL) SRP Interrupt Enable */
+#define UOTGHS_CTRL_VBERRE (0x1u << 3) /**< \brief (UOTGHS_CTRL) VBus Error Interrupt Enable */
+#define UOTGHS_CTRL_BCERRE (0x1u << 4) /**< \brief (UOTGHS_CTRL) B-Connection Error Interrupt Enable */
+#define UOTGHS_CTRL_ROLEEXE (0x1u << 5) /**< \brief (UOTGHS_CTRL) Role Exchange Interrupt Enable */
+#define UOTGHS_CTRL_HNPERRE (0x1u << 6) /**< \brief (UOTGHS_CTRL) HNP Error Interrupt Enable */
+#define UOTGHS_CTRL_STOE (0x1u << 7) /**< \brief (UOTGHS_CTRL) Suspend Time-Out Interrupt Enable */
+#define UOTGHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (UOTGHS_CTRL) VBus Hardware Control */
+#define UOTGHS_CTRL_SRPSEL (0x1u << 9) /**< \brief (UOTGHS_CTRL) SRP Selection */
+#define UOTGHS_CTRL_SRPREQ (0x1u << 10) /**< \brief (UOTGHS_CTRL) SRP Request */
+#define UOTGHS_CTRL_HNPREQ (0x1u << 11) /**< \brief (UOTGHS_CTRL) HNP Request */
+#define UOTGHS_CTRL_OTGPADE (0x1u << 12) /**< \brief (UOTGHS_CTRL) OTG Pad Enable */
+#define UOTGHS_CTRL_VBUSPO (0x1u << 13) /**< \brief (UOTGHS_CTRL) VBus Polarity Off */
+#define UOTGHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (UOTGHS_CTRL) Freeze USB Clock */
+#define UOTGHS_CTRL_USBE (0x1u << 15) /**< \brief (UOTGHS_CTRL) UOTGHS Enable */
+#define UOTGHS_CTRL_TIMVALUE_Pos 16
+#define UOTGHS_CTRL_TIMVALUE_Msk (0x3u << UOTGHS_CTRL_TIMVALUE_Pos) /**< \brief (UOTGHS_CTRL) Timer Value */
+#define UOTGHS_CTRL_TIMVALUE(value) ((UOTGHS_CTRL_TIMVALUE_Msk & ((value) << UOTGHS_CTRL_TIMVALUE_Pos)))
+#define UOTGHS_CTRL_TIMPAGE_Pos 20
+#define UOTGHS_CTRL_TIMPAGE_Msk (0x3u << UOTGHS_CTRL_TIMPAGE_Pos) /**< \brief (UOTGHS_CTRL) Timer Page */
+#define UOTGHS_CTRL_TIMPAGE(value) ((UOTGHS_CTRL_TIMPAGE_Msk & ((value) << UOTGHS_CTRL_TIMPAGE_Pos)))
+#define UOTGHS_CTRL_UNLOCK (0x1u << 22) /**< \brief (UOTGHS_CTRL) Timer Access Unlock */
+#define UOTGHS_CTRL_UIDE (0x1u << 24) /**< \brief (UOTGHS_CTRL) UOTGID Pin Enable */
+#define UOTGHS_CTRL_UIDE_UIMOD (0x0u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UIMOD bit. */
+#define UOTGHS_CTRL_UIDE_UOTGID (0x1u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UOTGID input pin. */
+#define UOTGHS_CTRL_UIMOD (0x1u << 25) /**< \brief (UOTGHS_CTRL) UOTGHS Mode */
+#define UOTGHS_CTRL_UIMOD_Host (0x0u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB host mode. */
+#define UOTGHS_CTRL_UIMOD_Device (0x1u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB device mode. */
+/* -------- UOTGHS_SR : (UOTGHS Offset: 0x0804) General Status Register -------- */
+#define UOTGHS_SR_IDTI (0x1u << 0) /**< \brief (UOTGHS_SR) ID Transition Interrupt */
+#define UOTGHS_SR_VBUSTI (0x1u << 1) /**< \brief (UOTGHS_SR) VBus Transition Interrupt */
+#define UOTGHS_SR_SRPI (0x1u << 2) /**< \brief (UOTGHS_SR) SRP Interrupt */
+#define UOTGHS_SR_VBERRI (0x1u << 3) /**< \brief (UOTGHS_SR) VBus Error Interrupt */
+#define UOTGHS_SR_BCERRI (0x1u << 4) /**< \brief (UOTGHS_SR) B-Connection Error Interrupt */
+#define UOTGHS_SR_ROLEEXI (0x1u << 5) /**< \brief (UOTGHS_SR) Role Exchange Interrupt */
+#define UOTGHS_SR_HNPERRI (0x1u << 6) /**< \brief (UOTGHS_SR) HNP Error Interrupt */
+#define UOTGHS_SR_STOI (0x1u << 7) /**< \brief (UOTGHS_SR) Suspend Time-Out Interrupt */
+#define UOTGHS_SR_VBUSRQ (0x1u << 9) /**< \brief (UOTGHS_SR) VBus Request */
+#define UOTGHS_SR_ID (0x1u << 10) /**< \brief (UOTGHS_SR) UOTGID Pin State */
+#define UOTGHS_SR_VBUS (0x1u << 11) /**< \brief (UOTGHS_SR) VBus Level */
+#define UOTGHS_SR_SPEED_Pos 12
+#define UOTGHS_SR_SPEED_Msk (0x3u << UOTGHS_SR_SPEED_Pos) /**< \brief (UOTGHS_SR) Speed Status */
+#define UOTGHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (UOTGHS_SR) Full-Speed mode */
+#define UOTGHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (UOTGHS_SR) High-Speed mode */
+#define UOTGHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (UOTGHS_SR) Low-Speed mode */
+#define UOTGHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (UOTGHS_SR) UTMI Clock Usable */
+/* -------- UOTGHS_SCR : (UOTGHS Offset: 0x0808) General Status Clear Register -------- */
+#define UOTGHS_SCR_IDTIC (0x1u << 0) /**< \brief (UOTGHS_SCR) ID Transition Interrupt Clear */
+#define UOTGHS_SCR_VBUSTIC (0x1u << 1) /**< \brief (UOTGHS_SCR) VBus Transition Interrupt Clear */
+#define UOTGHS_SCR_SRPIC (0x1u << 2) /**< \brief (UOTGHS_SCR) SRP Interrupt Clear */
+#define UOTGHS_SCR_VBERRIC (0x1u << 3) /**< \brief (UOTGHS_SCR) VBus Error Interrupt Clear */
+#define UOTGHS_SCR_BCERRIC (0x1u << 4) /**< \brief (UOTGHS_SCR) B-Connection Error Interrupt Clear */
+#define UOTGHS_SCR_ROLEEXIC (0x1u << 5) /**< \brief (UOTGHS_SCR) Role Exchange Interrupt Clear */
+#define UOTGHS_SCR_HNPERRIC (0x1u << 6) /**< \brief (UOTGHS_SCR) HNP Error Interrupt Clear */
+#define UOTGHS_SCR_STOIC (0x1u << 7) /**< \brief (UOTGHS_SCR) Suspend Time-Out Interrupt Clear */
+#define UOTGHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (UOTGHS_SCR) VBus Request Clear */
+/* -------- UOTGHS_SFR : (UOTGHS Offset: 0x080C) General Status Set Register -------- */
+#define UOTGHS_SFR_IDTIS (0x1u << 0) /**< \brief (UOTGHS_SFR) ID Transition Interrupt Set */
+#define UOTGHS_SFR_VBUSTIS (0x1u << 1) /**< \brief (UOTGHS_SFR) VBus Transition Interrupt Set */
+#define UOTGHS_SFR_SRPIS (0x1u << 2) /**< \brief (UOTGHS_SFR) SRP Interrupt Set */
+#define UOTGHS_SFR_VBERRIS (0x1u << 3) /**< \brief (UOTGHS_SFR) VBus Error Interrupt Set */
+#define UOTGHS_SFR_BCERRIS (0x1u << 4) /**< \brief (UOTGHS_SFR) B-Connection Error Interrupt Set */
+#define UOTGHS_SFR_ROLEEXIS (0x1u << 5) /**< \brief (UOTGHS_SFR) Role Exchange Interrupt Set */
+#define UOTGHS_SFR_HNPERRIS (0x1u << 6) /**< \brief (UOTGHS_SFR) HNP Error Interrupt Set */
+#define UOTGHS_SFR_STOIS (0x1u << 7) /**< \brief (UOTGHS_SFR) Suspend Time-Out Interrupt Set */
+#define UOTGHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (UOTGHS_SFR) VBus Request Set */
+/* -------- UOTGHS_FSM : (UOTGHS Offset: 0x082C) General Finite State Machine Register -------- */
+#define UOTGHS_FSM_DRDSTATE_Pos 0
+#define UOTGHS_FSM_DRDSTATE_Msk (0xfu << UOTGHS_FSM_DRDSTATE_Pos) /**< \brief (UOTGHS_FSM) */
+#define UOTGHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (UOTGHS_FSM) This is the start state for A-devices (when the ID pin is 0) */
+#define UOTGHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */
+#define UOTGHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */
+#define UOTGHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device that operates in Host mode is operational. */
+#define UOTGHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (UOTGHS_FSM) The A-device operating as a host is in the suspend mode. */
+#define UOTGHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (UOTGHS_FSM) The A-device operates as a peripheral. */
+#define UOTGHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */
+#define UOTGHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */
+#define UOTGHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */
+#define UOTGHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (UOTGHS_FSM) This is the start state for B-device (when the ID pin is 1). */
+#define UOTGHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the peripheral. */
+#define UOTGHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */
+#define UOTGHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host. */
+#define UOTGHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */
+#define UOTGHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the Host. */
+#define UOTGHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Usart hardware registers */
+typedef struct {
+ WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */
+ RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */
+ WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+ WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+ RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+ RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+ RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+ WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+ RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+ RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+ RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+ RoReg Reserved1[5];
+ RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+ RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+ RoReg Reserved2[1];
+ RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+ RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
+ RwReg US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */
+ RwReg US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */
+ RoReg Reserved3[34];
+ RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+ RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+ RoReg Reserved4[5];
+ RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+ RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+ RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+ RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+ RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+ RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+ RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+ RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+ WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+ RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* __ASSEMBLY__ */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */
+#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) */
+#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN Master */
+#define US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave */
+#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */
+#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */
+#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */
+#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
+#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */
+#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */
+#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */
+#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */
+#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */
+#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */
+#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */
+#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
+#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */
+#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */
+#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */
+#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */
+#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */
+#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */
+#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */
+#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
+#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */
+#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */
+#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */
+#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */
+#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt */
+#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received */
+#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received */
+#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
+#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error */
+#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error */
+#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error */
+#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error */
+#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
+#define US_MAN_TX_PL_Pos 0
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
+#define US_MAN_TX_PP_Pos 8
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
+#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
+#define US_MAN_RX_PL_Pos 16
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
+#define US_MAN_RX_PP_Pos 24
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
+#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN) */
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
+/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */
+#define US_LINMR_NACT_Pos 0
+#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */
+#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */
+#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */
+#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */
+#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */
+#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */
+#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */
+#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */
+#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */
+#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */
+#define US_LINMR_DLC_Pos 8
+#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */
+#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))
+#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) PDC Mode */
+/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */
+#define US_LINIR_IDCHR_Pos 0
+#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */
+#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_WDT Watchdog Timer */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Wdt hardware registers */
+typedef struct {
+ WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+ RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+ RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* __ASSEMBLY__ */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+/*@}*/
+
+/* ************************************************************************** */
+/* REGISTER ACCESS DEFINITIONS FOR SAM3XA */
+/* ************************************************************************** */
+/** \addtogroup SAM3XA_reg Registers Access Definitions */
+/*@{*/
+
+/* ========== Register definition for HSMCI peripheral ========== */
+#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_DMA REG_ACCESS(RwReg, 0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
+#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_FIFO REG_ACCESS(RwReg, 0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+/* ========== Register definition for SSC peripheral ========== */
+#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+/* ========== Register definition for SPI0 peripheral ========== */
+#define REG_SPI0_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI0) Control Register */
+#define REG_SPI0_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI0) Mode Register */
+#define REG_SPI0_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI0) Receive Data Register */
+#define REG_SPI0_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
+#define REG_SPI0_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI0) Status Register */
+#define REG_SPI0_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
+#define REG_SPI0_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
+#define REG_SPI0_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
+#define REG_SPI0_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI0) Chip Select Register */
+#define REG_SPI0_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */
+#define REG_SPI0_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
+/* ========== Register definition for SPI1 peripheral ========== */
+#define REG_SPI1_CR REG_ACCESS(WoReg, 0x4000C000U) /**< \brief (SPI1) Control Register */
+#define REG_SPI1_MR REG_ACCESS(RwReg, 0x4000C004U) /**< \brief (SPI1) Mode Register */
+#define REG_SPI1_RDR REG_ACCESS(RoReg, 0x4000C008U) /**< \brief (SPI1) Receive Data Register */
+#define REG_SPI1_TDR REG_ACCESS(WoReg, 0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */
+#define REG_SPI1_SR REG_ACCESS(RoReg, 0x4000C010U) /**< \brief (SPI1) Status Register */
+#define REG_SPI1_IER REG_ACCESS(WoReg, 0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */
+#define REG_SPI1_IDR REG_ACCESS(WoReg, 0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */
+#define REG_SPI1_IMR REG_ACCESS(RoReg, 0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */
+#define REG_SPI1_CSR REG_ACCESS(RwReg, 0x4000C030U) /**< \brief (SPI1) Chip Select Register */
+#define REG_SPI1_WPMR REG_ACCESS(RwReg, 0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */
+#define REG_SPI1_WPSR REG_ACCESS(RoReg, 0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */
+/* ========== Register definition for TC0 peripheral ========== */
+#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0 REG_ACCESS(RwReg, 0x40080008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1 REG_ACCESS(RwReg, 0x40080048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2 REG_ACCESS(RwReg, 0x40080088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400800C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400800C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR REG_ACCESS(RwReg, 0x400800D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400800E4U) /**< \brief (TC0) Write Protect Mode Register */
+/* ========== Register definition for TC1 peripheral ========== */
+#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40084000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40084004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0 REG_ACCESS(RwReg, 0x40084008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40084010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40084014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40084018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4008401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40084020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40084024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40084028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4008402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40084040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40084044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1 REG_ACCESS(RwReg, 0x40084048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40084050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40084054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40084058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4008405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40084060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40084064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40084068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4008406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40084080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40084084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2 REG_ACCESS(RwReg, 0x40084088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40084090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40084094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40084098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4008409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400840A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400840A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400840A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400840ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400840C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400840C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400840C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400840CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400840D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400840D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR REG_ACCESS(RwReg, 0x400840D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400840E4U) /**< \brief (TC1) Write Protect Mode Register */
+/* ========== Register definition for TC2 peripheral ========== */
+#define REG_TC2_CCR0 REG_ACCESS(WoReg, 0x40088000U) /**< \brief (TC2) Channel Control Register (channel = 0) */
+#define REG_TC2_CMR0 REG_ACCESS(RwReg, 0x40088004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */
+#define REG_TC2_SMMR0 REG_ACCESS(RwReg, 0x40088008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC2_CV0 REG_ACCESS(RoReg, 0x40088010U) /**< \brief (TC2) Counter Value (channel = 0) */
+#define REG_TC2_RA0 REG_ACCESS(RwReg, 0x40088014U) /**< \brief (TC2) Register A (channel = 0) */
+#define REG_TC2_RB0 REG_ACCESS(RwReg, 0x40088018U) /**< \brief (TC2) Register B (channel = 0) */
+#define REG_TC2_RC0 REG_ACCESS(RwReg, 0x4008801CU) /**< \brief (TC2) Register C (channel = 0) */
+#define REG_TC2_SR0 REG_ACCESS(RoReg, 0x40088020U) /**< \brief (TC2) Status Register (channel = 0) */
+#define REG_TC2_IER0 REG_ACCESS(WoReg, 0x40088024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */
+#define REG_TC2_IDR0 REG_ACCESS(WoReg, 0x40088028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */
+#define REG_TC2_IMR0 REG_ACCESS(RoReg, 0x4008802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */
+#define REG_TC2_CCR1 REG_ACCESS(WoReg, 0x40088040U) /**< \brief (TC2) Channel Control Register (channel = 1) */
+#define REG_TC2_CMR1 REG_ACCESS(RwReg, 0x40088044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */
+#define REG_TC2_SMMR1 REG_ACCESS(RwReg, 0x40088048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC2_CV1 REG_ACCESS(RoReg, 0x40088050U) /**< \brief (TC2) Counter Value (channel = 1) */
+#define REG_TC2_RA1 REG_ACCESS(RwReg, 0x40088054U) /**< \brief (TC2) Register A (channel = 1) */
+#define REG_TC2_RB1 REG_ACCESS(RwReg, 0x40088058U) /**< \brief (TC2) Register B (channel = 1) */
+#define REG_TC2_RC1 REG_ACCESS(RwReg, 0x4008805CU) /**< \brief (TC2) Register C (channel = 1) */
+#define REG_TC2_SR1 REG_ACCESS(RoReg, 0x40088060U) /**< \brief (TC2) Status Register (channel = 1) */
+#define REG_TC2_IER1 REG_ACCESS(WoReg, 0x40088064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */
+#define REG_TC2_IDR1 REG_ACCESS(WoReg, 0x40088068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */
+#define REG_TC2_IMR1 REG_ACCESS(RoReg, 0x4008806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */
+#define REG_TC2_CCR2 REG_ACCESS(WoReg, 0x40088080U) /**< \brief (TC2) Channel Control Register (channel = 2) */
+#define REG_TC2_CMR2 REG_ACCESS(RwReg, 0x40088084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */
+#define REG_TC2_SMMR2 REG_ACCESS(RwReg, 0x40088088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC2_CV2 REG_ACCESS(RoReg, 0x40088090U) /**< \brief (TC2) Counter Value (channel = 2) */
+#define REG_TC2_RA2 REG_ACCESS(RwReg, 0x40088094U) /**< \brief (TC2) Register A (channel = 2) */
+#define REG_TC2_RB2 REG_ACCESS(RwReg, 0x40088098U) /**< \brief (TC2) Register B (channel = 2) */
+#define REG_TC2_RC2 REG_ACCESS(RwReg, 0x4008809CU) /**< \brief (TC2) Register C (channel = 2) */
+#define REG_TC2_SR2 REG_ACCESS(RoReg, 0x400880A0U) /**< \brief (TC2) Status Register (channel = 2) */
+#define REG_TC2_IER2 REG_ACCESS(WoReg, 0x400880A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */
+#define REG_TC2_IDR2 REG_ACCESS(WoReg, 0x400880A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */
+#define REG_TC2_IMR2 REG_ACCESS(RoReg, 0x400880ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */
+#define REG_TC2_BCR REG_ACCESS(WoReg, 0x400880C0U) /**< \brief (TC2) Block Control Register */
+#define REG_TC2_BMR REG_ACCESS(RwReg, 0x400880C4U) /**< \brief (TC2) Block Mode Register */
+#define REG_TC2_QIER REG_ACCESS(WoReg, 0x400880C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */
+#define REG_TC2_QIDR REG_ACCESS(WoReg, 0x400880CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */
+#define REG_TC2_QIMR REG_ACCESS(RoReg, 0x400880D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */
+#define REG_TC2_QISR REG_ACCESS(RoReg, 0x400880D4U) /**< \brief (TC2) QDEC Interrupt Status Register */
+#define REG_TC2_FMR REG_ACCESS(RwReg, 0x400880D8U) /**< \brief (TC2) Fault Mode Register */
+#define REG_TC2_WPMR REG_ACCESS(RwReg, 0x400880E4U) /**< \brief (TC2) Write Protect Mode Register */
+/* ========== Register definition for TWI0 peripheral ========== */
+#define REG_TWI0_CR REG_ACCESS(WoReg, 0x4008C000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x4008C004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x4008C008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4008C00CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x4008C010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR REG_ACCESS(RoReg, 0x4008C020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER REG_ACCESS(WoReg, 0x4008C024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x4008C028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4008C02CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x4008C030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR REG_ACCESS(WoReg, 0x4008C034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x4008C100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x4008C104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x4008C108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4008C10CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x4008C110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x4008C114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x4008C118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4008C11CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x4008C120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x4008C124U) /**< \brief (TWI0) Transfer Status Register */
+/* ========== Register definition for TWI1 peripheral ========== */
+#define REG_TWI1_CR REG_ACCESS(WoReg, 0x40090000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x40090004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x40090008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4009000CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x40090010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR REG_ACCESS(RoReg, 0x40090020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER REG_ACCESS(WoReg, 0x40090024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x40090028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x40090030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR REG_ACCESS(WoReg, 0x40090034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x40090100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x40090104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x40090108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4009010CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x40090110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x40090114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x40090118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4009011CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x40090120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x40090124U) /**< \brief (TWI1) Transfer Status Register */
+/* ========== Register definition for PWM peripheral ========== */
+#define REG_PWM_CLK REG_ACCESS(RwReg, 0x40094000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40094004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40094008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR REG_ACCESS(RoReg, 0x4009400CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM REG_ACCESS(RwReg, 0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV REG_ACCESS(RwReg, 0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS REG_ACCESS(RwReg, 0x40094048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC REG_ACCESS(WoReg, 0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR REG_ACCESS(RoReg, 0x40094060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR REG_ACCESS(WoReg, 0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV REG_ACCESS(RwReg, 0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE1 REG_ACCESS(RwReg, 0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */
+#define REG_PWM_FPE2 REG_ACCESS(RwReg, 0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */
+#define REG_PWM_ELMR REG_ACCESS(RwReg, 0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR REG_ACCESS(RwReg, 0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_RPR REG_ACCESS(RwReg, 0x40094100U) /**< \brief (PWM) Receive Pointer Register */
+#define REG_PWM_RCR REG_ACCESS(RwReg, 0x40094104U) /**< \brief (PWM) Receive Counter Register */
+#define REG_PWM_TPR REG_ACCESS(RwReg, 0x40094108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4009410CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x40094110U) /**< \brief (PWM) Receive Next Pointer Register */
+#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x40094114U) /**< \brief (PWM) Receive Next Counter Register */
+#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x40094120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x40094124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0 REG_ACCESS(RwReg, 0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0 REG_ACCESS(WoReg, 0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0 REG_ACCESS(RwReg, 0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0 REG_ACCESS(WoReg, 0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1 REG_ACCESS(RwReg, 0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1 REG_ACCESS(WoReg, 0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1 REG_ACCESS(RwReg, 0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1 REG_ACCESS(WoReg, 0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2 REG_ACCESS(RwReg, 0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2 REG_ACCESS(WoReg, 0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2 REG_ACCESS(RwReg, 0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2 REG_ACCESS(WoReg, 0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3 REG_ACCESS(RwReg, 0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3 REG_ACCESS(WoReg, 0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3 REG_ACCESS(RwReg, 0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3 REG_ACCESS(WoReg, 0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4 REG_ACCESS(RwReg, 0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4 REG_ACCESS(WoReg, 0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4 REG_ACCESS(RwReg, 0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4 REG_ACCESS(WoReg, 0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5 REG_ACCESS(RwReg, 0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5 REG_ACCESS(WoReg, 0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5 REG_ACCESS(RwReg, 0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5 REG_ACCESS(WoReg, 0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6 REG_ACCESS(RwReg, 0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6 REG_ACCESS(WoReg, 0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6 REG_ACCESS(RwReg, 0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6 REG_ACCESS(WoReg, 0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7 REG_ACCESS(RwReg, 0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7 REG_ACCESS(WoReg, 0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7 REG_ACCESS(RwReg, 0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7 REG_ACCESS(WoReg, 0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#define REG_PWM_CMR4 REG_ACCESS(RwReg, 0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */
+#define REG_PWM_CDTY4 REG_ACCESS(RwReg, 0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */
+#define REG_PWM_CDTYUPD4 REG_ACCESS(WoReg, 0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */
+#define REG_PWM_CPRD4 REG_ACCESS(RwReg, 0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */
+#define REG_PWM_CPRDUPD4 REG_ACCESS(WoReg, 0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */
+#define REG_PWM_CCNT4 REG_ACCESS(RoReg, 0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */
+#define REG_PWM_DT4 REG_ACCESS(RwReg, 0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */
+#define REG_PWM_DTUPD4 REG_ACCESS(WoReg, 0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */
+#define REG_PWM_CMR5 REG_ACCESS(RwReg, 0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */
+#define REG_PWM_CDTY5 REG_ACCESS(RwReg, 0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */
+#define REG_PWM_CDTYUPD5 REG_ACCESS(WoReg, 0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */
+#define REG_PWM_CPRD5 REG_ACCESS(RwReg, 0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */
+#define REG_PWM_CPRDUPD5 REG_ACCESS(WoReg, 0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */
+#define REG_PWM_CCNT5 REG_ACCESS(RoReg, 0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */
+#define REG_PWM_DT5 REG_ACCESS(RwReg, 0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */
+#define REG_PWM_DTUPD5 REG_ACCESS(WoReg, 0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */
+#define REG_PWM_CMR6 REG_ACCESS(RwReg, 0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */
+#define REG_PWM_CDTY6 REG_ACCESS(RwReg, 0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */
+#define REG_PWM_CDTYUPD6 REG_ACCESS(WoReg, 0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */
+#define REG_PWM_CPRD6 REG_ACCESS(RwReg, 0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */
+#define REG_PWM_CPRDUPD6 REG_ACCESS(WoReg, 0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */
+#define REG_PWM_CCNT6 REG_ACCESS(RoReg, 0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */
+#define REG_PWM_DT6 REG_ACCESS(RwReg, 0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */
+#define REG_PWM_DTUPD6 REG_ACCESS(WoReg, 0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */
+#define REG_PWM_CMR7 REG_ACCESS(RwReg, 0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */
+#define REG_PWM_CDTY7 REG_ACCESS(RwReg, 0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */
+#define REG_PWM_CDTYUPD7 REG_ACCESS(WoReg, 0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */
+#define REG_PWM_CPRD7 REG_ACCESS(RwReg, 0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */
+#define REG_PWM_CPRDUPD7 REG_ACCESS(WoReg, 0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */
+#define REG_PWM_CCNT7 REG_ACCESS(RoReg, 0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */
+#define REG_PWM_DT7 REG_ACCESS(RwReg, 0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */
+#define REG_PWM_DTUPD7 REG_ACCESS(WoReg, 0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */
+/* ========== Register definition for USART0 peripheral ========== */
+#define REG_USART0_CR REG_ACCESS(WoReg, 0x40098000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR REG_ACCESS(RwReg, 0x40098004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER REG_ACCESS(WoReg, 0x40098008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4009800CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40098010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40098014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40098018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR REG_ACCESS(WoReg, 0x4009801CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40098020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40098024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40098028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40098040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER REG_ACCESS(RoReg, 0x40098044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF REG_ACCESS(RwReg, 0x4009804CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40098050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_LINMR REG_ACCESS(RwReg, 0x40098054U) /**< \brief (USART0) LIN Mode Register */
+#define REG_USART0_LINIR REG_ACCESS(RwReg, 0x40098058U) /**< \brief (USART0) LIN Identifier Register */
+#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400980E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400980E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40098100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40098104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40098108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4009810CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40098110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40098114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40098118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4009811CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40098120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40098124U) /**< \brief (USART0) Transfer Status Register */
+/* ========== Register definition for USART1 peripheral ========== */
+#define REG_USART1_CR REG_ACCESS(WoReg, 0x4009C000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR REG_ACCESS(RwReg, 0x4009C004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER REG_ACCESS(WoReg, 0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR REG_ACCESS(RoReg, 0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR REG_ACCESS(RoReg, 0x4009C014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR REG_ACCESS(RoReg, 0x4009C018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR REG_ACCESS(WoReg, 0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER REG_ACCESS(RoReg, 0x4009C044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF REG_ACCESS(RwReg, 0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN REG_ACCESS(RwReg, 0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_LINMR REG_ACCESS(RwReg, 0x4009C054U) /**< \brief (USART1) LIN Mode Register */
+#define REG_USART1_LINIR REG_ACCESS(RwReg, 0x4009C058U) /**< \brief (USART1) LIN Identifier Register */
+#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_RPR REG_ACCESS(RwReg, 0x4009C100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR REG_ACCESS(RwReg, 0x4009C104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR REG_ACCESS(RwReg, 0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x4009C120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x4009C124U) /**< \brief (USART1) Transfer Status Register */
+/* ========== Register definition for USART2 peripheral ========== */
+#define REG_USART2_CR REG_ACCESS(WoReg, 0x400A0000U) /**< \brief (USART2) Control Register */
+#define REG_USART2_MR REG_ACCESS(RwReg, 0x400A0004U) /**< \brief (USART2) Mode Register */
+#define REG_USART2_IER REG_ACCESS(WoReg, 0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */
+#define REG_USART2_IDR REG_ACCESS(WoReg, 0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */
+#define REG_USART2_IMR REG_ACCESS(RoReg, 0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */
+#define REG_USART2_CSR REG_ACCESS(RoReg, 0x400A0014U) /**< \brief (USART2) Channel Status Register */
+#define REG_USART2_RHR REG_ACCESS(RoReg, 0x400A0018U) /**< \brief (USART2) Receiver Holding Register */
+#define REG_USART2_THR REG_ACCESS(WoReg, 0x400A001CU) /**< \brief (USART2) Transmitter Holding Register */
+#define REG_USART2_BRGR REG_ACCESS(RwReg, 0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */
+#define REG_USART2_RTOR REG_ACCESS(RwReg, 0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */
+#define REG_USART2_TTGR REG_ACCESS(RwReg, 0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */
+#define REG_USART2_FIDI REG_ACCESS(RwReg, 0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */
+#define REG_USART2_NER REG_ACCESS(RoReg, 0x400A0044U) /**< \brief (USART2) Number of Errors Register */
+#define REG_USART2_IF REG_ACCESS(RwReg, 0x400A004CU) /**< \brief (USART2) IrDA Filter Register */
+#define REG_USART2_MAN REG_ACCESS(RwReg, 0x400A0050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
+#define REG_USART2_LINMR REG_ACCESS(RwReg, 0x400A0054U) /**< \brief (USART2) LIN Mode Register */
+#define REG_USART2_LINIR REG_ACCESS(RwReg, 0x400A0058U) /**< \brief (USART2) LIN Identifier Register */
+#define REG_USART2_WPMR REG_ACCESS(RwReg, 0x400A00E4U) /**< \brief (USART2) Write Protect Mode Register */
+#define REG_USART2_WPSR REG_ACCESS(RoReg, 0x400A00E8U) /**< \brief (USART2) Write Protect Status Register */
+#define REG_USART2_RPR REG_ACCESS(RwReg, 0x400A0100U) /**< \brief (USART2) Receive Pointer Register */
+#define REG_USART2_RCR REG_ACCESS(RwReg, 0x400A0104U) /**< \brief (USART2) Receive Counter Register */
+#define REG_USART2_TPR REG_ACCESS(RwReg, 0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */
+#define REG_USART2_TCR REG_ACCESS(RwReg, 0x400A010CU) /**< \brief (USART2) Transmit Counter Register */
+#define REG_USART2_RNPR REG_ACCESS(RwReg, 0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */
+#define REG_USART2_RNCR REG_ACCESS(RwReg, 0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */
+#define REG_USART2_TNPR REG_ACCESS(RwReg, 0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */
+#define REG_USART2_TNCR REG_ACCESS(RwReg, 0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */
+#define REG_USART2_PTCR REG_ACCESS(WoReg, 0x400A0120U) /**< \brief (USART2) Transfer Control Register */
+#define REG_USART2_PTSR REG_ACCESS(RoReg, 0x400A0124U) /**< \brief (USART2) Transfer Status Register */
+/* ========== Register definition for USART3 peripheral ========== */
+#define REG_USART3_CR REG_ACCESS(WoReg, 0x400A4000U) /**< \brief (USART3) Control Register */
+#define REG_USART3_MR REG_ACCESS(RwReg, 0x400A4004U) /**< \brief (USART3) Mode Register */
+#define REG_USART3_IER REG_ACCESS(WoReg, 0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */
+#define REG_USART3_IDR REG_ACCESS(WoReg, 0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */
+#define REG_USART3_IMR REG_ACCESS(RoReg, 0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */
+#define REG_USART3_CSR REG_ACCESS(RoReg, 0x400A4014U) /**< \brief (USART3) Channel Status Register */
+#define REG_USART3_RHR REG_ACCESS(RoReg, 0x400A4018U) /**< \brief (USART3) Receiver Holding Register */
+#define REG_USART3_THR REG_ACCESS(WoReg, 0x400A401CU) /**< \brief (USART3) Transmitter Holding Register */
+#define REG_USART3_BRGR REG_ACCESS(RwReg, 0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */
+#define REG_USART3_RTOR REG_ACCESS(RwReg, 0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */
+#define REG_USART3_TTGR REG_ACCESS(RwReg, 0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */
+#define REG_USART3_FIDI REG_ACCESS(RwReg, 0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */
+#define REG_USART3_NER REG_ACCESS(RoReg, 0x400A4044U) /**< \brief (USART3) Number of Errors Register */
+#define REG_USART3_IF REG_ACCESS(RwReg, 0x400A404CU) /**< \brief (USART3) IrDA Filter Register */
+#define REG_USART3_MAN REG_ACCESS(RwReg, 0x400A4050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
+#define REG_USART3_LINMR REG_ACCESS(RwReg, 0x400A4054U) /**< \brief (USART3) LIN Mode Register */
+#define REG_USART3_LINIR REG_ACCESS(RwReg, 0x400A4058U) /**< \brief (USART3) LIN Identifier Register */
+#define REG_USART3_WPMR REG_ACCESS(RwReg, 0x400A40E4U) /**< \brief (USART3) Write Protect Mode Register */
+#define REG_USART3_WPSR REG_ACCESS(RoReg, 0x400A40E8U) /**< \brief (USART3) Write Protect Status Register */
+#define REG_USART3_RPR REG_ACCESS(RwReg, 0x400A4100U) /**< \brief (USART3) Receive Pointer Register */
+#define REG_USART3_RCR REG_ACCESS(RwReg, 0x400A4104U) /**< \brief (USART3) Receive Counter Register */
+#define REG_USART3_TPR REG_ACCESS(RwReg, 0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */
+#define REG_USART3_TCR REG_ACCESS(RwReg, 0x400A410CU) /**< \brief (USART3) Transmit Counter Register */
+#define REG_USART3_RNPR REG_ACCESS(RwReg, 0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */
+#define REG_USART3_RNCR REG_ACCESS(RwReg, 0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */
+#define REG_USART3_TNPR REG_ACCESS(RwReg, 0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */
+#define REG_USART3_TNCR REG_ACCESS(RwReg, 0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */
+#define REG_USART3_PTCR REG_ACCESS(WoReg, 0x400A4120U) /**< \brief (USART3) Transfer Control Register */
+#define REG_USART3_PTSR REG_ACCESS(RoReg, 0x400A4124U) /**< \brief (USART3) Transfer Status Register */
+/* ========== Register definition for UOTGHS peripheral ========== */
+#define REG_UOTGHS_DEVCTRL REG_ACCESS(RwReg, 0x400AC000U) /**< \brief (UOTGHS) Device General Control Register */
+#define REG_UOTGHS_DEVISR REG_ACCESS(RoReg, 0x400AC004U) /**< \brief (UOTGHS) Device Global Interrupt Status Register */
+#define REG_UOTGHS_DEVICR REG_ACCESS(WoReg, 0x400AC008U) /**< \brief (UOTGHS) Device Global Interrupt Clear Register */
+#define REG_UOTGHS_DEVIFR REG_ACCESS(WoReg, 0x400AC00CU) /**< \brief (UOTGHS) Device Global Interrupt Set Register */
+#define REG_UOTGHS_DEVIMR REG_ACCESS(RoReg, 0x400AC010U) /**< \brief (UOTGHS) Device Global Interrupt Mask Register */
+#define REG_UOTGHS_DEVIDR REG_ACCESS(WoReg, 0x400AC014U) /**< \brief (UOTGHS) Device Global Interrupt Disable Register */
+#define REG_UOTGHS_DEVIER REG_ACCESS(WoReg, 0x400AC018U) /**< \brief (UOTGHS) Device Global Interrupt Enable Register */
+#define REG_UOTGHS_DEVEPT REG_ACCESS(RwReg, 0x400AC01CU) /**< \brief (UOTGHS) Device Endpoint Register */
+#define REG_UOTGHS_DEVFNUM REG_ACCESS(RoReg, 0x400AC020U) /**< \brief (UOTGHS) Device Frame Number Register */
+#define REG_UOTGHS_DEVEPTCFG REG_ACCESS(RwReg, 0x400AC100U) /**< \brief (UOTGHS) Device Endpoint Configuration Register (n = 0) */
+#define REG_UOTGHS_DEVEPTISR REG_ACCESS(RoReg, 0x400AC130U) /**< \brief (UOTGHS) Device Endpoint Status Register (n = 0) */
+#define REG_UOTGHS_DEVEPTICR REG_ACCESS(WoReg, 0x400AC160U) /**< \brief (UOTGHS) Device Endpoint Clear Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIFR REG_ACCESS(WoReg, 0x400AC190U) /**< \brief (UOTGHS) Device Endpoint Set Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIMR REG_ACCESS(RoReg, 0x400AC1C0U) /**< \brief (UOTGHS) Device Endpoint Mask Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIER REG_ACCESS(WoReg, 0x400AC1F0U) /**< \brief (UOTGHS) Device Endpoint Enable Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIDR REG_ACCESS(WoReg, 0x400AC220U) /**< \brief (UOTGHS) Device Endpoint Disable Register (n = 0) */
+#define REG_UOTGHS_DEVDMANXTDSC1 REG_ACCESS(RwReg, 0x400AC310U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 1) */
+#define REG_UOTGHS_DEVDMAADDRESS1 REG_ACCESS(RwReg, 0x400AC314U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 1) */
+#define REG_UOTGHS_DEVDMACONTROL1 REG_ACCESS(RwReg, 0x400AC318U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 1) */
+#define REG_UOTGHS_DEVDMASTATUS1 REG_ACCESS(RwReg, 0x400AC31CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 1) */
+#define REG_UOTGHS_DEVDMANXTDSC2 REG_ACCESS(RwReg, 0x400AC320U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 2) */
+#define REG_UOTGHS_DEVDMAADDRESS2 REG_ACCESS(RwReg, 0x400AC324U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 2) */
+#define REG_UOTGHS_DEVDMACONTROL2 REG_ACCESS(RwReg, 0x400AC328U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 2) */
+#define REG_UOTGHS_DEVDMASTATUS2 REG_ACCESS(RwReg, 0x400AC32CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 2) */
+#define REG_UOTGHS_DEVDMANXTDSC3 REG_ACCESS(RwReg, 0x400AC330U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 3) */
+#define REG_UOTGHS_DEVDMAADDRESS3 REG_ACCESS(RwReg, 0x400AC334U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 3) */
+#define REG_UOTGHS_DEVDMACONTROL3 REG_ACCESS(RwReg, 0x400AC338U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 3) */
+#define REG_UOTGHS_DEVDMASTATUS3 REG_ACCESS(RwReg, 0x400AC33CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 3) */
+#define REG_UOTGHS_DEVDMANXTDSC4 REG_ACCESS(RwReg, 0x400AC340U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 4) */
+#define REG_UOTGHS_DEVDMAADDRESS4 REG_ACCESS(RwReg, 0x400AC344U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 4) */
+#define REG_UOTGHS_DEVDMACONTROL4 REG_ACCESS(RwReg, 0x400AC348U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 4) */
+#define REG_UOTGHS_DEVDMASTATUS4 REG_ACCESS(RwReg, 0x400AC34CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 4) */
+#define REG_UOTGHS_DEVDMANXTDSC5 REG_ACCESS(RwReg, 0x400AC350U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 5) */
+#define REG_UOTGHS_DEVDMAADDRESS5 REG_ACCESS(RwReg, 0x400AC354U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 5) */
+#define REG_UOTGHS_DEVDMACONTROL5 REG_ACCESS(RwReg, 0x400AC358U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 5) */
+#define REG_UOTGHS_DEVDMASTATUS5 REG_ACCESS(RwReg, 0x400AC35CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 5) */
+#define REG_UOTGHS_DEVDMANXTDSC6 REG_ACCESS(RwReg, 0x400AC360U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 6) */
+#define REG_UOTGHS_DEVDMAADDRESS6 REG_ACCESS(RwReg, 0x400AC364U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 6) */
+#define REG_UOTGHS_DEVDMACONTROL6 REG_ACCESS(RwReg, 0x400AC368U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 6) */
+#define REG_UOTGHS_DEVDMASTATUS6 REG_ACCESS(RwReg, 0x400AC36CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 6) */
+#define REG_UOTGHS_DEVDMANXTDSC7 REG_ACCESS(RwReg, 0x400AC370U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 7) */
+#define REG_UOTGHS_DEVDMAADDRESS7 REG_ACCESS(RwReg, 0x400AC374U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 7) */
+#define REG_UOTGHS_DEVDMACONTROL7 REG_ACCESS(RwReg, 0x400AC378U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 7) */
+#define REG_UOTGHS_DEVDMASTATUS7 REG_ACCESS(RwReg, 0x400AC37CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 7) */
+#define REG_UOTGHS_HSTCTRL REG_ACCESS(RwReg, 0x400AC400U) /**< \brief (UOTGHS) Host General Control Register */
+#define REG_UOTGHS_HSTISR REG_ACCESS(RoReg, 0x400AC404U) /**< \brief (UOTGHS) Host Global Interrupt Status Register */
+#define REG_UOTGHS_HSTICR REG_ACCESS(WoReg, 0x400AC408U) /**< \brief (UOTGHS) Host Global Interrupt Clear Register */
+#define REG_UOTGHS_HSTIFR REG_ACCESS(WoReg, 0x400AC40CU) /**< \brief (UOTGHS) Host Global Interrupt Set Register */
+#define REG_UOTGHS_HSTIMR REG_ACCESS(RoReg, 0x400AC410U) /**< \brief (UOTGHS) Host Global Interrupt Mask Register */
+#define REG_UOTGHS_HSTIDR REG_ACCESS(WoReg, 0x400AC414U) /**< \brief (UOTGHS) Host Global Interrupt Disable Register */
+#define REG_UOTGHS_HSTIER REG_ACCESS(WoReg, 0x400AC418U) /**< \brief (UOTGHS) Host Global Interrupt Enable Register */
+#define REG_UOTGHS_HSTPIP REG_ACCESS(RwReg, 0x400AC41CU) /**< \brief (UOTGHS) Host Pipe Register */
+#define REG_UOTGHS_HSTFNUM REG_ACCESS(RwReg, 0x400AC420U) /**< \brief (UOTGHS) Host Frame Number Register */
+#define REG_UOTGHS_HSTADDR1 REG_ACCESS(RwReg, 0x400AC424U) /**< \brief (UOTGHS) Host Address 1 Register */
+#define REG_UOTGHS_HSTADDR2 REG_ACCESS(RwReg, 0x400AC428U) /**< \brief (UOTGHS) Host Address 2 Register */
+#define REG_UOTGHS_HSTADDR3 REG_ACCESS(RwReg, 0x400AC42CU) /**< \brief (UOTGHS) Host Address 3 Register */
+#define REG_UOTGHS_HSTPIPCFG REG_ACCESS(RwReg, 0x400AC500U) /**< \brief (UOTGHS) Host Pipe Configuration Register (n = 0) */
+#define REG_UOTGHS_HSTPIPISR REG_ACCESS(RoReg, 0x400AC530U) /**< \brief (UOTGHS) Host Pipe Status Register (n = 0) */
+#define REG_UOTGHS_HSTPIPICR REG_ACCESS(WoReg, 0x400AC560U) /**< \brief (UOTGHS) Host Pipe Clear Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIFR REG_ACCESS(WoReg, 0x400AC590U) /**< \brief (UOTGHS) Host Pipe Set Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIMR REG_ACCESS(RoReg, 0x400AC5C0U) /**< \brief (UOTGHS) Host Pipe Mask Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIER REG_ACCESS(WoReg, 0x400AC5F0U) /**< \brief (UOTGHS) Host Pipe Enable Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIDR REG_ACCESS(WoReg, 0x400AC620U) /**< \brief (UOTGHS) Host Pipe Disable Register (n = 0) */
+#define REG_UOTGHS_HSTPIPINRQ REG_ACCESS(RwReg, 0x400AC650U) /**< \brief (UOTGHS) Host Pipe IN Request Register (n = 0) */
+#define REG_UOTGHS_HSTPIPERR REG_ACCESS(RwReg, 0x400AC680U) /**< \brief (UOTGHS) Host Pipe Error Register (n = 0) */
+#define REG_UOTGHS_HSTDMANXTDSC1 REG_ACCESS(RwReg, 0x400AC710U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 1) */
+#define REG_UOTGHS_HSTDMAADDRESS1 REG_ACCESS(RwReg, 0x400AC714U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 1) */
+#define REG_UOTGHS_HSTDMACONTROL1 REG_ACCESS(RwReg, 0x400AC718U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 1) */
+#define REG_UOTGHS_HSTDMASTATUS1 REG_ACCESS(RwReg, 0x400AC71CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 1) */
+#define REG_UOTGHS_HSTDMANXTDSC2 REG_ACCESS(RwReg, 0x400AC720U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 2) */
+#define REG_UOTGHS_HSTDMAADDRESS2 REG_ACCESS(RwReg, 0x400AC724U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 2) */
+#define REG_UOTGHS_HSTDMACONTROL2 REG_ACCESS(RwReg, 0x400AC728U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 2) */
+#define REG_UOTGHS_HSTDMASTATUS2 REG_ACCESS(RwReg, 0x400AC72CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 2) */
+#define REG_UOTGHS_HSTDMANXTDSC3 REG_ACCESS(RwReg, 0x400AC730U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 3) */
+#define REG_UOTGHS_HSTDMAADDRESS3 REG_ACCESS(RwReg, 0x400AC734U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 3) */
+#define REG_UOTGHS_HSTDMACONTROL3 REG_ACCESS(RwReg, 0x400AC738U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 3) */
+#define REG_UOTGHS_HSTDMASTATUS3 REG_ACCESS(RwReg, 0x400AC73CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 3) */
+#define REG_UOTGHS_HSTDMANXTDSC4 REG_ACCESS(RwReg, 0x400AC740U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 4) */
+#define REG_UOTGHS_HSTDMAADDRESS4 REG_ACCESS(RwReg, 0x400AC744U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 4) */
+#define REG_UOTGHS_HSTDMACONTROL4 REG_ACCESS(RwReg, 0x400AC748U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 4) */
+#define REG_UOTGHS_HSTDMASTATUS4 REG_ACCESS(RwReg, 0x400AC74CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 4) */
+#define REG_UOTGHS_HSTDMANXTDSC5 REG_ACCESS(RwReg, 0x400AC750U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 5) */
+#define REG_UOTGHS_HSTDMAADDRESS5 REG_ACCESS(RwReg, 0x400AC754U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 5) */
+#define REG_UOTGHS_HSTDMACONTROL5 REG_ACCESS(RwReg, 0x400AC758U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 5) */
+#define REG_UOTGHS_HSTDMASTATUS5 REG_ACCESS(RwReg, 0x400AC75CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 5) */
+#define REG_UOTGHS_HSTDMANXTDSC6 REG_ACCESS(RwReg, 0x400AC760U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 6) */
+#define REG_UOTGHS_HSTDMAADDRESS6 REG_ACCESS(RwReg, 0x400AC764U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 6) */
+#define REG_UOTGHS_HSTDMACONTROL6 REG_ACCESS(RwReg, 0x400AC768U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 6) */
+#define REG_UOTGHS_HSTDMASTATUS6 REG_ACCESS(RwReg, 0x400AC76CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 6) */
+#define REG_UOTGHS_HSTDMANXTDSC7 REG_ACCESS(RwReg, 0x400AC770U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 7) */
+#define REG_UOTGHS_HSTDMAADDRESS7 REG_ACCESS(RwReg, 0x400AC774U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 7) */
+#define REG_UOTGHS_HSTDMACONTROL7 REG_ACCESS(RwReg, 0x400AC778U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 7) */
+#define REG_UOTGHS_HSTDMASTATUS7 REG_ACCESS(RwReg, 0x400AC77CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 7) */
+#define REG_UOTGHS_CTRL REG_ACCESS(RwReg, 0x400AC800U) /**< \brief (UOTGHS) General Control Register */
+#define REG_UOTGHS_SR REG_ACCESS(RoReg, 0x400AC804U) /**< \brief (UOTGHS) General Status Register */
+#define REG_UOTGHS_SCR REG_ACCESS(WoReg, 0x400AC808U) /**< \brief (UOTGHS) General Status Clear Register */
+#define REG_UOTGHS_SFR REG_ACCESS(WoReg, 0x400AC80CU) /**< \brief (UOTGHS) General Status Set Register */
+#define REG_UOTGHS_FSM REG_ACCESS(RoReg, 0x400AC82CU) /**< \brief (UOTGHS) General Finite State Machine Register */
+/* ========== Register definition for EMAC peripheral ========== */
+#define REG_EMAC_NCR REG_ACCESS(RwReg, 0x400B0000U) /**< \brief (EMAC) Network Control Register */
+#define REG_EMAC_NCFGR REG_ACCESS(RwReg, 0x400B0004U) /**< \brief (EMAC) Network Configuration Register */
+#define REG_EMAC_NSR REG_ACCESS(RoReg, 0x400B0008U) /**< \brief (EMAC) Network Status Register */
+#define REG_EMAC_TSR REG_ACCESS(RwReg, 0x400B0014U) /**< \brief (EMAC) Transmit Status Register */
+#define REG_EMAC_RBQP REG_ACCESS(RwReg, 0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */
+#define REG_EMAC_TBQP REG_ACCESS(RwReg, 0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */
+#define REG_EMAC_RSR REG_ACCESS(RwReg, 0x400B0020U) /**< \brief (EMAC) Receive Status Register */
+#define REG_EMAC_ISR REG_ACCESS(RwReg, 0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */
+#define REG_EMAC_IER REG_ACCESS(WoReg, 0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */
+#define REG_EMAC_IDR REG_ACCESS(WoReg, 0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */
+#define REG_EMAC_IMR REG_ACCESS(RoReg, 0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */
+#define REG_EMAC_MAN REG_ACCESS(RwReg, 0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */
+#define REG_EMAC_PTR REG_ACCESS(RwReg, 0x400B0038U) /**< \brief (EMAC) Pause Time Register */
+#define REG_EMAC_PFR REG_ACCESS(RwReg, 0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */
+#define REG_EMAC_FTO REG_ACCESS(RwReg, 0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */
+#define REG_EMAC_SCF REG_ACCESS(RwReg, 0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */
+#define REG_EMAC_MCF REG_ACCESS(RwReg, 0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */
+#define REG_EMAC_FRO REG_ACCESS(RwReg, 0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */
+#define REG_EMAC_FCSE REG_ACCESS(RwReg, 0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */
+#define REG_EMAC_ALE REG_ACCESS(RwReg, 0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */
+#define REG_EMAC_DTF REG_ACCESS(RwReg, 0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */
+#define REG_EMAC_LCOL REG_ACCESS(RwReg, 0x400B005CU) /**< \brief (EMAC) Late Collisions Register */
+#define REG_EMAC_ECOL REG_ACCESS(RwReg, 0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */
+#define REG_EMAC_TUND REG_ACCESS(RwReg, 0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */
+#define REG_EMAC_CSE REG_ACCESS(RwReg, 0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */
+#define REG_EMAC_RRE REG_ACCESS(RwReg, 0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */
+#define REG_EMAC_ROV REG_ACCESS(RwReg, 0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */
+#define REG_EMAC_RSE REG_ACCESS(RwReg, 0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */
+#define REG_EMAC_ELE REG_ACCESS(RwReg, 0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */
+#define REG_EMAC_RJA REG_ACCESS(RwReg, 0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */
+#define REG_EMAC_USF REG_ACCESS(RwReg, 0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */
+#define REG_EMAC_STE REG_ACCESS(RwReg, 0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */
+#define REG_EMAC_RLE REG_ACCESS(RwReg, 0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */
+#define REG_EMAC_HRB REG_ACCESS(RwReg, 0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */
+#define REG_EMAC_HRT REG_ACCESS(RwReg, 0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */
+#define REG_EMAC_SA1B REG_ACCESS(RwReg, 0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */
+#define REG_EMAC_SA1T REG_ACCESS(RwReg, 0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */
+#define REG_EMAC_SA2B REG_ACCESS(RwReg, 0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */
+#define REG_EMAC_SA2T REG_ACCESS(RwReg, 0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */
+#define REG_EMAC_SA3B REG_ACCESS(RwReg, 0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */
+#define REG_EMAC_SA3T REG_ACCESS(RwReg, 0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */
+#define REG_EMAC_SA4B REG_ACCESS(RwReg, 0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */
+#define REG_EMAC_SA4T REG_ACCESS(RwReg, 0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */
+#define REG_EMAC_TID REG_ACCESS(RwReg, 0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */
+#define REG_EMAC_USRIO REG_ACCESS(RwReg, 0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */
+/* ========== Register definition for CAN0 peripheral ========== */
+#define REG_CAN0_MR REG_ACCESS(RwReg, 0x400B4000U) /**< \brief (CAN0) Mode Register */
+#define REG_CAN0_IER REG_ACCESS(WoReg, 0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */
+#define REG_CAN0_IDR REG_ACCESS(WoReg, 0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */
+#define REG_CAN0_IMR REG_ACCESS(RoReg, 0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */
+#define REG_CAN0_SR REG_ACCESS(RoReg, 0x400B4010U) /**< \brief (CAN0) Status Register */
+#define REG_CAN0_BR REG_ACCESS(RwReg, 0x400B4014U) /**< \brief (CAN0) Baudrate Register */
+#define REG_CAN0_TIM REG_ACCESS(RoReg, 0x400B4018U) /**< \brief (CAN0) Timer Register */
+#define REG_CAN0_TIMESTP REG_ACCESS(RoReg, 0x400B401CU) /**< \brief (CAN0) Timestamp Register */
+#define REG_CAN0_ECR REG_ACCESS(RoReg, 0x400B4020U) /**< \brief (CAN0) Error Counter Register */
+#define REG_CAN0_TCR REG_ACCESS(WoReg, 0x400B4024U) /**< \brief (CAN0) Transfer Command Register */
+#define REG_CAN0_ACR REG_ACCESS(WoReg, 0x400B4028U) /**< \brief (CAN0) Abort Command Register */
+#define REG_CAN0_MMR0 REG_ACCESS(RwReg, 0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */
+#define REG_CAN0_MAM0 REG_ACCESS(RwReg, 0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN0_MID0 REG_ACCESS(RwReg, 0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */
+#define REG_CAN0_MFID0 REG_ACCESS(RoReg, 0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN0_MSR0 REG_ACCESS(RoReg, 0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */
+#define REG_CAN0_MDL0 REG_ACCESS(RwReg, 0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN0_MDH0 REG_ACCESS(RwReg, 0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */
+#define REG_CAN0_MCR0 REG_ACCESS(WoReg, 0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */
+#define REG_CAN0_MMR1 REG_ACCESS(RwReg, 0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */
+#define REG_CAN0_MAM1 REG_ACCESS(RwReg, 0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN0_MID1 REG_ACCESS(RwReg, 0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */
+#define REG_CAN0_MFID1 REG_ACCESS(RoReg, 0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN0_MSR1 REG_ACCESS(RoReg, 0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */
+#define REG_CAN0_MDL1 REG_ACCESS(RwReg, 0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN0_MDH1 REG_ACCESS(RwReg, 0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */
+#define REG_CAN0_MCR1 REG_ACCESS(WoReg, 0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */
+#define REG_CAN0_MMR2 REG_ACCESS(RwReg, 0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */
+#define REG_CAN0_MAM2 REG_ACCESS(RwReg, 0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN0_MID2 REG_ACCESS(RwReg, 0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */
+#define REG_CAN0_MFID2 REG_ACCESS(RoReg, 0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN0_MSR2 REG_ACCESS(RoReg, 0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */
+#define REG_CAN0_MDL2 REG_ACCESS(RwReg, 0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN0_MDH2 REG_ACCESS(RwReg, 0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */
+#define REG_CAN0_MCR2 REG_ACCESS(WoReg, 0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */
+#define REG_CAN0_MMR3 REG_ACCESS(RwReg, 0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */
+#define REG_CAN0_MAM3 REG_ACCESS(RwReg, 0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN0_MID3 REG_ACCESS(RwReg, 0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */
+#define REG_CAN0_MFID3 REG_ACCESS(RoReg, 0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN0_MSR3 REG_ACCESS(RoReg, 0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */
+#define REG_CAN0_MDL3 REG_ACCESS(RwReg, 0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN0_MDH3 REG_ACCESS(RwReg, 0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */
+#define REG_CAN0_MCR3 REG_ACCESS(WoReg, 0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */
+#define REG_CAN0_MMR4 REG_ACCESS(RwReg, 0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */
+#define REG_CAN0_MAM4 REG_ACCESS(RwReg, 0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN0_MID4 REG_ACCESS(RwReg, 0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */
+#define REG_CAN0_MFID4 REG_ACCESS(RoReg, 0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN0_MSR4 REG_ACCESS(RoReg, 0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */
+#define REG_CAN0_MDL4 REG_ACCESS(RwReg, 0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN0_MDH4 REG_ACCESS(RwReg, 0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */
+#define REG_CAN0_MCR4 REG_ACCESS(WoReg, 0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */
+#define REG_CAN0_MMR5 REG_ACCESS(RwReg, 0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */
+#define REG_CAN0_MAM5 REG_ACCESS(RwReg, 0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN0_MID5 REG_ACCESS(RwReg, 0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */
+#define REG_CAN0_MFID5 REG_ACCESS(RoReg, 0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN0_MSR5 REG_ACCESS(RoReg, 0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */
+#define REG_CAN0_MDL5 REG_ACCESS(RwReg, 0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN0_MDH5 REG_ACCESS(RwReg, 0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */
+#define REG_CAN0_MCR5 REG_ACCESS(WoReg, 0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */
+#define REG_CAN0_MMR6 REG_ACCESS(RwReg, 0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */
+#define REG_CAN0_MAM6 REG_ACCESS(RwReg, 0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN0_MID6 REG_ACCESS(RwReg, 0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */
+#define REG_CAN0_MFID6 REG_ACCESS(RoReg, 0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN0_MSR6 REG_ACCESS(RoReg, 0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */
+#define REG_CAN0_MDL6 REG_ACCESS(RwReg, 0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN0_MDH6 REG_ACCESS(RwReg, 0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */
+#define REG_CAN0_MCR6 REG_ACCESS(WoReg, 0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */
+#define REG_CAN0_MMR7 REG_ACCESS(RwReg, 0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */
+#define REG_CAN0_MAM7 REG_ACCESS(RwReg, 0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN0_MID7 REG_ACCESS(RwReg, 0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */
+#define REG_CAN0_MFID7 REG_ACCESS(RoReg, 0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN0_MSR7 REG_ACCESS(RoReg, 0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */
+#define REG_CAN0_MDL7 REG_ACCESS(RwReg, 0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN0_MDH7 REG_ACCESS(RwReg, 0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */
+#define REG_CAN0_MCR7 REG_ACCESS(WoReg, 0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */
+/* ========== Register definition for CAN1 peripheral ========== */
+#define REG_CAN1_MR REG_ACCESS(RwReg, 0x400B8000U) /**< \brief (CAN1) Mode Register */
+#define REG_CAN1_IER REG_ACCESS(WoReg, 0x400B8004U) /**< \brief (CAN1) Interrupt Enable Register */
+#define REG_CAN1_IDR REG_ACCESS(WoReg, 0x400B8008U) /**< \brief (CAN1) Interrupt Disable Register */
+#define REG_CAN1_IMR REG_ACCESS(RoReg, 0x400B800CU) /**< \brief (CAN1) Interrupt Mask Register */
+#define REG_CAN1_SR REG_ACCESS(RoReg, 0x400B8010U) /**< \brief (CAN1) Status Register */
+#define REG_CAN1_BR REG_ACCESS(RwReg, 0x400B8014U) /**< \brief (CAN1) Baudrate Register */
+#define REG_CAN1_TIM REG_ACCESS(RoReg, 0x400B8018U) /**< \brief (CAN1) Timer Register */
+#define REG_CAN1_TIMESTP REG_ACCESS(RoReg, 0x400B801CU) /**< \brief (CAN1) Timestamp Register */
+#define REG_CAN1_ECR REG_ACCESS(RoReg, 0x400B8020U) /**< \brief (CAN1) Error Counter Register */
+#define REG_CAN1_TCR REG_ACCESS(WoReg, 0x400B8024U) /**< \brief (CAN1) Transfer Command Register */
+#define REG_CAN1_ACR REG_ACCESS(WoReg, 0x400B8028U) /**< \brief (CAN1) Abort Command Register */
+#define REG_CAN1_MMR0 REG_ACCESS(RwReg, 0x400B8200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */
+#define REG_CAN1_MAM0 REG_ACCESS(RwReg, 0x400B8204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN1_MID0 REG_ACCESS(RwReg, 0x400B8208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */
+#define REG_CAN1_MFID0 REG_ACCESS(RoReg, 0x400B820CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN1_MSR0 REG_ACCESS(RoReg, 0x400B8210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */
+#define REG_CAN1_MDL0 REG_ACCESS(RwReg, 0x400B8214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN1_MDH0 REG_ACCESS(RwReg, 0x400B8218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */
+#define REG_CAN1_MCR0 REG_ACCESS(WoReg, 0x400B821CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */
+#define REG_CAN1_MMR1 REG_ACCESS(RwReg, 0x400B8220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */
+#define REG_CAN1_MAM1 REG_ACCESS(RwReg, 0x400B8224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN1_MID1 REG_ACCESS(RwReg, 0x400B8228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */
+#define REG_CAN1_MFID1 REG_ACCESS(RoReg, 0x400B822CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN1_MSR1 REG_ACCESS(RoReg, 0x400B8230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */
+#define REG_CAN1_MDL1 REG_ACCESS(RwReg, 0x400B8234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN1_MDH1 REG_ACCESS(RwReg, 0x400B8238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */
+#define REG_CAN1_MCR1 REG_ACCESS(WoReg, 0x400B823CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */
+#define REG_CAN1_MMR2 REG_ACCESS(RwReg, 0x400B8240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */
+#define REG_CAN1_MAM2 REG_ACCESS(RwReg, 0x400B8244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN1_MID2 REG_ACCESS(RwReg, 0x400B8248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */
+#define REG_CAN1_MFID2 REG_ACCESS(RoReg, 0x400B824CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN1_MSR2 REG_ACCESS(RoReg, 0x400B8250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */
+#define REG_CAN1_MDL2 REG_ACCESS(RwReg, 0x400B8254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN1_MDH2 REG_ACCESS(RwReg, 0x400B8258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */
+#define REG_CAN1_MCR2 REG_ACCESS(WoReg, 0x400B825CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */
+#define REG_CAN1_MMR3 REG_ACCESS(RwReg, 0x400B8260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */
+#define REG_CAN1_MAM3 REG_ACCESS(RwReg, 0x400B8264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN1_MID3 REG_ACCESS(RwReg, 0x400B8268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */
+#define REG_CAN1_MFID3 REG_ACCESS(RoReg, 0x400B826CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN1_MSR3 REG_ACCESS(RoReg, 0x400B8270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */
+#define REG_CAN1_MDL3 REG_ACCESS(RwReg, 0x400B8274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN1_MDH3 REG_ACCESS(RwReg, 0x400B8278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */
+#define REG_CAN1_MCR3 REG_ACCESS(WoReg, 0x400B827CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */
+#define REG_CAN1_MMR4 REG_ACCESS(RwReg, 0x400B8280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */
+#define REG_CAN1_MAM4 REG_ACCESS(RwReg, 0x400B8284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN1_MID4 REG_ACCESS(RwReg, 0x400B8288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */
+#define REG_CAN1_MFID4 REG_ACCESS(RoReg, 0x400B828CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN1_MSR4 REG_ACCESS(RoReg, 0x400B8290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */
+#define REG_CAN1_MDL4 REG_ACCESS(RwReg, 0x400B8294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN1_MDH4 REG_ACCESS(RwReg, 0x400B8298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */
+#define REG_CAN1_MCR4 REG_ACCESS(WoReg, 0x400B829CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */
+#define REG_CAN1_MMR5 REG_ACCESS(RwReg, 0x400B82A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */
+#define REG_CAN1_MAM5 REG_ACCESS(RwReg, 0x400B82A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN1_MID5 REG_ACCESS(RwReg, 0x400B82A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */
+#define REG_CAN1_MFID5 REG_ACCESS(RoReg, 0x400B82ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN1_MSR5 REG_ACCESS(RoReg, 0x400B82B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */
+#define REG_CAN1_MDL5 REG_ACCESS(RwReg, 0x400B82B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN1_MDH5 REG_ACCESS(RwReg, 0x400B82B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */
+#define REG_CAN1_MCR5 REG_ACCESS(WoReg, 0x400B82BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */
+#define REG_CAN1_MMR6 REG_ACCESS(RwReg, 0x400B82C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */
+#define REG_CAN1_MAM6 REG_ACCESS(RwReg, 0x400B82C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN1_MID6 REG_ACCESS(RwReg, 0x400B82C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */
+#define REG_CAN1_MFID6 REG_ACCESS(RoReg, 0x400B82CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN1_MSR6 REG_ACCESS(RoReg, 0x400B82D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */
+#define REG_CAN1_MDL6 REG_ACCESS(RwReg, 0x400B82D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN1_MDH6 REG_ACCESS(RwReg, 0x400B82D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */
+#define REG_CAN1_MCR6 REG_ACCESS(WoReg, 0x400B82DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */
+#define REG_CAN1_MMR7 REG_ACCESS(RwReg, 0x400B82E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */
+#define REG_CAN1_MAM7 REG_ACCESS(RwReg, 0x400B82E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN1_MID7 REG_ACCESS(RwReg, 0x400B82E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */
+#define REG_CAN1_MFID7 REG_ACCESS(RoReg, 0x400B82ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN1_MSR7 REG_ACCESS(RoReg, 0x400B82F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */
+#define REG_CAN1_MDL7 REG_ACCESS(RwReg, 0x400B82F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN1_MDH7 REG_ACCESS(RwReg, 0x400B82F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */
+#define REG_CAN1_MCR7 REG_ACCESS(WoReg, 0x400B82FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */
+/* ========== Register definition for TRNG peripheral ========== */
+#define REG_TRNG_CR REG_ACCESS(WoReg, 0x400BC000U) /**< \brief (TRNG) Control Register */
+#define REG_TRNG_IER REG_ACCESS(WoReg, 0x400BC010U) /**< \brief (TRNG) Interrupt Enable Register */
+#define REG_TRNG_IDR REG_ACCESS(WoReg, 0x400BC014U) /**< \brief (TRNG) Interrupt Disable Register */
+#define REG_TRNG_IMR REG_ACCESS(RoReg, 0x400BC018U) /**< \brief (TRNG) Interrupt Mask Register */
+#define REG_TRNG_ISR REG_ACCESS(RoReg, 0x400BC01CU) /**< \brief (TRNG) Interrupt Status Register */
+#define REG_TRNG_ODATA REG_ACCESS(RoReg, 0x400BC050U) /**< \brief (TRNG) Output Data Register */
+/* ========== Register definition for ADC peripheral ========== */
+#define REG_ADC_CR REG_ACCESS(WoReg, 0x400C0000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR REG_ACCESS(RwReg, 0x400C0004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1 REG_ACCESS(RwReg, 0x400C0008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2 REG_ACCESS(RwReg, 0x400C000CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER REG_ACCESS(WoReg, 0x400C0010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x400C0014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x400C0018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x400C0020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER REG_ACCESS(WoReg, 0x400C0024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR REG_ACCESS(WoReg, 0x400C0028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR REG_ACCESS(RoReg, 0x400C002CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR REG_ACCESS(RoReg, 0x400C0030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER REG_ACCESS(RoReg, 0x400C003CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR REG_ACCESS(RwReg, 0x400C0040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR REG_ACCESS(RwReg, 0x400C0044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR REG_ACCESS(RwReg, 0x400C0048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR REG_ACCESS(RwReg, 0x400C004CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR REG_ACCESS(RoReg, 0x400C0050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR REG_ACCESS(RwReg, 0x400C0094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400C00E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400C00E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR REG_ACCESS(RwReg, 0x400C0100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR REG_ACCESS(RwReg, 0x400C0104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_TPR REG_ACCESS(RwReg, 0x400C0108U) /**< \brief (ADC) Transmit Pointer Register */
+#define REG_ADC_TCR REG_ACCESS(RwReg, 0x400C010CU) /**< \brief (ADC) Transmit Counter Register */
+#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x400C0110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x400C0114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x400C0118U) /**< \brief (ADC) Transmit Next Pointer Register */
+#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x400C011CU) /**< \brief (ADC) Transmit Next Counter Register */
+#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x400C0120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x400C0124U) /**< \brief (ADC) Transfer Status Register */
+/* ========== Register definition for DMAC peripheral ========== */
+#define REG_DMAC_GCFG REG_ACCESS(RwReg, 0x400C4000U) /**< \brief (DMAC) DMAC Global Configuration Register */
+#define REG_DMAC_EN REG_ACCESS(RwReg, 0x400C4004U) /**< \brief (DMAC) DMAC Enable Register */
+#define REG_DMAC_SREQ REG_ACCESS(RwReg, 0x400C4008U) /**< \brief (DMAC) DMAC Software Single Request Register */
+#define REG_DMAC_CREQ REG_ACCESS(RwReg, 0x400C400CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
+#define REG_DMAC_LAST REG_ACCESS(RwReg, 0x400C4010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
+#define REG_DMAC_EBCIER REG_ACCESS(WoReg, 0x400C4018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+#define REG_DMAC_EBCIDR REG_ACCESS(WoReg, 0x400C401CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+#define REG_DMAC_EBCIMR REG_ACCESS(RoReg, 0x400C4020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+#define REG_DMAC_EBCISR REG_ACCESS(RoReg, 0x400C4024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+#define REG_DMAC_CHER REG_ACCESS(WoReg, 0x400C4028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
+#define REG_DMAC_CHDR REG_ACCESS(WoReg, 0x400C402CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
+#define REG_DMAC_CHSR REG_ACCESS(RoReg, 0x400C4030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
+#define REG_DMAC_SADDR0 REG_ACCESS(RwReg, 0x400C403CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
+#define REG_DMAC_DADDR0 REG_ACCESS(RwReg, 0x400C4040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
+#define REG_DMAC_DSCR0 REG_ACCESS(RwReg, 0x400C4044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
+#define REG_DMAC_CTRLA0 REG_ACCESS(RwReg, 0x400C4048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
+#define REG_DMAC_CTRLB0 REG_ACCESS(RwReg, 0x400C404CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
+#define REG_DMAC_CFG0 REG_ACCESS(RwReg, 0x400C4050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
+#define REG_DMAC_SADDR1 REG_ACCESS(RwReg, 0x400C4064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
+#define REG_DMAC_DADDR1 REG_ACCESS(RwReg, 0x400C4068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
+#define REG_DMAC_DSCR1 REG_ACCESS(RwReg, 0x400C406CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
+#define REG_DMAC_CTRLA1 REG_ACCESS(RwReg, 0x400C4070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
+#define REG_DMAC_CTRLB1 REG_ACCESS(RwReg, 0x400C4074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
+#define REG_DMAC_CFG1 REG_ACCESS(RwReg, 0x400C4078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
+#define REG_DMAC_SADDR2 REG_ACCESS(RwReg, 0x400C408CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
+#define REG_DMAC_DADDR2 REG_ACCESS(RwReg, 0x400C4090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
+#define REG_DMAC_DSCR2 REG_ACCESS(RwReg, 0x400C4094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
+#define REG_DMAC_CTRLA2 REG_ACCESS(RwReg, 0x400C4098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
+#define REG_DMAC_CTRLB2 REG_ACCESS(RwReg, 0x400C409CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
+#define REG_DMAC_CFG2 REG_ACCESS(RwReg, 0x400C40A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
+#define REG_DMAC_SADDR3 REG_ACCESS(RwReg, 0x400C40B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
+#define REG_DMAC_DADDR3 REG_ACCESS(RwReg, 0x400C40B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
+#define REG_DMAC_DSCR3 REG_ACCESS(RwReg, 0x400C40BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
+#define REG_DMAC_CTRLA3 REG_ACCESS(RwReg, 0x400C40C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
+#define REG_DMAC_CTRLB3 REG_ACCESS(RwReg, 0x400C40C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
+#define REG_DMAC_CFG3 REG_ACCESS(RwReg, 0x400C40C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
+#define REG_DMAC_SADDR4 REG_ACCESS(RwReg, 0x400C40DCU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 4) */
+#define REG_DMAC_DADDR4 REG_ACCESS(RwReg, 0x400C40E0U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 4) */
+#define REG_DMAC_DSCR4 REG_ACCESS(RwReg, 0x400C40E4U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 4) */
+#define REG_DMAC_CTRLA4 REG_ACCESS(RwReg, 0x400C40E8U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 4) */
+#define REG_DMAC_CTRLB4 REG_ACCESS(RwReg, 0x400C40ECU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 4) */
+#define REG_DMAC_CFG4 REG_ACCESS(RwReg, 0x400C40F0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 4) */
+#define REG_DMAC_SADDR5 REG_ACCESS(RwReg, 0x400C4104U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 5) */
+#define REG_DMAC_DADDR5 REG_ACCESS(RwReg, 0x400C4108U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 5) */
+#define REG_DMAC_DSCR5 REG_ACCESS(RwReg, 0x400C410CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 5) */
+#define REG_DMAC_CTRLA5 REG_ACCESS(RwReg, 0x400C4110U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 5) */
+#define REG_DMAC_CTRLB5 REG_ACCESS(RwReg, 0x400C4114U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 5) */
+#define REG_DMAC_CFG5 REG_ACCESS(RwReg, 0x400C4118U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 5) */
+#define REG_DMAC_WPMR REG_ACCESS(RwReg, 0x400C41E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */
+#define REG_DMAC_WPSR REG_ACCESS(RoReg, 0x400C41E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */
+/* ========== Register definition for DACC peripheral ========== */
+#define REG_DACC_CR REG_ACCESS(WoReg, 0x400C8000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR REG_ACCESS(RwReg, 0x400C8004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER REG_ACCESS(WoReg, 0x400C8010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR REG_ACCESS(WoReg, 0x400C8014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR REG_ACCESS(RoReg, 0x400C8018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR REG_ACCESS(WoReg, 0x400C8020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER REG_ACCESS(WoReg, 0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR REG_ACCESS(WoReg, 0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR REG_ACCESS(RoReg, 0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR REG_ACCESS(RoReg, 0x400C8030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR REG_ACCESS(RwReg, 0x400C8094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x400C80E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_RPR REG_ACCESS(RwReg, 0x400C8100U) /**< \brief (DACC) Receive Pointer Register */
+#define REG_DACC_RCR REG_ACCESS(RwReg, 0x400C8104U) /**< \brief (DACC) Receive Counter Register */
+#define REG_DACC_TPR REG_ACCESS(RwReg, 0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR REG_ACCESS(RwReg, 0x400C810CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x400C8110U) /**< \brief (DACC) Receive Next Pointer Register */
+#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x400C8114U) /**< \brief (DACC) Receive Next Counter Register */
+#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x400C8120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x400C8124U) /**< \brief (DACC) Transfer Status Register */
+/* ========== Register definition for SMC peripheral ========== */
+#define REG_SMC_CFG REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
+#define REG_SMC_CTRL REG_ACCESS(WoReg, 0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
+#define REG_SMC_SR REG_ACCESS(RoReg, 0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
+#define REG_SMC_IER REG_ACCESS(WoReg, 0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
+#define REG_SMC_IDR REG_ACCESS(WoReg, 0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
+#define REG_SMC_IMR REG_ACCESS(RoReg, 0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
+#define REG_SMC_ADDR REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
+#define REG_SMC_BANK REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
+#define REG_SMC_ECC_CTRL REG_ACCESS(WoReg, 0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
+#define REG_SMC_ECC_MD REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
+#define REG_SMC_ECC_SR1 REG_ACCESS(RoReg, 0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
+#define REG_SMC_ECC_PR0 REG_ACCESS(RoReg, 0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
+#define REG_SMC_ECC_PR1 REG_ACCESS(RoReg, 0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
+#define REG_SMC_ECC_SR2 REG_ACCESS(RoReg, 0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
+#define REG_SMC_ECC_PR2 REG_ACCESS(RoReg, 0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
+#define REG_SMC_ECC_PR3 REG_ACCESS(RoReg, 0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
+#define REG_SMC_ECC_PR4 REG_ACCESS(RoReg, 0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
+#define REG_SMC_ECC_PR5 REG_ACCESS(RoReg, 0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
+#define REG_SMC_ECC_PR6 REG_ACCESS(RoReg, 0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
+#define REG_SMC_ECC_PR7 REG_ACCESS(RoReg, 0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
+#define REG_SMC_ECC_PR8 REG_ACCESS(RoReg, 0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
+#define REG_SMC_ECC_PR9 REG_ACCESS(RoReg, 0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
+#define REG_SMC_ECC_PR10 REG_ACCESS(RoReg, 0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
+#define REG_SMC_ECC_PR11 REG_ACCESS(RoReg, 0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
+#define REG_SMC_ECC_PR12 REG_ACCESS(RoReg, 0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
+#define REG_SMC_ECC_PR13 REG_ACCESS(RoReg, 0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
+#define REG_SMC_ECC_PR14 REG_ACCESS(RoReg, 0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
+#define REG_SMC_ECC_PR15 REG_ACCESS(RoReg, 0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
+#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_TIMINGS0 REG_ACCESS(RwReg, 0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
+#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_TIMINGS1 REG_ACCESS(RwReg, 0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
+#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_TIMINGS2 REG_ACCESS(RwReg, 0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
+#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_TIMINGS3 REG_ACCESS(RwReg, 0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
+#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E00C0U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E00C4U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E00C8U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_TIMINGS4 REG_ACCESS(RwReg, 0x400E00CCU) /**< \brief (SMC) SMC Timings Register (CS_number = 4) */
+#define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E00D0U) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_SETUP5 REG_ACCESS(RwReg, 0x400E00D4U) /**< \brief (SMC) SMC Setup Register (CS_number = 5) */
+#define REG_SMC_PULSE5 REG_ACCESS(RwReg, 0x400E00D8U) /**< \brief (SMC) SMC Pulse Register (CS_number = 5) */
+#define REG_SMC_CYCLE5 REG_ACCESS(RwReg, 0x400E00DCU) /**< \brief (SMC) SMC Cycle Register (CS_number = 5) */
+#define REG_SMC_TIMINGS5 REG_ACCESS(RwReg, 0x400E00E0U) /**< \brief (SMC) SMC Timings Register (CS_number = 5) */
+#define REG_SMC_MODE5 REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Mode Register (CS_number = 5) */
+#define REG_SMC_SETUP6 REG_ACCESS(RwReg, 0x400E00E8U) /**< \brief (SMC) SMC Setup Register (CS_number = 6) */
+#define REG_SMC_PULSE6 REG_ACCESS(RwReg, 0x400E00ECU) /**< \brief (SMC) SMC Pulse Register (CS_number = 6) */
+#define REG_SMC_CYCLE6 REG_ACCESS(RwReg, 0x400E00F0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 6) */
+#define REG_SMC_TIMINGS6 REG_ACCESS(RwReg, 0x400E00F4U) /**< \brief (SMC) SMC Timings Register (CS_number = 6) */
+#define REG_SMC_MODE6 REG_ACCESS(RwReg, 0x400E00F8U) /**< \brief (SMC) SMC Mode Register (CS_number = 6) */
+#define REG_SMC_SETUP7 REG_ACCESS(RwReg, 0x400E00FCU) /**< \brief (SMC) SMC Setup Register (CS_number = 7) */
+#define REG_SMC_PULSE7 REG_ACCESS(RwReg, 0x400E0100U) /**< \brief (SMC) SMC Pulse Register (CS_number = 7) */
+#define REG_SMC_CYCLE7 REG_ACCESS(RwReg, 0x400E0104U) /**< \brief (SMC) SMC Cycle Register (CS_number = 7) */
+#define REG_SMC_TIMINGS7 REG_ACCESS(RwReg, 0x400E0108U) /**< \brief (SMC) SMC Timings Register (CS_number = 7) */
+#define REG_SMC_MODE7 REG_ACCESS(RwReg, 0x400E010CU) /**< \brief (SMC) SMC Mode Register (CS_number = 7) */
+#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
+#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPCR REG_ACCESS(WoReg, 0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
+#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
+/* ========== Register definition for SDRAMC peripheral ========== */
+#define REG_SDRAMC_MR REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */
+#define REG_SDRAMC_TR REG_ACCESS(RwReg, 0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
+#define REG_SDRAMC_CR REG_ACCESS(RwReg, 0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
+#define REG_SDRAMC_LPR REG_ACCESS(RwReg, 0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
+#define REG_SDRAMC_IER REG_ACCESS(WoReg, 0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
+#define REG_SDRAMC_IDR REG_ACCESS(WoReg, 0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
+#define REG_SDRAMC_IMR REG_ACCESS(RoReg, 0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
+#define REG_SDRAMC_ISR REG_ACCESS(RoReg, 0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
+#define REG_SDRAMC_MDR REG_ACCESS(RwReg, 0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
+#define REG_SDRAMC_CR1 REG_ACCESS(RwReg, 0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
+#define REG_SDRAMC_OCMS REG_ACCESS(RwReg, 0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */
+/* ========== Register definition for MATRIX peripheral ========== */
+#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_MATRIX_PRAS5 REG_ACCESS(RwReg, 0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
+#define REG_MATRIX_PRAS6 REG_ACCESS(RwReg, 0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
+#define REG_MATRIX_PRAS7 REG_ACCESS(RwReg, 0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
+#define REG_MATRIX_PRAS8 REG_ACCESS(RwReg, 0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
+#define REG_MATRIX_MRCR REG_ACCESS(RwReg, 0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */
+#define REG_CCFG_SYSIO REG_ACCESS(RwReg, 0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */
+/* ========== Register definition for PMC peripheral ========== */
+#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0604U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0608U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0 REG_ACCESS(WoReg, 0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0 REG_ACCESS(WoReg, 0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0 REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_UCKR REG_ACCESS(RwReg, 0x400E061CU) /**< \brief (PMC) UTMI Clock Register */
+#define REG_CKGR_MOR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR REG_ACCESS(RoReg, 0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR REG_ACCESS(RwReg, 0x400E0628U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0630U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB REG_ACCESS(RwReg, 0x400E0638U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0668U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1 REG_ACCESS(WoReg, 0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1 REG_ACCESS(WoReg, 0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1 REG_ACCESS(RoReg, 0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_PCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (PMC) Peripheral Control Register */
+/* ========== Register definition for UART peripheral ========== */
+#define REG_UART_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART) Control Register */
+#define REG_UART_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART) Mode Register */
+#define REG_UART_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART) Interrupt Enable Register */
+#define REG_UART_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART) Interrupt Disable Register */
+#define REG_UART_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART) Interrupt Mask Register */
+#define REG_UART_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART) Status Register */
+#define REG_UART_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART) Receive Holding Register */
+#define REG_UART_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART) Transmit Holding Register */
+#define REG_UART_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART) Baud Rate Generator Register */
+#define REG_UART_RPR REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART) Receive Pointer Register */
+#define REG_UART_RCR REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART) Receive Counter Register */
+#define REG_UART_TPR REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART) Transmit Pointer Register */
+#define REG_UART_TCR REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART) Transmit Counter Register */
+#define REG_UART_RNPR REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART) Receive Next Pointer Register */
+#define REG_UART_RNCR REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART) Receive Next Counter Register */
+#define REG_UART_TNPR REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART) Transmit Next Pointer Register */
+#define REG_UART_TNCR REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART) Transmit Next Counter Register */
+#define REG_UART_PTCR REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART) Transfer Control Register */
+#define REG_UART_PTSR REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART) Transfer Status Register */
+/* ========== Register definition for CHIPID peripheral ========== */
+#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0940U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */
+/* ========== Register definition for EFC0 peripheral ========== */
+#define REG_EFC0_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC0) EEFC Flash Mode Register */
+#define REG_EFC0_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC0) EEFC Flash Command Register */
+#define REG_EFC0_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC0) EEFC Flash Status Register */
+#define REG_EFC0_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC0) EEFC Flash Result Register */
+/* ========== Register definition for EFC1 peripheral ========== */
+#define REG_EFC1_FMR REG_ACCESS(RwReg, 0x400E0C00U) /**< \brief (EFC1) EEFC Flash Mode Register */
+#define REG_EFC1_FCR REG_ACCESS(WoReg, 0x400E0C04U) /**< \brief (EFC1) EEFC Flash Command Register */
+#define REG_EFC1_FSR REG_ACCESS(RoReg, 0x400E0C08U) /**< \brief (EFC1) EEFC Flash Status Register */
+#define REG_EFC1_FRR REG_ACCESS(RoReg, 0x400E0C0CU) /**< \brief (EFC1) EEFC Flash Result Register */
+/* ========== Register definition for PIOA peripheral ========== */
+#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral AB Select Register */
+#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
+#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
+#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+/* ========== Register definition for PIOB peripheral ========== */
+#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */
+#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
+#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
+#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+/* ========== Register definition for PIOC peripheral ========== */
+#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral AB Select Register */
+#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
+#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
+#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+/* ========== Register definition for PIOD peripheral ========== */
+#define REG_PIOD_PER REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
+#define REG_PIOD_PDR REG_ACCESS(WoReg, 0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
+#define REG_PIOD_PSR REG_ACCESS(RoReg, 0x400E1408U) /**< \brief (PIOD) PIO Status Register */
+#define REG_PIOD_OER REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (PIOD) Output Enable Register */
+#define REG_PIOD_ODR REG_ACCESS(WoReg, 0x400E1414U) /**< \brief (PIOD) Output Disable Register */
+#define REG_PIOD_OSR REG_ACCESS(RoReg, 0x400E1418U) /**< \brief (PIOD) Output Status Register */
+#define REG_PIOD_IFER REG_ACCESS(WoReg, 0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
+#define REG_PIOD_IFDR REG_ACCESS(WoReg, 0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
+#define REG_PIOD_IFSR REG_ACCESS(RoReg, 0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
+#define REG_PIOD_SODR REG_ACCESS(WoReg, 0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
+#define REG_PIOD_CODR REG_ACCESS(WoReg, 0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
+#define REG_PIOD_ODSR REG_ACCESS(RwReg, 0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
+#define REG_PIOD_PDSR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
+#define REG_PIOD_IER REG_ACCESS(WoReg, 0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
+#define REG_PIOD_IDR REG_ACCESS(WoReg, 0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
+#define REG_PIOD_IMR REG_ACCESS(RoReg, 0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
+#define REG_PIOD_ISR REG_ACCESS(RoReg, 0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
+#define REG_PIOD_MDER REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
+#define REG_PIOD_MDDR REG_ACCESS(WoReg, 0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
+#define REG_PIOD_MDSR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
+#define REG_PIOD_PUDR REG_ACCESS(WoReg, 0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
+#define REG_PIOD_PUER REG_ACCESS(WoReg, 0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
+#define REG_PIOD_PUSR REG_ACCESS(RoReg, 0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
+#define REG_PIOD_ABSR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */
+#define REG_PIOD_SCIFSR REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */
+#define REG_PIOD_DIFSR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */
+#define REG_PIOD_IFDGSR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOD_SCDR REG_ACCESS(RwReg, 0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
+#define REG_PIOD_OWER REG_ACCESS(WoReg, 0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
+#define REG_PIOD_OWDR REG_ACCESS(WoReg, 0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
+#define REG_PIOD_OWSR REG_ACCESS(RoReg, 0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
+#define REG_PIOD_AIMER REG_ACCESS(WoReg, 0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
+#define REG_PIOD_AIMDR REG_ACCESS(WoReg, 0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
+#define REG_PIOD_AIMMR REG_ACCESS(RoReg, 0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
+#define REG_PIOD_ESR REG_ACCESS(WoReg, 0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
+#define REG_PIOD_LSR REG_ACCESS(WoReg, 0x400E14C4U) /**< \brief (PIOD) Level Select Register */
+#define REG_PIOD_ELSR REG_ACCESS(RoReg, 0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
+#define REG_PIOD_FELLSR REG_ACCESS(WoReg, 0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
+#define REG_PIOD_REHLSR REG_ACCESS(WoReg, 0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
+#define REG_PIOD_FRLHSR REG_ACCESS(RoReg, 0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
+#define REG_PIOD_LOCKSR REG_ACCESS(RoReg, 0x400E14E0U) /**< \brief (PIOD) Lock Status */
+#define REG_PIOD_WPMR REG_ACCESS(RwReg, 0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */
+#define REG_PIOD_WPSR REG_ACCESS(RoReg, 0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */
+/* ========== Register definition for PIOE peripheral ========== */
+#define REG_PIOE_PER REG_ACCESS(WoReg, 0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
+#define REG_PIOE_PDR REG_ACCESS(WoReg, 0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
+#define REG_PIOE_PSR REG_ACCESS(RoReg, 0x400E1608U) /**< \brief (PIOE) PIO Status Register */
+#define REG_PIOE_OER REG_ACCESS(WoReg, 0x400E1610U) /**< \brief (PIOE) Output Enable Register */
+#define REG_PIOE_ODR REG_ACCESS(WoReg, 0x400E1614U) /**< \brief (PIOE) Output Disable Register */
+#define REG_PIOE_OSR REG_ACCESS(RoReg, 0x400E1618U) /**< \brief (PIOE) Output Status Register */
+#define REG_PIOE_IFER REG_ACCESS(WoReg, 0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
+#define REG_PIOE_IFDR REG_ACCESS(WoReg, 0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
+#define REG_PIOE_IFSR REG_ACCESS(RoReg, 0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
+#define REG_PIOE_SODR REG_ACCESS(WoReg, 0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
+#define REG_PIOE_CODR REG_ACCESS(WoReg, 0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
+#define REG_PIOE_ODSR REG_ACCESS(RwReg, 0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
+#define REG_PIOE_PDSR REG_ACCESS(RoReg, 0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
+#define REG_PIOE_IER REG_ACCESS(WoReg, 0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
+#define REG_PIOE_IDR REG_ACCESS(WoReg, 0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
+#define REG_PIOE_IMR REG_ACCESS(RoReg, 0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
+#define REG_PIOE_ISR REG_ACCESS(RoReg, 0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
+#define REG_PIOE_MDER REG_ACCESS(WoReg, 0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
+#define REG_PIOE_MDDR REG_ACCESS(WoReg, 0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
+#define REG_PIOE_MDSR REG_ACCESS(RoReg, 0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
+#define REG_PIOE_PUDR REG_ACCESS(WoReg, 0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
+#define REG_PIOE_PUER REG_ACCESS(WoReg, 0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
+#define REG_PIOE_PUSR REG_ACCESS(RoReg, 0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
+#define REG_PIOE_ABSR REG_ACCESS(RwReg, 0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */
+#define REG_PIOE_SCIFSR REG_ACCESS(WoReg, 0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */
+#define REG_PIOE_DIFSR REG_ACCESS(WoReg, 0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */
+#define REG_PIOE_IFDGSR REG_ACCESS(RoReg, 0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOE_SCDR REG_ACCESS(RwReg, 0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
+#define REG_PIOE_OWER REG_ACCESS(WoReg, 0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
+#define REG_PIOE_OWDR REG_ACCESS(WoReg, 0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
+#define REG_PIOE_OWSR REG_ACCESS(RoReg, 0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
+#define REG_PIOE_AIMER REG_ACCESS(WoReg, 0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
+#define REG_PIOE_AIMDR REG_ACCESS(WoReg, 0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */
+#define REG_PIOE_AIMMR REG_ACCESS(RoReg, 0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
+#define REG_PIOE_ESR REG_ACCESS(WoReg, 0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
+#define REG_PIOE_LSR REG_ACCESS(WoReg, 0x400E16C4U) /**< \brief (PIOE) Level Select Register */
+#define REG_PIOE_ELSR REG_ACCESS(RoReg, 0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
+#define REG_PIOE_FELLSR REG_ACCESS(WoReg, 0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */
+#define REG_PIOE_REHLSR REG_ACCESS(WoReg, 0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */
+#define REG_PIOE_FRLHSR REG_ACCESS(RoReg, 0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
+#define REG_PIOE_LOCKSR REG_ACCESS(RoReg, 0x400E16E0U) /**< \brief (PIOE) Lock Status */
+#define REG_PIOE_WPMR REG_ACCESS(RwReg, 0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */
+#define REG_PIOE_WPSR REG_ACCESS(RoReg, 0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */
+/* ========== Register definition for PIOF peripheral ========== */
+#define REG_PIOF_PER REG_ACCESS(WoReg, 0x400E1800U) /**< \brief (PIOF) PIO Enable Register */
+#define REG_PIOF_PDR REG_ACCESS(WoReg, 0x400E1804U) /**< \brief (PIOF) PIO Disable Register */
+#define REG_PIOF_PSR REG_ACCESS(RoReg, 0x400E1808U) /**< \brief (PIOF) PIO Status Register */
+#define REG_PIOF_OER REG_ACCESS(WoReg, 0x400E1810U) /**< \brief (PIOF) Output Enable Register */
+#define REG_PIOF_ODR REG_ACCESS(WoReg, 0x400E1814U) /**< \brief (PIOF) Output Disable Register */
+#define REG_PIOF_OSR REG_ACCESS(RoReg, 0x400E1818U) /**< \brief (PIOF) Output Status Register */
+#define REG_PIOF_IFER REG_ACCESS(WoReg, 0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */
+#define REG_PIOF_IFDR REG_ACCESS(WoReg, 0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */
+#define REG_PIOF_IFSR REG_ACCESS(RoReg, 0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */
+#define REG_PIOF_SODR REG_ACCESS(WoReg, 0x400E1830U) /**< \brief (PIOF) Set Output Data Register */
+#define REG_PIOF_CODR REG_ACCESS(WoReg, 0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */
+#define REG_PIOF_ODSR REG_ACCESS(RwReg, 0x400E1838U) /**< \brief (PIOF) Output Data Status Register */
+#define REG_PIOF_PDSR REG_ACCESS(RoReg, 0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */
+#define REG_PIOF_IER REG_ACCESS(WoReg, 0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */
+#define REG_PIOF_IDR REG_ACCESS(WoReg, 0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */
+#define REG_PIOF_IMR REG_ACCESS(RoReg, 0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */
+#define REG_PIOF_ISR REG_ACCESS(RoReg, 0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */
+#define REG_PIOF_MDER REG_ACCESS(WoReg, 0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */
+#define REG_PIOF_MDDR REG_ACCESS(WoReg, 0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */
+#define REG_PIOF_MDSR REG_ACCESS(RoReg, 0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */
+#define REG_PIOF_PUDR REG_ACCESS(WoReg, 0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */
+#define REG_PIOF_PUER REG_ACCESS(WoReg, 0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */
+#define REG_PIOF_PUSR REG_ACCESS(RoReg, 0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */
+#define REG_PIOF_ABSR REG_ACCESS(RwReg, 0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */
+#define REG_PIOF_SCIFSR REG_ACCESS(WoReg, 0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */
+#define REG_PIOF_DIFSR REG_ACCESS(WoReg, 0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */
+#define REG_PIOF_IFDGSR REG_ACCESS(RoReg, 0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOF_SCDR REG_ACCESS(RwReg, 0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */
+#define REG_PIOF_OWER REG_ACCESS(WoReg, 0x400E18A0U) /**< \brief (PIOF) Output Write Enable */
+#define REG_PIOF_OWDR REG_ACCESS(WoReg, 0x400E18A4U) /**< \brief (PIOF) Output Write Disable */
+#define REG_PIOF_OWSR REG_ACCESS(RoReg, 0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */
+#define REG_PIOF_AIMER REG_ACCESS(WoReg, 0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */
+#define REG_PIOF_AIMDR REG_ACCESS(WoReg, 0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */
+#define REG_PIOF_AIMMR REG_ACCESS(RoReg, 0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */
+#define REG_PIOF_ESR REG_ACCESS(WoReg, 0x400E18C0U) /**< \brief (PIOF) Edge Select Register */
+#define REG_PIOF_LSR REG_ACCESS(WoReg, 0x400E18C4U) /**< \brief (PIOF) Level Select Register */
+#define REG_PIOF_ELSR REG_ACCESS(RoReg, 0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */
+#define REG_PIOF_FELLSR REG_ACCESS(WoReg, 0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */
+#define REG_PIOF_REHLSR REG_ACCESS(WoReg, 0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */
+#define REG_PIOF_FRLHSR REG_ACCESS(RoReg, 0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */
+#define REG_PIOF_LOCKSR REG_ACCESS(RoReg, 0x400E18E0U) /**< \brief (PIOF) Lock Status */
+#define REG_PIOF_WPMR REG_ACCESS(RwReg, 0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */
+#define REG_PIOF_WPSR REG_ACCESS(RoReg, 0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */
+/* ========== Register definition for RSTC peripheral ========== */
+#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1A00U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1A04U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1A08U) /**< \brief (RSTC) Mode Register */
+/* ========== Register definition for SUPC peripheral ========== */
+#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1A10U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1A14U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1A18U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E1A1CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1A20U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1A24U) /**< \brief (SUPC) Supply Controller Status Register */
+/* ========== Register definition for RTT peripheral ========== */
+#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1A30U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1A34U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1A38U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E1A3CU) /**< \brief (RTT) Status Register */
+/* ========== Register definition for WDT peripheral ========== */
+#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1A50U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1A54U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1A58U) /**< \brief (WDT) Status Register */
+/* ========== Register definition for RTC peripheral ========== */
+#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1A60U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1A64U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1A68U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E1A6CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1A70U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1A78U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR REG_ACCESS(RwReg, 0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */
+/* ========== Register definition for GPBR peripheral ========== */
+#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1A90U) /**< \brief (GPBR) General Purpose Backup Register 0 */
+#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1A94U) /**< \brief (GPBR) General Purpose Backup Register 1 */
+#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1A98U) /**< \brief (GPBR) General Purpose Backup Register 2 */
+#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E1A9CU) /**< \brief (GPBR) General Purpose Backup Register 3 */
+#define REG_GPBR_GPBR4 REG_ACCESS(RwReg, 0x400E1AA0U) /**< \brief (GPBR) General Purpose Backup Register 4 */
+#define REG_GPBR_GPBR5 REG_ACCESS(RwReg, 0x400E1AA4U) /**< \brief (GPBR) General Purpose Backup Register 5 */
+#define REG_GPBR_GPBR6 REG_ACCESS(RwReg, 0x400E1AA8U) /**< \brief (GPBR) General Purpose Backup Register 6 */
+#define REG_GPBR_GPBR7 REG_ACCESS(RwReg, 0x400E1AACU) /**< \brief (GPBR) General Purpose Backup Register 7 */
+/*@}*/
+
+/* ************************************************************************** */
+/* PERIPHERAL ID DEFINITIONS FOR SAM3XA */
+/* ************************************************************************** */
+/** \addtogroup SAM3XA_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_SDRAMC (10) /**< \brief Synchronous Dynamic RAM Controller (SDRAMC) */
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */
+#define ID_PIOE (15) /**< \brief Parallel I/O Controller E (PIOE) */
+#define ID_PIOF (16) /**< \brief Parallel I/O Controller F (PIOF) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_USART3 (20) /**< \brief USART 3 (USART3) */
+#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SPI1 (25) /**< \brief Serial Peripheral Interface (SPI1) */
+#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */
+#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */
+#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */
+#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */
+#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */
+/*@}*/
+
+/* ************************************************************************** */
+/* BASE ADDRESS DEFINITIONS FOR SAM3XA */
+/* ************************************************************************** */
+/** \addtogroup SAM3XA_base Peripheral Base Address Definitions */
+/*@{*/
+
+#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */
+#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */
+#define SPI0 CAST(Spi , 0x40008000U) /**< \brief (SPI0 ) Base Address */
+#define SPI1 CAST(Spi , 0x4000C000U) /**< \brief (SPI1 ) Base Address */
+#define TC0 CAST(Tc , 0x40080000U) /**< \brief (TC0 ) Base Address */
+#define TC1 CAST(Tc , 0x40084000U) /**< \brief (TC1 ) Base Address */
+#define TC2 CAST(Tc , 0x40088000U) /**< \brief (TC2 ) Base Address */
+#define TWI0 CAST(Twi , 0x4008C000U) /**< \brief (TWI0 ) Base Address */
+#define PDC_TWI0 CAST(Pdc , 0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */
+#define TWI1 CAST(Twi , 0x40090000U) /**< \brief (TWI1 ) Base Address */
+#define PDC_TWI1 CAST(Pdc , 0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */
+#define PWM CAST(Pwm , 0x40094000U) /**< \brief (PWM ) Base Address */
+#define PDC_PWM CAST(Pdc , 0x40094100U) /**< \brief (PDC_PWM ) Base Address */
+#define USART0 CAST(Usart , 0x40098000U) /**< \brief (USART0 ) Base Address */
+#define PDC_USART0 CAST(Pdc , 0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1 CAST(Usart , 0x4009C000U) /**< \brief (USART1 ) Base Address */
+#define PDC_USART1 CAST(Pdc , 0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2 CAST(Usart , 0x400A0000U) /**< \brief (USART2 ) Base Address */
+#define PDC_USART2 CAST(Pdc , 0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3 CAST(Usart , 0x400A4000U) /**< \brief (USART3 ) Base Address */
+#define PDC_USART3 CAST(Pdc , 0x400A4100U) /**< \brief (PDC_USART3) Base Address */
+#define UOTGHS CAST(Uotghs , 0x400AC000U) /**< \brief (UOTGHS ) Base Address */
+#define EMAC CAST(Emac , 0x400B0000U) /**< \brief (EMAC ) Base Address */
+#define CAN0 CAST(Can , 0x400B4000U) /**< \brief (CAN0 ) Base Address */
+#define CAN1 CAST(Can , 0x400B8000U) /**< \brief (CAN1 ) Base Address */
+#define TRNG CAST(Trng , 0x400BC000U) /**< \brief (TRNG ) Base Address */
+#define ADC CAST(Adc , 0x400C0000U) /**< \brief (ADC ) Base Address */
+#define PDC_ADC CAST(Pdc , 0x400C0100U) /**< \brief (PDC_ADC ) Base Address */
+#define DMAC CAST(Dmac , 0x400C4000U) /**< \brief (DMAC ) Base Address */
+#define DACC CAST(Dacc , 0x400C8000U) /**< \brief (DACC ) Base Address */
+#define PDC_DACC CAST(Pdc , 0x400C8100U) /**< \brief (PDC_DACC ) Base Address */
+#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */
+#define SDRAMC CAST(Sdramc , 0x400E0200U) /**< \brief (SDRAMC ) Base Address */
+#define MATRIX CAST(Matrix , 0x400E0400U) /**< \brief (MATRIX ) Base Address */
+#define PMC CAST(Pmc , 0x400E0600U) /**< \brief (PMC ) Base Address */
+#define UART CAST(Uart , 0x400E0800U) /**< \brief (UART ) Base Address */
+#define PDC_UART CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART ) Base Address */
+#define CHIPID CAST(Chipid , 0x400E0940U) /**< \brief (CHIPID ) Base Address */
+#define EFC0 CAST(Efc , 0x400E0A00U) /**< \brief (EFC0 ) Base Address */
+#define EFC1 CAST(Efc , 0x400E0C00U) /**< \brief (EFC1 ) Base Address */
+#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */
+#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */
+#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */
+#define PIOD CAST(Pio , 0x400E1400U) /**< \brief (PIOD ) Base Address */
+#define PIOE CAST(Pio , 0x400E1600U) /**< \brief (PIOE ) Base Address */
+#define PIOF CAST(Pio , 0x400E1800U) /**< \brief (PIOF ) Base Address */
+#define RSTC CAST(Rstc , 0x400E1A00U) /**< \brief (RSTC ) Base Address */
+#define SUPC CAST(Supc , 0x400E1A10U) /**< \brief (SUPC ) Base Address */
+#define RTT CAST(Rtt , 0x400E1A30U) /**< \brief (RTT ) Base Address */
+#define WDT CAST(Wdt , 0x400E1A50U) /**< \brief (WDT ) Base Address */
+#define RTC CAST(Rtc , 0x400E1A60U) /**< \brief (RTC ) Base Address */
+#define GPBR CAST(Gpbr , 0x400E1A90U) /**< \brief (GPBR ) Base Address */
+/*@}*/
+
+/* ************************************************************************** */
+/* PIO DEFINITIONS FOR SAM3XA */
+/* ************************************************************************** */
+/** \addtogroup SAM3XA_pio Peripheral Pio Definitions */
+/*@{*/
+
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
+#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
+#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
+#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
+#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
+#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
+#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */
+#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
+#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
+#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
+#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */
+#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */
+#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */
+#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */
+#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */
+#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */
+#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */
+#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */
+#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */
+#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */
+#define PIO_PE6 (1u << 6) /**< \brief Pin Controlled by PE6 */
+#define PIO_PE7 (1u << 7) /**< \brief Pin Controlled by PE7 */
+#define PIO_PE8 (1u << 8) /**< \brief Pin Controlled by PE8 */
+#define PIO_PE9 (1u << 9) /**< \brief Pin Controlled by PE9 */
+#define PIO_PE10 (1u << 10) /**< \brief Pin Controlled by PE10 */
+#define PIO_PE11 (1u << 11) /**< \brief Pin Controlled by PE11 */
+#define PIO_PE12 (1u << 12) /**< \brief Pin Controlled by PE12 */
+#define PIO_PE13 (1u << 13) /**< \brief Pin Controlled by PE13 */
+#define PIO_PE14 (1u << 14) /**< \brief Pin Controlled by PE14 */
+#define PIO_PE15 (1u << 15) /**< \brief Pin Controlled by PE15 */
+#define PIO_PE16 (1u << 16) /**< \brief Pin Controlled by PE16 */
+#define PIO_PE17 (1u << 17) /**< \brief Pin Controlled by PE17 */
+#define PIO_PE18 (1u << 18) /**< \brief Pin Controlled by PE18 */
+#define PIO_PE19 (1u << 19) /**< \brief Pin Controlled by PE19 */
+#define PIO_PE20 (1u << 20) /**< \brief Pin Controlled by PE20 */
+#define PIO_PE21 (1u << 21) /**< \brief Pin Controlled by PE21 */
+#define PIO_PE22 (1u << 22) /**< \brief Pin Controlled by PE22 */
+#define PIO_PE23 (1u << 23) /**< \brief Pin Controlled by PE23 */
+#define PIO_PE24 (1u << 24) /**< \brief Pin Controlled by PE24 */
+#define PIO_PE25 (1u << 25) /**< \brief Pin Controlled by PE25 */
+#define PIO_PE26 (1u << 26) /**< \brief Pin Controlled by PE26 */
+#define PIO_PE27 (1u << 27) /**< \brief Pin Controlled by PE27 */
+#define PIO_PE28 (1u << 28) /**< \brief Pin Controlled by PE28 */
+#define PIO_PE29 (1u << 29) /**< \brief Pin Controlled by PE29 */
+#define PIO_PE30 (1u << 30) /**< \brief Pin Controlled by PE30 */
+#define PIO_PE31 (1u << 31) /**< \brief Pin Controlled by PE31 */
+#define PIO_PF0 (1u << 0) /**< \brief Pin Controlled by PF0 */
+#define PIO_PF1 (1u << 1) /**< \brief Pin Controlled by PF1 */
+#define PIO_PF2 (1u << 2) /**< \brief Pin Controlled by PF2 */
+#define PIO_PF3 (1u << 3) /**< \brief Pin Controlled by PF3 */
+#define PIO_PF4 (1u << 4) /**< \brief Pin Controlled by PF4 */
+#define PIO_PF5 (1u << 5) /**< \brief Pin Controlled by PF5 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC21A_A0_NBS0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PC22A_A1 (1u << 22) /**< \brief Ebi signal: A1 */
+#define PIO_PD0A_A10 (1u << 0) /**< \brief Ebi signal: A10 */
+#define PIO_PD22A_A10 (1u << 22) /**< \brief Ebi signal: A10 */
+#define PIO_PD1A_A11 (1u << 1) /**< \brief Ebi signal: A11 */
+#define PIO_PD23A_A11 (1u << 23) /**< \brief Ebi signal: A11 */
+#define PIO_PD2A_A12 (1u << 2) /**< \brief Ebi signal: A12 */
+#define PIO_PD24A_A12 (1u << 24) /**< \brief Ebi signal: A12 */
+#define PIO_PD3A_A13 (1u << 3) /**< \brief Ebi signal: A13 */
+#define PIO_PD25A_A13 (1u << 25) /**< \brief Ebi signal: A13 */
+#define PIO_PD4A_A14 (1u << 4) /**< \brief Ebi signal: A14 */
+#define PIO_PD26A_A14 (1u << 26) /**< \brief Ebi signal: A14 */
+#define PIO_PD5A_A15 (1u << 5) /**< \brief Ebi signal: A15 */
+#define PIO_PD27A_A15 (1u << 27) /**< \brief Ebi signal: A15 */
+#define PIO_PD6A_A16_BA0 (1u << 6) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD28A_A16_BA0 (1u << 28) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD7A_A17_BA1 (1u << 7) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD29A_A17_BA1 (1u << 29) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PA25B_A18 (1u << 25) /**< \brief Ebi signal: A18 */
+#define PIO_PB10B_A18 (1u << 10) /**< \brief Ebi signal: A18 */
+#define PIO_PD30A_A18 (1u << 30) /**< \brief Ebi signal: A18 */
+#define PIO_PA26B_A19 (1u << 26) /**< \brief Ebi signal: A19 */
+#define PIO_PB11B_A19 (1u << 11) /**< \brief Ebi signal: A19 */
+#define PIO_PE0A_A19 (1u << 0) /**< \brief Ebi signal: A19 */
+#define PIO_PC23A_A2 (1u << 23) /**< \brief Ebi signal: A2 */
+#define PIO_PA18B_A20 (1u << 18) /**< \brief Ebi signal: A20 */
+#define PIO_PA27B_A20 (1u << 27) /**< \brief Ebi signal: A20 */
+#define PIO_PE1A_A20 (1u << 1) /**< \brief Ebi signal: A20 */
+#define PIO_PD8A_A21_NANDALE (1u << 8) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PE2A_A21_NANDALE (1u << 2) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PD9A_A22_NANDCLE (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE3A_A22_NANDCLE (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE4A_A23 (1u << 4) /**< \brief Ebi signal: A23 */
+#define PIO_PC24A_A3 (1u << 24) /**< \brief Ebi signal: A3 */
+#define PIO_PC25A_A4 (1u << 25) /**< \brief Ebi signal: A4 */
+#define PIO_PC26A_A5 (1u << 26) /**< \brief Ebi signal: A5 */
+#define PIO_PD17A_A5 (1u << 17) /**< \brief Ebi signal: A5 */
+#define PIO_PC27A_A6 (1u << 27) /**< \brief Ebi signal: A6 */
+#define PIO_PD18A_A6 (1u << 18) /**< \brief Ebi signal: A6 */
+#define PIO_PC28A_A7 (1u << 28) /**< \brief Ebi signal: A7 */
+#define PIO_PD19A_A7 (1u << 19) /**< \brief Ebi signal: A7 */
+#define PIO_PC29A_A8 (1u << 29) /**< \brief Ebi signal: A8 */
+#define PIO_PD20A_A8 (1u << 20) /**< \brief Ebi signal: A8 */
+#define PIO_PC30A_A9 (1u << 30) /**< \brief Ebi signal: A9 */
+#define PIO_PD21A_A9 (1u << 21) /**< \brief Ebi signal: A9 */
+#define PIO_PD16A_CAS (1u << 16) /**< \brief Ebi signal: CAS */
+#define PIO_PC2A_D0 (1u << 2) /**< \brief Ebi signal: D0 */
+#define PIO_PC3A_D1 (1u << 3) /**< \brief Ebi signal: D1 */
+#define PIO_PC12A_D10 (1u << 12) /**< \brief Ebi signal: D10 */
+#define PIO_PC13A_D11 (1u << 13) /**< \brief Ebi signal: D11 */
+#define PIO_PC14A_D12 (1u << 14) /**< \brief Ebi signal: D12 */
+#define PIO_PC15A_D13 (1u << 15) /**< \brief Ebi signal: D13 */
+#define PIO_PC16A_D14 (1u << 16) /**< \brief Ebi signal: D14 */
+#define PIO_PC17A_D15 (1u << 17) /**< \brief Ebi signal: D15 */
+#define PIO_PC4A_D2 (1u << 4) /**< \brief Ebi signal: D2 */
+#define PIO_PC5A_D3 (1u << 5) /**< \brief Ebi signal: D3 */
+#define PIO_PC6A_D4 (1u << 6) /**< \brief Ebi signal: D4 */
+#define PIO_PC7A_D5 (1u << 7) /**< \brief Ebi signal: D5 */
+#define PIO_PC8A_D6 (1u << 8) /**< \brief Ebi signal: D6 */
+#define PIO_PC9A_D7 (1u << 9) /**< \brief Ebi signal: D7 */
+#define PIO_PC10A_D8 (1u << 10) /**< \brief Ebi signal: D8 */
+#define PIO_PC11A_D9 (1u << 11) /**< \brief Ebi signal: D9 */
+#define PIO_PC19A_NANDOE (1u << 19) /**< \brief Ebi signal: NANDOE */
+#define PIO_PA2B_NANDRDY (1u << 2) /**< \brief Ebi signal: NANDRDY */
+#define PIO_PC20A_NANDWE (1u << 20) /**< \brief Ebi signal: NANDWE */
+#define PIO_PA6B_NCS0 (1u << 6) /**< \brief Ebi signal: NCS0 */
+#define PIO_PA7B_NCS1 (1u << 7) /**< \brief Ebi signal: NCS1 */
+#define PIO_PB24B_NCS2 (1u << 24) /**< \brief Ebi signal: NCS2 */
+#define PIO_PB27A_NCS3 (1u << 27) /**< \brief Ebi signal: NCS3 */
+#define PIO_PE5A_NCS4 (1u << 5) /**< \brief Ebi signal: NCS4 */
+#define PIO_PE6A_NCS5 (1u << 6) /**< \brief Ebi signal: NCS5 */
+#define PIO_PE18B_NCS6 (1u << 18) /**< \brief Ebi signal: NCS6 */
+#define PIO_PE27A_NCS7 (1u << 27) /**< \brief Ebi signal: NCS7 */
+#define PIO_PA29B_NRD (1u << 29) /**< \brief Ebi signal: NRD */
+#define PIO_PA4B_NWAIT (1u << 4) /**< \brief Ebi signal: NWAIT */
+#define PIO_PC18A_NWR0_NWE (1u << 18) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PD10A_NWR1_NBS1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PD15A_RAS (1u << 15) /**< \brief Ebi signal: RAS */
+#define PIO_PD11A_SDA10 (1u << 11) /**< \brief Ebi signal: SDA10 */
+#define PIO_PD13A_SDCKE (1u << 13) /**< \brief Ebi signal: SDCKE */
+#define PIO_PD12A_SDCS (1u << 12) /**< \brief Ebi signal: SDCS */
+#define PIO_PD14A_SDWE (1u << 14) /**< \brief Ebi signal: SDWE */
+/* ========== Pio definition for EMAC peripheral ========== */
+#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */
+#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */
+#define PIO_PB4A_ECRSDV_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */
+#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */
+#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */
+#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */
+#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */
+#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */
+#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */
+#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */
+#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */
+#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */
+#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */
+#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */
+#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */
+#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */
+#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SPI1 peripheral ========== */
+#define PIO_PE28A_SPI1_MISO (1u << 28) /**< \brief Spi1 signal: SPI1_MISO */
+#define PIO_PE29A_SPI1_MOSI (1u << 29) /**< \brief Spi1 signal: SPI1_MOSI */
+#define PIO_PE31A_SPI1_NPCS0 (1u << 31) /**< \brief Spi1 signal: SPI1_NPCS0 */
+#define PIO_PF0A_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
+#define PIO_PF1A_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
+#define PIO_PF2A_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
+#define PIO_PE30A_SPI1_SPCK (1u << 30) /**< \brief Spi1 signal: SPI1_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TC2 peripheral ========== */
+#define PIO_PC27B_TCLK6 (1u << 27) /**< \brief Tc2 signal: TCLK6 */
+#define PIO_PC30B_TCLK7 (1u << 30) /**< \brief Tc2 signal: TCLK7 */
+#define PIO_PD9B_TCLK8 (1u << 9) /**< \brief Tc2 signal: TCLK8 */
+#define PIO_PC25B_TIOA6 (1u << 25) /**< \brief Tc2 signal: TIOA6 */
+#define PIO_PC28B_TIOA7 (1u << 28) /**< \brief Tc2 signal: TIOA7 */
+#define PIO_PD7B_TIOA8 (1u << 7) /**< \brief Tc2 signal: TIOA8 */
+#define PIO_PC26B_TIOB6 (1u << 26) /**< \brief Tc2 signal: TIOB6 */
+#define PIO_PC29B_TIOB7 (1u << 29) /**< \brief Tc2 signal: TIOB7 */
+#define PIO_PD8B_TIOB8 (1u << 8) /**< \brief Tc2 signal: TIOB8 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio definition for USART3 peripheral ========== */
+#define PIO_PF4A_CTS3 (1u << 4) /**< \brief Usart3 signal: CTS3 */
+#define PIO_PF5A_RTS3 (1u << 5) /**< \brief Usart3 signal: RTS3 */
+#define PIO_PD5B_RXD3 (1u << 5) /**< \brief Usart3 signal: RXD3 */
+#define PIO_PE16B_SCK3 (1u << 16) /**< \brief Usart3 signal: SCK3 */
+#define PIO_PD4B_TXD3 (1u << 4) /**< \brief Usart3 signal: TXD3 */
+/*@}*/
+
+/* ************************************************************************** */
+/* MEMORY MAPPING DEFINITIONS FOR SAM3XA */
+/* ************************************************************************** */
+
+#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */
+
+#if defined sam3x2
+# define IFLASH1_ADDR (0x00090000u) /**< Internal Flash 1 base address */
+# define IFLASH_SIZE (0x20000u)
+# define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */
+# define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */
+# define IFLASH_NB_OF_PAGES (256) /* Internal FLASH 0 Number of Pages: 256 */
+# define IFLASH_NB_OF_LOCK_BITS (8) /* Internal FLASH 0 Number of Lock Bits: 8 */
+
+# define NFC_RAM_SIZE (0x1000u)
+
+# define IRAM0_SIZE (0x4000u)
+# define IRAM1_SIZE (0x4000u)
+# define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)
+# define IRAM_ADDR (IRAM1_ADDR-IRAM0_SIZE)
+#elif defined sam3x2c | defined sam3a2
+# define IFLASH1_ADDR (0x00090000u) /**< Internal Flash 1 base address */
+# define IFLASH_SIZE (0x20000u)
+# define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */
+# define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */
+# define IFLASH_NB_OF_PAGES (256) /* Internal FLASH 0 Number of Pages: 256 */
+# define IFLASH_NB_OF_LOCK_BITS (8) /* Internal FLASH 0 Number of Lock Bits: 8 */
+# define IRAM_SIZE 0x8000
+
+# define IRAM0_SIZE (0x4000u)
+# define IRAM1_SIZE (0x4000u)
+# define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)
+# define IRAM_ADDR (IRAM1_ADDR-IRAM0_SIZE)
+#elif defined sam3x4
+# define IFLASH1_ADDR (0x000A0000u) /**< Internal Flash 1 base address */
+# define IFLASH_SIZE (0x40000u)
+# define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */
+# define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */
+# define IFLASH_NB_OF_PAGES (512) /* Internal FLASH 0 Number of Pages: 512 */
+# define IFLASH_NB_OF_LOCK_BITS (16) /* Internal FLASH 0 Number of Lock Bits: 16 */
+
+# define NFC_RAM_SIZE (0x1000u)
+
+# define IRAM0_SIZE (0x8000u)
+# define IRAM1_SIZE (0x8000u)
+# define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)
+# define IRAM_ADDR (IRAM1_ADDR-IRAM0_SIZE)
+#elif defined sam3x4c | defined sam3a4
+# define IFLASH1_ADDR (0x000A0000u) /**< Internal Flash 1 base address */
+# define IFLASH_SIZE (0x40000u)
+# define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */
+# define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */
+# define IFLASH_NB_OF_PAGES (512) /* Internal FLASH 0 Number of Pages: 512 */
+# define IFLASH_NB_OF_LOCK_BITS (16) /* Internal FLASH 0 Number of Lock Bits: 16 */
+
+# define IRAM0_SIZE (0x8000u)
+# define IRAM1_SIZE (0x8000u)
+# define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)
+# define IRAM_ADDR (IRAM1_ADDR-IRAM0_SIZE)
+#elif defined sam3x8
+# define IFLASH1_ADDR (0x000C0000u) /**< Internal Flash 1 base address */
+# define IFLASH_SIZE (0x80000u)
+# define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */
+# define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */
+# define IFLASH_NB_OF_PAGES (1024) /* Internal FLASH 0 Number of Pages: 1024 */
+# define IFLASH_NB_OF_LOCK_BITS (32) /* Internal FLASH 0 Number of Lock Bits: 32 */
+
+# define NFC_RAM_SIZE (0x1000u)
+
+# define IRAM0_SIZE (0x10000u)
+# define IRAM1_SIZE (0x8000u)
+# define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)
+# define IRAM_ADDR (IRAM1_ADDR-IRAM0_SIZE)
+#elif defined sam3x8c | defined sam3a8
+# define IFLASH1_ADDR (0x000C0000u) /**< Internal Flash 1 base address */
+# define IFLASH_SIZE (0x80000u)
+# define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */
+# define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */
+# define IFLASH_NB_OF_PAGES (1024) /* Internal FLASH 0 Number of Pages: 1024 */
+# define IFLASH_NB_OF_LOCK_BITS (32) /* Internal FLASH 0 Number of Lock Bits: 32 */
+
+# define IRAM0_SIZE (0x10000u)
+# define IRAM1_SIZE (0x8000u)
+# define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)
+# define IRAM_ADDR (IRAM1_ADDR-IRAM0_SIZE)
+#else
+ #error Library does not support the specified device.
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAM3XA_H */
+
+
+
+#endif
diff --git a/library/ADK2/SD.c b/library/ADK2/SD.c
new file mode 100644
index 0000000..db46baf
--- /dev/null
+++ b/library/ADK2/SD.c
@@ -0,0 +1,597 @@
+/*
+Copyright (c) 2011, Dmitry Grinberg (as published on http://dmitrygr.com)
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following condition is met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "SD.h"
+
+
+
+
+
+static const uint8_t pinCD = PORTA(5);
+static const uint8_t pinsSD[] = {PORTA(7), PORTA(19), PORTA(20), PORTA(21)};
+#define CS 0
+#define SCLK 1
+#define MOSI 2
+#define MISO 3
+
+
+
+#define FLAG_TIMEOUT 0x80
+#define FLAG_PARAM_ERR 0x40
+#define FLAG_ADDR_ERR 0x20
+#define FLAG_ERZ_SEQ_ERR 0x10
+#define FLAG_CMD_CRC_ERR 0x08
+#define FLAG_ILLEGAL_CMD 0x04
+#define FLAG_ERZ_RST 0x02
+#define FLAG_IN_IDLE_MODE 0x01
+
+
+
+char gSdSpiFast = 1;
+
+static void sdClockSpeed(char fast){
+
+ gSdSpiFast = fast;
+}
+
+static uint8_t sdSpiByte(uint32_t v){
+
+ uint32_t r = 0;
+
+ #define BIT(m, d) \
+ do{ \
+ gpioSetVal(pinsSD[MOSI], !!(v & (m))); \
+ gpioSetVal(pinsSD[SCLK], 1); \
+ d; \
+ if(gpioGetVal(pinsSD[MISO])) \
+ r |= (m); \
+ gpioSetVal(pinsSD[SCLK], 0); \
+ }while(0)
+
+ #define ASMBIT \
+ "lsls %1, #1 \n\t" \
+ "ite cs \n\t" \
+ "strcs r4, [r2, #0x30] \n\t" \
+ "strcc r4, [r2, #0x34] \n\t" \
+ "str r1, [r2, #0x30] \n\t" \
+ "ldr r3, [r2, #0x3C] \n\t" \
+ "str r1, [r2, #0x34] \n\t" \
+ "lsrs r3, #22 \n\t" \
+ "adcs %0, %0 \n\t"
+
+ if(gSdSpiFast){
+
+
+ asm(
+ "mov r4, #0x100000 \n\t" //mosi
+ "mov r1, #0x080000 \n\t" //sclk
+ "ldr r2, =0x400E0E00 \n\t" //PIOA
+ "lsl %1, #24 \n\t" //cleverness
+ ASMBIT
+ ASMBIT
+ ASMBIT
+ ASMBIT
+ ASMBIT
+ ASMBIT
+ ASMBIT
+ ASMBIT
+ :"=l"(r)
+ :"l"(v)
+ :"cc", "r4", "r1", "r2", "r3"
+ );
+
+ }
+ else{
+
+ volatile uint32_t x;
+ uint8_t t;
+
+ for(t = 0; t < 8; t++){
+
+ BIT(1 << (7 - t), for(x = 0; x < 0x10; x += 2) x--);
+ for(x = 0; x < 0x10; x += 2) x--;
+ }
+ }
+
+ return r;
+}
+
+uint8_t* __attribute__((naked)) sdStreamSec(uint8_t* buf){
+
+#define RDBIT \
+ "str r1, [r2, #0x30] \n\t" \
+ "ldr r3, [r2, #0x3C] \n\t" \
+ "str r1, [r2, #0x34] \n\t" \
+ "lsrs r3, #22 \n\t" \
+ "adcs r4, r4 \n\t"
+
+ asm(
+ " push {r4,r5,lr} \n\t"
+ " ldr r2, =0x400E0E00 \n\t"
+ " mov r1, #0x100000 \n\t" //mosi
+ " str r1, [r2, #0x30] \n\t"
+ " mov r1, #0x080000 \n\t"
+ " mov r5, #128 \n\t"
+ "loop: \n\t"
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ RDBIT
+ " rev r4, r4 \n\t"
+ " str r4, [r0], #4 \n\t"
+ " subs r5, #1 \n\t"
+ " bne loop \n\t"
+ " pop {r4,r5,pc} \n\t"
+ );
+}
+
+static void sdChipSelect(char on){
+
+ gpioSetVal(pinsSD[CS], !on);
+}
+
+static uint8_t sdCrc7(uint8_t* chr,uint8_t cnt,uint8_t crc){
+
+ uint8_t i, a;
+ uint8_t Data;
+
+ for(a = 0; a < cnt; a++){
+
+ Data = chr[a];
+
+ for(i = 0; i < 8; i++){
+
+ crc <<= 1;
+
+ if( (Data & 0x80) ^ (crc & 0x80) ) crc ^= 0x09;
+
+ Data <<= 1;
+ }
+ }
+
+ return crc & 0x7F;
+}
+
+static inline void sdPrvSendCmd(uint8_t cmd, uint32_t param, char crc){
+
+ uint8_t send[6];
+ uint8_t L = crc ? 6 : 5;
+
+ send[0] = cmd | 0x40;
+ send[1] = param >> 24;
+ send[2] = param >> 16;
+ send[3] = param >> 8;
+ send[4] = param;
+ send[5] = crc ? (sdCrc7(send, 5, 0) << 1) | 1 : 0;
+
+ for(cmd = 0; cmd < L; cmd++) sdSpiByte(send[cmd]);
+}
+
+static uint8_t sdPrvSimpleCommand(uint8_t cmd, uint32_t param, char crc, char cmdDone){ //do a command, return R1 reply
+
+ uint8_t ret;
+ uint8_t i = 0;
+
+ sdChipSelect(1);
+ sdPrvSendCmd(cmd, param, crc);
+
+ do{ //our max wait time is 128 byte clocks (1024 clock ticks)
+
+ ret = sdSpiByte(0xFF);
+
+ }while(i++ < 128 && (ret == 0xFF));
+ if(cmdDone){
+ sdChipSelect(0);
+ sdSpiByte(0xFF);
+ }
+
+ return ret;
+}
+
+static uint8_t sdPrvReadData(uint8_t* data, uint32_t sz, char cmdDone){
+
+ uint8_t ret;
+ uint16_t tries = 20000;
+
+ do{
+ ret = sdSpiByte(0xFF);
+ if((ret & 0xF0) == 0x00) return ret; //fail
+ if(ret == 0xFE) break;
+ tries--;
+ }while(tries);
+
+ if(!tries) return 0xFF;
+
+ *data = ret;
+
+ ret = 0;
+
+ while(sz--) *data++ = sdSpiByte(0xFF);
+
+ if(cmdDone){
+ sdChipSelect(0);
+ sdSpiByte(0xFF);
+ }
+
+ return ret;
+}
+
+static uint8_t sdPrvACMD(uint8_t cmd, uint32_t param, char crc){
+
+ uint8_t ret;
+
+ ret = sdPrvSimpleCommand(55, 0, crc, 1);
+ if(ret & FLAG_TIMEOUT) return ret;
+ if(ret & FLAG_ILLEGAL_CMD) return ret;
+
+ return sdPrvSimpleCommand(cmd, param, crc, 1);
+}
+
+static char sdPrvCardInit(char sd, char hc){
+
+ uint32_t time = 0;
+ uint32_t resp;
+ uint32_t param;
+
+ param = hc ? (1UL<< 30) : 0;
+
+ while(time++ < 10000UL){ //retry 10..0 times
+
+ resp = sd ? sdPrvACMD(41, param, 1) : sdPrvSimpleCommand(1, param, 1, 1);
+ if(resp & FLAG_TIMEOUT) break;
+ if(!(resp & FLAG_IN_IDLE_MODE)) return 1;
+ }
+
+ return 0;
+}
+
+static uint32_t sdPrvGetBits(uint8_t* data,uint32_t numBytesInArray,uint32_t startBit,uint32_t len){//for CID and CSD data..
+
+ uint32_t bitWrite = 0;
+ uint32_t numBitsInArray = numBytesInArray * 8;
+ uint32_t ret = 0;
+
+ do{
+
+ uint32_t bit,byte;
+
+ bit = numBitsInArray - startBit - 1;
+ byte = bit / 8;
+ bit = 7 - (bit % 8);
+
+ ret |= ((data[byte] >> bit) & 1) << (bitWrite++);
+
+ startBit++;
+ }while(--len);
+
+ return ret;
+}
+
+static uint32_t sdPrvGetCardNumBlocks(char mmc,uint8_t* csd){
+
+ uint32_t ver = sdPrvGetBits(csd,16,126,2);
+ uint32_t cardSz = 0;
+
+
+ if(ver == 0 || (mmc && ver <= 2)){
+
+ uint32_t cSize = sdPrvGetBits(csd,16,62,12);
+ uint32_t cSizeMult = sdPrvGetBits(csd,16,47,3);
+ uint32_t readBlLen = sdPrvGetBits(csd,16,80,4);
+ uint32_t blockLen,blockNr;
+ uint32_t divTimes = 9; //from bytes to blocks division
+
+ blockLen = 1UL << readBlLen;
+ blockNr = (cSize + 1) * (1UL << (cSizeMult + 2));
+
+ /*
+ multiplying those two produces result in bytes, we need it in blocks
+ so we shift right 9 times. doing it after multiplication might fuck up
+ the 4GB card, so we do it before, but to avoid killing significant bits
+ we only cut the zero-valued bits, if at the end we end up with non-zero
+ "divTimes", divide after multiplication, and thus underuse the card a bit.
+ This will never happen in reality since 512 is 2^9, and we are
+ multiplying two numbers whose product is a multiple of 2^9, so they
+ togethr should have at least 9 lower zero bits.
+ */
+
+ while(divTimes && !(blockLen & 1)){
+
+ blockLen = blockLen >> 1;
+ divTimes--;
+ }
+ while(divTimes && !(blockNr & 1)){
+
+ blockNr = blockNr >> 1;
+ divTimes--;
+ }
+
+ cardSz = (blockNr * blockLen) >> divTimes;
+ }
+ else if(ver == 1){
+
+ cardSz = sdPrvGetBits(csd,16,48,22)/*num 512K blocks*/ << 10;
+ }
+
+
+ return cardSz;
+}
+
+char sdInit(SD* sd){
+
+ uint8_t v, t;
+ uint16_t retries = 1050;
+ uint8_t respBuf[16];
+
+ dbgPrintf("SD: initing\n");
+
+ gpioSetFun(pinCD, GPIO_FUNC_GPIO);
+ gpioSetDir(pinCD, 1);
+
+ for(v = 0; v < sizeof(pinsSD); v++){
+
+ gpioSetFun(pinsSD[v], GPIO_FUNC_GPIO);
+ gpioSetDir(pinsSD[v], 0);
+ gpioSetVal(pinsSD[v], 0);
+ }
+ gpioSetDir(pinsSD[MISO], 1);
+ gpioSetVal(pinsSD[CS], 1);
+
+ sd->inited = 0;
+ sd->SD = 0;
+ sd->HC = 0;
+
+ sdClockSpeed(0);
+ sdChipSelect(0);
+ for(v = 0; v < 10; v++) sdSpiByte(0xFF); //80 clocks with CS not asserted to give card time to init
+
+ while(0x01 != sdPrvSimpleCommand(0, 0, 1, 1)) if(!--retries) return 0; //always a good idea
+
+ v = sdPrvSimpleCommand(8, 0x000001AAUL, 1, 0); //try CMD8 to init SDHC cards
+ if(v & FLAG_TIMEOUT) return 0;
+ sdSpiByte(0xFF); //ignore the reply
+ sdSpiByte(0xFF);
+ sdSpiByte(0xFF);
+ sdSpiByte(0xFF);
+ sdChipSelect(0);
+ sdSpiByte(0xFF);
+
+ v = sdPrvSimpleCommand(55, 0, 1, 1); //see if this is SD or MMC
+ if(v & FLAG_TIMEOUT) return 0;
+ sd->SD = !(v & FLAG_ILLEGAL_CMD);
+
+ dbgPrintf("SD: card is likely %s\n", sd->SD ? "SD" : "MMC");
+
+ if(sd->SD){
+
+ if(!sdPrvCardInit(1, 1) && !sdPrvCardInit(1, 0)){
+
+ return 0;
+ }
+
+ v = sdPrvSimpleCommand(58,0, 1, 0); //see if it is HC
+ t = sdSpiByte(0xFF); //get the reply
+ sdSpiByte(0xFF);
+ sdSpiByte(0xFF);
+ sdSpiByte(0xFF);
+ sdChipSelect(0);
+ sdSpiByte(0xFF);
+ if(v) t = 0;
+ if(t & 0x40) sd->HC = 1;
+ }
+ else{
+
+ if(!sdPrvCardInit(0, 1) && !sdPrvCardInit(0, 0)){
+
+ return 0;
+ }
+ }
+
+ v = sdPrvSimpleCommand(59, 0, 1, 1); //crc off
+ if(v & FLAG_TIMEOUT) return 0;
+
+ v = sdPrvSimpleCommand(9, 0, 0, 0); //read CSD
+ if(v & FLAG_TIMEOUT) return 0;
+
+ v = sdPrvReadData(respBuf, 16, 1);
+ if(v) return 0;
+
+ sd->numSec = sdPrvGetCardNumBlocks(!sd->SD, respBuf);
+ sd->inited = 1;
+
+ sdClockSpeed(1);
+
+ return 1;
+}
+
+uint32_t sdGetNumSec(SD* sd){
+
+ return sd->inited ? sd->numSec : 0;
+}
+
+char sdSecRead(SD* sd, uint32_t sec, void* buf){ //CMD17
+
+ uint8_t v, retry = 0;
+ char ret = 0;
+
+ if(!sd->inited) return 0;
+
+ do{
+
+ v = sdPrvSimpleCommand(17, sd->HC ? sec : sec << 9, 0, 0);
+ if(v & FLAG_TIMEOUT) return 0;
+
+ v = sdPrvReadData(buf, 0, 0);
+ sdStreamSec(buf);
+ sdSpiByte(0xFF); //skip crc
+ sdSpiByte(0xFF);
+ sdChipSelect(0);
+ if(!v){
+ ret = 1;
+ break;
+ }
+
+
+ }while(++retry < 5); //retry up to 5 times
+
+ return ret;
+}
+
+
+char sdSecWrite(SD* sd, uint32_t sec, const void* buf){ //CMD24
+
+ uint32_t v16;
+ uint8_t v, retry = 0;
+ uint8_t* buf_ = buf;
+ char ret = 0;
+
+
+ if(!sd->inited) return 0;
+
+ do{
+
+ v = sdPrvSimpleCommand(24, sd->HC ? sec : sec << 9, 0, 0);
+ if(v & FLAG_TIMEOUT) return 0;
+
+ sdSpiByte(0xFF); //as per SD-spi spec, we give it 8 clocks to consider the ramifications of the command we just sent
+
+ sdSpiByte(0xFE); //start of data block
+ for(v16 = 0; v16 < SD_BLOCK_SIZE; v16++) sdSpiByte(*buf_++); //data
+
+
+ while((v = sdSpiByte(0xFF)) == 0xFF); //wait while card isnt answering
+ while(sdSpiByte(0xFF) != 0xFF); //wait while card is busy
+
+ if((v & 0x1F) == 5){
+ ret = 1;
+ break;
+ }
+
+ }while(++retry < 5); //retry up to 5 times
+
+ return ret;
+}
+
+
+
+
+
+//stream mode
+char sdReadStart(SD* sd, uint32_t sec){
+
+ uint8_t v;
+
+ v = sdPrvSimpleCommand(18, sd->HC ? sec : sec << 9, 0, 0);
+ if(v & FLAG_TIMEOUT) return 0;
+
+ do{
+ v = sdSpiByte(0xFF);
+ }while(v == 0xFF);
+ if(v != 0xFE){
+ sdChipSelect(0);
+ return 0;
+ }
+ return 1;
+}
+
+void sdNextSec(SD* sd){
+
+ uint8_t v;
+
+ sdSpiByte(0xFF); //skip crc
+ sdSpiByte(0xFF);
+
+ do{
+ v = sdSpiByte(0xFF);
+ }while(v == 0xFF);
+}
+
+void sdSecReadStop(SD* sd){
+
+ sdChipSelect(0);
+ sdSpiByte(0xFF); //skip crc
+ sdSpiByte(0xFF);
+
+ //cancel read
+ sdPrvSimpleCommand(12, 0, 0, 1);
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/library/ADK2/SD.h b/library/ADK2/SD.h
new file mode 100644
index 0000000..341ce39
--- /dev/null
+++ b/library/ADK2/SD.h
@@ -0,0 +1,29 @@
+#ifdef ADK_INTERNAL
+#ifndef _SD_H_
+#define _SD_H_
+
+
+#define SD_BLOCK_SIZE 512
+
+typedef struct{
+
+ uint32_t numSec;
+ uint8_t HC : 1;
+ uint8_t inited : 1;
+ uint8_t SD : 1;
+
+}SD;
+
+char sdInit(SD* sd);
+uint32_t sdGetNumSec(SD* sd);
+char sdSecRead(SD* sd, uint32_t sec, void* buf);
+char sdSecWrite(SD* sd, uint32_t sec, const void* buf);
+
+//stream mode
+char sdReadStart(SD* sd, uint32_t sec);
+void sdNextSec(SD* sd);
+void sdSecReadStop(SD* sd);
+uint8_t* sdStreamSec(uint8_t* buf); //returns ptr to end of buffer...
+
+#endif
+#endif
diff --git a/library/ADK2/accel.c b/library/ADK2/accel.c
new file mode 100644
index 0000000..e4fc23d
--- /dev/null
+++ b/library/ADK2/accel.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "accel.h"
+#include "I2C.h"
+
+
+
+char accelInit(void){ //0 on failure
+
+ if(i2cScan(1, 0x19) == I2C_ERR_NAK) return 0; //not found
+
+ i2cSingleWrite(1, 0x19, 0x24, 0x80);
+ i2cSingleWrite(1, 0x19, 0x24, 0x00);
+
+ i2cSingleWrite(1, 0x19, 0x20, 0x97); // 1.344khz sample rate, no low power, all axes enabled
+ i2cSingleWrite(1, 0x19, 0x23, 0x80);
+ i2cSingleWrite(1, 0x19, 0x24, 0x00);
+
+ return 1;
+}
+
+
+void accelRead(int16_t* x, int16_t* y, int16_t* z){
+
+ while(!(i2cSingleRead(1, 0x19, 0x27) & 8));
+
+ if(x) *x = (int16_t)((uint16_t)i2cSingleRead(1, 0x19, 0x28) | ((uint16_t)i2cSingleRead(1, 0x19, 0x29) << 8));
+ if(y) *y = (int16_t)((uint16_t)i2cSingleRead(1, 0x19, 0x2A) | ((uint16_t)i2cSingleRead(1, 0x19, 0x2B) << 8));
+ if(z) *z = (int16_t)((uint16_t)i2cSingleRead(1, 0x19, 0x2C) | ((uint16_t)i2cSingleRead(1, 0x19, 0x2D) << 8));
+}
diff --git a/library/ADK2/accel.h b/library/ADK2/accel.h
new file mode 100644
index 0000000..c3ad879
--- /dev/null
+++ b/library/ADK2/accel.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _ACCEL_H_
+#define _ACCEL_H_
+
+
+
+char accelInit(void);
+void accelRead(int16_t* x, int16_t* y, int16_t* z);
+
+
+#endif
+#endif
+
diff --git a/library/ADK2/accessory.c b/library/ADK2/accessory.c
new file mode 100644
index 0000000..a18d919
--- /dev/null
+++ b/library/ADK2/accessory.c
@@ -0,0 +1,394 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Arduino.h"
+#include "string.h"
+#include "conf_usb.h"
+#include "usb_drv.h"
+#include "usb_ids.h"
+
+#define ADK_INTERNAL
+#include "Audio.h"
+#include "usbh.h"
+
+#define ACCESSORY_TIMEOUT 1000
+
+static int inpipe = -1;
+static int outpipe = -1;
+static int audiopipe = -1;
+static int audiopacketsize = -1;
+
+/* audio state */
+#define AUDBUFSIZE 682
+#define AUDBUFCOUNT 3
+static uint16_t *audbuf = 0x20100000; // flash memory controller's unused 4K buffer
+static size_t audbufpos;
+static int curraudbuf = 0;
+#define MAX_SAMPLE_SKEW 50
+static int audsamplerate;
+static int audsampleratebase;
+static uint8_t audrecvbuf[256]; // receive buffer for the iso endpoint
+
+static void audio_iso_callback(void *arg, int result, void *buf, size_t pos);
+size_t process_audio(uint16_t *outbuf, uint16_t *inbuf, size_t len);
+
+static int total_samp = 0;
+
+#define READ8(ptr, pos) (*(((uint8_t *)ptr) + pos))
+#define READ16(ptr, pos) (*(uint16_t *)(((uint8_t *)ptr) + pos))
+
+int accessory_init(usbh_device_t *dev)
+{
+ TRACE_OTG("vid 0x%x, pid 0x%x, devaddr %d\n", dev->vid, dev->pid, dev->address);
+
+ // main accessory endpoints
+ uint8_t inendp = 0;
+ size_t inpacketsize = 0;
+ uint8_t outendp = 0;
+ size_t outpacketsize = 0;
+
+ // audio interfaces
+ bool audio = false;
+ uint8_t audioendp = 0;
+ uint8_t audiointerface = 0;
+ uint8_t audio_alternate_setting = 0;
+
+ // find the correct endpoint
+ int pos = 0;
+ int total_len = READ16(dev->devconfig, OFFSET_FIELD_TOTAL_LENGTH);
+ bool found_acc_interface = false;
+ bool found_audio_interface = false;
+ while (pos < total_len) {
+ uint8_t length = READ8(dev->devconfig, pos);
+ uint8_t type = READ8(dev->devconfig, pos + 1);
+
+ TRACE_OTG("DESCRIPTOR: type %d, length %d\n", type, length);
+
+ switch (type) {
+ case DESCRIPTOR_INTERFACE: {
+ uint8_t num_ep = READ8(dev->devconfig, pos + OFFSET_FIELD_NB_OF_EP);
+ uint8_t class = READ8(dev->devconfig, pos + OFFSET_FIELD_CLASS);
+ uint8_t sub_class = READ8(dev->devconfig, pos + OFFSET_FIELD_SUB_CLASS);
+ uint8_t protocol = READ8(dev->devconfig, pos + OFFSET_FIELD_PROTOCOL);
+
+ TRACE_OTG("\tINTERFACE: ep %d class 0x%x sub 0x%x prot 0x%x\n", num_ep, class, sub_class, protocol);
+
+ // make sure we've cleared our corresponding endpoint search
+ found_acc_interface = false;
+ found_audio_interface = false;
+
+ // look for the accessory interface
+ if (num_ep == 2 &&
+ class == 0xff &&
+ sub_class == 0xff &&
+ (inendp <= 0 || outendp <= 0)) {
+
+ // this is probably our accessory interface
+ found_acc_interface = true;
+ } else if (class == 0x1 && // audio
+ sub_class == 0x2 && // streaming
+ num_ep > 0) { // alternate setting with actual endpoints
+
+ audiointerface = READ8(dev->devconfig, pos + OFFSET_FIELD_INTERFACE_NB);
+ audio_alternate_setting = READ8(dev->devconfig, pos + OFFSET_FIELD_ALT);
+
+ found_audio_interface = true;
+ }
+ break;
+ }
+ case DESCRIPTOR_ENDPOINT: {
+ uint8_t ep_type = READ8(dev->devconfig, pos + OFFSET_FIELD_EP_TYPE);
+ uint8_t endp = READ8(dev->devconfig, pos + OFFSET_FIELD_EP_ADDR);
+ size_t packetsize = READ16(dev->devconfig, pos + OFFSET_FIELD_EP_SIZE);
+
+ TRACE_OTG("\tENDPOINT: type 0x%x addr 0x%x\n", ep_type, endp);
+
+ if (found_acc_interface) {
+ if (ep_type != 2) // bulk
+ break;
+ if (endp & 0x80) {
+ // in
+ if (inendp <= 0) {
+ inendp = endp;
+ inpacketsize = packetsize;
+ }
+ } else {
+ // out
+ if (outendp <= 0) {
+ outendp = endp;
+ outpacketsize = packetsize;
+ }
+ }
+ }
+ if (found_audio_interface) {
+ if (ep_type != ((3 << 2) | (1 << 0))) // synchronous iso
+ break;
+
+ audiopacketsize = packetsize;
+ audioendp = endp;
+ }
+ break;
+ }
+ }
+
+ pos += length;
+ }
+
+ TRACE_OTG("inendp 0x%x (%d), outendp 0x%x (%d)\n", inendp, inpacketsize, outendp, outpacketsize);
+ outpipe = usbh_setup_endpoint(dev->address, outendp, ENDP_TYPE_BULK, outpacketsize);
+ TRACE_OTG("outpipe %d\n", outpipe);
+ inpipe = usbh_setup_endpoint(dev->address, inendp, ENDP_TYPE_BULK, inpacketsize);
+ TRACE_OTG("inpipe %d\n", inpipe);
+
+ if (audioendp > 0) {
+ TRACE_OTG("audio: interface %d alt setting %d endp 0x%x packet size %d\n",
+ audiointerface, audio_alternate_setting, audioendp, audiopacketsize);
+
+ audiopipe = usbh_setup_endpoint(dev->address, audioendp, ENDP_TYPE_ISO, audiopacketsize);
+ TRACE_OTG("audiopipe %d\n", audiopipe);
+
+ // enable audio
+ // set configuration 1
+ struct usb_setup_packet setup = (struct usb_setup_packet){
+ USB_SETUP_DIR_HOST_TO_DEVICE | USB_SETUP_RECIPIENT_INTERFACE,
+ SETUP_SET_INTERFACE,
+ audio_alternate_setting,
+ audiointerface,
+ 0
+ };
+
+ int len = usbh_send_setup(&setup, NULL, false);
+ TRACE_OTG("send_setup returns %d\n", len);
+
+ audsamplerate = 44100;
+ audsampleratebase = 44100;
+ audioOn(AUDIO_USB, audsamplerate);
+
+ // enable SMC so we can use its 4K memory buffer
+ pmc_enable_periph_clk(ID_SMC);
+
+ usbh_queue_iso_transfer(audiopipe, audrecvbuf, sizeof(audrecvbuf), &audio_iso_callback, NULL);
+ }
+
+ return 0;
+}
+
+void accessory_deinit(void)
+{
+ inpipe = -1;
+ outpipe = -1;
+ audiopipe = -1;
+}
+
+void accessory_work(void)
+{
+#if 0
+ static int last_samp = -1;
+
+ if (total_samp - last_samp >= 44100) {
+ last_samp = total_samp;
+ TRACE_OTG("samp %d\n", total_samp);
+ }
+#endif
+}
+
+/* bulk in/out */
+int accessory_send(const void *buf, size_t len)
+{
+ int res;
+
+ if (outpipe < 0)
+ return -1;
+ if (!usbh_accessory_connected())
+ return -1;
+
+// TRACE_OTG("buf %p, len %d... ", buf, len);
+
+ res = usbh_check_transfer(outpipe);
+ if (res != PIPE_RESULT_NOT_QUEUED) {
+// TRACE_OTG_NONL("pipe with bad result before transfer %d\n", res);
+ return -1;
+ }
+ usbh_queue_transfer(outpipe, buf, len);
+
+ res = -1;
+ int now = millis();
+ for (;;) {
+ coopYield();
+
+ res = usbh_check_transfer(outpipe);
+ if (res >= 0)
+ break;
+
+ if (res < 0 && res != PIPE_RESULT_NOT_READY) {
+// TRACE_OTG_NONL("error %d in transfer\n", res);
+ break;
+ }
+ if (millis() - now >= ACCESSORY_TIMEOUT) {
+// TRACE_OTG_NONL("timeout\n");
+ // XXX cancel transfer
+ break;
+ }
+ }
+
+// TRACE_OTG_NONL("res %d\n", res);
+ return res;
+}
+
+int accessory_receive(void *buf, size_t len)
+{
+ int res;
+
+ if (inpipe < 0)
+ return -1;
+
+ if (!usbh_accessory_connected())
+ return -1;
+
+// TRACE_OTG("buf %p, len %d... ", buf, len);
+
+ res = usbh_check_transfer(inpipe);
+ if (res != PIPE_RESULT_NOT_QUEUED) {
+// TRACE_OTG_NONL("pipe with bad result before transfer %d\n", res);
+ return -1;
+ }
+ usbh_queue_transfer(inpipe, buf, len);
+
+ res = -1;
+ int now = millis();
+ for (;;) {
+ coopYield();
+
+ res = usbh_check_transfer(inpipe);
+ if (res >= 0)
+ break;
+
+ if (res < 0 && res != PIPE_RESULT_NOT_READY) {
+// TRACE_OTG_NONL("error %d in transfer\n", res);
+ break;
+ }
+ if (millis() - now >= ACCESSORY_TIMEOUT) {
+// TRACE_OTG_NONL("timeout\n");
+ // XXX cancel transfer
+ break;
+ }
+ }
+
+// TRACE_OTG_NONL("res %d\n", res);
+ return res;
+}
+
+/* audio */
+static void skew_sample_rate(int skew)
+{
+ audsamplerate += skew;
+ if (audsamplerate - audsampleratebase > MAX_SAMPLE_SKEW)
+ audsamplerate = audsampleratebase + MAX_SAMPLE_SKEW;
+ if (audsampleratebase - audsamplerate > MAX_SAMPLE_SKEW)
+ audsamplerate = audsampleratebase - MAX_SAMPLE_SKEW;
+
+ audioSetSample(AUDIO_USB, audsamplerate);
+}
+
+static void audio_iso_callback(void *arg, int result, void *buf, size_t pos)
+{
+ if (pos == 0)
+ return;
+
+// TRACE_OTG("arg %p result %d buf %p pos %u\n", arg, result, buf, pos);
+
+ // set the next audio buffer
+ usbh_set_iso_buffer(audiopipe, audrecvbuf, sizeof(audrecvbuf));
+
+ // see if we can fit the processed one into the last buffer
+ if (AUDBUFSIZE - audbufpos < pos / 4) {
+ // we can't, kick this buffer and move onto the next
+ int res = audioTryAddBuffer(AUDIO_USB, audbuf + curraudbuf * AUDBUFSIZE, audbufpos);
+ if (!res) {
+ //dbgPrintf("%d\n", a);
+ //dbgPrintf("USB audio: Failed to queue audio buffer\n");
+ //dbgPrintf("over\n");
+ return;
+ }
+
+ static int lastres[2];
+ if (res > (AUDBUFSIZE / 2)) {
+ // we're overrunning the dac, increase its sample rate
+ static int a = 0;
+ if (lastres[1] < lastres[0] && lastres[0] < res) {
+ a++;
+ if (a > 5) {
+ int adj = (res / (AUDBUFSIZE / 20));
+ skew_sample_rate(adj);
+ //dbgPrintf("o%d +%d %d\n", res, adj, audsamplerate);
+ a = 0;
+ }
+ }
+ } else {
+ // we're underunning the dac, decrease its sample rate
+ static int a = 0;
+
+ if (res == 1 || lastres[1] > lastres[0] && lastres[0] > res) {
+ a++;
+ if (a > 5) {
+ int adj = ((AUDBUFSIZE - res) / (AUDBUFSIZE / 20));
+ skew_sample_rate(-adj);
+ //dbgPrintf("u%d -%d %d\n", res, adj, audsamplerate);
+ a = 0;
+ }
+ }
+ }
+ lastres[1] = lastres[0];
+ lastres[0] = res;
+
+ curraudbuf++;
+ if (curraudbuf >= AUDBUFCOUNT)
+ curraudbuf = 0;
+ audbufpos = 0;
+ }
+
+ // process the one we just got
+ size_t processed_samples = process_audio(audbuf + curraudbuf * AUDBUFSIZE + audbufpos, buf, pos);
+ audbufpos += processed_samples;
+
+ total_samp += processed_samples;
+}
+
+/* take 16 bit stereo signed samples and downconvert in place to mono 12 bit unsigned */
+size_t process_audio(uint16_t *outbuf, uint16_t *inbuf, size_t len)
+{
+ len /= 2; // number of words
+
+ // loop through the samples, combining left and right and decimating to 12 bits
+ size_t i;
+ for (i = 0; i < len/2; i++) {
+ int32_t temp = (int16_t)inbuf[i*2];
+ int32_t temp2 = (int16_t)inbuf[i*2 + 1];
+
+ temp = temp + temp2;
+
+ int32_t vol = getVolume();
+ temp *= vol;
+
+ temp = temp >> (5 + 8);
+ temp += 2048;
+ temp &= 0xfff; // XXX dither the sample
+ outbuf[i] = temp;
+ }
+
+ return i;
+}
+
+
diff --git a/library/ADK2/als.c b/library/ADK2/als.c
new file mode 100644
index 0000000..0fa6555
--- /dev/null
+++ b/library/ADK2/als.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "als.h"
+#include "I2C.h"
+
+
+
+char alsInit(void){ //1->success, 0->fail
+
+ if(i2cScan(1, 0x44) == I2C_ERR_NAK) return 0; //not found
+
+ i2cSingleWrite(1, 0x44, 0x00, 0x00); // Probably unnecessary
+ i2cSingleWrite(1, 0x44, 0x01, (0x4) << 4); // Turn on all the features, but no interrupts
+ i2cSingleWrite(1, 0x44, 0x02, 0x40); // Turn on IR comp, max gain settings
+
+ i2cSingleWrite(1, 0x44, 0x03, (0x0B) << 4); // Set it to 110mA LED current.
+
+ return 1;
+}
+
+void alsRead(uint16_t* prox, uint16_t* clear, uint16_t* R, uint16_t* G, uint16_t* B, uint16_t* IR, uint16_t* temp){
+
+ if(prox) *prox = ((uint16_t)i2cSingleRead(1, 0x44, 0x10) << 8) | (uint16_t)i2cSingleRead(1, 0x44, 0x11);
+ if(clear) *clear = ((uint16_t)i2cSingleRead(1, 0x44, 0x4) << 8) | (uint16_t)i2cSingleRead(1, 0x44, 0x5);
+ if(R) *R = ((uint16_t)i2cSingleRead(1, 0x44, 0x6) << 8) | (uint16_t)i2cSingleRead(1, 0x44, 0x7);
+ if(G) *G = ((uint16_t)i2cSingleRead(1, 0x44, 0x8) << 8) | (uint16_t)i2cSingleRead(1, 0x44, 0x9);
+ if(B) *B = ((uint16_t)i2cSingleRead(1, 0x44, 0xA) << 8) | (uint16_t)i2cSingleRead(1, 0x44, 0xB);
+ if(IR) *IR = ((uint16_t)i2cSingleRead(1, 0x44, 0xC) << 8) | (uint16_t)i2cSingleRead(1, 0x44, 0xD);
+ if(temp) *temp = ((uint16_t)i2cSingleRead(1, 0x44, 0x12) << 8) | (uint16_t)i2cSingleRead(1, 0x44, 0x13);
+}
diff --git a/library/ADK2/als.h b/library/ADK2/als.h
new file mode 100644
index 0000000..f7daeb3
--- /dev/null
+++ b/library/ADK2/als.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _ALS_H_
+#define _ALS_H_
+
+
+char alsInit(void); //1->success, 0->fail
+void alsRead(uint16_t* prox, uint16_t* clear, uint16_t* R, uint16_t* G, uint16_t* B, uint16_t* IR, uint16_t* temp);
+
+
+#endif
+#endif
+
diff --git a/library/ADK2/baro.c b/library/ADK2/baro.c
new file mode 100644
index 0000000..b61cbb6
--- /dev/null
+++ b/library/ADK2/baro.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "baro.h"
+#include "I2C.h"
+
+static struct {
+ int16_t AC1;
+ int16_t AC2;
+ int16_t AC3;
+ uint16_t AC4;
+ uint16_t AC5;
+ uint16_t AC6;
+ int16_t B1;
+ int16_t B2;
+ int16_t MB;
+ int16_t MC;
+ int16_t MD;
+} baro;
+
+
+
+#define BARO_REG_CTRL 0xF4
+#define BARO_REG_OUT_MSB 0xF6
+#define BARO_REG_OUT_LSB 0xF7
+#define BARO_REG_OUT_XLSB 0xF8
+#define BARO_SCO 0x20
+
+
+
+char baroInit(void){ //0 on failure
+
+ if(i2cSingleRead(1, 0x77, 0xD0) != 0x55) return 0; //not found
+
+ baro.AC1 = (i2cSingleRead(1, 0x77, 0xAA) << 8) | i2cSingleRead(1, 0x77, 0xAB);
+ baro.AC2 = (i2cSingleRead(1, 0x77, 0xAC) << 8) | i2cSingleRead(1, 0x77, 0xAD);
+ baro.AC3 = (i2cSingleRead(1, 0x77, 0xAE) << 8) | i2cSingleRead(1, 0x77, 0xAF);
+ baro.AC4 = (i2cSingleRead(1, 0x77, 0xB0) << 8) | i2cSingleRead(1, 0x77, 0xA1);
+ baro.AC5 = (i2cSingleRead(1, 0x77, 0xB2) << 8) | i2cSingleRead(1, 0x77, 0xA3);
+ baro.AC6 = (i2cSingleRead(1, 0x77, 0xB4) << 8) | i2cSingleRead(1, 0x77, 0xA5);
+ baro.B1 = (i2cSingleRead(1, 0x77, 0xB6) << 8) | i2cSingleRead(1, 0x77, 0xA7);
+ baro.B2 = (i2cSingleRead(1, 0x77, 0xB8) << 8) | i2cSingleRead(1, 0x77, 0xA9);
+ baro.MB = (i2cSingleRead(1, 0x77, 0xBA) << 8) | i2cSingleRead(1, 0x77, 0xBB);
+ baro.MC = (i2cSingleRead(1, 0x77, 0xBC) << 8) | i2cSingleRead(1, 0x77, 0xBD);
+ baro.MD = (i2cSingleRead(1, 0x77, 0xBE) << 8) | i2cSingleRead(1, 0x77, 0xBF);
+
+ return 1;
+}
+
+void baroRead(uint8_t oss, long* kPa, long* decicelsius){
+
+ long ut, up, x1, x2, x3, b3, b4, b5, b6, p, t;
+ unsigned long b7;
+
+ // Read uncompensated temp
+ oss = oss & 0x03; // Mask off to protect bits
+ i2cSingleWrite(1, 0x77, BARO_REG_CTRL, 0x2E);
+ while(i2cSingleRead(1, 0x77, BARO_REG_CTRL) & BARO_SCO) {}
+ ut = (i2cSingleRead(1, 0x77, BARO_REG_OUT_MSB) << 8) | i2cSingleRead(1, 0x77, BARO_REG_OUT_LSB);
+
+ // Read uncompensated pressure
+ i2cSingleWrite(1, 0x77, BARO_REG_CTRL, 0x34 | (oss << 6));
+ while(i2cSingleRead(1, 0x77, BARO_REG_CTRL) & BARO_SCO) {}
+ up = ((i2cSingleRead(1, 0x77, BARO_REG_OUT_MSB) << 16) | (i2cSingleRead(1, 0x77, BARO_REG_OUT_LSB) << 8)
+ | i2cSingleRead(1, 0x77, BARO_REG_OUT_XLSB)) >> (8 - oss);
+
+ // Calculate true temperature (in 0.1 degrees C)
+ x1 = ((ut - baro.AC6) * baro.AC5) >> 15;
+ x2 = (baro.MC << 11) / (x1 + baro.MD);
+ b5 = x1 + x2;
+ t = (b5 + 8) >> 4;
+ if(decicelsius) *decicelsius = t;
+
+ // Calculate true pressure
+ b6 = b5 - 4000;
+ x1 = (baro.B2 * ((b6 * b6) >> 12)) >> 11;
+ x2 = (baro.AC2 * b6) >> 11;
+ x3 = x1 + x2;
+ b3 = (((baro.AC1 * 4 + x3) << oss) + 2) / 4;
+
+
+ x1 = (baro.AC3 * b6) >> 13;
+ x2 = (baro.B1 * ((b6 * b6) >> 12)) >> 16;
+ x3 = ((x1 + x2) + 2) >> 2;
+ b4 = (baro.AC4 * (unsigned long)(x3 + 32768)) >> 15;
+ b7 = ((unsigned long)up - b3) * (50000 >> oss);
+ if (b7 < 0x80000000) {
+ p = (b7 * 2) / b4;
+ } else {
+ p = (b7 / b4) * 2;
+ }
+ x1 = ((p >> 3) * (p >> 3)) >> 10; // Split because they seem to be using floating point in the datasheet example
+ x1 = (x1 * 3038) >> 16;
+ x2 = (-7357 * p) >> 16;
+ p = p + ((x1 + x2 + 3791) >> 4);
+
+ if(kPa) *kPa = p;
+}
+
diff --git a/library/ADK2/baro.h b/library/ADK2/baro.h
new file mode 100644
index 0000000..bbfb5e0
--- /dev/null
+++ b/library/ADK2/baro.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _BARO_H_
+#define _BARO_H_
+
+
+//oversample coefficients (higher for more accuracy, lower for more speed)
+#define BARO_OSS_1X 0x00
+#define BARO_OSS_2X 0x01
+#define BARO_OSS_4X 0x02
+#define BARO_OSS_8X 0x03
+
+char baroInit(void); //0 on failure
+void baroRead(uint8_t oss, long* kPa, long* decicelsius);
+
+
+#endif
+#endif
+
diff --git a/library/ADK2/btA2DP.c b/library/ADK2/btA2DP.c
new file mode 100644
index 0000000..e35a6d3
--- /dev/null
+++ b/library/ADK2/btA2DP.c
@@ -0,0 +1,1502 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "btRFCOMM.h"
+#include "btA2DP.h"
+#include "btSDP.h"
+#include "btL2CAP.h"
+#include "dbg.h"
+#include "Audio.h"
+#include <string.h>
+#include "coop.h"
+
+
+#define UGLY_SCARY_DEBUGGING_CODE 0
+
+//endpoint media types
+ #define AVDTP_MEDIA_TYP_AUDIO 0
+ #define AVDTP_MEDIA_TYP_VIDEO 1
+ #define AVDTP_MEDIA_TYP_MULTIMEDIA 2
+
+//andpoint directions
+ #define AVDTP_DIR_SOURCE 0
+ #define AVDTP_DIR_SINK 1
+
+
+//A2DP packet header (2bytes)
+ //byte 0
+ #define AVDTP_HDR_MASK_TRANS 0xF0
+ #define AVDTP_HDR_SHIFT_TRANS 4
+ #define AVDTP_HDR_MASK_PKT_TYP 0x0C
+ #define AVDTP_HDR_SHIFT_PKT_TYP 2
+ #define AVDTP_HDR_MASK_MSG_TYP 0x03
+ #define AVDTP_HDR_SHIFT_MSG_TYP 0
+ //byte 1
+ #define AVDTP_HDR_MASK_SIG_ID 0x3F
+ #define AVDTP_HDR_SHIFT_SIG_ID 0
+
+//sigId
+ #define AVDTP_SIG_DISCOVER 0x01
+ #define AVDTP_SIG_GET_CAPABILITIES 0x02
+ #define AVDTP_SIG_SET_CONFIGURATION 0x03
+ #define AVDTP_SIG_GET_CONFIGURATION 0x04
+ #define AVDTP_SIG_RECONFIGURE 0x05
+ #define AVDTP_SIG_OPEN 0x06
+ #define AVDTP_SIG_START 0x07
+ #define AVDTP_SIG_CLOSE 0x08
+ #define AVDTP_SIG_SUSPEND 0x09
+ #define AVDTP_SIG_ABORT 0x0A
+ #define AVDTP_SIG_SECURITY_CONTROL 0x0B
+
+//pktTyp
+ #define AVDTP_PKT_TYP_SINGLE 0x00
+ #define AVDTP_PKT_TYP_START 0x01
+ #define AVDTP_PKT_TYP_CONTINUE 0x02
+ #define AVDTP_PKT_TYP_END 0x03
+
+//msgTyp
+ #define AVDTP_MSG_TYP_CMD 0x00
+ #define AVDTP_MSG_TYP_ACCEPT 0x02
+ #define AVDTP_MSG_TYP_REJ 0x03
+
+//seid info (2 bytes)
+ //byte0
+ #define AVDTP_SEID_NFO_MASK_SEID 0xFC
+ #define AVDTP_SEID_NFO_SHIFT_SEID 2
+ #define AVDTP_SEID_NFO_MASK_INUSE 0x02
+ #define AVDTP_SEID_NFO_SHIFT_INUSE 1
+ //byte1
+ #define AVDTP_SEID_NFO_MASK_MEDIA_TYP 0xF0
+ #define AVDTP_SEID_NFO_SHIFT_MEDIA_TYP 4
+ #define AVDTP_SEID_NFO_MASK_TYP 0x08
+ #define AVDTP_SEID_NFO_SHIFT_TYP 3
+
+
+//service capability categoris
+ #define AVDTP_SVC_CAT_MEDIA_TRANSPORT 1
+ #define AVDTP_SVC_CAT_REPORTING 2
+ #define AVDTP_SVC_CAT_RECOVERY 3
+ #define AVDTP_SVC_CAT_CONTENT_PROTECTION 4
+ #define AVDTP_SVC_CAT_HEADER_COMPRESSION 5
+ #define AVDTP_SVC_CAT_MULTIPLEXING 6
+ #define AVDTP_SVC_CAT_MEDIA_CODEC 7
+
+//codec types
+ #define A2DP_CODEC_TYP_SBC 0
+ //others exist...done don't implement them
+
+#define MY_ENDPT_ID 1 //we support just one, and this is it's ID
+
+#define A2DP_CHAN_MODE_MONO 0
+#define A2DP_CHAN_MODE_DUAL_CHANNEL 1
+#define A2DP_CHAN_MODE_STEREO 2
+#define A2DP_CHAN_MODE_JOINT_STEREO 3
+
+
+#define DATA_STATE_ENCODE(state) ((void*)(((uint32_t)(state)) ^ 0x80000000))
+#define IS_DATA_STATE(state) (!!(((uint32_t)(state)) & 0x80000000))
+
+typedef struct A2DPstate{
+
+ //L2CAP data
+ uint16_t aclConn;
+ uint16_t remChan; //remote channel num for control channel
+ uint16_t datChan; //remote channel num for data channel
+
+ //codec data
+ uint16_t samplingRate;
+
+ //our state
+ char needAudioConn;
+
+ //link
+ struct A2DPstate* next;
+
+}A2DPstate;
+
+static A2DPstate* conns = NULL;
+
+//copyright notice for SBC decoder
+/*
+Copyright (c) 2011, Dmitry Grinberg (as published on http://dmitrygr.com)
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following condition is met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+
+#define QUALITY_LOWEST 1 //you may notice the quality reduction
+#define QUALITY_MEDIUM 2 //pretty good
+#define QUALITY_GREAT 3 //as good as it will get without an FPU
+
+
+///config options begin
+
+/*
+ This is a rather clever little SBC decoder that I've put together
+
+*/
+
+#define QUALITY QUALITY_MEDIUM
+#define SPEED_OVER_ACCURACY //set to cheat a bit with shifts (saves a divide per sample)
+#define ITER uint32_t //iterator up to 180 use fastest type for your platform
+
+///config options end
+
+
+#if QUALITY == QUALITY_LOWEST
+
+ #define CONST(x) (x >> 24)
+ #define SAMPLE_CVT(x) (x >> 8)
+ #define INSAMPLE int8_t
+ #define OUTSAMPLE uint8_t //no point producing 16-bit samples using the 8-bit decoder
+ #define FIXED int8_t
+ #define FIXED_S int16_t
+ #define OUT_CLIP_MAX 0x7F
+ #define OUT_CLIP_MIN -0x80
+
+ #define NUM_FRAC_BITS_PROTO 8
+ #define NUM_FRAC_BITS_COS 6
+
+#elif QUALITY == QUALITY_MEDIUM
+
+ #define CONST(x) (x >> 16)
+ #define SAMPLE_CVT(x) (x)
+ #define INSAMPLE int16_t
+ #define OUTSAMPLE uint16_t
+ #define FIXED int16_t
+ #define FIXED_S int32_t
+ #define OUT_CLIP_MAX 0x7FFF
+ #define OUT_CLIP_MIN -0x8000
+
+ #define NUM_FRAC_BITS_PROTO 16
+ #define NUM_FRAC_BITS_COS 14
+
+#elif QUALITY == QUALITY_GREAT
+
+ #define CONST(x) (x)
+ #define SAMPLE_CVT(x) (x)
+ #define INSAMPLE int16_t
+ #define OUTSAMPLE uint16_t
+ #define FIXED int32_t
+ #define FIXED_S int64_t
+ #define OUT_CLIP_MAX 0x7FFF
+ #define OUT_CLIP_MIN -0x8000
+
+ #define NUM_FRAC_BITS_PROTO 32
+ #define NUM_FRAC_BITS_COS 30
+
+#else
+
+ #error "You did not define SBC decoder synthesizer quality to use"
+
+#endif
+
+
+
+static const FIXED proto_4_40[] =
+{
+ CONST(0x00000000), CONST(0x00FB7991), CONST(0x02CB3E8B), CONST(0x069FDC59),
+ CONST(0x22B63DA5), CONST(0x4B583FE6), CONST(0xDD49C25B), CONST(0x069FDC59),
+ CONST(0xFD34C175), CONST(0x00FB7991), CONST(0x002329CC), CONST(0x00FF11CA),
+ CONST(0x053B7546), CONST(0x0191E578), CONST(0x31EAB920), CONST(0x4825E4A3),
+ CONST(0xEC1F5E6D), CONST(0x083DDC80), CONST(0xFF3773A8), CONST(0x00B32807),
+ CONST(0x0061C5A7), CONST(0x007A4737), CONST(0x07646684), CONST(0xF89F23A7),
+ CONST(0x3F23948D), CONST(0x3F23948D), CONST(0xF89F23A7), CONST(0x07646684),
+ CONST(0x007A4737), CONST(0x0061C5A7), CONST(0x00B32807), CONST(0xFF3773A8),
+ CONST(0x083DDC80), CONST(0xEC1F5E6D), CONST(0x4825E4A3), CONST(0x31EAB920),
+ CONST(0x0191E578), CONST(0x053B7546), CONST(0x00FF11CA), CONST(0x002329CC)
+};
+
+static const FIXED proto_8_80[] =
+{
+ CONST(0x00000000), CONST(0x0083D8D4), CONST(0x0172E691), CONST(0x034FD9E0),
+ CONST(0x116860F5), CONST(0x259ED8EB), CONST(0xEE979F0B), CONST(0x034FD9E0),
+ CONST(0xFE8D196F), CONST(0x0083D8D4), CONST(0x000A42E6), CONST(0x0089DE90),
+ CONST(0x020E372C), CONST(0x02447D75), CONST(0x153E7D35), CONST(0x253844DE),
+ CONST(0xF2625120), CONST(0x03EBE849), CONST(0xFF1ACF26), CONST(0x0074E5CF),
+ CONST(0x00167EE3), CONST(0x0082B6EC), CONST(0x02AD6794), CONST(0x00BFA1FF),
+ CONST(0x18FAB36D), CONST(0x24086BF5), CONST(0xF5FF2BF8), CONST(0x04270CA8),
+ CONST(0xFF93E21B), CONST(0x0060C1E9), CONST(0x002458FC), CONST(0x0069F16C),
+ CONST(0x03436717), CONST(0xFEBDD6E5), CONST(0x1C7762DF), CONST(0x221D9DE0),
+ CONST(0xF950DCFC), CONST(0x0412523E), CONST(0xFFF44825), CONST(0x004AB4C5),
+ CONST(0x0035FF13), CONST(0x003B1FA4), CONST(0x03C04499), CONST(0xFC4086B8),
+ CONST(0x1F8E43F2), CONST(0x1F8E43F2), CONST(0xFC4086B8), CONST(0x03C04499),
+ CONST(0x003B1FA4), CONST(0x0035FF13), CONST(0x004AB4C5), CONST(0xFFF44825),
+ CONST(0x0412523E), CONST(0xF950DCFC), CONST(0x221D9DE0), CONST(0x1C7762DF),
+ CONST(0xFEBDD6E5), CONST(0x03436717), CONST(0x0069F16C), CONST(0x002458FC),
+ CONST(0x0060C1E9), CONST(0xFF93E21B), CONST(0x04270CA8), CONST(0xF5FF2BF8),
+ CONST(0x24086BF5), CONST(0x18FAB36D), CONST(0x00BFA1FF), CONST(0x02AD6794),
+ CONST(0x0082B6EC), CONST(0x00167EE3), CONST(0x0074E5CF), CONST(0xFF1ACF26),
+ CONST(0x03EBE849), CONST(0xF2625120), CONST(0x253844DE), CONST(0x153E7D35),
+ CONST(0x02447D75), CONST(0x020E372C), CONST(0x0089DE90), CONST(0x000A42E6)
+};
+
+static const FIXED costab_4[] =
+{
+ CONST(0x2D413CCD), CONST(0xD2BEC333), CONST(0xD2BEC333), CONST(0x2D413CCD),
+ CONST(0x187DE2A7), CONST(0xC4DF2862), CONST(0x3B20D79E), CONST(0xE7821D59),
+ CONST(0x00000000), CONST(0x00000000), CONST(0x00000000), CONST(0x00000000),
+ CONST(0xE7821D59), CONST(0x3B20D79E), CONST(0xC4DF2862), CONST(0x187DE2A7),
+ CONST(0xD2BEC333), CONST(0x2D413CCD), CONST(0x2D413CCD), CONST(0xD2BEC333),
+ CONST(0xC4DF2862), CONST(0xE7821D59), CONST(0x187DE2A7), CONST(0x3B20D79E),
+ CONST(0xC0000000), CONST(0xC0000000), CONST(0xC0000000), CONST(0xC0000000),
+ CONST(0xC4DF2862), CONST(0xE7821D59), CONST(0x187DE2A7), CONST(0x3B20D79E)
+};
+
+static const FIXED costab_8[] =
+{
+ CONST(0x2D413CCD), CONST(0xD2BEC333), CONST(0xD2BEC333), CONST(0x2D413CCD),
+ CONST(0x2D413CCD), CONST(0xD2BEC333), CONST(0xD2BEC333), CONST(0x2D413CCD),
+ CONST(0x238E7673), CONST(0xC13AD060), CONST(0x0C7C5C1E), CONST(0x3536CC52),
+ CONST(0xCAC933AE), CONST(0xF383A3E2), CONST(0x3EC52FA0), CONST(0xDC71898D),
+ CONST(0x187DE2A7), CONST(0xC4DF2862), CONST(0x3B20D79E), CONST(0xE7821D59),
+ CONST(0xE7821D59), CONST(0x3B20D79E), CONST(0xC4DF2862), CONST(0x187DE2A7),
+ CONST(0x0C7C5C1E), CONST(0xDC71898D), CONST(0x3536CC52), CONST(0xC13AD060),
+ CONST(0x3EC52FA0), CONST(0xCAC933AE), CONST(0x238E7673), CONST(0xF383A3E2),
+ CONST(0x00000000), CONST(0x00000000), CONST(0x00000000), CONST(0x00000000),
+ CONST(0x00000000), CONST(0x00000000), CONST(0x00000000), CONST(0x00000000),
+ CONST(0xF383A3E2), CONST(0x238E7673), CONST(0xCAC933AE), CONST(0x3EC52FA0),
+ CONST(0xC13AD060), CONST(0x3536CC52), CONST(0xDC71898D), CONST(0x0C7C5C1E),
+ CONST(0xE7821D59), CONST(0x3B20D79E), CONST(0xC4DF2862), CONST(0x187DE2A7),
+ CONST(0x187DE2A7), CONST(0xC4DF2862), CONST(0x3B20D79E), CONST(0xE7821D59),
+ CONST(0xDC71898D), CONST(0x3EC52FA0), CONST(0xF383A3E2), CONST(0xCAC933AE),
+ CONST(0x3536CC52), CONST(0x0C7C5C1E), CONST(0xC13AD060), CONST(0x238E7673),
+ CONST(0xD2BEC333), CONST(0x2D413CCD), CONST(0x2D413CCD), CONST(0xD2BEC333),
+ CONST(0xD2BEC333), CONST(0x2D413CCD), CONST(0x2D413CCD), CONST(0xD2BEC333),
+ CONST(0xCAC933AE), CONST(0x0C7C5C1E), CONST(0x3EC52FA0), CONST(0x238E7673),
+ CONST(0xDC71898D), CONST(0xC13AD060), CONST(0xF383A3E2), CONST(0x3536CC52),
+ CONST(0xC4DF2862), CONST(0xE7821D59), CONST(0x187DE2A7), CONST(0x3B20D79E),
+ CONST(0x3B20D79E), CONST(0x187DE2A7), CONST(0xE7821D59), CONST(0xC4DF2862),
+ CONST(0xC13AD060), CONST(0xCAC933AE), CONST(0xDC71898D), CONST(0xF383A3E2),
+ CONST(0x0C7C5C1E), CONST(0x238E7673), CONST(0x3536CC52), CONST(0x3EC52FA0),
+ CONST(0xC0000000), CONST(0xC0000000), CONST(0xC0000000), CONST(0xC0000000),
+ CONST(0xC0000000), CONST(0xC0000000), CONST(0xC0000000), CONST(0xC0000000),
+ CONST(0xC13AD060), CONST(0xCAC933AE), CONST(0xDC71898D), CONST(0xF383A3E2),
+ CONST(0x0C7C5C1E), CONST(0x238E7673), CONST(0x3536CC52), CONST(0x3EC52FA0),
+ CONST(0xC4DF2862), CONST(0xE7821D59), CONST(0x187DE2A7), CONST(0x3B20D79E),
+ CONST(0x3B20D79E), CONST(0x187DE2A7), CONST(0xE7821D59), CONST(0xC4DF2862),
+ CONST(0xCAC933AE), CONST(0x0C7C5C1E), CONST(0x3EC52FA0), CONST(0x238E7673),
+ CONST(0xDC71898D), CONST(0xC13AD060), CONST(0xF383A3E2), CONST(0x3536CC52)
+};
+
+static const int8_t loudness_4[4][4] =
+{
+ { -1, 0, 0, 0 }, { -2, 0, 0, 1 },
+ { -2, 0, 0, 1 }, { -2, 0, 0, 1 }
+};
+
+static const int8_t loudness_8[4][8] =
+{
+ { -2, 0, 0, 0, 0, 0, 0, 1 }, { -3, 0, 0, 0, 0, 0, 1, 2 },
+ { -4, 0, 0, 0, 0, 0, 1, 2 }, { -4, 0, 0, 0, 0, 0, 1, 2 }
+};
+
+
+#if QUALITY != QUALITY_MEDIUM //for medium we provide nice assembly routines
+
+ static void synth_4(OUTSAMPLE* dst, const INSAMPLE* src, FIXED* V){ //A2DP figure 12.3
+
+ ITER i, j;
+ const FIXED* tabl = proto_4_40;
+ const FIXED* costab = costab_4;
+
+ //shift
+ for(i = 79; i >= 8; i--) V[i] = V[i - 8];
+
+ //matrix
+ for(i = 0; i < 8; i++){
+
+ FIXED_S t = (FIXED_S)costab[0] * (FIXED_S)src[0] +
+ (FIXED_S)costab[1] * (FIXED_S)src[1] +
+ (FIXED_S)costab[2] * (FIXED_S)src[2] +
+ (FIXED_S)costab[3] * (FIXED_S)src[3];
+ costab += 4;
+ V[i] = t >> NUM_FRAC_BITS_COS;
+ }
+
+ //calculate audio samples
+ for(j = 0; j < 4; j++){
+
+ OUTSAMPLE s;
+ FIXED_S sample = (FIXED_S)V[j + 0] * (FIXED_S)tabl[0] +
+ (FIXED_S)V[j + 12] * (FIXED_S)tabl[1] +
+ (FIXED_S)V[j + 16] * (FIXED_S)tabl[2] +
+ (FIXED_S)V[j + 28] * (FIXED_S)tabl[3] +
+ (FIXED_S)V[j + 32] * (FIXED_S)tabl[4] +
+ (FIXED_S)V[j + 44] * (FIXED_S)tabl[5] +
+ (FIXED_S)V[j + 48] * (FIXED_S)tabl[6] +
+ (FIXED_S)V[j + 60] * (FIXED_S)tabl[7] +
+ (FIXED_S)V[j + 64] * (FIXED_S)tabl[8] +
+ (FIXED_S)V[j + 76] * (FIXED_S)tabl[9];
+ tabl += 10;
+
+ sample >>= (NUM_FRAC_BITS_PROTO - 1 - 2); //-2 is for the -4 we need to multiply by :)
+ sample = -sample;
+
+ if(sample > OUT_CLIP_MAX) sample = OUT_CLIP_MAX;
+ else if(sample < OUT_CLIP_MIN) sample = OUT_CLIP_MIN;
+ s = sample;
+
+ #ifndef DESKTOP
+ s += 0x8000;
+ s += 8;
+ s >>= 4;
+ #endif
+
+ dst[j] = s;
+ }
+ }
+
+ static void synth_8(OUTSAMPLE* dst, const INSAMPLE* src, FIXED* V){ //A2DP figure 12.3
+
+ ITER i, j;
+ const FIXED* tabl = proto_8_80;
+ const FIXED* costab = costab_8;
+
+ //shift
+ for(i = 159; i >= 16; i--) V[i] = V[i - 16];
+
+ //matrix
+ for(i = 0; i < 16; i++){
+
+ FIXED_S t = (FIXED_S)costab[0] * (FIXED_S)src[0] +
+ (FIXED_S)costab[1] * (FIXED_S)src[1] +
+ (FIXED_S)costab[2] * (FIXED_S)src[2] +
+ (FIXED_S)costab[3] * (FIXED_S)src[3] +
+ (FIXED_S)costab[4] * (FIXED_S)src[4] +
+ (FIXED_S)costab[5] * (FIXED_S)src[5] +
+ (FIXED_S)costab[6] * (FIXED_S)src[6] +
+ (FIXED_S)costab[7] * (FIXED_S)src[7];
+ costab += 8;
+ V[i] = t >> NUM_FRAC_BITS_COS;
+ }
+
+ //calculate audio samples
+ for(j = 0; j < 8; j++){
+
+ OUTSAMPLE s;
+ FIXED_S sample = (FIXED_S)V[j + 0] * (FIXED_S)tabl[0] +
+ (FIXED_S)V[j + 24] * (FIXED_S)tabl[1] +
+ (FIXED_S)V[j + 32] * (FIXED_S)tabl[2] +
+ (FIXED_S)V[j + 56] * (FIXED_S)tabl[3] +
+ (FIXED_S)V[j + 64] * (FIXED_S)tabl[4] +
+ (FIXED_S)V[j + 88] * (FIXED_S)tabl[5] +
+ (FIXED_S)V[j + 96] * (FIXED_S)tabl[6] +
+ (FIXED_S)V[j +120] * (FIXED_S)tabl[7] +
+ (FIXED_S)V[j +128] * (FIXED_S)tabl[8] +
+ (FIXED_S)V[j +152] * (FIXED_S)tabl[9];
+ tabl += 10;
+
+ sample >>= (NUM_FRAC_BITS_PROTO - 1 - 3); //-3 is for the -8 we need to multiply by :)
+ sample = -sample;
+
+ if(sample > OUT_CLIP_MAX) sample = OUT_CLIP_MAX;
+ else if(sample < OUT_CLIP_MIN) sample = OUT_CLIP_MIN;
+ s = sample;
+
+ #ifndef DESKTOP
+ s += 0x8000;
+ s += 8;
+ s >>= 4;
+ #endif
+
+ dst[j] = s;
+ }
+ }
+
+ static void synth(OUTSAMPLE* dst, const INSAMPLE* src, uint8_t nBands, FIXED* V){ //A2DP sigure 12.3
+
+ //efficient SBC synth by Dmitry Grinberg (as published May 26, 2012)
+ if(nBands == 4) synth_4(dst, src, V);
+ else synth_8(dst, src, V);
+ }
+
+#else
+
+ static void __attribute__((naked)) synth_4_med(OUTSAMPLE* dst, const INSAMPLE* src, FIXED* V, const FIXED* costabl, const FIXED* prot_Tabl){
+
+ asm(
+
+ //prologue {8 cycles}
+ "push {r4-r7} \n\t"
+
+ //shifting { 9x(9+9 + 1) + 1 = 171 cycles }
+ "add r2, #128 \n\t"
+ "ldmia r2!, {r4-r7} \n\t"
+ "stmia r2, {r4-r7} \n\t"
+ "subs r2, #32 \n\t"
+ "ldmia r2!, {r4-r7} \n\t"
+ "stmia r2, {r4-r7} \n\t"
+ "subs r2, #32 \n\t"
+ "ldmia r2!, {r4-r7} \n\t"
+ "stmia r2, {r4-r7} \n\t"
+ "subs r2, #32 \n\t"
+ "ldmia r2!, {r4-r7} \n\t"
+ "stmia r2, {r4-r7} \n\t"
+ "subs r2, #32 \n\t"
+ "ldmia r2!, {r4-r7} \n\t"
+ "stmia r2, {r4-r7} \n\t"
+ "subs r2, #32 \n\t"
+ "ldmia r2!, {r4-r7} \n\t"
+ "stmia r2, {r4-r7} \n\t"
+ "subs r2, #32 \n\t"
+ "ldmia r2!, {r4-r7} \n\t"
+ "stmia r2, {r4-r7} \n\t"
+ "subs r2, #32 \n\t"
+ "ldmia r2!, {r4-r7} \n\t"
+ "stmia r2, {r4-r7} \n\t"
+ "subs r2, #32 \n\t"
+ "ldmia r2!, {r4-r7} \n\t"
+ "stmia r2, {r4-r7} \n\t"
+ "subs r2, #16 \n\t" //r2 is right back where it started
+
+ //matrixing
+ "movs r7, #8 \n\t" //r7 is loop index
+ "matrix_loop_4: \n\t"
+ "ldrsh r4, [r3, #0] \n\t"
+ "ldrsh r5, [r1, #0] \n\t"
+ "mul r6, r4, r5 \n\t"
+ "ldrsh r4, [r3, #2] \n\t"
+ "ldrsh r5, [r1, #2] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #4] \n\t"
+ "ldrsh r5, [r1, #4] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #6] \n\t"
+ "ldrsh r5, [r1, #6] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "adds r3, #8 \n\t"
+ "asrs r6, #14 \n\t"
+ "strh r6, [r2], #2 \n\t"
+ "subs r7, #1 \n\t"
+ "bne matrix_loop_4 \n\t"
+ //return r2 to point where it should
+ "subs r2, #16 \n\t"
+
+ //sample production
+ "movs r7, #4 \n\t" //r7 is loop index
+ "ldr r3, [sp, #16] \n\t" //r3 is now proto table
+ "sample_loop_4: \n\t"
+ "ldrsh r4, [r3, #0] \n\t"
+ "ldrsh r5, [r2, #0] \n\t"
+ "mul r6, r4, r5 \n\t"
+ "ldrsh r4, [r3, #2] \n\t"
+ "ldrsh r5, [r2, #24] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #4] \n\t"
+ "ldrsh r5, [r2, #32] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #6] \n\t"
+ "ldrsh r5, [r2, #56] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #8] \n\t"
+ "ldrsh r5, [r2, #64] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #10] \n\t"
+ "ldrsh r5, [r2, #88] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #12] \n\t"
+ "ldrsh r5, [r2, #96] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #14] \n\t"
+ "ldrsh r5, [r2, #120] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #16] \n\t"
+ "ldrsh r5, [r2, #128] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #18] \n\t"
+ "ldrsh r5, [r2, #152] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "adds r3, #20 \n\t"
+ "adds r2, #2 \n\t"
+ "negs r6, r6 \n\t"
+ "ssat r6, #12, r6, asr #16 \n\t"
+ "add r6, #0x0800 \n\t"
+ "strh r6, [r0], #2 \n\t"
+ "subs r7, #1 \n\t"
+ "bne sample_loop_4 \n\t"
+
+ //cleanup
+ "pop {r4-r7} \n\t"
+ "bx lr \n\t"
+ );
+ }
+
+ static void __attribute__((naked)) synth_8_med(OUTSAMPLE* dst, const INSAMPLE* src, FIXED* V, const FIXED* costabl, const FIXED* prot_Tabl){
+
+ asm(
+
+ //prologue {8 cycles}
+ "push {r4-r10} \n\t"
+
+ //shifting { 9x(9+9 + 1) + 1 = 171 cycles }
+ "add r2, #256 \n\t"
+ "ldmia r2!, {r4-r10, r12} \n\t"
+ "stmia r2, {r4-r10, r12} \n\t"
+ "subs r2, #64 \n\t"
+ "ldmia r2!, {r4-r10, r12} \n\t"
+ "stmia r2, {r4-r10, r12} \n\t"
+ "subs r2, #64 \n\t"
+ "ldmia r2!, {r4-r10, r12} \n\t"
+ "stmia r2, {r4-r10, r12} \n\t"
+ "subs r2, #64 \n\t"
+ "ldmia r2!, {r4-r10, r12} \n\t"
+ "stmia r2, {r4-r10, r12} \n\t"
+ "subs r2, #64 \n\t"
+ "ldmia r2!, {r4-r10, r12} \n\t"
+ "stmia r2, {r4-r10, r12} \n\t"
+ "subs r2, #64 \n\t"
+ "ldmia r2!, {r4-r10, r12} \n\t"
+ "stmia r2, {r4-r10, r12} \n\t"
+ "subs r2, #64 \n\t"
+ "ldmia r2!, {r4-r10, r12} \n\t"
+ "stmia r2, {r4-r10, r12} \n\t"
+ "subs r2, #64 \n\t"
+ "ldmia r2!, {r4-r10, r12} \n\t"
+ "stmia r2, {r4-r10, r12} \n\t"
+ "subs r2, #64 \n\t"
+ "ldmia r2!, {r4-r10, r12} \n\t"
+ "stmia r2, {r4-r10, r12} \n\t"
+ "subs r2, #32 \n\t" //r2 is right back where it started
+
+ //matrixing
+ "movs r7, #16 \n\t" //r7 is loop index
+ "matrix_loop: \n\t"
+ "ldrsh r4, [r3, #0] \n\t"
+ "ldrsh r5, [r1, #0] \n\t"
+ "mul r6, r4, r5 \n\t"
+ "ldrsh r4, [r3, #2] \n\t"
+ "ldrsh r5, [r1, #2] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #4] \n\t"
+ "ldrsh r5, [r1, #4] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #6] \n\t"
+ "ldrsh r5, [r1, #6] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #8] \n\t"
+ "ldrsh r5, [r1, #8] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #10] \n\t"
+ "ldrsh r5, [r1, #10] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #12] \n\t"
+ "ldrsh r5, [r1, #12] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #14] \n\t"
+ "ldrsh r5, [r1, #14] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "adds r3, #16 \n\t"
+ "asrs r6, #14 \n\t"
+ "strh r6, [r2], #2 \n\t"
+ "subs r7, #1 \n\t"
+ "bne matrix_loop \n\t"
+ //return r2 to point where it should
+ "subs r2, #32 \n\t"
+
+ //sample production
+ "movs r7, #8 \n\t" //r7 is loop index
+ "ldr r3, [sp, #28] \n\t" //r3 is now proto table
+ "sample_loop: \n\t"
+ "ldrsh r4, [r3, #0] \n\t"
+ "ldrsh r5, [r2, #0] \n\t"
+ "mul r6, r4, r5 \n\t"
+ "ldrsh r4, [r3, #2] \n\t"
+ "ldrsh r5, [r2, #48] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #4] \n\t"
+ "ldrsh r5, [r2, #64] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #6] \n\t"
+ "ldrsh r5, [r2, #112] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #8] \n\t"
+ "ldrsh r5, [r2, #128] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #10] \n\t"
+ "ldrsh r5, [r2, #176] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #12] \n\t"
+ "ldrsh r5, [r2, #192] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #14] \n\t"
+ "ldrsh r5, [r2, #240] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #16] \n\t"
+ "ldrsh r5, [r2, #256] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "ldrsh r4, [r3, #18] \n\t"
+ "ldrsh r5, [r2, #304] \n\t"
+ "mla r6, r4, r5, r6 \n\t"
+ "adds r3, #20 \n\t"
+ "adds r2, #2 \n\t"
+ "negs r6, r6 \n\t"
+ "ssat r6, #12, r6, asr #16 \n\t"
+ "add r6, #0x0800 \n\t"
+ "strh r6, [r0], #2 \n\t"
+ "subs r7, #1 \n\t"
+ "bne sample_loop \n\t"
+
+ //cleanup
+ "pop {r4-r10} \n\t"
+ "bx lr \n\t"
+ );
+ }
+
+ static void synth(OUTSAMPLE* dst, const INSAMPLE* src, uint8_t nBands, FIXED* V){ //A2DP sigure 12.3
+
+ //efficient SBC synth by Dmitry Grinberg (as published May 26, 2012)
+ if(nBands == 4) synth_4_med(dst, src, V, costab_4, proto_4_40);
+ else synth_8_med(dst, src, V, costab_8, proto_8_80);
+ }
+
+#endif
+
+static void a2dpSbcPlay(const uint8_t* buf, uint16_t len){ //only supports mono (for simplicity)
+
+ //volume
+ int32_t vol = (uint32_t)getVolume();
+
+ //convenience
+ const uint8_t* end = buf + len;
+ #define left (end - buf)
+
+ //workspace
+ ITER i, j, k, ch, numChan;
+ uint8_t scaleFactors[2][8];
+ int8_t bitneed[2][8];
+ uint8_t bits[2][8], join = 0;
+ INSAMPLE samples[16][2][8];
+
+ //audio data
+ #define bufNumBuffers 3 //if less than 3, we're being suboptimal in speed.
+ #define bufNumSamples 1536 //FYI: 128 samples is the maximum number of samples a single packet may have. MUST be a multiple of 8!
+ static OUTSAMPLE audio[bufNumBuffers][bufNumSamples];
+ static uint8_t whichBuf = 0;
+ static uint16_t bufSamples = 0;
+
+ //process the packet header
+ if(left < 12) return; //too short of a packet header
+ uint8_t ver = (*buf) >> 6;
+ char pad = ((*buf) >> 5) & 1;
+ char ext = ((*buf) >> 4) & 1;
+ uint8_t cc = (*buf++) & 0x0F;
+ char mark = (*buf) >> 7;
+ uint8_t pt = (*buf++) & 0x7F;
+ uint16_t seq = (((uint16_t)buf[0]) << 8) | buf[1];
+ uint32_t time = (((uint32_t)buf[2]) << 24) | (((uint32_t)buf[3]) << 16) | (((uint32_t)buf[4]) << 8) | buf[5];
+ uint32_t src = (((uint32_t)buf[6]) << 24) | (((uint32_t)buf[7]) << 16) | (((uint32_t)buf[8]) << 8) | buf[9];
+ buf += 10;
+
+ //process the count
+ if(left < 1) return; //too short of a count
+ uint8_t numFrames = *buf++;
+
+ //process packets
+ while(numFrames--){
+
+ //process frame header
+ if(left < 4) break; //too short a frame header
+ uint8_t sync = *buf++;
+ uint8_t samplingRate = (*buf) >> 6; //see A2DP table 12.16
+ uint8_t blocks = ((*buf) >> 4) & 3; //see A2DP table 12.17
+ uint8_t chanMode = ((*buf) >> 2) & 3; //see A2DP table 12.18
+ uint8_t snr = ((*buf) >> 1) & 1; //see A2DP table 12.19
+ uint8_t numSubbands = (*buf++) & 1; //see A2DP table 12.20
+ uint8_t bitpoolSz = *buf++;
+ uint8_t hdrCRC = *buf++;
+ uint8_t bitpos = 0x80;
+
+ numChan = (chanMode == A2DP_CHAN_MODE_MONO) ? 1 : 2;
+
+ //process some numbers based on the tables
+ numSubbands = numSubbands ? 8 : 4;
+ blocks = (blocks + 1) << 2;
+
+ //read "join" table if expected
+ if(chanMode == A2DP_CHAN_MODE_JOINT_STEREO){
+ join = *buf; //we use it as a bitfield starting at top bit.
+ join >>= (8 - (numSubbands - 1));
+ join <<= (8 - (numSubbands - 1));
+ if(numSubbands == 8) buf++;
+ else bitpos = 0x08;
+ }
+
+ //read scale factors
+ for(ch = 0; ch < numChan; ch++) for(i = 0; i < numSubbands; i++){
+
+ if(bitpos == 0x80){
+
+ scaleFactors[ch][i] = (*buf) >> 4;
+ bitpos = 0x08;
+ }
+ else{
+
+ scaleFactors[ch][i] = (*buf++) & 0x0F;
+ bitpos = 0x80;
+ }
+ }
+
+ //calculate bitneed table and max_bitneed value (A2DP 12.6.3.1)
+ int8_t max_bitneed[2] = {0, 0};
+ for(ch = 0; ch < numChan; ch++){
+ if(snr){
+
+ for(i = 0; i < numSubbands; i++){
+
+ bitneed[ch][i] = scaleFactors[ch][i];
+ if(bitneed[ch][i] > max_bitneed[ch]) max_bitneed[ch] = bitneed[ch][i];
+ }
+ }
+ else{
+
+ const signed char* tbl;
+
+ if(numSubbands == 4) tbl = loudness_4[samplingRate];
+ else tbl = loudness_8[samplingRate];
+
+ for(i = 0; i < numSubbands; i++){
+
+ if(scaleFactors[ch][i]){
+
+ int loudness = scaleFactors[ch][i] - tbl[i];
+
+ if(loudness > 0) loudness /= 2;
+ bitneed[ch][i] = loudness;
+ }
+ else bitneed[ch][i] = -5;
+ if(bitneed[ch][i] > max_bitneed[ch]) max_bitneed[ch] = bitneed[ch][i];
+ }
+ }
+ }
+
+ if(chanMode == A2DP_CHAN_MODE_MONO || chanMode == A2DP_CHAN_MODE_DUAL_CHANNEL){
+ for(ch = 0; ch < numChan; ch++){
+ //fit bitslices into the bitpool
+ int32_t bitcount = 0, slicecount = 0, bitslice = max_bitneed[ch] + 1;
+ do{
+ bitslice--;
+ bitcount += slicecount;
+ slicecount = 0;
+ for(i = 0; i < numSubbands; i++){
+
+ if(bitneed[ch][i] > bitslice + 1 && bitneed[ch][i] < bitslice + 16) slicecount++;
+ else if(bitneed[ch][i] == bitslice + 1) slicecount += 2;
+ }
+
+ }while(bitcount + slicecount < bitpoolSz);
+
+ //distribute bits
+ for(i = 0; i < numSubbands; i++){
+
+ if(bitneed[ch][i] < bitslice + 2) bits[ch][i] = 0;
+ else{
+
+ int8_t v = bitneed[ch][i] - bitslice;
+ if(v > 16) v = 16;
+ bits[ch][i] = v;
+ }
+ }
+
+ //allocate remaining bits
+ for(i = 0; i < numSubbands && bitcount < bitpoolSz; i++){
+
+ if(bits[ch][i] >= 2 && bits[ch][i] < 16){
+
+ bits[ch][i]++;
+ bitcount++;
+ }
+ else if(bitneed[ch][i] == bitslice + 1 && bitpoolSz > bitcount + 1){
+
+ bits[ch][i] = 2;
+ bitcount += 2;
+ }
+ }
+ for(i = 0; i < numSubbands && bitcount < bitpoolSz; i++){
+
+ if(bits[ch][i] < 16){
+
+ bits[ch][i]++;
+ bitcount++;
+ }
+ }
+ }
+ }
+ else{
+ //calculate max_bitneed value (A2DP 12.6.3.2)
+ uint8_t max_bitneed_val = max_bitneed[0] > max_bitneed[1] ? max_bitneed[0] : max_bitneed[1];
+
+ //fit bitslices into the bitpool
+ int32_t bitcount = 0, slicecount = 0, bitslice = max_bitneed_val + 1;
+ do{
+ bitslice--;
+ bitcount += slicecount;
+ slicecount = 0;
+ for(ch = 0; ch < 2; ch++) for(i = 0; i < numSubbands; i++){
+
+ if(bitneed[ch][i] > bitslice + 1 && bitneed[ch][i] < bitslice + 16) slicecount++;
+ else if(bitneed[ch][i] == bitslice + 1) slicecount += 2;
+ }
+
+ }while(bitcount + slicecount < bitpoolSz);
+
+ //distribute bits
+ for(ch = 0; ch < 2; ch++) for(i = 0; i < numSubbands; i++){
+
+ if(bitneed[ch][i] < bitslice + 2) bits[ch][i] = 0;
+ else{
+
+ int8_t v = bitneed[ch][i] - bitslice;
+ if(v > 16) v = 16;
+ bits[ch][i] = v;
+ }
+ }
+
+ //allocate remaining bits
+ i = 0;
+ ch = 0;
+ while(i < numSubbands && bitcount < bitpoolSz){
+
+ if(bits[ch][i] >= 2 && bits[ch][i] < 16){
+
+ bits[ch][i]++;
+ bitcount++;
+ }
+ else if(bitneed[ch][i] == bitslice + 1 && bitpoolSz > bitcount + 1){
+
+ bits[ch][i] = 2;
+ bitcount += 2;
+ }
+ if(++ch == 2){
+ ch = 0;
+ i++;
+ }
+ }
+ i = 0;
+ ch = 0;
+ while(i < numSubbands && bitcount < bitpoolSz){
+
+ if(bits[ch][i] < 16){
+
+ bits[ch][i]++;
+ bitcount++;
+ }
+ if(++ch == 2){
+ ch = 0;
+ i++;
+ }
+ }
+ }
+
+ //reconstruct subband samples (A2DP 12.6.4)
+ #ifndef SPEED_OVER_ACCURACY
+ int32_t levels[2][8];
+ for(ch = 0; ch < numChan; ch++) for(i = 0; i < numSubbands; i++) levels[ch][i] = (1 << bits[ch][i]) - 1;
+ #endif
+ for(j = 0; j < blocks; j++){
+
+ for(ch = 0; ch < numChan; ch++) for(i = 0; i < numSubbands; i++){
+
+ if(bits[ch][i]){
+
+ uint32_t val = 0;
+ k = bits[ch][i];
+ do{
+
+ val <<= 1;
+ if(*buf & bitpos) val++;
+ if(!(bitpos >>= 1)){
+ bitpos = 0x80;
+ buf++;
+ }
+ }while(--k);
+
+ val = (val << 1) | 1;
+ val <<= scaleFactors[ch][i];
+
+ #ifdef SPEED_OVER_ACCURACY
+ val >>= bits[ch][i];
+ #else
+ val /= levels[ch][i];
+ #endif
+
+ val -= (1 << scaleFactors[ch][i]);
+
+ samples[j][ch][i] = SAMPLE_CVT(val);
+
+ }
+ else samples[j][ch][i] = SAMPLE_CVT(0);
+ }
+
+ //joint processing (if needed - if not needed join will be 0)
+ ITER bf = join;
+ for(i = 0; i < numSubbands; i++, bf <<= 1) if(bf & 0x80){
+
+ INSAMPLE t = samples[j][0][i];
+
+ samples[j][0][i] += samples[j][1][i];
+ samples[j][1][i] = t - samples[j][1][i];
+ }
+ }
+
+ //synthesis
+ static FIXED V[160] = {0, };
+ for(j = 0; j < blocks; j++){
+
+ //do the actual synthesis
+ synth(audio[whichBuf] + bufSamples, samples[j][0], numSubbands, V);
+ for(k = 0; k < numSubbands; k++, bufSamples++) audio[whichBuf][bufSamples] = (((int32_t)audio[whichBuf][bufSamples]) * vol) >> 8;
+
+ //if buffer is full, enqueue it
+ if(bufSamples == bufNumSamples){
+
+ audioAddBuffer(AUDIO_BT, audio[whichBuf++], bufSamples);
+
+ if(whichBuf == bufNumBuffers) whichBuf = 0;
+ bufSamples = 0;
+ }
+ }
+ //if we used a byte partially, skip the rest of it, it is "padding"
+ if(bitpos != 0x80) buf++;
+ if(left < 0) dbgPrintf("A2DP: buffer over-read: %d\n", left);
+ }
+}
+
+static void a2dpServiceDataRx(void* service, const uint8_t* req, uint16_t reqSz){
+
+ A2DPstate* state = service;
+ uint8_t trans, pktTyp, msgTyp, sigId, eid;
+ uint8_t buf[16];
+ uint16_t replSz = 0;
+
+ if(IS_DATA_STATE(service)){
+
+ if(DATA_STATE_ENCODE(service) == conns) a2dpSbcPlay(req, reqSz); //only latest plays data
+ return;
+ }
+
+ if(reqSz < 2){
+
+ dbgPrintf("A2DP: packet too small\n");
+ return;
+ }
+
+ trans = (req[0] & AVDTP_HDR_MASK_TRANS) >> AVDTP_HDR_SHIFT_TRANS;
+ pktTyp = (req[0] & AVDTP_HDR_MASK_PKT_TYP) >> AVDTP_HDR_SHIFT_PKT_TYP;
+ msgTyp = (req[0] & AVDTP_HDR_MASK_MSG_TYP) >> AVDTP_HDR_SHIFT_MSG_TYP;
+ sigId = (req[1] & AVDTP_HDR_MASK_SIG_ID) >> AVDTP_HDR_SHIFT_SIG_ID;
+ reqSz -= 2;
+ req += 2;
+
+ #if UGLY_SCARY_DEBUGGING_CODE
+ dbgPrintf("A2DP (%x) data(trans %d, pktTyp %d msgTyp %d sigId %d %ub)\n", state->remChan, trans, pktTyp, msgTyp, sigId, reqSz);
+ #endif
+
+ switch(sigId){
+
+ case AVDTP_SIG_DISCOVER:
+
+ if(reqSz) dbgPrintf("A2DP: unexpected further data in AVDTP_SIG_DISCOVER\n");
+ //packet header
+ buf[0] = (trans << AVDTP_HDR_SHIFT_TRANS) | (AVDTP_PKT_TYP_SINGLE << AVDTP_HDR_SHIFT_PKT_TYP) | (AVDTP_MSG_TYP_ACCEPT << AVDTP_HDR_SHIFT_MSG_TYP);
+ buf[1] = (sigId << AVDTP_HDR_SHIFT_SIG_ID);
+ //return a single SEID info structure
+ buf[2] = (MY_ENDPT_ID << AVDTP_SEID_NFO_SHIFT_SEID) | (0 << AVDTP_SEID_NFO_MASK_INUSE);
+ buf[3] = (AVDTP_MEDIA_TYP_AUDIO << AVDTP_SEID_NFO_SHIFT_MEDIA_TYP) | (AVDTP_DIR_SINK << AVDTP_SEID_NFO_SHIFT_TYP);
+ replSz = 4;
+ break;
+
+ case AVDTP_SIG_GET_CAPABILITIES:
+
+ if(reqSz > 1) dbgPrintf("A2DP: unexpected further data in AVDTP_SIG_GET_CAPABILITIES\n");
+ if(reqSz < 1){
+ dbgPrintf("A2DP: not enough data in AVDTP_SIG_GET_CAPABILITIES\n");
+ break;
+ }
+ eid = (*req++) >> 2;
+ if(eid != MY_ENDPT_ID){
+ dbgPrintf("A2DP: bad EID (%d) AVDTP_SIG_GET_CAPABILITIES\n", eid);
+ break;
+ }
+ //packet header
+ buf[0] = (trans << AVDTP_HDR_SHIFT_TRANS) | (AVDTP_PKT_TYP_SINGLE << AVDTP_HDR_SHIFT_PKT_TYP) | (AVDTP_MSG_TYP_ACCEPT << AVDTP_HDR_SHIFT_MSG_TYP);
+ buf[1] = (sigId << AVDTP_HDR_SHIFT_SIG_ID);
+ //capability 0 - media transport
+ buf[2] = AVDTP_SVC_CAT_MEDIA_TRANSPORT;
+ buf[3] = 0;
+ //capability 1 - SDB codec (and its info)
+ buf[4] = AVDTP_SVC_CAT_MEDIA_CODEC;
+ buf[5] = 6; //generic data is 2 bytes, SBC data is 4 bytes (see A2DP spec section 4.3.2)
+ buf[6] = (AVDTP_MEDIA_TYP_AUDIO << 4);
+ buf[7] = A2DP_CODEC_TYP_SBC;
+ buf[8] = 0xFF; //spec forces us to support all of these (even though ANDROID and LINUX both do not properly support mono [try it :) ])
+ buf[9] = 0xFF; //spec forces us to support all of these
+ buf[10] = 0x02; //min allowed by spec
+ buf[11] = 0x50; //nice high value
+ replSz = 12;
+ break;
+
+ case AVDTP_SIG_SET_CONFIGURATION:
+
+ if(reqSz < 8){ //no valid command is shorter
+ dbgPrintf("A2DP: not enough data in AVDTP_SIG_SET_CONFIGURATION\n");
+ break;
+ }
+ eid = (*req++) >> 2;
+ if(eid != MY_ENDPT_ID){
+ dbgPrintf("A2DP: bad EID (%d) AVDTP_SIG_GET_CAPABILITIES\n", eid);
+ break;
+ }
+ req++; //skip INT EID - we don't care
+ reqSz -= 2;
+ while(reqSz >= 2){
+
+ uint8_t cap = *req++;
+ uint8_t len = *req++;
+ reqSz -= 2;
+
+ if(len > reqSz) break;
+ reqSz -= len;
+
+ if(cap == AVDTP_SVC_CAT_MEDIA_CODEC){
+
+ if(*req++ != (AVDTP_MEDIA_TYP_AUDIO << 4)){
+ dbgPrintf("A2DP: requested data is not audio\n");
+ break;
+ }
+ else if(*req++ != A2DP_CODEC_TYP_SBC){
+ dbgPrintf("A2DP: requested codec is not SBC\n");
+ break;
+ }
+ else{
+
+ uint8_t samplingRate = (*req) >> 4;
+ uint8_t channelMode = (*req++) & 0x0F;
+ uint8_t blockLen = (*req) >> 4;
+ uint8_t subbands = (*req >> 2) & 3;
+ uint8_t allocMethod = (*req++) & 3;
+ uint8_t minBitpool = *req++;
+ uint8_t maxBitpool = *req++;
+
+ switch(samplingRate){
+ case 1: state->samplingRate = 48000; break;
+ case 2: state->samplingRate = 44100; break;
+ case 4: state->samplingRate = 32000; break;
+ case 8: state->samplingRate = 16000; break;
+ default:
+ dbgPrintf("A2DP: invalid sampling rate: %d\n", samplingRate);
+ goto out;
+ }
+ switch(blockLen){
+ case 1: blockLen = 16; break;
+ case 2: blockLen = 12; break;
+ case 4: blockLen = 8; break;
+ case 8: blockLen = 4; break;
+ default:
+ dbgPrintf("A2DP: invalid block len: %d\n", blockLen);
+ goto out;
+ }
+ switch(subbands){
+ case 1: subbands = 8; break;
+ case 2: subbands = 4; break;
+ default:
+ dbgPrintf("A2DP: invalid num subbands: %d\n", subbands);
+ goto out;
+ }
+ switch(allocMethod){
+ case 1: allocMethod = 0; break;
+ case 2: allocMethod = 1; break;
+ default:
+ dbgPrintf("A2DP: invalid allocMethod: %d\n", allocMethod);
+ goto out;
+ }
+ static const char* strMode[] = {NULL, "Joint Stereo", "Stereo", NULL, "Dual Channel", NULL, NULL, NULL, "Mono"};
+ dbgPrintf("A2DP:\n\t* %u %s-framed frames / block\n\t* %u subbands/frame\n\t* %u KHz sampling rate\n\t* '%s' channel mode\n\t* %u-%u bits per piece per channel\n",
+ blockLen, allocMethod ? "SNR" : "Loudness", subbands,
+ state->samplingRate, strMode[channelMode], minBitpool, maxBitpool);
+ }
+ }
+ else req += len;
+ }
+ if(reqSz){ //no valid command is shorter
+ dbgPrintf("A2DP: malformed config info in AVDTP_SIG_SET_CONFIGURATION\n");
+ }
+ else{
+ //prepare reply
+ buf[0] = (trans << AVDTP_HDR_SHIFT_TRANS) | (AVDTP_PKT_TYP_SINGLE << AVDTP_HDR_SHIFT_PKT_TYP) | (AVDTP_MSG_TYP_ACCEPT << AVDTP_HDR_SHIFT_MSG_TYP);
+ buf[1] = (sigId << AVDTP_HDR_SHIFT_SIG_ID);
+ replSz = 2;
+ #if UGLY_SCARY_DEBUGGING_CODE
+ dbgPrintf("A2DP: %u samp/sec, %db block w/%d subbands in %s mode with pool sizes %d-%d\n",
+ state->samplingRate, state->blockLen, state->subbands, state->allocTypeSNR ? "SNR" : "Loudness",
+ state->minBitpool, state->maxBitpool);
+ #endif
+ }
+ break;
+
+ case AVDTP_SIG_OPEN:
+
+ if(reqSz > 1) dbgPrintf("A2DP: unexpected further data in AVDTP_SIG_OPEN\n");
+ if(reqSz < 1){
+ dbgPrintf("A2DP: not enough data in AVDTP_SIG_OPEN\n");
+ break;
+ }
+ eid = (*req++) >> 2;
+ if(eid != MY_ENDPT_ID){
+ dbgPrintf("A2DP: bad EID (%d) AVDTP_SIG_OPEN\n", eid);
+ break;
+ }
+ state->needAudioConn = 1;
+ //packet header
+ buf[0] = (trans << AVDTP_HDR_SHIFT_TRANS) | (AVDTP_PKT_TYP_SINGLE << AVDTP_HDR_SHIFT_PKT_TYP) | (AVDTP_MSG_TYP_ACCEPT << AVDTP_HDR_SHIFT_MSG_TYP);
+ buf[1] = (sigId << AVDTP_HDR_SHIFT_SIG_ID);
+ replSz = 2;
+ break;
+
+ case AVDTP_SIG_START:
+
+ if(reqSz > 1) dbgPrintf("A2DP: unexpected further data in AVDTP_SIG_OPEN\n");
+ if(reqSz < 1){
+ dbgPrintf("A2DP: not enough data in AVDTP_SIG_OPEN\n");
+ break;
+ }
+ eid = (*req++) >> 2;
+ if(eid != MY_ENDPT_ID){
+ dbgPrintf("A2DP: bad EID (%d) AVDTP_SIG_OPEN\n", eid);
+ break;
+ }
+ audioOn(AUDIO_BT, state->samplingRate);
+ //packet header
+ buf[0] = (trans << AVDTP_HDR_SHIFT_TRANS) | (AVDTP_PKT_TYP_SINGLE << AVDTP_HDR_SHIFT_PKT_TYP) | (AVDTP_MSG_TYP_ACCEPT << AVDTP_HDR_SHIFT_MSG_TYP);
+ buf[1] = (sigId << AVDTP_HDR_SHIFT_SIG_ID);
+ replSz = 2;
+ break;
+
+ case AVDTP_SIG_CLOSE:
+ case AVDTP_SIG_SUSPEND:
+ case AVDTP_SIG_ABORT:
+
+ if(reqSz > 1) dbgPrintf("A2DP: unexpected further data in AVDTP_SIG_CLOSE/ABORT/SUSPEND\n");
+ if(reqSz < 1){
+ dbgPrintf("A2DP: not enough data in AVDTP_SIG_CLOSE/ABORT/SUSPEND\n");
+ break;
+ }
+ eid = (*req++) >> 2;
+ if(eid != MY_ENDPT_ID){
+ dbgPrintf("A2DP: bad EID (%d) AVDTP_SIG_CLOSE/ABORT/SUSPEND\n", eid);
+ break;
+ }
+ audioOff(AUDIO_BT);
+ //packet header
+ buf[0] = (trans << AVDTP_HDR_SHIFT_TRANS) | (AVDTP_PKT_TYP_SINGLE << AVDTP_HDR_SHIFT_PKT_TYP) | (AVDTP_MSG_TYP_ACCEPT << AVDTP_HDR_SHIFT_MSG_TYP);
+ buf[1] = (sigId << AVDTP_HDR_SHIFT_SIG_ID);
+ replSz = 2;
+ break;
+
+ default:
+
+ dbgPrintf("A2DP (%x) data(trans %d, pktTyp %d msgTyp %d sigId %d %ub)\n", state->remChan, trans, pktTyp, msgTyp, sigId, reqSz);
+ dbgPrintf("DATA: ");
+ while(reqSz--) dbgPrintf(" %02X", *req++);
+ dbgPrintf("\n");
+ break;
+ }
+
+out:
+ if(replSz){
+ sg_buf* sgbuf = sg_alloc();
+ if(!sgbuf) return;
+ if(sg_add_front(sgbuf, buf, replSz, SG_FLAG_MAKE_A_COPY)){
+
+ l2capServiceTx(state->aclConn, state->remChan, sgbuf);
+ }
+ else{
+
+ sg_free(sgbuf);
+ free(sgbuf);
+ }
+ }
+}
+
+static void* a2dpServiceAlloc(uint16_t conn, uint16_t chan, uint16_t remChan){
+
+ A2DPstate* state = conns;
+
+ while(state){
+
+ if(state->needAudioConn && state->aclConn == conn){
+
+ state->needAudioConn = 0;
+ return DATA_STATE_ENCODE(state);
+ }
+ state = state->next;
+ }
+
+ state = malloc(sizeof(A2DPstate));
+
+ if(state){
+
+ state->aclConn = conn;
+ state->remChan = remChan;
+ state->needAudioConn = 0;
+
+ state->next = conns;
+ conns = state;
+ }
+
+ return state;
+}
+
+static void a2dpServiceFree(void* service){
+
+ if(IS_DATA_STATE(service)) return;
+
+ A2DPstate *state = conns, *prev = NULL;
+
+ while(state){
+
+ if(state == service){
+
+ if(prev) prev->next = state->next;
+ else conns = state->next;
+
+ dbgPrintf("A2DP: connection %d.%d closed\n", state->aclConn, state->remChan);
+ if(conns) audioOn(AUDIO_BT, conns->samplingRate);
+
+ free(state);
+ return;
+ }
+
+ prev = state;
+ state = state->next;
+ }
+}
+
+static uint8_t sdpDescrA2DP[] =
+{
+ //service class ID list
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x01, SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 3,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x11, 0x0B, //Audio Sink
+ //ServiceId
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x03, SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x11, 0x0B, //Audio Sink
+ //ProtocolDescriptorList
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x04, SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 16,
+ SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 6,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x01, 0x00, // L2CAP
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), L2CAP_PSM_AVDTP >> 8, L2CAP_PSM_AVDTP & 0xFF, // AVDTP PSM
+ SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 6,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), L2CAP_PSM_AVDTP >> 8, L2CAP_PSM_AVDTP & 0xFF, // AVDTP
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x01, 0x00, //AVDTP version (as per spec)
+ //browse group list
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x05, SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 3,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x10, 0x02, // Public Browse Group
+ //profile descriptor list
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x09, SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 8,
+ SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 6,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x11, 0x0d, // Advanced Audio
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x01, 0x00, // Version 1.0
+ //name
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x01, 0x00, SDP_ITEM_DESC(SDP_TYPE_TEXT, SDP_SZ_u8), 8, 'A', 'D', 'K', ' ', 'A', '2', 'D', 'P'
+};
+
+
+char btA2dpRegister(void){
+
+ const L2capService a2dp = {L2CAP_FLAG_SUPPORT_CONNECTIONS, a2dpServiceAlloc, a2dpServiceFree, a2dpServiceDataRx};
+
+ if(!l2capServiceRegister(L2CAP_PSM_AVDTP, &a2dp)) return 0;
+ btSdpServiceDescriptorAdd(sdpDescrA2DP, sizeof(sdpDescrA2DP));
+
+ return 1;
+}
+
+
+
+
+/* original tables
+
+
+proto_4_40:
+ 0.00000000E+00,5.36548976E-04,1.49188357E-03,2.73370904E-03,
+ 3.83720193E-03,3.89205149E-03,1.86581691E-03,-3.06012286E-03,
+ 1.09137620E-02,2.04385087E-02,2.88757392E-02,3.21939290E-02,
+ 2.58767811E-02,6.13245186E-03,-2.88217274E-02,-7.76463494E-02,
+ 1.35593274E-01,1.94987841E-01,2.46636662E-01,2.81828203E-01,
+ 2.94315332E-01,2.81828203E-01,2.46636662E-01,1.94987841E-01,
+ -1.35593274E-01,-7.76463494E-02,-2.88217274E-02,6.13245186E-03,
+ 2.58767811E-02,3.21939290E-02,2.88757392E-02,2.04385087E-02,
+ -1.09137620E-02,-3.06012286E-03,1.86581691E-03,3.89205149E-03,
+ 3.83720193E-03,2.73370904E-03,1.49188357E-03,5.36548976E-04
+
+proto_8_80:
+
+ 0.00000000E+00,1.56575398E-04,3.43256425E-04,5.54620202E-04,
+ 8.23919506E-04,1.13992507E-03,1.47640169E-03,1.78371725E-03,
+ 2.01182542E-03,2.10371989E-03,1.99454554E-03,1.61656283E-03,
+ 9.02154502E-04,-1.78805361E-04,-1.64973098E-03,-3.49717454E-03,
+ 5.65949473E-03,8.02941163E-03,1.04584443E-02,1.27472335E-02,
+ 1.46525263E-02,1.59045603E-02,1.62208471E-02,1.53184106E-02,
+ 1.29371806E-02,8.85757540E-03,2.92408442E-03,-4.91578024E-03,
+ -1.46404076E-02,-2.61098752E-02,-3.90751381E-02,-5.31873032E-02,
+ 6.79989431E-02,8.29847578E-02,9.75753918E-02,1.11196689E-01,
+ 1.23264548E-01,1.33264415E-01,1.40753505E-01,1.45389847E-01,
+ 1.46955068E-01,1.45389847E-01,1.40753505E-01,1.33264415E-01,
+ 1.23264548E-01,1.11196689E-01,9.75753918E-02,8.29847578E-02,
+ -6.79989431E-02,-5.31873032E-02,-3.90751381E-02,-2.61098752E-02,
+ -1.46404076E-02,-4.91578024E-03,2.92408442E-03,8.85757540E-03,
+ 1.29371806E-02,1.53184106E-02,1.62208471E-02,1.59045603E-02,
+ 1.46525263E-02,1.27472335E-02,1.04584443E-02,8.02941163E-03,
+ -5.65949473E-03,-3.49717454E-03,-1.64973098E-03,-1.78805361E-04,
+ 9.02154502E-04,1.61656283E-03,1.99454554E-03,2.10371989E-03,
+ 2.01182542E-03,1.78371725E-03,1.47640169E-03,1.13992507E-03,
+ 8.23919506E-04,5.54620202E-04,3.43256425E-04,1.56575398E-04
+
+
+js code to convert to fixpoint:
+
+ var xa = new Array(values here...);
+
+ var num = 0;
+ var perRow = 4;
+ var L = parseInt(xa.length);
+
+ for(i = 0; i < L; i++){
+ x = xa[i];
+
+ var neg = 0;
+
+
+ if(x < 0){
+ neg = 1;
+ x = -x;
+ }
+ x *= (1 << 26); //this 26 should be the number of fraction bits
+ x = parseInt(x + 0.5);
+ s = x >> 28
+ x &= 0x0FFFFFFF;
+ if(neg){
+
+ x = x ^ 0x0FFFFFFF;
+ x++;
+ s ^= 0x0F;
+ if(x & 0x10000000) s++;
+ x &= 0x0FFFFFFF;
+ s &= 0x0F;
+ }
+
+ x = x.toString(16);
+ while(x.length < 7) x = "0" + x;
+ x = s.toString(16) + x;
+ x = x.toUpperCase();
+
+
+ document.write("0x" + x);
+ if(i != L - 1) document.write(",");
+ if(++num == perRow){
+ num = 0;
+ document.write("<BR>");
+ }
+ else document.write(" ");
+ }
+
+
+
+js code to produce costab (adjust loop variables as needed for both table vairants)
+
+ for(k = 0; k <= 7; k++) for(i = 0 ;i <= 3; i++){
+
+ document.write(Math.cos((i + 0.5) * (k + 2) * Math.PI / 4) + ", ")
+ }
+
+
+
+js code to generate order tables (they are used for those strange offsets into the V array in synth_* when generating samples):
+
+ var L = 200;
+ var V = new Array(L);
+ var U = new Array(80);
+ var i, j;
+ var nBands = 4;
+
+ for(i = 0; i <L; i++) V[i] = i + 1;
+
+
+ for(i = 0; i <= 4; i++) for(j = 0; j < nBands; j++){
+
+ if(nBands == 4){
+
+ U[i * 8 + j] = V[i * 16 + j];
+ U[i * 8 + 4 + j] = V[i * 16 + 12 + j];
+ }
+ else{
+
+ U[i * 16 + j] = V[i * 32 + j];
+ U[i * 16 + 8 + j] = V[i * 32 + 24 + j];
+ }
+ }
+
+
+ for(j = 0; j < nBands; j++) for(i = 0; i < 10; i++) document.write((U[j + nBands * i] - 1) + ",\t");
+
+
+
+
+
+
+
+C code for reordering the proto_* tables to access order. insert table values and modify nBands as needed
+
+ #include <stdio.h>
+ #include <stdint.h>
+
+
+
+ int32_t tabl[] =
+ {
+ table data here
+ };
+
+
+ int main(int argc, char** argv){
+
+ int i, j;
+ int nBands = 8;
+
+ for(j = 0; j < nBands; j++) for(i = 0; i < 10; i++) printf("0x%08X, ",tabl[j + nBands * i]);
+ }
+
+
+
+*/
+
diff --git a/library/ADK2/btA2DP.h b/library/ADK2/btA2DP.h
new file mode 100644
index 0000000..4711153
--- /dev/null
+++ b/library/ADK2/btA2DP.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _BT_A2DP_H_
+#define _BT_A2DP_H_
+
+
+
+
+char btA2dpRegister(void);
+
+
+
+#endif
+#endif
diff --git a/library/ADK2/btL2CAP.c b/library/ADK2/btL2CAP.c
new file mode 100644
index 0000000..42ca963
--- /dev/null
+++ b/library/ADK2/btL2CAP.c
@@ -0,0 +1,692 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "sgBuf.h"
+#include "btL2CAP.h"
+#include "BT.h"
+#include "dbg.h"
+#include <string.h>
+
+#define UGLY_SCARY_DEBUGGING_CODE 0
+
+#define L2CAP_CMD_REJECT 0x01
+#define L2CAP_CMD_CONN_REQ 0x02
+#define L2CAP_CMD_CONN_RESP 0x03
+#define L2CAP_CMD_CONFIG_REQ 0x04
+#define L2CAP_CMD_CONFIG_RESP 0x05
+#define L2CAP_CMD_DISC_REQ 0x06
+#define L2CAP_CMD_DISC_RESP 0x07
+#define L2CAP_CMD_ECHO_REQ 0x08
+#define L2CAP_CMD_ECHO_RESP 0x09
+#define L2CAP_CMD_INFO_REQ 0x0A
+#define L2CAP_CMD_INFO_RESP 0x0B
+
+#define L2CAP_CONN_SUCCESS 0x0000
+#define L2CAP_CONN_FAIL_NO_SUCH_PSM 0x0002
+#define L2CAP_CONN_FAIL_RESOURCES 0x0004
+
+#define L2CAP_REJECT_REASON_WTF 0x0000 //command not understood
+#define L2CAP_REJECT_REASON_INVALID_CID 0x0002
+
+#define L2CAP_FIRST_USABLE_CHANNEL 0x0040
+
+#define L2CAP_OPTION_MTU 1
+#define L2CAP_DEFAULT_MTU 672 //as per spec
+
+typedef struct Service{
+
+ struct Service* next;
+ uint16_t PSM;
+ L2capService descr;
+
+}Service;
+
+typedef struct Connection{
+
+ struct Connection* next;
+ Service* service;
+ void* serviceInstance;
+ uint16_t conn, chan, remChan;
+
+}Connection;
+
+Service* services = NULL;
+Connection* connections = NULL;
+
+static uint8_t gL2capID = 1;
+
+struct{
+
+ uint16_t conn;
+ uint16_t chan;
+ uint8_t* buf;
+ uint16_t lenGot;
+ uint16_t lenNeed;
+}gIncomingPieces[L2CAP_MAX_PIECED_MESSAGES] = {{0,},};
+
+
+
+static inline uint16_t getLE16(const uint8_t* ptr){
+
+ return (((uint16_t)ptr[1]) << 8) + ptr[0];
+}
+
+static inline void putLE16(uint8_t* ptr, uint16_t val){
+
+ ptr[0] = val & 0xFF;
+ ptr[1] = val >> 8;
+}
+
+void l2capServiceTx(uint16_t conn, uint16_t remChan, sg_buf* data){
+
+ uint8_t hdr[4];
+ uint16_t len = sg_length(data);
+
+ putLE16(hdr + 0, len);
+ putLE16(hdr + 2, remChan);
+
+ if(sg_add_front(data, hdr, 4, SG_FLAG_MAKE_A_COPY)){
+
+ #if UGLY_SCARY_DEBUGGING_CODE
+ uint32_t i;
+ uint8_t buf[256];
+ sg_copyto(data, buf);
+ dbgPrintf("L2CAP TX: ");
+ for(i = 0; i < sg_length(data); i++) dbgPrintf(" %02X", buf[i]);
+ dbgPrintf("\n");
+ #endif
+
+ btAclDataTx(conn, 1, BT_BCAST_NONE, data);
+ }
+ else{
+
+ sg_free(data);
+ free(data);
+ }
+}
+
+static void l2capSendControlRawBuf(uint16_t conn, const uint8_t* data, uint16_t len){
+
+ sg_buf* buf;
+
+ buf = sg_alloc();
+ if(buf){
+
+ if(sg_add_back(buf, data, len, SG_FLAG_MAKE_A_COPY)){
+
+ l2capServiceTx(conn, 1, buf);
+ }
+ else{
+
+ sg_free(buf);
+ free(buf);
+ }
+ }
+}
+
+static void l2capConnectionCloseEx(Connection* c, Connection* prev, char sendDiscPacket){
+
+ uint8_t discCmd[6];
+
+ if(c->service->descr.serviceInstanceFree) c->service->descr.serviceInstanceFree(c->serviceInstance);
+
+ if(sendDiscPacket){
+
+ discCmd[0] = L2CAP_CMD_DISC_REQ;
+ discCmd[1] = gL2capID++;
+ putLE16(discCmd + 2, c->remChan);
+ putLE16(discCmd + 4, c->chan);
+
+ l2capSendControlRawBuf(c->conn, discCmd, 6);
+ }
+
+ if(prev) prev->next = c->next;
+ else connections = c->next;
+ free(c);
+}
+
+static Connection* l2capFindConnection(uint16_t conn, uint16_t chan, Connection** prev){
+
+ Connection *c = connections, *p = NULL;
+
+ while(c && (c->conn != conn || c->chan != chan)){
+
+ p = c;
+ c = c->next;
+ }
+
+ if(prev) *prev = p;
+ return c;
+}
+
+static uint16_t l2capFindFreeLocalChannel(uint16_t conn){
+
+ Connection *c = connections;
+ uint32_t chan = L2CAP_FIRST_USABLE_CHANNEL;
+
+ //first try something fast
+ while(c){
+ if(c->chan >= chan && c->conn == conn) chan = c->chan + 1;
+ c = c->next;
+ }
+ if(chan <= 0xFFFF) return chan;
+
+ //else do something slower
+ for(chan = L2CAP_FIRST_USABLE_CHANNEL; chan <= 0xFFFF; chan++){
+
+ c = connections;
+ while(c && (c->chan != chan || c->conn != conn)) c = c->next;
+ if(!c) break;
+ }
+
+ if(chan <= 0xFFFF) return chan;
+
+ //now we failed
+ return 0;
+}
+
+void l2capServiceCloseConn(uint16_t conn, uint16_t chan){
+
+ Connection *c, *p;
+
+ if((c = l2capFindConnection(conn, chan, &p))) l2capConnectionCloseEx(c, p, 1);
+}
+
+static void l2capHandleControlChannel(uint16_t conn, const uint8_t* data, uint16_t size){
+
+ char rejectCommand = 0;
+ uint16_t rejectReason = L2CAP_REJECT_REASON_WTF;
+ Service* s = services;
+ Connection* c;
+ uint8_t cmd, id;
+ uint8_t buf[16];
+ uint16_t chan, remChan, len;
+
+ if(!gL2capID) gL2capID++;
+
+ if(size < 2){
+
+ rejectCommand = 1;
+ dbgPrintf("L2CAP: control packet too small\n");
+ }
+ else{
+
+ cmd = *data++;
+ id = *data++;
+ len = getLE16(data);
+ data += 2;
+ size -= 4;
+
+ if(len != size){
+
+ dbgPrintf("L2CAP (control packet internal sizes mismatch (%u != %u)\n", len, size);
+ rejectCommand = 1;
+ }
+ else switch(cmd){
+
+ case L2CAP_CMD_CONN_REQ:{
+
+ uint16_t PSM;
+
+ //get some request data
+ if(size != 4){
+
+ dbgPrintf("L2CAP: ConnectionRequest packet size is wrong(%u)\n", size);
+ rejectCommand = 1;
+ break;
+ }
+
+ PSM = getLE16(data + 0);
+ remChan = getLE16(data + 2);
+
+ //init the reply
+ buf[0] = L2CAP_CMD_CONN_RESP;
+ buf[1] = id;
+ putLE16(buf + 2, 8); //length
+ putLE16(buf + 4, 0); //DCID
+ putLE16(buf + 6, remChan); //SCID
+ putLE16(buf + 10, 0); //no further information
+
+ //find the service
+ while(s && s->PSM != PSM) s = s->next;
+ if(!s || !(s->descr.flags & L2CAP_FLAG_SUPPORT_CONNECTIONS)){
+
+ dbgPrintf("L2CAP: rejecting conection to unknown PSM 0x%04X\n", PSM);
+ putLE16(buf + 8, L2CAP_CONN_FAIL_NO_SUCH_PSM);
+ }
+ else{
+
+ void* instance = NULL;
+
+ chan = 0;
+ c = malloc(sizeof(Connection));
+ if(c) chan = l2capFindFreeLocalChannel(conn);
+ if(chan) instance = s->descr.serviceInstanceAllocate(conn, chan, remChan);
+
+ if(instance){
+
+ putLE16(buf + 4, chan);
+ putLE16(buf + 8, L2CAP_CONN_SUCCESS);
+
+ c->service = s;
+ c->serviceInstance = instance;
+ c->conn = conn;
+ c->chan = chan;
+ c->remChan = remChan;
+ c->next = connections;
+ connections = c;
+ }
+ else{
+
+ putLE16(buf + 8, L2CAP_CONN_FAIL_RESOURCES);
+
+ if(c) free(c);
+ }
+ }
+ size = 12;
+ break;
+ }
+
+ case L2CAP_CMD_CONFIG_REQ:{
+
+ uint16_t flags;
+
+ //get some request data
+ if(size < 4){
+ dbgPrintf("L2CAP: ConfigurationRequest packet size is wrong(%u)\n", size);
+ rejectCommand = 1;
+ break;
+ }
+
+ chan = getLE16(data + 0);
+ flags = getLE16(data + 2);
+ if(flags & 1){ //flags continue - we do not support that
+
+ size = 0;
+ break;
+ }
+ size -= 4;
+ data += 4;
+
+ //locate the connection at hand
+ c = l2capFindConnection(conn, chan, NULL);
+ if(!c){
+ dbgPrintf("L2CAP: ConfigurationRequest for an unknown channel %u.%u\n", conn, chan);
+ rejectCommand = 1;
+ break;
+ }
+ chan = c->remChan;
+
+ //reply with just our rx-MTU
+ buf[0] = L2CAP_CMD_CONFIG_RESP;
+ buf[1] = id;
+ putLE16(buf + 2, 10); //length
+ putLE16(buf + 4, c->remChan); //SCID
+ putLE16(buf + 6, 0); //flags
+ putLE16(buf + 8, 0); //success
+ buf[10] = L2CAP_OPTION_MTU; //mtu_property.type
+ buf[11] = 2; //mtu_property.len
+ putLE16(buf + 12, BT_RX_BUF_SZ - 8); //mtu value
+ l2capSendControlRawBuf(conn, buf, 14); //send it
+
+ //we need to send such a packet there too
+ buf[0] = L2CAP_CMD_CONFIG_REQ; //configuration request
+ buf[1] = gL2capID++;
+ putLE16(buf + 2, 4); //length
+ putLE16(buf + 4, c->remChan); //SCID
+ putLE16(buf + 6, 0); //flags
+ size = 8;
+ break;
+ }
+
+ case L2CAP_CMD_CONFIG_RESP:{
+
+ //we do nothing here - perhaps we should?
+ size = 0;
+ break;
+ }
+
+ case L2CAP_CMD_DISC_REQ:{
+
+ Connection* p;
+
+ //get some request data
+ if(size != 4){
+
+ dbgPrintf("L2CAP: DisconnectionRequest packet size is wrong(%u)\n", size);
+ rejectCommand = 1;
+ break;
+ }
+ chan = getLE16(data + 0);
+ remChan = getLE16(data + 2);
+ c = l2capFindConnection(conn, chan, &p);
+
+ //handle some likely error cases
+ if(!c){
+ dbgPrintf("L2CAP: DisconnectionRequest for an unknown channel %u.%u\n", conn, chan);
+ rejectReason = L2CAP_REJECT_REASON_INVALID_CID;
+ rejectCommand = 1; //reject as per spec
+ break;
+ }
+ if(c->remChan != remChan){
+ dbgPrintf("L2CAP: DisconnectionRequest for an unmatched channel on %u.%u (%u != %u)\n", conn, chan, c->remChan, remChan);
+ size = 0; //drop as per spec
+ break;
+ }
+
+ //perform needed cleanup
+ l2capConnectionCloseEx(c, p, 0);
+
+ //send the reply
+ buf[0] = L2CAP_CMD_DISC_RESP; //disconnection response
+ buf[1] = id; //copied as required
+ putLE16(buf + 2, 4); //length
+ putLE16(buf + 4, chan); //DCID
+ putLE16(buf + 6, remChan); //SCID
+ size = 8;
+ break;
+ }
+
+ case L2CAP_CMD_DISC_RESP:{
+
+ //nothing to do - we did cleanup when we requested the connection closure...
+ size = 0;
+ break;
+ }
+
+ case L2CAP_CMD_ECHO_REQ:{
+
+ buf[0] = L2CAP_CMD_ECHO_RESP; //ping response
+ buf[1] = id; //copied as required
+ putLE16(buf + 2, 0); //0-length replies are ok
+ size = 4;
+ break;
+ }
+
+ case L2CAP_CMD_INFO_REQ:{
+
+ uint16_t info;
+
+ //get some request data
+ if(size != 2){
+
+ dbgPrintf("L2CAP: InformationRequest packet size is wrong(%u)\n", size);
+ rejectCommand = 1;
+ break;
+ }
+ info = getLE16(data + 0);
+
+ buf[0] = L2CAP_CMD_INFO_RESP; //information response
+ buf[1] = id; //copied as required
+ putLE16(buf + 4, info); //info type
+ if(info == 1){ //connectionless mtu
+
+ putLE16(buf + 6, 0); //success
+ putLE16(buf + 8, BT_RX_BUF_SZ - 8);
+ putLE16(buf + 2, 6); //length
+ size = 10;
+ }
+ else if(info == 2){ //extended features
+
+ putLE16(buf + 6, 0); //success
+ putLE16(buf + 8, 0);
+ putLE16(buf + 10, 0);
+ putLE16(buf + 2, 8); //length
+ size = 12;
+ }
+ else{ //whatever this request is, we do not support it
+
+ putLE16(buf + 6, 1); //info type not supported
+ putLE16(buf + 2, 4); //length
+ size = 8;
+ }
+ break;
+ }
+
+ default:{
+
+ dbgPrintf("L2CAP: unexpected command 0x%02X recieved\n", cmd);
+ size = 0;
+ }
+ }
+ }
+
+ if(rejectCommand){
+
+ buf[0] = L2CAP_CMD_REJECT; //disconnection response
+ buf[1] = id; //copied as required
+ putLE16(buf + 2, 4); //length
+ putLE16(buf + 4, rejectReason); //rejection reason
+ size = 6;
+ }
+
+ if(size) l2capSendControlRawBuf(conn, buf, size);
+}
+
+
+char l2capServiceRegister(uint16_t PSM, const L2capService* svcData){
+
+ Service* s;
+
+ //first, see if this PSM is taken
+ s = services;
+ while(s){
+
+ if(s->PSM == PSM) return 0;
+ s = s->next;
+ }
+
+ //next, try to allocate the memory
+ s = malloc(sizeof(Service));
+ if(!s) return 0;
+
+ //then, init it and link it in
+ s->PSM = PSM;
+ s->descr = *svcData;
+ s->next = services;
+ services = s;
+
+ return 1;
+}
+
+char l2capServiceUnregister(uint16_t PSM){
+
+ Service *s = services, *ps = NULL;
+ Connection *c, *pc = NULL;
+
+ //first, find it in the list
+ while(s && s->PSM != PSM){
+
+ ps = s;
+ s = s->next;
+ }
+ if(!s) return 0;
+
+ //then, see if any connections are using it, and if so, kill them
+ do{
+ c = connections;
+ while(c){
+
+ if(c->service == s){
+
+ l2capConnectionCloseEx(c, pc, 1);
+ break;
+ }
+
+ pc = c;
+ c = c->next;
+ }
+ }while(c);
+
+ //now delete the service record
+ if(ps) ps->next = s->next;
+ else services = s->next;
+ free(s);
+ return 1;
+}
+
+void l2capAclLinkDataRx(uint16_t conn, char first, const uint8_t* data, uint16_t size){
+
+ uint16_t chan, len;
+ unsigned i;
+ char freeIt = 0;
+
+ #if UGLY_SCARY_DEBUGGING_CODE
+ dbgPrintf("L2CAP data:");
+ for(chan = 0; chan < size; chan++) dbgPrintf(" %02X", data[chan]);
+ dbgPrintf("\n\n");
+ #endif
+
+ if(first){
+
+ len = getLE16(data + 0);
+ chan = getLE16(data + 2);
+ data += 4;
+ size -= 4;
+
+ if(size >= len){
+ if(size > len) dbgPrintf("L2CAP: ACL provided likely invalid L2CAP packet (ACL.len=%u L2CAP.len=%u)\n", size, len);
+ }
+ else{
+ for(i = 0; i < L2CAP_MAX_PIECED_MESSAGES; i++){
+
+ if(gIncomingPieces[i].conn == conn){
+
+ dbgPrintf("L2CAP: conn %d: 'first' frame while another incomplete already buffered. Dropping the old one.\n", conn);
+ free(gIncomingPieces[i].buf);
+ gIncomingPieces[i].conn = 0;
+ break;
+ }
+ }
+ if(i == L2CAP_MAX_PIECED_MESSAGES) for(i = 0; i < L2CAP_MAX_PIECED_MESSAGES && gIncomingPieces[i].conn; i++);
+ if(i == L2CAP_MAX_PIECED_MESSAGES){
+
+ dbgPrintf("L2CAP: not enough buffer slots to buffer incomplete frame. Dropping\n");
+ }
+ else{
+
+ uint8_t* ptr = malloc(size);
+ if(!ptr){
+
+ dbgPrintf("L2CAP: cannot allocate partial frame buffer. Dropping\n");
+ return;
+ }
+ memcpy(ptr, data, size);
+ gIncomingPieces[i].buf = ptr;
+ gIncomingPieces[i].lenGot = size;
+ gIncomingPieces[i].lenNeed = len - size;
+ gIncomingPieces[i].chan = chan;
+ gIncomingPieces[i].conn = conn;
+ }
+ return;
+ }
+ }
+ else{
+
+ uint8_t* ptr;
+
+ for(i = 0; i < L2CAP_MAX_PIECED_MESSAGES && gIncomingPieces[i].conn != conn; i++);
+ if(i == L2CAP_MAX_PIECED_MESSAGES){
+ dbgPrintf("L2CAP: unexpected 'non-first' frame for conn %u. Dropping.\n", conn);
+ return;
+ }
+
+ if(size > gIncomingPieces[i].lenNeed){
+
+ dbgPrintf("L2CAP: 'non-first' frame too large. Need %u bytes, got %u. Dropping.\n", gIncomingPieces[i].lenNeed, size);
+ return;
+ }
+
+ ptr = realloc(gIncomingPieces[i].buf, gIncomingPieces[i].lenGot + size);
+ if(!ptr){
+
+ dbgPrintf("L2CAP: failed to resize buffer for partial frame receive. Droping\n");
+ free(gIncomingPieces[i].buf);
+ gIncomingPieces[i].conn = 0;
+ return;
+ }
+
+ memcpy(ptr + gIncomingPieces[i].lenGot, data, size);
+ gIncomingPieces[i].buf = ptr;
+ gIncomingPieces[i].lenGot += size;
+ gIncomingPieces[i].lenNeed -= size;
+
+ if(gIncomingPieces[i].lenNeed) return; //data still not complete
+
+ gIncomingPieces[i].conn = 0;
+ chan = gIncomingPieces[i].chan;
+ len = gIncomingPieces[i].lenGot;
+ data = ptr;
+ freeIt = 1;
+ }
+
+ if(chan == 0) dbgPrintf("L2CAP: data on connection %u.0\n", conn);
+ else if(chan == 1) l2capHandleControlChannel(conn, data, len);
+ else if(chan == 2){ //connectionless
+
+ uint16_t PSM = getLE16(data + 0);
+ data += 2;
+ len -= 2;
+
+ Service* s = services;
+
+ while(s && s->PSM != PSM) s = s->next;
+ if(!s || !(s->descr.flags & L2CAP_FLAG_SUPPORT_CONNECTIONLESS)) dbgPrintf("L2CAP: connectionless data on %u.2 for unknown PSM 0x%04X\n", conn, PSM);
+ else s->descr.serviceRx(NULL, data, len);
+ }
+ else{ //conection-oriented
+
+ Connection* c = l2capFindConnection(conn, chan, NULL);
+ if(!c) dbgPrintf("L2CAP: data for nonexistent connection %u.%u\n", conn, chan);
+ else c->service->descr.serviceRx(c->serviceInstance, data, len);
+ }
+
+ if(freeIt) free(data);
+}
+
+void l2capAclLinkUp(uint16_t conn){
+
+ //nothing here [yet?]
+}
+
+void l2capAclLinkDown(uint16_t conn){
+
+ Connection *p, *c;
+ unsigned i;
+
+ do{
+
+ p = NULL;
+ c = connections;
+
+ while(c && c->conn != conn){
+
+ p = c;
+ c = c->next;
+ }
+
+ if(c) l2capConnectionCloseEx(c, p, 0);
+
+ }while(c);
+
+ for(i = 0; i < L2CAP_MAX_PIECED_MESSAGES; i++) if(gIncomingPieces[i].conn == conn){
+
+ free(gIncomingPieces[i].buf);
+ gIncomingPieces[i].conn = 0;
+ }
+}
+
diff --git a/library/ADK2/btL2CAP.h b/library/ADK2/btL2CAP.h
new file mode 100644
index 0000000..de426b0
--- /dev/null
+++ b/library/ADK2/btL2CAP.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef _BT_L2CAP_H_
+#define _BT_L2CAP_H_
+
+#include <stdint.h>
+
+#define L2CAP_FLAG_SUPPORT_CONNECTIONS 1
+#define L2CAP_FLAG_SUPPORT_CONNECTIONLESS 2
+
+#define L2CAP_CHAN_CONNECTIONLESS 2 //pass to capServiceTx as needed
+
+
+#define L2CAP_PSM_SDP 0x0001
+#define L2CAP_PSM_RFCOMM 0x0003
+#define L2CAP_PSM_AVDTP 0x0019
+
+
+#define L2CAP_MAX_PIECED_MESSAGES 4 //most broken messages we support *at once*
+
+typedef struct{
+
+ uint8_t flags;
+
+ void* (*serviceInstanceAllocate)(uint16_t conn, uint16_t chan, uint16_t remChan);
+ void (*serviceInstanceFree)(void* service);
+
+ void (*serviceRx)(void* service, const uint8_t* data, uint16_t size);
+
+}L2capService;
+
+#ifdef ADK_INTERNAL
+
+#include "sgBuf.h"
+
+//API for services
+void l2capServiceTx(uint16_t conn, uint16_t remChan, sg_buf* data);
+void l2capServiceCloseConn(uint16_t conn, uint16_t chan);
+
+//API for service management
+char l2capServiceRegister(uint16_t PSM, const L2capService* svcData);
+char l2capServiceUnregister(uint16_t PSM);
+
+
+//API for ACL
+void l2capAclLinkUp(uint16_t conn);
+void l2capAclLinkDataRx(uint16_t conn, char first, const uint8_t* data, uint16_t size);
+void l2capAclLinkDown(uint16_t conn);
+
+
+#endif
+#endif
diff --git a/library/ADK2/btRFCOMM.c b/library/ADK2/btRFCOMM.c
new file mode 100644
index 0000000..de152db
--- /dev/null
+++ b/library/ADK2/btRFCOMM.c
@@ -0,0 +1,507 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "btRFCOMM.h"
+#include "BT.h"
+#include "dbg.h"
+#include "btL2CAP.h"
+#include "coop.h"
+
+//NOTE: to be good citizens, we really should verify incoming CRC. We have better things to do...sorry...
+//Plus, they do not provide safety for the data since data is not checksummed.
+//We are, however, forced to produce good CRCs.
+
+#define UGLY_SCARY_DEBUGGING_CODE 0
+
+#define BT_RFCOMM_DLCI_MSK_EA 0x01
+#define BT_RFCOMM_DLCI_MSK_CR 0x02
+#define BT_RFCOMM_DLCI_MSK_D 0x04
+#define BT_RFCOMM_DLCI_SHIFT 2
+
+#define BT_SZ_MASK_OVER 0x01
+
+#define BT_RFCOMM_CMD_DM 0x0F
+#define BT_RFCOMM_CMD_SABM 0x3F
+#define BT_RFCOMM_CMD_DISC 0x53
+#define BT_RFCOMM_CMD_UA 0x73
+#define BT_RFCOMM_CMD_UIH 0xEF
+#define BT_RFCOMM_CMD_UIH_CRED 0xFF
+
+//_C = command _R = resp
+#define BT_RFCOMM_NSC_R 0x11
+#define BT_RFCOMM_TEST_R 0x21
+#define BT_RFCOMM_TEST_C 0x23
+#define BT_RFCOMM_RLS_R 0x51
+#define BT_RFCOMM_RLS_C 0x53
+#define BT_RFCOMM_FCOFF_R 0x61
+#define BT_RFCOMM_FCOFF_C 0x63
+#define BT_RFCOMM_PN_R 0x81
+#define BT_RFCOMM_PN_C 0x83
+#define BT_RFCOMM_RPN_R 0x91
+#define BT_RFCOMM_RPN_C 0x93
+#define BT_RFCOMM_FCON_R 0xA1
+#define BT_RFCOMM_FCON_C 0xA3
+#define BT_RFCOMM_CLD_C 0xC3
+#define BT_RFCOMM_MSC_R 0xE1
+#define BT_RFCOMM_MSC_C 0xE3
+
+
+#define BT_RFCOMM_REMOTE_CREDS 4
+#define BT_RFCOMM_MAX_CRED_DEBT (BT_RFCOMM_REMOTE_CREDS - 1)
+
+typedef struct{
+
+ uint8_t addr;
+ uint8_t control;
+ uint8_t length; //we do not support 2-byte length
+ uint8_t data[]; //and one byte CRC (FCS)
+}RfcommPacket;
+
+typedef struct{
+
+ BtRfcommPortOpenF oF;
+ BtRfcommPortCloseF cF;
+ BtRfcommPortRxF rF;
+
+}RfcommPort;
+
+static RfcommPort gPortHandlers[NUM_DLCIs] = {{0,}, };
+
+static uint64_t reserved = 0xC000000000000003; //these are always reserved
+
+typedef struct{
+
+ uint16_t aclConn;
+ uint16_t remChan;
+ struct{
+
+ sg_buf* queued;
+ uint16_t MTU;
+ uint8_t credits;
+ uint8_t creditsOwed;
+ char on;
+
+ }ports[NUM_DLCIs];
+
+}RfcommInstanceState;
+
+extern uint8_t btRfcommFcs(uint8_t *data, uint32_t len);
+
+static void btRfcommSend(uint16_t conn, uint16_t remChan, const uint8_t* data, uint16_t sz){
+
+ int i;
+
+ #if UGLY_SCARY_DEBUGGING_CODE
+ dbgPrintf("Sending RFCOMM packet:");
+ for(i = 0; i < sz; i++) dbgPrintf(" %02X", data[i]);
+ dbgPrintf("\n\n");
+ #endif
+
+ sg_buf* buf = sg_alloc();
+ if(!buf) return;
+ if(sg_add_front(buf, data, sz, SG_FLAG_MAKE_A_COPY)){
+
+ l2capServiceTx(conn, remChan, buf);
+ return;
+ }
+ sg_free(buf);
+ free(buf);
+}
+
+static void btRfcommTxData(RfcommInstanceState* state, uint8_t dlci, sg_buf* buf){
+
+ uint8_t data[5] = {(dlci << BT_RFCOMM_DLCI_SHIFT) | BT_RFCOMM_DLCI_MSK_EA, BT_RFCOMM_CMD_UIH};
+ uint32_t dataLen = sg_length(buf);
+ uint8_t hdrLen = 3;
+
+ if(dataLen >= 128){ //need 2 length bytes
+
+ data[2] = dataLen << 1;
+ data[3] = dataLen >> 7;
+ hdrLen++;
+ } else data[2] = (dataLen << 1) | 1;
+
+ if(state->ports[dlci].creditsOwed){ //use the oportunity to send the credits
+
+ data[1] = BT_RFCOMM_CMD_UIH_CRED;
+ data[hdrLen++] = state->ports[dlci].creditsOwed;
+ state->ports[dlci].creditsOwed = 0;
+ }
+
+ if(sg_add_front(buf, data, hdrLen, SG_FLAG_MAKE_A_COPY)){
+
+ data[0] = btRfcommFcs(data, 2);
+
+ if(sg_add_back(buf, data, 1, SG_FLAG_MAKE_A_COPY)){
+
+ l2capServiceTx(state->aclConn, state->remChan, buf);
+ return;
+ }
+ }
+ sg_free(buf);
+ free(buf);
+}
+
+static void rfcommServiceDataRx(void* service, const uint8_t* req, uint16_t reqSz){
+
+ RfcommInstanceState* state = service;
+ const uint16_t conn = state->aclConn;
+ const uint16_t remChan = state->remChan;
+ const RfcommPacket* p = (RfcommPacket*)req; //note that we can do this only because packet has no non-8-bit-members
+ const uint8_t* data = p->data;
+ int i;
+ uint8_t DLCI = p->addr >> BT_RFCOMM_DLCI_SHIFT;
+ uint8_t ctrl = p->control;
+ uint16_t len;
+ uint8_t buf[32];
+
+
+ if(p->length & 1){
+
+ len = p->length >> 1;
+ }
+ else{
+
+ len = *data++;
+ len <<= 7;
+ len |= p->length >> 1;
+ }
+
+ if(ctrl == BT_RFCOMM_CMD_SABM || ctrl == BT_RFCOMM_CMD_DISC){
+
+ buf[ 0] = p->addr;
+ buf[ 1] = BT_RFCOMM_CMD_UA;
+ buf[ 2] = BT_SZ_MASK_OVER;
+ buf[ 3] = btRfcommFcs(buf, 3);
+ btRfcommSend(conn, remChan, buf, 4);
+
+ if(state->ports[DLCI].queued){
+
+ sg_free(state->ports[DLCI].queued);
+ free(state->ports[DLCI].queued);
+ }
+
+ state->ports[DLCI].creditsOwed = 0;
+ state->ports[DLCI].credits = 0;
+ state->ports[DLCI].queued = NULL;
+
+ if(ctrl == BT_RFCOMM_CMD_SABM){
+
+ if(gPortHandlers[DLCI].oF) gPortHandlers[DLCI].oF(state, DLCI);
+ else if(UGLY_SCARY_DEBUGGING_CODE) dbgPrintf("DLCI %2d opened\n", DLCI);
+ state->ports[DLCI].on = 0;
+ }
+ else{
+
+ if(gPortHandlers[DLCI].cF) gPortHandlers[DLCI].cF(state, DLCI);
+ else if(UGLY_SCARY_DEBUGGING_CODE) dbgPrintf("DLCI %2d closed\n", DLCI);
+ state->ports[DLCI].on = 1;
+ }
+ return;
+ }
+
+ if(ctrl == BT_RFCOMM_CMD_UIH && DLCI){ //we got a msg - send back credits if we already owe the limit, else buffer it
+
+ if(++state->ports[DLCI].creditsOwed == BT_RFCOMM_MAX_CRED_DEBT){
+
+ buf[ 0] = p->addr;
+ buf[ 1] = BT_RFCOMM_CMD_UIH_CRED;
+ buf[ 2] = BT_SZ_MASK_OVER;
+ buf[ 3] = state->ports[DLCI].creditsOwed + 1;
+ buf[ 4] = btRfcommFcs(buf, 2);
+ btRfcommSend(conn, remChan, buf, 5);
+ state->ports[DLCI].creditsOwed = 0;
+ }
+ }
+ if(ctrl == BT_RFCOMM_CMD_UIH_CRED){
+
+ state->ports[DLCI].credits += *data++;
+ ctrl = BT_RFCOMM_CMD_UIH;
+
+ if(state->ports[DLCI].queued && state->ports[DLCI].credits){
+
+ state->ports[DLCI].credits--;
+ btRfcommTxData(state, DLCI, state->ports[DLCI].queued);
+ state->ports[DLCI].queued = NULL;
+ }
+ }
+
+ if(DLCI == 0){ //control channel transaction
+ if(ctrl == BT_RFCOMM_CMD_UIH){ //data recieved
+
+ switch(data[0]){
+
+ case BT_RFCOMM_PN_C:{ //negotiations are for wusses!
+
+ uint8_t targetDLCI = data[2] & 0x3F;
+
+ state->ports[targetDLCI].credits = data[9];
+ state->ports[targetDLCI].MTU = (((uint16_t)data[7]) << 8) | data[6];
+
+ buf[ 0] = BT_RFCOMM_DLCI_MSK_EA;
+ buf[ 1] = BT_RFCOMM_CMD_UIH;
+ buf[ 2] = BT_SZ_MASK_OVER + (10 << 1);
+ buf[ 3] = BT_RFCOMM_PN_R;
+ buf[ 4] = BT_SZ_MASK_OVER + (8 << 1);
+ buf[ 5] = targetDLCI;
+ buf[ 6] = (data[3] == 0xF0) ? 0xE0 : 0x00; //as per spec
+ buf[ 7] = data[4]; //copy as per spec
+ buf[ 8] = 0; //0 as per spec
+ buf[ 9] = RFCOMM_MTU & 0xFF; //max_packet_size.lo
+ buf[ 10] = RFCOMM_MTU >> 8; //max_packet_size.hi
+ buf[ 11] = 0; //0 retransmissions
+ buf[ 12] = BT_RFCOMM_REMOTE_CREDS; //initial credits
+ buf[ 13] = btRfcommFcs(buf, 2);
+ btRfcommSend(conn, remChan, buf, 14);
+ break;
+ }
+
+ case BT_RFCOMM_RPN_C: //we need to echo back the negotiation
+ case BT_RFCOMM_MSC_C:{ //we need to echo back the control signals
+
+ if(len > 127) dbgPrintf("Control packet way too big\n");
+ else{
+
+ buf[ 0] = BT_RFCOMM_DLCI_MSK_EA;
+ buf[ 1] = BT_RFCOMM_CMD_UIH;
+ buf[ 2] = p->length;
+ buf[ 3] = (data[0] == BT_RFCOMM_MSC_C) ? BT_RFCOMM_MSC_R : BT_RFCOMM_RPN_C;
+ buf[ 4] = data[1];
+ for(i = 0; i < data[1] >> 1; i++) buf[ 5 + i] = data[2 + i];
+ buf[ 5 + i] = btRfcommFcs(buf, 2);
+ btRfcommSend(conn, remChan, buf, 6 + i);
+
+ if(data[0] == BT_RFCOMM_MSC_C){
+ //now we send our own signals (coincidentally they are identical ;-)
+ buf[ 3] = BT_RFCOMM_MSC_C;
+ btRfcommSend(conn, remChan, buf, 6 + i);
+ }
+ }
+ break;
+ }
+
+ case BT_RFCOMM_RPN_R:
+ case BT_RFCOMM_MSC_R:{
+
+ //nothing to do about this :)
+ break;
+ }
+
+ default:
+
+ dbgPrintf("Recieved unhandled RFCOMM packet:");
+ for(i = 0; i < reqSz; i++) dbgPrintf(" %02X", req[i]);
+ dbgPrintf("\n\n");
+ break;
+ }
+ }
+ }
+ else if(ctrl == BT_RFCOMM_CMD_UIH){
+
+ if(len){
+
+ if(gPortHandlers[DLCI].rF) gPortHandlers[DLCI].rF(state, DLCI, data, len);
+ else if(UGLY_SCARY_DEBUGGING_CODE){
+
+ dbgPrintf("RFCOMM DLCI %d data:", p->addr >> 2);
+ for(i = 0; i < len; i++) dbgPrintf(" %02X", data[i]);
+ dbgPrintf("\n\n\n");
+ }
+ }
+ }
+ else{
+
+ dbgPrintf("Recieved unhandled RFCOMM cmd (dlci=%d):", DLCI);
+ for(i = 0; i < reqSz; i++) dbgPrintf(" %02X", req[i]);
+ dbgPrintf("\n\n");
+ }
+}
+
+static void* rfcommServiceAlloc(uint16_t conn, uint16_t chan, uint16_t remChan){
+
+ RfcommInstanceState* state = malloc(sizeof(RfcommInstanceState));
+ int i;
+
+ if(!state) return NULL;
+
+ state->aclConn = conn;
+ state->remChan = remChan;
+
+ for(i = 0; i < NUM_DLCIs; i++){
+
+ state->ports[i].creditsOwed = 0;
+ state->ports[i].credits = 0;
+ state->ports[i].on = 0;
+ state->ports[i].queued = 0;
+ }
+
+ return state;
+}
+
+static void rfcommServiceFree(void* service){
+
+ free(service);
+}
+
+void btRfcommRegisterL2capService(){
+
+ const L2capService rfcom = {L2CAP_FLAG_SUPPORT_CONNECTIONS, rfcommServiceAlloc, rfcommServiceFree, rfcommServiceDataRx};
+ if(!l2capServiceRegister(L2CAP_PSM_RFCOMM, &rfcom)) dbgPrintf("SDP L2CAP registration failed\n");
+}
+
+void btRfcommRegisterPort(uint8_t dlci, BtRfcommPortOpenF oF, BtRfcommPortCloseF cF, BtRfcommPortRxF rF){
+
+ if(dlci >= NUM_DLCIs) return; //no such DLCI;
+
+ gPortHandlers[dlci].oF = oF;
+ gPortHandlers[dlci].cF = cF;
+ gPortHandlers[dlci].rF = rF;
+}
+
+void btRfcommPortTx(void* port, uint8_t dlci, const uint8_t* data, uint16_t size){
+
+ RfcommInstanceState* state = port;
+
+ if(dlci >= NUM_DLCIs || dlci == 0) return; //cannot send there, buddy...
+
+ sg_buf* buf = sg_alloc();
+ if(!buf) return;
+
+ if(!sg_add_front(buf, data, size, SG_FLAG_MAKE_A_COPY)){
+
+ sg_free(buf);
+ free(buf);
+ }
+ else{
+
+ if(state->ports[dlci].credits){ //send immediately
+
+ state->ports[dlci].credits--;
+ btRfcommTxData(state, dlci, buf);
+ }
+ else{ //enqueue it
+
+ if(state->ports[dlci].queued){
+
+ while(state->ports[dlci].queued && state->ports[dlci].on) coopYield();
+ if(!state->ports[dlci].on) return; //port closed - packet dropped
+ }
+ state->ports[dlci].queued = buf;
+ }
+ }
+}
+
+#define RFCOMM_DLCI_PREFERENCE_NONE 0x80 //use this param to the below
+#define RFCOMM_DLCI_NEED_EVEN 0x81
+#define RFCOMM_DLCI_NEED_ODD 0x82
+
+uint8_t btRfcommReserveDlci(uint8_t preference){
+
+ uint8_t start = 0, end = 64, step = 2;
+
+ if(preference == RFCOMM_DLCI_PREFERENCE_NONE) step = 1;
+ else if(preference == RFCOMM_DLCI_NEED_EVEN);
+ else if(preference == RFCOMM_DLCI_NEED_ODD) start++;
+ else{
+
+ start = preference;
+ end = preference + 1;
+ step = 1;
+ }
+
+ while(start < end && (reserved & (1ULL << ((uint64_t)start)))) start += step;
+
+ if(start >= end) return 0; //we failed
+
+ reserved |= (1ULL << ((uint64_t)start));
+
+ return start;
+}
+
+void btRfcommReleaseDlci(uint8_t dlci){
+
+ reserved &=~ (1ULL << ((uint64_t)dlci));
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+static const uint8_t crctab[256] = {
+ 0x00, 0x91, 0xE3, 0x72, 0x07, 0x96, 0xE4, 0x75,
+ 0x0E, 0x9F, 0xED, 0x7C, 0x09, 0x98, 0xEA, 0x7B,
+ 0x1C, 0x8D, 0xFF, 0x6E, 0x1B, 0x8A, 0xF8, 0x69,
+ 0x12, 0x83, 0xF1, 0x60, 0x15, 0x84, 0xF6, 0x67,
+ 0x38, 0xA9, 0xDB, 0x4A, 0x3F, 0xAE, 0xDC, 0x4D,
+ 0x36, 0xA7, 0xD5, 0x44, 0x31, 0xA0, 0xD2, 0x43,
+ 0x24, 0xB5, 0xC7, 0x56, 0x23, 0xB2, 0xC0, 0x51,
+ 0x2A, 0xBB, 0xC9, 0x58, 0x2D, 0xBC, 0xCE, 0x5F,
+ 0x70, 0xE1, 0x93, 0x02, 0x77, 0xE6, 0x94, 0x05,
+ 0x7E, 0xEF, 0x9D, 0x0C, 0x79, 0xE8, 0x9A, 0x0B,
+ 0x6C, 0xFD, 0x8F, 0x1E, 0x6B, 0xFA, 0x88, 0x19,
+ 0x62, 0xF3, 0x81, 0x10, 0x65, 0xF4, 0x86, 0x17,
+ 0x48, 0xD9, 0xAB, 0x3A, 0x4F, 0xDE, 0xAC, 0x3D,
+ 0x46, 0xD7, 0xA5, 0x34, 0x41, 0xD0, 0xA2, 0x33,
+ 0x54, 0xC5, 0xB7, 0x26, 0x53, 0xC2, 0xB0, 0x21,
+ 0x5A, 0xCB, 0xB9, 0x28, 0x5D, 0xCC, 0xBE, 0x2F,
+ 0xE0, 0x71, 0x03, 0x92, 0xE7, 0x76, 0x04, 0x95,
+ 0xEE, 0x7F, 0x0D, 0x9C, 0xE9, 0x78, 0x0A, 0x9B,
+ 0xFC, 0x6D, 0x1F, 0x8E, 0xFB, 0x6A, 0x18, 0x89,
+ 0xF2, 0x63, 0x11, 0x80, 0xF5, 0x64, 0x16, 0x87,
+ 0xD8, 0x49, 0x3B, 0xAA, 0xDF, 0x4E, 0x3C, 0xAD,
+ 0xD6, 0x47, 0x35, 0xA4, 0xD1, 0x40, 0x32, 0xA3,
+ 0xC4, 0x55, 0x27, 0xB6, 0xC3, 0x52, 0x20, 0xB1,
+ 0xCA, 0x5B, 0x29, 0xB8, 0xCD, 0x5C, 0x2E, 0xBF,
+ 0x90, 0x01, 0x73, 0xE2, 0x97, 0x06, 0x74, 0xE5,
+ 0x9E, 0x0F, 0x7D, 0xEC, 0x99, 0x08, 0x7A, 0xEB,
+ 0x8C, 0x1D, 0x6F, 0xFE, 0x8B, 0x1A, 0x68, 0xF9,
+ 0x82, 0x13, 0x61, 0xF0, 0x85, 0x14, 0x66, 0xF7,
+ 0xA8, 0x39, 0x4B, 0xDA, 0xAF, 0x3E, 0x4C, 0xDD,
+ 0xA6, 0x37, 0x45, 0xD4, 0xA1, 0x30, 0x42, 0xD3,
+ 0xB4, 0x25, 0x57, 0xC6, 0xB3, 0x22, 0x50, 0xC1,
+ 0xBA, 0x2B, 0x59, 0xC8, 0xBD, 0x2C, 0x5E, 0xCF
+};
+
+uint8_t btRfcommFcs(uint8_t *data, uint32_t len){ //calculate fcs value for RFCOMM
+
+ uint32_t i;
+ uint8_t crcval = 0xFF;
+
+ for (i = 0; i < len; i++) crcval = crctab[crcval ^ (*data++)];
+
+ return 0xFF - crcval;
+}
diff --git a/library/ADK2/btRFCOMM.h b/library/ADK2/btRFCOMM.h
new file mode 100644
index 0000000..fe9abeb
--- /dev/null
+++ b/library/ADK2/btRFCOMM.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef _BT_RFCOMM_H_
+#define _BT_RFCOMM_H_
+
+#include <stdint.h>
+
+#define NUM_DLCIs 62
+#define RFCOMM_MTU 511
+#define RFCOMM_DLCI_PREFERENCE_NONE 0x80 //use this param to the below
+#define RFCOMM_DLCI_NEED_EVEN 0x81
+#define RFCOMM_DLCI_NEED_ODD 0x82
+
+typedef void (*BtRfcommPortOpenF)(void* port, uint8_t dlci);
+typedef void (*BtRfcommPortCloseF)(void* port, uint8_t dlci);
+typedef void (*BtRfcommPortRxF)(void* port, uint8_t dlci, const uint8_t* buf, uint16_t sz);
+
+
+#ifdef ADK_INTERNAL
+
+#include "BT.h"
+
+
+void btRfcommRegisterPort(uint8_t dlci, BtRfcommPortOpenF oF, BtRfcommPortCloseF cF, BtRfcommPortRxF rF);
+void btRfcommPortTx(void* port, uint8_t dlci, const uint8_t* data, uint16_t size); //makes a copy of your buffer
+
+
+uint8_t btRfcommReserveDlci(uint8_t preference); //return dlci if success, zero if fail
+void btRfcommReleaseDlci(uint8_t dlci);
+
+
+void btRfcommRegisterL2capService(void);
+
+
+#endif
+#endif
+
diff --git a/library/ADK2/btSDP.c b/library/ADK2/btSDP.c
new file mode 100644
index 0000000..75a6035
--- /dev/null
+++ b/library/ADK2/btSDP.c
@@ -0,0 +1,746 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "btSDP.h"
+#include <string.h>
+#include "sgBuf.h"
+#include "btL2CAP.h"
+
+
+#define SDP_PDU_Error_Response 1
+#define SDP_PDU_Service_Search_Request 2
+#define SDP_PDU_Service_Search_Response 3
+#define SDP_PDU_Service_Attribute_Request 4
+#define SDP_PDU_Service_Attribute_Response 5
+#define SDP_PDU_Service_Search_Attribute_Request 6
+#define SDP_PDU_Service_Search_Attribute_Response 7
+
+#define SDP_ERR_Invalid_SDP_Version 0x0001
+#define SDP_ERR_Invalid_Service_Record_Handle 0x0002
+#define SDP_ERR_Invalid_Request_Syntax 0x0003
+#define SDP_ERR_Invalid_PDU_Size 0x0004
+#define SDP_ERR_Invalid_Continuation_State 0x0005
+#define SDP_ERR_Insufficient_Resources 0x0006
+
+
+typedef struct{
+
+ uint64_t hi, lo;
+
+}uuid;
+
+#define MAX_UUIDS_IN_SEARCH 12 //as per spec
+#define MAX_ATTRS_IN_SEARCH_STRING 8 //as per my opinion
+#define MAX_SEARCH_RESULTS 16 //no more than this will ever be returned
+
+typedef struct SdpService{
+
+ struct SdpService* next;
+
+ uint32_t handle;
+ const uint8_t* descriptor;
+ uint16_t descrLen;
+
+}SdpService;
+
+typedef struct{
+
+ uint16_t aclConn;
+ uint16_t remChan;
+
+ uint32_t contDescr; //which continuation descriptor we expect
+ uint8_t* result;
+ uint32_t resultSz;
+ uint16_t numMatches; //for servicesearch
+
+}SdpInstance;
+
+
+static SdpService* knownServices = NULL;
+static uint32_t sdpContVal = 0x12345678;
+static uint32_t sdpNextHandle = 0;
+
+static const uint8_t sdpDescrSdp[] =
+{
+ //define the SDP service itself
+ //service class ID list
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x01, SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 3,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x10, 0x00, // ServiceDiscoveryServerServiceClassID
+ //ProtocolDescriptorList
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x04, SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 8,
+ SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 6,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x01, 0x00, // L2CAP
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), L2CAP_PSM_SDP >> 8, L2CAP_PSM_SDP & 0xFF, // L2CAP PSM
+
+ //browse group list
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x05, SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 3,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x10, 0x02, // Public Browse Group
+
+ //magic data #1
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0xDD, 0xDD, SDP_ITEM_DESC(SDP_TYPE_TEXT, SDP_SZ_u8), 19, 0x53, 0x57, 0x3A, 0x20, 0x44, 0x6D, 0x69, 0x74, 0x72, 0x79, 0x20, 0x47, 0x72, 0x69, 0x6e, 0x62, 0x65, 0x72, 0x67,
+ //magic data #2
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0xDD, 0xDE, SDP_ITEM_DESC(SDP_TYPE_TEXT, SDP_SZ_u8), 19, 0x48, 0x57, 0x3A, 0x20, 0x45, 0x72, 0x69, 0x63, 0x20, 0x53, 0x63, 0x68, 0x6c, 0x61, 0x65, 0x70, 0x66, 0x65, 0x72
+};
+
+static const uuid bt_base_uuid = {0x0000000000001000ULL, 0x800000805F9B34FBULL};
+
+static void sdpIntToUUID(uuid* dst, uint32_t val){
+
+ *dst = bt_base_uuid;
+ dst->hi += ((uint64_t)val) << 32;
+}
+
+static char sdpUuidEqual(const uuid* a, const uuid* b){
+
+ return a->lo == b->lo && a->hi == b->hi;
+}
+
+static uint32_t btSdpGetElemSz(const uint8_t** descr){
+
+ const uint8_t* ptr = *descr;
+ uint8_t item = *ptr++;
+ uint32_t sz = 0;
+
+ if((item >> 3) != SDP_TYPE_NIL){
+
+ switch(item & 7){
+
+ case SDP_SZ_1:
+ case SDP_SZ_2:
+ case SDP_SZ_4:
+ case SDP_SZ_8:
+ case SDP_SZ_16:
+
+ sz = 1 << (item & 7);
+ break;
+
+ case SDP_SZ_u8:
+
+ sz = *ptr++;
+ break;
+
+ case SDP_SZ_u16:
+
+ sz = ptr[0];
+ sz = (sz << 8) | ptr[1];
+ ptr += 2;
+ break;
+
+ case SDP_SZ_u32:
+
+ sz = ptr[0];
+ sz = (sz << 8) | ptr[1];
+ sz = (sz << 8) | ptr[2];
+ sz = (sz << 8) | ptr[3];
+ ptr += 4;
+ break;
+ }
+ }
+ *descr = ptr;
+ return sz;
+}
+
+static uint8_t btSdpGetUUID(const uint8_t** descr, uuid* dst){ //return num bytes consumed
+
+ uint32_t sz, i;
+ const uint8_t* orig = *descr;
+
+ if(((**descr) >> 3) != SDP_TYPE_UUID) return 0; //not valid UUID type
+ sz = btSdpGetElemSz(descr);
+
+ switch(sz){
+
+ case 2:
+
+ sdpIntToUUID(dst, (((uint32_t)((*descr)[0])) << 8) | ((*descr)[1]));
+ break;
+
+ case 4:
+
+ sdpIntToUUID(dst, (((uint32_t)((*descr)[0])) << 24) | (((uint32_t)((*descr)[1])) << 16) | (((uint32_t)((*descr)[2])) << 8) | ((*descr)[3]));
+ break;
+
+ case 16:
+
+ dst->lo = 0;
+ dst->hi = 0;
+
+ for(i = 0; i < 8; i++){
+
+ dst->lo = (dst->lo << 8) | (*descr)[i];
+ dst->hi = (dst->lo << 8) | (*descr)[i + 8];
+ }
+ break;
+
+ default:
+
+ return 0;
+ }
+ *descr += sz;
+
+ return (*descr) - orig;
+}
+
+static void btStdRecursiveWalk(void* itemList, uint8_t* listSzP, sg_buf** walkResultP, const uint8_t** ptr, uint32_t len){
+
+ uint32_t sz;
+ uint8_t typ, numWantedIDs;
+ const uint8_t* end = (*ptr) + len;
+ uuid id;
+ sg_buf* result = NULL;
+ char isID = 1, skipNext = 0;
+ uuid* wantedIDs;
+ uint8_t* numWantedIDsP;
+ uint32_t* wantedRanges;
+ uint8_t wantedRangesListSz;
+
+
+ if(walkResultP){ //copy-traversal
+
+ result = sg_alloc();
+ if(!result) return;
+
+ wantedIDs = NULL;
+ numWantedIDsP = NULL;
+ wantedRanges = itemList;
+ wantedRangesListSz = *listSzP;
+ }
+ else{ //search for UUIDs
+
+ wantedIDs = itemList;
+ numWantedIDsP = listSzP;
+ numWantedIDs = *numWantedIDsP;
+ wantedRanges = NULL;
+ wantedRangesListSz = 0;
+ }
+
+ while((*ptr) < end){
+
+ typ = (**ptr) >> 3;
+
+ if(wantedIDs && typ == SDP_TYPE_UUID){
+
+ sz = btSdpGetUUID(ptr, &id);
+ if(end < (*ptr)){
+
+ dbgPrintf("SDP: UUID size > allowed size (%d, %d)\n", sz, end - (*ptr));
+ goto out;
+ }
+
+ for(sz = 0; sz < numWantedIDs; sz++){
+
+ if(sdpUuidEqual(wantedIDs + sz, &id)){
+
+ wantedIDs[sz] = wantedIDs[numWantedIDs - 1];
+ numWantedIDs--;
+ sz--;
+ }
+ }
+ }
+ else{
+
+ const uint8_t* itemStart = *ptr;
+
+ sz = btSdpGetElemSz(ptr);
+
+ if(sz > (unsigned)(end - (*ptr))){
+
+ dbgPrintf("SDP: element size > allowed size (%d, %d)\n", sz, end - (*ptr));
+ goto out;
+ }
+
+ if(typ == SDP_TYPE_ARRAY || typ == SDP_TYPE_OR_LIST){
+
+ btStdRecursiveWalk(wantedIDs, &numWantedIDs, NULL, ptr, sz);
+ }
+ else{
+
+ (*ptr) += sz;
+ }
+ if(walkResultP){
+
+ if(isID){
+
+ uint16_t attrID;
+ uint8_t i;
+
+ if(sz != 2) dbgPrintf("SDP: attrib ID not 16 bits!\n");
+
+ attrID = (*ptr)[-2];
+ attrID = (attrID << 8) | (*ptr)[-1];
+
+ skipNext = 2;
+ for(i = 0; i < wantedRangesListSz && skipNext; i++){
+
+ if(attrID >= (wantedRanges[i] >> 16) && attrID <= (wantedRanges[i] & 0xFFFF)) skipNext = 0; //in range
+ }
+ }
+ isID ^= 1;
+
+ if(skipNext){
+
+ skipNext--;
+ }
+ else{
+
+ if(!sg_add_back(result, itemStart, (*ptr) - itemStart, SG_FLAG_MAKE_A_COPY)){
+
+ sg_free(result);
+ return;
+ }
+ }
+ }
+ }
+ }
+
+out:
+ if(walkResultP) *walkResultP = result;
+ if(numWantedIDsP) *numWantedIDsP = numWantedIDs;
+}
+
+static char btSdpPutIntoGroup(sg_buf* buf){
+
+ uint8_t i, sizeFieldSz, sizeFieldName;
+ uint32_t sz = sg_length(buf);
+ uint8_t res[5];
+
+ //figure out needed header size field
+ if(sz < 0x100){
+
+ sizeFieldSz = 1;
+ sizeFieldName = SDP_SZ_u8;
+ sz <<= 24;
+ }
+ else if(sz < 0x10000){
+
+ sizeFieldSz = 2;
+ sizeFieldName = SDP_SZ_u16;
+ sz <<= 16;
+ }
+ else{
+
+ sizeFieldSz = 4;
+ sizeFieldName = SDP_SZ_u32;
+ }
+
+ //add the header
+ res[0] = SDP_ITEM_DESC(SDP_TYPE_ARRAY, sizeFieldName);
+ for(i = 0; i < sizeFieldSz; i++, sz <<= 8) res[1 + i] = sz >> 24;
+ return sg_add_front(buf, res, 1 + sizeFieldSz, SG_FLAG_MAKE_A_COPY);
+}
+
+static sg_buf* btSdpError(const uint8_t* trans, uint16_t errNum){
+
+ sg_buf* buf;
+ uint8_t data[] = {SDP_PDU_Error_Response, trans[0], trans[1], errNum >> 8, errNum, 0, 0};
+
+ buf = sg_alloc();
+ if(buf){
+
+ if(!sg_add_front(buf, data, sizeof(data), SG_FLAG_MAKE_A_COPY)){
+
+ sg_free(buf);
+ buf = NULL;
+ }
+ }
+ return NULL;
+}
+
+static sg_buf* btSdpProcessRequest(SdpInstance* inst, const uint8_t* req, uint16_t reqSz){
+ uint8_t trans[2] ,cmd, contStateSz, numIDs = 0, numAttrs = 0;
+ uint32_t maxReplSz = 0, wantedHandle = 0, sz;
+ uint32_t attrs[MAX_ATTRS_IN_SEARCH_STRING];
+ SdpService* results[MAX_SEARCH_RESULTS];
+ uuid ids[MAX_UUIDS_IN_SEARCH];
+ const uint8_t* end;
+ sg_buf* result;
+ unsigned i, j;
+
+ cmd = *req++;
+ trans[0] = *req++;
+ trans[1] = *req++;
+
+ reqSz -= 5;
+ if(reqSz != (((uint16_t)req[0]) << 8) + req[1]) return btSdpError(trans, SDP_ERR_Invalid_PDU_Size);
+ req += 2;
+
+ //dbgPrintf("SDP request cmd %d (session %02X%02X) with %d bytes of data\n", cmd, trans[0], trans[1], reqSz);
+
+ if(cmd == SDP_PDU_Service_Search_Request || cmd == SDP_PDU_Service_Search_Attribute_Request){
+
+ if((*req) >> 3 != SDP_TYPE_ARRAY) return btSdpError(trans, SDP_ERR_Invalid_Request_Syntax);
+ sz = btSdpGetElemSz(&req);
+ end = req + sz;
+
+ while(req < end){
+
+ if(numIDs == MAX_UUIDS_IN_SEARCH) return btSdpError(trans, SDP_ERR_Invalid_Request_Syntax); //too many requests
+ if(!btSdpGetUUID(&req, &ids[numIDs++])) return btSdpError(trans, SDP_ERR_Invalid_Request_Syntax); //malformed UUID
+ }
+ }
+ else if(cmd == SDP_PDU_Service_Attribute_Request){
+
+ for(i = 0; i < 4; i++) wantedHandle = (wantedHandle << 8) | *req++;
+ }
+ else{
+
+ dbgPrintf("SDP: invalid request: %d\n", cmd);
+ return btSdpError(trans, SDP_ERR_Invalid_Request_Syntax);
+ }
+
+ for(i = 0; i < 2; i++) maxReplSz = (maxReplSz << 8) | *req++;
+
+ if(cmd == SDP_PDU_Service_Attribute_Request || cmd == SDP_PDU_Service_Search_Attribute_Request){
+
+ if((*req) >> 3 != SDP_TYPE_ARRAY) return btSdpError(trans, SDP_ERR_Invalid_Request_Syntax);
+ sz = btSdpGetElemSz(&req);
+ end = req + sz;
+
+ while(req < end){
+
+ if(numAttrs == MAX_UUIDS_IN_SEARCH) return btSdpError(trans, SDP_ERR_Insufficient_Resources); //too many -> unsupported request -> fail
+ sz = btSdpGetElemSz(&req);
+ if(sz == 2){
+
+ sz = 0;
+ for(i =0; i < 2; i++) sz = (sz << 8) | *req++;
+ sz |= sz << 16;
+ }
+ else if(sz == 4){
+
+ sz = 0;
+ for(i =0; i < 4; i++) sz = (sz << 8) | *req++;
+ }
+ else return btSdpError(trans, SDP_ERR_Invalid_Request_Syntax); //fail -> invalid number format
+ attrs[numAttrs++] = sz;
+ }
+ }
+
+ contStateSz = *req++;
+
+ if(contStateSz){ // verify continuation is valid or fail
+ uint32_t contState = 0;
+
+ if(contStateSz != sizeof(uint32_t)) return btSdpError(trans, SDP_ERR_Invalid_Continuation_State);
+ for(i = 0; i < 4; i++) contState = (contState << 8) | *req++;
+
+ if(contState != inst->contDescr || !inst->result){
+
+ dbgPrintf("SDP: invalid continuation state. Wanted %08X, got %08X\n", inst->contDescr, contState);
+ if(inst->result){
+
+ free(inst->result);
+ inst->result = NULL;
+ }
+ return btSdpError(trans, SDP_ERR_Invalid_Continuation_State);
+ }
+ }
+ else{ //perform the actual search
+
+ SdpService* curSvc = knownServices;
+ uint8_t numFound = 0;
+
+ //cleanup first
+ if(inst->result){
+
+ free(inst->result);
+ inst->result = NULL;
+ }
+
+ //perform the search
+ if(cmd == SDP_PDU_Service_Search_Request || cmd == SDP_PDU_Service_Search_Attribute_Request){
+
+ for(curSvc = knownServices; curSvc && numFound < MAX_SEARCH_RESULTS; curSvc = curSvc->next){
+
+ const uint8_t* ptr = curSvc->descriptor;
+ uuid uuids_copy[MAX_UUIDS_IN_SEARCH];
+ uint8_t num;
+
+ for(num = 0; num < numIDs; num++) uuids_copy[num] = ids[num];
+
+ btStdRecursiveWalk(uuids_copy, &num, NULL, &ptr, curSvc->descrLen);
+ if(!num) results[numFound++] = curSvc;
+ }
+ }
+ else if(cmd == SDP_PDU_Service_Attribute_Request){
+
+ for(curSvc = knownServices; curSvc && !numFound; curSvc = curSvc->next){
+
+ if(curSvc->handle == wantedHandle) results[numFound++] = curSvc;
+ }
+ if(!numFound) return btSdpError(trans, SDP_ERR_Invalid_Service_Record_Handle);
+ }
+
+ //gather & prepare results
+ if(cmd == SDP_PDU_Service_Attribute_Request || cmd == SDP_PDU_Service_Search_Attribute_Request){
+
+ //we'll assemble the whole result in this buffer
+ sg_buf* resultSoFar = sg_alloc();
+ if(!resultSoFar) return btSdpError(trans, SDP_ERR_Insufficient_Resources);
+
+ //process each match
+ for(i = 0; i < numFound; i++){
+
+ const uint8_t* ptr = results[i]->descriptor;
+ sg_buf* res;
+
+ //collect wanted attributes
+ btStdRecursiveWalk(attrs, &numAttrs, &res, &ptr, results[i]->descrLen);
+ if(!res) continue;
+
+ //if requested, add the handle attribute
+ for(j = 0; j < numAttrs; j++) if(SDP_ATTR_HANDLE >= (attrs[j] >> 16) && SDP_ATTR_HANDLE <= (attrs[j] & 0xFFFF)) break;
+ if(j != numAttrs){
+ uint8_t buf[8] = {SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x00, SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_4)};
+
+ buf[4] = results[i]->handle >> 24;
+ buf[5] = results[i]->handle >> 16;
+ buf[6] = results[i]->handle >> 8;
+ buf[7] = results[i]->handle;
+
+ if(!sg_add_back(res, buf, sizeof(buf), SG_FLAG_MAKE_A_COPY)){
+
+ sg_free(res);
+ free(res);
+ continue;
+ }
+ }
+
+ //wrap and append to the full results list
+ if(btSdpPutIntoGroup(res)) sg_concat_back(resultSoFar, res);
+ sg_free(res);
+ free(res);
+ }
+
+ //wrap the whole thing if required
+ if((cmd == SDP_PDU_Service_Search_Attribute_Request) && !btSdpPutIntoGroup(resultSoFar)){
+ dbgPrintf("SDP: Failed to put results into a group\n");
+ sg_free(resultSoFar);
+ free(resultSoFar);
+ return btSdpError(trans, SDP_ERR_Insufficient_Resources);
+ }
+
+ //flatten to a buffer
+ uint8_t* buf = malloc(sg_length(resultSoFar));
+ if(!buf){
+
+ dbgPrintf("SDP: Failed to allocate flattened result array (%ub)\n", sg_length(resultSoFar));
+ sg_free(resultSoFar);
+ free(resultSoFar);
+ return btSdpError(trans, SDP_ERR_Insufficient_Resources);
+ }
+ inst->resultSz = sg_length(resultSoFar);
+ inst->result = buf;
+ inst->contDescr = sdpContVal;
+ sg_copyto(resultSoFar, buf);
+ sg_free(resultSoFar);
+ free(resultSoFar);
+ }
+ else if(cmd == SDP_PDU_Service_Search_Request){
+
+ //allocate the array
+ inst->resultSz = sizeof(uint32_t[numFound]);
+ uint8_t* buf = malloc(inst->resultSz);
+
+ if(!buf){
+
+ dbgPrintf("SDP: Failed to allocate flattened result array (%ub)\n", sizeof(uint32_t[numFound]));
+ return btSdpError(trans, SDP_ERR_Insufficient_Resources);
+ }
+
+ //process each match
+ for(i = 0; i < numFound; i++){
+
+ buf[i * 4 + 0] = results[i]->handle >> 24;
+ buf[i * 4 + 1] = results[i]->handle >> 16;
+ buf[i * 4 + 2] = results[i]->handle >> 8;
+ buf[i * 4 + 3] = results[i]->handle;
+ }
+
+ //put everything in the right place
+ inst->result = buf;
+ inst->contDescr = sdpContVal;
+ inst->numMatches = numFound;
+ }
+ }
+ if(++sdpContVal == 0) sdpContVal = 0x01234567; //update continuation state to the next value
+
+ //produce the packet to send
+ uint8_t bufPrepend[9], bufPostpend[5] = {0, }, preSz = 5, postSz = 1;
+ uint32_t sendSz = 0;
+ result = sg_alloc();
+ if(!result) return btSdpError(trans, SDP_ERR_Insufficient_Resources);
+
+ if(cmd == SDP_PDU_Service_Attribute_Request || cmd == SDP_PDU_Service_Search_Attribute_Request){
+
+ if(maxReplSz > 256) maxReplSz = 256; //no harm in fragmenting - keep the packets small
+
+ sendSz = inst->resultSz;
+ if(sendSz > maxReplSz) sendSz = maxReplSz;
+
+ bufPrepend[preSz++] = sendSz >> 8;
+ bufPrepend[preSz++] = sendSz & 0xFF;
+ }
+ else if(cmd == SDP_PDU_Service_Search_Request){
+
+ if(maxReplSz > 64) maxReplSz = 64; //no harm in fragmenting - keep the packets small
+
+ sendSz = inst->resultSz;
+ if(sendSz > maxReplSz * sizeof(uint32_t)) sendSz = maxReplSz * sizeof(uint32_t);
+
+ bufPrepend[preSz++] = inst->numMatches >> 8;
+ bufPrepend[preSz++] = inst->numMatches & 0xFF;
+ bufPrepend[preSz++] = (sendSz / sizeof(uint32_t)) >> 8;
+ bufPrepend[preSz++] = (sendSz / sizeof(uint32_t)) & 0xFF;
+ }
+
+ if(!sg_add_back(result, inst->result, sendSz, SG_FLAG_MAKE_A_COPY)){
+
+ dbgPrintf("SDP: Failed to attach reply. Droping");
+ free(inst->result);
+ inst->result = NULL;
+ sg_free(result);
+ free(result);
+ return btSdpError(trans, SDP_ERR_Insufficient_Resources);
+ }
+ else{
+
+ inst->resultSz -= sendSz;
+ if(inst->resultSz){
+
+ memcpy(inst->result, inst->result + sendSz, inst->resultSz);
+ inst->result = realloc(inst->result, inst->resultSz);
+ }
+ else{
+ free(inst->result);
+ inst->result = NULL;
+ }
+ }
+
+ if(inst->result){ //have more
+
+ bufPostpend[0] = 4;
+ for(i = 0; i < 4; i++) bufPostpend[i + 1] = inst->contDescr >> ((3 - i) << 3);
+ postSz = 5;
+ }
+
+ bufPrepend[0] = cmd + 1; //response to this request
+ bufPrepend[1] = trans[0];
+ bufPrepend[2] = trans[1];
+ bufPrepend[3] = (sendSz + preSz + postSz - 5) >> 8;
+ bufPrepend[4] = (sendSz + preSz + postSz - 5) & 0xFF;
+
+ if(sg_add_front(result, bufPrepend, preSz, SG_FLAG_MAKE_A_COPY) && sg_add_back(result, bufPostpend, postSz, SG_FLAG_MAKE_A_COPY)){
+
+ return result;
+ }
+ sg_free(result);
+ free(result);
+ return btSdpError(trans, SDP_ERR_Insufficient_Resources);
+}
+
+static void* sdpServiceAlloc(uint16_t conn, uint16_t chan, uint16_t remChan){
+
+ SdpInstance* inst = malloc(sizeof(SdpInstance));
+ if(inst){
+
+ inst->result = NULL;
+ inst->aclConn = conn;
+ inst->remChan = remChan;
+ }
+ return inst;
+}
+
+static void sdpServiceFree(void* service){
+
+ SdpInstance* inst = (SdpInstance*)service;
+
+ if(inst->result) free(inst->result);
+ free(inst);
+}
+
+static void sdpServiceDataRx(void* service, const uint8_t* data, uint16_t size){
+
+ SdpInstance* inst = (SdpInstance*)service;
+ uint16_t conn = inst->aclConn;
+ uint16_t remChan = inst->remChan;
+
+ sg_buf* reply = btSdpProcessRequest(inst, data, size);
+ if(reply){
+
+/*// -- ugly debugging code --
+ unsigned i;
+ uint8_t buf[256];
+ sg_copyto(reply, buf);
+
+ dbgPrintf("SDP req got (0x%x): ", size);
+ for(i = 0; i < size; i++) dbgPrintf(" %02X", data[i]);
+ dbgPrintf("\n");
+
+ dbgPrintf("SDP reply sent (0x%x): ", sg_length(reply));
+ for(i = 0; i < sg_length(reply); i++) dbgPrintf(" %02X", buf[i]);
+ dbgPrintf("\n");
+*/
+ l2capServiceTx(conn, remChan, reply);
+ }
+}
+
+void btSdpRegisterL2capService(){
+
+ const L2capService sdp = {L2CAP_FLAG_SUPPORT_CONNECTIONS, sdpServiceAlloc, sdpServiceFree, sdpServiceDataRx};
+ if(!l2capServiceRegister(L2CAP_PSM_SDP, &sdp)) dbgPrintf("SDP L2CAP registration failed\n");
+
+ btSdpServiceDescriptorAdd(sdpDescrSdp, sizeof(sdpDescrSdp));
+}
+
+void btSdpServiceDescriptorAdd(const uint8_t* descriptor, uint16_t descrLen){
+
+ SdpService *t, *s = malloc(sizeof(SdpService));
+ if(s){
+
+ s->handle = sdpNextHandle;
+
+ if(sdpNextHandle) sdpNextHandle++;
+ else sdpNextHandle = SDP_FIRST_USER_HANDLE; //first add is special - it adds the SDP service itself
+
+ s->descriptor = descriptor;
+ s->descrLen = descrLen;
+ s->next = NULL;
+
+ t = knownServices; //add at end
+ while(t && t->next) t = t->next;
+ if(t) t->next = s;
+ else knownServices = s;
+ }
+}
+
+void btSdpServiceDescriptorDel(const uint8_t* descriptor){
+
+ SdpService *s = knownServices, *p = NULL;
+
+ while(s && s->descriptor != descriptor){
+
+ p = s;
+ s = s->next;
+ }
+ if(p) p->next = s->next;
+ else knownServices = s->next;
+
+ free(s);
+}
+
+
diff --git a/library/ADK2/btSDP.h b/library/ADK2/btSDP.h
new file mode 100644
index 0000000..15f7dc7
--- /dev/null
+++ b/library/ADK2/btSDP.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef _BT_SDP_H_
+#define _BT_SDP_H_
+
+#include <stdint.h>
+
+//advised reading: https://www.bluetooth.org/Technical/AssignedNumbers/service_discovery.htm
+
+#define SDP_TYPE_NIL 0
+#define SDP_TYPE_UINT 1
+#define SDP_TYPE_SINT 2
+#define SDP_TYPE_UUID 3
+#define SDP_TYPE_TEXT 4
+#define SDP_TYPE_BOOL 5
+#define SDP_TYPE_ARRAY 6 //"data element sequence"
+#define SDP_TYPE_OR_LIST 7 //"data element alternative" - pick one of these
+#define SDP_TYPE_URL 8
+
+#define SDP_SZ_NIL 0
+#define SDP_SZ_1 0
+#define SDP_SZ_2 1
+#define SDP_SZ_4 2
+#define SDP_SZ_8 3
+#define SDP_SZ_16 4
+#define SDP_SZ_u8 5
+#define SDP_SZ_u16 6
+#define SDP_SZ_u32 7
+
+#define SDP_ITEM_DESC(type, sz) (((type << 3) & 0xF8) | (sz & 7))
+
+
+#define SDP_ATTR_HANDLE 0x0000
+#define SDP_ATTR_SVC_CLS_ID_LIST 0x0001
+#define SDP_ATTR_SVC_ID 0x0003
+#define SDP_ATTR_PROTOCOL_DESCR_LIST 0x0004
+#define SDP_ATTR_BROWSE_GRP_LIST 0x0005
+
+#define SDP_FIRST_USER_HANDLE 0x00010000
+
+
+#ifdef ADK_INTERNAL
+
+#include "sgBuf.h"
+
+void btSdpServiceDescriptorAdd(const uint8_t* descriptor, uint16_t descrLen); //a copy will NOT be made
+void btSdpServiceDescriptorDel(const uint8_t* descriptor);
+
+
+void btSdpRegisterL2capService(void);
+
+
+#endif
+#endif
+
+
diff --git a/library/ADK2/capsense.c b/library/ADK2/capsense.c
new file mode 100644
index 0000000..d93f040
--- /dev/null
+++ b/library/ADK2/capsense.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "capsense.h"
+#include "I2C.h"
+#include "dbg.h"
+
+#define I2C_MUX_ADDR 0x70
+#define QT_ADDR 0x1C
+
+#define QT_ID 0x3E
+#define QT_REG_ID 0
+#define QT_REG_SLIDER 5
+#define QT_REG_KEY0 3
+#define QT_REG_KEY1 4
+#define QT_REG_CAL 6
+#define QT_REG_SIG 52
+#define QT_REG_REF 76
+
+#define SLIDER_SENSE_TH 30
+#define ICON_SENSE_TH 18
+#define ICON_SENSE_TH2 19
+#define BUTTON_SENSE_TH 22
+#define BUTTON_SENSE_TH2 15
+#define SLIDER_PS 0x41
+#define ICON_PS 0x42
+#define ICON_PS_NOISY 0x64 /* For extra noisy icon buttons */
+#define BUTTON_PS 0x42
+#define BUTTON_PS_NOISY 0x64
+
+#define AKS_G1 1 << 2 /* Adjacent key suppression groups */
+#define AKS_G2 2 << 2
+#define AKS_G3 3 << 2
+
+const uint8_t capsense1_init_table[45] = { 8, /* Start address = 8 */
+ 1, /* 08 - LP mode = 1 (16ms) */
+ 20, /* 09 - TTD = 20 (3.2s/ref level) */
+ 5, /* 10 - ATD = 5 (0.8s/ref level) */
+ 5, /* 11 - DI = 5 (5 values integrated) */
+ 63, /* 12 - Touch recal = 63 (10s) */
+ 25, /* 13 - Drift hold = 25 (4 seconds) */
+ 0x80, /* 14 - Slider = Enabled, no wheel */
+ 0, /* 15 - Charge time = 0 */
+ SLIDER_SENSE_TH, /* 16 - Detect threshold CH0 */
+ SLIDER_SENSE_TH, /* 17 - Detect threshold CH1 */
+ SLIDER_SENSE_TH, /* 18 - Detect threshold CH2 */
+ ICON_SENSE_TH, /* 19 - Detect threshold CH3 */
+ ICON_SENSE_TH, /* 20 - Detect threshold CH4 */
+ ICON_SENSE_TH, /* 21 - Detect threshold CH5 */
+ ICON_SENSE_TH, /* 22 - Detect threshold CH6 */
+ ICON_SENSE_TH2, /* 23 - Detect threshold CH7 */
+ ICON_SENSE_TH, /* 24 - Detect threshold CH8 */
+ ICON_SENSE_TH, /* 25 - Detect threshold CH9 */
+ ICON_SENSE_TH, /* 26 - Detect threshold CH10 */
+ ICON_SENSE_TH, /* 27 - Detect threshold CH11 */
+ 0, /* 28 - Key control CH0 */
+ 0, /* 29 - Key control CH1 */
+ 0, /* 30 - Key control CH2 */
+ AKS_G1, /* 31 - Key control CH3 */
+ AKS_G1, /* 32 - Key control CH4 */
+ AKS_G1, /* 33 - Key control CH5 */
+ AKS_G1, /* 34 - Key control CH6 */
+ AKS_G1, /* 35 - Key control CH7 */
+ AKS_G1, /* 36 - Key control CH8 */
+ AKS_G1, /* 37 - Key control CH9 */
+ AKS_G1, /* 38 - Key control CH10 */
+ AKS_G1, /* 39 - Key control CH11 */
+ SLIDER_PS, /* 40 - Pulse/Scale CH0 */
+ SLIDER_PS, /* 41 - Pulse/Scale CH1 */
+ SLIDER_PS, /* 42 - Pulse/Scale CH2 */
+ ICON_PS, /* 43 - Pulse/Scale CH3 */
+ ICON_PS_NOISY, /* 44 - Pulse/Scale CH4 */
+ ICON_PS, /* 45 - Pulse/Scale CH5 */
+ ICON_PS, /* 46 - Pulse/Scale CH6 */
+ ICON_PS_NOISY, /* 47 - Pulse/Scale CH7 */
+ ICON_PS_NOISY, /* 48 - Pulse/Scale CH8 */
+ ICON_PS, /* 49 - Pulse/Scale CH9 */
+ ICON_PS, /* 50 - Pulse/Scale CH10 */
+ ICON_PS /* 51 - Pulse/Scale CH11 */ };
+
+const uint8_t capsense2_init_table[45] = { 8, /* Start address = 8 */
+ 1, /* 08 - LP mode = 1 (16ms) */
+ 20, /* 09 - TTD = 20 (3.2s/ref level) */
+ 5, /* 10 - ATD = 5 (0.8s/ref level) */
+ 5, /* 11 - DI = 5 (5 values integrated) */
+ 63, /* 12 - Touch recal = 63 (10s) */
+ 25, /* 13 - Drift hold = 25 (4 seconds) */
+ 0x00, /* 14 - Slider = Disabled, no wheel */
+ 0, /* 15 - Charge time = 0 */
+ BUTTON_SENSE_TH, /* 16 - Detect threshold CH0 */
+ BUTTON_SENSE_TH, /* 17 - Detect threshold CH1 */
+ BUTTON_SENSE_TH, /* 18 - Detect threshold CH2 */
+ BUTTON_SENSE_TH, /* 19 - Detect threshold CH3 */
+ BUTTON_SENSE_TH, /* 20 - Detect threshold CH4 */
+ BUTTON_SENSE_TH, /* 21 - Detect threshold CH5 */
+ BUTTON_SENSE_TH, /* 22 - Detect threshold CH6 */
+ BUTTON_SENSE_TH, /* 23 - Detect threshold CH7 */
+ BUTTON_SENSE_TH, /* 24 - Detect threshold CH8 */
+ BUTTON_SENSE_TH, /* 25 - Detect threshold CH9 */
+ BUTTON_SENSE_TH2,/* 26 - Detect threshold CH10 */
+ BUTTON_SENSE_TH2,/* 27 - Detect threshold CH11 */
+ AKS_G1, /* 28 - Key control CH0 */
+ AKS_G1, /* 29 - Key control CH1 */
+ AKS_G1, /* 30 - Key control CH2 */
+ AKS_G1, /* 31 - Key control CH3 */
+ AKS_G2, /* 32 - Key control CH4 */
+ AKS_G2, /* 33 - Key control CH5 */
+ AKS_G2, /* 34 - Key control CH6 */
+ AKS_G2, /* 35 - Key control CH7 */
+ AKS_G3, /* 36 - Key control CH8 */
+ AKS_G3, /* 37 - Key control CH9 */
+ AKS_G3, /* 38 - Key control CH10 */
+ AKS_G3, /* 39 - Key control CH11 */
+ BUTTON_PS_NOISY, /* 40 - Pulse/Scale CH0 */
+ BUTTON_PS_NOISY, /* 41 - Pulse/Scale CH1 */
+ BUTTON_PS, /* 42 - Pulse/Scale CH2 */
+ BUTTON_PS, /* 43 - Pulse/Scale CH3 */
+ BUTTON_PS, /* 44 - Pulse/Scale CH4 */
+ BUTTON_PS, /* 45 - Pulse/Scale CH5 */
+ BUTTON_PS, /* 46 - Pulse/Scale CH6 */
+ BUTTON_PS, /* 47 - Pulse/Scale CH7 */
+ BUTTON_PS, /* 48 - Pulse/Scale CH8 */
+ BUTTON_PS, /* 49 - Pulse/Scale CH9 */
+ BUTTON_PS, /* 50 - Pulse/Scale CH10 */
+ BUTTON_PS_NOISY /* 51 - Pulse/Scale CH11 */ };
+
+
+void I2C_Mux(uint8_t position)
+{
+ uint8_t reg;
+ switch(position){
+ case 1:
+ reg = 4;
+ break;
+ case 2:
+ reg = 5;
+ break;
+ default:
+ reg = 0;
+ break;
+ }
+ i2cQuick(1, I2C_MUX_ADDR, reg);
+}
+
+char capSenseInit(void)
+{
+ I2C_Mux(1);
+
+ if (QT_ID != i2cSingleRead(1, QT_ADDR, QT_REG_ID))
+ return 0;
+
+ if (I2C_ALL_OK != i2cOp(1, QT_ADDR, capsense1_init_table, sizeof(capsense1_init_table), NULL, 0))
+ return 0;
+
+ i2cSingleWrite(1, QT_ADDR, QT_REG_CAL, 1);
+
+ I2C_Mux(2);
+
+ if (QT_ID != i2cSingleRead(1, QT_ADDR, QT_REG_ID))
+ return 0;
+
+ if (I2C_ALL_OK != i2cOp(1, QT_ADDR, capsense2_init_table, sizeof(capsense2_init_table), NULL, 0))
+ return 0;
+
+ i2cSingleWrite(1, QT_ADDR, QT_REG_CAL, 1);
+
+ return 1;
+}
+
+uint8_t capSenseSlider(void)
+{
+ uint8_t cmd = QT_REG_SLIDER;
+ uint8_t dat;
+ I2C_Mux(1);
+ i2cOp(1, QT_ADDR, &cmd, 1, &dat, 1);
+ //return i2cSingleRead(1, QT_ADDR, QT_REG_SLIDER);
+ return dat;
+}
+
+uint16_t capSenseButtons(void)
+{
+ uint8_t cmd = QT_REG_KEY0;
+ uint8_t dat[2];
+ I2C_Mux(2);
+ i2cOp(1, QT_ADDR, &cmd, 1, dat, sizeof(dat));
+ return dat[0] + ((uint16_t)dat[1] << 8);
+}
+
+uint16_t capSenseIcons(void)
+{
+ uint8_t cmd = QT_REG_KEY0;
+ uint8_t dat[2];
+ I2C_Mux(1);
+ i2cOp(1, QT_ADDR, &cmd, 1, dat, sizeof(dat));
+ return dat[0] + ((uint16_t)dat[1] << 8);
+}
+
+void capSenseDump(void)
+{
+ int i;
+ uint8_t cmd;
+ uint16_t dat[48];
+ I2C_Mux(1);
+ cmd = QT_REG_SIG;
+ i2cOp(1, QT_ADDR, &cmd, 1, (uint8_t *)dat, 48);
+ I2C_Mux(2);
+ i2cOp(1, QT_ADDR, &cmd, 1, (uint8_t *)(&dat[24]), 48);
+
+ for (i = 0; i < 12; i++) {
+ dbgPrintf("%04x %04x ", dat[i], dat[i+12]);
+ }
+ for (i = 0; i < 12; i++) {
+ dbgPrintf("%04x %04x ", dat[i+24], dat[i+24+12]);
+ }
+ dbgPrintf("\n");
+
+}
diff --git a/library/ADK2/capsense.h b/library/ADK2/capsense.h
new file mode 100644
index 0000000..ebc264c
--- /dev/null
+++ b/library/ADK2/capsense.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _CAPSENSE_H_
+#define _CAPSENSE_H_
+
+char capSenseInit(void);
+uint8_t capSenseSlider(void);
+uint16_t capSenseButtons(void);
+uint16_t capSenseIcons(void);
+void capSenseDump(void);
+
+#endif
+#endif
+
diff --git a/library/ADK2/coop.c b/library/ADK2/coop.c
new file mode 100644
index 0000000..951c6bf
--- /dev/null
+++ b/library/ADK2/coop.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "coop.h"
+
+#define NUM_REGS 10 //r4-r11,sp,pc
+
+typedef struct CoopTask{
+
+ uint32_t regs[NUM_REGS];
+ void* stackPtr;
+ struct CoopTask* next;
+ struct CoopTask* prev;
+}CoopTask;
+
+CoopTask* cur = 0;
+
+static CoopTask* __attribute__((noinline)) coopSchedule(char taskDied){
+
+ CoopTask* next = cur->next;
+
+ if(taskDied){ //delete task
+
+ if(next == cur){
+ dbgPrintf("Last task died. Halting.\n");
+ while(1);
+ }
+
+ if(cur->stackPtr) free(cur->stackPtr);
+ cur->next->prev = cur->prev;
+ cur->prev->next = cur->next;
+ free(cur);
+ }
+ cur = next;
+ return next;
+}
+
+
+static void __attribute__((naked)) __attribute__((noinline)) coopTaskStart(void){
+
+ asm(
+ "mov r0, r5;"
+ "blx r4;"
+ "mov r0, #1;"
+ "bl coopSchedule;"
+ "ldmia r0, {r4-r12,lr};"
+ "mov sp, r12;"
+ "bx lr;"
+ );
+}
+
+static void __attribute__((naked)) __attribute__((noinline)) coopDoYield(CoopTask* curTask){
+
+ asm(
+ "mov r12, sp;"
+ "stmia r0, {r4-r12,lr};"
+ "mov r0, #0;"
+ "bl coopSchedule;"
+ "ldmia r0, {r4-r12,lr};"
+ "mov sp, r12;"
+ "bx lr;"
+ );
+}
+
+int coopInit(void){
+
+ CoopTask* task;
+
+ task = malloc(sizeof(CoopTask));
+ if(!task) return 0;
+
+ task->next = task;
+ task->prev = task;
+ task->stackPtr = 0;
+ cur = task;
+
+ return 1;
+}
+
+int coopSpawn(CoopTaskF taskF, void* taskData, uint32_t stackSz){
+
+ uint8_t* stack;
+ CoopTask* task;
+
+ stack = malloc(stackSz);
+ if(!stack) return 0;
+
+ task = malloc(sizeof(CoopTask));
+ if(!task){
+ free(stack);
+ return 0;
+ }
+
+ task->stackPtr = stack;
+ task->regs[0] = (uint32_t)taskF;
+ task->regs[1] = (uint32_t)taskData;
+ task->regs[8] = ((uint32_t)(stack + stackSz)) &~ 7;
+ task->regs[9] = (uint32_t)&coopTaskStart;
+
+ task->prev = cur;
+ task->next = cur->next;
+ cur->next->prev = task;
+ cur->next = task;
+
+ //these are here so compiler is sure that function is referenced in both variants (cancels a warning)
+ if(stackSz == 0xFFFFFFFF) coopSchedule(0);
+ if(stackSz == 0xFFFFFFFE) coopSchedule(1);
+
+ return 1;
+}
+
+void coopYield(void){
+ coopDoYield(cur);
+}
+
+void sleep(uint32_t ms)
+{
+ uint64_t a = fwkGetUptime();
+ while (fwkGetUptime() - a < ms)
+ coopYield();
+}
+
diff --git a/library/ADK2/coop.h b/library/ADK2/coop.h
new file mode 100644
index 0000000..bda73a9
--- /dev/null
+++ b/library/ADK2/coop.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _COOP_H_
+#define _COOP_H_
+
+
+typedef void (*CoopTaskF)(void* ptr);
+
+int coopInit(void); //0 on fail
+int coopSpawn(CoopTaskF task, void* taskData, uint32_t stackSz); //0 on fail
+void coopYield(void);
+
+void sleep(uint32_t ms);
+
+#endif
+#endif
+
diff --git a/library/ADK2/dbg.c b/library/ADK2/dbg.c
new file mode 100644
index 0000000..70eee46
--- /dev/null
+++ b/library/ADK2/dbg.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "dbg.h"
+#include "printf.h"
+#include <stdarg.h>
+
+#define USE_UART 0
+
+
+void (*putcharF)(char) = NULL;
+
+static char writeF(void* unused, char c){
+
+
+ if(c == '\n') if(putcharF) putcharF('\r'); //serial consoles need this
+ if(putcharF) putcharF(c);
+ return 1;
+}
+
+void dbgPrintf(const char* fmt, ...){
+
+ va_list vl;
+
+ va_start(vl, fmt);
+ _cvsprintf(writeF, NULL, fmt, vl);
+ va_end(vl);
+}
+
+void dbgSetPutchar(void (*fn)(char)){
+
+ putcharF = fn;
+}
diff --git a/library/ADK2/dbg.h b/library/ADK2/dbg.h
new file mode 100644
index 0000000..f90b133
--- /dev/null
+++ b/library/ADK2/dbg.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _DBG_H_
+#define _DBG_H_
+
+void dbgPrintf(const char* fmt, ...);
+
+void dbgSetPutchar(void (*fn)(char));
+
+
+#endif
+#endif
+
diff --git a/library/ADK2/eliza.c b/library/ADK2/eliza.c
new file mode 100644
index 0000000..84fa2af
--- /dev/null
+++ b/library/ADK2/eliza.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "btRFCOMM.h"
+#include "btSDP.h"
+#include "btL2CAP.h"
+#include "dbg.h"
+#include <string.h>
+
+
+
+static void elzSetup(void);
+static char* elzTalk(char* Is);
+
+#define MAGIX 0xFA
+
+static uint8_t sdpDescrEliza[] = //we are connectible to on unsecured channel of ADK chat app
+{
+ //service class ID list
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x01, SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 17,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_16), 0x8c, 0xe2, 0x55, 0xc0, 0x20, 0x0a, 0x11, 0xe0, 0xac, 0x64, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66,
+ //ServiceId
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x03, SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x11, 0x01,
+ //ProtocolDescriptorList
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x04, SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 15,
+ SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 6,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x01, 0x00, // L2CAP
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), L2CAP_PSM_RFCOMM >> 8, L2CAP_PSM_RFCOMM & 0xFF, // L2CAP PSM
+ SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 5,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x00, 0x03, // RFCOMM
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_1), MAGIX, // port ###
+ //browse group list
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x05, SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 3,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x10, 0x02, // Public Browse Group
+ //name
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x01, 0x00, SDP_ITEM_DESC(SDP_TYPE_TEXT, SDP_SZ_u8), 5, 'E', 'L', 'I', 'Z', 'A'
+};
+
+
+static void elzPortOpen(void* port, uint8_t dlci){
+
+ dbgPrintf("Remote client joined...\n");
+ elzSetup();
+}
+
+static void elzPortClose(void* port, uint8_t dlci){
+
+ dbgPrintf("Remote client left...\n");
+}
+
+static void elzPortRx(void* port, uint8_t dlci, const uint8_t* data, uint16_t sz){
+
+ char *c, *r;
+
+ while(data[sz - 1] == '\n') sz--;
+
+ c = malloc(sz + 1);
+ if(c){
+
+ memcpy(c, data, sz);
+ c[sz] = 0;
+ r = elzTalk(c);
+ if(r){
+ btRfcommPortTx(port, dlci, r, strlen(r));
+ free(r);
+ return;
+ }
+ }
+ btRfcommPortTx(port, dlci, "OUT OF MEMORY", 13);
+}
+
+void eliza(void){
+
+ uint8_t i, dlci = btRfcommReserveDlci(RFCOMM_DLCI_NEED_EVEN);
+ int f;
+
+ if(!dlci) dbgPrintf("ELIZA: failed to allocate DLCI\n");
+ else{
+
+ //change descriptor to be valid...
+ for(i = 0, f = -1; i < sizeof(sdpDescrEliza); i++){
+
+ if(sdpDescrEliza[i] == MAGIX){
+ if(f == -1) f = i;
+ else break;
+ }
+ }
+
+ if(i != sizeof(sdpDescrEliza) || f == -1){
+
+ dbgPrintf("ELIZA: failed to find a single marker in descriptor\n");
+ btRfcommReleaseDlci(dlci);
+ return;
+ }
+
+ sdpDescrEliza[f] = dlci >> 1;
+
+ btRfcommRegisterPort(dlci, elzPortOpen, elzPortClose, elzPortRx);
+ btSdpServiceDescriptorAdd(sdpDescrEliza, sizeof(sdpDescrEliza));
+ }
+}
+
+
+
+/////////////////utils
+
+char* cat(char* a, char *b){
+
+ char* r = malloc(strlen(a) + strlen(b) + 1);
+
+ strcpy(r, a);
+ strcat(r, b);
+ free(a);
+ free(b);
+ return r;
+}
+
+#define conststr(s) strdup(s)
+#define dup(s) strdup(s)
+
+char streq(char* a, char* b){
+
+ char ret = !strcmp(a,b);
+
+ free(a);
+ free(b);
+
+ return ret;
+}
+
+char* mid(char* str, long start, long len){
+
+ char* r = malloc(len + 1);
+ memcpy(r, str + start, len);
+ r[len] = 0;
+
+ return r;
+}
+
+char* right(char* str, long len){
+
+ if(strlen(str) < len) len = strlen(str);
+
+ return mid(str, strlen(str) - len, len);
+}
+
+
+
+
+
+
+
+
+
+///////////////////////////////////////////////////////////////////////////
+// ORIGINAL: http://www.vintagecomputer.net/commodore/64/TOK64/ELIZA.txt //
+// BASIC TO C PORT: Dmitry Grinberg (dmitrygr@gmail.com) //
+///////////////////////////////////////////////////////////////////////////
+
+
+
+static const char* data0[] =
+{
+ "CAN YOU","CAN I","YOU ARE","YOURE","I DONT","I FEEL",
+ "WHY DONT YOU","WHY CANT I","ARE YOU","I CANT","I AM"," IM ",
+ "YOU","I WANT","WHAT","HOW","WHO","WHERE","WHEN","WHY",
+ "NAME","CAUSE","SORRY","DREAM","HELLO","HI","MAYBE",
+ "NO","YOUR","ALWAYS","THINK","ALIKE","YES","FRIEND",
+ "COMPUTER","NOKEYFOUND"
+};
+
+static const char* data1[] =
+{
+ " ARE "," AM ","WERE ","WAS "," YOU "," I ","YOUR ","MY ",
+ " IVE "," YOUVE "," IM "," YOURE ", " YOU ", " ME "
+};
+
+static const char* data2[] =
+{
+ "DON'T YOU BELIEVE THAT I CAN.","PERHAPS YOU WOULD LIKE TO BE ABLE TO.",
+ "YOU WANT ME TO BE ABLE TO*","PERHAPS YOU DON'T WANT TO*",
+ "DO YOU WANT TO BE ABLE TO*","WHAT MAKES YOU THINK I AM*",
+ "DOES IT PLEASE YOU TO BELIEVE I AM*","PERHAPS YOU WOULD LIKE TO BE*",
+ "DO YOU SOMETIMES WISH YOU WERE*","DON'T YOU REALLY*","WHY DON'T YOU*",
+ "DO YOU WISH TO BE ABLE TO*","DOES THAT TROUBLE YOU?",
+ "TELL ME MORE ABOUT SUCH FEELINGS*","DO YOU OFTEN FEEL*",
+ "DO YOU ENJOY FEELING*","DO YOU REALLY BELIEVE I DON'T*",
+ "PERHAPS IN GD TIME I WILL*","DO YOU WANT ME TO*",
+ "DO YOU THINK YOU SHOULD BE ABLE TO*","WHY CAN'T YOU*",
+ "WHY ARE YOU INTERESTED IN WHETHER OR NOT I AM*",
+ "WOULD YOU PREFER IF I WERE NOT*","PERHAPS IN YOUR FANTASIES I AM*",
+ "HOW DO YOU KNOW YOU CAN'T*","HAVE YOU TRIED?","PERHAPS YOU CAN NOW*",
+ "DID YOU COME TO ME BECAUSE YOU ARE*","HOW LONG HAVE YOU BEEN*",
+ "DO YOU BELIEVE IT IS NORMAL TO BE*","DO YOU ENJOY BEING*",
+ "WE WERE DISCUSSING YOU-- NOT ME.","OH, I*",
+ "YOU'RE NOT REALLY TALKING ABOUT ME. ARE YOU?",
+ "WHAT WOULD IT MEAN TO YOU IF YOU GOT*","WHY DO YOU WANT*",
+ "SUPPOSE YOU SOON GOT*","WHAT IF YOU NEVER GOT*","I SOMETIMES ALSO WANT*",
+ "WHY DO YOU ASK?","DOES THAT QUESTION INTEREST YOU?",
+ "WHAT ANSWER WOULD PLEASE YOU THE MOST?","WHAT DO YOU THINK?",
+ "ARE SUCH QUESTIONS ON YOUR MIND OFTEN?",
+ "WHAT IS IT THAT YOU REALLY WANT TO KNOW?","HAVE YOU ASKED ANYONE ELSE?",
+ "HAVE YOU ASKED SUCH QUESTIONS BEFORE?",
+ "WHAT ELSE COMES TO MIND WHEN YOU ASK THAT?","NAMES DON'T INTEREST ME.",
+ "I DON'T CARE ABOUT NAMES-- PLEASE GO ON.","IS THAT THE REAL REASON?",
+ "DON'T ANY OTHER REASONS COME TO MIND?",
+ "DOES THAT REASON EXPLAIN ANYTHING ELSE?","WHAT OTHER REASONS MIGHT THERE BE?",
+ "PLEASE DON'T APOLOGIZE.","APOLOGIES ARE NOT NECESSARY.",
+ "WHAT FEELINGS DO YOU HAVE WHEN YOU APOLOGIZE.","DON'T BE SO DEFENSIVE!",
+ "WHAT DOES THAT DREAM SUGGEST TO YOU?","DO YOU DREAM OFTEN?",
+ "WHAT PERSONS APPEAR IN YOUR DREAMS?","ARE YOU DISTURBED BY YOUR DREAMS?",
+ "HOW DO YOU DO .,. PLEASE STATE YOUR PROBLEM.","YOU DON'T SEEM QUITE CERTAIN.",
+ "WHY THE UNCERTAIN TONE?","CAN'T YOU BE MORE POSITIVE?","YOU AREN'T SURE?",
+ "DON'T YOU KNOW?","ARE YOU SAYING NO JUST TO BE NEGATIVE?",
+ "YOU ARE BEING A BIT NEGATIVE.","WHY NOT?","ARE YOU SURE?","WHY NO?",
+ "WHY ARE YOU CONCERNED ABOUT MY*","WHAT ABOUT YOUR OWN*",
+ "CAN'T YOU THINK OF A SPECIFIC EXAMPLE?","WHEN?","WHAT ARE YOU THINKING OF?",
+ "REALLY. ALWAYS?","DO YOU REALLY THINK SO?","BUT YOU ARE NOT SURE YOU.",
+ "DO YOU DOUBT YOU.","IN WHAT WAY?","WHAT RESEMBLANCE DO YOU SEE?",
+ "WHAT DOES THE SIMILARITY SUGGEST TO YOU?",
+ "WHAT OTHER CONNECTIONS DO YOU SEE?","COULD THERE REALLY BE SOME CONNECTION?",
+ "HOW?","YOU SEEM QUITE POSITIVE.","ARE YOU SURE?","I SEE.","I UNDERSTAND.",
+ "WHY DO YOU BRING UP THE TOPIC OF FRIENDS?","DO YOUR FRIENDS WORRY YOU?",
+ "DO YOUR FRIENDS PICK ON YOU?","ARE YOU SURE YOU HAVE ANY FRIENDS?",
+ "DO YOU IMPOSE ON YOUR FRIENDS?","PERHAPS YOUR LOVE FOR FRIENDS WORRIES YOU.",
+ "DO COMPUTERS WORRY YOU?","ARE YOU TALKING ABOUT ME IN PARTICULAR?",
+ "ARE YOU FRIGHTENED BY MACHINES?","WHY DO YOU MENTION COMPUTERS?",
+ "WHAT DO YOU THINK MACHINES HAVE TO DO WITH YOUR PROBLEM?",
+ "DON'T YOU THINK COMPUTERS CAN HELP PEOPLE?",
+ "WHAT IS IT ABOUT MACHINES THAT WORRIES YOU?",
+ "SAY, DO YOU HAVE ANY PSYCHOLOGICAL PROBLEMS?",
+ "WHAT DOES THAT SUGGEST TO YOU?","I SEE.",
+ "I'M NOT SURE I UNDERSTAND YOU FULLY.","COME COME ELUCIDATE YOUR THOUGHTS.",
+ "CAN YOU ELABORATE ON THAT?","THAT IS QUITE INTERESTING."
+};
+
+static const char data3[] =
+{
+ 1,3,4,2,6,4,6,4,10,4,14,3,17,3,20,2,22,3,25,3,
+ 28,4,28,4,32,3,35,5,40,9,40,9,40,9,40,9,40,9,40,9,
+ 49,2,51,4,55,4,59,4,63,1,63,1,64,5,69,5,74,2,76,4,
+ 80,3,83,7,90,3,93,6,99,7,106,6
+};
+
+
+char S[36], R[36], N[36];
+const char N1 = 36, N2 = 14, N3 = 112;
+char* Ps = NULL;
+
+static void elzSetup(void){
+
+ char X;
+ const char* ptr = data3;
+
+ for(X = 0; X < N1; X++){
+
+ R[X] = S[X] = *ptr++;
+ N[X] = S[X] - 1 + *ptr++;
+ }
+}
+
+static char* elzTalk(char* Is){
+
+ const char *Fs;
+ char *Cs = NULL;
+ char result[128] = {0};
+ int X, Si, K, L, T;
+
+ //-----USER INPUT SECTION-----
+ // * UPCASE
+ // * GET RID OF APOSTROPHES
+ // * ADD SPACES IN FRONT AND BACK
+ {
+ char _c, *_s, *_t;
+
+ _s = malloc(strlen(Is) + 3);
+ _t = Is;
+ X = 0;
+ _s[X++] = ' ';
+
+ while((_c = *_t++)){
+
+ if(_c >= 'a' && _c <= 'z') _c += 'A' - 'a';
+ if(_c == '\'') continue;
+ _s[X++] = _c;
+ }
+ _s[X++] = ' ';
+ _s[X] = 0;
+ free(Is);
+ Is = _s;
+
+ if(strstr(Is, "SHUT")) strcat(result, "SHUT UP...\n");
+
+ if(Ps && !strcmp(Is, Ps)){
+
+ strcat(result, "PLEASE DON'T REPEAT YOURSELF!\n");
+ goto out;
+ }
+ }
+
+ //-----FIND KEYWORD IN I$-----
+ {
+
+ const char* Ks;
+ const char* _s;
+
+ Si = -1;
+ for(K = 0; K < N1; K++){
+ if(Si >= 0) continue;
+ for(L = 0; L <= (signed)strlen(Is) - (signed)strlen(data0[K]); L++){
+
+ if(!memcmp(Is + L, data0[K], strlen(data0[K]))){
+
+ Si = K;
+ T = L;
+ Fs = data0[K];
+ }
+ }
+ }
+
+ if(Si < 0) K = 35;//WE DIDN'T FIND ANY KEYWORDS
+ else{
+
+ const char *Rs, *Ss;
+
+ K = Si;
+ L = T;
+
+ //TAKE RIGHT PART OF STRING AND CONJUGATE IT
+ //USING THE LIST OF STRINGS TO BE SWAPPED
+
+ Cs = malloc(strlen(Is) - strlen(Fs) - L + 3);
+ sprintf(Cs, " %s", Is + L + strlen(Fs)); //maybe + 1
+ if(Ps) free(Ps);
+ Ps = Is;
+ Is = NULL;
+
+ for(X = 0; X < N2 / 2; X++){
+
+ Ss = data1[X * 2 + 0];
+ Rs = data1[X * 2 + 1];
+
+ for(L = 0; L < strlen(Cs); L++){
+
+ char _i;
+ const char* _f = Ss;
+ const char* _r = Rs;
+
+ for(_i = 0; _i < 2; _i++){
+
+ if(!memcmp(Cs + L, _f, strlen(_f))){
+ Is = malloc(strlen(Cs) - strlen(_f) + strlen(_r) + 1);
+
+ memmove(Is, Cs, L);
+ strcpy(Is + L, _r);
+ strcat(Is, Cs + L + strlen(_f));
+ free(Cs);
+ Cs = Is;
+ Is = NULL;
+
+ L += strlen(_r);
+ break;
+ }
+ _f = Rs;
+ _r = Ss;
+ }
+ }
+ }
+
+ if(Cs[0] == ' ' && Cs[1] == ' ') memmove(Cs, Cs + 1, strlen(Cs)); //ONLY 1 SPACE
+ }
+ }
+
+ //NOW USING THE KEYWORD NUMBER (K) GET REPLY
+ {
+
+ //READ RIGHT REPLY
+ Fs = data2[R[K] - 1];
+ R[K]++;
+ if(R[K] > N[K]) R[K] = S[K];
+
+ strcat(result, Fs);
+ if(result[strlen(result) - 1] == '*'){
+
+ result[strlen(result) - 1] = 0;
+ strcat(result, Cs);
+ }
+ }
+ if(Cs) free(Cs);
+
+out:
+ if(Is) free(Is);
+ return strdup(result);
+}
+
+
+
diff --git a/library/ADK2/examples/BluetoothScan/BluetoothScan.pde b/library/ADK2/examples/BluetoothScan/BluetoothScan.pde
new file mode 100644
index 0000000..f950aaf
--- /dev/null
+++ b/library/ADK2/examples/BluetoothScan/BluetoothScan.pde
@@ -0,0 +1,280 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <ADK.h>
+#include <HCI.h>
+
+
+ADK L;
+
+extern "C"{
+ void dbgPrintf(const char* fmt,...); //arduino print sucks...
+ void* malloc(unsigned sz); //who the hell programs BT without these?
+ void free(void*); //who the hell programs BT without these?
+}
+
+
+
+void adkPutchar(char c){
+ Serial.write(c);
+}
+
+void setup(void)
+{
+
+ Serial.begin(115200);
+
+ L.adkSetPutchar(adkPutchar);
+ L.adkInit();
+}
+
+typedef struct BTD{
+
+ struct BTD* next;
+ uint8_t mac[BLUETOOTH_MAC_SIZE];
+ uint8_t PSRM;
+ uint8_t PSPM;
+ uint8_t PSM;
+ uint16_t CO;
+ uint32_t dc;
+
+}BTD;
+
+BTD* devs;
+
+char adkBtDiscoveryResult(const uint8_t* mac, uint8_t PSRM, uint8_t PSPM, uint8_t PSM, uint16_t CO, uint32_t devClass){ //return 0 to stop scan immediately
+
+ int i;
+ static int nres = 0;
+
+ dbgPrintf("%d results so far...\n", ++nres);
+
+ BTD* btd = devs;
+ while(btd){
+
+ if(btd->mac[0] == mac[0] && btd->mac[1] == mac[1] && btd->mac[2] == mac[2] &&
+ btd->mac[3] == mac[3] && btd->mac[4] == mac[4] && btd->mac[5] == mac[5]) return 1;
+ btd = btd->next;
+ }
+
+ btd = (BTD*)malloc(sizeof(BTD));
+ if(!btd) return 0;
+
+ for(i = 0; i < BLUETOOTH_MAC_SIZE; i++) btd->mac[i] = mac[i];
+ btd->PSRM = PSRM;
+ btd->PSPM = PSPM;
+ btd->PSM = PSM;
+ btd->CO = CO;
+ btd->dc = devClass;
+ btd->next = devs;
+ devs = btd;
+ return 1;
+}
+
+void doScan(){
+
+ devs = NULL;
+
+ dbgPrintf("BT Scan...\n");
+ L.btScan();
+ dbgPrintf("\n");
+
+ BTD* dev = devs;
+
+ while(dev){
+
+ dbgPrintf("%02X:%02X:%02X:%02X:%02X:%02X - ", dev->mac[5], dev->mac[4], dev->mac[3], dev->mac[2], dev->mac[1], dev->mac[0]);
+ dbgPrintf("{%d,%d,%d} 0x%06X %6d - ", dev->PSRM, dev->PSPM, dev->PSM, dev->dc, dev->CO);
+
+ switch((dev->dc & DEVICE_CLASS_MAJOR_MASK) >> DEVICE_CLASS_MAJOR_SHIFT){
+
+ case DEVICE_CLASS_MAJOR_MISC:
+ dbgPrintf("MISC");
+ break;
+
+ case DEVICE_CLASS_MAJOR_COMPUTER:
+ dbgPrintf("Computer - ");
+
+ switch((dev->dc & DEVICE_CLASS_MINOR_COMPUTER_MASK) >> DEVICE_CLASS_MINOR_COMPUTER_SHIFT){
+
+ case DEVICE_CLASS_MINOR_COMPUTER_UNCATEG:
+ dbgPrintf("uncategorized");
+ break;
+ case DEVICE_CLASS_MINOR_COMPUTER_DESKTOP:
+ dbgPrintf("desktop");
+ break;
+ case DEVICE_CLASS_MINOR_COMPUTER_SERVER:
+ dbgPrintf("server");
+ break;
+ case DEVICE_CLASS_MINOR_COMPUTER_LAPTOP:
+ dbgPrintf("laptop");
+ break;
+ case DEVICE_CLASS_MINOR_COMPUTER_CLAM_PDA:
+ dbgPrintf("clamsghell PDA");
+ break;
+ case DEVICE_CLASS_MINOR_COMPUTER_PALM_PDA:
+ dbgPrintf("Palm PDA");
+ break;
+ case DEVICE_CLASS_MINOR_COMPUTER_WEARABLE:
+ dbgPrintf("wearable");
+ break;
+ default:
+ dbgPrintf("unknown minor %d", (dev->dc & DEVICE_CLASS_MINOR_COMPUTER_MASK) >> DEVICE_CLASS_MINOR_COMPUTER_SHIFT);
+ break;
+ }
+ break;
+
+ case DEVICE_CLASS_MAJOR_PHONE:
+ dbgPrintf("Phone - ");
+ switch((dev->dc & DEVICE_CLASS_MINOR_PHONE_MASK) >> DEVICE_CLASS_MINOR_PHONE_SHIFT){
+
+ case DEVICE_CLASS_MINOR_PHONE_UNCATEG:
+ dbgPrintf("uncategorized");
+ break;
+ case DEVICE_CLASS_MINOR_PHONE_CELL:
+ dbgPrintf("Cellular");
+ break;
+ case DEVICE_CLASS_MINOR_PHONE_CORDLESS:
+ dbgPrintf("Cordless");
+ break;
+ case DEVICE_CLASS_MINOR_PHONE_SMART:
+ dbgPrintf("Smartphone");
+ break;
+ case DEVICE_CLASS_MINOR_PHONE_MODEM:
+ dbgPrintf("Modem");
+ break;
+ case DEVICE_CLASS_MINOR_PHONE_ISDN:
+ dbgPrintf("ISDN");
+ break;
+ default:
+ dbgPrintf("unknown minor %d", (dev->dc & DEVICE_CLASS_MINOR_PHONE_MASK) >> DEVICE_CLASS_MINOR_PHONE_SHIFT);
+ break;
+ }
+ break;
+
+ case DEVICE_CLASS_MAJOR_LAN:
+ dbgPrintf("LAN");
+ break;
+
+ case DEVICE_CLASS_MAJOR_AV:
+ dbgPrintf("A/V - ");
+ switch((dev->dc & DEVICE_CLASS_MINOR_AV_MASK) >> DEVICE_CLASS_MINOR_AV_SHIFT){
+
+ case DEVICE_CLASS_MINOR_AV_UNCATEG:
+ dbgPrintf("uncategorized");
+ break;
+ case DEVICE_CLASS_MINOR_AV_HEADSET:
+ dbgPrintf("Headset");
+ break;
+ case DEVICE_CLASS_MINOR_AV_HANDSFREE:
+ dbgPrintf("Handsfree");
+ break;
+ case DEVICE_CLASS_MINOR_AV_MIC:
+ dbgPrintf("Microphone");
+ break;
+ case DEVICE_CLASS_MINOR_AV_LOUDSPEAKER:
+ dbgPrintf("Loudspeaker");
+ break;
+ case DEVICE_CLASS_MINOR_AV_HEADPHONES:
+ dbgPrintf("Headphones");
+ break;
+ case DEVICE_CLASS_MINOR_AV_PORTBL_AUDIO:
+ dbgPrintf("Portable Audio");
+ break;
+ case DEVICE_CLASS_MINOR_AV_CAR_AUDIO:
+ dbgPrintf("Car audio");
+ break;
+ case DEVICE_CLASS_MINOR_AV_SET_TOP_BOX:
+ dbgPrintf("Set-Top Box");
+ break;
+ case DEVICE_CLASS_MINOR_AV_HIFI:
+ dbgPrintf("Hi-Fi");
+ break;
+ case DEVICE_CLASS_MINOR_AV_VCR:
+ dbgPrintf("VCR");
+ break;
+ case DEVICE_CLASS_MINOR_AV_VID_CAM:
+ dbgPrintf("Vidoe Camera");
+ break;
+ case DEVICE_CLASS_MINOR_AV_CAMCORDER:
+ dbgPrintf("Camcorder");
+ break;
+ case DEVICE_CLASS_MINOR_AV_VID_MONITOR:
+ dbgPrintf("Video Monitor");
+ break;
+ case DEVICE_CLASS_MINOR_AV_DISPLAY_AND_SPKR:
+ dbgPrintf("Display With Speakers");
+ break;
+ case DEVICE_CLASS_MINOR_AV_VC:
+ dbgPrintf("Video conferencing device");
+ break;
+ case DEVICE_CLASS_MINOR_AV_TOY:
+ dbgPrintf("Toy");
+ break;
+ default:
+ dbgPrintf("unknown minor %d", (dev->dc & DEVICE_CLASS_MINOR_AV_MASK) >> DEVICE_CLASS_MINOR_AV_SHIFT);
+ break;
+ }
+ break;
+
+ case DEVICE_CLASS_MAJOR_IMAGING:
+ dbgPrintf("Imaging");
+ break;
+
+ case DEVICE_CLASS_MAJOR_WEARABLE:
+ dbgPrintf("Wearable");
+ break;
+
+ case DEVICE_CLASS_MAJOR_TOY:
+ dbgPrintf("Toy");
+ break;
+
+ case DEVICE_CLASS_MAJOR_HEALTH:
+ dbgPrintf("Health");
+ break;
+
+ case DEVICE_CLASS_MAJOR_UNCATEGORIZED:
+ dbgPrintf("Uncategorize");
+ break;
+
+ default:
+ dbgPrintf("UNKNOWN_MAJOR_%d", (dev->dc & DEVICE_CLASS_MAJOR_MASK) >> DEVICE_CLASS_MAJOR_SHIFT);
+ break;
+ }
+
+ char name[249];
+ if(L.btGetRemoteName(dev->mac, dev->PSRM, dev->PSM, dev->CO, name)) dbgPrintf(" \"%s\"", name);
+ else dbgPrintf("{FAILED TO GET DEVICE NAME}");
+
+ dbgPrintf("\n");
+
+ devs = dev;
+ dev = dev->next;
+ free(devs);
+ }
+ dbgPrintf("Scan done\n");
+}
+
+void loop(void)
+{
+
+ L.btEnable(0, 0, 0, 0, adkBtDiscoveryResult);
+
+ while(1) {
+
+ L.adkEventProcess();
+ doScan();
+ }
+}
diff --git a/library/ADK2/examples/clock/clock.ino b/library/ADK2/examples/clock/clock.ino
new file mode 100644
index 0000000..44f9044
--- /dev/null
+++ b/library/ADK2/examples/clock/clock.ino
@@ -0,0 +1,1660 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ADK.h>
+#include <HCI.h>
+
+ADK L;
+
+//android app needs to match this
+#define BT_ADK_UUID 0x1d, 0xd3, 0x50, 0x50, 0xa4, 0x37, 0x11, 0xe1, 0xb3, 0xdd, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66
+
+
+void adkPutchar(char c){Serial.write(c);}
+extern "C" void dbgPrintf(const char *, ... );
+
+enum AdkStates{
+ AdkClock,
+ AdkAlarm,
+ AdkBrightness,
+ AdkColor,
+ AdkVolume,
+ AdkDisplay,
+ AdkPresets,
+
+ //always last
+ AdkInvalid
+};
+
+enum AdkDisplayMode{
+
+ AdkShowAnimation,
+ AdkShowAccel,
+ AdkShowMag,
+ AdkShowTemp,
+ AdkShowHygro,
+ AdkShowBaro,
+ AdkShowProx,
+ AdkShowColor,
+
+ AdkShowLast //always last
+};
+
+enum AdkAlarmStates {
+ AdkAlarmIdle,
+ AdkAlarmIdleWait,
+ AdkAlarmAlarm,
+ AdkAlarmSnooze
+};
+/*
+
+ button numbering (all in hex)
+
+ __ __ __ __ __ __
+ |1A| |18| |16| |14| |12| |11| 03 04 05 06
+ -- -- -- -- -- -- 0A 09 08 07
+ |1B| |19| |17| |15| |13| |10|
+ -- -- -- -- -- --
+
+*/
+
+#define BTN_SLIDER_0 0x00
+#define BTN_SLIDER_1 0x01
+#define BTN_SLIDER_2 0x02
+#define BTN_0_UP 0x1A
+#define BTN_1_UP 0x18
+#define BTN_2_UP 0x16
+#define BTN_3_UP 0x14
+#define BTN_4_UP 0x12
+#define BTN_5_UP 0x11
+#define BTN_0_DN 0x1B
+#define BTN_1_DN 0x19
+#define BTN_2_DN 0x17
+#define BTN_3_DN 0x15
+#define BTN_4_DN 0x13
+#define BTN_5_DN 0x10
+#define BTN_CLOCK 0x03
+#define BTN_ALARM 0x04
+#define BTN_BRIGHTNESS 0x05
+#define BTN_COLOR 0x06
+#define BTN_LOCK 0x07
+#define BTN_PRESETS 0x08
+#define BTN_DISPLAY 0x09
+#define BTN_VOLUME 0x0A
+
+
+
+#define BTN_MASK_PRESS 0x8000
+#define BTN_MASK_HOLD 0x4000
+#define BTN_MASK_RELEASE 0x2000
+#define BTN_MASK_ID 0x003F
+
+#define BTN_INITIAL_DELAY 10 //10ms before a click registers
+#define BTN_HOLD_DELAY 400 //400mas before a click becomes a hold
+#define BTN_AUTOREPEAT 100 //auto-repeat every 100ms
+
+
+
+#define SETTINGS_NAME "/AdkSettings.bin"
+#define SETTINGS_MAGIX 0xAF
+typedef struct AdkSettings{
+
+ uint8_t magix;
+ uint8_t ver;
+
+//v1 settings:
+
+ uint8_t R, G, B, bri, vol, almH, almM, almOn;
+ char btName[249]; //null terminated
+ char btPIN[17]; //null terminated
+
+ uint16_t almSnooze;
+ char almTune[256]; // null terminated
+
+ uint8_t speed, displayMode;
+
+//later settings
+
+}AdkSettings;
+
+
+
+AdkSettings settings;
+const char* btPIN = 0;
+
+
+volatile static int32_t hTemp, hHum, bPress, bTemp;
+volatile static uint16_t prox[7]; //prox, clear, IR ,R, G, B, temp pProx, pClear, pR, pG, pB, pIR, pTemp;
+volatile static uint16_t proxNormalized[3];
+volatile static int16_t accel[3], mag[3];
+volatile static uint32_t btSSP = ADK_BT_SSP_DONE_VAL;
+volatile static char locked = 0;
+
+
+void btStart();
+
+static uint16_t btnProcess(){
+
+ static uint64_t lastActionTime[32] = {0, };
+ static uint32_t clickSent = 0;
+ static uint32_t holdSent = 0;
+ static uint32_t lastStates = 0;
+ uint32_t curState, t, i, mask;
+
+ curState = (((uint32_t)L.capSenseButtons()) << 16) | L.capSenseIcons();
+ t = lastStates ^ curState;
+ lastStates = curState;
+
+ //update states for all buttons
+ for(mask = 1, i = 0; i < 32; i++, mask <<= 1) if(t & mask){
+
+ lastActionTime[i] = L.getUptime();
+ }
+
+ //generate events
+ for(mask = 1, i = 0; i < 32; i++, mask <<= 1){
+ if(curState & mask){
+
+ uint64_t time = L.getUptime();
+ uint64_t lapsed = time - lastActionTime[i];
+
+ if(holdSent & mask){ //maybe resend hold
+
+ if(lapsed > BTN_AUTOREPEAT){
+
+ lastActionTime[i] = time;
+ return i | BTN_MASK_HOLD;
+ }
+ }
+ else if(clickSent & mask){ //maybe time for first hold
+
+ if(lapsed > BTN_HOLD_DELAY){
+
+ holdSent |= mask;
+ lastActionTime[i] = time;
+ return i | BTN_MASK_HOLD;
+ }
+ }
+ else{ //maybe time to click
+
+ if(lapsed > BTN_INITIAL_DELAY){
+
+ clickSent |= mask;
+ lastActionTime[i] = time;
+ return i | BTN_MASK_PRESS;
+ }
+ }
+ }
+ else if(clickSent & mask){ //release
+
+ clickSent &=~ mask;
+ holdSent &=~ mask;
+ return i | BTN_MASK_RELEASE;
+ }
+ }
+ return 0;
+}
+
+void readSettings(){
+
+ uint32_t read;
+ FatFileP f;
+ char r;
+ AdkSettings ts;
+
+ //apply defaults
+ strcpy(settings.btName, "ADK 2012");
+ strcpy(settings.btPIN, "1337");
+ settings.magix = SETTINGS_MAGIX;
+ settings.ver = 1;
+ settings.R = 0;
+ settings.G = 0;
+ settings.B = 255;
+ settings.bri = 255;
+ settings.vol = 255;
+ settings.almH = 6;
+ settings.almM = 0;
+ settings.almOn = 0;
+ settings.speed = 1;
+ settings.displayMode = AdkShowAnimation;
+ settings.almSnooze = 10 * 60; //10-minute alarm
+ strcpy(settings.almTune, "/Tunes/Alarm_Rooster_02.ogg");
+
+ r = L.fatfsOpen(&f, SETTINGS_NAME, FATFS_READ);
+ if(!r){
+
+ r = L.fatfsRead(f, &ts, sizeof(AdkSettings), &read);
+
+ if(r || read != sizeof(AdkSettings) || settings.magix != SETTINGS_MAGIX || settings.ver != 1){
+
+ //in future, check for other versions and read as needed here...
+ dbgPrintf("ADK: settings: file read failed: %d, %u/%u, 0x%x\n", r, read, sizeof(AdkSettings), settings.magix);
+ }
+ else settings = ts;
+ L.fatfsClose(f);
+ }
+ else dbgPrintf("ADK: settings: file open failed: %d\n", r);
+}
+
+void writeSettings(){
+
+ FatFileP f;
+ char r;
+
+ L.fatfsUnlink(SETTINGS_NAME);
+ r = L.fatfsOpen(&f, SETTINGS_NAME, FATFS_WRITE | FATFS_CREATE | FATFS_TRUNCATE);
+ if(!r){
+ uint32_t written = 0;
+
+ r = L.fatfsWrite(f, &settings, sizeof(AdkSettings), &written);
+
+ if(r || written != sizeof(AdkSettings)) dbgPrintf("ADK: settings: file write failed: %d, %u/%u\n", r, written, sizeof(AdkSettings));
+ L.fatfsClose(f);
+ }
+ else dbgPrintf("ADK: settings: file open failed: %d\n", r);
+}
+
+void setup(void)
+{
+
+ Serial.begin(115200);
+
+ L.adkSetPutchar(adkPutchar);
+ L.adkInit();
+ btStart();
+
+ if(L.fatfsMount()) dbgPrintf("ADK: failed to mount SD card\n");
+ L.usbStart();
+}
+
+static uint8_t rnd(void){
+
+ static uint64_t seed = 7454131806685196871ULL;
+
+ seed *= 2340027325706224672ULL;
+ seed += 7310016643071172983ULL;
+ seed %= 9876543210987654321ULL;
+ seed ^= seed << 3;
+ seed += L.getUptime();
+
+ return seed >> 53;
+}
+
+void gethue(uint8_t h, uint8_t* Rp, uint8_t* Gp, uint8_t* Bp){
+ uint8_t R, G, B, seg, prog;
+
+ if(h == 255) h = 254;
+ seg = (unsigned)h / 85;
+ prog = (((uint32_t)((unsigned)h % 85)) << 8) / 85;
+
+ switch(seg){
+ case 0: R = prog; G = 0; B = 255 - prog; break;
+ case 1: R = 255 - prog; G = prog; B = 0; break;
+ case 2: R = 0; G = 255 - prog; B = prog; break;
+ }
+
+ *Rp = R;
+ *Gp = G;
+ *Bp = B;
+}
+
+static void screenClear(void){
+ uint32_t i;
+
+ for(i = 0; i < NUM_LEDS; i++) L.ledWrite(i, 0, 0, 0); //clear screen if leaving display mode
+}
+
+void adkBtSspF(const uint8_t* mac, uint32_t val){
+
+ btSSP = val;
+ dbgPrintf("ssp with val %u\n", val);
+}
+
+void loop(void)
+{
+ uint8_t r, g, b, dimR, dimG, dimB;
+ uint8_t colorSlider, volSlider, briSlider, speedSlider;
+ static const uint8_t dimIconFactor = 6;
+ AdkStates state = AdkInvalid;
+ AdkStates newState = AdkClock;
+ AdkAlarmStates alarmState = AdkAlarmIdle;
+ uint32_t i, j, k;
+ uint8_t loopCounter = 0;
+ uint64_t nextTime = 0; //for animation
+ unsigned int snoozeStart;
+ char alarmEnded = 1;
+ char alarmStop, alarmFake = 0;
+ int32_t alarmDirPos = -1;
+ FatDirP dir = 0;
+ char wasBt = 0;
+ static const uint8_t btSeq[] = {6,5,8,12,11};
+
+ readSettings();
+
+ if(0){ //very helpful to some of us - set alarm song to the first song we find :)
+ FatDirP dir;
+ if(!L.fatfsOpenDir(&dir, "/Tunes")){
+
+ FatFileInfo fi;
+ fi.longName = settings.almTune + 7;
+ fi.nameSz = 100;
+
+ strcpy(settings.almTune, "/Tunes/");
+
+ if(!L.fatfsReadDir(dir, &fi)){
+
+ dbgPrintf("tune: '%s'\n", settings.almTune);
+ } else dbgPrintf("file find fail\n");
+ } else dbgPrintf("dir open fail\n");
+ }
+
+
+ btPIN = settings.btPIN;
+ L.setVolume(settings.vol);
+ dbgPrintf("ADK: setting BT name '%s' and pin '%s'\n", settings.btName, settings.btPIN);
+ if(!L.btSetDeviceClass(DEVICE_CLASS_SERVICE_AUDIO | DEVICE_CLASS_SERVICE_RENDERING |
+ DEVICE_CLASS_SERVICE_INFORMATION | (DEVICE_CLASS_MAJOR_AV << DEVICE_CLASS_MAJOR_SHIFT) |
+ (DEVICE_CLASS_MINOR_AV_PORTBL_AUDIO << DEVICE_CLASS_MINOR_AV_SHIFT))) dbgPrintf("ADK: Failed to set device class\n");
+ if(!L.btSetLocalName(settings.btName)) dbgPrintf("ADK: failed to set BT name\n");
+ if(!L.btDiscoverable(1)) dbgPrintf("ADK: Failed to set discoverable\n");
+ if(!L.btConnectable(1)) dbgPrintf("ADK: Failed to set connectable\n");
+ L.btSetSspCallback(adkBtSspF);
+
+ while(1){
+
+ loopCounter++;
+
+ uint16_t button = btnProcess();
+
+ if(locked == 2){
+ if(button == (BTN_MASK_HOLD | BTN_LOCK)) locked = 0;
+ else button = 0;
+ }
+ else if(button == (BTN_MASK_PRESS | BTN_LOCK) && locked == 0) locked = 1;
+ else if(button == (BTN_MASK_RELEASE | BTN_LOCK) && locked == 1) locked = 2;
+
+ L.adkEventProcess(); //let the adk framework do its thing
+
+ r = (((uint32_t)settings.R) * (settings.bri + 1)) >> 8;
+ g = (((uint32_t)settings.G) * (settings.bri + 1)) >> 8;
+ b = (((uint32_t)settings.B) * (settings.bri + 1)) >> 8;
+
+ dimR = (r + dimIconFactor - 1) / dimIconFactor;
+ dimG = (g + dimIconFactor - 1) / dimIconFactor;
+ dimB = (b + dimIconFactor - 1) / dimIconFactor;
+
+ if(newState != AdkInvalid){
+ state = newState;
+ newState = AdkInvalid;
+ for(i = 0; i < 8; i++) L.ledDrawIcon(i, dimR, dimG, dimB);
+ L.ledDrawIcon(state, r, g, b);
+ }
+ L.ledDrawIcon(7, locked ? r : dimR, locked ? g : dimG, locked ? b : dimB);
+
+ if(!(loopCounter & 127)) if(!L.hygroRead((int32_t *)&hTemp, (int32_t *)&hHum)) hTemp = hHum = 0;
+ if(!(loopCounter & 7)){
+ uint16_t proxMax;
+
+ L.baroRead(3, (long *)&bPress, (long *)&bTemp);
+ L.alsRead((uint16_t *)prox + 0, (uint16_t *)prox + 1, (uint16_t *)prox + 3, (uint16_t *)prox + 4, (uint16_t *)prox + 5, (uint16_t *)prox + 2, (uint16_t *)prox + 6);
+ L.accelRead((int16_t *)accel + 0, (int16_t *)accel + 1, (int16_t *)accel + 2);
+ L.magRead((int16_t *)mag + 0, (int16_t *)mag + 1, (int16_t *)mag + 2);
+ for(i = 0; i < 3; i++) mag[i] <<= 4; //convert to 16-bit value
+
+ //copy
+ for(i = 0; i < 3; i++) proxNormalized[i] = prox[i + 3];
+ proxNormalized[2] *= 3; //blue needs more sensitivity
+
+ //find max
+ proxMax = 0;
+ for(i = 0; i < 3; i++) if(proxMax < proxNormalized[i]) proxMax = proxNormalized[i];
+ proxMax++;
+
+ //normalize to 8-bits
+ for(i = 0; i < 3; i++) proxNormalized[i] = (proxNormalized[i] << 8) / proxMax;
+
+ //exponentize (as per human eyes)
+ static const uint16_t exp[] =
+ {
+ 0,19,39,59,79,100,121,143,165,187,209,232,255,279,303,327,352,377,402,428,454,481,508,536,564,592,621,650,680,710,741,772,804, 836,869,902,
+ 936,970,1005,1040,1076,1113,1150,1187,1226,1264,1304,1344,1385,1426,1468,1511,1554,1598,1643,1688,1734,1781,1829,1877,1926,1976,2026,2078,
+ 2130,2183,2237,2292,2348,2404,2461,2520,2579,2639,2700,2762,2825,2889,2954,3020,3088,3156,3225,3295,3367,3439,3513,3588,3664,3741,3819,3899,
+ 3980,4062,4146,4231,4317,4404,4493,4583,4675,4768,4863,4959,5057,5156,5257,5359,5463,5568,5676,5785,5895,6008,6122,6238,6355,6475,6597,
+ 6720,6845,6973,7102,7233,7367,7502,7640,7780,7922,8066,8213,8362,8513,8666,8822,8981,9142,9305,9471,9640,9811,9986,10162,10342,10524,10710,
+ 10898,11089,11283,11480,11681,11884,12091,12301,12514,12731,12951,13174,13401,13632,13866,14104,14345,14591,14840,15093,15351,15612,15877,16147,
+ 16421,16699,16981,17268,17560,17856,18156,18462,18772,19087,19407,19733,20063,20398,20739,21085,21437,21794,22157,22525,22899,23279,23666,
+ 24058,24456,24861,25272,25689,26113,26544,26982,27426,27878,28336,28802,29275,29756,30244,30740,31243,31755,32274,32802,33338,33883,34436,
+ 34998,35568,36148,36737,37335,37942,38559,39186,39823,40469,41126,41793,42471,43159,43859,44569,45290,46023,46767,47523,48291,49071,49863,
+ 50668,51486,52316,53159,54016,54886,55770,56668,57580,58506,59447,60403,61373,62359,63361,64378,65412
+ };
+
+ for(i = 0; i < 3; i++) proxNormalized[i] = exp[proxNormalized[i]];
+ }
+
+ if(wasBt && btSSP == ADK_BT_SSP_DONE_VAL){ //clear leftover segments
+
+ L.ledWrite(btSeq[wasBt - 1], 0, 0, 0);
+ wasBt = 0;
+ }
+ else if(btSSP != ADK_BT_SSP_DONE_VAL){
+
+ k = btSSP;
+ for(i = 0, j = 100000; i < 6; i++, j /= 10){
+
+ L.ledDrawLetter(i, k / j + '0', 0, 0, settings.bri);
+ k %= j;
+ }
+
+ L.ledWrite(9, 0, 0, 0);
+ L.ledWrite(2, 0, 0, 0);
+
+ if(wasBt) L.ledWrite(btSeq[wasBt - 1], 0, 0, 0);
+ k = (L.getUptime() >> 7) % sizeof(btSeq);
+ wasBt = k + 1;
+ L.ledWrite(btSeq[k], 0, 0, settings.bri);
+
+ button = 0;
+ }
+ else switch(state){
+
+ case AdkClock:{
+
+ uint16_t year;
+ uint8_t month, day, h, m, s, timechange = 1;
+
+ //get and draw time
+ L.rtcGet(&year, &month, &day, &h, &m, &s);
+ L.ledDrawLetter(0, h / 10 + '0', r, g, b);
+ L.ledDrawLetter(1, h % 10 + '0', r, g, b);
+ L.ledDrawLetter(2, m / 10 + '0', r, g, b);
+ L.ledDrawLetter(3, m % 10 + '0', r, g, b);
+ L.ledDrawLetter(4, s / 10 + '0', r, g, b);
+ L.ledDrawLetter(5, s % 10 + '0', r, g, b);
+ L.ledWrite(9, r, g, b);
+ L.ledWrite(2, r, g, b);
+
+ //handle buttons
+ if(button & (BTN_MASK_PRESS | BTN_MASK_HOLD)) switch(button & BTN_MASK_ID){
+
+ case BTN_5_DN:
+ if(s) s--;
+ break;
+ case BTN_5_UP:
+ if(s < 59) s++;
+ break;
+ case BTN_4_UP:
+ if(s < 50) s += 10;
+ break;
+ case BTN_4_DN:
+ if(s > 9) s -= 10;
+ break;
+ case BTN_3_UP:
+ if(m < 59) m++;
+ break;
+ case BTN_3_DN:
+ if(m) m--;
+ break;
+ case BTN_2_UP:
+ if(m < 50) m += 10;
+ break;
+ case BTN_2_DN:
+ if(m > 9) m -= 10;
+ break;
+ case BTN_1_UP:
+ if(h < 23) h++;
+ break;
+ case BTN_1_DN:
+ if(h) h--;
+ break;
+ case BTN_0_UP:
+ if(h < 14) h += 10;
+ break;
+ case BTN_0_DN :
+ if(h > 9) h -=10;
+ break;
+ default: timechange = 0;
+ } else timechange = 0;
+
+ if(timechange){
+ L.rtcSet(year, month, day, h, m, s);
+ }
+ break;
+ }
+ case AdkAlarm:{
+
+ if(!alarmFake || alarmEnded){
+ L.ledDrawLetter(0, settings.almH / 10 + '0', r, g, b);
+ L.ledDrawLetter(1, settings.almH % 10 + '0', r, g, b);
+ L.ledDrawLetter(2, settings.almM / 10 + '0', r, g, b);
+ L.ledDrawLetter(3, settings.almM % 10 + '0', r, g, b);
+ L.ledDrawLetter(4, 'O', r, g, b);
+ L.ledDrawLetter(5, (settings.almOn ? 'N' : 'F'), r, g, b);
+ L.ledWrite(9, r, g, b);
+ L.ledWrite(2, 0, 0, 0);
+
+ if(button & (BTN_MASK_PRESS | BTN_MASK_HOLD)) switch(button & BTN_MASK_ID){
+
+ case BTN_5_DN:
+ case BTN_5_UP:
+ case BTN_4_UP:
+ case BTN_4_DN:
+ settings.almOn ^= 1;
+ break;
+ case BTN_3_UP:
+ if(settings.almM < 59) settings.almM++;
+ break;
+ case BTN_3_DN:
+ if(settings.almM) settings.almM--;
+ break;
+ case BTN_2_UP:
+ if(settings.almM < 50) settings.almM += 10;
+ break;
+ case BTN_2_DN:
+ if(settings.almM > 9) settings.almM -= 10;
+ break;
+ case BTN_1_UP:
+ if(settings.almH < 23) settings.almH++;
+ break;
+ case BTN_1_DN:
+ if(settings.almH) settings.almH--;
+ break;
+ case BTN_0_UP:
+ if(settings.almH < 14) settings.almH += 10;
+ break;
+ case BTN_0_DN :
+ if(settings.almH > 9) settings.almH -=10;
+ break;
+ }
+ }
+ else{
+ L.ledWrite(9, 0, 0, 0);
+ L.ledWrite(2, 0, 0, 0);
+ }
+ if(button == (BTN_MASK_HOLD | BTN_ALARM) && alarmEnded && (alarmState == AdkAlarmIdle || alarmState == AdkAlarmIdleWait)){ //handle sound file selection
+
+ char* name = settings.almTune;
+ alarmFake = 1;
+ alarmEnded = 0;
+ alarmStop = 0;
+ dbgPrintf("Playing song '%s'\n", settings.almTune);
+ if(name[0] == '/' && (name[1] == 'T' || name[1] == 't') &&
+ (name[2] == 'u' || name[2] == 'U') && (name[3] == 'n' || name[3] == 'N') &&
+ (name[4] == 'e' || name[4] == 'E') && (name[5] == 's' || name[5] == 'S') &&
+ name[6] == '/') name += 7;
+ for(i = 0; i < 6; i++) L.ledDrawLetter(i, name[i], r, g, b);
+ L.playOggBackground(settings.almTune, &alarmEnded, &alarmStop);
+ }
+ if(button == (BTN_MASK_PRESS | BTN_SLIDER_0) || button == (BTN_MASK_PRESS | BTN_SLIDER_1) || button == (BTN_MASK_PRESS | BTN_SLIDER_2)){
+
+ char name[256] = "/Tunes/", found = 0;
+
+ dbgPrintf("next file\n");
+
+ for(j = 0; j < 2 && !found; j++) if(!L.fatfsOpenDir(&dir, "/Tunes")){
+
+ alarmDirPos++;
+ for(i = 0; i <= alarmDirPos; i++){
+
+ FatFileInfo fi;
+ fi.longName = name + 7;
+ fi.nameSz = sizeof(name) - 7;
+
+ if(!L.fatfsReadDir(dir, &fi)){
+
+ if(i == alarmDirPos){
+ dbgPrintf("file: '%s'\n", name);
+ found = 1;
+ }
+ }
+ else{
+
+ alarmDirPos = -1;
+ dbgPrintf("no more files\n");
+ break;
+ }
+ }
+ L.fatfsCloseDir(dir);
+ }
+ if(found) strcpy(settings.almTune, name);
+ }
+ break;
+ }
+ case AdkVolume:{
+
+ uint8_t dispVol = ((uint32_t)L.getVolume() * 100) >> 8;
+
+ L.ledDrawLetter(0, 'V', r, g, b);
+ L.ledDrawLetter(1, 'O', r, g, b);
+ L.ledDrawLetter(2, 'L', r, g, b);
+ L.ledDrawLetter(3, ' ', r, g, b);
+ L.ledDrawLetter(4, dispVol / 10 + '0', r, g, b);
+ L.ledDrawLetter(5, dispVol % 10 + '0', r, g, b);
+
+ dispVol = L.capSenseSlider();
+ if(dispVol != volSlider){
+ L.setVolume(settings.vol = dispVol);
+ volSlider = dispVol;
+ }
+
+ break;
+ }
+ case AdkColor:{
+
+ uint8_t slider, seg, prog;
+ static const char hexch[] = "0123456789ABCDEF";
+
+ L.ledDrawLetter(0, hexch[settings.R >> 4], r, g, b);
+ L.ledDrawLetter(1, hexch[settings.R & 15], r, g, b);
+ L.ledDrawLetter(2, hexch[settings.G >> 4], r, g, b);
+ L.ledDrawLetter(3, hexch[settings.G & 15], r, g, b);
+ L.ledDrawLetter(4, hexch[settings.B >> 4], r, g, b);
+ L.ledDrawLetter(5, hexch[settings.B & 15], r, g, b);
+ L.ledWrite(9, 0, 0, 0);
+ L.ledWrite(2, 0, 0, 0);
+
+ if(button & (BTN_MASK_PRESS | BTN_MASK_HOLD)) switch(button & BTN_MASK_ID){
+
+ case BTN_5_DN:
+ if(settings.B) settings.B--;
+ break;
+ case BTN_5_UP:
+ if(settings.B < 0xFF) settings.B++;
+ break;
+ case BTN_4_UP:
+ if(settings.B < 0xF0) settings.B += 0x10;
+ break;
+ case BTN_4_DN:
+ if(settings.B > 0x0F) settings.B -= 0x10;
+ break;
+ case BTN_3_UP:
+ if(settings.G < 0xFF) settings.G++;
+ break;
+ case BTN_3_DN:
+ if(settings.G) settings.G--;
+ break;
+ case BTN_2_UP:
+ if(settings.G < 0xF0) settings.G += 0x10;
+ break;
+ case BTN_2_DN:
+ if(settings.G > 0x0F) settings.G -= 0x10;
+ break;
+ case BTN_1_UP:
+ if(settings.R < 0xFF) settings.R++;
+ break;
+ case BTN_1_DN:
+ if(settings.R) settings.R--;
+ break;
+ case BTN_0_UP:
+ if(settings.R < 0xF0) settings.R += 0x10;
+ break;
+ case BTN_0_DN :
+ if(settings.R > 0x0F) settings.R -= 0x10;
+ break;
+ }
+
+ slider = L.capSenseSlider();
+ if(slider != colorSlider){
+ colorSlider = slider;
+
+ gethue(slider, &settings.R, &settings.G, &settings.B);
+ }
+ break;
+ }
+ case AdkBrightness:{
+
+ uint8_t slider;
+ uint8_t dispBri = ((uint32_t)settings.bri * 100) >> 8;
+
+ L.ledDrawLetter(0, 'B', r, g, b);
+ L.ledDrawLetter(1, 'R', r, g, b);
+ L.ledDrawLetter(2, 'I', r, g, b);
+ L.ledDrawLetter(3, ' ', r, g, b);
+ L.ledDrawLetter(4, dispBri / 10 + '0', r, g, b);
+ L.ledDrawLetter(5, dispBri % 10 + '0', r, g, b);
+ L.ledWrite(9, 0, 0, 0);
+ L.ledWrite(2, 0, 0, 0);
+
+ slider = L.capSenseSlider();
+ if(slider != briSlider){
+ slider = ((((uint32_t)slider) * 191) >> 8) + 64;
+ briSlider = slider;
+ settings.bri = slider;
+ }
+ break;
+ }
+ case AdkDisplay:{
+
+ static uint8_t vals[NUM_LEDS][3] = {{0,},};
+ static const uint8_t doNotTouch[] = {49, 33, 17, 1, 48, 32, 16, 0};
+ uint8_t slider = L.capSenseSlider();
+
+ if(slider != speedSlider){
+ speedSlider = slider;
+ settings.speed = (255 - slider) >> 3;
+ }
+
+ if(L.getUptime() > nextTime){
+
+ if(!nextTime){
+
+ const char* name = NULL;
+
+ switch(settings.displayMode){
+
+ default: settings.displayMode = AdkShowAnimation; //fallthrough
+ case AdkShowAnimation: name = "PRETTY"; break;
+ case AdkShowAccel: name = " ACCEL"; break;
+ case AdkShowMag: name = "MAGNET"; break;
+ case AdkShowTemp: name = " TEMP "; break;
+ case AdkShowHygro: name = " HYGRO"; break;
+ case AdkShowBaro: name = " BARO "; break;
+ case AdkShowProx: name = " PROX "; break;
+ case AdkShowColor: name = " COLOR"; break;
+ }
+ for(i = 0; i < 6; i++) L.ledDrawLetter(i, name[i], r, g, b);
+ L.ledWrite(9, 0, 0, 0);
+ L.ledWrite(2, 0, 0, 0);
+ nextTime = L.getUptime() + 1000;
+ }
+ else{
+ nextTime = L.getUptime() + settings.speed;
+ volatile int16_t* arrPtr = NULL;
+ static const long valUnused = 0x7FFFFFFF;
+ int val = valUnused;
+ char isSigned = 1, cR = r, cG = g, cB = b;
+
+ switch(settings.displayMode){
+
+ case AdkShowAnimation:
+
+ if(rnd() < 30){ //spawn
+
+ i = rnd() % NUM_LEDS;
+ gethue(rnd(), vals[i] + 0, vals[i] + 1, vals[i] + 2);
+ }
+ for(i = 0; i < NUM_LEDS; i++){
+ for(j = 0; j < 3; j++) vals[i][j] = ((uint32_t)vals[i][j] * 127) >> 7;
+ for(j = 0; j < sizeof(doNotTouch) && i != doNotTouch[j]; j++);
+ if(j == sizeof(doNotTouch)) L.ledWrite(i, vals[i][0], vals[i][1], vals[i][2]);
+ }
+ break;
+
+ case AdkShowAccel:
+
+ arrPtr = accel;
+ //fallthrough
+
+ case AdkShowMag:
+
+ if(!arrPtr) arrPtr = mag;
+ //fallthrough
+
+ case AdkShowProx:
+
+ if(!arrPtr){
+
+ arrPtr = (int16_t*)prox;
+ isSigned = 0;
+ }
+ //fallthrough
+
+ case AdkShowColor:
+
+ if(!arrPtr){
+
+ arrPtr = (int16_t*)proxNormalized;
+ isSigned = 0;
+ cR = proxNormalized[0] >> 8;
+ cG = proxNormalized[1] >> 8;
+ cB = proxNormalized[2] >> 8;
+ }
+
+ for(i = 0; i < 6; i += 2){
+
+ val = arrPtr[i >> 1];
+ if(isSigned){
+ if(val < 0){
+ val = -val;
+ j = 0;
+ }
+ else j = 1;
+ }
+ else val = (uint16_t)val;
+
+ val *= 100;
+ val >>= isSigned ? 15 : 16;
+ L.ledDrawLetter(i + 0, + val / 10 + '0', isSigned ? (j ? settings.bri : 0) : cR, isSigned ? 0 : cG, isSigned ? (j ? 0 : settings.bri) : cB);
+ L.ledDrawLetter(i + 1, + val % 10 + '0', isSigned ? (j ? settings.bri : 0) : cR, isSigned ? 0 : cG, isSigned ? (j ? 0 : settings.bri) : cB);
+ }
+ break;
+
+ case AdkShowTemp:
+
+ val = bTemp;
+ //fall through
+
+ case AdkShowHygro:
+
+ if(val == valUnused) val = hHum;
+ //fall through
+
+ case AdkShowBaro:
+
+ if(val == valUnused) val = (bPress + 50) / 100;
+ if(val < 0){
+ L.ledDrawLetter(0, '-', r, g, b);
+ val = -val;
+ }
+ for(j = 1000, i = 1, k = 0; i < 6; i++){
+
+ if(i == 4) L.ledDrawLetter(i, '.', r, g, b);
+ else{
+
+ if(val >= j || i >= 4 || k){
+ k = 1;
+ L.ledDrawLetter(i, val / j + '0', r, g, b);
+ }
+ else L.ledDrawLetter(i, ' ', r, g, b);
+ val %= j;
+ j /= 10;
+ }
+ }
+ break;
+ }
+ }
+ }
+ break;
+ }
+ case AdkPresets:{
+
+ L.ledWrite(9, 0, 0, 0);
+ L.ledWrite(2, 0, 0, 0);
+
+ L.ledDrawLetter(0, ' ', r, g, b);
+ L.ledDrawLetter(1, 'n', r, g, b);
+ L.ledDrawLetter(2, 'o', r, g, b);
+ L.ledDrawLetter(3, 'n', r, g, b);
+ L.ledDrawLetter(4, 'e', r, g, b);
+ L.ledDrawLetter(5, ' ', r, g, b);
+
+ break;
+ }
+ }
+
+ if(button == (BTN_MASK_RELEASE | BTN_ALARM) && alarmFake && !alarmEnded){
+
+ dbgPrintf("Stopping song\n");
+ alarmStop = 1;
+ alarmFake = 0;
+ }
+
+ if(button & BTN_MASK_PRESS) switch(button & BTN_MASK_ID){
+
+ case BTN_CLOCK: newState = AdkClock; break;
+ case BTN_ALARM:
+ // eat the transition to alarm edit mode if we're in an alarm
+ if (alarmState == AdkAlarmIdle || alarmState == AdkAlarmIdleWait)
+ newState = AdkAlarm;
+ break;
+ case BTN_BRIGHTNESS: newState = AdkBrightness; briSlider = L.capSenseSlider(); break;
+ case BTN_COLOR: newState = AdkColor; colorSlider = L.capSenseSlider(); break;
+ case BTN_PRESETS: newState = AdkPresets; break;
+ case BTN_DISPLAY: newState = AdkDisplay; nextTime = 0; speedSlider = L.capSenseSlider(); break;
+ case BTN_VOLUME: newState = AdkVolume; volSlider = L.capSenseSlider(); break;
+ }
+ if(newState != AdkInvalid){
+ writeSettings();
+ if(state == AdkDisplay){
+ screenClear();
+
+ //switch to next display mode
+ if(newState == AdkDisplay && ++settings.displayMode == AdkShowLast) settings.displayMode = 0;
+ }
+ }
+
+ // alarm
+ if (settings.almOn) {
+ uint8_t month, day, h, m, sec;
+
+ L.rtcGet(0, 0, 0, &h, &m, 0);
+
+ switch (alarmState) {
+ case AdkAlarmIdle: // see if we need to trigger an alarm
+ if (settings.almH == h && settings.almM == m) {
+ // start alarm
+ Serial.write("ALARM\n");
+ alarmState = AdkAlarmAlarm;
+ }
+ break;
+ case AdkAlarmIdleWait: // we had triggered, need to wait at least a minute before waiting for next alarm
+ if (settings.almH != h || settings.almM != m) {
+ alarmState = AdkAlarmIdle;
+ }
+ break;
+ case AdkAlarmAlarm: {
+ // check for alarm button to cancel playing alarm
+ if (((button & BTN_MASK_ID) == BTN_ALARM) &&
+ (button & (BTN_MASK_PRESS | BTN_MASK_HOLD))) {
+ alarmState = AdkAlarmIdleWait;
+ alarmStop = 1;
+ L.ledDrawIcon(1, (settings.R + dimIconFactor - 1) / dimIconFactor, (settings.G + dimIconFactor - 1) / dimIconFactor, (settings.B + dimIconFactor - 1) / dimIconFactor);
+ break;
+ }
+ // check for snooze button
+ if (((button & BTN_MASK_ID) <= 2) &&
+ (button & (BTN_MASK_PRESS | BTN_MASK_HOLD))) {
+ Serial.write("ALARM SNOOZE\n");
+ alarmState = AdkAlarmSnooze;
+ snoozeStart = millis() / 1000;
+ alarmStop = 1;
+ break;
+ }
+
+ // make sure ogg is playing
+ if (alarmEnded) {
+ alarmEnded = 0;
+ alarmStop = 0;
+ alarmFake = 0;
+ L.playOggBackground(settings.almTune, &alarmEnded, &alarmStop);
+ }
+
+ // blink the alarm button red
+ if ((millis() / 500) & 1)
+ L.ledDrawIcon(1, 0xff, 0, 0);
+ else
+ L.ledDrawIcon(1, (settings.R + dimIconFactor - 1) / dimIconFactor, (settings.G + dimIconFactor - 1) / dimIconFactor, (settings.B + dimIconFactor - 1) / dimIconFactor);
+ break;
+ }
+ case AdkAlarmSnooze:
+ // check for alarm button to cancel playing alarm
+ if (alarmState != AdkAlarmIdle &&
+ ((button & BTN_MASK_ID) == 4) &&
+ (button & (BTN_MASK_PRESS | BTN_MASK_HOLD))) {
+ alarmState = AdkAlarmIdleWait;
+ alarmStop = 1;
+ L.ledDrawIcon(1, (settings.R + dimIconFactor - 1) / dimIconFactor, (settings.G + dimIconFactor - 1) / dimIconFactor, (settings.B + dimIconFactor - 1) / dimIconFactor);
+ break;
+ }
+ // see if we need to transition back to alarm state
+ if ((millis() / 1000) - snoozeStart > settings.almSnooze) {
+ Serial.write("ALARM FROM SNOOZE\n");
+ alarmState = AdkAlarmAlarm;
+ break;
+ }
+
+ // blink the alarm button blue
+ if ((millis() / 500) & 1)
+ L.ledDrawIcon(1, 0, 0, 0xff);
+ else
+ L.ledDrawIcon(1, (settings.R + dimIconFactor - 1) / dimIconFactor, (settings.G + dimIconFactor - 1) / dimIconFactor, (settings.B + dimIconFactor - 1) / dimIconFactor);
+ break;
+ }
+ } else {
+ // make sure there are no dangling alarms
+ if(!alarmFake) alarmStop = 1;
+ }
+
+ // usb accessory processing
+ processUSBAccessory();
+ }
+}
+
+
+
+
+//////////// bt interface (fun)
+
+//commands
+#define MAX_PACKET_SZ 260 //256b payload + header
+
+// command header
+// u8 cmd opcode
+// u8 sequence
+// u16 size
+
+// data formats:
+// timespec = (year,month,day,hour,min,sec) (u16,u8,u8,u8,u8,u8)
+
+#define CMD_MASK_REPLY 0x80
+#define BT_CMD_GET_PROTO_VERSION 1 // () -> (u8 protocolVersion)
+#define BT_CMD_GET_SENSORS 2 // () -> (sensors: i32,i32,i32,i32,u16,u16,u16,u16,u16,u16,u16,i16,i16,i16,i16,i16,i16)
+#define BT_CMD_FILE_LIST 3 // FIRST: (char name[]) -> (fileinfo or single zero byte) OR NONLATER: () -> (fileinfo or empty or single zero byte)
+#define BT_CMD_FILE_DELETE 4 // (char name[0-255)) -> (char success)
+#define BT_CMD_FILE_OPEN 5 // (char name[0-255]) -> (char success)
+#define BT_CMD_FILE_WRITE 6 // (u8 data[]) -> (char success)
+#define BT_CMD_FILE_CLOSE 7 // () -> (char success)
+#define BT_CMD_GET_UNIQ_ID 8 // () -> (u8 uniq[16])
+#define BT_CMD_BT_NAME 9 // (char name[]) -> () OR () -> (char name[])
+#define BT_CMD_BT_PIN 10 // (char PIN[]) -> () OR () -> (char PIN[])
+#define BT_CMD_TIME 11 // (timespec) -> (char success)) OR () > (timespec)
+#define BT_CMD_SETTINGS 12 // () -> (alarm:u8,u8,u8,brightness:u8,color:u8,u8,u8:volume:u8) or (alarm:u8,u8,u8,brightness:u8,color:u8,u8,u8:volume:u8) > (char success)
+#define BT_CMD_ALARM_FILE 13 // () -> (char file[0-255]) OR (char file[0-255]) > (char success)
+#define BT_CMD_GET_LICENSE 14 // () -> (u8 licensechunk[]) OR () if last sent
+#define BT_CMD_DISPLAY_MODE 15 // () -> (u8) OR (u8) -> ()
+#define BT_CMD_LOCK 16 // () -> (u8) OR (u8) -> ()
+
+#define BT_PROTO_VERSION_1 1 //this line marks the end of v1.0 API, all things after this are the next version
+
+
+//constants
+#define BT_PROTO_VERSION_CURRENT BT_PROTO_VERSION_1
+
+static const uint8_t gzippedLicences[] = {
+ 0x1F, 0x8B, 0x08, 0x00, 0x36, 0xB6, 0xDF, 0x4F, 0x02, 0x03, 0xCD, 0x58, 0x5D, 0x73, 0xDA, 0x38, 0x14, 0x7D, 0xD7, 0xAF, 0xB8, 0x93, 0x97, 0x26, 0x19, 0x07, 0xB2, 0x79, 0xDA, 0x49, 0x9F, 0x0C,
+ 0x18, 0xD0, 0x2C, 0xB1, 0x59, 0xDB, 0x24, 0xE5, 0xAD, 0xC2, 0x16, 0xE0, 0x1D, 0x63, 0x79, 0x2D, 0x93, 0x34, 0xFF, 0x7E, 0xEF, 0x95, 0x6D, 0x3E, 0x12, 0x92, 0xA6, 0x09, 0xDD, 0x96, 0xE9, 0x34,
+ 0x06, 0x49, 0x57, 0xE7, 0x9E, 0xFB, 0x71, 0x2C, 0x31, 0x38, 0xC6, 0x87, 0xFD, 0x02, 0x2B, 0x2C, 0x5C, 0x26, 0x1A, 0xF2, 0x42, 0xC5, 0xEB, 0xA8, 0x84, 0x24, 0x8B, 0xD2, 0x75, 0x2C, 0x35, 0x68,
+ 0x35, 0x2F, 0x1F, 0x44, 0x21, 0x61, 0x5E, 0xA8, 0x15, 0x74, 0x97, 0xC2, 0xBD, 0x66, 0xE7, 0x17, 0xC7, 0xFB, 0xB4, 0x59, 0x1B, 0xA0, 0x2F, 0xCA, 0xBE, 0x86, 0x0B, 0xE8, 0xDB, 0x21, 0xCC, 0x93,
+ 0x54, 0x82, 0x7E, 0xD4, 0xA5, 0x5C, 0xC1, 0x0A, 0xC1, 0xE0, 0xB7, 0x1A, 0x4C, 0x35, 0x04, 0xFE, 0x65, 0xEB, 0xF2, 0xCF, 0x19, 0x41, 0x3E, 0xED, 0x9E, 0x11, 0x20, 0x0B, 0xAE, 0x2E, 0xFF, 0xF8,
+ 0x83, 0xB5, 0x2F, 0x8E, 0x0C, 0xAB, 0x42, 0xD5, 0x60, 0xD0, 0x20, 0x60, 0x21, 0x33, 0x59, 0x24, 0xD1, 0x4B, 0x38, 0xE7, 0xAA, 0x00, 0xBD, 0x12, 0x69, 0x0A, 0x72, 0x35, 0x93, 0x71, 0x2C, 0xE3,
+ 0x7A, 0x82, 0x6E, 0xA1, 0x39, 0xC3, 0xAF, 0x31, 0x33, 0x2F, 0xA4, 0xDC, 0x12, 0x5B, 0x2E, 0x45, 0x09, 0x2A, 0x47, 0xD3, 0xB1, 0xB1, 0x20, 0x31, 0x00, 0xA2, 0x4C, 0x54, 0x66, 0x41, 0x21, 0xB5,
+ 0x14, 0x45, 0xB4, 0x04, 0x91, 0xC5, 0x10, 0xA9, 0xD5, 0x4A, 0x16, 0x51, 0x22, 0x52, 0x34, 0x16, 0xCB, 0x7B, 0x99, 0xAA, 0x7C, 0x25, 0xB3, 0x52, 0xC3, 0x3A, 0x8B, 0x65, 0x01, 0x69, 0x12, 0xC9,
+ 0x4C, 0x4B, 0xC8, 0x15, 0x3E, 0x3D, 0x82, 0x9A, 0xA3, 0xB5, 0x34, 0x55, 0x0F, 0x49, 0xB6, 0x80, 0xB2, 0xA8, 0x40, 0x10, 0xD9, 0x5D, 0x95, 0x3F, 0x16, 0xC9, 0x62, 0x59, 0x12, 0x7F, 0x86, 0x3A,
+ 0x0B, 0x2A, 0x1A, 0x09, 0x79, 0x35, 0x42, 0x1B, 0x17, 0xF7, 0x32, 0xAE, 0x96, 0x9C, 0x23, 0x76, 0x79, 0x80, 0x8E, 0x7D, 0x3F, 0x08, 0x63, 0xB9, 0x94, 0x85, 0x19, 0x74, 0x3D, 0xB8, 0xB3, 0x7D,
+ 0xDF, 0x76, 0xC3, 0x69, 0xCB, 0x58, 0x70, 0x15, 0x19, 0x2D, 0x91, 0x3D, 0x72, 0x0D, 0xF0, 0xDF, 0x5A, 0xCB, 0x16, 0x4C, 0xD5, 0x1A, 0x22, 0x61, 0xBE, 0x58, 0x64, 0x3B, 0x99, 0x3F, 0x1A, 0x43,
+ 0x85, 0x8C, 0x13, 0x9A, 0x3D, 0x5B, 0x97, 0x68, 0xAF, 0x24, 0x62, 0x08, 0x3B, 0xE4, 0xB2, 0xD0, 0x2A, 0x13, 0xA9, 0x05, 0x99, 0xCA, 0x2E, 0x30, 0x5B, 0xE7, 0x38, 0x88, 0xA4, 0x6D, 0xC9, 0xD9,
+ 0xA4, 0xF0, 0xC4, 0xED, 0x39, 0x3E, 0x4C, 0xBD, 0x89, 0x0F, 0xBE, 0x13, 0x8C, 0x3D, 0x37, 0xE0, 0x1D, 0x3E, 0xE2, 0x0D, 0x20, 0x7F, 0xBB, 0x03, 0x02, 0xD2, 0xC4, 0x97, 0x56, 0xEB, 0x22, 0x92,
+ 0x68, 0x0B, 0x73, 0x6D, 0xB5, 0xD6, 0x44, 0x43, 0x29, 0x92, 0x8C, 0xBC, 0x02, 0x31, 0x53, 0xF7, 0x34, 0xD4, 0x70, 0x97, 0xA9, 0x12, 0xF9, 0x36, 0xFC, 0x1C, 0x33, 0xEF, 0xCE, 0xDB, 0x8C, 0xBD,
+ 0xA9, 0x12, 0x7B, 0xAB, 0xA4, 0x2C, 0x1E, 0x61, 0x50, 0x24, 0xD9, 0x4C, 0x16, 0x8B, 0x6B, 0xD6, 0x3E, 0x67, 0x3B, 0x91, 0x8D, 0x9A, 0xC8, 0x3E, 0x99, 0x07, 0xA7, 0x02, 0x4D, 0xAF, 0x67, 0x69,
+ 0xA2, 0x97, 0x75, 0xBE, 0xF5, 0x06, 0x5E, 0x40, 0xF1, 0x58, 0x96, 0x65, 0x7E, 0xDD, 0x6E, 0xC7, 0x0B, 0xA5, 0x67, 0xA9, 0x5A, 0xB4, 0xE8, 0x3F, 0x9D, 0xAB, 0xB2, 0x85, 0xDC, 0x9E, 0x31, 0xBB,
+ 0xC9, 0x0D, 0xBD, 0x93, 0x1C, 0x6C, 0x9F, 0x44, 0x13, 0x39, 0x8C, 0x24, 0x62, 0x6E, 0xB8, 0xA4, 0x5F, 0x66, 0x49, 0x26, 0x10, 0x02, 0xEE, 0xB5, 0xD2, 0x16, 0x3C, 0x24, 0xE5, 0x92, 0x22, 0x46,
+ 0x7F, 0xD5, 0xBA, 0x64, 0x26, 0xE8, 0x49, 0x93, 0xF1, 0xE4, 0x1F, 0xC6, 0x18, 0x41, 0x97, 0x08, 0x0F, 0x39, 0xB8, 0x4F, 0xA8, 0x8C, 0x4C, 0x8D, 0x50, 0x18, 0xB6, 0x29, 0x1D, 0xA9, 0x2C, 0x4E,
+ 0xCC, 0xAE, 0x48, 0xD6, 0x4A, 0x96, 0xD7, 0xC0, 0xD8, 0x91, 0xA2, 0x6A, 0xE1, 0x58, 0xA2, 0xA9, 0x7D, 0x22, 0x4D, 0x25, 0xD9, 0xD8, 0x6C, 0xA6, 0x9B, 0x34, 0xDF, 0x41, 0x82, 0x3B, 0x46, 0xA9,
+ 0x48, 0x30, 0xFF, 0x5A, 0x88, 0x21, 0x1C, 0xF2, 0x00, 0x02, 0xAF, 0x1F, 0x62, 0xFE, 0x3B, 0x80, 0xCF, 0x63, 0xDF, 0xBB, 0xE5, 0x3D, 0xA7, 0x07, 0x9D, 0x29, 0x84, 0x43, 0x07, 0xBA, 0xDE, 0x78,
+ 0xEA, 0xF3, 0xC1, 0x30, 0x84, 0xA1, 0x37, 0xC2, 0x14, 0x0D, 0xC0, 0x76, 0x7B, 0xF8, 0xAB, 0x1B, 0xFA, 0xBC, 0x33, 0x09, 0x3D, 0xFC, 0xE1, 0xC4, 0x0E, 0x70, 0xE5, 0x09, 0x0D, 0x30, 0xDB, 0x9D,
+ 0x82, 0xF3, 0x65, 0x8C, 0x29, 0x1C, 0x80, 0xE7, 0x03, 0xBF, 0x19, 0x8F, 0x38, 0x1A, 0xAB, 0xAB, 0x8B, 0x3B, 0x81, 0x05, 0xDC, 0xED, 0x8E, 0x26, 0x3D, 0xEE, 0x0E, 0x2C, 0x40, 0x03, 0x58, 0x7B,
+ 0x21, 0x8C, 0xF8, 0x0D, 0x0F, 0x71, 0x5A, 0xE8, 0x59, 0x66, 0xD3, 0x7A, 0x19, 0xDB, 0x2E, 0x03, 0xAF, 0x0F, 0x37, 0x8E, 0xDF, 0x1D, 0xE2, 0x57, 0xBB, 0x2A, 0x0C, 0x03, 0xA4, 0xCF, 0x43, 0x97,
+ 0xF6, 0xEA, 0xE3, 0x66, 0x36, 0x8C, 0x6D, 0x3F, 0xE4, 0xDD, 0xC9, 0xC8, 0xF6, 0x61, 0x3C, 0xF1, 0xC7, 0x5E, 0xE0, 0x00, 0xBA, 0xC5, 0x7A, 0x3C, 0xE8, 0x8E, 0x6C, 0x7E, 0xE3, 0xF4, 0x5A, 0xB8,
+ 0x3B, 0x55, 0xBB, 0x73, 0xEB, 0xB8, 0x21, 0x04, 0x43, 0x7B, 0x34, 0x7A, 0xE2, 0xA5, 0x77, 0xE7, 0x62, 0x1D, 0xA2, 0xB5, 0x3D, 0x17, 0x3B, 0x0E, 0x62, 0xB4, 0x3B, 0x23, 0x87, 0x36, 0x32, 0x4E,
+ 0xF6, 0xB8, 0xEF, 0x74, 0x43, 0xF2, 0x66, 0xFB, 0xD4, 0x45, 0xE2, 0x10, 0xDE, 0xC8, 0x82, 0x60, 0xEC, 0x74, 0x39, 0x3D, 0x38, 0x5F, 0x1C, 0xF4, 0xC5, 0xF6, 0xA7, 0x56, 0x6D, 0x33, 0x70, 0xFE,
+ 0x9E, 0xE0, 0x24, 0x1C, 0x84, 0x9E, 0x7D, 0x63, 0x0F, 0x9C, 0x80, 0x9D, 0x7E, 0x87, 0x11, 0x0C, 0x49, 0x77, 0xE2, 0x3B, 0x37, 0x04, 0x19, 0x69, 0x08, 0x26, 0x9D, 0x20, 0xE4, 0xE1, 0x24, 0x74,
+ 0x60, 0xE0, 0x79, 0x3D, 0xC3, 0x73, 0xE0, 0xF8, 0xB7, 0xBC, 0xEB, 0x04, 0x9F, 0xD9, 0xC8, 0x0B, 0x0C, 0x59, 0x93, 0xC0, 0xC1, 0x72, 0xB2, 0x43, 0xDB, 0x6C, 0x8C, 0x26, 0x90, 0xA9, 0xE0, 0x33,
+ 0x3D, 0x77, 0x26, 0x01, 0x37, 0x9C, 0x71, 0x37, 0x74, 0x7C, 0x7F, 0x32, 0x0E, 0xB9, 0xE7, 0x9E, 0x61, 0x78, 0xEF, 0x90, 0x15, 0xC4, 0x68, 0xE3, 0xD2, 0x9E, 0x09, 0xA6, 0xE7, 0x02, 0xB9, 0x8A,
+ 0x04, 0x79, 0xFE, 0x94, 0x8C, 0x12, 0x07, 0x86, 0x7B, 0x0B, 0xEE, 0x86, 0x0E, 0xFE, 0xEE, 0x13, 0x9F, 0x86, 0x29, 0x9B, 0x28, 0x08, 0x90, 0xB1, 0x6E, 0xB8, 0x3B, 0x0D, 0xF7, 0x43, 0x02, 0xC3,
+ 0x1D, 0x1F, 0xC1, 0x75, 0x06, 0x23, 0x3E, 0x70, 0xDC, 0xAE, 0x43, 0xA3, 0x1E, 0x59, 0xB9, 0xE3, 0x81, 0x73, 0x86, 0xA1, 0xE2, 0x01, 0x4D, 0xE0, 0xD5, 0xB6, 0x77, 0x36, 0xEE, 0x39, 0x31, 0x2E,
+ 0x53, 0x88, 0x10, 0x55, 0xF5, 0xC8, 0x03, 0xD6, 0x24, 0xAC, 0x65, 0x02, 0x09, 0xBC, 0x0F, 0x76, 0xEF, 0x96, 0x13, 0xEC, 0x7A, 0x32, 0x86, 0xBE, 0xE9, 0x9F, 0x15, 0x65, 0xDD, 0x61, 0x4D, 0x77,
+ 0x8B, 0xBD, 0xB9, 0x69, 0xD9, 0xE5, 0x4A, 0xA6, 0x28, 0x40, 0x45, 0xAE, 0x0A, 0x53, 0xF0, 0xD4, 0xB6, 0xE0, 0x50, 0xDB, 0x7A, 0x36, 0xF3, 0xAD, 0xAF, 0x31, 0x88, 0x05, 0x4D, 0x1E, 0xF5, 0x53,
+ 0x99, 0x3C, 0xD4, 0x00, 0x3F, 0x68, 0xF2, 0x27, 0xA0, 0xFC, 0x78, 0x43, 0x7E, 0x66, 0xF2, 0x78, 0x0D, 0xFA, 0x67, 0x3A, 0x7E, 0x71, 0xAC, 0xD6, 0xBF, 0x35, 0x49, 0x22, 0xF0, 0x9A, 0x02, 0x6C,
+ 0xFB, 0x3E, 0xCC, 0xF0, 0x65, 0xEC, 0xA1, 0xF5, 0x6B, 0xF2, 0x92, 0x2A, 0xE5, 0x93, 0x86, 0x4C, 0xAC, 0xD0, 0x49, 0xF1, 0x48, 0x8E, 0x20, 0x1E, 0x0A, 0x3B, 0xC2, 0x54, 0x20, 0xB3, 0x58, 0x15,
+ 0x98, 0x02, 0x18, 0x61, 0x8C, 0xD6, 0x4A, 0xE1, 0xFB, 0x54, 0x5D, 0xA5, 0x1A, 0xDF, 0x22, 0x8B, 0xE4, 0x9E, 0x5E, 0x03, 0xA8, 0x38, 0x9F, 0x38, 0xBE, 0xA9, 0xDC, 0x26, 0x2F, 0x74, 0x2E, 0x23,
+ 0x4A, 0x04, 0x5C, 0x9E, 0x50, 0xBA, 0x14, 0x94, 0x02, 0x59, 0x95, 0x0C, 0x5A, 0x23, 0x33, 0xAD, 0xFF, 0xD7, 0xF1, 0x8D, 0x06, 0xF9, 0x98, 0x59, 0xAF, 0xAA, 0xAE, 0x1D, 0xDE, 0x38, 0xA3, 0x5D,
+ 0x51, 0x85, 0x27, 0xA2, 0xDA, 0x98, 0xFC, 0x98, 0xB8, 0xC2, 0xBE, 0xB8, 0x56, 0x26, 0x9F, 0x48, 0xAC, 0xF5, 0x06, 0x7D, 0x45, 0x7C, 0xAE, 0xE7, 0x5E, 0x70, 0xB7, 0xEF, 0xE3, 0xB6, 0x95, 0x4A,
+ 0x91, 0x57, 0xCF, 0x1C, 0x3F, 0x28, 0xBE, 0x95, 0xB3, 0x7B, 0xF2, 0x0A, 0x87, 0xE5, 0x75, 0x87, 0xCB, 0xF7, 0x2A, 0x2D, 0x1C, 0x52, 0xDA, 0xCA, 0xE4, 0x7B, 0xF5, 0x16, 0x0E, 0xE8, 0x6D, 0x6D,
+ 0xF2, 0xBD, 0xB2, 0x0B, 0xCF, 0x64, 0x77, 0xE3, 0xF8, 0xBB, 0xF5, 0x77, 0xC7, 0xF3, 0x27, 0x79, 0xF9, 0x71, 0x35, 0x86, 0xAD, 0x1A, 0x57, 0x26, 0x7F, 0x5C, 0x93, 0x5F, 0xAF, 0x9E, 0x97, 0xD4,
+ 0x3A, 0xC4, 0x18, 0x21, 0xE6, 0x7D, 0xD1, 0xA6, 0x56, 0xF7, 0x25, 0xC9, 0x97, 0x2D, 0x85, 0xC7, 0x87, 0xBE, 0xC2, 0xC3, 0x66, 0x2D, 0xDD, 0x4F, 0x75, 0xFB, 0xF2, 0xCA, 0x3A, 0x34, 0xF1, 0xF7,
+ 0x38, 0x25, 0x68, 0x46, 0x8B, 0x48, 0x86, 0x18, 0xFB, 0xA8, 0x56, 0xB0, 0xDD, 0x63, 0xC2, 0x0F, 0x9F, 0x11, 0x0E, 0xED, 0x8F, 0xFB, 0xEC, 0xF8, 0xDF, 0xEC, 0x5F, 0xC5, 0x47, 0x1E, 0x1D, 0x02,
+ 0x54, 0x6E, 0xB1, 0x58, 0x45, 0x6B, 0xBA, 0x41, 0x10, 0x4D, 0x58, 0xDA, 0xC8, 0xB8, 0xA2, 0x33, 0x3C, 0x0A, 0x49, 0x89, 0xDA, 0x20, 0x52, 0xBD, 0x65, 0xD7, 0x84, 0xA4, 0xD6, 0xBD, 0x0D, 0x74,
+ 0xE3, 0x8D, 0x2B, 0x13, 0xB3, 0x88, 0x06, 0x8D, 0x0C, 0x21, 0x94, 0x17, 0xB2, 0x06, 0xD5, 0x69, 0x3B, 0xCF, 0xF0, 0x9E, 0x94, 0x9A, 0x21, 0xEE, 0xCA, 0x22, 0x2A, 0x95, 0xD1, 0xB0, 0x77, 0xE8,
+ 0x17, 0x7B, 0xAF, 0x6A, 0x1D, 0xE5, 0xC8, 0xC6, 0xBE, 0x7E, 0x35, 0xF2, 0xF2, 0xE9, 0xD3, 0x21, 0x7D, 0x79, 0x9B, 0xAE, 0xB0, 0xB7, 0xE9, 0xCA, 0x77, 0x0E, 0x6D, 0xEC, 0xA5, 0x43, 0xDB, 0x9E,
+ 0x6E, 0xBC, 0x70, 0x6A, 0xEB, 0x7B, 0x13, 0x17, 0x5B, 0x2E, 0xF6, 0x51, 0xF6, 0xEA, 0x81, 0x0D, 0xBE, 0x7B, 0x60, 0x63, 0x1F, 0x95, 0x11, 0x76, 0x14, 0x01, 0x61, 0x1F, 0x3B, 0xB0, 0xD5, 0xCA,
+ 0xC1, 0x7E, 0x9B, 0x03, 0x1B, 0x7B, 0x2E, 0x11, 0xEF, 0x38, 0xB0, 0xBD, 0xED, 0xB4, 0x46, 0x65, 0x6A, 0x67, 0x71, 0xA1, 0x92, 0x18, 0xBC, 0x5C, 0x66, 0x17, 0x41, 0xD5, 0x22, 0xC7, 0x85, 0xFA,
+ 0x47, 0x46, 0xA5, 0xB9, 0x72, 0x82, 0xF3, 0xE7, 0xF7, 0x89, 0x57, 0xE6, 0xBA, 0x70, 0x77, 0x25, 0xEC, 0xAF, 0xC4, 0x55, 0xB4, 0x70, 0x54, 0x5D, 0x58, 0xC6, 0xF5, 0xFD, 0xA5, 0xD9, 0x2E, 0x17,
+ 0x11, 0xFE, 0xA9, 0x47, 0x2C, 0xB8, 0x95, 0x05, 0xD5, 0x28, 0x5C, 0xB5, 0x2E, 0xE1, 0x94, 0x26, 0x9C, 0xD4, 0x43, 0x27, 0x67, 0x9F, 0xC9, 0xC4, 0xA3, 0x5A, 0x6F, 0xDE, 0x79, 0x49, 0x52, 0x4C,
+ 0x0F, 0x30, 0x37, 0xB3, 0xF2, 0x5B, 0x24, 0x73, 0x72, 0x8D, 0xAE, 0x06, 0xF3, 0x34, 0x11, 0x59, 0x24, 0xB7, 0x2D, 0xAC, 0xB6, 0xD2, 0x22, 0x1B, 0xD3, 0xDA, 0x86, 0x9A, 0x99, 0x7E, 0x2F, 0x4C,
+ 0x93, 0x6D, 0x5A, 0x58, 0x3D, 0x11, 0x44, 0x03, 0xDA, 0x7C, 0xEA, 0xAB, 0xB2, 0x87, 0x87, 0x87, 0x96, 0x30, 0x88, 0xA9, 0xCB, 0xB5, 0xEB, 0x0B, 0x58, 0xDD, 0x1E, 0x61, 0x1E, 0x62, 0x96, 0x5F,
+ 0x20, 0xEA, 0x7A, 0xD5, 0x24, 0x4B, 0xA5, 0xA6, 0x83, 0xE3, 0xBF, 0xEB, 0xA4, 0x40, 0x8F, 0x67, 0x8F, 0x20, 0x72, 0x44, 0x15, 0x89, 0x19, 0x62, 0x4D, 0xC5, 0x03, 0xB5, 0x37, 0xB1, 0x28, 0x64,
+ 0xD5, 0xF3, 0x10, 0x06, 0x35, 0x2A, 0xEC, 0xDA, 0xD6, 0x26, 0x26, 0x64, 0x66, 0x7B, 0x27, 0xBA, 0x4B, 0x5A, 0x83, 0x11, 0x5D, 0xDF, 0x9D, 0x60, 0x5A, 0xFA, 0xE6, 0xAD, 0xB7, 0x63, 0x07, 0x3C,
+ 0xB0, 0xC8, 0xC8, 0x1D, 0x0F, 0x87, 0x94, 0x54, 0xBB, 0x5D, 0xC5, 0xD4, 0x65, 0x8F, 0x53, 0x19, 0x98, 0xD2, 0xA1, 0xE4, 0xFB, 0x0B, 0xEB, 0xDA, 0x82, 0xBA, 0xB5, 0xCB, 0x6F, 0x79, 0x41, 0x1E,
+ 0x20, 0xCC, 0x84, 0xE8, 0xA4, 0xDB, 0x3F, 0xB4, 0x15, 0x48, 0xB9, 0x07, 0x61, 0x5E, 0x77, 0xF7, 0x4D, 0xD7, 0x4D, 0x45, 0xB6, 0x58, 0x8B, 0x85, 0x84, 0x05, 0xCA, 0x57, 0x91, 0x91, 0x0E, 0x6D,
+ 0x5B, 0xAF, 0x51, 0x29, 0x32, 0x93, 0x26, 0x28, 0xE5, 0xA2, 0x12, 0xAE, 0x67, 0x7E, 0xD1, 0x46, 0xF8, 0xCA, 0xF2, 0x1F, 0xF8, 0xB9, 0x5A, 0xB2, 0x5A, 0x19, 0x00, 0x00
+};
+
+
+static void putLE32(uint8_t* buf, uint16_t* idx, uint32_t val){
+
+ buf[(*idx)++] = val;
+ buf[(*idx)++] = val >> 8;
+ buf[(*idx)++] = val >> 16;
+ buf[(*idx)++] = val >> 24;
+}
+
+static void putLE16(uint8_t* buf, uint16_t* idx, uint32_t val){
+
+ buf[(*idx)++] = val;
+ buf[(*idx)++] = val >> 8;
+}
+
+static uint16_t adkProcessCommand(uint8_t cmd, const uint8_t* dataIn, uint16_t sz, char fromBT, uint8_t* reply, uint16_t maxReplySz){ //returns num bytes to reply with (or 0 for no reply)
+
+ uint16_t sendSz = 0;
+ static FatFileP btFile = 0, usbFile = 0;
+ static FatDirP btDir = 0, usbDir = 0;
+ static uint16_t btLicPos = 0, usbLicPos = 0;
+ FatFileP* filP = fromBT ? &btFile : &usbFile;
+ FatDirP* dirP = fromBT ? &btDir : &usbDir;
+ uint16_t* licPos = fromBT ? &btLicPos : &usbLicPos;
+
+ dbgPrintf("ADK: BT: have cmd 0x%x with %db of data\n", cmd, sz);
+
+ //NOTE: this code was written in a hurry and features little error checking. yes, I know it's bad. -DG
+
+ //process packet
+ switch(cmd){
+
+ case BT_CMD_GET_PROTO_VERSION:
+ {
+ reply[sendSz++] = BT_PROTO_VERSION_CURRENT;
+ }
+ break;
+
+ case BT_CMD_GET_SENSORS:
+ {
+ putLE32(reply, &sendSz, hTemp);
+ putLE32(reply, &sendSz, hHum);
+ putLE32(reply, &sendSz, bPress);
+ putLE32(reply, &sendSz, bTemp);
+ putLE16(reply, &sendSz, prox[0]);
+ putLE16(reply, &sendSz, prox[1]);
+ putLE16(reply, &sendSz, prox[3]);
+ putLE16(reply, &sendSz, prox[4]);
+ putLE16(reply, &sendSz, prox[5]);
+ putLE16(reply, &sendSz, prox[2]);
+ putLE16(reply, &sendSz, prox[6]);
+ putLE16(reply, &sendSz, accel[0]);
+ putLE16(reply, &sendSz, accel[1]);
+ putLE16(reply, &sendSz, accel[2]);
+ putLE16(reply, &sendSz, mag[0]);
+ putLE16(reply, &sendSz, mag[1]);
+ putLE16(reply, &sendSz, mag[2]);
+ }
+ break;
+
+ case BT_CMD_FILE_LIST:
+ {
+
+ if(sz){ //reset
+
+ if(*dirP) L.fatfsCloseDir(*dirP);
+ if(L.fatfsOpenDir(dirP, (char*)dataIn)) *dirP = 0;
+ }
+ if(*dirP){
+
+ FatFileInfo fi;
+ fi.longName = (char*)reply + 5;
+ fi.nameSz = maxReplySz - 5;
+
+ if(!L.fatfsReadDir(*dirP, &fi)){
+
+ fi.longName[fi.nameSz - 1] = 0;
+ reply[sendSz++] = fi.fsize;
+ reply[sendSz++] = fi.fsize >> 8;
+ reply[sendSz++] = fi.fsize >> 16;
+ reply[sendSz++] = fi.fsize >> 24;
+ reply[sendSz++] = fi.attrib;
+ sendSz += strlen(fi.longName) + 1;
+ }
+ else reply[sendSz++] = 0;
+ }
+ else reply[sendSz++] = 0;
+ }
+ break;
+
+ case BT_CMD_FILE_DELETE:
+ {
+ reply[sendSz++] = !L.fatfsUnlink((const char*)dataIn);
+ }
+ break;
+
+ case BT_CMD_FILE_OPEN:
+ {
+ if(*filP) L.fatfsClose(*filP);
+ reply[sendSz++] = !L.fatfsOpen(filP, (const char*)dataIn, FATFS_WRITE | FATFS_CREATE | FATFS_TRUNCATE);
+ if(!reply[sendSz - 1]) *filP = 0;
+ }
+ break;
+
+ case BT_CMD_FILE_WRITE:
+ {
+ uint32_t written;
+
+ reply[sendSz++] = !L.fatfsWrite(*filP, (void*)dataIn, sz, &written) && written == sz;
+ }
+ break;
+
+ case BT_CMD_FILE_CLOSE:
+ {
+ if(*filP){
+ reply[sendSz++] = 1;
+ L.fatfsClose(*filP);
+ *filP = 0;
+ }
+ else reply[sendSz++] = 0;
+ }
+ break;
+
+ case BT_CMD_GET_UNIQ_ID:
+ {
+
+ uint32_t id[4];
+
+ L.getUniqueId(id);
+ putLE32(reply, &sendSz, id[0]);
+ putLE32(reply, &sendSz, id[1]);
+ putLE32(reply, &sendSz, id[2]);
+ putLE32(reply, &sendSz, id[3]);
+ }
+ break;
+
+ case BT_CMD_BT_NAME:
+ {
+ if(sz){ //set
+ strcpy(settings.btName, (char*)dataIn);
+ reply[sendSz++] = 1;
+ writeSettings();
+ }
+ else{
+ strcpy((char*)reply, settings.btName);
+ sendSz = strlen((char*)reply) + 1;
+ }
+ }
+ break;
+
+ case BT_CMD_BT_PIN:
+ {
+ if(sz){ //set
+ strcpy(settings.btPIN, (char*)dataIn);
+ reply[sendSz++] = 1;
+ writeSettings();
+ }
+ else{
+ strcpy((char*)reply, settings.btPIN);
+ sendSz = strlen((char*)reply) + 1;
+ }
+ }
+ break;
+ case BT_CMD_TIME:
+ {
+ if (sz >= 7) { //set
+ L.rtcSet(dataIn[1] << 8 | dataIn[0], dataIn[2], dataIn[3], dataIn[4], dataIn[5], dataIn[6]);
+ reply[sendSz++] = 1;
+ } else if (sz == 0) {
+ L.rtcGet((uint16_t *)&reply[0], &reply[2], &reply[3], &reply[4], &reply[5], &reply[6]);
+ sendSz += 7;
+ }
+ }
+ break;
+ case BT_CMD_SETTINGS:
+ {
+ if (sz >= 8) { //set
+ settings.almH = dataIn[0];
+ settings.almM = dataIn[1];
+ settings.almOn = dataIn[2];
+ settings.bri = dataIn[3];
+ settings.R = dataIn[4];
+ settings.G = dataIn[5];
+ settings.B = dataIn[6];
+ settings.vol = dataIn[7];
+ L.setVolume(settings.vol);
+ writeSettings();
+ reply[sendSz++] = 1;
+ } else {
+ reply[sendSz++] = settings.almH;
+ reply[sendSz++] = settings.almM;
+ reply[sendSz++] = settings.almOn;
+ reply[sendSz++] = settings.bri;
+ reply[sendSz++] = settings.R;
+ reply[sendSz++] = settings.G;
+ reply[sendSz++] = settings.B;
+ reply[sendSz++] = settings.vol;
+ }
+ }
+ break;
+ case BT_CMD_ALARM_FILE:
+ {
+ if(sz){ //set
+ strcpy(settings.almTune, (char*)dataIn);
+ reply[sendSz++] = 1;
+ writeSettings();
+ } else{
+ strcpy((char*)reply, settings.almTune);
+ sendSz = strlen((char*)reply) + 1;
+ }
+ }
+ break;
+ case BT_CMD_GET_LICENSE:
+ {
+ static const uint32_t maxPacket = MAX_PACKET_SZ - 10; //seems reasonable
+
+ if(*licPos >= sizeof(gzippedLicences)){ //send terminator
+ reply[sendSz++] = 0;
+ *licPos = 0;
+ }
+ else{
+
+ uint32_t left = sizeof(gzippedLicences) - *licPos;
+ if(left > maxPacket) left = maxPacket;
+ reply[sendSz++] = 1;
+ while(left--) reply[sendSz++] = gzippedLicences[(*licPos)++];
+ }
+ }
+ break;
+ case BT_CMD_DISPLAY_MODE:
+ {
+ if (sz) { //set
+ settings.displayMode = dataIn[0];
+ reply[sendSz++] = 1;
+ } else if (sz == 0) {
+ reply[sendSz++] = settings.displayMode;
+ }
+ }
+ break;
+ case BT_CMD_LOCK:
+ {
+ if (sz) { //set
+ locked = dataIn[0] ? 2 : 0;
+ reply[sendSz++] = 1;
+ } else if (sz == 0) {
+ reply[sendSz++] = locked;
+ }
+ }
+ break;
+ }
+ return sendSz;
+}
+
+static uint8_t cmdBuf[MAX_PACKET_SZ];
+static uint32_t bufPos = 0;
+
+
+static void btAdkPortOpen(void* port, uint8_t dlci){
+
+ bufPos = 0;
+}
+
+static void btAdkPortClose(void* port, uint8_t dlci){
+
+ //nothing here [yet?]
+}
+
+
+static void btAdkPortRx(void* port, uint8_t dlci, const uint8_t* data, uint16_t sz){
+
+ uint8_t reply[MAX_PACKET_SZ];
+ uint32_t i;
+ uint8_t seq, cmd;
+ uint16_t cmdSz;
+ uint8_t* ptr;
+
+ while(sz || bufPos){
+
+ uint16_t sendSz = 0;
+
+ //copy to buffer as much as we can
+ while(bufPos < MAX_PACKET_SZ && sz){
+ cmdBuf[bufPos++] = *data++;
+ sz--;
+ }
+
+ //see if a packet exists
+ if(bufPos < 4) return; // too small to be a packet -> discard
+ cmd = cmdBuf[0];
+ seq = cmdBuf[1];
+ cmdSz = cmdBuf[3];
+ cmdSz <<= 8;
+ cmdSz += cmdBuf[2];
+
+ if(bufPos - 4 < cmdSz) return; //not entire command received yet
+
+ sendSz = adkProcessCommand(cmd, cmdBuf + 4, cmdSz, 1, reply + 4, MAX_PACKET_SZ - 4);
+ if(sendSz){
+
+ reply[0] = cmd | CMD_MASK_REPLY;
+ reply[1] = seq;
+ reply[2] = sendSz;
+ reply[3] = sendSz >> 8;
+ sendSz += 4;
+
+ L.btRfcommPortTx(port, dlci, reply, sendSz);
+ }
+
+ //adjust buffer as needed
+ for(i = 0; i < bufPos - cmdSz - 4; i++){
+ cmdBuf[i] = cmdBuf[i + cmdSz + 4];
+ }
+ bufPos = i;
+ }
+}
+
+
+
+
+
+
+//////////// bt support (boring)
+
+
+static const uint8_t maxPairedDevices = 4;
+static uint8_t numPairedDevices = 0;
+static uint8_t savedMac[maxPairedDevices][BLUETOOTH_MAC_SIZE];
+static uint8_t savedKey[maxPairedDevices][BLUETOOTH_LINK_KEY_SIZE];
+
+static char adkBtConnectionRequest(const uint8_t* mac, uint32_t devClass, uint8_t linkType){ //return 1 to accept
+
+ Serial.print("Accepting connection from ");
+ Serial.print(mac[5], HEX);
+ Serial.print(":");
+ Serial.print(mac[4], HEX);
+ Serial.print(":");
+ Serial.print(mac[3], HEX);
+ Serial.print(":");
+ Serial.print(mac[2], HEX);
+ Serial.print(":");
+ Serial.print(mac[1], HEX);
+ Serial.print(":");
+ Serial.println(mac[0], HEX);
+ return 1;
+}
+
+static char adkBtLinkKeyRequest(const uint8_t* mac, uint8_t* buf){ //link key create
+
+ uint8_t i, j;
+
+ Serial.print("Key request from ");
+ Serial.print(mac[5], HEX);
+ Serial.print(":");
+ Serial.print(mac[4], HEX);
+ Serial.print(":");
+ Serial.print(mac[3], HEX);
+ Serial.print(":");
+ Serial.print(mac[2], HEX);
+ Serial.print(":");
+ Serial.print(mac[1], HEX);
+ Serial.print(":");
+ Serial.print(mac[0], HEX);
+ Serial.print(" -> ");
+
+ for(i = 0; i < numPairedDevices; i++){
+
+ for(j = 0; j < BLUETOOTH_MAC_SIZE && savedMac[i][j] == mac[j]; j++);
+ if(j == BLUETOOTH_MAC_SIZE){ //match
+
+ Serial.print("{");
+ for(j = 0; j < BLUETOOTH_LINK_KEY_SIZE; j++){
+
+ Serial.print(" ");
+ Serial.print(savedKey[i][j], HEX);
+ buf[j] = savedKey[i][j];
+ }
+ Serial.println(" }");
+ return 1;
+ }
+ }
+ Serial.println("FAIL");
+ return 0;
+}
+
+static void adkBtLinkKeyCreated(const uint8_t* mac, const uint8_t* buf){ //link key was just created, save it if you want it later
+
+ uint8_t j;
+
+ Serial.print("Key created for ");
+ Serial.print(mac[5], HEX);
+ Serial.print(":");
+ Serial.print(mac[4], HEX);
+ Serial.print(":");
+ Serial.print(mac[3], HEX);
+ Serial.print(":");
+ Serial.print(mac[2], HEX);
+ Serial.print(":");
+ Serial.print(mac[1], HEX);
+ Serial.print(":");
+ Serial.print(mac[0], HEX);
+ Serial.print(" <- ");
+
+ Serial.print("{");
+ for(j = 0; j < BLUETOOTH_LINK_KEY_SIZE; j++){
+
+ Serial.print(" ");
+ Serial.print(buf[j], HEX);
+ }
+ Serial.print(" }");
+
+ if(numPairedDevices < maxPairedDevices){
+
+ for(j = 0; j < BLUETOOTH_LINK_KEY_SIZE; j++) savedKey[numPairedDevices][j] = buf[j];
+ for(j = 0; j < BLUETOOTH_MAC_SIZE; j++) savedMac[numPairedDevices][j] = mac[j];
+ numPairedDevices++;
+ Serial.print("saved to slot ");
+ Serial.print(numPairedDevices);
+ Serial.print("/");
+ Serial.println(maxPairedDevices);
+ }
+ else{
+ Serial.println("out of slots...discaring\n");
+ }
+}
+
+static char adkBtPinRequest(const uint8_t* mac, uint8_t* buf){ //fill buff with PIN code, return num bytes used (16 max) return 0 to decline
+
+ uint8_t v, i = 0;
+
+ Serial.print("PIN request from ");
+ Serial.print(mac[5], HEX);
+ Serial.print(":");
+ Serial.print(mac[4], HEX);
+ Serial.print(":");
+ Serial.print(mac[3], HEX);
+ Serial.print(":");
+ Serial.print(mac[2], HEX);
+ Serial.print(":");
+ Serial.print(mac[1], HEX);
+ Serial.print(":");
+ Serial.print(mac[0], HEX);
+
+ if(btPIN){
+ Serial.print(" -> using pin '");
+ Serial.print((char*)btPIN);
+ Serial.println("'");
+ for(i = 0; btPIN[i]; i++) buf[i] = btPIN[i];
+ return i;
+ }
+ else Serial.println(" no PIN set. rejecting");
+ return 0;
+}
+
+#define MAGIX 0xFA
+
+static uint8_t sdpDescrADK[] =
+{
+ //service class ID list
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x01, SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 17,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_16), BT_ADK_UUID,
+ //ServiceId
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x03, SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x11, 0x01,
+ //ProtocolDescriptorList
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x04, SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 15,
+ SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 6,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x01, 0x00, // L2CAP
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), L2CAP_PSM_RFCOMM >> 8, L2CAP_PSM_RFCOMM & 0xFF, // L2CAP PSM
+ SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 5,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x00, 0x03, // RFCOMM
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_1), MAGIX, // port ###
+ //browse group list
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x00, 0x05, SDP_ITEM_DESC(SDP_TYPE_ARRAY, SDP_SZ_u8), 3,
+ SDP_ITEM_DESC(SDP_TYPE_UUID, SDP_SZ_2), 0x10, 0x02, // Public Browse Group
+ //name
+ SDP_ITEM_DESC(SDP_TYPE_UINT, SDP_SZ_2), 0x01, 0x00, SDP_ITEM_DESC(SDP_TYPE_TEXT, SDP_SZ_u8), 12, 'A', 'D', 'K', ' ', 'B', 'T', ' ', 'C', 'O', 'M', 'M', 'S'
+};
+
+void btStart(){
+ uint8_t i, dlci;
+ int f;
+
+ L.btEnable(adkBtConnectionRequest, adkBtLinkKeyRequest, adkBtLinkKeyCreated, adkBtPinRequest, NULL);
+
+ dlci = L.btRfcommReserveDlci(RFCOMM_DLCI_NEED_EVEN);
+
+ if(!dlci) dbgPrintf("BTADK: failed to allocate DLCI\n");
+ else{
+
+ //change descriptor to be valid...
+ for(i = 0, f = -1; i < sizeof(sdpDescrADK); i++){
+
+ if(sdpDescrADK[i] == MAGIX){
+ if(f == -1) f = i;
+ else break;
+ }
+ }
+
+ if(i != sizeof(sdpDescrADK) || f == -1){
+
+ dbgPrintf("BTADK: failed to find a single marker in descriptor\n");
+ L.btRfcommReleaseDlci(dlci);
+ return;
+ }
+
+ sdpDescrADK[f] = dlci >> 1;
+
+ dbgPrintf("BTADK has DLCI %u\n", dlci);
+
+ L.btRfcommRegisterPort(dlci, btAdkPortOpen, btAdkPortClose, btAdkPortRx);
+ L.btSdpServiceDescriptorAdd(sdpDescrADK, sizeof(sdpDescrADK));
+ }
+}
+
+// USB accessory
+static void processUSBAccessory()
+{
+ if (!L.accessoryConnected())
+ return;
+
+ uint8_t receiveBuf[MAX_PACKET_SZ];
+ uint8_t reply[MAX_PACKET_SZ];
+
+ int res = L.accessoryReceive(receiveBuf, sizeof(receiveBuf));
+ if (res >= 4) {
+ uint8_t cmd = receiveBuf[0];
+ uint8_t seq = receiveBuf[1];
+ uint16_t size = receiveBuf[2] | receiveBuf[3] << 8;
+
+ if (size + 4 > res) {
+ // short packet
+ return;
+ }
+
+ uint16_t replylen = adkProcessCommand(cmd, receiveBuf + 4, size, 0, reply + 4, MAX_PACKET_SZ - 4);
+ if (replylen > 0) {
+ reply[0] = cmd | CMD_MASK_REPLY;
+ reply[1] = seq;
+ reply[2] = replylen;
+ reply[3] = replylen >> 8;
+ replylen += 4;
+
+ dbgPrintf("ADK: USB: sending %d bytes\n", replylen);
+ L.accessorySend(reply, replylen);
+ }
+ }
+}
+
diff --git a/library/ADK2/examples/usbaccessory/usbaccessory.ino b/library/ADK2/examples/usbaccessory/usbaccessory.ino
new file mode 100644
index 0000000..4cb6f7e
--- /dev/null
+++ b/library/ADK2/examples/usbaccessory/usbaccessory.ino
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Arduino.h"
+#include <ADK.h>
+
+ADK L;
+
+// ADK1 usb accessory strings
+#define ACCESSORY_STRING_VENDOR "Google, Inc."
+#define ACCESSORY_STRING_NAME "DemoKit"
+#define ACCESSORY_STRING_LONGNAME "DemoKit Arduino Board"
+#define ACCESSORY_STRING_VERSION "1.0"
+#define ACCESSORY_STRING_URL "http://www.android.com"
+#define ACCESSORY_STRING_SERIAL "0000000012345678"
+
+void adkPutchar(char c){Serial.write(c);}
+extern "C" void dbgPrintf(const char *, ... );
+
+void setup(void)
+{
+ Serial.begin(115200);
+
+ L.adkSetPutchar(adkPutchar);
+ L.adkInit();
+
+ // set the old accessory strings
+ L.usbSetAccessoryStringVendor(ACCESSORY_STRING_VENDOR);
+ L.usbSetAccessoryStringName(ACCESSORY_STRING_NAME);
+ L.usbSetAccessoryStringLongname(ACCESSORY_STRING_LONGNAME);
+ L.usbSetAccessoryStringVersion(ACCESSORY_STRING_VERSION);
+ L.usbSetAccessoryStringUrl(ACCESSORY_STRING_URL);
+ L.usbSetAccessoryStringSerial(ACCESSORY_STRING_SERIAL);
+
+ L.usbStart();
+}
+
+struct SendBuf {
+ void Reset() { pos = 0; memset(buf, 0, sizeof(buf)); }
+ void Append(int val) { buf[pos++] = val; }
+ void Append(uint8_t val) { buf[pos++] = val; }
+ void Append(uint16_t val) { buf[pos++] = val >> 8; buf[pos++] = val; }
+ void Append(uint32_t val) { buf[pos++] = val >> 24; buf[pos++] = val >> 16; buf[pos++] = val >> 8; buf[pos++] = val; }
+
+ int Send() { return L.accessorySend(buf, pos); }
+
+ uint8_t buf[128];
+ int pos;
+};
+
+void loop()
+{
+ static int last_report = 0;
+ static uint16_t temp = 0;
+ static uint16_t light = 0;
+ static uint8_t buttons = 0;
+ static uint8_t joyx = 0;
+ static uint8_t joyy = 0;
+ static uint8_t ledrgb[6][3];
+
+ int now = millis() / 100;
+
+ // see if we need to report our current status
+ if (now != last_report) {
+ SendBuf buf;
+ buf.Reset();
+
+ // temperature
+ buf.Append(0x04);
+ buf.Append(temp);
+ temp++;
+
+ // light<
+ buf.Append(0x05);
+ buf.Append(light);
+ light++;
+
+ // buttons
+ for (int i = 0; i < 5; i++) {
+ buf.Append(0x01);
+ buf.Append(i);
+ buf.Append((uint8_t)(buttons & (1 << i)));
+ }
+ buttons++;
+
+ // joystick
+ buf.Append(0x06);
+ buf.Append((uint8_t)(L.capSenseSlider() - 128));
+ buf.Append(0);
+ joyx += 2;
+ joyy += 3;
+
+ buf.Send();
+ }
+
+ // read from phone
+ {
+ uint8_t buf[64];
+
+ int res = L.accessoryReceive(buf, sizeof(buf));
+
+ int pos = 0;
+ while (pos < res) {
+ uint8_t op = buf[pos++];
+
+ switch (op) {
+ case 0x2: {
+ // color sliders
+ unsigned int led = buf[pos];
+
+ if (led < 12) {
+ ledrgb[led/3][led%3] = buf[pos+1];
+ } else if (led >= 0x10 || led <= 0x12) {
+ ledrgb[3][led%3] = buf[pos+1];
+ }
+
+ pos += 2;
+ break;
+ }
+ case 0x3: {
+ // relay
+ int val = buf[pos+1] ? 255 : 0;
+ int led = (buf[pos] == 0) ? 4 : 5;
+ ledrgb[led][0] = val;
+ ledrgb[led][1] = val;
+ ledrgb[led][2] = val;
+ pos += 2;
+ break;
+ }
+ default: // assume 3 byte packet
+ pos += 2;
+ break;
+ }
+ }
+ }
+
+ for (int i = 0; i < 6; i++) {
+ L.ledDrawLetter(i, '8', ledrgb[i][0], ledrgb[i][1], ledrgb[i][2]);
+ }
+
+ last_report = now;
+
+ L.adkEventProcess(); //let the adk framework do its thing
+}
diff --git a/library/ADK2/f_diskio.h b/library/ADK2/f_diskio.h
new file mode 100644
index 0000000..008cbde
--- /dev/null
+++ b/library/ADK2/f_diskio.h
@@ -0,0 +1,80 @@
+#ifdef ADK_INTERNAL
+/*-----------------------------------------------------------------------
+/ Low level disk interface modlue include file
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO
+
+#define _READONLY 0 /* 1: Remove write functions */
+#define _USE_IOCTL 1 /* 1: Use disk_ioctl fucntion */
+
+#include "f_integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE DSTATUS;
+
+/* Results of Disk Functions */
+typedef enum {
+ RES_OK = 0, /* 0: Successful */
+ RES_ERROR, /* 1: R/W Error */
+ RES_WRPRT, /* 2: Write Protected */
+ RES_NOTRDY, /* 3: Not Ready */
+ RES_PARERR /* 4: Invalid Parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+DSTATUS disk_initialize (BYTE);
+DSTATUS disk_status (BYTE);
+DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
+#if _READONLY == 0
+DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
+#endif
+DRESULT disk_ioctl (BYTE, BYTE, void*);
+
+
+
+/* Disk Status Bits (DSTATUS) */
+
+#define STA_NOINIT 0x01 /* Drive not initialized */
+#define STA_NODISK 0x02 /* No medium in the drive */
+#define STA_PROTECT 0x04 /* Write protected */
+
+
+/* Command code for disk_ioctrl fucntion */
+
+/* Generic command (defined for FatFs) */
+#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */
+#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */
+#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
+#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */
+#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */
+
+/* Generic command */
+#define CTRL_POWER 5 /* Get/Set power status */
+#define CTRL_LOCK 6 /* Lock/Unlock media removal */
+#define CTRL_EJECT 7 /* Eject media */
+
+/* MMC/SDC specific ioctl command */
+#define MMC_GET_TYPE 10 /* Get card type */
+#define MMC_GET_CSD 11 /* Get CSD */
+#define MMC_GET_CID 12 /* Get CID */
+#define MMC_GET_OCR 13 /* Get OCR */
+#define MMC_GET_SDSTAT 14 /* Get SD status */
+
+/* ATA/CF specific ioctl command */
+#define ATA_GET_REV 20 /* Get F/W revision */
+#define ATA_GET_MODEL 21 /* Get model name */
+#define ATA_GET_SN 22 /* Get serial number */
+
+/* NAND specific ioctl command */
+#define NAND_FORMAT 30 /* Create physical format */
+
+
+#define _DISKIO
+#endif
+#endif
+
diff --git a/library/ADK2/f_ff.c b/library/ADK2/f_ff.c
new file mode 100644
index 0000000..dd89e66
--- /dev/null
+++ b/library/ADK2/f_ff.c
@@ -0,0 +1,3988 @@
+#define ADK_INTERNAL
+/*----------------------------------------------------------------------------/
+/ FatFs - FAT file system module R0.08b (C)ChaN, 2011
+/-----------------------------------------------------------------------------/
+/ FatFs module is a generic FAT file system module for small embedded systems.
+/ This is a free software that opened for education, research and commercial
+/ developments under license policy of following terms.
+/
+/ Copyright (C) 2011, ChaN, all right reserved.
+/
+/ * The FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+/ Feb 26,'06 R0.00 Prototype.
+/
+/ Apr 29,'06 R0.01 First stable version.
+/
+/ Jun 01,'06 R0.02 Added FAT12 support.
+/ Removed unbuffered mode.
+/ Fixed a problem on small (<32M) partition.
+/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM).
+/
+/ Sep 22,'06 R0.03 Added f_rename().
+/ Changed option _FS_MINIMUM to _FS_MINIMIZE.
+/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast.
+/ Fixed f_mkdir() creates incorrect directory on FAT32.
+/
+/ Feb 04,'07 R0.04 Supported multiple drive system.
+/ Changed some interfaces for multiple drive system.
+/ Changed f_mountdrv() to f_mount().
+/ Added f_mkfs().
+/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive.
+/ Added a capability of extending file size to f_lseek().
+/ Added minimization level 3.
+/ Fixed an endian sensitive code in f_mkfs().
+/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG.
+/ Added FSInfo support.
+/ Fixed DBCS name can result FR_INVALID_NAME.
+/ Fixed short seek (<= csize) collapses the file object.
+/
+/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs().
+/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo.
+/ Fixed f_mkdir() on FAT32 creates incorrect directory.
+/ Feb 03,'08 R0.05a Added f_truncate() and f_utime().
+/ Fixed off by one error at FAT sub-type determination.
+/ Fixed btr in f_read() can be mistruncated.
+/ Fixed cached sector is not flushed when create and close without write.
+/
+/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets().
+/ Improved performance of f_lseek() on moving to the same or following cluster.
+/
+/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a configuration option. (_FS_TINY)
+/ Added long file name feature.
+/ Added multiple code page feature.
+/ Added re-entrancy for multitask operation.
+/ Added auto cluster size selection to f_mkfs().
+/ Added rewind option to f_readdir().
+/ Changed result code of critical errors.
+/ Renamed string functions to avoid name collision.
+/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg.
+/ Added multiple sector size feature.
+/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error.
+/ Fixed wrong cache control in f_lseek().
+/ Added relative path feature.
+/ Added f_chdir() and f_chdrive().
+/ Added proper case conversion to extended char.
+/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h.
+/ Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH.
+/ Fixed name matching error on the 13 char boundary.
+/ Added a configuration option, _LFN_UNICODE.
+/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
+/
+/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3)
+/ Added file lock feature. (_FS_SHARE)
+/ Added fast seek feature. (_USE_FASTSEEK)
+/ Changed some types on the API, XCHAR->TCHAR.
+/ Changed fname member in the FILINFO structure on Unicode cfg.
+/ String functions support UTF-8 encoding files on Unicode cfg.
+/ Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2)
+/ Added sector erase feature. (_USE_ERASE)
+/ Moved file lock semaphore table from fs object to the bss.
+/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'.
+/ Fixed f_mkfs() creates wrong FAT32 volume.
+/ Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write().
+/ f_lseek() reports required table size on creating CLMP.
+/ Extended format syntax of f_printf function.
+/ Ignores duplicated directory separators in given path names.
+/---------------------------------------------------------------------------*/
+
+#include "f_ff.h" /* FatFs configurations and declarations */
+#include "f_diskio.h" /* Declarations of low level disk I/O functions */
+
+
+/*--------------------------------------------------------------------------
+
+ Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+#if _FATFS != 8237
+#error Wrong include file (ff.h).
+#endif
+
+
+/* Definitions on sector size */
+#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096
+#error Wrong sector size.
+#endif
+#if _MAX_SS != 512
+#define SS(fs) ((fs)->ssize) /* Multiple sector size */
+#else
+#define SS(fs) 512U /* Fixed sector size */
+#endif
+
+
+/* Reentrancy related */
+#if _FS_REENTRANT
+#if _USE_LFN == 1
+#error Static LFN work area must not be used in re-entrant configuration.
+#endif
+#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; }
+#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; }
+#else
+#define ENTER_FF(fs)
+#define LEAVE_FF(fs, res) return res
+#endif
+
+#define ABORT(fs, res) { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); }
+
+
+/* File shareing feature */
+#if _FS_SHARE
+#if _FS_READONLY
+#error _FS_SHARE must be 0 on read-only cfg.
+#endif
+typedef struct {
+ FATFS *fs; /* File ID 1, volume (NULL:blank entry) */
+ DWORD clu; /* File ID 2, directory */
+ WORD idx; /* File ID 3, directory index */
+ WORD ctr; /* File open counter, 0:none, 0x01..0xFF:read open count, 0x100:write mode */
+} FILESEM;
+#endif
+
+
+/* Misc definitions */
+#define LD_CLUST(dir) (((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO))
+#define ST_CLUST(dir,cl) {ST_WORD(dir+DIR_FstClusLO, cl); ST_WORD(dir+DIR_FstClusHI, (DWORD)cl>>16);}
+
+
+#if 0 /* Removed to ff.h for application usage, by ATMEL */
+/* DBCS code ranges and SBCS extend char conversion table */
+
+#if _CODE_PAGE == 932 /* Japanese Shift-JIS */
+#define _DF1S 0x81 /* DBC 1st byte range 1 start */
+#define _DF1E 0x9F /* DBC 1st byte range 1 end */
+#define _DF2S 0xE0 /* DBC 1st byte range 2 start */
+#define _DF2E 0xFC /* DBC 1st byte range 2 end */
+#define _DS1S 0x40 /* DBC 2nd byte range 1 start */
+#define _DS1E 0x7E /* DBC 2nd byte range 1 end */
+#define _DS2S 0x80 /* DBC 2nd byte range 2 start */
+#define _DS2E 0xFC /* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */
+#define _DF1S 0x81
+#define _DF1E 0xFE
+#define _DS1S 0x40
+#define _DS1E 0x7E
+#define _DS2S 0x80
+#define _DS2E 0xFE
+
+#elif _CODE_PAGE == 949 /* Korean */
+#define _DF1S 0x81
+#define _DF1E 0xFE
+#define _DS1S 0x41
+#define _DS1E 0x5A
+#define _DS2S 0x61
+#define _DS2E 0x7A
+#define _DS3S 0x81
+#define _DS3E 0xFE
+
+#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */
+#define _DF1S 0x81
+#define _DF1E 0xFE
+#define _DS1S 0x40
+#define _DS1E 0x7E
+#define _DS2S 0xA1
+#define _DS2E 0xFE
+
+#elif _CODE_PAGE == 437 /* U.S. (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720 /* Arabic (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737 /* Greek (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+ 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775 /* Baltic (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+ 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+ 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+ 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857 /* Turkish (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862 /* Hebrew (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866 /* Russian (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+ 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+ 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */
+#if _USE_LFN
+#error Cannot use LFN feature without valid code page.
+#endif
+#define _DF1S 0
+
+#else
+#error Unknown code page
+
+#endif
+#endif
+
+/* Character code support macros */
+#define IsUpper(c) (((c)>='A')&&((c)<='Z'))
+#define IsLower(c) (((c)>='a')&&((c)<='z'))
+#define IsDigit(c) (((c)>='0')&&((c)<='9'))
+
+#if _DF1S /* Code page is DBCS */
+
+#ifdef _DF2S /* Two 1st byte areas */
+#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else /* One 1st byte area */
+#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S /* Three 2nd byte areas */
+#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else /* Two 2nd byte areas */
+#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else /* Code page is SBCS */
+
+#define IsDBCS1(c) 0
+#define IsDBCS2(c) 0
+
+#endif /* _DF1S */
+
+
+/* Name status flags */
+#define NS 11 /* Index of name status byte in fn[] */
+#define NS_LOSS 0x01 /* Out of 8.3 format */
+#define NS_LFN 0x02 /* Force to create LFN entry */
+#define NS_LAST 0x04 /* Last segment */
+#define NS_BODY 0x08 /* Lower case flag (body) */
+#define NS_EXT 0x10 /* Lower case flag (ext) */
+#define NS_DOT 0x20 /* Dot entry */
+
+
+/* FAT sub-type boundaries */
+/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */
+#define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */
+#define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */
+
+
+/* FatFs refers the members in the FAT structures as byte array instead of
+/ structure member because the structure is not binary compatible between
+/ different platforms */
+
+#define BS_jmpBoot 0 /* Jump instruction (3) */
+#define BS_OEMName 3 /* OEM name (8) */
+#define BPB_BytsPerSec 11 /* Sector size [byte] (2) */
+#define BPB_SecPerClus 13 /* Cluster size [sector] (1) */
+#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (2) */
+#define BPB_NumFATs 16 /* Number of FAT copies (1) */
+#define BPB_RootEntCnt 17 /* Number of root dir entries for FAT12/16 (2) */
+#define BPB_TotSec16 19 /* Volume size [sector] (2) */
+#define BPB_Media 21 /* Media descriptor (1) */
+#define BPB_FATSz16 22 /* FAT size [sector] (2) */
+#define BPB_SecPerTrk 24 /* Track size [sector] (2) */
+#define BPB_NumHeads 26 /* Number of heads (2) */
+#define BPB_HiddSec 28 /* Number of special hidden sectors (4) */
+#define BPB_TotSec32 32 /* Volume size [sector] (4) */
+#define BS_DrvNum 36 /* Physical drive number (2) */
+#define BS_BootSig 38 /* Extended boot signature (1) */
+#define BS_VolID 39 /* Volume serial number (4) */
+#define BS_VolLab 43 /* Volume label (8) */
+#define BS_FilSysType 54 /* File system type (1) */
+#define BPB_FATSz32 36 /* FAT size [sector] (4) */
+#define BPB_ExtFlags 40 /* Extended flags (2) */
+#define BPB_FSVer 42 /* File system version (2) */
+#define BPB_RootClus 44 /* Root dir first cluster (4) */
+#define BPB_FSInfo 48 /* Offset of FSInfo sector (2) */
+#define BPB_BkBootSec 50 /* Offset of backup boot sectot (2) */
+#define BS_DrvNum32 64 /* Physical drive number (2) */
+#define BS_BootSig32 66 /* Extended boot signature (1) */
+#define BS_VolID32 67 /* Volume serial number (4) */
+#define BS_VolLab32 71 /* Volume label (8) */
+#define BS_FilSysType32 82 /* File system type (1) */
+#define FSI_LeadSig 0 /* FSI: Leading signature (4) */
+#define FSI_StrucSig 484 /* FSI: Structure signature (4) */
+#define FSI_Free_Count 488 /* FSI: Number of free clusters (4) */
+#define FSI_Nxt_Free 492 /* FSI: Last allocated cluster (4) */
+#define MBR_Table 446 /* MBR: Partition table offset (2) */
+#define SZ_PTE 16 /* MBR: Size of a partition table entry */
+#define BS_55AA 510 /* Boot sector signature (2) */
+
+#define DIR_Name 0 /* Short file name (11) */
+#define DIR_Attr 11 /* Attribute (1) */
+#define DIR_NTres 12 /* NT flag (1) */
+#define DIR_CrtTime 14 /* Created time (2) */
+#define DIR_CrtDate 16 /* Created date (2) */
+#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (2) */
+#define DIR_WrtTime 22 /* Modified time (2) */
+#define DIR_WrtDate 24 /* Modified date (2) */
+#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (2) */
+#define DIR_FileSize 28 /* File size (4) */
+#define LDIR_Ord 0 /* LFN entry order and LLE flag (1) */
+#define LDIR_Attr 11 /* LFN attribute (1) */
+#define LDIR_Type 12 /* LFN type (1) */
+#define LDIR_Chksum 13 /* Sum of corresponding SFN entry */
+#define LDIR_FstClusLO 26 /* Filled by zero (0) */
+#define SZ_DIR 32 /* Size of a directory entry */
+#define LLE 0x40 /* Last long entry flag in LDIR_Ord */
+#define DDE 0xE5 /* Deleted directory enrty mark in DIR_Name[0] */
+#define NDDE 0x05 /* Replacement of a character collides with DDE */
+
+
+/*------------------------------------------------------------*/
+/* Work area */
+
+#if _VOLUMES
+static
+FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */
+#else
+#error Number of drives must not be 0.
+#endif
+
+static
+WORD Fsid; /* File system mount ID */
+
+#if _FS_RPATH
+static
+BYTE CurrVol; /* Current drive */
+#endif
+
+#if _FS_SHARE
+static
+FILESEM Files[_FS_SHARE]; /* File lock semaphores */
+#endif
+
+#if _USE_LFN == 0 /* No LFN */
+#define DEF_NAMEBUF BYTE sfn[12]
+#define INIT_BUF(dobj) (dobj).fn = sfn
+#define FREE_BUF()
+
+#elif _USE_LFN == 1 /* LFN with static LFN working buffer */
+static WCHAR LfnBuf[_MAX_LFN+1];
+#define DEF_NAMEBUF BYTE sfn[12]
+#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; }
+#define FREE_BUF()
+
+#elif _USE_LFN == 2 /* LFN with dynamic LFN working buffer on the stack */
+#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1]
+#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; }
+#define FREE_BUF()
+
+#elif _USE_LFN == 3 /* LFN with dynamic LFN working buffer on the heap */
+#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn
+#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \
+ if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \
+ (dobj).lfn = lfn; (dobj).fn = sfn; }
+#define FREE_BUF() ff_memfree(lfn)
+
+#else
+#error Wrong LFN configuration.
+#endif
+
+
+
+
+/*--------------------------------------------------------------------------
+
+ Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------------------*/
+/* String functions */
+/*-----------------------------------------------------------------------*/
+
+/* Copy memory to memory */
+static
+void mem_cpy (void* dst, const void* src, UINT cnt) {
+ BYTE *d = (BYTE*)dst;
+ const BYTE *s = (const BYTE*)src;
+
+#if _WORD_ACCESS == 1
+ while (cnt >= sizeof(int)) {
+ *(int*)d = *(int*)s;
+ d += sizeof(int); s += sizeof(int);
+ cnt -= sizeof(int);
+ }
+#endif
+ while (cnt--)
+ *d++ = *s++;
+}
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, UINT cnt) {
+ BYTE *d = (BYTE*)dst;
+
+ while (cnt--)
+ *d++ = (BYTE)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, UINT cnt) {
+ const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
+ int r = 0;
+
+ while (cnt-- && (r = *d++ - *s++) == 0) ;
+ return r;
+}
+
+/* Check if chr is contained in the string */
+static
+int chk_chr (const char* str, int chr) {
+ while (*str && *str != chr) str++;
+ return *str;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Request/Release grant to access the volume */
+/*-----------------------------------------------------------------------*/
+#if _FS_REENTRANT
+
+static
+int lock_fs (
+ FATFS *fs /* File system object */
+)
+{
+ return ff_req_grant(fs->sobj);
+}
+
+
+static
+void unlock_fs (
+ FATFS *fs, /* File system object */
+ FRESULT res /* Result code to be returned */
+)
+{
+ if (res != FR_NOT_ENABLED &&
+ res != FR_INVALID_DRIVE &&
+ res != FR_INVALID_OBJECT &&
+ res != FR_TIMEOUT) {
+ ff_rel_grant(fs->sobj);
+ }
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* File shareing control functions */
+/*-----------------------------------------------------------------------*/
+#if _FS_SHARE
+
+static
+FRESULT chk_lock ( /* Check if the file can be accessed */
+ DIR* dj, /* Directory object pointing the file to be checked */
+ int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+ UINT i, be;
+
+ /* Search file semaphore table */
+ for (i = be = 0; i < _FS_SHARE; i++) {
+ if (Files[i].fs) { /* Existing entry */
+ if (Files[i].fs == dj->fs && /* Check if the file matched with an open file */
+ Files[i].clu == dj->sclust &&
+ Files[i].idx == dj->index) break;
+ } else { /* Blank entry */
+ be++;
+ }
+ }
+ if (i == _FS_SHARE) /* The file is not opened */
+ return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new file? */
+
+ /* The file has been opened. Reject any open against writing file and all write mode open */
+ return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
+}
+
+
+static
+int enq_lock ( /* Check if an entry is available for a new file */
+ FATFS* fs /* File system object */
+)
+{
+ UINT i;
+
+ for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ;
+ return (i == _FS_SHARE) ? 0 : 1;
+}
+
+
+static
+UINT inc_lock ( /* Increment file open counter and returns its index (0:int error) */
+ DIR* dj, /* Directory object pointing the file to register or increment */
+ int acc /* Desired access mode (0:Read, !0:Write) */
+)
+{
+ UINT i;
+
+
+ for (i = 0; i < _FS_SHARE; i++) { /* Find the file */
+ if (Files[i].fs == dj->fs &&
+ Files[i].clu == dj->sclust &&
+ Files[i].idx == dj->index) break;
+ }
+
+ if (i == _FS_SHARE) { /* Not opened. Register it as new. */
+ for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ;
+ if (i == _FS_SHARE) return 0; /* No space to register (int err) */
+ Files[i].fs = dj->fs;
+ Files[i].clu = dj->sclust;
+ Files[i].idx = dj->index;
+ Files[i].ctr = 0;
+ }
+
+ if (acc && Files[i].ctr) return 0; /* Access violation (int err) */
+
+ Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */
+
+ return i + 1;
+}
+
+
+static
+FRESULT dec_lock ( /* Decrement file open counter */
+ UINT i /* Semaphore index */
+)
+{
+ WORD n;
+ FRESULT res;
+
+
+ if (--i < _FS_SHARE) {
+ n = Files[i].ctr;
+ if (n == 0x100) n = 0;
+ if (n) n--;
+ Files[i].ctr = n;
+ if (!n) Files[i].fs = 0;
+ res = FR_OK;
+ } else {
+ res = FR_INT_ERR;
+ }
+ return res;
+}
+
+
+static
+void clear_lock ( /* Clear lock entries of the volume */
+ FATFS *fs
+)
+{
+ UINT i;
+
+ for (i = 0; i < _FS_SHARE; i++) {
+ if (Files[i].fs == fs) Files[i].fs = 0;
+ }
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change window offset */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT move_window (
+ FATFS *fs, /* File system object */
+ DWORD sector /* Sector number to make appearance in the fs->win[] */
+) /* Move to zero only writes back dirty window */
+{
+ DWORD wsect;
+
+
+ wsect = fs->winsect;
+ if (wsect != sector) { /* Changed current window */
+#if !_FS_READONLY
+ if (fs->wflag) { /* Write back dirty window if needed */
+ if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK)
+ return FR_DISK_ERR;
+ fs->wflag = 0;
+ if (wsect < (fs->fatbase + fs->fsize)) { /* In FAT area */
+ BYTE nf;
+ for (nf = fs->n_fats; nf > 1; nf--) { /* Reflect the change to all FAT copies */
+ wsect += fs->fsize;
+ disk_write(fs->drv, fs->win, wsect, 1);
+ }
+ }
+ }
+#endif
+ if (sector) {
+ if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK)
+ return FR_DISK_ERR;
+ fs->winsect = sector;
+ }
+ }
+
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Clean-up cached data */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT sync ( /* FR_OK: successful, FR_DISK_ERR: failed */
+ FATFS *fs /* File system object */
+)
+{
+ FRESULT res;
+
+
+ res = move_window(fs, 0);
+ if (res == FR_OK) {
+ /* Update FSInfo sector if needed */
+ if (fs->fs_type == FS_FAT32 && fs->fsi_flag) {
+ fs->winsect = 0;
+ /* Create FSInfo structure */
+ mem_set(fs->win, 0, 512);
+ ST_WORD(fs->win+BS_55AA, 0xAA55);
+ ST_DWORD(fs->win+FSI_LeadSig, 0x41615252);
+ ST_DWORD(fs->win+FSI_StrucSig, 0x61417272);
+ ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust);
+ ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust);
+ /* Write it into the FSInfo sector */
+ disk_write(fs->drv, fs->win, fs->fsi_sector, 1);
+ fs->fsi_flag = 0;
+ }
+ /* Make sure that no pending write process in the physical drive */
+ if (disk_ioctl(fs->drv, CTRL_SYNC, (void*)0) != RES_OK)
+ res = FR_DISK_ERR;
+ }
+
+ return res;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster# */
+/*-----------------------------------------------------------------------*/
+
+
+DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */
+ FATFS *fs, /* File system object */
+ DWORD clst /* Cluster# to be converted */
+)
+{
+ clst -= 2;
+ if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */
+ return clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry */
+/*-----------------------------------------------------------------------*/
+
+
+DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */
+ FATFS *fs, /* File system object */
+ DWORD clst /* Cluster# to get the link information */
+)
+{
+ UINT wc, bc;
+ BYTE *p;
+
+
+ if (clst < 2 || clst >= fs->n_fatent) /* Chack range */
+ return 1;
+
+ switch (fs->fs_type) {
+ case FS_FAT12 :
+ bc = (UINT)clst; bc += bc / 2;
+ if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
+ wc = fs->win[bc % SS(fs)]; bc++;
+ if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
+ wc |= fs->win[bc % SS(fs)] << 8;
+ return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+
+ case FS_FAT16 :
+ if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break;
+ p = &fs->win[clst * 2 % SS(fs)];
+ return LD_WORD(p);
+
+ case FS_FAT32 :
+ if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break;
+ p = &fs->win[clst * 4 % SS(fs)];
+ return LD_DWORD(p) & 0x0FFFFFFF;
+ }
+
+ return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Change value of a FAT entry */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+
+FRESULT put_fat (
+ FATFS *fs, /* File system object */
+ DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */
+ DWORD val /* New value to mark the cluster */
+)
+{
+ UINT bc;
+ BYTE *p;
+ FRESULT res;
+
+
+ if (clst < 2 || clst >= fs->n_fatent) { /* Check range */
+ res = FR_INT_ERR;
+
+ } else {
+ switch (fs->fs_type) {
+ case FS_FAT12 :
+ bc = clst; bc += bc / 2;
+ res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+ if (res != FR_OK) break;
+ p = &fs->win[bc % SS(fs)];
+ *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+ bc++;
+ fs->wflag = 1;
+ res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+ if (res != FR_OK) break;
+ p = &fs->win[bc % SS(fs)];
+ *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
+ break;
+
+ case FS_FAT16 :
+ res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
+ if (res != FR_OK) break;
+ p = &fs->win[clst * 2 % SS(fs)];
+ ST_WORD(p, (WORD)val);
+ break;
+
+ case FS_FAT32 :
+ res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
+ if (res != FR_OK) break;
+ p = &fs->win[clst * 4 % SS(fs)];
+ val |= LD_DWORD(p) & 0xF0000000;
+ ST_DWORD(p, val);
+ break;
+
+ default :
+ res = FR_INT_ERR;
+ }
+ fs->wflag = 1;
+ }
+
+ return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Remove a cluster chain */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT remove_chain (
+ FATFS *fs, /* File system object */
+ DWORD clst /* Cluster# to remove a chain from */
+)
+{
+ FRESULT res;
+ DWORD nxt;
+#if _USE_ERASE
+ DWORD scl = clst, ecl = clst, resion[2];
+#endif
+
+ if (clst < 2 || clst >= fs->n_fatent) { /* Check range */
+ res = FR_INT_ERR;
+
+ } else {
+ res = FR_OK;
+ while (clst < fs->n_fatent) { /* Not a last link? */
+ nxt = get_fat(fs, clst); /* Get cluster status */
+ if (nxt == 0) break; /* Empty cluster? */
+ if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */
+ if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */
+ res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */
+ if (res != FR_OK) break;
+ if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */
+ fs->free_clust++;
+ fs->fsi_flag = 1;
+ }
+#if _USE_ERASE
+ if (ecl + 1 == nxt) { /* Next cluster is contiguous */
+ ecl = nxt;
+ } else { /* End of contiguous clusters */
+ resion[0] = clust2sect(fs, scl); /* Start sector */
+ resion[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */
+ disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, resion); /* Erase the block */
+ scl = ecl = nxt;
+ }
+#endif
+ clst = nxt; /* Next cluster */
+ }
+ }
+
+ return res;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Stretch or Create a cluster chain */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
+ FATFS *fs, /* File system object */
+ DWORD clst /* Cluster# to stretch. 0 means create a new chain. */
+)
+{
+ DWORD cs, ncl, scl;
+ FRESULT res;
+
+
+ if (clst == 0) { /* Create a new chain */
+ scl = fs->last_clust; /* Get suggested start point */
+ if (!scl || scl >= fs->n_fatent) scl = 1;
+ }
+ else { /* Stretch the current chain */
+ cs = get_fat(fs, clst); /* Check the cluster status */
+ if (cs < 2) return 1; /* It is an invalid cluster */
+ if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */
+ scl = clst;
+ }
+
+ ncl = scl; /* Start cluster */
+ for (;;) {
+ ncl++; /* Next cluster */
+ if (ncl >= fs->n_fatent) { /* Wrap around */
+ ncl = 2;
+ if (ncl > scl) return 0; /* No free cluster */
+ }
+ cs = get_fat(fs, ncl); /* Get the cluster status */
+ if (cs == 0) break; /* Found a free cluster */
+ if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */
+ return cs;
+ if (ncl == scl) return 0; /* No free cluster */
+ }
+
+ res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */
+ if (res == FR_OK && clst != 0) {
+ res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */
+ }
+ if (res == FR_OK) {
+ fs->last_clust = ncl; /* Update FSINFO */
+ if (fs->free_clust != 0xFFFFFFFF) {
+ fs->free_clust--;
+ fs->fsi_flag = 1;
+ }
+ } else {
+ ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;
+ }
+
+ return ncl; /* Return new cluster number or error code */
+}
+#endif /* !_FS_READONLY */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Convert offset into cluster with link map table */
+/*-----------------------------------------------------------------------*/
+
+#if _USE_FASTSEEK
+static
+DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */
+ FIL* fp, /* Pointer to the file object */
+ DWORD ofs /* File offset to be converted to cluster# */
+)
+{
+ DWORD cl, ncl, *tbl;
+
+
+ tbl = fp->cltbl + 1; /* Top of CLMT */
+ cl = ofs / SS(fp->fs) / fp->fs->csize; /* Cluster order from top of the file */
+ for (;;) {
+ ncl = *tbl++; /* Number of cluters in the fragment */
+ if (!ncl) return 0; /* End of table? (error) */
+ if (cl < ncl) break; /* In this fragment? */
+ cl -= ncl; tbl++; /* Next fragment */
+ }
+ return cl + *tbl; /* Return the cluster number */
+}
+#endif /* _USE_FASTSEEK */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Set directory index */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_sdi (
+ DIR *dj, /* Pointer to directory object */
+ WORD idx /* Directory index number */
+)
+{
+ DWORD clst;
+ WORD ic;
+
+
+ dj->index = idx;
+ clst = dj->sclust;
+ if (clst == 1 || clst >= dj->fs->n_fatent) /* Check start cluster range */
+ return FR_INT_ERR;
+ if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */
+ clst = dj->fs->dirbase;
+
+ if (clst == 0) { /* Static table (root-dir in FAT12/16) */
+ dj->clust = clst;
+ if (idx >= dj->fs->n_rootdir) /* Index is out of range */
+ return FR_INT_ERR;
+ dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */
+ }
+ else { /* Dynamic table (sub-dirs or root-dir in FAT32) */
+ ic = SS(dj->fs) / SZ_DIR * dj->fs->csize; /* Entries per cluster */
+ while (idx >= ic) { /* Follow cluster chain */
+ clst = get_fat(dj->fs, clst); /* Get next cluster */
+ if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
+ if (clst < 2 || clst >= dj->fs->n_fatent) /* Reached to end of table or int error */
+ return FR_INT_ERR;
+ idx -= ic;
+ }
+ dj->clust = clst;
+ dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */
+ }
+
+ dj->dir = dj->fs->win + (idx % (SS(dj->fs) / SZ_DIR)) * SZ_DIR; /* Ptr to the entry in the sector */
+
+ return FR_OK; /* Seek succeeded */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory index next */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not stretch */
+ DIR *dj, /* Pointer to directory object */
+ int stretch /* 0: Do not stretch table, 1: Stretch table if needed */
+)
+{
+ DWORD clst;
+ WORD i;
+
+
+ i = dj->index + 1;
+ if (!i || !dj->sect) /* Report EOT when index has reached 65535 */
+ return FR_NO_FILE;
+
+ if (!(i % (SS(dj->fs) / SZ_DIR))) { /* Sector changed? */
+ dj->sect++; /* Next sector */
+
+ if (dj->clust == 0) { /* Static table */
+ if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */
+ return FR_NO_FILE;
+ }
+ else { /* Dynamic table */
+ if (((i / (SS(dj->fs) / SZ_DIR)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */
+ clst = get_fat(dj->fs, dj->clust); /* Get next cluster */
+ if (clst <= 1) return FR_INT_ERR;
+ if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
+ if (clst >= dj->fs->n_fatent) { /* When it reached end of dynamic table */
+#if !_FS_READONLY
+ BYTE c;
+ if (!stretch) return FR_NO_FILE; /* When do not stretch, report EOT */
+ clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */
+ if (clst == 0) return FR_DENIED; /* No free cluster */
+ if (clst == 1) return FR_INT_ERR;
+ if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
+ /* Clean-up stretched table */
+ if (move_window(dj->fs, 0)) return FR_DISK_ERR; /* Flush active window */
+ mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */
+ dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */
+ for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */
+ dj->fs->wflag = 1;
+ if (move_window(dj->fs, 0)) return FR_DISK_ERR;
+ dj->fs->winsect++;
+ }
+ dj->fs->winsect -= c; /* Rewind window address */
+#else
+ return FR_NO_FILE; /* Report EOT */
+#endif
+ }
+ dj->clust = clst; /* Initialize data for new cluster */
+ dj->sect = clust2sect(dj->fs, clst);
+ }
+ }
+ }
+
+ dj->index = i;
+ dj->dir = dj->fs->win + (i % (SS(dj->fs) / SZ_DIR)) * SZ_DIR;
+
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN chars in the directory entry */
+
+
+static
+int cmp_lfn ( /* 1:Matched, 0:Not matched */
+ WCHAR *lfnbuf, /* Pointer to the LFN to be compared */
+ BYTE *dir /* Pointer to the directory entry containing a part of LFN */
+)
+{
+ UINT i, s;
+ WCHAR wc, uc;
+
+
+ i = ((dir[LDIR_Ord] & ~LLE) - 1) * 13; /* Get offset in the LFN buffer */
+ s = 0; wc = 1;
+ do {
+ uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */
+ if (wc) { /* Last char has not been processed */
+ wc = ff_wtoupper(uc); /* Convert it to upper case */
+ if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */
+ return 0; /* Not matched */
+ } else {
+ if (uc != 0xFFFF) return 0; /* Check filler */
+ }
+ } while (++s < 13); /* Repeat until all chars in the entry are checked */
+
+ if ((dir[LDIR_Ord] & LLE) && wc && lfnbuf[i]) /* Last segment matched but different length */
+ return 0;
+
+ return 1; /* The part of LFN matched */
+}
+
+
+
+static
+int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */
+ WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */
+ BYTE *dir /* Pointer to the directory entry */
+)
+{
+ UINT i, s;
+ WCHAR wc, uc;
+
+
+ i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */
+
+ s = 0; wc = 1;
+ do {
+ uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */
+ if (wc) { /* Last char has not been processed */
+ if (i >= _MAX_LFN) return 0; /* Buffer overflow? */
+ lfnbuf[i++] = wc = uc; /* Store it */
+ } else {
+ if (uc != 0xFFFF) return 0; /* Check filler */
+ }
+ } while (++s < 13); /* Read all character in the entry */
+
+ if (dir[LDIR_Ord] & LLE) { /* Put terminator if it is the last LFN part */
+ if (i >= _MAX_LFN) return 0; /* Buffer overflow? */
+ lfnbuf[i] = 0;
+ }
+
+ return 1;
+}
+
+
+#if !_FS_READONLY
+static
+void fit_lfn (
+ const WCHAR *lfnbuf, /* Pointer to the LFN buffer */
+ BYTE *dir, /* Pointer to the directory entry */
+ BYTE ord, /* LFN order (1-20) */
+ BYTE sum /* SFN sum */
+)
+{
+ UINT i, s;
+
+
+ WCHAR wc;
+
+
+ dir[LDIR_Chksum] = sum; /* Set check sum */
+ dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */
+ dir[LDIR_Type] = 0;
+ ST_WORD(dir+LDIR_FstClusLO, 0);
+
+ i = (ord - 1) * 13; /* Get offset in the LFN buffer */
+ s = wc = 0;
+ do {
+ if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */
+ ST_WORD(dir+LfnOfs[s], wc); /* Put it */
+ if (!wc) wc = 0xFFFF; /* Padding chars following last char */
+ } while (++s < 13);
+ if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLE; /* Bottom LFN part is the start of LFN sequence */
+ dir[LDIR_Ord] = ord; /* Set the LFN order */
+}
+
+#endif
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create numbered name */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+void gen_numname (
+ BYTE *dst, /* Pointer to generated SFN */
+ const BYTE *src, /* Pointer to source SFN to be modified */
+ const WCHAR *lfn, /* Pointer to LFN */
+ WORD seq /* Sequence number */
+)
+{
+ BYTE ns[8], c;
+ UINT i, j;
+
+
+ mem_cpy(dst, src, 11);
+
+ if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */
+ do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn);
+ }
+
+ /* itoa (hexdecimal) */
+ i = 7;
+ do {
+ c = (seq % 16) + '0';
+ if (c > '9') c += 7;
+ ns[i--] = c;
+ seq /= 16;
+ } while (seq);
+ ns[i] = '~';
+
+ /* Append the number */
+ for (j = 0; j < i && dst[j] != ' '; j++) {
+ if (IsDBCS1(dst[j])) {
+ if (j == i - 1) break;
+ j++;
+ }
+ }
+ do {
+ dst[j++] = (i < 8) ? ns[i++] : ' ';
+ } while (j < 8);
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Calculate sum of an SFN */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+BYTE sum_sfn (
+ const BYTE *dir /* Ptr to directory entry */
+)
+{
+ BYTE sum = 0;
+ UINT n = 11;
+
+ do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n);
+ return sum;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+ DIR *dj /* Pointer to the directory object linked to the file name */
+)
+{
+ FRESULT res;
+ BYTE c, *dir;
+#if _USE_LFN
+ BYTE a, ord, sum;
+#endif
+
+ res = dir_sdi(dj, 0); /* Rewind directory object */
+ if (res != FR_OK) return res;
+
+#if _USE_LFN
+ ord = sum = 0xFF;
+#endif
+ do {
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ dir = dj->dir; /* Ptr to the directory entry of current index */
+ c = dir[DIR_Name];
+ if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
+#if _USE_LFN /* LFN configuration */
+ a = dir[DIR_Attr] & AM_MASK;
+ if (c == DDE || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */
+ ord = 0xFF;
+ } else {
+ if (a == AM_LFN) { /* An LFN entry is found */
+ if (dj->lfn) {
+ if (c & LLE) { /* Is it start of LFN sequence? */
+ sum = dir[LDIR_Chksum];
+ c &= ~LLE; ord = c; /* LFN start order */
+ dj->lfn_idx = dj->index;
+ }
+ /* Check validity of the LFN entry and compare it with given name */
+ ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
+ }
+ } else { /* An SFN entry is found */
+ if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */
+ ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */
+ if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */
+ }
+ }
+#else /* Non LFN configuration */
+ if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+ break;
+#endif
+ res = dir_next(dj, 0); /* Next entry */
+ } while (res == FR_OK);
+
+ return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory */
+/*-----------------------------------------------------------------------*/
+#if _FS_MINIMIZE <= 1
+static
+FRESULT dir_read (
+ DIR *dj /* Pointer to the directory object that pointing the entry to be read */
+)
+{
+ FRESULT res;
+ BYTE c, *dir;
+#if _USE_LFN
+ BYTE a, ord = 0xFF, sum = 0xFF;
+#endif
+
+ res = FR_NO_FILE;
+ while (dj->sect) {
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ dir = dj->dir; /* Ptr to the directory entry of current index */
+ c = dir[DIR_Name];
+ if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
+#if _USE_LFN /* LFN configuration */
+ a = dir[DIR_Attr] & AM_MASK;
+ if (c == DDE || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */
+ ord = 0xFF;
+ } else {
+ if (a == AM_LFN) { /* An LFN entry is found */
+ if (c & LLE) { /* Is it start of LFN sequence? */
+ sum = dir[LDIR_Chksum];
+ c &= ~LLE; ord = c;
+ dj->lfn_idx = dj->index;
+ }
+ /* Check LFN validity and capture it */
+ ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
+ } else { /* An SFN entry is found */
+ if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */
+ dj->lfn_idx = 0xFFFF; /* It has no LFN. */
+ break;
+ }
+ }
+#else /* Non LFN configuration */
+ if (c != DDE && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */
+ break;
+#endif
+ res = dir_next(dj, 0); /* Next entry */
+ if (res != FR_OK) break;
+ }
+
+ if (res != FR_OK) dj->sect = 0;
+
+ return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Register an object to the directory */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */
+ DIR *dj /* Target directory with object name to be created */
+)
+{
+ FRESULT res;
+ BYTE c, *dir;
+#if _USE_LFN /* LFN configuration */
+ WORD n, ne, is;
+ BYTE sn[12], *fn, sum;
+ WCHAR *lfn;
+
+
+ fn = dj->fn; lfn = dj->lfn;
+ mem_cpy(sn, fn, 12);
+
+ if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */
+ return FR_INVALID_NAME;
+
+ if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */
+ fn[NS] = 0; dj->lfn = 0; /* Find only SFN */
+ for (n = 1; n < 100; n++) {
+ gen_numname(fn, sn, lfn, n); /* Generate a numbered name */
+ res = dir_find(dj); /* Check if the name collides with existing SFN */
+ if (res != FR_OK) break;
+ }
+ if (n == 100) return FR_DENIED; /* Abort if too many collisions */
+ if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */
+ fn[NS] = sn[NS]; dj->lfn = lfn;
+ }
+
+ if (sn[NS] & NS_LFN) { /* When LFN is to be created, reserve an SFN + LFN entries. */
+ for (ne = 0; lfn[ne]; ne++) ;
+ ne = (ne + 25) / 13;
+ } else { /* Otherwise reserve only an SFN entry. */
+ ne = 1;
+ }
+
+ /* Reserve contiguous entries */
+ res = dir_sdi(dj, 0);
+ if (res != FR_OK) return res;
+ n = is = 0;
+ do {
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ c = *dj->dir; /* Check the entry status */
+ if (c == DDE || c == 0) { /* Is it a blank entry? */
+ if (n == 0) is = dj->index; /* First index of the contiguous entry */
+ if (++n == ne) break; /* A contiguous entry that required count is found */
+ } else {
+ n = 0; /* Not a blank entry. Restart to search */
+ }
+ res = dir_next(dj, 1); /* Next entry with table stretch */
+ } while (res == FR_OK);
+
+ if (res == FR_OK && ne > 1) { /* Initialize LFN entry if needed */
+ res = dir_sdi(dj, is);
+ if (res == FR_OK) {
+ sum = sum_sfn(dj->fn); /* Sum of the SFN tied to the LFN */
+ ne--;
+ do { /* Store LFN entries in bottom first */
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum);
+ dj->fs->wflag = 1;
+ res = dir_next(dj, 0); /* Next entry */
+ } while (res == FR_OK && --ne);
+ }
+ }
+
+#else /* Non LFN configuration */
+ res = dir_sdi(dj, 0);
+ if (res == FR_OK) {
+ do { /* Find a blank entry for the SFN */
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ c = *dj->dir;
+ if (c == DDE || c == 0) break; /* Is it a blank entry? */
+ res = dir_next(dj, 1); /* Next entry with table stretch */
+ } while (res == FR_OK);
+ }
+#endif
+
+ if (res == FR_OK) { /* Initialize the SFN entry */
+ res = move_window(dj->fs, dj->sect);
+ if (res == FR_OK) {
+ dir = dj->dir;
+ mem_set(dir, 0, SZ_DIR); /* Clean the entry */
+ mem_cpy(dir, dj->fn, 11); /* Put SFN */
+#if _USE_LFN
+ dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */
+#endif
+ dj->fs->wflag = 1;
+ }
+ }
+
+ return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Remove an object from the directory */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY && !_FS_MINIMIZE
+static
+FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */
+ DIR *dj /* Directory object pointing the entry to be removed */
+)
+{
+ FRESULT res;
+#if _USE_LFN /* LFN configuration */
+ WORD i;
+
+ i = dj->index; /* SFN index */
+ res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of the LFN entries */
+ if (res == FR_OK) {
+ do {
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ *dj->dir = DDE; /* Mark the entry "deleted" */
+ dj->fs->wflag = 1;
+ if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */
+ res = dir_next(dj, 0); /* Next entry */
+ } while (res == FR_OK);
+ if (res == FR_NO_FILE) res = FR_INT_ERR;
+ }
+
+#else /* Non LFN configuration */
+ res = dir_sdi(dj, dj->index);
+ if (res == FR_OK) {
+ res = move_window(dj->fs, dj->sect);
+ if (res == FR_OK) {
+ *dj->dir = DDE; /* Mark the entry "deleted" */
+ dj->fs->wflag = 1;
+ }
+ }
+#endif
+
+ return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT create_name (
+ DIR *dj, /* Pointer to the directory object */
+ const TCHAR **path /* Pointer to pointer to the segment in the path string */
+)
+{
+#ifdef _EXCVT
+ static const BYTE excvt[] = _EXCVT; /* Upper conversion table for extended chars */
+#endif
+
+#if _USE_LFN /* LFN configuration */
+ BYTE b, cf;
+ WCHAR w, *lfn;
+ UINT i, ni, si, di;
+ const TCHAR *p;
+
+ /* Create LFN in Unicode */
+ for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */
+ lfn = dj->lfn;
+ si = di = 0;
+ for (;;) {
+ w = p[si++]; /* Get a character */
+ if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */
+ if (di >= _MAX_LFN) /* Reject too long name */
+ return FR_INVALID_NAME;
+#if !_LFN_UNICODE
+ w &= 0xFF;
+ if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+ b = (BYTE)p[si++]; /* Get 2nd byte */
+ if (!IsDBCS2(b))
+ return FR_INVALID_NAME; /* Reject invalid sequence */
+ else /* Added by ATMEL, remove warnings */
+ w = (w << 8) + b; /* Create a DBC */
+ }
+ w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */
+ if (!w) return FR_INVALID_NAME; /* Reject invalid code */
+#endif
+ if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */
+ return FR_INVALID_NAME;
+ lfn[di++] = w; /* Store the Unicode char */
+ }
+ *path = &p[si]; /* Return pointer to the next segment */
+ cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */
+#if _FS_RPATH
+ if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */
+ (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) {
+ lfn[di] = 0;
+ for (i = 0; i < 11; i++)
+ dj->fn[i] = (i < di) ? '.' : ' ';
+ dj->fn[i] = cf | NS_DOT; /* This is a dot entry */
+ return FR_OK;
+ }
+#endif
+ while (di) { /* Strip trailing spaces and dots */
+ w = lfn[di-1];
+ if (w != ' ' && w != '.') break;
+ di--;
+ }
+ if (!di) return FR_INVALID_NAME; /* Reject nul string */
+
+ lfn[di] = 0; /* LFN is created */
+
+ /* Create SFN in directory form */
+ mem_set(dj->fn, ' ', 11);
+ for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */
+ if (si) cf |= NS_LOSS | NS_LFN;
+ while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */
+
+ b = i = 0; ni = 8;
+ for (;;) {
+ w = lfn[si++]; /* Get an LFN char */
+ if (!w) break; /* Break on end of the LFN */
+ if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */
+ cf |= NS_LOSS | NS_LFN; continue;
+ }
+
+ if (i >= ni || si == di) { /* Extension or end of SFN */
+ if (ni == 11) { /* Long extension */
+ cf |= NS_LOSS | NS_LFN; break;
+ }
+ if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */
+ if (si > di) break; /* No extension */
+ si = di; i = 8; ni = 11; /* Enter extension section */
+ b <<= 2; continue;
+ }
+
+ if (w >= 0x80) { /* Non ASCII char */
+
+#ifdef _EXCVT
+ w = ff_convert(w, 0); /* Unicode -> OEM code */
+ if (w) w = excvt[w - 0x80]; /* Convert extended char to upper (SBCS) */
+#else
+ w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */
+#endif
+ cf |= NS_LFN; /* Force create LFN entry */
+ }
+
+ if (_DF1S && w >= 0x100) { /* Double byte char (always false on SBCS cfg) */
+ if (i >= ni - 1) {
+ cf |= NS_LOSS | NS_LFN; i = ni; continue;
+ }
+ dj->fn[i++] = (BYTE)(w >> 8);
+ } else { /* Single byte char */
+ if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal chars for SFN */
+ w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
+ } else {
+ if (IsUpper(w)) { /* ASCII large capital */
+ b |= 2;
+ } else {
+ if (IsLower(w)) { /* ASCII small capital */
+ b |= 1; w -= 0x20;
+ }
+ }
+ }
+ }
+ dj->fn[i++] = (BYTE)w;
+ }
+
+ if (dj->fn[0] == DDE) dj->fn[0] = NDDE; /* If the first char collides with deleted mark, replace it with 0x05 */
+
+ if (ni == 8) b <<= 2;
+ if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */
+ cf |= NS_LFN;
+ if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are created */
+ if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */
+ if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */
+ }
+
+ dj->fn[NS] = cf; /* SFN is created */
+
+ return FR_OK;
+
+
+#else /* Non-LFN configuration */
+ BYTE b, c, d, *sfn;
+ UINT ni, si, i;
+ const char *p;
+
+ /* Create file name in directory form */
+ for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */
+ sfn = dj->fn;
+ mem_set(sfn, ' ', 11);
+ si = i = b = 0; ni = 8;
+#if _FS_RPATH
+ if (p[si] == '.') { /* Is this a dot entry? */
+ for (;;) {
+ c = (BYTE)p[si++];
+ if (c != '.' || si >= 3) break;
+ sfn[i++] = c;
+ }
+ if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
+ *path = &p[si]; /* Return pointer to the next segment */
+ sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */
+ return FR_OK;
+ }
+#endif
+ for (;;) {
+ c = (BYTE)p[si++];
+ if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */
+ if (c == '.' || i >= ni) {
+ if (ni != 8 || c != '.') return FR_INVALID_NAME;
+ i = 8; ni = 11;
+ b <<= 2; continue;
+ }
+ if (c >= 0x80) { /* Extended char? */
+ b |= 3; /* Eliminate NT flag */
+#ifdef _EXCVT
+ c = excvt[c-0x80]; /* Upper conversion (SBCS) */
+#else
+#if !_DF1S /* ASCII only cfg */
+ return FR_INVALID_NAME;
+#endif
+#endif
+ }
+ if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+ d = (BYTE)p[si++]; /* Get 2nd byte */
+ if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */
+ return FR_INVALID_NAME;
+ sfn[i++] = c;
+ sfn[i++] = d;
+ } else { /* Single byte code */
+ if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */
+ return FR_INVALID_NAME;
+ if (IsUpper(c)) { /* ASCII large capital? */
+ b |= 2;
+ } else {
+ if (IsLower(c)) { /* ASCII small capital? */
+ b |= 1; c -= 0x20;
+ }
+ }
+ sfn[i++] = c;
+ }
+ }
+ *path = &p[si]; /* Return pointer to the next segment */
+ c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */
+
+ if (!i) return FR_INVALID_NAME; /* Reject nul string */
+ if (sfn[0] == DDE) sfn[0] = NDDE; /* When first char collides with DDE, replace it with 0x05 */
+
+ if (ni == 8) b <<= 2;
+ if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */
+ if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */
+
+ sfn[NS] = c; /* Store NT flag, File name is created */
+
+ return FR_OK;
+#endif
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry */
+/*-----------------------------------------------------------------------*/
+#if _FS_MINIMIZE <= 1
+static
+void get_fileinfo ( /* No return code */
+ DIR *dj, /* Pointer to the directory object */
+ FILINFO *fno /* Pointer to the file information to be filled */
+)
+{
+ UINT i;
+ BYTE nt, *dir;
+ TCHAR *p, c;
+
+
+ p = fno->fname;
+ if (dj->sect) {
+ dir = dj->dir;
+ nt = dir[DIR_NTres]; /* NT flag */
+ for (i = 0; i < 8; i++) { /* Copy name body */
+ c = dir[i];
+ if (c == ' ') break;
+ if (c == NDDE) c = (TCHAR)DDE;
+ if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20;
+#if _LFN_UNICODE
+ if (IsDBCS1(c) && i < 7 && IsDBCS2(dir[i+1]))
+ c = (c << 8) | dir[++i];
+ c = ff_convert(c, 1);
+ if (!c) c = '?';
+#endif
+ *p++ = c;
+ }
+ if (dir[8] != ' ') { /* Copy name extension */
+ *p++ = '.';
+ for (i = 8; i < 11; i++) {
+ c = dir[i];
+ if (c == ' ') break;
+ if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20;
+#if _LFN_UNICODE
+ if (IsDBCS1(c) && i < 10 && IsDBCS2(dir[i+1]))
+ c = (c << 8) | dir[++i];
+ c = ff_convert(c, 1);
+ if (!c) c = '?';
+#endif
+ *p++ = c;
+ }
+ }
+ fno->fattrib = dir[DIR_Attr]; /* Attribute */
+ fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */
+ fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */
+ fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */
+ }
+ *p = 0; /* Terminate SFN str by a \0 */
+
+#if _USE_LFN
+ if (fno->lfname && fno->lfsize) {
+ TCHAR *tp = fno->lfname;
+ WCHAR w, *lfn;
+
+ i = 0;
+ if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */
+ lfn = dj->lfn;
+ while ((w = *lfn++) != 0) { /* Get an LFN char */
+#if !_LFN_UNICODE
+ w = ff_convert(w, 0); /* Unicode -> OEM conversion */
+ if (!w) { i = 0; break; } /* Could not convert, no LFN */
+ if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */
+ tp[i++] = (TCHAR)(w >> 8);
+#endif
+ if (i >= fno->lfsize - 1) { i = 0; break; } /* Buffer overflow, no LFN */
+ tp[i++] = (TCHAR)w;
+ }
+ }
+ tp[i] = 0; /* Terminate the LFN str by a \0 */
+ }
+#endif
+}
+#endif /* _FS_MINIMIZE <= 1 */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */
+ DIR *dj, /* Directory object to return last directory and found object */
+ const TCHAR *path /* Full-path string to find a file or directory */
+)
+{
+ FRESULT res;
+ BYTE *dir, ns;
+
+
+#if _FS_RPATH
+ if (*path == '/' || *path == '\\') { /* There is a heading separator */
+ path++; dj->sclust = 0; /* Strip it and start from the root dir */
+ } else { /* No heading separator */
+ dj->sclust = dj->fs->cdir; /* Start from the current dir */
+ }
+#else
+ if (*path == '/' || *path == '\\') /* Strip heading separator if exist */
+ path++;
+ dj->sclust = 0; /* Start from the root dir */
+#endif
+
+ if ((UINT)*path < ' ') { /* Nul path means the start directory itself */
+ res = dir_sdi(dj, 0);
+ dj->dir = 0;
+
+ } else { /* Follow path */
+ for (;;) {
+ res = create_name(dj, &path); /* Get a segment */
+ if (res != FR_OK) break;
+ res = dir_find(dj); /* Find it */
+ ns = *(dj->fn+NS);
+ if (res != FR_OK) { /* Failed to find the object */
+ if (res != FR_NO_FILE) break; /* Abort if any hard error occured */
+ /* Object not found */
+ if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exit */
+ dj->sclust = 0; dj->dir = 0; /* It is the root dir */
+ res = FR_OK;
+ if (!(ns & NS_LAST)) continue;
+ } else { /* Could not find the object */
+ if (!(ns & NS_LAST)) res = FR_NO_PATH;
+ }
+ break;
+ }
+ if (ns & NS_LAST) break; /* Last segment match. Function completed. */
+ dir = dj->dir; /* There is next segment. Follow the sub directory */
+ if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
+ res = FR_NO_PATH; break;
+ }
+ dj->sclust = LD_CLUST(dir);
+ }
+ }
+
+ return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Load boot record and check if it is an FAT boot record */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs ( /* 0:The FAT BR, 1:Valid BR but not an FAT, 2:Not a BR, 3:Disk error */
+ FATFS *fs, /* File system object */
+ DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+ if (disk_read(fs->drv, fs->win, sect, 1) != RES_OK) /* Load boot record */
+ return 3;
+ if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 even if the sector size is >512) */
+ return 2;
+
+ if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */
+ return 0;
+ if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146)
+ return 0;
+
+ return 1;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file system object is valid or not */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occurred */
+ const TCHAR **path, /* Pointer to pointer to the path name (drive number) */
+ FATFS **rfs, /* Pointer to pointer to the found file system object */
+ BYTE chk_wp /* !=0: Check media write protection for write access */
+)
+{
+ BYTE fmt, b, *tbl;
+ UINT vol;
+ DSTATUS stat;
+ DWORD bsect, fasize, tsect, sysect, nclst, szbfat;
+ WORD nrsv;
+ const TCHAR *p = *path;
+ FATFS *fs;
+
+ /* Get logical drive number from the path name */
+ vol = p[0] - '0'; /* Is there a drive number? */
+ if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */
+ p += 2; *path = p; /* Return pointer to the path name */
+ } else { /* No drive number is given */
+#if _FS_RPATH
+ vol = CurrVol; /* Use current drive */
+#else
+ vol = 0; /* Use drive 0 */
+#endif
+ }
+
+ /* Check if the logical drive is valid or not */
+ if (vol >= _VOLUMES) /* Is the drive number valid? */
+ return FR_INVALID_DRIVE;
+ *rfs = fs = FatFs[vol]; /* Return pointer to the corresponding file system object */
+ if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */
+
+ ENTER_FF(fs); /* Lock file system */
+
+ if (fs->fs_type) { /* If the logical drive has been mounted */
+ stat = disk_status(fs->drv);
+ if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed), */
+#if !_FS_READONLY
+ if (chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */
+ return FR_WRITE_PROTECTED;
+#endif
+ return FR_OK; /* The file system object is valid */
+ }
+ }
+
+ /* The logical drive must be mounted. */
+ /* Following code attempts to mount a volume. (analyze BPB and initialize the fs object) */
+
+ fs->fs_type = 0; /* Clear the file system object */
+ fs->drv = (BYTE)LD2PD(vol); /* Bind the logical drive and a physical drive */
+ stat = disk_initialize(fs->drv); /* Initialize low level disk I/O layer */
+ if (stat & STA_NOINIT) /* Check if the initialization succeeded */
+ return FR_NOT_READY; /* Failed to initialize due to no media or hard error */
+#if _MAX_SS != 512 /* Get disk sector size (variable sector size cfg only) */
+ if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK)
+ return FR_DISK_ERR;
+#endif
+#if !_FS_READONLY
+ if (chk_wp && (stat & STA_PROTECT)) /* Check disk write protection if needed */
+ return FR_WRITE_PROTECTED;
+#endif
+ /* Search FAT partition on the drive. Supports only generic partitionings, FDISK and SFD. */
+ fmt = check_fs(fs, bsect = 0); /* Check sector 0 if it is a VBR */
+ if (fmt == 1) { /* Not an FAT-VBR, the disk may be partitioned */
+ /* Check the partition listed in top of the partition table */
+ tbl = &fs->win[MBR_Table + LD2PT(vol) * SZ_PTE];/* Partition table */
+ if (tbl[4]) { /* Is the partition existing? */
+ bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */
+ fmt = check_fs(fs, bsect); /* Check the partition */
+ }
+ }
+ if (fmt == 3) return FR_DISK_ERR;
+ if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */
+
+ /* Following code initializes the file system object */
+
+ if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* (BPB_BytsPerSec must be equal to the physical sector size) */
+ return FR_NO_FILESYSTEM;
+
+ fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */
+ if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32);
+ fs->fsize = fasize;
+
+ fs->n_fats = b = fs->win[BPB_NumFATs]; /* Number of FAT copies */
+ if (b != 1 && b != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */
+ fasize *= b; /* Number of sectors for FAT area */
+
+ fs->csize = b = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */
+ if (!b || (b & (b - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */
+
+ fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */
+ if (fs->n_rootdir % (SS(fs) / SZ_DIR)) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be sector aligned) */
+
+ tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */
+ if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32);
+
+ nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */
+ if (!nrsv) return FR_NO_FILESYSTEM; /* (BPB_RsvdSecCnt must not be 0) */
+
+ /* Determine the FAT sub type */
+ sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIR); /* RSV+FAT+DIR */
+ if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */
+ nclst = (tsect - sysect) / fs->csize; /* Number of clusters */
+ if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */
+ fmt = FS_FAT12;
+ if (nclst >= MIN_FAT16) fmt = FS_FAT16;
+ if (nclst >= MIN_FAT32) fmt = FS_FAT32;
+
+ /* Boundaries and Limits */
+ fs->n_fatent = nclst + 2; /* Number of FAT entries */
+ fs->database = bsect + sysect; /* Data start sector */
+ fs->fatbase = bsect + nrsv; /* FAT start sector */
+ if (fmt == FS_FAT32) {
+ if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */
+ fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */
+ szbfat = fs->n_fatent * 4; /* (Required FAT size) */
+ } else {
+ if (!fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */
+ fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */
+ szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */
+ fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+ }
+ if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (BPB_FATSz must not be less than required) */
+ return FR_NO_FILESYSTEM;
+
+#if !_FS_READONLY
+ /* Initialize cluster allocation information */
+ fs->free_clust = 0xFFFFFFFF;
+ fs->last_clust = 0;
+
+ /* Get fsinfo if available */
+ if (fmt == FS_FAT32) {
+ fs->fsi_flag = 0;
+ fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo);
+ if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK &&
+ LD_WORD(fs->win+BS_55AA) == 0xAA55 &&
+ LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 &&
+ LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) {
+ fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free);
+ fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count);
+ }
+ }
+#endif
+ fs->fs_type = fmt; /* FAT sub-type */
+ fs->id = ++Fsid; /* File system mount ID */
+ fs->winsect = 0; /* Invalidate sector cache */
+ fs->wflag = 0;
+#if _FS_RPATH
+ fs->cdir = 0; /* Current directory (root dir) */
+#endif
+#if _FS_SHARE /* Clear file lock semaphores */
+ clear_lock(fs);
+#endif
+
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file/dir object is valid or not */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */
+ FATFS *fs, /* Pointer to the file system object */
+ WORD id /* Member id of the target object to be checked */
+)
+{
+ if (!fs || !fs->fs_type || fs->id != id)
+ return FR_INVALID_OBJECT;
+
+ ENTER_FF(fs); /* Lock file system */
+
+ if (disk_status(fs->drv) & STA_NOINIT)
+ return FR_NOT_READY;
+
+ return FR_OK;
+}
+
+
+
+
+/*--------------------------------------------------------------------------
+
+ Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Logical Drive */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mount (
+ BYTE vol, /* Logical drive number to be mounted/unmounted */
+ FATFS *fs /* Pointer to new file system object (NULL for unmount)*/
+)
+{
+ FATFS *rfs;
+
+
+ if (vol >= _VOLUMES) /* Check if the drive number is valid */
+ return FR_INVALID_DRIVE;
+ rfs = FatFs[vol]; /* Get current fs object */
+
+ if (rfs) {
+#if _FS_SHARE
+ clear_lock(rfs);
+#endif
+#if _FS_REENTRANT /* Discard sync object of the current volume */
+ if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR;
+#endif
+ rfs->fs_type = 0; /* Clear old fs object */
+ }
+
+ if (fs) {
+ fs->fs_type = 0; /* Clear new fs object */
+#if _FS_REENTRANT /* Create sync object for the new volume */
+ if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR;
+#endif
+ }
+ FatFs[vol] = fs; /* Register new fs object */
+
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_open (
+ FIL *fp, /* Pointer to the blank file object */
+ const TCHAR *path, /* Pointer to the file name */
+ BYTE mode /* Access mode and file open mode flags */
+)
+{
+ FRESULT res;
+ DIR dj;
+ BYTE *dir;
+ DEF_NAMEBUF;
+
+
+ fp->fs = 0; /* Clear file object */
+
+#if !_FS_READONLY
+ mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW;
+ res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ));
+#else
+ mode &= FA_READ;
+ res = chk_mounted(&path, &dj.fs, 0);
+#endif
+ INIT_BUF(dj);
+ if (res == FR_OK)
+ res = follow_path(&dj, path); /* Follow the file path */
+ dir = dj.dir;
+
+#if !_FS_READONLY /* R/W configuration */
+ if (res == FR_OK) {
+ if (!dir) /* Current dir itself */
+ res = FR_INVALID_NAME;
+#if _FS_SHARE
+ else
+ res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+#endif
+ }
+ /* Create or Open a file */
+ if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
+ DWORD dw, cl;
+
+ if (res != FR_OK) { /* No file, create new */
+ if (res == FR_NO_FILE) /* There is no file to open, create a new entry */
+#if _FS_SHARE
+ res = enq_lock(dj.fs) ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
+#else
+ res = dir_register(&dj);
+#endif
+ mode |= FA_CREATE_ALWAYS; /* File is created */
+ dir = dj.dir; /* New entry */
+ }
+ else { /* Any object is already existing */
+ if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */
+ res = FR_DENIED;
+ } else {
+ if (mode & FA_CREATE_NEW) /* Cannot create as new file */
+ res = FR_EXIST;
+ }
+ }
+ if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */
+ dw = get_fattime(); /* Created time */
+ ST_DWORD(dir+DIR_CrtTime, dw);
+ dir[DIR_Attr] = 0; /* Reset attribute */
+ ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */
+ cl = LD_CLUST(dir); /* Get start cluster */
+ ST_CLUST(dir, 0); /* cluster = 0 */
+ dj.fs->wflag = 1;
+ if (cl) { /* Remove the cluster chain if exist */
+ dw = dj.fs->winsect;
+ res = remove_chain(dj.fs, cl);
+ if (res == FR_OK) {
+ dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */
+ res = move_window(dj.fs, dw);
+ }
+ }
+ }
+ }
+ else { /* Open an existing file */
+ if (res == FR_OK) { /* Follow succeeded */
+ if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */
+ res = FR_NO_FILE;
+ } else {
+ if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */
+ res = FR_DENIED;
+ }
+ }
+ }
+ if (res == FR_OK) {
+ if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */
+ mode |= FA__WRITTEN;
+ fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */
+ fp->dir_ptr = dir;
+#if _FS_SHARE
+ fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+ if (!fp->lockid) res = FR_INT_ERR;
+#endif
+ }
+
+#else /* R/O configuration */
+ if (res == FR_OK) { /* Follow succeeded */
+ if (!dir) { /* Current dir itself */
+ res = FR_INVALID_NAME;
+ } else {
+ if (dir[DIR_Attr] & AM_DIR) /* It is a directory */
+ res = FR_NO_FILE;
+ }
+ }
+#endif
+ FREE_BUF();
+
+ if (res == FR_OK) {
+ fp->flag = mode; /* File access mode */
+ fp->sclust = LD_CLUST(dir); /* File start cluster */
+ fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */
+ fp->fptr = 0; /* File pointer */
+ fp->dsect = 0;
+#if _USE_FASTSEEK
+ fp->cltbl = 0; /* Normal seek mode */
+#endif
+ fp->fs = dj.fs; fp->id = dj.fs->id; /* Validate file object */
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_read (
+ FIL *fp, /* Pointer to the file object */
+ void *buff, /* Pointer to data buffer */
+ UINT btr, /* Number of bytes to read */
+ UINT *br /* Pointer to number of bytes read */
+)
+{
+ FRESULT res;
+ DWORD clst, sect, remain;
+ UINT rcnt, cc;
+ BYTE csect, *rbuff = buff;
+
+
+ *br = 0; /* Initialize byte counter */
+
+ res = validate(fp->fs, fp->id); /* Check validity */
+ if (res != FR_OK) LEAVE_FF(fp->fs, res);
+ if (fp->flag & FA__ERROR) /* Aborted file? */
+ LEAVE_FF(fp->fs, FR_INT_ERR);
+ if (!(fp->flag & FA_READ)) /* Check access mode */
+ LEAVE_FF(fp->fs, FR_DENIED);
+ remain = fp->fsize - fp->fptr;
+ if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */
+
+ for ( ; btr; /* Repeat until all data read */
+ rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
+ if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
+ csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
+ if (!csect) { /* On the cluster boundary? */
+ if (fp->fptr == 0) { /* On the top of the file? */
+ clst = fp->sclust; /* Follow from the origin */
+ } else { /* Middle or end of the file */
+#if _USE_FASTSEEK
+ if (fp->cltbl)
+ clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */
+ else
+#endif
+ clst = get_fat(fp->fs, fp->clust); /* Follow cluster chain on the FAT */
+ }
+ if (clst < 2) ABORT(fp->fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ fp->clust = clst; /* Update current cluster */
+ }
+ sect = clust2sect(fp->fs, fp->clust); /* Get current sector */
+ if (!sect) ABORT(fp->fs, FR_INT_ERR);
+ sect += csect;
+ cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */
+ if (cc) { /* Read maximum contiguous sectors directly */
+ if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
+ cc = fp->fs->csize - csect;
+ if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */
+#if _FS_TINY
+ if (fp->fs->wflag && fp->fs->winsect - sect < cc)
+ mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs));
+#else
+ if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc)
+ mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs));
+#endif
+#endif
+ rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */
+ continue;
+ }
+#if !_FS_TINY
+ if (fp->dsect != sect) { /* Load data sector if not in cache */
+#if !_FS_READONLY
+ if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) /* Fill sector cache */
+ ABORT(fp->fs, FR_DISK_ERR);
+ }
+#endif
+ fp->dsect = sect;
+ }
+ rcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */
+ if (rcnt > btr) rcnt = btr;
+#if _FS_TINY
+ if (move_window(fp->fs, fp->dsect)) /* Move sector window */
+ ABORT(fp->fs, FR_DISK_ERR);
+ mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */
+#else
+ mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */
+#endif
+ }
+
+ LEAVE_FF(fp->fs, FR_OK);
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Write File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_write (
+ FIL *fp, /* Pointer to the file object */
+ const void *buff, /* Pointer to the data to be written */
+ UINT btw, /* Number of bytes to write */
+ UINT *bw /* Pointer to number of bytes written */
+)
+{
+ FRESULT res;
+ DWORD clst, sect;
+ UINT wcnt, cc;
+ const BYTE *wbuff = buff;
+ BYTE csect;
+
+
+ *bw = 0; /* Initialize byte counter */
+
+ res = validate(fp->fs, fp->id); /* Check validity */
+ if (res != FR_OK) LEAVE_FF(fp->fs, res);
+ if (fp->flag & FA__ERROR) /* Aborted file? */
+ LEAVE_FF(fp->fs, FR_INT_ERR);
+ if (!(fp->flag & FA_WRITE)) /* Check access mode */
+ LEAVE_FF(fp->fs, FR_DENIED);
+ if ((DWORD)(fp->fsize + btw) < fp->fsize) btw = 0; /* File size cannot reach 4GB */
+
+ for ( ; btw; /* Repeat until all data written */
+ wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) {
+ if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
+ csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
+ if (!csect) { /* On the cluster boundary? */
+ if (fp->fptr == 0) { /* On the top of the file? */
+ clst = fp->sclust; /* Follow from the origin */
+ if (clst == 0) /* When no cluster is allocated, */
+ fp->sclust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */
+ } else { /* Middle or end of the file */
+#if _USE_FASTSEEK
+ if (fp->cltbl)
+ clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */
+ else
+#endif
+ clst = create_chain(fp->fs, fp->clust); /* Follow or stretch cluster chain on the FAT */
+ }
+ if (clst == 0) break; /* Could not allocate a new cluster (disk full) */
+ if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ fp->clust = clst; /* Update current cluster */
+ }
+#if _FS_TINY
+ if (fp->fs->winsect == fp->dsect && move_window(fp->fs, 0)) /* Write-back sector cache */
+ ABORT(fp->fs, FR_DISK_ERR);
+#else
+ if (fp->flag & FA__DIRTY) { /* Write-back sector cache */
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ sect = clust2sect(fp->fs, fp->clust); /* Get current sector */
+ if (!sect) ABORT(fp->fs, FR_INT_ERR);
+ sect += csect;
+ cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */
+ if (cc) { /* Write maximum contiguous sectors directly */
+ if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
+ cc = fp->fs->csize - csect;
+ if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+#if _FS_TINY
+ if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+ mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs));
+ fp->fs->wflag = 0;
+ }
+#else
+ if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+ mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs));
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */
+ continue;
+ }
+#if _FS_TINY
+ if (fp->fptr >= fp->fsize) { /* Avoid silly cache filling at growing edge */
+ if (move_window(fp->fs, 0)) ABORT(fp->fs, FR_DISK_ERR);
+ fp->fs->winsect = sect;
+ }
+#else
+ if (fp->dsect != sect) { /* Fill sector cache with file data */
+ if (fp->fptr < fp->fsize &&
+ disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ }
+#endif
+ fp->dsect = sect;
+ }
+ wcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */
+ if (wcnt > btw) wcnt = btw;
+#if _FS_TINY
+ if (move_window(fp->fs, fp->dsect)) /* Move sector window */
+ ABORT(fp->fs, FR_DISK_ERR);
+ mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */
+ fp->fs->wflag = 1;
+#else
+ mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */
+ fp->flag |= FA__DIRTY;
+#endif
+ }
+
+ if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */
+ fp->flag |= FA__WRITTEN; /* Set file change flag */
+
+ LEAVE_FF(fp->fs, FR_OK);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize the File Object */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_sync (
+ FIL *fp /* Pointer to the file object */
+)
+{
+ FRESULT res;
+ DWORD tim;
+ BYTE *dir;
+
+
+ res = validate(fp->fs, fp->id); /* Check validity of the object */
+ if (res == FR_OK) {
+ if (fp->flag & FA__WRITTEN) { /* Has the file been written? */
+#if !_FS_TINY /* Write-back dirty buffer */
+ if (fp->flag & FA__DIRTY) {
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ LEAVE_FF(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ /* Update the directory entry */
+ res = move_window(fp->fs, fp->dir_sect);
+ if (res == FR_OK) {
+ dir = fp->dir_ptr;
+ dir[DIR_Attr] |= AM_ARC; /* Set archive bit */
+ ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */
+ ST_CLUST(dir, fp->sclust); /* Update start cluster */
+ tim = get_fattime(); /* Update updated time */
+ ST_DWORD(dir+DIR_WrtTime, tim);
+ fp->flag &= ~FA__WRITTEN;
+ fp->fs->wflag = 1;
+ res = sync(fp->fs);
+ }
+ }
+ }
+
+ LEAVE_FF(fp->fs, res);
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_close (
+ FIL *fp /* Pointer to the file object to be closed */
+)
+{
+ FRESULT res;
+
+#if _FS_READONLY
+ FATFS *fs = fp->fs;
+ res = validate(fs, fp->id);
+ if (res == FR_OK) fp->fs = 0; /* Discard file object */
+ LEAVE_FF(fs, res);
+
+#else
+ res = f_sync(fp); /* Flush cached data */
+#if _FS_SHARE
+ if (res == FR_OK) { /* Decrement open counter */
+#if _FS_REENTRANT
+ res = validate(fp->fs, fp->id);
+ if (res == FR_OK) {
+ res = dec_lock(fp->lockid);
+ unlock_fs(fp->fs, FR_OK);
+ }
+#else
+ res = dec_lock(fp->lockid);
+#endif
+ }
+#endif
+ if (res == FR_OK) fp->fs = 0; /* Discard file object */
+ return res;
+#endif
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Current Drive/Directory Handlings */
+/*-----------------------------------------------------------------------*/
+
+#if _FS_RPATH >= 1
+
+FRESULT f_chdrive (
+ BYTE drv /* Drive number */
+)
+{
+ if (drv >= _VOLUMES) return FR_INVALID_DRIVE;
+
+ CurrVol = drv;
+
+ return FR_OK;
+}
+
+
+
+FRESULT f_chdir (
+ const TCHAR *path /* Pointer to the directory path */
+)
+{
+ FRESULT res;
+ DIR dj;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 0);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the path */
+ FREE_BUF();
+ if (res == FR_OK) { /* Follow completed */
+ if (!dj.dir) {
+ dj.fs->cdir = dj.sclust; /* Start directory itself */
+ } else {
+ if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */
+ dj.fs->cdir = LD_CLUST(dj.dir);
+ else
+ res = FR_NO_PATH; /* Reached but a file */
+ }
+ }
+ if (res == FR_NO_FILE) res = FR_NO_PATH;
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+#if _FS_RPATH >= 2
+FRESULT f_getcwd (
+ TCHAR *path, /* Pointer to the directory path */
+ UINT sz_path /* Size of path */
+)
+{
+ FRESULT res;
+ DIR dj;
+ UINT i, n;
+ DWORD ccl;
+ TCHAR *tp;
+ FILINFO fno;
+ DEF_NAMEBUF;
+
+
+ *path = 0;
+ res = chk_mounted((const TCHAR**)&path, &dj.fs, 0); /* Get current volume */
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ i = sz_path; /* Bottom of buffer (dir stack base) */
+ dj.sclust = dj.fs->cdir; /* Start to follow upper dir from current dir */
+ while ((ccl = dj.sclust) != 0) { /* Repeat while current dir is a sub-dir */
+ res = dir_sdi(&dj, 1); /* Get parent dir */
+ if (res != FR_OK) break;
+ res = dir_read(&dj);
+ if (res != FR_OK) break;
+ dj.sclust = LD_CLUST(dj.dir); /* Goto parent dir */
+ res = dir_sdi(&dj, 0);
+ if (res != FR_OK) break;
+ do { /* Find the entry links to the child dir */
+ res = dir_read(&dj);
+ if (res != FR_OK) break;
+ if (ccl == LD_CLUST(dj.dir)) break; /* Found the entry */
+ res = dir_next(&dj, 0);
+ } while (res == FR_OK);
+ if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
+ if (res != FR_OK) break;
+#if _USE_LFN
+ fno.lfname = path;
+ fno.lfsize = i;
+#endif
+ get_fileinfo(&dj, &fno); /* Get the dir name and push it to the buffer */
+ tp = fno.fname;
+ if (_USE_LFN && *path) tp = path;
+ for (n = 0; tp[n]; n++) ;
+ if (i < n + 3) {
+ res = FR_NOT_ENOUGH_CORE; break;
+ }
+ while (n) path[--i] = tp[--n];
+ path[--i] = '/';
+ }
+ tp = path;
+ if (res == FR_OK) {
+ *tp++ = '0' + CurrVol; /* Put drive number */
+ *tp++ = ':';
+ if (i == sz_path) { /* Root-dir */
+ *tp++ = '/';
+ } else { /* Sub-dir */
+ do /* Add stacked path str */
+ *tp++ = path[i++];
+ while (i < sz_path);
+ }
+ }
+ *tp = 0;
+ FREE_BUF();
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+#endif /* _FS_RPATH >= 2 */
+#endif /* _FS_RPATH >= 1 */
+
+
+
+#if _FS_MINIMIZE <= 2
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_lseek (
+ FIL *fp, /* Pointer to the file object */
+ DWORD ofs /* File pointer from top of file */
+)
+{
+ FRESULT res;
+
+
+ res = validate(fp->fs, fp->id); /* Check validity of the object */
+ if (res != FR_OK) LEAVE_FF(fp->fs, res);
+ if (fp->flag & FA__ERROR) /* Check abort flag */
+ LEAVE_FF(fp->fs, FR_INT_ERR);
+
+#if _USE_FASTSEEK
+ if (fp->cltbl) { /* Fast seek */
+ DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
+
+ if (ofs == CREATE_LINKMAP) { /* Create CLMT */
+ tbl = fp->cltbl;
+ tlen = *tbl++; ulen = 2; /* Given table size and required table size */
+ cl = fp->sclust; /* Top of the chain */
+ if (cl) {
+ do {
+ /* Get a fragment */
+ tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */
+ do {
+ pcl = cl; ncl++;
+ cl = get_fat(fp->fs, cl);
+ if (cl <= 1) ABORT(fp->fs, FR_INT_ERR);
+ if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ } while (cl == pcl + 1);
+ if (ulen <= tlen) { /* Store the length and top of the fragment */
+ *tbl++ = ncl; *tbl++ = tcl;
+ }
+ } while (cl < fp->fs->n_fatent); /* Repeat until end of chain */
+ }
+ *fp->cltbl = ulen; /* Number of items used */
+ if (ulen <= tlen)
+ *tbl = 0; /* Terminate table */
+ else
+ res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */
+
+ } else { /* Fast seek */
+ if (ofs > fp->fsize) /* Clip offset at the file size */
+ ofs = fp->fsize;
+ fp->fptr = ofs; /* Set file pointer */
+ if (ofs) {
+ fp->clust = clmt_clust(fp, ofs - 1);
+ dsc = clust2sect(fp->fs, fp->clust);
+ if (!dsc) ABORT(fp->fs, FR_INT_ERR);
+ dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1);
+ if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) { /* Refill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+ if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK) /* Load current sector */
+ ABORT(fp->fs, FR_DISK_ERR);
+#endif
+ fp->dsect = dsc;
+ }
+ }
+ }
+ } else
+#endif
+
+ /* Normal Seek */
+ {
+ DWORD clst, bcs, nsect, ifptr;
+
+ if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */
+#if !_FS_READONLY
+ && !(fp->flag & FA_WRITE)
+#endif
+ ) ofs = fp->fsize;
+
+ ifptr = fp->fptr;
+ fp->fptr = nsect = 0;
+ if (ofs) {
+ bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */
+ if (ifptr > 0 &&
+ (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */
+ fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */
+ ofs -= fp->fptr;
+ clst = fp->clust;
+ } else { /* When seek to back cluster, */
+ clst = fp->sclust; /* start from the first cluster */
+#if !_FS_READONLY
+ if (clst == 0) { /* If no cluster chain, create a new chain */
+ clst = create_chain(fp->fs, 0);
+ if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ fp->sclust = clst;
+ }
+#endif
+ fp->clust = clst;
+ }
+ if (clst != 0) {
+ while (ofs > bcs) { /* Cluster following loop */
+#if !_FS_READONLY
+ if (fp->flag & FA_WRITE) { /* Check if in write mode or not */
+ clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */
+ if (clst == 0) { /* When disk gets full, clip file size */
+ ofs = bcs; break;
+ }
+ } else
+#endif
+ clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR);
+ fp->clust = clst;
+ fp->fptr += bcs;
+ ofs -= bcs;
+ }
+ fp->fptr += ofs;
+ if (ofs % SS(fp->fs)) {
+ nsect = clust2sect(fp->fs, clst); /* Current sector */
+ if (!nsect) ABORT(fp->fs, FR_INT_ERR);
+ nsect += ofs / SS(fp->fs);
+ }
+ }
+ }
+ if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { /* Fill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+ if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK) /* Fill sector cache */
+ ABORT(fp->fs, FR_DISK_ERR);
+#endif
+ fp->dsect = nsect;
+ }
+#if !_FS_READONLY
+ if (fp->fptr > fp->fsize) { /* Set file change flag if the file size is extended */
+ fp->fsize = fp->fptr;
+ fp->flag |= FA__WRITTEN;
+ }
+#endif
+ }
+
+ LEAVE_FF(fp->fs, res);
+}
+
+
+
+#if _FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Create a Directroy Object */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_opendir (
+ DIR *dj, /* Pointer to directory object to create */
+ const TCHAR *path /* Pointer to the directory path */
+)
+{
+ FRESULT res;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj->fs, 0);
+ if (res == FR_OK) {
+ INIT_BUF(*dj);
+ res = follow_path(dj, path); /* Follow the path to the directory */
+ FREE_BUF();
+ if (res == FR_OK) { /* Follow completed */
+ if (dj->dir) { /* It is not the root dir */
+ if (dj->dir[DIR_Attr] & AM_DIR) { /* The object is a directory */
+ dj->sclust = LD_CLUST(dj->dir);
+ } else { /* The object is not a directory */
+ res = FR_NO_PATH;
+ }
+ }
+ if (res == FR_OK) {
+ dj->id = dj->fs->id;
+ res = dir_sdi(dj, 0); /* Rewind dir */
+ }
+ }
+ if (res == FR_NO_FILE) res = FR_NO_PATH;
+ }
+
+ LEAVE_FF(dj->fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequense */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_readdir (
+ DIR *dj, /* Pointer to the open directory object */
+ FILINFO *fno /* Pointer to file information to return */
+)
+{
+ FRESULT res;
+ DEF_NAMEBUF;
+
+
+ res = validate(dj->fs, dj->id); /* Check validity of the object */
+ if (res == FR_OK) {
+ if( dj->sect == 0) res = FR_NO_FILE;
+ else if (!fno) {
+ res = dir_sdi(dj, 0); /* Rewind the directory object */
+ } else {
+ INIT_BUF(*dj);
+ res = dir_read(dj); /* Read an directory item */
+ if (res == FR_NO_FILE) { /* Reached end of dir */
+ dj->sect = 0;
+ res = FR_NO_FILE;
+ }
+ if (res == FR_OK) { /* A valid entry is found */
+ get_fileinfo(dj, fno); /* Get the object information */
+ res = dir_next(dj, 0); /* Increment index for next */
+ if (res == FR_NO_FILE) {
+ dj->sect = 0;
+ res = FR_OK;
+ }
+ }
+ FREE_BUF();
+ }
+ }
+
+ LEAVE_FF(dj->fs, res);
+}
+
+
+
+#if _FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Get File Status */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_stat (
+ const TCHAR *path, /* Pointer to the file path */
+ FILINFO *fno /* Pointer to file information to return */
+)
+{
+ FRESULT res;
+ DIR dj;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 0);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (res == FR_OK) { /* Follow completed */
+ if (dj.dir) /* Found an object */
+ get_fileinfo(&dj, fno);
+ else /* It is root dir */
+ res = FR_INVALID_NAME;
+ }
+ FREE_BUF();
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Get Number of Free Clusters */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getfree (
+ const TCHAR *path, /* Pointer to the logical drive number (root dir) */
+ DWORD *nclst, /* Pointer to the variable to return number of free clusters */
+ FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */
+)
+{
+ FRESULT res;
+ DWORD n, clst, sect, stat;
+ UINT i;
+ BYTE fat, *p;
+
+
+ /* Get drive number */
+ res = chk_mounted(&path, fatfs, 0);
+ if (res == FR_OK) {
+ /* If free_clust is valid, return it without full cluster scan */
+ if ((*fatfs)->free_clust <= (*fatfs)->n_fatent - 2) {
+ *nclst = (*fatfs)->free_clust;
+ } else {
+ /* Get number of free clusters */
+ fat = (*fatfs)->fs_type;
+ n = 0;
+ if (fat == FS_FAT12) {
+ clst = 2;
+ do {
+ stat = get_fat(*fatfs, clst);
+ if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+ if (stat == 1) { res = FR_INT_ERR; break; }
+ if (stat == 0) n++;
+ } while (++clst < (*fatfs)->n_fatent);
+ } else {
+ clst = (*fatfs)->n_fatent;
+ sect = (*fatfs)->fatbase;
+ i = 0; p = 0;
+ do {
+ if (!i) {
+ res = move_window(*fatfs, sect++);
+ if (res != FR_OK) break;
+ p = (*fatfs)->win;
+ i = SS(*fatfs);
+ }
+ if (fat == FS_FAT16) {
+ if (LD_WORD(p) == 0) n++;
+ p += 2; i -= 2;
+ } else {
+ if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++;
+ p += 4; i -= 4;
+ }
+ } while (--clst);
+ }
+ (*fatfs)->free_clust = n;
+ if (fat == FS_FAT32) (*fatfs)->fsi_flag = 1;
+ *nclst = n;
+ }
+ }
+ LEAVE_FF(*fatfs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Truncate File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_truncate (
+ FIL *fp /* Pointer to the file object */
+)
+{
+ FRESULT res;
+ DWORD ncl;
+
+
+ res = validate(fp->fs, fp->id); /* Check validity of the object */
+ if (res == FR_OK) {
+ if (fp->flag & FA__ERROR) { /* Check abort flag */
+ res = FR_INT_ERR;
+ } else {
+ if (!(fp->flag & FA_WRITE)) /* Check access mode */
+ res = FR_DENIED;
+ }
+ }
+ if (res == FR_OK) {
+ if (fp->fsize > fp->fptr) {
+ fp->fsize = fp->fptr; /* Set file size to current R/W point */
+ fp->flag |= FA__WRITTEN;
+ if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */
+ res = remove_chain(fp->fs, fp->sclust);
+ fp->sclust = 0;
+ } else { /* When truncate a part of the file, remove remaining clusters */
+ ncl = get_fat(fp->fs, fp->clust);
+ res = FR_OK;
+ if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ if (ncl == 1) res = FR_INT_ERR;
+ if (res == FR_OK && ncl < fp->fs->n_fatent) {
+ res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF);
+ if (res == FR_OK) res = remove_chain(fp->fs, ncl);
+ }
+ }
+ }
+ if (res != FR_OK) fp->flag |= FA__ERROR;
+ }
+
+ LEAVE_FF(fp->fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Delete a File or Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_unlink (
+ const TCHAR *path /* Pointer to the file or directory path */
+)
+{
+ FRESULT res;
+ DIR dj, sdj;
+ BYTE *dir;
+ DWORD dclst;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 1);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME; /* Cannot remove dot entry */
+#if _FS_SHARE
+ if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */
+#endif
+ if (res == FR_OK) { /* The object is accessible */
+ dir = dj.dir;
+ if (!dir) {
+ res = FR_INVALID_NAME; /* Cannot remove the start directory */
+ } else {
+ if (dir[DIR_Attr] & AM_RDO)
+ res = FR_DENIED; /* Cannot remove R/O object */
+ }
+ dclst = LD_CLUST(dir);
+ if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */
+ if (dclst < 2) {
+ res = FR_INT_ERR;
+ } else {
+ mem_cpy(&sdj, &dj, sizeof(DIR)); /* Check if the sub-dir is empty or not */
+ sdj.sclust = dclst;
+ res = dir_sdi(&sdj, 2); /* Exclude dot entries */
+ if (res == FR_OK) {
+ res = dir_read(&sdj);
+ if (res == FR_OK /* Not empty dir */
+#if _FS_RPATH
+ || dclst == sdj.fs->cdir /* Current dir */
+#endif
+ ) res = FR_DENIED;
+ if (res == FR_NO_FILE) res = FR_OK; /* Empty */
+ }
+ }
+ }
+ if (res == FR_OK) {
+ res = dir_remove(&dj); /* Remove the directory entry */
+ if (res == FR_OK) {
+ if (dclst) /* Remove the cluster chain if exist */
+ res = remove_chain(dj.fs, dclst);
+ if (res == FR_OK) res = sync(dj.fs);
+ }
+ }
+ }
+ FREE_BUF();
+ }
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkdir (
+ const TCHAR *path /* Pointer to the directory path */
+)
+{
+ FRESULT res;
+ DIR dj;
+ BYTE *dir, n;
+ DWORD dsc, dcl, pcl, tim = get_fattime();
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 1);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */
+ if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME;
+ if (res == FR_NO_FILE) { /* Can create a new directory */
+ dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */
+ res = FR_OK;
+ if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */
+ if (dcl == 1) res = FR_INT_ERR;
+ if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ if (res == FR_OK) /* Flush FAT */
+ res = move_window(dj.fs, 0);
+ if (res == FR_OK) { /* Initialize the new directory table */
+ dsc = clust2sect(dj.fs, dcl);
+ dir = dj.fs->win;
+ mem_set(dir, 0, SS(dj.fs));
+ mem_set(dir+DIR_Name, ' ', 8+3); /* Create "." entry */
+ dir[DIR_Name] = '.';
+ dir[DIR_Attr] = AM_DIR;
+ ST_DWORD(dir+DIR_WrtTime, tim);
+ ST_CLUST(dir, dcl);
+ mem_cpy(dir+SZ_DIR, dir, SZ_DIR); /* Create ".." entry */
+ dir[33] = '.'; pcl = dj.sclust;
+ if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase)
+ pcl = 0;
+ ST_CLUST(dir+SZ_DIR, pcl);
+ for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */
+ dj.fs->winsect = dsc++;
+ dj.fs->wflag = 1;
+ res = move_window(dj.fs, 0);
+ if (res != FR_OK) break;
+ mem_set(dir, 0, SS(dj.fs));
+ }
+ }
+ if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */
+ if (res != FR_OK) {
+ remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */
+ } else {
+ dir = dj.dir;
+ dir[DIR_Attr] = AM_DIR; /* Attribute */
+ ST_DWORD(dir+DIR_WrtTime, tim); /* Created time */
+ ST_CLUST(dir, dcl); /* Table start cluster */
+ dj.fs->wflag = 1;
+ res = sync(dj.fs);
+ }
+ }
+ FREE_BUF();
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Attribute */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chmod (
+ const TCHAR *path, /* Pointer to the file path */
+ BYTE value, /* Attribute bits */
+ BYTE mask /* Attribute mask to change */
+)
+{
+ FRESULT res;
+ DIR dj;
+ BYTE *dir;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 1);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ FREE_BUF();
+ if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME;
+ if (res == FR_OK) {
+ dir = dj.dir;
+ if (!dir) { /* Is it a root directory? */
+ res = FR_INVALID_NAME;
+ } else { /* File or sub directory */
+ mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */
+ dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */
+ dj.fs->wflag = 1;
+ res = sync(dj.fs);
+ }
+ }
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Timestamp */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_utime (
+ const TCHAR *path, /* Pointer to the file/directory name */
+ const FILINFO *fno /* Pointer to the time stamp to be set */
+)
+{
+ FRESULT res;
+ DIR dj;
+ BYTE *dir;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 1);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ FREE_BUF();
+ if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME;
+ if (res == FR_OK) {
+ dir = dj.dir;
+ if (!dir) { /* Root directory */
+ res = FR_INVALID_NAME;
+ } else { /* File or sub-directory */
+ ST_WORD(dir+DIR_WrtTime, fno->ftime);
+ ST_WORD(dir+DIR_WrtDate, fno->fdate);
+ dj.fs->wflag = 1;
+ res = sync(dj.fs);
+ }
+ }
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Rename File/Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_rename (
+ const TCHAR *path_old, /* Pointer to the old name */
+ const TCHAR *path_new /* Pointer to the new name */
+)
+{
+ FRESULT res;
+ DIR djo, djn;
+ BYTE buf[21], *dir;
+ DWORD dw;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path_old, &djo.fs, 1);
+ if (res == FR_OK) {
+ djn.fs = djo.fs;
+ INIT_BUF(djo);
+ res = follow_path(&djo, path_old); /* Check old object */
+ if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME;
+#if _FS_SHARE
+ if (res == FR_OK) res = chk_lock(&djo, 2);
+#endif
+ if (res == FR_OK) { /* Old object is found */
+ if (!djo.dir) { /* Is root dir? */
+ res = FR_NO_FILE;
+ } else {
+ mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */
+ mem_cpy(&djn, &djo, sizeof(DIR)); /* Check new object */
+ res = follow_path(&djn, path_new);
+ if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */
+ if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */
+/* Start critical section that any interruption or error can cause cross-link */
+ res = dir_register(&djn); /* Register the new entry */
+ if (res == FR_OK) {
+ dir = djn.dir; /* Copy object information except for name */
+ mem_cpy(dir+13, buf+2, 19);
+ dir[DIR_Attr] = buf[0] | AM_ARC;
+ djo.fs->wflag = 1;
+ if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */
+ dw = clust2sect(djn.fs, LD_CLUST(dir));
+ if (!dw) {
+ res = FR_INT_ERR;
+ } else {
+ res = move_window(djn.fs, dw);
+ dir = djn.fs->win+SZ_DIR; /* .. entry */
+ if (res == FR_OK && dir[1] == '.') {
+ dw = (djn.fs->fs_type == FS_FAT32 && djn.sclust == djn.fs->dirbase) ? 0 : djn.sclust;
+ ST_CLUST(dir, dw);
+ djn.fs->wflag = 1;
+ }
+ }
+ }
+ if (res == FR_OK) {
+ res = dir_remove(&djo); /* Remove old entry */
+ if (res == FR_OK)
+ res = sync(djo.fs);
+ }
+ }
+/* End critical section */
+ }
+ }
+ }
+ FREE_BUF();
+ }
+ LEAVE_FF(djo.fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _FS_MINIMIZE == 0 */
+#endif /* _FS_MINIMIZE <= 1 */
+#endif /* _FS_MINIMIZE <= 2 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Forward data to the stream directly (available on only tiny cfg) */
+/*-----------------------------------------------------------------------*/
+#if _USE_FORWARD && _FS_TINY
+
+FRESULT f_forward (
+ FIL *fp, /* Pointer to the file object */
+ UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */
+ UINT btr, /* Number of bytes to forward */
+ UINT *bf /* Pointer to number of bytes forwarded */
+)
+{
+ FRESULT res;
+ DWORD remain, clst, sect;
+ UINT rcnt;
+ BYTE csect;
+
+
+ *bf = 0; /* Initialize byte counter */
+
+ res = validate(fp->fs, fp->id); /* Check validity of the object */
+ if (res != FR_OK) LEAVE_FF(fp->fs, res);
+ if (fp->flag & FA__ERROR) /* Check error flag */
+ LEAVE_FF(fp->fs, FR_INT_ERR);
+ if (!(fp->flag & FA_READ)) /* Check access mode */
+ LEAVE_FF(fp->fs, FR_DENIED);
+
+ remain = fp->fsize - fp->fptr;
+ if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */
+
+ for ( ; btr && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */
+ fp->fptr += rcnt, *bf += rcnt, btr -= rcnt) {
+ csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
+ if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
+ if (!csect) { /* On the cluster boundary? */
+ clst = (fp->fptr == 0) ? /* On the top of the file? */
+ fp->sclust : get_fat(fp->fs, fp->clust);
+ if (clst <= 1) ABORT(fp->fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ fp->clust = clst; /* Update current cluster */
+ }
+ }
+ sect = clust2sect(fp->fs, fp->clust); /* Get current data sector */
+ if (!sect) ABORT(fp->fs, FR_INT_ERR);
+ sect += csect;
+ if (move_window(fp->fs, sect)) /* Move sector window */
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->dsect = sect;
+ rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */
+ if (rcnt > btr) rcnt = btr;
+ rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt);
+ if (!rcnt) ABORT(fp->fs, FR_INT_ERR);
+ }
+
+ LEAVE_FF(fp->fs, FR_OK);
+}
+#endif /* _USE_FORWARD */
+
+
+
+#if _USE_MKFS && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Create File System on the Drive */
+/*-----------------------------------------------------------------------*/
+#define N_ROOTDIR 512 /* Number of root dir entries for FAT12/16 */
+#define N_FATS 1 /* Number of FAT copies (1 or 2) */
+
+
+FRESULT f_mkfs (
+ BYTE drv, /* Logical drive number */
+ BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */
+ UINT au /* Allocation unit size [bytes] */
+)
+{
+ static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0};
+ static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512};
+ BYTE fmt, md, *tbl;
+ DWORD n_clst, vs, n, wsect;
+ UINT i;
+ DWORD b_vol, b_fat, b_dir, b_data; /* Offset (LBA) */
+ DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */
+ FATFS *fs;
+ DSTATUS stat;
+
+
+ /* Check mounted drive and clear work area */
+ if (drv >= _VOLUMES) return FR_INVALID_DRIVE;
+ fs = FatFs[drv];
+ if (!fs) return FR_NOT_ENABLED;
+ fs->fs_type = 0;
+ drv = LD2PD(drv);
+
+ /* Get disk statics */
+ stat = disk_initialize(drv);
+ if (stat & STA_NOINIT) return FR_NOT_READY;
+ if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+#if _MAX_SS != 512 /* Get disk sector size */
+ if (disk_ioctl(drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK)
+ return FR_DISK_ERR;
+#endif
+ if (disk_ioctl(drv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128)
+ return FR_DISK_ERR;
+ b_vol = (sfd) ? 0 : 63; /* Volume start sector */
+ n_vol -= b_vol;
+ if (au & (au - 1)) au = 0; /* Check validity of the AU size */
+
+ if (!au) { /* AU auto selection */
+ vs = n_vol / (2000 / (SS(fs) / 512));
+ for (i = 0; vs < vst[i]; i++) ;
+ au = cst[i];
+ }
+ au /= SS(fs); /* Number of sectors per cluster */
+ if (au == 0) au = 1;
+ if (au > 128) au = 128;
+
+ /* Pre-compute number of clusters and FAT syb-type */
+ n_clst = n_vol / au;
+ fmt = FS_FAT12;
+ if (n_clst >= MIN_FAT16) fmt = FS_FAT16;
+ if (n_clst >= MIN_FAT32) fmt = FS_FAT32;
+
+ /* Determine offset and size of FAT structure */
+ if (fmt == FS_FAT32) {
+ n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs);
+ n_rsv = 32;
+ n_dir = 0;
+ } else {
+ n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4;
+ n_fat = (n_fat + SS(fs) - 1) / SS(fs);
+ n_rsv = 1;
+ n_dir = (DWORD)N_ROOTDIR * SZ_DIR / SS(fs);
+ }
+ b_fat = b_vol + n_rsv; /* FAT area start sector */
+ b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */
+ b_data = b_dir + n_dir; /* Data area start sector */
+ if (n_vol < b_data + au) return FR_MKFS_ABORTED; /* Too small volume */
+
+ /* Align data start sector to erase block boundary (for flash memory media) */
+ if (disk_ioctl(drv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1;
+ n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */
+ n = (n - b_data) / N_FATS;
+ if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */
+ n_rsv += n;
+ b_fat += n;
+ } else { /* FAT12/16: Expand FAT size */
+ n_fat += n;
+ }
+
+ /* Determine number of clusters and final check of validity of the FAT sub-type */
+ n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au;
+ if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16)
+ || (fmt == FS_FAT32 && n_clst < MIN_FAT32))
+ return FR_MKFS_ABORTED;
+
+ /* Create partition table if required */
+ if (sfd) { /* No patition table (SFD) */
+ md = 0xF0;
+ } else { /* With patition table (FDISK) */
+ DWORD n_disk = b_vol + n_vol;
+
+ mem_set(fs->win, 0, SS(fs));
+ tbl = fs->win+MBR_Table;
+ ST_DWORD(tbl, 0x00010180); /* Partition start in CHS */
+ if (n_disk < 63UL * 255 * 1024) { /* Partition end in CHS */
+ n_disk = n_disk / 63 / 255;
+ tbl[7] = (BYTE)n_disk;
+ tbl[6] = (BYTE)((n_disk >> 2) | 63);
+ } else {
+ ST_WORD(&tbl[6], 0xFFFF); /* CHS saturated */
+ }
+ tbl[5] = 254;
+ if (fmt != FS_FAT32) /* System ID */
+ tbl[4] = (n_vol < 0x10000) ? 0x04 : 0x06;
+ else
+ tbl[4] = 0x0c;
+ ST_DWORD(tbl+8, 63); /* Partition start in LBA */
+ ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */
+ ST_WORD(fs->win+BS_55AA, 0xAA55); /* MBR signature */
+ if (disk_write(drv, fs->win, 0, 1) != RES_OK) /* Put the MBR into first physical sector */
+ return FR_DISK_ERR;
+ md = 0xF8;
+ }
+
+ /* Create volume boot record */
+ tbl = fs->win; /* Clear sector */
+ mem_set(tbl, 0, SS(fs));
+ mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */
+ i = SS(fs); /* Sector size */
+ ST_WORD(tbl+BPB_BytsPerSec, i);
+ tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */
+ ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */
+ tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */
+ i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of rootdir entries */
+ ST_WORD(tbl+BPB_RootEntCnt, i);
+ if (n_vol < 0x10000) { /* Number of total sectors */
+ ST_WORD(tbl+BPB_TotSec16, n_vol);
+ } else {
+ ST_DWORD(tbl+BPB_TotSec32, n_vol);
+ }
+ tbl[BPB_Media] = md; /* Media descriptor */
+ ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */
+ ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */
+ ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */
+ n = get_fattime(); /* Use current time as VSN */
+ if (fmt == FS_FAT32) {
+ ST_DWORD(tbl+BS_VolID32, n); /* VSN */
+ ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */
+ ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */
+ ST_WORD(tbl+BPB_FSInfo, 1); /* FSInfo record offset (VBR+1) */
+ ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */
+ tbl[BS_DrvNum32] = 0x80; /* Drive number */
+ tbl[BS_BootSig32] = 0x29; /* Extended boot signature */
+ mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */
+ } else {
+ ST_DWORD(tbl+BS_VolID, n); /* VSN */
+ ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */
+ tbl[BS_DrvNum] = 0x80; /* Drive number */
+ tbl[BS_BootSig] = 0x29; /* Extended boot signature */
+ mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */
+ }
+ ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */
+ if (disk_write(drv, tbl, b_vol, 1) != RES_OK) /* Write VBR */
+ return FR_DISK_ERR;
+ if (fmt == FS_FAT32) /* Write backup VBR if needed (VBR+6) */
+ disk_write(drv, tbl, b_vol + 6, 1);
+
+ /* Initialize FAT area */
+ wsect = b_fat;
+ for (i = 0; i < N_FATS; i++) { /* Initialize each FAT copy */
+ mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */
+ n = md; /* Media descriptor byte */
+ if (fmt != FS_FAT32) {
+ n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00;
+ ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */
+ } else {
+ n |= 0xFFFFFF00;
+ ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */
+ ST_DWORD(tbl+4, 0xFFFFFFFF);
+ ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root dir */
+ }
+ if (disk_write(drv, tbl, wsect++, 1) != RES_OK)
+ return FR_DISK_ERR;
+ mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */
+ for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector writes */
+ if (disk_write(drv, tbl, wsect++, 1) != RES_OK)
+ return FR_DISK_ERR;
+ }
+ }
+
+ /* Initialize root directory */
+ i = (fmt == FS_FAT32) ? au : n_dir;
+ do {
+ if (disk_write(drv, tbl, wsect++, 1) != RES_OK)
+ return FR_DISK_ERR;
+ } while (--i);
+
+#if _USE_ERASE /* Erase data area if needed */
+ {
+ DWORD eb[2];
+
+ eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1;
+ disk_ioctl(drv, CTRL_ERASE_SECTOR, eb);
+ }
+#endif
+
+ /* Create FSInfo if needed */
+ if (fmt == FS_FAT32) {
+ ST_DWORD(tbl+FSI_LeadSig, 0x41615252);
+ ST_DWORD(tbl+FSI_StrucSig, 0x61417272);
+ ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); /* Number of free clusters */
+ ST_DWORD(tbl+FSI_Nxt_Free, 2); /* Last allocated cluster# */
+ ST_WORD(tbl+BS_55AA, 0xAA55);
+ disk_write(drv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */
+ disk_write(drv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */
+ }
+
+ return (disk_ioctl(drv, CTRL_SYNC, (void*)0) == RES_OK) ? FR_OK : FR_DISK_ERR;
+}
+
+#endif /* _USE_MKFS && !_FS_READONLY */
+
+
+
+
+#if _USE_STRFUNC
+/*-----------------------------------------------------------------------*/
+/* Get a string from the file */
+/*-----------------------------------------------------------------------*/
+TCHAR* f_gets (
+ TCHAR* buff, /* Pointer to the string buffer to read */
+ int len, /* Size of string buffer (characters) */
+ FIL* fil /* Pointer to the file object */
+)
+{
+ int n = 0;
+ TCHAR c, *p = buff;
+ BYTE s[2];
+ UINT rc;
+
+
+ while (n < len - 1) { /* Read bytes until buffer gets filled */
+ f_read(fil, s, 1, &rc);
+ if (rc != 1) break; /* Break on EOF or error */
+ c = s[0];
+#if _LFN_UNICODE /* Read a character in UTF-8 encoding */
+ if (c >= 0x80) {
+ if (c < 0xC0) continue; /* Skip stray trailer */
+ if (c < 0xE0) { /* Two-byte sequense */
+ f_read(fil, s, 1, &rc);
+ if (rc != 1) break;
+ c = ((c & 0x1F) << 6) | (s[0] & 0x3F);
+ if (c < 0x80) c = '?';
+ } else {
+ if (c < 0xF0) { /* Three-byte sequense */
+ f_read(fil, s, 2, &rc);
+ if (rc != 2) break;
+ c = (c << 12) | ((s[0] & 0x3F) << 6) | (s[1] & 0x3F);
+ if (c < 0x800) c = '?';
+ } else { /* Reject four-byte sequense */
+ c = '?';
+ }
+ }
+ }
+#endif
+#if _USE_STRFUNC >= 2
+ if (c == '\r') continue; /* Strip '\r' */
+#endif
+ *p++ = c;
+ n++;
+ if (c == '\n') break; /* Break on EOL */
+ }
+ *p = 0;
+ return n ? buff : 0; /* When no data read (eof or error), return with error. */
+}
+
+
+
+#if !_FS_READONLY
+#include <stdarg.h>
+/*-----------------------------------------------------------------------*/
+/* Put a character to the file */
+/*-----------------------------------------------------------------------*/
+int f_putc (
+ TCHAR c, /* A character to be output */
+ FIL* fil /* Pointer to the file object */
+)
+{
+ UINT bw, btw;
+ BYTE s[3];
+
+
+#if _USE_STRFUNC >= 2
+ if (c == '\n') f_putc ('\r', fil); /* LF -> CRLF conversion */
+#endif
+
+#if _LFN_UNICODE /* Write the character in UTF-8 encoding */
+ if (c < 0x80) { /* 7-bit */
+ s[0] = (BYTE)c;
+ btw = 1;
+ } else {
+ if (c < 0x800) { /* 11-bit */
+ s[0] = (BYTE)(0xC0 | (c >> 6));
+ s[1] = (BYTE)(0x80 | (c & 0x3F));
+ btw = 2;
+ } else { /* 16-bit */
+ s[0] = (BYTE)(0xE0 | (c >> 12));
+ s[1] = (BYTE)(0x80 | ((c >> 6) & 0x3F));
+ s[2] = (BYTE)(0x80 | (c & 0x3F));
+ btw = 3;
+ }
+ }
+#else /* Write the character without conversion */
+ s[0] = (BYTE)c;
+ btw = 1;
+#endif
+ f_write(fil, s, btw, &bw); /* Write the char to the file */
+ return (bw == btw) ? 1 : EOF; /* Return the result */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a string to the file */
+/*-----------------------------------------------------------------------*/
+int f_puts (
+ const TCHAR* str, /* Pointer to the string to be output */
+ FIL* fil /* Pointer to the file object */
+)
+{
+ int n;
+
+
+ for (n = 0; *str; str++, n++) {
+ if (f_putc(*str, fil) == EOF) return EOF;
+ }
+ return n;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a formatted string to the file */
+/*-----------------------------------------------------------------------*/
+int f_printf (
+ FIL* fil, /* Pointer to the file object */
+ const TCHAR* str, /* Pointer to the format string */
+ ... /* Optional arguments... */
+)
+{
+ va_list arp;
+ BYTE f, r;
+ UINT i, j, w;
+ ULONG v;
+ TCHAR c, d, s[16], *p;
+ int res, cc;
+
+
+ va_start(arp, str);
+
+ for (cc = res = 0; cc != EOF; res += cc) {
+ c = *str++;
+ if (c == 0) break; /* End of string */
+ if (c != '%') { /* Non escape character */
+ cc = f_putc(c, fil);
+ if (cc != EOF) cc = 1;
+ continue;
+ }
+ w = f = 0;
+ c = *str++;
+ if (c == '0') { /* Flag: '0' padding */
+ f = 1; c = *str++;
+ } else {
+ if (c == '-') { /* Flag: left justified */
+ f = 2; c = *str++;
+ }
+ }
+ while (IsDigit(c)) { /* Precision */
+ w = w * 10 + c - '0';
+ c = *str++;
+ }
+ if (c == 'l' || c == 'L') { /* Prefix: Size is long int */
+ f |= 4; c = *str++;
+ }
+ if (!c) break;
+ d = c;
+ if (IsLower(d)) d -= 0x20;
+ switch (d) { /* Type is... */
+ case 'S' : /* String */
+ p = va_arg(arp, TCHAR*);
+ for (j = 0; p[j]; j++) ;
+ res = 0;
+ while (!(f & 2) && j++ < w) res += (cc = f_putc(' ', fil));
+ res += (cc = f_puts(p, fil));
+ while (j++ < w) res += (cc = f_putc(' ', fil));
+ if (cc != EOF) cc = res;
+ continue;
+ case 'C' : /* Character */
+ cc = f_putc((TCHAR)va_arg(arp, int), fil); continue;
+ case 'B' : /* Binary */
+ r = 2; break;
+ case 'O' : /* Octal */
+ r = 8; break;
+ case 'D' : /* Signed decimal */
+ case 'U' : /* Unsigned decimal */
+ r = 10; break;
+ case 'X' : /* Hexdecimal */
+ r = 16; break;
+ default: /* Unknown type (passthrough) */
+ cc = f_putc(c, fil); continue;
+ }
+
+ /* Get an argument and put it in numeral */
+ v = (f & 4) ? va_arg(arp, long) : ((d == 'D') ? (long)va_arg(arp, int) : va_arg(arp, unsigned int));
+ if (d == 'D' && (v & 0x80000000)) {
+ v = 0 - v;
+ f |= 8;
+ }
+ i = 0;
+ do {
+ d = (TCHAR)(v % r); v /= r;
+ if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+ s[i++] = d + '0';
+ } while (v && i < sizeof(s) / sizeof(s[0]));
+ if (f & 8) s[i++] = '-';
+ j = i; d = (f & 1) ? '0' : ' ';
+ res = 0;
+ while (!(f & 2) && j++ < w) res += (cc = f_putc(d, fil));
+ do res += (cc = f_putc(s[--i], fil)); while(i);
+ while (j++ < w) res += (cc = f_putc(' ', fil));
+ if (cc != EOF) cc = res;
+ }
+
+ va_end(arp);
+ return (cc == EOF) ? cc : res;
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_STRFUNC */
diff --git a/library/ADK2/f_ff.h b/library/ADK2/f_ff.h
new file mode 100644
index 0000000..9578b3a
--- /dev/null
+++ b/library/ADK2/f_ff.h
@@ -0,0 +1,532 @@
+#ifdef ADK_INTERNAL
+/*---------------------------------------------------------------------------/
+/ FatFs - FAT file system module include file R0.08b (C)ChaN, 2011
+/----------------------------------------------------------------------------/
+/ FatFs module is a generic FAT file system module for small embedded systems.
+/ This is a free software that opened for education, research and commercial
+/ developments under license policy of following trems.
+/
+/ Copyright (C) 2011, ChaN, all right reserved.
+/
+/ * The FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/----------------------------------------------------------------------------*/
+
+#ifndef _FATFS
+#define _FATFS 8237 /* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "f_integer.h" /* Basic integer types */
+#include "f_ffconf.h" /* FatFs configuration options */
+
+#if _FATFS != _FFCONF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+/* Moved DBCS code from ff.c, by ATMEL */
+/* DBCS code ranges and SBCS extend char conversion table */
+
+#if _CODE_PAGE == 932 /* Japanese Shift-JIS */
+#define _DF1S 0x81 /* DBC 1st byte range 1 start */
+#define _DF1E 0x9F /* DBC 1st byte range 1 end */
+#define _DF2S 0xE0 /* DBC 1st byte range 2 start */
+#define _DF2E 0xFC /* DBC 1st byte range 2 end */
+#define _DS1S 0x40 /* DBC 2nd byte range 1 start */
+#define _DS1E 0x7E /* DBC 2nd byte range 1 end */
+#define _DS2S 0x80 /* DBC 2nd byte range 2 start */
+#define _DS2E 0xFC /* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */
+#define _DF1S 0x81
+#define _DF1E 0xFE
+#define _DS1S 0x40
+#define _DS1E 0x7E
+#define _DS2S 0x80
+#define _DS2E 0xFE
+
+#elif _CODE_PAGE == 949 /* Korean */
+#define _DF1S 0x81
+#define _DF1E 0xFE
+#define _DS1S 0x41
+#define _DS1E 0x5A
+#define _DS2S 0x61
+#define _DS2E 0x7A
+#define _DS3S 0x81
+#define _DS3E 0xFE
+
+#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */
+#define _DF1S 0x81
+#define _DF1E 0xFE
+#define _DS1S 0x40
+#define _DS1E 0x7E
+#define _DS2S 0xA1
+#define _DS2E 0xFE
+
+#elif _CODE_PAGE == 437 /* U.S. (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720 /* Arabic (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737 /* Greek (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+ 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775 /* Baltic (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+ 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+ 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+ 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857 /* Turkish (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862 /* Hebrew (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866 /* Russian (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+ 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+ 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */
+#define _DF1S 0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+
+/* Definitions of volume management */
+
+#if _MULTI_PARTITION /* Multiple partition configuration */
+#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive# */
+#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition# */
+typedef struct {
+ BYTE pd; /* Physical drive# */
+ BYTE pt; /* Partition # (0-3) */
+} PARTITION;
+extern const PARTITION VolToPart[]; /* Volume - Physical location resolution table */
+
+#else /* Single partition configuration */
+#define LD2PD(vol) (vol) /* Logical drive# is bound to the same physical drive# */
+#define LD2PT(vol) 0 /* Always mounts the 1st partition */
+
+#endif
+
+
+
+/* Type of path name strings on FatFs API */
+
+#if _LFN_UNICODE /* Unicode string */
+#if !_USE_LFN
+#error _LFN_UNICODE must be 0 in non-LFN cfg.
+#endif
+#ifndef _INC_TCHAR
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#endif
+
+#else /* ANSI/OEM string */
+#ifndef _INC_TCHAR
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+
+#endif
+
+
+
+/* File system object structure (FATFS) */
+
+typedef struct {
+ BYTE fs_type; /* FAT sub-type (0:Not mounted) */
+ BYTE drv; /* Physical drive number */
+ BYTE csize; /* Sectors per cluster (1,2,4...128) */
+ BYTE n_fats; /* Number of FAT copies (1,2) */
+ BYTE wflag; /* win[] dirty flag (1:must be written back) */
+ BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */
+ WORD id; /* File system mount ID */
+ WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
+#if _MAX_SS != 512
+ WORD ssize; /* Bytes per sector (512,1024,2048,4096) */
+#endif
+#if _FS_REENTRANT
+ _SYNC_t sobj; /* Identifier of sync object */
+#endif
+#if !_FS_READONLY
+ DWORD last_clust; /* Last allocated cluster */
+ DWORD free_clust; /* Number of free clusters */
+ DWORD fsi_sector; /* fsinfo sector (FAT32) */
+#endif
+#if _FS_RPATH
+ DWORD cdir; /* Current directory start cluster (0:root) */
+#endif
+ DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */
+ DWORD fsize; /* Sectors per FAT */
+ DWORD fatbase; /* FAT start sector */
+ DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */
+ DWORD database; /* Data start sector */
+ DWORD winsect; /* Current sector appearing in the win[] */
+ BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */
+} FATFS;
+
+
+
+/* File object structure (FIL) */
+
+typedef struct {
+ FATFS* fs; /* Pointer to the owner file system object */
+ WORD id; /* Owner file system mount ID */
+ BYTE flag; /* File status flags */
+ BYTE pad1;
+ DWORD fptr; /* File read/write pointer (0 on file open) */
+ DWORD fsize; /* File size */
+ DWORD sclust; /* File start cluster (0 when fsize==0) */
+ DWORD clust; /* Current cluster */
+ DWORD dsect; /* Current data sector */
+#if !_FS_READONLY
+ DWORD dir_sect; /* Sector containing the directory entry */
+ BYTE* dir_ptr; /* Ponter to the directory entry in the window */
+#endif
+#if _USE_FASTSEEK
+ DWORD* cltbl; /* Pointer to the cluster link map table (null on file open) */
+#endif
+#if _FS_SHARE
+ UINT lockid; /* File lock ID (index of file semaphore table) */
+#endif
+#if !_FS_TINY
+ BYTE buf[_MAX_SS]; /* File data read/write buffer */
+#endif
+} FIL;
+
+
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+ FATFS* fs; /* Pointer to the owner file system object */
+ WORD id; /* Owner file system mount ID */
+ WORD index; /* Current read/write index number */
+ DWORD sclust; /* Table start cluster (0:Root dir) */
+ DWORD clust; /* Current cluster */
+ DWORD sect; /* Current sector */
+ BYTE* dir; /* Pointer to the current SFN entry in the win[] */
+ BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+#if _USE_LFN
+ WCHAR* lfn; /* Pointer to the LFN working buffer */
+ WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */
+#endif
+} DIR;
+
+
+
+/* File status structure (FILINFO) */
+
+typedef struct {
+ DWORD fsize; /* File size */
+ WORD fdate; /* Last modified date */
+ WORD ftime; /* Last modified time */
+ BYTE fattrib; /* Attribute */
+ TCHAR fname[13]; /* Short file name (8.3 format) */
+#if _USE_LFN
+ TCHAR* lfname; /* Pointer to the LFN buffer */
+ UINT lfsize; /* Size of LFN buffer in TCHAR */
+#endif
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+ FR_OK = 0, /* (0) Succeeded */
+ FR_DISK_ERR, /* (1) A hard error occured in the low level disk I/O layer */
+ FR_INT_ERR, /* (2) Assertion failed */
+ FR_NOT_READY, /* (3) The physical drive cannot work */
+ FR_NO_FILE, /* (4) Could not find the file */ //or dir listing is over
+ FR_NO_PATH, /* (5) Could not find the path */
+ FR_INVALID_NAME, /* (6) The path name format is invalid */
+ FR_DENIED, /* (7) Acces denied due to prohibited access or directory full */
+ FR_EXIST, /* (8) Acces denied due to prohibited access */
+ FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
+ FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
+ FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
+ FR_NOT_ENABLED, /* (12) The volume has no work area */
+ FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume on the physical drive */
+ FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */
+ FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
+ FR_LOCKED, /* (16) The operation is rejected according to the file shareing policy */
+ FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
+ FR_TOO_MANY_OPEN_FILES /* (18) Number of open files > _FS_SHARE */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* FatFs module application interface */
+
+FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */
+FRESULT f_open (FIL*, const TCHAR*, BYTE); /* Open or create a file */
+FRESULT f_read (FIL*, void*, UINT, UINT*); /* Read data from a file */
+FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */
+FRESULT f_close (FIL*); /* Close an open file object */
+FRESULT f_opendir (DIR*, const TCHAR*); /* Open an existing directory */
+FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */
+FRESULT f_stat (const TCHAR*, FILINFO*); /* Get file status */
+FRESULT f_write (FIL*, const void*, UINT, UINT*); /* Write data to a file */
+FRESULT f_getfree (const TCHAR*, DWORD*, FATFS**); /* Get number of free clusters on the drive */
+FRESULT f_truncate (FIL*); /* Truncate file */
+FRESULT f_sync (FIL*); /* Flush cached data of a writing file */
+FRESULT f_unlink (const TCHAR*); /* Delete an existing file or directory */
+FRESULT f_mkdir (const TCHAR*); /* Create a new directory */
+FRESULT f_chmod (const TCHAR*, BYTE, BYTE); /* Change attriburte of the file/dir */
+FRESULT f_utime (const TCHAR*, const FILINFO*); /* Change timestamp of the file/dir */
+FRESULT f_rename (const TCHAR*, const TCHAR*); /* Rename/Move a file or directory */
+FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*); /* Forward data to the stream */
+FRESULT f_mkfs (BYTE, BYTE, UINT); /* Create a file system on the drive */
+FRESULT f_chdrive (BYTE); /* Change current drive */
+FRESULT f_chdir (const TCHAR*); /* Change current directory */
+FRESULT f_getcwd (TCHAR*, UINT); /* Get current directory */
+int f_putc (TCHAR, FIL*); /* Put a character to the file */
+int f_puts (const TCHAR*, FIL*); /* Put a string to the file */
+int f_printf (FIL*, const TCHAR*, ...); /* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR*, int, FIL*); /* Get a string from the file */
+
+#ifndef EOF
+#define EOF (-1)
+#endif
+
+#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0)
+#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->fsize)
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Additional user defined functions */
+
+/* RTC function */
+#if !_FS_READONLY
+DWORD get_fattime (void);
+#endif
+
+/* Unicode support functions */
+#if _USE_LFN /* Unicode - OEM code conversion */
+WCHAR ff_convert (WCHAR, UINT); /* OEM-Unicode bidirectional conversion */
+WCHAR ff_wtoupper (WCHAR); /* Unicode upper-case conversion */
+#if _USE_LFN == 3 /* Memory functions */
+void* ff_memalloc (UINT); /* Allocate memory block */
+void ff_memfree (void*); /* Free memory block */
+#endif
+#endif
+
+/* Sync functions */
+#if _FS_REENTRANT
+int ff_cre_syncobj (BYTE, _SYNC_t*);/* Create a sync object */
+int ff_req_grant (_SYNC_t); /* Lock sync object */
+void ff_rel_grant (_SYNC_t); /* Unlock sync object */
+int ff_del_syncobj (_SYNC_t); /* Delete a sync object */
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address */
+
+
+/* File access control and file status flags (FIL.flag) */
+
+#define FA_READ 0x01
+#define FA_OPEN_EXISTING 0x00
+#define FA__ERROR 0x80
+
+#if !_FS_READONLY
+#define FA_WRITE 0x02
+#define FA_CREATE_NEW 0x04
+#define FA_CREATE_ALWAYS 0x08
+#define FA_OPEN_ALWAYS 0x10
+#define FA__WRITTEN 0x20
+#define FA__DIRTY 0x40
+#endif
+
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12 1
+#define FS_FAT16 2
+#define FS_FAT32 3
+
+
+/* File attribute bits for directory entry */
+
+#define AM_RDO 0x01 /* Read only */
+#define AM_HID 0x02 /* Hidden */
+#define AM_SYS 0x04 /* System */
+#define AM_VOL 0x08 /* Volume label */
+#define AM_LFN 0x0F /* LFN entry */
+#define AM_DIR 0x10 /* Directory */
+#define AM_ARC 0x20 /* Archive */
+#define AM_MASK 0x3F /* Mask of defined bits */
+
+
+/* Fast seek function */
+#define CREATE_LINKMAP 0xFFFFFFFF
+
+
+
+/*--------------------------------*/
+/* Multi-byte word access macros */
+
+#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */
+#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr))
+#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else /* Use byte-by-byte access to the FAT structure */
+#define LD_WORD(ptr) (WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define LD_DWORD(ptr) (DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FATFS */
+#endif
+
diff --git a/library/ADK2/f_ffconf.h b/library/ADK2/f_ffconf.h
new file mode 100644
index 0000000..77f0024
--- /dev/null
+++ b/library/ADK2/f_ffconf.h
@@ -0,0 +1,193 @@
+#ifdef ADK_INTERNAL
+/*---------------------------------------------------------------------------/
+/ FatFs - FAT file system module configuration file R0.08b (C)ChaN, 2011
+/----------------------------------------------------------------------------/
+/
+/ CAUTION! Do not forget to make clean the project after any changes to
+/ the configuration options.
+/
+/----------------------------------------------------------------------------*/
+
+#ifndef _FFCONF
+#define _FFCONF 8237 /* Revision ID */
+
+
+/*---------------------------------------------------------------------------/
+/ Function and Buffer Configurations
+/----------------------------------------------------------------------------*/
+
+#define _FS_TINY 1 /* 0:Normal or 1:Tiny */
+/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
+/ object instead of the sector buffer in the individual file object for file
+/ data transfer. This reduces memory consumption 512 bytes each file object. */
+
+
+#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */
+/* Setting _FS_READONLY to 1 defines read only configuration. This removes
+/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename,
+/ f_truncate and useless f_getfree. */
+
+
+#define _FS_MINIMIZE 0 /* 0 to 3 */
+/* The _FS_MINIMIZE option defines minimization level to remove some functions.
+/
+/ 0: Full function.
+/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename
+/ are removed.
+/ 2: f_opendir and f_readdir are removed in addition to 1.
+/ 3: f_lseek is removed in addition to 2. */
+
+
+#define _USE_STRFUNC 0 /* 0:Disable or 1/2:Enable */
+/* To enable string functions, set _USE_STRFUNC to 1 or 2. */
+
+
+#define _USE_MKFS 0 /* 0:Disable or 1:Enable */
+/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
+
+
+#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */
+/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
+
+
+#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */
+/* To enable fast seek feature, set _USE_FASTSEEK to 1. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/----------------------------------------------------------------------------*/
+
+#define _CODE_PAGE 1
+/* The _CODE_PAGE specifies the OEM code page to be used on the target system.
+/ Incorrect setting of the code page can cause a file open failure.
+/
+/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows)
+/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows)
+/ 949 - Korean (DBCS, OEM, Windows)
+/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows)
+/ 1250 - Central Europe (Windows)
+/ 1251 - Cyrillic (Windows)
+/ 1252 - Latin 1 (Windows)
+/ 1253 - Greek (Windows)
+/ 1254 - Turkish (Windows)
+/ 1255 - Hebrew (Windows)
+/ 1256 - Arabic (Windows)
+/ 1257 - Baltic (Windows)
+/ 1258 - Vietnam (OEM, Windows)
+/ 437 - U.S. (OEM)
+/ 720 - Arabic (OEM)
+/ 737 - Greek (OEM)
+/ 775 - Baltic (OEM)
+/ 850 - Multilingual Latin 1 (OEM)
+/ 858 - Multilingual Latin 1 + Euro (OEM)
+/ 852 - Latin 2 (OEM)
+/ 855 - Cyrillic (OEM)
+/ 866 - Russian (OEM)
+/ 857 - Turkish (OEM)
+/ 862 - Hebrew (OEM)
+/ 874 - Thai (OEM, Windows)
+/ 1 - ASCII only (Valid for non LFN cfg.)
+*/
+
+
+#define _USE_LFN 1 /* 0 to 3 */
+#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
+/* The _USE_LFN option switches the LFN support.
+/
+/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect.
+/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant.
+/ 2: Enable LFN with dynamic working buffer on the STACK.
+/ 3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN,
+/ Unicode handling functions ff_convert() and ff_wtoupper() must be added
+/ to the project. When enable to use heap, memory control functions
+/ ff_memalloc() and ff_memfree() must be added to the project. */
+
+
+#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
+/* To switch the character code set on FatFs API to Unicode,
+/ enable LFN feature and set _LFN_UNICODE to 1. */
+
+
+#define _FS_RPATH 0 /* 0 to 2 */
+/* The _FS_RPATH option configures relative path feature.
+/
+/ 0: Disable relative path feature and remove related functions.
+/ 1: Enable relative path. f_chdrive() and f_chdir() are available.
+/ 2: f_getcwd() is available in addition to 1.
+/
+/ Note that output of the f_readdir fnction is affected by this option. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ Physical Drive Configurations
+/----------------------------------------------------------------------------*/
+
+#define _VOLUMES 1
+/* Number of volumes (logical drives) to be used. */
+
+
+#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */
+/* Maximum sector size to be handled.
+/ Always set 512 for memory card and hard disk but a larger value may be
+/ required for on-board flash memory, floppy disk and optical disk.
+/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size
+/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */
+
+
+#define _MULTI_PARTITION 0 /* 0:Single partition or 1:Multiple partition */
+/* When set to 0, each volume is bound to the same physical drive number and
+/ it can mount only first primaly partition. When it is set to 1, each volume
+/ is tied to the partitions listed in VolToPart[]. */
+
+
+#define _USE_ERASE 0 /* 0:Disable or 1:Enable */
+/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command
+/ should be added to the disk_ioctl functio. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/----------------------------------------------------------------------------*/
+
+#define _WORD_ACCESS 0 /* 0 or 1 */
+/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS
+/ option defines which access method is used to the word data on the FAT volume.
+/
+/ 0: Byte-by-byte access.
+/ 1: Word access. Do not choose this unless following condition is met.
+/
+/ When the byte order on the memory is big-endian or address miss-aligned word
+/ access results incorrect behavior, the _WORD_ACCESS must be set to 0.
+/ If it is not the case, the value can also be set to 1 to improve the
+/ performance and code size. */
+
+
+/* A header file that defines sync object types on the O/S, such as
+/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */
+
+#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */
+#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */
+#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */
+
+/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module.
+/
+/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect.
+/ 1: Enable reentrancy. Also user provided synchronization handlers,
+/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj
+/ function must be added to the project. */
+
+
+#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */
+/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value
+ defines how many files can be opened simultaneously. */
+
+
+#endif /* _FFCONFIG */
+#endif
+
diff --git a/library/ADK2/f_integer.h b/library/ADK2/f_integer.h
new file mode 100644
index 0000000..3291ea1
--- /dev/null
+++ b/library/ADK2/f_integer.h
@@ -0,0 +1,40 @@
+#ifdef ADK_INTERNAL
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _INTEGER
+#define _INTEGER
+
+#ifdef _WIN32 /* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+
+#else /* Embedded platform */
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef long INT;
+typedef unsigned long UINT;
+
+/* These types must be 8-bit integer */
+typedef char CHAR;
+typedef unsigned char UCHAR;
+typedef unsigned char BYTE;
+
+/* These types must be 16-bit integer */
+typedef short SHORT;
+typedef unsigned short USHORT;
+typedef unsigned short WORD;
+typedef unsigned short WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long LONG;
+typedef unsigned long ULONG;
+typedef unsigned long DWORD;
+
+#endif
+
+#endif
+#endif
+
diff --git a/library/ADK2/f_sdDisk.c b/library/ADK2/f_sdDisk.c
new file mode 100644
index 0000000..e554131
--- /dev/null
+++ b/library/ADK2/f_sdDisk.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "dbg.h"
+#include "SD.h"
+#include "f_ff.h"
+#include "f_diskio.h"
+
+
+static SD sd;
+
+DWORD get_fattime (void){
+ return 0; //hehehehehehehe
+}
+
+WCHAR ff_convert (WCHAR c, UINT dir){
+
+ return c;
+}
+
+WCHAR ff_wtoupper (WCHAR c){
+
+ if(c >= 'a' && c<='z') c -= 'a' - 'A';
+ return c;
+}
+
+DSTATUS disk_initialize (BYTE drv){
+
+ if(drv) return STA_NODISK;
+
+ if(!sdInit(&sd)){
+
+ dbgPrintf("ADK: SD init failed\n");
+ return STA_NODISK;
+ }
+
+ dbgPrintf("disk size: %lu sectors\n", sdGetNumSec(&sd));
+
+ return 0;
+}
+
+DSTATUS disk_status (BYTE drv){
+
+ if(drv) return STA_NODISK;
+
+ return 0;
+}
+
+DRESULT disk_read (BYTE drv, BYTE *buff, DWORD sector, BYTE numSec){
+
+ if(drv) return STA_NODISK;
+
+
+ while(numSec--){
+ if(!sdSecRead(&sd, sector++, buff)) return RES_ERROR;
+ buff+=512;
+ }
+ return RES_OK;
+//this is more clever, but does not yet work
+
+ if(!sdReadStart(&sd, sector)) return RES_ERROR;
+ while(numSec){
+ buff = sdStreamSec(buff);
+ if(--numSec) sdNextSec(&sd);
+ }
+ sdSecReadStop(&sd);
+ return RES_OK;
+}
+
+DRESULT disk_write (BYTE drv, const BYTE *buff, DWORD sector, BYTE numSec){
+
+ if(drv) return STA_NODISK;
+
+ while(numSec--){
+ if(!sdSecWrite(&sd, sector++, buff)) return RES_ERROR;
+ buff+=512;
+ }
+ return RES_OK;
+}
+
+DRESULT disk_ioctl (BYTE drv, BYTE ctrl, void *buff){
+
+ DRESULT res;
+
+ if(drv) return STA_NODISK;
+
+ switch (ctrl){
+ case GET_BLOCK_SIZE:
+ *(DWORD*)buff = 1;
+ res = RES_OK;
+ break;
+
+ case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */
+ *(DWORD*)buff = sdGetNumSec(&sd);
+ res = RES_OK;
+ break;
+
+ case GET_SECTOR_SIZE : /* Get sectors on the disk (WORD) */
+ *(DWORD*)buff = 512;
+ res = RES_OK;
+ break;
+
+ case CTRL_SYNC : /* Make sure that data has been written */
+ res = RES_OK;
+ break;
+
+ default:
+ res = RES_PARERR;
+ }
+ return res;
+}
diff --git a/library/ADK2/fwk.c b/library/ADK2/fwk.c
new file mode 100644
index 0000000..92b4078
--- /dev/null
+++ b/library/ADK2/fwk.c
@@ -0,0 +1,443 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+
+#define TRACE_DEBUG(...)
+#define assert(...)
+
+void PMC_EnablePeripheral( uint32_t dwId )
+{
+ assert( dwId < 45 ) ;
+
+ if ( dwId < 32 )
+ {
+ if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) )
+ {
+ TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", dwId ) ;
+ }
+ else
+ {
+ PMC->PMC_PCER0 = 1 << dwId ;
+ }
+ }
+ else
+ {
+ dwId -= 32;
+ if ((PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId))
+ {
+ TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", dwId + 32 ) ;
+ }
+ else
+ {
+ PMC->PMC_PCER1 = 1 << dwId ;
+ }
+ }
+}
+
+void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration )
+{
+ PMC_EnablePeripheral( dwId ) ;
+ spi->SPI_CR = SPI_CR_SPIDIS ;
+
+ /* Execute a software reset of the SPI twice */
+ spi->SPI_CR = SPI_CR_SWRST ;
+ spi->SPI_CR = SPI_CR_SWRST ;
+ spi->SPI_MR = dwConfiguration ;
+}
+
+void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration )
+{
+ spi->SPI_CSR[dwNpcs] = dwConfiguration ;
+}
+
+void SPI_Enable( Spi* spi )
+{
+ spi->SPI_CR = SPI_CR_SPIEN;
+}
+
+void DACC_Initialize( Dacc* pDACC,
+ uint8_t idDACC,
+ uint8_t trgEn,
+ uint8_t trgSel,
+ uint8_t word,
+ uint8_t sleepMode,
+ uint32_t mck,
+ uint8_t refresh, // refresh period
+ uint8_t user_sel, // user channel selection
+ uint32_t tag_mode, // using tag for channel number
+ uint32_t startup
+ )
+{
+ assert( 1024*refresh*1000/(mck>>1) < 20 ) ;
+
+ // mck is for future usage, remove warnings.
+ mck = mck;
+
+ // Enable peripheral clock
+ PMC_EnablePeripheral(idDACC);
+
+ // Reset the controller
+ DACC_SoftReset(pDACC);
+
+ // Write to the MR register
+ DACC_CfgModeReg( pDACC,
+ ( (trgEn<<0) & DACC_MR_TRGEN)
+ | DACC_MR_TRGSEL(trgSel)
+ | ( (word<<4) & DACC_MR_WORD)
+ | ( (sleepMode<<5) & DACC_MR_SLEEP)
+ | DACC_MR_REFRESH(refresh)
+ | ( (user_sel<<DACC_MR_USER_SEL_Pos)& DACC_MR_USER_SEL_Msk)
+ | ( (tag_mode<<20) & DACC_MR_TAG)
+ | ( (startup<<DACC_MR_STARTUP_Pos) & DACC_MR_STARTUP_Msk));
+}
+
+uint32_t DACC_WriteBuffer( Dacc* pDACC, uint16_t *pwBuffer, uint32_t dwSize )
+{
+
+ // Check if the first PDC bank is free
+ if ( (pDACC->DACC_TCR == 0) && (pDACC->DACC_TNCR == 0) )
+ {
+ pDACC->DACC_TPR = (uint32_t)pwBuffer ;
+ pDACC->DACC_TCR = dwSize ;
+ pDACC->DACC_PTCR = DACC_PTCR_TXTEN ;
+
+ return 1 ;
+ }
+ // Check if the second PDC bank is free
+ else
+ {
+ if (pDACC->DACC_TNCR == 0)
+ {
+ pDACC->DACC_TNPR = (uint32_t)pwBuffer ;
+ pDACC->DACC_TNCR = dwSize ;
+
+ return 1 ;
+ }
+ else
+ {
+ return 0 ;
+ }
+ }
+}
+
+static uint16_t FindClockConfiguration(
+ uint32_t frequency,
+ uint32_t mck)
+{
+ uint32_t divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024};
+ uint8_t divisor = 0;
+ uint32_t prescaler;
+
+ assert(frequency < mck);
+
+ // Find prescaler and divisor values
+ prescaler = (mck / divisors[divisor]) / frequency;
+ while ((prescaler > 255) && (divisor < 11)) {
+
+ divisor++;
+ prescaler = (mck / divisors[divisor]) / frequency;
+ }
+
+ // Return result
+ if ( divisor < 11 )
+ {
+ TRACE_DEBUG( "Found divisor=%u and prescaler=%u for freq=%uHz\n\r", divisors[divisor], prescaler, frequency ) ;
+
+ return prescaler | (divisor << 8) ;
+ }
+ else
+ {
+ return 0 ;
+ }
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+typedef struct PeriodicNode{
+ struct PeriodicNode* next;
+ PeriodicFunc pF;
+ void* pD;
+ uint32_t count;
+ uint32_t reload;
+}PeriodicNode;
+
+
+
+volatile static uint64_t msec = 0;
+volatile static PeriodicNode* periodics = 0;
+
+static uint8_t volume = 255;
+
+#define JOINER(x,y,z) x ## y ## z
+#define CALLER(x,y,z) JOINER(x,y,z)
+#define TIMER_NAME CALLER(TC, TIMER_FOR_ADK, _Handler)
+#define IRQ_NAME CALLER(TC, TIMER_FOR_ADK, _IRQn)
+
+void TIMER_NAME(){
+
+ uint32_t unused = TC0->TC_CHANNEL[TIMER_FOR_ADK].TC_SR;
+ PeriodicNode* n = periodics;
+
+ msec++;
+
+ while(n){
+
+ if(!--n->count){
+
+ n->pF(n->pD);
+ n->count = n->reload;
+ }
+ n = n->next;
+ }
+}
+
+uint64_t fwkGetUptime(void){
+
+ uint64_t t;
+
+ do{
+ t = msec;
+ }while(t != msec);
+
+ return t;
+}
+
+uint64_t fwkGetTicks(void){
+
+ uint64_t hi;
+ uint32_t lo;
+
+ do{
+ lo = TC0->TC_CHANNEL[TIMER_FOR_ADK].TC_CV;
+ hi = msec;
+ }while(lo > TC0->TC_CHANNEL[TIMER_FOR_ADK].TC_CV);
+
+ return (hi * TICKS_PER_MS) + lo;
+}
+
+void fwkDelay(uint64_t ticks){
+
+ uint64_t start = fwkGetTicks();
+
+ while(fwkGetTicks() - start < ticks);
+}
+
+void periodicAdd(PeriodicFunc f, void* data, uint32_t periodMs){
+
+ PeriodicNode* n = malloc(sizeof(PeriodicNode));
+ uint32_t failed = 0;
+
+ n->reload = n->count = periodMs;
+ n->pF = f;
+ n->pD = data;
+
+ do{
+ asm(
+ "ldrex r0, [%1] \n\t" //atomic linked list addition..booyah!
+ "str r0, [%2] \n\t"
+ "strex %0, %3, [%1] \n\t"
+ :"=r"(failed)
+ :"r"(&periodics), "r"(&n->next), "r"(n)
+ :"r0"
+ );
+ }while(failed);
+}
+
+void periodicDel(PeriodicFunc f){
+
+ uint32_t failed;
+
+ PeriodicNode* p = 0;
+ PeriodicNode* n = periodics;
+
+ while(n && n != f){
+
+ p = n;
+ n = n->next;
+ }
+ if(!n) return; //nothing to delete
+
+ if(p) p->next = n->next;
+ else periodics = n->next;
+ free(n);
+}
+
+static void __attribute__((naked)) cpuGetUniqIdFunc(uint32_t interfaceAddr, uint32_t cmd1, uint32_t cmd2, uint32_t* buf){
+
+ asm(
+ " cpsid i \n\t" // There is some pretty scary stuff that can happen
+ " mov r12, r2 \n\t" // if you reset the device while this code is in
+ " str r1, [r0, #4] \n\t" // the middle of doing its thing. Sometimes the
+ "lbl_wait_1: \n\t" // flash controller does not get reset to "code"
+ " ldr r1, [r0, #8] \n\t" // mode and stays in "read unique ID" mode, even
+ " lsrs r1, #1 \n\t" // when the chip itself is externally reset. This
+ " bcs lbl_wait_1 \n\t" // will cause the unique ID to be treated like the
+ " mov r2, #0x00080000 \n\t" // vector table. Needless to say: the chip unique
+ " ldr r1, [r2, #0] \n\t" // ID is not a suitable vector table. After reset,
+ " str r1, [r3, #0] \n\t" // this will likely cause the chip to take a hard
+ " ldr r1, [r2, #4] \n\t" // fault immediately. Worse yet, the hard fault
+ " str r1, [r3, #4] \n\t" // handler vector will also be invalid, causing
+ " ldr r1, [r2, #8] \n\t" // the chip to take yet another hard fault. This
+ " str r1, [r3, #8] \n\t" // will continue forever. The debug bridge, as it
+ " ldr r1, [r2, #12] \n\t" // currently is, cannot handle this chip state.
+ " str r1, [r3, #12] \n\t" // It will be unable to flash or debug the chip,
+ " str r12, [r0, #4] \n\t" // and you - the user - will be sad. The practical
+ "lbl_wait_2: \n\t" // upshot of all this: use this code rarely, and
+ " ldr r1, [r0, #8] \n\t" // if you interrupt it, power-cycle the system if
+ " lsrs r1, #1 \n\t" // you suspect that you somehow got into this
+ " bcc lbl_wait_2 \n\t" // weird state. It is possible that future revs
+ " cpsie i \n\t" // of SAM3X will fix this issue by properly
+ " bx lr \n\t" // resetting the flash controller at reset time.
+ );
+}
+
+void cpuGetUniqId(uint32_t* dst){ //produce the 128-bit unique ID
+
+ const unsigned numInstr = 23; //it better match the above function...
+ uint16_t buffer[numInstr];
+ uint16_t* src = (uint16_t*)(((uint32_t)&cpuGetUniqIdFunc) &~ 1);
+ unsigned i;
+
+ for(i = 0; i < numInstr; i++) buffer[i] = *src++;
+
+ ((void (*)(uint32_t,uint32_t,uint32_t,uint32_t*))(((uint32_t)buffer) + 1))(0x400E0A00, 0x5A00000E, 0x5A00000F, dst);
+}
+
+void fwkInit(void){
+
+ //clock & periodic setup (MCLK/2, interrupt every ms)
+ PMC_EnablePeripheral(ID_TC0);
+ TC0->TC_CHANNEL[TIMER_FOR_ADK].TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_WAVSEL_UP_RC | TC_CMR_WAVE;
+ TC0->TC_CHANNEL[TIMER_FOR_ADK].TC_CV = 0;
+ TC0->TC_CHANNEL[TIMER_FOR_ADK].TC_RC = TICKS_PER_MS;
+ TC0->TC_CHANNEL[TIMER_FOR_ADK].TC_IER = TC_IER_CPCS;
+ TC0->TC_CHANNEL[TIMER_FOR_ADK].TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;
+ NVIC_EnableIRQ(IRQ_NAME);
+
+ //IO on
+ PMC_EnablePeripheral(ID_PIOC);
+ PMC_EnablePeripheral(ID_PIOB);
+ PMC_EnablePeripheral(ID_PIOA);
+
+ //dma setup
+ PMC_EnablePeripheral(ID_DMAC);
+ DMAC->DMAC_EBCIDR = 0x003F3F3F; //disable all interrupts
+ DMAC->DMAC_CHDR = 0x0000003F; //disable all channels
+ DMAC->DMAC_EN = 1;
+}
+
+#define PER 0
+#define PDR 1
+#define OER 4
+#define ODR 5
+#define SODR 12
+#define CODR 13
+#define PDSR 15
+#define PUDR 24
+#define PUER 25
+#define ABSR 28
+
+static inline volatile uint32_t* gpioGetPort(uint8_t pin){
+
+ uint32_t addr = pin >> 5;
+ addr <<= 9;
+ addr += 0x400E0E00;
+
+ return (volatile uint32_t*)addr;
+}
+
+static inline uint32_t gpioGetBit(uint8_t pin){
+
+ return 1UL << (pin & 31);
+}
+
+void gpioSetFun(uint8_t pin, uint8_t func){
+
+ volatile uint32_t* port = gpioGetPort(pin);
+ uint32_t bit = gpioGetBit(pin);
+
+ if(func == GPIO_FUNC_GPIO){
+
+ port[PER] = bit;
+ }
+ else{
+
+ port[PDR] = bit;
+ if(func == GPIO_FUNC_A) port[ABSR] &=~ bit;
+ else port[ABSR] |= bit;
+ }
+}
+
+void gpioSetDir(uint8_t pin, char in){
+
+ volatile uint32_t* port = gpioGetPort(pin);
+ uint32_t bit = gpioGetBit(pin);
+
+ if(in) port[ODR] = bit;
+ else port[OER] = bit;
+}
+
+void gpioSetVal(uint8_t pin, char on){
+
+ volatile uint32_t* port = gpioGetPort(pin);
+ uint32_t bit = gpioGetBit(pin);
+
+ if(on) port[SODR] = bit;
+ else port[CODR] = bit;
+}
+
+char gpioGetVal(uint8_t pin){
+
+ volatile uint32_t* port = gpioGetPort(pin);
+ uint32_t bit = gpioGetBit(pin);
+
+ return (port[PDSR] & bit) != 0;
+}
+
+void gpioSetPullup(uint8_t pin, char on){
+
+ volatile uint32_t* port = gpioGetPort(pin);
+ uint32_t bit = gpioGetBit(pin);
+
+ if(on) port[PUER] = bit;
+ else port[PUDR] = bit;
+}
+
+uint8_t getVolume(void){
+
+ return volume;
+}
+
+void setVolume(uint8_t vol){
+
+ volume = vol;
+}
+
+
+
diff --git a/library/ADK2/fwk.h b/library/ADK2/fwk.h
new file mode 100644
index 0000000..e8b8be5
--- /dev/null
+++ b/library/ADK2/fwk.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _ADK_FWK_H_
+#define _ADK_FWK_H_
+
+#include <stdint.h>
+#include <stdlib.h>
+
+//stuff we need from Atmel's build system
+ #define sam3x8
+ #include "SAM3XA.h"
+ void PMC_EnablePeripheral( uint32_t dwId );
+ void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration );
+ void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration );
+ void SPI_Enable( Spi* spi );
+ void DACC_Initialize( Dacc* pDACC,uint8_t idDACC,uint8_t trgEn,uint8_t trgSel,uint8_t word,uint8_t sleepMode,uint32_t mck,uint8_t refresh,uint8_t user_sel, uint32_t tag_mode,uint32_t startup);
+ uint32_t DACC_WriteBuffer( Dacc* pDACC, uint16_t *pwBuffer, uint32_t dwSize );
+ #define DACC_EnableChannel(pDACC, channel) (pDACC)->DACC_CHER = (1 << (channel));
+ #define DACC_DisableChannel(pDACC, channel) (pDACC)->DACC_CHDR = (1 << (channel));
+ #define DACC_CHANNEL_0 0
+ #define DACC_CHANNEL_1 1
+ #define DACC_CfgModeReg(pDACC, mode) (pDACC)->DACC_MR = (mode);
+ #define DACC_SoftReset(pDACC) ((pDACC)->DACC_CR = DACC_CR_SWRST)
+ void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck);
+ void PWMC_ConfigureChannel(Pwm* pPwm,uint8_t channel,uint32_t prescaler,uint32_t alignment,uint32_t polarity);
+ void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period);
+ void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, uint32_t value, uint32_t mode);
+ void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode);
+ void PWMC_EnableChannel( Pwm* pPwm, uint8_t channel);
+
+
+//common
+
+ #define NULL 0
+
+ #define BOARD_MCK 84000000ULL
+ #define TICKS_PER_MS ((BOARD_MCK) / 2000)
+ #define ADK_HEAP_SZ 65536
+
+ void fwkInit(void);
+ uint64_t fwkGetUptime(void);
+ uint64_t fwkGetTicks(void);
+ void fwkDelay(uint64_t ticks);
+
+ #define delay_s(s) fwkDelay(TICKS_PER_MS * 1000ULL * (unsigned long long)(ms))
+ #define delay_ms(ms) fwkDelay(TICKS_PER_MS * (unsigned long long)(ms))
+ #define delay_us(us) fwkDelay((TICKS_PER_MS * (unsigned long long)(ms)) / 1000ULL)
+
+ typedef void (*PeriodicFunc)(void* data);
+ void periodicAdd(PeriodicFunc f, void* data, uint32_t periodMs);
+ void periodicDel(PeriodicFunc f);
+
+ void cpuGetUniqId(uint32_t* dst); //produce the 128-bit unique ID
+
+ #define DMA_CHANNEL_LEDS 0
+ #define TIMER_FOR_ADK 0 // only in timer unit 0
+
+ uint8_t getVolume(void);
+ void setVolume(uint8_t);
+
+
+//GPIO stuffs
+
+ #define PORTA(x) (x)
+ #define PORTB(x) ((x) + 32)
+ #define PORTC(x) ((x) + 64)
+ #define PORTD(x) ((x) + 96)
+ #define PORTE(x) ((x) + 128)
+ #define PORTF(x) ((x) + 160)
+
+ #define GPIO_FUNC_GPIO 0
+ #define GPIO_FUNC_A 1
+ #define GPIO_FUNC_B 2
+
+ void gpioSetFun(uint8_t pin, uint8_t func);
+ void gpioSetDir(uint8_t pin, char in);
+ void gpioSetVal(uint8_t pin, char on);
+ char gpioGetVal(uint8_t pin);
+ void gpioSetPullup(uint8_t pin, char on);
+
+
+#endif
+#endif
+
+
diff --git a/library/ADK2/hygro.c b/library/ADK2/hygro.c
new file mode 100644
index 0000000..5ceb014
--- /dev/null
+++ b/library/ADK2/hygro.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "I2C.h"
+#include "hygro.h"
+#include "dbg.h"
+
+#define HYGRO_HOLD 1
+
+#define HYGRO_I2C_ADDR 0x40
+#define HYGRO_TRIG_TEMP_HOLD 0xE3
+#define HYGRO_TRIG_HUM_HOLD 0xE5
+#define HYGRO_TRIG_TEMP 0xF3
+#define HYGRO_TRIG_HUM 0xF5
+#define HYGRO_WRITE_USER 0xE6
+#define HYGRO_READ_USER 0xE7
+#define HYGRO_RESET 0xFE
+
+#define TEMP_SLOPE (175.72)
+#define TEMP_OFFSET (-46.85)
+#define HUM_SLOPE (125)
+#define HUM_OFFSET (-6)
+char hygroInit( void )
+{
+ if (I2C_ALL_OK != i2cSingleWrite(1, HYGRO_I2C_ADDR, HYGRO_WRITE_USER, 0x02)) // Write defaults to user register
+ return 0;
+ return 1;
+}
+
+char hygroRead( int32_t *temp, int32_t *humidity )
+{
+ uint8_t cmd, vals[2], ret;
+ uint16_t val;
+ int32_t stat, oldstat, tmp;
+#if HYGRO_HOLD
+ cmd = HYGRO_TRIG_TEMP_HOLD;
+ if (I2C_ALL_OK != i2cOp(1, HYGRO_I2C_ADDR, &cmd, 1, vals, 2))
+ return 0;
+#else
+ cmd = HYGRO_TRIG_TEMP;
+ if (I2C_ALL_OK != i2cOp(1, HYGRO_I2C_ADDR, &cmd, 1, NULL, 0))
+ return 0;
+ do {
+ stat = i2cOp(1, HYGRO_I2C_ADDR, NULL, 0, vals, 2);
+ } while (stat != I2C_ALL_OK);
+#endif
+
+ val = (vals[1] & 0xFC) | (((uint16_t)vals[0]) << 8);
+
+ *temp = (int)(TEMP_OFFSET * 8) + ((int)(TEMP_SLOPE * 8) * (int)val / 65536); // 8 fixed point
+
+#if HYGRO_HOLD
+ cmd = HYGRO_TRIG_HUM_HOLD;
+ if (I2C_ALL_OK != i2cOp(1, HYGRO_I2C_ADDR, &cmd, 1, vals, 2))
+ return 0;
+#else
+ cmd = HYGRO_TRIG_HUM;
+ if (I2C_ALL_OK != i2cOp(1, HYGRO_I2C_ADDR, &cmd, 1, NULL, 0))
+ return 0;
+ do {
+ stat = i2cOp(1, HYGRO_I2C_ADDR, NULL, 0, vals, 2);
+ } while (stat != I2C_ALL_OK);
+#endif
+
+ val = (vals[1] & 0xFC) | (((uint16_t)vals[0]) << 8);
+ *humidity = (int32_t)(HUM_OFFSET * 8) + ((int32_t)(HUM_SLOPE * 8) * (int32_t)val / 65536);
+ return 1;
+}
diff --git a/library/ADK2/hygro.h b/library/ADK2/hygro.h
new file mode 100644
index 0000000..cf1d01b
--- /dev/null
+++ b/library/ADK2/hygro.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _HYGRO_H_
+#define _HYGRO_H_
+
+
+char hygroInit( void );
+char hygroRead( int32_t *temp, int32_t *humidity );
+
+
+#endif
+#endif
+
diff --git a/library/ADK2/mag.c b/library/ADK2/mag.c
new file mode 100644
index 0000000..0f218e8
--- /dev/null
+++ b/library/ADK2/mag.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "mag.h"
+#include "I2C.h"
+
+
+
+
+char magInit(void){ //1->success, 0->fail
+
+ if(i2cSingleRead(1, 0x1E, 0x0A) != 0x48) return 0; //not found
+ if(i2cSingleRead(1, 0x1E, 0x0B) != 0x34) return 0; //not found
+ if(i2cSingleRead(1, 0x1E, 0x0C) != 0x33) return 0; //not found
+
+ i2cSingleWrite(1, 0x1E, 0x00, 0x14); // No temp sensor
+ i2cSingleWrite(1, 0x1E, 0x01, 0x20); // Gain setting of 1.3 gauss
+ i2cSingleWrite(1, 0x1E, 0x02, 0x00); // Continuous conversion mode
+
+ return 1;
+}
+
+void magRead(int16_t* x, int16_t* y, int16_t* z) {
+
+ while(!(i2cSingleRead(1, 0x1E, 0x09) & 1)); //wait
+
+ if(x) *x = (int16_t)(((uint16_t)i2cSingleRead(1, 0x1E, 0x03) << 8) | (uint16_t)i2cSingleRead(1, 0x1E, 0x04));
+ if(y) *y = (int16_t)(((uint16_t)i2cSingleRead(1, 0x1E, 0x05) << 8) | (uint16_t)i2cSingleRead(1, 0x1E, 0x06));
+ if(z) *z = (int16_t)(((uint16_t)i2cSingleRead(1, 0x1E, 0x07) << 8) | (uint16_t)i2cSingleRead(1, 0x1E, 0x08));
+}
diff --git a/library/ADK2/mag.h b/library/ADK2/mag.h
new file mode 100644
index 0000000..12f0d87
--- /dev/null
+++ b/library/ADK2/mag.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _MAG_H_
+#define _MAG_H_
+
+char magInit(void);
+void magRead(int16_t* x, int16_t* y, int16_t* z);
+
+#endif
+#endif
+
diff --git a/library/ADK2/printf.c b/library/ADK2/printf.c
new file mode 100644
index 0000000..c8ae62a
--- /dev/null
+++ b/library/ADK2/printf.c
@@ -0,0 +1,465 @@
+/*
+Copyright (c) 2011, Dmitry Grinberg (as published for DGOS on http://dgosblog.blogspot.com)
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following condition is met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "printf.h"
+#include <stdarg.h>
+
+typedef struct {
+
+ void* dest;
+ uint32_t maxChars;
+
+ void* furtherCallback;
+ void* furtherUserData;
+
+} PrintData;
+
+typedef char (*StrPrintfExCbk)(void* userData, char chr); //return 0 to stop printing
+
+static uint32_t StrPrvPrintfEx_number(StrPrintfExCbk putc_,void* userData,unsigned long long number,uint32_t base,char zeroExtend,char isSigned,char capitals,uint32_t padToLength, char* bail){
+
+ char buf[64];
+ uint32_t idx = sizeof(buf) - 1;
+ uint32_t chr, i;
+ char neg = 0;
+ uint32_t numPrinted = 0;
+
+ *bail = 0;
+
+ if(padToLength > 63) padToLength = 63;
+
+ buf[idx--] = 0; //terminate
+
+ if(isSigned){
+
+ if(number & 0x8000000000000000ULL){
+
+ neg = 1;
+ number = -number;
+ }
+ }
+
+ do{
+ chr = number % base;
+ number = number / base;
+
+ buf[idx--] = (chr >= 10)?(chr + (capitals ? 'A' : 'a') - 10):(chr + '0');
+
+ numPrinted++;
+
+ }while(number);
+
+ if(neg){
+
+ buf[idx--] = '-';
+ numPrinted++;
+ }
+
+ if(padToLength > numPrinted){
+
+ padToLength -= numPrinted;
+ }
+ else{
+
+ padToLength = 0;
+ }
+
+ while(padToLength--){
+
+ buf[idx--] = zeroExtend?'0':' ';
+ numPrinted++;
+ }
+
+ idx++;
+
+
+ for(i = 0; i < numPrinted; i++){
+
+ if(!putc_(userData,(buf + idx)[i])){
+
+ *bail = 1;
+ break;
+ }
+ }
+
+
+ return numPrinted;
+}
+
+static uint32_t StrVPrintf_StrLen_withMax(const char* s,uint32_t max){
+
+ uint32_t len = 0;
+
+ while((*s++) && (len < max)) len++;
+
+ return len;
+}
+
+static uint32_t StrVPrintf_StrLen(const char* s){
+
+ uint32_t len = 0;
+
+ while(*s++) len++;
+
+ return len;
+}
+
+static inline char prvGetChar(const char** fmtP){
+
+ char ret;
+ const char* fmt;
+
+ fmt = *fmtP;
+ ret = *fmt++;
+ *fmtP = fmt;
+
+ return ret;
+}
+
+static unsigned long long SignExt32to64(uint32_t v_){
+
+ unsigned long long v = v_;
+
+ if(v & 0x80000000) v |= 0xFFFFFFFF00000000ULL;
+
+ return v;
+}
+
+static uint32_t StrVPrintfEx(StrPrintfExCbk putc_f,void* userData, const char* fmtStr,va_list vl){
+
+ char c;
+ uint32_t i, numPrinted = 0;
+ unsigned long long val64;
+
+#define putc_(_ud,_c) if(!putc_f(_ud,_c)) goto out;
+
+ while((c = prvGetChar(&fmtStr)) != 0){
+
+ if(c == '\n'){
+
+ putc_(userData,c);
+ numPrinted++;
+ }
+ else if(c == '%'){
+
+ char zeroExtend = 0, useLong = 0, bail = 0, useVeryLong = 0;
+ uint32_t padToLength = 0,len;
+ const char* str;
+ int capitals = 0;
+
+more_fmt:
+
+ c = prvGetChar(&fmtStr);
+
+ switch(c){
+
+ case '%':
+
+ putc_(userData,c);
+ numPrinted++;
+ break;
+
+ case 'c':
+
+ putc_(userData,va_arg(vl,unsigned int));
+ numPrinted++;
+ break;
+
+ case 's':
+
+ str = va_arg(vl,char*);
+ if(!str) str = "(null)";
+ if(padToLength){
+
+ len = StrVPrintf_StrLen_withMax(str,padToLength);
+ }
+ else{
+
+ padToLength = len = StrVPrintf_StrLen(str);
+ }
+ if(len > padToLength) len = padToLength;
+ else{
+
+ for(i=len;i<padToLength;i++) putc_(userData,L' ');
+ }
+ numPrinted += padToLength;
+ for(i = 0; i < len; i++){
+
+ putc_(userData,*str++);
+ }
+ numPrinted += len;
+ break;
+
+ case '0':
+
+ if(!zeroExtend && !padToLength){
+
+ zeroExtend = 1;
+ goto more_fmt;
+ }
+
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+
+ padToLength = (padToLength * 10) + c - '0';
+ goto more_fmt;
+
+ case 'u':
+
+ val64 = useVeryLong ? va_arg(vl,unsigned long long) : va_arg(vl,uint32_t);
+ numPrinted += StrPrvPrintfEx_number(putc_f, userData,val64,10,zeroExtend,0,0,padToLength, &bail);
+ if(bail) goto out;
+ break;
+
+ case 'd':
+
+ val64 = useVeryLong ? va_arg(vl,unsigned long long) : SignExt32to64(va_arg(vl,uint32_t));
+ numPrinted += StrPrvPrintfEx_number(putc_f, userData,val64,10,zeroExtend,1,0,padToLength, &bail);
+ if(bail) goto out;
+ break;
+
+ case 'X':
+
+ capitals = 1;
+
+ case 'x':
+
+ val64 = useVeryLong ? va_arg(vl,unsigned long long) : va_arg(vl,uint32_t);
+ numPrinted += StrPrvPrintfEx_number(putc_f, userData,val64,16,zeroExtend,0,capitals,padToLength, &bail);
+ if(bail) goto out;
+ break;
+
+ case 'p':
+
+ putc_(userData,'0');
+ numPrinted++;
+ putc_(userData,'x');
+ numPrinted++;
+
+ val64 = va_arg(vl,unsigned long);
+ numPrinted += StrPrvPrintfEx_number(putc_f, userData,val64,16,0,0,0,0, &bail);
+ if(bail) goto out;
+ break;
+
+ case 'b':
+
+ val64 = useVeryLong ? va_arg(vl,unsigned long long) : va_arg(vl,uint32_t);
+ numPrinted += StrPrvPrintfEx_number(putc_f, userData,val64,2,zeroExtend,0,0,padToLength, &bail);
+ if(bail) goto out;
+ break;
+
+ case 'l':
+ if(useLong) useVeryLong = 1;
+ useLong = 1;
+ goto more_fmt;
+
+ default:
+
+ putc_(userData,c);
+ numPrinted++;
+ break;
+ }
+ }
+ else{
+
+ putc_(userData,c);
+ numPrinted++;
+ }
+ }
+
+ putc_(userData,0); //terminate it
+ numPrinted++;
+
+out:
+
+ return numPrinted;
+}
+
+
+static char StrPrintF_putc(void* ud, char c){
+
+ PrintData* pd = ud;
+ char** dst = pd->dest;
+ char ret = 1;
+
+ if(pd->maxChars-- == 1){
+
+ c = 0;
+ ret = 0;
+ }
+
+ if(pd->furtherCallback){
+
+ ret = ((printf_write_c)pd->furtherCallback)(pd->furtherUserData, c);
+ }
+ else{
+ *(*dst)++ = c;
+ }
+
+
+ return ret;
+}
+
+uint32_t _sprintf(char* dst, const char* fmtStr, ...){
+
+ uint32_t ret;
+ va_list vl;
+ PrintData pd;
+
+ pd.dest = &dst;
+ pd.maxChars = 0xFFFFFFFF;
+ pd.furtherCallback = NULL;
+
+ va_start(vl,fmtStr);
+
+ ret = StrVPrintfEx(&StrPrintF_putc, &pd, fmtStr,vl);
+
+ va_end(vl);
+
+ return ret;
+}
+
+uint32_t _snprintf(char* dst, uint32_t maxChars, const char* fmtStr, ...){
+
+ uint32_t ret;
+ va_list vl;
+ PrintData pd;
+
+ pd.dest = &dst;
+ pd.maxChars = maxChars;
+ pd.furtherCallback = NULL;
+
+ va_start(vl,fmtStr);
+
+ ret = StrVPrintfEx(&StrPrintF_putc, &pd, fmtStr,vl);
+
+ va_end(vl);
+
+ return ret;
+}
+
+uint32_t _csprintf(printf_write_c writeF, void* writeD, const char* fmtStr, ...){
+
+ uint32_t ret;
+ va_list vl;
+ PrintData pd;
+
+ pd.dest = NULL;
+ pd.maxChars = 0xFFFFFFFF;
+ pd.furtherCallback = writeF;
+ pd.furtherUserData = writeD;
+
+ va_start(vl,fmtStr);
+
+ ret = StrVPrintfEx(&StrPrintF_putc, &pd, fmtStr,vl);
+
+ va_end(vl);
+
+ return ret;
+}
+
+uint32_t _csnprintf(printf_write_c writeF, void* writeD, uint32_t maxChars, const char* fmtStr, ...){
+
+ uint32_t ret;
+ va_list vl;
+ PrintData pd;
+
+ pd.dest = NULL;
+ pd.maxChars = maxChars;
+ pd.furtherCallback = writeF;
+ pd.furtherUserData = writeD;
+
+ va_start(vl,fmtStr);
+
+ ret = StrVPrintfEx(&StrPrintF_putc, &pd, fmtStr,vl);
+
+ va_end(vl);
+
+ return ret;
+}
+
+uint32_t _vsprintf(char* dst, const char* fmtStr, va_list vl){
+
+ uint32_t ret;
+ PrintData pd;
+
+ pd.dest = &dst;
+ pd.maxChars = 0xFFFFFFFF;
+ pd.furtherCallback = NULL;
+
+ ret = StrVPrintfEx(&StrPrintF_putc, &pd, fmtStr,vl);
+
+ return ret;
+}
+
+uint32_t _vsnprintf(char* dst, uint32_t maxChars, const char* fmtStr, va_list vl){
+
+ uint32_t ret;
+ PrintData pd;
+
+ pd.dest = &dst;
+ pd.maxChars = maxChars;
+ pd.furtherCallback = NULL;
+
+ ret = StrVPrintfEx(&StrPrintF_putc, &pd, fmtStr,vl);
+
+ return ret;
+}
+
+uint32_t _cvsprintf(printf_write_c writeF, void* writeD, const char* fmtStr, va_list vl){
+
+ uint32_t ret;
+ PrintData pd;
+
+ pd.dest = NULL;
+ pd.maxChars = 0xFFFFFFFF;
+ pd.furtherCallback = writeF;
+ pd.furtherUserData = writeD;
+
+ ret = StrVPrintfEx(&StrPrintF_putc, &pd, fmtStr,vl);
+
+ return ret;
+}
+
+uint32_t _cvsnprintf(printf_write_c writeF, void* writeD, uint32_t maxChars, const char* fmtStr, va_list vl){
+
+ uint32_t ret;
+ PrintData pd;
+
+ pd.dest = NULL;
+ pd.maxChars = maxChars;
+ pd.furtherCallback = writeF;
+ pd.furtherUserData = writeD;
+
+ ret = StrVPrintfEx(&StrPrintF_putc, &pd, fmtStr,vl);
+
+ return ret;
+}
diff --git a/library/ADK2/printf.h b/library/ADK2/printf.h
new file mode 100644
index 0000000..eeb532d
--- /dev/null
+++ b/library/ADK2/printf.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _PRINTF_H_
+#define _PRINTF_H_
+
+#include <stdarg.h>
+
+typedef char (*printf_write_c)(void* userData, char c); //return 0 to stop printing, else 1
+
+
+uint32_t _sprintf(char* dst, const char* fmtStr, ...);
+uint32_t _snprintf(char* dst, uint32_t maxChars, const char* fmtStr, ...);
+uint32_t _csprintf(printf_write_c writeF, void* writeD, const char* fmtStr, ...);
+uint32_t _csnprintf(printf_write_c writeF, void* writeD, uint32_t maxChars, const char* fmtStr, ...);
+uint32_t _vsprintf(char* dst, const char* fmtStr, va_list vl);
+uint32_t _vsnprintf(char* dst, uint32_t maxChars, const char* fmtStr, va_list vl);
+uint32_t _cvsprintf(printf_write_c writeF, void* writeD, const char* fmtStr, va_list vl);
+uint32_t _cvsnprintf(printf_write_c writeF, void* writeD, uint32_t maxChars, const char* fmtStr, va_list vl);
+
+#endif
+#endif
+
diff --git a/library/ADK2/sgBuf.c b/library/ADK2/sgBuf.c
new file mode 100644
index 0000000..c030ba8
--- /dev/null
+++ b/library/ADK2/sgBuf.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "sgBuf.h"
+#include <string.h>
+
+
+#define INFO_MASK_NEEDS_FREE 0x80000000
+#define INFO_MASK_SIZE 0x00FFFFFF
+
+
+void sg_init(sg_buf* buf){
+
+ buf->first = NULL;
+ buf->last = NULL;
+ buf->totalLen = 0;
+}
+
+sg_buf* sg_alloc(void){
+
+ sg_buf* b = malloc(sizeof(sg_buf));
+ if(b) sg_init(b);
+
+ return b;
+}
+
+void sg_free(sg_buf* buf){
+
+ sg_buf_node* n = buf->first;
+ sg_buf_node* t;
+
+ while(n){
+
+ if(n->info & INFO_MASK_NEEDS_FREE) free(n->data);
+
+ t = n->next;
+ free(n);
+ n = t;
+ }
+}
+
+uint32_t sg_length(const sg_buf* buf){
+
+ return buf->totalLen;
+}
+
+static sg_buf_node* sg_alloc_node(const uint8_t* data, uint32_t len, uint8_t flags){
+
+ sg_buf_node* n;
+ uint32_t sz;
+
+ if(len &~ INFO_MASK_SIZE) return NULL; //too big
+
+ sz = sizeof(sg_buf_node);
+ if(flags & SG_FLAG_MAKE_A_COPY) sz += len;
+
+ n = malloc(sz);
+
+ if(n){
+
+ if(flags & SG_FLAG_MAKE_A_COPY){
+
+ uint8_t* ptr = (uint8_t*)(n + 1);
+ memcpy(ptr, data, len);
+ data = ptr;
+ flags &=~ SG_FLAG_NEEDS_FREEING; //definitely not
+ }
+
+ n->info = len | ((flags & SG_FLAG_NEEDS_FREEING) ? INFO_MASK_NEEDS_FREE : 0);
+ n->data = data;
+ }
+ return n;
+}
+
+char sg_add_front(sg_buf* buf, const uint8_t* data, uint32_t len, uint8_t flags){
+
+ sg_buf_node* n = sg_alloc_node(data, len, flags);
+
+ if(!n) return 0;
+
+ n->next = buf->first;
+ buf->first = n;
+ if(!buf->last) buf->last = n;
+
+ buf->totalLen += len;
+
+ return 1;
+}
+
+char sg_add_back(sg_buf* buf, const uint8_t* data, uint32_t len, uint8_t flags){
+
+ sg_buf_node* n = sg_alloc_node(data, len, flags);
+
+ if(!n) return 0;
+
+ n->next = NULL;
+ if(buf->last) buf->last->next = n;
+ else buf->first = n;
+ buf->last = n;
+
+ buf->totalLen += len;
+
+ return 1;
+}
+
+void sg_concat_back(sg_buf* buf, sg_buf* second){
+
+ buf->totalLen += second->totalLen;
+
+ if(buf->last) buf->last->next = second->first;
+ else buf->first = second->first;
+ buf->last = second->last;
+
+ sg_init(second);
+}
+
+void sg_concat_front(sg_buf* buf, sg_buf* second){
+
+ sg_concat_back(second, buf);
+ *buf = *second;
+
+ sg_init(buf);
+}
+
+sg_iter sg_iter_start(const sg_buf* buf){
+
+ return (sg_iter)(buf->first);
+}
+
+char sg_iter_next(sg_iter* iterP, const uint8_t** buf, uint32_t* sz){
+
+ sg_buf_node* n = (sg_buf_node*)*iterP;
+
+ if(!n) return 0; //end of line
+
+ if(buf) *buf = n->data;
+ if(sz) *sz = n->info & INFO_MASK_SIZE;
+
+ *iterP = n->next;
+ return 1;
+}
+
+void sg_copyto(const sg_buf* buf, uint8_t* dst){
+
+ sg_buf_node* n = buf->first;
+ uint32_t len;
+
+ while(n){
+
+ len = n->info & INFO_MASK_SIZE;
+
+ memcpy(dst, n->data, len);
+ dst += len;
+
+ n = n->next;
+ }
+}
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/library/ADK2/sgBuf.h b/library/ADK2/sgBuf.h
new file mode 100644
index 0000000..4ebb45d
--- /dev/null
+++ b/library/ADK2/sgBuf.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _SG_BUF_H_
+#define _SG_BUF_H_
+
+
+/*
+ sg_buf is a linked-list based buffer which makes it easy to encapsulate
+ data in places like bluetooth, where each layer needs to add some data
+ to the packet on its way out. This is batter than normal buffers since
+ no data has to be moved and header sizes need nto be known ahead of time.
+*/
+
+typedef struct sg_buf_node{
+
+ struct sg_buf_node* next;
+ uint32_t info;
+ const uint8_t* data;
+
+}sg_buf_node;
+
+typedef struct{
+
+ sg_buf_node* first;
+ sg_buf_node* last;
+ uint32_t totalLen;
+
+}sg_buf;
+
+typedef void* sg_iter;
+
+#define SG_BUF_STATIC_INITIALIZER {NULL, NULL, 0}
+
+#define SG_FLAG_NEEDS_FREEING 1
+#define SG_FLAG_MAKE_A_COPY 2
+
+void sg_init(sg_buf* buf);
+sg_buf* sg_alloc(void);
+void sg_free(sg_buf* buf);
+uint32_t sg_length(const sg_buf* buf);
+char sg_add_front(sg_buf* buf, const uint8_t* data, uint32_t len, uint8_t flags); //0 on fail
+char sg_add_back(sg_buf* buf, const uint8_t* data, uint32_t len, uint8_t flags); //0 on fail
+
+void sg_concat_front(sg_buf* buf, sg_buf* second); //prepend second to buf
+void sg_concat_back(sg_buf* buf, sg_buf* second); //append second to buf
+
+sg_iter sg_iter_start(const sg_buf* buf);
+char sg_iter_next(sg_iter* iterP, const uint8_t** buf, uint32_t* sz);
+
+void sg_copyto(const sg_buf* buf, uint8_t* dst);
+
+#endif
+#endif
diff --git a/library/ADK2/simpleOgg.c b/library/ADK2/simpleOgg.c
new file mode 100644
index 0000000..899faf6
--- /dev/null
+++ b/library/ADK2/simpleOgg.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "fwk.h"
+#include "simpleOgg.h"
+#include "Audio.h"
+#include "coop.h"
+#include "f_ff.h"
+#include "v_ivorbiscodec.h"
+#include "v_ivorbisfile.h"
+
+static size_t oggRead2(void *ptr, size_t size, size_t nmemb, void *data){
+
+ FIL *f = data;
+ FRESULT r;
+ UINT read = 0;
+
+ read = size * nmemb;
+ if(read + f->fptr > f->fsize) read = f->fsize - f->fptr;
+ if(!read) return 0;
+
+ r = f_read(f, ptr, size * nmemb, &read);
+
+ if(r) return 0;
+ return read / size;
+}
+
+static int oggSeek2(void *data, ogg_int64_t offset, int whence){
+
+ return -1;
+}
+
+static int oggClose2(void *data){
+
+ FIL *f = data;
+
+ f_close(f);
+ return 0;
+}
+
+static long oggTell2(void *data){
+
+ FIL *f = data;
+
+ return f->fptr;
+}
+
+static char _playOgg(const char *name, char *abort){
+
+ const static ov_callbacks cbks ={ oggRead2, oggSeek2, oggClose2, oggTell2 };
+ const uint32_t bufSz = 2048;
+ const uint32_t numBufs = 3;
+ uint16_t** bufs;
+ uint32_t bufIdx = 0;
+ int vorbis_state = 0;
+ OggVorbis_File F;
+ long i, t;
+ char ret = SIMPLE_OGG_MEM_ERR;
+
+ FRESULT r;
+ FIL f;
+
+ ret = SIMPLE_OGG_OK;
+
+ r = f_open(&f, name, FA_READ);
+ if(r) return SIMPLE_OGG_OPEN_ERR;
+
+ i = ov_open_callbacks(&f, &F, NULL, 0, cbks);
+ if(i != 0) return SIMPLE_OFF_OGG_OPEN_ERR;
+
+ bufs = malloc(sizeof(uint16_t*[numBufs]));
+ if(!bufs) goto errout;
+
+ for(i = 0; i < numBufs; i++) bufs[i] = NULL;
+ for(i = 0; i < numBufs; i++) if(!(bufs[i] = malloc(sizeof(uint16_t[bufSz])))) break;
+ if(i != numBufs) goto errout;
+
+ vorbis_info *info = ov_info(&F, 0);
+ //dbgPrintf("vorbis info: version %d channels %d rate %d\n", info->version, info->channels, info->rate);
+
+ audioOn(AUDIO_ALARM, ov_info(&F, 0)->rate);
+ while(!(*abort)){
+ uint8_t volume = getVolume();
+
+ i = ov_read(&F, bufs[bufIdx], bufSz * 2, &vorbis_state);
+ if(i == 0){
+ break;
+ } else if(i == OV_HOLE || i == OV_EBADLINK){
+ ret = SIMPLE_OGG_FILE_ERR;
+ break;
+ } else {
+ i >>= 1;
+ if (info->channels == 1) {
+ for (t = 0; t < i; t++){
+ bufs[bufIdx][t] =
+ ((signed long)(((((int16_t) bufs[bufIdx][t]) >> 4) * (signed long)((unsigned long)volume) + 1)) >> 8) + 2048;
+ }
+ } else {
+ // 2 channels, pick the left channel
+ i >>= 1;
+ for (t = 0; t < i; t++){
+ bufs[bufIdx][t] =
+ ((signed long)(((((int16_t) bufs[bufIdx][t*2]) >> 4) * (signed long)((unsigned long)volume) + 1)) >> 8) + 2048;
+ }
+ }
+ }
+ audioAddBuffer(AUDIO_ALARM, bufs[bufIdx], i);
+ if(++bufIdx == numBufs) bufIdx = 0;
+ }
+ bufs[bufIdx][0] = 2048;
+ audioAddBuffer(AUDIO_ALARM, bufs[bufIdx], 1);
+ ov_clear(&F);
+ f_close(&f);
+ audioOff(AUDIO_ALARM);
+
+errout:
+ for(i = 0; i < numBufs; i++) if(bufs[i]) free(bufs[i]);
+ free(bufs);
+ return ret;
+}
+
+char playOgg(const char *name){
+ char abort = 0;
+ return _playOgg(name, &abort);
+}
+
+struct oggWorkerArgs {
+ const char *name;
+ char *complete;
+ char *abort;
+};
+
+static void oggBackgroundWorker(void *_arg)
+{
+ struct oggWorkerArgs *args = _arg;
+
+ char ret = _playOgg(args->name, args->abort);
+
+ *args->complete = 1;
+
+ free(args);
+}
+
+char playOggBackground(const char *name, char *complete, char *abort){
+
+ struct oggWorkerArgs *args = malloc(sizeof(struct oggWorkerArgs));
+ if (!args)
+ return -1;
+
+ args->name = name;
+ args->complete = complete;
+ args->abort = abort;
+ coopSpawn(&oggBackgroundWorker, args, 12*1024);
+
+ return 0;
+
+}
+
diff --git a/library/ADK2/simpleOgg.h b/library/ADK2/simpleOgg.h
new file mode 100644
index 0000000..ebd5975
--- /dev/null
+++ b/library/ADK2/simpleOgg.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef _SIMPLE_OGG_H_
+#define _SIMPLE_OGG_H_
+
+
+#define SIMPLE_OGG_OK 0
+#define SIMPLE_OGG_OPEN_ERR 1
+#define SIMPLE_OFF_OGG_OPEN_ERR 2
+#define SIMPLE_OGG_FILE_ERR 3
+#define SIMPLE_OGG_MEM_ERR 4
+
+char playOgg(const char* name);
+char playOggBackground(const char* name, char *complete, char *abort);
+
+#endif
+#endif
+
diff --git a/library/ADK2/usbh.c b/library/ADK2/usbh.c
new file mode 100644
index 0000000..9123ba0
--- /dev/null
+++ b/library/ADK2/usbh.c
@@ -0,0 +1,1197 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#define ADK_INTERNAL
+#include "Arduino.h"
+#include "usbh.h"
+#include "coop.h"
+#include "conf_usb.h"
+#include "usb_drv.h"
+#include "usb_ids.h"
+
+#define USE_HIGH_SPEED 0
+#define AUDIO_ACCESSORY 1
+
+#define PIPE_FLAG_INCOMPLETE_SETUP 0x1
+
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+
+typedef struct usbh_pipe {
+ volatile enum pipe_state {
+ PIPE_NO_CONFIG,
+ PIPE_IDLE,
+ PIPE_SETUP_DTOH,
+ PIPE_SETUP_DTOH_IN,
+ PIPE_SETUP_DTOH_OUT,
+ PIPE_SETUP_HTOD,
+ PIPE_SETUP_HTOD_OUT,
+ PIPE_SETUP_HTOD_IN,
+ PIPE_SETUP_COMPLETE,
+ PIPE_IN,
+ PIPE_IN_COMPLETE,
+ PIPE_OUT,
+ PIPE_OUT_COMPLETE,
+ PIPE_ISO_IN,
+ PIPE_ISO_IN_WAIT,
+ } state;
+ uint32_t flags;
+ uint8_t endp;
+ enum usbh_endp_type type;
+
+ /* current transfer stats */
+ void *ptr;
+ size_t pos;
+ size_t total_len;
+ int result;
+
+ /* isochronous transfers */
+ usbh_iso_callback_t iso_cb;
+ void *iso_cb_arg;
+} usbh_pipe_t;
+
+typedef struct usbh_state {
+ enum {
+ USBH_DISABLED,
+ USBH_INIT,
+ USBH_DEVICE_UNATTACHED,
+ USBH_WAIT_FOR_DEVICE,
+ USBH_DEVICE_ATTACHED,
+ USBH_DEVICE_ATTACHED_SOF_WAIT,
+ USBH_DEVICE_ATTACHED_RESET,
+ USBH_DEVICE_ATTACHED_RESET_WAIT,
+ USBH_DEVICE_ATTACHED_POST_RESET_WAIT,
+ USBH_DEVICE_ATTACHED_QUERY,
+ USBH_DEVICE_TRY_ACCESSORY,
+ USBH_DEVICE_ACCESSORY_INIT,
+ USBH_DEVICE_ACCESSORY,
+ USBH_DEVICE_IDLE,
+ } state;
+ uint8_t next_address;
+ uint32_t last_sof;
+ uint32_t irq_count;
+
+ usbh_device_t dev;
+
+ usbh_pipe_t pipe[CHIP_USB_NUMENDPOINTS];
+
+ uint64_t sleep_ts;
+
+
+ // accessory strings
+ const char *accessory_string_vendor;
+ const char *accessory_string_name;
+ const char *accessory_string_longname;
+ const char *accessory_string_version;
+ const char *accessory_string_url;
+ const char *accessory_string_serial;
+} usbh_state_t;
+
+/* master state for the stack */
+static usbh_state_t usbh;
+
+static const char *pipe_state_to_str(enum pipe_state state)
+{
+#define STATE2STR(x) case x: return #x;
+
+ switch (state) {
+ STATE2STR(PIPE_NO_CONFIG)
+ STATE2STR(PIPE_IDLE)
+ STATE2STR(PIPE_SETUP_DTOH)
+ STATE2STR(PIPE_SETUP_DTOH_IN)
+ STATE2STR(PIPE_SETUP_DTOH_OUT)
+ STATE2STR(PIPE_SETUP_HTOD)
+ STATE2STR(PIPE_SETUP_HTOD_OUT)
+ STATE2STR(PIPE_SETUP_HTOD_IN)
+ STATE2STR(PIPE_SETUP_COMPLETE)
+ STATE2STR(PIPE_IN)
+ STATE2STR(PIPE_IN_COMPLETE)
+ STATE2STR(PIPE_OUT)
+ STATE2STR(PIPE_OUT_COMPLETE)
+ default: return "unknown";
+ }
+
+#undef STATE2STR
+}
+
+static void dump_pipe(int pipe)
+{
+ const usbh_pipe_t *p = &usbh.pipe[pipe];
+
+ TRACE_OTG("pipe %d: state %d (%s) flags 0x%x ptr 0x%x pos %u total_len %u\n",
+ pipe, p->state, pipe_state_to_str(p->state), p->flags, p->ptr, p->pos, p->total_len);
+}
+
+static void usbh_start_sleep(void)
+{
+ usbh.sleep_ts = millis();
+}
+
+static bool usbh_sleep_expired(uint32_t ms)
+{
+ uint64_t now = millis();
+
+ if (now - usbh.sleep_ts >= ms)
+ return true;
+ else
+ return false;
+}
+
+int usbh_setup_endpoint(uint8_t addr, uint8_t endp, enum usbh_endp_type type, size_t packet_size)
+{
+ // find a free pipe
+ int pipe;
+ for (pipe = 0; pipe < CHIP_USB_NUMENDPOINTS; pipe++) {
+ if (usbh.pipe[pipe].state == PIPE_NO_CONFIG)
+ break;
+ }
+ if (pipe >= CHIP_USB_NUMENDPOINTS)
+ return -1;
+
+ usbh_pipe_t *p = &usbh.pipe[pipe];
+
+ p->state = PIPE_IDLE;
+ p->endp = endp;
+ p->type = type;
+
+ // set up hardware
+ uint32_t token = (endp & USB_ENDPOINT_IN) ? TOKEN_IN : TOKEN_OUT;
+ switch (type) {
+ default:
+ case ENDP_TYPE_CONTROL:
+ Host_configure_pipe(pipe, 0, endp, TYPE_CONTROL, TOKEN_SETUP, packet_size, SINGLE_BANK);
+ break;
+ case ENDP_TYPE_BULK:
+ Host_configure_pipe(pipe, 0, endp, TYPE_BULK, token, packet_size, SINGLE_BANK);
+ break;
+ case ENDP_TYPE_INT:
+ Host_configure_pipe(pipe, 0, endp, TYPE_INTERRUPT, token, packet_size, SINGLE_BANK);
+ break;
+ case ENDP_TYPE_ISO:
+ Host_configure_pipe(pipe, 0, endp, TYPE_ISOCHRONOUS, token, packet_size, SINGLE_BANK);
+ break;
+ }
+ Host_configure_address(pipe, addr);
+ Host_enable_pipe_interrupt(pipe);
+
+ return pipe;
+}
+
+int usbh_free_endpoint(int pipe)
+{
+ usbh_pipe_t *p = &usbh.pipe[pipe];
+
+ Host_disable_pipe_interrupt(pipe);
+ Host_reset_pipe(pipe);
+ Host_unallocate_memory(pipe);
+ Host_disable_pipe(pipe);
+
+ memset(p, 0, sizeof(usbh_pipe_t));
+
+ return 0;
+}
+
+static void usbh_start_iso_transfer(int pipe)
+{
+ usbh_pipe_t *p = &usbh.pipe[pipe];
+
+ ASSERT(p->type == ENDP_TYPE_ISO);
+
+ if (p->endp & USB_ENDPOINT_IN) {
+ p->state = PIPE_ISO_IN;
+ Disable_global_interrupt();
+ Host_reset_pipe(pipe);
+ UOTGHS->UOTGHS_HSTPIPERR[pipe] = 0;
+ Host_ack_in_received(pipe); Host_enable_in_received_interrupt(pipe);
+ Host_ack_pipe_error(pipe); Host_enable_pipe_error_interrupt(pipe);
+ Enable_global_interrupt();
+ Host_disable_continuous_in_mode(pipe);
+ Host_configure_pipe_token(pipe, TOKEN_IN);
+ Host_ack_in_received(pipe);
+ Host_unfreeze_pipe(pipe);
+ } else {
+ panic("unsupported iso out\n");
+ }
+}
+
+int usbh_queue_iso_transfer(int pipe, void *buf, size_t buflen, usbh_iso_callback_t cb, void *arg)
+{
+ usbh_pipe_t *p = &usbh.pipe[pipe];
+
+// TRACE_OTG("pipe %d buf %p buflen %d cb %p arg %p\n", pipe, buf, buflen, cb, arg);
+
+ ASSERT(p->type == ENDP_TYPE_ISO);
+ ASSERT(p->state == PIPE_IDLE);
+
+ p->ptr = buf;
+ p->total_len = buflen;
+ p->pos = 0;
+
+ /* iso specific bits */
+ p->iso_cb = cb;
+ p->iso_cb_arg = arg;
+
+ ASSERT(p->endp & USB_ENDPOINT_IN);
+
+ usbh_start_iso_transfer(pipe);
+
+ return 0;
+}
+
+int usbh_set_iso_buffer(int pipe, void *buf, size_t buflen)
+{
+ usbh_pipe_t *p = &usbh.pipe[pipe];
+
+ ASSERT(p->type == ENDP_TYPE_ISO);
+
+ p->ptr = buf;
+ p->total_len = buflen;
+ p->pos = 0;
+
+ return 0;
+}
+
+int usbh_queue_transfer(int pipe, void *buf, size_t len)
+{
+ usbh_pipe_t *p = &usbh.pipe[pipe];
+
+ //TRACE_OTG("pipe %d, endp 0x%x, buf %p, len 0x%x\n", pipe, p->endp, buf, len);
+
+ ASSERT(p->state == PIPE_IDLE);
+
+ p->ptr = buf;
+ p->total_len = len;
+ p->pos = 0;
+
+ if (p->type == ENDP_TYPE_BULK || p->type == ENDP_TYPE_ISO) {
+ if (p->endp & USB_ENDPOINT_IN) {
+ p->state = PIPE_IN;
+ Disable_global_interrupt();
+ Host_reset_pipe(pipe);
+ UOTGHS->UOTGHS_HSTPIPERR[pipe] = 0;
+ Host_ack_in_received(pipe); Host_enable_in_received_interrupt(pipe);
+ Host_ack_nak_received(pipe); Host_enable_nak_received_interrupt(pipe);
+ //Host_ack_short_packet(pipe); Host_enable_short_packet_interrupt(pipe);
+ Host_ack_pipe_error(pipe); Host_enable_pipe_error_interrupt(pipe);
+ Enable_global_interrupt();
+ Host_disable_continuous_in_mode(pipe);
+ Host_configure_pipe_token(pipe, TOKEN_IN);
+ Host_ack_in_received(pipe);
+ Host_unfreeze_pipe(pipe);
+ } else {
+ p->state = PIPE_OUT;
+ Disable_global_interrupt();
+ Host_reset_pipe(pipe);
+ Host_configure_pipe_token(pipe, TOKEN_OUT);
+ Host_ack_out_ready(pipe); Host_enable_out_ready_interrupt(pipe);
+ Host_ack_pipe_error(pipe); Host_enable_pipe_error_interrupt(pipe);
+ //Host_enable_ping(pipe); // XXX ONLY for usb 2.0
+
+ Host_unfreeze_pipe(pipe);
+ Enable_global_interrupt();
+
+ Host_reset_pipe_fifo_access(pipe);
+
+ size_t towrite = MIN(p->total_len, Host_get_pipe_size(pipe));
+ uint32_t written = host_write_p_txpacket(pipe, p->ptr, towrite, NULL);
+ p->pos += written;
+
+ Host_ack_out_ready(pipe);
+ Host_send_out(pipe);
+ }
+ } else {
+ panic("unimplemented\n");
+ }
+#if 0
+ dbgPrintf("INRQ 0x%x\n", UOTGHS->UOTGHS_HSTPIPINRQ[pipe]);
+ dbgPrintf("PIPCFG 0x%x\n", UOTGHS->UOTGHS_HSTPIPCFG[pipe]);
+ dbgPrintf("PIPIMR 0x%x\n", UOTGHS->UOTGHS_HSTPIPIMR[pipe]);
+ dbgPrintf("PIPERR 0x%x\n", UOTGHS->UOTGHS_HSTPIPERR[pipe]);
+ dbgPrintf("PIP 0x%x\n", UOTGHS->UOTGHS_HSTPIP);
+#endif
+
+ return 0;
+}
+
+int usbh_check_transfer(int pipe)
+{
+ usbh_pipe_t *p = &usbh.pipe[pipe];
+
+ // poll the pipe to wait for it to get to complete
+ int result;
+ switch (p->state) {
+ case PIPE_IN_COMPLETE:
+ case PIPE_OUT_COMPLETE:
+ p->state = PIPE_IDLE;
+ if (p->result < 0) {
+ result = p->result;
+ } else {
+ result = p->pos;
+ }
+ p->result = PIPE_RESULT_OK;
+ break;
+ case PIPE_IN:
+ case PIPE_OUT:
+ result = PIPE_RESULT_NOT_READY;
+ break;
+ default:
+ case PIPE_NO_CONFIG:
+ case PIPE_IDLE:
+ result = PIPE_RESULT_NOT_QUEUED;
+ break;
+ }
+
+ return result;
+}
+
+uint32_t usbh_get_frame_num(void)
+{
+ return (UOTGHS->UOTGHS_HSTFNUM >> 3) & 0x7ff;
+}
+
+static void usbh_host_reset_pipe(int pipe)
+{
+ usbh_pipe_t *p = &usbh.pipe[pipe];
+
+ switch (p->state) {
+ case PIPE_SETUP_DTOH:
+ case PIPE_SETUP_DTOH_IN:
+ case PIPE_SETUP_DTOH_OUT:
+ case PIPE_SETUP_HTOD:
+ case PIPE_SETUP_HTOD_OUT:
+ case PIPE_SETUP_HTOD_IN:
+ case PIPE_SETUP_COMPLETE:
+ p->state = PIPE_SETUP_COMPLETE;
+ p->result = PIPE_RESULT_RESET;
+ break;
+ default:
+ p->state = PIPE_IDLE;
+ ;
+ }
+}
+
+static void usbh_reset_all_pipes(void)
+{
+ int i;
+ for (i = 0; i < CHIP_USB_NUMENDPOINTS; i++) {
+ usbh_host_reset_pipe(i);
+ }
+}
+
+static void usbh_clear_all_pipes(void)
+{
+ int i;
+ for (i = 0; i < CHIP_USB_NUMENDPOINTS; i++) {
+ usbh_free_endpoint(i);
+ }
+}
+
+static void usbh_host_pipe_irq(int pipe)
+{
+ usbh_pipe_t *p = &usbh.pipe[pipe];
+
+ uint32_t pipe_isr = UOTGHS->UOTGHS_HSTPIPISR[pipe];
+// TRACE_OTG("pipe isr 0x%x\n", pipe_isr);
+ pipe_isr &= UOTGHS->UOTGHS_HSTPIPIMR[pipe];
+// TRACE_OTG("pipe %d isr 0x%x (post mask)\n", pipe, pipe_isr);
+// dump_pipe(pipe);
+
+ if (pipe_isr & UOTGHS_HSTPIPISR_TXSTPI) { // transmitted setup
+ Host_ack_setup_ready();
+ Host_disable_setup_ready_interrupt();
+ if (p->state == PIPE_SETUP_DTOH) {
+ if (p->total_len > 0) {
+ // deal with the IN token
+ Host_disable_continuous_in_mode(pipe);
+ Host_configure_pipe_token(pipe, TOKEN_IN);
+ Host_ack_in_received_free(pipe); Host_enable_in_received_interrupt(pipe);
+ Host_ack_stall(pipe); Host_enable_stall_interrupt(pipe);
+ Host_unfreeze_pipe(pipe);
+
+ p->state = PIPE_SETUP_DTOH_IN;
+ } else {
+ panic("unhandled situation\n");
+ p->state = PIPE_SETUP_DTOH_OUT;
+ }
+ } else if (p->state == PIPE_SETUP_HTOD) {
+ if (p->total_len > 0) {
+ // out token phase
+ Host_configure_pipe_token(pipe, TOKEN_OUT);
+ Host_ack_out_ready(pipe); Host_enable_out_ready_interrupt(pipe);
+ Host_ack_stall(pipe); Host_enable_stall_interrupt(pipe);
+
+ Host_unfreeze_pipe(pipe);
+
+ Host_reset_pipe_fifo_access(pipe);
+ uint32_t written = host_write_p_txpacket(pipe, p->ptr, p->total_len, NULL);
+ //TRACE_OTG("%d bytes written to packet\n", written);
+ p->pos += written;
+
+ Host_send_out(pipe);
+
+// panic("unhandled situation: out phase with bytes\n");
+ p->state = PIPE_SETUP_HTOD_OUT;
+ } else {
+ // deal with the IN token
+ Host_disable_continuous_in_mode(pipe);
+ Host_configure_pipe_token(pipe, TOKEN_IN);
+ Host_ack_in_received_free(pipe); Host_enable_in_received_interrupt(pipe);
+ Host_ack_stall(pipe); Host_enable_stall_interrupt(pipe);
+ Host_unfreeze_pipe(pipe);
+
+ p->state = PIPE_SETUP_HTOD_IN;
+ }
+ } else {
+ panic("bad state %d (%s) with TXSTPI\n", p->state, pipe_state_to_str(p->state));
+ }
+ }
+ if (pipe_isr & UOTGHS_HSTPIPISR_RXINI) { // in packet
+ if (p->state == PIPE_SETUP_DTOH_IN) {
+ //TRACE_OTG("got in, ");
+
+ Host_reset_pipe_fifo_access(pipe);
+
+ uint32_t read = host_read_p_rxpacket(pipe, (uint8_t *)p->ptr + p->pos, p->total_len - p->pos, NULL);
+ p->pos += read;
+
+ //TRACE_OTG_NONL("read %d\n", read);
+
+ Host_freeze_pipe(pipe);
+
+ if ((p->flags & PIPE_FLAG_INCOMPLETE_SETUP) || read < Host_get_pipe_size(pipe) || p->pos == p->total_len) {
+ // deal with OUT token
+ //TRACE_OTG("done, moving to OUT phase\n");
+ Host_ack_in_received(pipe);
+ Host_disable_in_received_interrupt(pipe);
+ Host_configure_pipe_token(pipe, TOKEN_OUT);
+ Host_ack_out_ready_send(pipe); Host_enable_out_ready_interrupt(pipe);
+ Host_ack_stall(pipe); Host_enable_stall_interrupt(pipe);
+ Host_unfreeze_pipe(pipe);
+ p->state = PIPE_SETUP_DTOH_OUT;
+ } else {
+ Host_ack_in_received_free(pipe);
+ Host_unfreeze_pipe(pipe);
+ }
+ } else if (p->state == PIPE_SETUP_HTOD_IN) {
+ Host_free_in(pipe);
+ Host_disable_in_received_interrupt(pipe);
+ p->state = PIPE_SETUP_COMPLETE;
+ //TRACE_OTG("end of in, done\n");
+ } else if (p->state == PIPE_IN) {
+ // regular pipe in in mode
+ Host_ack_in_received(pipe);
+
+ //TRACE_OTG("got in, ");
+
+ Host_reset_pipe_fifo_access(pipe);
+ uint32_t read = host_read_p_rxpacket(pipe, (uint8_t *)p->ptr + p->pos, p->total_len - p->pos, NULL);
+ p->pos += read;
+
+ //TRACE_OTG_NONL("read %d\n", read);
+
+ Host_freeze_pipe(pipe);
+
+ if (read < Host_get_pipe_size(pipe) || p->pos == p->total_len) {
+ Host_reset_pipe(pipe);
+ p->state = PIPE_IN_COMPLETE;
+ p->result = PIPE_RESULT_OK;
+ } else {
+ // multi in transfer
+ //Host_configure_pipe_token(pipe, TOKEN_IN);
+ Host_ack_in_received_free(pipe);
+ Host_unfreeze_pipe(pipe);
+ }
+ } else if (p->state == PIPE_ISO_IN) {
+ // isochronous pipe in in mode
+ Host_ack_in_received(pipe);
+
+ //TRACE_OTG("ISO got in, ");
+
+ Host_reset_pipe_fifo_access(pipe);
+ uint32_t read = host_read_p_rxpacket(pipe, (uint8_t *)p->ptr + p->pos, p->total_len - p->pos, NULL);
+ p->pos += read;
+
+ //TRACE_OTG_NONL("read %d\n", read);
+
+ Host_freeze_pipe(pipe);
+
+ p->state = PIPE_ISO_IN_WAIT;
+ p->result = PIPE_RESULT_OK;
+
+ Host_ack_in_received(pipe);
+
+ // schedule for a new sof interrupt
+ Host_enable_sof_interrupt();
+ usbh.last_sof = (UOTGHS->UOTGHS_HSTFNUM >> 3) & 0x7ff;
+
+ // do callback
+ p->iso_cb(p->iso_cb_arg, p->result, p->ptr, p->pos);
+ } else {
+ panic("bad state %d (%s) with RXINIT\n", p->state, pipe_state_to_str(p->state));
+ }
+ }
+ if (pipe_isr & UOTGHS_HSTPIPISR_TXOUTI) { // out packet complete
+ if (p->state == PIPE_SETUP_DTOH_OUT) {
+ Host_disable_out_ready_interrupt(pipe);
+ Host_ack_out_ready(pipe);
+ p->state = PIPE_SETUP_COMPLETE;
+ p->result = PIPE_RESULT_OK;
+ //TRACE_OTG("end of out, done\n");
+ } else if (p->state == PIPE_SETUP_HTOD_OUT) {
+ if (p->pos == p->total_len) {
+ // deal with the IN token
+ Host_disable_out_ready_interrupt(pipe);
+ Host_ack_out_ready(pipe);
+ Host_disable_continuous_in_mode(pipe);
+ Host_configure_pipe_token(pipe, TOKEN_IN);
+ Host_ack_in_received_free(pipe); Host_enable_in_received_interrupt(pipe);
+ Host_ack_stall(pipe); Host_enable_stall_interrupt(pipe);
+ Host_unfreeze_pipe(pipe);
+ p->state = PIPE_SETUP_HTOD_IN;
+ } else {
+ panic("unhandled situation, multi out control transfer\n");
+ Host_ack_out_ready(pipe);
+ Host_unfreeze_pipe(pipe);
+ }
+ } else if (p->state == PIPE_OUT) {
+ // regular pipe in out mode
+ Host_ack_out_ready(pipe);
+ if (p->pos == p->total_len) {
+ //TRACE_OTG("OUT complete\n");
+ Host_reset_pipe(pipe);
+ p->state = PIPE_OUT_COMPLETE;
+ p->result = PIPE_RESULT_OK;
+ } else {
+ //Host_reset_pipe(pipe);
+ Host_configure_pipe_token(pipe, TOKEN_OUT);
+ Host_ack_out_ready(pipe); Host_enable_out_ready_interrupt(pipe);
+ Host_ack_pipe_error(pipe); Host_enable_pipe_error_interrupt(pipe);
+
+ Host_unfreeze_pipe(pipe);
+
+ Host_reset_pipe_fifo_access(pipe);
+ size_t towrite = MIN(p->total_len - p->pos, Host_get_pipe_size(pipe));
+ //TRACE_OTG("second part of out: towrite %d pos %d\n", towrite, p->pos);
+ uint32_t written = host_write_p_txpacket(pipe, p->ptr + p->pos, towrite, NULL);
+ p->pos += written;
+
+ Host_ack_out_ready(pipe);
+ Host_send_out(pipe);
+ }
+ } else {
+ panic("bad state %d (%s) with TXOUTI\n", p->state, pipe_state_to_str(p->state));
+ }
+ }
+ if (pipe_isr & UOTGHS_HSTPIPISR_NAKEDI) { // nak received
+ //TRACE_OTG("pipe %d got nak\n", pipe);
+ Host_ack_nak_received(pipe);
+ Host_disable_nak_received_interrupt(pipe);
+ if (p->state == PIPE_IN) {
+ Host_reset_pipe(pipe);
+ p->state = PIPE_IN_COMPLETE;
+ p->result = PIPE_RESULT_NAK;
+ } if (p->state == PIPE_IN_COMPLETE) {
+ ; // do nothing
+ } else {
+ panic("bad state %d (%s) with NAKEDI\n", p->state, pipe_state_to_str(p->state));
+ }
+ }
+ if (pipe_isr & UOTGHS_HSTPIPISR_RXSTALLDI) { // stall received
+ Host_disable_stall_interrupt(pipe);
+ Host_ack_stall(pipe);
+ if (p->state == PIPE_SETUP_DTOH_IN) {
+ Host_disable_in_received_interrupt(pipe);
+ p->state = PIPE_SETUP_COMPLETE;
+ p->result = PIPE_RESULT_STALL;
+ } else if (p->state == PIPE_SETUP_HTOD_IN) {
+ Host_disable_in_received_interrupt(pipe);
+ p->state = PIPE_SETUP_COMPLETE;
+ p->result = PIPE_RESULT_STALL;
+ } else {
+ panic("bad state %d (%s) with RXSTALLDI\n", p->state, pipe_state_to_str(p->state));
+ }
+ }
+ if (pipe_isr & UOTGHS_HSTPIPISR_PERRI) { // pipe error
+ uint32_t perr = UOTGHS->UOTGHS_HSTPIPERR[pipe];
+ TRACE_OTG("pipe %d got perr 0x%x\n", pipe, perr);
+
+ Host_ack_pipe_error(pipe);
+
+ if (p->state == PIPE_IN && perr & UOTGHS_HSTPIPERR_PID) {
+ UOTGHS->UOTGHS_HSTPIPERR[pipe] = ~0x64;
+
+ panic("got PID error\n");
+
+ // XXX why do we get pid error?
+ Host_unfreeze_pipe(pipe);
+ }
+ }
+}
+
+static void usbh_host_irq(uint32_t isr)
+{
+ int i;
+
+ if (isr & UOTGHS_HSTISR_DCONNI) { // device connected
+ dbgPrintf("USB: connect\n");
+ }
+ if (isr & UOTGHS_HSTISR_DDISCI) { // device disconnected
+ dbgPrintf("USB: disconnect\n");
+ usbh.state = USBH_DEVICE_UNATTACHED;
+ host_disable_all_pipes();
+ usbh_reset_all_pipes();
+ goto done;
+ }
+ if (isr & UOTGHS_HSTISR_HSOFI) { // start of frame
+ Host_ack_sof();
+
+ //uint32_t f = (UOTGHS->UOTGHS_HSTFNUM >> 3) & 0x7ff;
+ //if (usbh.last_sof != f) {
+ for (i = 0; i < CHIP_USB_NUMENDPOINTS; i++) {
+ if (usbh.pipe[i].state == PIPE_ISO_IN_WAIT) {
+ //dbgPrintf("SOF: iso in wait pipe %d\n", i);
+ //dbgPrintf("last 0x%x f 0x%x\n", last_sof, f);
+ Host_disable_sof_interrupt();
+
+ usbh_start_iso_transfer(i);
+ }
+ }
+ //}
+ }
+
+ for (i = 0; i < CHIP_USB_NUMENDPOINTS; i++) {
+ if (isr & (1 << (8 + i)))
+ usbh_host_pipe_irq(i);
+ }
+
+done:
+ UOTGHS->UOTGHS_HSTICR = isr;
+}
+
+void UOTGHS_Handler(void)
+{
+ usbh.irq_count++;
+
+#if 0
+ if ((usbh.irq_count % 1024) == 0)
+ TRACE_OTG("%d usb irqs\n", usbh.irq_count);
+#endif
+
+ uint32_t gen_sr = UOTGHS->UOTGHS_SR;
+ uint32_t host_isr = UOTGHS->UOTGHS_HSTISR;
+ host_isr &= UOTGHS->UOTGHS_HSTIMR;
+
+ if (host_isr) {
+ usbh_host_irq(host_isr);
+ }
+}
+
+int usbh_send_setup(const void *_setup, void *buf, int incomplete)
+{
+ const struct usb_setup_packet *setup = _setup;
+
+// TRACE_OTG("setup %p, buf %p, incomplete %d\n", setup, buf, incomplete);
+ ASSERT(usbh.pipe[P_CONTROL].state == PIPE_IDLE);
+
+ Disable_global_interrupt();
+ Host_configure_pipe_token(P_CONTROL, TOKEN_SETUP);
+ Host_ack_setup_ready();
+ Host_unfreeze_pipe(P_CONTROL);
+ Host_enable_setup_ready_interrupt();
+
+ Host_reset_pipe_fifo_access(P_CONTROL);
+ host_write_p_txpacket(P_CONTROL, setup, sizeof(*setup), NULL);
+ Host_send_setup();
+
+ /* set up pipe state */
+ usbh_pipe_t *p = &usbh.pipe[P_CONTROL];
+ p->state = (setup->bmRequestType & USB_SETUP_DIR_DEVICE_TO_HOST) ? PIPE_SETUP_DTOH : PIPE_SETUP_HTOD;
+ p->flags = incomplete ? PIPE_FLAG_INCOMPLETE_SETUP : 0;
+ p->ptr = buf;
+ p->pos = 0;
+ p->total_len = setup->wLength;
+
+ Enable_global_interrupt();
+
+ // XXX timeout
+ uint64_t t = micros();
+ int result = 0;
+ for (;;) {
+ coopYield();
+
+ ASSERT(p->state != PIPE_NO_CONFIG);
+ ASSERT(p->state != PIPE_IDLE);
+
+ // poll the pipe to wait for it to get to complete
+ if (p->state == PIPE_SETUP_COMPLETE) {
+ p->state = PIPE_IDLE;
+ if (p->result < 0) {
+ result = p->result;
+ } else {
+ result = p->pos;
+ }
+ p->result = PIPE_RESULT_OK;
+ break;
+ }
+ }
+ //TRACE_OTG("transfer complete, took %lld usecs\n", micros());
+
+// TRACE_OTG("transfer complete, result %d\n", result);
+ return result;
+}
+
+
+void usbh_work(void)
+{
+ switch (usbh.state) {
+ case USBH_DISABLED:
+ break;
+ case USBH_INIT:
+ Usb_unfreeze_clock();
+
+ Usb_force_host_mode();
+ //Wr_bitfield(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SPDCONF_Msk, 1, UOTGHS_HSTCTRL_SPDCONF_Pos); // force full/low speed
+ Usb_disable_id_pin();
+
+ Disable_global_interrupt();
+ Usb_disable();
+ (void)Is_usb_enabled();
+ Enable_global_interrupt();
+ Usb_enable_otg_pad();
+ Usb_set_vbof_active_high();
+ Usb_enable_vbus_hw_control();
+ Usb_enable();
+ Host_enable_device_disconnection_interrupt();
+#if !USE_HIGH_SPEED
+ Wr_bitfield(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SPDCONF_Msk, 3, UOTGHS_HSTCTRL_SPDCONF_Pos); // force full speed mode
+#endif
+ usbh.state = USBH_DEVICE_UNATTACHED;
+
+ // clear all ints
+ UOTGHS->UOTGHS_SCR = 0xf;
+ UOTGHS->UOTGHS_HSTICR = 0xf;
+ break;
+
+ case USBH_DEVICE_UNATTACHED:
+ TRACE_OTG("DEVICE_UNATTACHED\n");
+ // clear all ints
+ UOTGHS->UOTGHS_SCR = 0xf;
+ UOTGHS->UOTGHS_HSTICR = 0xf;
+ Host_disable_sof();
+ Host_ack_sof();
+ Usb_enable_vbus();
+
+ // clear all the pipes
+ host_disable_all_pipes();
+ usbh_clear_all_pipes();
+
+ // wipe any accessory state
+ accessory_deinit();
+
+ usbh.state = USBH_WAIT_FOR_DEVICE;
+ TRACE_OTG("USBH_WAIT_FOR_DEVICE\n");
+ break;
+ case USBH_WAIT_FOR_DEVICE:
+ Usb_enable_vbus();
+ if (Is_usb_vbus_high()) {
+ if (Is_host_device_connection()) {
+ TRACE_OTG("vbus high and saw device connection, moving to USBH_DEVICE_ATTACHED\n");
+ Usb_ack_bconnection_error_interrupt();
+ Usb_ack_vbus_error_interrupt();
+ Host_ack_device_connection();
+ Host_ack_hwup();
+ usbh.state = USBH_DEVICE_ATTACHED;
+ }
+ }
+ break;
+ case USBH_DEVICE_ATTACHED:
+ TRACE_OTG("USBH_DEVICE_ATTACHED\n");
+ TRACE_OTG("starting SOF\n");
+ Host_enable_sof();
+
+ // wait 100ms
+ usbh.state = USBH_DEVICE_ATTACHED_SOF_WAIT;
+ usbh_start_sleep();
+ break;
+ case USBH_DEVICE_ATTACHED_SOF_WAIT:
+ if (usbh_sleep_expired(100))
+ usbh.state = USBH_DEVICE_ATTACHED_RESET;
+ break;
+ case USBH_DEVICE_ATTACHED_RESET:
+ // reset the bus
+ TRACE_OTG("USBH_DEVICE_RESET\n");
+ TRACE_OTG("resetting bus\n");
+ Host_send_reset();
+ usbh.state = USBH_DEVICE_ATTACHED_RESET_WAIT;
+ break;
+ case USBH_DEVICE_ATTACHED_RESET_WAIT:
+ if (Is_host_reset_sent()) {
+ Host_ack_reset_sent();
+
+ TRACE_OTG("done with reset\n");
+
+ // wait 100ms
+ usbh.state = USBH_DEVICE_ATTACHED_POST_RESET_WAIT;
+ usbh_start_sleep();
+ }
+ break;
+ case USBH_DEVICE_ATTACHED_POST_RESET_WAIT:
+ if (usbh_sleep_expired(100))
+ usbh.state = USBH_DEVICE_ATTACHED_QUERY;
+ break;
+ case USBH_DEVICE_ATTACHED_QUERY: {
+ TRACE_OTG("USBH_DEVICE_ATTACHED_QUERY\n");
+ TRACE_OTG("configuring ep0 pipe\n");
+ int pip = usbh_setup_endpoint(0, 0, ENDP_TYPE_CONTROL, 8);
+ ASSERT(pip == P_CONTROL);
+
+ // build get device descriptor setup packet, send short version first (to find maxpacketsize)
+ struct usb_setup_packet setup = {
+ USB_SETUP_DIR_DEVICE_TO_HOST,
+ SETUP_GET_DESCRIPTOR,
+ DESCRIPTOR_DEVICE << 8,
+ 0,
+ 8
+ };
+
+ uint8_t buf[64];
+ int len = usbh_send_setup(&setup, buf, true);
+ TRACE_OTG("usbh_send_setup returns %d\n", len);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+ // configure the pipe for the maxpacket size the device requests
+ uint32_t maxpacketsize = buf[OFFSET_FIELD_MAXPACKETSIZE];
+ TRACE_OTG("got initial descriptor: len %d, maxpacketsize %d\n", buf[OFFSET_DESCRIPTOR_LENGTH], buf[OFFSET_FIELD_MAXPACKETSIZE]);
+
+ Host_configure_pipe(P_CONTROL, 0, EP_CONTROL, TYPE_CONTROL, TOKEN_SETUP, maxpacketsize, SINGLE_BANK);
+
+ // assign the device an address
+ usbh.dev.address = usbh.next_address++;
+ setup = (struct usb_setup_packet){
+ USB_SETUP_DIR_HOST_TO_DEVICE,
+ SETUP_SET_ADDRESS,
+ usbh.dev.address,
+ 0,
+ 0
+ };
+
+ len = usbh_send_setup(&setup, buf, false);
+ TRACE_OTG("usbh_send_setup returns %d\n", len);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+ Host_configure_address(P_CONTROL, usbh.dev.address);
+
+ TRACE_OTG("USBH_DEVICE_ADDRESSED, address %d\n", usbh.dev.address);
+
+ // read the final copy of the device descriptor
+ setup = (struct usb_setup_packet){
+ USB_SETUP_DIR_DEVICE_TO_HOST,
+ SETUP_GET_DESCRIPTOR,
+ DESCRIPTOR_DEVICE << 8,
+ 0,
+ 0x40
+ };
+
+ usbh.dev.devdesc;
+ len = usbh_send_setup(&setup, usbh.dev.devdesc, false);
+ TRACE_OTG("usbh_send_setup returns %d\n", len);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+ // pick out the vid/pid
+ usbh.dev.vid = *(uint16_t *)(usbh.dev.devdesc + OFFSET_FIELD_VID);
+ usbh.dev.pid = *(uint16_t *)(usbh.dev.devdesc + OFFSET_FIELD_PID);
+
+ dbgPrintf("USB: found device vid/pid 0x%x/0x%x\n", usbh.dev.vid, usbh.dev.pid);
+
+ // read a copy of the config descriptor
+ setup = (struct usb_setup_packet){
+ USB_SETUP_DIR_DEVICE_TO_HOST,
+ SETUP_GET_DESCRIPTOR,
+ DESCRIPTOR_CONFIGURATION << 8,
+ 0,
+ 9
+ };
+ len = usbh_send_setup(&setup, buf, false);
+ TRACE_OTG("usbh_send_setup returns %d\n", len);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+ uint16_t total_config_length = *(uint16_t *)(buf + OFFSET_FIELD_TOTAL_LENGTH);
+
+ TRACE_OTG("config descriptor length %d\n", total_config_length);
+
+ ASSERT(total_config_length < usbh.dev.devconfig);
+
+ // get the final copy of the config descriptor
+ setup = (struct usb_setup_packet){
+ USB_SETUP_DIR_DEVICE_TO_HOST,
+ SETUP_GET_DESCRIPTOR,
+ DESCRIPTOR_CONFIGURATION << 8,
+ 0,
+ total_config_length
+ };
+
+ len = usbh_send_setup(&setup, usbh.dev.devconfig, false);
+ TRACE_OTG("usbh_send_setup returns %d\n", len);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+ // see if we're connected to an accessory
+ switch ((usbh.dev.vid << 16) | usbh.dev.pid) {
+ case 0x18d12d00: // accessory
+ case 0x18d12d01: // accessory + adb
+ case 0x18d12d02: // audio
+ case 0x18d12d03: // audio + adb
+ case 0x18d12d04: // accessory + audio
+ case 0x18d12d05: // accessory + audio + adb
+ dbgPrintf("USB: found accessory 0x%x:0x%x\n", usbh.dev.vid, usbh.dev.pid);
+ usbh.state = USBH_DEVICE_ACCESSORY_INIT;
+ break;
+ default:
+ dbgPrintf("USB: didn't find accessory, trying to change its mode\n");
+ usbh.state = USBH_DEVICE_TRY_ACCESSORY;
+ break;
+ }
+
+ break;
+ }
+ case USBH_DEVICE_TRY_ACCESSORY: {
+ // read protocol version
+ struct usb_setup_packet setup = (struct usb_setup_packet){
+ USB_SETUP_DIR_DEVICE_TO_HOST | USB_SETUP_TYPE_VENDOR,
+ 0x33,
+ 0,
+ 0,
+ 2
+ };
+
+ uint16_t version;
+ int len = usbh_send_setup(&setup, &version, false);
+ TRACE_OTG("version len %d\n", len);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+ if (len <= 0) {
+ dbgPrintf("USB: no version returned, not accessory\n");
+ usbh.state = USBH_DEVICE_IDLE;
+ break;
+ }
+ TRACE_OTG("accessory returned version %d\n", version);
+ if (version < 1 || version > 2) {
+ dbgPrintf("USB: bad protocol version %d, not accessory\n", version);
+ usbh.state = USBH_DEVICE_IDLE;
+ break;
+ }
+
+ // send google strings
+ setup = (struct usb_setup_packet){
+ USB_SETUP_DIR_HOST_TO_DEVICE | USB_SETUP_TYPE_VENDOR,
+ 0x34,
+ 0,
+ 0,
+ 0
+ };
+
+ setup.wIndex = 0;
+ setup.wLength = strlen(usbh.accessory_string_vendor) + 1;
+ len = usbh_send_setup(&setup, (void *)usbh.accessory_string_vendor, false);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+ setup.wIndex = 1;
+ setup.wLength = strlen(usbh.accessory_string_name) + 1;
+ len = usbh_send_setup(&setup, (void *)usbh.accessory_string_name, false);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+ setup.wIndex = 2;
+ setup.wLength = strlen(usbh.accessory_string_longname) + 1;
+ len = usbh_send_setup(&setup, (void *)usbh.accessory_string_longname, false);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+ setup.wIndex = 3;
+ setup.wLength = strlen(usbh.accessory_string_version) + 1;
+ len = usbh_send_setup(&setup, (void *)usbh.accessory_string_version, false);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+ setup.wIndex = 4;
+ setup.wLength = strlen(usbh.accessory_string_url) + 1;
+ len = usbh_send_setup(&setup, (void *)usbh.accessory_string_url, false);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+ setup.wIndex = 5;
+ setup.wLength = strlen(usbh.accessory_string_serial) + 1;
+ len = usbh_send_setup(&setup, (void *)usbh.accessory_string_serial, false);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+#if AUDIO_ACCESSORY
+ // we want audio
+ setup = (struct usb_setup_packet){
+ USB_SETUP_DIR_HOST_TO_DEVICE | USB_SETUP_TYPE_VENDOR,
+ 0x3a,
+ 1,
+ 0,
+ 0
+ };
+ len = usbh_send_setup(&setup, NULL, false);
+ if (len == PIPE_RESULT_RESET)
+ break;
+#endif
+
+ // send accessory start
+ setup = (struct usb_setup_packet){
+ USB_SETUP_DIR_HOST_TO_DEVICE | USB_SETUP_TYPE_VENDOR,
+ 0x35,
+ 0,
+ 0,
+ 0
+ };
+ len = usbh_send_setup(&setup, NULL, false);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+ // go to idle mode, wait for the device to reset out from underneath us
+ usbh.state = USBH_DEVICE_IDLE;
+ break;
+ }
+ case USBH_DEVICE_ACCESSORY_INIT: {
+ // set configuration 1
+ struct usb_setup_packet setup = (struct usb_setup_packet){
+ USB_SETUP_DIR_HOST_TO_DEVICE,
+ SETUP_SET_CONFIGURATION,
+ 1,
+ 0,
+ 0
+ };
+
+ int len = usbh_send_setup(&setup, NULL, false);
+ if (len == PIPE_RESULT_RESET)
+ break;
+
+ int ret = accessory_init(&usbh.dev);
+ if (ret < 0) {
+ usbh.state = USBH_DEVICE_IDLE;
+ break;
+ }
+
+ usbh.state = USBH_DEVICE_ACCESSORY;
+ break;
+ }
+ case USBH_DEVICE_ACCESSORY:
+ case USBH_DEVICE_IDLE:
+ //TRACE_OTG("USBH_DEVICE_WAIT\n");
+ break;
+ }
+}
+
+/* for the coop threading system */
+static void usbhTask(void* ptr)
+{
+ for (;;) {
+ coopYield();
+ usbh_work();
+ // let the accessory state machine run
+ accessory_work();
+ }
+}
+
+void usbh_init(void)
+{
+ usbh.next_address = 1;
+ usbh.state = USBH_DISABLED;
+
+ /* default accessory strings */
+ usbh.accessory_string_vendor = DEFAULT_ACCESSORY_STRING_VENDOR;
+ usbh.accessory_string_name = DEFAULT_ACCESSORY_STRING_NAME;
+ usbh.accessory_string_longname = DEFAULT_ACCESSORY_STRING_LONGNAME;
+ usbh.accessory_string_version = DEFAULT_ACCESSORY_STRING_VERSION;
+ usbh.accessory_string_url = DEFAULT_ACCESSORY_STRING_URL;
+ usbh.accessory_string_serial = DEFAULT_ACCESSORY_STRING_SERIAL;
+
+ /* Enable peripheral clock for UOTGHS */
+ pmc_enable_periph_clk(ID_UOTGHS);
+
+#if 1
+ /* Enable UPLL 480 MHz */
+ PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(7);
+ /* Wait that UPLL is considered locked by the PMC */
+ while( !(PMC->PMC_SR & PMC_SR_LOCKU) )
+ ;
+
+ /* USB clock register: USB Clock Input is UTMI PLL */
+ PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(0);
+
+ PMC->PMC_SCER = PMC_SCER_UOTGCLK;
+#else
+ PMC->CKGR_UCKR = 0;
+ PMC->PMC_USB = PMC_USB_USBDIV(0);
+ PMC->PMC_SCER = PMC_SCER_UOTGCK;
+#endif
+
+ NVIC_SetPriority(UOTGHS_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
+ NVIC_EnableIRQ(UOTGHS_IRQn);
+
+ coopSpawn(&usbhTask, NULL, 2048);
+
+ Usb_freeze_clock();
+}
+
+void usbh_set_accessory_string_vendor(const char *str)
+{
+ usbh.accessory_string_vendor = str;
+}
+
+void usbh_set_accessory_string_name(const char *str)
+{
+ usbh.accessory_string_name = str;
+}
+
+void usbh_set_accessory_string_longname(const char *str)
+{
+ usbh.accessory_string_longname = str;
+}
+
+void usbh_set_accessory_string_version(const char *str)
+{
+ usbh.accessory_string_version = str;
+}
+
+void usbh_set_accessory_string_url(const char *str)
+{
+ usbh.accessory_string_url = str;
+}
+
+void usbh_set_accessory_string_serial(const char *str)
+{
+ usbh.accessory_string_serial = str;
+}
+
+void usbh_start(void)
+{
+ if (usbh.state == USBH_DISABLED)
+ usbh.state = USBH_INIT;
+}
+
+int usbh_accessory_connected(void)
+{
+ return usbh.state == USBH_DEVICE_ACCESSORY;
+}
+
diff --git a/library/ADK2/usbh.h b/library/ADK2/usbh.h
new file mode 100644
index 0000000..237c548
--- /dev/null
+++ b/library/ADK2/usbh.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef ADK_INTERNAL
+#ifndef __USB_USBH_H
+#define __USB_USBH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct usbh_device {
+ uint8_t address;
+ uint8_t devdesc[64];
+ uint8_t devconfig[512]; // XXX max
+
+ uint16_t vid;
+ uint16_t pid;
+} usbh_device_t;
+
+#define PIPE_RESULT_OK (0)
+#define PIPE_RESULT_NOT_READY (-1)
+#define PIPE_RESULT_NOT_QUEUED (-2)
+#define PIPE_RESULT_ERR (-3)
+#define PIPE_RESULT_RESET (-4)
+#define PIPE_RESULT_NAK (-5)
+#define PIPE_RESULT_STALL (-6)
+
+#define DEFAULT_ACCESSORY_STRING_VENDOR "Google, Inc."
+#define DEFAULT_ACCESSORY_STRING_NAME "DemoKit"
+#define DEFAULT_ACCESSORY_STRING_LONGNAME "DemoKit Arduino Board"
+#define DEFAULT_ACCESSORY_STRING_VERSION "2.0"
+#define DEFAULT_ACCESSORY_STRING_URL "http://www.android.com"
+#define DEFAULT_ACCESSORY_STRING_SERIAL "0000000012345678"
+
+void usbh_init(void);
+void usbh_start(void);
+void usbh_work(void);
+
+void usbh_set_accessory_string_vendor(const char *str);
+void usbh_set_accessory_string_name(const char *str);
+void usbh_set_accessory_string_longname(const char *str);
+void usbh_set_accessory_string_version(const char *str);
+void usbh_set_accessory_string_url(const char *str);
+void usbh_set_accessory_string_serial(const char *str);
+
+enum usbh_endp_type {
+ ENDP_TYPE_CONTROL,
+ ENDP_TYPE_BULK,
+ ENDP_TYPE_INT,
+ ENDP_TYPE_ISO
+};
+
+int usbh_accessory_connected(void);
+
+int usbh_setup_endpoint(uint8_t addr, uint8_t endp, enum usbh_endp_type type, size_t packet_size);
+int usbh_free_endpoint(int pipe);
+
+int usbh_queue_transfer(int pipe, void *buf, size_t len);
+int usbh_check_transfer(int pipe);
+int usbh_send_setup(const void *setup, void *buf, int incomplete);
+
+/* isochronous transfers */
+typedef void (*usbh_iso_callback_t)(void *arg, int result, void *buf, size_t pos);
+int usbh_queue_iso_transfer(int pipe, void *buf, size_t buflen, usbh_iso_callback_t cb, void *arg);
+int usbh_set_iso_buffer(int pipe, void *buf, size_t buflen);
+
+uint32_t usbh_get_frame_num(void);
+
+int accessory_init(usbh_device_t *dev);
+void accessory_deinit(void);
+
+int accessory_send(const void *buf, size_t len);
+int accessory_receive(void *buf, size_t len);
+
+void accessory_work(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+#endif
diff --git a/library/ADK2/utility/compiler.h b/library/ADK2/utility/compiler.h
new file mode 100644
index 0000000..a4fb157
--- /dev/null
+++ b/library/ADK2/utility/compiler.h
@@ -0,0 +1,1242 @@
+/* This header file is part of the AVR Software Framework 2.0.0 release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Compiler file for AVR32.
+ *
+ * This file defines commonly used types and macros.
+ *
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices: All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _COMPILER_H_
+#define _COMPILER_H_
+
+
+/*_____ D E C L A R A T I O N S ____________________________________________*/
+
+
+#include <stddef.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <Arduino.h>
+
+
+
+#define LITTLE_ENDIAN_MCU 1==1
+/*#undef __ICCAVR32__*/
+
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+extern uint32_t q_get_PRIMASK(void);
+extern void q_set_PRIMASK(uint32_t priMask);
+
+/* Enable interrupts */
+#define Enable_global_interrupt() __set_PRIMASK(0)
+#define sei() __set_PRIMASK(0)
+/* Disable interrupts */
+#define Disable_global_interrupt() __set_PRIMASK(1)
+#define cli() __set_PRIMASK(1)
+/* Disable IRQ interrupt and save status */
+#define sai() __get_PRIMASK()
+/* Restore interrupt status */
+#define rei(X) __set_PRIMASK(X)
+
+#define Is_global_interrupt_enabled() ((__get_PRIMASK()) ? 1 : 0)
+
+///*
+// * @brief Return the Priority Mask value
+// *
+// * @param none
+// * @return uint32_t PriMask
+// *
+// * Return the state of the priority mask bit from the priority mask
+// * register
+// */
+//#if defined(__GNUC__)
+//uint32_t q_get_PRIMASK(void)
+//{
+// uint32_t result=0;
+//
+// asm volatile ("MRS %0, primask" : "=r" (result) );
+// return(result);
+//}
+//#elif defined(__ICCARM__)
+//uint32_t q_get_PRIMASK(void)
+//{
+// __asm("mrs r0, primask");
+// __asm("bx lr");
+//}
+//#elif defined(__CC_ARM)
+///*__asm*/ uint32_t __get_PRIMASK(void)
+//{
+// uint32_t primask=0;
+//
+//// mrs r0, primask
+// return(primask);
+//}
+//#endif
+//
+///*
+// * @brief Set the Priority Mask value
+// *
+// * @param uint32_t PriMask
+// * @return none
+// *
+// * Set the priority mask bit in the priority mask register
+// */
+//#if defined(__GNUC__)
+//void q_set_PRIMASK(uint32_t priMask)
+//{
+// asm volatile ("MSR primask, %0" : : "r" (priMask) );
+//}
+//#elif defined(__ICCARM__)
+//void q_set_PRIMASK(uint32_t priMask)
+//{
+// __asm("msr primask, r0");
+// __asm("bx lr");
+//}
+//#elif defined(__CC_ARM)
+//__asm void __set_PRIMASK(uint32_t priMask)
+//{
+//// msr primask, r0
+//// bx lr
+//}
+//#endif
+
+
+
+#if (defined __ICCAVR32__)
+
+/*! \name Compiler Keywords
+ *
+ * Port of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32.
+ */
+//! @{
+#define __asm__ asm
+#define __inline__ inline
+#define __volatile__
+//! @}
+
+#endif
+
+/**
+ * \def barrier
+ * \brief Memory barrier
+ */
+#if defined(__GNUC__)
+# define barrier() asm volatile("" ::: "memory")
+#elif defined(__ICCAVR32__)
+# define barrier() asm ("")
+#endif
+
+/**
+ * \brief Emit the compiler pragma \a arg.
+ *
+ * \param arg The pragma directive as it would appear after \e \#pragma
+ * (i.e. not stringified).
+ */
+#define COMPILER_PRAGMA(arg) _Pragma(#arg)
+
+/**
+ * \def COMPILER_PACK_SET(alignment)
+ * \brief Set maximum alignment for subsequent struct and union
+ * definitions to \a alignment.
+ */
+#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))
+
+/**
+ * \def COMPILER_PACK_RESET()
+ * \brief Set default alignment for subsequent struct and union
+ * definitions.
+ */
+#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
+
+
+/**
+ * \brief Set word-aligned boundary.
+ */
+#if (defined __GNUC__)
+#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))
+#elif (defined __ICCAVR32__)
+#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)
+#endif
+
+/**
+ * \name System Register Access
+ * @{
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+/**
+ * \brief Get value of system register
+ *
+ * \param reg Address of the system register of which to get the value.
+ *
+ * \return Value of system register \a reg.
+ */
+# define sysreg_read(reg) __builtin_mfsr(reg)
+
+/**
+ * \brief Set value of system register
+ *
+ * \param reg Address of the system register of which to set the value.
+ * \param val Value to set the system register \a reg to.
+ */
+# define sysreg_write(reg, val) __builtin_mtsr(reg, val)
+
+#elif defined(__ICCAVR32__)
+# define sysreg_read(reg) __get_system_register(reg)
+# define sysreg_write(reg, val) __set_system_register(reg, val)
+#endif
+
+/* Deprecated definitions */
+#define Get_system_register(reg) sysreg_read(reg)
+#define Set_system_register(reg, val) sysreg_write((reg), (val))
+
+
+/* \name Status Types
+ */
+typedef Bool Status_bool_t; //!< Boolean status.
+typedef U8 Status_t; //!< 8-bit-coded status.
+
+
+/* \name Aliasing Aggregate Types
+ */
+
+/* 16-bit union. */
+typedef union
+{
+ S16 s16 ;
+ U16 u16 ;
+ S8 s8 [2];
+ U8 u8 [2];
+} Union16;
+
+/* 32-bit union.*/
+typedef union
+{
+ S32 s32 ;
+ U32 u32 ;
+ S16 s16[2];
+ U16 u16[2];
+ S8 s8 [4];
+ U8 u8 [4];
+} Union32;
+
+/* 64-bit union. */
+typedef union
+{
+ S64 s64 ;
+ U64 u64 ;
+ S32 s32[2];
+ U32 u32[2];
+ S16 s16[4];
+ U16 u16[4];
+ S8 s8 [8];
+ U8 u8 [8];
+} Union64;
+
+/* Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union
+{
+ S64 *s64ptr;
+ U64 *u64ptr;
+ S32 *s32ptr;
+ U32 *u32ptr;
+ S16 *s16ptr;
+ U16 *u16ptr;
+ S8 *s8ptr ;
+ U8 *u8ptr ;
+} UnionPtr;
+
+//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union
+{
+ volatile S64 *s64ptr;
+ volatile U64 *u64ptr;
+ volatile S32 *s32ptr;
+ volatile U32 *u32ptr;
+ volatile S16 *s16ptr;
+ volatile U16 *u16ptr;
+ volatile S8 *s8ptr ;
+ volatile U8 *u8ptr ;
+} UnionVPtr;
+
+//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union
+{
+ const S64 *s64ptr;
+ const U64 *u64ptr;
+ const S32 *s32ptr;
+ const U32 *u32ptr;
+ const S16 *s16ptr;
+ const U16 *u16ptr;
+ const S8 *s8ptr ;
+ const U8 *u8ptr ;
+} UnionCPtr;
+
+//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union
+{
+ const volatile S64 *s64ptr;
+ const volatile U64 *u64ptr;
+ const volatile S32 *s32ptr;
+ const volatile U32 *u32ptr;
+ const volatile S16 *s16ptr;
+ const volatile U16 *u16ptr;
+ const volatile S8 *s8ptr ;
+ const volatile U8 *u8ptr ;
+} UnionCVPtr;
+
+//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct
+{
+ S64 *s64ptr;
+ U64 *u64ptr;
+ S32 *s32ptr;
+ U32 *u32ptr;
+ S16 *s16ptr;
+ U16 *u16ptr;
+ S8 *s8ptr ;
+ U8 *u8ptr ;
+} StructPtr;
+
+//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct
+{
+ volatile S64 *s64ptr;
+ volatile U64 *u64ptr;
+ volatile S32 *s32ptr;
+ volatile U32 *u32ptr;
+ volatile S16 *s16ptr;
+ volatile U16 *u16ptr;
+ volatile S8 *s8ptr ;
+ volatile U8 *u8ptr ;
+} StructVPtr;
+
+//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct
+{
+ const S64 *s64ptr;
+ const U64 *u64ptr;
+ const S32 *s32ptr;
+ const U32 *u32ptr;
+ const S16 *s16ptr;
+ const U16 *u16ptr;
+ const S8 *s8ptr ;
+ const U8 *u8ptr ;
+} StructCPtr;
+
+//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct
+{
+ const volatile S64 *s64ptr;
+ const volatile U64 *u64ptr;
+ const volatile S32 *s32ptr;
+ const volatile U32 *u32ptr;
+ const volatile S16 *s16ptr;
+ const volatile U16 *u16ptr;
+ const volatile S8 *s8ptr ;
+ const volatile U8 *u8ptr ;
+} StructCVPtr;
+
+//! @}
+
+//#endif // __AVR32_ABI_COMPILER__
+
+
+//_____ M A C R O S ________________________________________________________
+
+/*! \name Usual Constants
+ */
+//! @{
+#define DISABLE 0
+#define ENABLE 1
+#define DISABLED 0
+#define ENABLED 1
+#define OFF 0
+#define ON 1
+#define FALSE 0
+#define TRUE 1
+#ifndef __cplusplus
+#if !defined(__bool_true_false_are_defined)
+#define false FALSE
+#define true TRUE
+#endif
+#endif
+#define KO 0
+#define OK 1
+#define PASS 0
+#define FAIL 1
+#define LOW 0
+#define HIGH 1
+#define CLR 0
+#define SET 1
+//! @}
+
+
+//#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+//! \name Optimization Control
+//@{
+
+/**
+ * \def likely(exp)
+ * \brief The expression \a exp is likely to be true
+ */
+#ifndef likely
+# define likely(exp) (exp)
+#endif
+
+/**
+ * \def unlikely(exp)
+ * \brief The expression \a exp is unlikely to be true
+ */
+#ifndef unlikely
+# define unlikely(exp) (exp)
+#endif
+
+/**
+ * \def is_constant(exp)
+ * \brief Determine if an expression evaluates to a constant value.
+ *
+ * \param exp Any expression
+ *
+ * \return true if \a exp is constant, false otherwise.
+ */
+#ifdef __GNUC__
+# define is_constant(exp) __builtin_constant_p(exp)
+#else
+# define is_constant(exp) (0)
+#endif
+
+//! @}
+
+/*! \name Bit-Field Handling
+ */
+//! @{
+
+/*! \brief Reads the bits of a value specified by a given bit-mask.
+ *
+ * \param value Value to read bits from.
+ * \param mask Bit-mask indicating bits to read.
+ *
+ * \return Read bits.
+ */
+#define Rd_bits( value, mask) ((value) & (mask))
+
+/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue C lvalue to write bits to.
+ * \param mask Bit-mask indicating bits to write.
+ * \param bits Bits to write.
+ *
+ * \return Resulting value with written bits.
+ */
+#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\
+ ((bits ) & (mask)))
+
+/*! \brief Tests the bits of a value specified by a given bit-mask.
+ *
+ * \param value Value of which to test bits.
+ * \param mask Bit-mask indicating bits to test.
+ *
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.
+ */
+#define Tst_bits( value, mask) (Rd_bits((value), (mask)) != 0)
+
+/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue C lvalue of which to clear bits.
+ * \param mask Bit-mask indicating bits to clear.
+ *
+ * \return Resulting value with cleared bits.
+ */
+#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))
+
+/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue C lvalue of which to set bits.
+ * \param mask Bit-mask indicating bits to set.
+ *
+ * \return Resulting value with set bits.
+ */
+#define Set_bits(lvalue, mask) ((lvalue) |= (mask))
+
+/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue C lvalue of which to toggle bits.
+ * \param mask Bit-mask indicating bits to toggle.
+ *
+ * \return Resulting value with toggled bits.
+ */
+#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))
+
+/*! \brief Reads the bit-field of a value specified by a given bit-mask.
+ *
+ * \param value Value to read a bit-field from.
+ * \param mask Bit-mask indicating the bit-field to read.
+ *
+ * \return Read bit-field.
+ */
+#define Rd_bitfield( value, mask, offset) (Rd_bits( (value), (mask)) >> (offset))
+
+/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue C lvalue to write a bit-field to.
+ * \param mask Bit-mask indicating the bit-field to write.
+ * \param bitfield Bit-field to write.
+ *
+ * \return Resulting value with written bit-field.
+ */
+#define Wr_bitfield(lvalue, mask, bitfield, offset) (Wr_bits((lvalue), (mask), (U32)(bitfield) << (offset)))
+//#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))
+
+//! @}
+
+
+/*! \brief This macro is used to test fatal errors.
+ *
+ * The macro tests if the expression is FALSE. If it is, a fatal error is
+ * detected and the application hangs up.
+ *
+ * \param expr Expression to evaluate and supposed to be nonzero.
+ */
+#ifdef _ASSERT_ENABLE_
+ #define Assert(expr) \
+ {\
+ if (!(expr)) while (TRUE);\
+ }
+#else
+ #define Assert(expr)
+#endif
+
+
+///*! \name Zero-Bit Counting
+// *
+// * Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when
+// * applied to constant expressions (values known at compile time), so they are
+// * more optimized than the use of the corresponding assembly instructions and
+// * they can be used as constant expressions e.g. to initialize objects having
+// * static storage duration, and like the corresponding assembly instructions
+// * when applied to non-constant expressions (values unknown at compile time), so
+// * they are more optimized than an assembly periphrasis. Hence, clz and ctz
+// * ensure a possible and optimized behavior for both constant and non-constant
+// * expressions.
+// */
+////! @{
+///*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
+// *
+// * \param u Value of which to count the leading zero bits.
+// *
+// * \return The count of leading zero bits in \a u.
+// */
+//#if (defined __GNUC__)
+// #define clz(u) __builtin_clz(u)
+//#elif (defined __ICCAVR32__)
+// #if (__VER__ == 330) && (__SUBVERSION__ <= 1)
+// // __count_leading_zeros is broken and returns a value which is offset by
+// // -32 when called with a constant parameter.
+// #define clz(v) (0 == v ? 32 : (31 & __count_leading_zeros(v)))
+// #else
+// #define clz(v) __count_leading_zeros(v)
+// #endif
+//#elif (defined __ICCARM__)
+// #define clz(v) __count_leading_zeros(v)
+//#endif
+//
+///*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
+// *
+// * \param u Value of which to count the trailing zero bits.
+// *
+// * \return The count of trailing zero bits in \a u.
+// */
+//#if (defined __GNUC__)
+// #define ctz(u) __builtin_ctz(u)
+//#elif (defined __ICCAVR32__)
+// #define ctz(u) __count_trailing_zeros(u)
+//#endif
+//
+////! @}
+//
+////! \name Logarithmic functions
+////! @{
+//
+///**
+// * \internal
+// * Undefined function. Will cause a link failure if ilog2() is called
+// * with an invalid constant value.
+// */
+//int_fast8_t ilog2_undefined(void);
+//
+///**
+// * \brief Calculate the base-2 logarithm of a number rounded down to
+// * the nearest integer.
+// *
+// * \param x A 32-bit value
+// * \return The base-2 logarithm of \a x, or -1 if \a x is 0.
+// */
+//static inline int_fast8_t ilog2(uint32_t x)
+//{
+// if (is_constant(x))
+// return ((x) & (1ULL << 31) ? 31 :
+// (x) & (1ULL << 30) ? 30 :
+// (x) & (1ULL << 29) ? 29 :
+// (x) & (1ULL << 28) ? 28 :
+// (x) & (1ULL << 27) ? 27 :
+// (x) & (1ULL << 26) ? 26 :
+// (x) & (1ULL << 25) ? 25 :
+// (x) & (1ULL << 24) ? 24 :
+// (x) & (1ULL << 23) ? 23 :
+// (x) & (1ULL << 22) ? 22 :
+// (x) & (1ULL << 21) ? 21 :
+// (x) & (1ULL << 20) ? 20 :
+// (x) & (1ULL << 19) ? 19 :
+// (x) & (1ULL << 18) ? 18 :
+// (x) & (1ULL << 17) ? 17 :
+// (x) & (1ULL << 16) ? 16 :
+// (x) & (1ULL << 15) ? 15 :
+// (x) & (1ULL << 14) ? 14 :
+// (x) & (1ULL << 13) ? 13 :
+// (x) & (1ULL << 12) ? 12 :
+// (x) & (1ULL << 11) ? 11 :
+// (x) & (1ULL << 10) ? 10 :
+// (x) & (1ULL << 9) ? 9 :
+// (x) & (1ULL << 8) ? 8 :
+// (x) & (1ULL << 7) ? 7 :
+// (x) & (1ULL << 6) ? 6 :
+// (x) & (1ULL << 5) ? 5 :
+// (x) & (1ULL << 4) ? 4 :
+// (x) & (1ULL << 3) ? 3 :
+// (x) & (1ULL << 2) ? 2 :
+// (x) & (1ULL << 1) ? 1 :
+// (x) & (1ULL << 0) ? 0 :
+// ilog2_undefined());
+//
+// return 31 - clz(x);
+//}
+
+//! @}
+
+/*! \name Bit Reversing
+ */
+//! @{
+
+/*! \brief Reverses the bits of \a u8.
+ *
+ * \param u8 U8 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u8 with reversed bits.
+ */
+#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24))
+
+/*! \brief Reverses the bits of \a u16.
+ *
+ * \param u16 U16 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u16 with reversed bits.
+ */
+#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16))
+
+/*! \brief Reverses the bits of \a u32.
+ *
+ * \param u32 U32 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u32 with reversed bits.
+ */
+#if (defined __GNUC__)
+ #define bit_reverse32(u32) \
+ (\
+ {\
+ unsigned int __value = (U32)(u32);\
+ __asm__ ("brev\t%0" : "+r" (__value) : : "cc");\
+ (U32)__value;\
+ }\
+ )
+#elif (defined __ICCAVR32__)
+ #define bit_reverse32(u32) ((U32)__bit_reverse((U32)(u32)))
+#endif
+
+/*! \brief Reverses the bits of \a u64.
+ *
+ * \param u64 U64 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u64 with reversed bits.
+ */
+#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\
+ ((U64)bit_reverse32((U64)(u64)) << 32)))
+
+//! @}
+
+
+/*! \name Alignment
+ */
+//! @{
+
+/*! \brief Tests alignment of the number \a val with the \a n boundary.
+ *
+ * \param val Input value.
+ * \param n Boundary.
+ *
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
+ */
+#define Test_align(val, n ) (!Tst_bits( (val), (n) - 1 ) )
+
+/*! \brief Gets alignment of the number \a val with respect to the \a n boundary.
+ *
+ * \param val Input value.
+ * \param n Boundary.
+ *
+ * \return Alignment of the number \a val with respect to the \a n boundary.
+ */
+#define Get_align( val, n ) ( Rd_bits( (val), (n) - 1 ) )
+
+/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
+ *
+ * \param lval Input/output lvalue.
+ * \param n Boundary.
+ * \param alg Alignment.
+ *
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
+ */
+#define Set_align(lval, n, alg) ( Wr_bits((lval), (n) - 1, (alg)) )
+
+/*! \brief Aligns the number \a val with the upper \a n boundary.
+ *
+ * \param val Input value.
+ * \param n Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.
+ */
+#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1))
+
+/*! \brief Aligns the number \a val with the lower \a n boundary.
+ *
+ * \param val Input value.
+ * \param n Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.
+ */
+#define Align_down(val, n ) ( (val) & ~((n) - 1))
+
+//! @}
+
+#if 0
+
+/*! \name Mathematics
+ *
+ * The same considerations as for clz and ctz apply here but AVR32-GCC does not
+ * provide built-in functions to access the assembly instructions abs, min and
+ * max and it does not produce them by itself in most cases, so two sets of
+ * macros are defined here:
+ * - Abs, Min and Max to apply to constant expressions (values known at
+ * compile time);
+ * - abs, min and max to apply to non-constant expressions (values unknown at
+ * compile time).
+ */
+//! @{
+
+/*! \brief Takes the absolute value of \a a.
+ *
+ * \param a Input value.
+ *
+ * \return Absolute value of \a a.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Abs(a) (((a) < 0 ) ? -(a) : (a))
+
+/*! \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Min(a, b) (((a) < (b)) ? (a) : (b))
+
+/*! \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Max(a, b) (((a) > (b)) ? (a) : (b))
+
+/*! \brief Takes the absolute value of \a a.
+ *
+ * \param a Input value.
+ *
+ * \return Absolute value of \a a.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+ #define abs(a) \
+ (\
+ {\
+ int __value = (a);\
+ __asm__ ("abs\t%0" : "+r" (__value) : : "cc");\
+ __value;\
+ }\
+ )
+#elif (defined __ICCAVR32__)
+ #define abs(a) Abs(a)
+#endif
+
+/*! \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+ #define min(a, b) \
+ (\
+ {\
+ int __value, __arg_a = (a), __arg_b = (b);\
+ __asm__ ("min\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\
+ __value;\
+ }\
+ )
+#elif (defined __ICCAVR32__)
+ #define min(a, b) __min(a, b)
+#endif
+
+/*! \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+ #define max(a, b) \
+ (\
+ {\
+ int __value, __arg_a = (a), __arg_b = (b);\
+ __asm__ ("max\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\
+ __value;\
+ }\
+ )
+#elif (defined __ICCAVR32__)
+ #define max(a, b) __max(a, b)
+#endif
+
+//! @}
+
+
+/*! \brief Calls the routine at address \a addr.
+ *
+ * It generates a long call opcode.
+ *
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
+ * it is invoked from the CPU supervisor mode.
+ *
+ * \param addr Address of the routine to call.
+ *
+ * \note It may be used as a long jump opcode in some special cases.
+ */
+#define Long_call(addr) ((*(void (*)(void))(addr))())
+
+/*! \brief Resets the CPU by software.
+ *
+ * \warning It shall not be called from the CPU application mode.
+ */
+#if (defined __GNUC__)
+ #define Reset_CPU() \
+ (\
+ {\
+ __asm__ __volatile__ (\
+ "lddpc r9, 3f\n\t"\
+ "mfsr r8, %[SR]\n\t"\
+ "bfextu r8, r8, %[SR_M_OFFSET], %[SR_M_SIZE]\n\t"\
+ "cp.w r8, 0b001\n\t"\
+ "breq 0f\n\t"\
+ "sub r8, pc, $ - 1f\n\t"\
+ "pushm r8-r9\n\t"\
+ "rete\n"\
+ "0:\n\t"\
+ "mtsr %[SR], r9\n"\
+ "1:\n\t"\
+ "mov r0, 0\n\t"\
+ "mov r1, 0\n\t"\
+ "mov r2, 0\n\t"\
+ "mov r3, 0\n\t"\
+ "mov r4, 0\n\t"\
+ "mov r5, 0\n\t"\
+ "mov r6, 0\n\t"\
+ "mov r7, 0\n\t"\
+ "mov r8, 0\n\t"\
+ "mov r9, 0\n\t"\
+ "mov r10, 0\n\t"\
+ "mov r11, 0\n\t"\
+ "mov r12, 0\n\t"\
+ "mov sp, 0\n\t"\
+ "stdsp sp[0], sp\n\t"\
+ "ldmts sp, sp\n\t"\
+ "mov lr, 0\n\t"\
+ "lddpc pc, 2f\n\t"\
+ ".balign 4\n"\
+ "2:\n\t"\
+ ".word _start\n"\
+ "3:\n\t"\
+ ".word %[RESET_SR]"\
+ :\
+ : [SR] "i" (AVR32_SR),\
+ [SR_M_OFFSET] "i" (AVR32_SR_M_OFFSET),\
+ [SR_M_SIZE] "i" (AVR32_SR_M_SIZE),\
+ [RESET_SR] "i" (AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))\
+ );\
+ }\
+ )
+#elif (defined __ICCAVR32__)
+ #define Reset_CPU() \
+ {\
+ extern void *volatile __program_start;\
+ __asm__ __volatile__ (\
+ "mov r7, LWRD(__program_start)\n\t"\
+ "orh r7, HWRD(__program_start)\n\t"\
+ "mov r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\
+ "orh r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\
+ "mfsr r8, "ASTRINGZ(AVR32_SR)"\n\t"\
+ "bfextu r8, r8, "ASTRINGZ(AVR32_SR_M_OFFSET)", "ASTRINGZ(AVR32_SR_M_SIZE)"\n\t"\
+ "cp.w r8, 001b\n\t"\
+ "breq $ + 10\n\t"\
+ "sub r8, pc, -12\n\t"\
+ "pushm r8-r9\n\t"\
+ "rete\n\t"\
+ "mtsr "ASTRINGZ(AVR32_SR)", r9\n\t"\
+ "mov r0, 0\n\t"\
+ "mov r1, 0\n\t"\
+ "mov r2, 0\n\t"\
+ "mov r3, 0\n\t"\
+ "mov r4, 0\n\t"\
+ "mov r5, 0\n\t"\
+ "mov r6, 0\n\t"\
+ "st.w r0[4], r7\n\t"\
+ "mov r7, 0\n\t"\
+ "mov r8, 0\n\t"\
+ "mov r9, 0\n\t"\
+ "mov r10, 0\n\t"\
+ "mov r11, 0\n\t"\
+ "mov r12, 0\n\t"\
+ "mov sp, 0\n\t"\
+ "stdsp sp[0], sp\n\t"\
+ "ldmts sp, sp\n\t"\
+ "mov lr, 0\n\t"\
+ "ld.w pc, lr[4]"\
+ );\
+ __program_start;\
+ }
+#endif
+
+
+
+
+/*! \name CPU Status Register Access
+ */
+//! @{
+
+/*! \brief Tells whether exceptions are globally enabled.
+ *
+ * \return \c 1 if exceptions are globally enabled, else \c 0.
+ */
+#define Is_global_exception_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_EM_MASK))
+
+/*! \brief Disables exceptions globally.
+ */
+#if (defined __GNUC__)
+ #define Disable_global_exception() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})
+#elif (defined __ICCAVR32__)
+ #define Disable_global_exception() (__set_status_flag(AVR32_SR_EM_OFFSET))
+#endif
+
+/*! \brief Enables exceptions globally.
+ */
+#if (defined __GNUC__)
+ #define Enable_global_exception() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})
+#elif (defined __ICCAVR32__)
+ #define Enable_global_exception() (__clear_status_flag(AVR32_SR_EM_OFFSET))
+#endif
+
+//! @}
+
+
+/*! \name Debug Register Access
+ */
+//! @{
+
+/*! \brief Gets the value of the \a dbgreg debug register.
+ *
+ * \param dbgreg Address of the debug register of which to get the value.
+ *
+ * \return Value of the \a dbgreg debug register.
+ */
+#if (defined __GNUC__)
+ #define Get_debug_register(dbgreg) __builtin_mfdr(dbgreg)
+#elif (defined __ICCAVR32__)
+ #define Get_debug_register(dbgreg) __get_debug_register(dbgreg)
+#endif
+
+/*! \brief Sets the value of the \a dbgreg debug register to \a value.
+ *
+ * \param dbgreg Address of the debug register of which to set the value.
+ * \param value Value to set the \a dbgreg debug register to.
+ */
+#if (defined __GNUC__)
+ #define Set_debug_register(dbgreg, value) __builtin_mtdr(dbgreg, value)
+#elif (defined __ICCAVR32__)
+ #define Set_debug_register(dbgreg, value) __set_debug_register(dbgreg, value)
+#endif
+
+//! @}
+#endif
+
+
+/*! \name Force Assembly Inline Code Section
+ */
+//! @{
+#if (defined __GNUC__)
+#define __always_inline __attribute__((__always_inline__))
+#elif (defined __ICCAVR32__)
+#define __always_inline _Pragma("inline=forced")
+#endif
+//! @}
+
+/*! \name MCU Endianism Handling
+ * AVR32 is MCU big endianism.
+ */
+//! @{
+#define MSB(u16) (((U8 *)&(u16))[0]) //!< Most significant byte of \a u16.
+#define LSB(u16) (((U8 *)&(u16))[1]) //!< Least significant byte of \a u16.
+
+#define MSH(u32) (((U16 *)&(u32))[0]) //!< Most significant half-word of \a u32.
+#define LSH(u32) (((U16 *)&(u32))[1]) //!< Least significant half-word of \a u32.
+#define MSB0W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 1st rank of \a u32.
+#define MSB1W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 2nd rank of \a u32.
+#define MSB2W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 3rd rank of \a u32.
+#define MSB3W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 4th rank of \a u32.
+#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.
+#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.
+#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.
+#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.
+
+#define MSW(u64) (((U32 *)&(u64))[0]) //!< Most significant word of \a u64.
+#define LSW(u64) (((U32 *)&(u64))[1]) //!< Least significant word of \a u64.
+#define MSH0(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 1st rank of \a u64.
+#define MSH1(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 2nd rank of \a u64.
+#define MSH2(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 3rd rank of \a u64.
+#define MSH3(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 4th rank of \a u64.
+#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.
+#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.
+#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.
+#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.
+#define MSB0D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 1st rank of \a u64.
+#define MSB1D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 2nd rank of \a u64.
+#define MSB2D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 3rd rank of \a u64.
+#define MSB3D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 4th rank of \a u64.
+#define MSB4D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 5th rank of \a u64.
+#define MSB5D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 6th rank of \a u64.
+#define MSB6D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 7th rank of \a u64.
+#define MSB7D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 8th rank of \a u64.
+#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.
+#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.
+#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.
+#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.
+#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.
+#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.
+#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.
+#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.
+
+#define LE16(x) Swap16(x)
+#define le16_to_cpu(x) swap16(x)
+#define cpu_to_le16(x) swap16(x)
+#define LE16_TO_CPU(x) Swap16(x)
+#define CPU_TO_LE16(x) Swap16(x)
+
+#define be16_to_cpu(x) (x)
+#define cpu_to_be16(x) (x)
+#define BE16_TO_CPU(x) (x)
+#define CPU_TO_BE16(x) (x)
+
+#define le32_to_cpu(x) swap32(x)
+#define cpu_to_le32(x) swap32(x)
+#define LE32_TO_CPU(x) Swap32(x)
+#define CPU_TO_LE32(x) Swap32(x)
+
+#define be32_to_cpu(x) (x)
+#define cpu_to_be32(x) (x)
+#define BE32_TO_CPU(x) (x)
+#define CPU_TO_BE32(x) (x)
+//! @}
+
+
+/*! \name Endianism Conversion
+ *
+ * The same considerations as for clz and ctz apply here but AVR32-GCC's
+ * __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when
+ * applied to constant expressions, so two sets of macros are defined here:
+ * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
+ * at compile time);
+ * - swap16, swap32 and swap64 to apply to non-constant expressions (values
+ * unknown at compile time).
+ */
+//! @{
+
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\
+ ((U16)(u16) << 8)))
+
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\
+ ((U32)Swap16((U32)(u32)) << 16)))
+
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\
+ ((U64)Swap32((U64)(u64)) << 32)))
+
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+ #define swap16(u16) ((U16)__builtin_bswap_16((U16)(u16)))
+#elif (defined __ICCAVR32__)
+ #define swap16(u16) ((U16)__swap_bytes_in_halfwords((U16)(u16)))
+#endif
+
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+ #define swap32(u32) ((U32)__builtin_bswap_32((U32)(u32)))
+#elif (defined __ICCAVR32__)
+ #define swap32(u32) ((U32)__swap_bytes((U32)(u32)))
+#endif
+
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\
+ ((U64)swap32((U64)(u64)) << 32)))
+
+//! @}
+
+
+/*! \name Target Abstraction
+ */
+//! @{
+
+#define _GLOBEXT_ extern //!< extern storage-class specifier.
+#define _CONST_TYPE_ const //!< const type qualifier.
+#define _MEM_TYPE_SLOW_ //!< Slow memory type.
+#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type.
+#define _MEM_TYPE_FAST_ //!< Fast memory type.
+
+typedef U8 Byte; //!< 8-bit unsigned integer.
+
+#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM.
+#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM.
+#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM.
+#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM.
+
+#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.
+#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.
+#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.
+#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.
+#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.
+#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.
+#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.
+#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.
+
+//! @}
+
+//#endif // __AVR32_ABI_COMPILER__
+
+
+#endif // _COMPILER_H_
diff --git a/library/ADK2/utility/conf_usb.h b/library/ADK2/utility/conf_usb.h
new file mode 100644
index 0000000..105ec41
--- /dev/null
+++ b/library/ADK2/utility/conf_usb.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __CONF_USB_H
+#define __CONF_USB_H
+
+#define DISABLED 0
+#define ENABLED 1
+
+#define TRACE_USB 1
+
+#if TRACE_USB
+#define LOG_STR(...) (dbgPrintf(__VA_ARGS__),dbgPrintf("\n\r"))
+#define TRACE_OTG(fmt, ...) do{ dbgPrintf("%s %ld: " fmt, __func__, millis(), ##__VA_ARGS__); } while (0)
+#define TRACE_OTG_NONL(fmt, ...) do{ dbgPrintf(fmt, ##__VA_ARGS__); } while (0)
+#else
+#define LOG_STR(...) ()
+#define TRACE_OTG(fmt, ...) do{ } while (0)
+#define TRACE_OTG_NONL(fmt, ...) do{ } while (0)
+#endif
+
+#define USB_HOST_FEATURE ENABLED
+#define USB_DEVICE_FEATURE DISABLED
+
+#define USB_HOST_PIPE_INTERRUPT_TRANSFER ENABLE
+
+#define CHIP_USB_NUMENDPOINTS 10
+
+#define halt() do { for(;;); } while (0)
+#define ASSERT(x) do { if (!(x)) { dbgPrintf("%s:%d ASSERT failed: %s\n", __FILE__, __LINE__, #x); halt(); } } while (0)
+#define panic(fmt, ...) do{ dbgPrintf("panic at %s: " fmt, __func__, ##__VA_ARGS__); halt(); } while (0)
+
+#undef printf
+#define printf(x...) ERROR_DONT_USE_PRINTF
+
+#endif
+
diff --git a/library/ADK2/utility/usb_drv.c b/library/ADK2/utility/usb_drv.c
new file mode 100644
index 0000000..2052301
--- /dev/null
+++ b/library/ADK2/utility/usb_drv.c
@@ -0,0 +1,590 @@
+/* This source file is part of the AVR Software Framework 2.0.0 release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file ******************************************************************
+ *
+ * \brief Low-level driver for AVR32 USBB.
+ *
+ * This file contains the USBB low-level driver routines.
+ *
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices: All AVR32 devices with a USBB module can be used.
+ * - AppNote:
+ *
+ * \author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ***************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+//_____ I N C L U D E S ____________________________________________________
+
+#include "usb_drv.h"
+
+
+//_____ M A C R O S ________________________________________________________
+#define min(x,y) ((x)>(y)?(y):(x))
+
+
+//_____ D E C L A R A T I O N S ____________________________________________
+
+#if USB_DEVICE_FEATURE == DISABLED && USB_HOST_FEATURE == DISABLED
+ #error At least one of USB_DEVICE_FEATURE and USB_HOST_FEATURE must be enabled
+#endif
+
+void Uotghs_trace(void)
+{
+ TRACE_OTG("CTRL: 0x%X\n\r",UOTGHS->UOTGHS_CTRL);
+ TRACE_OTG("SR: 0x%X\n\r",UOTGHS->UOTGHS_SR);
+ TRACE_OTG("FSM: 0x%X\n\r",UOTGHS->UOTGHS_FSM);
+ TRACE_OTG("DEVCTRL: 0x%X\n\r",UOTGHS->UOTGHS_DEVCTRL);
+ TRACE_OTG("DEVISR: 0x%X\n\r",UOTGHS->UOTGHS_DEVISR);
+ TRACE_OTG("DEVIMR: 0x%X\n\r",UOTGHS->UOTGHS_DEVIMR);
+ TRACE_OTG("DEVEPTCFG0: 0x%X\n\r",UOTGHS->UOTGHS_DEVEPTCFG[0]);
+ TRACE_OTG("DEVEPTCFG1: 0x%X\n\r",UOTGHS->UOTGHS_DEVEPTCFG[1]);
+ TRACE_OTG("DEVEPTCFG2: 0x%X\n\r",UOTGHS->UOTGHS_DEVEPTCFG[2]);
+ TRACE_OTG("DEVEPTISR: 0x%X\n\r",UOTGHS->UOTGHS_DEVEPTISR[0]);
+ TRACE_OTG("HSTCTRL: 0x%X\n\r",UOTGHS->UOTGHS_HSTCTRL);
+ TRACE_OTG("HSTISR: 0x%X\n\r",UOTGHS->UOTGHS_HSTISR);
+ TRACE_OTG("HSTIMR: 0x%X\n\r",UOTGHS->UOTGHS_HSTIMR);
+ TRACE_OTG("HSTPIP: 0x%X\n\r",UOTGHS->UOTGHS_HSTPIP);
+ TRACE_OTG("HSTFNUM: 0x%X\n\r",UOTGHS->UOTGHS_HSTFNUM);
+ TRACE_OTG("HSTADDR1: 0x%X\n\r",UOTGHS->UOTGHS_HSTADDR1);
+ TRACE_OTG("HSTADDR2: 0x%X\n\r",UOTGHS->UOTGHS_HSTADDR2);
+ TRACE_OTG("HSTADDR3: 0x%X\n\r",UOTGHS->UOTGHS_HSTADDR3);
+ TRACE_OTG("HSTPIPCFG: 0x%X\n\r",UOTGHS->UOTGHS_HSTPIPCFG[0]);
+ TRACE_OTG("HSTPIPCFG1: 0x%X\n\r",UOTGHS->UOTGHS_HSTPIPCFG[1]);
+ TRACE_OTG("HSTPIPCFG2: 0x%X\n\r",UOTGHS->UOTGHS_HSTPIPCFG[2]);
+ TRACE_OTG("HSTPIPINRQ: 0x%X\n\r",UOTGHS->UOTGHS_HSTPIPINRQ[0]);
+ TRACE_OTG("HSTPIPERR0: 0x%X\n\r",UOTGHS->UOTGHS_HSTPIPERR[0]);
+ TRACE_OTG("HSTPIPISR0: 0x%X\n\r",UOTGHS->UOTGHS_HSTPIPISR[0]);
+ TRACE_OTG("HSTPIPIMR0: 0x%X\n\r",UOTGHS->UOTGHS_HSTPIPIMR[0]);
+
+ /* Test ID */
+ if( UOTGHS->UOTGHS_SR & UOTGHS_SR_ID)
+ {
+ TRACE_OTG("ID=1: PERIPHERAL\n\r");
+ }
+ else
+ {
+ TRACE_OTG("ID=0: HOST\n\r");
+ }
+
+ /* Test VBUS */
+ if( 0 != (UOTGHS->UOTGHS_SR & UOTGHS_SR_VBUS) ) {
+ TRACE_OTG("VBUS = 1\n\r");
+ }
+ else {
+ TRACE_OTG("VBUS = 0\n\r");
+ }
+
+ /* Test SPEED */
+ TRACE_OTG("Speed = 0x%X\n\r", UOTGHS->UOTGHS_SR & UOTGHS_SR_SPEED_Msk);
+
+ /* FSM State:
+ * 0 A_IDLESTATE This is the start state for A-devices (when the ID pin is 0)
+ * 1 A_WAIT_VRISE In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus
+ * Valid threshold (4.4 V).
+ * 2 A_WAIT_BCON In this state, the A-device waits for the B-device to signal a connection.
+ * 3 A_HOST In this state, the A-device that operates in Host mode is operational.
+ * 4 A_SUSPEND The A-device operating as a host is in the suspend mode.
+ * 5 A_PERIPHERAL The A-device operates as a peripheral.
+ * 6 A_WAIT_VFALL In this state, the A-device waits for the voltage on VBus to drop below the A-device
+ * Session Valid threshold (1.4 V).
+ * 7 A_VBUS_ERR In this state, the A-device waits for recovery of the over-current condition that caused it
+ * to enter this state.
+ * 8 A_WAIT_DISCHARGE In this state, the A-device waits for the data USB line to discharge (100 us).
+ * 9 B_IDLE This is the start state for B-device (when the ID pin is 1).
+ * 10 B_PERIPHERAL In this state, the B-device acts as the peripheral.
+ * 11 B_WAIT_BEGIN_HNP In this state, the B-device is in suspend mode and waits until 3 ms before initiating the
+ * HNP protocol if requested.
+ * 12 B_WAIT_DISCHARGE In this state, the B-device waits for the data USB line to discharge (100 us) before
+ * becoming Host.
+ * 13 B_WAIT_ACON In this state, the B-device waits for the A-device to signal a connect before becoming B-
+ * Host.
+ * 14 B_HOST In this state, the B-device acts as the Host.
+ * 15 B_SRP_INIT In this state, the B-device attempts to start a session using the SRP protocol. */
+ TRACE_OTG("FSM = 0x%X\n\r", UOTGHS->UOTGHS_FSM);
+}
+
+//! Pointers to the FIFO data registers of pipes/endpoints
+//! Use aggregated pointers to have several alignments available for a same address
+UnionVPtr pep_fifo[MAX_PEP_NB];
+
+//! ---------------------------------------------------------
+//! ------------------ HOST ---------------------------------
+//! ---------------------------------------------------------
+
+#if USB_HOST_FEATURE == ENABLED
+
+void Host_configure_address( uint8_t pipe, uint8_t addr)
+{
+ if( pipe == 0 ) {
+ UOTGHS->UOTGHS_HSTADDR1 &= ~UOTGHS_HSTADDR1_HSTADDRP0_Msk;
+ UOTGHS->UOTGHS_HSTADDR1 |= UOTGHS_HSTADDR1_HSTADDRP0(addr);
+ }
+ else if( pipe == 1 ) {
+ UOTGHS->UOTGHS_HSTADDR1 &= ~UOTGHS_HSTADDR1_HSTADDRP1_Msk;
+ UOTGHS->UOTGHS_HSTADDR1 |= UOTGHS_HSTADDR1_HSTADDRP1(addr);
+ }
+ else if( pipe == 2 ) {
+ UOTGHS->UOTGHS_HSTADDR1 &= ~UOTGHS_HSTADDR1_HSTADDRP2_Msk;
+ UOTGHS->UOTGHS_HSTADDR1 |= UOTGHS_HSTADDR1_HSTADDRP2(addr);
+ }
+ else if( pipe == 3 ) {
+ UOTGHS->UOTGHS_HSTADDR1 &= ~UOTGHS_HSTADDR1_HSTADDRP3_Msk;
+ UOTGHS->UOTGHS_HSTADDR1 |= UOTGHS_HSTADDR1_HSTADDRP3(addr);
+ }
+ else if( pipe == 4 ) {
+ UOTGHS->UOTGHS_HSTADDR2 &= ~(0x7F<<0);
+ UOTGHS->UOTGHS_HSTADDR2 |= addr;
+ }
+ else if( pipe == 5 ) {
+ UOTGHS->UOTGHS_HSTADDR2 &= ~(0x7F<<8);
+ UOTGHS->UOTGHS_HSTADDR2 |= (addr<<8);
+ }
+ else if( pipe == 6 ) {
+ UOTGHS->UOTGHS_HSTADDR2 &= ~(0x7F<<16);
+ UOTGHS->UOTGHS_HSTADDR2 |= (addr<<16);
+ }
+ else if( pipe == 7 ) {
+ UOTGHS->UOTGHS_HSTADDR2 &= ~(0x7F<<24);
+ UOTGHS->UOTGHS_HSTADDR2 |= (addr<<24);
+ }
+ else if( pipe == 8 ) {
+ UOTGHS->UOTGHS_HSTADDR3 &= ~UOTGHS_HSTADDR3_HSTADDRP8_Msk;
+ UOTGHS->UOTGHS_HSTADDR3 |= UOTGHS_HSTADDR3_HSTADDRP8(addr);
+ }
+ else if( pipe == 9 ) {
+ UOTGHS->UOTGHS_HSTADDR3 &= ~(0x7F<<8);
+ UOTGHS->UOTGHS_HSTADDR3 |= (addr<<8);
+ }
+}
+
+
+
+//! host_disable_all_pipes
+//!
+//! This function disables all pipes for the host controller.
+//! Useful to execute upon disconnection.
+//!
+//! @return Void
+//!
+void host_disable_all_pipes(void)
+{
+#if USB_HOST_PIPE_INTERRUPT_TRANSFER == ENABLE
+ Bool sav_glob_int_en;
+#endif
+ U8 p;
+
+#if USB_HOST_PIPE_INTERRUPT_TRANSFER == ENABLE
+ // Disable global interrupts
+ if ((sav_glob_int_en = Is_global_interrupt_enabled())) Disable_global_interrupt();
+#endif
+ for (p = 0; p < MAX_PEP_NB; p++)
+ { // Disable the pipe <p> (disable interrupt, free memory, reset pipe, ...)
+ Host_disable_pipe_interrupt(p);
+ Host_reset_pipe(p);
+ Host_unallocate_memory(p);
+ Host_disable_pipe(p);
+ }
+#if USB_HOST_PIPE_INTERRUPT_TRANSFER == ENABLE
+ (void)Is_host_pipe_enabled(MAX_PEP_NB - 1);
+ // Restore the global interrupts to the initial state
+ if (sav_glob_int_en) Enable_global_interrupt();
+#endif
+}
+
+//! host_set_p_txpacket
+//!
+//! This function fills the selected pipe FIFO with a constant byte, using
+//! as few accesses as possible.
+//!
+//! @param p Number of the addressed pipe
+//! @param txbyte Byte to fill the pipe with
+//! @param data_length Number of bytes to write
+//!
+//! @return Number of non-written bytes
+//!
+//! @note The selected pipe FIFO may be filled in several steps by calling
+//! host_set_p_txpacket several times.
+//!
+//! @warning Invoke Host_reset_pipe_fifo_access before this function when at
+//! FIFO beginning whether or not the FIFO is to be filled in several steps.
+//!
+//! @warning Do not mix calls to this function with calls to indexed macros.
+//!
+U32 host_set_p_txpacket(U8 p, U8 txbyte, U32 data_length)
+{
+ // Use aggregated pointers to have several alignments available for a same address
+ UnionVPtr p_fifo_cur;
+#if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used
+ StructCVPtr p_fifo_end;
+ Union64 txval;
+#else
+ UnionCVPtr p_fifo_end;
+ union
+ {
+ U8 u8[1];
+ } txval;
+#endif // !__OPTIMIZE_SIZE__
+
+ // Initialize pointers for write loops and limit the number of bytes to write
+ p_fifo_cur.u8ptr = pep_fifo[p].u8ptr;
+ p_fifo_end.u8ptr = p_fifo_cur.u8ptr +
+ min(data_length, Host_get_pipe_size(p) - Host_byte_count(p));
+#if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used
+ p_fifo_end.u16ptr = (U16 *)Align_down((U32)p_fifo_end.u8ptr, sizeof(U16));
+ p_fifo_end.u32ptr = (U32 *)Align_down((U32)p_fifo_end.u16ptr, sizeof(U32));
+ p_fifo_end.u64ptr = (U64 *)Align_down((U32)p_fifo_end.u32ptr, sizeof(U64));
+#endif // !__OPTIMIZE_SIZE__
+ txval.u8[0] = txbyte;
+#if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used
+ txval.u8[1] = txval.u8[0];
+ txval.u16[1] = txval.u16[0];
+ txval.u32[1] = txval.u32[0];
+
+ // If pointer to FIFO data register is not 16-bit aligned
+ if (!Test_align((U32)p_fifo_cur.u8ptr, sizeof(U16)))
+ {
+ // Write 8-bit data to reach 16-bit alignment
+ if (p_fifo_cur.u8ptr < p_fifo_end.u8ptr)
+ {
+ *p_fifo_cur.u8ptr++ = txval.u8[0];
+ }
+ }
+
+ // If pointer to FIFO data register is not 32-bit aligned
+ if (!Test_align((U32)p_fifo_cur.u16ptr, sizeof(U32)))
+ {
+ // Write 16-bit data to reach 32-bit alignment
+ if (p_fifo_cur.u16ptr < p_fifo_end.u16ptr)
+ {
+ *p_fifo_cur.u16ptr++ = txval.u16[0];
+ }
+ }
+
+ // If pointer to FIFO data register is not 64-bit aligned
+ if (!Test_align((U32)p_fifo_cur.u32ptr, sizeof(U64)))
+ {
+ // Write 32-bit data to reach 64-bit alignment
+ if (p_fifo_cur.u32ptr < p_fifo_end.u32ptr)
+ {
+ *p_fifo_cur.u32ptr++ = txval.u32[0];
+ }
+ }
+
+ // Write 64-bit-aligned data
+ while (p_fifo_cur.u64ptr < p_fifo_end.u64ptr)
+ {
+ *p_fifo_cur.u64ptr++ = txval.u64;
+ }
+
+ // Write remaining 32-bit data if some
+ if (p_fifo_cur.u32ptr < p_fifo_end.u32ptr)
+ {
+ *p_fifo_cur.u32ptr++ = txval.u32[0];
+ }
+
+ // Write remaining 16-bit data if some
+ if (p_fifo_cur.u16ptr < p_fifo_end.u16ptr)
+ {
+ *p_fifo_cur.u16ptr++ = txval.u16[0];
+ }
+
+ // Write remaining 8-bit data if some
+ if (p_fifo_cur.u8ptr < p_fifo_end.u8ptr)
+ {
+ *p_fifo_cur.u8ptr++ = txval.u8[0];
+ }
+
+#else
+
+ // Write remaining 8-bit data if some
+ while (p_fifo_cur.u8ptr < p_fifo_end.u8ptr)
+ {
+ *p_fifo_cur.u8ptr++ = txval.u8[0];
+ }
+
+#endif // !__OPTIMIZE_SIZE__
+
+ // Compute the number of non-written bytes
+ data_length -= p_fifo_cur.u8ptr - pep_fifo[p].u8ptr;
+
+ // Save current position in FIFO data register
+ pep_fifo[p].u8ptr = p_fifo_cur.u8ptr;
+
+ // Return the number of non-written bytes
+ return data_length;
+}
+
+//! host_write_p_txpacket
+//!
+//! This function writes the buffer pointed to by txbuf to the selected
+//! pipe FIFO, using as few accesses as possible.
+//!
+//! @param p Number of the addressed pipe
+//! @param txbuf Address of buffer to read
+//! @param data_length Number of bytes to write
+//! @param ptxbuf NULL or pointer to the buffer address to update
+//!
+//! @return Number of written bytes
+//!
+//! @note The selected pipe FIFO may be written in several steps by calling
+//! host_write_p_txpacket several times.
+//!
+//! @warning Invoke Host_reset_pipe_fifo_access before this function when at
+//! FIFO beginning whether or not the FIFO is to be written in several steps.
+//!
+//! @warning Do not mix calls to this function with calls to indexed macros.
+//!
+U32 host_write_p_txpacket(U8 p, const void *txbuf, U32 data_length, const void **ptxbuf)
+{
+ // Use aggregated pointers to have several alignments available for a same address
+ UnionVPtr p_fifo;
+ UnionCPtr txbuf_cur;
+#if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used
+ StructCPtr txbuf_end;
+#else
+ UnionCPtr txbuf_end;
+#endif // !__OPTIMIZE_SIZE__
+
+ // Initialize pointers for copy loops and limit the number of bytes to copy
+ p_fifo.u8ptr = pep_fifo[p].u8ptr;
+ txbuf_cur.u8ptr = txbuf;
+ txbuf_end.u8ptr = txbuf_cur.u8ptr +
+ min(data_length, Host_get_pipe_size(p) - Host_byte_count(p));
+#if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used
+ txbuf_end.u16ptr = (U16 *)Align_down((U32)txbuf_end.u8ptr, sizeof(U16));
+ txbuf_end.u32ptr = (U32 *)Align_down((U32)txbuf_end.u16ptr, sizeof(U32));
+ txbuf_end.u64ptr = (U64 *)Align_down((U32)txbuf_end.u32ptr, sizeof(U64));
+
+ // If all addresses are aligned the same way with respect to 16-bit boundaries
+ if (Get_align((U32)txbuf_cur.u8ptr, sizeof(U16)) == Get_align((U32)p_fifo.u8ptr, sizeof(U16)))
+ {
+ // If pointer to transmission buffer is not 16-bit aligned
+ if (!Test_align((U32)txbuf_cur.u8ptr, sizeof(U16)))
+ {
+ // Copy 8-bit data to reach 16-bit alignment
+ if (txbuf_cur.u8ptr < txbuf_end.u8ptr)
+ {
+ // 8-bit accesses to FIFO data registers do require pointer post-increment
+ *p_fifo.u8ptr++ = *txbuf_cur.u8ptr++;
+ }
+ }
+
+ // If all addresses are aligned the same way with respect to 32-bit boundaries
+ if (Get_align((U32)txbuf_cur.u16ptr, sizeof(U32)) == Get_align((U32)p_fifo.u16ptr, sizeof(U32)))
+ {
+ // If pointer to transmission buffer is not 32-bit aligned
+ if (!Test_align((U32)txbuf_cur.u16ptr, sizeof(U32)))
+ {
+ // Copy 16-bit data to reach 32-bit alignment
+ if (txbuf_cur.u16ptr < txbuf_end.u16ptr)
+ {
+ // 16-bit accesses to FIFO data registers do require pointer post-increment
+ *p_fifo.u16ptr++ = *txbuf_cur.u16ptr++;
+ }
+ }
+
+ // If pointer to transmission buffer is not 64-bit aligned
+ if (!Test_align((U32)txbuf_cur.u32ptr, sizeof(U64)))
+ {
+ // Copy 32-bit data to reach 64-bit alignment
+ if (txbuf_cur.u32ptr < txbuf_end.u32ptr)
+ {
+ // 32-bit accesses to FIFO data registers do not require pointer post-increment
+ *p_fifo.u32ptr = *txbuf_cur.u32ptr++;
+ }
+ }
+
+ // Copy 64-bit-aligned data
+ while (txbuf_cur.u64ptr < txbuf_end.u64ptr)
+ {
+ // 64-bit accesses to FIFO data registers do not require pointer post-increment
+ *p_fifo.u64ptr = *txbuf_cur.u64ptr++;
+ }
+
+ // Copy 32-bit-aligned data
+ if (txbuf_cur.u32ptr < txbuf_end.u32ptr)
+ {
+ // 32-bit accesses to FIFO data registers do not require pointer post-increment
+ *p_fifo.u32ptr = *txbuf_cur.u32ptr++;
+ }
+ }
+
+ // Copy remaining 16-bit data if some
+ while (txbuf_cur.u16ptr < txbuf_end.u16ptr)
+ {
+ // 16-bit accesses to FIFO data registers do require pointer post-increment
+ *p_fifo.u16ptr++ = *txbuf_cur.u16ptr++;
+ }
+ }
+
+#endif // !__OPTIMIZE_SIZE__
+
+ // Copy remaining 8-bit data if some
+ while (txbuf_cur.u8ptr < txbuf_end.u8ptr)
+ {
+ // 8-bit accesses to FIFO data registers do require pointer post-increment
+ *p_fifo.u8ptr++ = *txbuf_cur.u8ptr++;
+ }
+
+ // Save current position in FIFO data register
+ pep_fifo[p].u8ptr = p_fifo.u8ptr;
+
+ // Return the updated buffer address and the number of non-copied bytes
+ if (ptxbuf) *ptxbuf = txbuf_cur.u8ptr;
+ return txbuf_cur.u8ptr - (U8 *)txbuf;
+}
+
+//! host_read_p_rxpacket
+//!
+//! This function reads the selected pipe FIFO to the buffer pointed to by
+//! rxbuf, using as few accesses as possible.
+//!
+//! @param p Number of the addressed pipe
+//! @param rxbuf Address of buffer to write
+//! @param data_length Number of bytes to read
+//! @param prxbuf NULL or pointer to the buffer address to update
+//!
+//! @return Number of read bytes
+//!
+//! @note The selected pipe FIFO may be read in several steps by calling
+//! host_read_p_rxpacket several times.
+//!
+//! @warning Invoke Host_reset_pipe_fifo_access before this function when at
+//! FIFO beginning whether or not the FIFO is to be read in several steps.
+//!
+//! @warning Do not mix calls to this function with calls to indexed macros.
+//!
+U32 host_read_p_rxpacket(U8 p, void *rxbuf, U32 data_length, void **prxbuf)
+{
+ // Use aggregated pointers to have several alignments available for a same address
+ UnionCVPtr p_fifo;
+ UnionPtr rxbuf_cur;
+#if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used
+ StructCPtr rxbuf_end;
+#else
+ UnionCPtr rxbuf_end;
+#endif // !__OPTIMIZE_SIZE__
+
+ // Initialize pointers for copy loops and limit the number of bytes to copy
+ p_fifo.u8ptr = pep_fifo[p].u8ptr;
+ rxbuf_cur.u8ptr = rxbuf;
+ rxbuf_end.u8ptr = rxbuf_cur.u8ptr + min(data_length, Host_byte_count(p));
+#if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used
+ rxbuf_end.u16ptr = (U16 *)Align_down((U32)rxbuf_end.u8ptr, sizeof(U16));
+ rxbuf_end.u32ptr = (U32 *)Align_down((U32)rxbuf_end.u16ptr, sizeof(U32));
+ rxbuf_end.u64ptr = (U64 *)Align_down((U32)rxbuf_end.u32ptr, sizeof(U64));
+
+ // If all addresses are aligned the same way with respect to 16-bit boundaries
+ if (Get_align((U32)rxbuf_cur.u8ptr, sizeof(U16)) == Get_align((U32)p_fifo.u8ptr, sizeof(U16)))
+ {
+ // If pointer to reception buffer is not 16-bit aligned
+ if (!Test_align((U32)rxbuf_cur.u8ptr, sizeof(U16)))
+ {
+ // Copy 8-bit data to reach 16-bit alignment
+ if (rxbuf_cur.u8ptr < rxbuf_end.u8ptr)
+ {
+ // 8-bit accesses to FIFO data registers do require pointer post-increment
+ *rxbuf_cur.u8ptr++ = *p_fifo.u8ptr++;
+ }
+ }
+
+ // If all addresses are aligned the same way with respect to 32-bit boundaries
+ if (Get_align((U32)rxbuf_cur.u16ptr, sizeof(U32)) == Get_align((U32)p_fifo.u16ptr, sizeof(U32)))
+ {
+ // If pointer to reception buffer is not 32-bit aligned
+ if (!Test_align((U32)rxbuf_cur.u16ptr, sizeof(U32)))
+ {
+ // Copy 16-bit data to reach 32-bit alignment
+ if (rxbuf_cur.u16ptr < rxbuf_end.u16ptr)
+ {
+ // 16-bit accesses to FIFO data registers do require pointer post-increment
+ *rxbuf_cur.u16ptr++ = *p_fifo.u16ptr++;
+ }
+ }
+
+ // If pointer to reception buffer is not 64-bit aligned
+ if (!Test_align((U32)rxbuf_cur.u32ptr, sizeof(U64)))
+ {
+ // Copy 32-bit data to reach 64-bit alignment
+ if (rxbuf_cur.u32ptr < rxbuf_end.u32ptr)
+ {
+ // 32-bit accesses to FIFO data registers do not require pointer post-increment
+ *rxbuf_cur.u32ptr++ = *p_fifo.u32ptr;
+ }
+ }
+
+ // Copy 64-bit-aligned data
+ while (rxbuf_cur.u64ptr < rxbuf_end.u64ptr)
+ {
+ // 64-bit accesses to FIFO data registers do not require pointer post-increment
+ *rxbuf_cur.u64ptr++ = *p_fifo.u64ptr;
+ }
+
+ // Copy 32-bit-aligned data
+ if (rxbuf_cur.u32ptr < rxbuf_end.u32ptr)
+ {
+ // 32-bit accesses to FIFO data registers do not require pointer post-increment
+ *rxbuf_cur.u32ptr++ = *p_fifo.u32ptr;
+ }
+ }
+
+ // Copy remaining 16-bit data if some
+ while (rxbuf_cur.u16ptr < rxbuf_end.u16ptr)
+ {
+ // 16-bit accesses to FIFO data registers do require pointer post-increment
+ *rxbuf_cur.u16ptr++ = *p_fifo.u16ptr++;
+ }
+ }
+
+#endif // !__OPTIMIZE_SIZE__
+
+ // Copy remaining 8-bit data if some
+ while (rxbuf_cur.u8ptr < rxbuf_end.u8ptr)
+ {
+ // 8-bit accesses to FIFO data registers do require pointer post-increment
+ *rxbuf_cur.u8ptr++ = *p_fifo.u8ptr++;
+ }
+
+ // Save current position in FIFO data register
+ pep_fifo[p].u8ptr = (volatile U8 *)p_fifo.u8ptr;
+
+ // Return the updated buffer address and the number of copied bytes
+ if (prxbuf) *prxbuf = rxbuf_cur.u8ptr;
+ return (rxbuf_cur.u8ptr - (U8 *)rxbuf);
+}
+
+#endif // USB_HOST_FEATURE == ENABLED
diff --git a/library/ADK2/utility/usb_drv.h b/library/ADK2/utility/usb_drv.h
new file mode 100644
index 0000000..e2513fd
--- /dev/null
+++ b/library/ADK2/utility/usb_drv.h
@@ -0,0 +1,1600 @@
+/* This header file is part of the AVR Software Framework 2.0.0 release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file ******************************************************************
+ *
+ * \brief Low-level driver for AVR32 USBB.
+ *
+ * This file contains the USBB low-level driver definitions.
+ *
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices: All AVR32 devices with a USBB module can be used.
+ * - AppNote:
+ *
+ * \author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ***************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _USB_DRV_H_
+#define _USB_DRV_H_
+
+
+//_____ I N C L U D E S ____________________________________________________
+
+#include "compiler.h"
+//#include "preprocessor.h"
+//#include "usbb.h"
+#include "conf_usb.h"
+#include "chip.h"
+
+//! @defgroup USBB_low_level_driver USBB low-level driver module
+//! USBB low-level driver module
+//! @warning Bit-masks are used instead of bit-fields because PB registers
+//! require 32-bit write accesses while AVR32-GCC 4.0.2 builds 8-bit
+//! accesses even when volatile unsigned int bit-fields are specified.
+//! @{
+
+//_____ M A C R O S ________________________________________________________
+//#ifndef UOTGHS_RAM_ADDR
+//#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+//#endif
+
+//! Maximal number of USBB pipes/endpoints.
+//! This is the same value as the one produced by Usb_get_pipe_endpoint_max_nbr().
+//! As it is constant and known for a given target, there is no need to decrease
+//! performance and to complexify program structure by using a value in memory.
+//! The use of MAX_PEP_NB is hence preferred here to the use of a variable
+//! initialized from Usb_get_pipe_endpoint_max_nbr().
+#define MAX_PEP_NB CHIP_USB_NUMENDPOINTS
+
+//! @defgroup USBB_endpoints USBB endpoints
+//! Identifiers of USBB endpoints (USBB device operating mode).
+//! @{
+#define EP_CONTROL 0
+#define EP_0 0
+#define EP_1 1
+#define EP_2 2
+#define EP_3 3
+#define EP_4 4
+#define EP_5 5
+#define EP_6 6
+//! @}
+
+//! @defgroup USBB_pipes USBB pipes
+//! Identifiers of USBB pipes (USBB host operating mode).
+//! @{
+#define P_CONTROL 0
+#define P_0 0
+#define P_1 1
+#define P_2 2
+#define P_3 3
+#define P_4 4
+#define P_5 5
+#define P_6 6
+//! @}
+
+//! @defgroup USBB_types USBB standard types
+//! List of the standard types used in USBB.
+//! @{
+#define IP_NAME_PART_1 1
+#define IP_NAME_PART_2 2
+
+#define DMA_BUFFER_SIZE_16_BITS AVR32_USBB_UFEATURES_DMA_BUFFER_SIZE_16_BITS
+#define DMA_BUFFER_SIZE_24_BITS AVR32_USBB_UFEATURES_DMA_BUFFER_SIZE_24_BITS
+
+#define AWAITVRISE_TIMER AVR32_USBB_USBCON_TIMPAGE_A_WAIT_VRISE
+ #define AWAITVRISE_TMOUT_20_MS AVR32_USBB_USBCON_TIMVALUE_A_WAIT_VRISE_20_MS
+ #define AWAITVRISE_TMOUT_50_MS AVR32_USBB_USBCON_TIMVALUE_A_WAIT_VRISE_50_MS
+ #define AWAITVRISE_TMOUT_70_MS AVR32_USBB_USBCON_TIMVALUE_A_WAIT_VRISE_70_MS
+ #define AWAITVRISE_TMOUT_100_MS AVR32_USBB_USBCON_TIMVALUE_A_WAIT_VRISE_100_MS
+#define VBBUSPULSING_TIMER AVR32_USBB_USBCON_TIMPAGE_VB_BUS_PULSING
+ #define VBBUSPULSING_TMOUT_15_MS AVR32_USBB_USBCON_TIMVALUE_VB_BUS_PULSING_15_MS
+ #define VBBUSPULSING_TMOUT_23_MS AVR32_USBB_USBCON_TIMVALUE_VB_BUS_PULSING_23_MS
+ #define VBBUSPULSING_TMOUT_31_MS AVR32_USBB_USBCON_TIMVALUE_VB_BUS_PULSING_31_MS
+ #define VBBUSPULSING_TMOUT_40_MS AVR32_USBB_USBCON_TIMVALUE_VB_BUS_PULSING_40_MS
+#define PDTMOUTCNT_TIMER AVR32_USBB_USBCON_TIMPAGE_PD_TMOUT_CNT
+ #define PDTMOUTCNT_TMOUT_93_MS AVR32_USBB_USBCON_TIMVALUE_PD_TMOUT_CNT_93_MS
+ #define PDTMOUTCNT_TMOUT_105_MS AVR32_USBB_USBCON_TIMVALUE_PD_TMOUT_CNT_105_MS
+ #define PDTMOUTCNT_TMOUT_118_MS AVR32_USBB_USBCON_TIMVALUE_PD_TMOUT_CNT_118_MS
+ #define PDTMOUTCNT_TMOUT_131_MS AVR32_USBB_USBCON_TIMVALUE_PD_TMOUT_CNT_131_MS
+#define SRPDETTMOUT_TIMER AVR32_USBB_USBCON_TIMPAGE_SRP_DET_TMOUT
+ #define SRPDETTMOUT_TMOUT_10_US AVR32_USBB_USBCON_TIMVALUE_SRP_DET_TMOUT_10_US
+ #define SRPDETTMOUT_TMOUT_100_US AVR32_USBB_USBCON_TIMVALUE_SRP_DET_TMOUT_100_US
+ #define SRPDETTMOUT_TMOUT_1_MS AVR32_USBB_USBCON_TIMVALUE_SRP_DET_TMOUT_1_MS
+ #define SRPDETTMOUT_TMOUT_11_MS AVR32_USBB_USBCON_TIMVALUE_SRP_DET_TMOUT_11_MS
+
+#define TYPE_CONTROL (UOTGHS_HSTPIPCFG_PTYPE_CTRL >> UOTGHS_HSTPIPCFG_PTYPE_Pos)
+#define TYPE_ISOCHRONOUS (UOTGHS_HSTPIPCFG_PTYPE_ISO >> UOTGHS_HSTPIPCFG_PTYPE_Pos)
+#define TYPE_BULK (UOTGHS_HSTPIPCFG_PTYPE_BLK >> UOTGHS_HSTPIPCFG_PTYPE_Pos)
+#define TYPE_INTERRUPT (UOTGHS_HSTPIPCFG_PTYPE_INTRPT >> UOTGHS_HSTPIPCFG_PTYPE_Pos)
+
+#define TRANSFER_TYPE_MASK 0x03
+#define SYNCHRONIZATION_TYPE_MASK 0x0c
+#define USAGE_TYPE_MASK 0x30
+
+#define DIRECTION_OUT 0 // OUT
+#define DIRECTION_IN UOTGHS_DEVEPTCFG_EPDIR // IN
+
+#define TOKEN_SETUP (UOTGHS_HSTPIPCFG_PTOKEN_SETUP >> UOTGHS_HSTPIPCFG_PTOKEN_Pos)
+#define TOKEN_IN (UOTGHS_HSTPIPCFG_PTOKEN_IN >> UOTGHS_HSTPIPCFG_PTOKEN_Pos)
+#define TOKEN_OUT (UOTGHS_HSTPIPCFG_PTOKEN_OUT >> UOTGHS_HSTPIPCFG_PTOKEN_Pos)
+
+#define SINGLE_BANK (UOTGHS_HSTPIPCFG_PBK_1_BANK >> UOTGHS_HSTPIPCFG_PBK_Pos)
+#define DOUBLE_BANK (UOTGHS_HSTPIPCFG_PBK_2_BANK >> UOTGHS_HSTPIPCFG_PBK_Pos)
+#define TRIPLE_BANK (UOTGHS_HSTPIPCFG_PBK_3_BANK >> UOTGHS_HSTPIPCFG_PBK_Pos)
+
+#define BANK_PID_DATA0 0
+#define BANK_PID_DATA1 1
+//! @}
+
+
+//! Post-increment operations associated with 64-, 32-, 16- and 8-bit accesses to
+//! the FIFO data registers of pipes/endpoints
+//! @note 64- and 32-bit accesses to FIFO data registers do not require pointer
+//! post-increment while 16- and 8-bit ones do.
+//! @note Only for internal use.
+//! @{
+#define Pep_fifo_access_64_post_inc()
+#define Pep_fifo_access_32_post_inc()
+#define Pep_fifo_access_16_post_inc() ++
+#define Pep_fifo_access_8_post_inc() ++
+//! @}
+
+
+//! @defgroup USBB_properties USBB IP properties
+//! These macros give access to IP properties
+//! @{
+ //! Get IP name part 1 or 2
+#define Usb_get_ip_name(part) (AVR32_USBB_unamex(part))
+ //! Get IP version
+#define Usb_get_ip_version() (Rd_bitfield(AVR32_USBB_uvers, AVR32_USBB_UVERS_VERSION_NUM_MASK))
+ //! Get number of metal fixes
+#define Usb_get_metal_fix_nbr() (Rd_bitfield(AVR32_USBB_uvers, AVR32_USBB_UVERS_METAL_FIX_NUM_MASK))
+ //! Get maximal number of pipes/endpoints (number of hardware-implemented pipes/endpoints)
+#define Usb_get_pipe_endpoint_max_nbr() (((Rd_bitfield(AVR32_USBB_ufeatures, AVR32_USBB_UFEATURES_EPT_NBR_MAX_MASK) - 1) & ((1 << AVR32_USBB_UFEATURES_EPT_NBR_MAX_SIZE) - 1)) + 1)
+ //! Get number of hardware-implemented DMA channels
+#define Usb_get_dma_channel_nbr() (Rd_bitfield(AVR32_USBB_ufeatures, AVR32_USBB_UFEATURES_DMA_CHANNEL_NBR_MASK))
+ //! Get DMA buffer size
+#define Usb_get_dma_buffer_size() (Rd_bitfield(AVR32_USBB_ufeatures, AVR32_USBB_UFEATURES_DMA_BUFFER_SIZE_MASK))
+ //! Get DMA FIFO depth in words
+#define Usb_get_dma_fifo_word_depth() (((Rd_bitfield(AVR32_USBB_ufeatures, AVR32_USBB_UFEATURES_DMA_FIFO_WORD_DEPTH_MASK) - 1) & ((1 << AVR32_USBB_UFEATURES_DMA_FIFO_WORD_DEPTH_SIZE) - 1)) + 1)
+ //! Get DPRAM size (FIFO maximal size) in bytes
+#define Usb_get_dpram_size() (128 << Rd_bitfield(AVR32_USBB_ufeatures, AVR32_USBB_UFEATURES_FIFO_MAX_SIZE_MASK))
+ //! Test if DPRAM is natively byte write capable
+#define Is_usb_dpram_byte_write_capable() (Tst_bits(AVR32_USBB_ufeatures, AVR32_USBB_UFEATURES_BYTE_WRITE_DPRAM_MASK))
+ //! Get size of USBB PB address space
+#define Usb_get_ip_paddress_size() (AVR32_USBB_uaddrsize)
+//! @}
+
+
+//! @defgroup USBB_general USBB common management drivers
+//! These macros manage the USBB controller
+//! @{
+ //! Configure time-out of specified OTG timer
+#define Usb_configure_timeout(timer, timeout) (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\
+ Wr_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMPAGE_Msk, timer, UOTGHS_CTRL_TIMPAGE_Pos),\
+ Wr_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMVALUE_Msk, timeout, UOTGHS_CTRL_TIMVALUE_Pos),\
+ Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK))
+ //! Get configured time-out of specified OTG timer
+#define Usb_get_timeout(timer) (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\
+ Wr_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMPAGE_Msk, timer, UOTGHS_CTRL_TIMPAGE_Pos),\
+ Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\
+ Rd_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMVALUE_Msk, UOTGHS_CTRL_TIMVALUE_Pos))
+
+ //! Enable external USB_ID pin (listened to by USB)
+#define Usb_enable_id_pin() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIDE))
+ //! Disable external USB_ID pin (ignored by USB)
+#define Usb_disable_id_pin() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIDE))
+ //! Test if external USB_ID pin enabled (listened to by USB)
+#define Is_usb_id_pin_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIDE))
+ //! Disable external USB_ID pin and force device mode
+#define Usb_force_device_mode() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD), Usb_disable_id_pin())
+ //! Test if device mode is forced
+#define Is_usb_device_mode_forced() (!Is_usb_id_pin_enabled() && Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD))
+ //! Disable external USB_ID pin and force host mode
+#define Usb_force_host_mode() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD), Usb_disable_id_pin())
+ //! Test if host mode is forced
+#define Is_usb_host_mode_forced() (!Is_usb_id_pin_enabled() && !Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD))
+
+#if USB_HOST_FEATURE == ENABLED
+ //! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x.
+ //! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and
+ //! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from <avr32/uc3cxxxx.h>.
+// #if (defined AVR32_USBB)
+// # define USB_VBOF AVR32_USBB_VBOF_0_0
+// #else
+ #define USB_VBOF AVR32_USBC_VBOF
+// #endif
+
+ //! Check that multiplexed pin used for USB_VBOF is defined
+ #ifndef USB_VBOF
+ #error YOU MUST define in your board header file the multiplexed pin used for USB_VBOF as AVR32_USBB_USB_VBOF_x_x
+ #endif
+ //! Pin and function for USB_VBOF according to configuration from USB_VBOF
+#define USB_VBOF_PIN ATPASTE2(USB_VBOF, _PIN)
+#define USB_VBOF_FUNCTION ATPASTE2(USB_VBOF, _FUNCTION)
+ //! Output USB_VBOF onto its pin
+#define Usb_output_vbof_pin() {const Pin pUOTGHSPinVBOF[] = {PIN_UOTGHS_VBOF};\
+ PIO_PinConfigure( pUOTGHSPinVBOF, PIO_LISTSIZE( pUOTGHSPinVBOF ));}
+
+
+
+
+#endif // USB_HOST_FEATURE == ENABLED
+ //! Set USB_VBOF output pin polarity
+#define Usb_set_vbof_active_high() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSPO))
+#define Usb_set_vbof_active_low() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSPO))
+ //! Get USB_VBOF output pin polarity
+#define Is_usb_vbof_active_high() (!Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSPO))
+#define Is_usb_vbof_active_low() (!Is_usb_vbof_active_high())
+
+ //! Use device full speed mode (default)
+#define Usb_use_full_speed_mode() (Clr_bits(UOTGHS->UOTGHS_DEVCTRL, (1<<16) /*AVR32_USBB_UDCON_LS_MASK*/))
+ //! Test if device full speed mode is used
+#define Is_usb_full_speed_mode_used() (!Is_usb_low_speed_mode_forced())
+#ifdef AVR32_USBB_UDCON_SPDCONF
+ //! Force device full speed mode (i.e. disable high speed)
+//#define Usb_force_full_speed_mode() (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_Msk, 3))
+#define Usb_force_full_speed_mode() (Clr_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_Msk)),\
+ (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_FULL_SPEED))
+//! Enable dual speed mode (full speed and high speed; default)
+#define Usb_use_dual_speed_mode() (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_Msk, 0, UOTGHS_DEVCTRL_SPDCONF_Pos))
+#else
+#define Usb_force_full_speed_mode() do { } while (0)
+#define Usb_use_dual_speed_mode() do { } while (0)
+#endif
+ //! Force device low-speed mode
+#define Usb_force_low_speed_mode() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_LS))
+ //! Test if device low-speed mode is forced
+#define Is_usb_low_speed_mode_forced() (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_LS))
+ //! Test if controller is in full speed mode
+#define Is_usb_full_speed_mode() (Rd_bitfield(UOTGHS->UOTGHS_SR, UOTGHS_SR_SPEED_Msk, UOTGHS_SR_SPEED_Pos) == 0x00)
+ //! Test if controller is in low-speed mode
+//#define Is_usb_low_speed_mode() (Rd_bitfield(UOTGHS->UOTGHS_SR, UOTGHS_SR_SPEED_Msk) == AVR32_USBB_USBSTA_SPEED_LOW)
+#define Is_usb_low_speed_mode() (Rd_bitfield(UOTGHS->UOTGHS_SR, UOTGHS_SR_SPEED_Msk, UOTGHS_SR_SPEED_Pos) == 0x02)
+
+ //! Enable USB macro
+#define Usb_enable() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_USBE))
+ //! Disable USB macro
+#define Usb_disable() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_USBE))
+#define Is_usb_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_USBE))
+
+ //! Enable OTG pad
+#define Usb_enable_otg_pad() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_OTGPADE))
+ //! Disable OTG pad
+#define Usb_disable_otg_pad() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_OTGPADE))
+#define Is_usb_otg_pad_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_OTGPADE))
+
+ //! Stop (freeze) internal USB clock
+#define Usb_freeze_clock() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_FRZCLK))
+#define Usb_unfreeze_clock() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_FRZCLK))
+#define Is_usb_clock_frozen() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_FRZCLK))
+
+ //! Get the dual-role device state of the internal USB finite state machine of the USBB controller
+#define Usb_get_fsm_drd_state() (Rd_bitfield(UOTGHS->UOTGHS_FSM, UOTGHS_FSM_DRDSTATE_Msk))
+
+#define Usb_enable_id_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_IDTE))
+#define Usb_disable_id_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_IDTE))
+#define Is_usb_id_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_IDTE))
+#define Is_usb_id_device() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_IDTI))
+#define Usb_ack_id_transition() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_IDTIC)
+#define Usb_raise_id_transition() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_IDTIS)
+#define Is_usb_id_transition() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_IDTI))
+
+#define Usb_enable_vbus_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
+#define Usb_disable_vbus_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
+#define Is_usb_vbus_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
+#define Is_usb_vbus_high() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUS))
+#define Is_usb_vbus_low() (!Is_usb_vbus_high())
+#define Usb_ack_vbus_transition() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_VBUSTIC)
+#define Usb_raise_vbus_transition() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_VBUSTIS)
+#define Is_usb_vbus_transition() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUSTI))
+
+ //! enables hardware control over the USB_VBOF output pin
+#define Usb_enable_vbus_hw_control() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSHWC))
+ //! disables hardware control over the USB_VBOF output pin
+#define Usb_disable_vbus_hw_control() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSHWC))
+#define Is_usb_vbus_hw_control_enabled() (!Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSHWC))
+ //! requests VBus activation
+#define Usb_enable_vbus() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_VBUSRQS)
+ //! requests VBus deactivation
+#define Usb_disable_vbus() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_VBUSRQC)
+ //! tests if VBus activation has been requested
+#define Is_usb_vbus_enabled() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUSRQ))
+
+ //! initiates a Host Negociation Protocol
+#define Usb_device_initiate_hnp() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ))
+ //! accepts a Host Negociation Protocol
+#define Usb_host_accept_hnp() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ))
+ //! rejects a Host Negociation Protocol
+#define Usb_host_reject_hnp() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ))
+ //! initiates a Session Request Protocol
+#define Usb_device_initiate_srp() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPREQ))
+ //! selects VBus as SRP method
+#define Usb_select_vbus_srp_method() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPSEL))
+#define Is_usb_vbus_srp_method_selected() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPSEL))
+ //! selects data line as SRP method
+#define Usb_select_data_srp_method() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPSEL))
+#define Is_usb_data_srp_method_selected() (!Is_usb_vbus_srp_method_selected())
+ //! tests if a HNP occurs
+#define Is_usb_hnp() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ))
+ //! tests if a SRP from device occurs
+#define Is_usb_device_srp() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPREQ))
+
+ //! enables suspend time out interrupt
+#define Usb_enable_suspend_time_out_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_STOE))
+ //! disables suspend time out interrupt
+#define Usb_disable_suspend_time_out_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_STOE))
+#define Is_usb_suspend_time_out_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_STOE))
+ //! acks suspend time out interrupt
+#define Usb_ack_suspend_time_out_interrupt() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_STOIC)
+ //! raises suspend time out interrupt
+#define Usb_raise_suspend_time_out_interrupt() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_STOIS)
+ //! tests if a suspend time out occurs
+#define Is_usb_suspend_time_out_interrupt() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_STOI))
+
+ //! enables HNP error interrupt
+#define Usb_enable_hnp_error_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPERRE))
+ //! disables HNP error interrupt
+#define Usb_disable_hnp_error_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPERRE))
+#define Is_usb_hnp_error_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPERRE))
+ //! acks HNP error interrupt
+#define Usb_ack_hnp_error_interrupt() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_HNPERRIC)
+ //! raises HNP error interrupt
+#define Usb_raise_hnp_error_interrupt() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_HNPERRIS)
+ //! tests if a HNP error occurs
+#define Is_usb_hnp_error_interrupt() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_HNPERRI))
+
+ //! enables role exchange interrupt
+#define Usb_enable_role_exchange_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_ROLEEXE))
+ //! disables role exchange interrupt
+#define Usb_disable_role_exchange_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_ROLEEXE))
+#define Is_usb_role_exchange_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_ROLEEXE))
+ //! acks role exchange interrupt
+#define Usb_ack_role_exchange_interrupt() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_ROLEEXIC)
+ //! raises role exchange interrupt
+#define Usb_raise_role_exchange_interrupt() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_ROLEEXIS)
+ //! tests if a role exchange occurs
+#define Is_usb_role_exchange_interrupt() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_ROLEEXI))
+
+ //! enables B-device connection error interrupt
+#define Usb_enable_bconnection_error_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_BCERRE))
+ //! disables B-device connection error interrupt
+#define Usb_disable_bconnection_error_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_BCERRE))
+#define Is_usb_bconnection_error_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_BCERRE))
+ //! acks B-device connection error interrupt
+#define Usb_ack_bconnection_error_interrupt() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_BCERRIC)
+ //! raises B-device connection error interrupt
+#define Usb_raise_bconnection_error_interrupt() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_BCERRIS)
+ //! tests if a B-device connection error occurs
+#define Is_usb_bconnection_error_interrupt() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_BCERRI))
+
+ //! enables VBus error interrupt
+#define Usb_enable_vbus_error_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBERRE))
+ //! disables VBus error interrupt
+#define Usb_disable_vbus_error_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBERRE))
+#define Is_usb_vbus_error_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBERRE))
+ //! acks VBus error interrupt
+#define Usb_ack_vbus_error_interrupt() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_VBERRIC)
+ //! raises VBus error interrupt
+#define Usb_raise_vbus_error_interrupt() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_VBERRIS)
+ //! tests if a VBus error occurs
+#define Is_usb_vbus_error_interrupt() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBERRI))
+
+ //! enables SRP interrupt
+#define Usb_enable_srp_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPE))
+ //! disables SRP interrupt
+#define Usb_disable_srp_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPE))
+#define Is_usb_srp_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPE))
+ //! acks SRP interrupt
+#define Usb_ack_srp_interrupt() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_SRPIC)
+ //! raises SRP interrupt
+#define Usb_raise_srp_interrupt() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_SRPIS)
+ //! tests if a SRP occurs
+#define Is_usb_srp_interrupt() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_SRPI))
+//! @}
+
+
+//! @defgroup USBB_device_driver USBB device controller drivers
+//! These macros manage the USBB Device controller.
+//! @{
+ //! initiates a remote wake-up
+#define Usb_initiate_remote_wake_up() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_RMWKUP))
+ //! detaches from USB bus
+#define Usb_detach() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_DETACH))
+ //! attaches to USB bus
+#define Usb_attach() (Clr_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_DETACH))
+ //! test if remote wake-up still running
+#define Is_usb_pending_remote_wake_up() (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_RMWKUP))
+ //! test if the device is detached
+#define Is_usb_detached() (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_DETACH))
+
+ //! Test device compliance
+#define Usb_dev_forceHighSpeed() Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_Msk, 2, UOTGHS_DEVCTRL_SPDCONF_Pos)
+
+ //! enables remote wake-up interrupt
+#define Usb_enable_remote_wake_up_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_UPRSMES)
+ //! disables remote wake-up interrupt
+#define Usb_disable_remote_wake_up_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_UPRSMEC)
+
+#define Is_usb_remote_wake_up_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_UPRSME))
+ //! acks remote wake-up
+#define Usb_ack_remote_wake_up_start() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_UPRSMC)
+ //! raises remote wake-up
+#define Usb_raise_remote_wake_up_start() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_UPRSMS)
+ //! tests if remote wake-up still running
+#define Is_usb_remote_wake_up_start() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_UPRSM))
+
+ //! enables resume interrupt
+#define Usb_enable_resume_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_EORSMES)
+ //! disables resume interrupt
+#define Usb_disable_resume_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_EORSMEC)
+#define Is_usb_resume_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_EORSME))
+ //! acks resume
+#define Usb_ack_resume() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_EORSMC)
+ //! raises resume
+#define Usb_raise_resume() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_EORSMS)
+ //! tests if resume occurs
+#define Is_usb_resume() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_EORSM))
+
+ //! enables wake-up interrupt
+#define Usb_enable_wake_up_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_WAKEUPES)
+ //! disables wake-up interrupt
+#define Usb_disable_wake_up_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_WAKEUPEC)
+#define Is_usb_wake_up_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_WAKEUPE))
+ //! acks wake-up
+#define Usb_ack_wake_up() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_WAKEUPC)
+ //! raises wake-up
+#define Usb_raise_wake_up() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_WAKEUPS)
+ //! tests if wake-up occurs
+#define Is_usb_wake_up() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_WAKEUP))
+
+ //! enables USB reset interrupt
+#define Usb_enable_reset_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_EORSTES)
+ //! disables USB reset interrupt
+#define Usb_disable_reset_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_EORSTEC)
+#define Is_usb_reset_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_EORSTE))
+ //! acks USB reset
+#define Usb_ack_reset() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_EORSTC)
+ //! raises USB reset
+#define Usb_raise_reset() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_EORSTS)
+ //! tests if USB reset occurs
+#define Is_usb_reset() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_EORST))
+
+//! disables Micro Start of Frame Interrupt
+#define Usb_disable_msof_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_MSOFEC)
+//! enables Start-of-Frame Interrupt
+#define Usb_enable_sof_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_SOFES)
+ //! disables Start-of-Frame Interrupt
+#define Usb_disable_sof_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_SOFEC)
+#define Is_usb_sof_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVICR_SOFC))
+ //! acks Start-of-Frame
+#define Usb_ack_sof() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_SOFC)
+ //! raises Start-of-Frame
+#define Usb_raise_sof() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_SOFS)
+ //! tests if Start-of-Frame occurs
+#define Is_usb_sof() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_SOF))
+
+ //! enables suspend state interrupt
+#define Usb_enable_suspend_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_SUSPES)
+ //! disables suspend state interrupt
+#define Usb_disable_suspend_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_SUSPEC)
+#define Is_usb_suspend_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_SUSPE))
+ //! acks Suspend
+#define Usb_ack_suspend() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_SUSPC)
+
+ //! raises Suspend
+#define Usb_raise_suspend() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_SUSPS)
+ //! tests if Suspend state detected
+#define Is_usb_suspend() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_SUSP))
+
+ //! enables USB device address
+#define Usb_enable_address() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_ADDEN))
+ //! disables USB device address
+#define Usb_disable_address() (Clr_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_ADDEN))
+#define Is_usb_address_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_ADDEN))
+ //! configures the USB device address
+//#define Usb_configure_address(addr) (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, AVR32_USBB_UDCON_UADD_MASK, addr))
+#define Usb_configure_address(addr) UOTGHS->UOTGHS_DEVCTRL &= ~UOTGHS_DEVCTRL_UADD_Msk;\
+ UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_UADD(addr)
+ //! gets the currently configured USB device address
+#define Usb_get_configured_address() (Rd_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_UADD_Msk))
+
+ //! returns the current frame number
+#define Usb_frame_number() (Rd_bitfield(UOTGHS->UOTGHS_DEVFNUM, UOTGHS_DEVFNUM_MFNUM_Msk))
+ //! tests if a crc error occurs in frame number
+#define Is_usb_frame_number_crc_error() (Tst_bits(UOTGHS->UOTGHS_DEVFNUM, UOTGHS_DEVFNUM_FNCERR))
+//! @}
+
+
+//! @defgroup USBB_general_endpoint USBB endpoint drivers
+//! These macros manage the common features of the endpoints.
+//! @{
+ //! resets the selected endpoint
+#define Usb_reset_endpoint(ep) (Set_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)),\
+ Clr_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)))
+ //! tests if the selected endpoint is being reset
+#define Is_usb_resetting_endpoint(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)))
+
+ //! enables the selected endpoint
+#define Usb_enable_endpoint(ep) (Set_bits(UOTGHS->UOTGHS_DEVEPT, 1 << (ep)))
+ //! enables the STALL handshake
+#define Usb_enable_stall_handshake(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_STALLRQS)
+ //! Sends a STALL handshake for the next host request. A STALL handshake will
+ //! be sent for each following request until a SETUP or a Clear Halt Feature
+ //! occurs for this endpoint.
+#define Usb_halt_endpoint(ep) (Usb_enable_stall_handshake(ep))
+ //! resets the data toggle sequence
+#define Usb_reset_data_toggle(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_RSTDTS)
+ //! disables the selected endpoint
+#define Usb_disable_endpoint(ep) (Clr_bits(UOTGHS->UOTGHS_DEVEPT, 1 << (ep)))
+ //! disables the STALL handshake
+#define Usb_disable_stall_handshake(ep) (UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_STALLRQC)
+ //! tests if the selected endpoint is enabled
+#define Is_usb_endpoint_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPT, 1 << (ep)))
+ //! tests if STALL handshake request is running
+#define Is_usb_endpoint_stall_requested(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_STALLRQ))
+ //! tests if the data toggle sequence is being reset
+#define Is_usb_data_toggle_reset(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_RSTDT))
+
+ //! tests if an interrupt is triggered by the selected endpoint
+#define Is_usb_endpoint_interrupt(ep) (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_PEP_0 << (ep)))
+ //! enables the selected endpoint interrupt
+#define Usb_enable_endpoint_interrupt(ep) (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_PEP_0 << (ep))
+ //! disables the selected endpoint interrupt
+#define Usb_disable_endpoint_interrupt(ep) (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_PEP_0 << (ep))
+ //! tests if the selected endpoint interrupt is enabled
+#define Is_usb_endpoint_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_PEP_0 << (ep)))
+ //! returns the lowest endpoint number generating an endpoint interrupt or MAX_PEP_NB if none
+#define Usb_get_interrupt_endpoint_number() (ctz(((UOTGHS->UOTGHS_DEVISR >> 12 /*AVR32_USBB_UDINT_EP0INT_OFFSET*/) &\
+ (UOTGHS->UOTGHS_DEVIMR >> 12 /*AVR32_USBB_UDINTE_EP0INTE_OFFSET*/)) |\
+ (1 << MAX_PEP_NB)))
+
+ //! configures the selected endpoint type
+#define Usb_configure_endpoint_type(ep, type) (Wr_bitfield(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_EPTYPE_Msk, type, UOTGHS_DEVEPTCFG_EPTYPE_Pos))
+ //! gets the configured selected endpoint type
+#define Usb_get_endpoint_type(ep) (Rd_bitfield(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_EPTYPE_Msk))
+ //! enables the bank autoswitch for the selected endpoint
+#define Usb_enable_endpoint_bank_autoswitch(ep) (Set_bits(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_AUTOSW))
+ //! disables the bank autoswitch for the selected endpoint
+#define Usb_disable_endpoint_bank_autoswitch(ep) (Clr_bits(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_AUTOSW))
+#define Is_usb_endpoint_bank_autoswitch_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_AUTOSW))
+ //! configures the selected endpoint direction
+#define Usb_configure_endpoint_direction(ep, dir) (Wr_bitfield(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_EPDIR, dir, 8))
+ //! gets the configured selected endpoint direction
+#define Usb_get_endpoint_direction(ep) (Rd_bitfield(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_EPDIR, 8))
+ //! Bounds given integer size to allowed range and rounds it up to the nearest
+ //! available greater size, then applies register format of USBB controller
+ //! for endpoint size bit-field.
+//#define Usb_format_endpoint_size(size) (32 - clz(((U32)min(max(size, 8), 1024) << 1) - 1) - 1 - 3)
+#define Usb_format_endpoint_size(size) ((size <= 8 ) ? 0:\
+ (size <= 16 ) ? 1:\
+ (size <= 32 ) ? 2:\
+ (size <= 64 ) ? 3:\
+ (size <= 128) ? 4:\
+ (size <= 256) ? 5:\
+ (size <= 512) ? 6:7)
+
+ //! configures the selected endpoint size
+#define Usb_configure_endpoint_size(ep, size) (Wr_bitfield(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_EPSIZE_Msk, Usb_format_endpoint_size(size), UOTGHS_DEVEPTCFG_EPSIZE_Pos))
+ //! gets the configured selected endpoint size
+#define Usb_get_endpoint_size(ep) (8 << Rd_bitfield(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_EPSIZE_Msk, UOTGHS_DEVEPTCFG_EPSIZE_Pos))
+ //! configures the selected endpoint number of banks
+#define Usb_configure_endpoint_bank(ep, bank) (Wr_bitfield(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_EPBK_Msk, bank, UOTGHS_DEVEPTCFG_EPBK_Pos))
+ //! gets the configured selected endpoint number of banks
+#define Usb_get_endpoint_bank(ep) (Rd_bitfield(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_EPBK_Msk, UOTGHS_DEVEPTCFG_EPBK_Pos))
+ //! allocates the configuration x in DPRAM memory
+#define Usb_allocate_memory(ep) (Set_bits(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_ALLOC))
+ //! un-allocates the configuration x in DPRAM memory
+#define Usb_unallocate_memory(ep) (Clr_bits(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_ALLOC))
+#define Is_usb_memory_allocated(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_ALLOC))
+
+ //! configures selected endpoint in one step
+#define Usb_configure_endpoint(ep, type, dir, size, bank) \
+(\
+ Usb_enable_endpoint(ep),\
+ Clr_bits(UOTGHS->UOTGHS_DEVEPTCFG[ep], 0xFFFF),\
+ Wr_bits(UOTGHS->UOTGHS_DEVEPTCFG[ep], UOTGHS_DEVEPTCFG_EPTYPE_Msk |\
+ UOTGHS_DEVEPTCFG_EPDIR |\
+ UOTGHS_DEVEPTCFG_EPSIZE_Msk |\
+ UOTGHS_DEVEPTCFG_EPBK_Msk, \
+ ( (U32)(type) << UOTGHS_DEVEPTCFG_EPTYPE_Pos ) |\
+ ( (U32)((dir) << 8 ) & UOTGHS_DEVEPTCFG_EPDIR ) |\
+ ( (U32)(Usb_format_endpoint_size(size)) << UOTGHS_DEVEPTCFG_EPSIZE_Pos ) |\
+ ( (U32)((bank) << UOTGHS_DEVEPTCFG_EPBK_Pos ) )),\
+ Usb_allocate_memory(ep),\
+\
+ Is_usb_endpoint_configured(ep)\
+)
+
+ //! acks endpoint overflow interrupt
+#define Usb_ack_overflow_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_OVERFIC)
+ //! raises endpoint overflow interrupt
+#define Usb_raise_overflow_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIFR[ep] = UOTGHS_DEVEPTIFR_OVERFIS)
+ //! acks endpoint underflow interrupt
+#define Usb_ack_underflow_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_RXSTPIC)
+ //! raises endpoint underflow interrupt
+#define Usb_raise_underflow_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIFR[ep] = UOTGHS_DEVEPTIFR_RXSTPIS)
+ //! returns data toggle
+#define Usb_data_toggle(ep) (Rd_bitfield(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_DTSEQ_Msk))
+ //! returns the number of busy banks
+#define Usb_nb_busy_bank(ep) (Rd_bitfield(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_NBUSYBK_Msk))
+ //! tests if current endpoint is configured
+#define Is_usb_endpoint_configured(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_CFGOK))
+ //! tests if an overflow occurs
+#define Is_usb_overflow(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_OVERFI))
+ //! tests if an underflow occurs
+#define Is_usb_underflow(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_RXSTPI))
+
+ //! returns the byte count
+#define Usb_byte_count(ep) (Rd_bitfield(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_BYCT_Msk, UOTGHS_DEVEPTISR_BYCT_Pos))
+ //! returns the control direction
+#define Usb_control_direction() (Rd_bitfield(UOTGHS->UOTGHS_DEVEPTISR(EP_CONTROL), UOTGHS_DEVEPTISR_CTRLDIR, 17))
+ //! returns the number of the current bank
+#define Usb_current_bank(ep) (Rd_bitfield(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_CURRBK_Msk, UOTGHS_DEVEPTISR_CURRBK_Pos))
+
+ //! kills last bank
+#define Usb_kill_last_in_bank(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_KILLBKS)
+ //! acks SHORT PACKET received
+#define Usb_ack_short_packet(ep) (UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_SHORTPACKETC)
+ //! raises SHORT PACKET received
+#define Usb_raise_short_packet(ep) (UOTGHS->UOTGHS_DEVEPTIFR[ep] = UOTGHS_DEVEPTIFR_SHORTPACKETS)
+ //! acks STALL sent
+#define Usb_ack_stall(ep) (UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_STALLEDIC)
+ //! raises STALL sent
+#define Usb_raise_stall(ep) (UOTGHS->UOTGHS_DEVEPTIFR[ep] = UOTGHS_DEVEPTIFR_SHORTPACKETS)
+ //! acks CRC ERROR ISO OUT detected
+#define Usb_ack_crc_error(ep) (UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_STALLEDIC)
+ //! raises CRC ERROR ISO OUT detected
+#define Usb_raise_crc_error(ep) (UOTGHS->UOTGHS_DEVEPTIFR[ep] = UOTGHS_DEVEPTIFR_STALLEDIS)
+ //! acks NAK IN received
+#define Usb_ack_nak_in(ep) (UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_NAKINIC)
+ //! raises NAK IN received
+#define Usb_raise_nak_in(ep) (UOTGHS->UOTGHS_DEVEPTIFR[ep] = UOTGHS_DEVEPTIFR_NAKINIS)
+ //! acks NAK OUT received
+#define Usb_ack_nak_out(ep) (UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_NAKOUTIC)
+ //! raises NAK OUT received
+#define Usb_raise_nak_out(ep) (UOTGHS->UOTGHS_DEVEPTIFR[ep] = UOTGHS_DEVEPTIFR_NAKOUTIS)
+
+ //! tests if last bank killed
+#define Is_usb_last_in_bank_killed(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_KILLBK))
+ //! tests if endpoint read allowed
+#define Is_usb_read_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_RWALL))
+ //! tests if endpoint write allowed
+#define Is_usb_write_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_RWALL))
+ //! tests if SHORT PACKET received
+#define Is_usb_short_packet(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_SHORTPACKET))
+ //! tests if STALL sent
+#define Is_usb_stall(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_STALLEDI))
+ //! tests if CRC ERROR ISO OUT detected
+#define Is_usb_crc_error(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_STALLEDI))
+ //! tests if NAK IN received
+#define Is_usb_nak_in(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_NAKINI))
+ //! tests if NAK OUT received
+#define Is_usb_nak_out(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_NAKOUTI))
+
+ //! clears FIFOCON bit
+#define Usb_ack_fifocon(ep) (UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_FIFOCONC)
+
+ //! acks SETUP received
+#define Usb_ack_setup_received_free() (UOTGHS->UOTGHS_DEVEPTICR[EP_CONTROL] = UOTGHS_DEVEPTICR_RXSTPIC)
+ //! raises SETUP received
+#define Usb_raise_setup_received() (UOTGHS->UOTGHS_DEVEPTIFR[EP_CONTROL] = UOTGHS_DEVEPTIFR_RXSTPIS)
+ //! acks OUT received
+#define Usb_ack_out_received(ep) (UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_RXOUTIC)
+ //! raises OUT received
+#define Usb_raise_out_received(ep) (UOTGHS->UOTGHS_DEVEPTIFR[ep] = UOTGHS_DEVEPTIFR_RXOUTIS)
+ //! frees current bank for OUT endpoint
+#define Usb_free_out(ep) (Usb_ack_fifocon(ep))
+ //! acks OUT received and frees current bank
+#define Usb_ack_out_received_free(ep) (Usb_ack_out_received(ep), Usb_free_out(ep))
+ //! acks OUT received on control endpoint and frees current bank
+#define Usb_ack_control_out_received_free() (UOTGHS->UOTGHS_DEVEPTICR[EP_CONTROL] = UOTGHS_DEVEPTICR_RXOUTIC)
+ //! raises OUT received on control endpoint
+#define Usb_raise_control_out_received() (UOTGHS->UOTGHS_DEVEPTIFR[EP_CONTROL] = UOTGHS_DEVEPTIFR_RXOUTIS)
+
+ //! acks IN ready
+#define Usb_ack_in_ready(ep) (UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_TXINIC)
+ //! raises IN ready
+#define Usb_raise_in_ready(ep) (UOTGHS->UOTGHS_DEVEPTIFR[ep] = UOTGHS_DEVEPTIFR_TXINIS)
+ //! sends current bank for IN endpoint
+#define Usb_send_in(ep) (Usb_ack_fifocon(ep))
+ //! acks IN ready and sends current bank
+#define Usb_ack_in_ready_send(ep) (Usb_ack_in_ready(ep), Usb_send_in(ep))
+ //! acks IN ready on control endpoint and sends current bank
+#define Usb_ack_control_in_ready_send() (UOTGHS->UOTGHS_DEVEPTICR[EP_CONTROL] = UOTGHS_DEVEPTICR_TXINIC)
+ //! raises IN ready on control endpoint
+#define Usb_raise_control_in_ready() (UOTGHS->UOTGHS_DEVEPTIFR[EP_CONTROL] = UOTGHS_DEVEPTIFR_TXINIS)
+
+ //! tests if FIFOCON bit set
+#define Is_usb_fifocon(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_FIFOCON))
+
+ //! tests if SETUP received
+#define Is_usb_setup_received() (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[EP_CONTROL], UOTGHS_DEVEPTISR_RXSTPI))
+ //! tests if OUT received
+#define Is_usb_out_received(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_RXOUTI))
+ //! tests if current bank filled for OUT endpoint
+#define Is_usb_out_filled(ep) (Is_usb_fifocon(ep))
+ //! tests if OUT received on control endpoint
+#define Is_usb_control_out_received() (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[EP_CONTROL], UOTGHS_DEVEPTISR_RXOUTI))
+
+ //! tests if IN ready
+#define Is_usb_in_ready(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[ep], UOTGHS_DEVEPTISR_TXINI))
+ //! tests if current bank sent for IN endpoint
+#define Is_usb_in_sent(ep) (Is_usb_fifocon(ep))
+ //! tests if IN ready on control endpoint
+#define Is_usb_control_in_ready() (Tst_bits(UOTGHS->UOTGHS_DEVEPTISR[EP_CONTROL], UOTGHS_DEVEPTISR_TXINI))
+
+ //! forces all banks full (OUT) or free (IN) interrupt
+#define Usb_force_bank_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIFR[ep] = UOTGHS_DEVEPTIFR_NBUSYBKS)
+ //! unforces all banks full (OUT) or free (IN) interrupt
+#define Usb_unforce_bank_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIFR[ep] = UOTGHS_DEVEPTIFR_NBUSYBKS)
+ //! enables all banks full (OUT) or free (IN) interrupt
+#define Usb_enable_bank_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_NBUSYBKES)
+ //! enables SHORT PACKET received interrupt
+#define Usb_enable_short_packet_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_SHORTPACKETES)
+ //! enables STALL sent interrupt
+#define Usb_enable_stall_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_STALLRQS)
+ //! enables CRC ERROR ISO OUT detected interrupt
+#define Usb_enable_crc_error_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_STALLRQS)
+ //! enables overflow interrupt
+#define Usb_enable_overflow_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_OVERFES)
+ //! enables NAK IN interrupt
+#define Usb_enable_nak_in_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_NAKINES)
+ //! enables NAK OUT interrupt
+#define Usb_enable_nak_out_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_NAKOUTES)
+ //! enables SETUP received interrupt
+#define Usb_enable_setup_received_interrupt() (UOTGHS->UOTGHS_DEVEPTIER(EP_CONTROL) = UOTGHS_DEVEPTIER_RXSTPES)
+ //! enables underflow interrupt
+#define Usb_enable_underflow_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_UNDERFES)
+ //! enables OUT received interrupt
+#define Usb_enable_out_received_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_RXOUTES)
+ //! enables OUT received on control endpoint interrupt
+#define Usb_enable_control_out_received_interrupt() (UOTGHS->UOTGHS_DEVEPTIER(EP_CONTROL) = UOTGHS_DEVEPTIER_RXOUTES)
+ //! enables IN ready interrupt
+#define Usb_enable_in_ready_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_TXINES)
+ //! enables IN ready on control endpoint interrupt
+#define Usb_enable_control_in_ready_interrupt() (UOTGHS->UOTGHS_DEVEPTIER(EP_CONTROL) = UOTGHS_DEVEPTIER_TXINES)
+ //! disables all banks full (OUT) or free (IN) interrupt
+#define Usb_disable_bank_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_NBUSYBKEC)
+ //! disables SHORT PACKET received interrupt
+#define Usb_disable_short_packet_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_SHORTPACKETEC)
+ //! disables STALL sent interrupt
+#define Usb_disable_stall_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_STALLEDEC)
+ //! disables CRC ERROR ISO OUT detected interrupt
+#define Usb_disable_crc_error_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_STALLEDEC)
+ //! disables overflow interrupt
+#define Usb_disable_overflow_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_OVERFEC)
+ //! disables NAK IN interrupt
+#define Usb_disable_nak_in_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_NAKINEC)
+ //! disables NAK OUT interrupt
+#define Usb_disable_nak_out_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_NAKOUTEC)
+ //! disables SETUP received interrupt
+#define Usb_disable_setup_received_interrupt() (UOTGHS->UOTGHS_DEVEPTIDR[EP_CONTROL] = UOTGHS_DEVEPTIDR_RXSTPEC)
+ //! disables underflow interrupt
+#define Usb_disable_underflow_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_RXSTPEC)
+ //! disables OUT received interrupt
+#define Usb_disable_out_received_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_RXOUTEC)
+ //! disables OUT received on control endpoint interrupt
+#define Usb_disable_control_out_received_interrupt() (UOTGHS->UOTGHS_DEVEPTIDR[EP_CONTROL] = UOTGHS_DEVEPTIDR_RXOUTEC)
+ //! disables IN ready interrupt
+#define Usb_disable_in_ready_interrupt(ep) (UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_TXINEC)
+ //! disables IN ready on control endpoint interrupt
+#define Usb_disable_control_in_ready_interrupt() (UOTGHS->UOTGHS_DEVEPTIDR[EP_CONTROL] = UOTGHS_DEVEPTIDR_TXINEC)
+ //! tests if all banks full (OUT) or free (IN) interrupt enabled
+#define Is_usb_bank_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_NBUSYBKE))
+ //! tests if SHORT PACKET received interrupt is enabled
+#define Is_usb_short_packet_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_SHORTPACKETE))
+ //! tests if STALL sent interrupt is enabled
+#define Is_usb_stall_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_STALLEDE))
+ //! tests if CRC ERROR ISO OUT detected interrupt is enabled
+#define Is_usb_crc_error_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_STALLEDE))
+ //! tests if overflow interrupt is enabled
+#define Is_usb_overflow_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_OVERFE))
+ //! tests if NAK IN interrupt is enabled
+#define Is_usb_nak_in_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_NAKINE))
+ //! tests if NAK OUT interrupt is enabled
+#define Is_usb_nak_out_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_NAKOUTE))
+ //! tests if SETUP received interrupt is enabled
+#define Is_usb_setup_received_interrupt_enabled() (Tst_bits(Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[EP_CONTROL], UOTGHS_DEVEPTIMR_RXSTPE))
+ //! tests if underflow interrupt is enabled
+#define Is_usb_underflow_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_RXSTPE))
+ //! tests if OUT received interrupt is enabled
+#define Is_usb_out_received_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_RXOUTE))
+ //! tests if OUT received on control endpoint interrupt is enabled
+#define Is_usb_control_out_received_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[EP_CONTROL], UOTGHS_DEVEPTIMR_RXOUTE))
+ //! tests if IN ready interrupt is enabled
+#define Is_usb_in_ready_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_TXINE))
+ //! tests if IN ready on control endpoint interrupt is enabled
+#define Is_usb_control_in_ready_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[EP_CONTROL], UOTGHS_DEVEPTIMR_TXINE))
+
+
+#define AVR32_USBB_SLAVE_ADDRESS UOTGHS_RAM_ADDR
+#define AVR32_USBB_SLAVE_SIZE 0x00800000
+#define AVR32_USBB_SLAVE ((unsigned char *)AVR32_USBB_SLAVE_ADDRESS)
+//#define USB_FIFO (((volatile uint32_t *)UOTGHS_RAM_ADDR))
+//#define USB_FIFO_CHAR (((volatile uint8_t *)UOTGHS_RAM_ADDR))
+#define TPASTE2( a, b) a##b
+#define TPASTE3( a, b, c) a##b##c
+
+//! Access point to the FIFO data registers of pipes/endpoints
+ //! @param x Pipe/endpoint of which to access FIFO data register
+ //! @param scale Data index scale in bits: 64, 32, 16 or 8
+ //! @return Volatile 64-, 32-, 16- or 8-bit data pointer to FIFO data register
+#define AVR32_USBB_FIFOX_DATA(x, scale) \
+ (((volatile TPASTE2(U, scale) (*)[0x8000 / ((scale) / 8)])AVR32_USBB_SLAVE)[(x)])
+
+
+//! Get 64-, 32-, 16- or 8-bit access to FIFO data register of selected endpoint.
+ //! @param ep Endpoint of which to access FIFO data register
+ //! @param scale Data scale in bits: 64, 32, 16 or 8
+ //! @return Volatile 64-, 32-, 16- or 8-bit data pointer to FIFO data register
+ //! @warning It is up to the user of this macro to make sure that all accesses
+ //! are aligned with their natural boundaries except 64-bit accesses which
+ //! require only 32-bit alignment.
+ //! @warning It is up to the user of this macro to make sure that used HSB
+ //! addresses are identical to the DPRAM internal pointer modulo 32 bits.
+#define Usb_get_endpoint_fifo_access(ep, scale) \
+ (AVR32_USBB_FIFOX_DATA(ep, scale))
+
+ //! Reset known position inside FIFO data register of selected endpoint.
+ //! @param ep Endpoint of which to reset known position
+ //! @warning Always call this macro before any read/write macro/function
+ //! when at FIFO beginning.
+#define Usb_reset_endpoint_fifo_access(ep) \
+ (pep_fifo[(ep)].u64ptr = Usb_get_endpoint_fifo_access(ep, 64))
+
+ //! Read 64-, 32-, 16- or 8-bit data from FIFO data register of selected endpoint.
+ //! @param ep Endpoint of which to access FIFO data register
+ //! @param scale Data scale in bits: 64, 32, 16 or 8
+ //! @return 64-, 32-, 16- or 8-bit data read
+ //! @warning It is up to the user of this macro to make sure that all accesses
+ //! are aligned with their natural boundaries except 64-bit accesses which
+ //! require only 32-bit alignment.
+ //! @note This macro assures that used HSB addresses are identical to the
+ //! DPRAM internal pointer modulo 32 bits.
+ //! @warning Always call Usb_reset_endpoint_fifo_access before this macro when
+ //! at FIFO beginning.
+ //! @warning Do not mix calls to this macro with calls to indexed macros below.
+#define Usb_read_endpoint_data(ep, scale) \
+ (*pep_fifo[(ep)].TPASTE3(u, scale, ptr)\
+ TPASTE3(Pep_fifo_access_, scale, _post_inc)())
+
+ //! Write 64-, 32-, 16- or 8-bit data to FIFO data register of selected endpoint.
+ //! @param ep Endpoint of which to access FIFO data register
+ //! @param scale Data scale in bits: 64, 32, 16 or 8
+ //! @param data 64-, 32-, 16- or 8-bit data to write
+ //! @return 64-, 32-, 16- or 8-bit data written
+ //! @warning It is up to the user of this macro to make sure that all accesses
+ //! are aligned with their natural boundaries except 64-bit accesses which
+ //! require only 32-bit alignment.
+ //! @note This macro assures that used HSB addresses are identical to the
+ //! DPRAM internal pointer modulo 32 bits.
+ //! @warning Always call Usb_reset_endpoint_fifo_access before this macro when
+ //! at FIFO beginning.
+ //! @warning Do not mix calls to this macro with calls to indexed macros below.
+#define Usb_write_endpoint_data(ep, scale, data) \
+ (*pep_fifo[(ep)].TPASTE3(u, scale, ptr)\
+ TPASTE3(Pep_fifo_access_, scale, _post_inc)() = (data))
+
+ //! Read 64-, 32-, 16- or 8-bit indexed data from FIFO data register of selected endpoint.
+ //! @param ep Endpoint of which to access FIFO data register
+ //! @param scale Data scale in bits: 64, 32, 16 or 8
+ //! @param index Index of scaled data array to access
+ //! @return 64-, 32-, 16- or 8-bit data read
+ //! @warning It is up to the user of this macro to make sure that all accesses
+ //! are aligned with their natural boundaries except 64-bit accesses which
+ //! require only 32-bit alignment.
+ //! @warning It is up to the user of this macro to make sure that used HSB
+ //! addresses are identical to the DPRAM internal pointer modulo 32 bits.
+ //! @warning Do not mix calls to this macro with calls to non-indexed macros above.
+#define Usb_read_endpoint_indexed_data(ep, scale, index) \
+ (AVR32_USBB_FIFOX_DATA(ep, scale)[(index)])
+
+ //! Write 64-, 32-, 16- or 8-bit indexed data to FIFO data register of selected endpoint.
+ //! @param ep Endpoint of which to access FIFO data register
+ //! @param scale Data scale in bits: 64, 32, 16 or 8
+ //! @param index Index of scaled data array to access
+ //! @param data 64-, 32-, 16- or 8-bit data to write
+ //! @return 64-, 32-, 16- or 8-bit data written
+ //! @warning It is up to the user of this macro to make sure that all accesses
+ //! are aligned with their natural boundaries except 64-bit accesses which
+ //! require only 32-bit alignment.
+ //! @warning It is up to the user of this macro to make sure that used HSB
+ //! addresses are identical to the DPRAM internal pointer modulo 32 bits.
+ //! @warning Do not mix calls to this macro with calls to non-indexed macros above.
+#define Usb_write_endpoint_indexed_data(ep, scale, index, data) \
+ (AVR32_USBB_FIFOX_DATA(ep, scale)[(index)] = (data))
+//! @}
+
+
+//! @defgroup USBB_general_endpoint_dma USBB endpoint DMA drivers
+//! These macros manage the common features of the endpoint DMA channels.
+//! @{
+ //! enables the disabling of HDMA requests by endpoint interrupts
+#define Usb_enable_endpoint_int_dis_hdma_req(ep) (UOTGHS->UOTGHS_DEVEPTIER[ep] = UOTGHS_DEVEPTIER_EPDISHDMAS)
+ //! disables the disabling of HDMA requests by endpoint interrupts
+#define Usb_disable_endpoint_int_dis_hdma_req(ep) (UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_EPDISHDMAC)
+ //! tests if the disabling of HDMA requests by endpoint interrupts is enabled
+#define Is_usb_endpoint_int_dis_hdma_req_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPTIMR[ep], UOTGHS_DEVEPTIMR_EPDISHDMA))
+
+ //! raises the selected endpoint DMA channel interrupt
+#define Usb_raise_endpoint_dma_interrupt(epdma) (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_DMA_1 << ((epdma) - 1))
+ //! tests if an interrupt is triggered by the selected endpoint DMA channel
+#define Is_usb_endpoint_dma_interrupt(epdma) (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_DMA_1 << ((epdma) - 1)))
+ //! enables the selected endpoint DMA channel interrupt
+#define Usb_enable_endpoint_dma_interrupt(epdma) (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_DMA_1 << ((epdma) - 1))
+ //! disables the selected endpoint DMA channel interrupt
+#define Usb_disable_endpoint_dma_interrupt(epdma) (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_DMA_1 << ((epdma) - 1))
+ //! tests if the selected endpoint DMA channel interrupt is enabled
+#define Is_usb_endpoint_dma_interrupt_enabled(epdma) (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_DMA_1 << ((epdma) - 1)))
+//! @todo Implement macros for endpoint DMA registers and descriptors
+#if 0
+#define Usb_set_endpoint_dma_nxt_desc_addr(epdma, nxt_desc_addr) (AVR32_USBB_UDDMAX_NEXTDESC(epdma).nxt_desc_addr = (U32)(nxt_desc_addr))
+#define Usb_get_endpoint_dma_nxt_desc_addr(epdma) ((avr32_usbb_uxdmax_t *)AVR32_USBB_UDDMAX_NEXTDESC(epdma).nxt_desc_addr)
+#define (epdma) (AVR32_USBB_UDDMAX_addr(epdma))
+#define (epdma) (AVR32_USBB_UDDMAX_CONTROL(epdma).ch_byte_length)
+#define (epdma) (AVR32_USBB_UDDMAX_CONTROL(epdma).burst_lock_en)
+#define (epdma) (AVR32_USBB_UDDMAX_CONTROL(epdma).desc_ld_irq_en)
+#define (epdma) (AVR32_USBB_UDDMAX_CONTROL(epdma).eobuff_irq_en)
+#define (epdma) (AVR32_USBB_UDDMAX_CONTROL(epdma).eot_irq_en)
+#define (epdma) (AVR32_USBB_UDDMAX_CONTROL(epdma).dmaend_en)
+#define (epdma) (AVR32_USBB_UDDMAX_CONTROL(epdma).buff_close_in_en)
+#define (epdma) (AVR32_USBB_UDDMAX_CONTROL(epdma).ld_nxt_ch_desc_en)
+#define (epdma) (AVR32_USBB_UDDMAX_CONTROL(epdma).ch_en)
+#define (epdma) (AVR32_USBB_UDDMAX_STATUS(epdma).ch_byte_cnt)
+#define (epdma) (AVR32_USBB_UDDMAX_STATUS(epdma).desc_ld_sta)
+#define (epdma) (AVR32_USBB_UDDMAX_STATUS(epdma).eoch_buff_sta)
+#define (epdma) (AVR32_USBB_UDDMAX_STATUS(epdma).eot_sta)
+#define (epdma) (AVR32_USBB_UDDMAX_STATUS(epdma).ch_active)
+#define (epdma) (AVR32_USBB_UDDMAX_STATUS(epdma).ch_en)
+#endif
+//! @}
+
+
+//! @defgroup USBB_host_driver USBB host controller drivers
+//! These macros manage the USBB Host controller.
+//! @{
+ //! enables SOF generation
+#define Host_enable_sof() (Set_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SOFE))
+ //! disables SOF generation
+#define Host_disable_sof() (Clr_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SOFE))
+ //! tests if SOF generation enabled
+#define Is_host_sof_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SOFE))
+ //! sends a USB Reset to the device
+#define Host_send_reset() (Set_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESET))
+ //! stops sending a USB Reset to the device
+#define Host_stop_sending_reset() (Clr_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESET))
+ //! tests if USB Reset running
+#define Is_host_sending_reset() (Tst_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESET))
+ //! sends a USB Resume to the device
+#define Host_send_resume() (Set_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESUME))
+ //! tests if USB Resume running
+#define Is_host_sending_resume() (Tst_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESUME))
+
+#ifdef AVR32_USBB_UHCON_SPDCONF
+ //! Force device full speed mode (i.e. disable high speed)
+#define Host_force_full_speed_mode() (Wr_bitfield(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SPDCONF_Msk, 3, UOTGHS_HSTCTRL_SPDCONF_Pos))
+ //! Enable hihgh speed mode
+#define Host_enable_high_speed_mode() (Wr_bitfield(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SPDCONF_Msk, 0, UOTGHS_HSTCTRL_SPDCONF_Pos))
+#endif
+
+ //! enables host Start-of-Frame interrupt
+#define Host_enable_sof_interrupt() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_HSOFIES)
+ //! enables host Start-of-Frame interrupt
+#define Host_disable_sof_interrupt() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_HSOFIEC)
+#define Is_host_sof_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_HSOFIE))
+ //! acks SOF detection
+#define Host_ack_sof() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_HSOFIC)
+ //! raises SOF detection
+#define Host_raise_sof() (UOTGHS->UOTGHS_HSTIFR = UOTGHS_HSTIFR_HSOFIS)
+ //! tests if SOF detected
+#define Is_host_sof() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_HSOFI))
+
+ //! enables host wake-up interrupt detection
+#define Host_enable_hwup_interrupt() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_HWUPIES)
+ //! disables host wake-up interrupt detection
+#define Host_disable_hwup_interrupt() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_HWUPIEC)
+#define Is_host_hwup_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_HWUPIE))
+ //! acks host wake-up detection
+#define Host_ack_hwup() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_HWUPIC)
+ //! raises host wake-up detection
+#define Host_raise_hwup() (UOTGHS->UOTGHS_HSTIFR = UOTGHS_HSTIFR_HWUPIS)
+ //! tests if host wake-up detected
+#define Is_host_hwup() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_HWUPI))
+
+ //! enables host down stream rsm sent interrupt detection
+#define Host_enable_down_stream_resume_interrupt() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_RSMEDIES)
+ //! disables host down stream rsm sent interrupt detection
+#define Host_disable_down_stream_resume_interrupt() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_RSMEDIEC)
+#define Is_host_down_stream_resume_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_RSMEDIE))
+ //! acks host down stream resume sent
+#define Host_ack_down_stream_resume() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_RSMEDIC)
+ //! raises host down stream resume sent
+#define Host_raise_down_stream_resume() (UOTGHS->UOTGHS_HSTIFR = UOTGHS_HSTIFR_RSMEDIS)
+#define Is_host_down_stream_resume() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_RSMEDI))
+
+ //! enables host remote wake-up interrupt detection
+#define Host_enable_remote_wakeup_interrupt() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_RXRSMIES)
+ //! disables host remote wake-up interrupt detection
+#define Host_disable_remote_wakeup_interrupt() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_RXRSMIEC)
+#define Is_host_remote_wakeup_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_RXRSMIE))
+ //! acks host remote wake-up detection
+#define Host_ack_remote_wakeup() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_RXRSMIC)
+ //! raises host remote wake-up detection
+#define Host_raise_remote_wakeup() (UOTGHS->UOTGHS_HSTIFR = UOTGHS_HSTIFR_RXRSMIS)
+ //! tests if host remote wake-up detected
+#define Is_host_remote_wakeup() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_RXRSMI))
+
+ //! enables host device connection interrupt
+#define Host_enable_device_connection_interrupt() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_DCONNIES)
+ //! disables USB device connection interrupt
+#define Host_disable_device_connection_interrupt() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_DCONNIEC)
+#define Is_host_device_connection_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_DCONNIE))
+ //! acks device connection
+#define Host_ack_device_connection() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_DCONNIC)
+ //! raises device connection
+#define Host_raise_device_connection() (UOTGHS->UOTGHS_HSTIFR = UOTGHS_HSTIFR_DCONNIS)
+ //! tests if a USB device has been detected
+#define Is_host_device_connection() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_DCONNI))
+
+ //! enables host device disconnection interrupt
+#define Host_enable_device_disconnection_interrupt() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_DDISCIES)
+ //! disables USB device connection interrupt
+#define Host_disable_device_disconnection_interrupt() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_DDISCIEC)
+#define Is_host_device_disconnection_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_DDISCIE))
+ //! acks device disconnection
+#define Host_ack_device_disconnection() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_DDISCIC)
+ //! raises device disconnection
+#define Host_raise_device_disconnection() (UOTGHS->UOTGHS_HSTIFR = UOTGHS_HSTIFR_DDISCIS)
+ //! tests if a USB device has been removed
+#define Is_host_device_disconnection() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_DDISCI))
+
+ //! enables host USB reset sent interrupt
+#define Host_enable_reset_sent_interrupt() (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_RSTIES)
+ //! disables host USB reset sent interrupt
+#define Host_disable_reset_sent_interrupt() (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_RSTIEC)
+#define Is_host_reset_sent_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_RSTIE))
+ //! acks host USB reset sent
+#define Host_ack_reset_sent() (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_RSTIC)
+ //! raises host USB reset sent
+#define Host_raise_reset_sent() (UOTGHS->UOTGHS_HSTIFR = UOTGHS_HSTIFR_RSTIS)
+ //! tests if host USB reset sent
+#define Is_host_reset_sent() (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_RSTI))
+
+ //! sets the current frame number
+#define Host_set_frame_number(fnum) (Wr_bitfield(UOTGHS->UOTGHS_HSTFNUM, UOTGHS_HSTFNUM_MFNUM_Msk, fnum, UOTGHS_HSTFNUM_MFNUM_Pos))
+ //! returns the current frame number
+#define Host_frame_number() (Rd_bitfield(UOTGHS->UOTGHS_HSTFNUM, UOTGHS_HSTFNUM_MFNUM_Msk, UOTGHS_HSTFNUM_MFNUM_Pos))
+ //! returns the current frame length
+#define Host_frame_length() (Rd_bitfield(UOTGHS->UOTGHS_HSTFNUM, UOTGHS_HSTFNUM_FLENHIGH_Msk, UOTGHS_HSTFNUM_FLENHIGH_Pos))
+
+ //! configures the USB device address associated with the selected pipe
+//#define Host_configure_address(p, addr) (Wr_bitfield(AVR32_USBB_uhaddrx(1 + ((p) >> 2)), AVR32_USBB_UHADDR1_UHADDR_P0_MASK << (((p) & 0x03) << 3), addr))
+//#define Host_configure_address(p, addr) (Wr_bitfield(UOTGHS->UOTGHS_HSTADDR1[1 + ((p) >> 2)], UOTGHS_HSTADDR1_HSTADDRP0_Msk << (((p) & 0x03) << 3), addr, UOTGHS_HSTADDR1_HSTADDRP0_Pos))
+ //! gets the currently configured USB device address associated with the selected pipe
+//#define Host_get_configured_address(p) (Rd_bitfield(AVR32_USBB_uhaddrx(1 + ((p) >> 2)), AVR32_USBB_UHADDR1_UHADDR_P0_MASK << (((p) & 0x03) << 3)))
+#define Host_get_configured_address(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTADDR1[1 + ((p) >> 2)], UOTGHS_HSTADDR1_HSTADDRP0_Msk << (((p) & 0x03) << 3), UOTGHS_HSTADDR1_HSTADDRP0_Pos))
+//! @}
+
+
+//! @defgroup USBB_general_pipe USBB pipe drivers
+//! These macros manage the common features of the pipes.
+//! @{
+ //! enables the selected pipe
+#define Host_enable_pipe(p) (Set_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p)))
+ //! disables the selected pipe
+#define Host_disable_pipe(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p)))
+ //! tests if the selected pipe is enabled
+#define Is_host_pipe_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p)))
+
+ //! tests if an interrupt is triggered by the selected pipe
+#define Is_host_pipe_interrupt(p) (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_PEP_0 << (p)))
+ //! enables the selected pipe interrupt
+#define Host_enable_pipe_interrupt(p) (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_PEP_0 << (p))
+ //! disables the selected pipe interrupt
+#define Host_disable_pipe_interrupt(p) (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_PEP_0 << (p))
+ //! tests if the selected pipe interrupt is enabled
+#define Is_host_pipe_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_PEP_0 << (p)))
+ //! returns the lowest pipe number generating a pipe interrupt or MAX_PEP_NB if none
+#define Host_get_interrupt_pipe_number(p) ((UOTGHS->UOTGHS_HSTISR >> 8 >> p) &\
+ (UOTGHS->UOTGHS_HSTIMR >> 8 >> p))
+
+ //! configures the interrupt pipe request frequency (period in ms) for the selected pipe
+#define Host_configure_pipe_int_req_freq(p, freq) (Wr_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_INTFRQ_Msk, freq, UOTGHS_HSTPIPCFG_INTFRQ_Pos))
+ //! gets the configured interrupt pipe request frequency (period in ms) for the selected pipe
+#define Host_get_pipe_int_req_freq(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_INTFRQ_Msk, UOTGHS_HSTPIPCFG_INTFRQ_Pos))
+ //! configures the selected pipe endpoint number
+#define Host_configure_pipe_endpoint_number(p, ep_num) (Wr_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PEPNUM_Msk, ep_num, UOTGHS_HSTPIPCFG_PEPNUM_Pos))
+ //! gets the configured selected pipe endpoint number
+#define Host_get_pipe_endpoint_number(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PEPNUM_Msk, UOTGHS_HSTPIPCFG_PEPNUM_Pos))
+ //! configures the selected pipe type
+#define Host_configure_pipe_type(p, type) (Wr_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PTYPE_Msk, type, UOTGHS_HSTPIPCFG_PTYPE_Pos))
+ //! gets the configured selected pipe type
+#define Host_get_pipe_type(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PTYPE_Msk, UOTGHS_HSTPIPCFG_PTYPE_Pos))
+ //! enables the bank autoswitch for the selected pipe
+#define Host_enable_pipe_bank_autoswitch(p) (Set_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_AUTOSW))
+ //! disables the bank autoswitch for the selected pipe
+#define Host_disable_pipe_bank_autoswitch(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_AUTOSW))
+#define Is_host_pipe_bank_autoswitch_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_AUTOSW))
+ //! configures the selected pipe token
+#define Host_configure_pipe_token(p, token) (Wr_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PTOKEN_Msk, token, UOTGHS_HSTPIPCFG_PTOKEN_Pos))
+ //! gets the configured selected pipe token
+#define Host_get_pipe_token(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PTOKEN_Msk, UOTGHS_HSTPIPCFG_PTOKEN_Pos))
+ //! Bounds given integer size to allowed range and rounds it up to the nearest
+ //! available greater size, then applies register format of USBB controller
+ //! for pipe size bit-field.
+//#define Host_format_pipe_size(size) (32 - clz(((U32)min(max(size, 8), 1024) << 1) - 1) - 1 - 3)
+#define Host_format_pipe_size(size) (size <= 8 ) ? ( 8):\
+ (size <= 16 ) ? ( 16):\
+ (size <= 32 ) ? ( 32):\
+ (size <= 64 ) ? ( 64):\
+ (size <= 128) ? (128):\
+ (size <= 256) ? (256):\
+ (size <= 512) ? (512):(1024)
+ //! configures the selected pipe size
+#define Host_configure_pipe_size(p, size) (Wr_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PSIZE_Msk, Host_format_pipe_size(size), UOTGHS_HSTPIPCFG_PSIZE_Pos))
+ //! gets the configured selected pipe size
+#define Host_get_pipe_size(p) (8U << Rd_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PSIZE_Msk, UOTGHS_HSTPIPCFG_PSIZE_Pos))
+ //! configures the selected pipe number of banks
+#define Host_configure_pipe_bank(p, bank) (Wr_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PBK_Msk, bank, UOTGHS_HSTPIPCFG_PBK_Pos))
+ //! gets the configured selected pipe number of banks
+#define Host_get_pipe_bank(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PBK_Msk, UOTGHS_HSTPIPCFG_PBK_Pos))
+ //! allocates the configuration x in DPRAM memory
+#define Host_allocate_memory(p) (Set_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_ALLOC))
+ //! un-allocates the configuration x in DPRAM memory
+#define Host_unallocate_memory(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_ALLOC))
+#define Is_host_memory_allocated(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_ALLOC))
+ //! Enable PING management for the endpoint p
+#define Host_enable_ping(p) (Set_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PINGEN))
+
+ //! configures selected pipe in one step
+#define Host_configure_pipe(p, freq, ep_num, type, token, size, bank) \
+(\
+ Host_enable_pipe(p),\
+ Clr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], 0xFFFFFFFF),\
+ Wr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_INTFRQ_Msk |\
+ UOTGHS_HSTPIPCFG_PEPNUM_Msk |\
+ UOTGHS_HSTPIPCFG_PTYPE_Msk |\
+ UOTGHS_HSTPIPCFG_PTOKEN_Msk |\
+ UOTGHS_HSTPIPCFG_PSIZE_Msk |\
+ UOTGHS_HSTPIPCFG_PBK_Msk, \
+ (UOTGHS_HSTPIPCFG_INTFRQ((U32)(freq ))) |\
+ (UOTGHS_HSTPIPCFG_PEPNUM((U32)(ep_num))) |\
+ ( (U32)(type ) << UOTGHS_HSTPIPCFG_PTYPE_Pos ) |\
+ ( (U32)(token ) << UOTGHS_HSTPIPCFG_PTOKEN_Pos) |\
+ ( (U32)Usb_format_endpoint_size(size) << UOTGHS_HSTPIPCFG_PSIZE_Pos ) |\
+ ( (U32)(bank ) << UOTGHS_HSTPIPCFG_PBK_Pos ) ),\
+ Host_allocate_memory(p),\
+\
+ Is_host_pipe_configured(p)\
+)
+
+
+//static void Host_configure_pipe(uint8_t p, uint32_t freq, uint32_t ep_num, uint32_t type, uint32_t token, uint32_t size, uint32_t bank)
+//{
+//// Host_enable_pipe(p);
+//// Wr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_INTFRQ_Msk |
+//// UOTGHS_HSTPIPCFG_PEPNUM_Msk |
+//// UOTGHS_HSTPIPCFG_PTYPE_Msk |
+//// UOTGHS_HSTPIPCFG_PTOKEN_Msk |
+//// UOTGHS_HSTPIPCFG_PSIZE_Msk |
+//// UOTGHS_HSTPIPCFG_PBK_Msk,
+//// (UOTGHS_HSTPIPCFG_INTFRQ((U32)(freq ))) |
+//// (UOTGHS_HSTPIPCFG_PEPNUM((U32)(ep_num))) |
+//// (((U32)(type ) << UOTGHS_HSTPIPCFG_PTYPE_Pos ) & UOTGHS_HSTPIPCFG_PTYPE_Msk ) |
+//// (((U32)(token ) << UOTGHS_HSTPIPCFG_PTOKEN_Pos) & UOTGHS_HSTPIPCFG_PTOKEN_Msk) |
+//// ( (U32)Host_format_pipe_size(size) << UOTGHS_HSTPIPCFG_PSIZE_Pos ) |
+//// (((U32)(bank ) << UOTGHS_HSTPIPCFG_PBK_Pos ) & UOTGHS_HSTPIPCFG_PBK_Msk ));
+//// Host_allocate_memory(p);
+//// Is_host_pipe_configured(p);
+//}
+
+ //! resets the selected pipe
+#define Host_reset_pipe(p) (Set_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PRST0 << (p)),\
+ Clr_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PRST0 << (p)))
+ //! tests if the selected pipe is being reset
+#define Is_host_resetting_pipe(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PRST0 << (p)))
+
+ //! freezes the pipe
+#define Host_freeze_pipe(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_PFREEZES)
+ //! unfreezees the pipe
+#define Host_unfreeze_pipe(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_PFREEZEC)
+ //! tests if the current pipe is frozen
+#define Is_host_pipe_frozen(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_PFREEZE))
+
+ //! resets the data toggle sequence
+#define Host_reset_data_toggle(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_RSTDTS)
+ //! tests if the data toggle sequence is being reset
+#define Is_host_data_toggle_reset(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_RSTDT))
+
+ //! acks pipe overflow interrupt
+#define Host_ack_overflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_OVERFIC)
+ //! raises pipe overflow interrupt
+#define Host_raise_overflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIFR[p] = UOTGHS_HSTPIPIFR_OVERFIS)
+ //! acks pipe underflow interrupt
+#define Host_ack_underflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_TXSTPIC)
+ //! raises pipe underflow interrupt
+#define Host_raise_underflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIFR[p] = UOTGHS_HSTPIPIFR_TXSTPIS)
+ //! tests if an overflow occurs
+#define Is_host_overflow(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_OVERFI))
+ //! tests if an underflow occurs
+#define Is_host_underflow(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_TXSTPI))
+
+ //! returns data toggle
+#define Host_data_toggle(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_DTSEQ_Msk, UOTGHS_HSTPIPISR_DTSEQ_Pos))
+ //! returns the number of busy banks
+#define Host_nb_busy_bank(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_NBUSYBK_Msk, UOTGHS_HSTPIPISR_NBUSYBK_Pos))
+ //! returns the number of the current bank
+#define Host_current_bank(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_CURRBK_Msk, UOTGHS_HSTPIPISR_CURRBK_Pos))
+ //! tests if current pipe is configured
+#define Is_host_pipe_configured(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_CFGOK))
+ //! returns the byte count
+#define Host_byte_count(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_PBYCT_Msk, UOTGHS_HSTPIPISR_PBYCT_Pos))
+
+ //! tests if a STALL has been received
+#define Is_host_stall(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_RXSTALLDI))
+ //! tests if CRC ERROR ISO IN detected
+#define Is_host_crc_error(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_RXSTALLDI))
+ //! tests if an error occurs on current pipe
+#define Is_host_pipe_error(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_PERRI))
+ //! tests if SHORT PACKET received
+#define Is_host_short_packet(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_SHORTPACKETI))
+
+ //! clears FIFOCON bit
+#define Host_ack_fifocon(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_FIFOCONC)
+
+ //! acks setup
+#define Host_ack_setup_ready() (UOTGHS->UOTGHS_HSTPIPICR[P_CONTROL] = UOTGHS_HSTPIPICR_TXSTPIC)
+ //! raises setup
+#define Host_raise_setup_ready() (UOTGHS->UOTGHS_HSTPIPIFR[P_CONTROL] = UOTGHS_HSTPIPIFR_TXSTPIS)
+ //! sends current bank for SETUP pipe
+#define Host_send_setup() (Host_ack_fifocon(P_CONTROL))
+ //! acks setup and sends current bank
+#define Host_ack_setup_ready_send() (Host_ack_setup_ready(), Host_send_setup())
+ //! acks OUT sent
+#define Host_ack_out_ready(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_TXOUTIC)
+ //! raises OUT sent
+#define Host_raise_out_ready(p) (UOTGHS->UOTGHS_HSTPIPIFR[p] = UOTGHS_HSTPIPIFR_TXOUTIS)
+ //! sends current bank for OUT pipe
+#define Host_send_out(p) (Host_ack_fifocon(p))
+ //! acks OUT sent and sends current bank
+#define Host_ack_out_ready_send(p) (Host_ack_out_ready(p), Host_send_out(p))
+
+ //! acks IN reception
+#define Host_ack_in_received(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_RXINIC)
+ //! raises IN reception
+#define Host_raise_in_received(p) (UOTGHS->UOTGHS_HSTPIPIFR[p] = UOTGHS_HSTPIPIFR_RXINIS)
+ //! frees current bank for IN pipe
+#define Host_free_in(p) (Host_ack_fifocon(p))
+ //! acks IN reception and frees current bank
+#define Host_ack_in_received_free(p) (Host_ack_in_received(p), Host_free_in(p))
+
+ //! tests if FIFOCON bit set
+#define Is_host_fifocon(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_FIFOCON))
+
+ //! tests if SETUP has been sent
+#define Is_host_setup_ready() (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[P_CONTROL], UOTGHS_HSTPIPISR_TXSTPI))
+ //! tests if current bank sent for SETUP pipe
+#define Is_host_setup_sent() (Is_host_fifocon(P_CONTROL))
+ //! tests if OUT has been sent
+#define Is_host_out_ready(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_TXOUTI))
+ //! tests if current bank sent for OUT pipe
+#define Is_host_out_sent(p) (Is_host_fifocon(p))
+
+ //! tests if IN received
+#define Is_host_in_received(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_RXINI))
+ //! tests if IN received in current bank
+#define Is_host_in_filled(p) (Is_host_fifocon(p))
+
+ //! acks STALL reception
+#define Host_ack_stall(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_RXSTALLDIC)
+ //! raises STALL reception
+#define Host_raise_stall(p) (UOTGHS->UOTGHS_HSTPIPIFR[p] = UOTGHS_HSTPIPIFR_RXSTALLDIS)
+ //! acks CRC ERROR ISO IN detected
+#define Host_ack_crc_error(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_RXSTALLDIC)
+ //! raises CRC ERROR ISO IN detected
+#define Host_raise_crc_error(p) (UOTGHS->UOTGHS_HSTPIPIFR[p] = UOTGHS_HSTPIPIFR_RXSTALLDIS)
+ //! acks pipe error
+#define Host_ack_pipe_error(p) (UOTGHS->UOTGHS_HSTPIPIFR[p] = (Is_host_pipe_error(p)) ? UOTGHS_HSTPIPIFR_PERRIS : 0)
+ //! raises pipe error
+#define Host_raise_pipe_error(p) (UOTGHS->UOTGHS_HSTPIPIFR[p] = (Is_host_pipe_error(p)) ? 0 : UOTGHS_HSTPIPIFR_PERRIS)
+ //! acks SHORT PACKET received
+#define Host_ack_short_packet(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_SHORTPACKETIC)
+ //! raises SHORT PACKET received
+#define Host_raise_short_packet(p) (UOTGHS->UOTGHS_HSTPIPIFR[p] = UOTGHS_HSTPIPIFR_SHORTPACKETIS)
+
+ //! tests if NAK handshake has been received
+#define Is_host_nak_received(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_NAKEDI))
+ //! acks NAK received
+#define Host_ack_nak_received(p) (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_NAKEDIC)
+ //! raises NAK received
+#define Host_raise_nak_received(p) (UOTGHS->UOTGHS_HSTPIPIFR[p] = UOTGHS_HSTPIPIFR_NAKEDIS)
+
+ //! tests if pipe read allowed
+#define Is_host_read_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_RWALL))
+ //! tests if pipe write allowed
+#define Is_host_write_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_RWALL))
+
+ //! enables continuous IN mode
+#define Host_enable_continuous_in_mode(p) (Set_bits(UOTGHS->UOTGHS_HSTPIPINRQ[p], UOTGHS_HSTPIPINRQ_INMODE))
+ //! disables continuous IN mode
+#define Host_disable_continuous_in_mode(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIPINRQ[p], UOTGHS_HSTPIPINRQ_INMODE))
+ //! tests if continuous IN mode is enabled
+#define Is_host_continuous_in_mode_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPINRQ[p], UOTGHS_HSTPIPINRQ_INMODE))
+
+ //! sets number of IN requests to perform before freeze
+#define Host_in_request_number(p, in_num) (Wr_bitfield(UOTGHS->UOTGHS_HSTPIPINRQ[p], UOTGHS_HSTPIPINRQ_INRQ_Msk, (in_num) - 1, UOTGHS_HSTPIPINRQ_INRQ_Pos))
+ //! returns number of remaining IN requests
+#define Host_get_in_request_number(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPINRQ[p], UOTGHS_HSTPIPINRQ_INRQ_Msk) + 1, UOTGHS_HSTPIPINRQ_INRQ_Pos)
+
+ //! acks all pipe error
+#define Host_ack_all_errors(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_DATATGL |\
+ UOTGHS_HSTPIPERR_DATAPID |\
+ UOTGHS_HSTPIPERR_PID |\
+ UOTGHS_HSTPIPERR_TIMEOUT |\
+ UOTGHS_HSTPIPERR_CRC16 |\
+ UOTGHS_HSTPIPERR_COUNTER_Msk))
+ //! tests if error occurs on pipe
+#define Host_error_status(p) (Rd_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_DATATGL |\
+ UOTGHS_HSTPIPERR_DATAPID |\
+ UOTGHS_HSTPIPERR_PID |\
+ UOTGHS_HSTPIPERR_TIMEOUT |\
+ UOTGHS_HSTPIPERR_CRC16))
+
+ //! acks bad data toggle
+#define Host_ack_bad_data_toggle(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_DATATGL))
+#define Is_host_bad_data_toggle(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_DATATGL))
+ //! acks data PID error
+#define Host_ack_data_pid_error(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_DATAPID))
+#define Is_host_data_pid_error(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_DATAPID))
+ //! acks PID error
+#define Host_ack_pid_error(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_PID))
+#define Is_host_pid_error(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_PID))
+ //! acks time-out error
+#define Host_ack_timeout_error(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_TIMEOUT))
+#define Is_host_timeout_error(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_TIMEOUT))
+ //! acks CRC16 error
+#define Host_ack_crc16_error(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_CRC16))
+#define Is_host_crc16_error(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_CRC16))
+ //! clears the error counter
+#define Host_clear_error_counter(p) (Clr_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_COUNTER_Msk))
+#define Host_get_error_counter(p) (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_COUNTER_Msk, UOTGHS_HSTPIPERR_COUNTER_Pos))
+
+ //! enables overflow interrupt
+#define Host_enable_overflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_OVERFIES)
+ //! disables overflow interrupt
+#define Host_disable_overflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_OVERFIEC)
+ //! tests if overflow interrupt is enabled
+#define Is_host_overflow_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_OVERFIE))
+
+ //! enables underflow interrupt
+#define Host_enable_underflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_TXSTPES)
+ //! disables underflow interrupt
+#define Host_disable_underflow_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_TXSTPEC)
+ //! tests if underflow interrupt is enabled
+#define Is_host_underflow_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_TXSTPE))
+
+ //! forces all banks full (OUT) or free (IN) interrupt
+#define Host_force_bank_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIFR[p] = UOTGHS_HSTPIPIFR_NBUSYBKS)
+ //! unforces all banks full (OUT) or free (IN) interrupt
+#define Host_unforce_bank_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIFR[p] = UOTGHS_HSTPIPIFR_NBUSYBKS)
+ //! enables all banks full (IN) or free (OUT) interrupt
+#define Host_enable_bank_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_NBUSYBKES)
+ //! disables all banks full (IN) or free (OUT) interrupt
+#define Host_disable_bank_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_NBUSYBKEC)
+ //! tests if all banks full (IN) or free (OUT) interrupt is enabled
+#define Is_host_bank_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_NBUSYBKE))
+
+ //! enables SHORT PACKET received interrupt
+#define Host_enable_short_packet_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_SHORTPACKETIES)
+ //! disables SHORT PACKET received interrupt
+#define Host_disable_short_packet_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_SHORTPACKETIEC)
+ //! tests if SHORT PACKET received interrupt is enabled
+#define Is_host_short_packet_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_SHORTPACKETIE))
+
+ //! enables STALL received interrupt
+#define Host_enable_stall_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_RXSTALLDES)
+ //! disables STALL received interrupt
+#define Host_disable_stall_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_RXSTALLDEC)
+ //! tests if STALL received interrupt is enabled
+#define Is_host_stall_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_RXSTALLDE))
+
+ //! enables CRC ERROR ISO IN detected interrupt
+#define Host_enable_crc_error_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_RXSTALLDES)
+ //! disables CRC ERROR ISO IN detected interrupt
+#define Host_disable_crc_error_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_RXSTALLDEC)
+ //! tests if CRC ERROR ISO IN detected interrupt is enabled
+#define Is_host_crc_error_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_RXSTALLDE))
+
+ //! enables NAK received interrupt
+#define Host_enable_nak_received_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_NAKEDES)
+ //! disables NAK received interrupt
+#define Host_disable_nak_received_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_NAKEDEC)
+ //! tests if NAK received interrupt is enabled
+#define Is_host_nak_received_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_NAKEDE))
+
+ //! enables pipe error interrupt
+#define Host_enable_pipe_error_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_PERRES)
+ //! disables pipe error interrupt
+#define Host_disable_pipe_error_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_PERREC)
+ //! tests if pipe error interrupt is enabled
+#define Is_host_pipe_error_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_PERRE))
+
+ //! enables SETUP pipe ready interrupt
+#define Host_enable_setup_ready_interrupt() (UOTGHS->UOTGHS_HSTPIPIER[P_CONTROL] = UOTGHS_HSTPIPIER_TXSTPES)
+ //! disables SETUP pipe ready interrupt
+#define Host_disable_setup_ready_interrupt() (UOTGHS->UOTGHS_HSTPIPIDR[P_CONTROL] = UOTGHS_HSTPIPIDR_TXSTPEC)
+ //! tests if SETUP pipe ready interrupt is enabled
+#define Is_host_setup_ready_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[P_CONTROL], UOTGHS_HSTPIPIMR_TXSTPE))
+
+ //! enables OUT pipe ready interrupt
+#define Host_enable_out_ready_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_TXOUTES)
+ //! disables OUT pipe ready interrupt
+#define Host_disable_out_ready_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_TXOUTEC)
+ //! tests if OUT pipe ready interrupt is enabled
+#define Is_host_out_ready_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_TXOUTE))
+
+ //! enables IN pipe reception interrupt
+#define Host_enable_in_received_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_RXINES)
+ //! disables IN pipe reception interrupt
+#define Host_disable_in_received_interrupt(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_RXINEC)
+ //! tests if IN pipe reception interrupt is enabled
+#define Is_host_in_received_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_RXINE))
+
+ //! Get 64-, 32-, 16- or 8-bit access to FIFO data register of selected pipe.
+ //! @param p Pipe of which to access FIFO data register
+ //! @param scale Data scale in bits: 64, 32, 16 or 8
+ //! @return Volatile 64-, 32-, 16- or 8-bit data pointer to FIFO data register
+ //! @warning It is up to the user of this macro to make sure that all accesses
+ //! are aligned with their natural boundaries except 64-bit accesses which
+ //! require only 32-bit alignment.
+ //! @warning It is up to the user of this macro to make sure that used HSB
+ //! addresses are identical to the DPRAM internal pointer modulo 32 bits.
+#define Host_get_pipe_fifo_access(p, scale) \
+ (AVR32_USBB_FIFOX_DATA(p, scale))
+
+ //! Reset known position inside FIFO data register of selected pipe.
+ //! @param p Pipe of which to reset known position
+ //! @warning Always call this macro before any read/write macro/function
+ //! when at FIFO beginning.
+#define Host_reset_pipe_fifo_access(p) \
+ (pep_fifo[(p)].u64ptr = Host_get_pipe_fifo_access(p, 64))
+
+ //! Read 64-, 32-, 16- or 8-bit data from FIFO data register of selected pipe.
+ //! @param p Pipe of which to access FIFO data register
+ //! @param scale Data scale in bits: 64, 32, 16 or 8
+ //! @return 64-, 32-, 16- or 8-bit data read
+ //! @warning It is up to the user of this macro to make sure that all accesses
+ //! are aligned with their natural boundaries except 64-bit accesses which
+ //! require only 32-bit alignment.
+ //! @note This macro assures that used HSB addresses are identical to the
+ //! DPRAM internal pointer modulo 32 bits.
+ //! @warning Always call Host_reset_pipe_fifo_access before this macro when
+ //! at FIFO beginning.
+ //! @warning Do not mix calls to this macro with calls to indexed macros below.
+#define Host_read_pipe_data(p, scale) \
+ (*pep_fifo[(p)].TPASTE3(u, scale, ptr)\
+ TPASTE3(Pep_fifo_access_, scale, _post_inc)())
+
+ //! Write 64-, 32-, 16- or 8-bit data to FIFO data register of selected pipe.
+ //! @param p Pipe of which to access FIFO data register
+ //! @param scale Data scale in bits: 64, 32, 16 or 8
+ //! @param data 64-, 32-, 16- or 8-bit data to write
+ //! @return 64-, 32-, 16- or 8-bit data written
+ //! @warning It is up to the user of this macro to make sure that all accesses
+ //! are aligned with their natural boundaries except 64-bit accesses which
+ //! require only 32-bit alignment.
+ //! @note This macro assures that used HSB addresses are identical to the
+ //! DPRAM internal pointer modulo 32 bits.
+ //! @warning Always call Host_reset_pipe_fifo_access before this macro when
+ //! at FIFO beginning.
+ //! @warning Do not mix calls to this macro with calls to indexed macros below.
+#define Host_write_pipe_data(p, scale, data) \
+ (*pep_fifo[(p)].TPASTE3(u, scale, ptr)\
+ TPASTE3(Pep_fifo_access_, scale, _post_inc)() = (data))
+
+ //! Read 64-, 32-, 16- or 8-bit indexed data from FIFO data register of selected pipe.
+ //! @param p Pipe of which to access FIFO data register
+ //! @param scale Data scale in bits: 64, 32, 16 or 8
+ //! @param index Index of scaled data array to access
+ //! @return 64-, 32-, 16- or 8-bit data read
+ //! @warning It is up to the user of this macro to make sure that all accesses
+ //! are aligned with their natural boundaries except 64-bit accesses which
+ //! require only 32-bit alignment.
+ //! @warning It is up to the user of this macro to make sure that used HSB
+ //! addresses are identical to the DPRAM internal pointer modulo 32 bits.
+ //! @warning Do not mix calls to this macro with calls to non-indexed macros above.
+#define Host_read_pipe_indexed_data(p, scale, index) \
+ (AVR32_USBB_FIFOX_DATA(p, scale)[(index)])
+
+ //! Write 64-, 32-, 16- or 8-bit indexed data to FIFO data register of selected pipe.
+ //! @param p Pipe of which to access FIFO data register
+ //! @param scale Data scale in bits: 64, 32, 16 or 8
+ //! @param index Index of scaled data array to access
+ //! @param data 64-, 32-, 16- or 8-bit data to write
+ //! @return 64-, 32-, 16- or 8-bit data written
+ //! @warning It is up to the user of this macro to make sure that all accesses
+ //! are aligned with their natural boundaries except 64-bit accesses which
+ //! require only 32-bit alignment.
+ //! @warning It is up to the user of this macro to make sure that used HSB
+ //! addresses are identical to the DPRAM internal pointer modulo 32 bits.
+ //! @warning Do not mix calls to this macro with calls to non-indexed macros above.
+#define Host_write_pipe_indexed_data(p, scale, index, data) \
+ (AVR32_USBB_FIFOX_DATA(p, scale)[(index)] = (data))
+//! @}
+
+
+//! @defgroup USBB_general_pipe_dma USBB pipe DMA drivers
+//! These macros manage the common features of the pipe DMA channels.
+//! @{
+ //! enables the disabling of HDMA requests by pipe interrupts
+#define Host_enable_pipe_int_dis_hdma_req(p) (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_PDISHDMAS)
+ //! disables the disabling of HDMA requests by pipe interrupts
+#define Host_disable_pipe_int_dis_hdma_req(p) (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_PDISHDMAC)
+ //! tests if the disabling of HDMA requests by pipe interrupts si enabled
+#define Is_host_pipe_int_dis_hdma_req_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_PDISHDMA))
+
+ //! raises the selected pipe DMA channel interrupt
+#define Host_raise_pipe_dma_interrupt(pdma) (UOTGHS->UOTGHS_HSTIFR = UOTGHS_HSTIFR_DMA_1 << ((pdma) - 1))
+ //! tests if an interrupt is triggered by the selected pipe DMA channel
+#define Is_host_pipe_dma_interrupt(pdma) (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_DMA_1 << ((pdma) - 1)))
+ //! enables the selected pipe DMA channel interrupt
+#define Host_enable_pipe_dma_interrupt(pdma) (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_DMA_1 << ((pdma) - 1))
+ //! disables the selected pipe DMA channel interrupt
+#define Host_disable_pipe_dma_interrupt(pdma) (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_DMA_1 << ((pdma) - 1))
+ //! tests if the selected pipe DMA channel interrupt is enabled
+#define Is_host_pipe_dma_interrupt_enabled(pdma) (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_DMA_1 << ((pdma) - 1)))
+//! @todo Implement macros for pipe DMA registers and descriptors
+//! @}
+
+//! @}
+
+
+//_____ D E C L A R A T I O N S ____________________________________________
+
+extern UnionVPtr pep_fifo[MAX_PEP_NB];
+
+#if USB_HOST_FEATURE == ENABLED
+extern void host_disable_all_pipes ( void );
+extern U32 host_set_p_txpacket (U8, U8 , U32 );
+extern U32 host_write_p_txpacket (U8, const void *, U32, const void **);
+extern U32 host_read_p_rxpacket (U8, void *, U32, void **);
+#endif
+
+extern void Host_configure_address( uint8_t pipe, uint8_t addr);
+extern void Uotghs_trace(void);
+
+#endif // _USB_DRV_H_
diff --git a/library/ADK2/utility/usb_ids.h b/library/ADK2/utility/usb_ids.h
new file mode 100644
index 0000000..19f47d4
--- /dev/null
+++ b/library/ADK2/utility/usb_ids.h
@@ -0,0 +1,457 @@
+/* This header file is part of the AVR Software Framework 2.0.0 release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file ******************************************************************
+ *
+ * \brief Contains some IDs (VID, PID, Class numbers) used in the various
+ * demos.
+ *
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices: All AVR32 devices with a USB module can be used.
+ * - AppNote:
+ *
+ * \author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ***************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _USB_IDS_H_
+#define _USB_IDS_H_
+
+
+//_____ I N C L U D E S ____________________________________________________
+
+//_____ M A C R O S ________________________________________________________
+
+//_____ D E C L A R A T I O N S ____________________________________________
+
+/*! \name Vendor ID (VID)
+ */
+//! @{
+#define ATMEL_VID 0x03EB
+#define APPLE_VID 0x05AC
+//! @}
+
+/*! \name USB Product ID (PID)
+ */
+//! @{
+#define IPOD_PID 0x1200
+#define IPOD_SHUFFLE_PID 0x1300
+#define HID_GENERIC_EXAMPLE_PID 0x2013
+#define HID_QTOUCH_DEBUG_PID 0x211F
+#define ENUM_EXAMPLE_PID 0x2300
+#define MS_EXAMPLE_PID 0x2301
+#define MS_SDRAM_LOADER_PID 0x2302
+#define EVK1100_CTRL_PANEL_DEMO_PID 0x2303
+#define HID_EXAMPLE_PID 0x2304
+#define EVK1101_CTRL_PANEL_DEMO_HID_PID 0x2305
+#define EVK1101_CTRL_PANEL_DEMO_HID_MS_PID 0x2306
+#define CDC_EXAMPLE_PID 0x2307
+#define AUDIO_MIC_EXAMPLE_PID 0x2308
+#define EVK11xx_VIRTUAL_COM_PORT_PID 0x2310
+#define AUDIO_SPEAKER_MICRO_EXAMPLE_PID 0x2311
+#define ISP_UC3A_PID 0x2FF8
+#define ISP_UC3A3_PID 0x2FF1
+#define ISP_UC3B_PID 0x2FF6
+
+//! @}
+
+#define USB_ENDPOINT_OUT 0x00
+#define USB_ENDPOINT_IN 0x80
+
+/*! \name Generic definitions (Class, subclass and protocol)
+ */
+//! @{
+#define NO_CLASS 0x00
+#define NO_SUBCLASS 0x00
+#define NO_PROTOCOL 0x00
+//! @}
+
+/*! \name Audio specific definitions (Class, subclass and protocol)
+ */
+//! @{
+#define AUDIO_CLASS 0x01
+#define AUDIOCONTROL_SUBCLASS 0x01
+#define AUDIOSTREAMING_SUBCLASS 0x02
+#define MIDISTREAMING_SUBCLASS 0x03
+//! @}
+
+/*! \name CDC specific definitions (Class, subclass and protocol)
+ */
+//! @{
+#define CDC_COMM_DEVICE_CLASS 0x02
+#define CDC_COMM_CLASS 0x02
+#define CDC_COMM_DIRECT_LINE_CM_SUBCLASS 0x01
+#define CDC_COMM_ABSTRACT_CM_SUBCLASS 0x02
+#define CDC_COMM_TELEPHONE_CM_SUBCLASS 0x03
+#define CDC_COMM_MULTICHANNEL_CM_SUBCLASS 0x04
+#define CDC_COMM_CAPI_CM_SUBCLASS 0x05
+#define CDC_COMM_ETHERNET_NETWORKING_CM_SUBCLASS 0x06
+#define CDC_COMM_ATM_NETWORKING_CM_SUBCLASS 0x07
+#define CDC_COMM_V25ter_PROTOCOL 0x01
+#define CDC_DATA_CLASS 0x0A
+#define CDC_DATA_SUBCLASS 0x00
+#define CDC_DATA_PHYS_ISDN_BRI_PROTOCOL 0x30
+#define CDC_DATA_HDLC_PROTOCOL 0x31
+#define CDC_DATA_TRANSPARENT_PROTOCOL 0x32
+//! @}
+
+/*! \name HID specific definitions (Class, subclass and protocol)
+ */
+//! @{
+#define HID_CLASS 0x03
+#define BOOT_SUBCLASS 0x01
+#define KEYBOARD_PROTOCOL 0x01
+#define MOUSE_PROTOCOL 0x02
+//! @}
+
+/*! \name MS specific definitions (Class, subclass and protocol)
+ */
+//! @{
+#define MS_CLASS 0x08
+#define SFF8020I_MMC2_SUBCLASS 0x02
+#define SFF8070I_SUBCLASS 0x05
+#define SCSI_SUBCLASS 0x06
+#define BULK_PROTOCOL 0x50
+//! @}
+
+/*! \name DFU specific definitions (Class, subclass and protocol)
+ */
+//! @{
+#define APPLICATION_CLASS 0xFE
+#define DFU_SUBCLASS 0x01
+#define RUNTIME_PROTOCOL 0x01
+#define DFU_MODE_PROTOCOL 0x02
+//! @}
+
+/*! \name Others specific definitions (Class, subclass and protocol)
+ */
+//! @{
+#define VENDOR_CLASS 0xFF
+//! @}
+
+ //! \name Requests type (bmRequestTypes)
+ //! @{
+
+ //! \name Data transfer direction
+ //! bit 7,
+ //! 0 = Host to device
+ //! 1 = Device to host
+ //! @{
+#define USB_SETUP_DIR_HOST_TO_DEVICE (0<<7)
+#define USB_SETUP_DIR_DEVICE_TO_HOST (1<<7)
+ //! @}
+
+ //! \name Type
+ //! bit 6 to 5,
+ //! 0 = Standard
+ //! 1 = Class
+ //! 2 = Vendor
+ //! 3 = Reserved
+ //! @{
+#define USB_SETUP_TYPE_STANDARD (0<<5)
+#define USB_SETUP_TYPE_CLASS (1<<5)
+#define USB_SETUP_TYPE_VENDOR (2<<5)
+ //! @}
+
+ //! \name Recipient
+ //! bit 4 to 0,
+ //! 0 = device
+ //! 1 = Interface
+ //! 2 = Endpoint
+ //! 3 = Other
+ //! 4...31 = Reserved
+ //! @{
+#define USB_SETUP_RECIPIENT_DEVICE (0)
+#define USB_SETUP_RECIPIENT_INTERFACE (1)
+#define USB_SETUP_RECIPIENT_ENDPOINT (2)
+#define USB_SETUP_RECIPIENT_OTHER (3)
+ //! @}
+
+ //! \name Request type used by standard setup request
+ //! @{
+#define USB_SETUP_SET_STAND_DEVICE (USB_SETUP_DIR_HOST_TO_DEVICE |USB_SETUP_TYPE_STANDARD |USB_SETUP_RECIPIENT_DEVICE) // 0x00
+#define USB_SETUP_GET_STAND_DEVICE (USB_SETUP_DIR_DEVICE_TO_HOST |USB_SETUP_TYPE_STANDARD |USB_SETUP_RECIPIENT_DEVICE) // 0x80
+#define USB_SETUP_SET_STAND_INTERFACE (USB_SETUP_DIR_HOST_TO_DEVICE |USB_SETUP_TYPE_STANDARD |USB_SETUP_RECIPIENT_INTERFACE) // 0x01
+#define USB_SETUP_GET_STAND_INTERFACE (USB_SETUP_DIR_DEVICE_TO_HOST |USB_SETUP_TYPE_STANDARD |USB_SETUP_RECIPIENT_INTERFACE) // 0x81
+#define USB_SETUP_SET_STAND_ENDPOINT (USB_SETUP_DIR_HOST_TO_DEVICE |USB_SETUP_TYPE_STANDARD |USB_SETUP_RECIPIENT_ENDPOINT) // 0x02
+#define USB_SETUP_GET_STAND_ENDPOINT (USB_SETUP_DIR_DEVICE_TO_HOST |USB_SETUP_TYPE_STANDARD |USB_SETUP_RECIPIENT_ENDPOINT) // 0x82
+ //! @}
+
+ //! \name Request type used by specific setup request from class driver
+ //! @{
+#define USB_SETUP_SET_CLASS_DEVICE (USB_SETUP_DIR_HOST_TO_DEVICE |USB_SETUP_TYPE_CLASS |USB_SETUP_RECIPIENT_DEVICE) // 0x20
+#define USB_SETUP_GET_CLASS_DEVICE (USB_SETUP_DIR_DEVICE_TO_HOST |USB_SETUP_TYPE_CLASS |USB_SETUP_RECIPIENT_DEVICE) // 0xA0
+#define USB_SETUP_SET_CLASS_INTER (USB_SETUP_DIR_HOST_TO_DEVICE |USB_SETUP_TYPE_CLASS |USB_SETUP_RECIPIENT_INTERFACE) // 0x21
+#define USB_SETUP_GET_CLASS_INTER (USB_SETUP_DIR_DEVICE_TO_HOST |USB_SETUP_TYPE_CLASS |USB_SETUP_RECIPIENT_INTERFACE) // 0xA1
+#define USB_SETUP_SET_CLASS_ENDPOINT (USB_SETUP_DIR_HOST_TO_DEVICE |USB_SETUP_TYPE_CLASS |USB_SETUP_RECIPIENT_ENDPOINT) // 0x22
+#define USB_SETUP_GET_CLASS_ENDPOINT (USB_SETUP_DIR_DEVICE_TO_HOST |USB_SETUP_TYPE_CLASS |USB_SETUP_RECIPIENT_ENDPOINT) // 0xA2
+#define USB_SETUP_SET_CLASS_OTHER (USB_SETUP_DIR_HOST_TO_DEVICE |USB_SETUP_TYPE_CLASS |USB_SETUP_RECIPIENT_OTHER) // 0x23
+#define USB_SETUP_GET_CLASS_OTHER (USB_SETUP_DIR_DEVICE_TO_HOST |USB_SETUP_TYPE_CLASS |USB_SETUP_RECIPIENT_OTHER) // 0xA3
+#define USB_SETUP_SET_VENDOR_DEVICE (USB_SETUP_DIR_HOST_TO_DEVICE |USB_SETUP_TYPE_VENDOR |USB_SETUP_RECIPIENT_DEVICE) // 0x40
+#define USB_SETUP_GET_VENDOR_DEVICE (USB_SETUP_DIR_DEVICE_TO_HOST |USB_SETUP_TYPE_VENDOR |USB_SETUP_RECIPIENT_DEVICE) // 0xC0
+ //! @}
+ //! @}
+
+ //! \name Standard Requests (bRequest)
+ //! @{
+#define SETUP_GET_STATUS 0x00
+#define SETUP_GET_DEVICE 0x01
+#define SETUP_CLEAR_FEATURE 0x01
+#define SETUP_GET_STRING 0x03
+#define SETUP_SET_FEATURE 0x03
+#define SETUP_SET_ADDRESS 0x05
+#define SETUP_GET_DESCRIPTOR 0x06
+#define SETUP_SET_DESCRIPTOR 0x07
+#define SETUP_GET_CONFIGURATION 0x08
+#define SETUP_SET_CONFIGURATION 0x09
+#define SETUP_GET_INTERFACE 0x0A
+#define SETUP_SET_INTERFACE 0x0B
+#define SETUP_SYNCH_FRAME 0x0C
+ //! @}
+
+ //! \name Descriptor types used in several setup requests
+ //! @{
+#define DESCRIPTOR_DEVICE 0x01
+#define DESCRIPTOR_CONFIGURATION 0x02
+#define DESCRIPTOR_STRING 0x03
+#define DESCRIPTOR_INTERFACE 0x04
+#define DESCRIPTOR_ENDPOINT 0x05
+#define DESCRIPTOR_DEVICE_QUALIFIER 0x06
+#define DESCRIPTOR_CONF_OTHER_SPEED 0x07
+#define DESCRIPTOR_OTG 0x09
+#define DESCRIPTOR_IAD 0x0B
+ //! @}
+
+ //! \name Feature types for SETUP_X_FEATURE standard request
+ //! @{
+#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01
+#define FEATURE_DEVICE_TEST 0x02
+#define FEATURE_DEVICE_OTG_B_HNP_ENABLE 0x03
+#define FEATURE_DEVICE_OTG_A_HNP_SUPPORT 0x04
+#define FEATURE_DEVICE_OTG_A_ALT_HNP_SUPPORT 0x05
+#define FEATURE_ENDPOINT_HALT 0x00
+ //! @}
+
+ //! \name Feature types for SETUP_X_FEATURE standard test request
+ //! @{
+#define FEATURE_DEVICE_TEST_J 0x01
+#define FEATURE_DEVICE_TEST_K 0x02
+#define FEATURE_DEVICE_TEST_SEO_NAK 0x03
+#define FEATURE_DEVICE_TEST_PACKET 0x04
+#define FEATURE_DEVICE_TEST_FORCE_ENABLE 0x05
+ //! @}
+//! @}
+
+#define MAX_EP_PER_INTERFACE 3
+
+//! USB Setup Data
+struct usb_setup_packet
+{
+ U8 bmRequestType; //!< Characteristics of the request
+ U8 bRequest; //!< Specific request
+ U16 wValue; //!< Field that varies according to request
+ U16 wIndex; //!< Field that varies according to request
+ U16 wLength; //!< Number of bytes to transfer if Data
+};
+
+#define CONTROL_GOOD 0x00
+#define CONTROL_DATA_TOGGLE 0x01
+#define CONTROL_DATA_PID 0x02
+#define CONTROL_PID 0x04
+#define CONTROL_TIMEOUT 0x08
+#define CONTROL_CRC16 0x10
+#define CONTROL_STALL 0x20
+#define CONTROL_NO_DEVICE 0x40
+
+//! Offsets common to all descriptor types
+#define OFFSET_DESCRIPTOR_LENGTH 0
+#define OFFSET_FIELD_DESCRIPTOR_TYPE 1
+
+//! Offsets in device descriptors
+#define OFFSET_FIELD_MAXPACKETSIZE 7
+#define OFFSET_FIELD_VID 8
+#define OFFSET_FIELD_PID 10
+#define OFFSET_FIELD_NB_CONFIGURATION 17
+
+//! Offsets in configuration descriptors
+#define OFFSET_FIELD_TOTAL_LENGTH 2
+#define OFFSET_FIELD_NB_INTERFACE 4
+#define OFFSET_FIELD_CONFIGURATION_NB 5
+#define OFFSET_FIELD_BMATTRIBUTES 7
+#define REMOTE_WAKEUP_BIT 5
+#define REMOTE_WAKEUP_MASK (1 << REMOTE_WAKEUP_BIT)
+#define SELF_POWERED_BIT 6
+#define SELF_POWERED_MASK (1 << SELF_POWERED_BIT)
+#define OFFSET_FIELD_MAXPOWER 8
+
+//! Offsets in interface descriptors
+#define OFFSET_FIELD_INTERFACE_NB 2
+#define OFFSET_FIELD_ALT 3
+#define OFFSET_FIELD_NB_OF_EP 4
+#define OFFSET_FIELD_CLASS 5
+#define OFFSET_FIELD_SUB_CLASS 6
+#define OFFSET_FIELD_PROTOCOL 7
+
+//! Offsets in endpoint descriptors
+#define OFFSET_FIELD_EP_ADDR 2
+#define OFFSET_FIELD_EP_TYPE 3
+#define OFFSET_FIELD_EP_SIZE 4
+#define OFFSET_FIELD_EP_INTERVAL 6
+
+#define host_clear_endpoint_feature(ep) \
+(\
+ usb_request.bmRequestType = 0x02,\
+ usb_request.bRequest = CLEAR_FEATURE,\
+ usb_request.wValue = FEATURE_ENDPOINT_HALT << 8,\
+ usb_request.wIndex = (ep),\
+ usb_request.wLength = 0,\
+ usb_request.incomplete_read = FALSE,\
+ host_transfer_control(data_stage)\
+)
+
+//! @brief Send a "set configuration" request
+//! @param cfg_nb U8: Configuration to activate
+//! @return Status
+#define host_set_configuration(cfg_nb) \
+(\
+ usb_request.bmRequestType = 0x00,\
+ usb_request.bRequest = SET_CONFIGURATION,\
+ usb_request.wValue = (cfg_nb),\
+ usb_request.wIndex = 0,\
+ usb_request.wLength = 0,\
+ usb_request.incomplete_read = FALSE,\
+ host_transfer_control(data_stage)\
+)
+
+//! @brief Send a "set interface" request to specify an alternate setting for an interface
+//! @param interface_nb U8: Interface
+//! @param alt_setting U8: Alternate setting
+//! @return Status
+#define host_set_interface(interface_nb, alt_setting) \
+(\
+ usb_request.bmRequestType = 0x01,\
+ usb_request.bRequest = SET_INTERFACE,\
+ usb_request.wValue = (alt_setting),\
+ usb_request.wIndex = (interface_nb),\
+ usb_request.wLength = 0,\
+ usb_request.incomplete_read = FALSE,\
+ host_transfer_control(data_stage)\
+)
+
+//! @brief Send an incomplete "get device desriptor" request
+//! The descriptor received is stored in the data_stage array.
+//! The received descriptors are limited to the length of the control pipe.
+//! @return Status
+#define host_get_device_descriptor_incomplete() \
+(\
+ usb_request.bmRequestType = 0x80,\
+ usb_request.bRequest = GET_DESCRIPTOR,\
+ usb_request.wValue = DEVICE_DESCRIPTOR << 8,\
+ usb_request.wIndex = 0,\
+ usb_request.wLength = 64,\
+ usb_request.incomplete_read = TRUE,\
+ host_transfer_control(data_stage)\
+)
+
+//! @brief Send a "get device desriptor" request
+//! The descriptor received is stored in the data_stage array.
+//! @return Status
+#define host_get_device_descriptor() \
+(\
+ usb_request.bmRequestType = 0x80,\
+ usb_request.bRequest = GET_DESCRIPTOR,\
+ usb_request.wValue = DEVICE_DESCRIPTOR << 8,\
+ usb_request.wIndex = 0,\
+ usb_request.wLength = 18,\
+ usb_request.incomplete_read = FALSE,\
+ host_transfer_control(data_stage)\
+)
+
+//! @brief Send a "get device configuration descriptor" request
+//! The configuration descriptor received is stored in the data_stage array.
+//! @param cfg_ix U8: Index of the configuration descriptor to get
+//! @return Status
+#define host_get_configuration_descriptor(cfg_ix) \
+(\
+ usb_request.bmRequestType = 0x80,\
+ usb_request.bRequest = GET_DESCRIPTOR,\
+ usb_request.wValue = CONFIGURATION_DESCRIPTOR << 8 | (cfg_ix),\
+ usb_request.wIndex = 0,\
+ usb_request.wLength = SIZEOF_DATA_STAGE,\
+ usb_request.incomplete_read = FALSE,\
+ host_transfer_control(data_stage)\
+)
+
+//! @brief Send a "set address" request
+//! @param addr U8: Address assigned to the device
+//! @return Status
+#define host_set_address(addr) \
+(\
+ usb_request.bmRequestType = 0x00,\
+ usb_request.bRequest = SET_ADDRESS,\
+ usb_request.wValue = (addr),\
+ usb_request.wIndex = 0,\
+ usb_request.wLength = 0,\
+ usb_request.incomplete_read = FALSE,\
+ host_transfer_control(data_stage)\
+)
+
+//! @brief Send a "set feature" "device remote wake-up"
+//! @return Status
+#define host_set_feature_remote_wakeup() \
+(\
+ usb_request.bmRequestType = 0x00,\
+ usb_request.bRequest = SET_FEATURE,\
+ usb_request.wValue = 1,\
+ usb_request.wIndex = 1,\
+ usb_request.wLength = 0,\
+ usb_request.incomplete_read = FALSE,\
+ host_transfer_control(data_stage)\
+)
+
+//! @brief Send the mass-storage specific request "get max LUN"
+//! @return Status
+#define host_ms_get_max_lun() \
+(\
+ usb_request.bmRequestType = 0xA1,\
+ usb_request.bRequest = MS_GET_MAX_LUN,\
+ usb_request.wValue = 0,\
+ usb_request.wIndex = 0,\
+ usb_request.wLength = 1,\
+ usb_request.incomplete_read = FALSE,\
+ host_transfer_control(data_stage)\
+)
+
+#endif // _USB_IDS_H_
diff --git a/library/ADK2/v_COPYING b/library/ADK2/v_COPYING
new file mode 100644
index 0000000..6111c6c
--- /dev/null
+++ b/library/ADK2/v_COPYING
@@ -0,0 +1,28 @@
+Copyright (c) 2002, Xiph.org Foundation
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+- Redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer.
+
+- Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in the
+documentation and/or other materials provided with the distribution.
+
+- Neither the name of the Xiph.org Foundation nor the names of its
+contributors may be used to endorse or promote products derived from
+this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION
+OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/library/ADK2/v_asm_arm.h b/library/ADK2/v_asm_arm.h
new file mode 100644
index 0000000..8ecbed3
--- /dev/null
+++ b/library/ADK2/v_asm_arm.h
@@ -0,0 +1,260 @@
+#ifdef ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2002 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: arm7 and later wide math functions
+
+ ********************************************************************/
+
+#ifdef _ARM_ASSEM_
+
+#if !defined(_V_WIDE_MATH) && !defined(_LOW_ACCURACY_)
+#define _V_WIDE_MATH
+
+static inline ogg_int32_t MULT32(ogg_int32_t x, ogg_int32_t y) {
+ int lo,hi;
+ asm volatile("smull\t%0, %1, %2, %3"
+ : "=&r"(lo),"=&r"(hi)
+ : "%r"(x),"r"(y)
+ : "cc");
+ return(hi);
+}
+
+static inline ogg_int32_t MULT31(ogg_int32_t x, ogg_int32_t y) {
+ return MULT32(x,y)<<1;
+}
+
+static inline ogg_int32_t MULT31_SHIFT15(ogg_int32_t x, ogg_int32_t y) {
+ int lo,hi;
+ asm volatile("smull %0, %1, %2, %3\n\t"
+ "movs %0, %0, lsr #15\n\t"
+ "adc %1, %0, %1, lsl #17\n\t"
+ : "=&r"(lo),"=&r"(hi)
+ : "%r"(x),"r"(y)
+ : "cc");
+ return(hi);
+}
+
+#define MB() asm volatile ("" : : : "memory")
+
+static inline void XPROD32(ogg_int32_t a, ogg_int32_t b,
+ ogg_int32_t t, ogg_int32_t v,
+ ogg_int32_t *x, ogg_int32_t *y)
+{
+ int x1, y1, l;
+ asm( "smull %0, %1, %4, %6\n\t"
+ "smlal %0, %1, %5, %7\n\t"
+ "rsb %3, %4, #0\n\t"
+ "smull %0, %2, %5, %6\n\t"
+ "smlal %0, %2, %3, %7"
+ : "=&r" (l), "=&r" (x1), "=&r" (y1), "=r" (a)
+ : "3" (a), "r" (b), "r" (t), "r" (v)
+ : "cc" );
+ *x = x1;
+ MB();
+ *y = y1;
+}
+
+static inline void XPROD31(ogg_int32_t a, ogg_int32_t b,
+ ogg_int32_t t, ogg_int32_t v,
+ ogg_int32_t *x, ogg_int32_t *y)
+{
+ int x1, y1, l;
+ asm( "smull %0, %1, %4, %6\n\t"
+ "smlal %0, %1, %5, %7\n\t"
+ "rsb %3, %4, #0\n\t"
+ "smull %0, %2, %5, %6\n\t"
+ "smlal %0, %2, %3, %7"
+ : "=&r" (l), "=&r" (x1), "=&r" (y1), "=r" (a)
+ : "3" (a), "r" (b), "r" (t), "r" (v)
+ : "cc" );
+ *x = x1 << 1;
+ MB();
+ *y = y1 << 1;
+}
+
+static inline void XNPROD31(ogg_int32_t a, ogg_int32_t b,
+ ogg_int32_t t, ogg_int32_t v,
+ ogg_int32_t *x, ogg_int32_t *y)
+{
+ int x1, y1, l;
+ asm( "rsb %2, %4, #0\n\t"
+ "smull %0, %1, %3, %5\n\t"
+ "smlal %0, %1, %2, %6\n\t"
+ "smull %0, %2, %4, %5\n\t"
+ "smlal %0, %2, %3, %6"
+ : "=&r" (l), "=&r" (x1), "=&r" (y1)
+ : "r" (a), "r" (b), "r" (t), "r" (v)
+ : "cc" );
+ *x = x1 << 1;
+ MB();
+ *y = y1 << 1;
+}
+
+#endif
+
+#ifndef _V_CLIP_MATH
+#define _V_CLIP_MATH
+
+static inline ogg_int32_t CLIP_TO_15(ogg_int32_t x) {
+ int tmp;
+ asm volatile("subs %1, %0, #32768\n\t"
+ "itt pl\n\t"
+ "movpl %0, #0x7f00\n\t"
+ "orrpl %0, %0, #0xff\n"
+ "adds %1, %0, #32768\n\t"
+ "it mi\n\t"
+ "movmi %0, #0x8000"
+ : "+r"(x),"=r"(tmp)
+ :
+ : "cc");
+ return(x);
+}
+
+#endif
+
+#ifndef _V_LSP_MATH_ASM
+#define _V_LSP_MATH_ASM
+
+static inline void lsp_loop_asm(ogg_uint32_t *qip,ogg_uint32_t *pip,
+ ogg_int32_t *qexpp,
+ ogg_int32_t *ilsp,ogg_int32_t wi,
+ ogg_int32_t m){
+
+ ogg_uint32_t qi=*qip,pi=*pip;
+ ogg_int32_t qexp=*qexpp;
+
+ asm("mov r0,%3;"
+ "mov r1,%5,asr#1;"
+ "add r0,r0,r1,lsl#3;"
+ "1:"
+
+ "ldmdb r0!,{r1,r3};"
+ "subs r1,r1,%4;" //ilsp[j]-wi
+ "it mi;"
+ "rsbmi r1,r1,#0;" //labs(ilsp[j]-wi)
+ "umull %0,r2,r1,%0;" //qi*=labs(ilsp[j]-wi)
+
+ "subs r1,r3,%4;" //ilsp[j+1]-wi
+ "it mi;"
+ "rsbmi r1,r1,#0;" //labs(ilsp[j+1]-wi)
+ "umull %1,r3,r1,%1;" //pi*=labs(ilsp[j+1]-wi)
+
+ "cmn r2,r3;" // shift down 16?
+ "beq 0f;"
+ "add %2,%2,#16;"
+ "mov %0,%0,lsr #16;"
+ "orr %0,%0,r2,lsl #16;"
+ "mov %1,%1,lsr #16;"
+ "orr %1,%1,r3,lsl #16;"
+ "0:"
+ "cmp r0,%3;\n"
+ "bhi 1b;\n"
+
+ // odd filter assymetry
+ "ands r0,%5,#1;\n"
+ "beq 2f;\n"
+ "add r0,%3,%5,lsl#2;\n"
+
+ "ldr r1,[r0,#-4];\n"
+ "mov r0,#0x4000;\n"
+
+ "subs r1,r1,%4;\n" //ilsp[j]-wi
+ "it mi;"
+ "rsbmi r1,r1,#0;\n" //labs(ilsp[j]-wi)
+ "umull %0,r2,r1,%0;\n" //qi*=labs(ilsp[j]-wi)
+ "umull %1,r3,r0,%1;\n" //pi*=labs(ilsp[j+1]-wi)
+
+ "cmn r2,r3;\n" // shift down 16?
+ "beq 2f;\n"
+ "add %2,%2,#16;\n"
+ "mov %0,%0,lsr #16;\n"
+ "orr %0,%0,r2,lsl #16;\n"
+ "mov %1,%1,lsr #16;\n"
+ "orr %1,%1,r3,lsl #16;\n"
+
+ //qi=(pi>>shift)*labs(ilsp[j]-wi);
+ //pi=(qi>>shift)*labs(ilsp[j+1]-wi);
+ //qexp+=shift;
+
+ //}
+
+ /* normalize to max 16 sig figs */
+ "2:"
+ "mov r2,#0;"
+ "orr r1,%0,%1;"
+ "tst r1,#0xff000000;"
+ "itt ne;"
+ "addne r2,r2,#8;"
+ "movne r1,r1,lsr #8;"
+ "tst r1,#0x00f00000;"
+ "itt ne;"
+ "addne r2,r2,#4;"
+ "movne r1,r1,lsr #4;"
+ "tst r1,#0x000c0000;"
+ "itt ne;"
+ "addne r2,r2,#2;"
+ "movne r1,r1,lsr #2;"
+ "tst r1,#0x00020000;"
+ "itt ne;"
+ "addne r2,r2,#1;"
+ "movne r1,r1,lsr #1;"
+ "tst r1,#0x00010000;"
+ "it ne;"
+ "addne r2,r2,#1;"
+ "mov %0,%0,lsr r2;"
+ "mov %1,%1,lsr r2;"
+ "add %2,%2,r2;"
+
+ : "+r"(qi),"+r"(pi),"+r"(qexp)
+ : "r"(ilsp),"r"(wi),"r"(m)
+ : "r0","r1","r2","r3","cc");
+
+ *qip=qi;
+ *pip=pi;
+ *qexpp=qexp;
+}
+
+static inline void lsp_norm_asm(ogg_uint32_t *qip,ogg_int32_t *qexpp){
+
+ ogg_uint32_t qi=*qip;
+ ogg_int32_t qexp=*qexpp;
+
+ asm("tst %0,#0x0000ff00;"
+ "itt eq;"
+ "moveq %0,%0,lsl #8;"
+ "subeq %1,%1,#8;"
+ "tst %0,#0x0000f000;"
+ "itt eq;"
+ "moveq %0,%0,lsl #4;"
+ "subeq %1,%1,#4;"
+ "tst %0,#0x0000c000;"
+ "itt eq;"
+ "moveq %0,%0,lsl #2;"
+ "subeq %1,%1,#2;"
+ "tst %0,#0x00008000;"
+ "itt eq;"
+ "moveq %0,%0,lsl #1;"
+ "subeq %1,%1,#1;"
+ : "+r"(qi),"+r"(qexp)
+ :
+ : "cc");
+ *qip=qi;
+ *qexpp=qexp;
+}
+
+#endif
+#endif
+
+#endif
+
diff --git a/library/ADK2/v_bitwise.c b/library/ADK2/v_bitwise.c
new file mode 100644
index 0000000..328eebe
--- /dev/null
+++ b/library/ADK2/v_bitwise.c
@@ -0,0 +1,676 @@
+#define ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: packing variable sized words into an octet stream
+
+ ********************************************************************/
+
+/* We're 'LSb' endian; if we write a word but read individual bits,
+ then we'll read the lsb first */
+
+#include <string.h>
+#include <stdlib.h>
+#include "v_misc.h"
+#include "v_ogg.h"
+
+static unsigned long mask[]=
+{0x00000000,0x00000001,0x00000003,0x00000007,0x0000000f,
+ 0x0000001f,0x0000003f,0x0000007f,0x000000ff,0x000001ff,
+ 0x000003ff,0x000007ff,0x00000fff,0x00001fff,0x00003fff,
+ 0x00007fff,0x0000ffff,0x0001ffff,0x0003ffff,0x0007ffff,
+ 0x000fffff,0x001fffff,0x003fffff,0x007fffff,0x00ffffff,
+ 0x01ffffff,0x03ffffff,0x07ffffff,0x0fffffff,0x1fffffff,
+ 0x3fffffff,0x7fffffff,0xffffffff };
+
+/* spans forward, skipping as many bytes as headend is negative; if
+ headend is zero, simply finds next byte. If we're up to the end
+ of the buffer, leaves headend at zero. If we've read past the end,
+ halt the decode process. */
+
+static void _span(oggpack_buffer *b){
+ while(b->headend-(b->headbit>>3)<1){
+ b->headend-=b->headbit>>3;
+ b->headbit&=0x7;
+
+ if(b->head->next){
+ b->count+=b->head->length;
+ b->head=b->head->next;
+
+ if(b->headend+b->head->length>0)
+ b->headptr=b->head->buffer->data+b->head->begin-b->headend;
+
+ b->headend+=b->head->length;
+ }else{
+ /* we've either met the end of decode, or gone past it. halt
+ only if we're past */
+ if(b->headend*8<b->headbit)
+ /* read has fallen off the end */
+ b->headend=-1;
+ break;
+ }
+ }
+}
+
+void oggpack_readinit(oggpack_buffer *b,ogg_reference *r){
+ memset(b,0,sizeof(*b));
+
+ b->tail=b->head=r;
+ b->count=0;
+ b->headptr=b->head->buffer->data+b->head->begin;
+ b->headend=b->head->length;
+ _span(b);
+}
+
+#define _lookspan() while(!end){\
+ head=head->next;\
+ if(!head) return -1;\
+ ptr=head->buffer->data + head->begin;\
+ end=head->length;\
+ }
+
+/* Read in bits without advancing the bitptr; bits <= 32 */
+long oggpack_look(oggpack_buffer *b,int bits){
+ unsigned long m=mask[bits];
+ unsigned long ret;
+
+ bits+=b->headbit;
+
+ if(bits >= b->headend<<3){
+ int end=b->headend;
+ unsigned char *ptr=b->headptr;
+ ogg_reference *head=b->head;
+
+ if(end<0)return -1;
+
+ if(bits){
+ _lookspan();
+ ret=*ptr++>>b->headbit;
+ if(bits>8){
+ --end;
+ _lookspan();
+ ret|=*ptr++<<(8-b->headbit);
+ if(bits>16){
+ --end;
+ _lookspan();
+ ret|=*ptr++<<(16-b->headbit);
+ if(bits>24){
+ --end;
+ _lookspan();
+ ret|=*ptr++<<(24-b->headbit);
+ if(bits>32 && b->headbit){
+ --end;
+ _lookspan();
+ ret|=*ptr<<(32-b->headbit);
+ }
+ }
+ }
+ }
+ }
+
+ }else{
+
+ /* make this a switch jump-table */
+ ret=b->headptr[0]>>b->headbit;
+ if(bits>8){
+ ret|=b->headptr[1]<<(8-b->headbit);
+ if(bits>16){
+ ret|=b->headptr[2]<<(16-b->headbit);
+ if(bits>24){
+ ret|=b->headptr[3]<<(24-b->headbit);
+ if(bits>32 && b->headbit)
+ ret|=b->headptr[4]<<(32-b->headbit);
+ }
+ }
+ }
+ }
+
+ ret&=m;
+ return ret;
+}
+
+/* limited to 32 at a time */
+void oggpack_adv(oggpack_buffer *b,int bits){
+ bits+=b->headbit;
+ b->headbit=bits&7;
+ b->headend-=(bits>>3);
+ b->headptr+=(bits>>3);
+ if(b->headend<1)_span(b);
+}
+
+int oggpack_eop(oggpack_buffer *b){
+ if(b->headend<0)return -1;
+ return 0;
+}
+
+/* bits <= 32 */
+long oggpack_read(oggpack_buffer *b,int bits){
+ long ret=oggpack_look(b,bits);
+ oggpack_adv(b,bits);
+ return(ret);
+}
+
+long oggpack_bytes(oggpack_buffer *b){
+ if(b->headend<0)return b->count+b->head->length;
+ return b->count + b->head->length-b->headend +
+ (b->headbit+7)/8;
+}
+
+long oggpack_bits(oggpack_buffer *b){
+ if(b->headend<0)return (b->count+b->head->length)*8;
+ return (b->count + b->head->length-b->headend)*8 +
+ b->headbit;
+}
+
+/* Self test of the bitwise routines; everything else is based on
+ them, so they damned well better be solid. */
+
+#ifdef _V_BIT_TEST
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include "vobis_framing.c"
+
+static int ilog(unsigned long v){
+ int ret=0;
+ while(v){
+ ret++;
+ v>>=1;
+ }
+ return(ret);
+}
+
+oggpack_buffer r;
+oggpack_buffer o;
+ogg_buffer_state *bs;
+ogg_reference *or;
+#define TESTWORDS 256
+
+void report(char *in){
+ fprintf(stderr,"%s",in);
+ exit(1);
+}
+
+int getbyte(ogg_reference *or,int position){
+ while(or && position>=or->length){
+ position-=or->length;
+ or=or->next;
+ if(or==NULL){
+ fprintf(stderr,"\n\tERROR: getbyte ran off end of buffer.\n");
+ exit(1);
+ }
+ }
+
+ if((position+or->begin)&1)
+ return (or->buffer->data[(position+or->begin)>>1])&0xff;
+ else
+ return (or->buffer->data[(position+or->begin)>>1]>>8)&0xff;
+}
+
+void cliptest(unsigned long *b,int vals,int bits,int *comp,int compsize){
+ long i,bitcount=0;
+ ogg_reference *or=ogg_buffer_alloc(bs,64);
+ for(i=0;i<compsize;i++)
+ or->buffer->data[i]= comp[i];
+ or->length=i;
+
+ oggpack_readinit(&r,or);
+ for(i=0;i<vals;i++){
+ unsigned long test;
+ int tbit=bits?bits:ilog(b[i]);
+ if((test=oggpack_look(&r,tbit))==0xffffffff)
+ report("out of data!\n");
+ if(test!=(b[i]&mask[tbit])){
+ fprintf(stderr,"%ld) %lx %lx\n",i,(b[i]&mask[tbit]),test);
+ report("looked at incorrect value!\n");
+ }
+ if((test=oggpack_read(&r,tbit))==0xffffffff){
+ report("premature end of data when reading!\n");
+ }
+ if(test!=(b[i]&mask[tbit])){
+ fprintf(stderr,"%ld) %lx %lx\n",i,(b[i]&mask[tbit]),test);
+ report("read incorrect value!\n");
+ }
+ bitcount+=tbit;
+
+ if(bitcount!=oggpack_bits(&r))
+ report("wrong number of bits while reading!\n");
+ if((bitcount+7)/8!=oggpack_bytes(&r))
+ report("wrong number of bytes while reading!\n");
+
+ }
+ if(oggpack_bytes(&r)!=(bitcount+7)/8)report("leftover bytes after read!\n");
+ ogg_buffer_release(or);
+}
+
+void _end_verify(int count){
+ int i;
+
+ /* are the proper number of bits left over? */
+ int leftover=count*8-oggpack_bits(&o);
+ if(leftover>7)
+ report("\nERROR: too many bits reported left over.\n");
+
+ /* does reading to exactly byte alignment *not* trip EOF? */
+ if(oggpack_read(&o,leftover)==-1)
+ report("\nERROR: read to but not past exact end tripped EOF.\n");
+ if(oggpack_bits(&o)!=count*8)
+ report("\nERROR: read to but not past exact end reported bad bitcount.\n");
+
+ /* does EOF trip properly after a single additional bit? */
+ if(oggpack_read(&o,1)!=-1)
+ report("\nERROR: read past exact end did not trip EOF.\n");
+ if(oggpack_bits(&o)!=count*8)
+ report("\nERROR: read past exact end reported bad bitcount.\n");
+
+ /* does EOF stay set over additional bit reads? */
+ for(i=0;i<=32;i++){
+ if(oggpack_read(&o,i)!=-1)
+ report("\nERROR: EOF did not stay set on stream.\n");
+ if(oggpack_bits(&o)!=count*8)
+ report("\nERROR: read past exact end reported bad bitcount.\n");
+ }
+}
+
+void _end_verify2(int count){
+ int i;
+
+ /* are the proper number of bits left over? */
+ int leftover=count*8-oggpack_bits(&o);
+ if(leftover>7)
+ report("\nERROR: too many bits reported left over.\n");
+
+ /* does reading to exactly byte alignment *not* trip EOF? */
+ oggpack_adv(&o,leftover);
+ if(o.headend!=0)
+ report("\nERROR: read to but not past exact end tripped EOF.\n");
+ if(oggpack_bits(&o)!=count*8)
+ report("\nERROR: read to but not past exact end reported bad bitcount.\n");
+
+ /* does EOF trip properly after a single additional bit? */
+ oggpack_adv(&o,1);
+ if(o.headend>=0)
+ report("\nERROR: read past exact end did not trip EOF.\n");
+ if(oggpack_bits(&o)!=count*8)
+ report("\nERROR: read past exact end reported bad bitcount.\n");
+
+ /* does EOF stay set over additional bit reads? */
+ for(i=0;i<=32;i++){
+ oggpack_adv(&o,i);
+ if(o.headend>=0)
+ report("\nERROR: EOF did not stay set on stream.\n");
+ if(oggpack_bits(&o)!=count*8)
+ report("\nERROR: read past exact end reported bad bitcount.\n");
+ }
+}
+
+long ogg_buffer_length(ogg_reference *or){
+ int count=0;
+ while(or){
+ count+=or->length;
+ or=or->next;
+ }
+ return count;
+}
+
+ogg_reference *ogg_buffer_extend(ogg_reference *or,long bytes){
+ if(or){
+ while(or->next){
+ or=or->next;
+ }
+ or->next=ogg_buffer_alloc(or->buffer->ptr.owner,bytes);
+ return(or->next);
+ }
+ return 0;
+}
+
+void ogg_buffer_posttruncate(ogg_reference *or,long pos){
+ /* walk to the point where we want to begin truncate */
+ while(or && pos>or->length){
+ pos-=or->length;
+ or=or->next;
+ }
+ if(or){
+ ogg_buffer_release(or->next);
+ or->next=0;
+ or->length=pos;
+ }
+}
+
+int main(void){
+ long i;
+ static unsigned long testbuffer1[]=
+ {18,12,103948,4325,543,76,432,52,3,65,4,56,32,42,34,21,1,23,32,546,456,7,
+ 567,56,8,8,55,3,52,342,341,4,265,7,67,86,2199,21,7,1,5,1,4};
+ int test1size=43;
+
+ static unsigned long testbuffer2[]=
+ {216531625L,1237861823,56732452,131,3212421,12325343,34547562,12313212,
+ 1233432,534,5,346435231,14436467,7869299,76326614,167548585,
+ 85525151,0,12321,1,349528352};
+ int test2size=21;
+
+ static unsigned long testbuffer3[]=
+ {1,0,14,0,1,0,12,0,1,0,0,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,0,1,1,1,1,1,0,0,1,
+ 0,1,30,1,1,1,0,0,1,0,0,0,12,0,11,0,1,0,0,1};
+ int test3size=56;
+
+ static unsigned long large[]=
+ {2136531625L,2137861823,56732452,131,3212421,12325343,34547562,12313212,
+ 1233432,534,5,2146435231,14436467,7869299,76326614,167548585,
+ 85525151,0,12321,1,2146528352};
+
+ int onesize=33;
+ static int one[33]={146,25,44,151,195,15,153,176,233,131,196,65,85,172,47,40,
+ 34,242,223,136,35,222,211,86,171,50,225,135,214,75,172,
+ 223,4};
+
+ int twosize=6;
+ static int two[6]={61,255,255,251,231,29};
+
+ int threesize=54;
+ static int three[54]={169,2,232,252,91,132,156,36,89,13,123,176,144,32,254,
+ 142,224,85,59,121,144,79,124,23,67,90,90,216,79,23,83,
+ 58,135,196,61,55,129,183,54,101,100,170,37,127,126,10,
+ 100,52,4,14,18,86,77,1};
+
+ int foursize=38;
+ static int four[38]={18,6,163,252,97,194,104,131,32,1,7,82,137,42,129,11,72,
+ 132,60,220,112,8,196,109,64,179,86,9,137,195,208,122,169,
+ 28,2,133,0,1};
+
+ int fivesize=45;
+ static int five[45]={169,2,126,139,144,172,30,4,80,72,240,59,130,218,73,62,
+ 241,24,210,44,4,20,0,248,116,49,135,100,110,130,181,169,
+ 84,75,159,2,1,0,132,192,8,0,0,18,22};
+
+ int sixsize=7;
+ static int six[7]={17,177,170,242,169,19,148};
+
+ /* Test read/write together */
+ /* Later we test against pregenerated bitstreams */
+ bs=ogg_buffer_create();
+
+ fprintf(stderr,"\nSmall preclipped packing (LSb): ");
+ cliptest(testbuffer1,test1size,0,one,onesize);
+ fprintf(stderr,"ok.");
+
+ fprintf(stderr,"\nNull bit call (LSb): ");
+ cliptest(testbuffer3,test3size,0,two,twosize);
+ fprintf(stderr,"ok.");
+
+ fprintf(stderr,"\nLarge preclipped packing (LSb): ");
+ cliptest(testbuffer2,test2size,0,three,threesize);
+ fprintf(stderr,"ok.");
+
+ fprintf(stderr,"\n32 bit preclipped packing (LSb): ");
+
+ or=ogg_buffer_alloc(bs,128);
+ for(i=0;i<test2size;i++){
+ or->buffer->data[i*4] = large[i]&0xff;
+ or->buffer->data[i*4+1] = (large[i]>>8)&0xff;
+ or->buffer->data[i*4+2] = (large[i]>>16)&0xff;
+ or->buffer->data[i*4+3] = (large[i]>>24)&0xff;
+ }
+ or->length=test2size*4;
+ oggpack_readinit(&r,or);
+ for(i=0;i<test2size;i++){
+ unsigned long test;
+ if((test=oggpack_look(&r,32))==0xffffffffUL)report("out of data. failed!");
+ if(test!=large[i]){
+ fprintf(stderr,"%ld != %ld (%lx!=%lx):",test,large[i],
+ test,large[i]);
+ report("read incorrect value!\n");
+ }
+ oggpack_adv(&r,32);
+ }
+ ogg_buffer_release(or);
+ if(oggpack_bytes(&r)!=test2size*4)report("leftover bytes after read!\n");
+ fprintf(stderr,"ok.");
+
+ fprintf(stderr,"\nSmall unclipped packing (LSb): ");
+ cliptest(testbuffer1,test1size,7,four,foursize);
+ fprintf(stderr,"ok.");
+
+ fprintf(stderr,"\nLarge unclipped packing (LSb): ");
+ cliptest(testbuffer2,test2size,17,five,fivesize);
+ fprintf(stderr,"ok.");
+
+ fprintf(stderr,"\nSingle bit unclipped packing (LSb): ");
+ cliptest(testbuffer3,test3size,1,six,sixsize);
+ fprintf(stderr,"ok.");
+
+ fprintf(stderr,"\nTesting read past end (LSb): ");
+ {
+ unsigned char dda[]={0,0,0,0};
+ ogg_buffer lob={dda,8,0,{0}};
+ ogg_reference lor={&lob,0,8,0};
+
+ oggpack_readinit(&r,&lor);
+ for(i=0;i<64;i++){
+ if(oggpack_read(&r,1)<0){
+ fprintf(stderr,"failed; got -1 prematurely.\n");
+ exit(1);
+ }
+ }
+ if(oggpack_look(&r,1)!=-1 ||
+ oggpack_read(&r,1)!=-1){
+ fprintf(stderr,"failed; read past end without -1.\n");
+ exit(1);
+ }
+ }
+ {
+ unsigned char dda[]={0,0,0,0};
+ ogg_buffer lob={dda,8,0,{0}};
+ ogg_reference lor={&lob,0,8,0};
+ unsigned long test;
+
+ oggpack_readinit(&r,&lor);
+ if((test=oggpack_read(&r,30))==0xffffffffUL ||
+ (test=oggpack_read(&r,16))==0xffffffffUL){
+ fprintf(stderr,"failed 2; got -1 prematurely.\n");
+ exit(1);
+ }
+
+ if((test=oggpack_look(&r,18))==0xffffffffUL){
+ fprintf(stderr,"failed 3; got -1 prematurely.\n");
+ exit(1);
+ }
+ if((test=oggpack_look(&r,19))!=0xffffffffUL){
+ fprintf(stderr,"failed; read past end without -1.\n");
+ exit(1);
+ }
+ if((test=oggpack_look(&r,32))!=0xffffffffUL){
+ fprintf(stderr,"failed; read past end without -1.\n");
+ exit(1);
+ }
+ }
+ fprintf(stderr,"ok.\n");
+
+ /* now the scary shit: randomized testing */
+
+ for(i=0;i<10000;i++){
+ long j,count=0,count2=0,bitcount=0;
+ unsigned long values[TESTWORDS];
+ int len[TESTWORDS];
+ unsigned char flat[4*TESTWORDS]; /* max possible needed size */
+
+ memset(flat,0,sizeof(flat));
+ fprintf(stderr,"\rRandomized testing (LSb)... (%ld) ",10000-i);
+
+ /* generate a list of words and lengths */
+ /* write the required number of bits out to packbuffer */
+ {
+ long word=0;
+ long bit=0;
+ int k;
+
+ for(j=0;j<TESTWORDS;j++){
+ values[j]=rand();
+ len[j]=(rand()%33);
+
+ for(k=0;k<len[j];k++){
+ flat[word] |= ((values[j]>>k)&0x1)<<bit;
+ bit++;
+ bitcount++;
+ if(bit>7){
+ bit=0;
+ word++;
+ }
+ }
+ }
+ }
+ count2=(bitcount+7)>>3;
+
+ /* construct random-length buffer chain from flat vector; random
+ byte starting offset within the length of the vector */
+ {
+ ogg_reference *or=NULL,*orl=NULL;
+ long pos=0;
+
+ /* build buffer chain */
+ while(count2){
+ int ilen=(rand()%32),k;
+ int ibegin=(rand()%32);
+
+
+ if(ilen>count2)ilen=count2;
+
+ if(or)
+ orl=ogg_buffer_extend(orl,64);
+ else
+ or=orl=ogg_buffer_alloc(bs,64);
+
+ orl->length=ilen;
+ orl->begin=ibegin;
+
+ for(k=0;k<ilen;k++)
+ orl->buffer->data[ibegin++]= flat[pos++];
+
+ count2-=ilen;
+ }
+
+ if(ogg_buffer_length(or)!=(bitcount+7)/8){
+ fprintf(stderr,"\nERROR: buffer length incorrect after build.\n");
+ exit(1);
+ }
+
+
+ {
+ int begin=0; //=(rand()%TESTWORDS);
+ int ilen=(rand()%(TESTWORDS-begin));
+ int bitoffset,bitcount=0;
+ unsigned long temp;
+
+ for(j=0;j<begin;j++)
+ bitcount+=len[j];
+ or=ogg_buffer_pretruncate(or,bitcount/8);
+ bitoffset=bitcount%=8;
+ for(;j<begin+ilen;j++)
+ bitcount+=len[j];
+ ogg_buffer_posttruncate(or,((bitcount+7)/8));
+
+ if((count=ogg_buffer_length(or))!=(bitcount+7)/8){
+ fprintf(stderr,"\nERROR: buffer length incorrect after truncate.\n");
+ exit(1);
+ }
+
+ oggpack_readinit(&o,or);
+
+ /* verify bit count */
+ if(oggpack_bits(&o)!=0){
+ fprintf(stderr,"\nERROR: Read bitcounter not zero!\n");
+ exit(1);
+ }
+ if(oggpack_bytes(&o)!=0){
+ fprintf(stderr,"\nERROR: Read bytecounter not zero!\n");
+ exit(1);
+ }
+
+ bitcount=bitoffset;
+ oggpack_read(&o,bitoffset);
+
+ /* read and compare to original list */
+ for(j=begin;j<begin+ilen;j++){
+ temp=oggpack_read(&o,len[j]);
+ if(temp==0xffffffffUL){
+ fprintf(stderr,"\nERROR: End of stream too soon! word: %ld,%d\n",
+ j-begin,ilen);
+ exit(1);
+ }
+ if(temp!=(values[j]&mask[len[j]])){
+ fprintf(stderr,"\nERROR: Incorrect read %lx != %lx, word %ld, len %d\n"
+,
+ values[j]&mask[len[j]],temp,j-begin,len[j]);
+ exit(1);
+ }
+ bitcount+=len[j];
+ if(oggpack_bits(&o)!=bitcount){
+ fprintf(stderr,"\nERROR: Read bitcounter %d != %ld!\n",
+ bitcount,oggpack_bits(&o));
+ exit(1);
+ }
+ if(oggpack_bytes(&o)!=(bitcount+7)/8){
+ fprintf(stderr,"\nERROR: Read bytecounter %d != %ld!\n",
+ (bitcount+7)/8,oggpack_bytes(&o));
+ exit(1);
+ }
+
+ }
+ _end_verify(count);
+
+ /* look/adv version */
+ oggpack_readinit(&o,or);
+ bitcount=bitoffset;
+ oggpack_adv(&o,bitoffset);
+
+ /* read and compare to original list */
+ for(j=begin;j<begin+ilen;j++){
+ temp=oggpack_look(&o,len[j]);
+
+ if(temp==0xffffffffUL){
+ fprintf(stderr,"\nERROR: End of stream too soon! word: %ld\n",
+ j-begin);
+ exit(1);
+ }
+ if(temp!=(values[j]&mask[len[j]])){
+ fprintf(stderr,"\nERROR: Incorrect look %lx != %lx, word %ld, len %d\n"
+,
+ values[j]&mask[len[j]],temp,j-begin,len[j]);
+ exit(1);
+ }
+ oggpack_adv(&o,len[j]);
+ bitcount+=len[j];
+ if(oggpack_bits(&o)!=bitcount){
+ fprintf(stderr,"\nERROR: Look/Adv bitcounter %d != %ld!\n",
+ bitcount,oggpack_bits(&o));
+ exit(1);
+ }
+ if(oggpack_bytes(&o)!=(bitcount+7)/8){
+ fprintf(stderr,"\nERROR: Look/Adv bytecounter %d != %ld!\n",
+ (bitcount+7)/8,oggpack_bytes(&o));
+ exit(1);
+ }
+
+ }
+ _end_verify2(count);
+
+ }
+ ogg_buffer_release(or);
+ }
+ }
+ fprintf(stderr,"\rRandomized testing (LSb)... ok. \n");
+
+ return(0);
+}
+#endif
diff --git a/library/ADK2/v_codebook.c b/library/ADK2/v_codebook.c
new file mode 100644
index 0000000..176efab
--- /dev/null
+++ b/library/ADK2/v_codebook.c
@@ -0,0 +1,792 @@
+#define ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2002 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: basic codebook pack/unpack/code/decode operations
+
+ ********************************************************************/
+
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+#include "v_ogg.h"
+#include "v_ivorbiscodec.h"
+#include "v_codebook.h"
+#include "v_misc.h"
+#include "v_os.h"
+
+
+/**** pack/unpack helpers ******************************************/
+int _ilog(unsigned int v){
+ int ret=0;
+ while(v){
+ ret++;
+ v>>=1;
+ }
+ return(ret);
+}
+
+static ogg_uint32_t decpack(long entry,long used_entry,long quantvals,
+ codebook *b,oggpack_buffer *opb,int maptype){
+ ogg_uint32_t ret=0;
+ int j;
+
+ switch(b->dec_type){
+
+ case 0:
+ return (ogg_uint32_t)entry;
+
+ case 1:
+ if(maptype==1){
+ /* vals are already read into temporary column vector here */
+ for(j=0;j<b->dim;j++){
+ ogg_uint32_t off=entry%quantvals;
+ entry/=quantvals;
+ ret|=((ogg_uint16_t *)(b->q_val))[off]<<(b->q_bits*j);
+ }
+ }else{
+ for(j=0;j<b->dim;j++)
+ ret|=oggpack_read(opb,b->q_bits)<<(b->q_bits*j);
+ }
+ return ret;
+
+ case 2:
+ for(j=0;j<b->dim;j++){
+ ogg_uint32_t off=entry%quantvals;
+ entry/=quantvals;
+ ret|=off<<(b->q_pack*j);
+ }
+ return ret;
+
+ case 3:
+ return (ogg_uint32_t)used_entry;
+
+ }
+ return 0; /* silence compiler */
+}
+
+/* 32 bit float (not IEEE; nonnormalized mantissa +
+ biased exponent) : neeeeeee eeemmmmm mmmmmmmm mmmmmmmm
+ Why not IEEE? It's just not that important here. */
+
+static ogg_int32_t _float32_unpack(long val,int *point){
+ long mant=val&0x1fffff;
+ int sign=val&0x80000000;
+
+ *point=((val&0x7fe00000L)>>21)-788;
+
+ if(mant){
+ while(!(mant&0x40000000)){
+ mant<<=1;
+ *point-=1;
+ }
+ if(sign)mant= -mant;
+ }else{
+ *point=-9999;
+ }
+ return mant;
+}
+
+/* choose the smallest supported node size that fits our decode table.
+ Legal bytewidths are 1/1 1/2 2/2 2/4 4/4 */
+static int _determine_node_bytes(long used, int leafwidth){
+
+ /* special case small books to size 4 to avoid multiple special
+ cases in repack */
+ if(used<2)
+ return 4;
+
+ if(leafwidth==3)leafwidth=4;
+ if(_ilog(3*used-6)+1 <= leafwidth*4)
+ return leafwidth/2?leafwidth/2:1;
+ return leafwidth;
+}
+
+/* convenience/clarity; leaves are specified as multiple of node word
+ size (1 or 2) */
+static int _determine_leaf_words(int nodeb, int leafwidth){
+ if(leafwidth>nodeb)return 2;
+ return 1;
+}
+
+/* given a list of word lengths, number of used entries, and byte
+ width of a leaf, generate the decode table */
+static int _make_words(char *l,long n,ogg_uint32_t *r,long quantvals,
+ codebook *b, oggpack_buffer *opb,int maptype){
+ long i,j,count=0;
+ long top=0;
+ ogg_uint32_t marker[33];
+
+ if(n<2){
+ r[0]=0x80000000;
+ }else{
+ memset(marker,0,sizeof(marker));
+
+ for(i=0;i<n;i++){
+ long length=l[i];
+ if(length){
+ ogg_uint32_t entry=marker[length];
+ long chase=0;
+ if(count && !entry)return -1; /* overpopulated tree! */
+
+ /* chase the tree as far as it's already populated, fill in past */
+ for(j=0;j<length-1;j++){
+ int bit=(entry>>(length-j-1))&1;
+ if(chase>=top){
+ top++;
+ r[chase*2]=top;
+ r[chase*2+1]=0;
+ }else
+ if(!r[chase*2+bit])
+ r[chase*2+bit]=top;
+ chase=r[chase*2+bit];
+ }
+ {
+ int bit=(entry>>(length-j-1))&1;
+ if(chase>=top){
+ top++;
+ r[chase*2+1]=0;
+ }
+ r[chase*2+bit]= decpack(i,count++,quantvals,b,opb,maptype) |
+ 0x80000000;
+ }
+
+ /* Look to see if the next shorter marker points to the node
+ above. if so, update it and repeat. */
+ for(j=length;j>0;j--){
+ if(marker[j]&1){
+ marker[j]=marker[j-1]<<1;
+ break;
+ }
+ marker[j]++;
+ }
+
+ /* prune the tree; the implicit invariant says all the longer
+ markers were dangling from our just-taken node. Dangle them
+ from our *new* node. */
+ for(j=length+1;j<33;j++)
+ if((marker[j]>>1) == entry){
+ entry=marker[j];
+ marker[j]=marker[j-1]<<1;
+ }else
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int _make_decode_table(codebook *s,char *lengthlist,long quantvals,
+ oggpack_buffer *opb,int maptype){
+ int i;
+ ogg_uint32_t *work;
+
+ if(s->dec_nodeb==4){
+ s->dec_table=_ogg_malloc((s->used_entries*2+1)*sizeof(*work));
+ /* +1 (rather than -2) is to accommodate 0 and 1 sized books,
+ which are specialcased to nodeb==4 */
+ if(_make_words(lengthlist,s->entries,
+ s->dec_table,quantvals,s,opb,maptype))return 1;
+
+ return 0;
+ }
+
+ work=alloca((s->used_entries*2-2)*sizeof(*work));
+ if(_make_words(lengthlist,s->entries,work,quantvals,s,opb,maptype))return 1;
+ s->dec_table=_ogg_malloc((s->used_entries*(s->dec_leafw+1)-2)*
+ s->dec_nodeb);
+
+ if(s->dec_leafw==1){
+ switch(s->dec_nodeb){
+ case 1:
+ for(i=0;i<s->used_entries*2-2;i++)
+ ((unsigned char *)s->dec_table)[i]=
+ ((work[i] & 0x80000000UL) >> 24) | work[i];
+ break;
+ case 2:
+ for(i=0;i<s->used_entries*2-2;i++)
+ ((ogg_uint16_t *)s->dec_table)[i]=
+ ((work[i] & 0x80000000UL) >> 16) | work[i];
+ break;
+ }
+
+ }else{
+ /* more complex; we have to do a two-pass repack that updates the
+ node indexing. */
+ long top=s->used_entries*3-2;
+ if(s->dec_nodeb==1){
+ unsigned char *out=(unsigned char *)s->dec_table;
+
+ for(i=s->used_entries*2-4;i>=0;i-=2){
+ if(work[i]&0x80000000UL){
+ if(work[i+1]&0x80000000UL){
+ top-=4;
+ out[top]=(work[i]>>8 & 0x7f)|0x80;
+ out[top+1]=(work[i+1]>>8 & 0x7f)|0x80;
+ out[top+2]=work[i] & 0xff;
+ out[top+3]=work[i+1] & 0xff;
+ }else{
+ top-=3;
+ out[top]=(work[i]>>8 & 0x7f)|0x80;
+ out[top+1]=work[work[i+1]*2];
+ out[top+2]=work[i] & 0xff;
+ }
+ }else{
+ if(work[i+1]&0x80000000UL){
+ top-=3;
+ out[top]=work[work[i]*2];
+ out[top+1]=(work[i+1]>>8 & 0x7f)|0x80;
+ out[top+2]=work[i+1] & 0xff;
+ }else{
+ top-=2;
+ out[top]=work[work[i]*2];
+ out[top+1]=work[work[i+1]*2];
+ }
+ }
+ work[i]=top;
+ }
+ }else{
+ ogg_uint16_t *out=(ogg_uint16_t *)s->dec_table;
+ for(i=s->used_entries*2-4;i>=0;i-=2){
+ if(work[i]&0x80000000UL){
+ if(work[i+1]&0x80000000UL){
+ top-=4;
+ out[top]=(work[i]>>16 & 0x7fff)|0x8000;
+ out[top+1]=(work[i+1]>>16 & 0x7fff)|0x8000;
+ out[top+2]=work[i] & 0xffff;
+ out[top+3]=work[i+1] & 0xffff;
+ }else{
+ top-=3;
+ out[top]=(work[i]>>16 & 0x7fff)|0x8000;
+ out[top+1]=work[work[i+1]*2];
+ out[top+2]=work[i] & 0xffff;
+ }
+ }else{
+ if(work[i+1]&0x80000000UL){
+ top-=3;
+ out[top]=work[work[i]*2];
+ out[top+1]=(work[i+1]>>16 & 0x7fff)|0x8000;
+ out[top+2]=work[i+1] & 0xffff;
+ }else{
+ top-=2;
+ out[top]=work[work[i]*2];
+ out[top+1]=work[work[i+1]*2];
+ }
+ }
+ work[i]=top;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/* most of the time, entries%dimensions == 0, but we need to be
+ well defined. We define that the possible vales at each
+ scalar is values == entries/dim. If entries%dim != 0, we'll
+ have 'too few' values (values*dim<entries), which means that
+ we'll have 'left over' entries; left over entries use zeroed
+ values (and are wasted). So don't generate codebooks like
+ that */
+/* there might be a straightforward one-line way to do the below
+ that's portable and totally safe against roundoff, but I haven't
+ thought of it. Therefore, we opt on the side of caution */
+long _book_maptype1_quantvals(codebook *b){
+ /* get us a starting hint, we'll polish it below */
+ int bits=_ilog(b->entries);
+ int vals=b->entries>>((bits-1)*(b->dim-1)/b->dim);
+
+ while(1){
+ long acc=1;
+ long acc1=1;
+ int i;
+ for(i=0;i<b->dim;i++){
+ acc*=vals;
+ acc1*=vals+1;
+ }
+ if(acc<=b->entries && acc1>b->entries){
+ return(vals);
+ }else{
+ if(acc>b->entries){
+ vals--;
+ }else{
+ vals++;
+ }
+ }
+ }
+}
+
+void vorbis_book_clear(codebook *b){
+ /* static book is not cleared; we're likely called on the lookup and
+ the static codebook belongs to the info struct */
+ if(b->q_val)_ogg_free(b->q_val);
+ if(b->dec_table)_ogg_free(b->dec_table);
+
+ memset(b,0,sizeof(*b));
+}
+
+int vorbis_book_unpack(oggpack_buffer *opb,codebook *s){
+ char *lengthlist=NULL;
+ int quantvals=0;
+ long i,j;
+ int maptype;
+
+ memset(s,0,sizeof(*s));
+
+ /* make sure alignment is correct */
+ if(oggpack_read(opb,24)!=0x564342)goto _eofout;
+
+ /* first the basic parameters */
+ s->dim=oggpack_read(opb,16);
+ s->entries=oggpack_read(opb,24);
+ if(s->entries==-1)goto _eofout;
+
+ /* codeword ordering.... length ordered or unordered? */
+ switch((int)oggpack_read(opb,1)){
+ case 0:
+ /* unordered */
+ lengthlist=(char *)alloca(sizeof(*lengthlist)*s->entries);
+
+ /* allocated but unused entries? */
+ if(oggpack_read(opb,1)){
+ /* yes, unused entries */
+
+ for(i=0;i<s->entries;i++){
+ if(oggpack_read(opb,1)){
+ long num=oggpack_read(opb,5);
+ if(num==-1)goto _eofout;
+ lengthlist[i]=num+1;
+ s->used_entries++;
+ if(num+1>s->dec_maxlength)s->dec_maxlength=num+1;
+ }else
+ lengthlist[i]=0;
+ }
+ }else{
+ /* all entries used; no tagging */
+ s->used_entries=s->entries;
+ for(i=0;i<s->entries;i++){
+ long num=oggpack_read(opb,5);
+ if(num==-1)goto _eofout;
+ lengthlist[i]=num+1;
+ if(num+1>s->dec_maxlength)s->dec_maxlength=num+1;
+ }
+ }
+
+ break;
+ case 1:
+ /* ordered */
+ {
+ long length=oggpack_read(opb,5)+1;
+
+ s->used_entries=s->entries;
+ lengthlist=(char *)alloca(sizeof(*lengthlist)*s->entries);
+
+ for(i=0;i<s->entries;){
+ long num=oggpack_read(opb,_ilog(s->entries-i));
+ if(num==-1)goto _eofout;
+ for(j=0;j<num && i<s->entries;j++,i++)
+ lengthlist[i]=length;
+ s->dec_maxlength=length;
+ length++;
+ }
+ }
+ break;
+ default:
+ /* EOF */
+ goto _eofout;
+ }
+
+
+ /* Do we have a mapping to unpack? */
+
+ if((maptype=oggpack_read(opb,4))>0){
+ s->q_min=_float32_unpack(oggpack_read(opb,32),&s->q_minp);
+ s->q_del=_float32_unpack(oggpack_read(opb,32),&s->q_delp);
+ s->q_bits=oggpack_read(opb,4)+1;
+ s->q_seq=oggpack_read(opb,1);
+
+ s->q_del>>=s->q_bits;
+ s->q_delp+=s->q_bits;
+ }
+
+ switch(maptype){
+ case 0:
+
+ /* no mapping; decode type 0 */
+
+ /* how many bytes for the indexing? */
+ /* this is the correct boundary here; we lose one bit to
+ node/leaf mark */
+ s->dec_nodeb=_determine_node_bytes(s->used_entries,_ilog(s->entries)/8+1);
+ s->dec_leafw=_determine_leaf_words(s->dec_nodeb,_ilog(s->entries)/8+1);
+ s->dec_type=0;
+
+ if(_make_decode_table(s,lengthlist,quantvals,opb,maptype)) goto _errout;
+ break;
+
+ case 1:
+
+ /* mapping type 1; implicit values by lattice position */
+ quantvals=_book_maptype1_quantvals(s);
+
+ /* dec_type choices here are 1,2; 3 doesn't make sense */
+ {
+ /* packed values */
+ long total1=(s->q_bits*s->dim+8)/8; /* remember flag bit */
+ /* vector of column offsets; remember flag bit */
+ long total2=(_ilog(quantvals-1)*s->dim+8)/8+(s->q_bits+7)/8;
+
+
+ if(total1<=4 && total1<=total2){
+ /* use dec_type 1: vector of packed values */
+
+ /* need quantized values before */
+ s->q_val=alloca(sizeof(ogg_uint16_t)*quantvals);
+ for(i=0;i<quantvals;i++)
+ ((ogg_uint16_t *)s->q_val)[i]=oggpack_read(opb,s->q_bits);
+
+ if(oggpack_eop(opb)){
+ s->q_val=0; /* cleanup must not free alloca memory */
+ goto _eofout;
+ }
+
+ s->dec_type=1;
+ s->dec_nodeb=_determine_node_bytes(s->used_entries,
+ (s->q_bits*s->dim+8)/8);
+ s->dec_leafw=_determine_leaf_words(s->dec_nodeb,
+ (s->q_bits*s->dim+8)/8);
+ if(_make_decode_table(s,lengthlist,quantvals,opb,maptype)){
+ s->q_val=0; /* cleanup must not free alloca memory */
+ goto _errout;
+ }
+
+ s->q_val=0; /* about to go out of scope; _make_decode_table
+ was using it */
+
+ }else{
+ /* use dec_type 2: packed vector of column offsets */
+
+ /* need quantized values before */
+ if(s->q_bits<=8){
+ s->q_val=_ogg_malloc(quantvals);
+ for(i=0;i<quantvals;i++)
+ ((unsigned char *)s->q_val)[i]=oggpack_read(opb,s->q_bits);
+ }else{
+ s->q_val=_ogg_malloc(quantvals*2);
+ for(i=0;i<quantvals;i++)
+ ((ogg_uint16_t *)s->q_val)[i]=oggpack_read(opb,s->q_bits);
+ }
+
+ if(oggpack_eop(opb))goto _eofout;
+
+ s->q_pack=_ilog(quantvals-1);
+ s->dec_type=2;
+ s->dec_nodeb=_determine_node_bytes(s->used_entries,
+ (_ilog(quantvals-1)*s->dim+8)/8);
+ s->dec_leafw=_determine_leaf_words(s->dec_nodeb,
+ (_ilog(quantvals-1)*s->dim+8)/8);
+ if(_make_decode_table(s,lengthlist,quantvals,opb,maptype))goto _errout;
+
+ }
+ }
+ break;
+ case 2:
+
+ /* mapping type 2; explicit array of values */
+ quantvals=s->entries*s->dim;
+ /* dec_type choices here are 1,3; 2 is not possible */
+
+ if( (s->q_bits*s->dim+8)/8 <=4){ /* remember flag bit */
+ /* use dec_type 1: vector of packed values */
+
+ s->dec_type=1;
+ s->dec_nodeb=_determine_node_bytes(s->used_entries,(s->q_bits*s->dim+8)/8);
+ s->dec_leafw=_determine_leaf_words(s->dec_nodeb,(s->q_bits*s->dim+8)/8);
+ if(_make_decode_table(s,lengthlist,quantvals,opb,maptype))goto _errout;
+
+ }else{
+ /* use dec_type 3: scalar offset into packed value array */
+
+ s->dec_type=3;
+ s->dec_nodeb=_determine_node_bytes(s->used_entries,_ilog(s->used_entries-1)/8+1);
+ s->dec_leafw=_determine_leaf_words(s->dec_nodeb,_ilog(s->used_entries-1)/8+1);
+ if(_make_decode_table(s,lengthlist,quantvals,opb,maptype))goto _errout;
+
+ /* get the vals & pack them */
+ s->q_pack=(s->q_bits+7)/8*s->dim;
+ s->q_val=_ogg_malloc(s->q_pack*s->used_entries);
+
+ if(s->q_bits<=8){
+ for(i=0;i<s->used_entries*s->dim;i++)
+ ((unsigned char *)(s->q_val))[i]=oggpack_read(opb,s->q_bits);
+ }else{
+ for(i=0;i<s->used_entries*s->dim;i++)
+ ((ogg_uint16_t *)(s->q_val))[i]=oggpack_read(opb,s->q_bits);
+ }
+ }
+ break;
+ default:
+ goto _errout;
+ }
+
+ if(oggpack_eop(opb))goto _eofout;
+
+ return 0;
+ _errout:
+ _eofout:
+ vorbis_book_clear(s);
+ return -1;
+}
+
+static inline ogg_uint32_t decode_packed_entry_number(codebook *book,
+ oggpack_buffer *b){
+ ogg_uint32_t chase=0;
+ int read=book->dec_maxlength;
+ long lok = oggpack_look(b,read),i;
+
+ while(lok<0 && read>1)
+ lok = oggpack_look(b, --read);
+
+ if(lok<0){
+ oggpack_adv(b,1); /* force eop */
+ return -1;
+ }
+
+ /* chase the tree with the bits we got */
+ if(book->dec_nodeb==1){
+ if(book->dec_leafw==1){
+
+ /* 8/8 */
+ unsigned char *t=(unsigned char *)book->dec_table;
+ for(i=0;i<read;i++){
+ chase=t[chase*2+((lok>>i)&1)];
+ if(chase&0x80UL)break;
+ }
+ chase&=0x7fUL;
+
+ }else{
+
+ /* 8/16 */
+ unsigned char *t=(unsigned char *)book->dec_table;
+ for(i=0;i<read;i++){
+ int bit=(lok>>i)&1;
+ int next=t[chase+bit];
+ if(next&0x80){
+ chase= (next<<8) | t[chase+bit+1+(!bit || t[chase]&0x80)];
+ break;
+ }
+ chase=next;
+ }
+ chase&=0x7fffUL;
+ }
+
+ }else{
+ if(book->dec_nodeb==2){
+ if(book->dec_leafw==1){
+
+ /* 16/16 */
+ for(i=0;i<read;i++){
+ chase=((ogg_uint16_t *)(book->dec_table))[chase*2+((lok>>i)&1)];
+ if(chase&0x8000UL)break;
+ }
+ chase&=0x7fffUL;
+
+ }else{
+
+ /* 16/32 */
+ ogg_uint16_t *t=(ogg_uint16_t *)book->dec_table;
+ for(i=0;i<read;i++){
+ int bit=(lok>>i)&1;
+ int next=t[chase+bit];
+ if(next&0x8000){
+ chase= (next<<16) | t[chase+bit+1+(!bit || t[chase]&0x8000)];
+ break;
+ }
+ chase=next;
+ }
+ chase&=0x7fffffffUL;
+ }
+
+ }else{
+
+ for(i=0;i<read;i++){
+ chase=((ogg_uint32_t *)(book->dec_table))[chase*2+((lok>>i)&1)];
+ if(chase&0x80000000UL)break;
+ }
+ chase&=0x7fffffffUL;
+
+ }
+ }
+
+ if(i<read){
+ oggpack_adv(b,i+1);
+ return chase;
+ }
+ oggpack_adv(b,read+1);
+ return(-1);
+}
+
+/* returns the [original, not compacted] entry number or -1 on eof *********/
+long vorbis_book_decode(codebook *book, oggpack_buffer *b){
+ if(book->dec_type)return -1;
+ return decode_packed_entry_number(book,b);
+}
+
+int decode_map(codebook *s, oggpack_buffer *b, ogg_int32_t *v, int point){
+ ogg_uint32_t entry = decode_packed_entry_number(s,b);
+ int i;
+ if(oggpack_eop(b))return(-1);
+
+ /* according to decode type */
+ switch(s->dec_type){
+ case 1:{
+ /* packed vector of values */
+ int mask=(1<<s->q_bits)-1;
+ for(i=0;i<s->dim;i++){
+ v[i]=entry&mask;
+ entry>>=s->q_bits;
+ }
+ break;
+ }
+ case 2:{
+ /* packed vector of column offsets */
+ int mask=(1<<s->q_pack)-1;
+ for(i=0;i<s->dim;i++){
+ if(s->q_bits<=8)
+ v[i]=((unsigned char *)(s->q_val))[entry&mask];
+ else
+ v[i]=((ogg_uint16_t *)(s->q_val))[entry&mask];
+ entry>>=s->q_pack;
+ }
+ break;
+ }
+ case 3:{
+ /* offset into array */
+ void *ptr=s->q_val+entry*s->q_pack;
+
+ if(s->q_bits<=8){
+ for(i=0;i<s->dim;i++)
+ v[i]=((unsigned char *)ptr)[i];
+ }else{
+ for(i=0;i<s->dim;i++)
+ v[i]=((ogg_uint16_t *)ptr)[i];
+ }
+ break;
+ }
+ default:
+ return -1;
+ }
+
+ /* we have the unpacked multiplicands; compute final vals */
+ {
+ int shiftM=point-s->q_delp;
+ ogg_int32_t add=point-s->q_minp;
+ if(add>0)
+ add= s->q_min >> add;
+ else
+ add= s->q_min << -add;
+
+ if(shiftM>0)
+ for(i=0;i<s->dim;i++)
+ v[i]= add + ((v[i] * s->q_del) >> shiftM);
+ else
+ for(i=0;i<s->dim;i++)
+ v[i]= add + ((v[i] * s->q_del) << -shiftM);
+
+ if(s->q_seq)
+ for(i=1;i<s->dim;i++)
+ v[i]+=v[i-1];
+ }
+
+ return 0;
+}
+
+/* returns 0 on OK or -1 on eof *************************************/
+long vorbis_book_decodevs_add(codebook *book,ogg_int32_t *a,
+ oggpack_buffer *b,int n,int point){
+ if(book->used_entries>0){
+ int step=n/book->dim;
+ ogg_int32_t *v = (ogg_int32_t *)alloca(sizeof(*v)*book->dim);
+ int i,j,o;
+
+ for (j=0;j<step;j++){
+ if(decode_map(book,b,v,point))return -1;
+ for(i=0,o=j;i<book->dim;i++,o+=step)
+ a[o]+=v[i];
+ }
+ }
+ return 0;
+}
+
+long vorbis_book_decodev_add(codebook *book,ogg_int32_t *a,
+ oggpack_buffer *b,int n,int point){
+ if(book->used_entries>0){
+ ogg_int32_t *v = (ogg_int32_t *)alloca(sizeof(*v)*book->dim);
+ int i,j;
+
+ for(i=0;i<n;){
+ if(decode_map(book,b,v,point))return -1;
+ for (j=0;j<book->dim;j++)
+ a[i++]+=v[j];
+ }
+ }
+ return 0;
+}
+
+long vorbis_book_decodev_set(codebook *book,ogg_int32_t *a,
+ oggpack_buffer *b,int n,int point){
+ if(book->used_entries>0){
+ ogg_int32_t *v = (ogg_int32_t *)alloca(sizeof(*v)*book->dim);
+ int i,j;
+
+ for(i=0;i<n;){
+ if(decode_map(book,b,v,point))return -1;
+ for (j=0;j<book->dim;j++)
+ a[i++]=v[j];
+ }
+ }else{
+ int i,j;
+
+ for(i=0;i<n;){
+ for (j=0;j<book->dim;j++)
+ a[i++]=0;
+ }
+ }
+
+ return 0;
+}
+
+long vorbis_book_decodevv_add(codebook *book,ogg_int32_t **a,
+ long offset,int ch,
+ oggpack_buffer *b,int n,int point){
+ if(book->used_entries>0){
+
+ ogg_int32_t *v = (ogg_int32_t *)alloca(sizeof(*v)*book->dim);
+ long i,j;
+ int chptr=0;
+
+ for(i=offset;i<offset+n;){
+ if(decode_map(book,b,v,point))return -1;
+ for (j=0;j<book->dim;j++){
+ a[chptr++][i]+=v[j];
+ if(chptr==ch){
+ chptr=0;
+ i++;
+ }
+ }
+ }
+ }
+
+ return 0;
+}
diff --git a/library/ADK2/v_codebook.h b/library/ADK2/v_codebook.h
new file mode 100644
index 0000000..57c37ad
--- /dev/null
+++ b/library/ADK2/v_codebook.h
@@ -0,0 +1,68 @@
+#ifdef ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2002 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: basic shared codebook operations
+
+ ********************************************************************/
+
+#ifndef _V_CODEBOOK_H_
+#define _V_CODEBOOK_H_
+
+#include "v_ogg.h"
+
+typedef struct codebook{
+ long dim; /* codebook dimensions (elements per vector) */
+ long entries; /* codebook entries */
+ long used_entries; /* populated codebook entries */
+
+ int dec_maxlength;
+ void *dec_table;
+ int dec_nodeb;
+ int dec_leafw;
+ int dec_type; /* 0 = entry number
+ 1 = packed vector of values
+ 2 = packed vector of column offsets, maptype 1
+ 3 = scalar offset into value array, maptype 2 */
+
+ ogg_int32_t q_min;
+ int q_minp;
+ ogg_int32_t q_del;
+ int q_delp;
+ int q_seq;
+ int q_bits;
+ int q_pack;
+ void *q_val;
+
+} codebook;
+
+extern void vorbis_book_clear(codebook *b);
+extern int vorbis_book_unpack(oggpack_buffer *b,codebook *c);
+
+extern long vorbis_book_decode(codebook *book, oggpack_buffer *b);
+extern long vorbis_book_decodevs_add(codebook *book, ogg_int32_t *a,
+ oggpack_buffer *b,int n,int point);
+extern long vorbis_book_decodev_set(codebook *book, ogg_int32_t *a,
+ oggpack_buffer *b,int n,int point);
+extern long vorbis_book_decodev_add(codebook *book, ogg_int32_t *a,
+ oggpack_buffer *b,int n,int point);
+extern long vorbis_book_decodevv_add(codebook *book, ogg_int32_t **a,
+ long off,int ch,
+ oggpack_buffer *b,int n,int point);
+
+extern int _ilog(unsigned int v);
+
+
+#endif
+#endif
+
diff --git a/library/ADK2/v_codec_internal.h b/library/ADK2/v_codec_internal.h
new file mode 100644
index 0000000..91f92ff
--- /dev/null
+++ b/library/ADK2/v_codec_internal.h
@@ -0,0 +1,216 @@
+#ifdef ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: libvorbis codec headers
+
+ ********************************************************************/
+
+#ifndef _V_CODECI_H_
+#define _V_CODECI_H_
+
+#define CHUNKSIZE 1024
+
+#include "v_codebook.h"
+#include "v_ivorbiscodec.h"
+
+#define VI_TRANSFORMB 1
+#define VI_WINDOWB 1
+#define VI_TIMEB 1
+#define VI_FLOORB 2
+#define VI_RESB 3
+#define VI_MAPB 1
+
+typedef void vorbis_info_floor;
+
+/* vorbis_dsp_state buffers the current vorbis audio
+ analysis/synthesis state. The DSP state belongs to a specific
+ logical bitstream ****************************************************/
+struct vorbis_dsp_state{
+ vorbis_info *vi;
+ oggpack_buffer opb;
+
+ ogg_int32_t **work;
+ ogg_int32_t **mdctright;
+ int out_begin;
+ int out_end;
+
+ long lW;
+ long W;
+
+ ogg_int64_t granulepos;
+ ogg_int64_t sequence;
+ ogg_int64_t sample_count;
+
+};
+
+
+/* Floor backend generic *****************************************/
+
+extern vorbis_info_floor *floor0_info_unpack(vorbis_info *,oggpack_buffer *);
+extern void floor0_free_info(vorbis_info_floor *);
+extern int floor0_memosize(vorbis_info_floor *);
+extern ogg_int32_t *floor0_inverse1(struct vorbis_dsp_state *,
+ vorbis_info_floor *,ogg_int32_t *);
+extern int floor0_inverse2 (struct vorbis_dsp_state *,vorbis_info_floor *,
+ ogg_int32_t *buffer,ogg_int32_t *);
+
+extern vorbis_info_floor *floor1_info_unpack(vorbis_info *,oggpack_buffer *);
+extern void floor1_free_info(vorbis_info_floor *);
+extern int floor1_memosize(vorbis_info_floor *);
+extern ogg_int32_t *floor1_inverse1(struct vorbis_dsp_state *,
+ vorbis_info_floor *,ogg_int32_t *);
+extern int floor1_inverse2 (struct vorbis_dsp_state *,vorbis_info_floor *,
+ ogg_int32_t *buffer,ogg_int32_t *);
+
+typedef struct{
+ int order;
+ long rate;
+ long barkmap;
+
+ int ampbits;
+ int ampdB;
+
+ int numbooks; /* <= 16 */
+ char books[16];
+
+} vorbis_info_floor0;
+
+typedef struct{
+ char class_dim; /* 1 to 8 */
+ char class_subs; /* 0,1,2,3 (bits: 1<<n poss) */
+ unsigned char class_book; /* subs ^ dim entries */
+ unsigned char class_subbook[8]; /* [VIF_CLASS][subs] */
+} floor1class;
+
+typedef struct{
+ floor1class *class; /* [VIF_CLASS] */
+ char *partitionclass; /* [VIF_PARTS]; 0 to 15 */
+ ogg_uint16_t *postlist; /* [VIF_POSIT+2]; first two implicit */
+ char *forward_index; /* [VIF_POSIT+2]; */
+ char *hineighbor; /* [VIF_POSIT]; */
+ char *loneighbor; /* [VIF_POSIT]; */
+
+ int partitions; /* 0 to 31 */
+ int posts;
+ int mult; /* 1 2 3 or 4 */
+
+} vorbis_info_floor1;
+
+/* Residue backend generic *****************************************/
+
+typedef struct vorbis_info_residue{
+ int type;
+ unsigned char *stagemasks;
+ unsigned char *stagebooks;
+
+/* block-partitioned VQ coded straight residue */
+ long begin;
+ long end;
+
+ /* first stage (lossless partitioning) */
+ int grouping; /* group n vectors per partition */
+ char partitions; /* possible codebooks for a partition */
+ unsigned char groupbook; /* huffbook for partitioning */
+ char stages;
+} vorbis_info_residue;
+
+extern void res_clear_info(vorbis_info_residue *info);
+extern int res_unpack(vorbis_info_residue *info,
+ vorbis_info *vi,oggpack_buffer *opb);
+extern int res_inverse(vorbis_dsp_state *,vorbis_info_residue *info,
+ ogg_int32_t **in,int *nonzero,int ch);
+
+/* mode ************************************************************/
+typedef struct {
+ unsigned char blockflag;
+ unsigned char mapping;
+} vorbis_info_mode;
+
+/* Mapping backend generic *****************************************/
+typedef struct coupling_step{
+ unsigned char mag;
+ unsigned char ang;
+} coupling_step;
+
+typedef struct submap{
+ char floor;
+ char residue;
+} submap;
+
+typedef struct vorbis_info_mapping{
+ int submaps;
+
+ unsigned char *chmuxlist;
+ submap *submaplist;
+
+ int coupling_steps;
+ coupling_step *coupling;
+} vorbis_info_mapping;
+
+extern int mapping_info_unpack(vorbis_info_mapping *,vorbis_info *,
+ oggpack_buffer *);
+extern void mapping_clear_info(vorbis_info_mapping *);
+extern int mapping_inverse(struct vorbis_dsp_state *,vorbis_info_mapping *);
+
+/* codec_setup_info contains all the setup information specific to the
+ specific compression/decompression mode in progress (eg,
+ psychoacoustic settings, channel setup, options, codebook
+ etc).
+*********************************************************************/
+
+typedef struct codec_setup_info {
+
+ /* Vorbis supports only short and long blocks, but allows the
+ encoder to choose the sizes */
+
+ long blocksizes[2];
+
+ /* modes are the primary means of supporting on-the-fly different
+ blocksizes, different channel mappings (LR or M/A),
+ different residue backends, etc. Each mode consists of a
+ blocksize flag and a mapping (along with the mapping setup */
+
+ int modes;
+ int maps;
+ int floors;
+ int residues;
+ int books;
+
+ vorbis_info_mode *mode_param;
+ vorbis_info_mapping *map_param;
+ char *floor_type;
+ vorbis_info_floor **floor_param;
+ vorbis_info_residue *residue_param;
+ codebook *book_param;
+
+} codec_setup_info;
+
+extern vorbis_dsp_state *vorbis_dsp_create(vorbis_info *vi);
+extern void vorbis_dsp_destroy(vorbis_dsp_state *v);
+extern int vorbis_dsp_headerin(vorbis_info *vi,vorbis_comment *vc,
+ ogg_packet *op);
+
+extern int vorbis_dsp_restart(vorbis_dsp_state *v);
+extern int vorbis_dsp_synthesis(vorbis_dsp_state *vd,
+ ogg_packet *op,int decodep);
+extern int vorbis_dsp_pcmout(vorbis_dsp_state *v,
+ ogg_int16_t *pcm,int samples);
+extern int vorbis_dsp_read(vorbis_dsp_state *v,int samples);
+extern long vorbis_packet_blocksize(vorbis_info *vi,ogg_packet *op);
+
+
+
+#endif
+#endif
+
diff --git a/library/ADK2/v_config.h b/library/ADK2/v_config.h
new file mode 100644
index 0000000..60985c3
--- /dev/null
+++ b/library/ADK2/v_config.h
@@ -0,0 +1,89 @@
+#ifdef ADK_INTERNAL
+/* config.h. Generated from config.h.in by configure. */
+/* config.h.in. Generated from configure.in by autoheader. */
+
+/* Define to one of `_getb67', `GETB67', `getb67' for Cray-2 and Cray-YMP
+ systems. This function is required for `alloca.c' support on those systems.
+ */
+/* #undef CRAY_STACKSEG_END */
+
+/* Define to 1 if using `alloca.c'. */
+#define C_ALLOCA 1
+
+/* Define to 1 if you have `alloca', as a function or macro. */
+/* #undef HAVE_ALLOCA */
+
+/* Define to 1 if you have <alloca.h> and it should be used (not on Ultrix).
+ */
+/* #undef HAVE_ALLOCA_H */
+
+/* Define to 1 if you have the <dlfcn.h> header file. */
+#define HAVE_DLFCN_H 1
+
+/* Define to 1 if you have the <inttypes.h> header file. */
+#define HAVE_INTTYPES_H 1
+
+/* Define to 1 if you have the <memory.h> header file. */
+#define HAVE_MEMORY_H 1
+
+/* Define to 1 if you have the <stdint.h> header file. */
+#define HAVE_STDINT_H 1
+
+/* Define to 1 if you have the <stdlib.h> header file. */
+#define HAVE_STDLIB_H 1
+
+/* Define to 1 if you have the <strings.h> header file. */
+#define HAVE_STRINGS_H 1
+
+/* Define to 1 if you have the <string.h> header file. */
+#define HAVE_STRING_H 1
+
+/* Define to 1 if you have the <sys/stat.h> header file. */
+#define HAVE_SYS_STAT_H 1
+
+/* Define to 1 if you have the <sys/types.h> header file. */
+#define HAVE_SYS_TYPES_H 1
+
+/* Define to 1 if you have the <unistd.h> header file. */
+#define HAVE_UNISTD_H 1
+
+/* Define to the sub-directory in which libtool stores uninstalled libraries.
+ */
+#define LT_OBJDIR ".libs/"
+
+/* Name of package */
+#define PACKAGE "libvorbisidec"
+
+/* Define to the address where bug reports for this package should be sent. */
+#define PACKAGE_BUGREPORT ""
+
+/* Define to the full name of this package. */
+#define PACKAGE_NAME ""
+
+/* Define to the full name and version of this package. */
+#define PACKAGE_STRING ""
+
+/* Define to the one symbol short name of this package. */
+#define PACKAGE_TARNAME ""
+
+/* Define to the home page for this package. */
+#define PACKAGE_URL ""
+
+/* Define to the version of this package. */
+#define PACKAGE_VERSION ""
+
+/* If using the C implementation of alloca, define if you know the
+ direction of stack growth for your system; otherwise it will be
+ automatically deduced at runtime.
+ STACK_DIRECTION > 0 => grows toward higher addresses
+ STACK_DIRECTION < 0 => grows toward lower addresses
+ STACK_DIRECTION = 0 => direction of growth unknown */
+#define STACK_DIRECTION -1
+
+/* Define to 1 if you have the ANSI C header files. */
+#define STDC_HEADERS 1
+
+/* Version number of package */
+#define VERSION "1.2.1"
+#endif
+
diff --git a/library/ADK2/v_config_types.h b/library/ADK2/v_config_types.h
new file mode 100644
index 0000000..e00f0d4
--- /dev/null
+++ b/library/ADK2/v_config_types.h
@@ -0,0 +1,29 @@
+#ifdef ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2002 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: #ifdef jail to whip a few platforms into the UNIX ideal.
+
+ ********************************************************************/
+#ifndef _OS_CVTYPES_H
+#define _OS_CVTYPES_H
+
+typedef long long ogg_int64_t;
+typedef int ogg_int32_t;
+typedef unsigned int ogg_uint32_t;
+typedef short ogg_int16_t;
+typedef unsigned short ogg_uint16_t;
+
+#endif
+#endif
+
diff --git a/library/ADK2/v_dsp.c b/library/ADK2/v_dsp.c
new file mode 100644
index 0000000..71bc672
--- /dev/null
+++ b/library/ADK2/v_dsp.c
@@ -0,0 +1,299 @@
+#define ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: PCM data vector blocking, windowing and dis/reassembly
+
+ ********************************************************************/
+
+#include <stdlib.h>
+#include "v_ogg.h"
+#include "v_mdct.h"
+#include "v_ivorbiscodec.h"
+#include "v_codec_internal.h"
+#include "v_misc.h"
+#include "v_window_lookup.h"
+
+int vorbis_dsp_restart(vorbis_dsp_state *v){
+ if(!v)return -1;
+ {
+ vorbis_info *vi=v->vi;
+ codec_setup_info *ci;
+
+ if(!vi)return -1;
+ ci=vi->codec_setup;
+ if(!ci)return -1;
+
+ v->out_end=-1;
+ v->out_begin=-1;
+
+ v->granulepos=-1;
+ v->sequence=-1;
+ v->sample_count=-1;
+ }
+ return 0;
+}
+
+vorbis_dsp_state *vorbis_dsp_create(vorbis_info *vi){
+ int i;
+
+ vorbis_dsp_state *v=_ogg_calloc(1,sizeof(*v));
+ codec_setup_info *ci=(codec_setup_info *)vi->codec_setup;
+
+ v->vi=vi;
+
+ v->work=(ogg_int32_t **)_ogg_malloc(vi->channels*sizeof(*v->work));
+ v->mdctright=(ogg_int32_t **)_ogg_malloc(vi->channels*sizeof(*v->mdctright));
+ for(i=0;i<vi->channels;i++){
+ v->work[i]=(ogg_int32_t *)_ogg_calloc(1,(ci->blocksizes[1]>>1)*
+ sizeof(*v->work[i]));
+ v->mdctright[i]=(ogg_int32_t *)_ogg_calloc(1,(ci->blocksizes[1]>>2)*
+ sizeof(*v->mdctright[i]));
+ }
+
+ v->lW=0; /* previous window size */
+ v->W=0; /* current window size */
+
+ vorbis_dsp_restart(v);
+ return v;
+}
+
+void vorbis_dsp_destroy(vorbis_dsp_state *v){
+ int i;
+ if(v){
+ vorbis_info *vi=v->vi;
+
+ if(v->work){
+ for(i=0;i<vi->channels;i++)
+ if(v->work[i])_ogg_free(v->work[i]);
+ _ogg_free(v->work);
+ }
+ if(v->mdctright){
+ for(i=0;i<vi->channels;i++)
+ if(v->mdctright[i])_ogg_free(v->mdctright[i]);
+ _ogg_free(v->mdctright);
+ }
+
+ _ogg_free(v);
+ }
+}
+
+static LOOKUP_T *_vorbis_window(int left){
+ switch(left){
+ case 32:
+ return vwin64;
+ case 64:
+ return vwin128;
+ case 128:
+ return vwin256;
+ case 256:
+ return vwin512;
+ case 512:
+ return vwin1024;
+ case 1024:
+ return vwin2048;
+ case 2048:
+ return vwin4096;
+#ifndef LIMIT_TO_64kHz
+ case 4096:
+ return vwin8192;
+#endif
+ default:
+ return(0);
+ }
+}
+
+/* pcm==0 indicates we just want the pending samples, no more */
+int vorbis_dsp_pcmout(vorbis_dsp_state *v,ogg_int16_t *pcm,int samples){
+ vorbis_info *vi=v->vi;
+ codec_setup_info *ci=(codec_setup_info *)vi->codec_setup;
+ if(v->out_begin>-1 && v->out_begin<v->out_end){
+ int n=v->out_end-v->out_begin;
+ if(pcm){
+ int i;
+ if(n>samples)n=samples;
+ for(i=0;i<vi->channels;i++)
+ mdct_unroll_lap(ci->blocksizes[0],ci->blocksizes[1],
+ v->lW,v->W,v->work[i],v->mdctright[i],
+ _vorbis_window(ci->blocksizes[0]>>1),
+ _vorbis_window(ci->blocksizes[1]>>1),
+ pcm+i,vi->channels,
+ v->out_begin,v->out_begin+n);
+ }
+ return(n);
+ }
+ return(0);
+}
+
+int vorbis_dsp_read(vorbis_dsp_state *v,int s){
+ if(s && v->out_begin+s>v->out_end)return(OV_EINVAL);
+ v->out_begin+=s;
+ return(0);
+}
+
+long vorbis_packet_blocksize(vorbis_info *vi,ogg_packet *op){
+ codec_setup_info *ci=(codec_setup_info *)vi->codec_setup;
+ oggpack_buffer opb;
+ int mode;
+ int modebits=0;
+ int v=ci->modes;
+
+ oggpack_readinit(&opb,op->packet);
+
+ /* Check the packet type */
+ if(oggpack_read(&opb,1)!=0){
+ /* Oops. This is not an audio data packet */
+ return(OV_ENOTAUDIO);
+ }
+
+ while(v>1){
+ modebits++;
+ v>>=1;
+ }
+
+ /* read our mode and pre/post windowsize */
+ mode=oggpack_read(&opb,modebits);
+ if(mode==-1)return(OV_EBADPACKET);
+ return(ci->blocksizes[ci->mode_param[mode].blockflag]);
+}
+
+
+static int ilog(ogg_uint32_t v){
+ int ret=0;
+ if(v)--v;
+ while(v){
+ ret++;
+ v>>=1;
+ }
+ return(ret);
+}
+
+int vorbis_dsp_synthesis(vorbis_dsp_state *vd,ogg_packet *op,int decodep){
+ vorbis_info *vi=vd->vi;
+ codec_setup_info *ci=(codec_setup_info *)vi->codec_setup;
+ int mode,i;
+
+ oggpack_readinit(&vd->opb,op->packet);
+
+ /* Check the packet type */
+ if(oggpack_read(&vd->opb,1)!=0){
+ /* Oops. This is not an audio data packet */
+ return OV_ENOTAUDIO ;
+ }
+
+ /* read our mode and pre/post windowsize */
+ mode=oggpack_read(&vd->opb,ilog(ci->modes));
+ if(mode==-1 || mode>=ci->modes) return OV_EBADPACKET;
+
+ /* shift information we still need from last window */
+ vd->lW=vd->W;
+ vd->W=ci->mode_param[mode].blockflag;
+ for(i=0;i<vi->channels;i++)
+ mdct_shift_right(ci->blocksizes[vd->lW],vd->work[i],vd->mdctright[i]);
+
+ if(vd->W){
+ int temp;
+ oggpack_read(&vd->opb,1);
+ temp=oggpack_read(&vd->opb,1);
+ if(temp==-1) return OV_EBADPACKET;
+ }
+
+ /* packet decode and portions of synthesis that rely on only this block */
+ if(decodep){
+ mapping_inverse(vd,ci->map_param+ci->mode_param[mode].mapping);
+
+ if(vd->out_begin==-1){
+ vd->out_begin=0;
+ vd->out_end=0;
+ }else{
+ vd->out_begin=0;
+ vd->out_end=ci->blocksizes[vd->lW]/4+ci->blocksizes[vd->W]/4;
+ }
+ }
+
+ /* track the frame number... This is for convenience, but also
+ making sure our last packet doesn't end with added padding.
+
+ This is not foolproof! It will be confused if we begin
+ decoding at the last page after a seek or hole. In that case,
+ we don't have a starting point to judge where the last frame
+ is. For this reason, vorbisfile will always try to make sure
+ it reads the last two marked pages in proper sequence */
+
+ /* if we're out of sequence, dump granpos tracking until we sync back up */
+ if(vd->sequence==-1 || vd->sequence+1 != op->packetno-3){
+ /* out of sequence; lose count */
+ vd->granulepos=-1;
+ vd->sample_count=-1;
+ }
+
+ vd->sequence=op->packetno;
+ vd->sequence=vd->sequence-3;
+
+ if(vd->sample_count==-1){
+ vd->sample_count=0;
+ }else{
+ vd->sample_count+=
+ ci->blocksizes[vd->lW]/4+ci->blocksizes[vd->W]/4;
+ }
+
+ if(vd->granulepos==-1){
+ if(op->granulepos!=-1){ /* only set if we have a
+ position to set to */
+
+ vd->granulepos=op->granulepos;
+
+ /* is this a short page? */
+ if(vd->sample_count>vd->granulepos){
+ /* corner case; if this is both the first and last audio page,
+ then spec says the end is cut, not beginning */
+ if(op->e_o_s){
+ /* trim the end */
+ /* no preceeding granulepos; assume we started at zero (we'd
+ have to in a short single-page stream) */
+ /* granulepos could be -1 due to a seek, but that would result
+ in a long coun t, not short count */
+
+ vd->out_end-=vd->sample_count-vd->granulepos;
+ }else{
+ /* trim the beginning */
+ vd->out_begin+=vd->sample_count-vd->granulepos;
+ if(vd->out_begin>vd->out_end)
+ vd->out_begin=vd->out_end;
+ }
+
+ }
+
+ }
+ }else{
+ vd->granulepos+=
+ ci->blocksizes[vd->lW]/4+ci->blocksizes[vd->W]/4;
+ if(op->granulepos!=-1 && vd->granulepos!=op->granulepos){
+
+ if(vd->granulepos>op->granulepos){
+ long extra=vd->granulepos-op->granulepos;
+
+ if(extra)
+ if(op->e_o_s){
+ /* partial last frame. Strip the extra samples off */
+ vd->out_end-=extra;
+ } /* else {Shouldn't happen *unless* the bitstream is out of
+ spec. Either way, believe the bitstream } */
+ } /* else {Shouldn't happen *unless* the bitstream is out of
+ spec. Either way, believe the bitstream } */
+ vd->granulepos=op->granulepos;
+ }
+ }
+
+ return(0);
+}
diff --git a/library/ADK2/v_floor0.c b/library/ADK2/v_floor0.c
new file mode 100644
index 0000000..ebb1e42
--- /dev/null
+++ b/library/ADK2/v_floor0.c
@@ -0,0 +1,429 @@
+#define ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: floor backend 0 implementation
+
+ ********************************************************************/
+
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+#include "v_ogg.h"
+#include "v_ivorbiscodec.h"
+#include "v_codec_internal.h"
+#include "v_codebook.h"
+#include "v_misc.h"
+#include "v_os.h"
+
+#define LSP_FRACBITS 14
+extern const ogg_int32_t FLOOR_fromdB_LOOKUP[];
+
+/*************** LSP decode ********************/
+
+#include "v_lsp_lookup.h"
+
+/* interpolated 1./sqrt(p) where .5 <= a < 1. (.100000... to .111111...) in
+ 16.16 format
+ returns in m.8 format */
+
+static long ADJUST_SQRT2[2]={8192,5792};
+static inline ogg_int32_t vorbis_invsqlook_i(long a,long e){
+ long i=(a&0x7fff)>>(INVSQ_LOOKUP_I_SHIFT-1);
+ long d=a&INVSQ_LOOKUP_I_MASK; /* 0.10 */
+ long val=INVSQ_LOOKUP_I[i]- /* 1.16 */
+ ((INVSQ_LOOKUP_IDel[i]*d)>>INVSQ_LOOKUP_I_SHIFT); /* result 1.16 */
+ val*=ADJUST_SQRT2[e&1];
+ e=(e>>1)+21;
+ return(val>>e);
+}
+
+/* interpolated lookup based fromdB function, domain -140dB to 0dB only */
+/* a is in n.12 format */
+#ifdef _LOW_ACCURACY_
+static inline ogg_int32_t vorbis_fromdBlook_i(long a){
+ if(a>0) return 0x7fffffff;
+ if(a<(-140<<12)) return 0;
+ return FLOOR_fromdB_LOOKUP[((a+140)*467)>>20]<<9;
+}
+#else
+static inline ogg_int32_t vorbis_fromdBlook_i(long a){
+ if(a>0) return 0x7fffffff;
+ if(a<(-140<<12)) return 0;
+ return FLOOR_fromdB_LOOKUP[((a+(140<<12))*467)>>20];
+}
+#endif
+
+/* interpolated lookup based cos function, domain 0 to PI only */
+/* a is in 0.16 format, where 0==0, 2^^16-1==PI, return 0.14 */
+static inline ogg_int32_t vorbis_coslook_i(long a){
+ int i=a>>COS_LOOKUP_I_SHIFT;
+ int d=a&COS_LOOKUP_I_MASK;
+ return COS_LOOKUP_I[i]- ((d*(COS_LOOKUP_I[i]-COS_LOOKUP_I[i+1]))>>
+ COS_LOOKUP_I_SHIFT);
+}
+
+/* interpolated half-wave lookup based cos function */
+/* a is in 0.16 format, where 0==0, 2^^16==PI, return .LSP_FRACBITS */
+static inline ogg_int32_t vorbis_coslook2_i(long a){
+ int i=a>>COS_LOOKUP_I_SHIFT;
+ int d=a&COS_LOOKUP_I_MASK;
+ return ((COS_LOOKUP_I[i]<<COS_LOOKUP_I_SHIFT)-
+ d*(COS_LOOKUP_I[i]-COS_LOOKUP_I[i+1]))>>
+ (COS_LOOKUP_I_SHIFT-LSP_FRACBITS+14);
+}
+
+static const ogg_uint16_t barklook[54]={
+ 0,51,102,154, 206,258,311,365,
+ 420,477,535,594, 656,719,785,854,
+ 926,1002,1082,1166, 1256,1352,1454,1564,
+ 1683,1812,1953,2107, 2276,2463,2670,2900,
+ 3155,3440,3756,4106, 4493,4919,5387,5901,
+ 6466,7094,7798,8599, 9528,10623,11935,13524,
+ 15453,17775,20517,23667, 27183,31004
+};
+
+/* used in init only; interpolate the long way */
+static inline ogg_int32_t toBARK(int n){
+ int i;
+ for(i=0;i<54;i++)
+ if(n>=barklook[i] && n<barklook[i+1])break;
+
+ if(i==54){
+ return 54<<14;
+ }else{
+ return (i<<14)+(((n-barklook[i])*
+ ((1UL<<31)/(barklook[i+1]-barklook[i])))>>17);
+ }
+}
+
+static const unsigned char MLOOP_1[64]={
+ 0,10,11,11, 12,12,12,12, 13,13,13,13, 13,13,13,13,
+ 14,14,14,14, 14,14,14,14, 14,14,14,14, 14,14,14,14,
+ 15,15,15,15, 15,15,15,15, 15,15,15,15, 15,15,15,15,
+ 15,15,15,15, 15,15,15,15, 15,15,15,15, 15,15,15,15,
+};
+
+static const unsigned char MLOOP_2[64]={
+ 0,4,5,5, 6,6,6,6, 7,7,7,7, 7,7,7,7,
+ 8,8,8,8, 8,8,8,8, 8,8,8,8, 8,8,8,8,
+ 9,9,9,9, 9,9,9,9, 9,9,9,9, 9,9,9,9,
+ 9,9,9,9, 9,9,9,9, 9,9,9,9, 9,9,9,9,
+};
+
+static const unsigned char MLOOP_3[8]={0,1,2,2,3,3,3,3};
+
+void vorbis_lsp_to_curve(ogg_int32_t *curve,int n,int ln,
+ ogg_int32_t *lsp,int m,
+ ogg_int32_t amp,
+ ogg_int32_t ampoffset,
+ ogg_int32_t nyq){
+
+ /* 0 <= m < 256 */
+
+ /* set up for using all int later */
+ int i;
+ int ampoffseti=ampoffset*4096;
+ int ampi=amp;
+ ogg_int32_t *ilsp=(ogg_int32_t *)alloca(m*sizeof(*ilsp));
+
+ ogg_uint32_t inyq= (1UL<<31) / toBARK(nyq);
+ ogg_uint32_t imap= (1UL<<31) / ln;
+ ogg_uint32_t tBnyq1 = toBARK(nyq)<<1;
+
+ /* Besenham for frequency scale to avoid a division */
+ int f=0;
+ int fdx=n;
+ int fbase=nyq/fdx;
+ int ferr=0;
+ int fdy=nyq-fbase*fdx;
+ int map=0;
+
+#ifdef _LOW_ACCURACY_
+ ogg_uint32_t nextbark=((tBnyq1<<11)/ln)>>12;
+#else
+ ogg_uint32_t nextbark=MULT31(imap>>1,tBnyq1);
+#endif
+ int nextf=barklook[nextbark>>14]+(((nextbark&0x3fff)*
+ (barklook[(nextbark>>14)+1]-barklook[nextbark>>14]))>>14);
+
+ /* lsp is in 8.24, range 0 to PI; coslook wants it in .16 0 to 1*/
+ for(i=0;i<m;i++){
+#ifndef _LOW_ACCURACY_
+ ogg_int32_t val=MULT32(lsp[i],0x517cc2);
+#else
+ ogg_int32_t val=((lsp[i]>>10)*0x517d)>>14;
+#endif
+
+ /* safeguard against a malicious stream */
+ if(val<0 || (val>>COS_LOOKUP_I_SHIFT)>=COS_LOOKUP_I_SZ){
+ memset(curve,0,sizeof(*curve)*n);
+ return;
+ }
+
+ ilsp[i]=vorbis_coslook_i(val);
+ }
+
+ i=0;
+ while(i<n){
+ int j;
+ ogg_uint32_t pi=46341; /* 2**-.5 in 0.16 */
+ ogg_uint32_t qi=46341;
+ ogg_int32_t qexp=0,shift;
+ ogg_int32_t wi;
+
+ wi=vorbis_coslook2_i((map*imap)>>15);
+
+
+#ifdef _V_LSP_MATH_ASM
+ lsp_loop_asm(&qi,&pi,&qexp,ilsp,wi,m);
+
+ pi=((pi*pi)>>16);
+ qi=((qi*qi)>>16);
+
+ if(m&1){
+ qexp= qexp*2-28*((m+1)>>1)+m;
+ pi*=(1<<14)-((wi*wi)>>14);
+ qi+=pi>>14;
+ }else{
+ qexp= qexp*2-13*m;
+
+ pi*=(1<<14)-wi;
+ qi*=(1<<14)+wi;
+
+ qi=(qi+pi)>>14;
+ }
+
+ if(qi&0xffff0000){ /* checks for 1.xxxxxxxxxxxxxxxx */
+ qi>>=1; qexp++;
+ }else
+ lsp_norm_asm(&qi,&qexp);
+
+#else
+
+ qi*=labs(ilsp[0]-wi);
+ pi*=labs(ilsp[1]-wi);
+
+ for(j=3;j<m;j+=2){
+ if(!(shift=MLOOP_1[(pi|qi)>>25]))
+ if(!(shift=MLOOP_2[(pi|qi)>>19]))
+ shift=MLOOP_3[(pi|qi)>>16];
+
+ qi=(qi>>shift)*labs(ilsp[j-1]-wi);
+ pi=(pi>>shift)*labs(ilsp[j]-wi);
+ qexp+=shift;
+ }
+ if(!(shift=MLOOP_1[(pi|qi)>>25]))
+ if(!(shift=MLOOP_2[(pi|qi)>>19]))
+ shift=MLOOP_3[(pi|qi)>>16];
+
+ /* pi,qi normalized collectively, both tracked using qexp */
+
+ if(m&1){
+ /* odd order filter; slightly assymetric */
+ /* the last coefficient */
+ qi=(qi>>shift)*labs(ilsp[j-1]-wi);
+ pi=(pi>>shift)<<14;
+ qexp+=shift;
+
+ if(!(shift=MLOOP_1[(pi|qi)>>25]))
+ if(!(shift=MLOOP_2[(pi|qi)>>19]))
+ shift=MLOOP_3[(pi|qi)>>16];
+
+ pi>>=shift;
+ qi>>=shift;
+ qexp+=shift-14*((m+1)>>1);
+
+ pi=((pi*pi)>>16);
+ qi=((qi*qi)>>16);
+ qexp=qexp*2+m;
+
+ pi*=(1<<14)-((wi*wi)>>14);
+ qi+=pi>>14;
+
+ }else{
+ /* even order filter; still symmetric */
+
+ /* p*=p(1-w), q*=q(1+w), let normalization drift because it isn't
+ worth tracking step by step */
+
+ pi>>=shift;
+ qi>>=shift;
+ qexp+=shift-7*m;
+
+ pi=((pi*pi)>>16);
+ qi=((qi*qi)>>16);
+ qexp=qexp*2+m;
+
+ pi*=(1<<14)-wi;
+ qi*=(1<<14)+wi;
+ qi=(qi+pi)>>14;
+
+ }
+
+
+ /* we've let the normalization drift because it wasn't important;
+ however, for the lookup, things must be normalized again. We
+ need at most one right shift or a number of left shifts */
+
+ if(qi&0xffff0000){ /* checks for 1.xxxxxxxxxxxxxxxx */
+ qi>>=1; qexp++;
+ }else
+ while(qi && !(qi&0x8000)){ /* checks for 0.0xxxxxxxxxxxxxxx or less*/
+ qi<<=1; qexp--;
+ }
+
+#endif
+
+ amp=vorbis_fromdBlook_i(ampi* /* n.4 */
+ vorbis_invsqlook_i(qi,qexp)-
+ /* m.8, m+n<=8 */
+ ampoffseti); /* 8.12[0] */
+
+#ifdef _LOW_ACCURACY_
+ amp>>=9;
+#endif
+ curve[i]= MULT31_SHIFT15(curve[i],amp);
+
+ while(++i<n){
+
+ /* line plot to get new f */
+ ferr+=fdy;
+ if(ferr>=fdx){
+ ferr-=fdx;
+ f++;
+ }
+ f+=fbase;
+
+ if(f>=nextf)break;
+
+ curve[i]= MULT31_SHIFT15(curve[i],amp);
+ }
+
+ while(1){
+ map++;
+
+ if(map+1<ln){
+
+#ifdef _LOW_ACCURACY_
+ nextbark=((tBnyq1<<11)/ln*(map+1))>>12;
+#else
+ nextbark=MULT31((map+1)*(imap>>1),tBnyq1);
+#endif
+ nextf=barklook[nextbark>>14]+
+ (((nextbark&0x3fff)*
+ (barklook[(nextbark>>14)+1]-barklook[nextbark>>14]))>>14);
+ if(f<=nextf)break;
+
+ }else{
+ nextf=9999999;
+ break;
+ }
+ }
+ if(map>=ln){
+ map=ln-1; /* guard against the approximation */
+ nextf=9999999;
+ }
+ }
+}
+
+/*************** vorbis decode glue ************/
+
+void floor0_free_info(vorbis_info_floor *i){
+ vorbis_info_floor0 *info=(vorbis_info_floor0 *)i;
+ if(info)_ogg_free(info);
+}
+
+vorbis_info_floor *floor0_info_unpack (vorbis_info *vi,oggpack_buffer *opb){
+ codec_setup_info *ci=(codec_setup_info *)vi->codec_setup;
+ int j;
+
+ vorbis_info_floor0 *info=(vorbis_info_floor0 *)_ogg_malloc(sizeof(*info));
+ info->order=oggpack_read(opb,8);
+ info->rate=oggpack_read(opb,16);
+ info->barkmap=oggpack_read(opb,16);
+ info->ampbits=oggpack_read(opb,6);
+ info->ampdB=oggpack_read(opb,8);
+ info->numbooks=oggpack_read(opb,4)+1;
+
+ if(info->order<1)goto err_out;
+ if(info->rate<1)goto err_out;
+ if(info->barkmap<1)goto err_out;
+
+ for(j=0;j<info->numbooks;j++){
+ info->books[j]=oggpack_read(opb,8);
+ if(info->books[j]>=ci->books)goto err_out;
+ }
+
+ if(oggpack_eop(opb))goto err_out;
+ return(info);
+
+ err_out:
+ floor0_free_info(info);
+ return(NULL);
+}
+
+int floor0_memosize(vorbis_info_floor *i){
+ vorbis_info_floor0 *info=(vorbis_info_floor0 *)i;
+ return info->order+1;
+}
+
+ogg_int32_t *floor0_inverse1(vorbis_dsp_state *vd,vorbis_info_floor *i,
+ ogg_int32_t *lsp){
+ vorbis_info_floor0 *info=(vorbis_info_floor0 *)i;
+ int j,k;
+
+ int ampraw=oggpack_read(&vd->opb,info->ampbits);
+ if(ampraw>0){ /* also handles the -1 out of data case */
+ long maxval=(1<<info->ampbits)-1;
+ int amp=((ampraw*info->ampdB)<<4)/maxval;
+ int booknum=oggpack_read(&vd->opb,_ilog(info->numbooks));
+
+ if(booknum!=-1 && booknum<info->numbooks){ /* be paranoid */
+ codec_setup_info *ci=(codec_setup_info *)vd->vi->codec_setup;
+ codebook *b=ci->book_param+info->books[booknum];
+ ogg_int32_t last=0;
+
+ for(j=0;j<info->order;j+=b->dim)
+ if(vorbis_book_decodev_set(b,lsp+j,&vd->opb,b->dim,-24)==-1)goto eop;
+ for(j=0;j<info->order;){
+ for(k=0;k<b->dim;k++,j++)lsp[j]+=last;
+ last=lsp[j-1];
+ }
+
+ lsp[info->order]=amp;
+ return(lsp);
+ }
+ }
+ eop:
+ return(NULL);
+}
+
+int floor0_inverse2(vorbis_dsp_state *vd,vorbis_info_floor *i,
+ ogg_int32_t *lsp,ogg_int32_t *out){
+ vorbis_info_floor0 *info=(vorbis_info_floor0 *)i;
+ codec_setup_info *ci=(codec_setup_info *)vd->vi->codec_setup;
+
+ if(lsp){
+ ogg_int32_t amp=lsp[info->order];
+
+ /* take the coefficients back to a spectral envelope curve */
+ vorbis_lsp_to_curve(out,ci->blocksizes[vd->W]/2,info->barkmap,
+ lsp,info->order,amp,info->ampdB,
+ info->rate>>1);
+ return(1);
+ }
+ memset(out,0,sizeof(*out)*ci->blocksizes[vd->W]/2);
+ return(0);
+}
+
diff --git a/library/ADK2/v_floor1.c b/library/ADK2/v_floor1.c
new file mode 100644
index 0000000..ecd340b
--- /dev/null
+++ b/library/ADK2/v_floor1.c
@@ -0,0 +1,353 @@
+#define ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: floor backend 1 implementation
+
+ ********************************************************************/
+
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+#include "v_ogg.h"
+#include "v_ivorbiscodec.h"
+#include "v_codec_internal.h"
+#include "v_codebook.h"
+#include "v_misc.h"
+
+extern const ogg_int32_t FLOOR_fromdB_LOOKUP[];
+#define floor1_rangedB 140 /* floor 1 fixed at -140dB to 0dB range */
+#define VIF_POSIT 63
+
+/***********************************************/
+
+void floor1_free_info(vorbis_info_floor *i){
+ vorbis_info_floor1 *info=(vorbis_info_floor1 *)i;
+ if(info){
+ if(info->class)_ogg_free(info->class);
+ if(info->partitionclass)_ogg_free(info->partitionclass);
+ if(info->postlist)_ogg_free(info->postlist);
+ if(info->forward_index)_ogg_free(info->forward_index);
+ if(info->hineighbor)_ogg_free(info->hineighbor);
+ if(info->loneighbor)_ogg_free(info->loneighbor);
+ memset(info,0,sizeof(*info));
+ _ogg_free(info);
+ }
+}
+
+static int ilog(unsigned int v){
+ int ret=0;
+ while(v){
+ ret++;
+ v>>=1;
+ }
+ return(ret);
+}
+
+static void vorbis_mergesort(char *index,ogg_uint16_t *vals,ogg_uint16_t n){
+ ogg_uint16_t i,j;
+ char *temp,*A=index,*B=_ogg_malloc(n*sizeof(*B));
+
+ for(i=1;i<n;i<<=1){
+ for(j=0;j+i<n;){
+ int k1=j;
+ int mid=j+i;
+ int k2=mid;
+ int end=(j+i*2<n?j+i*2:n);
+ while(k1<mid && k2<end){
+ if(vals[A[k1]]<vals[A[k2]])
+ B[j++]=A[k1++];
+ else
+ B[j++]=A[k2++];
+ }
+ while(k1<mid) B[j++]=A[k1++];
+ while(k2<end) B[j++]=A[k2++];
+ }
+ for(;j<n;j++)B[j]=A[j];
+ temp=A;A=B;B=temp;
+ }
+
+ if(B==index){
+ for(j=0;j<n;j++)B[j]=A[j];
+ _ogg_free(A);
+ }else
+ _ogg_free(B);
+}
+
+
+vorbis_info_floor *floor1_info_unpack (vorbis_info *vi,oggpack_buffer *opb){
+ codec_setup_info *ci=(codec_setup_info *)vi->codec_setup;
+ int j,k,count=0,maxclass=-1,rangebits;
+
+ vorbis_info_floor1 *info=(vorbis_info_floor1 *)_ogg_calloc(1,sizeof(*info));
+ /* read partitions */
+ info->partitions=oggpack_read(opb,5); /* only 0 to 31 legal */
+ info->partitionclass=
+ (char *)_ogg_malloc(info->partitions*sizeof(*info->partitionclass));
+ for(j=0;j<info->partitions;j++){
+ info->partitionclass[j]=oggpack_read(opb,4); /* only 0 to 15 legal */
+ if(maxclass<info->partitionclass[j])maxclass=info->partitionclass[j];
+ }
+
+ /* read partition classes */
+ info->class=
+ (floor1class *)_ogg_malloc((maxclass+1)*sizeof(*info->class));
+ for(j=0;j<maxclass+1;j++){
+ info->class[j].class_dim=oggpack_read(opb,3)+1; /* 1 to 8 */
+ info->class[j].class_subs=oggpack_read(opb,2); /* 0,1,2,3 bits */
+ if(oggpack_eop(opb)<0) goto err_out;
+ if(info->class[j].class_subs)
+ info->class[j].class_book=oggpack_read(opb,8);
+ else
+ info->class[j].class_book=0;
+ if(info->class[j].class_book>=ci->books)goto err_out;
+ for(k=0;k<(1<<info->class[j].class_subs);k++){
+ info->class[j].class_subbook[k]=oggpack_read(opb,8)-1;
+ if(info->class[j].class_subbook[k]>=ci->books &&
+ info->class[j].class_subbook[k]!=0xff)goto err_out;
+ }
+ }
+
+ /* read the post list */
+ info->mult=oggpack_read(opb,2)+1; /* only 1,2,3,4 legal now */
+ rangebits=oggpack_read(opb,4);
+
+ for(j=0,k=0;j<info->partitions;j++)
+ count+=info->class[info->partitionclass[j]].class_dim;
+ info->postlist=
+ (ogg_uint16_t *)_ogg_malloc((count+2)*sizeof(*info->postlist));
+ info->forward_index=
+ (char *)_ogg_malloc((count+2)*sizeof(*info->forward_index));
+ info->loneighbor=
+ (char *)_ogg_malloc(count*sizeof(*info->loneighbor));
+ info->hineighbor=
+ (char *)_ogg_malloc(count*sizeof(*info->hineighbor));
+
+ count=0;
+ for(j=0,k=0;j<info->partitions;j++){
+ count+=info->class[info->partitionclass[j]].class_dim;
+ if(count>VIF_POSIT)goto err_out;
+ for(;k<count;k++){
+ int t=info->postlist[k+2]=oggpack_read(opb,rangebits);
+ if(t>=(1<<rangebits))goto err_out;
+ }
+ }
+ if(oggpack_eop(opb))goto err_out;
+ info->postlist[0]=0;
+ info->postlist[1]=1<<rangebits;
+ info->posts=count+2;
+
+ /* also store a sorted position index */
+ for(j=0;j<info->posts;j++)info->forward_index[j]=j;
+ vorbis_mergesort(info->forward_index,info->postlist,info->posts);
+
+ /* discover our neighbors for decode where we don't use fit flags
+ (that would push the neighbors outward) */
+ for(j=0;j<info->posts-2;j++){
+ int lo=0;
+ int hi=1;
+ int lx=0;
+ int hx=info->postlist[1];
+ int currentx=info->postlist[j+2];
+ for(k=0;k<j+2;k++){
+ int x=info->postlist[k];
+ if(x>lx && x<currentx){
+ lo=k;
+ lx=x;
+ }
+ if(x<hx && x>currentx){
+ hi=k;
+ hx=x;
+ }
+ }
+ info->loneighbor[j]=lo;
+ info->hineighbor[j]=hi;
+ }
+
+ return(info);
+
+ err_out:
+ floor1_free_info(info);
+ return(NULL);
+}
+
+static int render_point(int x0,int x1,int y0,int y1,int x){
+ y0&=0x7fff; /* mask off flag */
+ y1&=0x7fff;
+
+ {
+ int dy=y1-y0;
+ int adx=x1-x0;
+ int ady=abs(dy);
+ int err=ady*(x-x0);
+
+ int off=err/adx;
+ if(dy<0)return(y0-off);
+ return(y0+off);
+ }
+}
+
+static void render_line(int n,int x0,int x1,int y0,int y1,ogg_int32_t *d){
+ int dy=y1-y0;
+ int adx=x1-x0;
+ int ady=abs(dy);
+ int base=dy/adx;
+ int sy=(dy<0?base-1:base+1);
+ int x=x0;
+ int y=y0;
+ int err=0;
+
+ if(n>x1)n=x1;
+ ady-=abs(base*adx);
+
+ if(x<n)
+ d[x]= MULT31_SHIFT15(d[x],FLOOR_fromdB_LOOKUP[y]);
+
+ while(++x<n){
+ err=err+ady;
+ if(err>=adx){
+ err-=adx;
+ y+=sy;
+ }else{
+ y+=base;
+ }
+ d[x]= MULT31_SHIFT15(d[x],FLOOR_fromdB_LOOKUP[y]);
+ }
+}
+
+int floor1_memosize(vorbis_info_floor *i){
+ vorbis_info_floor1 *info=(vorbis_info_floor1 *)i;
+ return info->posts;
+}
+
+static int quant_look[4]={256,128,86,64};
+
+ogg_int32_t *floor1_inverse1(vorbis_dsp_state *vd,vorbis_info_floor *in,
+ ogg_int32_t *fit_value){
+ vorbis_info_floor1 *info=(vorbis_info_floor1 *)in;
+ codec_setup_info *ci=(codec_setup_info *)vd->vi->codec_setup;
+
+ int i,j,k;
+ codebook *books=ci->book_param;
+ int quant_q=quant_look[info->mult-1];
+
+ /* unpack wrapped/predicted values from stream */
+ if(oggpack_read(&vd->opb,1)==1){
+ fit_value[0]=oggpack_read(&vd->opb,ilog(quant_q-1));
+ fit_value[1]=oggpack_read(&vd->opb,ilog(quant_q-1));
+
+ /* partition by partition */
+ /* partition by partition */
+ for(i=0,j=2;i<info->partitions;i++){
+ int classv=info->partitionclass[i];
+ int cdim=info->class[classv].class_dim;
+ int csubbits=info->class[classv].class_subs;
+ int csub=1<<csubbits;
+ int cval=0;
+
+ /* decode the partition's first stage cascade value */
+ if(csubbits){
+ cval=vorbis_book_decode(books+info->class[classv].class_book,&vd->opb);
+
+ if(cval==-1)goto eop;
+ }
+
+ for(k=0;k<cdim;k++){
+ int book=info->class[classv].class_subbook[cval&(csub-1)];
+ cval>>=csubbits;
+ if(book!=0xff){
+ if((fit_value[j+k]=vorbis_book_decode(books+book,&vd->opb))==-1)
+ goto eop;
+ }else{
+ fit_value[j+k]=0;
+ }
+ }
+ j+=cdim;
+ }
+
+ /* unwrap positive values and reconsitute via linear interpolation */
+ for(i=2;i<info->posts;i++){
+ int predicted=render_point(info->postlist[info->loneighbor[i-2]],
+ info->postlist[info->hineighbor[i-2]],
+ fit_value[info->loneighbor[i-2]],
+ fit_value[info->hineighbor[i-2]],
+ info->postlist[i]);
+ int hiroom=quant_q-predicted;
+ int loroom=predicted;
+ int room=(hiroom<loroom?hiroom:loroom)<<1;
+ int val=fit_value[i];
+
+ if(val){
+ if(val>=room){
+ if(hiroom>loroom){
+ val = val-loroom;
+ }else{
+ val = -1-(val-hiroom);
+ }
+ }else{
+ if(val&1){
+ val= -((val+1)>>1);
+ }else{
+ val>>=1;
+ }
+ }
+
+ fit_value[i]=val+predicted;
+ fit_value[info->loneighbor[i-2]]&=0x7fff;
+ fit_value[info->hineighbor[i-2]]&=0x7fff;
+
+ }else{
+ fit_value[i]=predicted|0x8000;
+ }
+
+ }
+
+ return(fit_value);
+ }
+ eop:
+ return(NULL);
+}
+
+int floor1_inverse2(vorbis_dsp_state *vd,vorbis_info_floor *in,
+ ogg_int32_t *fit_value,ogg_int32_t *out){
+ vorbis_info_floor1 *info=(vorbis_info_floor1 *)in;
+
+ codec_setup_info *ci=(codec_setup_info *)vd->vi->codec_setup;
+ int n=ci->blocksizes[vd->W]/2;
+ int j;
+
+ if(fit_value){
+ /* render the lines */
+ int hx=0;
+ int lx=0;
+ int ly=fit_value[0]*info->mult;
+ for(j=1;j<info->posts;j++){
+ int current=info->forward_index[j];
+ int hy=fit_value[current]&0x7fff;
+ if(hy==fit_value[current]){
+
+ hy*=info->mult;
+ hx=info->postlist[current];
+
+ render_line(n,lx,hx,ly,hy,out);
+
+ lx=hx;
+ ly=hy;
+ }
+ }
+ for(j=hx;j<n;j++)out[j]*=ly; /* be certain */
+ return(1);
+ }
+ memset(out,0,sizeof(*out)*n);
+ return(0);
+}
diff --git a/library/ADK2/v_floor_lookup.c b/library/ADK2/v_floor_lookup.c
new file mode 100644
index 0000000..f88d096
--- /dev/null
+++ b/library/ADK2/v_floor_lookup.c
@@ -0,0 +1,93 @@
+#define ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: floor dB lookup
+
+ ********************************************************************/
+
+#include "v_os.h"
+
+#ifdef _LOW_ACCURACY_
+# define XdB(n) ((((n)>>8)+1)>>1)
+#else
+# define XdB(n) (n)
+#endif
+
+const ogg_int32_t FLOOR_fromdB_LOOKUP[256]={
+ XdB(0x000000e5), XdB(0x000000f4), XdB(0x00000103), XdB(0x00000114),
+ XdB(0x00000126), XdB(0x00000139), XdB(0x0000014e), XdB(0x00000163),
+ XdB(0x0000017a), XdB(0x00000193), XdB(0x000001ad), XdB(0x000001c9),
+ XdB(0x000001e7), XdB(0x00000206), XdB(0x00000228), XdB(0x0000024c),
+ XdB(0x00000272), XdB(0x0000029b), XdB(0x000002c6), XdB(0x000002f4),
+ XdB(0x00000326), XdB(0x0000035a), XdB(0x00000392), XdB(0x000003cd),
+ XdB(0x0000040c), XdB(0x00000450), XdB(0x00000497), XdB(0x000004e4),
+ XdB(0x00000535), XdB(0x0000058c), XdB(0x000005e8), XdB(0x0000064a),
+ XdB(0x000006b3), XdB(0x00000722), XdB(0x00000799), XdB(0x00000818),
+ XdB(0x0000089e), XdB(0x0000092e), XdB(0x000009c6), XdB(0x00000a69),
+ XdB(0x00000b16), XdB(0x00000bcf), XdB(0x00000c93), XdB(0x00000d64),
+ XdB(0x00000e43), XdB(0x00000f30), XdB(0x0000102d), XdB(0x0000113a),
+ XdB(0x00001258), XdB(0x0000138a), XdB(0x000014cf), XdB(0x00001629),
+ XdB(0x0000179a), XdB(0x00001922), XdB(0x00001ac4), XdB(0x00001c82),
+ XdB(0x00001e5c), XdB(0x00002055), XdB(0x0000226f), XdB(0x000024ac),
+ XdB(0x0000270e), XdB(0x00002997), XdB(0x00002c4b), XdB(0x00002f2c),
+ XdB(0x0000323d), XdB(0x00003581), XdB(0x000038fb), XdB(0x00003caf),
+ XdB(0x000040a0), XdB(0x000044d3), XdB(0x0000494c), XdB(0x00004e10),
+ XdB(0x00005323), XdB(0x0000588a), XdB(0x00005e4b), XdB(0x0000646b),
+ XdB(0x00006af2), XdB(0x000071e5), XdB(0x0000794c), XdB(0x0000812e),
+ XdB(0x00008993), XdB(0x00009283), XdB(0x00009c09), XdB(0x0000a62d),
+ XdB(0x0000b0f9), XdB(0x0000bc79), XdB(0x0000c8b9), XdB(0x0000d5c4),
+ XdB(0x0000e3a9), XdB(0x0000f274), XdB(0x00010235), XdB(0x000112fd),
+ XdB(0x000124dc), XdB(0x000137e4), XdB(0x00014c29), XdB(0x000161bf),
+ XdB(0x000178bc), XdB(0x00019137), XdB(0x0001ab4a), XdB(0x0001c70e),
+ XdB(0x0001e4a1), XdB(0x0002041f), XdB(0x000225aa), XdB(0x00024962),
+ XdB(0x00026f6d), XdB(0x000297f0), XdB(0x0002c316), XdB(0x0002f109),
+ XdB(0x000321f9), XdB(0x00035616), XdB(0x00038d97), XdB(0x0003c8b4),
+ XdB(0x000407a7), XdB(0x00044ab2), XdB(0x00049218), XdB(0x0004de23),
+ XdB(0x00052f1e), XdB(0x0005855c), XdB(0x0005e135), XdB(0x00064306),
+ XdB(0x0006ab33), XdB(0x00071a24), XdB(0x0007904b), XdB(0x00080e20),
+ XdB(0x00089422), XdB(0x000922da), XdB(0x0009bad8), XdB(0x000a5cb6),
+ XdB(0x000b091a), XdB(0x000bc0b1), XdB(0x000c8436), XdB(0x000d5471),
+ XdB(0x000e3233), XdB(0x000f1e5f), XdB(0x001019e4), XdB(0x001125c1),
+ XdB(0x00124306), XdB(0x001372d5), XdB(0x0014b663), XdB(0x00160ef7),
+ XdB(0x00177df0), XdB(0x001904c1), XdB(0x001aa4f9), XdB(0x001c603d),
+ XdB(0x001e384f), XdB(0x00202f0f), XdB(0x0022467a), XdB(0x002480b1),
+ XdB(0x0026dff7), XdB(0x002966b3), XdB(0x002c1776), XdB(0x002ef4fc),
+ XdB(0x0032022d), XdB(0x00354222), XdB(0x0038b828), XdB(0x003c67c2),
+ XdB(0x004054ae), XdB(0x004482e8), XdB(0x0048f6af), XdB(0x004db488),
+ XdB(0x0052c142), XdB(0x005821ff), XdB(0x005ddc33), XdB(0x0063f5b0),
+ XdB(0x006a74a7), XdB(0x00715faf), XdB(0x0078bdce), XdB(0x0080967f),
+ XdB(0x0088f1ba), XdB(0x0091d7f9), XdB(0x009b5247), XdB(0x00a56a41),
+ XdB(0x00b02a27), XdB(0x00bb9ce2), XdB(0x00c7ce12), XdB(0x00d4ca17),
+ XdB(0x00e29e20), XdB(0x00f15835), XdB(0x0101074b), XdB(0x0111bb4e),
+ XdB(0x01238531), XdB(0x01367704), XdB(0x014aa402), XdB(0x016020a7),
+ XdB(0x017702c3), XdB(0x018f6190), XdB(0x01a955cb), XdB(0x01c4f9cf),
+ XdB(0x01e269a8), XdB(0x0201c33b), XdB(0x0223265a), XdB(0x0246b4ea),
+ XdB(0x026c9302), XdB(0x0294e716), XdB(0x02bfda13), XdB(0x02ed9793),
+ XdB(0x031e4e09), XdB(0x03522ee4), XdB(0x03896ed0), XdB(0x03c445e2),
+ XdB(0x0402efd6), XdB(0x0445ac4b), XdB(0x048cbefc), XdB(0x04d87013),
+ XdB(0x05290c67), XdB(0x057ee5ca), XdB(0x05da5364), XdB(0x063bb204),
+ XdB(0x06a36485), XdB(0x0711d42b), XdB(0x0787710e), XdB(0x0804b299),
+ XdB(0x088a17ef), XdB(0x0918287e), XdB(0x09af747c), XdB(0x0a50957e),
+ XdB(0x0afc2f19), XdB(0x0bb2ef7f), XdB(0x0c759034), XdB(0x0d44d6ca),
+ XdB(0x0e2195bc), XdB(0x0f0cad0d), XdB(0x10070b62), XdB(0x1111aeea),
+ XdB(0x122da66c), XdB(0x135c120f), XdB(0x149e24d9), XdB(0x15f525b1),
+ XdB(0x176270e3), XdB(0x18e7794b), XdB(0x1a85c9ae), XdB(0x1c3f06d1),
+ XdB(0x1e14f07d), XdB(0x200963d7), XdB(0x221e5ccd), XdB(0x2455f870),
+ XdB(0x26b2770b), XdB(0x29363e2b), XdB(0x2be3db5c), XdB(0x2ebe06b6),
+ XdB(0x31c7a55b), XdB(0x3503ccd4), XdB(0x3875c5aa), XdB(0x3c210f44),
+ XdB(0x4009632b), XdB(0x4432b8cf), XdB(0x48a149bc), XdB(0x4d59959e),
+ XdB(0x52606733), XdB(0x57bad899), XdB(0x5d6e593a), XdB(0x6380b298),
+ XdB(0x69f80e9a), XdB(0x70dafda8), XdB(0x78307d76), XdB(0x7fffffff),
+};
+
diff --git a/library/ADK2/v_framing.c b/library/ADK2/v_framing.c
new file mode 100644
index 0000000..58fdbf7
--- /dev/null
+++ b/library/ADK2/v_framing.c
@@ -0,0 +1,1118 @@
+#define ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: decode Ogg streams back into raw packets
+
+ note: The CRC code is directly derived from public domain code by
+ Ross Williams (ross@guest.adelaide.edu.au). See docs/framing.html
+ for details.
+
+ ********************************************************************/
+
+#include <stdlib.h>
+#include <string.h>
+#include "v_ogg.h"
+#include "v_misc.h"
+
+
+/* A complete description of Ogg framing exists in docs/framing.html */
+
+/* basic, centralized Ogg memory management based on linked lists of
+ references to refcounted memory buffers. References and buffers
+ are both recycled. Buffers are passed around and consumed in
+ reference form. */
+
+static ogg_buffer_state *ogg_buffer_create(void){
+ ogg_buffer_state *bs=_ogg_calloc(1,sizeof(*bs));
+ return bs;
+}
+
+/* destruction is 'lazy'; there may be memory references outstanding,
+ and yanking the buffer state out from underneath would be
+ antisocial. Dealloc what is currently unused and have
+ _release_one watch for the stragglers to come in. When they do,
+ finish destruction. */
+
+/* call the helper while holding lock */
+static void _ogg_buffer_destroy(ogg_buffer_state *bs){
+ ogg_buffer *bt;
+ ogg_reference *rt;
+
+ if(bs->shutdown){
+
+ bt=bs->unused_buffers;
+ rt=bs->unused_references;
+
+ while(bt){
+ ogg_buffer *b=bt;
+ bt=b->ptr.next;
+ if(b->data)_ogg_free(b->data);
+ _ogg_free(b);
+ }
+ bs->unused_buffers=0;
+ while(rt){
+ ogg_reference *r=rt;
+ rt=r->next;
+ _ogg_free(r);
+ }
+ bs->unused_references=0;
+
+ if(!bs->outstanding)
+ _ogg_free(bs);
+
+ }
+}
+
+static void ogg_buffer_destroy(ogg_buffer_state *bs){
+ bs->shutdown=1;
+ _ogg_buffer_destroy(bs);
+}
+
+static ogg_buffer *_fetch_buffer(ogg_buffer_state *bs,long bytes){
+ ogg_buffer *ob;
+ bs->outstanding++;
+
+ /* do we have an unused buffer sitting in the pool? */
+ if(bs->unused_buffers){
+ ob=bs->unused_buffers;
+ bs->unused_buffers=ob->ptr.next;
+
+ /* if the unused buffer is too small, grow it */
+ if(ob->size<bytes){
+ ob->data=_ogg_realloc(ob->data,bytes);
+ ob->size=bytes;
+ }
+ }else{
+ /* allocate a new buffer */
+ ob=_ogg_malloc(sizeof(*ob));
+ ob->data=_ogg_malloc(bytes<16?16:bytes);
+ ob->size=bytes;
+ }
+
+ ob->refcount=1;
+ ob->ptr.owner=bs;
+ return ob;
+}
+
+static ogg_reference *_fetch_ref(ogg_buffer_state *bs){
+ ogg_reference *or;
+ bs->outstanding++;
+
+ /* do we have an unused reference sitting in the pool? */
+ if(bs->unused_references){
+ or=bs->unused_references;
+ bs->unused_references=or->next;
+ }else{
+ /* allocate a new reference */
+ or=_ogg_malloc(sizeof(*or));
+ }
+
+ or->begin=0;
+ or->length=0;
+ or->next=0;
+ return or;
+}
+
+/* fetch a reference pointing to a fresh, initially continguous buffer
+ of at least [bytes] length */
+static ogg_reference *ogg_buffer_alloc(ogg_buffer_state *bs,long bytes){
+ ogg_buffer *ob=_fetch_buffer(bs,bytes);
+ ogg_reference *or=_fetch_ref(bs);
+ or->buffer=ob;
+ return or;
+}
+
+/* enlarge the data buffer in the current link */
+static void ogg_buffer_realloc(ogg_reference *or,long bytes){
+ ogg_buffer *ob=or->buffer;
+
+ /* if the unused buffer is too small, grow it */
+ if(ob->size<bytes){
+ ob->data=_ogg_realloc(ob->data,bytes);
+ ob->size=bytes;
+ }
+}
+
+static void _ogg_buffer_mark_one(ogg_reference *or){
+ or->buffer->refcount++;
+}
+
+/* increase the refcount of the buffers to which the reference points */
+static void ogg_buffer_mark(ogg_reference *or){
+ while(or){
+ _ogg_buffer_mark_one(or);
+ or=or->next;
+ }
+}
+
+/* duplicate a reference (pointing to the same actual buffer memory)
+ and increment buffer refcount. If the desired segment is zero
+ length, a zero length ref is returned. */
+static ogg_reference *ogg_buffer_sub(ogg_reference *or,long length){
+ ogg_reference *ret=0,*head=0;
+
+ /* duplicate the reference chain; increment refcounts */
+ while(or && length){
+ ogg_reference *temp=_fetch_ref(or->buffer->ptr.owner);
+ if(head)
+ head->next=temp;
+ else
+ ret=temp;
+ head=temp;
+ head->buffer=or->buffer;
+ head->begin=or->begin;
+ head->length=length;
+ if(head->length>or->length)
+ head->length=or->length;
+
+ length-=head->length;
+ or=or->next;
+ }
+
+ ogg_buffer_mark(ret);
+ return ret;
+}
+
+ogg_reference *ogg_buffer_dup(ogg_reference *or){
+ ogg_reference *ret=0,*head=0;
+ /* duplicate the reference chain; increment refcounts */
+ while(or){
+ ogg_reference *temp=_fetch_ref(or->buffer->ptr.owner);
+ if(head)
+ head->next=temp;
+ else
+ ret=temp;
+ head=temp;
+ head->buffer=or->buffer;
+ head->begin=or->begin;
+ head->length=or->length;
+ or=or->next;
+ }
+
+ ogg_buffer_mark(ret);
+ return ret;
+}
+
+/* split a reference into two references; 'return' is a reference to
+ the buffer preceeding pos and 'head'/'tail' are the buffer past the
+ split. If pos is at or past the end of the passed in segment,
+ 'head/tail' are NULL */
+static ogg_reference *ogg_buffer_split(ogg_reference **tail,
+ ogg_reference **head,long pos){
+
+ /* walk past any preceeding fragments to one of:
+ a) the exact boundary that seps two fragments
+ b) the fragment that needs split somewhere in the middle */
+ ogg_reference *ret=*tail;
+ ogg_reference *or=*tail;
+
+ while(or && pos>or->length){
+ pos-=or->length;
+ or=or->next;
+ }
+
+ if(!or || pos==0){
+
+ return 0;
+
+ }else{
+
+ if(pos>=or->length){
+ /* exact split, or off the end? */
+ if(or->next){
+
+ /* a split */
+ *tail=or->next;
+ or->next=0;
+
+ }else{
+
+ /* off or at the end */
+ *tail=*head=0;
+
+ }
+ }else{
+
+ /* split within a fragment */
+ long lengthA=pos;
+ long beginB=or->begin+pos;
+ long lengthB=or->length-pos;
+
+ /* make a new reference to tail the second piece */
+ *tail=_fetch_ref(or->buffer->ptr.owner);
+
+ (*tail)->buffer=or->buffer;
+ (*tail)->begin=beginB;
+ (*tail)->length=lengthB;
+ (*tail)->next=or->next;
+ _ogg_buffer_mark_one(*tail);
+ if(head && or==*head)*head=*tail;
+
+ /* update the first piece */
+ or->next=0;
+ or->length=lengthA;
+
+ }
+ }
+ return ret;
+}
+
+static void ogg_buffer_release_one(ogg_reference *or){
+ ogg_buffer *ob=or->buffer;
+ ogg_buffer_state *bs=ob->ptr.owner;
+
+ ob->refcount--;
+ if(ob->refcount==0){
+ bs->outstanding--; /* for the returned buffer */
+ ob->ptr.next=bs->unused_buffers;
+ bs->unused_buffers=ob;
+ }
+
+ bs->outstanding--; /* for the returned reference */
+ or->next=bs->unused_references;
+ bs->unused_references=or;
+
+ _ogg_buffer_destroy(bs); /* lazy cleanup (if needed) */
+
+}
+
+/* release the references, decrease the refcounts of buffers to which
+ they point, release any buffers with a refcount that drops to zero */
+static void ogg_buffer_release(ogg_reference *or){
+ while(or){
+ ogg_reference *next=or->next;
+ ogg_buffer_release_one(or);
+ or=next;
+ }
+}
+
+static ogg_reference *ogg_buffer_pretruncate(ogg_reference *or,long pos){
+ /* release preceeding fragments we don't want */
+ while(or && pos>=or->length){
+ ogg_reference *next=or->next;
+ pos-=or->length;
+ ogg_buffer_release_one(or);
+ or=next;
+ }
+ if (or) {
+ or->begin+=pos;
+ or->length-=pos;
+ }
+ return or;
+}
+
+static ogg_reference *ogg_buffer_walk(ogg_reference *or){
+ if(!or)return NULL;
+ while(or->next){
+ or=or->next;
+ }
+ return(or);
+}
+
+/* *head is appended to the front end (head) of *tail; both continue to
+ be valid pointers, with *tail at the tail and *head at the head */
+static ogg_reference *ogg_buffer_cat(ogg_reference *tail, ogg_reference *head){
+ if(!tail)return head;
+
+ while(tail->next){
+ tail=tail->next;
+ }
+ tail->next=head;
+ return ogg_buffer_walk(head);
+}
+
+static void _positionB(oggbyte_buffer *b,int pos){
+ if(pos<b->pos){
+ /* start at beginning, scan forward */
+ b->ref=b->baseref;
+ b->pos=0;
+ b->end=b->pos+b->ref->length;
+ b->ptr=b->ref->buffer->data+b->ref->begin;
+ }
+}
+
+static void _positionF(oggbyte_buffer *b,int pos){
+ /* scan forward for position */
+ while(pos>=b->end){
+ /* just seek forward */
+ b->pos+=b->ref->length;
+ b->ref=b->ref->next;
+ b->end=b->ref->length+b->pos;
+ b->ptr=b->ref->buffer->data+b->ref->begin;
+ }
+}
+
+static int oggbyte_init(oggbyte_buffer *b,ogg_reference *or){
+ memset(b,0,sizeof(*b));
+ if(or){
+ b->ref=b->baseref=or;
+ b->pos=0;
+ b->end=b->ref->length;
+ b->ptr=b->ref->buffer->data+b->ref->begin;
+ return 0;
+ }else
+ return -1;
+}
+
+static void oggbyte_set4(oggbyte_buffer *b,ogg_uint32_t val,int pos){
+ int i;
+ _positionB(b,pos);
+ for(i=0;i<4;i++){
+ _positionF(b,pos);
+ b->ptr[pos-b->pos]=val;
+ val>>=8;
+ ++pos;
+ }
+}
+
+static unsigned char oggbyte_read1(oggbyte_buffer *b,int pos){
+ _positionB(b,pos);
+ _positionF(b,pos);
+ return b->ptr[pos-b->pos];
+}
+
+static ogg_uint32_t oggbyte_read4(oggbyte_buffer *b,int pos){
+ ogg_uint32_t ret;
+ _positionB(b,pos);
+ _positionF(b,pos);
+ ret=b->ptr[pos-b->pos];
+ _positionF(b,++pos);
+ ret|=b->ptr[pos-b->pos]<<8;
+ _positionF(b,++pos);
+ ret|=b->ptr[pos-b->pos]<<16;
+ _positionF(b,++pos);
+ ret|=b->ptr[pos-b->pos]<<24;
+ return ret;
+}
+
+static ogg_int64_t oggbyte_read8(oggbyte_buffer *b,int pos){
+ ogg_int64_t ret;
+ unsigned char t[7];
+ int i;
+ _positionB(b,pos);
+ for(i=0;i<7;i++){
+ _positionF(b,pos);
+ t[i]=b->ptr[pos++ -b->pos];
+ }
+
+ _positionF(b,pos);
+ ret=b->ptr[pos-b->pos];
+
+ for(i=6;i>=0;--i)
+ ret= ret<<8 | t[i];
+
+ return ret;
+}
+
+/* Now we get to the actual framing code */
+
+int ogg_page_version(ogg_page *og){
+ oggbyte_buffer ob;
+ if(oggbyte_init(&ob,og->header))return -1;
+ return oggbyte_read1(&ob,4);
+}
+
+int ogg_page_continued(ogg_page *og){
+ oggbyte_buffer ob;
+ if(oggbyte_init(&ob,og->header))return -1;
+ return oggbyte_read1(&ob,5)&0x01;
+}
+
+int ogg_page_bos(ogg_page *og){
+ oggbyte_buffer ob;
+ if(oggbyte_init(&ob,og->header))return -1;
+ return oggbyte_read1(&ob,5)&0x02;
+}
+
+int ogg_page_eos(ogg_page *og){
+ oggbyte_buffer ob;
+ if(oggbyte_init(&ob,og->header))return -1;
+ return oggbyte_read1(&ob,5)&0x04;
+}
+
+ogg_int64_t ogg_page_granulepos(ogg_page *og){
+ oggbyte_buffer ob;
+ if(oggbyte_init(&ob,og->header))return -1;
+ return oggbyte_read8(&ob,6);
+}
+
+ogg_uint32_t ogg_page_serialno(ogg_page *og){
+ oggbyte_buffer ob;
+ if(oggbyte_init(&ob,og->header)) return 0xffffffffUL;
+ return oggbyte_read4(&ob,14);
+}
+
+ogg_uint32_t ogg_page_pageno(ogg_page *og){
+ oggbyte_buffer ob;
+ if(oggbyte_init(&ob,og->header))return 0xffffffffUL;
+ return oggbyte_read4(&ob,18);
+}
+
+/* returns the number of packets that are completed on this page (if
+ the leading packet is begun on a previous page, but ends on this
+ page, it's counted */
+
+/* NOTE:
+If a page consists of a packet begun on a previous page, and a new
+packet begun (but not completed) on this page, the return will be:
+ ogg_page_packets(page) ==1,
+ ogg_page_continued(page) !=0
+
+If a page happens to be a single packet that was begun on a
+previous page, and spans to the next page (in the case of a three or
+more page packet), the return will be:
+ ogg_page_packets(page) ==0,
+ ogg_page_continued(page) !=0
+*/
+
+int ogg_page_packets(ogg_page *og){
+ int i;
+ int n;
+ int count=0;
+ oggbyte_buffer ob;
+ oggbyte_init(&ob,og->header);
+
+ n=oggbyte_read1(&ob,26);
+ for(i=0;i<n;i++)
+ if(oggbyte_read1(&ob,27+i)<255)count++;
+ return(count);
+}
+
+/* Static CRC calculation table. See older code in CVS for dead
+ run-time initialization code. */
+
+static ogg_uint32_t crc_lookup[256]={
+ 0x00000000,0x04c11db7,0x09823b6e,0x0d4326d9,
+ 0x130476dc,0x17c56b6b,0x1a864db2,0x1e475005,
+ 0x2608edb8,0x22c9f00f,0x2f8ad6d6,0x2b4bcb61,
+ 0x350c9b64,0x31cd86d3,0x3c8ea00a,0x384fbdbd,
+ 0x4c11db70,0x48d0c6c7,0x4593e01e,0x4152fda9,
+ 0x5f15adac,0x5bd4b01b,0x569796c2,0x52568b75,
+ 0x6a1936c8,0x6ed82b7f,0x639b0da6,0x675a1011,
+ 0x791d4014,0x7ddc5da3,0x709f7b7a,0x745e66cd,
+ 0x9823b6e0,0x9ce2ab57,0x91a18d8e,0x95609039,
+ 0x8b27c03c,0x8fe6dd8b,0x82a5fb52,0x8664e6e5,
+ 0xbe2b5b58,0xbaea46ef,0xb7a96036,0xb3687d81,
+ 0xad2f2d84,0xa9ee3033,0xa4ad16ea,0xa06c0b5d,
+ 0xd4326d90,0xd0f37027,0xddb056fe,0xd9714b49,
+ 0xc7361b4c,0xc3f706fb,0xceb42022,0xca753d95,
+ 0xf23a8028,0xf6fb9d9f,0xfbb8bb46,0xff79a6f1,
+ 0xe13ef6f4,0xe5ffeb43,0xe8bccd9a,0xec7dd02d,
+ 0x34867077,0x30476dc0,0x3d044b19,0x39c556ae,
+ 0x278206ab,0x23431b1c,0x2e003dc5,0x2ac12072,
+ 0x128e9dcf,0x164f8078,0x1b0ca6a1,0x1fcdbb16,
+ 0x018aeb13,0x054bf6a4,0x0808d07d,0x0cc9cdca,
+ 0x7897ab07,0x7c56b6b0,0x71159069,0x75d48dde,
+ 0x6b93dddb,0x6f52c06c,0x6211e6b5,0x66d0fb02,
+ 0x5e9f46bf,0x5a5e5b08,0x571d7dd1,0x53dc6066,
+ 0x4d9b3063,0x495a2dd4,0x44190b0d,0x40d816ba,
+ 0xaca5c697,0xa864db20,0xa527fdf9,0xa1e6e04e,
+ 0xbfa1b04b,0xbb60adfc,0xb6238b25,0xb2e29692,
+ 0x8aad2b2f,0x8e6c3698,0x832f1041,0x87ee0df6,
+ 0x99a95df3,0x9d684044,0x902b669d,0x94ea7b2a,
+ 0xe0b41de7,0xe4750050,0xe9362689,0xedf73b3e,
+ 0xf3b06b3b,0xf771768c,0xfa325055,0xfef34de2,
+ 0xc6bcf05f,0xc27dede8,0xcf3ecb31,0xcbffd686,
+ 0xd5b88683,0xd1799b34,0xdc3abded,0xd8fba05a,
+ 0x690ce0ee,0x6dcdfd59,0x608edb80,0x644fc637,
+ 0x7a089632,0x7ec98b85,0x738aad5c,0x774bb0eb,
+ 0x4f040d56,0x4bc510e1,0x46863638,0x42472b8f,
+ 0x5c007b8a,0x58c1663d,0x558240e4,0x51435d53,
+ 0x251d3b9e,0x21dc2629,0x2c9f00f0,0x285e1d47,
+ 0x36194d42,0x32d850f5,0x3f9b762c,0x3b5a6b9b,
+ 0x0315d626,0x07d4cb91,0x0a97ed48,0x0e56f0ff,
+ 0x1011a0fa,0x14d0bd4d,0x19939b94,0x1d528623,
+ 0xf12f560e,0xf5ee4bb9,0xf8ad6d60,0xfc6c70d7,
+ 0xe22b20d2,0xe6ea3d65,0xeba91bbc,0xef68060b,
+ 0xd727bbb6,0xd3e6a601,0xdea580d8,0xda649d6f,
+ 0xc423cd6a,0xc0e2d0dd,0xcda1f604,0xc960ebb3,
+ 0xbd3e8d7e,0xb9ff90c9,0xb4bcb610,0xb07daba7,
+ 0xae3afba2,0xaafbe615,0xa7b8c0cc,0xa379dd7b,
+ 0x9b3660c6,0x9ff77d71,0x92b45ba8,0x9675461f,
+ 0x8832161a,0x8cf30bad,0x81b02d74,0x857130c3,
+ 0x5d8a9099,0x594b8d2e,0x5408abf7,0x50c9b640,
+ 0x4e8ee645,0x4a4ffbf2,0x470cdd2b,0x43cdc09c,
+ 0x7b827d21,0x7f436096,0x7200464f,0x76c15bf8,
+ 0x68860bfd,0x6c47164a,0x61043093,0x65c52d24,
+ 0x119b4be9,0x155a565e,0x18197087,0x1cd86d30,
+ 0x029f3d35,0x065e2082,0x0b1d065b,0x0fdc1bec,
+ 0x3793a651,0x3352bbe6,0x3e119d3f,0x3ad08088,
+ 0x2497d08d,0x2056cd3a,0x2d15ebe3,0x29d4f654,
+ 0xc5a92679,0xc1683bce,0xcc2b1d17,0xc8ea00a0,
+ 0xd6ad50a5,0xd26c4d12,0xdf2f6bcb,0xdbee767c,
+ 0xe3a1cbc1,0xe760d676,0xea23f0af,0xeee2ed18,
+ 0xf0a5bd1d,0xf464a0aa,0xf9278673,0xfde69bc4,
+ 0x89b8fd09,0x8d79e0be,0x803ac667,0x84fbdbd0,
+ 0x9abc8bd5,0x9e7d9662,0x933eb0bb,0x97ffad0c,
+ 0xafb010b1,0xab710d06,0xa6322bdf,0xa2f33668,
+ 0xbcb4666d,0xb8757bda,0xb5365d03,0xb1f740b4};
+
+ogg_sync_state *ogg_sync_create(void){
+ ogg_sync_state *oy=_ogg_calloc(1,sizeof(*oy));
+ memset(oy,0,sizeof(*oy));
+ oy->bufferpool=ogg_buffer_create();
+ return oy;
+}
+
+int ogg_sync_destroy(ogg_sync_state *oy){
+ if(oy){
+ ogg_sync_reset(oy);
+ ogg_buffer_destroy(oy->bufferpool);
+ memset(oy,0,sizeof(*oy));
+ _ogg_free(oy);
+ }
+ return OGG_SUCCESS;
+}
+
+unsigned char *ogg_sync_bufferin(ogg_sync_state *oy, long bytes){
+
+ /* [allocate and] expose a buffer for data submission.
+
+ If there is no head fragment
+ allocate one and expose it
+ else
+ if the current head fragment has sufficient unused space
+ expose it
+ else
+ if the current head fragment is unused
+ resize and expose it
+ else
+ allocate new fragment and expose it
+ */
+
+ /* base case; fifo uninitialized */
+ if(!oy->fifo_head){
+ oy->fifo_head=oy->fifo_tail=ogg_buffer_alloc(oy->bufferpool,bytes);
+ return oy->fifo_head->buffer->data;
+ }
+
+ /* space left in current fragment case */
+ if(oy->fifo_head->buffer->size-
+ oy->fifo_head->length-
+ oy->fifo_head->begin >= bytes)
+ return oy->fifo_head->buffer->data+
+ oy->fifo_head->length+oy->fifo_head->begin;
+
+ /* current fragment is unused, but too small */
+ if(!oy->fifo_head->length){
+ ogg_buffer_realloc(oy->fifo_head,bytes);
+ return oy->fifo_head->buffer->data+oy->fifo_head->begin;
+ }
+
+ /* current fragment used/full; get new fragment */
+ {
+ ogg_reference *new=ogg_buffer_alloc(oy->bufferpool,bytes);
+ oy->fifo_head->next=new;
+ oy->fifo_head=new;
+ }
+ return oy->fifo_head->buffer->data;
+}
+
+int ogg_sync_wrote(ogg_sync_state *oy, long bytes){
+ if(!oy->fifo_head)return OGG_EINVAL;
+ if(oy->fifo_head->buffer->size-oy->fifo_head->length-oy->fifo_head->begin <
+ bytes)return OGG_EINVAL;
+ oy->fifo_head->length+=bytes;
+ oy->fifo_fill+=bytes;
+ return OGG_SUCCESS;
+}
+
+static ogg_uint32_t _checksum(ogg_reference *or, int bytes){
+ ogg_uint32_t crc_reg=0;
+ int j,post;
+
+ while(or){
+ unsigned char *data=or->buffer->data+or->begin;
+ post=(bytes<or->length?bytes:or->length);
+ for(j=0;j<post;++j)
+ crc_reg=(crc_reg<<8)^crc_lookup[((crc_reg >> 24)&0xff)^data[j]];
+ bytes-=j;
+ or=or->next;
+ }
+
+ return crc_reg;
+}
+
+
+/* sync the stream. This is meant to be useful for finding page
+ boundaries.
+
+ return values for this:
+ -n) skipped n bytes
+ 0) page not ready; more data (no bytes skipped)
+ n) page synced at current location; page length n bytes
+
+*/
+
+long ogg_sync_pageseek(ogg_sync_state *oy,ogg_page *og){
+ oggbyte_buffer page;
+ long bytes,ret=0;
+
+ ogg_page_release(og);
+
+ bytes=oy->fifo_fill;
+ oggbyte_init(&page,oy->fifo_tail);
+
+ if(oy->headerbytes==0){
+ if(bytes<27)goto sync_out; /* not enough for even a minimal header */
+
+ /* verify capture pattern */
+ if(oggbyte_read1(&page,0)!=(int)'O' ||
+ oggbyte_read1(&page,1)!=(int)'g' ||
+ oggbyte_read1(&page,2)!=(int)'g' ||
+ oggbyte_read1(&page,3)!=(int)'S' ) goto sync_fail;
+
+ oy->headerbytes=oggbyte_read1(&page,26)+27;
+ }
+ if(bytes<oy->headerbytes)goto sync_out; /* not enough for header +
+ seg table */
+ if(oy->bodybytes==0){
+ int i;
+ /* count up body length in the segment table */
+ for(i=0;i<oy->headerbytes-27;i++)
+ oy->bodybytes+=oggbyte_read1(&page,27+i);
+ }
+
+ if(oy->bodybytes+oy->headerbytes>bytes)goto sync_out;
+
+ /* we have what appears to be a complete page; last test: verify
+ checksum */
+ {
+ ogg_uint32_t chksum=oggbyte_read4(&page,22);
+ oggbyte_set4(&page,0,22);
+
+ /* Compare checksums; memory continues to be common access */
+ if(chksum!=_checksum(oy->fifo_tail,oy->bodybytes+oy->headerbytes)){
+
+ /* D'oh. Mismatch! Corrupt page (or miscapture and not a page
+ at all). replace the computed checksum with the one actually
+ read in; remember all the memory is common access */
+
+ oggbyte_set4(&page,chksum,22);
+ goto sync_fail;
+ }
+ oggbyte_set4(&page,chksum,22);
+ }
+
+ /* We have a page. Set up page return. */
+ if(og){
+ /* set up page output */
+ og->header=ogg_buffer_split(&oy->fifo_tail,&oy->fifo_head,oy->headerbytes);
+ og->header_len=oy->headerbytes;
+ og->body=ogg_buffer_split(&oy->fifo_tail,&oy->fifo_head,oy->bodybytes);
+ og->body_len=oy->bodybytes;
+ }else{
+ /* simply advance */
+ oy->fifo_tail=
+ ogg_buffer_pretruncate(oy->fifo_tail,oy->headerbytes+oy->bodybytes);
+ if(!oy->fifo_tail)oy->fifo_head=0;
+ }
+
+ ret=oy->headerbytes+oy->bodybytes;
+ oy->unsynced=0;
+ oy->headerbytes=0;
+ oy->bodybytes=0;
+ oy->fifo_fill-=ret;
+
+ return ret;
+
+ sync_fail:
+
+ oy->headerbytes=0;
+ oy->bodybytes=0;
+ oy->fifo_tail=ogg_buffer_pretruncate(oy->fifo_tail,1);
+ ret--;
+
+ /* search forward through fragments for possible capture */
+ while(oy->fifo_tail){
+ /* invariant: fifo_cursor points to a position in fifo_tail */
+ unsigned char *now=oy->fifo_tail->buffer->data+oy->fifo_tail->begin;
+ unsigned char *next=memchr(now, 'O', oy->fifo_tail->length);
+
+ if(next){
+ /* possible capture in this segment */
+ long bytes=next-now;
+ oy->fifo_tail=ogg_buffer_pretruncate(oy->fifo_tail,bytes);
+ ret-=bytes;
+ break;
+ }else{
+ /* no capture. advance to next segment */
+ long bytes=oy->fifo_tail->length;
+ ret-=bytes;
+ oy->fifo_tail=ogg_buffer_pretruncate(oy->fifo_tail,bytes);
+ }
+ }
+ if(!oy->fifo_tail)oy->fifo_head=0;
+ oy->fifo_fill+=ret;
+
+ sync_out:
+ return ret;
+}
+
+/* sync the stream and get a page. Keep trying until we find a page.
+ Supress 'sync errors' after reporting the first.
+
+ return values:
+ OGG_HOLE) recapture (hole in data)
+ 0) need more data
+ 1) page returned
+
+ Returns pointers into buffered data; invalidated by next call to
+ _stream, _clear, _init, or _buffer */
+
+int ogg_sync_pageout(ogg_sync_state *oy, ogg_page *og){
+
+ /* all we need to do is verify a page at the head of the stream
+ buffer. If it doesn't verify, we look for the next potential
+ frame */
+
+ while(1){
+ long ret=ogg_sync_pageseek(oy,og);
+ if(ret>0){
+ /* have a page */
+ return 1;
+ }
+ if(ret==0){
+ /* need more data */
+ return 0;
+ }
+
+ /* head did not start a synced page... skipped some bytes */
+ if(!oy->unsynced){
+ oy->unsynced=1;
+ return OGG_HOLE;
+ }
+
+ /* loop. keep looking */
+
+ }
+}
+
+/* clear things to an initial state. Good to call, eg, before seeking */
+int ogg_sync_reset(ogg_sync_state *oy){
+
+ ogg_buffer_release(oy->fifo_tail);
+ oy->fifo_tail=0;
+ oy->fifo_head=0;
+ oy->fifo_fill=0;
+
+ oy->unsynced=0;
+ oy->headerbytes=0;
+ oy->bodybytes=0;
+ return OGG_SUCCESS;
+}
+
+ogg_stream_state *ogg_stream_create(int serialno){
+ ogg_stream_state *os=_ogg_calloc(1,sizeof(*os));
+ os->serialno=serialno;
+ os->pageno=-1;
+ return os;
+}
+
+int ogg_stream_destroy(ogg_stream_state *os){
+ if(os){
+ ogg_buffer_release(os->header_tail);
+ ogg_buffer_release(os->body_tail);
+ memset(os,0,sizeof(*os));
+ _ogg_free(os);
+ }
+ return OGG_SUCCESS;
+}
+
+
+#define FINFLAG 0x80000000UL
+#define FINMASK 0x7fffffffUL
+
+static void _next_lace(oggbyte_buffer *ob,ogg_stream_state *os){
+ /* search ahead one lace */
+ os->body_fill_next=0;
+ while(os->laceptr<os->lacing_fill){
+ int val=oggbyte_read1(ob,27+os->laceptr++);
+ os->body_fill_next+=val;
+ if(val<255){
+ os->body_fill_next|=FINFLAG;
+ os->clearflag=1;
+ break;
+ }
+ }
+}
+
+static void _span_queued_page(ogg_stream_state *os){
+ while( !(os->body_fill&FINFLAG) ){
+
+ if(!os->header_tail)break;
+
+ /* first flush out preceeding page header (if any). Body is
+ flushed as it's consumed, so that's not done here. */
+
+ if(os->lacing_fill>=0)
+ os->header_tail=ogg_buffer_pretruncate(os->header_tail,
+ os->lacing_fill+27);
+ os->lacing_fill=0;
+ os->laceptr=0;
+ os->clearflag=0;
+
+ if(!os->header_tail){
+ os->header_head=0;
+ break;
+ }else{
+
+ /* process/prepare next page, if any */
+
+ long pageno;
+ oggbyte_buffer ob;
+ ogg_page og; /* only for parsing header values */
+ og.header=os->header_tail; /* only for parsing header values */
+ pageno=ogg_page_pageno(&og);
+
+ oggbyte_init(&ob,os->header_tail);
+ os->lacing_fill=oggbyte_read1(&ob,26);
+
+ /* are we in sequence? */
+ if(pageno!=os->pageno){
+ if(os->pageno==-1) /* indicates seek or reset */
+ os->holeflag=1; /* set for internal use */
+ else
+ os->holeflag=2; /* set for external reporting */
+
+ os->body_tail=ogg_buffer_pretruncate(os->body_tail,
+ os->body_fill);
+ if(os->body_tail==0)os->body_head=0;
+ os->body_fill=0;
+
+ }
+
+ if(ogg_page_continued(&og)){
+ if(os->body_fill==0){
+ /* continued packet, but no preceeding data to continue */
+ /* dump the first partial packet on the page */
+ _next_lace(&ob,os);
+ os->body_tail=
+ ogg_buffer_pretruncate(os->body_tail,os->body_fill_next&FINMASK);
+ if(os->body_tail==0)os->body_head=0;
+ /* set span flag */
+ if(!os->spanflag && !os->holeflag)os->spanflag=2;
+ }
+ }else{
+ if(os->body_fill>0){
+ /* preceeding data to continue, but not a continued page */
+ /* dump body_fill */
+ os->body_tail=ogg_buffer_pretruncate(os->body_tail,
+ os->body_fill);
+ if(os->body_tail==0)os->body_head=0;
+ os->body_fill=0;
+
+ /* set espan flag */
+ if(!os->spanflag && !os->holeflag)os->spanflag=2;
+ }
+ }
+
+ if(os->laceptr<os->lacing_fill){
+ os->granulepos=ogg_page_granulepos(&og);
+
+ /* get current packet size & flag */
+ _next_lace(&ob,os);
+ os->body_fill+=os->body_fill_next; /* addition handles the flag fine;
+ unsigned on purpose */
+ /* ...and next packet size & flag */
+ _next_lace(&ob,os);
+
+ }
+
+ os->pageno=pageno+1;
+ os->e_o_s=ogg_page_eos(&og);
+ os->b_o_s=ogg_page_bos(&og);
+
+ }
+ }
+}
+
+/* add the incoming page to the stream state; we decompose the page
+ into packet segments here as well. */
+
+int ogg_stream_pagein(ogg_stream_state *os, ogg_page *og){
+
+ int serialno=ogg_page_serialno(og);
+ int version=ogg_page_version(og);
+
+ /* check the serial number */
+ if(serialno!=os->serialno){
+ ogg_page_release(og);
+ return OGG_ESERIAL;
+ }
+ if(version>0){
+ ogg_page_release(og);
+ return OGG_EVERSION;
+ }
+
+ /* add to fifos */
+ if(!os->body_tail){
+ os->body_tail=og->body;
+ os->body_head=ogg_buffer_walk(og->body);
+ }else{
+ os->body_head=ogg_buffer_cat(os->body_head,og->body);
+ }
+ if(!os->header_tail){
+ os->header_tail=og->header;
+ os->header_head=ogg_buffer_walk(og->header);
+ os->lacing_fill=-27;
+ }else{
+ os->header_head=ogg_buffer_cat(os->header_head,og->header);
+ }
+
+ memset(og,0,sizeof(*og));
+ return OGG_SUCCESS;
+}
+
+int ogg_stream_reset(ogg_stream_state *os){
+
+ ogg_buffer_release(os->header_tail);
+ ogg_buffer_release(os->body_tail);
+ os->header_tail=os->header_head=0;
+ os->body_tail=os->body_head=0;
+
+ os->e_o_s=0;
+ os->b_o_s=0;
+ os->pageno=-1;
+ os->packetno=0;
+ os->granulepos=0;
+
+ os->body_fill=0;
+ os->lacing_fill=0;
+
+ os->holeflag=0;
+ os->spanflag=0;
+ os->clearflag=0;
+ os->laceptr=0;
+ os->body_fill_next=0;
+
+ return OGG_SUCCESS;
+}
+
+int ogg_stream_reset_serialno(ogg_stream_state *os,int serialno){
+ ogg_stream_reset(os);
+ os->serialno=serialno;
+ return OGG_SUCCESS;
+}
+
+static int _packetout(ogg_stream_state *os,ogg_packet *op,int adv){
+
+ ogg_packet_release(op);
+ _span_queued_page(os);
+
+ if(os->holeflag){
+ int temp=os->holeflag;
+ if(os->clearflag)
+ os->holeflag=0;
+ else
+ os->holeflag=1;
+ if(temp==2){
+ os->packetno++;
+ return OGG_HOLE;
+ }
+ }
+ if(os->spanflag){
+ int temp=os->spanflag;
+ if(os->clearflag)
+ os->spanflag=0;
+ else
+ os->spanflag=1;
+ if(temp==2){
+ os->packetno++;
+ return OGG_SPAN;
+ }
+ }
+
+ if(!(os->body_fill&FINFLAG)) return 0;
+ if(!op && !adv)return 1; /* just using peek as an inexpensive way
+ to ask if there's a whole packet
+ waiting */
+ if(op){
+ op->b_o_s=os->b_o_s;
+ if(os->e_o_s && os->body_fill_next==0)
+ op->e_o_s=os->e_o_s;
+ else
+ op->e_o_s=0;
+ if( (os->body_fill&FINFLAG) && !(os->body_fill_next&FINFLAG) )
+ op->granulepos=os->granulepos;
+ else
+ op->granulepos=-1;
+ op->packetno=os->packetno;
+ }
+
+ if(adv){
+ oggbyte_buffer ob;
+ oggbyte_init(&ob,os->header_tail);
+
+ /* split the body contents off */
+ if(op){
+ op->packet=ogg_buffer_split(&os->body_tail,&os->body_head,
+ os->body_fill&FINMASK);
+ op->bytes=os->body_fill&FINMASK;
+ }else{
+ os->body_tail=ogg_buffer_pretruncate(os->body_tail,
+ os->body_fill&FINMASK);
+ if(os->body_tail==0)os->body_head=0;
+ }
+
+ /* update lacing pointers */
+ os->body_fill=os->body_fill_next;
+ _next_lace(&ob,os);
+ }else{
+ if(op){
+ op->packet=ogg_buffer_sub(os->body_tail,os->body_fill&FINMASK);
+ op->bytes=os->body_fill&FINMASK;
+ }
+ }
+
+ if(adv){
+ os->packetno++;
+ os->b_o_s=0;
+ }
+
+ return 1;
+}
+
+int ogg_stream_packetout(ogg_stream_state *os,ogg_packet *op){
+ return _packetout(os,op,1);
+}
+
+int ogg_stream_packetpeek(ogg_stream_state *os,ogg_packet *op){
+ return _packetout(os,op,0);
+}
+
+int ogg_packet_release(ogg_packet *op) {
+ if(op){
+ ogg_buffer_release(op->packet);
+ memset(op, 0, sizeof(*op));
+ }
+ return OGG_SUCCESS;
+}
+
+int ogg_page_release(ogg_page *og) {
+ if(og){
+ ogg_buffer_release(og->header);
+ ogg_buffer_release(og->body);
+ memset(og, 0, sizeof(*og));
+ }
+ return OGG_SUCCESS;
+}
+
+void ogg_page_dup(ogg_page *dup,ogg_page *orig){
+ dup->header_len=orig->header_len;
+ dup->body_len=orig->body_len;
+ dup->header=ogg_buffer_dup(orig->header);
+ dup->body=ogg_buffer_dup(orig->body);
+}
+
diff --git a/library/ADK2/v_info.c b/library/ADK2/v_info.c
new file mode 100644
index 0000000..ec2a91d
--- /dev/null
+++ b/library/ADK2/v_info.c
@@ -0,0 +1,349 @@
+#define ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: maintain the info structure, info <-> header packets
+
+ ********************************************************************/
+
+/* general handling of the header and the vorbis_info structure (and
+ substructures) */
+
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include "v_ogg.h"
+#include "v_ivorbiscodec.h"
+#include "v_codec_internal.h"
+#include "v_codebook.h"
+#include "v_misc.h"
+#include "v_os.h"
+
+/* helpers */
+static void _v_readstring(oggpack_buffer *o,char *buf,int bytes){
+ while(bytes--){
+ *buf++=oggpack_read(o,8);
+ }
+}
+
+void vorbis_comment_init(vorbis_comment *vc){
+ memset(vc,0,sizeof(*vc));
+}
+
+/* This is more or less the same as strncasecmp - but that doesn't exist
+ * everywhere, and this is a fairly trivial function, so we include it */
+static int tagcompare(const char *s1, const char *s2, int n){
+ int c=0;
+ while(c < n){
+ if(toupper(s1[c]) != toupper(s2[c]))
+ return !0;
+ c++;
+ }
+ return 0;
+}
+
+char *vorbis_comment_query(vorbis_comment *vc, char *tag, int count){
+ long i;
+ int found = 0;
+ int taglen = strlen(tag)+1; /* +1 for the = we append */
+ char *fulltag = (char *)alloca(taglen+ 1);
+
+ strcpy(fulltag, tag);
+ strcat(fulltag, "=");
+
+ for(i=0;i<vc->comments;i++){
+ if(!tagcompare(vc->user_comments[i], fulltag, taglen)){
+ if(count == found)
+ /* We return a pointer to the data, not a copy */
+ return vc->user_comments[i] + taglen;
+ else
+ found++;
+ }
+ }
+ return NULL; /* didn't find anything */
+}
+
+int vorbis_comment_query_count(vorbis_comment *vc, char *tag){
+ int i,count=0;
+ int taglen = strlen(tag)+1; /* +1 for the = we append */
+ char *fulltag = (char *)alloca(taglen+1);
+ strcpy(fulltag,tag);
+ strcat(fulltag, "=");
+
+ for(i=0;i<vc->comments;i++){
+ if(!tagcompare(vc->user_comments[i], fulltag, taglen))
+ count++;
+ }
+
+ return count;
+}
+
+void vorbis_comment_clear(vorbis_comment *vc){
+ if(vc){
+ long i;
+ for(i=0;i<vc->comments;i++)
+ if(vc->user_comments[i])_ogg_free(vc->user_comments[i]);
+ if(vc->user_comments)_ogg_free(vc->user_comments);
+ if(vc->comment_lengths)_ogg_free(vc->comment_lengths);
+ if(vc->vendor)_ogg_free(vc->vendor);
+ }
+ memset(vc,0,sizeof(*vc));
+}
+
+/* blocksize 0 is guaranteed to be short, 1 is guarantted to be long.
+ They may be equal, but short will never ge greater than long */
+int vorbis_info_blocksize(vorbis_info *vi,int zo){
+ codec_setup_info *ci = (codec_setup_info *)vi->codec_setup;
+ return ci ? ci->blocksizes[zo] : -1;
+}
+
+/* used by synthesis, which has a full, alloced vi */
+void vorbis_info_init(vorbis_info *vi){
+ memset(vi,0,sizeof(*vi));
+ vi->codec_setup=(codec_setup_info *)_ogg_calloc(1,sizeof(codec_setup_info));
+}
+
+void vorbis_info_clear(vorbis_info *vi){
+ codec_setup_info *ci=(codec_setup_info *)vi->codec_setup;
+ int i;
+
+ if(ci){
+
+ if(ci->mode_param)_ogg_free(ci->mode_param);
+
+ if(ci->map_param){
+ for(i=0;i<ci->maps;i++) /* unpack does the range checking */
+ mapping_clear_info(ci->map_param+i);
+ _ogg_free(ci->map_param);
+ }
+
+ if(ci->floor_param){
+ for(i=0;i<ci->floors;i++) /* unpack does the range checking */
+ if(ci->floor_type[i])
+ floor1_free_info(ci->floor_param[i]);
+ else
+ floor0_free_info(ci->floor_param[i]);
+ _ogg_free(ci->floor_param);
+ _ogg_free(ci->floor_type);
+ }
+
+ if(ci->residue_param){
+ for(i=0;i<ci->residues;i++) /* unpack does the range checking */
+ res_clear_info(ci->residue_param+i);
+ _ogg_free(ci->residue_param);
+ }
+
+ if(ci->book_param){
+ for(i=0;i<ci->books;i++)
+ vorbis_book_clear(ci->book_param+i);
+ _ogg_free(ci->book_param);
+ }
+
+ _ogg_free(ci);
+ }
+
+ memset(vi,0,sizeof(*vi));
+}
+
+/* Header packing/unpacking ********************************************/
+
+static int _vorbis_unpack_info(vorbis_info *vi,oggpack_buffer *opb){
+ codec_setup_info *ci=(codec_setup_info *)vi->codec_setup;
+ if(!ci)return(OV_EFAULT);
+
+ vi->version=oggpack_read(opb,32);
+ if(vi->version!=0)return(OV_EVERSION);
+
+ vi->channels=oggpack_read(opb,8);
+ vi->rate=oggpack_read(opb,32);
+
+ vi->bitrate_upper=oggpack_read(opb,32);
+ vi->bitrate_nominal=oggpack_read(opb,32);
+ vi->bitrate_lower=oggpack_read(opb,32);
+
+ ci->blocksizes[0]=1<<oggpack_read(opb,4);
+ ci->blocksizes[1]=1<<oggpack_read(opb,4);
+
+#ifdef LIMIT_TO_64kHz
+ if(vi->rate>=64000 || ci->blocksizes[1]>4096)goto err_out;
+#else
+ if(vi->rate<64000 && ci->blocksizes[1]>4096)goto err_out;
+#endif
+
+ if(vi->rate<1)goto err_out;
+ if(vi->channels<1)goto err_out;
+ if(ci->blocksizes[0]<64)goto err_out;
+ if(ci->blocksizes[1]<ci->blocksizes[0])goto err_out;
+ if(ci->blocksizes[1]>8192)goto err_out;
+
+ if(oggpack_read(opb,1)!=1)goto err_out; /* EOP check */
+
+ return(0);
+ err_out:
+ vorbis_info_clear(vi);
+ return(OV_EBADHEADER);
+}
+
+static int _vorbis_unpack_comment(vorbis_comment *vc,oggpack_buffer *opb){
+ int i;
+ int vendorlen=oggpack_read(opb,32);
+ if(vendorlen<0)goto err_out;
+ vc->vendor=(char *)_ogg_calloc(vendorlen+1,1);
+ _v_readstring(opb,vc->vendor,vendorlen);
+ vc->comments=oggpack_read(opb,32);
+ if(vc->comments<0)goto err_out;
+ vc->user_comments=(char **)_ogg_calloc(vc->comments+1,sizeof(*vc->user_comments));
+ vc->comment_lengths=(int *)_ogg_calloc(vc->comments+1, sizeof(*vc->comment_lengths));
+
+ for(i=0;i<vc->comments;i++){
+ int len=oggpack_read(opb,32);
+ if(len<0)goto err_out;
+ vc->comment_lengths[i]=len;
+ vc->user_comments[i]=(char *)_ogg_calloc(len+1,1);
+ _v_readstring(opb,vc->user_comments[i],len);
+ }
+ if(oggpack_read(opb,1)!=1)goto err_out; /* EOP check */
+
+ return(0);
+ err_out:
+ vorbis_comment_clear(vc);
+ return(OV_EBADHEADER);
+}
+
+/* all of the real encoding details are here. The modes, books,
+ everything */
+static int _vorbis_unpack_books(vorbis_info *vi,oggpack_buffer *opb){
+ codec_setup_info *ci=(codec_setup_info *)vi->codec_setup;
+ int i;
+ if(!ci)return(OV_EFAULT);
+
+ /* codebooks */
+ ci->books=oggpack_read(opb,8)+1;
+ ci->book_param=(codebook *)_ogg_calloc(ci->books,sizeof(*ci->book_param));
+ for(i=0;i<ci->books;i++)
+ if(vorbis_book_unpack(opb,ci->book_param+i))goto err_out;
+
+ /* time backend settings, not actually used */
+ i=oggpack_read(opb,6);
+ for(;i>=0;i--)
+ if(oggpack_read(opb,16)!=0)goto err_out;
+
+ /* floor backend settings */
+ ci->floors=oggpack_read(opb,6)+1;
+ ci->floor_param=_ogg_malloc(sizeof(*ci->floor_param)*ci->floors);
+ ci->floor_type=_ogg_malloc(sizeof(*ci->floor_type)*ci->floors);
+ for(i=0;i<ci->floors;i++){
+ ci->floor_type[i]=oggpack_read(opb,16);
+ if(ci->floor_type[i]<0 || ci->floor_type[i]>=VI_FLOORB)goto err_out;
+ if(ci->floor_type[i])
+ ci->floor_param[i]=floor1_info_unpack(vi,opb);
+ else
+ ci->floor_param[i]=floor0_info_unpack(vi,opb);
+ if(!ci->floor_param[i])goto err_out;
+ }
+
+ /* residue backend settings */
+ ci->residues=oggpack_read(opb,6)+1;
+ ci->residue_param=_ogg_malloc(sizeof(*ci->residue_param)*ci->residues);
+ for(i=0;i<ci->residues;i++)
+ if(res_unpack(ci->residue_param+i,vi,opb))goto err_out;
+
+ /* map backend settings */
+ ci->maps=oggpack_read(opb,6)+1;
+ ci->map_param=_ogg_malloc(sizeof(*ci->map_param)*ci->maps);
+ for(i=0;i<ci->maps;i++){
+ if(oggpack_read(opb,16)!=0)goto err_out;
+ if(mapping_info_unpack(ci->map_param+i,vi,opb))goto err_out;
+ }
+
+ /* mode settings */
+ ci->modes=oggpack_read(opb,6)+1;
+ ci->mode_param=
+ (vorbis_info_mode *)_ogg_malloc(ci->modes*sizeof(*ci->mode_param));
+ for(i=0;i<ci->modes;i++){
+ ci->mode_param[i].blockflag=oggpack_read(opb,1);
+ if(oggpack_read(opb,16))goto err_out;
+ if(oggpack_read(opb,16))goto err_out;
+ ci->mode_param[i].mapping=oggpack_read(opb,8);
+ if(ci->mode_param[i].mapping>=ci->maps)goto err_out;
+ }
+
+ if(oggpack_read(opb,1)!=1)goto err_out; /* top level EOP check */
+
+ return(0);
+ err_out:
+ vorbis_info_clear(vi);
+ return(OV_EBADHEADER);
+}
+
+/* The Vorbis header is in three packets; the initial small packet in
+ the first page that identifies basic parameters, a second packet
+ with bitstream comments and a third packet that holds the
+ codebook. */
+
+int vorbis_dsp_headerin(vorbis_info *vi,vorbis_comment *vc,ogg_packet *op){
+ oggpack_buffer opb;
+
+ if(op){
+ oggpack_readinit(&opb,op->packet);
+
+ /* Which of the three types of header is this? */
+ /* Also verify header-ness, vorbis */
+ {
+ char buffer[6];
+ int packtype=oggpack_read(&opb,8);
+ memset(buffer,0,6);
+ _v_readstring(&opb,buffer,6);
+ if(memcmp(buffer,"vorbis",6)){
+ /* not a vorbis header */
+ return(OV_ENOTVORBIS);
+ }
+ switch(packtype){
+ case 0x01: /* least significant *bit* is read first */
+ if(!op->b_o_s){
+ /* Not the initial packet */
+ return(OV_EBADHEADER);
+ }
+ if(vi->rate!=0){
+ /* previously initialized info header */
+ return(OV_EBADHEADER);
+ }
+
+ return(_vorbis_unpack_info(vi,&opb));
+
+ case 0x03: /* least significant *bit* is read first */
+ if(vi->rate==0){
+ /* um... we didn't get the initial header */
+ return(OV_EBADHEADER);
+ }
+
+ return(_vorbis_unpack_comment(vc,&opb));
+
+ case 0x05: /* least significant *bit* is read first */
+ if(vi->rate==0 || vc->vendor==NULL){
+ /* um... we didn;t get the initial header or comments yet */
+ return(OV_EBADHEADER);
+ }
+
+ return(_vorbis_unpack_books(vi,&opb));
+
+ default:
+ /* Not a valid vorbis header type */
+ return(OV_EBADHEADER);
+ break;
+ }
+ }
+ }
+ return(OV_EBADHEADER);
+}
+
diff --git a/library/ADK2/v_ivorbiscodec.h b/library/ADK2/v_ivorbiscodec.h
new file mode 100644
index 0000000..94df8f7
--- /dev/null
+++ b/library/ADK2/v_ivorbiscodec.h
@@ -0,0 +1,107 @@
+#ifdef ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2002 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: libvorbis codec headers
+
+ ********************************************************************/
+
+#ifndef _vorbis_codec_h_
+#define _vorbis_codec_h_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+#include "v_ogg.h"
+
+struct vorbis_dsp_state;
+typedef struct vorbis_dsp_state vorbis_dsp_state;
+
+typedef struct vorbis_info{
+ int version;
+ int channels;
+ long rate;
+
+ /* The below bitrate declarations are *hints*.
+ Combinations of the three values carry the following implications:
+
+ all three set to the same value:
+ implies a fixed rate bitstream
+ only nominal set:
+ implies a VBR stream that averages the nominal bitrate. No hard
+ upper/lower limit
+ upper and or lower set:
+ implies a VBR bitstream that obeys the bitrate limits. nominal
+ may also be set to give a nominal rate.
+ none set:
+ the coder does not care to speculate.
+ */
+
+ long bitrate_upper;
+ long bitrate_nominal;
+ long bitrate_lower;
+ long bitrate_window;
+
+ void *codec_setup;
+} vorbis_info;
+
+typedef struct vorbis_comment{
+ char **user_comments;
+ int *comment_lengths;
+ int comments;
+ char *vendor;
+
+} vorbis_comment;
+
+
+/* Vorbis PRIMITIVES: general ***************************************/
+
+extern void vorbis_info_init(vorbis_info *vi);
+extern void vorbis_info_clear(vorbis_info *vi);
+extern int vorbis_info_blocksize(vorbis_info *vi,int zo);
+extern void vorbis_comment_init(vorbis_comment *vc);
+extern void vorbis_comment_add(vorbis_comment *vc, char *comment);
+extern void vorbis_comment_add_tag(vorbis_comment *vc,
+ char *tag, char *contents);
+extern char *vorbis_comment_query(vorbis_comment *vc, char *tag, int count);
+extern int vorbis_comment_query_count(vorbis_comment *vc, char *tag);
+extern void vorbis_comment_clear(vorbis_comment *vc);
+
+/* Vorbis ERRORS and return codes ***********************************/
+
+#define OV_FALSE -1
+#define OV_EOF -2
+#define OV_HOLE -3
+
+#define OV_EREAD -128
+#define OV_EFAULT -129
+#define OV_EIMPL -130
+#define OV_EINVAL -131
+#define OV_ENOTVORBIS -132
+#define OV_EBADHEADER -133
+#define OV_EVERSION -134
+#define OV_ENOTAUDIO -135
+#define OV_EBADPACKET -136
+#define OV_EBADLINK -137
+#define OV_ENOSEEK -138
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
+
+#endif
+
diff --git a/library/ADK2/v_ivorbisfile.h b/library/ADK2/v_ivorbisfile.h
new file mode 100644
index 0000000..8b3350a
--- /dev/null
+++ b/library/ADK2/v_ivorbisfile.h
@@ -0,0 +1,125 @@
+#ifdef ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: stdio-based convenience library for opening/seeking/decoding
+
+ ********************************************************************/
+
+#ifndef _OV_FILE_H_
+#define _OV_FILE_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+#include <stdio.h>
+#include "v_ivorbiscodec.h"
+
+/* The function prototypes for the callbacks are basically the same as for
+ * the stdio functions fread, fseek, fclose, ftell.
+ * The one difference is that the FILE * arguments have been replaced with
+ * a void * - this is to be used as a pointer to whatever internal data these
+ * functions might need. In the stdio case, it's just a FILE * cast to a void *
+ *
+ * If you use other functions, check the docs for these functions and return
+ * the right values. For seek_func(), you *MUST* return -1 if the stream is
+ * unseekable
+ */
+typedef struct {
+ size_t (*read_func) (void *ptr, size_t size, size_t nmemb, void *datasource);
+ int (*seek_func) (void *datasource, ogg_int64_t offset, int whence);
+ int (*close_func) (void *datasource);
+ long (*tell_func) (void *datasource);
+} ov_callbacks;
+
+typedef struct OggVorbis_File {
+ void *datasource; /* Pointer to a FILE *, etc. */
+ int seekable;
+ ogg_int64_t offset;
+ ogg_int64_t end;
+ ogg_sync_state *oy;
+
+ /* If the FILE handle isn't seekable (eg, a pipe), only the current
+ stream appears */
+ int links;
+ ogg_int64_t *offsets;
+ ogg_int64_t *dataoffsets;
+ ogg_uint32_t *serialnos;
+ ogg_int64_t *pcmlengths;
+ vorbis_info vi;
+ vorbis_comment vc;
+
+ /* Decoding working state local storage */
+ ogg_int64_t pcm_offset;
+ int ready_state;
+ ogg_uint32_t current_serialno;
+ int current_link;
+
+ ogg_int64_t bittrack;
+ ogg_int64_t samptrack;
+
+ ogg_stream_state *os; /* take physical pages, weld into a logical
+ stream of packets */
+ vorbis_dsp_state *vd; /* central working state for the packet->PCM decoder */
+
+ ov_callbacks callbacks;
+
+} OggVorbis_File;
+
+extern int ov_clear(OggVorbis_File *vf);
+extern int ov_open(FILE *f,OggVorbis_File *vf,char *initial,long ibytes);
+extern int ov_open_callbacks(void *datasource, OggVorbis_File *vf,
+ char *initial, long ibytes, ov_callbacks callbacks);
+
+extern int ov_test(FILE *f,OggVorbis_File *vf,char *initial,long ibytes);
+extern int ov_test_callbacks(void *datasource, OggVorbis_File *vf,
+ char *initial, long ibytes, ov_callbacks callbacks);
+extern int ov_test_open(OggVorbis_File *vf);
+
+extern long ov_bitrate(OggVorbis_File *vf,int i);
+extern long ov_bitrate_instant(OggVorbis_File *vf);
+extern long ov_streams(OggVorbis_File *vf);
+extern long ov_seekable(OggVorbis_File *vf);
+extern long ov_serialnumber(OggVorbis_File *vf,int i);
+
+extern ogg_int64_t ov_raw_total(OggVorbis_File *vf,int i);
+extern ogg_int64_t ov_pcm_total(OggVorbis_File *vf,int i);
+extern ogg_int64_t ov_time_total(OggVorbis_File *vf,int i);
+
+extern int ov_raw_seek(OggVorbis_File *vf,ogg_int64_t pos);
+extern int ov_pcm_seek(OggVorbis_File *vf,ogg_int64_t pos);
+extern int ov_pcm_seek_page(OggVorbis_File *vf,ogg_int64_t pos);
+extern int ov_time_seek(OggVorbis_File *vf,ogg_int64_t pos);
+extern int ov_time_seek_page(OggVorbis_File *vf,ogg_int64_t pos);
+
+extern ogg_int64_t ov_raw_tell(OggVorbis_File *vf);
+extern ogg_int64_t ov_pcm_tell(OggVorbis_File *vf);
+extern ogg_int64_t ov_time_tell(OggVorbis_File *vf);
+
+extern vorbis_info *ov_info(OggVorbis_File *vf,int link);
+extern vorbis_comment *ov_comment(OggVorbis_File *vf,int link);
+
+extern long ov_read(OggVorbis_File *vf,void *buffer,int length,
+ int *bitstream);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
+
+
+#endif
+
diff --git a/library/ADK2/v_lsp_lookup.h b/library/ADK2/v_lsp_lookup.h
new file mode 100644
index 0000000..c8d16fa
--- /dev/null
+++ b/library/ADK2/v_lsp_lookup.h
@@ -0,0 +1,111 @@
+#ifdef ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2002 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: lookup data
+
+ ********************************************************************/
+
+#ifndef _V_LOOKUP_DATA_H_
+#define _V_LOOKUP_DATA_H_
+
+#include "v_os_types.h"
+
+#define INVSQ_LOOKUP_I_SHIFT 10
+#define INVSQ_LOOKUP_I_MASK 1023
+static const long INVSQ_LOOKUP_I[64+1]={
+ 92682, 91966, 91267, 90583,
+ 89915, 89261, 88621, 87995,
+ 87381, 86781, 86192, 85616,
+ 85051, 84497, 83953, 83420,
+ 82897, 82384, 81880, 81385,
+ 80899, 80422, 79953, 79492,
+ 79039, 78594, 78156, 77726,
+ 77302, 76885, 76475, 76072,
+ 75674, 75283, 74898, 74519,
+ 74146, 73778, 73415, 73058,
+ 72706, 72359, 72016, 71679,
+ 71347, 71019, 70695, 70376,
+ 70061, 69750, 69444, 69141,
+ 68842, 68548, 68256, 67969,
+ 67685, 67405, 67128, 66855,
+ 66585, 66318, 66054, 65794,
+ 65536,
+};
+
+static const long INVSQ_LOOKUP_IDel[64]={
+ 716, 699, 684, 668,
+ 654, 640, 626, 614,
+ 600, 589, 576, 565,
+ 554, 544, 533, 523,
+ 513, 504, 495, 486,
+ 477, 469, 461, 453,
+ 445, 438, 430, 424,
+ 417, 410, 403, 398,
+ 391, 385, 379, 373,
+ 368, 363, 357, 352,
+ 347, 343, 337, 332,
+ 328, 324, 319, 315,
+ 311, 306, 303, 299,
+ 294, 292, 287, 284,
+ 280, 277, 273, 270,
+ 267, 264, 260, 258,
+};
+
+#define COS_LOOKUP_I_SHIFT 9
+#define COS_LOOKUP_I_MASK 511
+#define COS_LOOKUP_I_SZ 128
+static const ogg_int32_t COS_LOOKUP_I[COS_LOOKUP_I_SZ+1]={
+ 16384, 16379, 16364, 16340,
+ 16305, 16261, 16207, 16143,
+ 16069, 15986, 15893, 15791,
+ 15679, 15557, 15426, 15286,
+ 15137, 14978, 14811, 14635,
+ 14449, 14256, 14053, 13842,
+ 13623, 13395, 13160, 12916,
+ 12665, 12406, 12140, 11866,
+ 11585, 11297, 11003, 10702,
+ 10394, 10080, 9760, 9434,
+ 9102, 8765, 8423, 8076,
+ 7723, 7366, 7005, 6639,
+ 6270, 5897, 5520, 5139,
+ 4756, 4370, 3981, 3590,
+ 3196, 2801, 2404, 2006,
+ 1606, 1205, 804, 402,
+ 0, -401, -803, -1204,
+ -1605, -2005, -2403, -2800,
+ -3195, -3589, -3980, -4369,
+ -4755, -5138, -5519, -5896,
+ -6269, -6638, -7004, -7365,
+ -7722, -8075, -8422, -8764,
+ -9101, -9433, -9759, -10079,
+ -10393, -10701, -11002, -11296,
+ -11584, -11865, -12139, -12405,
+ -12664, -12915, -13159, -13394,
+ -13622, -13841, -14052, -14255,
+ -14448, -14634, -14810, -14977,
+ -15136, -15285, -15425, -15556,
+ -15678, -15790, -15892, -15985,
+ -16068, -16142, -16206, -16260,
+ -16304, -16339, -16363, -16378,
+ -16383,
+};
+
+#endif
+
+
+
+
+
+#endif
+
diff --git a/library/ADK2/v_mapping0.c b/library/ADK2/v_mapping0.c
new file mode 100644
index 0000000..870fba3
--- /dev/null
+++ b/library/ADK2/v_mapping0.c
@@ -0,0 +1,242 @@
+#define ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: channel mapping 0 implementation
+
+ ********************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <math.h>
+#include "v_ogg.h"
+#include "v_os.h"
+#include "v_ivorbiscodec.h"
+#include "v_mdct.h"
+#include "v_codec_internal.h"
+#include "v_codebook.h"
+#include "v_misc.h"
+
+void mapping_clear_info(vorbis_info_mapping *info){
+ if(info){
+ if(info->chmuxlist)_ogg_free(info->chmuxlist);
+ if(info->submaplist)_ogg_free(info->submaplist);
+ if(info->coupling)_ogg_free(info->coupling);
+ memset(info,0,sizeof(*info));
+ }
+}
+
+static int ilog(unsigned int v){
+ int ret=0;
+ if(v)--v;
+ while(v){
+ ret++;
+ v>>=1;
+ }
+ return(ret);
+}
+
+/* also responsible for range checking */
+int mapping_info_unpack(vorbis_info_mapping *info,vorbis_info *vi,
+ oggpack_buffer *opb){
+ int i;
+ codec_setup_info *ci=(codec_setup_info *)vi->codec_setup;
+ memset(info,0,sizeof(*info));
+
+ if(oggpack_read(opb,1))
+ info->submaps=oggpack_read(opb,4)+1;
+ else
+ info->submaps=1;
+
+ if(oggpack_read(opb,1)){
+ info->coupling_steps=oggpack_read(opb,8)+1;
+ info->coupling=
+ _ogg_malloc(info->coupling_steps*sizeof(*info->coupling));
+
+ for(i=0;i<info->coupling_steps;i++){
+ int testM=info->coupling[i].mag=oggpack_read(opb,ilog(vi->channels));
+ int testA=info->coupling[i].ang=oggpack_read(opb,ilog(vi->channels));
+
+ if(testM<0 ||
+ testA<0 ||
+ testM==testA ||
+ testM>=vi->channels ||
+ testA>=vi->channels) goto err_out;
+ }
+
+ }
+
+ if(oggpack_read(opb,2)>0)goto err_out; /* 2,3:reserved */
+
+ if(info->submaps>1){
+ info->chmuxlist=_ogg_malloc(sizeof(*info->chmuxlist)*vi->channels);
+ for(i=0;i<vi->channels;i++){
+ info->chmuxlist[i]=oggpack_read(opb,4);
+ if(info->chmuxlist[i]>=info->submaps)goto err_out;
+ }
+ }
+
+ info->submaplist=_ogg_malloc(sizeof(*info->submaplist)*info->submaps);
+ for(i=0;i<info->submaps;i++){
+ int temp=oggpack_read(opb,8);
+ info->submaplist[i].floor=oggpack_read(opb,8);
+ if(info->submaplist[i].floor>=ci->floors)goto err_out;
+ info->submaplist[i].residue=oggpack_read(opb,8);
+ if(info->submaplist[i].residue>=ci->residues)goto err_out;
+ }
+
+ return 0;
+
+ err_out:
+ mapping_clear_info(info);
+ return -1;
+}
+
+int mapping_inverse(vorbis_dsp_state *vd,vorbis_info_mapping *info){
+ vorbis_info *vi=vd->vi;
+ codec_setup_info *ci=(codec_setup_info *)vi->codec_setup;
+
+ int i,j;
+ long n=ci->blocksizes[vd->W];
+
+ ogg_int32_t **pcmbundle=
+ alloca(sizeof(*pcmbundle)*vi->channels);
+ int *zerobundle=
+ alloca(sizeof(*zerobundle)*vi->channels);
+ int *nonzero=
+ alloca(sizeof(*nonzero)*vi->channels);
+ ogg_int32_t **floormemo=
+ alloca(sizeof(*floormemo)*vi->channels);
+
+ /* recover the spectral envelope; store it in the PCM vector for now */
+ for(i=0;i<vi->channels;i++){
+ int submap=0;
+ int floorno;
+
+ if(info->submaps>1)
+ submap=info->chmuxlist[i];
+ floorno=info->submaplist[submap].floor;
+
+ if(ci->floor_type[floorno]){
+ /* floor 1 */
+ floormemo[i]=alloca(sizeof(*floormemo[i])*
+ floor1_memosize(ci->floor_param[floorno]));
+ floormemo[i]=floor1_inverse1(vd,ci->floor_param[floorno],floormemo[i]);
+ }else{
+ /* floor 0 */
+ floormemo[i]=alloca(sizeof(*floormemo[i])*
+ floor0_memosize(ci->floor_param[floorno]));
+ floormemo[i]=floor0_inverse1(vd,ci->floor_param[floorno],floormemo[i]);
+ }
+
+ if(floormemo[i])
+ nonzero[i]=1;
+ else
+ nonzero[i]=0;
+ memset(vd->work[i],0,sizeof(*vd->work[i])*n/2);
+ }
+
+ /* channel coupling can 'dirty' the nonzero listing */
+ for(i=0;i<info->coupling_steps;i++){
+ if(nonzero[info->coupling[i].mag] ||
+ nonzero[info->coupling[i].ang]){
+ nonzero[info->coupling[i].mag]=1;
+ nonzero[info->coupling[i].ang]=1;
+ }
+ }
+
+ /* recover the residue into our working vectors */
+ for(i=0;i<info->submaps;i++){
+ int ch_in_bundle=0;
+ for(j=0;j<vi->channels;j++){
+ if(!info->chmuxlist || info->chmuxlist[j]==i){
+ if(nonzero[j])
+ zerobundle[ch_in_bundle]=1;
+ else
+ zerobundle[ch_in_bundle]=0;
+ pcmbundle[ch_in_bundle++]=vd->work[j];
+ }
+ }
+
+ res_inverse(vd,ci->residue_param+info->submaplist[i].residue,
+ pcmbundle,zerobundle,ch_in_bundle);
+ }
+
+ //for(j=0;j<vi->channels;j++)
+ //_analysis_output("coupled",seq+j,vb->pcm[j],-8,n/2,0,0);
+
+ /* channel coupling */
+ for(i=info->coupling_steps-1;i>=0;i--){
+ ogg_int32_t *pcmM=vd->work[info->coupling[i].mag];
+ ogg_int32_t *pcmA=vd->work[info->coupling[i].ang];
+
+ for(j=0;j<n/2;j++){
+ ogg_int32_t mag=pcmM[j];
+ ogg_int32_t ang=pcmA[j];
+
+ if(mag>0)
+ if(ang>0){
+ pcmM[j]=mag;
+ pcmA[j]=mag-ang;
+ }else{
+ pcmA[j]=mag;
+ pcmM[j]=mag+ang;
+ }
+ else
+ if(ang>0){
+ pcmM[j]=mag;
+ pcmA[j]=mag+ang;
+ }else{
+ pcmA[j]=mag;
+ pcmM[j]=mag-ang;
+ }
+ }
+ }
+
+ //for(j=0;j<vi->channels;j++)
+ //_analysis_output("residue",seq+j,vb->pcm[j],-8,n/2,0,0);
+
+ /* compute and apply spectral envelope */
+ for(i=0;i<vi->channels;i++){
+ ogg_int32_t *pcm=vd->work[i];
+ int submap=0;
+ int floorno;
+
+ if(info->submaps>1)
+ submap=info->chmuxlist[i];
+ floorno=info->submaplist[submap].floor;
+
+ if(ci->floor_type[floorno]){
+ /* floor 1 */
+ floor1_inverse2(vd,ci->floor_param[floorno],floormemo[i],pcm);
+ }else{
+ /* floor 0 */
+ floor0_inverse2(vd,ci->floor_param[floorno],floormemo[i],pcm);
+ }
+ }
+
+ //for(j=0;j<vi->channels;j++)
+ //_analysis_output("mdct",seq+j,vb->pcm[j],-24,n/2,0,1);
+
+ /* transform the PCM data; takes PCM vector, vb; modifies PCM vector */
+ /* only MDCT right now.... */
+ for(i=0;i<vi->channels;i++)
+ mdct_backward(n,vd->work[i]);
+
+ //for(j=0;j<vi->channels;j++)
+ //_analysis_output("imdct",seq+j,vb->pcm[j],-24,n,0,0);
+
+ /* all done! */
+ return(0);
+}
diff --git a/library/ADK2/v_mdct.c b/library/ADK2/v_mdct.c
new file mode 100644
index 0000000..cd393be
--- /dev/null
+++ b/library/ADK2/v_mdct.c
@@ -0,0 +1,487 @@
+#define ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: normalized modified discrete cosine transform
+ power of two length transform only [64 <= n ]
+ last mod: $Id: mdct.c,v 1.9.6.5 2003/04/29 04:03:27 xiphmont Exp $
+
+ Original algorithm adapted long ago from _The use of multirate filter
+ banks for coding of high quality digital audio_, by T. Sporer,
+ K. Brandenburg and B. Edler, collection of the European Signal
+ Processing Conference (EUSIPCO), Amsterdam, June 1992, Vol.1, pp
+ 211-214
+
+ The below code implements an algorithm that no longer looks much like
+ that presented in the paper, but the basic structure remains if you
+ dig deep enough to see it.
+
+ This module DOES NOT INCLUDE code to generate/apply the window
+ function. Everybody has their own weird favorite including me... I
+ happen to like the properties of y=sin(.5PI*sin^2(x)), but others may
+ vehemently disagree.
+
+ ********************************************************************/
+
+#include "v_ivorbiscodec.h"
+#include "v_os.h"
+#include "v_misc.h"
+#include "v_mdct.h"
+#include "v_mdct_lookup.h"
+
+STIN void presymmetry(DATA_TYPE *in,int n2,int step){
+ DATA_TYPE *aX;
+ DATA_TYPE *bX;
+ LOOKUP_T *T;
+ int n4=n2>>1;
+
+ aX = in+n2-3;
+ T = sincos_lookup0;
+
+ do{
+ REG_TYPE r0= aX[0];
+ REG_TYPE r2= aX[2];
+ XPROD31( r0, r2, T[0], T[1], &aX[0], &aX[2] ); T+=step;
+ aX-=4;
+ }while(aX>=in+n4);
+ do{
+ REG_TYPE r0= aX[0];
+ REG_TYPE r2= aX[2];
+ XPROD31( r0, r2, T[1], T[0], &aX[0], &aX[2] ); T-=step;
+ aX-=4;
+ }while(aX>=in);
+
+ aX = in+n2-4;
+ bX = in;
+ T = sincos_lookup0;
+ do{
+ REG_TYPE ri0= aX[0];
+ REG_TYPE ri2= aX[2];
+ REG_TYPE ro0= bX[0];
+ REG_TYPE ro2= bX[2];
+
+ XNPROD31( ro2, ro0, T[1], T[0], &aX[0], &aX[2] ); T+=step;
+ XNPROD31( ri2, ri0, T[0], T[1], &bX[0], &bX[2] );
+
+ aX-=4;
+ bX+=4;
+ }while(aX>=in+n4);
+
+}
+
+/* 8 point butterfly (in place) */
+STIN void mdct_butterfly_8(DATA_TYPE *x){
+
+ REG_TYPE r0 = x[0] + x[1];
+ REG_TYPE r1 = x[0] - x[1];
+ REG_TYPE r2 = x[2] + x[3];
+ REG_TYPE r3 = x[2] - x[3];
+ REG_TYPE r4 = x[4] + x[5];
+ REG_TYPE r5 = x[4] - x[5];
+ REG_TYPE r6 = x[6] + x[7];
+ REG_TYPE r7 = x[6] - x[7];
+
+ x[0] = r5 + r3;
+ x[1] = r7 - r1;
+ x[2] = r5 - r3;
+ x[3] = r7 + r1;
+ x[4] = r4 - r0;
+ x[5] = r6 - r2;
+ x[6] = r4 + r0;
+ x[7] = r6 + r2;
+ MB();
+}
+
+/* 16 point butterfly (in place, 4 register) */
+STIN void mdct_butterfly_16(DATA_TYPE *x){
+
+ REG_TYPE r0, r1, r2, r3;
+
+ r0 = x[ 8] - x[ 9]; x[ 8] += x[ 9];
+ r1 = x[10] - x[11]; x[10] += x[11];
+ r2 = x[ 1] - x[ 0]; x[ 9] = x[ 1] + x[0];
+ r3 = x[ 3] - x[ 2]; x[11] = x[ 3] + x[2];
+ x[ 0] = MULT31((r0 - r1) , cPI2_8);
+ x[ 1] = MULT31((r2 + r3) , cPI2_8);
+ x[ 2] = MULT31((r0 + r1) , cPI2_8);
+ x[ 3] = MULT31((r3 - r2) , cPI2_8);
+ MB();
+
+ r2 = x[12] - x[13]; x[12] += x[13];
+ r3 = x[14] - x[15]; x[14] += x[15];
+ r0 = x[ 4] - x[ 5]; x[13] = x[ 5] + x[ 4];
+ r1 = x[ 7] - x[ 6]; x[15] = x[ 7] + x[ 6];
+ x[ 4] = r2; x[ 5] = r1;
+ x[ 6] = r3; x[ 7] = r0;
+ MB();
+
+ mdct_butterfly_8(x);
+ mdct_butterfly_8(x+8);
+}
+
+/* 32 point butterfly (in place, 4 register) */
+STIN void mdct_butterfly_32(DATA_TYPE *x){
+
+ REG_TYPE r0, r1, r2, r3;
+
+ r0 = x[16] - x[17]; x[16] += x[17];
+ r1 = x[18] - x[19]; x[18] += x[19];
+ r2 = x[ 1] - x[ 0]; x[17] = x[ 1] + x[ 0];
+ r3 = x[ 3] - x[ 2]; x[19] = x[ 3] + x[ 2];
+ XNPROD31( r0, r1, cPI3_8, cPI1_8, &x[ 0], &x[ 2] );
+ XPROD31 ( r2, r3, cPI1_8, cPI3_8, &x[ 1], &x[ 3] );
+ MB();
+
+ r0 = x[20] - x[21]; x[20] += x[21];
+ r1 = x[22] - x[23]; x[22] += x[23];
+ r2 = x[ 5] - x[ 4]; x[21] = x[ 5] + x[ 4];
+ r3 = x[ 7] - x[ 6]; x[23] = x[ 7] + x[ 6];
+ x[ 4] = MULT31((r0 - r1) , cPI2_8);
+ x[ 5] = MULT31((r3 + r2) , cPI2_8);
+ x[ 6] = MULT31((r0 + r1) , cPI2_8);
+ x[ 7] = MULT31((r3 - r2) , cPI2_8);
+ MB();
+
+ r0 = x[24] - x[25]; x[24] += x[25];
+ r1 = x[26] - x[27]; x[26] += x[27];
+ r2 = x[ 9] - x[ 8]; x[25] = x[ 9] + x[ 8];
+ r3 = x[11] - x[10]; x[27] = x[11] + x[10];
+ XNPROD31( r0, r1, cPI1_8, cPI3_8, &x[ 8], &x[10] );
+ XPROD31 ( r2, r3, cPI3_8, cPI1_8, &x[ 9], &x[11] );
+ MB();
+
+ r0 = x[28] - x[29]; x[28] += x[29];
+ r1 = x[30] - x[31]; x[30] += x[31];
+ r2 = x[12] - x[13]; x[29] = x[13] + x[12];
+ r3 = x[15] - x[14]; x[31] = x[15] + x[14];
+ x[12] = r0; x[13] = r3;
+ x[14] = r1; x[15] = r2;
+ MB();
+
+ mdct_butterfly_16(x);
+ mdct_butterfly_16(x+16);
+}
+
+/* N/stage point generic N stage butterfly (in place, 2 register) */
+STIN void mdct_butterfly_generic(DATA_TYPE *x,int points,int step){
+
+ LOOKUP_T *T = sincos_lookup0;
+ DATA_TYPE *x1 = x + points - 4;
+ DATA_TYPE *x2 = x + (points>>1) - 4;
+ REG_TYPE r0, r1, r2, r3;
+
+ do{
+ r0 = x1[0] - x1[1]; x1[0] += x1[1];
+ r1 = x1[3] - x1[2]; x1[2] += x1[3];
+ r2 = x2[1] - x2[0]; x1[1] = x2[1] + x2[0];
+ r3 = x2[3] - x2[2]; x1[3] = x2[3] + x2[2];
+ XPROD31( r1, r0, T[0], T[1], &x2[0], &x2[2] );
+ XPROD31( r2, r3, T[0], T[1], &x2[1], &x2[3] ); T+=step;
+ x1-=4;
+ x2-=4;
+ }while(T<sincos_lookup0+1024);
+ do{
+ r0 = x1[0] - x1[1]; x1[0] += x1[1];
+ r1 = x1[2] - x1[3]; x1[2] += x1[3];
+ r2 = x2[0] - x2[1]; x1[1] = x2[1] + x2[0];
+ r3 = x2[3] - x2[2]; x1[3] = x2[3] + x2[2];
+ XNPROD31( r0, r1, T[0], T[1], &x2[0], &x2[2] );
+ XNPROD31( r3, r2, T[0], T[1], &x2[1], &x2[3] ); T-=step;
+ x1-=4;
+ x2-=4;
+ }while(T>sincos_lookup0);
+}
+
+STIN void mdct_butterflies(DATA_TYPE *x,int points,int shift){
+
+ int stages=8-shift;
+ int i,j;
+
+ for(i=0;--stages>0;i++){
+ for(j=0;j<(1<<i);j++)
+ mdct_butterfly_generic(x+(points>>i)*j,points>>i,4<<(i+shift));
+ }
+
+ for(j=0;j<points;j+=32)
+ mdct_butterfly_32(x+j);
+}
+
+static unsigned char bitrev[16]={0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15};
+
+STIN int bitrev12(int x){
+ return bitrev[x>>8]|(bitrev[(x&0x0f0)>>4]<<4)|(((int)bitrev[x&0x00f])<<8);
+}
+
+STIN void mdct_bitreverse(DATA_TYPE *x,int n,int shift){
+ int bit = 0;
+ DATA_TYPE *w = x+(n>>1);
+
+ do{
+ DATA_TYPE b = bitrev12(bit++);
+ DATA_TYPE *xx = x + (b>>shift);
+ REG_TYPE r;
+
+ w -= 2;
+
+ if(w>xx){
+
+ r = xx[0];
+ xx[0] = w[0];
+ w[0] = r;
+
+ r = xx[1];
+ xx[1] = w[1];
+ w[1] = r;
+ }
+ }while(w>x);
+}
+
+STIN void mdct_step7(DATA_TYPE *x,int n,int step){
+ DATA_TYPE *w0 = x;
+ DATA_TYPE *w1 = x+(n>>1);
+ LOOKUP_T *T = (step>=4)?(sincos_lookup0+(step>>1)):sincos_lookup1;
+ LOOKUP_T *Ttop = T+1024;
+ REG_TYPE r0, r1, r2, r3;
+
+ do{
+ w1 -= 2;
+
+ r0 = w0[0] + w1[0];
+ r1 = w1[1] - w0[1];
+ r2 = MULT32(r0, T[1]) + MULT32(r1, T[0]);
+ r3 = MULT32(r1, T[1]) - MULT32(r0, T[0]);
+ T+=step;
+
+ r0 = (w0[1] + w1[1])>>1;
+ r1 = (w0[0] - w1[0])>>1;
+ w0[0] = r0 + r2;
+ w0[1] = r1 + r3;
+ w1[0] = r0 - r2;
+ w1[1] = r3 - r1;
+
+ w0 += 2;
+ }while(T<Ttop);
+ do{
+ w1 -= 2;
+
+ r0 = w0[0] + w1[0];
+ r1 = w1[1] - w0[1];
+ T-=step;
+ r2 = MULT32(r0, T[0]) + MULT32(r1, T[1]);
+ r3 = MULT32(r1, T[0]) - MULT32(r0, T[1]);
+
+ r0 = (w0[1] + w1[1])>>1;
+ r1 = (w0[0] - w1[0])>>1;
+ w0[0] = r0 + r2;
+ w0[1] = r1 + r3;
+ w1[0] = r0 - r2;
+ w1[1] = r3 - r1;
+
+ w0 += 2;
+ }while(w0<w1);
+}
+
+STIN void mdct_step8(DATA_TYPE *x, int n, int step){
+ LOOKUP_T *T;
+ LOOKUP_T *V;
+ DATA_TYPE *iX =x+(n>>1);
+ step>>=2;
+
+ switch(step) {
+ default:
+ T=(step>=4)?(sincos_lookup0+(step>>1)):sincos_lookup1;
+ do{
+ REG_TYPE r0 = x[0];
+ REG_TYPE r1 = -x[1];
+ XPROD31( r0, r1, T[0], T[1], x, x+1); T+=step;
+ x +=2;
+ }while(x<iX);
+ break;
+
+ case 1:
+ {
+ /* linear interpolation between table values: offset=0.5, step=1 */
+ REG_TYPE t0,t1,v0,v1,r0,r1;
+ T = sincos_lookup0;
+ V = sincos_lookup1;
+ t0 = (*T++)>>1;
+ t1 = (*T++)>>1;
+ do{
+ r0 = x[0];
+ r1 = -x[1];
+ t0 += (v0 = (*V++)>>1);
+ t1 += (v1 = (*V++)>>1);
+ XPROD31( r0, r1, t0, t1, x, x+1 );
+
+ r0 = x[2];
+ r1 = -x[3];
+ v0 += (t0 = (*T++)>>1);
+ v1 += (t1 = (*T++)>>1);
+ XPROD31( r0, r1, v0, v1, x+2, x+3 );
+
+ x += 4;
+ }while(x<iX);
+ break;
+ }
+
+ case 0:
+ {
+ /* linear interpolation between table values: offset=0.25, step=0.5 */
+ REG_TYPE t0,t1,v0,v1,q0,q1,r0,r1;
+ T = sincos_lookup0;
+ V = sincos_lookup1;
+ t0 = *T++;
+ t1 = *T++;
+ do{
+
+
+ v0 = *V++;
+ v1 = *V++;
+ t0 += (q0 = (v0-t0)>>2);
+ t1 += (q1 = (v1-t1)>>2);
+ r0 = x[0];
+ r1 = -x[1];
+ XPROD31( r0, r1, t0, t1, x, x+1 );
+ t0 = v0-q0;
+ t1 = v1-q1;
+ r0 = x[2];
+ r1 = -x[3];
+ XPROD31( r0, r1, t0, t1, x+2, x+3 );
+
+ t0 = *T++;
+ t1 = *T++;
+ v0 += (q0 = (t0-v0)>>2);
+ v1 += (q1 = (t1-v1)>>2);
+ r0 = x[4];
+ r1 = -x[5];
+ XPROD31( r0, r1, v0, v1, x+4, x+5 );
+ v0 = t0-q0;
+ v1 = t1-q1;
+ r0 = x[6];
+ r1 = -x[7];
+ XPROD31( r0, r1, v0, v1, x+5, x+6 );
+
+ x+=8;
+ }while(x<iX);
+ break;
+ }
+ }
+}
+
+/* partial; doesn't perform last-step deinterleave/unrolling. That
+ can be done more efficiently during pcm output */
+void mdct_backward(int n, DATA_TYPE *in){
+ int shift;
+ int step;
+
+ for (shift=4;!(n&(1<<shift));shift++);
+ shift=13-shift;
+ step=2<<shift;
+
+ presymmetry(in,n>>1,step);
+ mdct_butterflies(in,n>>1,shift);
+ mdct_bitreverse(in,n,shift);
+ mdct_step7(in,n,step);
+ mdct_step8(in,n,step);
+}
+
+void mdct_shift_right(int n, DATA_TYPE *in, DATA_TYPE *right){
+ int i;
+ n>>=2;
+ in+=1;
+
+ for(i=0;i<n;i++)
+ right[i]=in[i<<1];
+}
+
+void mdct_unroll_lap(int n0,int n1,
+ int lW,int W,
+ DATA_TYPE *in,
+ DATA_TYPE *right,
+ LOOKUP_T *w0,
+ LOOKUP_T *w1,
+ ogg_int16_t *out,
+ int step,
+ int start, /* samples, this frame */
+ int end /* samples, this frame */){
+
+ DATA_TYPE *l=in+(W&&lW ? n1>>1 : n0>>1);
+ DATA_TYPE *r=right+(lW ? n1>>2 : n0>>2);
+ DATA_TYPE *post;
+ LOOKUP_T *wR=(W && lW ? w1+(n1>>1) : w0+(n0>>1));
+ LOOKUP_T *wL=(W && lW ? w1 : w0 );
+
+ int preLap=(lW && !W ? (n1>>2)-(n0>>2) : 0 );
+ int halfLap=(lW && W ? (n1>>2) : (n0>>2) );
+ int postLap=(!lW && W ? (n1>>2)-(n0>>2) : 0 );
+ int n,off;
+
+ /* preceeding direct-copy lapping from previous frame, if any */
+ if(preLap){
+ n = (end<preLap?end:preLap);
+ off = (start<preLap?start:preLap);
+ post = r-n;
+ r -= off;
+ start -= off;
+ end -= n;
+ while(r>post){
+ *out = CLIP_TO_15((*--r)>>9);
+ out+=step;
+ }
+ }
+
+ /* cross-lap; two halves due to wrap-around */
+ n = (end<halfLap?end:halfLap);
+ off = (start<halfLap?start:halfLap);
+ post = r-n;
+ r -= off;
+ l -= off*2;
+ start -= off;
+ wR -= off;
+ wL += off;
+ end -= n;
+ while(r>post){
+ l-=2;
+ *out = CLIP_TO_15((MULT31(*--r,*--wR) + MULT31(*l,*wL++))>>9);
+ out+=step;
+ }
+
+ n = (end<halfLap?end:halfLap);
+ off = (start<halfLap?start:halfLap);
+ post = r+n;
+ r += off;
+ l += off*2;
+ start -= off;
+ end -= n;
+ wR -= off;
+ wL += off;
+ while(r<post){
+ *out = CLIP_TO_15((MULT31(*r++,*--wR) - MULT31(*l,*wL++))>>9);
+ out+=step;
+ l+=2;
+ }
+
+ /* preceeding direct-copy lapping from previous frame, if any */
+ if(postLap){
+ n = (end<postLap?end:postLap);
+ off = (start<postLap?start:postLap);
+ post = l+n*2;
+ l += off*2;
+ while(l<post){
+ *out = CLIP_TO_15((-*l)>>9);
+ out+=step;
+ l+=2;
+ }
+ }
+}
+
diff --git a/library/ADK2/v_mdct.h b/library/ADK2/v_mdct.h
new file mode 100644
index 0000000..6248179
--- /dev/null
+++ b/library/ADK2/v_mdct.h
@@ -0,0 +1,62 @@
+#ifdef ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: modified discrete cosine transform prototypes
+
+ ********************************************************************/
+
+#ifndef _OGG_mdct_H_
+#define _OGG_mdct_H_
+
+#include "v_ivorbiscodec.h"
+#include "v_misc.h"
+
+#define DATA_TYPE ogg_int32_t
+#define REG_TYPE register ogg_int32_t
+
+#ifdef _LOW_ACCURACY_
+#define cPI3_8 (0x0062)
+#define cPI2_8 (0x00b5)
+#define cPI1_8 (0x00ed)
+#else
+#define cPI3_8 (0x30fbc54d)
+#define cPI2_8 (0x5a82799a)
+#define cPI1_8 (0x7641af3d)
+#endif
+
+extern void mdct_backward(int n, DATA_TYPE *in);
+extern void mdct_shift_right(int n, DATA_TYPE *in, DATA_TYPE *right);
+extern void mdct_unroll_lap(int n0,int n1,
+ int lW,int W,
+ DATA_TYPE *in,DATA_TYPE *right,
+ LOOKUP_T *w0,LOOKUP_T *w1,
+ ogg_int16_t *out,
+ int step,
+ int start,int end /* samples, this frame */);
+
+#endif
+
+
+
+
+
+
+
+
+
+
+
+
+#endif
+
diff --git a/library/ADK2/v_mdct_lookup.h b/library/ADK2/v_mdct_lookup.h
new file mode 100644
index 0000000..4e51ced
--- /dev/null
+++ b/library/ADK2/v_mdct_lookup.h
@@ -0,0 +1,543 @@
+#ifdef ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2002 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: sin,cos lookup tables
+
+ ********************************************************************/
+
+#include "v_os_types.h"
+
+/* {sin(2*i*PI/4096), cos(2*i*PI/4096)}, with i = 0 to 512 */
+static LOOKUP_T sincos_lookup0[1026] = {
+ X(0x00000000), X(0x7fffffff), X(0x003243f5), X(0x7ffff621),
+ X(0x006487e3), X(0x7fffd886), X(0x0096cbc1), X(0x7fffa72c),
+ X(0x00c90f88), X(0x7fff6216), X(0x00fb5330), X(0x7fff0943),
+ X(0x012d96b1), X(0x7ffe9cb2), X(0x015fda03), X(0x7ffe1c65),
+ X(0x01921d20), X(0x7ffd885a), X(0x01c45ffe), X(0x7ffce093),
+ X(0x01f6a297), X(0x7ffc250f), X(0x0228e4e2), X(0x7ffb55ce),
+ X(0x025b26d7), X(0x7ffa72d1), X(0x028d6870), X(0x7ff97c18),
+ X(0x02bfa9a4), X(0x7ff871a2), X(0x02f1ea6c), X(0x7ff75370),
+ X(0x03242abf), X(0x7ff62182), X(0x03566a96), X(0x7ff4dbd9),
+ X(0x0388a9ea), X(0x7ff38274), X(0x03bae8b2), X(0x7ff21553),
+ X(0x03ed26e6), X(0x7ff09478), X(0x041f6480), X(0x7feeffe1),
+ X(0x0451a177), X(0x7fed5791), X(0x0483ddc3), X(0x7feb9b85),
+ X(0x04b6195d), X(0x7fe9cbc0), X(0x04e8543e), X(0x7fe7e841),
+ X(0x051a8e5c), X(0x7fe5f108), X(0x054cc7b1), X(0x7fe3e616),
+ X(0x057f0035), X(0x7fe1c76b), X(0x05b137df), X(0x7fdf9508),
+ X(0x05e36ea9), X(0x7fdd4eec), X(0x0615a48b), X(0x7fdaf519),
+ X(0x0647d97c), X(0x7fd8878e), X(0x067a0d76), X(0x7fd6064c),
+ X(0x06ac406f), X(0x7fd37153), X(0x06de7262), X(0x7fd0c8a3),
+ X(0x0710a345), X(0x7fce0c3e), X(0x0742d311), X(0x7fcb3c23),
+ X(0x077501be), X(0x7fc85854), X(0x07a72f45), X(0x7fc560cf),
+ X(0x07d95b9e), X(0x7fc25596), X(0x080b86c2), X(0x7fbf36aa),
+ X(0x083db0a7), X(0x7fbc040a), X(0x086fd947), X(0x7fb8bdb8),
+ X(0x08a2009a), X(0x7fb563b3), X(0x08d42699), X(0x7fb1f5fc),
+ X(0x09064b3a), X(0x7fae7495), X(0x09386e78), X(0x7faadf7c),
+ X(0x096a9049), X(0x7fa736b4), X(0x099cb0a7), X(0x7fa37a3c),
+ X(0x09cecf89), X(0x7f9faa15), X(0x0a00ece8), X(0x7f9bc640),
+ X(0x0a3308bd), X(0x7f97cebd), X(0x0a6522fe), X(0x7f93c38c),
+ X(0x0a973ba5), X(0x7f8fa4b0), X(0x0ac952aa), X(0x7f8b7227),
+ X(0x0afb6805), X(0x7f872bf3), X(0x0b2d7baf), X(0x7f82d214),
+ X(0x0b5f8d9f), X(0x7f7e648c), X(0x0b919dcf), X(0x7f79e35a),
+ X(0x0bc3ac35), X(0x7f754e80), X(0x0bf5b8cb), X(0x7f70a5fe),
+ X(0x0c27c389), X(0x7f6be9d4), X(0x0c59cc68), X(0x7f671a05),
+ X(0x0c8bd35e), X(0x7f62368f), X(0x0cbdd865), X(0x7f5d3f75),
+ X(0x0cefdb76), X(0x7f5834b7), X(0x0d21dc87), X(0x7f531655),
+ X(0x0d53db92), X(0x7f4de451), X(0x0d85d88f), X(0x7f489eaa),
+ X(0x0db7d376), X(0x7f434563), X(0x0de9cc40), X(0x7f3dd87c),
+ X(0x0e1bc2e4), X(0x7f3857f6), X(0x0e4db75b), X(0x7f32c3d1),
+ X(0x0e7fa99e), X(0x7f2d1c0e), X(0x0eb199a4), X(0x7f2760af),
+ X(0x0ee38766), X(0x7f2191b4), X(0x0f1572dc), X(0x7f1baf1e),
+ X(0x0f475bff), X(0x7f15b8ee), X(0x0f7942c7), X(0x7f0faf25),
+ X(0x0fab272b), X(0x7f0991c4), X(0x0fdd0926), X(0x7f0360cb),
+ X(0x100ee8ad), X(0x7efd1c3c), X(0x1040c5bb), X(0x7ef6c418),
+ X(0x1072a048), X(0x7ef05860), X(0x10a4784b), X(0x7ee9d914),
+ X(0x10d64dbd), X(0x7ee34636), X(0x11082096), X(0x7edc9fc6),
+ X(0x1139f0cf), X(0x7ed5e5c6), X(0x116bbe60), X(0x7ecf1837),
+ X(0x119d8941), X(0x7ec8371a), X(0x11cf516a), X(0x7ec14270),
+ X(0x120116d5), X(0x7eba3a39), X(0x1232d979), X(0x7eb31e78),
+ X(0x1264994e), X(0x7eabef2c), X(0x1296564d), X(0x7ea4ac58),
+ X(0x12c8106f), X(0x7e9d55fc), X(0x12f9c7aa), X(0x7e95ec1a),
+ X(0x132b7bf9), X(0x7e8e6eb2), X(0x135d2d53), X(0x7e86ddc6),
+ X(0x138edbb1), X(0x7e7f3957), X(0x13c0870a), X(0x7e778166),
+ X(0x13f22f58), X(0x7e6fb5f4), X(0x1423d492), X(0x7e67d703),
+ X(0x145576b1), X(0x7e5fe493), X(0x148715ae), X(0x7e57dea7),
+ X(0x14b8b17f), X(0x7e4fc53e), X(0x14ea4a1f), X(0x7e47985b),
+ X(0x151bdf86), X(0x7e3f57ff), X(0x154d71aa), X(0x7e37042a),
+ X(0x157f0086), X(0x7e2e9cdf), X(0x15b08c12), X(0x7e26221f),
+ X(0x15e21445), X(0x7e1d93ea), X(0x16139918), X(0x7e14f242),
+ X(0x16451a83), X(0x7e0c3d29), X(0x1676987f), X(0x7e0374a0),
+ X(0x16a81305), X(0x7dfa98a8), X(0x16d98a0c), X(0x7df1a942),
+ X(0x170afd8d), X(0x7de8a670), X(0x173c6d80), X(0x7ddf9034),
+ X(0x176dd9de), X(0x7dd6668f), X(0x179f429f), X(0x7dcd2981),
+ X(0x17d0a7bc), X(0x7dc3d90d), X(0x1802092c), X(0x7dba7534),
+ X(0x183366e9), X(0x7db0fdf8), X(0x1864c0ea), X(0x7da77359),
+ X(0x18961728), X(0x7d9dd55a), X(0x18c7699b), X(0x7d9423fc),
+ X(0x18f8b83c), X(0x7d8a5f40), X(0x192a0304), X(0x7d808728),
+ X(0x195b49ea), X(0x7d769bb5), X(0x198c8ce7), X(0x7d6c9ce9),
+ X(0x19bdcbf3), X(0x7d628ac6), X(0x19ef0707), X(0x7d58654d),
+ X(0x1a203e1b), X(0x7d4e2c7f), X(0x1a517128), X(0x7d43e05e),
+ X(0x1a82a026), X(0x7d3980ec), X(0x1ab3cb0d), X(0x7d2f0e2b),
+ X(0x1ae4f1d6), X(0x7d24881b), X(0x1b161479), X(0x7d19eebf),
+ X(0x1b4732ef), X(0x7d0f4218), X(0x1b784d30), X(0x7d048228),
+ X(0x1ba96335), X(0x7cf9aef0), X(0x1bda74f6), X(0x7ceec873),
+ X(0x1c0b826a), X(0x7ce3ceb2), X(0x1c3c8b8c), X(0x7cd8c1ae),
+ X(0x1c6d9053), X(0x7ccda169), X(0x1c9e90b8), X(0x7cc26de5),
+ X(0x1ccf8cb3), X(0x7cb72724), X(0x1d00843d), X(0x7cabcd28),
+ X(0x1d31774d), X(0x7ca05ff1), X(0x1d6265dd), X(0x7c94df83),
+ X(0x1d934fe5), X(0x7c894bde), X(0x1dc4355e), X(0x7c7da505),
+ X(0x1df5163f), X(0x7c71eaf9), X(0x1e25f282), X(0x7c661dbc),
+ X(0x1e56ca1e), X(0x7c5a3d50), X(0x1e879d0d), X(0x7c4e49b7),
+ X(0x1eb86b46), X(0x7c4242f2), X(0x1ee934c3), X(0x7c362904),
+ X(0x1f19f97b), X(0x7c29fbee), X(0x1f4ab968), X(0x7c1dbbb3),
+ X(0x1f7b7481), X(0x7c116853), X(0x1fac2abf), X(0x7c0501d2),
+ X(0x1fdcdc1b), X(0x7bf88830), X(0x200d888d), X(0x7bebfb70),
+ X(0x203e300d), X(0x7bdf5b94), X(0x206ed295), X(0x7bd2a89e),
+ X(0x209f701c), X(0x7bc5e290), X(0x20d0089c), X(0x7bb9096b),
+ X(0x21009c0c), X(0x7bac1d31), X(0x21312a65), X(0x7b9f1de6),
+ X(0x2161b3a0), X(0x7b920b89), X(0x219237b5), X(0x7b84e61f),
+ X(0x21c2b69c), X(0x7b77ada8), X(0x21f3304f), X(0x7b6a6227),
+ X(0x2223a4c5), X(0x7b5d039e), X(0x225413f8), X(0x7b4f920e),
+ X(0x22847de0), X(0x7b420d7a), X(0x22b4e274), X(0x7b3475e5),
+ X(0x22e541af), X(0x7b26cb4f), X(0x23159b88), X(0x7b190dbc),
+ X(0x2345eff8), X(0x7b0b3d2c), X(0x23763ef7), X(0x7afd59a4),
+ X(0x23a6887f), X(0x7aef6323), X(0x23d6cc87), X(0x7ae159ae),
+ X(0x24070b08), X(0x7ad33d45), X(0x243743fa), X(0x7ac50dec),
+ X(0x24677758), X(0x7ab6cba4), X(0x2497a517), X(0x7aa8766f),
+ X(0x24c7cd33), X(0x7a9a0e50), X(0x24f7efa2), X(0x7a8b9348),
+ X(0x25280c5e), X(0x7a7d055b), X(0x2558235f), X(0x7a6e648a),
+ X(0x2588349d), X(0x7a5fb0d8), X(0x25b84012), X(0x7a50ea47),
+ X(0x25e845b6), X(0x7a4210d8), X(0x26184581), X(0x7a332490),
+ X(0x26483f6c), X(0x7a24256f), X(0x26783370), X(0x7a151378),
+ X(0x26a82186), X(0x7a05eead), X(0x26d809a5), X(0x79f6b711),
+ X(0x2707ebc7), X(0x79e76ca7), X(0x2737c7e3), X(0x79d80f6f),
+ X(0x27679df4), X(0x79c89f6e), X(0x27976df1), X(0x79b91ca4),
+ X(0x27c737d3), X(0x79a98715), X(0x27f6fb92), X(0x7999dec4),
+ X(0x2826b928), X(0x798a23b1), X(0x2856708d), X(0x797a55e0),
+ X(0x288621b9), X(0x796a7554), X(0x28b5cca5), X(0x795a820e),
+ X(0x28e5714b), X(0x794a7c12), X(0x29150fa1), X(0x793a6361),
+ X(0x2944a7a2), X(0x792a37fe), X(0x29743946), X(0x7919f9ec),
+ X(0x29a3c485), X(0x7909a92d), X(0x29d34958), X(0x78f945c3),
+ X(0x2a02c7b8), X(0x78e8cfb2), X(0x2a323f9e), X(0x78d846fb),
+ X(0x2a61b101), X(0x78c7aba2), X(0x2a911bdc), X(0x78b6fda8),
+ X(0x2ac08026), X(0x78a63d11), X(0x2aefddd8), X(0x789569df),
+ X(0x2b1f34eb), X(0x78848414), X(0x2b4e8558), X(0x78738bb3),
+ X(0x2b7dcf17), X(0x786280bf), X(0x2bad1221), X(0x7851633b),
+ X(0x2bdc4e6f), X(0x78403329), X(0x2c0b83fa), X(0x782ef08b),
+ X(0x2c3ab2b9), X(0x781d9b65), X(0x2c69daa6), X(0x780c33b8),
+ X(0x2c98fbba), X(0x77fab989), X(0x2cc815ee), X(0x77e92cd9),
+ X(0x2cf72939), X(0x77d78daa), X(0x2d263596), X(0x77c5dc01),
+ X(0x2d553afc), X(0x77b417df), X(0x2d843964), X(0x77a24148),
+ X(0x2db330c7), X(0x7790583e), X(0x2de2211e), X(0x777e5cc3),
+ X(0x2e110a62), X(0x776c4edb), X(0x2e3fec8b), X(0x775a2e89),
+ X(0x2e6ec792), X(0x7747fbce), X(0x2e9d9b70), X(0x7735b6af),
+ X(0x2ecc681e), X(0x77235f2d), X(0x2efb2d95), X(0x7710f54c),
+ X(0x2f29ebcc), X(0x76fe790e), X(0x2f58a2be), X(0x76ebea77),
+ X(0x2f875262), X(0x76d94989), X(0x2fb5fab2), X(0x76c69647),
+ X(0x2fe49ba7), X(0x76b3d0b4), X(0x30133539), X(0x76a0f8d2),
+ X(0x3041c761), X(0x768e0ea6), X(0x30705217), X(0x767b1231),
+ X(0x309ed556), X(0x76680376), X(0x30cd5115), X(0x7654e279),
+ X(0x30fbc54d), X(0x7641af3d), X(0x312a31f8), X(0x762e69c4),
+ X(0x3158970e), X(0x761b1211), X(0x3186f487), X(0x7607a828),
+ X(0x31b54a5e), X(0x75f42c0b), X(0x31e39889), X(0x75e09dbd),
+ X(0x3211df04), X(0x75ccfd42), X(0x32401dc6), X(0x75b94a9c),
+ X(0x326e54c7), X(0x75a585cf), X(0x329c8402), X(0x7591aedd),
+ X(0x32caab6f), X(0x757dc5ca), X(0x32f8cb07), X(0x7569ca99),
+ X(0x3326e2c3), X(0x7555bd4c), X(0x3354f29b), X(0x75419de7),
+ X(0x3382fa88), X(0x752d6c6c), X(0x33b0fa84), X(0x751928e0),
+ X(0x33def287), X(0x7504d345), X(0x340ce28b), X(0x74f06b9e),
+ X(0x343aca87), X(0x74dbf1ef), X(0x3468aa76), X(0x74c7663a),
+ X(0x34968250), X(0x74b2c884), X(0x34c4520d), X(0x749e18cd),
+ X(0x34f219a8), X(0x7489571c), X(0x351fd918), X(0x74748371),
+ X(0x354d9057), X(0x745f9dd1), X(0x357b3f5d), X(0x744aa63f),
+ X(0x35a8e625), X(0x74359cbd), X(0x35d684a6), X(0x74208150),
+ X(0x36041ad9), X(0x740b53fb), X(0x3631a8b8), X(0x73f614c0),
+ X(0x365f2e3b), X(0x73e0c3a3), X(0x368cab5c), X(0x73cb60a8),
+ X(0x36ba2014), X(0x73b5ebd1), X(0x36e78c5b), X(0x73a06522),
+ X(0x3714f02a), X(0x738acc9e), X(0x37424b7b), X(0x73752249),
+ X(0x376f9e46), X(0x735f6626), X(0x379ce885), X(0x73499838),
+ X(0x37ca2a30), X(0x7333b883), X(0x37f76341), X(0x731dc70a),
+ X(0x382493b0), X(0x7307c3d0), X(0x3851bb77), X(0x72f1aed9),
+ X(0x387eda8e), X(0x72db8828), X(0x38abf0ef), X(0x72c54fc1),
+ X(0x38d8fe93), X(0x72af05a7), X(0x39060373), X(0x7298a9dd),
+ X(0x3932ff87), X(0x72823c67), X(0x395ff2c9), X(0x726bbd48),
+ X(0x398cdd32), X(0x72552c85), X(0x39b9bebc), X(0x723e8a20),
+ X(0x39e6975e), X(0x7227d61c), X(0x3a136712), X(0x7211107e),
+ X(0x3a402dd2), X(0x71fa3949), X(0x3a6ceb96), X(0x71e35080),
+ X(0x3a99a057), X(0x71cc5626), X(0x3ac64c0f), X(0x71b54a41),
+ X(0x3af2eeb7), X(0x719e2cd2), X(0x3b1f8848), X(0x7186fdde),
+ X(0x3b4c18ba), X(0x716fbd68), X(0x3b78a007), X(0x71586b74),
+ X(0x3ba51e29), X(0x71410805), X(0x3bd19318), X(0x7129931f),
+ X(0x3bfdfecd), X(0x71120cc5), X(0x3c2a6142), X(0x70fa74fc),
+ X(0x3c56ba70), X(0x70e2cbc6), X(0x3c830a50), X(0x70cb1128),
+ X(0x3caf50da), X(0x70b34525), X(0x3cdb8e09), X(0x709b67c0),
+ X(0x3d07c1d6), X(0x708378ff), X(0x3d33ec39), X(0x706b78e3),
+ X(0x3d600d2c), X(0x70536771), X(0x3d8c24a8), X(0x703b44ad),
+ X(0x3db832a6), X(0x7023109a), X(0x3de4371f), X(0x700acb3c),
+ X(0x3e10320d), X(0x6ff27497), X(0x3e3c2369), X(0x6fda0cae),
+ X(0x3e680b2c), X(0x6fc19385), X(0x3e93e950), X(0x6fa90921),
+ X(0x3ebfbdcd), X(0x6f906d84), X(0x3eeb889c), X(0x6f77c0b3),
+ X(0x3f1749b8), X(0x6f5f02b2), X(0x3f430119), X(0x6f463383),
+ X(0x3f6eaeb8), X(0x6f2d532c), X(0x3f9a5290), X(0x6f1461b0),
+ X(0x3fc5ec98), X(0x6efb5f12), X(0x3ff17cca), X(0x6ee24b57),
+ X(0x401d0321), X(0x6ec92683), X(0x40487f94), X(0x6eaff099),
+ X(0x4073f21d), X(0x6e96a99d), X(0x409f5ab6), X(0x6e7d5193),
+ X(0x40cab958), X(0x6e63e87f), X(0x40f60dfb), X(0x6e4a6e66),
+ X(0x4121589b), X(0x6e30e34a), X(0x414c992f), X(0x6e174730),
+ X(0x4177cfb1), X(0x6dfd9a1c), X(0x41a2fc1a), X(0x6de3dc11),
+ X(0x41ce1e65), X(0x6dca0d14), X(0x41f93689), X(0x6db02d29),
+ X(0x42244481), X(0x6d963c54), X(0x424f4845), X(0x6d7c3a98),
+ X(0x427a41d0), X(0x6d6227fa), X(0x42a5311b), X(0x6d48047e),
+ X(0x42d0161e), X(0x6d2dd027), X(0x42faf0d4), X(0x6d138afb),
+ X(0x4325c135), X(0x6cf934fc), X(0x4350873c), X(0x6cdece2f),
+ X(0x437b42e1), X(0x6cc45698), X(0x43a5f41e), X(0x6ca9ce3b),
+ X(0x43d09aed), X(0x6c8f351c), X(0x43fb3746), X(0x6c748b3f),
+ X(0x4425c923), X(0x6c59d0a9), X(0x4450507e), X(0x6c3f055d),
+ X(0x447acd50), X(0x6c242960), X(0x44a53f93), X(0x6c093cb6),
+ X(0x44cfa740), X(0x6bee3f62), X(0x44fa0450), X(0x6bd3316a),
+ X(0x452456bd), X(0x6bb812d1), X(0x454e9e80), X(0x6b9ce39b),
+ X(0x4578db93), X(0x6b81a3cd), X(0x45a30df0), X(0x6b66536b),
+ X(0x45cd358f), X(0x6b4af279), X(0x45f7526b), X(0x6b2f80fb),
+ X(0x4621647d), X(0x6b13fef5), X(0x464b6bbe), X(0x6af86c6c),
+ X(0x46756828), X(0x6adcc964), X(0x469f59b4), X(0x6ac115e2),
+ X(0x46c9405c), X(0x6aa551e9), X(0x46f31c1a), X(0x6a897d7d),
+ X(0x471cece7), X(0x6a6d98a4), X(0x4746b2bc), X(0x6a51a361),
+ X(0x47706d93), X(0x6a359db9), X(0x479a1d67), X(0x6a1987b0),
+ X(0x47c3c22f), X(0x69fd614a), X(0x47ed5be6), X(0x69e12a8c),
+ X(0x4816ea86), X(0x69c4e37a), X(0x48406e08), X(0x69a88c19),
+ X(0x4869e665), X(0x698c246c), X(0x48935397), X(0x696fac78),
+ X(0x48bcb599), X(0x69532442), X(0x48e60c62), X(0x69368bce),
+ X(0x490f57ee), X(0x6919e320), X(0x49389836), X(0x68fd2a3d),
+ X(0x4961cd33), X(0x68e06129), X(0x498af6df), X(0x68c387e9),
+ X(0x49b41533), X(0x68a69e81), X(0x49dd282a), X(0x6889a4f6),
+ X(0x4a062fbd), X(0x686c9b4b), X(0x4a2f2be6), X(0x684f8186),
+ X(0x4a581c9e), X(0x683257ab), X(0x4a8101de), X(0x68151dbe),
+ X(0x4aa9dba2), X(0x67f7d3c5), X(0x4ad2a9e2), X(0x67da79c3),
+ X(0x4afb6c98), X(0x67bd0fbd), X(0x4b2423be), X(0x679f95b7),
+ X(0x4b4ccf4d), X(0x67820bb7), X(0x4b756f40), X(0x676471c0),
+ X(0x4b9e0390), X(0x6746c7d8), X(0x4bc68c36), X(0x67290e02),
+ X(0x4bef092d), X(0x670b4444), X(0x4c177a6e), X(0x66ed6aa1),
+ X(0x4c3fdff4), X(0x66cf8120), X(0x4c6839b7), X(0x66b187c3),
+ X(0x4c9087b1), X(0x66937e91), X(0x4cb8c9dd), X(0x6675658c),
+ X(0x4ce10034), X(0x66573cbb), X(0x4d092ab0), X(0x66390422),
+ X(0x4d31494b), X(0x661abbc5), X(0x4d595bfe), X(0x65fc63a9),
+ X(0x4d8162c4), X(0x65ddfbd3), X(0x4da95d96), X(0x65bf8447),
+ X(0x4dd14c6e), X(0x65a0fd0b), X(0x4df92f46), X(0x65826622),
+ X(0x4e210617), X(0x6563bf92), X(0x4e48d0dd), X(0x6545095f),
+ X(0x4e708f8f), X(0x6526438f), X(0x4e984229), X(0x65076e25),
+ X(0x4ebfe8a5), X(0x64e88926), X(0x4ee782fb), X(0x64c99498),
+ X(0x4f0f1126), X(0x64aa907f), X(0x4f369320), X(0x648b7ce0),
+ X(0x4f5e08e3), X(0x646c59bf), X(0x4f857269), X(0x644d2722),
+ X(0x4faccfab), X(0x642de50d), X(0x4fd420a4), X(0x640e9386),
+ X(0x4ffb654d), X(0x63ef3290), X(0x50229da1), X(0x63cfc231),
+ X(0x5049c999), X(0x63b0426d), X(0x5070e92f), X(0x6390b34a),
+ X(0x5097fc5e), X(0x637114cc), X(0x50bf031f), X(0x635166f9),
+ X(0x50e5fd6d), X(0x6331a9d4), X(0x510ceb40), X(0x6311dd64),
+ X(0x5133cc94), X(0x62f201ac), X(0x515aa162), X(0x62d216b3),
+ X(0x518169a5), X(0x62b21c7b), X(0x51a82555), X(0x6292130c),
+ X(0x51ced46e), X(0x6271fa69), X(0x51f576ea), X(0x6251d298),
+ X(0x521c0cc2), X(0x62319b9d), X(0x524295f0), X(0x6211557e),
+ X(0x5269126e), X(0x61f1003f), X(0x528f8238), X(0x61d09be5),
+ X(0x52b5e546), X(0x61b02876), X(0x52dc3b92), X(0x618fa5f7),
+ X(0x53028518), X(0x616f146c), X(0x5328c1d0), X(0x614e73da),
+ X(0x534ef1b5), X(0x612dc447), X(0x537514c2), X(0x610d05b7),
+ X(0x539b2af0), X(0x60ec3830), X(0x53c13439), X(0x60cb5bb7),
+ X(0x53e73097), X(0x60aa7050), X(0x540d2005), X(0x60897601),
+ X(0x5433027d), X(0x60686ccf), X(0x5458d7f9), X(0x604754bf),
+ X(0x547ea073), X(0x60262dd6), X(0x54a45be6), X(0x6004f819),
+ X(0x54ca0a4b), X(0x5fe3b38d), X(0x54efab9c), X(0x5fc26038),
+ X(0x55153fd4), X(0x5fa0fe1f), X(0x553ac6ee), X(0x5f7f8d46),
+ X(0x556040e2), X(0x5f5e0db3), X(0x5585adad), X(0x5f3c7f6b),
+ X(0x55ab0d46), X(0x5f1ae274), X(0x55d05faa), X(0x5ef936d1),
+ X(0x55f5a4d2), X(0x5ed77c8a), X(0x561adcb9), X(0x5eb5b3a2),
+ X(0x56400758), X(0x5e93dc1f), X(0x566524aa), X(0x5e71f606),
+ X(0x568a34a9), X(0x5e50015d), X(0x56af3750), X(0x5e2dfe29),
+ X(0x56d42c99), X(0x5e0bec6e), X(0x56f9147e), X(0x5de9cc33),
+ X(0x571deefa), X(0x5dc79d7c), X(0x5742bc06), X(0x5da5604f),
+ X(0x57677b9d), X(0x5d8314b1), X(0x578c2dba), X(0x5d60baa7),
+ X(0x57b0d256), X(0x5d3e5237), X(0x57d5696d), X(0x5d1bdb65),
+ X(0x57f9f2f8), X(0x5cf95638), X(0x581e6ef1), X(0x5cd6c2b5),
+ X(0x5842dd54), X(0x5cb420e0), X(0x58673e1b), X(0x5c9170bf),
+ X(0x588b9140), X(0x5c6eb258), X(0x58afd6bd), X(0x5c4be5b0),
+ X(0x58d40e8c), X(0x5c290acc), X(0x58f838a9), X(0x5c0621b2),
+ X(0x591c550e), X(0x5be32a67), X(0x594063b5), X(0x5bc024f0),
+ X(0x59646498), X(0x5b9d1154), X(0x598857b2), X(0x5b79ef96),
+ X(0x59ac3cfd), X(0x5b56bfbd), X(0x59d01475), X(0x5b3381ce),
+ X(0x59f3de12), X(0x5b1035cf), X(0x5a1799d1), X(0x5aecdbc5),
+ X(0x5a3b47ab), X(0x5ac973b5), X(0x5a5ee79a), X(0x5aa5fda5),
+ X(0x5a82799a), X(0x5a82799a)
+ };
+
+ /* {sin((2*i+1)*PI/4096), cos((2*i+1)*PI/4096)}, with i = 0 to 511 */
+static LOOKUP_T sincos_lookup1[1024] = {
+ X(0x001921fb), X(0x7ffffd88), X(0x004b65ee), X(0x7fffe9cb),
+ X(0x007da9d4), X(0x7fffc251), X(0x00afeda8), X(0x7fff8719),
+ X(0x00e23160), X(0x7fff3824), X(0x011474f6), X(0x7ffed572),
+ X(0x0146b860), X(0x7ffe5f03), X(0x0178fb99), X(0x7ffdd4d7),
+ X(0x01ab3e97), X(0x7ffd36ee), X(0x01dd8154), X(0x7ffc8549),
+ X(0x020fc3c6), X(0x7ffbbfe6), X(0x024205e8), X(0x7ffae6c7),
+ X(0x027447b0), X(0x7ff9f9ec), X(0x02a68917), X(0x7ff8f954),
+ X(0x02d8ca16), X(0x7ff7e500), X(0x030b0aa4), X(0x7ff6bcf0),
+ X(0x033d4abb), X(0x7ff58125), X(0x036f8a51), X(0x7ff4319d),
+ X(0x03a1c960), X(0x7ff2ce5b), X(0x03d407df), X(0x7ff1575d),
+ X(0x040645c7), X(0x7fefcca4), X(0x04388310), X(0x7fee2e30),
+ X(0x046abfb3), X(0x7fec7c02), X(0x049cfba7), X(0x7feab61a),
+ X(0x04cf36e5), X(0x7fe8dc78), X(0x05017165), X(0x7fe6ef1c),
+ X(0x0533ab20), X(0x7fe4ee06), X(0x0565e40d), X(0x7fe2d938),
+ X(0x05981c26), X(0x7fe0b0b1), X(0x05ca5361), X(0x7fde7471),
+ X(0x05fc89b8), X(0x7fdc247a), X(0x062ebf22), X(0x7fd9c0ca),
+ X(0x0660f398), X(0x7fd74964), X(0x06932713), X(0x7fd4be46),
+ X(0x06c5598a), X(0x7fd21f72), X(0x06f78af6), X(0x7fcf6ce8),
+ X(0x0729bb4e), X(0x7fcca6a7), X(0x075bea8c), X(0x7fc9ccb2),
+ X(0x078e18a7), X(0x7fc6df08), X(0x07c04598), X(0x7fc3dda9),
+ X(0x07f27157), X(0x7fc0c896), X(0x08249bdd), X(0x7fbd9fd0),
+ X(0x0856c520), X(0x7fba6357), X(0x0888ed1b), X(0x7fb7132b),
+ X(0x08bb13c5), X(0x7fb3af4e), X(0x08ed3916), X(0x7fb037bf),
+ X(0x091f5d06), X(0x7facac7f), X(0x09517f8f), X(0x7fa90d8e),
+ X(0x0983a0a7), X(0x7fa55aee), X(0x09b5c048), X(0x7fa1949e),
+ X(0x09e7de6a), X(0x7f9dbaa0), X(0x0a19fb04), X(0x7f99ccf4),
+ X(0x0a4c1610), X(0x7f95cb9a), X(0x0a7e2f85), X(0x7f91b694),
+ X(0x0ab0475c), X(0x7f8d8de1), X(0x0ae25d8d), X(0x7f895182),
+ X(0x0b147211), X(0x7f850179), X(0x0b4684df), X(0x7f809dc5),
+ X(0x0b7895f0), X(0x7f7c2668), X(0x0baaa53b), X(0x7f779b62),
+ X(0x0bdcb2bb), X(0x7f72fcb4), X(0x0c0ebe66), X(0x7f6e4a5e),
+ X(0x0c40c835), X(0x7f698461), X(0x0c72d020), X(0x7f64aabf),
+ X(0x0ca4d620), X(0x7f5fbd77), X(0x0cd6da2d), X(0x7f5abc8a),
+ X(0x0d08dc3f), X(0x7f55a7fa), X(0x0d3adc4e), X(0x7f507fc7),
+ X(0x0d6cda53), X(0x7f4b43f2), X(0x0d9ed646), X(0x7f45f47b),
+ X(0x0dd0d01f), X(0x7f409164), X(0x0e02c7d7), X(0x7f3b1aad),
+ X(0x0e34bd66), X(0x7f359057), X(0x0e66b0c3), X(0x7f2ff263),
+ X(0x0e98a1e9), X(0x7f2a40d2), X(0x0eca90ce), X(0x7f247ba5),
+ X(0x0efc7d6b), X(0x7f1ea2dc), X(0x0f2e67b8), X(0x7f18b679),
+ X(0x0f604faf), X(0x7f12b67c), X(0x0f923546), X(0x7f0ca2e7),
+ X(0x0fc41876), X(0x7f067bba), X(0x0ff5f938), X(0x7f0040f6),
+ X(0x1027d784), X(0x7ef9f29d), X(0x1059b352), X(0x7ef390ae),
+ X(0x108b8c9b), X(0x7eed1b2c), X(0x10bd6356), X(0x7ee69217),
+ X(0x10ef377d), X(0x7edff570), X(0x11210907), X(0x7ed94538),
+ X(0x1152d7ed), X(0x7ed28171), X(0x1184a427), X(0x7ecbaa1a),
+ X(0x11b66dad), X(0x7ec4bf36), X(0x11e83478), X(0x7ebdc0c6),
+ X(0x1219f880), X(0x7eb6aeca), X(0x124bb9be), X(0x7eaf8943),
+ X(0x127d7829), X(0x7ea85033), X(0x12af33ba), X(0x7ea1039b),
+ X(0x12e0ec6a), X(0x7e99a37c), X(0x1312a230), X(0x7e922fd6),
+ X(0x13445505), X(0x7e8aa8ac), X(0x137604e2), X(0x7e830dff),
+ X(0x13a7b1bf), X(0x7e7b5fce), X(0x13d95b93), X(0x7e739e1d),
+ X(0x140b0258), X(0x7e6bc8eb), X(0x143ca605), X(0x7e63e03b),
+ X(0x146e4694), X(0x7e5be40c), X(0x149fe3fc), X(0x7e53d462),
+ X(0x14d17e36), X(0x7e4bb13c), X(0x1503153a), X(0x7e437a9c),
+ X(0x1534a901), X(0x7e3b3083), X(0x15663982), X(0x7e32d2f4),
+ X(0x1597c6b7), X(0x7e2a61ed), X(0x15c95097), X(0x7e21dd73),
+ X(0x15fad71b), X(0x7e194584), X(0x162c5a3b), X(0x7e109a24),
+ X(0x165dd9f0), X(0x7e07db52), X(0x168f5632), X(0x7dff0911),
+ X(0x16c0cef9), X(0x7df62362), X(0x16f2443e), X(0x7ded2a47),
+ X(0x1723b5f9), X(0x7de41dc0), X(0x17552422), X(0x7ddafdce),
+ X(0x17868eb3), X(0x7dd1ca75), X(0x17b7f5a3), X(0x7dc883b4),
+ X(0x17e958ea), X(0x7dbf298d), X(0x181ab881), X(0x7db5bc02),
+ X(0x184c1461), X(0x7dac3b15), X(0x187d6c82), X(0x7da2a6c6),
+ X(0x18aec0db), X(0x7d98ff17), X(0x18e01167), X(0x7d8f4409),
+ X(0x19115e1c), X(0x7d85759f), X(0x1942a6f3), X(0x7d7b93da),
+ X(0x1973ebe6), X(0x7d719eba), X(0x19a52ceb), X(0x7d679642),
+ X(0x19d669fc), X(0x7d5d7a74), X(0x1a07a311), X(0x7d534b50),
+ X(0x1a38d823), X(0x7d4908d9), X(0x1a6a0929), X(0x7d3eb30f),
+ X(0x1a9b361d), X(0x7d3449f5), X(0x1acc5ef6), X(0x7d29cd8c),
+ X(0x1afd83ad), X(0x7d1f3dd6), X(0x1b2ea43a), X(0x7d149ad5),
+ X(0x1b5fc097), X(0x7d09e489), X(0x1b90d8bb), X(0x7cff1af5),
+ X(0x1bc1ec9e), X(0x7cf43e1a), X(0x1bf2fc3a), X(0x7ce94dfb),
+ X(0x1c240786), X(0x7cde4a98), X(0x1c550e7c), X(0x7cd333f3),
+ X(0x1c861113), X(0x7cc80a0f), X(0x1cb70f43), X(0x7cbcccec),
+ X(0x1ce80906), X(0x7cb17c8d), X(0x1d18fe54), X(0x7ca618f3),
+ X(0x1d49ef26), X(0x7c9aa221), X(0x1d7adb73), X(0x7c8f1817),
+ X(0x1dabc334), X(0x7c837ad8), X(0x1ddca662), X(0x7c77ca65),
+ X(0x1e0d84f5), X(0x7c6c06c0), X(0x1e3e5ee5), X(0x7c602fec),
+ X(0x1e6f342c), X(0x7c5445e9), X(0x1ea004c1), X(0x7c4848ba),
+ X(0x1ed0d09d), X(0x7c3c3860), X(0x1f0197b8), X(0x7c3014de),
+ X(0x1f325a0b), X(0x7c23de35), X(0x1f63178f), X(0x7c179467),
+ X(0x1f93d03c), X(0x7c0b3777), X(0x1fc4840a), X(0x7bfec765),
+ X(0x1ff532f2), X(0x7bf24434), X(0x2025dcec), X(0x7be5ade6),
+ X(0x205681f1), X(0x7bd9047c), X(0x208721f9), X(0x7bcc47fa),
+ X(0x20b7bcfe), X(0x7bbf7860), X(0x20e852f6), X(0x7bb295b0),
+ X(0x2118e3dc), X(0x7ba59fee), X(0x21496fa7), X(0x7b989719),
+ X(0x2179f64f), X(0x7b8b7b36), X(0x21aa77cf), X(0x7b7e4c45),
+ X(0x21daf41d), X(0x7b710a49), X(0x220b6b32), X(0x7b63b543),
+ X(0x223bdd08), X(0x7b564d36), X(0x226c4996), X(0x7b48d225),
+ X(0x229cb0d5), X(0x7b3b4410), X(0x22cd12bd), X(0x7b2da2fa),
+ X(0x22fd6f48), X(0x7b1feee5), X(0x232dc66d), X(0x7b1227d3),
+ X(0x235e1826), X(0x7b044dc7), X(0x238e646a), X(0x7af660c2),
+ X(0x23beab33), X(0x7ae860c7), X(0x23eeec78), X(0x7ada4dd8),
+ X(0x241f2833), X(0x7acc27f7), X(0x244f5e5c), X(0x7abdef25),
+ X(0x247f8eec), X(0x7aafa367), X(0x24afb9da), X(0x7aa144bc),
+ X(0x24dfdf20), X(0x7a92d329), X(0x250ffeb7), X(0x7a844eae),
+ X(0x25401896), X(0x7a75b74f), X(0x25702cb7), X(0x7a670d0d),
+ X(0x25a03b11), X(0x7a584feb), X(0x25d0439f), X(0x7a497feb),
+ X(0x26004657), X(0x7a3a9d0f), X(0x26304333), X(0x7a2ba75a),
+ X(0x26603a2c), X(0x7a1c9ece), X(0x26902b39), X(0x7a0d836d),
+ X(0x26c01655), X(0x79fe5539), X(0x26effb76), X(0x79ef1436),
+ X(0x271fda96), X(0x79dfc064), X(0x274fb3ae), X(0x79d059c8),
+ X(0x277f86b5), X(0x79c0e062), X(0x27af53a6), X(0x79b15435),
+ X(0x27df1a77), X(0x79a1b545), X(0x280edb23), X(0x79920392),
+ X(0x283e95a1), X(0x79823f20), X(0x286e49ea), X(0x797267f2),
+ X(0x289df7f8), X(0x79627e08), X(0x28cd9fc1), X(0x79528167),
+ X(0x28fd4140), X(0x79427210), X(0x292cdc6d), X(0x79325006),
+ X(0x295c7140), X(0x79221b4b), X(0x298bffb2), X(0x7911d3e2),
+ X(0x29bb87bc), X(0x790179cd), X(0x29eb0957), X(0x78f10d0f),
+ X(0x2a1a847b), X(0x78e08dab), X(0x2a49f920), X(0x78cffba3),
+ X(0x2a796740), X(0x78bf56f9), X(0x2aa8ced3), X(0x78ae9fb0),
+ X(0x2ad82fd2), X(0x789dd5cb), X(0x2b078a36), X(0x788cf94c),
+ X(0x2b36ddf7), X(0x787c0a36), X(0x2b662b0e), X(0x786b088c),
+ X(0x2b957173), X(0x7859f44f), X(0x2bc4b120), X(0x7848cd83),
+ X(0x2bf3ea0d), X(0x7837942b), X(0x2c231c33), X(0x78264849),
+ X(0x2c52478a), X(0x7814e9df), X(0x2c816c0c), X(0x780378f1),
+ X(0x2cb089b1), X(0x77f1f581), X(0x2cdfa071), X(0x77e05f91),
+ X(0x2d0eb046), X(0x77ceb725), X(0x2d3db928), X(0x77bcfc3f),
+ X(0x2d6cbb10), X(0x77ab2ee2), X(0x2d9bb5f6), X(0x77994f11),
+ X(0x2dcaa9d5), X(0x77875cce), X(0x2df996a3), X(0x7775581d),
+ X(0x2e287c5a), X(0x776340ff), X(0x2e575af3), X(0x77511778),
+ X(0x2e863267), X(0x773edb8b), X(0x2eb502ae), X(0x772c8d3a),
+ X(0x2ee3cbc1), X(0x771a2c88), X(0x2f128d99), X(0x7707b979),
+ X(0x2f41482e), X(0x76f5340e), X(0x2f6ffb7a), X(0x76e29c4b),
+ X(0x2f9ea775), X(0x76cff232), X(0x2fcd4c19), X(0x76bd35c7),
+ X(0x2ffbe95d), X(0x76aa670d), X(0x302a7f3a), X(0x76978605),
+ X(0x30590dab), X(0x768492b4), X(0x308794a6), X(0x76718d1c),
+ X(0x30b61426), X(0x765e7540), X(0x30e48c22), X(0x764b4b23),
+ X(0x3112fc95), X(0x76380ec8), X(0x31416576), X(0x7624c031),
+ X(0x316fc6be), X(0x76115f63), X(0x319e2067), X(0x75fdec60),
+ X(0x31cc7269), X(0x75ea672a), X(0x31fabcbd), X(0x75d6cfc5),
+ X(0x3228ff5c), X(0x75c32634), X(0x32573a3f), X(0x75af6a7b),
+ X(0x32856d5e), X(0x759b9c9b), X(0x32b398b3), X(0x7587bc98),
+ X(0x32e1bc36), X(0x7573ca75), X(0x330fd7e1), X(0x755fc635),
+ X(0x333debab), X(0x754bafdc), X(0x336bf78f), X(0x7537876c),
+ X(0x3399fb85), X(0x75234ce8), X(0x33c7f785), X(0x750f0054),
+ X(0x33f5eb89), X(0x74faa1b3), X(0x3423d78a), X(0x74e63108),
+ X(0x3451bb81), X(0x74d1ae55), X(0x347f9766), X(0x74bd199f),
+ X(0x34ad6b32), X(0x74a872e8), X(0x34db36df), X(0x7493ba34),
+ X(0x3508fa66), X(0x747eef85), X(0x3536b5be), X(0x746a12df),
+ X(0x356468e2), X(0x74552446), X(0x359213c9), X(0x744023bc),
+ X(0x35bfb66e), X(0x742b1144), X(0x35ed50c9), X(0x7415ece2),
+ X(0x361ae2d3), X(0x7400b69a), X(0x36486c86), X(0x73eb6e6e),
+ X(0x3675edd9), X(0x73d61461), X(0x36a366c6), X(0x73c0a878),
+ X(0x36d0d746), X(0x73ab2ab4), X(0x36fe3f52), X(0x73959b1b),
+ X(0x372b9ee3), X(0x737ff9ae), X(0x3758f5f2), X(0x736a4671),
+ X(0x37864477), X(0x73548168), X(0x37b38a6d), X(0x733eaa96),
+ X(0x37e0c7cc), X(0x7328c1ff), X(0x380dfc8d), X(0x7312c7a5),
+ X(0x383b28a9), X(0x72fcbb8c), X(0x38684c19), X(0x72e69db7),
+ X(0x389566d6), X(0x72d06e2b), X(0x38c278d9), X(0x72ba2cea),
+ X(0x38ef821c), X(0x72a3d9f7), X(0x391c8297), X(0x728d7557),
+ X(0x39497a43), X(0x7276ff0d), X(0x39766919), X(0x7260771b),
+ X(0x39a34f13), X(0x7249dd86), X(0x39d02c2a), X(0x72333251),
+ X(0x39fd0056), X(0x721c7580), X(0x3a29cb91), X(0x7205a716),
+ X(0x3a568dd4), X(0x71eec716), X(0x3a834717), X(0x71d7d585),
+ X(0x3aaff755), X(0x71c0d265), X(0x3adc9e86), X(0x71a9bdba),
+ X(0x3b093ca3), X(0x71929789), X(0x3b35d1a5), X(0x717b5fd3),
+ X(0x3b625d86), X(0x7164169d), X(0x3b8ee03e), X(0x714cbbeb),
+ X(0x3bbb59c7), X(0x71354fc0), X(0x3be7ca1a), X(0x711dd220),
+ X(0x3c143130), X(0x7106430e), X(0x3c408f03), X(0x70eea28e),
+ X(0x3c6ce38a), X(0x70d6f0a4), X(0x3c992ec0), X(0x70bf2d53),
+ X(0x3cc5709e), X(0x70a7589f), X(0x3cf1a91c), X(0x708f728b),
+ X(0x3d1dd835), X(0x70777b1c), X(0x3d49fde1), X(0x705f7255),
+ X(0x3d761a19), X(0x70475839), X(0x3da22cd7), X(0x702f2ccd),
+ X(0x3dce3614), X(0x7016f014), X(0x3dfa35c8), X(0x6ffea212),
+ X(0x3e262bee), X(0x6fe642ca), X(0x3e52187f), X(0x6fcdd241),
+ X(0x3e7dfb73), X(0x6fb5507a), X(0x3ea9d4c3), X(0x6f9cbd79),
+ X(0x3ed5a46b), X(0x6f841942), X(0x3f016a61), X(0x6f6b63d8),
+ X(0x3f2d26a0), X(0x6f529d40), X(0x3f58d921), X(0x6f39c57d),
+ X(0x3f8481dd), X(0x6f20dc92), X(0x3fb020ce), X(0x6f07e285),
+ X(0x3fdbb5ec), X(0x6eeed758), X(0x40074132), X(0x6ed5bb10),
+ X(0x4032c297), X(0x6ebc8db0), X(0x405e3a16), X(0x6ea34f3d),
+ X(0x4089a7a8), X(0x6e89ffb9), X(0x40b50b46), X(0x6e709f2a),
+ X(0x40e064ea), X(0x6e572d93), X(0x410bb48c), X(0x6e3daaf8),
+ X(0x4136fa27), X(0x6e24175c), X(0x416235b2), X(0x6e0a72c5),
+ X(0x418d6729), X(0x6df0bd35), X(0x41b88e84), X(0x6dd6f6b1),
+ X(0x41e3abbc), X(0x6dbd1f3c), X(0x420ebecb), X(0x6da336dc),
+ X(0x4239c7aa), X(0x6d893d93), X(0x4264c653), X(0x6d6f3365),
+ X(0x428fbabe), X(0x6d551858), X(0x42baa4e6), X(0x6d3aec6e),
+ X(0x42e584c3), X(0x6d20afac), X(0x43105a50), X(0x6d066215),
+ X(0x433b2585), X(0x6cec03af), X(0x4365e65b), X(0x6cd1947c),
+ X(0x43909ccd), X(0x6cb71482), X(0x43bb48d4), X(0x6c9c83c3),
+ X(0x43e5ea68), X(0x6c81e245), X(0x44108184), X(0x6c67300b),
+ X(0x443b0e21), X(0x6c4c6d1a), X(0x44659039), X(0x6c319975),
+ X(0x449007c4), X(0x6c16b521), X(0x44ba74bd), X(0x6bfbc021),
+ X(0x44e4d71c), X(0x6be0ba7b), X(0x450f2edb), X(0x6bc5a431),
+ X(0x45397bf4), X(0x6baa7d49), X(0x4563be60), X(0x6b8f45c7),
+ X(0x458df619), X(0x6b73fdae), X(0x45b82318), X(0x6b58a503),
+ X(0x45e24556), X(0x6b3d3bcb), X(0x460c5cce), X(0x6b21c208),
+ X(0x46366978), X(0x6b0637c1), X(0x46606b4e), X(0x6aea9cf8),
+ X(0x468a624a), X(0x6acef1b2), X(0x46b44e65), X(0x6ab335f4),
+ X(0x46de2f99), X(0x6a9769c1), X(0x470805df), X(0x6a7b8d1e),
+ X(0x4731d131), X(0x6a5fa010), X(0x475b9188), X(0x6a43a29a),
+ X(0x478546de), X(0x6a2794c1), X(0x47aef12c), X(0x6a0b7689),
+ X(0x47d8906d), X(0x69ef47f6), X(0x48022499), X(0x69d3090e),
+ X(0x482badab), X(0x69b6b9d3), X(0x48552b9b), X(0x699a5a4c),
+ X(0x487e9e64), X(0x697dea7b), X(0x48a805ff), X(0x69616a65),
+ X(0x48d16265), X(0x6944da10), X(0x48fab391), X(0x6928397e),
+ X(0x4923f97b), X(0x690b88b5), X(0x494d341e), X(0x68eec7b9),
+ X(0x49766373), X(0x68d1f68f), X(0x499f8774), X(0x68b5153a),
+ X(0x49c8a01b), X(0x689823bf), X(0x49f1ad61), X(0x687b2224),
+ X(0x4a1aaf3f), X(0x685e106c), X(0x4a43a5b0), X(0x6840ee9b),
+ X(0x4a6c90ad), X(0x6823bcb7), X(0x4a957030), X(0x68067ac3),
+ X(0x4abe4433), X(0x67e928c5), X(0x4ae70caf), X(0x67cbc6c0),
+ X(0x4b0fc99d), X(0x67ae54ba), X(0x4b387af9), X(0x6790d2b6),
+ X(0x4b6120bb), X(0x677340ba), X(0x4b89badd), X(0x67559eca),
+ X(0x4bb24958), X(0x6737ecea), X(0x4bdacc28), X(0x671a2b20),
+ X(0x4c034345), X(0x66fc596f), X(0x4c2baea9), X(0x66de77dc),
+ X(0x4c540e4e), X(0x66c0866d), X(0x4c7c622d), X(0x66a28524),
+ X(0x4ca4aa41), X(0x66847408), X(0x4ccce684), X(0x6666531d),
+ X(0x4cf516ee), X(0x66482267), X(0x4d1d3b7a), X(0x6629e1ec),
+ X(0x4d455422), X(0x660b91af), X(0x4d6d60df), X(0x65ed31b5),
+ X(0x4d9561ac), X(0x65cec204), X(0x4dbd5682), X(0x65b0429f),
+ X(0x4de53f5a), X(0x6591b38c), X(0x4e0d1c30), X(0x657314cf),
+ X(0x4e34ecfc), X(0x6554666d), X(0x4e5cb1b9), X(0x6535a86b),
+ X(0x4e846a60), X(0x6516dacd), X(0x4eac16eb), X(0x64f7fd98),
+ X(0x4ed3b755), X(0x64d910d1), X(0x4efb4b96), X(0x64ba147d),
+ X(0x4f22d3aa), X(0x649b08a0), X(0x4f4a4f89), X(0x647bed3f),
+ X(0x4f71bf2e), X(0x645cc260), X(0x4f992293), X(0x643d8806),
+ X(0x4fc079b1), X(0x641e3e38), X(0x4fe7c483), X(0x63fee4f8),
+ X(0x500f0302), X(0x63df7c4d), X(0x50363529), X(0x63c0043b),
+ X(0x505d5af1), X(0x63a07cc7), X(0x50847454), X(0x6380e5f6),
+ X(0x50ab814d), X(0x63613fcd), X(0x50d281d5), X(0x63418a50),
+ X(0x50f975e6), X(0x6321c585), X(0x51205d7b), X(0x6301f171),
+ X(0x5147388c), X(0x62e20e17), X(0x516e0715), X(0x62c21b7e),
+ X(0x5194c910), X(0x62a219aa), X(0x51bb7e75), X(0x628208a1),
+ X(0x51e22740), X(0x6261e866), X(0x5208c36a), X(0x6241b8ff),
+ X(0x522f52ee), X(0x62217a72), X(0x5255d5c5), X(0x62012cc2),
+ X(0x527c4bea), X(0x61e0cff5), X(0x52a2b556), X(0x61c06410),
+ X(0x52c91204), X(0x619fe918), X(0x52ef61ee), X(0x617f5f12),
+ X(0x5315a50e), X(0x615ec603), X(0x533bdb5d), X(0x613e1df0),
+ X(0x536204d7), X(0x611d66de), X(0x53882175), X(0x60fca0d2),
+ X(0x53ae3131), X(0x60dbcbd1), X(0x53d43406), X(0x60bae7e1),
+ X(0x53fa29ed), X(0x6099f505), X(0x542012e1), X(0x6078f344),
+ X(0x5445eedb), X(0x6057e2a2), X(0x546bbdd7), X(0x6036c325),
+ X(0x54917fce), X(0x601594d1), X(0x54b734ba), X(0x5ff457ad),
+ X(0x54dcdc96), X(0x5fd30bbc), X(0x5502775c), X(0x5fb1b104),
+ X(0x55280505), X(0x5f90478a), X(0x554d858d), X(0x5f6ecf53),
+ X(0x5572f8ed), X(0x5f4d4865), X(0x55985f20), X(0x5f2bb2c5),
+ X(0x55bdb81f), X(0x5f0a0e77), X(0x55e303e6), X(0x5ee85b82),
+ X(0x5608426e), X(0x5ec699e9), X(0x562d73b2), X(0x5ea4c9b3),
+ X(0x565297ab), X(0x5e82eae5), X(0x5677ae54), X(0x5e60fd84),
+ X(0x569cb7a8), X(0x5e3f0194), X(0x56c1b3a1), X(0x5e1cf71c),
+ X(0x56e6a239), X(0x5dfade20), X(0x570b8369), X(0x5dd8b6a7),
+ X(0x5730572e), X(0x5db680b4), X(0x57551d80), X(0x5d943c4e),
+ X(0x5779d65b), X(0x5d71e979), X(0x579e81b8), X(0x5d4f883b),
+ X(0x57c31f92), X(0x5d2d189a), X(0x57e7afe4), X(0x5d0a9a9a),
+ X(0x580c32a7), X(0x5ce80e41), X(0x5830a7d6), X(0x5cc57394),
+ X(0x58550f6c), X(0x5ca2ca99), X(0x58796962), X(0x5c801354),
+ X(0x589db5b3), X(0x5c5d4dcc), X(0x58c1f45b), X(0x5c3a7a05),
+ X(0x58e62552), X(0x5c179806), X(0x590a4893), X(0x5bf4a7d2),
+ X(0x592e5e19), X(0x5bd1a971), X(0x595265df), X(0x5bae9ce7),
+ X(0x59765fde), X(0x5b8b8239), X(0x599a4c12), X(0x5b68596d),
+ X(0x59be2a74), X(0x5b452288), X(0x59e1faff), X(0x5b21dd90),
+ X(0x5a05bdae), X(0x5afe8a8b), X(0x5a29727b), X(0x5adb297d),
+ X(0x5a4d1960), X(0x5ab7ba6c), X(0x5a70b258), X(0x5a943d5e),
+};
+
+#endif
+
diff --git a/library/ADK2/v_misc.c b/library/ADK2/v_misc.c
new file mode 100644
index 0000000..020c01b
--- /dev/null
+++ b/library/ADK2/v_misc.c
@@ -0,0 +1,209 @@
+#define ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis SOFTWARE CODEC SOURCE CODE. *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis SOURCE CODE IS (C) COPYRIGHT 1994-2002 *
+ * by the XIPHOPHORUS Company http://www.xiph.org/ *
+ * *
+ ********************************************************************/
+
+#define HEAD_ALIGN 64
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#define MISC_C
+#include "v_misc.h"
+#include <sys/time.h>
+
+static void **pointers=NULL;
+static long *insertlist=NULL; /* We can't embed this in the pointer list;
+ a pointer can have any value... */
+
+static char **files=NULL;
+static long *file_bytes=NULL;
+static int filecount=0;
+
+static int ptop=0;
+static int palloced=0;
+static int pinsert=0;
+
+typedef struct {
+ char *file;
+ long line;
+ long ptr;
+ long bytes;
+} head;
+
+long global_bytes=0;
+long start_time=-1;
+
+static void *_insert(void *ptr,long bytes,char *file,long line){
+ ((head *)ptr)->file=file;
+ ((head *)ptr)->line=line;
+ ((head *)ptr)->ptr=pinsert;
+ ((head *)ptr)->bytes=bytes-HEAD_ALIGN;
+
+ if(pinsert>=palloced){
+ palloced+=64;
+ if(pointers){
+ pointers=(void **)realloc(pointers,sizeof(void **)*palloced);
+ insertlist=(long *)realloc(insertlist,sizeof(long *)*palloced);
+ }else{
+ pointers=(void **)malloc(sizeof(void **)*palloced);
+ insertlist=(long *)malloc(sizeof(long *)*palloced);
+ }
+ }
+
+ pointers[pinsert]=ptr;
+
+ if(pinsert==ptop)
+ pinsert=++ptop;
+ else
+ pinsert=insertlist[pinsert];
+
+#ifdef _VDBG_GRAPHFILE
+ {
+ FILE *out;
+ struct timeval tv;
+ static struct timezone tz;
+ int i;
+ char buffer[80];
+ gettimeofday(&tv,&tz);
+
+ for(i=0;i<filecount;i++)
+ if(!strcmp(file,files[i]))break;
+
+ if(i==filecount){
+ filecount++;
+ if(!files){
+ files=malloc(filecount*sizeof(*files));
+ file_bytes=malloc(filecount*sizeof(*file_bytes));
+ }else{
+ files=realloc(files,filecount*sizeof(*files));
+ file_bytes=realloc(file_bytes,filecount*sizeof(*file_bytes));
+ }
+ files[i]=strdup(file);
+ file_bytes[i]=0;
+ }
+
+ file_bytes[i]+=bytes-HEAD_ALIGN;
+
+ if(start_time==-1)start_time=(tv.tv_sec*1000)+(tv.tv_usec/1000);
+
+ snprintf(buffer,80,"%s",file);
+ if(strchr(buffer,'.'))strchr(buffer,'.')[0]=0;
+ strcat(buffer,_VDBG_GRAPHFILE);
+ out=fopen(buffer,"a");
+ fprintf(out,"%ld, %ld\n",-start_time+(tv.tv_sec*1000)+(tv.tv_usec/1000),
+ file_bytes[i]-(bytes-HEAD_ALIGN));
+ fprintf(out,"%ld, %ld # FILE %s LINE %ld\n",
+ -start_time+(tv.tv_sec*1000)+(tv.tv_usec/1000),
+ file_bytes[i],file,line);
+ fclose(out);
+
+ out=fopen("total"_VDBG_GRAPHFILE,"a");
+ fprintf(out,"%ld, %ld\n",-start_time+(tv.tv_sec*1000)+(tv.tv_usec/1000),
+ global_bytes);
+ fprintf(out,"%ld, %ld\n",-start_time+(tv.tv_sec*1000)+(tv.tv_usec/1000),
+ global_bytes+(bytes-HEAD_ALIGN));
+ fclose(out);
+ }
+#endif
+
+ global_bytes+=(bytes-HEAD_ALIGN);
+
+ return(ptr+HEAD_ALIGN);
+}
+
+static void _ripremove(void *ptr){
+ int insert;
+
+#ifdef _VDBG_GRAPHFILE
+ {
+ FILE *out=fopen("total"_VDBG_GRAPHFILE,"a");
+ struct timeval tv;
+ static struct timezone tz;
+ char buffer[80];
+ char *file =((head *)ptr)->file;
+ long bytes =((head *)ptr)->bytes;
+ int i;
+
+ gettimeofday(&tv,&tz);
+ fprintf(out,"%ld, %ld\n",-start_time+(tv.tv_sec*1000)+(tv.tv_usec/1000),
+ global_bytes);
+ fprintf(out,"%ld, %ld\n",-start_time+(tv.tv_sec*1000)+(tv.tv_usec/1000),
+ global_bytes-((head *)ptr)->bytes);
+ fclose(out);
+
+ for(i=0;i<filecount;i++)
+ if(!strcmp(file,files[i]))break;
+
+ snprintf(buffer,80,"%s",file);
+ if(strchr(buffer,'.'))strchr(buffer,'.')[0]=0;
+ strcat(buffer,_VDBG_GRAPHFILE);
+ out=fopen(buffer,"a");
+ fprintf(out,"%ld, %ld\n",-start_time+(tv.tv_sec*1000)+(tv.tv_usec/1000),
+ file_bytes[i]);
+ fprintf(out,"%ld, %ld\n",-start_time+(tv.tv_sec*1000)+(tv.tv_usec/1000),
+ file_bytes[i]-bytes);
+ fclose(out);
+
+ file_bytes[i]-=bytes;
+
+ }
+#endif
+
+ global_bytes-=((head *)ptr)->bytes;
+
+ insert=((head *)ptr)->ptr;
+ insertlist[insert]=pinsert;
+ pinsert=insert;
+
+ if(pointers[insert]==NULL){
+ fprintf(stderr,"DEBUGGING MALLOC ERROR: freeing previously freed memory\n");
+ fprintf(stderr,"\t%s %ld\n",((head *)ptr)->file,((head *)ptr)->line);
+ }
+
+ if(global_bytes<0){
+ fprintf(stderr,"DEBUGGING MALLOC ERROR: freeing unmalloced memory\n");
+ }
+
+ pointers[insert]=NULL;
+}
+
+void _VDBG_dump(void){
+ int i;
+ for(i=0;i<ptop;i++){
+ head *ptr=pointers[i];
+ if(ptr)
+ fprintf(stderr,"unfreed bytes from %s:%ld\n",
+ ptr->file,ptr->line);
+ }
+
+}
+
+extern void *_VDBG_malloc(void *ptr,long bytes,char *file,long line){
+ bytes+=HEAD_ALIGN;
+ if(ptr){
+ ptr-=HEAD_ALIGN;
+ _ripremove(ptr);
+ ptr=realloc(ptr,bytes);
+ }else{
+ ptr=malloc(bytes);
+ memset(ptr,0,bytes);
+ }
+ return _insert(ptr,bytes,file,line);
+}
+
+extern void _VDBG_free(void *ptr,char *file,long line){
+ if(ptr){
+ ptr-=HEAD_ALIGN;
+ _ripremove(ptr);
+ free(ptr);
+ }
+}
+
diff --git a/library/ADK2/v_misc.h b/library/ADK2/v_misc.h
new file mode 100644
index 0000000..a6f1bc1
--- /dev/null
+++ b/library/ADK2/v_misc.h
@@ -0,0 +1,196 @@
+#ifdef ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: miscellaneous math and prototypes
+
+ ********************************************************************/
+
+#ifndef _V_RANDOM_H_
+#define _V_RANDOM_H_
+#include "v_ivorbiscodec.h"
+#include "v_os_types.h"
+
+
+/*#define _VDBG_GRAPHFILE "_0.m"*/
+
+
+#ifdef _VDBG_GRAPHFILE
+extern void *_VDBG_malloc(void *ptr,long bytes,char *file,long line);
+extern void _VDBG_free(void *ptr,char *file,long line);
+
+#undef _ogg_malloc
+#undef _ogg_calloc
+#undef _ogg_realloc
+#undef _ogg_free
+
+#define _ogg_malloc(x) _VDBG_malloc(NULL,(x),__FILE__,__LINE__)
+#define _ogg_calloc(x,y) _VDBG_malloc(NULL,(x)*(y),__FILE__,__LINE__)
+#define _ogg_realloc(x,y) _VDBG_malloc((x),(y),__FILE__,__LINE__)
+#define _ogg_free(x) _VDBG_free((x),__FILE__,__LINE__)
+#endif
+
+#include "v_asm_arm.h"
+
+#ifndef _V_WIDE_MATH
+#define _V_WIDE_MATH
+
+#ifndef _LOW_ACCURACY_
+/* 64 bit multiply */
+
+#include <sys/types.h>
+
+#if BYTE_ORDER==LITTLE_ENDIAN
+union magic {
+ struct {
+ ogg_int32_t lo;
+ ogg_int32_t hi;
+ } halves;
+ ogg_int64_t whole;
+};
+#endif
+
+#if BYTE_ORDER==BIG_ENDIAN
+union magic {
+ struct {
+ ogg_int32_t hi;
+ ogg_int32_t lo;
+ } halves;
+ ogg_int64_t whole;
+};
+#endif
+
+static inline ogg_int32_t MULT32(ogg_int32_t x, ogg_int32_t y) {
+ union magic magic;
+ magic.whole = (ogg_int64_t)x * y;
+ return magic.halves.hi;
+}
+
+static inline ogg_int32_t MULT31(ogg_int32_t x, ogg_int32_t y) {
+ return MULT32(x,y)<<1;
+}
+
+static inline ogg_int32_t MULT31_SHIFT15(ogg_int32_t x, ogg_int32_t y) {
+ union magic magic;
+ magic.whole = (ogg_int64_t)x * y;
+ return ((ogg_uint32_t)(magic.halves.lo)>>15) | ((magic.halves.hi)<<17);
+}
+
+#else
+/* 32 bit multiply, more portable but less accurate */
+
+/*
+ * Note: Precision is biased towards the first argument therefore ordering
+ * is important. Shift values were chosen for the best sound quality after
+ * many listening tests.
+ */
+
+/*
+ * For MULT32 and MULT31: The second argument is always a lookup table
+ * value already preshifted from 31 to 8 bits. We therefore take the
+ * opportunity to save on text space and use unsigned char for those
+ * tables in this case.
+ */
+
+static inline ogg_int32_t MULT32(ogg_int32_t x, ogg_int32_t y) {
+ return (x >> 9) * y; /* y preshifted >>23 */
+}
+
+static inline ogg_int32_t MULT31(ogg_int32_t x, ogg_int32_t y) {
+ return (x >> 8) * y; /* y preshifted >>23 */
+}
+
+static inline ogg_int32_t MULT31_SHIFT15(ogg_int32_t x, ogg_int32_t y) {
+ return (x >> 6) * y; /* y preshifted >>9 */
+}
+
+#endif
+
+/*
+ * This should be used as a memory barrier, forcing all cached values in
+ * registers to wr writen back to memory. Might or might not be beneficial
+ * depending on the architecture and compiler.
+ */
+#define MB()
+
+/*
+ * The XPROD functions are meant to optimize the cross products found all
+ * over the place in mdct.c by forcing memory operation ordering to avoid
+ * unnecessary register reloads as soon as memory is being written to.
+ * However this is only beneficial on CPUs with a sane number of general
+ * purpose registers which exclude the Intel x86. On Intel, better let the
+ * compiler actually reload registers directly from original memory by using
+ * macros.
+ */
+
+#ifdef __i386__
+
+#define XPROD32(_a, _b, _t, _v, _x, _y) \
+ { *(_x)=MULT32(_a,_t)+MULT32(_b,_v); \
+ *(_y)=MULT32(_b,_t)-MULT32(_a,_v); }
+#define XPROD31(_a, _b, _t, _v, _x, _y) \
+ { *(_x)=MULT31(_a,_t)+MULT31(_b,_v); \
+ *(_y)=MULT31(_b,_t)-MULT31(_a,_v); }
+#define XNPROD31(_a, _b, _t, _v, _x, _y) \
+ { *(_x)=MULT31(_a,_t)-MULT31(_b,_v); \
+ *(_y)=MULT31(_b,_t)+MULT31(_a,_v); }
+
+#else
+
+static inline void XPROD32(ogg_int32_t a, ogg_int32_t b,
+ ogg_int32_t t, ogg_int32_t v,
+ ogg_int32_t *x, ogg_int32_t *y)
+{
+ *x = MULT32(a, t) + MULT32(b, v);
+ *y = MULT32(b, t) - MULT32(a, v);
+}
+
+static inline void XPROD31(ogg_int32_t a, ogg_int32_t b,
+ ogg_int32_t t, ogg_int32_t v,
+ ogg_int32_t *x, ogg_int32_t *y)
+{
+ *x = MULT31(a, t) + MULT31(b, v);
+ *y = MULT31(b, t) - MULT31(a, v);
+}
+
+static inline void XNPROD31(ogg_int32_t a, ogg_int32_t b,
+ ogg_int32_t t, ogg_int32_t v,
+ ogg_int32_t *x, ogg_int32_t *y)
+{
+ *x = MULT31(a, t) - MULT31(b, v);
+ *y = MULT31(b, t) + MULT31(a, v);
+}
+
+#endif
+
+#endif
+
+#ifndef _V_CLIP_MATH
+#define _V_CLIP_MATH
+
+static inline ogg_int32_t CLIP_TO_15(ogg_int32_t x) {
+ int ret=x;
+ ret-= ((x<=32767)-1)&(x-32767);
+ ret-= ((x>=-32768)-1)&(x+32768);
+ return(ret);
+}
+
+#endif
+
+#endif
+
+
+
+
+#endif
+
diff --git a/library/ADK2/v_ogg.h b/library/ADK2/v_ogg.h
new file mode 100644
index 0000000..1cbaf2c
--- /dev/null
+++ b/library/ADK2/v_ogg.h
@@ -0,0 +1,209 @@
+#ifdef ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: subsumed libogg includes
+
+ ********************************************************************/
+#ifndef _OGG_H
+#define _OGG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "v_os_types.h"
+
+typedef struct ogg_buffer_state{
+ struct ogg_buffer *unused_buffers;
+ struct ogg_reference *unused_references;
+ int outstanding;
+ int shutdown;
+} ogg_buffer_state;
+
+typedef struct ogg_buffer {
+ unsigned char *data;
+ long size;
+ int refcount;
+
+ union {
+ ogg_buffer_state *owner;
+ struct ogg_buffer *next;
+ } ptr;
+} ogg_buffer;
+
+typedef struct ogg_reference {
+ ogg_buffer *buffer;
+ long begin;
+ long length;
+
+ struct ogg_reference *next;
+} ogg_reference;
+
+typedef struct oggpack_buffer {
+ int headbit;
+ unsigned char *headptr;
+ long headend;
+
+ /* memory management */
+ ogg_reference *head;
+ ogg_reference *tail;
+
+ /* render the byte/bit counter API constant time */
+ long count; /* doesn't count the tail */
+} oggpack_buffer;
+
+typedef struct oggbyte_buffer {
+ ogg_reference *baseref;
+
+ ogg_reference *ref;
+ unsigned char *ptr;
+ long pos;
+ long end;
+} oggbyte_buffer;
+
+typedef struct ogg_sync_state {
+ /* decode memory management pool */
+ ogg_buffer_state *bufferpool;
+
+ /* stream buffers */
+ ogg_reference *fifo_head;
+ ogg_reference *fifo_tail;
+ long fifo_fill;
+
+ /* stream sync management */
+ int unsynced;
+ int headerbytes;
+ int bodybytes;
+
+} ogg_sync_state;
+
+typedef struct ogg_stream_state {
+ ogg_reference *header_head;
+ ogg_reference *header_tail;
+ ogg_reference *body_head;
+ ogg_reference *body_tail;
+
+ int e_o_s; /* set when we have buffered the last
+ packet in the logical bitstream */
+ int b_o_s; /* set after we've written the initial page
+ of a logical bitstream */
+ long serialno;
+ long pageno;
+ ogg_int64_t packetno; /* sequence number for decode; the framing
+ knows where there's a hole in the data,
+ but we need coupling so that the codec
+ (which is in a seperate abstraction
+ layer) also knows about the gap */
+ ogg_int64_t granulepos;
+
+ int lacing_fill;
+ ogg_uint32_t body_fill;
+
+ /* decode-side state data */
+ int holeflag;
+ int spanflag;
+ int clearflag;
+ int laceptr;
+ ogg_uint32_t body_fill_next;
+
+} ogg_stream_state;
+
+typedef struct {
+ ogg_reference *packet;
+ long bytes;
+ long b_o_s;
+ long e_o_s;
+ ogg_int64_t granulepos;
+ ogg_int64_t packetno; /* sequence number for decode; the framing
+ knows where there's a hole in the data,
+ but we need coupling so that the codec
+ (which is in a seperate abstraction
+ layer) also knows about the gap */
+} ogg_packet;
+
+typedef struct {
+ ogg_reference *header;
+ int header_len;
+ ogg_reference *body;
+ long body_len;
+} ogg_page;
+
+/* Ogg BITSTREAM PRIMITIVES: bitstream ************************/
+
+extern void oggpack_readinit(oggpack_buffer *b,ogg_reference *r);
+extern long oggpack_look(oggpack_buffer *b,int bits);
+extern void oggpack_adv(oggpack_buffer *b,int bits);
+extern long oggpack_read(oggpack_buffer *b,int bits);
+extern long oggpack_bytes(oggpack_buffer *b);
+extern long oggpack_bits(oggpack_buffer *b);
+extern int oggpack_eop(oggpack_buffer *b);
+
+/* Ogg BITSTREAM PRIMITIVES: decoding **************************/
+
+extern ogg_sync_state *ogg_sync_create(void);
+extern int ogg_sync_destroy(ogg_sync_state *oy);
+extern int ogg_sync_reset(ogg_sync_state *oy);
+
+extern unsigned char *ogg_sync_bufferin(ogg_sync_state *oy, long size);
+extern int ogg_sync_wrote(ogg_sync_state *oy, long bytes);
+extern long ogg_sync_pageseek(ogg_sync_state *oy,ogg_page *og);
+extern int ogg_sync_pageout(ogg_sync_state *oy, ogg_page *og);
+extern int ogg_stream_pagein(ogg_stream_state *os, ogg_page *og);
+extern int ogg_stream_packetout(ogg_stream_state *os,ogg_packet *op);
+extern int ogg_stream_packetpeek(ogg_stream_state *os,ogg_packet *op);
+
+/* Ogg BITSTREAM PRIMITIVES: general ***************************/
+
+extern ogg_stream_state *ogg_stream_create(int serialno);
+extern int ogg_stream_destroy(ogg_stream_state *os);
+extern int ogg_stream_reset(ogg_stream_state *os);
+extern int ogg_stream_reset_serialno(ogg_stream_state *os,int serialno);
+extern int ogg_stream_eos(ogg_stream_state *os);
+
+extern int ogg_page_checksum_set(ogg_page *og);
+
+extern int ogg_page_version(ogg_page *og);
+extern int ogg_page_continued(ogg_page *og);
+extern int ogg_page_bos(ogg_page *og);
+extern int ogg_page_eos(ogg_page *og);
+extern ogg_int64_t ogg_page_granulepos(ogg_page *og);
+extern ogg_uint32_t ogg_page_serialno(ogg_page *og);
+extern ogg_uint32_t ogg_page_pageno(ogg_page *og);
+extern int ogg_page_packets(ogg_page *og);
+extern int ogg_page_getbuffer(ogg_page *og, unsigned char **buffer);
+
+extern int ogg_packet_release(ogg_packet *op);
+extern int ogg_page_release(ogg_page *og);
+
+extern void ogg_page_dup(ogg_page *d, ogg_page *s);
+
+/* Ogg BITSTREAM PRIMITIVES: return codes ***************************/
+
+#define OGG_SUCCESS 0
+
+#define OGG_HOLE -10
+#define OGG_SPAN -11
+#define OGG_EVERSION -12
+#define OGG_ESERIAL -13
+#define OGG_EINVAL -14
+#define OGG_EEOS -15
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OGG_H */
+#endif
+
diff --git a/library/ADK2/v_os.h b/library/ADK2/v_os.h
new file mode 100644
index 0000000..301b3a3
--- /dev/null
+++ b/library/ADK2/v_os.h
@@ -0,0 +1,65 @@
+#ifdef ADK_INTERNAL
+#ifndef _OS_H
+#define _OS_H
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2002 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: #ifdef jail to whip a few platforms into the UNIX ideal.
+
+ ********************************************************************/
+
+#include <math.h>
+#include "v_os_types.h"
+
+#ifndef _V_IFDEFJAIL_H_
+# define _V_IFDEFJAIL_H_
+
+# ifdef __GNUC__
+# define STIN static __inline__
+# elif _WIN32
+# define STIN static __inline
+# endif
+#else
+# define STIN static
+#endif
+
+#ifndef M_PI
+# define M_PI (3.1415926536f)
+#endif
+
+#ifdef _WIN32
+# include <malloc.h>
+# define rint(x) (floor((x)+0.5f))
+# define NO_FLOAT_MATH_LIB
+# define FAST_HYPOT(a, b) sqrt((a)*(a) + (b)*(b))
+#endif
+
+#ifdef HAVE_ALLOCA_H
+# include <alloca.h>
+#endif
+
+#ifdef USE_MEMORY_H
+# include <memory.h>
+#endif
+
+#ifndef min
+# define min(x,y) ((x)>(y)?(y):(x))
+#endif
+
+#ifndef max
+# define max(x,y) ((x)<(y)?(y):(x))
+#endif
+
+#endif /* _OS_H */
+#endif
+
diff --git a/library/ADK2/v_os_types.h b/library/ADK2/v_os_types.h
new file mode 100644
index 0000000..97c85d0
--- /dev/null
+++ b/library/ADK2/v_os_types.h
@@ -0,0 +1,140 @@
+#ifdef ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2002 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: #ifdef jail to whip a few platforms into the UNIX ideal.
+
+ ********************************************************************/
+#ifndef _OS_TYPES_H
+#define _OS_TYPES_H
+
+//defines since we cannot have a makefile...
+#define BYTE_ORDER 1
+#define LITTLE_ENDIAN 1
+#define BIG_ENDIAN=2
+#define _ARM_ASSEM_
+
+
+#ifdef _LOW_ACCURACY_
+# define X(n) (((((n)>>22)+1)>>1) - ((((n)>>22)+1)>>9))
+# define LOOKUP_T const unsigned char
+#else
+# define X(n) (n)
+# define LOOKUP_T const ogg_int32_t
+#endif
+
+/* make it easy on the folks that want to compile the libs with a
+ different malloc than stdlib */
+#if 1
+#define _ogg_malloc malloc
+#define _ogg_calloc calloc
+#define _ogg_realloc realloc
+#define _ogg_free free
+#else
+#define _ogg_malloc(x) ({ \
+ void *p = malloc(x); \
+ dbgPrintf("M %d = %p\n", (x), p); \
+ p; \
+})
+#define _ogg_calloc(x,y) ({ \
+ void *p = calloc(x,y); \
+ dbgPrintf("C %d %d \ %p\n", (x), (y), p); \
+ p; \
+})
+#define _ogg_realloc(x,y) ({ \
+ void *p = realloc(x,y); \
+ dbgPrintf("R %d %d = %p\n", (x), (y), p); \
+ p; \
+})
+#define _ogg_free(x) ({ \
+ dbgPrintf("F %p\n", (x)); \
+ free(x); \
+})
+
+#undef alloca
+#define alloca(x) ({ \
+ void *p = __builtin_alloca(x); \
+ dbgPrintf("A %d F %p bot %p\n", (x), __builtin_frame_address(0), p); \
+ p; \
+})
+#endif
+
+#if 0
+#define VT do { \
+ dbgPrintf("%s:%d Frame %p\n", __func__, __LINE__, __builtin_frame_address(0)); \
+} while (0)
+#else
+#define VT do { } while (0)
+#endif
+
+#ifdef _WIN32
+
+# ifndef __GNUC__
+ /* MSVC/Borland */
+ typedef __int64 ogg_int64_t;
+ typedef __int32 ogg_int32_t;
+ typedef unsigned __int32 ogg_uint32_t;
+ typedef __int16 ogg_int16_t;
+ typedef unsigned __int16 ogg_uint16_t;
+# else
+ /* Cygwin */
+ #include <_G_config.h>
+ typedef _G_int64_t ogg_int64_t;
+ typedef _G_int32_t ogg_int32_t;
+ typedef _G_uint32_t ogg_uint32_t;
+ typedef _G_int16_t ogg_int16_t;
+ typedef _G_uint16_t ogg_uint16_t;
+# endif
+
+#elif defined(__MACOS__)
+
+# include <sys/types.h>
+ typedef SInt16 ogg_int16_t;
+ typedef UInt16 ogg_uint16_t;
+ typedef SInt32 ogg_int32_t;
+ typedef UInt32 ogg_uint32_t;
+ typedef SInt64 ogg_int64_t;
+
+#elif defined(__MACOSX__) /* MacOS X Framework build */
+
+# include <sys/types.h>
+ typedef int16_t ogg_int16_t;
+ typedef u_int16_t ogg_uint16_t;
+ typedef int32_t ogg_int32_t;
+ typedef u_int32_t ogg_uint32_t;
+ typedef int64_t ogg_int64_t;
+
+#elif defined(__BEOS__)
+
+ /* Be */
+# include <inttypes.h>
+
+#elif defined (__EMX__)
+
+ /* OS/2 GCC */
+ typedef short ogg_int16_t;
+ typedef unsigned short ogg_uint16_t;
+ typedef int ogg_int32_t;
+ typedef unsigned int ogg_uint32_t;
+ typedef long long ogg_int64_t;
+
+#else
+
+# include <sys/types.h>
+# include "v_config_types.h"
+
+#endif
+
+#endif /* _OS_TYPES_H */
+#endif
+
diff --git a/library/ADK2/v_res012.c b/library/ADK2/v_res012.c
new file mode 100644
index 0000000..143f1ba
--- /dev/null
+++ b/library/ADK2/v_res012.c
@@ -0,0 +1,226 @@
+#define ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: residue backend 0, 1 and 2 implementation
+
+ ********************************************************************/
+
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+#include "v_ogg.h"
+#include "v_ivorbiscodec.h"
+#include "v_codec_internal.h"
+#include "v_codebook.h"
+#include "v_misc.h"
+#include "v_os.h"
+
+void res_clear_info(vorbis_info_residue *info){
+ if(info){
+ if(info->stagemasks)_ogg_free(info->stagemasks);
+ if(info->stagebooks)_ogg_free(info->stagebooks);
+ memset(info,0,sizeof(*info));
+ }
+}
+
+
+/* vorbis_info is for range checking */
+int res_unpack(vorbis_info_residue *info,
+ vorbis_info *vi,oggpack_buffer *opb){
+ int j,k;
+ codec_setup_info *ci=(codec_setup_info *)vi->codec_setup;
+ memset(info,0,sizeof(*info));
+
+ info->type=oggpack_read(opb,16);
+ if(info->type>2 || info->type<0)goto errout;
+ info->begin=oggpack_read(opb,24);
+ info->end=oggpack_read(opb,24);
+ info->grouping=oggpack_read(opb,24)+1;
+ info->partitions=oggpack_read(opb,6)+1;
+ info->groupbook=oggpack_read(opb,8);
+ if(info->groupbook>=ci->books)goto errout;
+
+ info->stagemasks=_ogg_malloc(info->partitions*sizeof(*info->stagemasks));
+ info->stagebooks=_ogg_malloc(info->partitions*8*sizeof(*info->stagebooks));
+
+ for(j=0;j<info->partitions;j++){
+ int cascade=oggpack_read(opb,3);
+ if(oggpack_read(opb,1))
+ cascade|=(oggpack_read(opb,5)<<3);
+ info->stagemasks[j]=cascade;
+ }
+
+ for(j=0;j<info->partitions;j++){
+ for(k=0;k<8;k++){
+ if((info->stagemasks[j]>>k)&1){
+ unsigned char book=oggpack_read(opb,8);
+ if(book>=ci->books)goto errout;
+ info->stagebooks[j*8+k]=book;
+ if(k+1>info->stages)info->stages=k+1;
+ }else
+ info->stagebooks[j*8+k]=0xff;
+ }
+ }
+
+ if(oggpack_eop(opb))goto errout;
+
+ return 0;
+ errout:
+ res_clear_info(info);
+ return 1;
+}
+
+int res_inverse(vorbis_dsp_state *vd,vorbis_info_residue *info,
+ ogg_int32_t **in,int *nonzero,int ch){
+
+ int i,j,k,s,used=0;
+ codec_setup_info *ci=(codec_setup_info *)vd->vi->codec_setup;
+ codebook *phrasebook=ci->book_param+info->groupbook;
+ int samples_per_partition=info->grouping;
+ int partitions_per_word=phrasebook->dim;
+ int pcmend=ci->blocksizes[vd->W];
+
+ if(info->type<2){
+ int max=pcmend>>1;
+ int end=(info->end<max?info->end:max);
+ int n=end-info->begin;
+
+ if(n>0){
+ int partvals=n/samples_per_partition;
+ int partwords=(partvals+partitions_per_word-1)/partitions_per_word;
+
+ for(i=0;i<ch;i++)
+ if(nonzero[i])
+ in[used++]=in[i];
+ ch=used;
+
+ if(used){
+
+ char **partword=(char **)alloca(ch*sizeof(*partword));
+ for(j=0;j<ch;j++)
+ partword[j]=(char *)alloca(partwords*partitions_per_word*
+ sizeof(*partword[j]));
+
+ for(s=0;s<info->stages;s++){
+
+ for(i=0;i<partvals;){
+ if(s==0){
+ /* fetch the partition word for each channel */
+
+ partword[0][i+partitions_per_word-1]=1;
+ for(k=partitions_per_word-2;k>=0;k--)
+ partword[0][i+k]=partword[0][i+k+1]*info->partitions;
+
+ for(j=1;j<ch;j++)
+ for(k=partitions_per_word-1;k>=0;k--)
+ partword[j][i+k]=partword[j-1][i+k];
+
+ for(j=0;j<ch;j++){
+ int temp=vorbis_book_decode(phrasebook,&vd->opb);
+ if(temp==-1)goto eopbreak;
+
+ /* this can be done quickly in assembly due to the quotient
+ always being at most six bits */
+ for(k=0;k<partitions_per_word;k++){
+ ogg_uint32_t div=partword[j][i+k];
+ partword[j][i+k]=temp/div;
+ temp-=partword[j][i+k]*div;
+ }
+
+ }
+ }
+
+ /* now we decode residual values for the partitions */
+ for(k=0;k<partitions_per_word && i<partvals;k++,i++)
+ for(j=0;j<ch;j++){
+ long offset=info->begin+i*samples_per_partition;
+ if(info->stagemasks[(int)partword[j][i]]&(1<<s)){
+ codebook *stagebook=ci->book_param+
+ info->stagebooks[(partword[j][i]<<3)+s];
+ if(info->type){
+ if(vorbis_book_decodev_add(stagebook,in[j]+offset,&vd->opb,
+ samples_per_partition,-8)==-1)
+ goto eopbreak;
+ }else{
+ if(vorbis_book_decodevs_add(stagebook,in[j]+offset,&vd->opb,
+ samples_per_partition,-8)==-1)
+ goto eopbreak;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }else{
+ int max=(pcmend*ch)>>1;
+ int end=(info->end<max?info->end:max);
+ int n=end-info->begin;
+
+ if(n>0){
+ int partvals=n/samples_per_partition;
+ int partwords=(partvals+partitions_per_word-1)/partitions_per_word;
+
+ char *partword=
+ (char *)alloca(partwords*partitions_per_word*sizeof(*partword));
+ int beginoff=info->begin/ch;
+
+ for(i=0;i<ch;i++)if(nonzero[i])break;
+ if(i==ch)return(0); /* no nonzero vectors */
+
+ samples_per_partition/=ch;
+
+ for(s=0;s<info->stages;s++){
+ for(i=0;i<partvals;){
+
+ if(s==0){
+ int temp;
+ partword[i+partitions_per_word-1]=1;
+ for(k=partitions_per_word-2;k>=0;k--)
+ partword[i+k]=partword[i+k+1]*info->partitions;
+
+ /* fetch the partition word */
+ temp=vorbis_book_decode(phrasebook,&vd->opb);
+ if(temp==-1)goto eopbreak;
+
+ /* this can be done quickly in assembly due to the quotient
+ always being at most six bits */
+ for(k=0;k<partitions_per_word;k++){
+ ogg_uint32_t div=partword[i+k];
+ partword[i+k]=temp/div;
+ temp-=partword[i+k]*div;
+ }
+ }
+
+ /* now we decode residual values for the partitions */
+ for(k=0;k<partitions_per_word && i<partvals;k++,i++)
+ if(info->stagemasks[(int)partword[i]]&(1<<s)){
+ codebook *stagebook=ci->book_param+
+ info->stagebooks[(partword[i]<<3)+s];
+ if(vorbis_book_decodevv_add(stagebook,in,
+ i*samples_per_partition+beginoff,ch,
+ &vd->opb,
+ samples_per_partition,-8)==-1)
+ goto eopbreak;
+ }
+ }
+ }
+ }
+ }
+ errout:
+ eopbreak:
+
+ return 0;
+}
+
diff --git a/library/ADK2/v_vorbisfile.c b/library/ADK2/v_vorbisfile.c
new file mode 100644
index 0000000..b9e2788
--- /dev/null
+++ b/library/ADK2/v_vorbisfile.c
@@ -0,0 +1,1590 @@
+#define ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2003 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: stdio-based convenience library for opening/seeking/decoding
+ last mod: $Id: vorbisfile.c,v 1.6.2.5 2003/11/20 06:16:17 xiphmont Exp $
+
+ ********************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <errno.h>
+#include <string.h>
+#include <math.h>
+
+#include "v_codec_internal.h"
+#include "v_ivorbisfile.h"
+
+#include "v_os.h"
+#include "v_misc.h"
+
+#define NOTOPEN 0
+#define PARTOPEN 1
+#define OPENED 2
+#define STREAMSET 3 /* serialno and link set, but not to current link */
+#define LINKSET 4 /* serialno and link set to current link */
+#define INITSET 5
+
+/* A 'chained bitstream' is a Vorbis bitstream that contains more than
+ one logical bitstream arranged end to end (the only form of Ogg
+ multiplexing allowed in a Vorbis bitstream; grouping [parallel
+ multiplexing] is not allowed in Vorbis) */
+
+/* A Vorbis file can be played beginning to end (streamed) without
+ worrying ahead of time about chaining (see decoder_example.c). If
+ we have the whole file, however, and want random access
+ (seeking/scrubbing) or desire to know the total length/time of a
+ file, we need to account for the possibility of chaining. */
+
+/* We can handle things a number of ways; we can determine the entire
+ bitstream structure right off the bat, or find pieces on demand.
+ This example determines and caches structure for the entire
+ bitstream, but builds a virtual decoder on the fly when moving
+ between links in the chain. */
+
+/* There are also different ways to implement seeking. Enough
+ information exists in an Ogg bitstream to seek to
+ sample-granularity positions in the output. Or, one can seek by
+ picking some portion of the stream roughly in the desired area if
+ we only want coarse navigation through the stream. */
+
+/*************************************************************************
+ * Many, many internal helpers. The intention is not to be confusing;
+ * rampant duplication and monolithic function implementation would be
+ * harder to understand anyway. The high level functions are last. Begin
+ * grokking near the end of the file */
+
+
+/* read a little more data from the file/pipe into the ogg_sync framer */
+static long _get_data(OggVorbis_File *vf){
+ errno=0;
+ if(vf->datasource){
+ unsigned char *buffer=ogg_sync_bufferin(vf->oy,CHUNKSIZE);
+ long bytes=(vf->callbacks.read_func)(buffer,1,CHUNKSIZE,vf->datasource);
+ if(bytes>0)ogg_sync_wrote(vf->oy,bytes);
+ if(bytes==0 && errno)return -1;
+ return bytes;
+ }else
+ return 0;
+}
+
+/* save a tiny smidge of verbosity to make the code more readable */
+static void _seek_helper(OggVorbis_File *vf,ogg_int64_t offset){
+ if(vf->datasource){
+ (vf->callbacks.seek_func)(vf->datasource, offset, SEEK_SET);
+ vf->offset=offset;
+ ogg_sync_reset(vf->oy);
+ }else{
+ /* shouldn't happen unless someone writes a broken callback */
+ return;
+ }
+}
+
+/* The read/seek functions track absolute position within the stream */
+
+/* from the head of the stream, get the next page. boundary specifies
+ if the function is allowed to fetch more data from the stream (and
+ how much) or only use internally buffered data.
+
+ boundary: -1) unbounded search
+ 0) read no additional data; use cached only
+ n) search for a new page beginning for n bytes
+
+ return: <0) did not find a page (OV_FALSE, OV_EOF, OV_EREAD)
+ n) found a page at absolute offset n
+
+ produces a refcounted page */
+
+static ogg_int64_t _get_next_page(OggVorbis_File *vf,ogg_page *og,
+ ogg_int64_t boundary){
+ if(boundary>0)boundary+=vf->offset;
+ while(1){
+ long more;
+
+ if(boundary>0 && vf->offset>=boundary)return OV_FALSE;
+ more=ogg_sync_pageseek(vf->oy,og);
+
+ if(more<0){
+ /* skipped n bytes */
+ vf->offset-=more;
+ }else{
+ if(more==0){
+ /* send more paramedics */
+ if(!boundary)return OV_FALSE;
+ {
+ long ret=_get_data(vf);
+ if(ret==0)return OV_EOF;
+ if(ret<0)return OV_EREAD;
+ }
+ }else{
+ /* got a page. Return the offset at the page beginning,
+ advance the internal offset past the page end */
+ ogg_int64_t ret=vf->offset;
+ vf->offset+=more;
+ return ret;
+
+ }
+ }
+ }
+}
+
+/* find the latest page beginning before the current stream cursor
+ position. Much dirtier than the above as Ogg doesn't have any
+ backward search linkage. no 'readp' as it will certainly have to
+ read. */
+/* returns offset or OV_EREAD, OV_FAULT and produces a refcounted page */
+
+static ogg_int64_t _get_prev_page(OggVorbis_File *vf,ogg_page *og){
+ ogg_int64_t begin=vf->offset;
+ ogg_int64_t end=begin;
+ ogg_int64_t ret;
+ ogg_int64_t offset=-1;
+
+ while(offset==-1){
+ begin-=CHUNKSIZE;
+ if(begin<0)
+ begin=0;
+ _seek_helper(vf,begin);
+ while(vf->offset<end){
+ ret=_get_next_page(vf,og,end-vf->offset);
+ if(ret==OV_EREAD)return OV_EREAD;
+ if(ret<0){
+ break;
+ }else{
+ offset=ret;
+ }
+ }
+ }
+
+ /* we have the offset. Actually snork and hold the page now */
+ _seek_helper(vf,offset);
+ ret=_get_next_page(vf,og,CHUNKSIZE);
+ if(ret<0)
+ /* this shouldn't be possible */
+ return OV_EFAULT;
+
+ return offset;
+}
+
+/* finds each bitstream link one at a time using a bisection search
+ (has to begin by knowing the offset of the lb's initial page).
+ Recurses for each link so it can alloc the link storage after
+ finding them all, then unroll and fill the cache at the same time */
+static int _bisect_forward_serialno(OggVorbis_File *vf,
+ ogg_int64_t begin,
+ ogg_int64_t searched,
+ ogg_int64_t end,
+ ogg_uint32_t currentno,
+ long m){
+ ogg_int64_t endsearched=end;
+ ogg_int64_t next=end;
+ ogg_page og={0,0,0,0};
+ ogg_int64_t ret;
+
+ /* the below guards against garbage seperating the last and
+ first pages of two links. */
+ while(searched<endsearched){
+ ogg_int64_t bisect;
+
+ if(endsearched-searched<CHUNKSIZE){
+ bisect=searched;
+ }else{
+ bisect=(searched+endsearched)/2;
+ }
+
+ _seek_helper(vf,bisect);
+ ret=_get_next_page(vf,&og,-1);
+ if(ret==OV_EREAD)return OV_EREAD;
+ if(ret<0 || ogg_page_serialno(&og)!=currentno){
+ endsearched=bisect;
+ if(ret>=0)next=ret;
+ }else{
+ searched=ret+og.header_len+og.body_len;
+ }
+ ogg_page_release(&og);
+ }
+
+ _seek_helper(vf,next);
+ ret=_get_next_page(vf,&og,-1);
+ if(ret==OV_EREAD)return OV_EREAD;
+
+ if(searched>=end || ret<0){
+ ogg_page_release(&og);
+ vf->links=m+1;
+ vf->offsets=_ogg_malloc((vf->links+1)*sizeof(*vf->offsets));
+ vf->serialnos=_ogg_malloc(vf->links*sizeof(*vf->serialnos));
+ vf->offsets[m+1]=searched;
+ }else{
+ ret=_bisect_forward_serialno(vf,next,vf->offset,
+ end,ogg_page_serialno(&og),m+1);
+ ogg_page_release(&og);
+ if(ret==OV_EREAD)return OV_EREAD;
+ }
+
+ vf->offsets[m]=begin;
+ vf->serialnos[m]=currentno;
+ return 0;
+}
+
+static int _decode_clear(OggVorbis_File *vf){
+ if(vf->ready_state==INITSET){
+ vorbis_dsp_destroy(vf->vd);
+ vf->vd=0;
+ vf->ready_state=STREAMSET;
+ }
+
+ if(vf->ready_state>=STREAMSET){
+ vorbis_info_clear(&vf->vi);
+ vorbis_comment_clear(&vf->vc);
+ vf->ready_state=OPENED;
+ }
+ return 0;
+}
+
+/* uses the local ogg_stream storage in vf; this is important for
+ non-streaming input sources */
+/* consumes the page that's passed in (if any) */
+/* state is LINKSET upon successful return */
+
+static int _fetch_headers(OggVorbis_File *vf,
+ vorbis_info *vi,
+ vorbis_comment *vc,
+ ogg_uint32_t *serialno,
+ ogg_page *og_ptr){
+ ogg_page og={0,0,0,0};
+ ogg_packet op={0,0,0,0,0,0};
+ int i,ret;
+
+ if(vf->ready_state>OPENED)_decode_clear(vf);
+
+ if(!og_ptr){
+ ogg_int64_t llret=_get_next_page(vf,&og,CHUNKSIZE);
+ if(llret==OV_EREAD)return OV_EREAD;
+ if(llret<0)return OV_ENOTVORBIS;
+ og_ptr=&og;
+ }
+
+ ogg_stream_reset_serialno(vf->os,ogg_page_serialno(og_ptr));
+ if(serialno)*serialno=vf->os->serialno;
+
+ /* extract the initial header from the first page and verify that the
+ Ogg bitstream is in fact Vorbis data */
+
+ vorbis_info_init(vi);
+ vorbis_comment_init(vc);
+
+ i=0;
+ while(i<3){
+ ogg_stream_pagein(vf->os,og_ptr);
+ while(i<3){
+ int result=ogg_stream_packetout(vf->os,&op);
+ if(result==0)break;
+ if(result==-1){
+ ret=OV_EBADHEADER;
+ goto bail_header;
+ }
+ if((ret=vorbis_dsp_headerin(vi,vc,&op))){
+ goto bail_header;
+ }
+ i++;
+ }
+ if(i<3)
+ if(_get_next_page(vf,og_ptr,CHUNKSIZE)<0){
+ ret=OV_EBADHEADER;
+ goto bail_header;
+ }
+ }
+
+ ogg_packet_release(&op);
+ ogg_page_release(&og);
+ vf->ready_state=LINKSET;
+ return 0;
+
+ bail_header:
+ ogg_packet_release(&op);
+ ogg_page_release(&og);
+ vorbis_info_clear(vi);
+ vorbis_comment_clear(vc);
+ vf->ready_state=OPENED;
+
+ return ret;
+}
+
+/* we no longer preload all vorbis_info (and the associated
+ codec_setup) structs. Call this to seek and fetch the info from
+ the bitstream, if needed */
+static int _set_link_number(OggVorbis_File *vf,int link){
+ if(link != vf->current_link) _decode_clear(vf);
+ if(vf->ready_state<STREAMSET){
+ _seek_helper(vf,vf->offsets[link]);
+ ogg_stream_reset_serialno(vf->os,vf->serialnos[link]);
+ vf->current_serialno=vf->serialnos[link];
+ vf->current_link=link;
+ return _fetch_headers(vf,&vf->vi,&vf->vc,&vf->current_serialno,NULL);
+ }
+ return 0;
+}
+
+static int _set_link_number_preserve_pos(OggVorbis_File *vf,int link){
+ ogg_int64_t pos=vf->offset;
+ int ret=_set_link_number(vf,link);
+ if(ret)return ret;
+ _seek_helper(vf,pos);
+ if(pos<vf->offsets[link] || pos>=vf->offsets[link+1])
+ vf->ready_state=STREAMSET;
+ return 0;
+}
+
+/* last step of the OggVorbis_File initialization; get all the offset
+ positions. Only called by the seekable initialization (local
+ stream storage is hacked slightly; pay attention to how that's
+ done) */
+
+/* this is void and does not propogate errors up because we want to be
+ able to open and use damaged bitstreams as well as we can. Just
+ watch out for missing information for links in the OggVorbis_File
+ struct */
+static void _prefetch_all_offsets(OggVorbis_File *vf, ogg_int64_t dataoffset){
+ ogg_page og={0,0,0,0};
+ int i;
+ ogg_int64_t ret;
+
+ vf->dataoffsets=_ogg_malloc(vf->links*sizeof(*vf->dataoffsets));
+ vf->pcmlengths=_ogg_malloc(vf->links*2*sizeof(*vf->pcmlengths));
+
+ for(i=0;i<vf->links;i++){
+ if(i==0){
+ /* we already grabbed the initial header earlier. Just set the offset */
+ vf->dataoffsets[i]=dataoffset;
+ _seek_helper(vf,dataoffset);
+
+ }else{
+
+ /* seek to the location of the initial header */
+
+ _seek_helper(vf,vf->offsets[i]);
+ if(_fetch_headers(vf,&vf->vi,&vf->vc,NULL,NULL)<0){
+ vf->dataoffsets[i]=-1;
+ }else{
+ vf->dataoffsets[i]=vf->offset;
+ }
+ }
+
+ /* fetch beginning PCM offset */
+
+ if(vf->dataoffsets[i]!=-1){
+ ogg_int64_t accumulated=0,pos;
+ long lastblock=-1;
+ int result;
+
+ ogg_stream_reset_serialno(vf->os,vf->serialnos[i]);
+
+ while(1){
+ ogg_packet op={0,0,0,0,0,0};
+
+ ret=_get_next_page(vf,&og,-1);
+ if(ret<0)
+ /* this should not be possible unless the file is
+ truncated/mangled */
+ break;
+
+ if(ogg_page_serialno(&og)!=vf->serialnos[i])
+ break;
+
+ pos=ogg_page_granulepos(&og);
+
+ /* count blocksizes of all frames in the page */
+ ogg_stream_pagein(vf->os,&og);
+ while((result=ogg_stream_packetout(vf->os,&op))){
+ if(result>0){ /* ignore holes */
+ long thisblock=vorbis_packet_blocksize(&vf->vi,&op);
+ if(lastblock!=-1)
+ accumulated+=(lastblock+thisblock)>>2;
+ lastblock=thisblock;
+ }
+ }
+ ogg_packet_release(&op);
+
+ if(pos!=-1){
+ /* pcm offset of last packet on the first audio page */
+ accumulated= pos-accumulated;
+ break;
+ }
+ }
+
+ /* less than zero? This is a stream with samples trimmed off
+ the beginning, a normal occurrence; set the offset to zero */
+ if(accumulated<0)accumulated=0;
+
+ vf->pcmlengths[i*2]=accumulated;
+ }
+
+ /* get the PCM length of this link. To do this,
+ get the last page of the stream */
+ {
+ ogg_int64_t end=vf->offsets[i+1];
+ _seek_helper(vf,end);
+
+ while(1){
+ ret=_get_prev_page(vf,&og);
+ if(ret<0){
+ /* this should not be possible */
+ vorbis_info_clear(&vf->vi);
+ vorbis_comment_clear(&vf->vc);
+ break;
+ }
+ if(ogg_page_granulepos(&og)!=-1){
+ vf->pcmlengths[i*2+1]=ogg_page_granulepos(&og)-vf->pcmlengths[i*2];
+ break;
+ }
+ vf->offset=ret;
+ }
+ }
+ }
+ ogg_page_release(&og);
+}
+
+static int _make_decode_ready(OggVorbis_File *vf){
+ int i;
+ switch(vf->ready_state){
+ case OPENED:
+ case STREAMSET:
+ for(i=0;i<vf->links;i++)
+ if(vf->offsets[i+1]>=vf->offset)break;
+ if(i==vf->links)return -1;
+ i=_set_link_number_preserve_pos(vf,i);
+ if(i)return i;
+ /* fall through */
+ case LINKSET:
+ vf->vd=vorbis_dsp_create(&vf->vi);
+ vf->ready_state=INITSET;
+ vf->bittrack=0;
+ vf->samptrack=0;
+ case INITSET:
+ return 0;
+ default:
+ return -1;
+ }
+
+}
+
+static int _open_seekable2(OggVorbis_File *vf){
+ ogg_uint32_t serialno=vf->current_serialno;
+ ogg_uint32_t tempserialno;
+ ogg_int64_t dataoffset=vf->offset, end;
+ ogg_page og={0,0,0,0};
+
+ /* we're partially open and have a first link header state in
+ storage in vf */
+ /* we can seek, so set out learning all about this file */
+ (vf->callbacks.seek_func)(vf->datasource,0,SEEK_END);
+ vf->offset=vf->end=(vf->callbacks.tell_func)(vf->datasource);
+
+ /* We get the offset for the last page of the physical bitstream.
+ Most OggVorbis files will contain a single logical bitstream */
+ end=_get_prev_page(vf,&og);
+ if(end<0)return end;
+
+ /* more than one logical bitstream? */
+ tempserialno=ogg_page_serialno(&og);
+ ogg_page_release(&og);
+
+ if(tempserialno!=serialno){
+
+ /* Chained bitstream. Bisect-search each logical bitstream
+ section. Do so based on serial number only */
+ if(_bisect_forward_serialno(vf,0,0,end+1,serialno,0)<0)return OV_EREAD;
+
+ }else{
+
+ /* Only one logical bitstream */
+ if(_bisect_forward_serialno(vf,0,end,end+1,serialno,0))return OV_EREAD;
+
+ }
+
+ /* the initial header memory is referenced by vf after; don't free it */
+ _prefetch_all_offsets(vf,dataoffset);
+ return ov_raw_seek(vf,0);
+}
+
+/* fetch and process a packet. Handles the case where we're at a
+ bitstream boundary and dumps the decoding machine. If the decoding
+ machine is unloaded, it loads it. It also keeps pcm_offset up to
+ date (seek and read both use this. seek uses a special hack with
+ readp).
+
+ return: <0) error, OV_HOLE (lost packet) or OV_EOF
+ 0) need more data (only if readp==0)
+ 1) got a packet
+*/
+
+static int _fetch_and_process_packet(OggVorbis_File *vf,
+ int readp,
+ int spanp){
+ ogg_page og={0,0,0,0};
+ ogg_packet op={0,0,0,0,0,0};
+ int ret=0;
+
+ /* handle one packet. Try to fetch it from current stream state */
+ /* extract packets from page */
+ while(1){
+
+ /* process a packet if we can. If the machine isn't loaded,
+ neither is a page */
+ if(vf->ready_state==INITSET){
+ while(1) {
+ int result=ogg_stream_packetout(vf->os,&op);
+ ogg_int64_t granulepos;
+
+ if(result<0){
+ ret=OV_HOLE; /* hole in the data. */
+ goto cleanup;
+ }
+ if(result>0){
+ /* got a packet. process it */
+ granulepos=op.granulepos;
+ if(!vorbis_dsp_synthesis(vf->vd,&op,1)){ /* lazy check for lazy
+ header handling. The
+ header packets aren't
+ audio, so if/when we
+ submit them,
+ vorbis_synthesis will
+ reject them */
+
+ vf->samptrack+=vorbis_dsp_pcmout(vf->vd,NULL,0);
+ vf->bittrack+=op.bytes*8;
+
+ /* update the pcm offset. */
+ if(granulepos!=-1 && !op.e_o_s){
+ int link=(vf->seekable?vf->current_link:0);
+ int i,samples;
+
+ /* this packet has a pcm_offset on it (the last packet
+ completed on a page carries the offset) After processing
+ (above), we know the pcm position of the *last* sample
+ ready to be returned. Find the offset of the *first*
+
+ As an aside, this trick is inaccurate if we begin
+ reading anew right at the last page; the end-of-stream
+ granulepos declares the last frame in the stream, and the
+ last packet of the last page may be a partial frame.
+ So, we need a previous granulepos from an in-sequence page
+ to have a reference point. Thus the !op.e_o_s clause
+ above */
+
+ if(vf->seekable && link>0)
+ granulepos-=vf->pcmlengths[link*2];
+ if(granulepos<0)granulepos=0; /* actually, this
+ shouldn't be possible
+ here unless the stream
+ is very broken */
+
+ samples=vorbis_dsp_pcmout(vf->vd,NULL,0);
+
+ granulepos-=samples;
+ for(i=0;i<link;i++)
+ granulepos+=vf->pcmlengths[i*2+1];
+ vf->pcm_offset=granulepos;
+ }
+ ret=1;
+ goto cleanup;
+ }
+ }
+ else
+ break;
+ }
+ }
+
+ if(vf->ready_state>=OPENED){
+ int ret;
+ if(!readp){
+ ret=0;
+ goto cleanup;
+ }
+ if((ret=_get_next_page(vf,&og,-1))<0){
+ ret=OV_EOF; /* eof. leave unitialized */
+ goto cleanup;
+ }
+
+ /* bitrate tracking; add the header's bytes here, the body bytes
+ are done by packet above */
+ vf->bittrack+=og.header_len*8;
+
+ /* has our decoding just traversed a bitstream boundary? */
+ if(vf->ready_state==INITSET){
+ if(vf->current_serialno!=ogg_page_serialno(&og)){
+ if(!spanp){
+ ret=OV_EOF;
+ goto cleanup;
+ }
+
+ _decode_clear(vf);
+ }
+ }
+ }
+
+ /* Do we need to load a new machine before submitting the page? */
+ /* This is different in the seekable and non-seekable cases.
+
+ In the seekable case, we already have all the header
+ information loaded and cached; we just initialize the machine
+ with it and continue on our merry way.
+
+ In the non-seekable (streaming) case, we'll only be at a
+ boundary if we just left the previous logical bitstream and
+ we're now nominally at the header of the next bitstream
+ */
+
+ if(vf->ready_state!=INITSET){
+ int link,ret;
+
+ if(vf->ready_state<STREAMSET){
+ if(vf->seekable){
+ vf->current_serialno=ogg_page_serialno(&og);
+
+ /* match the serialno to bitstream section. We use this rather than
+ offset positions to avoid problems near logical bitstream
+ boundaries */
+ for(link=0;link<vf->links;link++)
+ if(vf->serialnos[link]==vf->current_serialno)break;
+ if(link==vf->links){
+ ret=OV_EBADLINK; /* sign of a bogus stream. error out,
+ leave machine uninitialized */
+ goto cleanup;
+ }
+
+ vf->current_link=link;
+ ret=_fetch_headers(vf,&vf->vi,&vf->vc,&vf->current_serialno,&og);
+ if(ret) goto cleanup;
+
+ }else{
+ /* we're streaming */
+ /* fetch the three header packets, build the info struct */
+
+ int ret=_fetch_headers(vf,&vf->vi,&vf->vc,&vf->current_serialno,&og);
+ if(ret) goto cleanup;
+ vf->current_link++;
+ }
+ }
+
+ if(_make_decode_ready(vf)) return OV_EBADLINK;
+ }
+ ogg_stream_pagein(vf->os,&og);
+ }
+ cleanup:
+ ogg_packet_release(&op);
+ ogg_page_release(&og);
+ return ret;
+}
+
+/* if, eg, 64 bit stdio is configured by default, this will build with
+ fseek64 */
+static int _fseek64_wrap(FILE *f,ogg_int64_t off,int whence){
+ if(f==NULL)return -1;
+ return fseek(f,off,whence);
+}
+
+static int _ov_open1(void *f,OggVorbis_File *vf,char *initial,
+ long ibytes, ov_callbacks callbacks){
+ int offsettest=(f?callbacks.seek_func(f,0,SEEK_CUR):-1);
+ int ret;
+
+ memset(vf,0,sizeof(*vf));
+
+ /* Tremor assumes in multiple places that right shift of a signed
+ integer is an arithmetic shift */
+ if( (-1>>1) != -1) return OV_EIMPL;
+
+ vf->datasource=f;
+ vf->callbacks = callbacks;
+
+ /* init the framing state */
+ vf->oy=ogg_sync_create();
+
+ /* perhaps some data was previously read into a buffer for testing
+ against other stream types. Allow initialization from this
+ previously read data (as we may be reading from a non-seekable
+ stream) */
+ if(initial){
+ unsigned char *buffer=ogg_sync_bufferin(vf->oy,ibytes);
+ memcpy(buffer,initial,ibytes);
+ ogg_sync_wrote(vf->oy,ibytes);
+ }
+
+ /* can we seek? Stevens suggests the seek test was portable */
+ if(offsettest!=-1)vf->seekable=1;
+
+ /* No seeking yet; Set up a 'single' (current) logical bitstream
+ entry for partial open */
+ vf->links=1;
+ vf->os=ogg_stream_create(-1); /* fill in the serialno later */
+
+ /* Try to fetch the headers, maintaining all the storage */
+ if((ret=_fetch_headers(vf,&vf->vi,&vf->vc,&vf->current_serialno,NULL))<0){
+ vf->datasource=NULL;
+ ov_clear(vf);
+ }else if(vf->ready_state < PARTOPEN)
+ vf->ready_state=PARTOPEN;
+ return ret;
+}
+
+static int _ov_open2(OggVorbis_File *vf){
+ if(vf->ready_state < OPENED)
+ vf->ready_state=OPENED;
+ if(vf->seekable){
+ int ret=_open_seekable2(vf);
+ if(ret){
+ vf->datasource=NULL;
+ ov_clear(vf);
+ }
+ return ret;
+ }
+ return 0;
+}
+
+
+/* clear out the OggVorbis_File struct */
+int ov_clear(OggVorbis_File *vf){
+ if(vf){
+ vorbis_dsp_destroy(vf->vd);
+ vf->vd=0;
+ ogg_stream_destroy(vf->os);
+ vorbis_info_clear(&vf->vi);
+ vorbis_comment_clear(&vf->vc);
+ if(vf->dataoffsets)_ogg_free(vf->dataoffsets);
+ if(vf->pcmlengths)_ogg_free(vf->pcmlengths);
+ if(vf->serialnos)_ogg_free(vf->serialnos);
+ if(vf->offsets)_ogg_free(vf->offsets);
+ ogg_sync_destroy(vf->oy);
+
+ if(vf->datasource)(vf->callbacks.close_func)(vf->datasource);
+ memset(vf,0,sizeof(*vf));
+ }
+#ifdef DEBUG_LEAKS
+ _VDBG_dump();
+#endif
+ return 0;
+}
+
+/* inspects the OggVorbis file and finds/documents all the logical
+ bitstreams contained in it. Tries to be tolerant of logical
+ bitstream sections that are truncated/woogie.
+
+ return: -1) error
+ 0) OK
+*/
+
+int ov_open_callbacks(void *f,OggVorbis_File *vf,char *initial,long ibytes,
+ ov_callbacks callbacks){
+ int ret=_ov_open1(f,vf,initial,ibytes,callbacks);
+ if(ret)return ret;
+ return _ov_open2(vf);
+}
+
+int ov_open(FILE *f,OggVorbis_File *vf,char *initial,long ibytes){
+ ov_callbacks callbacks = {
+ (size_t (*)(void *, size_t, size_t, void *)) fread,
+ (int (*)(void *, ogg_int64_t, int)) _fseek64_wrap,
+ (int (*)(void *)) fclose,
+ (long (*)(void *)) ftell
+ };
+
+ return ov_open_callbacks((void *)f, vf, initial, ibytes, callbacks);
+}
+
+/* Only partially open the vorbis file; test for Vorbisness, and load
+ the headers for the first chain. Do not seek (although test for
+ seekability). Use ov_test_open to finish opening the file, else
+ ov_clear to close/free it. Same return codes as open. */
+
+int ov_test_callbacks(void *f,OggVorbis_File *vf,char *initial,long ibytes,
+ ov_callbacks callbacks)
+{
+ return _ov_open1(f,vf,initial,ibytes,callbacks);
+}
+
+int ov_test(FILE *f,OggVorbis_File *vf,char *initial,long ibytes){
+ ov_callbacks callbacks = {
+ (size_t (*)(void *, size_t, size_t, void *)) fread,
+ (int (*)(void *, ogg_int64_t, int)) _fseek64_wrap,
+ (int (*)(void *)) fclose,
+ (long (*)(void *)) ftell
+ };
+
+ return ov_test_callbacks((void *)f, vf, initial, ibytes, callbacks);
+}
+
+int ov_test_open(OggVorbis_File *vf){
+ if(vf->ready_state!=PARTOPEN)return OV_EINVAL;
+ return _ov_open2(vf);
+}
+
+/* How many logical bitstreams in this physical bitstream? */
+long ov_streams(OggVorbis_File *vf){
+ return vf->links;
+}
+
+/* Is the FILE * associated with vf seekable? */
+long ov_seekable(OggVorbis_File *vf){
+ return vf->seekable;
+}
+
+/* returns the bitrate for a given logical bitstream or the entire
+ physical bitstream. If the file is open for random access, it will
+ find the *actual* average bitrate. If the file is streaming, it
+ returns the nominal bitrate (if set) else the average of the
+ upper/lower bounds (if set) else -1 (unset).
+
+ If you want the actual bitrate field settings, get them from the
+ vorbis_info structs */
+
+long ov_bitrate(OggVorbis_File *vf,int i){
+ if(vf->ready_state<OPENED)return OV_EINVAL;
+ if(i>=vf->links)return OV_EINVAL;
+ if(!vf->seekable && i!=0)return ov_bitrate(vf,0);
+ if(i<0){
+ ogg_int64_t bits=0;
+ int i;
+ for(i=0;i<vf->links;i++)
+ bits+=(vf->offsets[i+1]-vf->dataoffsets[i])*8;
+ /* This once read: return(rint(bits/ov_time_total(vf,-1)));
+ * gcc 3.x on x86 miscompiled this at optimisation level 2 and above,
+ * so this is slightly transformed to make it work.
+ */
+ return bits*1000/ov_time_total(vf,-1);
+ }else{
+ if(vf->seekable){
+ /* return the actual bitrate */
+ return (vf->offsets[i+1]-vf->dataoffsets[i])*8000/ov_time_total(vf,i);
+ }else{
+ /* return nominal if set */
+ if(vf->vi.bitrate_nominal>0){
+ return vf->vi.bitrate_nominal;
+ }else{
+ if(vf->vi.bitrate_upper>0){
+ if(vf->vi.bitrate_lower>0){
+ return (vf->vi.bitrate_upper+vf->vi.bitrate_lower)/2;
+ }else{
+ return vf->vi.bitrate_upper;
+ }
+ }
+ return OV_FALSE;
+ }
+ }
+ }
+}
+
+/* returns the actual bitrate since last call. returns -1 if no
+ additional data to offer since last call (or at beginning of stream),
+ EINVAL if stream is only partially open
+*/
+long ov_bitrate_instant(OggVorbis_File *vf){
+ long ret;
+ if(vf->ready_state<OPENED)return OV_EINVAL;
+ if(vf->samptrack==0)return OV_FALSE;
+ ret=vf->bittrack/vf->samptrack*vf->vi.rate;
+ vf->bittrack=0;
+ vf->samptrack=0;
+ return ret;
+}
+
+/* Guess */
+long ov_serialnumber(OggVorbis_File *vf,int i){
+ if(i>=vf->links)return ov_serialnumber(vf,vf->links-1);
+ if(!vf->seekable && i>=0)return ov_serialnumber(vf,-1);
+ if(i<0){
+ return vf->current_serialno;
+ }else{
+ return vf->serialnos[i];
+ }
+}
+
+/* returns: total raw (compressed) length of content if i==-1
+ raw (compressed) length of that logical bitstream for i==0 to n
+ OV_EINVAL if the stream is not seekable (we can't know the length)
+ or if stream is only partially open
+*/
+ogg_int64_t ov_raw_total(OggVorbis_File *vf,int i){
+ if(vf->ready_state<OPENED)return OV_EINVAL;
+ if(!vf->seekable || i>=vf->links)return OV_EINVAL;
+ if(i<0){
+ ogg_int64_t acc=0;
+ int i;
+ for(i=0;i<vf->links;i++)
+ acc+=ov_raw_total(vf,i);
+ return acc;
+ }else{
+ return vf->offsets[i+1]-vf->offsets[i];
+ }
+}
+
+/* returns: total PCM length (samples) of content if i==-1 PCM length
+ (samples) of that logical bitstream for i==0 to n
+ OV_EINVAL if the stream is not seekable (we can't know the
+ length) or only partially open
+*/
+ogg_int64_t ov_pcm_total(OggVorbis_File *vf,int i){
+ if(vf->ready_state<OPENED)return OV_EINVAL;
+ if(!vf->seekable || i>=vf->links)return OV_EINVAL;
+ if(i<0){
+ ogg_int64_t acc=0;
+ int i;
+ for(i=0;i<vf->links;i++)
+ acc+=ov_pcm_total(vf,i);
+ return acc;
+ }else{
+ return vf->pcmlengths[i*2+1];
+ }
+}
+
+/* returns: total milliseconds of content if i==-1
+ milliseconds in that logical bitstream for i==0 to n
+ OV_EINVAL if the stream is not seekable (we can't know the
+ length) or only partially open
+*/
+ogg_int64_t ov_time_total(OggVorbis_File *vf,int i){
+ if(vf->ready_state<OPENED)return OV_EINVAL;
+ if(!vf->seekable || i>=vf->links)return OV_EINVAL;
+ if(i<0){
+ ogg_int64_t acc=0;
+ int i;
+ for(i=0;i<vf->links;i++)
+ acc+=ov_time_total(vf,i);
+ return acc;
+ }else{
+ return ((ogg_int64_t)vf->pcmlengths[i*2+1])*1000/vf->vi.rate;
+ }
+}
+
+/* seek to an offset relative to the *compressed* data. This also
+ scans packets to update the PCM cursor. It will cross a logical
+ bitstream boundary, but only if it can't get any packets out of the
+ tail of the bitstream we seek to (so no surprises).
+
+ returns zero on success, nonzero on failure */
+
+int ov_raw_seek(OggVorbis_File *vf,ogg_int64_t pos){
+ ogg_stream_state *work_os=NULL;
+ ogg_page og={0,0,0,0};
+ ogg_packet op={0,0,0,0,0,0};
+
+ if(vf->ready_state<OPENED)return OV_EINVAL;
+ if(!vf->seekable)
+ return OV_ENOSEEK; /* don't dump machine if we can't seek */
+
+ if(pos<0 || pos>vf->end)return OV_EINVAL;
+
+ /* don't yet clear out decoding machine (if it's initialized), in
+ the case we're in the same link. Restart the decode lapping, and
+ let _fetch_and_process_packet deal with a potential bitstream
+ boundary */
+ vf->pcm_offset=-1;
+ ogg_stream_reset_serialno(vf->os,
+ vf->current_serialno); /* must set serialno */
+ vorbis_dsp_restart(vf->vd);
+
+ _seek_helper(vf,pos);
+
+ /* we need to make sure the pcm_offset is set, but we don't want to
+ advance the raw cursor past good packets just to get to the first
+ with a granulepos. That's not equivalent behavior to beginning
+ decoding as immediately after the seek position as possible.
+
+ So, a hack. We use two stream states; a local scratch state and
+ the shared vf->os stream state. We use the local state to
+ scan, and the shared state as a buffer for later decode.
+
+ Unfortuantely, on the last page we still advance to last packet
+ because the granulepos on the last page is not necessarily on a
+ packet boundary, and we need to make sure the granpos is
+ correct.
+ */
+
+ {
+ int lastblock=0;
+ int accblock=0;
+ int thisblock;
+ int eosflag;
+
+ work_os=ogg_stream_create(vf->current_serialno); /* get the memory ready */
+ while(1){
+ if(vf->ready_state>=STREAMSET){
+ /* snarf/scan a packet if we can */
+ int result=ogg_stream_packetout(work_os,&op);
+
+ if(result>0){
+
+ if(vf->vi.codec_setup){
+ thisblock=vorbis_packet_blocksize(&vf->vi,&op);
+ if(thisblock<0){
+ ogg_stream_packetout(vf->os,NULL);
+ thisblock=0;
+ }else{
+
+ if(eosflag)
+ ogg_stream_packetout(vf->os,NULL);
+ else
+ if(lastblock)accblock+=(lastblock+thisblock)>>2;
+ }
+
+ if(op.granulepos!=-1){
+ int i,link=vf->current_link;
+ ogg_int64_t granulepos=op.granulepos-vf->pcmlengths[link*2];
+ if(granulepos<0)granulepos=0;
+
+ for(i=0;i<link;i++)
+ granulepos+=vf->pcmlengths[i*2+1];
+ vf->pcm_offset=granulepos-accblock;
+ break;
+ }
+ lastblock=thisblock;
+ continue;
+ }else
+ ogg_stream_packetout(vf->os,NULL);
+ }
+ }
+
+ if(!lastblock){
+ if(_get_next_page(vf,&og,-1)<0){
+ vf->pcm_offset=ov_pcm_total(vf,-1);
+ break;
+ }
+ }else{
+ /* huh? Bogus stream with packets but no granulepos */
+ vf->pcm_offset=-1;
+ break;
+ }
+
+ /* did we just grab a page from other than current link? */
+ if(vf->ready_state>=STREAMSET)
+ if(vf->current_serialno!=ogg_page_serialno(&og)){
+ _decode_clear(vf); /* clear out stream state */
+ ogg_stream_destroy(work_os);
+ }
+
+ if(vf->ready_state<STREAMSET){
+ int link;
+
+ vf->current_serialno=ogg_page_serialno(&og);
+ for(link=0;link<vf->links;link++)
+ if(vf->serialnos[link]==vf->current_serialno)break;
+ if(link==vf->links)
+ goto seek_error; /* sign of a bogus stream. error out,
+ leave machine uninitialized */
+
+ /* need to initialize machine to this link */
+ {
+ int ret=_set_link_number_preserve_pos(vf,link);
+ if(ret) goto seek_error;
+ }
+ ogg_stream_reset_serialno(vf->os,vf->current_serialno);
+ ogg_stream_reset_serialno(work_os,vf->current_serialno);
+
+
+ }
+
+ {
+ ogg_page dup;
+ ogg_page_dup(&dup,&og);
+ eosflag=ogg_page_eos(&og);
+ ogg_stream_pagein(vf->os,&og);
+ ogg_stream_pagein(work_os,&dup);
+ }
+ }
+ }
+
+ ogg_packet_release(&op);
+ ogg_page_release(&og);
+ ogg_stream_destroy(work_os);
+ vf->bittrack=0;
+ vf->samptrack=0;
+ return 0;
+
+ seek_error:
+ ogg_packet_release(&op);
+ ogg_page_release(&og);
+
+ /* dump the machine so we're in a known state */
+ vf->pcm_offset=-1;
+ ogg_stream_destroy(work_os);
+ _decode_clear(vf);
+ return OV_EBADLINK;
+}
+
+/* Page granularity seek (faster than sample granularity because we
+ don't do the last bit of decode to find a specific sample).
+
+ Seek to the last [granule marked] page preceeding the specified pos
+ location, such that decoding past the returned point will quickly
+ arrive at the requested position. */
+int ov_pcm_seek_page(OggVorbis_File *vf,ogg_int64_t pos){
+ int link=-1;
+ ogg_int64_t result=0;
+ ogg_int64_t total=ov_pcm_total(vf,-1);
+ ogg_page og={0,0,0,0};
+ ogg_packet op={0,0,0,0,0,0};
+
+ if(vf->ready_state<OPENED)return OV_EINVAL;
+ if(!vf->seekable)return OV_ENOSEEK;
+ if(pos<0 || pos>total)return OV_EINVAL;
+
+ /* which bitstream section does this pcm offset occur in? */
+ for(link=vf->links-1;link>=0;link--){
+ total-=vf->pcmlengths[link*2+1];
+ if(pos>=total)break;
+ }
+
+
+ if(link!=vf->current_link){
+ int ret=_set_link_number(vf,link);
+ if(ret) goto seek_error;
+ }else{
+ vorbis_dsp_restart(vf->vd);
+ }
+
+ ogg_stream_reset_serialno(vf->os,vf->serialnos[link]);
+
+ /* search within the logical bitstream for the page with the highest
+ pcm_pos preceeding (or equal to) pos. There is a danger here;
+ missing pages or incorrect frame number information in the
+ bitstream could make our task impossible. Account for that (it
+ would be an error condition) */
+
+ /* new search algorithm by HB (Nicholas Vinen) */
+ {
+ ogg_int64_t end=vf->offsets[link+1];
+ ogg_int64_t begin=vf->offsets[link];
+ ogg_int64_t begintime = vf->pcmlengths[link*2];
+ ogg_int64_t endtime = vf->pcmlengths[link*2+1]+begintime;
+ ogg_int64_t target=pos-total+begintime;
+ ogg_int64_t best=begin;
+
+ while(begin<end){
+ ogg_int64_t bisect;
+
+ if(end-begin<CHUNKSIZE){
+ bisect=begin;
+ }else{
+ /* take a (pretty decent) guess. */
+ bisect=begin +
+ (target-begintime)*(end-begin)/(endtime-begintime) - CHUNKSIZE;
+ if(bisect<=begin)
+ bisect=begin+1;
+ }
+
+ _seek_helper(vf,bisect);
+
+ while(begin<end){
+ result=_get_next_page(vf,&og,end-vf->offset);
+ if(result==OV_EREAD) goto seek_error;
+ if(result<0){
+ if(bisect<=begin+1)
+ end=begin; /* found it */
+ else{
+ if(bisect==0) goto seek_error;
+ bisect-=CHUNKSIZE;
+ if(bisect<=begin)bisect=begin+1;
+ _seek_helper(vf,bisect);
+ }
+ }else{
+ ogg_int64_t granulepos=ogg_page_granulepos(&og);
+ if(granulepos==-1)continue;
+ if(granulepos<target){
+ best=result; /* raw offset of packet with granulepos */
+ begin=vf->offset; /* raw offset of next page */
+ begintime=granulepos;
+
+ if(target-begintime>44100)break;
+ bisect=begin; /* *not* begin + 1 */
+ }else{
+ if(bisect<=begin+1)
+ end=begin; /* found it */
+ else{
+ if(end==vf->offset){ /* we're pretty close - we'd be stuck in */
+ end=result;
+ bisect-=CHUNKSIZE; /* an endless loop otherwise. */
+ if(bisect<=begin)bisect=begin+1;
+ _seek_helper(vf,bisect);
+ }else{
+ end=result;
+ endtime=granulepos;
+ break;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ /* found our page. seek to it, update pcm offset. Easier case than
+ raw_seek, don't keep packets preceeding granulepos. */
+ {
+
+ /* seek */
+ _seek_helper(vf,best);
+ vf->pcm_offset=-1;
+
+ if(_get_next_page(vf,&og,-1)<0){
+ ogg_page_release(&og);
+ return OV_EOF; /* shouldn't happen */
+ }
+
+ ogg_stream_pagein(vf->os,&og);
+
+ /* pull out all but last packet; the one with granulepos */
+ while(1){
+ result=ogg_stream_packetpeek(vf->os,&op);
+ if(result==0){
+ /* !!! the packet finishing this page originated on a
+ preceeding page. Keep fetching previous pages until we
+ get one with a granulepos or without the 'continued' flag
+ set. Then just use raw_seek for simplicity. */
+
+ _seek_helper(vf,best);
+
+ while(1){
+ result=_get_prev_page(vf,&og);
+ if(result<0) goto seek_error;
+ if(ogg_page_granulepos(&og)>-1 ||
+ !ogg_page_continued(&og)){
+ return ov_raw_seek(vf,result);
+ }
+ vf->offset=result;
+ }
+ }
+ if(result<0){
+ result = OV_EBADPACKET;
+ goto seek_error;
+ }
+ if(op.granulepos!=-1){
+ vf->pcm_offset=op.granulepos-vf->pcmlengths[vf->current_link*2];
+ if(vf->pcm_offset<0)vf->pcm_offset=0;
+ vf->pcm_offset+=total;
+ break;
+ }else
+ result=ogg_stream_packetout(vf->os,NULL);
+ }
+ }
+ }
+
+ /* verify result */
+ if(vf->pcm_offset>pos || pos>ov_pcm_total(vf,-1)){
+ result=OV_EFAULT;
+ goto seek_error;
+ }
+ vf->bittrack=0;
+ vf->samptrack=0;
+
+ ogg_page_release(&og);
+ ogg_packet_release(&op);
+ return 0;
+
+ seek_error:
+
+ ogg_page_release(&og);
+ ogg_packet_release(&op);
+
+ /* dump machine so we're in a known state */
+ vf->pcm_offset=-1;
+ _decode_clear(vf);
+ return (int)result;
+}
+
+/* seek to a sample offset relative to the decompressed pcm stream
+ returns zero on success, nonzero on failure */
+
+int ov_pcm_seek(OggVorbis_File *vf,ogg_int64_t pos){
+ ogg_packet op={0,0,0,0,0,0};
+ ogg_page og={0,0,0,0};
+ int thisblock,lastblock=0;
+ int ret=ov_pcm_seek_page(vf,pos);
+ if(ret<0)return ret;
+ if(_make_decode_ready(vf))return OV_EBADLINK;
+
+ /* discard leading packets we don't need for the lapping of the
+ position we want; don't decode them */
+
+ while(1){
+
+ int ret=ogg_stream_packetpeek(vf->os,&op);
+ if(ret>0){
+ thisblock=vorbis_packet_blocksize(&vf->vi,&op);
+ if(thisblock<0){
+ ogg_stream_packetout(vf->os,NULL);
+ continue; /* non audio packet */
+ }
+ if(lastblock)vf->pcm_offset+=(lastblock+thisblock)>>2;
+
+ if(vf->pcm_offset+((thisblock+
+ vorbis_info_blocksize(&vf->vi,1))>>2)>=pos)break;
+
+ /* remove the packet from packet queue and track its granulepos */
+ ogg_stream_packetout(vf->os,NULL);
+ vorbis_dsp_synthesis(vf->vd,&op,0); /* set up a vb with
+ only tracking, no
+ pcm_decode */
+
+ /* end of logical stream case is hard, especially with exact
+ length positioning. */
+
+ if(op.granulepos>-1){
+ int i;
+ /* always believe the stream markers */
+ vf->pcm_offset=op.granulepos-vf->pcmlengths[vf->current_link*2];
+ if(vf->pcm_offset<0)vf->pcm_offset=0;
+ for(i=0;i<vf->current_link;i++)
+ vf->pcm_offset+=vf->pcmlengths[i*2+1];
+ }
+
+ lastblock=thisblock;
+
+ }else{
+ if(ret<0 && ret!=OV_HOLE)break;
+
+ /* suck in a new page */
+ if(_get_next_page(vf,&og,-1)<0)break;
+ if(vf->current_serialno!=ogg_page_serialno(&og))_decode_clear(vf);
+
+ if(vf->ready_state<STREAMSET){
+ int link,ret;
+
+ vf->current_serialno=ogg_page_serialno(&og);
+ for(link=0;link<vf->links;link++)
+ if(vf->serialnos[link]==vf->current_serialno)break;
+ if(link==vf->links){
+ ogg_page_release(&og);
+ ogg_packet_release(&op);
+ return OV_EBADLINK;
+ }
+
+
+ vf->current_link=link;
+ ret=_fetch_headers(vf,&vf->vi,&vf->vc,&vf->current_serialno,&og);
+ if(ret) return ret;
+ if(_make_decode_ready(vf))return OV_EBADLINK;
+ lastblock=0;
+ }
+
+ ogg_stream_pagein(vf->os,&og);
+ }
+ }
+
+ vf->bittrack=0;
+ vf->samptrack=0;
+ /* discard samples until we reach the desired position. Crossing a
+ logical bitstream boundary with abandon is OK. */
+ while(vf->pcm_offset<pos){
+ ogg_int64_t target=pos-vf->pcm_offset;
+ long samples=vorbis_dsp_pcmout(vf->vd,NULL,0);
+
+ if(samples>target)samples=target;
+ vorbis_dsp_read(vf->vd,samples);
+ vf->pcm_offset+=samples;
+
+ if(samples<target)
+ if(_fetch_and_process_packet(vf,1,1)<=0)
+ vf->pcm_offset=ov_pcm_total(vf,-1); /* eof */
+ }
+
+ ogg_page_release(&og);
+ ogg_packet_release(&op);
+ return 0;
+}
+
+/* seek to a playback time relative to the decompressed pcm stream
+ returns zero on success, nonzero on failure */
+int ov_time_seek(OggVorbis_File *vf,ogg_int64_t milliseconds){
+ /* translate time to PCM position and call ov_pcm_seek */
+
+ int link=-1;
+ ogg_int64_t pcm_total=ov_pcm_total(vf,-1);
+ ogg_int64_t time_total=ov_time_total(vf,-1);
+
+ if(vf->ready_state<OPENED)return OV_EINVAL;
+ if(!vf->seekable)return OV_ENOSEEK;
+ if(milliseconds<0 || milliseconds>time_total)return OV_EINVAL;
+
+ /* which bitstream section does this time offset occur in? */
+ for(link=vf->links-1;link>=0;link--){
+ pcm_total-=vf->pcmlengths[link*2+1];
+ time_total-=ov_time_total(vf,link);
+ if(milliseconds>=time_total)break;
+ }
+
+ /* enough information to convert time offset to pcm offset */
+ {
+ int ret=_set_link_number(vf,link);
+ if(ret)return ret;
+ return
+ ov_pcm_seek(vf,pcm_total+(milliseconds-time_total)*
+ vf->vi.rate/1000);
+ }
+}
+
+/* page-granularity version of ov_time_seek
+ returns zero on success, nonzero on failure */
+int ov_time_seek_page(OggVorbis_File *vf,ogg_int64_t milliseconds){
+ /* translate time to PCM position and call ov_pcm_seek */
+
+ int link=-1;
+ ogg_int64_t pcm_total=ov_pcm_total(vf,-1);
+ ogg_int64_t time_total=ov_time_total(vf,-1);
+
+ if(vf->ready_state<OPENED)return OV_EINVAL;
+ if(!vf->seekable)return OV_ENOSEEK;
+ if(milliseconds<0 || milliseconds>time_total)return OV_EINVAL;
+
+ /* which bitstream section does this time offset occur in? */
+ for(link=vf->links-1;link>=0;link--){
+ pcm_total-=vf->pcmlengths[link*2+1];
+ time_total-=ov_time_total(vf,link);
+ if(milliseconds>=time_total)break;
+ }
+
+ /* enough information to convert time offset to pcm offset */
+ {
+ int ret=_set_link_number(vf,link);
+ if(ret)return ret;
+ return
+ ov_pcm_seek_page(vf,pcm_total+(milliseconds-time_total)*
+ vf->vi.rate/1000);
+ }
+}
+
+/* tell the current stream offset cursor. Note that seek followed by
+ tell will likely not give the set offset due to caching */
+ogg_int64_t ov_raw_tell(OggVorbis_File *vf){
+ if(vf->ready_state<OPENED)return OV_EINVAL;
+ return vf->offset;
+}
+
+/* return PCM offset (sample) of next PCM sample to be read */
+ogg_int64_t ov_pcm_tell(OggVorbis_File *vf){
+ if(vf->ready_state<OPENED)return OV_EINVAL;
+ return vf->pcm_offset;
+}
+
+/* return time offset (milliseconds) of next PCM sample to be read */
+ogg_int64_t ov_time_tell(OggVorbis_File *vf){
+ int link=0;
+ ogg_int64_t pcm_total=0;
+ ogg_int64_t time_total=0;
+
+ if(vf->ready_state<OPENED)return OV_EINVAL;
+ if(vf->seekable){
+ pcm_total=ov_pcm_total(vf,-1);
+ time_total=ov_time_total(vf,-1);
+
+ /* which bitstream section does this time offset occur in? */
+ for(link=vf->links-1;link>=0;link--){
+ pcm_total-=vf->pcmlengths[link*2+1];
+ time_total-=ov_time_total(vf,link);
+ if(vf->pcm_offset>=pcm_total)break;
+ }
+ }
+
+ return time_total+(1000*vf->pcm_offset-pcm_total)/vf->vi.rate;
+}
+
+/* link: -1) return the vorbis_info struct for the bitstream section
+ currently being decoded
+ 0-n) to request information for a specific bitstream section
+
+ In the case of a non-seekable bitstream, any call returns the
+ current bitstream. NULL in the case that the machine is not
+ initialized */
+
+vorbis_info *ov_info(OggVorbis_File *vf,int link){
+ if(vf->seekable){
+ if(link>=vf->links)return NULL;
+ if(link>=0){
+ int ret=_set_link_number_preserve_pos(vf,link);
+ if(ret)return NULL;
+ }
+ }
+ return &vf->vi;
+}
+
+/* grr, strong typing, grr, no templates/inheritence, grr */
+vorbis_comment *ov_comment(OggVorbis_File *vf,int link){
+ if(vf->seekable){
+ if(link>=vf->links)return NULL;
+ if(link>=0){
+ int ret=_set_link_number_preserve_pos(vf,link);
+ if(ret)return NULL;
+ }
+ }
+ return &vf->vc;
+}
+
+/* up to this point, everything could more or less hide the multiple
+ logical bitstream nature of chaining from the toplevel application
+ if the toplevel application didn't particularly care. However, at
+ the point that we actually read audio back, the multiple-section
+ nature must surface: Multiple bitstream sections do not necessarily
+ have to have the same number of channels or sampling rate.
+
+ ov_read returns the sequential logical bitstream number currently
+ being decoded along with the PCM data in order that the toplevel
+ application can take action on channel/sample rate changes. This
+ number will be incremented even for streamed (non-seekable) streams
+ (for seekable streams, it represents the actual logical bitstream
+ index within the physical bitstream. Note that the accessor
+ functions above are aware of this dichotomy).
+
+ input values: buffer) a buffer to hold packed PCM data for return
+ length) the byte length requested to be placed into buffer
+
+ return values: <0) error/hole in data (OV_HOLE), partial open (OV_EINVAL)
+ 0) EOF
+ n) number of bytes of PCM actually returned. The
+ below works on a packet-by-packet basis, so the
+ return length is not related to the 'length' passed
+ in, just guaranteed to fit.
+
+ *section) set to the logical bitstream number */
+
+long ov_read(OggVorbis_File *vf,void *buffer,int bytes_req,int *bitstream){
+
+ long samples;
+ long channels;
+
+ if(vf->ready_state<OPENED)return OV_EINVAL;
+
+ while(1){
+ if(vf->ready_state==INITSET){
+ channels=vf->vi.channels;
+ samples=vorbis_dsp_pcmout(vf->vd,buffer,(bytes_req>>1)/channels);
+ if(samples){
+ if(samples>0){
+ vorbis_dsp_read(vf->vd,samples);
+ vf->pcm_offset+=samples;
+ if(bitstream)*bitstream=vf->current_link;
+ return samples*2*channels;
+ }
+ return samples;
+ }
+ }
+
+ /* suck in another packet */
+ {
+ int ret=_fetch_and_process_packet(vf,1,1);
+ if(ret==OV_EOF)
+ return 0;
+ if(ret<=0)
+ return ret;
+ }
+
+ }
+}
diff --git a/library/ADK2/v_window_lookup.h b/library/ADK2/v_window_lookup.h
new file mode 100644
index 0000000..690d677
--- /dev/null
+++ b/library/ADK2/v_window_lookup.h
@@ -0,0 +1,2090 @@
+#ifdef ADK_INTERNAL
+/********************************************************************
+ * *
+ * THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE CODE. *
+ * *
+ * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
+ * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
+ * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
+ * *
+ * THE OggVorbis 'TREMOR' SOURCE CODE IS (C) COPYRIGHT 1994-2002 *
+ * BY THE Xiph.Org FOUNDATION http://www.xiph.org/ *
+ * *
+ ********************************************************************
+
+ function: window lookup tables
+
+ ********************************************************************/
+
+
+#include "v_os_types.h"
+
+static LOOKUP_T vwin64[32] = {
+ X(0x001f0003), X(0x01168c98), X(0x030333c8), X(0x05dfe3a4),
+ X(0x09a49562), X(0x0e45df18), X(0x13b47ef2), X(0x19dcf676),
+ X(0x20a74d83), X(0x27f7137c), X(0x2fabb05a), X(0x37a1105a),
+ X(0x3fb0ab28), X(0x47b2dcd1), X(0x4f807bc6), X(0x56f48e70),
+ X(0x5dedfc79), X(0x64511653), X(0x6a08cfff), X(0x6f079328),
+ X(0x734796f4), X(0x76cab7f2), X(0x7999d6e8), X(0x7bc3cf9f),
+ X(0x7d5c20c1), X(0x7e7961df), X(0x7f33a567), X(0x7fa2e1d0),
+ X(0x7fdd78a5), X(0x7ff6ec6d), X(0x7ffed0e9), X(0x7ffffc3f),
+};
+
+static LOOKUP_T vwin128[64] = {
+ X(0x0007c04d), X(0x0045bb89), X(0x00c18b87), X(0x017ae294),
+ X(0x02714a4e), X(0x03a4217a), X(0x05129952), X(0x06bbb24f),
+ X(0x089e38a1), X(0x0ab8c073), X(0x0d09a228), X(0x0f8ef6bd),
+ X(0x12469488), X(0x152e0c7a), X(0x1842a81c), X(0x1b81686d),
+ X(0x1ee705d9), X(0x226ff15d), X(0x26185705), X(0x29dc21cc),
+ X(0x2db700fe), X(0x31a46f08), X(0x359fb9c1), X(0x39a40c0c),
+ X(0x3dac78b6), X(0x41b40674), X(0x45b5bcb0), X(0x49acb109),
+ X(0x4d94152b), X(0x516744bd), X(0x5521d320), X(0x58bf98a5),
+ X(0x5c3cbef4), X(0x5f95cc5d), X(0x62c7add7), X(0x65cfbf64),
+ X(0x68abd2ba), X(0x6b5a3405), X(0x6dd9acab), X(0x7029840d),
+ X(0x72497e38), X(0x7439d8ac), X(0x75fb4532), X(0x778ee30a),
+ X(0x78f6367e), X(0x7a331f1a), X(0x7b47cccd), X(0x7c36b416),
+ X(0x7d028192), X(0x7dae0d18), X(0x7e3c4caa), X(0x7eb04763),
+ X(0x7f0d08a7), X(0x7f5593b7), X(0x7f8cd7d5), X(0x7fb5a513),
+ X(0x7fd2a1fc), X(0x7fe64212), X(0x7ff2bd4c), X(0x7ffa0890),
+ X(0x7ffdcf39), X(0x7fff6dac), X(0x7fffed01), X(0x7fffffc4),
+};
+
+static LOOKUP_T vwin256[128] = {
+ X(0x0001f018), X(0x00117066), X(0x00306e9e), X(0x005ee5f1),
+ X(0x009ccf26), X(0x00ea208b), X(0x0146cdea), X(0x01b2c87f),
+ X(0x022dfedf), X(0x02b85ced), X(0x0351cbbd), X(0x03fa317f),
+ X(0x04b17167), X(0x05776b90), X(0x064bfcdc), X(0x072efedd),
+ X(0x082047b4), X(0x091fa9f1), X(0x0a2cf477), X(0x0b47f25d),
+ X(0x0c706ad2), X(0x0da620ff), X(0x0ee8d3ef), X(0x10383e75),
+ X(0x11941716), X(0x12fc0ff6), X(0x146fd6c8), X(0x15ef14c2),
+ X(0x17796e8e), X(0x190e844f), X(0x1aadf196), X(0x1c574d6e),
+ X(0x1e0a2a62), X(0x1fc61688), X(0x218a9b9c), X(0x23573f12),
+ X(0x252b823d), X(0x2706e269), X(0x28e8d913), X(0x2ad0dc0e),
+ X(0x2cbe5dc1), X(0x2eb0cd60), X(0x30a79733), X(0x32a224d5),
+ X(0x349fdd8b), X(0x36a02690), X(0x38a2636f), X(0x3aa5f65e),
+ X(0x3caa409e), X(0x3eaea2df), X(0x40b27da6), X(0x42b531b8),
+ X(0x44b62086), X(0x46b4ac99), X(0x48b03a05), X(0x4aa82ed5),
+ X(0x4c9bf37d), X(0x4e8af349), X(0x50749ccb), X(0x52586246),
+ X(0x5435ba1c), X(0x560c1f31), X(0x57db1152), X(0x59a21591),
+ X(0x5b60b6a3), X(0x5d168535), X(0x5ec31839), X(0x60660d36),
+ X(0x61ff0886), X(0x638db595), X(0x6511c717), X(0x668af734),
+ X(0x67f907b0), X(0x695bc207), X(0x6ab2f787), X(0x6bfe815a),
+ X(0x6d3e4090), X(0x6e721e16), X(0x6f9a0ab5), X(0x70b5fef8),
+ X(0x71c5fb16), X(0x72ca06cd), X(0x73c2313d), X(0x74ae90b2),
+ X(0x758f4275), X(0x76646a85), X(0x772e335c), X(0x77eccda0),
+ X(0x78a06fd7), X(0x79495613), X(0x79e7c19c), X(0x7a7bf894),
+ X(0x7b064596), X(0x7b86f757), X(0x7bfe6044), X(0x7c6cd615),
+ X(0x7cd2b16e), X(0x7d304d71), X(0x7d860756), X(0x7dd43e06),
+ X(0x7e1b51ad), X(0x7e5ba355), X(0x7e95947e), X(0x7ec986bb),
+ X(0x7ef7db4a), X(0x7f20f2b9), X(0x7f452c7f), X(0x7f64e6a7),
+ X(0x7f807d71), X(0x7f984aff), X(0x7faca700), X(0x7fbde662),
+ X(0x7fcc5b04), X(0x7fd85372), X(0x7fe21a99), X(0x7fe9f791),
+ X(0x7ff02d58), X(0x7ff4fa9e), X(0x7ff89990), X(0x7ffb3faa),
+ X(0x7ffd1d8b), X(0x7ffe5ecc), X(0x7fff29e0), X(0x7fff9ff3),
+ X(0x7fffdcd2), X(0x7ffff6d6), X(0x7ffffed0), X(0x7ffffffc),
+};
+
+static LOOKUP_T vwin512[256] = {
+ X(0x00007c06), X(0x00045c32), X(0x000c1c62), X(0x0017bc4c),
+ X(0x00273b7a), X(0x003a9955), X(0x0051d51c), X(0x006cede7),
+ X(0x008be2a9), X(0x00aeb22a), X(0x00d55b0d), X(0x00ffdbcc),
+ X(0x012e32b6), X(0x01605df5), X(0x01965b85), X(0x01d02939),
+ X(0x020dc4ba), X(0x024f2b83), X(0x02945ae6), X(0x02dd5004),
+ X(0x032a07d3), X(0x037a7f19), X(0x03ceb26e), X(0x04269e37),
+ X(0x04823eab), X(0x04e18fcc), X(0x05448d6d), X(0x05ab3329),
+ X(0x06157c68), X(0x0683645e), X(0x06f4e607), X(0x0769fc25),
+ X(0x07e2a146), X(0x085ecfbc), X(0x08de819f), X(0x0961b0cc),
+ X(0x09e856e3), X(0x0a726d46), X(0x0affed1d), X(0x0b90cf4c),
+ X(0x0c250c79), X(0x0cbc9d0b), X(0x0d577926), X(0x0df598aa),
+ X(0x0e96f337), X(0x0f3b8026), X(0x0fe3368f), X(0x108e0d42),
+ X(0x113bfaca), X(0x11ecf56b), X(0x12a0f324), X(0x1357e9ac),
+ X(0x1411ce70), X(0x14ce9698), X(0x158e3702), X(0x1650a444),
+ X(0x1715d2aa), X(0x17ddb638), X(0x18a842aa), X(0x19756b72),
+ X(0x1a4523b9), X(0x1b175e62), X(0x1bec0e04), X(0x1cc324f0),
+ X(0x1d9c9532), X(0x1e78508a), X(0x1f564876), X(0x20366e2e),
+ X(0x2118b2a2), X(0x21fd0681), X(0x22e35a37), X(0x23cb9dee),
+ X(0x24b5c18e), X(0x25a1b4c0), X(0x268f66f1), X(0x277ec74e),
+ X(0x286fc4cc), X(0x29624e23), X(0x2a5651d7), X(0x2b4bbe34),
+ X(0x2c428150), X(0x2d3a8913), X(0x2e33c332), X(0x2f2e1d35),
+ X(0x30298478), X(0x3125e62d), X(0x32232f61), X(0x33214cfc),
+ X(0x34202bc2), X(0x351fb85a), X(0x361fdf4f), X(0x37208d10),
+ X(0x3821adf7), X(0x39232e49), X(0x3a24fa3c), X(0x3b26fdf6),
+ X(0x3c292593), X(0x3d2b5d29), X(0x3e2d90c8), X(0x3f2fac7f),
+ X(0x40319c5f), X(0x41334c81), X(0x4234a905), X(0x43359e16),
+ X(0x443617f3), X(0x453602eb), X(0x46354b65), X(0x4733dde1),
+ X(0x4831a6ff), X(0x492e937f), X(0x4a2a9045), X(0x4b258a5f),
+ X(0x4c1f6f06), X(0x4d182ba2), X(0x4e0fadce), X(0x4f05e35b),
+ X(0x4ffaba53), X(0x50ee20fd), X(0x51e005e1), X(0x52d057ca),
+ X(0x53bf05ca), X(0x54abff3b), X(0x559733c7), X(0x56809365),
+ X(0x57680e62), X(0x584d955d), X(0x59311952), X(0x5a128b96),
+ X(0x5af1dddd), X(0x5bcf023a), X(0x5ca9eb27), X(0x5d828b81),
+ X(0x5e58d68d), X(0x5f2cbffc), X(0x5ffe3be9), X(0x60cd3edf),
+ X(0x6199bdda), X(0x6263ae45), X(0x632b0602), X(0x63efbb66),
+ X(0x64b1c53f), X(0x65711ad0), X(0x662db3d7), X(0x66e7888d),
+ X(0x679e91a5), X(0x6852c84e), X(0x69042635), X(0x69b2a582),
+ X(0x6a5e40dd), X(0x6b06f36c), X(0x6bacb8d2), X(0x6c4f8d30),
+ X(0x6cef6d26), X(0x6d8c55d4), X(0x6e2644d4), X(0x6ebd3840),
+ X(0x6f512ead), X(0x6fe2272e), X(0x7070214f), X(0x70fb1d17),
+ X(0x71831b06), X(0x72081c16), X(0x728a21b5), X(0x73092dc8),
+ X(0x738542a6), X(0x73fe631b), X(0x74749261), X(0x74e7d421),
+ X(0x75582c72), X(0x75c59fd5), X(0x76303333), X(0x7697ebdd),
+ X(0x76fccf85), X(0x775ee443), X(0x77be308a), X(0x781abb2e),
+ X(0x78748b59), X(0x78cba88e), X(0x79201aa7), X(0x7971e9cd),
+ X(0x79c11e79), X(0x7a0dc170), X(0x7a57dbc2), X(0x7a9f76c1),
+ X(0x7ae49c07), X(0x7b27556b), X(0x7b67ad02), X(0x7ba5ad1b),
+ X(0x7be1603a), X(0x7c1ad118), X(0x7c520a9e), X(0x7c8717e1),
+ X(0x7cba0421), X(0x7ceadac3), X(0x7d19a74f), X(0x7d46756e),
+ X(0x7d7150e5), X(0x7d9a4592), X(0x7dc15f69), X(0x7de6aa71),
+ X(0x7e0a32c0), X(0x7e2c0479), X(0x7e4c2bc7), X(0x7e6ab4db),
+ X(0x7e87abe9), X(0x7ea31d24), X(0x7ebd14be), X(0x7ed59edd),
+ X(0x7eecc7a3), X(0x7f029b21), X(0x7f17255a), X(0x7f2a723f),
+ X(0x7f3c8daa), X(0x7f4d835d), X(0x7f5d5f00), X(0x7f6c2c1b),
+ X(0x7f79f617), X(0x7f86c83a), X(0x7f92ada2), X(0x7f9db146),
+ X(0x7fa7ddf3), X(0x7fb13e46), X(0x7fb9dcb0), X(0x7fc1c36c),
+ X(0x7fc8fc83), X(0x7fcf91c7), X(0x7fd58cd2), X(0x7fdaf702),
+ X(0x7fdfd979), X(0x7fe43d1c), X(0x7fe82a8b), X(0x7febaa29),
+ X(0x7feec412), X(0x7ff1801c), X(0x7ff3e5d6), X(0x7ff5fc86),
+ X(0x7ff7cb29), X(0x7ff9586f), X(0x7ffaaaba), X(0x7ffbc81e),
+ X(0x7ffcb660), X(0x7ffd7af3), X(0x7ffe1afa), X(0x7ffe9b42),
+ X(0x7fff0047), X(0x7fff4e2f), X(0x7fff88c9), X(0x7fffb390),
+ X(0x7fffd1a6), X(0x7fffe5d7), X(0x7ffff296), X(0x7ffff9fd),
+ X(0x7ffffdcd), X(0x7fffff6d), X(0x7fffffed), X(0x7fffffff),
+};
+
+static LOOKUP_T vwin1024[512] = {
+ X(0x00001f02), X(0x0001170e), X(0x00030724), X(0x0005ef40),
+ X(0x0009cf59), X(0x000ea767), X(0x0014775e), X(0x001b3f2e),
+ X(0x0022fec8), X(0x002bb618), X(0x00356508), X(0x00400b81),
+ X(0x004ba968), X(0x00583ea0), X(0x0065cb0a), X(0x00744e84),
+ X(0x0083c8ea), X(0x00943a14), X(0x00a5a1da), X(0x00b80010),
+ X(0x00cb5488), X(0x00df9f10), X(0x00f4df76), X(0x010b1584),
+ X(0x01224101), X(0x013a61b2), X(0x01537759), X(0x016d81b6),
+ X(0x01888087), X(0x01a47385), X(0x01c15a69), X(0x01df34e6),
+ X(0x01fe02b1), X(0x021dc377), X(0x023e76e7), X(0x02601ca9),
+ X(0x0282b466), X(0x02a63dc1), X(0x02cab85d), X(0x02f023d6),
+ X(0x03167fcb), X(0x033dcbd3), X(0x03660783), X(0x038f3270),
+ X(0x03b94c29), X(0x03e4543a), X(0x04104a2e), X(0x043d2d8b),
+ X(0x046afdd5), X(0x0499ba8c), X(0x04c9632d), X(0x04f9f734),
+ X(0x052b7615), X(0x055ddf46), X(0x05913237), X(0x05c56e53),
+ X(0x05fa9306), X(0x06309fb6), X(0x066793c5), X(0x069f6e93),
+ X(0x06d82f7c), X(0x0711d5d9), X(0x074c60fe), X(0x0787d03d),
+ X(0x07c422e4), X(0x0801583e), X(0x083f6f91), X(0x087e681f),
+ X(0x08be4129), X(0x08fef9ea), X(0x0940919a), X(0x0983076d),
+ X(0x09c65a92), X(0x0a0a8a38), X(0x0a4f9585), X(0x0a957b9f),
+ X(0x0adc3ba7), X(0x0b23d4b9), X(0x0b6c45ee), X(0x0bb58e5a),
+ X(0x0bffad0f), X(0x0c4aa11a), X(0x0c966982), X(0x0ce3054d),
+ X(0x0d30737b), X(0x0d7eb308), X(0x0dcdc2eb), X(0x0e1da21a),
+ X(0x0e6e4f83), X(0x0ebfca11), X(0x0f1210ad), X(0x0f652238),
+ X(0x0fb8fd91), X(0x100da192), X(0x10630d11), X(0x10b93ee0),
+ X(0x111035cb), X(0x1167f09a), X(0x11c06e13), X(0x1219acf5),
+ X(0x1273abfb), X(0x12ce69db), X(0x1329e54a), X(0x13861cf3),
+ X(0x13e30f80), X(0x1440bb97), X(0x149f1fd8), X(0x14fe3ade),
+ X(0x155e0b40), X(0x15be8f92), X(0x161fc662), X(0x1681ae38),
+ X(0x16e4459b), X(0x17478b0b), X(0x17ab7d03), X(0x181019fb),
+ X(0x18756067), X(0x18db4eb3), X(0x1941e34a), X(0x19a91c92),
+ X(0x1a10f8ea), X(0x1a7976af), X(0x1ae29439), X(0x1b4c4fda),
+ X(0x1bb6a7e2), X(0x1c219a9a), X(0x1c8d2649), X(0x1cf9492e),
+ X(0x1d660188), X(0x1dd34d8e), X(0x1e412b74), X(0x1eaf996a),
+ X(0x1f1e959b), X(0x1f8e1e2f), X(0x1ffe3146), X(0x206ecd01),
+ X(0x20dfef78), X(0x215196c2), X(0x21c3c0f0), X(0x22366c10),
+ X(0x22a9962a), X(0x231d3d45), X(0x23915f60), X(0x2405fa7a),
+ X(0x247b0c8c), X(0x24f09389), X(0x25668d65), X(0x25dcf80c),
+ X(0x2653d167), X(0x26cb175e), X(0x2742c7d0), X(0x27bae09e),
+ X(0x28335fa2), X(0x28ac42b3), X(0x292587a5), X(0x299f2c48),
+ X(0x2a192e69), X(0x2a938bd1), X(0x2b0e4247), X(0x2b894f8d),
+ X(0x2c04b164), X(0x2c806588), X(0x2cfc69b2), X(0x2d78bb9a),
+ X(0x2df558f4), X(0x2e723f6f), X(0x2eef6cbb), X(0x2f6cde83),
+ X(0x2fea9270), X(0x30688627), X(0x30e6b74e), X(0x31652385),
+ X(0x31e3c86b), X(0x3262a39e), X(0x32e1b2b8), X(0x3360f352),
+ X(0x33e06303), X(0x345fff5e), X(0x34dfc5f8), X(0x355fb462),
+ X(0x35dfc82a), X(0x365ffee0), X(0x36e0560f), X(0x3760cb43),
+ X(0x37e15c05), X(0x386205df), X(0x38e2c657), X(0x39639af5),
+ X(0x39e4813e), X(0x3a6576b6), X(0x3ae678e3), X(0x3b678547),
+ X(0x3be89965), X(0x3c69b2c1), X(0x3ceacedc), X(0x3d6beb37),
+ X(0x3ded0557), X(0x3e6e1abb), X(0x3eef28e6), X(0x3f702d5a),
+ X(0x3ff1259a), X(0x40720f29), X(0x40f2e789), X(0x4173ac3f),
+ X(0x41f45ad0), X(0x4274f0c2), X(0x42f56b9a), X(0x4375c8e0),
+ X(0x43f6061d), X(0x447620db), X(0x44f616a5), X(0x4575e509),
+ X(0x45f58994), X(0x467501d6), X(0x46f44b62), X(0x477363cb),
+ X(0x47f248a6), X(0x4870f78e), X(0x48ef6e1a), X(0x496da9e8),
+ X(0x49eba897), X(0x4a6967c8), X(0x4ae6e521), X(0x4b641e47),
+ X(0x4be110e5), X(0x4c5dbaa7), X(0x4cda193f), X(0x4d562a5f),
+ X(0x4dd1ebbd), X(0x4e4d5b15), X(0x4ec87623), X(0x4f433aa9),
+ X(0x4fbda66c), X(0x5037b734), X(0x50b16acf), X(0x512abf0e),
+ X(0x51a3b1c5), X(0x521c40ce), X(0x52946a06), X(0x530c2b50),
+ X(0x53838292), X(0x53fa6db8), X(0x5470eab3), X(0x54e6f776),
+ X(0x555c91fc), X(0x55d1b844), X(0x56466851), X(0x56baa02f),
+ X(0x572e5deb), X(0x57a19f98), X(0x58146352), X(0x5886a737),
+ X(0x58f8696d), X(0x5969a81c), X(0x59da6177), X(0x5a4a93b4),
+ X(0x5aba3d0f), X(0x5b295bcb), X(0x5b97ee30), X(0x5c05f28d),
+ X(0x5c736738), X(0x5ce04a8d), X(0x5d4c9aed), X(0x5db856c1),
+ X(0x5e237c78), X(0x5e8e0a89), X(0x5ef7ff6f), X(0x5f6159b0),
+ X(0x5fca17d4), X(0x6032386e), X(0x6099ba15), X(0x61009b69),
+ X(0x6166db11), X(0x61cc77b9), X(0x62317017), X(0x6295c2e7),
+ X(0x62f96eec), X(0x635c72f1), X(0x63becdc8), X(0x64207e4b),
+ X(0x6481835a), X(0x64e1dbde), X(0x654186c8), X(0x65a0830e),
+ X(0x65fecfb1), X(0x665c6bb7), X(0x66b95630), X(0x67158e30),
+ X(0x677112d7), X(0x67cbe34b), X(0x6825feb9), X(0x687f6456),
+ X(0x68d81361), X(0x69300b1e), X(0x69874ada), X(0x69ddd1ea),
+ X(0x6a339fab), X(0x6a88b382), X(0x6add0cdb), X(0x6b30ab2a),
+ X(0x6b838dec), X(0x6bd5b4a6), X(0x6c271ee2), X(0x6c77cc36),
+ X(0x6cc7bc3d), X(0x6d16ee9b), X(0x6d6562fb), X(0x6db31911),
+ X(0x6e001099), X(0x6e4c4955), X(0x6e97c311), X(0x6ee27d9f),
+ X(0x6f2c78d9), X(0x6f75b4a2), X(0x6fbe30e4), X(0x7005ed91),
+ X(0x704ceaa1), X(0x70932816), X(0x70d8a5f8), X(0x711d6457),
+ X(0x7161634b), X(0x71a4a2f3), X(0x71e72375), X(0x7228e500),
+ X(0x7269e7c8), X(0x72aa2c0a), X(0x72e9b209), X(0x73287a12),
+ X(0x73668476), X(0x73a3d18f), X(0x73e061bc), X(0x741c3566),
+ X(0x74574cfa), X(0x7491a8ee), X(0x74cb49be), X(0x75042fec),
+ X(0x753c5c03), X(0x7573ce92), X(0x75aa882f), X(0x75e08979),
+ X(0x7615d313), X(0x764a65a7), X(0x767e41e5), X(0x76b16884),
+ X(0x76e3da40), X(0x771597dc), X(0x7746a221), X(0x7776f9dd),
+ X(0x77a69fe6), X(0x77d59514), X(0x7803da49), X(0x7831706a),
+ X(0x785e5861), X(0x788a9320), X(0x78b6219c), X(0x78e104cf),
+ X(0x790b3dbb), X(0x7934cd64), X(0x795db4d5), X(0x7985f51d),
+ X(0x79ad8f50), X(0x79d48486), X(0x79fad5de), X(0x7a208478),
+ X(0x7a45917b), X(0x7a69fe12), X(0x7a8dcb6c), X(0x7ab0fabb),
+ X(0x7ad38d36), X(0x7af5841a), X(0x7b16e0a3), X(0x7b37a416),
+ X(0x7b57cfb8), X(0x7b7764d4), X(0x7b9664b6), X(0x7bb4d0b0),
+ X(0x7bd2aa14), X(0x7beff23b), X(0x7c0caa7f), X(0x7c28d43c),
+ X(0x7c4470d2), X(0x7c5f81a5), X(0x7c7a081a), X(0x7c940598),
+ X(0x7cad7b8b), X(0x7cc66b5e), X(0x7cded680), X(0x7cf6be64),
+ X(0x7d0e247b), X(0x7d250a3c), X(0x7d3b711c), X(0x7d515a95),
+ X(0x7d66c822), X(0x7d7bbb3c), X(0x7d903563), X(0x7da43814),
+ X(0x7db7c4d0), X(0x7dcadd16), X(0x7ddd826a), X(0x7defb64d),
+ X(0x7e017a44), X(0x7e12cfd3), X(0x7e23b87f), X(0x7e3435cc),
+ X(0x7e444943), X(0x7e53f467), X(0x7e6338c0), X(0x7e7217d5),
+ X(0x7e80932b), X(0x7e8eac49), X(0x7e9c64b7), X(0x7ea9bdf8),
+ X(0x7eb6b994), X(0x7ec35910), X(0x7ecf9def), X(0x7edb89b6),
+ X(0x7ee71de9), X(0x7ef25c09), X(0x7efd4598), X(0x7f07dc16),
+ X(0x7f122103), X(0x7f1c15dc), X(0x7f25bc1f), X(0x7f2f1547),
+ X(0x7f3822cd), X(0x7f40e62b), X(0x7f4960d6), X(0x7f519443),
+ X(0x7f5981e7), X(0x7f612b31), X(0x7f689191), X(0x7f6fb674),
+ X(0x7f769b45), X(0x7f7d416c), X(0x7f83aa51), X(0x7f89d757),
+ X(0x7f8fc9df), X(0x7f958348), X(0x7f9b04ef), X(0x7fa0502e),
+ X(0x7fa56659), X(0x7faa48c7), X(0x7faef8c7), X(0x7fb377a7),
+ X(0x7fb7c6b3), X(0x7fbbe732), X(0x7fbfda67), X(0x7fc3a196),
+ X(0x7fc73dfa), X(0x7fcab0ce), X(0x7fcdfb4a), X(0x7fd11ea0),
+ X(0x7fd41c00), X(0x7fd6f496), X(0x7fd9a989), X(0x7fdc3bff),
+ X(0x7fdead17), X(0x7fe0fdee), X(0x7fe32f9d), X(0x7fe54337),
+ X(0x7fe739ce), X(0x7fe9146c), X(0x7fead41b), X(0x7fec79dd),
+ X(0x7fee06b2), X(0x7fef7b94), X(0x7ff0d97b), X(0x7ff22158),
+ X(0x7ff35417), X(0x7ff472a3), X(0x7ff57de0), X(0x7ff676ac),
+ X(0x7ff75de3), X(0x7ff8345a), X(0x7ff8fae4), X(0x7ff9b24b),
+ X(0x7ffa5b58), X(0x7ffaf6cd), X(0x7ffb8568), X(0x7ffc07e2),
+ X(0x7ffc7eed), X(0x7ffceb38), X(0x7ffd4d6d), X(0x7ffda631),
+ X(0x7ffdf621), X(0x7ffe3dd8), X(0x7ffe7dea), X(0x7ffeb6e7),
+ X(0x7ffee959), X(0x7fff15c4), X(0x7fff3ca9), X(0x7fff5e80),
+ X(0x7fff7bc0), X(0x7fff94d6), X(0x7fffaa2d), X(0x7fffbc29),
+ X(0x7fffcb29), X(0x7fffd786), X(0x7fffe195), X(0x7fffe9a3),
+ X(0x7fffeffa), X(0x7ffff4dd), X(0x7ffff889), X(0x7ffffb37),
+ X(0x7ffffd1a), X(0x7ffffe5d), X(0x7fffff29), X(0x7fffffa0),
+ X(0x7fffffdd), X(0x7ffffff7), X(0x7fffffff), X(0x7fffffff),
+};
+
+static LOOKUP_T vwin2048[1024] = {
+ X(0x000007c0), X(0x000045c4), X(0x0000c1ca), X(0x00017bd3),
+ X(0x000273de), X(0x0003a9eb), X(0x00051df9), X(0x0006d007),
+ X(0x0008c014), X(0x000aee1e), X(0x000d5a25), X(0x00100428),
+ X(0x0012ec23), X(0x00161216), X(0x001975fe), X(0x001d17da),
+ X(0x0020f7a8), X(0x00251564), X(0x0029710c), X(0x002e0a9e),
+ X(0x0032e217), X(0x0037f773), X(0x003d4ab0), X(0x0042dbca),
+ X(0x0048aabe), X(0x004eb788), X(0x00550224), X(0x005b8a8f),
+ X(0x006250c5), X(0x006954c1), X(0x0070967e), X(0x007815f9),
+ X(0x007fd32c), X(0x0087ce13), X(0x009006a9), X(0x00987ce9),
+ X(0x00a130cc), X(0x00aa224f), X(0x00b3516b), X(0x00bcbe1a),
+ X(0x00c66856), X(0x00d0501a), X(0x00da755f), X(0x00e4d81f),
+ X(0x00ef7853), X(0x00fa55f4), X(0x010570fc), X(0x0110c963),
+ X(0x011c5f22), X(0x01283232), X(0x0134428c), X(0x01409027),
+ X(0x014d1afb), X(0x0159e302), X(0x0166e831), X(0x01742a82),
+ X(0x0181a9ec), X(0x018f6665), X(0x019d5fe5), X(0x01ab9663),
+ X(0x01ba09d6), X(0x01c8ba34), X(0x01d7a775), X(0x01e6d18d),
+ X(0x01f63873), X(0x0205dc1e), X(0x0215bc82), X(0x0225d997),
+ X(0x02363350), X(0x0246c9a3), X(0x02579c86), X(0x0268abed),
+ X(0x0279f7cc), X(0x028b801a), X(0x029d44c9), X(0x02af45ce),
+ X(0x02c1831d), X(0x02d3fcaa), X(0x02e6b269), X(0x02f9a44c),
+ X(0x030cd248), X(0x03203c4f), X(0x0333e255), X(0x0347c44b),
+ X(0x035be225), X(0x03703bd5), X(0x0384d14d), X(0x0399a280),
+ X(0x03aeaf5e), X(0x03c3f7d9), X(0x03d97be4), X(0x03ef3b6e),
+ X(0x0405366a), X(0x041b6cc8), X(0x0431de78), X(0x04488b6c),
+ X(0x045f7393), X(0x047696dd), X(0x048df53b), X(0x04a58e9b),
+ X(0x04bd62ee), X(0x04d57223), X(0x04edbc28), X(0x050640ed),
+ X(0x051f0060), X(0x0537fa70), X(0x05512f0a), X(0x056a9e1e),
+ X(0x05844798), X(0x059e2b67), X(0x05b84978), X(0x05d2a1b8),
+ X(0x05ed3414), X(0x06080079), X(0x062306d3), X(0x063e470f),
+ X(0x0659c119), X(0x067574dd), X(0x06916247), X(0x06ad8941),
+ X(0x06c9e9b8), X(0x06e68397), X(0x070356c8), X(0x07206336),
+ X(0x073da8cb), X(0x075b2772), X(0x0778df15), X(0x0796cf9c),
+ X(0x07b4f8f3), X(0x07d35b01), X(0x07f1f5b1), X(0x0810c8eb),
+ X(0x082fd497), X(0x084f189e), X(0x086e94e9), X(0x088e495e),
+ X(0x08ae35e6), X(0x08ce5a68), X(0x08eeb6cc), X(0x090f4af8),
+ X(0x093016d3), X(0x09511a44), X(0x09725530), X(0x0993c77f),
+ X(0x09b57115), X(0x09d751d8), X(0x09f969ae), X(0x0a1bb87c),
+ X(0x0a3e3e26), X(0x0a60fa91), X(0x0a83eda2), X(0x0aa7173c),
+ X(0x0aca7743), X(0x0aee0d9b), X(0x0b11da28), X(0x0b35dccc),
+ X(0x0b5a156a), X(0x0b7e83e5), X(0x0ba3281f), X(0x0bc801fa),
+ X(0x0bed1159), X(0x0c12561c), X(0x0c37d025), X(0x0c5d7f55),
+ X(0x0c83638d), X(0x0ca97cae), X(0x0ccfca97), X(0x0cf64d2a),
+ X(0x0d1d0444), X(0x0d43efc7), X(0x0d6b0f92), X(0x0d926383),
+ X(0x0db9eb79), X(0x0de1a752), X(0x0e0996ee), X(0x0e31ba29),
+ X(0x0e5a10e2), X(0x0e829af6), X(0x0eab5841), X(0x0ed448a2),
+ X(0x0efd6bf4), X(0x0f26c214), X(0x0f504ade), X(0x0f7a062e),
+ X(0x0fa3f3df), X(0x0fce13cd), X(0x0ff865d2), X(0x1022e9ca),
+ X(0x104d9f8e), X(0x107886f9), X(0x10a39fe5), X(0x10ceea2c),
+ X(0x10fa65a6), X(0x1126122d), X(0x1151ef9a), X(0x117dfdc5),
+ X(0x11aa3c87), X(0x11d6abb6), X(0x12034b2c), X(0x12301ac0),
+ X(0x125d1a48), X(0x128a499b), X(0x12b7a891), X(0x12e536ff),
+ X(0x1312f4bb), X(0x1340e19c), X(0x136efd75), X(0x139d481e),
+ X(0x13cbc16a), X(0x13fa692f), X(0x14293f40), X(0x14584371),
+ X(0x14877597), X(0x14b6d585), X(0x14e6630d), X(0x15161e04),
+ X(0x1546063b), X(0x15761b85), X(0x15a65db3), X(0x15d6cc99),
+ X(0x16076806), X(0x16382fcd), X(0x166923bf), X(0x169a43ab),
+ X(0x16cb8f62), X(0x16fd06b5), X(0x172ea973), X(0x1760776b),
+ X(0x1792706e), X(0x17c49449), X(0x17f6e2cb), X(0x18295bc3),
+ X(0x185bfeff), X(0x188ecc4c), X(0x18c1c379), X(0x18f4e452),
+ X(0x19282ea4), X(0x195ba23c), X(0x198f3ee6), X(0x19c3046e),
+ X(0x19f6f2a1), X(0x1a2b094a), X(0x1a5f4833), X(0x1a93af28),
+ X(0x1ac83df3), X(0x1afcf460), X(0x1b31d237), X(0x1b66d744),
+ X(0x1b9c034e), X(0x1bd15621), X(0x1c06cf84), X(0x1c3c6f40),
+ X(0x1c72351e), X(0x1ca820e6), X(0x1cde3260), X(0x1d146953),
+ X(0x1d4ac587), X(0x1d8146c3), X(0x1db7eccd), X(0x1deeb76c),
+ X(0x1e25a667), X(0x1e5cb982), X(0x1e93f085), X(0x1ecb4b33),
+ X(0x1f02c953), X(0x1f3a6aaa), X(0x1f722efb), X(0x1faa160b),
+ X(0x1fe21f9e), X(0x201a4b79), X(0x2052995d), X(0x208b0910),
+ X(0x20c39a53), X(0x20fc4cea), X(0x21352097), X(0x216e151c),
+ X(0x21a72a3a), X(0x21e05fb5), X(0x2219b54d), X(0x22532ac3),
+ X(0x228cbfd8), X(0x22c6744d), X(0x230047e2), X(0x233a3a58),
+ X(0x23744b6d), X(0x23ae7ae3), X(0x23e8c878), X(0x242333ec),
+ X(0x245dbcfd), X(0x24986369), X(0x24d326f1), X(0x250e0750),
+ X(0x25490446), X(0x25841d90), X(0x25bf52ec), X(0x25faa417),
+ X(0x263610cd), X(0x267198cc), X(0x26ad3bcf), X(0x26e8f994),
+ X(0x2724d1d6), X(0x2760c451), X(0x279cd0c0), X(0x27d8f6e0),
+ X(0x2815366a), X(0x28518f1b), X(0x288e00ac), X(0x28ca8ad8),
+ X(0x29072d5a), X(0x2943e7eb), X(0x2980ba45), X(0x29bda422),
+ X(0x29faa53c), X(0x2a37bd4a), X(0x2a74ec07), X(0x2ab2312b),
+ X(0x2aef8c6f), X(0x2b2cfd8b), X(0x2b6a8437), X(0x2ba8202c),
+ X(0x2be5d120), X(0x2c2396cc), X(0x2c6170e7), X(0x2c9f5f29),
+ X(0x2cdd6147), X(0x2d1b76fa), X(0x2d599ff7), X(0x2d97dbf5),
+ X(0x2dd62aab), X(0x2e148bcf), X(0x2e52ff16), X(0x2e918436),
+ X(0x2ed01ae5), X(0x2f0ec2d9), X(0x2f4d7bc6), X(0x2f8c4562),
+ X(0x2fcb1f62), X(0x300a097a), X(0x3049035f), X(0x30880cc6),
+ X(0x30c72563), X(0x31064cea), X(0x3145830f), X(0x3184c786),
+ X(0x31c41a03), X(0x32037a39), X(0x3242e7dc), X(0x3282629f),
+ X(0x32c1ea36), X(0x33017e53), X(0x33411ea9), X(0x3380caec),
+ X(0x33c082ce), X(0x34004602), X(0x34401439), X(0x347fed27),
+ X(0x34bfd07e), X(0x34ffbdf0), X(0x353fb52e), X(0x357fb5ec),
+ X(0x35bfbfda), X(0x35ffd2aa), X(0x363fee0f), X(0x368011b9),
+ X(0x36c03d5a), X(0x370070a4), X(0x3740ab48), X(0x3780ecf7),
+ X(0x37c13562), X(0x3801843a), X(0x3841d931), X(0x388233f7),
+ X(0x38c2943d), X(0x3902f9b4), X(0x3943640d), X(0x3983d2f8),
+ X(0x39c44626), X(0x3a04bd48), X(0x3a45380e), X(0x3a85b62a),
+ X(0x3ac6374a), X(0x3b06bb20), X(0x3b47415c), X(0x3b87c9ae),
+ X(0x3bc853c7), X(0x3c08df57), X(0x3c496c0f), X(0x3c89f99f),
+ X(0x3cca87b6), X(0x3d0b1605), X(0x3d4ba43d), X(0x3d8c320e),
+ X(0x3dccbf27), X(0x3e0d4b3a), X(0x3e4dd5f6), X(0x3e8e5f0c),
+ X(0x3ecee62b), X(0x3f0f6b05), X(0x3f4fed49), X(0x3f906ca8),
+ X(0x3fd0e8d2), X(0x40116177), X(0x4051d648), X(0x409246f6),
+ X(0x40d2b330), X(0x41131aa7), X(0x41537d0c), X(0x4193da10),
+ X(0x41d43162), X(0x421482b4), X(0x4254cdb7), X(0x4295121b),
+ X(0x42d54f91), X(0x431585ca), X(0x4355b477), X(0x4395db49),
+ X(0x43d5f9f1), X(0x44161021), X(0x44561d8a), X(0x449621dd),
+ X(0x44d61ccc), X(0x45160e08), X(0x4555f544), X(0x4595d230),
+ X(0x45d5a47f), X(0x46156be3), X(0x4655280e), X(0x4694d8b2),
+ X(0x46d47d82), X(0x4714162f), X(0x4753a26d), X(0x479321ef),
+ X(0x47d29466), X(0x4811f987), X(0x48515104), X(0x48909a91),
+ X(0x48cfd5e1), X(0x490f02a7), X(0x494e2098), X(0x498d2f66),
+ X(0x49cc2ec7), X(0x4a0b1e6f), X(0x4a49fe11), X(0x4a88cd62),
+ X(0x4ac78c18), X(0x4b0639e6), X(0x4b44d683), X(0x4b8361a2),
+ X(0x4bc1dafa), X(0x4c004241), X(0x4c3e972c), X(0x4c7cd970),
+ X(0x4cbb08c5), X(0x4cf924e1), X(0x4d372d7a), X(0x4d752247),
+ X(0x4db30300), X(0x4df0cf5a), X(0x4e2e870f), X(0x4e6c29d6),
+ X(0x4ea9b766), X(0x4ee72f78), X(0x4f2491c4), X(0x4f61de02),
+ X(0x4f9f13ec), X(0x4fdc333b), X(0x50193ba8), X(0x50562ced),
+ X(0x509306c3), X(0x50cfc8e5), X(0x510c730d), X(0x514904f6),
+ X(0x51857e5a), X(0x51c1def5), X(0x51fe2682), X(0x523a54bc),
+ X(0x52766961), X(0x52b2642c), X(0x52ee44d9), X(0x532a0b26),
+ X(0x5365b6d0), X(0x53a14793), X(0x53dcbd2f), X(0x54181760),
+ X(0x545355e5), X(0x548e787d), X(0x54c97ee6), X(0x550468e1),
+ X(0x553f362c), X(0x5579e687), X(0x55b479b3), X(0x55eeef70),
+ X(0x5629477f), X(0x566381a1), X(0x569d9d97), X(0x56d79b24),
+ X(0x57117a0a), X(0x574b3a0a), X(0x5784dae9), X(0x57be5c69),
+ X(0x57f7be4d), X(0x5831005a), X(0x586a2254), X(0x58a32400),
+ X(0x58dc0522), X(0x5914c57f), X(0x594d64de), X(0x5985e305),
+ X(0x59be3fba), X(0x59f67ac3), X(0x5a2e93e9), X(0x5a668af2),
+ X(0x5a9e5fa6), X(0x5ad611ce), X(0x5b0da133), X(0x5b450d9d),
+ X(0x5b7c56d7), X(0x5bb37ca9), X(0x5bea7ede), X(0x5c215d41),
+ X(0x5c58179d), X(0x5c8eadbe), X(0x5cc51f6f), X(0x5cfb6c7c),
+ X(0x5d3194b2), X(0x5d6797de), X(0x5d9d75cf), X(0x5dd32e51),
+ X(0x5e08c132), X(0x5e3e2e43), X(0x5e737551), X(0x5ea8962d),
+ X(0x5edd90a7), X(0x5f12648e), X(0x5f4711b4), X(0x5f7b97ea),
+ X(0x5faff702), X(0x5fe42ece), X(0x60183f20), X(0x604c27cc),
+ X(0x607fe8a6), X(0x60b38180), X(0x60e6f22f), X(0x611a3a89),
+ X(0x614d5a62), X(0x61805190), X(0x61b31fe9), X(0x61e5c545),
+ X(0x62184179), X(0x624a945d), X(0x627cbdca), X(0x62aebd98),
+ X(0x62e0939f), X(0x63123fba), X(0x6343c1c1), X(0x6375198f),
+ X(0x63a646ff), X(0x63d749ec), X(0x64082232), X(0x6438cfad),
+ X(0x64695238), X(0x6499a9b3), X(0x64c9d5f9), X(0x64f9d6ea),
+ X(0x6529ac63), X(0x65595643), X(0x6588d46a), X(0x65b826b8),
+ X(0x65e74d0e), X(0x6616474b), X(0x66451552), X(0x6673b704),
+ X(0x66a22c44), X(0x66d074f4), X(0x66fe90f8), X(0x672c8033),
+ X(0x675a428a), X(0x6787d7e1), X(0x67b5401f), X(0x67e27b27),
+ X(0x680f88e1), X(0x683c6934), X(0x68691c05), X(0x6895a13e),
+ X(0x68c1f8c7), X(0x68ee2287), X(0x691a1e68), X(0x6945ec54),
+ X(0x69718c35), X(0x699cfdf5), X(0x69c8417f), X(0x69f356c0),
+ X(0x6a1e3da3), X(0x6a48f615), X(0x6a738002), X(0x6a9ddb5a),
+ X(0x6ac80808), X(0x6af205fd), X(0x6b1bd526), X(0x6b457575),
+ X(0x6b6ee6d8), X(0x6b982940), X(0x6bc13c9f), X(0x6bea20e5),
+ X(0x6c12d605), X(0x6c3b5bf1), X(0x6c63b29c), X(0x6c8bd9fb),
+ X(0x6cb3d200), X(0x6cdb9aa0), X(0x6d0333d0), X(0x6d2a9d86),
+ X(0x6d51d7b7), X(0x6d78e25a), X(0x6d9fbd67), X(0x6dc668d3),
+ X(0x6dece498), X(0x6e1330ad), X(0x6e394d0c), X(0x6e5f39ae),
+ X(0x6e84f68d), X(0x6eaa83a2), X(0x6ecfe0ea), X(0x6ef50e5e),
+ X(0x6f1a0bfc), X(0x6f3ed9bf), X(0x6f6377a4), X(0x6f87e5a8),
+ X(0x6fac23c9), X(0x6fd03206), X(0x6ff4105c), X(0x7017becc),
+ X(0x703b3d54), X(0x705e8bf5), X(0x7081aaaf), X(0x70a49984),
+ X(0x70c75874), X(0x70e9e783), X(0x710c46b2), X(0x712e7605),
+ X(0x7150757f), X(0x71724523), X(0x7193e4f6), X(0x71b554fd),
+ X(0x71d6953e), X(0x71f7a5bd), X(0x72188681), X(0x72393792),
+ X(0x7259b8f5), X(0x727a0ab2), X(0x729a2cd2), X(0x72ba1f5d),
+ X(0x72d9e25c), X(0x72f975d8), X(0x7318d9db), X(0x73380e6f),
+ X(0x735713a0), X(0x7375e978), X(0x73949003), X(0x73b3074c),
+ X(0x73d14f61), X(0x73ef684f), X(0x740d5222), X(0x742b0ce9),
+ X(0x744898b1), X(0x7465f589), X(0x74832381), X(0x74a022a8),
+ X(0x74bcf30e), X(0x74d994c3), X(0x74f607d8), X(0x75124c5f),
+ X(0x752e6268), X(0x754a4a05), X(0x7566034b), X(0x75818e4a),
+ X(0x759ceb16), X(0x75b819c4), X(0x75d31a66), X(0x75eded12),
+ X(0x760891dc), X(0x762308da), X(0x763d5221), X(0x76576dc8),
+ X(0x76715be4), X(0x768b1c8c), X(0x76a4afd9), X(0x76be15e0),
+ X(0x76d74ebb), X(0x76f05a82), X(0x7709394d), X(0x7721eb35),
+ X(0x773a7054), X(0x7752c8c4), X(0x776af49f), X(0x7782f400),
+ X(0x779ac701), X(0x77b26dbd), X(0x77c9e851), X(0x77e136d8),
+ X(0x77f8596f), X(0x780f5032), X(0x78261b3f), X(0x783cbab2),
+ X(0x78532eaa), X(0x78697745), X(0x787f94a0), X(0x789586db),
+ X(0x78ab4e15), X(0x78c0ea6d), X(0x78d65c03), X(0x78eba2f7),
+ X(0x7900bf68), X(0x7915b179), X(0x792a7949), X(0x793f16fb),
+ X(0x79538aaf), X(0x7967d488), X(0x797bf4a8), X(0x798feb31),
+ X(0x79a3b846), X(0x79b75c0a), X(0x79cad6a1), X(0x79de282e),
+ X(0x79f150d5), X(0x7a0450bb), X(0x7a172803), X(0x7a29d6d3),
+ X(0x7a3c5d50), X(0x7a4ebb9f), X(0x7a60f1e6), X(0x7a73004a),
+ X(0x7a84e6f2), X(0x7a96a604), X(0x7aa83da7), X(0x7ab9ae01),
+ X(0x7acaf73a), X(0x7adc1979), X(0x7aed14e6), X(0x7afde9a8),
+ X(0x7b0e97e8), X(0x7b1f1fcd), X(0x7b2f8182), X(0x7b3fbd2d),
+ X(0x7b4fd2f9), X(0x7b5fc30f), X(0x7b6f8d98), X(0x7b7f32bd),
+ X(0x7b8eb2a9), X(0x7b9e0d85), X(0x7bad437d), X(0x7bbc54b9),
+ X(0x7bcb4166), X(0x7bda09ae), X(0x7be8adbc), X(0x7bf72dbc),
+ X(0x7c0589d8), X(0x7c13c23d), X(0x7c21d716), X(0x7c2fc88f),
+ X(0x7c3d96d5), X(0x7c4b4214), X(0x7c58ca78), X(0x7c66302d),
+ X(0x7c737362), X(0x7c809443), X(0x7c8d92fc), X(0x7c9a6fbc),
+ X(0x7ca72aaf), X(0x7cb3c404), X(0x7cc03be8), X(0x7ccc9288),
+ X(0x7cd8c814), X(0x7ce4dcb9), X(0x7cf0d0a5), X(0x7cfca406),
+ X(0x7d08570c), X(0x7d13e9e5), X(0x7d1f5cbf), X(0x7d2aafca),
+ X(0x7d35e335), X(0x7d40f72e), X(0x7d4bebe4), X(0x7d56c188),
+ X(0x7d617848), X(0x7d6c1054), X(0x7d7689db), X(0x7d80e50e),
+ X(0x7d8b221b), X(0x7d954133), X(0x7d9f4286), X(0x7da92643),
+ X(0x7db2ec9b), X(0x7dbc95bd), X(0x7dc621da), X(0x7dcf9123),
+ X(0x7dd8e3c6), X(0x7de219f6), X(0x7deb33e2), X(0x7df431ba),
+ X(0x7dfd13af), X(0x7e05d9f2), X(0x7e0e84b4), X(0x7e171424),
+ X(0x7e1f8874), X(0x7e27e1d4), X(0x7e302074), X(0x7e384487),
+ X(0x7e404e3c), X(0x7e483dc4), X(0x7e501350), X(0x7e57cf11),
+ X(0x7e5f7138), X(0x7e66f9f4), X(0x7e6e6979), X(0x7e75bff5),
+ X(0x7e7cfd9a), X(0x7e842298), X(0x7e8b2f22), X(0x7e922366),
+ X(0x7e98ff97), X(0x7e9fc3e4), X(0x7ea6707f), X(0x7ead0598),
+ X(0x7eb38360), X(0x7eb9ea07), X(0x7ec039bf), X(0x7ec672b7),
+ X(0x7ecc9521), X(0x7ed2a12c), X(0x7ed8970a), X(0x7ede76ea),
+ X(0x7ee440fd), X(0x7ee9f573), X(0x7eef947d), X(0x7ef51e4b),
+ X(0x7efa930d), X(0x7efff2f2), X(0x7f053e2b), X(0x7f0a74e8),
+ X(0x7f0f9758), X(0x7f14a5ac), X(0x7f19a013), X(0x7f1e86bc),
+ X(0x7f2359d8), X(0x7f281995), X(0x7f2cc623), X(0x7f315fb1),
+ X(0x7f35e66e), X(0x7f3a5a8a), X(0x7f3ebc33), X(0x7f430b98),
+ X(0x7f4748e7), X(0x7f4b7450), X(0x7f4f8e01), X(0x7f539629),
+ X(0x7f578cf5), X(0x7f5b7293), X(0x7f5f4732), X(0x7f630b00),
+ X(0x7f66be2b), X(0x7f6a60df), X(0x7f6df34b), X(0x7f71759b),
+ X(0x7f74e7fe), X(0x7f784aa0), X(0x7f7b9daf), X(0x7f7ee156),
+ X(0x7f8215c3), X(0x7f853b22), X(0x7f88519f), X(0x7f8b5967),
+ X(0x7f8e52a6), X(0x7f913d87), X(0x7f941a36), X(0x7f96e8df),
+ X(0x7f99a9ad), X(0x7f9c5ccb), X(0x7f9f0265), X(0x7fa19aa5),
+ X(0x7fa425b5), X(0x7fa6a3c1), X(0x7fa914f3), X(0x7fab7974),
+ X(0x7fadd16f), X(0x7fb01d0d), X(0x7fb25c78), X(0x7fb48fd9),
+ X(0x7fb6b75a), X(0x7fb8d323), X(0x7fbae35d), X(0x7fbce831),
+ X(0x7fbee1c7), X(0x7fc0d047), X(0x7fc2b3d9), X(0x7fc48ca5),
+ X(0x7fc65ad3), X(0x7fc81e88), X(0x7fc9d7ee), X(0x7fcb872a),
+ X(0x7fcd2c63), X(0x7fcec7bf), X(0x7fd05966), X(0x7fd1e17c),
+ X(0x7fd36027), X(0x7fd4d58d), X(0x7fd641d3), X(0x7fd7a51e),
+ X(0x7fd8ff94), X(0x7fda5157), X(0x7fdb9a8e), X(0x7fdcdb5b),
+ X(0x7fde13e2), X(0x7fdf4448), X(0x7fe06caf), X(0x7fe18d3b),
+ X(0x7fe2a60e), X(0x7fe3b74b), X(0x7fe4c114), X(0x7fe5c38b),
+ X(0x7fe6bed2), X(0x7fe7b30a), X(0x7fe8a055), X(0x7fe986d4),
+ X(0x7fea66a7), X(0x7feb3ff0), X(0x7fec12cd), X(0x7fecdf5f),
+ X(0x7feda5c5), X(0x7fee6620), X(0x7fef208d), X(0x7fefd52c),
+ X(0x7ff0841c), X(0x7ff12d7a), X(0x7ff1d164), X(0x7ff26ff9),
+ X(0x7ff30955), X(0x7ff39d96), X(0x7ff42cd9), X(0x7ff4b739),
+ X(0x7ff53cd4), X(0x7ff5bdc5), X(0x7ff63a28), X(0x7ff6b217),
+ X(0x7ff725af), X(0x7ff7950a), X(0x7ff80043), X(0x7ff86773),
+ X(0x7ff8cab4), X(0x7ff92a21), X(0x7ff985d1), X(0x7ff9dddf),
+ X(0x7ffa3262), X(0x7ffa8374), X(0x7ffad12c), X(0x7ffb1ba1),
+ X(0x7ffb62ec), X(0x7ffba723), X(0x7ffbe85c), X(0x7ffc26b0),
+ X(0x7ffc6233), X(0x7ffc9afb), X(0x7ffcd11e), X(0x7ffd04b1),
+ X(0x7ffd35c9), X(0x7ffd647b), X(0x7ffd90da), X(0x7ffdbafa),
+ X(0x7ffde2f0), X(0x7ffe08ce), X(0x7ffe2ca7), X(0x7ffe4e8e),
+ X(0x7ffe6e95), X(0x7ffe8cce), X(0x7ffea94a), X(0x7ffec41b),
+ X(0x7ffedd52), X(0x7ffef4ff), X(0x7fff0b33), X(0x7fff1ffd),
+ X(0x7fff336e), X(0x7fff4593), X(0x7fff567d), X(0x7fff663a),
+ X(0x7fff74d8), X(0x7fff8265), X(0x7fff8eee), X(0x7fff9a81),
+ X(0x7fffa52b), X(0x7fffaef8), X(0x7fffb7f5), X(0x7fffc02d),
+ X(0x7fffc7ab), X(0x7fffce7c), X(0x7fffd4a9), X(0x7fffda3e),
+ X(0x7fffdf44), X(0x7fffe3c6), X(0x7fffe7cc), X(0x7fffeb60),
+ X(0x7fffee8a), X(0x7ffff153), X(0x7ffff3c4), X(0x7ffff5e3),
+ X(0x7ffff7b8), X(0x7ffff94b), X(0x7ffffaa1), X(0x7ffffbc1),
+ X(0x7ffffcb2), X(0x7ffffd78), X(0x7ffffe19), X(0x7ffffe9a),
+ X(0x7ffffeff), X(0x7fffff4e), X(0x7fffff89), X(0x7fffffb3),
+ X(0x7fffffd2), X(0x7fffffe6), X(0x7ffffff3), X(0x7ffffffa),
+ X(0x7ffffffe), X(0x7fffffff), X(0x7fffffff), X(0x7fffffff),
+};
+
+static LOOKUP_T vwin4096[2048] = {
+ X(0x000001f0), X(0x00001171), X(0x00003072), X(0x00005ef5),
+ X(0x00009cf8), X(0x0000ea7c), X(0x00014780), X(0x0001b405),
+ X(0x0002300b), X(0x0002bb91), X(0x00035698), X(0x0004011e),
+ X(0x0004bb25), X(0x000584ac), X(0x00065db3), X(0x0007463a),
+ X(0x00083e41), X(0x000945c7), X(0x000a5ccc), X(0x000b8350),
+ X(0x000cb954), X(0x000dfed7), X(0x000f53d8), X(0x0010b857),
+ X(0x00122c55), X(0x0013afd1), X(0x001542ca), X(0x0016e541),
+ X(0x00189735), X(0x001a58a7), X(0x001c2995), X(0x001e09ff),
+ X(0x001ff9e6), X(0x0021f948), X(0x00240826), X(0x00262680),
+ X(0x00285454), X(0x002a91a3), X(0x002cde6c), X(0x002f3aaf),
+ X(0x0031a66b), X(0x003421a0), X(0x0036ac4f), X(0x00394675),
+ X(0x003bf014), X(0x003ea92a), X(0x004171b7), X(0x004449bb),
+ X(0x00473135), X(0x004a2824), X(0x004d2e8a), X(0x00504463),
+ X(0x005369b2), X(0x00569e74), X(0x0059e2aa), X(0x005d3652),
+ X(0x0060996d), X(0x00640bf9), X(0x00678df7), X(0x006b1f66),
+ X(0x006ec045), X(0x00727093), X(0x00763051), X(0x0079ff7d),
+ X(0x007dde16), X(0x0081cc1d), X(0x0085c991), X(0x0089d671),
+ X(0x008df2bc), X(0x00921e71), X(0x00965991), X(0x009aa41a),
+ X(0x009efe0c), X(0x00a36766), X(0x00a7e028), X(0x00ac6850),
+ X(0x00b0ffde), X(0x00b5a6d1), X(0x00ba5d28), X(0x00bf22e4),
+ X(0x00c3f802), X(0x00c8dc83), X(0x00cdd065), X(0x00d2d3a8),
+ X(0x00d7e64a), X(0x00dd084c), X(0x00e239ac), X(0x00e77a69),
+ X(0x00ecca83), X(0x00f229f9), X(0x00f798ca), X(0x00fd16f5),
+ X(0x0102a479), X(0x01084155), X(0x010ded89), X(0x0113a913),
+ X(0x011973f3), X(0x011f4e27), X(0x012537af), X(0x012b308a),
+ X(0x013138b7), X(0x01375035), X(0x013d7702), X(0x0143ad1f),
+ X(0x0149f289), X(0x01504741), X(0x0156ab44), X(0x015d1e92),
+ X(0x0163a12a), X(0x016a330b), X(0x0170d433), X(0x017784a3),
+ X(0x017e4458), X(0x01851351), X(0x018bf18e), X(0x0192df0d),
+ X(0x0199dbcd), X(0x01a0e7cd), X(0x01a8030c), X(0x01af2d89),
+ X(0x01b66743), X(0x01bdb038), X(0x01c50867), X(0x01cc6fd0),
+ X(0x01d3e670), X(0x01db6c47), X(0x01e30153), X(0x01eaa593),
+ X(0x01f25907), X(0x01fa1bac), X(0x0201ed81), X(0x0209ce86),
+ X(0x0211beb8), X(0x0219be17), X(0x0221cca2), X(0x0229ea56),
+ X(0x02321733), X(0x023a5337), X(0x02429e60), X(0x024af8af),
+ X(0x02536220), X(0x025bdab3), X(0x02646267), X(0x026cf93a),
+ X(0x02759f2a), X(0x027e5436), X(0x0287185d), X(0x028feb9d),
+ X(0x0298cdf4), X(0x02a1bf62), X(0x02aabfe5), X(0x02b3cf7b),
+ X(0x02bcee23), X(0x02c61bdb), X(0x02cf58a2), X(0x02d8a475),
+ X(0x02e1ff55), X(0x02eb693e), X(0x02f4e230), X(0x02fe6a29),
+ X(0x03080127), X(0x0311a729), X(0x031b5c2d), X(0x03252031),
+ X(0x032ef334), X(0x0338d534), X(0x0342c630), X(0x034cc625),
+ X(0x0356d512), X(0x0360f2f6), X(0x036b1fce), X(0x03755b99),
+ X(0x037fa655), X(0x038a0001), X(0x0394689a), X(0x039ee020),
+ X(0x03a9668f), X(0x03b3fbe6), X(0x03bea024), X(0x03c95347),
+ X(0x03d4154d), X(0x03dee633), X(0x03e9c5f9), X(0x03f4b49b),
+ X(0x03ffb219), X(0x040abe71), X(0x0415d9a0), X(0x042103a5),
+ X(0x042c3c7d), X(0x04378428), X(0x0442daa2), X(0x044e3fea),
+ X(0x0459b3fd), X(0x046536db), X(0x0470c880), X(0x047c68eb),
+ X(0x0488181a), X(0x0493d60b), X(0x049fa2bc), X(0x04ab7e2a),
+ X(0x04b76854), X(0x04c36137), X(0x04cf68d1), X(0x04db7f21),
+ X(0x04e7a424), X(0x04f3d7d8), X(0x05001a3b), X(0x050c6b4a),
+ X(0x0518cb04), X(0x05253966), X(0x0531b66e), X(0x053e421a),
+ X(0x054adc68), X(0x05578555), X(0x05643cdf), X(0x05710304),
+ X(0x057dd7c1), X(0x058abb15), X(0x0597acfd), X(0x05a4ad76),
+ X(0x05b1bc7f), X(0x05beda14), X(0x05cc0635), X(0x05d940dd),
+ X(0x05e68a0b), X(0x05f3e1bd), X(0x060147f0), X(0x060ebca1),
+ X(0x061c3fcf), X(0x0629d176), X(0x06377194), X(0x06452027),
+ X(0x0652dd2c), X(0x0660a8a2), X(0x066e8284), X(0x067c6ad1),
+ X(0x068a6186), X(0x069866a1), X(0x06a67a1e), X(0x06b49bfc),
+ X(0x06c2cc38), X(0x06d10acf), X(0x06df57bf), X(0x06edb304),
+ X(0x06fc1c9d), X(0x070a9487), X(0x07191abe), X(0x0727af40),
+ X(0x0736520b), X(0x0745031c), X(0x0753c270), X(0x07629004),
+ X(0x07716bd6), X(0x078055e2), X(0x078f4e26), X(0x079e549f),
+ X(0x07ad694b), X(0x07bc8c26), X(0x07cbbd2e), X(0x07dafc5f),
+ X(0x07ea49b7), X(0x07f9a533), X(0x08090ed1), X(0x0818868c),
+ X(0x08280c62), X(0x0837a051), X(0x08474255), X(0x0856f26b),
+ X(0x0866b091), X(0x08767cc3), X(0x088656fe), X(0x08963f3f),
+ X(0x08a63584), X(0x08b639c8), X(0x08c64c0a), X(0x08d66c45),
+ X(0x08e69a77), X(0x08f6d69d), X(0x090720b3), X(0x091778b7),
+ X(0x0927dea5), X(0x0938527a), X(0x0948d433), X(0x095963cc),
+ X(0x096a0143), X(0x097aac94), X(0x098b65bb), X(0x099c2cb6),
+ X(0x09ad0182), X(0x09bde41a), X(0x09ced47d), X(0x09dfd2a5),
+ X(0x09f0de90), X(0x0a01f83b), X(0x0a131fa3), X(0x0a2454c3),
+ X(0x0a359798), X(0x0a46e820), X(0x0a584656), X(0x0a69b237),
+ X(0x0a7b2bc0), X(0x0a8cb2ec), X(0x0a9e47ba), X(0x0aafea24),
+ X(0x0ac19a29), X(0x0ad357c3), X(0x0ae522ef), X(0x0af6fbab),
+ X(0x0b08e1f1), X(0x0b1ad5c0), X(0x0b2cd712), X(0x0b3ee5e5),
+ X(0x0b510234), X(0x0b632bfd), X(0x0b75633b), X(0x0b87a7eb),
+ X(0x0b99fa08), X(0x0bac5990), X(0x0bbec67e), X(0x0bd140cf),
+ X(0x0be3c87e), X(0x0bf65d89), X(0x0c08ffeb), X(0x0c1bafa1),
+ X(0x0c2e6ca6), X(0x0c4136f6), X(0x0c540e8f), X(0x0c66f36c),
+ X(0x0c79e588), X(0x0c8ce4e1), X(0x0c9ff172), X(0x0cb30b37),
+ X(0x0cc6322c), X(0x0cd9664d), X(0x0ceca797), X(0x0cfff605),
+ X(0x0d135193), X(0x0d26ba3d), X(0x0d3a2fff), X(0x0d4db2d5),
+ X(0x0d6142ba), X(0x0d74dfac), X(0x0d8889a5), X(0x0d9c40a1),
+ X(0x0db0049d), X(0x0dc3d593), X(0x0dd7b380), X(0x0deb9e60),
+ X(0x0dff962f), X(0x0e139ae7), X(0x0e27ac85), X(0x0e3bcb05),
+ X(0x0e4ff662), X(0x0e642e98), X(0x0e7873a2), X(0x0e8cc57d),
+ X(0x0ea12423), X(0x0eb58f91), X(0x0eca07c2), X(0x0ede8cb1),
+ X(0x0ef31e5b), X(0x0f07bcba), X(0x0f1c67cb), X(0x0f311f88),
+ X(0x0f45e3ee), X(0x0f5ab4f7), X(0x0f6f92a0), X(0x0f847ce3),
+ X(0x0f9973bc), X(0x0fae7726), X(0x0fc3871e), X(0x0fd8a39d),
+ X(0x0fedcca1), X(0x10030223), X(0x1018441f), X(0x102d9291),
+ X(0x1042ed74), X(0x105854c3), X(0x106dc879), X(0x10834892),
+ X(0x1098d508), X(0x10ae6dd8), X(0x10c412fc), X(0x10d9c46f),
+ X(0x10ef822d), X(0x11054c30), X(0x111b2274), X(0x113104f5),
+ X(0x1146f3ac), X(0x115cee95), X(0x1172f5ab), X(0x118908e9),
+ X(0x119f284a), X(0x11b553ca), X(0x11cb8b62), X(0x11e1cf0f),
+ X(0x11f81ecb), X(0x120e7a90), X(0x1224e25a), X(0x123b5624),
+ X(0x1251d5e9), X(0x126861a3), X(0x127ef94e), X(0x12959ce3),
+ X(0x12ac4c5f), X(0x12c307bb), X(0x12d9cef2), X(0x12f0a200),
+ X(0x130780df), X(0x131e6b8a), X(0x133561fa), X(0x134c642c),
+ X(0x1363721a), X(0x137a8bbe), X(0x1391b113), X(0x13a8e214),
+ X(0x13c01eba), X(0x13d76702), X(0x13eebae5), X(0x14061a5e),
+ X(0x141d8567), X(0x1434fbfb), X(0x144c7e14), X(0x14640bae),
+ X(0x147ba4c1), X(0x14934949), X(0x14aaf941), X(0x14c2b4a2),
+ X(0x14da7b67), X(0x14f24d8a), X(0x150a2b06), X(0x152213d5),
+ X(0x153a07f1), X(0x15520755), X(0x156a11fb), X(0x158227dd),
+ X(0x159a48f5), X(0x15b2753d), X(0x15caacb1), X(0x15e2ef49),
+ X(0x15fb3d01), X(0x161395d2), X(0x162bf9b6), X(0x164468a8),
+ X(0x165ce2a1), X(0x1675679c), X(0x168df793), X(0x16a69280),
+ X(0x16bf385c), X(0x16d7e922), X(0x16f0a4cc), X(0x17096b54),
+ X(0x17223cb4), X(0x173b18e5), X(0x1753ffe2), X(0x176cf1a5),
+ X(0x1785ee27), X(0x179ef562), X(0x17b80750), X(0x17d123eb),
+ X(0x17ea4b2d), X(0x18037d10), X(0x181cb98d), X(0x1836009e),
+ X(0x184f523c), X(0x1868ae63), X(0x1882150a), X(0x189b862c),
+ X(0x18b501c4), X(0x18ce87c9), X(0x18e81836), X(0x1901b305),
+ X(0x191b582f), X(0x193507ad), X(0x194ec17a), X(0x1968858f),
+ X(0x198253e5), X(0x199c2c75), X(0x19b60f3a), X(0x19cffc2d),
+ X(0x19e9f347), X(0x1a03f482), X(0x1a1dffd7), X(0x1a381540),
+ X(0x1a5234b5), X(0x1a6c5e31), X(0x1a8691ac), X(0x1aa0cf21),
+ X(0x1abb1687), X(0x1ad567da), X(0x1aefc311), X(0x1b0a2826),
+ X(0x1b249712), X(0x1b3f0fd0), X(0x1b599257), X(0x1b741ea1),
+ X(0x1b8eb4a7), X(0x1ba95462), X(0x1bc3fdcd), X(0x1bdeb0de),
+ X(0x1bf96d91), X(0x1c1433dd), X(0x1c2f03bc), X(0x1c49dd27),
+ X(0x1c64c017), X(0x1c7fac85), X(0x1c9aa269), X(0x1cb5a1be),
+ X(0x1cd0aa7c), X(0x1cebbc9c), X(0x1d06d816), X(0x1d21fce4),
+ X(0x1d3d2aff), X(0x1d586260), X(0x1d73a2fe), X(0x1d8eecd4),
+ X(0x1daa3fda), X(0x1dc59c09), X(0x1de1015a), X(0x1dfc6fc5),
+ X(0x1e17e743), X(0x1e3367cd), X(0x1e4ef15b), X(0x1e6a83e7),
+ X(0x1e861f6a), X(0x1ea1c3da), X(0x1ebd7133), X(0x1ed9276b),
+ X(0x1ef4e67c), X(0x1f10ae5e), X(0x1f2c7f0a), X(0x1f485879),
+ X(0x1f643aa2), X(0x1f80257f), X(0x1f9c1908), X(0x1fb81536),
+ X(0x1fd41a00), X(0x1ff02761), X(0x200c3d4f), X(0x20285bc3),
+ X(0x204482b7), X(0x2060b221), X(0x207ce9fb), X(0x20992a3e),
+ X(0x20b572e0), X(0x20d1c3dc), X(0x20ee1d28), X(0x210a7ebe),
+ X(0x2126e895), X(0x21435aa6), X(0x215fd4ea), X(0x217c5757),
+ X(0x2198e1e8), X(0x21b57493), X(0x21d20f51), X(0x21eeb21b),
+ X(0x220b5ce7), X(0x22280fb0), X(0x2244ca6c), X(0x22618d13),
+ X(0x227e579f), X(0x229b2a06), X(0x22b80442), X(0x22d4e649),
+ X(0x22f1d015), X(0x230ec19d), X(0x232bbad9), X(0x2348bbc1),
+ X(0x2365c44c), X(0x2382d474), X(0x239fec30), X(0x23bd0b78),
+ X(0x23da3244), X(0x23f7608b), X(0x24149646), X(0x2431d36c),
+ X(0x244f17f5), X(0x246c63da), X(0x2489b711), X(0x24a71193),
+ X(0x24c47358), X(0x24e1dc57), X(0x24ff4c88), X(0x251cc3e2),
+ X(0x253a425e), X(0x2557c7f4), X(0x2575549a), X(0x2592e848),
+ X(0x25b082f7), X(0x25ce249e), X(0x25ebcd34), X(0x26097cb2),
+ X(0x2627330e), X(0x2644f040), X(0x2662b441), X(0x26807f07),
+ X(0x269e5089), X(0x26bc28c1), X(0x26da07a4), X(0x26f7ed2b),
+ X(0x2715d94d), X(0x2733cc02), X(0x2751c540), X(0x276fc500),
+ X(0x278dcb39), X(0x27abd7e2), X(0x27c9eaf3), X(0x27e80463),
+ X(0x28062429), X(0x28244a3e), X(0x28427697), X(0x2860a92d),
+ X(0x287ee1f7), X(0x289d20eb), X(0x28bb6603), X(0x28d9b134),
+ X(0x28f80275), X(0x291659c0), X(0x2934b709), X(0x29531a49),
+ X(0x29718378), X(0x298ff28b), X(0x29ae677b), X(0x29cce23e),
+ X(0x29eb62cb), X(0x2a09e91b), X(0x2a287523), X(0x2a4706dc),
+ X(0x2a659e3c), X(0x2a843b39), X(0x2aa2ddcd), X(0x2ac185ec),
+ X(0x2ae0338f), X(0x2afee6ad), X(0x2b1d9f3c), X(0x2b3c5d33),
+ X(0x2b5b208b), X(0x2b79e939), X(0x2b98b734), X(0x2bb78a74),
+ X(0x2bd662ef), X(0x2bf5409d), X(0x2c142374), X(0x2c330b6b),
+ X(0x2c51f87a), X(0x2c70ea97), X(0x2c8fe1b9), X(0x2caeddd6),
+ X(0x2ccddee7), X(0x2cece4e1), X(0x2d0befbb), X(0x2d2aff6d),
+ X(0x2d4a13ec), X(0x2d692d31), X(0x2d884b32), X(0x2da76de4),
+ X(0x2dc69540), X(0x2de5c13d), X(0x2e04f1d0), X(0x2e2426f0),
+ X(0x2e436095), X(0x2e629eb4), X(0x2e81e146), X(0x2ea1283f),
+ X(0x2ec07398), X(0x2edfc347), X(0x2eff1742), X(0x2f1e6f80),
+ X(0x2f3dcbf8), X(0x2f5d2ca0), X(0x2f7c916f), X(0x2f9bfa5c),
+ X(0x2fbb675d), X(0x2fdad869), X(0x2ffa4d76), X(0x3019c67b),
+ X(0x3039436f), X(0x3058c448), X(0x307848fc), X(0x3097d183),
+ X(0x30b75dd3), X(0x30d6ede2), X(0x30f681a6), X(0x31161917),
+ X(0x3135b42b), X(0x315552d8), X(0x3174f514), X(0x31949ad7),
+ X(0x31b44417), X(0x31d3f0ca), X(0x31f3a0e6), X(0x32135462),
+ X(0x32330b35), X(0x3252c555), X(0x327282b7), X(0x32924354),
+ X(0x32b20720), X(0x32d1ce13), X(0x32f19823), X(0x33116546),
+ X(0x33313573), X(0x3351089f), X(0x3370dec2), X(0x3390b7d1),
+ X(0x33b093c3), X(0x33d0728f), X(0x33f05429), X(0x3410388a),
+ X(0x34301fa7), X(0x34500977), X(0x346ff5ef), X(0x348fe506),
+ X(0x34afd6b3), X(0x34cfcaeb), X(0x34efc1a5), X(0x350fbad7),
+ X(0x352fb678), X(0x354fb47d), X(0x356fb4dd), X(0x358fb78e),
+ X(0x35afbc86), X(0x35cfc3bc), X(0x35efcd25), X(0x360fd8b8),
+ X(0x362fe66c), X(0x364ff636), X(0x3670080c), X(0x36901be5),
+ X(0x36b031b7), X(0x36d04978), X(0x36f0631e), X(0x37107ea0),
+ X(0x37309bf3), X(0x3750bb0e), X(0x3770dbe6), X(0x3790fe73),
+ X(0x37b122aa), X(0x37d14881), X(0x37f16fee), X(0x381198e8),
+ X(0x3831c365), X(0x3851ef5a), X(0x38721cbe), X(0x38924b87),
+ X(0x38b27bac), X(0x38d2ad21), X(0x38f2dfde), X(0x391313d8),
+ X(0x39334906), X(0x39537f5d), X(0x3973b6d4), X(0x3993ef60),
+ X(0x39b428f9), X(0x39d46393), X(0x39f49f25), X(0x3a14dba6),
+ X(0x3a35190a), X(0x3a555748), X(0x3a759657), X(0x3a95d62c),
+ X(0x3ab616be), X(0x3ad65801), X(0x3af699ed), X(0x3b16dc78),
+ X(0x3b371f97), X(0x3b576341), X(0x3b77a76c), X(0x3b97ec0d),
+ X(0x3bb8311b), X(0x3bd8768b), X(0x3bf8bc55), X(0x3c19026d),
+ X(0x3c3948ca), X(0x3c598f62), X(0x3c79d62b), X(0x3c9a1d1b),
+ X(0x3cba6428), X(0x3cdaab48), X(0x3cfaf271), X(0x3d1b3999),
+ X(0x3d3b80b6), X(0x3d5bc7be), X(0x3d7c0ea8), X(0x3d9c5569),
+ X(0x3dbc9bf7), X(0x3ddce248), X(0x3dfd2852), X(0x3e1d6e0c),
+ X(0x3e3db36c), X(0x3e5df866), X(0x3e7e3cf2), X(0x3e9e8106),
+ X(0x3ebec497), X(0x3edf079b), X(0x3eff4a09), X(0x3f1f8bd7),
+ X(0x3f3fccfa), X(0x3f600d69), X(0x3f804d1a), X(0x3fa08c02),
+ X(0x3fc0ca19), X(0x3fe10753), X(0x400143a7), X(0x40217f0a),
+ X(0x4041b974), X(0x4061f2da), X(0x40822b32), X(0x40a26272),
+ X(0x40c29891), X(0x40e2cd83), X(0x41030140), X(0x412333bd),
+ X(0x414364f1), X(0x416394d2), X(0x4183c355), X(0x41a3f070),
+ X(0x41c41c1b), X(0x41e4464a), X(0x42046ef4), X(0x42249610),
+ X(0x4244bb92), X(0x4264df72), X(0x428501a5), X(0x42a52222),
+ X(0x42c540de), X(0x42e55dd0), X(0x430578ed), X(0x4325922d),
+ X(0x4345a985), X(0x4365beeb), X(0x4385d255), X(0x43a5e3ba),
+ X(0x43c5f30f), X(0x43e6004b), X(0x44060b65), X(0x44261451),
+ X(0x44461b07), X(0x44661f7c), X(0x448621a7), X(0x44a6217d),
+ X(0x44c61ef6), X(0x44e61a07), X(0x450612a6), X(0x452608ca),
+ X(0x4545fc69), X(0x4565ed79), X(0x4585dbf1), X(0x45a5c7c6),
+ X(0x45c5b0ef), X(0x45e59761), X(0x46057b15), X(0x46255bfe),
+ X(0x46453a15), X(0x4665154f), X(0x4684eda2), X(0x46a4c305),
+ X(0x46c4956e), X(0x46e464d3), X(0x4704312b), X(0x4723fa6c),
+ X(0x4743c08d), X(0x47638382), X(0x47834344), X(0x47a2ffc9),
+ X(0x47c2b906), X(0x47e26ef2), X(0x48022183), X(0x4821d0b1),
+ X(0x48417c71), X(0x486124b9), X(0x4880c981), X(0x48a06abe),
+ X(0x48c00867), X(0x48dfa272), X(0x48ff38d6), X(0x491ecb8a),
+ X(0x493e5a84), X(0x495de5b9), X(0x497d6d22), X(0x499cf0b4),
+ X(0x49bc7066), X(0x49dbec2e), X(0x49fb6402), X(0x4a1ad7db),
+ X(0x4a3a47ad), X(0x4a59b370), X(0x4a791b1a), X(0x4a987ea1),
+ X(0x4ab7ddfd), X(0x4ad73924), X(0x4af6900c), X(0x4b15e2ad),
+ X(0x4b3530fc), X(0x4b547af1), X(0x4b73c082), X(0x4b9301a6),
+ X(0x4bb23e53), X(0x4bd17681), X(0x4bf0aa25), X(0x4c0fd937),
+ X(0x4c2f03ae), X(0x4c4e297f), X(0x4c6d4aa3), X(0x4c8c670f),
+ X(0x4cab7eba), X(0x4cca919c), X(0x4ce99fab), X(0x4d08a8de),
+ X(0x4d27ad2c), X(0x4d46ac8b), X(0x4d65a6f3), X(0x4d849c5a),
+ X(0x4da38cb7), X(0x4dc27802), X(0x4de15e31), X(0x4e003f3a),
+ X(0x4e1f1b16), X(0x4e3df1ba), X(0x4e5cc31e), X(0x4e7b8f3a),
+ X(0x4e9a5603), X(0x4eb91771), X(0x4ed7d37b), X(0x4ef68a18),
+ X(0x4f153b3f), X(0x4f33e6e7), X(0x4f528d08), X(0x4f712d97),
+ X(0x4f8fc88e), X(0x4fae5de1), X(0x4fcced8a), X(0x4feb777f),
+ X(0x5009fbb6), X(0x50287a28), X(0x5046f2cc), X(0x50656598),
+ X(0x5083d284), X(0x50a23988), X(0x50c09a9a), X(0x50def5b1),
+ X(0x50fd4ac7), X(0x511b99d0), X(0x5139e2c5), X(0x5158259e),
+ X(0x51766251), X(0x519498d6), X(0x51b2c925), X(0x51d0f334),
+ X(0x51ef16fb), X(0x520d3473), X(0x522b4b91), X(0x52495c4e),
+ X(0x526766a2), X(0x52856a83), X(0x52a367e9), X(0x52c15ecd),
+ X(0x52df4f24), X(0x52fd38e8), X(0x531b1c10), X(0x5338f892),
+ X(0x5356ce68), X(0x53749d89), X(0x539265eb), X(0x53b02788),
+ X(0x53cde257), X(0x53eb964f), X(0x54094369), X(0x5426e99c),
+ X(0x544488df), X(0x5462212c), X(0x547fb279), X(0x549d3cbe),
+ X(0x54babff4), X(0x54d83c12), X(0x54f5b110), X(0x55131ee7),
+ X(0x5530858d), X(0x554de4fc), X(0x556b3d2a), X(0x55888e11),
+ X(0x55a5d7a8), X(0x55c319e7), X(0x55e054c7), X(0x55fd883f),
+ X(0x561ab447), X(0x5637d8d8), X(0x5654f5ea), X(0x56720b75),
+ X(0x568f1971), X(0x56ac1fd7), X(0x56c91e9e), X(0x56e615c0),
+ X(0x57030534), X(0x571fecf2), X(0x573cccf3), X(0x5759a530),
+ X(0x577675a0), X(0x57933e3c), X(0x57affefd), X(0x57ccb7db),
+ X(0x57e968ce), X(0x580611cf), X(0x5822b2d6), X(0x583f4bdd),
+ X(0x585bdcdb), X(0x587865c9), X(0x5894e69f), X(0x58b15f57),
+ X(0x58cdcfe9), X(0x58ea384e), X(0x5906987d), X(0x5922f071),
+ X(0x593f4022), X(0x595b8788), X(0x5977c69c), X(0x5993fd57),
+ X(0x59b02bb2), X(0x59cc51a6), X(0x59e86f2c), X(0x5a04843c),
+ X(0x5a2090d0), X(0x5a3c94e0), X(0x5a589065), X(0x5a748359),
+ X(0x5a906db4), X(0x5aac4f70), X(0x5ac82884), X(0x5ae3f8ec),
+ X(0x5affc09f), X(0x5b1b7f97), X(0x5b3735cd), X(0x5b52e33a),
+ X(0x5b6e87d8), X(0x5b8a239f), X(0x5ba5b689), X(0x5bc1408f),
+ X(0x5bdcc1aa), X(0x5bf839d5), X(0x5c13a907), X(0x5c2f0f3b),
+ X(0x5c4a6c6a), X(0x5c65c08d), X(0x5c810b9e), X(0x5c9c4d97),
+ X(0x5cb78670), X(0x5cd2b623), X(0x5ceddcaa), X(0x5d08f9ff),
+ X(0x5d240e1b), X(0x5d3f18f8), X(0x5d5a1a8f), X(0x5d7512da),
+ X(0x5d9001d3), X(0x5daae773), X(0x5dc5c3b5), X(0x5de09692),
+ X(0x5dfb6004), X(0x5e162004), X(0x5e30d68d), X(0x5e4b8399),
+ X(0x5e662721), X(0x5e80c11f), X(0x5e9b518e), X(0x5eb5d867),
+ X(0x5ed055a4), X(0x5eeac940), X(0x5f053334), X(0x5f1f937b),
+ X(0x5f39ea0f), X(0x5f5436ea), X(0x5f6e7a06), X(0x5f88b35d),
+ X(0x5fa2e2e9), X(0x5fbd08a6), X(0x5fd7248d), X(0x5ff13698),
+ X(0x600b3ec2), X(0x60253d05), X(0x603f315b), X(0x60591bc0),
+ X(0x6072fc2d), X(0x608cd29e), X(0x60a69f0b), X(0x60c06171),
+ X(0x60da19ca), X(0x60f3c80f), X(0x610d6c3d), X(0x6127064d),
+ X(0x6140963a), X(0x615a1bff), X(0x61739797), X(0x618d08fc),
+ X(0x61a67029), X(0x61bfcd1a), X(0x61d91fc8), X(0x61f2682f),
+ X(0x620ba64a), X(0x6224da13), X(0x623e0386), X(0x6257229d),
+ X(0x62703754), X(0x628941a6), X(0x62a2418e), X(0x62bb3706),
+ X(0x62d4220a), X(0x62ed0296), X(0x6305d8a3), X(0x631ea42f),
+ X(0x63376533), X(0x63501bab), X(0x6368c793), X(0x638168e5),
+ X(0x6399ff9e), X(0x63b28bb8), X(0x63cb0d2f), X(0x63e383ff),
+ X(0x63fbf022), X(0x64145195), X(0x642ca853), X(0x6444f457),
+ X(0x645d359e), X(0x64756c22), X(0x648d97e0), X(0x64a5b8d3),
+ X(0x64bdcef6), X(0x64d5da47), X(0x64eddabf), X(0x6505d05c),
+ X(0x651dbb19), X(0x65359af2), X(0x654d6fe3), X(0x656539e7),
+ X(0x657cf8fb), X(0x6594ad1b), X(0x65ac5643), X(0x65c3f46e),
+ X(0x65db8799), X(0x65f30fc0), X(0x660a8ce0), X(0x6621fef3),
+ X(0x663965f7), X(0x6650c1e7), X(0x666812c1), X(0x667f5880),
+ X(0x66969320), X(0x66adc29e), X(0x66c4e6f7), X(0x66dc0026),
+ X(0x66f30e28), X(0x670a10fa), X(0x67210898), X(0x6737f4ff),
+ X(0x674ed62b), X(0x6765ac19), X(0x677c76c5), X(0x6793362c),
+ X(0x67a9ea4b), X(0x67c0931f), X(0x67d730a3), X(0x67edc2d6),
+ X(0x680449b3), X(0x681ac538), X(0x68313562), X(0x68479a2d),
+ X(0x685df396), X(0x6874419b), X(0x688a8438), X(0x68a0bb6a),
+ X(0x68b6e72e), X(0x68cd0782), X(0x68e31c63), X(0x68f925cd),
+ X(0x690f23be), X(0x69251633), X(0x693afd29), X(0x6950d89e),
+ X(0x6966a88f), X(0x697c6cf8), X(0x699225d9), X(0x69a7d32d),
+ X(0x69bd74f3), X(0x69d30b27), X(0x69e895c8), X(0x69fe14d2),
+ X(0x6a138844), X(0x6a28f01b), X(0x6a3e4c54), X(0x6a539ced),
+ X(0x6a68e1e4), X(0x6a7e1b37), X(0x6a9348e3), X(0x6aa86ae6),
+ X(0x6abd813d), X(0x6ad28be7), X(0x6ae78ae2), X(0x6afc7e2b),
+ X(0x6b1165c0), X(0x6b26419f), X(0x6b3b11c7), X(0x6b4fd634),
+ X(0x6b648ee6), X(0x6b793bda), X(0x6b8ddd0e), X(0x6ba27281),
+ X(0x6bb6fc31), X(0x6bcb7a1b), X(0x6bdfec3e), X(0x6bf45299),
+ X(0x6c08ad29), X(0x6c1cfbed), X(0x6c313ee4), X(0x6c45760a),
+ X(0x6c59a160), X(0x6c6dc0e4), X(0x6c81d493), X(0x6c95dc6d),
+ X(0x6ca9d86f), X(0x6cbdc899), X(0x6cd1acea), X(0x6ce5855f),
+ X(0x6cf951f7), X(0x6d0d12b1), X(0x6d20c78c), X(0x6d347087),
+ X(0x6d480da0), X(0x6d5b9ed6), X(0x6d6f2427), X(0x6d829d94),
+ X(0x6d960b1a), X(0x6da96cb9), X(0x6dbcc270), X(0x6dd00c3c),
+ X(0x6de34a1f), X(0x6df67c16), X(0x6e09a221), X(0x6e1cbc3f),
+ X(0x6e2fca6e), X(0x6e42ccaf), X(0x6e55c300), X(0x6e68ad60),
+ X(0x6e7b8bd0), X(0x6e8e5e4d), X(0x6ea124d8), X(0x6eb3df70),
+ X(0x6ec68e13), X(0x6ed930c3), X(0x6eebc77d), X(0x6efe5242),
+ X(0x6f10d111), X(0x6f2343e9), X(0x6f35aacb), X(0x6f4805b5),
+ X(0x6f5a54a8), X(0x6f6c97a2), X(0x6f7ecea4), X(0x6f90f9ae),
+ X(0x6fa318be), X(0x6fb52bd6), X(0x6fc732f4), X(0x6fd92e19),
+ X(0x6feb1d44), X(0x6ffd0076), X(0x700ed7ad), X(0x7020a2eb),
+ X(0x7032622f), X(0x7044157a), X(0x7055bcca), X(0x70675821),
+ X(0x7078e77e), X(0x708a6ae2), X(0x709be24c), X(0x70ad4dbd),
+ X(0x70bead36), X(0x70d000b5), X(0x70e1483d), X(0x70f283cc),
+ X(0x7103b363), X(0x7114d704), X(0x7125eead), X(0x7136fa60),
+ X(0x7147fa1c), X(0x7158ede4), X(0x7169d5b6), X(0x717ab193),
+ X(0x718b817d), X(0x719c4573), X(0x71acfd76), X(0x71bda988),
+ X(0x71ce49a8), X(0x71deddd7), X(0x71ef6617), X(0x71ffe267),
+ X(0x721052ca), X(0x7220b73e), X(0x72310fc6), X(0x72415c62),
+ X(0x72519d14), X(0x7261d1db), X(0x7271faba), X(0x728217b1),
+ X(0x729228c0), X(0x72a22dea), X(0x72b22730), X(0x72c21491),
+ X(0x72d1f611), X(0x72e1cbaf), X(0x72f1956c), X(0x7301534c),
+ X(0x7311054d), X(0x7320ab72), X(0x733045bc), X(0x733fd42d),
+ X(0x734f56c5), X(0x735ecd86), X(0x736e3872), X(0x737d9789),
+ X(0x738ceacf), X(0x739c3243), X(0x73ab6de7), X(0x73ba9dbe),
+ X(0x73c9c1c8), X(0x73d8da08), X(0x73e7e67f), X(0x73f6e72e),
+ X(0x7405dc17), X(0x7414c53c), X(0x7423a29f), X(0x74327442),
+ X(0x74413a26), X(0x744ff44d), X(0x745ea2b9), X(0x746d456c),
+ X(0x747bdc68), X(0x748a67ae), X(0x7498e741), X(0x74a75b23),
+ X(0x74b5c356), X(0x74c41fdb), X(0x74d270b6), X(0x74e0b5e7),
+ X(0x74eeef71), X(0x74fd1d57), X(0x750b3f9a), X(0x7519563c),
+ X(0x75276140), X(0x753560a8), X(0x75435477), X(0x75513cae),
+ X(0x755f1951), X(0x756cea60), X(0x757aafdf), X(0x758869d1),
+ X(0x75961837), X(0x75a3bb14), X(0x75b1526a), X(0x75bede3c),
+ X(0x75cc5e8d), X(0x75d9d35f), X(0x75e73cb5), X(0x75f49a91),
+ X(0x7601ecf6), X(0x760f33e6), X(0x761c6f65), X(0x76299f74),
+ X(0x7636c417), X(0x7643dd51), X(0x7650eb24), X(0x765ded93),
+ X(0x766ae4a0), X(0x7677d050), X(0x7684b0a4), X(0x7691859f),
+ X(0x769e4f45), X(0x76ab0d98), X(0x76b7c09c), X(0x76c46852),
+ X(0x76d104bf), X(0x76dd95e6), X(0x76ea1bc9), X(0x76f6966b),
+ X(0x770305d0), X(0x770f69fb), X(0x771bc2ef), X(0x772810af),
+ X(0x7734533e), X(0x77408aa0), X(0x774cb6d7), X(0x7758d7e8),
+ X(0x7764edd5), X(0x7770f8a2), X(0x777cf852), X(0x7788ece8),
+ X(0x7794d668), X(0x77a0b4d5), X(0x77ac8833), X(0x77b85085),
+ X(0x77c40dce), X(0x77cfc013), X(0x77db6756), X(0x77e7039b),
+ X(0x77f294e6), X(0x77fe1b3b), X(0x7809969c), X(0x7815070e),
+ X(0x78206c93), X(0x782bc731), X(0x783716ea), X(0x78425bc3),
+ X(0x784d95be), X(0x7858c4e1), X(0x7863e92d), X(0x786f02a8),
+ X(0x787a1156), X(0x78851539), X(0x78900e56), X(0x789afcb1),
+ X(0x78a5e04d), X(0x78b0b92f), X(0x78bb875b), X(0x78c64ad4),
+ X(0x78d1039e), X(0x78dbb1be), X(0x78e65537), X(0x78f0ee0e),
+ X(0x78fb7c46), X(0x7905ffe4), X(0x791078ec), X(0x791ae762),
+ X(0x79254b4a), X(0x792fa4a7), X(0x7939f380), X(0x794437d7),
+ X(0x794e71b0), X(0x7958a111), X(0x7962c5fd), X(0x796ce078),
+ X(0x7976f087), X(0x7980f62f), X(0x798af173), X(0x7994e258),
+ X(0x799ec8e2), X(0x79a8a515), X(0x79b276f7), X(0x79bc3e8b),
+ X(0x79c5fbd6), X(0x79cfaedc), X(0x79d957a2), X(0x79e2f62c),
+ X(0x79ec8a7f), X(0x79f6149f), X(0x79ff9492), X(0x7a090a5a),
+ X(0x7a1275fe), X(0x7a1bd781), X(0x7a252ee9), X(0x7a2e7c39),
+ X(0x7a37bf77), X(0x7a40f8a7), X(0x7a4a27ce), X(0x7a534cf0),
+ X(0x7a5c6813), X(0x7a65793b), X(0x7a6e806d), X(0x7a777dad),
+ X(0x7a807100), X(0x7a895a6b), X(0x7a9239f4), X(0x7a9b0f9e),
+ X(0x7aa3db6f), X(0x7aac9d6b), X(0x7ab55597), X(0x7abe03f9),
+ X(0x7ac6a895), X(0x7acf4370), X(0x7ad7d48f), X(0x7ae05bf6),
+ X(0x7ae8d9ac), X(0x7af14db5), X(0x7af9b815), X(0x7b0218d2),
+ X(0x7b0a6ff2), X(0x7b12bd78), X(0x7b1b016a), X(0x7b233bce),
+ X(0x7b2b6ca7), X(0x7b3393fc), X(0x7b3bb1d1), X(0x7b43c62c),
+ X(0x7b4bd111), X(0x7b53d286), X(0x7b5bca90), X(0x7b63b935),
+ X(0x7b6b9e78), X(0x7b737a61), X(0x7b7b4cf3), X(0x7b831634),
+ X(0x7b8ad629), X(0x7b928cd8), X(0x7b9a3a45), X(0x7ba1de77),
+ X(0x7ba97972), X(0x7bb10b3c), X(0x7bb893d9), X(0x7bc01350),
+ X(0x7bc789a6), X(0x7bcef6e0), X(0x7bd65b03), X(0x7bddb616),
+ X(0x7be5081c), X(0x7bec511c), X(0x7bf3911b), X(0x7bfac81f),
+ X(0x7c01f62c), X(0x7c091b49), X(0x7c10377b), X(0x7c174ac7),
+ X(0x7c1e5532), X(0x7c2556c4), X(0x7c2c4f80), X(0x7c333f6c),
+ X(0x7c3a268e), X(0x7c4104ec), X(0x7c47da8a), X(0x7c4ea76f),
+ X(0x7c556ba1), X(0x7c5c2724), X(0x7c62d9fe), X(0x7c698435),
+ X(0x7c7025cf), X(0x7c76bed0), X(0x7c7d4f40), X(0x7c83d723),
+ X(0x7c8a567f), X(0x7c90cd5a), X(0x7c973bb9), X(0x7c9da1a2),
+ X(0x7ca3ff1b), X(0x7caa542a), X(0x7cb0a0d3), X(0x7cb6e51e),
+ X(0x7cbd210f), X(0x7cc354ac), X(0x7cc97ffc), X(0x7ccfa304),
+ X(0x7cd5bdc9), X(0x7cdbd051), X(0x7ce1daa3), X(0x7ce7dcc3),
+ X(0x7cedd6b8), X(0x7cf3c888), X(0x7cf9b238), X(0x7cff93cf),
+ X(0x7d056d51), X(0x7d0b3ec5), X(0x7d110830), X(0x7d16c99a),
+ X(0x7d1c8306), X(0x7d22347c), X(0x7d27de00), X(0x7d2d7f9a),
+ X(0x7d33194f), X(0x7d38ab24), X(0x7d3e351f), X(0x7d43b748),
+ X(0x7d4931a2), X(0x7d4ea435), X(0x7d540f06), X(0x7d59721b),
+ X(0x7d5ecd7b), X(0x7d64212a), X(0x7d696d2f), X(0x7d6eb190),
+ X(0x7d73ee53), X(0x7d79237e), X(0x7d7e5117), X(0x7d837723),
+ X(0x7d8895a9), X(0x7d8dacae), X(0x7d92bc3a), X(0x7d97c451),
+ X(0x7d9cc4f9), X(0x7da1be39), X(0x7da6b017), X(0x7dab9a99),
+ X(0x7db07dc4), X(0x7db5599e), X(0x7dba2e2f), X(0x7dbefb7b),
+ X(0x7dc3c189), X(0x7dc8805e), X(0x7dcd3802), X(0x7dd1e879),
+ X(0x7dd691ca), X(0x7ddb33fb), X(0x7ddfcf12), X(0x7de46315),
+ X(0x7de8f00a), X(0x7ded75f8), X(0x7df1f4e3), X(0x7df66cd3),
+ X(0x7dfaddcd), X(0x7dff47d7), X(0x7e03aaf8), X(0x7e080735),
+ X(0x7e0c5c95), X(0x7e10ab1e), X(0x7e14f2d5), X(0x7e1933c1),
+ X(0x7e1d6de8), X(0x7e21a150), X(0x7e25cdff), X(0x7e29f3fc),
+ X(0x7e2e134c), X(0x7e322bf5), X(0x7e363dfd), X(0x7e3a496b),
+ X(0x7e3e4e45), X(0x7e424c90), X(0x7e464454), X(0x7e4a3595),
+ X(0x7e4e205a), X(0x7e5204aa), X(0x7e55e289), X(0x7e59b9ff),
+ X(0x7e5d8b12), X(0x7e6155c7), X(0x7e651a24), X(0x7e68d831),
+ X(0x7e6c8ff2), X(0x7e70416e), X(0x7e73ecac), X(0x7e7791b0),
+ X(0x7e7b3082), X(0x7e7ec927), X(0x7e825ba6), X(0x7e85e804),
+ X(0x7e896e48), X(0x7e8cee77), X(0x7e906899), X(0x7e93dcb2),
+ X(0x7e974aca), X(0x7e9ab2e5), X(0x7e9e150b), X(0x7ea17141),
+ X(0x7ea4c78e), X(0x7ea817f7), X(0x7eab6283), X(0x7eaea737),
+ X(0x7eb1e61a), X(0x7eb51f33), X(0x7eb85285), X(0x7ebb8019),
+ X(0x7ebea7f4), X(0x7ec1ca1d), X(0x7ec4e698), X(0x7ec7fd6d),
+ X(0x7ecb0ea1), X(0x7ece1a3a), X(0x7ed1203f), X(0x7ed420b6),
+ X(0x7ed71ba4), X(0x7eda110f), X(0x7edd00ff), X(0x7edfeb78),
+ X(0x7ee2d081), X(0x7ee5b01f), X(0x7ee88a5a), X(0x7eeb5f36),
+ X(0x7eee2eba), X(0x7ef0f8ed), X(0x7ef3bdd3), X(0x7ef67d73),
+ X(0x7ef937d3), X(0x7efbecf9), X(0x7efe9ceb), X(0x7f0147ae),
+ X(0x7f03ed4a), X(0x7f068dc4), X(0x7f092922), X(0x7f0bbf69),
+ X(0x7f0e50a1), X(0x7f10dcce), X(0x7f1363f7), X(0x7f15e622),
+ X(0x7f186355), X(0x7f1adb95), X(0x7f1d4ee9), X(0x7f1fbd57),
+ X(0x7f2226e4), X(0x7f248b96), X(0x7f26eb74), X(0x7f294683),
+ X(0x7f2b9cc9), X(0x7f2dee4d), X(0x7f303b13), X(0x7f328322),
+ X(0x7f34c680), X(0x7f370533), X(0x7f393f40), X(0x7f3b74ad),
+ X(0x7f3da581), X(0x7f3fd1c1), X(0x7f41f972), X(0x7f441c9c),
+ X(0x7f463b43), X(0x7f48556d), X(0x7f4a6b21), X(0x7f4c7c64),
+ X(0x7f4e893c), X(0x7f5091ae), X(0x7f5295c1), X(0x7f54957a),
+ X(0x7f5690e0), X(0x7f5887f7), X(0x7f5a7ac5), X(0x7f5c6951),
+ X(0x7f5e53a0), X(0x7f6039b8), X(0x7f621b9e), X(0x7f63f958),
+ X(0x7f65d2ed), X(0x7f67a861), X(0x7f6979ba), X(0x7f6b46ff),
+ X(0x7f6d1034), X(0x7f6ed560), X(0x7f709687), X(0x7f7253b1),
+ X(0x7f740ce1), X(0x7f75c21f), X(0x7f777370), X(0x7f7920d8),
+ X(0x7f7aca5f), X(0x7f7c7008), X(0x7f7e11db), X(0x7f7fafdd),
+ X(0x7f814a13), X(0x7f82e082), X(0x7f847331), X(0x7f860224),
+ X(0x7f878d62), X(0x7f8914f0), X(0x7f8a98d4), X(0x7f8c1912),
+ X(0x7f8d95b0), X(0x7f8f0eb5), X(0x7f908425), X(0x7f91f605),
+ X(0x7f93645c), X(0x7f94cf2f), X(0x7f963683), X(0x7f979a5d),
+ X(0x7f98fac4), X(0x7f9a57bb), X(0x7f9bb14a), X(0x7f9d0775),
+ X(0x7f9e5a41), X(0x7f9fa9b4), X(0x7fa0f5d3), X(0x7fa23ea4),
+ X(0x7fa3842b), X(0x7fa4c66f), X(0x7fa60575), X(0x7fa74141),
+ X(0x7fa879d9), X(0x7fa9af42), X(0x7faae182), X(0x7fac109e),
+ X(0x7fad3c9a), X(0x7fae657d), X(0x7faf8b4c), X(0x7fb0ae0b),
+ X(0x7fb1cdc0), X(0x7fb2ea70), X(0x7fb40420), X(0x7fb51ad5),
+ X(0x7fb62e95), X(0x7fb73f64), X(0x7fb84d48), X(0x7fb95846),
+ X(0x7fba6062), X(0x7fbb65a2), X(0x7fbc680c), X(0x7fbd67a3),
+ X(0x7fbe646d), X(0x7fbf5e70), X(0x7fc055af), X(0x7fc14a31),
+ X(0x7fc23bf9), X(0x7fc32b0d), X(0x7fc41773), X(0x7fc5012e),
+ X(0x7fc5e844), X(0x7fc6ccba), X(0x7fc7ae94), X(0x7fc88dd8),
+ X(0x7fc96a8a), X(0x7fca44af), X(0x7fcb1c4c), X(0x7fcbf167),
+ X(0x7fccc403), X(0x7fcd9425), X(0x7fce61d3), X(0x7fcf2d11),
+ X(0x7fcff5e3), X(0x7fd0bc4f), X(0x7fd1805a), X(0x7fd24207),
+ X(0x7fd3015c), X(0x7fd3be5d), X(0x7fd47910), X(0x7fd53178),
+ X(0x7fd5e79b), X(0x7fd69b7c), X(0x7fd74d21), X(0x7fd7fc8e),
+ X(0x7fd8a9c8), X(0x7fd954d4), X(0x7fd9fdb5), X(0x7fdaa471),
+ X(0x7fdb490b), X(0x7fdbeb89), X(0x7fdc8bef), X(0x7fdd2a42),
+ X(0x7fddc685), X(0x7fde60be), X(0x7fdef8f0), X(0x7fdf8f20),
+ X(0x7fe02353), X(0x7fe0b58d), X(0x7fe145d3), X(0x7fe1d428),
+ X(0x7fe26091), X(0x7fe2eb12), X(0x7fe373b0), X(0x7fe3fa6f),
+ X(0x7fe47f53), X(0x7fe50260), X(0x7fe5839b), X(0x7fe60308),
+ X(0x7fe680ab), X(0x7fe6fc88), X(0x7fe776a4), X(0x7fe7ef02),
+ X(0x7fe865a7), X(0x7fe8da97), X(0x7fe94dd6), X(0x7fe9bf68),
+ X(0x7fea2f51), X(0x7fea9d95), X(0x7feb0a39), X(0x7feb7540),
+ X(0x7febdeae), X(0x7fec4687), X(0x7fecaccf), X(0x7fed118b),
+ X(0x7fed74be), X(0x7fedd66c), X(0x7fee3698), X(0x7fee9548),
+ X(0x7feef27e), X(0x7fef4e3f), X(0x7fefa88e), X(0x7ff0016f),
+ X(0x7ff058e7), X(0x7ff0aef8), X(0x7ff103a6), X(0x7ff156f6),
+ X(0x7ff1a8eb), X(0x7ff1f988), X(0x7ff248d2), X(0x7ff296cc),
+ X(0x7ff2e37a), X(0x7ff32edf), X(0x7ff378ff), X(0x7ff3c1de),
+ X(0x7ff4097e), X(0x7ff44fe5), X(0x7ff49515), X(0x7ff4d911),
+ X(0x7ff51bde), X(0x7ff55d7f), X(0x7ff59df7), X(0x7ff5dd4a),
+ X(0x7ff61b7b), X(0x7ff6588d), X(0x7ff69485), X(0x7ff6cf65),
+ X(0x7ff70930), X(0x7ff741eb), X(0x7ff77998), X(0x7ff7b03b),
+ X(0x7ff7e5d7), X(0x7ff81a6f), X(0x7ff84e06), X(0x7ff880a1),
+ X(0x7ff8b241), X(0x7ff8e2ea), X(0x7ff912a0), X(0x7ff94165),
+ X(0x7ff96f3d), X(0x7ff99c2b), X(0x7ff9c831), X(0x7ff9f354),
+ X(0x7ffa1d95), X(0x7ffa46f9), X(0x7ffa6f81), X(0x7ffa9731),
+ X(0x7ffabe0d), X(0x7ffae416), X(0x7ffb0951), X(0x7ffb2dbf),
+ X(0x7ffb5164), X(0x7ffb7442), X(0x7ffb965d), X(0x7ffbb7b8),
+ X(0x7ffbd854), X(0x7ffbf836), X(0x7ffc175f), X(0x7ffc35d3),
+ X(0x7ffc5394), X(0x7ffc70a5), X(0x7ffc8d09), X(0x7ffca8c2),
+ X(0x7ffcc3d4), X(0x7ffcde3f), X(0x7ffcf809), X(0x7ffd1132),
+ X(0x7ffd29be), X(0x7ffd41ae), X(0x7ffd5907), X(0x7ffd6fc9),
+ X(0x7ffd85f9), X(0x7ffd9b97), X(0x7ffdb0a7), X(0x7ffdc52b),
+ X(0x7ffdd926), X(0x7ffdec99), X(0x7ffdff88), X(0x7ffe11f4),
+ X(0x7ffe23e0), X(0x7ffe354f), X(0x7ffe4642), X(0x7ffe56bc),
+ X(0x7ffe66bf), X(0x7ffe764e), X(0x7ffe856a), X(0x7ffe9416),
+ X(0x7ffea254), X(0x7ffeb026), X(0x7ffebd8e), X(0x7ffeca8f),
+ X(0x7ffed72a), X(0x7ffee362), X(0x7ffeef38), X(0x7ffefaaf),
+ X(0x7fff05c9), X(0x7fff1087), X(0x7fff1aec), X(0x7fff24f9),
+ X(0x7fff2eb1), X(0x7fff3816), X(0x7fff4128), X(0x7fff49eb),
+ X(0x7fff5260), X(0x7fff5a88), X(0x7fff6266), X(0x7fff69fc),
+ X(0x7fff714b), X(0x7fff7854), X(0x7fff7f1a), X(0x7fff859f),
+ X(0x7fff8be3), X(0x7fff91ea), X(0x7fff97b3), X(0x7fff9d41),
+ X(0x7fffa296), X(0x7fffa7b3), X(0x7fffac99), X(0x7fffb14b),
+ X(0x7fffb5c9), X(0x7fffba15), X(0x7fffbe31), X(0x7fffc21d),
+ X(0x7fffc5dc), X(0x7fffc96f), X(0x7fffccd8), X(0x7fffd016),
+ X(0x7fffd32d), X(0x7fffd61c), X(0x7fffd8e7), X(0x7fffdb8d),
+ X(0x7fffde0f), X(0x7fffe071), X(0x7fffe2b1), X(0x7fffe4d2),
+ X(0x7fffe6d5), X(0x7fffe8bb), X(0x7fffea85), X(0x7fffec34),
+ X(0x7fffedc9), X(0x7fffef45), X(0x7ffff0aa), X(0x7ffff1f7),
+ X(0x7ffff330), X(0x7ffff453), X(0x7ffff562), X(0x7ffff65f),
+ X(0x7ffff749), X(0x7ffff823), X(0x7ffff8ec), X(0x7ffff9a6),
+ X(0x7ffffa51), X(0x7ffffaee), X(0x7ffffb7e), X(0x7ffffc02),
+ X(0x7ffffc7a), X(0x7ffffce7), X(0x7ffffd4a), X(0x7ffffda3),
+ X(0x7ffffdf4), X(0x7ffffe3c), X(0x7ffffe7c), X(0x7ffffeb6),
+ X(0x7ffffee8), X(0x7fffff15), X(0x7fffff3c), X(0x7fffff5e),
+ X(0x7fffff7b), X(0x7fffff95), X(0x7fffffaa), X(0x7fffffbc),
+ X(0x7fffffcb), X(0x7fffffd7), X(0x7fffffe2), X(0x7fffffea),
+ X(0x7ffffff0), X(0x7ffffff5), X(0x7ffffff9), X(0x7ffffffb),
+ X(0x7ffffffd), X(0x7ffffffe), X(0x7fffffff), X(0x7fffffff),
+ X(0x7fffffff), X(0x7fffffff), X(0x7fffffff), X(0x7fffffff),
+};
+
+#ifndef LIMIT_TO_64kHz
+
+static LOOKUP_T vwin8192[4096] = {
+ X(0x0000007c), X(0x0000045c), X(0x00000c1d), X(0x000017bd),
+ X(0x0000273e), X(0x00003a9f), X(0x000051e0), X(0x00006d02),
+ X(0x00008c03), X(0x0000aee5), X(0x0000d5a7), X(0x00010049),
+ X(0x00012ecb), X(0x0001612d), X(0x00019770), X(0x0001d193),
+ X(0x00020f96), X(0x00025178), X(0x0002973c), X(0x0002e0df),
+ X(0x00032e62), X(0x00037fc5), X(0x0003d509), X(0x00042e2c),
+ X(0x00048b30), X(0x0004ec13), X(0x000550d7), X(0x0005b97a),
+ X(0x000625fe), X(0x00069661), X(0x00070aa4), X(0x000782c8),
+ X(0x0007fecb), X(0x00087eae), X(0x00090271), X(0x00098a14),
+ X(0x000a1597), X(0x000aa4f9), X(0x000b383b), X(0x000bcf5d),
+ X(0x000c6a5f), X(0x000d0941), X(0x000dac02), X(0x000e52a3),
+ X(0x000efd23), X(0x000fab84), X(0x00105dc3), X(0x001113e3),
+ X(0x0011cde2), X(0x00128bc0), X(0x00134d7e), X(0x0014131b),
+ X(0x0014dc98), X(0x0015a9f4), X(0x00167b30), X(0x0017504a),
+ X(0x00182945), X(0x0019061e), X(0x0019e6d7), X(0x001acb6f),
+ X(0x001bb3e6), X(0x001ca03c), X(0x001d9071), X(0x001e8485),
+ X(0x001f7c79), X(0x0020784b), X(0x002177fc), X(0x00227b8c),
+ X(0x002382fb), X(0x00248e49), X(0x00259d76), X(0x0026b081),
+ X(0x0027c76b), X(0x0028e234), X(0x002a00dc), X(0x002b2361),
+ X(0x002c49c6), X(0x002d7409), X(0x002ea22a), X(0x002fd42a),
+ X(0x00310a08), X(0x003243c5), X(0x00338160), X(0x0034c2d9),
+ X(0x00360830), X(0x00375165), X(0x00389e78), X(0x0039ef6a),
+ X(0x003b4439), X(0x003c9ce6), X(0x003df971), X(0x003f59da),
+ X(0x0040be20), X(0x00422645), X(0x00439247), X(0x00450226),
+ X(0x004675e3), X(0x0047ed7e), X(0x004968f5), X(0x004ae84b),
+ X(0x004c6b7d), X(0x004df28d), X(0x004f7d7a), X(0x00510c44),
+ X(0x00529eeb), X(0x00543570), X(0x0055cfd1), X(0x00576e0f),
+ X(0x00591029), X(0x005ab621), X(0x005c5ff5), X(0x005e0da6),
+ X(0x005fbf33), X(0x0061749d), X(0x00632de4), X(0x0064eb06),
+ X(0x0066ac05), X(0x006870e0), X(0x006a3998), X(0x006c062b),
+ X(0x006dd69b), X(0x006faae6), X(0x0071830d), X(0x00735f10),
+ X(0x00753eef), X(0x007722a9), X(0x00790a3f), X(0x007af5b1),
+ X(0x007ce4fe), X(0x007ed826), X(0x0080cf29), X(0x0082ca08),
+ X(0x0084c8c2), X(0x0086cb57), X(0x0088d1c7), X(0x008adc11),
+ X(0x008cea37), X(0x008efc37), X(0x00911212), X(0x00932bc7),
+ X(0x00954957), X(0x00976ac2), X(0x00999006), X(0x009bb925),
+ X(0x009de61e), X(0x00a016f1), X(0x00a24b9e), X(0x00a48425),
+ X(0x00a6c086), X(0x00a900c0), X(0x00ab44d4), X(0x00ad8cc2),
+ X(0x00afd889), X(0x00b22829), X(0x00b47ba2), X(0x00b6d2f5),
+ X(0x00b92e21), X(0x00bb8d26), X(0x00bdf004), X(0x00c056ba),
+ X(0x00c2c149), X(0x00c52fb1), X(0x00c7a1f1), X(0x00ca180a),
+ X(0x00cc91fb), X(0x00cf0fc5), X(0x00d19166), X(0x00d416df),
+ X(0x00d6a031), X(0x00d92d5a), X(0x00dbbe5b), X(0x00de5333),
+ X(0x00e0ebe3), X(0x00e3886b), X(0x00e628c9), X(0x00e8ccff),
+ X(0x00eb750c), X(0x00ee20f0), X(0x00f0d0ab), X(0x00f3843d),
+ X(0x00f63ba5), X(0x00f8f6e4), X(0x00fbb5fa), X(0x00fe78e5),
+ X(0x01013fa7), X(0x01040a3f), X(0x0106d8ae), X(0x0109aaf2),
+ X(0x010c810c), X(0x010f5afb), X(0x011238c0), X(0x01151a5b),
+ X(0x0117ffcb), X(0x011ae910), X(0x011dd62a), X(0x0120c719),
+ X(0x0123bbdd), X(0x0126b476), X(0x0129b0e4), X(0x012cb126),
+ X(0x012fb53c), X(0x0132bd27), X(0x0135c8e6), X(0x0138d879),
+ X(0x013bebdf), X(0x013f031a), X(0x01421e28), X(0x01453d0a),
+ X(0x01485fbf), X(0x014b8648), X(0x014eb0a4), X(0x0151ded2),
+ X(0x015510d4), X(0x015846a8), X(0x015b8050), X(0x015ebdc9),
+ X(0x0161ff15), X(0x01654434), X(0x01688d24), X(0x016bd9e6),
+ X(0x016f2a7b), X(0x01727ee1), X(0x0175d718), X(0x01793321),
+ X(0x017c92fc), X(0x017ff6a7), X(0x01835e24), X(0x0186c972),
+ X(0x018a3890), X(0x018dab7f), X(0x0191223f), X(0x01949ccf),
+ X(0x01981b2f), X(0x019b9d5f), X(0x019f235f), X(0x01a2ad2f),
+ X(0x01a63acf), X(0x01a9cc3e), X(0x01ad617c), X(0x01b0fa8a),
+ X(0x01b49767), X(0x01b83813), X(0x01bbdc8d), X(0x01bf84d6),
+ X(0x01c330ee), X(0x01c6e0d4), X(0x01ca9488), X(0x01ce4c0b),
+ X(0x01d2075b), X(0x01d5c679), X(0x01d98964), X(0x01dd501d),
+ X(0x01e11aa3), X(0x01e4e8f6), X(0x01e8bb17), X(0x01ec9104),
+ X(0x01f06abd), X(0x01f44844), X(0x01f82996), X(0x01fc0eb5),
+ X(0x01fff7a0), X(0x0203e456), X(0x0207d4d9), X(0x020bc926),
+ X(0x020fc140), X(0x0213bd24), X(0x0217bcd4), X(0x021bc04e),
+ X(0x021fc793), X(0x0223d2a3), X(0x0227e17d), X(0x022bf421),
+ X(0x02300a90), X(0x023424c8), X(0x023842ca), X(0x023c6495),
+ X(0x02408a2a), X(0x0244b389), X(0x0248e0b0), X(0x024d11a0),
+ X(0x02514659), X(0x02557eda), X(0x0259bb24), X(0x025dfb35),
+ X(0x02623f0f), X(0x026686b1), X(0x026ad21a), X(0x026f214b),
+ X(0x02737443), X(0x0277cb02), X(0x027c2588), X(0x028083d5),
+ X(0x0284e5e9), X(0x02894bc2), X(0x028db562), X(0x029222c8),
+ X(0x029693f4), X(0x029b08e6), X(0x029f819d), X(0x02a3fe19),
+ X(0x02a87e5b), X(0x02ad0261), X(0x02b18a2c), X(0x02b615bb),
+ X(0x02baa50f), X(0x02bf3827), X(0x02c3cf03), X(0x02c869a3),
+ X(0x02cd0807), X(0x02d1aa2d), X(0x02d65017), X(0x02daf9c4),
+ X(0x02dfa734), X(0x02e45866), X(0x02e90d5b), X(0x02edc612),
+ X(0x02f2828b), X(0x02f742c6), X(0x02fc06c3), X(0x0300ce80),
+ X(0x030599ff), X(0x030a6940), X(0x030f3c40), X(0x03141302),
+ X(0x0318ed84), X(0x031dcbc6), X(0x0322adc8), X(0x0327938a),
+ X(0x032c7d0c), X(0x03316a4c), X(0x03365b4d), X(0x033b500c),
+ X(0x03404889), X(0x034544c6), X(0x034a44c0), X(0x034f4879),
+ X(0x03544ff0), X(0x03595b24), X(0x035e6a16), X(0x03637cc5),
+ X(0x03689331), X(0x036dad5a), X(0x0372cb40), X(0x0377ece2),
+ X(0x037d1240), X(0x03823b5a), X(0x03876830), X(0x038c98c1),
+ X(0x0391cd0e), X(0x03970516), X(0x039c40d8), X(0x03a18055),
+ X(0x03a6c38d), X(0x03ac0a7f), X(0x03b1552b), X(0x03b6a390),
+ X(0x03bbf5af), X(0x03c14b88), X(0x03c6a519), X(0x03cc0263),
+ X(0x03d16366), X(0x03d6c821), X(0x03dc3094), X(0x03e19cc0),
+ X(0x03e70ca2), X(0x03ec803d), X(0x03f1f78e), X(0x03f77296),
+ X(0x03fcf155), X(0x040273cb), X(0x0407f9f7), X(0x040d83d9),
+ X(0x04131170), X(0x0418a2bd), X(0x041e37c0), X(0x0423d077),
+ X(0x04296ce4), X(0x042f0d04), X(0x0434b0da), X(0x043a5863),
+ X(0x044003a0), X(0x0445b290), X(0x044b6534), X(0x04511b8b),
+ X(0x0456d595), X(0x045c9352), X(0x046254c1), X(0x046819e1),
+ X(0x046de2b4), X(0x0473af39), X(0x04797f6e), X(0x047f5355),
+ X(0x04852aec), X(0x048b0635), X(0x0490e52d), X(0x0496c7d6),
+ X(0x049cae2e), X(0x04a29836), X(0x04a885ed), X(0x04ae7753),
+ X(0x04b46c68), X(0x04ba652b), X(0x04c0619d), X(0x04c661bc),
+ X(0x04cc658a), X(0x04d26d04), X(0x04d8782c), X(0x04de8701),
+ X(0x04e49983), X(0x04eaafb0), X(0x04f0c98a), X(0x04f6e710),
+ X(0x04fd0842), X(0x05032d1e), X(0x050955a6), X(0x050f81d8),
+ X(0x0515b1b5), X(0x051be53d), X(0x05221c6e), X(0x05285748),
+ X(0x052e95cd), X(0x0534d7fa), X(0x053b1dd0), X(0x0541674e),
+ X(0x0547b475), X(0x054e0544), X(0x055459bb), X(0x055ab1d9),
+ X(0x05610d9e), X(0x05676d0a), X(0x056dd01c), X(0x057436d5),
+ X(0x057aa134), X(0x05810f38), X(0x058780e2), X(0x058df631),
+ X(0x05946f25), X(0x059aebbe), X(0x05a16bfa), X(0x05a7efdb),
+ X(0x05ae775f), X(0x05b50287), X(0x05bb9152), X(0x05c223c0),
+ X(0x05c8b9d0), X(0x05cf5382), X(0x05d5f0d6), X(0x05dc91cc),
+ X(0x05e33663), X(0x05e9de9c), X(0x05f08a75), X(0x05f739ee),
+ X(0x05fded07), X(0x0604a3c0), X(0x060b5e19), X(0x06121c11),
+ X(0x0618dda8), X(0x061fa2dd), X(0x06266bb1), X(0x062d3822),
+ X(0x06340831), X(0x063adbde), X(0x0641b328), X(0x06488e0e),
+ X(0x064f6c91), X(0x06564eaf), X(0x065d346a), X(0x06641dc0),
+ X(0x066b0ab1), X(0x0671fb3d), X(0x0678ef64), X(0x067fe724),
+ X(0x0686e27f), X(0x068de173), X(0x0694e400), X(0x069bea27),
+ X(0x06a2f3e6), X(0x06aa013d), X(0x06b1122c), X(0x06b826b3),
+ X(0x06bf3ed1), X(0x06c65a86), X(0x06cd79d1), X(0x06d49cb3),
+ X(0x06dbc32b), X(0x06e2ed38), X(0x06ea1adb), X(0x06f14c13),
+ X(0x06f880df), X(0x06ffb940), X(0x0706f535), X(0x070e34bd),
+ X(0x071577d9), X(0x071cbe88), X(0x072408c9), X(0x072b569d),
+ X(0x0732a802), X(0x0739fcf9), X(0x07415582), X(0x0748b19b),
+ X(0x07501145), X(0x0757747f), X(0x075edb49), X(0x076645a3),
+ X(0x076db38c), X(0x07752503), X(0x077c9a09), X(0x0784129e),
+ X(0x078b8ec0), X(0x07930e70), X(0x079a91ac), X(0x07a21876),
+ X(0x07a9a2cc), X(0x07b130ad), X(0x07b8c21b), X(0x07c05714),
+ X(0x07c7ef98), X(0x07cf8ba6), X(0x07d72b3f), X(0x07dece62),
+ X(0x07e6750e), X(0x07ee1f43), X(0x07f5cd01), X(0x07fd7e48),
+ X(0x08053316), X(0x080ceb6d), X(0x0814a74a), X(0x081c66af),
+ X(0x0824299a), X(0x082bf00c), X(0x0833ba03), X(0x083b8780),
+ X(0x08435882), X(0x084b2d09), X(0x08530514), X(0x085ae0a3),
+ X(0x0862bfb6), X(0x086aa24c), X(0x08728865), X(0x087a7201),
+ X(0x08825f1e), X(0x088a4fbe), X(0x089243de), X(0x089a3b80),
+ X(0x08a236a2), X(0x08aa3545), X(0x08b23767), X(0x08ba3d09),
+ X(0x08c2462a), X(0x08ca52c9), X(0x08d262e7), X(0x08da7682),
+ X(0x08e28d9c), X(0x08eaa832), X(0x08f2c645), X(0x08fae7d4),
+ X(0x09030cdf), X(0x090b3566), X(0x09136168), X(0x091b90e5),
+ X(0x0923c3dc), X(0x092bfa4d), X(0x09343437), X(0x093c719b),
+ X(0x0944b277), X(0x094cf6cc), X(0x09553e99), X(0x095d89dd),
+ X(0x0965d899), X(0x096e2acb), X(0x09768073), X(0x097ed991),
+ X(0x09873625), X(0x098f962e), X(0x0997f9ac), X(0x09a0609e),
+ X(0x09a8cb04), X(0x09b138dd), X(0x09b9aa29), X(0x09c21ee8),
+ X(0x09ca9719), X(0x09d312bc), X(0x09db91d0), X(0x09e41456),
+ X(0x09ec9a4b), X(0x09f523b1), X(0x09fdb087), X(0x0a0640cc),
+ X(0x0a0ed47f), X(0x0a176ba2), X(0x0a200632), X(0x0a28a42f),
+ X(0x0a31459a), X(0x0a39ea72), X(0x0a4292b5), X(0x0a4b3e65),
+ X(0x0a53ed80), X(0x0a5ca006), X(0x0a6555f7), X(0x0a6e0f51),
+ X(0x0a76cc16), X(0x0a7f8c44), X(0x0a884fda), X(0x0a9116d9),
+ X(0x0a99e140), X(0x0aa2af0e), X(0x0aab8043), X(0x0ab454df),
+ X(0x0abd2ce1), X(0x0ac60849), X(0x0acee716), X(0x0ad7c948),
+ X(0x0ae0aedf), X(0x0ae997d9), X(0x0af28437), X(0x0afb73f7),
+ X(0x0b04671b), X(0x0b0d5da0), X(0x0b165788), X(0x0b1f54d0),
+ X(0x0b285579), X(0x0b315983), X(0x0b3a60ec), X(0x0b436bb5),
+ X(0x0b4c79dd), X(0x0b558b63), X(0x0b5ea048), X(0x0b67b88a),
+ X(0x0b70d429), X(0x0b79f324), X(0x0b83157c), X(0x0b8c3b30),
+ X(0x0b95643f), X(0x0b9e90a8), X(0x0ba7c06c), X(0x0bb0f38a),
+ X(0x0bba2a01), X(0x0bc363d1), X(0x0bcca0f9), X(0x0bd5e17a),
+ X(0x0bdf2552), X(0x0be86c81), X(0x0bf1b706), X(0x0bfb04e2),
+ X(0x0c045613), X(0x0c0daa99), X(0x0c170274), X(0x0c205da3),
+ X(0x0c29bc25), X(0x0c331dfb), X(0x0c3c8323), X(0x0c45eb9e),
+ X(0x0c4f576a), X(0x0c58c688), X(0x0c6238f6), X(0x0c6baeb5),
+ X(0x0c7527c3), X(0x0c7ea421), X(0x0c8823cd), X(0x0c91a6c8),
+ X(0x0c9b2d10), X(0x0ca4b6a6), X(0x0cae4389), X(0x0cb7d3b8),
+ X(0x0cc16732), X(0x0ccafdf8), X(0x0cd49809), X(0x0cde3564),
+ X(0x0ce7d609), X(0x0cf179f7), X(0x0cfb212e), X(0x0d04cbad),
+ X(0x0d0e7974), X(0x0d182a83), X(0x0d21ded8), X(0x0d2b9673),
+ X(0x0d355154), X(0x0d3f0f7b), X(0x0d48d0e6), X(0x0d529595),
+ X(0x0d5c5d88), X(0x0d6628be), X(0x0d6ff737), X(0x0d79c8f2),
+ X(0x0d839dee), X(0x0d8d762c), X(0x0d9751aa), X(0x0da13068),
+ X(0x0dab1266), X(0x0db4f7a3), X(0x0dbee01e), X(0x0dc8cbd8),
+ X(0x0dd2bace), X(0x0ddcad02), X(0x0de6a272), X(0x0df09b1e),
+ X(0x0dfa9705), X(0x0e049627), X(0x0e0e9883), X(0x0e189e19),
+ X(0x0e22a6e8), X(0x0e2cb2f0), X(0x0e36c230), X(0x0e40d4a8),
+ X(0x0e4aea56), X(0x0e55033b), X(0x0e5f1f56), X(0x0e693ea7),
+ X(0x0e73612c), X(0x0e7d86e5), X(0x0e87afd3), X(0x0e91dbf3),
+ X(0x0e9c0b47), X(0x0ea63dcc), X(0x0eb07383), X(0x0ebaac6b),
+ X(0x0ec4e883), X(0x0ecf27cc), X(0x0ed96a44), X(0x0ee3afea),
+ X(0x0eedf8bf), X(0x0ef844c2), X(0x0f0293f2), X(0x0f0ce64e),
+ X(0x0f173bd6), X(0x0f21948a), X(0x0f2bf069), X(0x0f364f72),
+ X(0x0f40b1a5), X(0x0f4b1701), X(0x0f557f86), X(0x0f5feb32),
+ X(0x0f6a5a07), X(0x0f74cc02), X(0x0f7f4124), X(0x0f89b96b),
+ X(0x0f9434d8), X(0x0f9eb369), X(0x0fa9351e), X(0x0fb3b9f7),
+ X(0x0fbe41f3), X(0x0fc8cd11), X(0x0fd35b51), X(0x0fddecb2),
+ X(0x0fe88134), X(0x0ff318d6), X(0x0ffdb397), X(0x10085177),
+ X(0x1012f275), X(0x101d9691), X(0x10283dca), X(0x1032e81f),
+ X(0x103d9591), X(0x1048461e), X(0x1052f9c5), X(0x105db087),
+ X(0x10686a62), X(0x10732756), X(0x107de763), X(0x1088aa87),
+ X(0x109370c2), X(0x109e3a14), X(0x10a9067c), X(0x10b3d5f9),
+ X(0x10bea88b), X(0x10c97e31), X(0x10d456eb), X(0x10df32b8),
+ X(0x10ea1197), X(0x10f4f387), X(0x10ffd889), X(0x110ac09b),
+ X(0x1115abbe), X(0x112099ef), X(0x112b8b2f), X(0x11367f7d),
+ X(0x114176d9), X(0x114c7141), X(0x11576eb6), X(0x11626f36),
+ X(0x116d72c1), X(0x11787957), X(0x118382f6), X(0x118e8f9e),
+ X(0x11999f4f), X(0x11a4b208), X(0x11afc7c7), X(0x11bae08e),
+ X(0x11c5fc5a), X(0x11d11b2c), X(0x11dc3d02), X(0x11e761dd),
+ X(0x11f289ba), X(0x11fdb49b), X(0x1208e27e), X(0x12141362),
+ X(0x121f4748), X(0x122a7e2d), X(0x1235b812), X(0x1240f4f6),
+ X(0x124c34d9), X(0x125777b9), X(0x1262bd96), X(0x126e0670),
+ X(0x12795245), X(0x1284a115), X(0x128ff2e0), X(0x129b47a5),
+ X(0x12a69f63), X(0x12b1fa19), X(0x12bd57c7), X(0x12c8b86c),
+ X(0x12d41c08), X(0x12df829a), X(0x12eaec21), X(0x12f6589d),
+ X(0x1301c80c), X(0x130d3a6f), X(0x1318afc4), X(0x1324280b),
+ X(0x132fa344), X(0x133b216d), X(0x1346a286), X(0x1352268e),
+ X(0x135dad85), X(0x1369376a), X(0x1374c43c), X(0x138053fb),
+ X(0x138be6a5), X(0x13977c3b), X(0x13a314bc), X(0x13aeb026),
+ X(0x13ba4e79), X(0x13c5efb5), X(0x13d193d9), X(0x13dd3ae4),
+ X(0x13e8e4d6), X(0x13f491ad), X(0x1400416a), X(0x140bf40b),
+ X(0x1417a98f), X(0x142361f7), X(0x142f1d41), X(0x143adb6d),
+ X(0x14469c7a), X(0x14526067), X(0x145e2734), X(0x1469f0df),
+ X(0x1475bd69), X(0x14818cd0), X(0x148d5f15), X(0x14993435),
+ X(0x14a50c31), X(0x14b0e708), X(0x14bcc4b8), X(0x14c8a542),
+ X(0x14d488a5), X(0x14e06edf), X(0x14ec57f1), X(0x14f843d9),
+ X(0x15043297), X(0x1510242b), X(0x151c1892), X(0x15280fcd),
+ X(0x153409dc), X(0x154006bc), X(0x154c066e), X(0x155808f1),
+ X(0x15640e44), X(0x15701666), X(0x157c2157), X(0x15882f16),
+ X(0x15943fa2), X(0x15a052fb), X(0x15ac691f), X(0x15b8820f),
+ X(0x15c49dc8), X(0x15d0bc4c), X(0x15dcdd98), X(0x15e901ad),
+ X(0x15f52888), X(0x1601522b), X(0x160d7e93), X(0x1619adc1),
+ X(0x1625dfb3), X(0x16321469), X(0x163e4be2), X(0x164a861d),
+ X(0x1656c31a), X(0x166302d8), X(0x166f4555), X(0x167b8a92),
+ X(0x1687d28e), X(0x16941d47), X(0x16a06abe), X(0x16acbaf0),
+ X(0x16b90ddf), X(0x16c56388), X(0x16d1bbeb), X(0x16de1708),
+ X(0x16ea74dd), X(0x16f6d56a), X(0x170338ae), X(0x170f9ea8),
+ X(0x171c0758), X(0x172872bd), X(0x1734e0d6), X(0x174151a2),
+ X(0x174dc520), X(0x175a3b51), X(0x1766b432), X(0x17732fc4),
+ X(0x177fae05), X(0x178c2ef4), X(0x1798b292), X(0x17a538dd),
+ X(0x17b1c1d4), X(0x17be4d77), X(0x17cadbc5), X(0x17d76cbc),
+ X(0x17e4005e), X(0x17f096a7), X(0x17fd2f98), X(0x1809cb31),
+ X(0x1816696f), X(0x18230a53), X(0x182faddc), X(0x183c5408),
+ X(0x1848fcd8), X(0x1855a849), X(0x1862565d), X(0x186f0711),
+ X(0x187bba64), X(0x18887057), X(0x189528e9), X(0x18a1e418),
+ X(0x18aea1e3), X(0x18bb624b), X(0x18c8254e), X(0x18d4eaeb),
+ X(0x18e1b321), X(0x18ee7df1), X(0x18fb4b58), X(0x19081b57),
+ X(0x1914edec), X(0x1921c317), X(0x192e9ad6), X(0x193b7529),
+ X(0x19485210), X(0x19553189), X(0x19621393), X(0x196ef82e),
+ X(0x197bdf59), X(0x1988c913), X(0x1995b55c), X(0x19a2a432),
+ X(0x19af9595), X(0x19bc8983), X(0x19c97ffd), X(0x19d67900),
+ X(0x19e3748e), X(0x19f072a3), X(0x19fd7341), X(0x1a0a7665),
+ X(0x1a177c10), X(0x1a248440), X(0x1a318ef4), X(0x1a3e9c2c),
+ X(0x1a4babe7), X(0x1a58be24), X(0x1a65d2e2), X(0x1a72ea20),
+ X(0x1a8003de), X(0x1a8d201a), X(0x1a9a3ed5), X(0x1aa7600c),
+ X(0x1ab483bf), X(0x1ac1a9ee), X(0x1aced297), X(0x1adbfdba),
+ X(0x1ae92b56), X(0x1af65b69), X(0x1b038df4), X(0x1b10c2f5),
+ X(0x1b1dfa6b), X(0x1b2b3456), X(0x1b3870b5), X(0x1b45af87),
+ X(0x1b52f0ca), X(0x1b60347f), X(0x1b6d7aa4), X(0x1b7ac339),
+ X(0x1b880e3c), X(0x1b955bad), X(0x1ba2ab8b), X(0x1baffdd5),
+ X(0x1bbd528a), X(0x1bcaa9a9), X(0x1bd80332), X(0x1be55f24),
+ X(0x1bf2bd7d), X(0x1c001e3d), X(0x1c0d8164), X(0x1c1ae6ef),
+ X(0x1c284edf), X(0x1c35b932), X(0x1c4325e7), X(0x1c5094fe),
+ X(0x1c5e0677), X(0x1c6b7a4f), X(0x1c78f086), X(0x1c86691b),
+ X(0x1c93e40d), X(0x1ca1615c), X(0x1caee107), X(0x1cbc630c),
+ X(0x1cc9e76b), X(0x1cd76e23), X(0x1ce4f733), X(0x1cf2829a),
+ X(0x1d001057), X(0x1d0da06a), X(0x1d1b32d1), X(0x1d28c78c),
+ X(0x1d365e9a), X(0x1d43f7f9), X(0x1d5193a9), X(0x1d5f31aa),
+ X(0x1d6cd1f9), X(0x1d7a7497), X(0x1d881982), X(0x1d95c0ba),
+ X(0x1da36a3d), X(0x1db1160a), X(0x1dbec422), X(0x1dcc7482),
+ X(0x1dda272b), X(0x1de7dc1a), X(0x1df59350), X(0x1e034ccb),
+ X(0x1e11088a), X(0x1e1ec68c), X(0x1e2c86d1), X(0x1e3a4958),
+ X(0x1e480e20), X(0x1e55d527), X(0x1e639e6d), X(0x1e7169f1),
+ X(0x1e7f37b2), X(0x1e8d07b0), X(0x1e9ad9e8), X(0x1ea8ae5b),
+ X(0x1eb68507), X(0x1ec45dec), X(0x1ed23908), X(0x1ee0165b),
+ X(0x1eedf5e4), X(0x1efbd7a1), X(0x1f09bb92), X(0x1f17a1b6),
+ X(0x1f258a0d), X(0x1f337494), X(0x1f41614b), X(0x1f4f5032),
+ X(0x1f5d4147), X(0x1f6b3489), X(0x1f7929f7), X(0x1f872192),
+ X(0x1f951b56), X(0x1fa31744), X(0x1fb1155b), X(0x1fbf159a),
+ X(0x1fcd17ff), X(0x1fdb1c8b), X(0x1fe9233b), X(0x1ff72c0f),
+ X(0x20053706), X(0x20134420), X(0x2021535a), X(0x202f64b4),
+ X(0x203d782e), X(0x204b8dc6), X(0x2059a57c), X(0x2067bf4e),
+ X(0x2075db3b), X(0x2083f943), X(0x20921964), X(0x20a03b9e),
+ X(0x20ae5fef), X(0x20bc8657), X(0x20caaed5), X(0x20d8d967),
+ X(0x20e7060e), X(0x20f534c7), X(0x21036592), X(0x2111986e),
+ X(0x211fcd59), X(0x212e0454), X(0x213c3d5d), X(0x214a7873),
+ X(0x2158b594), X(0x2166f4c1), X(0x217535f8), X(0x21837938),
+ X(0x2191be81), X(0x21a005d0), X(0x21ae4f26), X(0x21bc9a81),
+ X(0x21cae7e0), X(0x21d93743), X(0x21e788a8), X(0x21f5dc0e),
+ X(0x22043174), X(0x221288da), X(0x2220e23e), X(0x222f3da0),
+ X(0x223d9afe), X(0x224bfa58), X(0x225a5bac), X(0x2268bef9),
+ X(0x2277243f), X(0x22858b7d), X(0x2293f4b0), X(0x22a25fda),
+ X(0x22b0ccf8), X(0x22bf3c09), X(0x22cdad0d), X(0x22dc2002),
+ X(0x22ea94e8), X(0x22f90bbe), X(0x23078482), X(0x2315ff33),
+ X(0x23247bd1), X(0x2332fa5b), X(0x23417acf), X(0x234ffd2c),
+ X(0x235e8173), X(0x236d07a0), X(0x237b8fb4), X(0x238a19ae),
+ X(0x2398a58c), X(0x23a7334d), X(0x23b5c2f1), X(0x23c45477),
+ X(0x23d2e7dd), X(0x23e17d22), X(0x23f01446), X(0x23fead47),
+ X(0x240d4825), X(0x241be4dd), X(0x242a8371), X(0x243923dd),
+ X(0x2447c622), X(0x24566a3e), X(0x24651031), X(0x2473b7f8),
+ X(0x24826194), X(0x24910d03), X(0x249fba44), X(0x24ae6957),
+ X(0x24bd1a39), X(0x24cbccea), X(0x24da816a), X(0x24e937b7),
+ X(0x24f7efcf), X(0x2506a9b3), X(0x25156560), X(0x252422d6),
+ X(0x2532e215), X(0x2541a31a), X(0x255065e4), X(0x255f2a74),
+ X(0x256df0c7), X(0x257cb8dd), X(0x258b82b4), X(0x259a4e4c),
+ X(0x25a91ba4), X(0x25b7eaba), X(0x25c6bb8e), X(0x25d58e1e),
+ X(0x25e46269), X(0x25f3386e), X(0x2602102d), X(0x2610e9a4),
+ X(0x261fc4d3), X(0x262ea1b7), X(0x263d8050), X(0x264c609e),
+ X(0x265b429e), X(0x266a2650), X(0x26790bb3), X(0x2687f2c6),
+ X(0x2696db88), X(0x26a5c5f7), X(0x26b4b213), X(0x26c39fda),
+ X(0x26d28f4c), X(0x26e18067), X(0x26f0732b), X(0x26ff6796),
+ X(0x270e5da7), X(0x271d555d), X(0x272c4eb7), X(0x273b49b5),
+ X(0x274a4654), X(0x27594495), X(0x27684475), X(0x277745f4),
+ X(0x27864910), X(0x27954dc9), X(0x27a4541e), X(0x27b35c0d),
+ X(0x27c26596), X(0x27d170b7), X(0x27e07d6f), X(0x27ef8bbd),
+ X(0x27fe9ba0), X(0x280dad18), X(0x281cc022), X(0x282bd4be),
+ X(0x283aeaeb), X(0x284a02a7), X(0x28591bf2), X(0x286836cb),
+ X(0x28775330), X(0x28867120), X(0x2895909b), X(0x28a4b19e),
+ X(0x28b3d42a), X(0x28c2f83d), X(0x28d21dd5), X(0x28e144f3),
+ X(0x28f06d94), X(0x28ff97b8), X(0x290ec35d), X(0x291df082),
+ X(0x292d1f27), X(0x293c4f4a), X(0x294b80eb), X(0x295ab407),
+ X(0x2969e89e), X(0x29791eaf), X(0x29885639), X(0x29978f3b),
+ X(0x29a6c9b3), X(0x29b605a0), X(0x29c54302), X(0x29d481d7),
+ X(0x29e3c21e), X(0x29f303d6), X(0x2a0246fd), X(0x2a118b94),
+ X(0x2a20d198), X(0x2a301909), X(0x2a3f61e6), X(0x2a4eac2c),
+ X(0x2a5df7dc), X(0x2a6d44f4), X(0x2a7c9374), X(0x2a8be359),
+ X(0x2a9b34a2), X(0x2aaa8750), X(0x2ab9db60), X(0x2ac930d1),
+ X(0x2ad887a3), X(0x2ae7dfd3), X(0x2af73962), X(0x2b06944e),
+ X(0x2b15f096), X(0x2b254e38), X(0x2b34ad34), X(0x2b440d89),
+ X(0x2b536f34), X(0x2b62d236), X(0x2b72368d), X(0x2b819c38),
+ X(0x2b910336), X(0x2ba06b86), X(0x2bafd526), X(0x2bbf4015),
+ X(0x2bceac53), X(0x2bde19de), X(0x2bed88b5), X(0x2bfcf8d7),
+ X(0x2c0c6a43), X(0x2c1bdcf7), X(0x2c2b50f3), X(0x2c3ac635),
+ X(0x2c4a3cbd), X(0x2c59b488), X(0x2c692d97), X(0x2c78a7e7),
+ X(0x2c882378), X(0x2c97a049), X(0x2ca71e58), X(0x2cb69da4),
+ X(0x2cc61e2c), X(0x2cd59ff0), X(0x2ce522ed), X(0x2cf4a723),
+ X(0x2d042c90), X(0x2d13b334), X(0x2d233b0d), X(0x2d32c41a),
+ X(0x2d424e5a), X(0x2d51d9cc), X(0x2d61666e), X(0x2d70f440),
+ X(0x2d808340), X(0x2d90136e), X(0x2d9fa4c7), X(0x2daf374c),
+ X(0x2dbecafa), X(0x2dce5fd1), X(0x2dddf5cf), X(0x2ded8cf4),
+ X(0x2dfd253d), X(0x2e0cbeab), X(0x2e1c593b), X(0x2e2bf4ed),
+ X(0x2e3b91c0), X(0x2e4b2fb1), X(0x2e5acec1), X(0x2e6a6eee),
+ X(0x2e7a1037), X(0x2e89b29b), X(0x2e995618), X(0x2ea8faad),
+ X(0x2eb8a05a), X(0x2ec8471c), X(0x2ed7eef4), X(0x2ee797df),
+ X(0x2ef741dc), X(0x2f06eceb), X(0x2f16990a), X(0x2f264639),
+ X(0x2f35f475), X(0x2f45a3bd), X(0x2f555412), X(0x2f650570),
+ X(0x2f74b7d8), X(0x2f846b48), X(0x2f941fbe), X(0x2fa3d53a),
+ X(0x2fb38bbb), X(0x2fc3433f), X(0x2fd2fbc5), X(0x2fe2b54c),
+ X(0x2ff26fd3), X(0x30022b58), X(0x3011e7db), X(0x3021a55a),
+ X(0x303163d4), X(0x30412348), X(0x3050e3b5), X(0x3060a519),
+ X(0x30706773), X(0x30802ac3), X(0x308fef06), X(0x309fb43d),
+ X(0x30af7a65), X(0x30bf417d), X(0x30cf0985), X(0x30ded27a),
+ X(0x30ee9c5d), X(0x30fe672b), X(0x310e32e3), X(0x311dff85),
+ X(0x312dcd0f), X(0x313d9b80), X(0x314d6ad7), X(0x315d3b12),
+ X(0x316d0c30), X(0x317cde31), X(0x318cb113), X(0x319c84d4),
+ X(0x31ac5974), X(0x31bc2ef1), X(0x31cc054b), X(0x31dbdc7f),
+ X(0x31ebb48e), X(0x31fb8d74), X(0x320b6733), X(0x321b41c7),
+ X(0x322b1d31), X(0x323af96e), X(0x324ad67e), X(0x325ab45f),
+ X(0x326a9311), X(0x327a7291), X(0x328a52e0), X(0x329a33fb),
+ X(0x32aa15e1), X(0x32b9f892), X(0x32c9dc0c), X(0x32d9c04d),
+ X(0x32e9a555), X(0x32f98b22), X(0x330971b4), X(0x33195909),
+ X(0x3329411f), X(0x333929f6), X(0x3349138c), X(0x3358fde1),
+ X(0x3368e8f2), X(0x3378d4c0), X(0x3388c147), X(0x3398ae89),
+ X(0x33a89c82), X(0x33b88b32), X(0x33c87a98), X(0x33d86ab2),
+ X(0x33e85b80), X(0x33f84d00), X(0x34083f30), X(0x34183210),
+ X(0x3428259f), X(0x343819db), X(0x34480ec3), X(0x34580455),
+ X(0x3467fa92), X(0x3477f176), X(0x3487e902), X(0x3497e134),
+ X(0x34a7da0a), X(0x34b7d384), X(0x34c7cda0), X(0x34d7c85e),
+ X(0x34e7c3bb), X(0x34f7bfb7), X(0x3507bc50), X(0x3517b985),
+ X(0x3527b756), X(0x3537b5c0), X(0x3547b4c3), X(0x3557b45d),
+ X(0x3567b48d), X(0x3577b552), X(0x3587b6aa), X(0x3597b895),
+ X(0x35a7bb12), X(0x35b7be1e), X(0x35c7c1b9), X(0x35d7c5e1),
+ X(0x35e7ca96), X(0x35f7cfd6), X(0x3607d5a0), X(0x3617dbf3),
+ X(0x3627e2cd), X(0x3637ea2d), X(0x3647f212), X(0x3657fa7b),
+ X(0x36680366), X(0x36780cd2), X(0x368816bf), X(0x3698212b),
+ X(0x36a82c14), X(0x36b83779), X(0x36c8435a), X(0x36d84fb4),
+ X(0x36e85c88), X(0x36f869d2), X(0x37087793), X(0x371885c9),
+ X(0x37289473), X(0x3738a38f), X(0x3748b31d), X(0x3758c31a),
+ X(0x3768d387), X(0x3778e461), X(0x3788f5a7), X(0x37990759),
+ X(0x37a91975), X(0x37b92bf9), X(0x37c93ee4), X(0x37d95236),
+ X(0x37e965ed), X(0x37f97a08), X(0x38098e85), X(0x3819a363),
+ X(0x3829b8a2), X(0x3839ce3f), X(0x3849e43a), X(0x3859fa91),
+ X(0x386a1143), X(0x387a284f), X(0x388a3fb4), X(0x389a5770),
+ X(0x38aa6f83), X(0x38ba87ea), X(0x38caa0a5), X(0x38dab9b2),
+ X(0x38ead311), X(0x38faecbf), X(0x390b06bc), X(0x391b2107),
+ X(0x392b3b9e), X(0x393b5680), X(0x394b71ac), X(0x395b8d20),
+ X(0x396ba8dc), X(0x397bc4dd), X(0x398be124), X(0x399bfdae),
+ X(0x39ac1a7a), X(0x39bc3788), X(0x39cc54d5), X(0x39dc7261),
+ X(0x39ec902a), X(0x39fcae2f), X(0x3a0ccc70), X(0x3a1ceaea),
+ X(0x3a2d099c), X(0x3a3d2885), X(0x3a4d47a5), X(0x3a5d66f9),
+ X(0x3a6d8680), X(0x3a7da63a), X(0x3a8dc625), X(0x3a9de63f),
+ X(0x3aae0688), X(0x3abe26fe), X(0x3ace47a0), X(0x3ade686d),
+ X(0x3aee8963), X(0x3afeaa82), X(0x3b0ecbc7), X(0x3b1eed32),
+ X(0x3b2f0ec2), X(0x3b3f3075), X(0x3b4f524a), X(0x3b5f7440),
+ X(0x3b6f9656), X(0x3b7fb889), X(0x3b8fdada), X(0x3b9ffd46),
+ X(0x3bb01fce), X(0x3bc0426e), X(0x3bd06526), X(0x3be087f6),
+ X(0x3bf0aada), X(0x3c00cdd4), X(0x3c10f0e0), X(0x3c2113fe),
+ X(0x3c31372d), X(0x3c415a6b), X(0x3c517db7), X(0x3c61a110),
+ X(0x3c71c475), X(0x3c81e7e4), X(0x3c920b5c), X(0x3ca22edc),
+ X(0x3cb25262), X(0x3cc275ee), X(0x3cd2997e), X(0x3ce2bd11),
+ X(0x3cf2e0a6), X(0x3d03043b), X(0x3d1327cf), X(0x3d234b61),
+ X(0x3d336ef0), X(0x3d43927a), X(0x3d53b5ff), X(0x3d63d97c),
+ X(0x3d73fcf1), X(0x3d84205c), X(0x3d9443bd), X(0x3da46711),
+ X(0x3db48a58), X(0x3dc4ad91), X(0x3dd4d0ba), X(0x3de4f3d1),
+ X(0x3df516d7), X(0x3e0539c9), X(0x3e155ca6), X(0x3e257f6d),
+ X(0x3e35a21d), X(0x3e45c4b4), X(0x3e55e731), X(0x3e660994),
+ X(0x3e762bda), X(0x3e864e03), X(0x3e96700d), X(0x3ea691f7),
+ X(0x3eb6b3bf), X(0x3ec6d565), X(0x3ed6f6e8), X(0x3ee71845),
+ X(0x3ef7397c), X(0x3f075a8c), X(0x3f177b73), X(0x3f279c30),
+ X(0x3f37bcc2), X(0x3f47dd27), X(0x3f57fd5f), X(0x3f681d68),
+ X(0x3f783d40), X(0x3f885ce7), X(0x3f987c5c), X(0x3fa89b9c),
+ X(0x3fb8baa7), X(0x3fc8d97c), X(0x3fd8f819), X(0x3fe9167e),
+ X(0x3ff934a8), X(0x40095296), X(0x40197049), X(0x40298dbd),
+ X(0x4039aaf2), X(0x4049c7e7), X(0x4059e49a), X(0x406a010a),
+ X(0x407a1d36), X(0x408a391d), X(0x409a54bd), X(0x40aa7015),
+ X(0x40ba8b25), X(0x40caa5ea), X(0x40dac063), X(0x40eada90),
+ X(0x40faf46e), X(0x410b0dfe), X(0x411b273d), X(0x412b402a),
+ X(0x413b58c4), X(0x414b710a), X(0x415b88fa), X(0x416ba093),
+ X(0x417bb7d5), X(0x418bcebe), X(0x419be54c), X(0x41abfb7e),
+ X(0x41bc1153), X(0x41cc26ca), X(0x41dc3be2), X(0x41ec5099),
+ X(0x41fc64ef), X(0x420c78e1), X(0x421c8c6f), X(0x422c9f97),
+ X(0x423cb258), X(0x424cc4b2), X(0x425cd6a2), X(0x426ce827),
+ X(0x427cf941), X(0x428d09ee), X(0x429d1a2c), X(0x42ad29fb),
+ X(0x42bd3959), X(0x42cd4846), X(0x42dd56bf), X(0x42ed64c3),
+ X(0x42fd7252), X(0x430d7f6a), X(0x431d8c0a), X(0x432d9831),
+ X(0x433da3dd), X(0x434daf0d), X(0x435db9c0), X(0x436dc3f5),
+ X(0x437dcdab), X(0x438dd6df), X(0x439ddf92), X(0x43ade7c1),
+ X(0x43bdef6c), X(0x43cdf691), X(0x43ddfd2f), X(0x43ee0345),
+ X(0x43fe08d2), X(0x440e0dd4), X(0x441e124b), X(0x442e1634),
+ X(0x443e198f), X(0x444e1c5a), X(0x445e1e95), X(0x446e203e),
+ X(0x447e2153), X(0x448e21d5), X(0x449e21c0), X(0x44ae2115),
+ X(0x44be1fd1), X(0x44ce1df4), X(0x44de1b7d), X(0x44ee186a),
+ X(0x44fe14ba), X(0x450e106b), X(0x451e0b7e), X(0x452e05ef),
+ X(0x453dffbf), X(0x454df8eb), X(0x455df173), X(0x456de956),
+ X(0x457de092), X(0x458dd726), X(0x459dcd10), X(0x45adc251),
+ X(0x45bdb6e5), X(0x45cdaacd), X(0x45dd9e06), X(0x45ed9091),
+ X(0x45fd826a), X(0x460d7392), X(0x461d6407), X(0x462d53c8),
+ X(0x463d42d4), X(0x464d3129), X(0x465d1ec6), X(0x466d0baa),
+ X(0x467cf7d3), X(0x468ce342), X(0x469ccdf3), X(0x46acb7e7),
+ X(0x46bca11c), X(0x46cc8990), X(0x46dc7143), X(0x46ec5833),
+ X(0x46fc3e5f), X(0x470c23c6), X(0x471c0867), X(0x472bec40),
+ X(0x473bcf50), X(0x474bb196), X(0x475b9311), X(0x476b73c0),
+ X(0x477b53a1), X(0x478b32b4), X(0x479b10f6), X(0x47aaee67),
+ X(0x47bacb06), X(0x47caa6d1), X(0x47da81c7), X(0x47ea5be7),
+ X(0x47fa3530), X(0x480a0da1), X(0x4819e537), X(0x4829bbf3),
+ X(0x483991d3), X(0x484966d6), X(0x48593afb), X(0x48690e3f),
+ X(0x4878e0a3), X(0x4888b225), X(0x489882c4), X(0x48a8527e),
+ X(0x48b82153), X(0x48c7ef41), X(0x48d7bc47), X(0x48e78863),
+ X(0x48f75396), X(0x49071ddc), X(0x4916e736), X(0x4926afa2),
+ X(0x4936771f), X(0x49463dac), X(0x49560347), X(0x4965c7ef),
+ X(0x49758ba4), X(0x49854e63), X(0x4995102c), X(0x49a4d0fe),
+ X(0x49b490d7), X(0x49c44fb6), X(0x49d40d9a), X(0x49e3ca82),
+ X(0x49f3866c), X(0x4a034159), X(0x4a12fb45), X(0x4a22b430),
+ X(0x4a326c19), X(0x4a4222ff), X(0x4a51d8e1), X(0x4a618dbd),
+ X(0x4a714192), X(0x4a80f45f), X(0x4a90a623), X(0x4aa056dd),
+ X(0x4ab0068b), X(0x4abfb52c), X(0x4acf62c0), X(0x4adf0f44),
+ X(0x4aeebab9), X(0x4afe651c), X(0x4b0e0e6c), X(0x4b1db6a9),
+ X(0x4b2d5dd1), X(0x4b3d03e2), X(0x4b4ca8dd), X(0x4b5c4cbf),
+ X(0x4b6bef88), X(0x4b7b9136), X(0x4b8b31c8), X(0x4b9ad13d),
+ X(0x4baa6f93), X(0x4bba0ccb), X(0x4bc9a8e2), X(0x4bd943d7),
+ X(0x4be8dda9), X(0x4bf87658), X(0x4c080de1), X(0x4c17a444),
+ X(0x4c27397f), X(0x4c36cd92), X(0x4c46607b), X(0x4c55f239),
+ X(0x4c6582cb), X(0x4c75122f), X(0x4c84a065), X(0x4c942d6c),
+ X(0x4ca3b942), X(0x4cb343e6), X(0x4cc2cd57), X(0x4cd25594),
+ X(0x4ce1dc9c), X(0x4cf1626d), X(0x4d00e707), X(0x4d106a68),
+ X(0x4d1fec8f), X(0x4d2f6d7a), X(0x4d3eed2a), X(0x4d4e6b9d),
+ X(0x4d5de8d1), X(0x4d6d64c5), X(0x4d7cdf79), X(0x4d8c58eb),
+ X(0x4d9bd11a), X(0x4dab4804), X(0x4dbabdaa), X(0x4dca3209),
+ X(0x4dd9a520), X(0x4de916ef), X(0x4df88774), X(0x4e07f6ae),
+ X(0x4e17649c), X(0x4e26d13c), X(0x4e363c8f), X(0x4e45a692),
+ X(0x4e550f44), X(0x4e6476a4), X(0x4e73dcb2), X(0x4e83416c),
+ X(0x4e92a4d1), X(0x4ea206df), X(0x4eb16796), X(0x4ec0c6f5),
+ X(0x4ed024fa), X(0x4edf81a5), X(0x4eeedcf3), X(0x4efe36e5),
+ X(0x4f0d8f79), X(0x4f1ce6ad), X(0x4f2c3c82), X(0x4f3b90f4),
+ X(0x4f4ae405), X(0x4f5a35b1), X(0x4f6985fa), X(0x4f78d4dc),
+ X(0x4f882257), X(0x4f976e6a), X(0x4fa6b914), X(0x4fb60254),
+ X(0x4fc54a28), X(0x4fd49090), X(0x4fe3d58b), X(0x4ff31917),
+ X(0x50025b33), X(0x50119bde), X(0x5020db17), X(0x503018dd),
+ X(0x503f552f), X(0x504e900b), X(0x505dc971), X(0x506d0160),
+ X(0x507c37d7), X(0x508b6cd3), X(0x509aa055), X(0x50a9d25b),
+ X(0x50b902e4), X(0x50c831ef), X(0x50d75f7b), X(0x50e68b87),
+ X(0x50f5b612), X(0x5104df1a), X(0x5114069f), X(0x51232ca0),
+ X(0x5132511a), X(0x5141740f), X(0x5150957b), X(0x515fb55f),
+ X(0x516ed3b8), X(0x517df087), X(0x518d0bca), X(0x519c257f),
+ X(0x51ab3da7), X(0x51ba543f), X(0x51c96947), X(0x51d87cbd),
+ X(0x51e78ea1), X(0x51f69ef1), X(0x5205adad), X(0x5214bad3),
+ X(0x5223c662), X(0x5232d05a), X(0x5241d8b9), X(0x5250df7d),
+ X(0x525fe4a7), X(0x526ee835), X(0x527dea26), X(0x528cea78),
+ X(0x529be92c), X(0x52aae63f), X(0x52b9e1b0), X(0x52c8db80),
+ X(0x52d7d3ac), X(0x52e6ca33), X(0x52f5bf15), X(0x5304b251),
+ X(0x5313a3e5), X(0x532293d0), X(0x53318212), X(0x53406ea8),
+ X(0x534f5993), X(0x535e42d2), X(0x536d2a62), X(0x537c1043),
+ X(0x538af475), X(0x5399d6f6), X(0x53a8b7c4), X(0x53b796e0),
+ X(0x53c67447), X(0x53d54ffa), X(0x53e429f6), X(0x53f3023b),
+ X(0x5401d8c8), X(0x5410ad9c), X(0x541f80b5), X(0x542e5213),
+ X(0x543d21b5), X(0x544bef9a), X(0x545abbc0), X(0x54698627),
+ X(0x54784ece), X(0x548715b3), X(0x5495dad6), X(0x54a49e35),
+ X(0x54b35fd0), X(0x54c21fa6), X(0x54d0ddb5), X(0x54df99fd),
+ X(0x54ee547c), X(0x54fd0d32), X(0x550bc41d), X(0x551a793d),
+ X(0x55292c91), X(0x5537de16), X(0x55468dce), X(0x55553bb6),
+ X(0x5563e7cd), X(0x55729213), X(0x55813a87), X(0x558fe127),
+ X(0x559e85f2), X(0x55ad28e9), X(0x55bbca08), X(0x55ca6950),
+ X(0x55d906c0), X(0x55e7a257), X(0x55f63c13), X(0x5604d3f4),
+ X(0x561369f8), X(0x5621fe1f), X(0x56309067), X(0x563f20d1),
+ X(0x564daf5a), X(0x565c3c02), X(0x566ac6c7), X(0x56794faa),
+ X(0x5687d6a8), X(0x56965bc1), X(0x56a4def4), X(0x56b36040),
+ X(0x56c1dfa4), X(0x56d05d1f), X(0x56ded8af), X(0x56ed5255),
+ X(0x56fbca0f), X(0x570a3fdc), X(0x5718b3bc), X(0x572725ac),
+ X(0x573595ad), X(0x574403bd), X(0x57526fdb), X(0x5760da07),
+ X(0x576f423f), X(0x577da883), X(0x578c0cd1), X(0x579a6f29),
+ X(0x57a8cf8a), X(0x57b72df2), X(0x57c58a61), X(0x57d3e4d6),
+ X(0x57e23d50), X(0x57f093cd), X(0x57fee84e), X(0x580d3ad1),
+ X(0x581b8b54), X(0x5829d9d8), X(0x5838265c), X(0x584670dd),
+ X(0x5854b95c), X(0x5862ffd8), X(0x5871444f), X(0x587f86c1),
+ X(0x588dc72c), X(0x589c0591), X(0x58aa41ed), X(0x58b87c40),
+ X(0x58c6b489), X(0x58d4eac7), X(0x58e31ef9), X(0x58f1511f),
+ X(0x58ff8137), X(0x590daf40), X(0x591bdb3a), X(0x592a0524),
+ X(0x59382cfc), X(0x594652c2), X(0x59547675), X(0x59629815),
+ X(0x5970b79f), X(0x597ed513), X(0x598cf071), X(0x599b09b7),
+ X(0x59a920e5), X(0x59b735f9), X(0x59c548f4), X(0x59d359d2),
+ X(0x59e16895), X(0x59ef753b), X(0x59fd7fc4), X(0x5a0b882d),
+ X(0x5a198e77), X(0x5a2792a0), X(0x5a3594a9), X(0x5a43948e),
+ X(0x5a519251), X(0x5a5f8df0), X(0x5a6d876a), X(0x5a7b7ebe),
+ X(0x5a8973ec), X(0x5a9766f2), X(0x5aa557d0), X(0x5ab34685),
+ X(0x5ac1330f), X(0x5acf1d6f), X(0x5add05a3), X(0x5aeaebaa),
+ X(0x5af8cf84), X(0x5b06b12f), X(0x5b1490ab), X(0x5b226df7),
+ X(0x5b304912), X(0x5b3e21fc), X(0x5b4bf8b2), X(0x5b59cd35),
+ X(0x5b679f84), X(0x5b756f9e), X(0x5b833d82), X(0x5b91092e),
+ X(0x5b9ed2a3), X(0x5bac99e0), X(0x5bba5ee3), X(0x5bc821ac),
+ X(0x5bd5e23a), X(0x5be3a08c), X(0x5bf15ca1), X(0x5bff1679),
+ X(0x5c0cce12), X(0x5c1a836c), X(0x5c283686), X(0x5c35e760),
+ X(0x5c4395f7), X(0x5c51424c), X(0x5c5eec5e), X(0x5c6c942b),
+ X(0x5c7a39b4), X(0x5c87dcf7), X(0x5c957df3), X(0x5ca31ca8),
+ X(0x5cb0b915), X(0x5cbe5338), X(0x5ccbeb12), X(0x5cd980a1),
+ X(0x5ce713e5), X(0x5cf4a4dd), X(0x5d023387), X(0x5d0fbfe4),
+ X(0x5d1d49f2), X(0x5d2ad1b1), X(0x5d38571f), X(0x5d45da3c),
+ X(0x5d535b08), X(0x5d60d981), X(0x5d6e55a7), X(0x5d7bcf78),
+ X(0x5d8946f5), X(0x5d96bc1c), X(0x5da42eec), X(0x5db19f65),
+ X(0x5dbf0d86), X(0x5dcc794e), X(0x5dd9e2bd), X(0x5de749d1),
+ X(0x5df4ae8a), X(0x5e0210e7), X(0x5e0f70e7), X(0x5e1cce8a),
+ X(0x5e2a29ce), X(0x5e3782b4), X(0x5e44d93a), X(0x5e522d5f),
+ X(0x5e5f7f23), X(0x5e6cce85), X(0x5e7a1b85), X(0x5e876620),
+ X(0x5e94ae58), X(0x5ea1f42a), X(0x5eaf3797), X(0x5ebc789d),
+ X(0x5ec9b73c), X(0x5ed6f372), X(0x5ee42d41), X(0x5ef164a5),
+ X(0x5efe999f), X(0x5f0bcc2f), X(0x5f18fc52), X(0x5f262a09),
+ X(0x5f335553), X(0x5f407e2f), X(0x5f4da49d), X(0x5f5ac89b),
+ X(0x5f67ea29), X(0x5f750946), X(0x5f8225f2), X(0x5f8f402b),
+ X(0x5f9c57f2), X(0x5fa96d44), X(0x5fb68023), X(0x5fc3908c),
+ X(0x5fd09e7f), X(0x5fdda9fc), X(0x5feab302), X(0x5ff7b990),
+ X(0x6004bda5), X(0x6011bf40), X(0x601ebe62), X(0x602bbb09),
+ X(0x6038b534), X(0x6045ace4), X(0x6052a216), X(0x605f94cb),
+ X(0x606c8502), X(0x607972b9), X(0x60865df2), X(0x609346aa),
+ X(0x60a02ce1), X(0x60ad1096), X(0x60b9f1c9), X(0x60c6d079),
+ X(0x60d3aca5), X(0x60e0864d), X(0x60ed5d70), X(0x60fa320d),
+ X(0x61070424), X(0x6113d3b4), X(0x6120a0bc), X(0x612d6b3c),
+ X(0x613a3332), X(0x6146f89f), X(0x6153bb82), X(0x61607bd9),
+ X(0x616d39a5), X(0x6179f4e5), X(0x6186ad98), X(0x619363bd),
+ X(0x61a01753), X(0x61acc85b), X(0x61b976d3), X(0x61c622bc),
+ X(0x61d2cc13), X(0x61df72d8), X(0x61ec170c), X(0x61f8b8ad),
+ X(0x620557ba), X(0x6211f434), X(0x621e8e18), X(0x622b2568),
+ X(0x6237ba21), X(0x62444c44), X(0x6250dbd0), X(0x625d68c4),
+ X(0x6269f320), X(0x62767ae2), X(0x6283000b), X(0x628f829a),
+ X(0x629c028e), X(0x62a87fe6), X(0x62b4faa2), X(0x62c172c2),
+ X(0x62cde844), X(0x62da5b29), X(0x62e6cb6e), X(0x62f33915),
+ X(0x62ffa41c), X(0x630c0c83), X(0x63187248), X(0x6324d56d),
+ X(0x633135ef), X(0x633d93ce), X(0x6349ef0b), X(0x635647a3),
+ X(0x63629d97), X(0x636ef0e6), X(0x637b418f), X(0x63878f92),
+ X(0x6393daef), X(0x63a023a4), X(0x63ac69b1), X(0x63b8ad15),
+ X(0x63c4edd1), X(0x63d12be3), X(0x63dd674b), X(0x63e9a008),
+ X(0x63f5d61a), X(0x64020980), X(0x640e3a39), X(0x641a6846),
+ X(0x642693a5), X(0x6432bc56), X(0x643ee258), X(0x644b05ab),
+ X(0x6457264e), X(0x64634441), X(0x646f5f83), X(0x647b7814),
+ X(0x64878df3), X(0x6493a120), X(0x649fb199), X(0x64abbf5f),
+ X(0x64b7ca71), X(0x64c3d2ce), X(0x64cfd877), X(0x64dbdb69),
+ X(0x64e7dba6), X(0x64f3d92b), X(0x64ffd3fa), X(0x650bcc11),
+ X(0x6517c16f), X(0x6523b415), X(0x652fa402), X(0x653b9134),
+ X(0x65477bad), X(0x6553636a), X(0x655f486d), X(0x656b2ab3),
+ X(0x65770a3d), X(0x6582e70a), X(0x658ec11a), X(0x659a986d),
+ X(0x65a66d00), X(0x65b23ed5), X(0x65be0deb), X(0x65c9da41),
+ X(0x65d5a3d7), X(0x65e16aac), X(0x65ed2ebf), X(0x65f8f011),
+ X(0x6604aea1), X(0x66106a6e), X(0x661c2377), X(0x6627d9be),
+ X(0x66338d40), X(0x663f3dfd), X(0x664aebf5), X(0x66569728),
+ X(0x66623f95), X(0x666de53b), X(0x6679881b), X(0x66852833),
+ X(0x6690c583), X(0x669c600b), X(0x66a7f7ca), X(0x66b38cc0),
+ X(0x66bf1eec), X(0x66caae4f), X(0x66d63ae6), X(0x66e1c4b3),
+ X(0x66ed4bb4), X(0x66f8cfea), X(0x67045153), X(0x670fcfef),
+ X(0x671b4bbe), X(0x6726c4bf), X(0x67323af3), X(0x673dae58),
+ X(0x67491eee), X(0x67548cb5), X(0x675ff7ab), X(0x676b5fd2),
+ X(0x6776c528), X(0x678227ad), X(0x678d8761), X(0x6798e443),
+ X(0x67a43e52), X(0x67af958f), X(0x67bae9f9), X(0x67c63b8f),
+ X(0x67d18a52), X(0x67dcd640), X(0x67e81f59), X(0x67f3659d),
+ X(0x67fea90c), X(0x6809e9a5), X(0x68152768), X(0x68206254),
+ X(0x682b9a68), X(0x6836cfa6), X(0x6842020b), X(0x684d3199),
+ X(0x68585e4d), X(0x68638829), X(0x686eaf2b), X(0x6879d354),
+ X(0x6884f4a2), X(0x68901316), X(0x689b2eb0), X(0x68a6476d),
+ X(0x68b15d50), X(0x68bc7056), X(0x68c78080), X(0x68d28dcd),
+ X(0x68dd983e), X(0x68e89fd0), X(0x68f3a486), X(0x68fea65d),
+ X(0x6909a555), X(0x6914a16f), X(0x691f9aa9), X(0x692a9104),
+ X(0x69358480), X(0x6940751b), X(0x694b62d5), X(0x69564daf),
+ X(0x696135a7), X(0x696c1abe), X(0x6976fcf3), X(0x6981dc46),
+ X(0x698cb8b6), X(0x69979243), X(0x69a268ed), X(0x69ad3cb4),
+ X(0x69b80d97), X(0x69c2db96), X(0x69cda6b0), X(0x69d86ee5),
+ X(0x69e33436), X(0x69edf6a1), X(0x69f8b626), X(0x6a0372c5),
+ X(0x6a0e2c7e), X(0x6a18e350), X(0x6a23973c), X(0x6a2e4840),
+ X(0x6a38f65d), X(0x6a43a191), X(0x6a4e49de), X(0x6a58ef42),
+ X(0x6a6391be), X(0x6a6e3151), X(0x6a78cdfa), X(0x6a8367ba),
+ X(0x6a8dfe90), X(0x6a98927c), X(0x6aa3237d), X(0x6aadb194),
+ X(0x6ab83cc0), X(0x6ac2c500), X(0x6acd4a55), X(0x6ad7ccbf),
+ X(0x6ae24c3c), X(0x6aecc8cd), X(0x6af74271), X(0x6b01b929),
+ X(0x6b0c2cf4), X(0x6b169dd1), X(0x6b210bc1), X(0x6b2b76c2),
+ X(0x6b35ded6), X(0x6b4043fc), X(0x6b4aa632), X(0x6b55057a),
+ X(0x6b5f61d3), X(0x6b69bb3d), X(0x6b7411b7), X(0x6b7e6541),
+ X(0x6b88b5db), X(0x6b930385), X(0x6b9d4e3f), X(0x6ba79607),
+ X(0x6bb1dadf), X(0x6bbc1cc6), X(0x6bc65bbb), X(0x6bd097bf),
+ X(0x6bdad0d0), X(0x6be506f0), X(0x6bef3a1d), X(0x6bf96a58),
+ X(0x6c0397a0), X(0x6c0dc1f5), X(0x6c17e957), X(0x6c220dc6),
+ X(0x6c2c2f41), X(0x6c364dc9), X(0x6c40695c), X(0x6c4a81fc),
+ X(0x6c5497a7), X(0x6c5eaa5d), X(0x6c68ba1f), X(0x6c72c6eb),
+ X(0x6c7cd0c3), X(0x6c86d7a6), X(0x6c90db92), X(0x6c9adc8a),
+ X(0x6ca4da8b), X(0x6caed596), X(0x6cb8cdab), X(0x6cc2c2ca),
+ X(0x6cccb4f2), X(0x6cd6a424), X(0x6ce0905e), X(0x6cea79a1),
+ X(0x6cf45fee), X(0x6cfe4342), X(0x6d0823a0), X(0x6d120105),
+ X(0x6d1bdb73), X(0x6d25b2e8), X(0x6d2f8765), X(0x6d3958ea),
+ X(0x6d432777), X(0x6d4cf30a), X(0x6d56bba5), X(0x6d608147),
+ X(0x6d6a43f0), X(0x6d7403a0), X(0x6d7dc056), X(0x6d877a13),
+ X(0x6d9130d6), X(0x6d9ae4a0), X(0x6da4956f), X(0x6dae4345),
+ X(0x6db7ee20), X(0x6dc19601), X(0x6dcb3ae7), X(0x6dd4dcd3),
+ X(0x6dde7bc4), X(0x6de817bb), X(0x6df1b0b6), X(0x6dfb46b7),
+ X(0x6e04d9bc), X(0x6e0e69c7), X(0x6e17f6d5), X(0x6e2180e9),
+ X(0x6e2b0801), X(0x6e348c1d), X(0x6e3e0d3d), X(0x6e478b62),
+ X(0x6e51068a), X(0x6e5a7eb7), X(0x6e63f3e7), X(0x6e6d661b),
+ X(0x6e76d552), X(0x6e80418e), X(0x6e89aacc), X(0x6e93110f),
+ X(0x6e9c7454), X(0x6ea5d49d), X(0x6eaf31e9), X(0x6eb88c37),
+ X(0x6ec1e389), X(0x6ecb37de), X(0x6ed48936), X(0x6eddd790),
+ X(0x6ee722ee), X(0x6ef06b4d), X(0x6ef9b0b0), X(0x6f02f315),
+ X(0x6f0c327c), X(0x6f156ee6), X(0x6f1ea852), X(0x6f27dec1),
+ X(0x6f311232), X(0x6f3a42a5), X(0x6f43701a), X(0x6f4c9a91),
+ X(0x6f55c20a), X(0x6f5ee686), X(0x6f680803), X(0x6f712682),
+ X(0x6f7a4203), X(0x6f835a86), X(0x6f8c700b), X(0x6f958291),
+ X(0x6f9e921a), X(0x6fa79ea4), X(0x6fb0a830), X(0x6fb9aebd),
+ X(0x6fc2b24c), X(0x6fcbb2dd), X(0x6fd4b06f), X(0x6fddab03),
+ X(0x6fe6a299), X(0x6fef9730), X(0x6ff888c9), X(0x70017763),
+ X(0x700a62ff), X(0x70134b9c), X(0x701c313b), X(0x702513dc),
+ X(0x702df37e), X(0x7036d021), X(0x703fa9c6), X(0x7048806d),
+ X(0x70515415), X(0x705a24bf), X(0x7062f26b), X(0x706bbd17),
+ X(0x707484c6), X(0x707d4976), X(0x70860b28), X(0x708ec9dc),
+ X(0x70978591), X(0x70a03e48), X(0x70a8f400), X(0x70b1a6bb),
+ X(0x70ba5677), X(0x70c30335), X(0x70cbacf5), X(0x70d453b6),
+ X(0x70dcf77a), X(0x70e59840), X(0x70ee3607), X(0x70f6d0d1),
+ X(0x70ff689d), X(0x7107fd6b), X(0x71108f3b), X(0x71191e0d),
+ X(0x7121a9e2), X(0x712a32b9), X(0x7132b892), X(0x713b3b6e),
+ X(0x7143bb4c), X(0x714c382d), X(0x7154b211), X(0x715d28f7),
+ X(0x71659ce0), X(0x716e0dcc), X(0x71767bbb), X(0x717ee6ac),
+ X(0x71874ea1), X(0x718fb399), X(0x71981594), X(0x71a07493),
+ X(0x71a8d094), X(0x71b1299a), X(0x71b97fa2), X(0x71c1d2af),
+ X(0x71ca22bf), X(0x71d26fd2), X(0x71dab9ea), X(0x71e30106),
+ X(0x71eb4526), X(0x71f3864a), X(0x71fbc472), X(0x7203ff9e),
+ X(0x720c37cf), X(0x72146d05), X(0x721c9f3f), X(0x7224ce7e),
+ X(0x722cfac2), X(0x7235240b), X(0x723d4a59), X(0x72456dad),
+ X(0x724d8e05), X(0x7255ab63), X(0x725dc5c7), X(0x7265dd31),
+ X(0x726df1a0), X(0x72760315), X(0x727e1191), X(0x72861d12),
+ X(0x728e259a), X(0x72962b28), X(0x729e2dbd), X(0x72a62d59),
+ X(0x72ae29fc), X(0x72b623a5), X(0x72be1a56), X(0x72c60e0e),
+ X(0x72cdfece), X(0x72d5ec95), X(0x72ddd764), X(0x72e5bf3b),
+ X(0x72eda41a), X(0x72f58601), X(0x72fd64f1), X(0x730540e9),
+ X(0x730d19e9), X(0x7314eff3), X(0x731cc305), X(0x73249321),
+ X(0x732c6046), X(0x73342a75), X(0x733bf1ad), X(0x7343b5ef),
+ X(0x734b773b), X(0x73533591), X(0x735af0f2), X(0x7362a95d),
+ X(0x736a5ed3), X(0x73721153), X(0x7379c0df), X(0x73816d76),
+ X(0x73891719), X(0x7390bdc7), X(0x73986181), X(0x73a00247),
+ X(0x73a7a01a), X(0x73af3af8), X(0x73b6d2e4), X(0x73be67dc),
+ X(0x73c5f9e1), X(0x73cd88f3), X(0x73d51513), X(0x73dc9e40),
+ X(0x73e4247c), X(0x73eba7c5), X(0x73f3281c), X(0x73faa582),
+ X(0x74021ff7), X(0x7409977b), X(0x74110c0d), X(0x74187daf),
+ X(0x741fec61), X(0x74275822), X(0x742ec0f3), X(0x743626d5),
+ X(0x743d89c7), X(0x7444e9c9), X(0x744c46dd), X(0x7453a101),
+ X(0x745af837), X(0x74624c7f), X(0x74699dd8), X(0x7470ec44),
+ X(0x747837c2), X(0x747f8052), X(0x7486c5f5), X(0x748e08ac),
+ X(0x74954875), X(0x749c8552), X(0x74a3bf43), X(0x74aaf648),
+ X(0x74b22a62), X(0x74b95b90), X(0x74c089d2), X(0x74c7b52a),
+ X(0x74cedd97), X(0x74d6031a), X(0x74dd25b2), X(0x74e44561),
+ X(0x74eb6226), X(0x74f27c02), X(0x74f992f5), X(0x7500a6ff),
+ X(0x7507b820), X(0x750ec659), X(0x7515d1aa), X(0x751cda14),
+ X(0x7523df96), X(0x752ae231), X(0x7531e1e5), X(0x7538deb2),
+ X(0x753fd89a), X(0x7546cf9b), X(0x754dc3b7), X(0x7554b4ed),
+ X(0x755ba33e), X(0x75628eaa), X(0x75697732), X(0x75705cd5),
+ X(0x75773f95), X(0x757e1f71), X(0x7584fc6a), X(0x758bd67f),
+ X(0x7592adb2), X(0x75998203), X(0x75a05371), X(0x75a721fe),
+ X(0x75adeda9), X(0x75b4b673), X(0x75bb7c5c), X(0x75c23f65),
+ X(0x75c8ff8d), X(0x75cfbcd6), X(0x75d6773f), X(0x75dd2ec8),
+ X(0x75e3e373), X(0x75ea953f), X(0x75f1442d), X(0x75f7f03d),
+ X(0x75fe996f), X(0x76053fc5), X(0x760be33d), X(0x761283d8),
+ X(0x76192197), X(0x761fbc7b), X(0x76265482), X(0x762ce9af),
+ X(0x76337c01), X(0x763a0b78), X(0x76409814), X(0x764721d7),
+ X(0x764da8c1), X(0x76542cd1), X(0x765aae08), X(0x76612c67),
+ X(0x7667a7ee), X(0x766e209d), X(0x76749675), X(0x767b0975),
+ X(0x7681799f), X(0x7687e6f3), X(0x768e5170), X(0x7694b918),
+ X(0x769b1deb), X(0x76a17fe9), X(0x76a7df13), X(0x76ae3b68),
+ X(0x76b494ea), X(0x76baeb98), X(0x76c13f74), X(0x76c7907c),
+ X(0x76cddeb3), X(0x76d42a18), X(0x76da72ab), X(0x76e0b86d),
+ X(0x76e6fb5e), X(0x76ed3b7f), X(0x76f378d0), X(0x76f9b352),
+ X(0x76ffeb05), X(0x77061fe8), X(0x770c51fe), X(0x77128145),
+ X(0x7718adbf), X(0x771ed76c), X(0x7724fe4c), X(0x772b225f),
+ X(0x773143a7), X(0x77376223), X(0x773d7dd3), X(0x774396ba),
+ X(0x7749acd5), X(0x774fc027), X(0x7755d0af), X(0x775bde6f),
+ X(0x7761e965), X(0x7767f193), X(0x776df6fa), X(0x7773f998),
+ X(0x7779f970), X(0x777ff681), X(0x7785f0cd), X(0x778be852),
+ X(0x7791dd12), X(0x7797cf0d), X(0x779dbe43), X(0x77a3aab6),
+ X(0x77a99465), X(0x77af7b50), X(0x77b55f79), X(0x77bb40e0),
+ X(0x77c11f85), X(0x77c6fb68), X(0x77ccd48a), X(0x77d2aaec),
+ X(0x77d87e8d), X(0x77de4f6f), X(0x77e41d92), X(0x77e9e8f5),
+ X(0x77efb19b), X(0x77f57782), X(0x77fb3aad), X(0x7800fb1a),
+ X(0x7806b8ca), X(0x780c73bf), X(0x78122bf7), X(0x7817e175),
+ X(0x781d9438), X(0x78234440), X(0x7828f18f), X(0x782e9c25),
+ X(0x78344401), X(0x7839e925), X(0x783f8b92), X(0x78452b46),
+ X(0x784ac844), X(0x7850628b), X(0x7855fa1c), X(0x785b8ef8),
+ X(0x7861211e), X(0x7866b090), X(0x786c3d4d), X(0x7871c757),
+ X(0x78774ead), X(0x787cd351), X(0x78825543), X(0x7887d483),
+ X(0x788d5111), X(0x7892caef), X(0x7898421c), X(0x789db69a),
+ X(0x78a32868), X(0x78a89787), X(0x78ae03f8), X(0x78b36dbb),
+ X(0x78b8d4d1), X(0x78be393a), X(0x78c39af6), X(0x78c8fa06),
+ X(0x78ce566c), X(0x78d3b026), X(0x78d90736), X(0x78de5b9c),
+ X(0x78e3ad58), X(0x78e8fc6c), X(0x78ee48d7), X(0x78f3929b),
+ X(0x78f8d9b7), X(0x78fe1e2c), X(0x79035ffb), X(0x79089f24),
+ X(0x790ddba8), X(0x79131587), X(0x79184cc2), X(0x791d8159),
+ X(0x7922b34d), X(0x7927e29e), X(0x792d0f4d), X(0x7932395a),
+ X(0x793760c6), X(0x793c8591), X(0x7941a7bd), X(0x7946c749),
+ X(0x794be435), X(0x7950fe84), X(0x79561634), X(0x795b2b47),
+ X(0x79603dbc), X(0x79654d96), X(0x796a5ad4), X(0x796f6576),
+ X(0x79746d7e), X(0x797972eb), X(0x797e75bf), X(0x798375f9),
+ X(0x7988739b), X(0x798d6ea5), X(0x79926717), X(0x79975cf2),
+ X(0x799c5037), X(0x79a140e6), X(0x79a62f00), X(0x79ab1a85),
+ X(0x79b00376), X(0x79b4e9d3), X(0x79b9cd9d), X(0x79beaed4),
+ X(0x79c38d79), X(0x79c8698d), X(0x79cd4310), X(0x79d21a03),
+ X(0x79d6ee66), X(0x79dbc03a), X(0x79e08f7f), X(0x79e55c36),
+ X(0x79ea265f), X(0x79eeedfc), X(0x79f3b30c), X(0x79f87590),
+ X(0x79fd3589), X(0x7a01f2f7), X(0x7a06addc), X(0x7a0b6636),
+ X(0x7a101c08), X(0x7a14cf52), X(0x7a198013), X(0x7a1e2e4d),
+ X(0x7a22da01), X(0x7a27832f), X(0x7a2c29d7), X(0x7a30cdfa),
+ X(0x7a356f99), X(0x7a3a0eb4), X(0x7a3eab4c), X(0x7a434561),
+ X(0x7a47dcf5), X(0x7a4c7207), X(0x7a510498), X(0x7a5594a9),
+ X(0x7a5a223a), X(0x7a5ead4d), X(0x7a6335e0), X(0x7a67bbf6),
+ X(0x7a6c3f8f), X(0x7a70c0ab), X(0x7a753f4b), X(0x7a79bb6f),
+ X(0x7a7e3519), X(0x7a82ac48), X(0x7a8720fe), X(0x7a8b933b),
+ X(0x7a9002ff), X(0x7a94704b), X(0x7a98db20), X(0x7a9d437e),
+ X(0x7aa1a967), X(0x7aa60cd9), X(0x7aaa6dd7), X(0x7aaecc61),
+ X(0x7ab32877), X(0x7ab7821b), X(0x7abbd94b), X(0x7ac02e0a),
+ X(0x7ac48058), X(0x7ac8d035), X(0x7acd1da3), X(0x7ad168a1),
+ X(0x7ad5b130), X(0x7ad9f751), X(0x7ade3b05), X(0x7ae27c4c),
+ X(0x7ae6bb27), X(0x7aeaf796), X(0x7aef319a), X(0x7af36934),
+ X(0x7af79e64), X(0x7afbd12c), X(0x7b00018a), X(0x7b042f81),
+ X(0x7b085b10), X(0x7b0c8439), X(0x7b10aafc), X(0x7b14cf5a),
+ X(0x7b18f153), X(0x7b1d10e8), X(0x7b212e1a), X(0x7b2548e9),
+ X(0x7b296155), X(0x7b2d7761), X(0x7b318b0b), X(0x7b359c55),
+ X(0x7b39ab3f), X(0x7b3db7cb), X(0x7b41c1f8), X(0x7b45c9c8),
+ X(0x7b49cf3b), X(0x7b4dd251), X(0x7b51d30b), X(0x7b55d16b),
+ X(0x7b59cd70), X(0x7b5dc71b), X(0x7b61be6d), X(0x7b65b366),
+ X(0x7b69a608), X(0x7b6d9653), X(0x7b718447), X(0x7b756fe5),
+ X(0x7b79592e), X(0x7b7d4022), X(0x7b8124c3), X(0x7b850710),
+ X(0x7b88e70a), X(0x7b8cc4b3), X(0x7b90a00a), X(0x7b947911),
+ X(0x7b984fc8), X(0x7b9c242f), X(0x7b9ff648), X(0x7ba3c612),
+ X(0x7ba79390), X(0x7bab5ec1), X(0x7baf27a5), X(0x7bb2ee3f),
+ X(0x7bb6b28e), X(0x7bba7493), X(0x7bbe344e), X(0x7bc1f1c1),
+ X(0x7bc5acec), X(0x7bc965cf), X(0x7bcd1c6c), X(0x7bd0d0c3),
+ X(0x7bd482d4), X(0x7bd832a1), X(0x7bdbe02a), X(0x7bdf8b70),
+ X(0x7be33473), X(0x7be6db34), X(0x7bea7fb4), X(0x7bee21f4),
+ X(0x7bf1c1f3), X(0x7bf55fb3), X(0x7bf8fb35), X(0x7bfc9479),
+ X(0x7c002b7f), X(0x7c03c04a), X(0x7c0752d8), X(0x7c0ae32b),
+ X(0x7c0e7144), X(0x7c11fd23), X(0x7c1586c9), X(0x7c190e36),
+ X(0x7c1c936c), X(0x7c20166b), X(0x7c239733), X(0x7c2715c6),
+ X(0x7c2a9224), X(0x7c2e0c4e), X(0x7c318444), X(0x7c34fa07),
+ X(0x7c386d98), X(0x7c3bdef8), X(0x7c3f4e26), X(0x7c42bb25),
+ X(0x7c4625f4), X(0x7c498e95), X(0x7c4cf507), X(0x7c50594c),
+ X(0x7c53bb65), X(0x7c571b51), X(0x7c5a7913), X(0x7c5dd4aa),
+ X(0x7c612e17), X(0x7c64855b), X(0x7c67da76), X(0x7c6b2d6a),
+ X(0x7c6e7e37), X(0x7c71ccdd), X(0x7c75195e), X(0x7c7863ba),
+ X(0x7c7babf1), X(0x7c7ef206), X(0x7c8235f7), X(0x7c8577c6),
+ X(0x7c88b774), X(0x7c8bf502), X(0x7c8f306f), X(0x7c9269bd),
+ X(0x7c95a0ec), X(0x7c98d5fe), X(0x7c9c08f2), X(0x7c9f39cb),
+ X(0x7ca26887), X(0x7ca59528), X(0x7ca8bfb0), X(0x7cabe81d),
+ X(0x7caf0e72), X(0x7cb232af), X(0x7cb554d4), X(0x7cb874e2),
+ X(0x7cbb92db), X(0x7cbeaebe), X(0x7cc1c88d), X(0x7cc4e047),
+ X(0x7cc7f5ef), X(0x7ccb0984), X(0x7cce1b08), X(0x7cd12a7b),
+ X(0x7cd437dd), X(0x7cd74330), X(0x7cda4c74), X(0x7cdd53aa),
+ X(0x7ce058d3), X(0x7ce35bef), X(0x7ce65cff), X(0x7ce95c04),
+ X(0x7cec58ff), X(0x7cef53f0), X(0x7cf24cd7), X(0x7cf543b7),
+ X(0x7cf8388f), X(0x7cfb2b60), X(0x7cfe1c2b), X(0x7d010af1),
+ X(0x7d03f7b2), X(0x7d06e26f), X(0x7d09cb29), X(0x7d0cb1e0),
+ X(0x7d0f9696), X(0x7d12794b), X(0x7d1559ff), X(0x7d1838b4),
+ X(0x7d1b156a), X(0x7d1df022), X(0x7d20c8dd), X(0x7d239f9b),
+ X(0x7d26745e), X(0x7d294725), X(0x7d2c17f1), X(0x7d2ee6c4),
+ X(0x7d31b39f), X(0x7d347e81), X(0x7d37476b), X(0x7d3a0e5f),
+ X(0x7d3cd35d), X(0x7d3f9665), X(0x7d425779), X(0x7d451699),
+ X(0x7d47d3c6), X(0x7d4a8f01), X(0x7d4d484b), X(0x7d4fffa3),
+ X(0x7d52b50c), X(0x7d556885), X(0x7d581a0f), X(0x7d5ac9ac),
+ X(0x7d5d775c), X(0x7d60231f), X(0x7d62ccf6), X(0x7d6574e3),
+ X(0x7d681ae6), X(0x7d6abeff), X(0x7d6d612f), X(0x7d700178),
+ X(0x7d729fd9), X(0x7d753c54), X(0x7d77d6e9), X(0x7d7a6f9a),
+ X(0x7d7d0666), X(0x7d7f9b4f), X(0x7d822e55), X(0x7d84bf79),
+ X(0x7d874ebc), X(0x7d89dc1e), X(0x7d8c67a1), X(0x7d8ef144),
+ X(0x7d91790a), X(0x7d93fef2), X(0x7d9682fd), X(0x7d99052d),
+ X(0x7d9b8581), X(0x7d9e03fb), X(0x7da0809b), X(0x7da2fb62),
+ X(0x7da57451), X(0x7da7eb68), X(0x7daa60a8), X(0x7dacd413),
+ X(0x7daf45a9), X(0x7db1b56a), X(0x7db42357), X(0x7db68f71),
+ X(0x7db8f9b9), X(0x7dbb6230), X(0x7dbdc8d6), X(0x7dc02dac),
+ X(0x7dc290b3), X(0x7dc4f1eb), X(0x7dc75156), X(0x7dc9aef4),
+ X(0x7dcc0ac5), X(0x7dce64cc), X(0x7dd0bd07), X(0x7dd31379),
+ X(0x7dd56821), X(0x7dd7bb01), X(0x7dda0c1a), X(0x7ddc5b6b),
+ X(0x7ddea8f7), X(0x7de0f4bd), X(0x7de33ebe), X(0x7de586fc),
+ X(0x7de7cd76), X(0x7dea122e), X(0x7dec5525), X(0x7dee965a),
+ X(0x7df0d5d0), X(0x7df31386), X(0x7df54f7e), X(0x7df789b8),
+ X(0x7df9c235), X(0x7dfbf8f5), X(0x7dfe2dfa), X(0x7e006145),
+ X(0x7e0292d5), X(0x7e04c2ac), X(0x7e06f0cb), X(0x7e091d32),
+ X(0x7e0b47e1), X(0x7e0d70db), X(0x7e0f981f), X(0x7e11bdaf),
+ X(0x7e13e18a), X(0x7e1603b3), X(0x7e182429), X(0x7e1a42ed),
+ X(0x7e1c6001), X(0x7e1e7b64), X(0x7e209518), X(0x7e22ad1d),
+ X(0x7e24c375), X(0x7e26d81f), X(0x7e28eb1d), X(0x7e2afc70),
+ X(0x7e2d0c17), X(0x7e2f1a15), X(0x7e31266a), X(0x7e333115),
+ X(0x7e353a1a), X(0x7e374177), X(0x7e39472e), X(0x7e3b4b3f),
+ X(0x7e3d4dac), X(0x7e3f4e75), X(0x7e414d9a), X(0x7e434b1e),
+ X(0x7e4546ff), X(0x7e474140), X(0x7e4939e0), X(0x7e4b30e2),
+ X(0x7e4d2644), X(0x7e4f1a09), X(0x7e510c30), X(0x7e52fcbc),
+ X(0x7e54ebab), X(0x7e56d900), X(0x7e58c4bb), X(0x7e5aaedd),
+ X(0x7e5c9766), X(0x7e5e7e57), X(0x7e6063b2), X(0x7e624776),
+ X(0x7e6429a5), X(0x7e660a3f), X(0x7e67e945), X(0x7e69c6b8),
+ X(0x7e6ba299), X(0x7e6d7ce7), X(0x7e6f55a5), X(0x7e712cd3),
+ X(0x7e730272), X(0x7e74d682), X(0x7e76a904), X(0x7e7879f9),
+ X(0x7e7a4962), X(0x7e7c173f), X(0x7e7de392), X(0x7e7fae5a),
+ X(0x7e817799), X(0x7e833f50), X(0x7e85057f), X(0x7e86ca27),
+ X(0x7e888d49), X(0x7e8a4ee5), X(0x7e8c0efd), X(0x7e8dcd91),
+ X(0x7e8f8aa1), X(0x7e914630), X(0x7e93003c), X(0x7e94b8c8),
+ X(0x7e966fd4), X(0x7e982560), X(0x7e99d96e), X(0x7e9b8bfe),
+ X(0x7e9d3d10), X(0x7e9eeca7), X(0x7ea09ac2), X(0x7ea24762),
+ X(0x7ea3f288), X(0x7ea59c35), X(0x7ea7446a), X(0x7ea8eb27),
+ X(0x7eaa906c), X(0x7eac343c), X(0x7eadd696), X(0x7eaf777b),
+ X(0x7eb116ed), X(0x7eb2b4eb), X(0x7eb45177), X(0x7eb5ec91),
+ X(0x7eb7863b), X(0x7eb91e74), X(0x7ebab53e), X(0x7ebc4a99),
+ X(0x7ebdde87), X(0x7ebf7107), X(0x7ec1021b), X(0x7ec291c3),
+ X(0x7ec42001), X(0x7ec5acd5), X(0x7ec7383f), X(0x7ec8c241),
+ X(0x7eca4adb), X(0x7ecbd20d), X(0x7ecd57da), X(0x7ecedc41),
+ X(0x7ed05f44), X(0x7ed1e0e2), X(0x7ed3611d), X(0x7ed4dff6),
+ X(0x7ed65d6d), X(0x7ed7d983), X(0x7ed95438), X(0x7edacd8f),
+ X(0x7edc4586), X(0x7eddbc20), X(0x7edf315c), X(0x7ee0a53c),
+ X(0x7ee217c1), X(0x7ee388ea), X(0x7ee4f8b9), X(0x7ee6672f),
+ X(0x7ee7d44c), X(0x7ee94012), X(0x7eeaaa80), X(0x7eec1397),
+ X(0x7eed7b59), X(0x7eeee1c6), X(0x7ef046df), X(0x7ef1aaa5),
+ X(0x7ef30d18), X(0x7ef46e39), X(0x7ef5ce09), X(0x7ef72c88),
+ X(0x7ef889b8), X(0x7ef9e599), X(0x7efb402c), X(0x7efc9972),
+ X(0x7efdf16b), X(0x7eff4818), X(0x7f009d79), X(0x7f01f191),
+ X(0x7f03445f), X(0x7f0495e4), X(0x7f05e620), X(0x7f073516),
+ X(0x7f0882c5), X(0x7f09cf2d), X(0x7f0b1a51), X(0x7f0c6430),
+ X(0x7f0daccc), X(0x7f0ef425), X(0x7f103a3b), X(0x7f117f11),
+ X(0x7f12c2a5), X(0x7f1404fa), X(0x7f15460f), X(0x7f1685e6),
+ X(0x7f17c47f), X(0x7f1901db), X(0x7f1a3dfb), X(0x7f1b78e0),
+ X(0x7f1cb28a), X(0x7f1deafa), X(0x7f1f2231), X(0x7f20582f),
+ X(0x7f218cf5), X(0x7f22c085), X(0x7f23f2de), X(0x7f252401),
+ X(0x7f2653f0), X(0x7f2782ab), X(0x7f28b032), X(0x7f29dc87),
+ X(0x7f2b07aa), X(0x7f2c319c), X(0x7f2d5a5e), X(0x7f2e81f0),
+ X(0x7f2fa853), X(0x7f30cd88), X(0x7f31f18f), X(0x7f33146a),
+ X(0x7f343619), X(0x7f35569c), X(0x7f3675f6), X(0x7f379425),
+ X(0x7f38b12c), X(0x7f39cd0a), X(0x7f3ae7c0), X(0x7f3c0150),
+ X(0x7f3d19ba), X(0x7f3e30fe), X(0x7f3f471e), X(0x7f405c1a),
+ X(0x7f416ff3), X(0x7f4282a9), X(0x7f43943e), X(0x7f44a4b2),
+ X(0x7f45b405), X(0x7f46c239), X(0x7f47cf4e), X(0x7f48db45),
+ X(0x7f49e61f), X(0x7f4aefdc), X(0x7f4bf87e), X(0x7f4d0004),
+ X(0x7f4e0670), X(0x7f4f0bc2), X(0x7f500ffb), X(0x7f51131c),
+ X(0x7f521525), X(0x7f531618), X(0x7f5415f4), X(0x7f5514bb),
+ X(0x7f56126e), X(0x7f570f0c), X(0x7f580a98), X(0x7f590511),
+ X(0x7f59fe78), X(0x7f5af6ce), X(0x7f5bee14), X(0x7f5ce44a),
+ X(0x7f5dd972), X(0x7f5ecd8b), X(0x7f5fc097), X(0x7f60b296),
+ X(0x7f61a389), X(0x7f629370), X(0x7f63824e), X(0x7f647021),
+ X(0x7f655ceb), X(0x7f6648ad), X(0x7f673367), X(0x7f681d19),
+ X(0x7f6905c6), X(0x7f69ed6d), X(0x7f6ad40f), X(0x7f6bb9ad),
+ X(0x7f6c9e48), X(0x7f6d81e0), X(0x7f6e6475), X(0x7f6f460a),
+ X(0x7f70269d), X(0x7f710631), X(0x7f71e4c6), X(0x7f72c25c),
+ X(0x7f739ef4), X(0x7f747a8f), X(0x7f75552e), X(0x7f762ed1),
+ X(0x7f770779), X(0x7f77df27), X(0x7f78b5db), X(0x7f798b97),
+ X(0x7f7a605a), X(0x7f7b3425), X(0x7f7c06fa), X(0x7f7cd8d9),
+ X(0x7f7da9c2), X(0x7f7e79b7), X(0x7f7f48b8), X(0x7f8016c5),
+ X(0x7f80e3e0), X(0x7f81b009), X(0x7f827b40), X(0x7f834588),
+ X(0x7f840edf), X(0x7f84d747), X(0x7f859ec1), X(0x7f86654d),
+ X(0x7f872aec), X(0x7f87ef9e), X(0x7f88b365), X(0x7f897641),
+ X(0x7f8a3832), X(0x7f8af93a), X(0x7f8bb959), X(0x7f8c7890),
+ X(0x7f8d36df), X(0x7f8df448), X(0x7f8eb0ca), X(0x7f8f6c67),
+ X(0x7f90271e), X(0x7f90e0f2), X(0x7f9199e2), X(0x7f9251f0),
+ X(0x7f93091b), X(0x7f93bf65), X(0x7f9474ce), X(0x7f952958),
+ X(0x7f95dd01), X(0x7f968fcd), X(0x7f9741ba), X(0x7f97f2ca),
+ X(0x7f98a2fd), X(0x7f995254), X(0x7f9a00d0), X(0x7f9aae71),
+ X(0x7f9b5b38), X(0x7f9c0726), X(0x7f9cb23b), X(0x7f9d5c78),
+ X(0x7f9e05de), X(0x7f9eae6e), X(0x7f9f5627), X(0x7f9ffd0b),
+ X(0x7fa0a31b), X(0x7fa14856), X(0x7fa1ecbf), X(0x7fa29054),
+ X(0x7fa33318), X(0x7fa3d50b), X(0x7fa4762c), X(0x7fa5167e),
+ X(0x7fa5b601), X(0x7fa654b5), X(0x7fa6f29b), X(0x7fa78fb3),
+ X(0x7fa82bff), X(0x7fa8c77f), X(0x7fa96234), X(0x7fa9fc1e),
+ X(0x7faa953e), X(0x7fab2d94), X(0x7fabc522), X(0x7fac5be8),
+ X(0x7facf1e6), X(0x7fad871d), X(0x7fae1b8f), X(0x7faeaf3b),
+ X(0x7faf4222), X(0x7fafd445), X(0x7fb065a4), X(0x7fb0f641),
+ X(0x7fb1861b), X(0x7fb21534), X(0x7fb2a38c), X(0x7fb33124),
+ X(0x7fb3bdfb), X(0x7fb44a14), X(0x7fb4d56f), X(0x7fb5600c),
+ X(0x7fb5e9ec), X(0x7fb6730f), X(0x7fb6fb76), X(0x7fb78323),
+ X(0x7fb80a15), X(0x7fb8904d), X(0x7fb915cc), X(0x7fb99a92),
+ X(0x7fba1ea0), X(0x7fbaa1f7), X(0x7fbb2497), X(0x7fbba681),
+ X(0x7fbc27b5), X(0x7fbca835), X(0x7fbd2801), X(0x7fbda719),
+ X(0x7fbe257e), X(0x7fbea331), X(0x7fbf2032), X(0x7fbf9c82),
+ X(0x7fc01821), X(0x7fc09311), X(0x7fc10d52), X(0x7fc186e4),
+ X(0x7fc1ffc8), X(0x7fc277ff), X(0x7fc2ef89), X(0x7fc36667),
+ X(0x7fc3dc9a), X(0x7fc45221), X(0x7fc4c6ff), X(0x7fc53b33),
+ X(0x7fc5aebe), X(0x7fc621a0), X(0x7fc693db), X(0x7fc7056f),
+ X(0x7fc7765c), X(0x7fc7e6a3), X(0x7fc85645), X(0x7fc8c542),
+ X(0x7fc9339b), X(0x7fc9a150), X(0x7fca0e63), X(0x7fca7ad3),
+ X(0x7fcae6a2), X(0x7fcb51cf), X(0x7fcbbc5c), X(0x7fcc2649),
+ X(0x7fcc8f97), X(0x7fccf846), X(0x7fcd6058), X(0x7fcdc7cb),
+ X(0x7fce2ea2), X(0x7fce94dd), X(0x7fcefa7b), X(0x7fcf5f7f),
+ X(0x7fcfc3e8), X(0x7fd027b7), X(0x7fd08aed), X(0x7fd0ed8b),
+ X(0x7fd14f90), X(0x7fd1b0fd), X(0x7fd211d4), X(0x7fd27214),
+ X(0x7fd2d1bf), X(0x7fd330d4), X(0x7fd38f55), X(0x7fd3ed41),
+ X(0x7fd44a9a), X(0x7fd4a761), X(0x7fd50395), X(0x7fd55f37),
+ X(0x7fd5ba48), X(0x7fd614c9), X(0x7fd66eba), X(0x7fd6c81b),
+ X(0x7fd720ed), X(0x7fd77932), X(0x7fd7d0e8), X(0x7fd82812),
+ X(0x7fd87eae), X(0x7fd8d4bf), X(0x7fd92a45), X(0x7fd97f40),
+ X(0x7fd9d3b0), X(0x7fda2797), X(0x7fda7af5), X(0x7fdacdca),
+ X(0x7fdb2018), X(0x7fdb71dd), X(0x7fdbc31c), X(0x7fdc13d5),
+ X(0x7fdc6408), X(0x7fdcb3b6), X(0x7fdd02df), X(0x7fdd5184),
+ X(0x7fdd9fa5), X(0x7fdded44), X(0x7fde3a60), X(0x7fde86fb),
+ X(0x7fded314), X(0x7fdf1eac), X(0x7fdf69c4), X(0x7fdfb45d),
+ X(0x7fdffe76), X(0x7fe04811), X(0x7fe0912e), X(0x7fe0d9ce),
+ X(0x7fe121f0), X(0x7fe16996), X(0x7fe1b0c1), X(0x7fe1f770),
+ X(0x7fe23da4), X(0x7fe2835f), X(0x7fe2c89f), X(0x7fe30d67),
+ X(0x7fe351b5), X(0x7fe3958c), X(0x7fe3d8ec), X(0x7fe41bd4),
+ X(0x7fe45e46), X(0x7fe4a042), X(0x7fe4e1c8), X(0x7fe522da),
+ X(0x7fe56378), X(0x7fe5a3a1), X(0x7fe5e358), X(0x7fe6229b),
+ X(0x7fe6616d), X(0x7fe69fcc), X(0x7fe6ddbb), X(0x7fe71b39),
+ X(0x7fe75847), X(0x7fe794e5), X(0x7fe7d114), X(0x7fe80cd5),
+ X(0x7fe84827), X(0x7fe8830c), X(0x7fe8bd84), X(0x7fe8f78f),
+ X(0x7fe9312f), X(0x7fe96a62), X(0x7fe9a32b), X(0x7fe9db8a),
+ X(0x7fea137e), X(0x7fea4b09), X(0x7fea822b), X(0x7feab8e5),
+ X(0x7feaef37), X(0x7feb2521), X(0x7feb5aa4), X(0x7feb8fc1),
+ X(0x7febc478), X(0x7febf8ca), X(0x7fec2cb6), X(0x7fec603e),
+ X(0x7fec9363), X(0x7fecc623), X(0x7fecf881), X(0x7fed2a7c),
+ X(0x7fed5c16), X(0x7fed8d4e), X(0x7fedbe24), X(0x7fedee9b),
+ X(0x7fee1eb1), X(0x7fee4e68), X(0x7fee7dc0), X(0x7feeacb9),
+ X(0x7feedb54), X(0x7fef0991), X(0x7fef3771), X(0x7fef64f5),
+ X(0x7fef921d), X(0x7fefbee8), X(0x7fefeb59), X(0x7ff0176f),
+ X(0x7ff0432a), X(0x7ff06e8c), X(0x7ff09995), X(0x7ff0c444),
+ X(0x7ff0ee9c), X(0x7ff1189b), X(0x7ff14243), X(0x7ff16b94),
+ X(0x7ff1948e), X(0x7ff1bd32), X(0x7ff1e581), X(0x7ff20d7b),
+ X(0x7ff2351f), X(0x7ff25c70), X(0x7ff2836d), X(0x7ff2aa17),
+ X(0x7ff2d06d), X(0x7ff2f672), X(0x7ff31c24), X(0x7ff34185),
+ X(0x7ff36695), X(0x7ff38b55), X(0x7ff3afc4), X(0x7ff3d3e4),
+ X(0x7ff3f7b4), X(0x7ff41b35), X(0x7ff43e69), X(0x7ff4614e),
+ X(0x7ff483e6), X(0x7ff4a631), X(0x7ff4c82f), X(0x7ff4e9e1),
+ X(0x7ff50b47), X(0x7ff52c62), X(0x7ff54d33), X(0x7ff56db9),
+ X(0x7ff58df5), X(0x7ff5ade7), X(0x7ff5cd90), X(0x7ff5ecf1),
+ X(0x7ff60c09), X(0x7ff62ada), X(0x7ff64963), X(0x7ff667a5),
+ X(0x7ff685a1), X(0x7ff6a357), X(0x7ff6c0c7), X(0x7ff6ddf1),
+ X(0x7ff6fad7), X(0x7ff71778), X(0x7ff733d6), X(0x7ff74fef),
+ X(0x7ff76bc6), X(0x7ff78759), X(0x7ff7a2ab), X(0x7ff7bdba),
+ X(0x7ff7d888), X(0x7ff7f315), X(0x7ff80d61), X(0x7ff8276c),
+ X(0x7ff84138), X(0x7ff85ac4), X(0x7ff87412), X(0x7ff88d20),
+ X(0x7ff8a5f0), X(0x7ff8be82), X(0x7ff8d6d7), X(0x7ff8eeef),
+ X(0x7ff906c9), X(0x7ff91e68), X(0x7ff935cb), X(0x7ff94cf2),
+ X(0x7ff963dd), X(0x7ff97a8f), X(0x7ff99105), X(0x7ff9a742),
+ X(0x7ff9bd45), X(0x7ff9d30f), X(0x7ff9e8a0), X(0x7ff9fdf9),
+ X(0x7ffa131a), X(0x7ffa2803), X(0x7ffa3cb4), X(0x7ffa512f),
+ X(0x7ffa6573), X(0x7ffa7981), X(0x7ffa8d59), X(0x7ffaa0fc),
+ X(0x7ffab46a), X(0x7ffac7a3), X(0x7ffadaa8), X(0x7ffaed78),
+ X(0x7ffb0015), X(0x7ffb127f), X(0x7ffb24b6), X(0x7ffb36bb),
+ X(0x7ffb488d), X(0x7ffb5a2e), X(0x7ffb6b9d), X(0x7ffb7cdb),
+ X(0x7ffb8de9), X(0x7ffb9ec6), X(0x7ffbaf73), X(0x7ffbbff1),
+ X(0x7ffbd03f), X(0x7ffbe05e), X(0x7ffbf04f), X(0x7ffc0012),
+ X(0x7ffc0fa6), X(0x7ffc1f0d), X(0x7ffc2e47), X(0x7ffc3d54),
+ X(0x7ffc4c35), X(0x7ffc5ae9), X(0x7ffc6971), X(0x7ffc77ce),
+ X(0x7ffc8600), X(0x7ffc9407), X(0x7ffca1e4), X(0x7ffcaf96),
+ X(0x7ffcbd1f), X(0x7ffcca7e), X(0x7ffcd7b4), X(0x7ffce4c1),
+ X(0x7ffcf1a5), X(0x7ffcfe62), X(0x7ffd0af6), X(0x7ffd1763),
+ X(0x7ffd23a9), X(0x7ffd2fc8), X(0x7ffd3bc1), X(0x7ffd4793),
+ X(0x7ffd533f), X(0x7ffd5ec5), X(0x7ffd6a27), X(0x7ffd7563),
+ X(0x7ffd807a), X(0x7ffd8b6e), X(0x7ffd963d), X(0x7ffda0e8),
+ X(0x7ffdab70), X(0x7ffdb5d5), X(0x7ffdc017), X(0x7ffdca36),
+ X(0x7ffdd434), X(0x7ffdde0f), X(0x7ffde7c9), X(0x7ffdf161),
+ X(0x7ffdfad8), X(0x7ffe042f), X(0x7ffe0d65), X(0x7ffe167b),
+ X(0x7ffe1f71), X(0x7ffe2848), X(0x7ffe30ff), X(0x7ffe3997),
+ X(0x7ffe4211), X(0x7ffe4a6c), X(0x7ffe52a9), X(0x7ffe5ac8),
+ X(0x7ffe62c9), X(0x7ffe6aae), X(0x7ffe7275), X(0x7ffe7a1f),
+ X(0x7ffe81ad), X(0x7ffe891f), X(0x7ffe9075), X(0x7ffe97b0),
+ X(0x7ffe9ece), X(0x7ffea5d2), X(0x7ffeacbb), X(0x7ffeb38a),
+ X(0x7ffeba3e), X(0x7ffec0d8), X(0x7ffec758), X(0x7ffecdbf),
+ X(0x7ffed40d), X(0x7ffeda41), X(0x7ffee05d), X(0x7ffee660),
+ X(0x7ffeec4b), X(0x7ffef21f), X(0x7ffef7da), X(0x7ffefd7e),
+ X(0x7fff030b), X(0x7fff0881), X(0x7fff0de0), X(0x7fff1328),
+ X(0x7fff185b), X(0x7fff1d77), X(0x7fff227e), X(0x7fff276f),
+ X(0x7fff2c4b), X(0x7fff3112), X(0x7fff35c4), X(0x7fff3a62),
+ X(0x7fff3eeb), X(0x7fff4360), X(0x7fff47c2), X(0x7fff4c0f),
+ X(0x7fff504a), X(0x7fff5471), X(0x7fff5885), X(0x7fff5c87),
+ X(0x7fff6076), X(0x7fff6452), X(0x7fff681d), X(0x7fff6bd6),
+ X(0x7fff6f7d), X(0x7fff7313), X(0x7fff7698), X(0x7fff7a0c),
+ X(0x7fff7d6f), X(0x7fff80c2), X(0x7fff8404), X(0x7fff8736),
+ X(0x7fff8a58), X(0x7fff8d6b), X(0x7fff906e), X(0x7fff9362),
+ X(0x7fff9646), X(0x7fff991c), X(0x7fff9be3), X(0x7fff9e9c),
+ X(0x7fffa146), X(0x7fffa3e2), X(0x7fffa671), X(0x7fffa8f1),
+ X(0x7fffab65), X(0x7fffadca), X(0x7fffb023), X(0x7fffb26f),
+ X(0x7fffb4ae), X(0x7fffb6e0), X(0x7fffb906), X(0x7fffbb20),
+ X(0x7fffbd2e), X(0x7fffbf30), X(0x7fffc126), X(0x7fffc311),
+ X(0x7fffc4f1), X(0x7fffc6c5), X(0x7fffc88f), X(0x7fffca4d),
+ X(0x7fffcc01), X(0x7fffcdab), X(0x7fffcf4a), X(0x7fffd0e0),
+ X(0x7fffd26b), X(0x7fffd3ec), X(0x7fffd564), X(0x7fffd6d2),
+ X(0x7fffd838), X(0x7fffd993), X(0x7fffdae6), X(0x7fffdc31),
+ X(0x7fffdd72), X(0x7fffdeab), X(0x7fffdfdb), X(0x7fffe104),
+ X(0x7fffe224), X(0x7fffe33c), X(0x7fffe44d), X(0x7fffe556),
+ X(0x7fffe657), X(0x7fffe751), X(0x7fffe844), X(0x7fffe930),
+ X(0x7fffea15), X(0x7fffeaf3), X(0x7fffebca), X(0x7fffec9b),
+ X(0x7fffed66), X(0x7fffee2a), X(0x7fffeee8), X(0x7fffefa0),
+ X(0x7ffff053), X(0x7ffff0ff), X(0x7ffff1a6), X(0x7ffff247),
+ X(0x7ffff2e4), X(0x7ffff37a), X(0x7ffff40c), X(0x7ffff499),
+ X(0x7ffff520), X(0x7ffff5a3), X(0x7ffff621), X(0x7ffff69b),
+ X(0x7ffff710), X(0x7ffff781), X(0x7ffff7ee), X(0x7ffff857),
+ X(0x7ffff8bb), X(0x7ffff91c), X(0x7ffff979), X(0x7ffff9d2),
+ X(0x7ffffa27), X(0x7ffffa79), X(0x7ffffac8), X(0x7ffffb13),
+ X(0x7ffffb5b), X(0x7ffffba0), X(0x7ffffbe2), X(0x7ffffc21),
+ X(0x7ffffc5d), X(0x7ffffc96), X(0x7ffffccd), X(0x7ffffd01),
+ X(0x7ffffd32), X(0x7ffffd61), X(0x7ffffd8e), X(0x7ffffdb8),
+ X(0x7ffffde0), X(0x7ffffe07), X(0x7ffffe2b), X(0x7ffffe4d),
+ X(0x7ffffe6d), X(0x7ffffe8b), X(0x7ffffea8), X(0x7ffffec3),
+ X(0x7ffffedc), X(0x7ffffef4), X(0x7fffff0a), X(0x7fffff1f),
+ X(0x7fffff33), X(0x7fffff45), X(0x7fffff56), X(0x7fffff66),
+ X(0x7fffff75), X(0x7fffff82), X(0x7fffff8f), X(0x7fffff9a),
+ X(0x7fffffa5), X(0x7fffffaf), X(0x7fffffb8), X(0x7fffffc0),
+ X(0x7fffffc8), X(0x7fffffce), X(0x7fffffd5), X(0x7fffffda),
+ X(0x7fffffdf), X(0x7fffffe4), X(0x7fffffe8), X(0x7fffffeb),
+ X(0x7fffffef), X(0x7ffffff1), X(0x7ffffff4), X(0x7ffffff6),
+ X(0x7ffffff8), X(0x7ffffff9), X(0x7ffffffb), X(0x7ffffffc),
+ X(0x7ffffffd), X(0x7ffffffd), X(0x7ffffffe), X(0x7fffffff),
+ X(0x7fffffff), X(0x7fffffff), X(0x7fffffff), X(0x7fffffff),
+ X(0x7fffffff), X(0x7fffffff), X(0x7fffffff), X(0x7fffffff),
+ X(0x7fffffff), X(0x7fffffff), X(0x7fffffff), X(0x7fffffff),
+};
+
+#endif
+#endif
+
diff --git a/tools/adk2inst/adk2inst.c b/tools/adk2inst/adk2inst.c
new file mode 100644
index 0000000..2db398a
--- /dev/null
+++ b/tools/adk2inst/adk2inst.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include <stdlib.h>
+
+// args are
+// path to adk2tool (without .exe)
+// serial port
+// path to bossac (without .exe)
+// binary to flash
+
+int main(int argc, char **argv)
+{
+ char strbuf[1024];
+
+ if (argc < 5) {
+ fprintf(stderr, "not enough args\n");
+ return 1;
+ }
+
+ snprintf(strbuf, sizeof(strbuf), "%s.exe %s erase", argv[1], argv[2]);
+ puts(strbuf);
+ fflush(stdout);
+ system(strbuf);
+
+ snprintf(strbuf, sizeof(strbuf), "%s.exe --port=%s -w -b %s", argv[3], argv[2], argv[4]);
+ puts(strbuf);
+ fflush(stdout);
+ system(strbuf);
+
+ snprintf(strbuf, sizeof(strbuf), "%s.exe %s reset", argv[1], argv[2]);
+ puts(strbuf);
+ fflush(stdout);
+ system(strbuf);
+
+ return 0;
+}
diff --git a/tools/adk2inst/makefile b/tools/adk2inst/makefile
new file mode 100644
index 0000000..6e113c4
--- /dev/null
+++ b/tools/adk2inst/makefile
@@ -0,0 +1,68 @@
+
+TARGET := adk2inst
+BUILDDIR := build-$(TARGET)
+
+# compiler flags, default libs to link against
+COMPILEFLAGS := -g -O2
+CFLAGS :=
+CPPFLAGS :=
+ASMFLAGS :=
+LDFLAGS :=
+LDLIBS :=
+
+UNAME := $(shell uname -s)
+ARCH := $(shell uname -m)
+
+# switch any platform specific stuff here
+# ifeq ($(findstring CYGWIN,$(UNAME)),CYGWIN)
+# ...
+# endif
+ifeq ($(UNAME),Darwin)
+COMPILEFLAGS += -arch i386
+LDFLAGS += -arch i386
+endif
+ifeq ($(UNAME),Linux)
+COMPILEFLAGS += -m32
+LDFLAGS += -m32
+endif
+
+CFLAGS += $(COMPILEFLAGS)
+CPPFLAGS += $(COMPILEFLAGS)
+ASMFLAGS += $(COMPILEFLAGS)
+
+OBJS := adk2inst.o
+
+OBJS := $(addprefix $(BUILDDIR)/,$(OBJS))
+
+DEPS := $(OBJS:.o=.d)
+
+$(BUILDDIR)/$(TARGET): $(OBJS)
+ $(CC) $(LDFLAGS) $(OBJS) -o $@ $(LDLIBS)
+
+clean:
+ rm -f $(OBJS) $(DEPS) $(TARGET)
+
+spotless:
+ rm -rf build-*
+
+# makes sure the target dir exists
+MKDIR = if [ ! -d $(dir $@) ]; then mkdir -p $(dir $@); fi
+
+$(BUILDDIR)/%.o: %.c
+ @$(MKDIR)
+ @echo compiling $<
+ $(CC) $(CFLAGS) -c $< -MD -MT $@ -MF $(@:%o=%d) -o $@
+
+$(BUILDDIR)/%.o: %.cpp
+ @$(MKDIR)
+ @echo compiling $<
+ @$(CC) $(CPPFLAGS) -c $< -MD -MT $@ -MF $(@:%o=%d) -o $@
+
+$(BUILDDIR)/%.o: %.S
+ @$(MKDIR)
+ @echo compiling $<
+ @$(CC) $(ASMFLAGS) -c $< -MD -MT $@ -MF $(@:%o=%d) -o $@
+
+ifeq ($(filter $(MAKECMDGOALS), clean), )
+-include $(DEPS)
+endif
diff --git a/tools/adk2tool/adk2tool.c b/tools/adk2tool/adk2tool.c
new file mode 100644
index 0000000..914bbbe
--- /dev/null
+++ b/tools/adk2tool/adk2tool.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <fcntl.h>
+
+#include "serial.h"
+
+/* RTS is erase, asserted high */
+static void set_erase(int en)
+{
+ serial_set_rts(en);
+}
+
+static int get_erase(void)
+{
+ return serial_get_rts();
+}
+
+/* DTR is reset, asserted low */
+static void set_reset(int en)
+{
+ serial_set_dtr(!en);
+}
+
+static int get_reset(void)
+{
+ return !serial_get_dtr();
+}
+
+static void secret_knock(void)
+{
+ int i;
+ const int magic = 0xac5a;
+
+ set_reset(1);
+ set_erase(0);
+
+ for (i = 0; i < 16; i++) {
+ set_erase(!(~(magic >> i) & 1));
+ set_reset(0);
+ usleep(1000);
+ set_reset(1);
+ }
+ set_erase(0);
+ set_reset(0);
+}
+
+#ifndef __WIN32
+#include <termios.h>
+#include <poll.h>
+
+/* raw terminal stuff */
+static struct termios oldstdin;
+static struct termios oldstdout;
+
+
+static void resetconsole(void)
+{
+ tcsetattr(0, TCSANOW, &oldstdin);
+ tcsetattr(1, TCSANOW, &oldstdout);
+}
+
+static void setconsole(void)
+{
+ struct termios t;
+
+ tcgetattr(0, &oldstdin);
+ tcgetattr(1, &oldstdout);
+
+ atexit(&resetconsole);
+
+ t = oldstdin;
+ t.c_lflag = ISIG; // no input processing
+ // Don't interpret various control characters, pass them through instead
+ t.c_cc[VINTR] = t.c_cc[VQUIT] = t.c_cc[VSUSP] = '\0';
+ t.c_cc[VMIN] = 0; // nonblocking read
+ t.c_cc[VTIME] = 0; // nonblocking read
+ tcsetattr(0, TCSANOW, &t);
+
+ fcntl(0, F_SETFL, O_NONBLOCK);
+
+ t = oldstdout;
+ t.c_lflag = ISIG; // no output processing
+ tcsetattr(1, TCSANOW, &t);
+}
+
+static void console(int serial_fd)
+{
+ struct pollfd pfd[2];
+ char c;
+ int err;
+
+ printf("starting console mode, ctrl-c to exit\n");
+ fflush(stdout);
+ setconsole();
+
+ pfd[0].fd = STDIN_FILENO;
+ pfd[0].events = POLLIN | POLLERR;
+ pfd[1].fd = serial_fd;
+ pfd[1].events = POLLIN | POLLERR;
+
+ for (;;) {
+ err = poll(pfd, 2, -1);
+ if (err <= 0)
+ break;
+
+ if (pfd[0].revents & POLLIN) {
+ err = read(STDIN_FILENO, &c, 1);
+ if (err < 0)
+ break;
+
+ write(serial_fd, &c, 1);
+ }
+ if (pfd[1].revents & POLLIN) {
+ err = read(serial_fd, &c, 1);
+ if (err < 0)
+ break;
+ write(STDOUT_FILENO, &c, 1);
+ }
+
+ if ((pfd[0].revents | pfd[1].revents) & POLLERR)
+ break;
+ }
+}
+#endif
+
+static void usage(int argc, char **argv)
+{
+ fprintf(stderr, "usage: %s <serial port> [commands ...]\n", argv[0]);
+ fprintf(stderr, "valid commands are:\n");
+ fprintf(stderr, "\terase: perform a handshake with a microcontroller to erase the flash\n");
+ fprintf(stderr, "\treset: toggle the reset line\n");
+ fprintf(stderr, "\tolderase: toggle the erase line\n");
+#ifndef __WIN32
+ fprintf(stderr, "\tconsole: go into console mode on the serial line\n");
+ fprintf(stderr, "\tmonitor: display the current status of the lines\n");
+ fprintf(stderr, "\thold: keep the uart open and wait for ctrl-c\n");
+#endif
+
+ exit(1);
+}
+
+int main(int argc, char **argv)
+{
+ int i, serial, status;
+
+ if (argc < 3) {
+ fprintf(stderr, "not enough arguments\n");
+ usage(argc, argv);
+ }
+
+ const char *port;
+ port = argv[1];
+
+ if (serial_open(port) < 0) {
+ fprintf(stderr, "error opening serial\n");
+ return 1;
+ }
+
+ int arg;
+ for (arg = 2; arg < argc; arg++) {
+ if (!strcasecmp(argv[arg], "erase")) {
+ printf("erasing...");
+ set_reset(1);
+ usleep(500000);
+ set_reset(0);
+ secret_knock();
+ usleep(1000000);
+ printf("done.\n");
+ } else if (!strcasecmp(argv[arg], "olderase")) {
+ set_reset(0);
+ set_erase(1);
+ usleep(300000);
+
+ set_erase(0);
+ set_reset(1);
+ usleep(100000);
+ set_reset(0);
+ } else if (!strcasecmp(argv[arg], "reset")) {
+ printf("resetting...");
+ set_erase(0);
+ set_reset(0);
+ usleep(100000);
+ set_reset(1);
+ usleep(500000);
+ set_reset(0);
+ printf("done.\n");
+#ifndef __WIN32
+ } else if (!strcasecmp(argv[arg], "monitor")) {
+ printf("monitoring state of erase and reset lines\n");
+ int r, e;
+
+ e = get_erase();
+ r = get_reset();
+
+ for (;;) {
+ int e1 = get_erase();
+ if (e1 != e)
+ printf("erase %d\n", e1);
+
+ int r1 = get_reset();
+ if (r1 != r)
+ printf("reset %d\n", r1);
+
+ e = e1;
+ r = r1;
+ }
+ } else if (!strcasecmp(argv[arg], "hold")) {
+ printf("holding port open, ctrl-c to exit.\n");
+ set_erase(0);
+ set_reset(0);
+ for (;;)
+ usleep(1000000);
+ } else if (!strcasecmp(argv[arg], "console")) {
+ console(serial_get_fd());
+#endif
+ } else {
+ printf("bad command '%s'\n", argv[arg]);
+ exit(1);
+ }
+ }
+
+ serial_close();
+}
+
diff --git a/tools/adk2tool/makefile b/tools/adk2tool/makefile
new file mode 100644
index 0000000..86307fa
--- /dev/null
+++ b/tools/adk2tool/makefile
@@ -0,0 +1,72 @@
+
+TARGET := adk2tool
+BUILDDIR := build-$(TARGET)
+
+# compiler flags, default libs to link against
+COMPILEFLAGS := -g -O2
+CFLAGS :=
+CPPFLAGS :=
+ASMFLAGS :=
+LDFLAGS :=
+LDLIBS :=
+
+UNAME := $(shell uname -s)
+ARCH := $(shell uname -m)
+
+SERIAL:=win32
+
+# switch any platform specific stuff here
+# ifeq ($(findstring CYGWIN,$(UNAME)),CYGWIN)
+# ...
+# endif
+ifeq ($(UNAME),Darwin)
+COMPILEFLAGS += -arch i386
+LDFLAGS += -arch i386
+SERIAL:=posix
+endif
+ifeq ($(UNAME),Linux)
+COMPILEFLAGS += -m32
+LDFLAGS += -m32
+SERIAL:=posix
+endif
+
+CFLAGS += $(COMPILEFLAGS)
+CPPFLAGS += $(COMPILEFLAGS)
+ASMFLAGS += $(COMPILEFLAGS)
+
+OBJS := adk2tool.o serial-$(SERIAL).o
+
+OBJS := $(addprefix $(BUILDDIR)/,$(OBJS))
+
+DEPS := $(OBJS:.o=.d)
+
+$(BUILDDIR)/$(TARGET): $(OBJS)
+ $(CC) $(LDFLAGS) $(OBJS) -o $@ $(LDLIBS)
+
+clean:
+ rm -f $(OBJS) $(DEPS) $(TARGET)
+
+spotless:
+ rm -rf build-*
+
+# makes sure the target dir exists
+MKDIR = if [ ! -d $(dir $@) ]; then mkdir -p $(dir $@); fi
+
+$(BUILDDIR)/%.o: %.c
+ @$(MKDIR)
+ @echo compiling $<
+ @$(CC) $(CFLAGS) -c $< -MD -MT $@ -MF $(@:%o=%d) -o $@
+
+$(BUILDDIR)/%.o: %.cpp
+ @$(MKDIR)
+ @echo compiling $<
+ @$(CC) $(CPPFLAGS) -c $< -MD -MT $@ -MF $(@:%o=%d) -o $@
+
+$(BUILDDIR)/%.o: %.S
+ @$(MKDIR)
+ @echo compiling $<
+ @$(CC) $(ASMFLAGS) -c $< -MD -MT $@ -MF $(@:%o=%d) -o $@
+
+ifeq ($(filter $(MAKECMDGOALS), clean), )
+-include $(DEPS)
+endif
diff --git a/tools/adk2tool/serial-posix.c b/tools/adk2tool/serial-posix.c
new file mode 100644
index 0000000..4e915a8
--- /dev/null
+++ b/tools/adk2tool/serial-posix.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <termios.h>
+#include <fcntl.h>
+#include <curses.h>
+#include <sys/ioctl.h>
+
+static int fd;
+
+/* rts's logic is inverted, since rs232 defines it as active low */
+void serial_set_rts(int en)
+{
+ int status;
+
+ ioctl(fd, TIOCMGET, &status);
+ if (en)
+ status &= ~TIOCM_RTS;
+ else
+ status |= TIOCM_RTS;
+ ioctl(fd, TIOCMSET, &status);
+}
+
+int serial_get_rts(void)
+{
+ int status;
+ ioctl(fd, TIOCMGET, &status);
+ return !!(status & TIOCM_RTS);
+}
+
+void serial_set_dtr(int en)
+{
+ int status;
+
+ ioctl(fd, TIOCMGET, &status);
+ if (en)
+ status |= TIOCM_DTR;
+ else
+ status &= ~TIOCM_DTR;
+ ioctl(fd, TIOCMSET, &status);
+}
+
+int serial_get_dtr(void)
+{
+ int status;
+ ioctl(fd, TIOCMGET, &status);
+ return !!(status & TIOCM_DTR);
+}
+
+int serial_open(const char *port)
+{
+ int i, serial, status;
+
+ fd = open(port, O_RDWR | O_NOCTTY | O_NDELAY);
+ if (fd < 0) {
+ fprintf(stderr, "error opening serial\n");
+ return -1;
+ }
+
+ /* set the serial port */
+ struct termios s;
+ tcgetattr(fd, &s);
+ s.c_cflag = CS8 | CREAD;
+ s.c_ispeed = s.c_ospeed = 115200;
+ tcsetattr(fd, TCSANOW, &s);
+
+ return 0;
+}
+
+void serial_close(void)
+{
+ close(fd);
+}
+
+int serial_get_fd(void)
+{
+ return fd;
+}
+
+
diff --git a/tools/adk2tool/serial-win32.c b/tools/adk2tool/serial-win32.c
new file mode 100644
index 0000000..05fa857
--- /dev/null
+++ b/tools/adk2tool/serial-win32.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <windows.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+
+static HANDLE serial;
+
+int serial_get_dtr(void)
+{
+ return 0;
+}
+
+int serial_get_rts(void)
+{
+ return 0;
+}
+
+void serial_set_dtr(int val)
+{
+ if (val)
+ EscapeCommFunction(serial, SETDTR);
+ else
+ EscapeCommFunction(serial, CLRDTR);
+}
+
+/* rts's logic is inverted, since rs232 defines it as active low */
+void serial_set_rts(int val)
+{
+ if (val)
+ EscapeCommFunction(serial, CLRRTS);
+ else
+ EscapeCommFunction(serial, SETRTS);
+}
+
+int serial_open(const char *port)
+{
+ // open the port
+ serial = CreateFile(port,
+ GENERIC_READ | GENERIC_WRITE,
+ 0,
+ NULL,
+ OPEN_EXISTING,
+ 0,
+ NULL);
+ //printf("serial handle %u\n", serial);
+
+ if (serial == INVALID_HANDLE_VALUE)
+ return -1;
+
+ //SetupComm(serial, 1024, 1024);
+
+ // config it
+ DCB config;
+ GetCommState(serial, &config);
+ config.BaudRate = 115200;
+ config.ByteSize = 8;
+ config.Parity = NOPARITY;
+ config.StopBits = ONESTOPBIT;
+ config.fBinary = TRUE;
+ config.fParity = TRUE;
+ config.fDtrControl = DTR_CONTROL_ENABLE;
+ config.fRtsControl = RTS_CONTROL_ENABLE;
+ SetCommState(serial, &config);
+
+ COMMTIMEOUTS timeout;
+ GetCommTimeouts(serial, &timeout);
+ timeout.ReadIntervalTimeout = 0;
+ timeout.ReadTotalTimeoutConstant = 0;
+ timeout.ReadTotalTimeoutMultiplier = 0;
+ timeout.WriteTotalTimeoutConstant = 1000;
+ timeout.WriteTotalTimeoutMultiplier = 0;
+ SetCommTimeouts(serial, &timeout);
+
+ return 0;
+}
+
+void serial_close(void)
+{
+}
+
+int serial_get_fd(void)
+{
+ return (int)serial;
+}
diff --git a/tools/adk2tool/serial.h b/tools/adk2tool/serial.h
new file mode 100644
index 0000000..2ed02bd
--- /dev/null
+++ b/tools/adk2tool/serial.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __SERIAL_H
+#define __SERIAL_H
+
+int serial_open(const char *port);
+void serial_close(void);
+int serial_get_fd(void);
+int serial_get_dtr(void);
+int serial_get_rts(void);
+void serial_set_dtr(int val);
+void serial_set_rts(int val);
+
+#endif
