Update git submodules
* Update external/arm-trusted-firmware from branch 'master'
to 45f609b090a495170650d858ac9f0a74af479dc2
- Merge Trusted Firmware-A v2.5 release
Change-Id: I97d35685a9d2253feca2dbba27f1bed85119c77f
- Merge changes I10b5cc17,I382d599f into integration
* changes:
docs(prerequisites): add `--no-save` to `npm install`
fix(hooks): downgrade `package-lock.json` version
- docs(prerequisites): add `--no-save` to `npm install`
To avoid the mistake fixed by the previous commit, ensure users install
the Node.js dependencies without polluting the lock file by passing
`--no-save` to the `npm install` line.
Change-Id: I10b5cc17b9001fc2e26deee02bf99ce033a949c1
Signed-off-by: Chris Kay <chris.kay@arm.com>
- fix(hooks): downgrade `package-lock.json` version
The NPM lock file was accidentally updated using a later version of
Node.js than required by the prerequisites. This upgraded the lock file
to the v2 format, which causes a warning on Node.js 14 (the
prerequisites version). This moves the lock file back to v1 by
installing the dependencies with Node.js 14.
Change-Id: I382d599fd2b67b07eb9234d14e7b631db6b11453
Signed-off-by: Chris Kay <chris.kay@arm.com>
- Merge "feat(makefile): incrementing minor version to reflect v2.5 release" into integration
- Merge "docs(juno): update TF-A build instructions" into integration
- Merge "docs: spm design document refresh" into integration
- Merge "build(hooks): update Commitizen to ^4.2.4" into integration
- Merge "docs(release): add change log for v2.5 release" into integration
- docs(juno): update TF-A build instructions
Clean up instructions for building/running TF-A on the
Juno platform and add correct link to SCP binaries.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I536f98082e167edbf45f29ca23cc0db44687bb3b
- feat(makefile): incrementing minor version to reflect v2.5 release
Updated the minor version in the makefile
Change-Id: Ie2b3ce5b36a105a0e2fff52c3740cc9702ca3108
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
- build(hooks): update Commitizen to ^4.2.4
An indirect dependency of Commitizen (`merge`) is currently failing the
NPM.js auditor due to vulnerability CVE-2020-28499. This commit moves
the minimum version of Commitizen to 4.2.4, which has resolved this
vulnerability.
Change-Id: Ia9455bdbe02f7406c1a106f173c4095943a201ed
Signed-off-by: Chris Kay <chris.kay@arm.com>
- docs: spm design document refresh
General refresh of the SPM document.
Change-Id: I2f8e37c3f34bc8511b115f00b9a53b6a6ff41bea
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
- docs(release): add change log for v2.5 release
Change log for trusted-firmware-a v2.5 release
Change-Id: I6ffc8a40d2cc3a18145b87f895acdc1400db485a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
- Merge "fix(plat/arm_fpga): increase initrd size" into integration
- Merge "docs: removing "upcoming" change log" into integration
- docs: removing "upcoming" change log
Removing the "Upcoming" change log due to the change in change log
processing.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I6d2cc095dca3e654bd7e6fec2077c58bfbc48bb5
- fix(plat/arm_fpga): increase initrd size
In the comment in the ARM FPGA DT we promise a generous 100 MB initrd,
but actually describe only a size of 20 MB.
As initrds are the most common and easy userland option for the boards,
let's increase the maximum size to the advertised 100 MB, to avoid
unpacking errors when an initrd exceeds the current limit of 20 MB.
Change-Id: If08ba3fabdad27b2c2aff93b18c3f664728b4348
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- Merge "docs: revert FVP versions for select models" into integration
- docs: revert FVP versions for select models
Reverting FVP versions to previous version 11.12.38 for Cortex-A32x4
and Neoverse-N2x4.
Change-Id: I81e8ad24794dd425a9e9a66dc8bb02b42191abf1
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
- Merge "docs: update list of supported FVP platforms" into integration
- Merge "docs(threat model): add TF-A threat model" into integration
- docs(threat model): add TF-A threat model
This is the first release of the public Trusted
Firmware A class threat model. This release
provides the baseline for future updates to be
applied as required by developments to the
TF-A code base.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I3c9aadc46196837679f0b1377bec9ed4fc42ff11
- docs: update list of supported FVP platforms
Updated the list of supported FVP platforms as per the latest FVP
release.
Change-Id: I1abd0a7885b1133715062ee1b176733556a4820e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
- Merge "plat/st: do not rely on tainted value for dt property length" into integration
- Merge changes from topic "imx8mp_fix" into integration
* changes:
plat: imx8mp: change the bl31 physical load address
plat: imx8m: Fix the macro define error
- plat: imx8mp: change the bl31 physical load address
on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K,
currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will
leave the last 64KB in non-continuous space. To provide a continuous
384KB + 64KB space for generic use, so move the BL31 space to
0x970000-0x990000 range.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I96d572fc0f87f05a60f55e0552a68b6e70f8e7f4
- plat: imx8m: Fix the macro define error
the 'always_on' member should be initialized from 'on'.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I5746ff40075b4fcda2ac7d04a8d7f1269af17e91
- Merge changes I8e67a921,I0dc06072,I5e149063,I962cdfc7,I5c5d0444 into integration
* changes:
plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
plat: ti: k3: board: Lets cast our macros
plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computing
plat: ti: k3: platform_def.h: Define the correct number of max table entries
plat: ti: k3: board: lite: Increase SRAM size to account for additional table
- Merge "feat(tc0): update Matterhorn ELP DVFS clock index" into integration
- feat(tc0): update Matterhorn ELP DVFS clock index
This allows the the Matterhorn ELP Arm core to operate at its
designated OPP.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I7ccef0cfd079d630c3cfe7874590bf42789a1dca
- Merge "docs: remove PSA wording for SPM chapters" into integration
- Merge "revert(commitlint): disable `signed-off-by` rule" into integration
- docs: remove PSA wording for SPM chapters
PSA wording is not longer associated with FF-A.
Change-Id: Id7c53b9c6c8f383543f6a32a15eb15b7749d8658
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
- plat/st: do not rely on tainted value for dt property length
To compare the "okay" string of a property, strncmp is used but with the
length given by fdt_getprop. This len value is reported as tainted by
Coverity [1]. We just can use strlen("okay") which is a known value
to compare the 2 strings.
[1] https://scan4.coverity.com/reports.htm#v51972/p11439/fileInstanceId=96515154&defectInstanceId=14219121&mergedDefectId=342997
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ic8fb6ccf3126a37df615e433eb028861812015da
- Merge changes from topic "fw-update" into integration
* changes:
docs: add build options for GPT support enablement
feat(plat/arm): add GPT parser support
- Merge changes I15e7cc43,Id7411bd5,I92bafe70,I8f1c0658 into integration
* changes:
stm32mp1: enable PIE for BL32
stm32mp1: set BL sizes regardless of flags
Add PIE support for AARCH32
Avoid the use of linker *_SIZE__ macros
- docs: add build options for GPT support enablement
Documented the build options used in Arm GPT parser enablement.
Change-Id: I9d7ef2f44b8f9d2731dd17c2639e5ed0eb6d0b3a
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
- feat(plat/arm): add GPT parser support
Added GPT parser support in BL2 for Arm platforms to get the entry
address and length of the FIP in the GPT image.
Also, increased BL2 maximum size for FVP platform to successfully
compile ROM-enabled build with this change.
Verified this change using a patch:
https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/9654
Change-Id: Ie8026db054966653b739a82d9ba106d283f534d0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
- Merge "refactor(plat/arm): replace FIP base and size macro with a generic name" into integration
- Merge "refactor(plat/arm): store UUID as a string, rather than ints" into integration
- Merge "feat(fdt): introduce wrapper function to read DT UUIDs" into integration
- Merge "fix(driver/auth): avoid NV counter upgrade without certificate validation" into integration
- Merge changes from topic "mp/update_release_timelines" into integration
* changes:
docs: update release information for v2.6
docs: update code freeze & target date for v2.5
- docs: update release information for v2.6
Updated tentative code freeze and release target date for v2.6
release.
Change-Id: I3dd6cfef1a07f3e0159ec7996d18f6cbcb975da7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
- docs: update code freeze & target date for v2.5
Updated code freeze and release target date for v2.5 release.
Change-Id: I72850eed2aa77d3adecaf71d74e9ecebcc36d5b4
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
- Merge changes from topic "mit-license" into integration
* changes:
fix(dt-bindings): fix static checks
docs(license): rectify `arm-gic.h` license
- refactor(plat/arm): store UUID as a string, rather than ints
NOTE: Breaking change to the way UUIDs are stored in the DT
Currently, UUIDs are stored in the device tree as
sequences of 4 integers. There is a mismatch in endianness
between the way UUIDs are represented in memory and the way
they are parsed from the device tree. As a result, we must either
store the UUIDs in little-endian format in the DT (which means
that they do not match up with their string representations)
or perform endianness conversion after parsing them.
Currently, TF-A chooses the second option, with unwieldy
endianness-conversion taking place after reading a UUID.
To fix this problem, and to make it convenient to copy and
paste UUIDs from other tools, change to store UUIDs in string
format, using a new wrapper function to parse them from the
device tree.
Change-Id: I38bd63c907be14e412f03ef0aab9dcabfba0eaa0
Signed-off-by: David Horstmann <david.horstmann@arm.com>
- feat(fdt): introduce wrapper function to read DT UUIDs
TF-A does not have the capability to read UUIDs in string form
from the device tree. This capability is useful for readability,
so add a wrapper function, fdtw_read_uuid() to parse UUIDs from
the DT.
This function should parse a string of the form:
"aabbccdd-eeff-4099-8877-665544332211"
to the byte sequence in memory:
[aa bb cc dd ee ff 40 99 88 77 66 55 44 33 22 11]
Change-Id: I99a92fbeb40f4f4713f3458b36cb3863354d2bdf
Signed-off-by: David Horstmann <david.horstmann@arm.com>
- refactor(plat/arm): replace FIP base and size macro with a generic name
Replaced PLAT_ARM_FIP_BASE and PLAT_ARM_FIP_MAX_SIZE macro with a
generic name PLAT_ARM_FLASH_IMAGE_BASE and PLAT_ARM_FLASH_IMAGE_MAX_SIZE
so that these macros can be reused in the subsequent GPT based support
changes.
Change-Id: I88fdbd53e1966578af4f1e8e9d5fef42c27b1173
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
- Merge changes I2c9aecc9,Ie6a019f4,Ief6f0a63,Iec9c80f2 into integration
* changes:
fdts: stm32mp1: add support for the Seeed Odyssey SoM and board
fdts: stm32mp1: add alternative SDMMC2 pins to the pinctrl
fdts: stm32mp1: add I2C2 pins in the pinctrl
fdts: stm32mp1: add the I2C2 peripheral in the SoC DTS
- Merge "plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRC" into integration
- plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRC
This new compile option is only for Armada 3720 Development Board. When
it is set to 1 then TF-A will setup PM wake up src configuration.
By default this new option is disabled as it is board specific and no
other A37xx board has PM wake up src configuration.
Currently neither upstream U-Boot nor upstream Linux kernel has wakeup
support for A37xx platforms, so having it disabled does not cause any
issue.
Prior this commit PM wake up src configuration specific for Armada 3720
Development Board was enabled for every A37xx board. After this change it
is enabled only when compiling with build flag A3720_DB_PM_WAKEUP_SRC=1
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I09fea1172c532df639acb3bb009cfde32d3c5766
- revert(commitlint): disable `signed-off-by` rule
The `signed-off-by` rule does not correctly detect the `Signed-off-by:`
trailer if it's not the last trailer. Therefore, this rule has been
disabled until we can resolve this in the commitlint upstream.
Change-Id: I50ea29067528f3c1c25beeea5eb25134b25b2af2
Signed-off-by: Chris Kay <chris.kay@arm.com>
- fix(driver/auth): avoid NV counter upgrade without certificate validation
Platform NV counter get updated (if cert NV counter > plat NV counter)
before authenticating the certificate if the platform specifies NV
counter method before signature authentication in its CoT, and this
provides an opportunity for a tempered certificate to upgrade the
platform NV counter. This is theoretical issue, as in practice none
of the standard CoT (TBBR, dualroot) or upstream platforms ones (NXP)
exercised this issue.
To fix this issue, modified the auth_nvctr method to do only NV
counter check, and flags if the NV counter upgrade is needed or not.
Then ensured that the platform NV counter gets upgraded with the NV
counter value from the certificate only after that certificate gets
authenticated.
This change is verified manually by modifying the CoT that specifies
certificate with:
1. NV counter authentication before signature authentication
method
2. NV counter authentication method only
Change-Id: I1ad17f1a911fb1035a1a60976cc26b2965b05166
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
- Merge changes from topic "rd_plat_variants" into integration
* changes:
feat(board/rdn2): add support for variant 1 of rd-n2 platform
feat(plat/sgi): introduce platform variant build option
- fix(dt-bindings): fix static checks
This patch fixes static checks errors reported for missing copyright in
`include/dt-bindings/interrupt-controller/arm-gic.h` and the include
order of header files in `.dts` and `.dtsi` files.
Change-Id: I2baaf2719fd2c84cbcc08a8f0c4440a17a9f24f6
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Signed-off-by: Chris Kay <chris.kay@arm.com>
- feat(board/rdn2): add support for variant 1 of rd-n2 platform
Add board support for RD-N2 Cfg1 variant of RD-N2 platform. It is a
variant of RD-N2 platform with a reduced interconnect mesh size (3x3)
and core count (8-cores). Its platform variant id is 1.
Change-Id: I34ad35c5a5c1e9b69a658fb92ed00e5bc5fe72f3
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
- feat(plat/sgi): introduce platform variant build option
A Neoverse reference design platform can have two or more variants that
differ in core count, cluster count or other peripherals. To allow reuse
of platform code across all the variants of a platform, introduce build
option CSS_SGI_PLATFORM_VARIANT for Arm Neoverse reference design
platforms. The range of allowed values for the build option is platform
specific. The recommended range is an interval of non negative integers.
An example usage of the build option is
make PLAT=rdn2 CSS_SGI_PLATFORM_VARIANT=1
Change-Id: Iaae79c0b4d0dc700521bf6e9b4979339eafe0359
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
- Merge changes I36e45c0a,I69c21293 into integration
* changes:
plat/qemu: add "max" cpu support
Add support for QEMU "max" CPU
- Merge changes from topic "sgm775_deprecation" into integration
* changes:
build: deprecate Arm sgm775 FVP platform
docs: introduce process for platform deprecation
- Merge "plat/arm: move compile time switch from source to dt file" into integration
- Merge changes I20c73f6e,I9962263c,I177796e3,I6ff6875c,I21fe9d85, ... into integration
* changes:
mediatek: mt8195: add rtc power off sequence
mediatek: mt8195: add power-off support
mediatek: mt8195: Add reboot function for PSCI
mediatek: mt8195: Add gpio driver
mediatek: mt8195: Add SiP service
mediatek: mt8195: Add CPU hotplug and MCDI support
mediatek: mt8195: Add MCDI drivers
mediatek: mt8195: Add SPMC driver
mediatek: mt8195: Initialize delay_timer
mediatek: mt8195: initialize systimer
mediatek: mt8192: move timer driver to common folder
mediatek: mt8195: add sys_cirq support
mediatek: mt8195: initialize GIC
Initialize platform for MediaTek MT8195
- plat/arm: move compile time switch from source to dt file
This will help in keeping source file generic and conditional
compilation can be contained in platform provided dt files.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I3c6e0a429073f0afb412b9ba521ce43f880b57fe
- docs(license): rectify `arm-gic.h` license
The `arm-gic.h` file distributed by the Linux kernel is disjunctively
dual-licensed under the GPL-2.0 or MIT licenses, but the BSD-3-Clause
license has been applied in violation of the requirements of both
licenses. This change ensures the file is correctly licensed under the
terms of the MIT license, and that we comply with it by distributing a
copy of the license text.
Change-Id: Ie90066753a5eb8c0e2fc95ba43e3f5bcbe2fa459
Signed-off-by: Chris Kay <chris.kay@arm.com>
- Merge "Arm: Fix error message printing in board makefile" into integration
- build: deprecate Arm sgm775 FVP platform
sgm775 is an old platform and is no longer maintained by Arm and its
fast model FVP_CSS_SGM-775 is no longer available for download.
This platform is now superseded by Total Compute(tc) platforms.
This platform is now deprecated but the source will be kept for cooling
off period of 2 release cycle before removing it completely.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I8fe1fc3da0c508dba62ed4fc60cbc1642e0f7f2a
- docs: introduce process for platform deprecation
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ifb8a3220f2fc2286fa91614887d17f54178ed002
- mediatek: mt8195: add rtc power off sequence
mt8195 also uses mt6359p RTC. Revice mt8192 RTC and share the
driver with mt8195.
Change-Id: I20c73f6e0af67ef9d4c3d4e0ff373f93950e07db
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
- mediatek: mt8195: add power-off support
mt8195 also uses PMIC mt6359p. The only difference is the
pwrap register definition.
Change-Id: I9962263c46187d1344f14f857bf4b51e33aedda0
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
- mediatek: mt8195: Add reboot function for PSCI
Add system_reset function in PSCI ops
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I177796e30198b0a53402093ee0917dda43074385
- mediatek: mt8195: Add gpio driver
Add gpio driver.
Signed-off-by: mtk20895 <zhiqiang.ma@mediatek.com>
Change-Id: I6ff6875c35294f56f2d8298d75cd18c230aad211
- mediatek: mt8195: Add SiP service
Add the basic SiP service
Change-Id: I21fe9d85eac4be9101b12c4b6c28294c5b93cb5f
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
- mediatek: mt8195: Add CPU hotplug and MCDI support
Implement PSCI platform OPs to support CPU hotplug and MCDI.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Change-Id: I1321f7989c8a3d116d698768a7146e8f180ee9c0
- mediatek: mt8195: Add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Change-Id: I6a6f9bf5d1d8bda1ee603d8bf3fc206437de7ad8
- mediatek: mt8195: Add SPMC driver
Add SPMC driver for CPU power on/off.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Change-Id: If47d7f3f3b9965f3c0402ea6cdb917ad1d16bb32
- mediatek: mt8195: Initialize delay_timer
Initialize delay_timer for delay functions.
Change-Id: Ib554135151f8b5c642b5a6511c942bb9efc0a47f
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
- mediatek: mt8195: initialize systimer
Change-Id: I7e0fbd04b0cdf5da92b8ef39737342f2d66f5f10
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
- mediatek: mt8192: move timer driver to common folder
The timer driver can be shared with mt8195. Move the the timer
driver to common/.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I84c97ab9cc9b469f35e0f44dd8e7b2b95f1b3926
- mediatek: mt8195: add sys_cirq support
MT8192 cirq driver can be shared with MT8195. Move cirq driver to common
common folder.
Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com>
Change-Id: Iba5cdcfd2116f0bd07e0497250f2da45613e3a4f
- mediatek: mt8195: initialize GIC
MT8192 GIC driver can be shared with MT8195. Move GIC driver to common
and do the initialization.
Signed-off-by: christine.zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I63f3e668b5ca6df8bcf17b5cd4d53fa84f330fed
- Initialize platform for MediaTek MT8195
- Add basic platform setup
- Add MT8195 documentation at docs/plat/
- Add generic CPU helper functions
- Add basic register address
Change-Id: I7978e2f32e58900e5cf93f741ee8eaf8b8e3b842
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
- Merge changes Ib0a2ce81,I5332fb52 into integration
* changes:
plat/qemu: add cortex-a72 support to 'virt' platform
plat/qemu: include gicv2.mk
- Merge changes from topic "xlnx_error_management" into integration
* changes:
plat: send an sgi to communicate to linux
plat: xilinx: Error management support
- plat: send an sgi to communicate to linux
Upon recieving the interrupt send an SGI.
The sgi number is communicated by linux.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change-Id: Ib8f07ff7132ba5ac202b546914efb16d04820ed3
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
- plat: xilinx: Error management support
Add support for the trapping the IPI in TF-A.
Register handler for the irq no 62 which is the IPI interrupt.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change-Id: I9c04fdae7be3dda6a34a9b196274c0b5fdf39223
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
- Merge "Plat FVP: Fix Generic Timer interrupt types" into integration
- Merge "mediatek: mt8192: devapc: Add devapc driver" into integration
- Merge changes from topic "my-topic-name" into integration
* changes:
plat: imx8mm: Add in BL2 with FIP
plat: imx8mm: Enable Trusted Boot
- fdts: stm32mp1: add support for the Seeed Odyssey SoM and board
Seeed Studio’s SoM‐STM32MP157C is a System‐on‐Module that integrates the
STM32MP157C MPU (the 650 MHz dual‐core variant with a GPU and a
cryptographic processor) the STPMIC1A PMIC, 512 MB of DDR3 RAM and a
4 GB eMMC. There are two LEDs as well, one hardwired to the PMIC’s VDD
output, and the other available at the MPU’s port PG3. The SoM can be
plugged into a carrier board using its three 70‑pin connectors.
Seeed Odyssey‐STM32MP157C is the reference carrier board for the SoM in
a Raspberry Pi‐like form factor. It features a WiFi/Bluetooth chip, a
microSD card port and various I/O interfaces.
The device tree is based on the DKx boards. TF‑A was successfully tested
on the board with Buildroot 2021.02 and U-Boot 2021.04.
Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: I2c9aecc925561e8d338dddbb192d3bb23a533914
- fdts: stm32mp1: add alternative SDMMC2 pins to the pinctrl
The new pins—PA8, PA9, PE5, and PC7—are described in a new pinctrl node
named “sdmmc2-d47-3”, AKA phandle “sdmmc2_d47_pins_d”. These names are
identical to their Linux kernel counterparts (commit
7af08140979a6e7e12b78c93b8625c8d25b084e2).
Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: Ie6a019f4361790f6b5d4910ce1e7b507a6c6a21a
- fdts: stm32mp1: add I2C2 pins in the pinctrl
Some STM32MP1‐based boards, like Seeed Studio’s SoM‐STM32MP157C, have
the SoC connected to the PMIC via I2C2 instead of I2C4 (which is used on
the official ST development boards). This commit brings TF‑A one step
closer to boot on such boards.
The pins used, PH4 and PH5, are described in a new pinctrl node named
“i2c2-0”, AKA phandle “i2c2_pins_a”. These names are identical to their
Linux kernel counterparts (commit
7af08140979a6e7e12b78c93b8625c8d25b084e2).
Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: Ief6f0a632cfa992dcf3fed95d266ad6a07a96fe0
- fdts: stm32mp1: add the I2C2 peripheral in the SoC DTS
Some STM32MP1‐based boards, like Seeed Studio’s SoM‐STM32MP157C, have
the SoC connected to the PMIC via I2C2 instead of I2C4 (which is used on
the official ST development boards). This commit brings TF‑A one step
closer to boot on such boards.
Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: Iec9c80f29ce95496e8f1b079b7a23f1914b74901
- Merge "Add documentation for SMMUv3 driver in Hafnium(SPM)" into integration
- Merge "Add "_arm" suffix to Makalu ELP CPU lib" into integration
- Merge changes Id7bdbc9b,Ia813e051,I2c437380,I736724cc,I454fb40a, ... into integration
* changes:
renesas: rzg: Add support to identify EK874 RZ/G2E board
drivers: renesas: common: watchdog: Add support for RZ/G2E
drivers: renesas: rzg: Add QoS support for RZ/G2E
drivers: renesas: rzg: Add PFC support for RZ/G2E
drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board
drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC
drivers: renesas: rzg: Add QoS support for RZ/G2N
drivers: renesas: rzg: Add PFC support for RZ/G2N
drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board
drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC
drivers: renesas: rzg: Add QoS support for RZ/G2H
drivers: renesas: rzg: Add PFC support for RZ/G2H
drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
drivers: renesas: rzg: Switch using common ddr code
drivers: renesas: ddr: Move to common
- Merge "plat: xilinx: zynqmp: Configure counter frequency during initialization" into integration
- stm32mp1: enable PIE for BL32
In order to prepare future support of FIP, BL32 (SP_min) is compiled
as Position Independent Executable.
Change-Id: I15e7cc433fb03e1833002f4fe2eaecb6ed42eb47
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
- stm32mp1: set BL sizes regardless of flags
BL2 size is set to 100kB, and BL32 to 72kB, regardless of OP-TEE
or stack protector flags.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Id7411bd55a4140718d64a647d81037720615fc81
- Add PIE support for AARCH32
Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just
stubbed with _pie_fixup_size=0.
The changes are an adaptation for AARCH32 on what has been done for
PIE support on AARCH64.
The RELA_SECTION is redefined for AARCH32, as the created section is
.rel.dyn and the symbols are .rel*.
Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9
Signed-off-by: Yann Gautier <yann.gautier@st.com>
- Avoid the use of linker *_SIZE__ macros
The use of end addresses is preferred over the size of sections.
This was done for some AARCH64 files for PIE with commit [1],
and some extra explanations can be found in its commit message.
Align the missing AARCH64 files.
For AARCH32 files, this is required to prepare PIE support introduction.
[1] f1722b693d36 ("PIE: Use PC relative adrp/adr for symbol reference")
Change-Id: I8f1c06580182b10c680310850f72904e58a54d7d
Signed-off-by: Yann Gautier <yann.gautier@st.com>
- Plat FVP: Fix Generic Timer interrupt types
The Arm Generic Timer specification mandates that the
interrupt associated with each timer is low level triggered,
see:
Arm Cortex-A76 Core:
"Each timer provides an active-LOW interrupt output to the SoC."
Arm Cortex-A53 MPCore Processor:
"It generates timer events as active-LOW interrupt outputs and
event streams."
The following files in fdts\
fvp-base-gicv3-psci-common.dtsi
fvp-base-gicv3-psci-aarch32-common.dtsi
fvp-base-gicv2-psci-aarch32.dts
fvp-base-gicv2-psci.dts
fvp-foundation-gicv2-psci.dts
fvp-foundation-gicv3-psci.dts
describe interrupt types as edge rising
IRQ_TYPE_EDGE_RISING = 0x01:
interrupts = <1 13 0xff01>,
<1 14 0xff01>,
<1 11 0xff01>,
<1 10 0xff01>;
, see include\dt-bindings\interrupt-controller\arm-gic.h:
which causes Linux to generate the warnings below:
arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low
arch_timer: WARNING: Please fix your firmware
This patch adds GIC_CPU_MASK_RAW macro definition to
include\dt-bindings\interrupt-controller\arm-gic.h,
modifies interrupt type to IRQ_TYPE_LEVEL_LOW and
makes use of type definitions in arm-gic.h.
Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
- Merge changes I3c25c715,I6d30b081 into integration
* changes:
plat: xilinx: versal: Add the IPI CRC checksum macro support
plat: xilinx: common: Rename the IPI CRC checksum macro
- Merge changes from topic "ck/conventional-commits" into integration
* changes:
build(hooks): add commitlint hook
build(hooks): add Commitizen hook
build(hooks): add Gerrit hook
build(hooks): add Husky configuration
- plat: xilinx: zynqmp: Configure counter frequency during initialization
Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stage Boot
Loader(FSBL) does not initialize counter frequency. This happens
when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU).
Because of that generic timer driver functionality is not working.
So configure counter frequency during initialization.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896
- plat: xilinx: versal: Add the IPI CRC checksum macro support
Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I3c25c715885759076055c6505471339b5d6edcd5
- plat: xilinx: common: Rename the IPI CRC checksum macro
Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and
move the related defines to the common include.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I6d30b081ac607572a0b23e10ca8031bc90489e58
- Merge changes from topic "od/ns-interrupts" into integration
* changes:
spmd: add FFA_INTERRUPT forwarding
doc: spm: update messaging method field
- Add "_arm" suffix to Makalu ELP CPU lib
ELP processors can sometimes have different MIDR values or features so
we are adding the "_arm" suffix to differentiate the reference
implementation from other future versions.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20
- Merge changes from topic "arm_ethosn_npu_sip" into integration
* changes:
Add SiP service to configure Arm Ethos-N NPU
plat/arm/juno: Add support to use hw_config in BL31
- spmd: add FFA_INTERRUPT forwarding
In the case of a SP pre-empted by a non-secure interrupt, the SPMC
returns to the SPMD through the FFA_INTERRUPT ABI. It is then forwarded
to the normal world driver hinting the SP has to be resumed after the
non-secure interrupt has been serviced.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I51a694dddcb8ea30fa84e1f11d018bc2abec0a56
- doc: spm: update messaging method field
As per FF-A v1.0 spec, Table 3.1, messaging method field also contains
information about whether partition supports managed exit or not.
Since a partition can support managed exit only if it supports direct
messaging, so there are two new possible values, managed exit with only
direct messaging or with both messaging methods.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ic77cfb37d70975c3a36c56f8b7348d385735f378
- renesas: rzg: Add support to identify EK874 RZ/G2E board
Add support to identify Silicon Linux RZ/G2E evaluation kit (EK874).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Id7bdbc9b0d25aa9af496d58d4bd5055579edc104
- drivers: renesas: common: watchdog: Add support for RZ/G2E
Add watchdog support for RZ/G2E SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ia813e051f6605028d0bb83967893ebd107fc8551
- drivers: renesas: rzg: Add QoS support for RZ/G2E
Add QoS support for RZ/G2E SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I2c4373807ab8c550d86d6abc97f5b01f2fb78fb3
- drivers: renesas: rzg: Add PFC support for RZ/G2E
Add pin control support for RZ/G2E SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I736724cc0dd32f2169018ed7f2f48319b039b61f
- drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the
same.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I454fb40af4f8ce6c4c0d2a53edb307326efd02df
- renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board
Add support to identify HopeRun HiHope RZ/G2N board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib47aba84b63488247f6e9da1f5878140129766ce
- drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC
Select MMC_CH1 for eMMC on RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib584b5203f38423ffe2ab52c6e6922f5b34a33ee
- drivers: renesas: rzg: Add QoS support for RZ/G2N
Add QoS support for RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I663b50d9fb41b9b20a6b54795278659b2b184bc4
- drivers: renesas: rzg: Add PFC support for RZ/G2N
Add pin control support for RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib5eb4f3b1b75e158ec13c4eefdbe9688344206a3
- drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
Add support for initializing DRAM on RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Id09a367b92b11a5da88f2dce6887677cc935d0c0
- renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board
Add support to identify HopeRun HiHope RZ/G2H board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I6b28350ef50595fea9a1b1b7353fcabaeb935970
- drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC
Select MMC_CH1 for eMMC on RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I1bdfa462fd98b144042c014701b342b87e1efc9d
- drivers: renesas: rzg: Add QoS support for RZ/G2H
Add QoS support for RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: If7d8940148fc31887568fd501c6cab609e715ba4
- drivers: renesas: rzg: Add PFC support for RZ/G2H
Add pin control support for RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I06dc259d7d26a5a5313e8731ea72f846bfca09ed
- drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
Add support for initializing DRAM on RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Iae23f1093f65a9efd065d37b7d6e9340ff6350b9
- drivers: renesas: rzg: Switch using common ddr code
Switch using common ddr driver code from renesas/common/ddr directory
for RZ/G2M SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I807dcb0bc5186bd32bc1c577945d28634bb10e1f
- drivers: renesas: ddr: Move to common
Move ddr driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I9aef73d3e9a027a127ce7483b72d339559866727
- Merge "mediatek: move uart.h to common folder" into integration
- Add SiP service to configure Arm Ethos-N NPU
By default the Arm Ethos-N NPU will boot up in secure mode. In this mode
the non-secure world cannot access the registers needed to use the NPU.
To still allow the non-secure world to use the NPU, a SiP service has
been added that can delegate non-secure access to the registers needed
to use it.
Only the HW_CONFIG for the Arm Juno platform has been updated to include
the device tree for the NPU and the platform currently only loads the
HW_CONFIG in AArch64 builds.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
- plat/arm/juno: Add support to use hw_config in BL31
To make it possible to use the hw_config device tree for dynamic
configuration in BL31 on the Arm Juno platform. A placeholder hw_config
has been added that is included in the FIP and a Juno specific BL31
setup has been added to populate fconf with the hw_config.
Juno's BL2 setup has been updated to align it with the new behavior
implemented in the Arm FVP platform, where fw_config is passed in arg1
to BL31 instead of soc_fw_config. The BL31 setup is expected to use the
fw_config passed in arg1 to find the hw_config.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: Ib3570faa6714f92ab8451e8f1e59779dcf19c0b6
- Merge "docs: marvell: Add information about CZ.NIC Armada 3720 Secure Firmware" into integration
- Merge changes I8f3afbe3,I441e7c69,I2e9465f7,Ib8756cd3,Iebe6ea7c, ... into integration
* changes:
plat/marvell: remove subversion from Marvell make files
drivers/marvell: check if TRNG unit is present
plat/marvell: a8k: move efuse definitions to separate header
plat/marvell/armada: fix TRNG return SMC handling
drivers: marvell: comphy: add rx training on 10G port
plat/marvell/armada: postpone MSS CPU startup to BL31 stage
plat: marvell: armada: a8k: Fix LD selector mask
plat/marvell/armada: allow builds without MSS support
drivers: marvell: misc-dfx: extend dfx whitelist
drivers: marvell: add support for secure read/write of dfx register-set
ddr_phy: use smc calls to access ddr phy registers
drivers: marvell: thermal: use dedicated function for thermal SiPs
drivers: marvell: add thermal sensor driver and expose it via SIP service
fix: plat: marvell: fix MSS loader for A8K family
- plat/marvell: remove subversion from Marvell make files
Subversion is not reflecting the Marvell sources variant anymore.
This patch removes version.mk from Marvell plafroms.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I8f3afbe3fab3a38da68876f77455f449f5fe0179
- drivers/marvell: check if TRNG unit is present
Some Marvell SoCs may have crypto engine disabled in the HW.
This patch checks the AP LD0 efuse for crypto engine/TRNG
presence before initializing the driver.
Change-Id: I441e7c69a137106bd36302b028b04c0b31896dbd
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47314
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
- plat/marvell: a8k: move efuse definitions to separate header
Move efuse definitions to a separate header file for later
usage with other FW modules.
Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47313
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
- plat/marvell/armada: fix TRNG return SMC handling
Use single 64b register for the return value instead of two 32b.
Report an error if caller requested larger than than 64b random
number in a single SMC call.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Ib8756cd3c0808b78c359f90c6f6913f7d16ac360
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/33280
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
- drivers: marvell: comphy: add rx training on 10G port
This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.
Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
- plat/marvell/armada: postpone MSS CPU startup to BL31 stage
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2.
However, (especailly in secure boot mode), some bus attributes should be
changed from defaults before the MSS CPU tries to access shared resources.
This patch starts to use CP MSS SRAM for FW load in both secure and
non-secure boot modes.
The FW loader inserts a magic number into MSS SRAM as an indicator of
successfully loaded FS during the BL2 stage and skips releasing the MSS
CPU from the reset state.
Then, at BL31 stage, the MSS CPU is released from reset following the
call to cp110_init function that handles all the required bus attributes
configurations.
Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
- plat: marvell: armada: a8k: Fix LD selector mask
Fixed a bug that the actually bit number was used as a mask to
select LD0 or LD1 fuse
Signed-off-by: Guo Yi <yguo@cavium.com>
Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
- plat/marvell/armada: allow builds without MSS support
Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2
definition.
Images build with MSS_SUPPORT=0 will not include service CPUs
FW and will not support PM, FC and other features implemented
in these FW images.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
- drivers: marvell: misc-dfx: extend dfx whitelist
Linux cpu clk driver requires access to some dfx registers. By adding
these registers to the white list, we enable access to them from
non-secure world.
Change-Id: Ic05c96b375121c025bfb41c2ac9474a530720155
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25187
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
- drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In introduced misc_dfx
driver some registers are white-listed so non-secure software can still
access them.
This will allow non-secure word drivers access some white-listed
registers related to e.g.: Sample at reset, efuses, SoC type and
revision ID accesses.
Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25055
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
- ddr_phy: use smc calls to access ddr phy registers
Added smc calls support to access ddr phy registers.
Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870
Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/20791
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
- drivers: marvell: thermal: use dedicated function for thermal SiPs
Since more drivers which uses dfx register set need to be handled with
use of SiP services, use dedicated and more meaningful name for thermal
SiP services.
Change-Id: Ic2ac27535a4902477df8edc4c86df3e34cb2344f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25054
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
- drivers: marvell: add thermal sensor driver and expose it via SIP service
Since the dfx register set is going to be marked as secure (in order to
protect efuse registers for non secure access), accessing thermal
registers which are part of dfx register set, will not be possible from
lower exception levels. Due to above expose thermal driver as a SiP
service. This will allow Linux and U-Boot thermal driver to initialise
and perform various operations on thermal sensor.
The thermal sensor driver is based on Linux
drivers/thermal/armada_thermal.c.
Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/20581
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
- fix: plat: marvell: fix MSS loader for A8K family
Wrong brakets caused MSS FW load timeout error:
ERROR: MSS DMA failed (timeout)
ERROR: MSS FW chunk 0 load failed
ERROR: SCP Image load failed
This patch fixes the operator precedence in MSS FW load.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I78c215606bde112f40429926c51f5fa1e4334c13
- mediatek: mt8192: devapc: Add devapc driver
Add devapc driver for setting default permission.
Change-Id: I103f27ae090fbed76ce9319606ac082d78b74566
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
- Merge "services: spm_mm: Use sp_boot_info to set SP context" into integration
- Add documentation for SMMUv3 driver in Hafnium(SPM)
Change-Id: I0b38c114fd2958d2b4040585611cafa132ccfd9c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
- services: spm_mm: Use sp_boot_info to set SP context
The current SPM_MM implementations expects the SP image addresses
as static macros. This means platforms wanting to use dynamically
allocated memory addresses are left out. This patch gets sp_boot_info
at the beginning of spm_sp_setup function and uses member variables
of sp_boot_info to setup the context. So member variables of
struct sp_boot_info and consequently the context can be initialized
by static macros or dynamiclly allocated memory address..
Change-Id: I1cb75190ab8026b845ae20a9c6cc416945b5d7b9
Signed-off-by: Mayur Gudmeti <mgudmeti@nvidia.com>
- build(hooks): add commitlint hook
This change adds a configuration for commitlint - a tool designed to
enforce a particular commit message style - and run it as part of Git's
commit-msg hook. This validates commits immediately after the editor has
been exited, and the configuration is derived from the configuration we
provide to Commitizen.
While the configuration provided suggests a maximum header and body
length, neither of these are hard errors. This is to accommodate the
occasional commit where it may be difficult or impossible to comply
with the length requirements (for example, with a particularly long
scope, or a long URL in the message body).
Change-Id: Ib5e90472fd1f1da9c2bff47703c9682232ee5679
Signed-off-by: Chris Kay <chris.kay@arm.com>
- build(hooks): add Commitizen hook
This change adds Commitizen, an interactive tool for writing commit
messages, to the package.json file. This installs Commitizen within the
`node_modules` directory automatically when developers invoke
`npm install` from the root repository directory.
Additionally, this change adds a prepare-commit-msg Git hook which
invokes Commitizen prior to generation of the default commit message.
It may be exited with the standard ^C signal without terminating the
commit process for those who desperately want to avoid using it, but
otherwise should encourage developers to conform to the new commit style
without running into post-commit linting errors.
Change-Id: I8a1e268ed40b61af38519d13d62b116fce76a494
Signed-off-by: Chris Kay <chris.kay@arm.com>
- build(hooks): add Gerrit hook
This change adds the Gerrit commit-msg hook to Husky, such that it now
no longer requires manual installation by the developer.
This hook was pulled directly from the TF-A Gerrit review server.
Change-Id: I79c9b0ce78fd326fda6db7a930b7277690177f28
Signed-off-by: Chris Kay <chris.kay@arm.com>
- build(hooks): add Husky configuration
Husky is a tool for managing Git hooks within the repository itself.
Traditionally, commit hooks need to be manually installed on a per-user
basis, but Husky allows us to install these hooks either automatically
when `npm install` is invoked within the repository, or manually with
`npx husky install`.
This will become useful for us in the next few patches when we begin
introducing tools for enforcing a commit message style.
Change-Id: I64cae147e9ea910347416cfe0bcc4652ec9b4830
Signed-off-by: Chris Kay <chris.kay@arm.com>
- Arm: Fix error message printing in board makefile
Remove an incorrect tabulation in front of an $(error) function call
outside of a recipe, which caused the following text to be displayed:
plat/arm/board/common/board_common.mk:36: *** recipe commences before first target. Stop.
instead of:
plat/arm/board/common/board_common.mk:36: *** "Unsupported ARM_ROTPK_LOCATION value". Stop.
Change-Id: I8592948e7de8ab0c4abbc56eb65a53eb1875a83c
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
- Merge "docs: Update Mbed TLS supported version" into integration
- Merge changes from topic "scmi_v2_0" into integration
* changes:
drivers/arm/css/scmi: Update power domain protocol version to 2.0
tc0: update GICR base address
- mediatek: move uart.h to common folder
UART register definition is the same on MediaTek platforms.
Move uart.h to common folder and remove the duplicate file.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Iea0931dfd606ae4a7ab475b9cb3a08dc6de68b36
- drivers/arm/css/scmi: Update power domain protocol version to 2.0
The SCMI power domain protocol in firmware has been updated to v2.0,
thus update the corresponding version in TF-A too.
Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com>
Change-Id: If3920ff71136dce94b2780e29a47f24aa09876c0
- tc0: update GICR base address
The number of ITS have changed from 4 to 1, resulting
in GICR base address change.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7
- docs: Update Mbed TLS supported version
Updated the documentation with latest Mbed TLS supported
version i.e. Mbed TLS v2.26.0
Fixes available in this version of Mbed TLS mainly affect
key generation/writing and certificates writing, which
are features used in the cert_create tool.
Release notes of Mbed TLSv2.26.0 are available here:
https://github.com/ARMmbed/mbedtls/releases/tag/v2.26.0
Change-Id: Ie15ee45d878b7681e15ec4bf64d54b416a31aa2f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
- Merge changes from topic "dcc_console" into integration
* changes:
plat:xilinx:versal: Add JTAG DCC support
plat:xilinx:zynqmp: Add JTAG DCC support
drivers: dcc: Support JTAG DCC console
- Merge "plat/arm: don't provide NT_FW_CONFIG when booting hafnium" into integration
- plat/qemu: add "max" cpu support
Add support to qemu "max" cpu for both "qemu" ('virt') and
"qemu_sbsa" ('sbsa-ref') platforms.
Change-Id: I36e45c0a3c4e30ba546d2a3cb44dfef11a680305
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
- Add support for QEMU "max" CPU
Enable basic support for QEMU "max" CPU.
The "max" CPU does not attampt to emulate any specific CPU, but rather
just enables all the functions emulated by QEMU.
Change-Id: I69c212932ef61433509662d0fefbabb1e9e71cf2
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
- plat/qemu: add cortex-a72 support to 'virt' platform
Cortex-A72 support is already enabled for sbsa-ref platform,
so add it also to virt platform for parity.
Change-Id: Ib0a2ce81ef7c0a71ef8dc66dbec179191bf2e6cc
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
- plat/qemu: include gicv2.mk
The build now gives deprecation warnings for including
drivers/arm/gic/common/gic_common.c directly. Move to including the
common gicv2 sources via gicv2.mk instead - which also matches the
pattern already used for gicv3.
Change-Id: I5332fb52c5801272e5e2bb6111f96087b4894325
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
- Merge "fiptool: Do not print duplicate verbose lines about building fiptool" into integration
- Merge "driver: brcm: add USB driver" into integration
- Merge "driver: brcm: add mdio driver" into integration
- Merge "arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms" into integration
- plat/arm: don't provide NT_FW_CONFIG when booting hafnium
NT_FW_CONFIG file is meant to be passed from BL31 to be consumed by
BL33, fvp platforms use this to pass measured boot configuration and
the x0 register is used to pass the base address of it.
In case of hafnium used as hypervisor in normal world, hypervisor
manifest is expected to be passed from BL31 and its base address is
passed in x0 register.
As only one of NT_FW_CONFIG or hypervisor manifest base address can be
passed in x0 register and also measured boot is not required for SPM so
disable passing NT_FW_CONFIG.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ifad9d3658f55ba7d70f468a88997d5272339e53e
- docs: marvell: Add information about CZ.NIC Armada 3720 Secure Firmware
CZ.NIC as part of Turris project released free and open source WTMI
application firmware 'wtmi_app.bin' for all Armada 3720 devices. This
firmware includes additional features like access to Hardware Random
Number Generator of Armada 3720 SoC which original Marvell's 'fuse.bin'
image does not have.
CZ.NIC's Armada 3720 Secure Firmware is available at website:
https://gitlab.nic.cz/turris/mox-boot-builder/
This change updates documentation to include steps how to build Marvell
firmware image for Espressobin with this firmware to enable Hardware
Random Number Generator on Espressobin.
In this change is fixed also URL to TF-A and U-Boot git repositories in
Espressobin build example. And as Marvell github repositories switched
default branch to master, explicit branch via -b parameter is redundant
and therefore from examples removed.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I59ee29cb6ed149264c5e4202f2af8f9ab3859418
- Merge changes from topic "mmc_device_info" into integration
* changes:
plat/st: do not keep mmc_device_info in stack
plat/intel: do not keep mmc_device_info in stack
plat/hisilicon: do not keep mmc_device_info in stack
- Merge changes from topic "mmc_device_info" into integration
* changes:
mmc: remove useless extra semicolons
Revert "mmc:prevent accessing to the released space in case of wrong usage"
- fiptool: Do not print duplicate verbose lines about building fiptool
Makefile for fiptool already prints verbose line when is (re)building
fiptool, so there is no need to print it also from top level Makefile.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6936a508702f1bf796d17578bb1f043f06365319
- Merge "fiptool: Do not call 'make clean' in 'all' target" into integration
- plat/st: do not keep mmc_device_info in stack
Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].
[1] 13f3c5166f1 ("mmc:prevent accessing to the released space in case of wrong usage")
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I73a079715253699d903721c865d6470d58f6bd30
- plat/intel: do not keep mmc_device_info in stack
Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].
[1] 13f3c5166f1 ("mmc:prevent accessing to the released space in case of wrong usage")
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Id52c0be61a30f453a551385883eaf3cbe32b04b9
- plat/hisilicon: do not keep mmc_device_info in stack
Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].
[1] 13f3c5166f1 ("mmc:prevent accessing to the released space in case of wrong usage")
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If5db8857cccec2e677b16a38eb3eeb41628a264c
- mmc: remove useless extra semicolons
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If1d6b2040e482577292890e3554449096648c2ae
- Revert "mmc:prevent accessing to the released space in case of wrong usage"
This reverts commit 13f3c5166f126b021e5f6e09e4a7c97f12495a35.
The STM32MP1 platform can no more boot qwith this change.
The driver will not be aware when the static struct in framework is updated.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Icc544e243136ee3b0067f316b71dff7dfd6526d6
- Merge "lib/cpu: Workaround for Cortex A77 erratum 1946167" into integration
- Merge "Fix: Remove save/restore of EL2 timer registers" into integration
- fiptool: Do not call 'make clean' in 'all' target
Calling 'make clean' in 'all' target is causing recompilation of binary
at every 'make' call, which is wrong.
Also building a new target via 'make TARGET' can cause infinite loop as
it is not defined as explicit make dependency. Dependent targets must be
specified after colon when defining target, which also prevents infinite
loops as make is able to detect these circular dependencies.
Moreover calling 'make clean' is supposed to be done by user when
configuration is changing.
So remove calling 'make clean' in 'all' target and define dependency for
'${PROJECT}' at correct place.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I70e7fd2b04b02f6a0650c82df91d58c9a4cb24d9
- Merge changes Id2a538c3,Ifa0339e7,I8b09fab8 into integration
* changes:
drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization
drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call
drivers: marvell: comphy-a3700: Fix configuring polarity invert bits
- Merge changes from topic "my-topic-name" into integration
* changes:
plat: imx8mm: Add image load logic for TBBR FIP booting
plat: imx8mm: Add initial defintions to facilitate FIP layout
plat: imx8mm: Add image io-storage logic for TBBR FIP booting
plat: imx8mm: Add imx8mm_private.h to the build
- Fix: Remove save/restore of EL2 timer registers
Since there is a secure and non-secure version of the timer registers
there is no need to preserve their context in EL3.
With that, following registers were removed from EL3 save/restore
routine:
cnthps_ctl_el2
cnthps_tval_el2
cnthps_cval_el2
cnthvs_ctl_el2
cnthvs_tval_el2
cnthvs_cval_el2
cnthp_ctl_el2
cnthp_cval_el2
cnthp_tval_el2
cnthv_ctl_el2
cnthv_cval_el2
cnthv_tval_el2
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I6e2fc09c74a7375c4fccc11f12af4e39e6dc616b
- Merge changes I4061428b,Icaee5da1 into integration
* changes:
plat/arm/arm_image_load: refine plat_add_sp_images_load_info
plat/arm/arm_image_load: fix bug of overriding the last node
- drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization
Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
Root Complex mode. Both U-Boot and Linux kernel support only Root Complex
mode. Set this bit.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Id2a538c379b911b62597f9463b4842b7b5c24df7
- drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call
The third argument of the reg_set() function has name 'mask', which
indicates that it is a mask applied to the register value which is
going to be updated. But the implementation of this function uses
this argument to clear prior value of the register, i.e. instead of
new_val = (old_val & ~mask) | (data & mask);
it does
new_val = (new_val & ~mask) | data;
(The more proper name for this function should be reg_clrsetbits(),
since internally it calls mmio_clrsetbits_32().)
To make code more readable set 'mask' argument to real mask, i.e. bits
of register values which are going to be updated.
This patch does not make any functional change, only cosmetic, due to
how 'mask' is interpreted.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ifa0339e79c07d1994c7971b65d966b92cb735f65
- drivers: marvell: comphy-a3700: Fix configuring polarity invert bits
TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when
appropriate polarity is inverted. Otherwise these bits should be
cleared.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8b09fab883a7b995fd72a7d8ae6233f0fa07011b
- plat/arm/arm_image_load: refine plat_add_sp_images_load_info
Refine the function plat_add_sp_images_load_info() by saving the
previous node and only setting its next link when the current node is
valid. This can reduce the check for the next node and simply the
total logic.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I4061428bf49ef0c3816ac22aaeb2e50315531f88
- plat/arm/arm_image_load: fix bug of overriding the last node
The traverse flow in function plat_add_sp_images_load_info() will find
the last node in the main load info list, with its
next_load_info==NULL. However this node is still useful and should not
be overridden with SP node info.
The bug will cause below error on RDN2 for spmd enabled:
ERROR: Invalid NT_FW_CONFIG DTB passed
Fix the bug by only setting the next_load_info of the last node in the
original main node list.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Icaee5da1f2d53b29fdd6085a8cc507446186fd57
- lib/cpu: Workaround for Cortex A77 erratum 1946167
Cortex A77 erratum 1946167 is a Cat B erratum that applies to revisions
<= r1p1. This erratum is avoided by inserting a DMB ST before acquire
atomic instructions without release semantics through a series of
writes to implementation defined system registers.
SDEN can be found here:
https://documentation-service.arm.com/static/600057a29b9c2d1bb22cd1be?token=
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I53e3b4fb7e7575ec83d75c2f132eda5ae0b4f01f
- Merge "Add Cortex_A78C CPU lib" into integration
- plat:xilinx:versal: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I77994ce387caf0d695986df3d01d414a920978d0
- plat:xilinx:zynqmp: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I62cfbb57ae7e454fbc91d1c54aafa6e99f9a35c8
- drivers: dcc: Support JTAG DCC console
The legacy console is gone. Re-add DCC console support based
on the multi-console framework.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Ia8388721093bc1be3af40974530d7c9a9ae5f43e
- Add Cortex_A78C CPU lib
Add basic support for Cortex_A78C CPU.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56
- Merge changes from topic "allwinner_h616" into integration
* changes:
allwinner: H616: Add reserved-memory node to DT
allwinner: Add Allwinner H616 SoC support
allwinner: Add H616 SoC ID
allwinner: Express memmap more dynamically
allwinner: Move sunxi_cpu_power_off_self() into platforms
allwinner: Move SEPARATE_NOBITS_REGION to platforms
doc: allwinner: Reorder sections, document memory mapping
- Merge "Add Makalu ELP CPU lib" into integration
- Merge changes from topic "rd_updates" into integration
* changes:
plat/sgi: allow usage of secure partions on rdn2 platform
board/rdv1mc: initialize tzc400 controllers
plat/sgi: allow access to TZC controller on all chips
plat/sgi: define memory regions for multi-chip platforms
plat/sgi: allow access to nor2 flash and system registers from s-el0
plat/sgi: define default list of memory regions for dmc620 tzc
plat/sgi: improve macros defining cper buffer memory region
plat/sgi: refactor DMC-620 error handling SMC function id
plat/sgi: refactor SDEI specific macros
- plat/sgi: allow usage of secure partions on rdn2 platform
Add the secure partition mmap table and the secure partition boot
information to support secure partitions on RD-N2 platform. In addition
to this, add the required memory region mapping for accessing the
SoC peripherals from the secure partition.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I2c75760d6c8c3da3ff4885599be420e924aeaf3c
- Merge changes from topic "tzc400_stm32mp" into integration
* changes:
stm32mp1: add TZC400 interrupt management
stm32mp1: use TZC400 macro to describe filters
tzc400: add support for interrupts
- board/rdv1mc: initialize tzc400 controllers
A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM memory. Configure each of the TZC controllers
across the Chips.
For use by secure software, configure the first chip's trustzone
controller to protect the upper 16MB of the memory of the first DRAM
block for secure accesses only. The other regions are configured for
non-secure read write access. For all the remote chips, all the DRAM
regions are allowed for non-secure read and write access.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I809f27eccadfc23ea0ef64e2fd87f95eb8f195c1
- plat/sgi: allow access to TZC controller on all chips
On a multi-chip platform, the boot CPU on the first chip programs the
TZC controllers on all the remote chips. Define a memory region map for
the TZC controllers for all the remote chips and include it in the BL2
memory map table.
In addition to this, for SPM_MM enabled multi-chip platforms, increase
the number of mmap entries and xlat table counts for EL3 execution
context as well because the shared RAM regions and GIC address space of
remote chips are accessed.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I6f0b5fd22f9f28046451e382eef7f1f9258d88f7
- plat/sgi: define memory regions for multi-chip platforms
For multi-chip platforms, add a macro to define the memory regions on
chip numbers >1 and its associated access permissions. These memory
regions are marked with non-secure access.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: If3d6180fd8ea61f45147c39d3140d694abf06617
- plat/sgi: allow access to nor2 flash and system registers from s-el0
Allow the access of system registers and nor2 flash memory region
from s-el0. This allows the secure parititions residing at s-el0
to access these memory regions.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I3887a86770de806323fbde0d20fdc96eec6e0c3c
- plat/sgi: define default list of memory regions for dmc620 tzc
Define a default DMC-620 TZC memory region configuration and use it to
specify the TZC memory regions on sgi575, rdn1edge and rde1edge
platforms. The default DMC-620 TZC memory regions are defined
considering the support for secure paritition as well.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: Iedee3e57d0d3de5b65321444da51ec990d3702db
- plat/sgi: improve macros defining cper buffer memory region
Remove the 'ARM_' prefix from the macros defining the CPER buffer memory
and replace it with 'CSS_SGI_' prefix. These macros are applicable only
for platforms supported within plat/sgi. In addition to this, ensure
that these macros are defined only if the RAS_EXTENSION build option is
enabled.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I44df42cded18d9d3a4cb13e5c990e9ab3194daee
- plat/sgi: refactor DMC-620 error handling SMC function id
The macros defining the SMC function ids for DMC-620 error handling are
listed in the sgi_base_platform_def.h header file. But these macros are
not applicable for all platforms supported under plat/sgi. So move these
macro definitions to sgi_ras.c file in which these are consumed. While
at it, remove the AArch32 and error injection function ids as these are
unused.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I249b54bf4c1b1694188a1e3b297345b942f16bc9
- plat/sgi: refactor SDEI specific macros
The macros specific to SDEI defined in the sgi_base_platform_def.h are
not applicable for all the platforms supported by plat/sgi. So refactor
the SDEI specific macros into a new header file and include this file on
only on platforms it is applicable on.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I0cb7125334f02a21cae1837cdfd765c16ab50bf5
- Merge "driver: brcm: add i2c driver" into integration
- Merge "doc: update maintainer list for Arm platforms" into integration
- Merge "doc: re-format maintainer.rst file rendering" into integration
- driver: brcm: add i2c driver
Broadcom I2C controller driver. Follwoing API's are supported:-
- i2c_init() Intialize ethe I2C controller
- i2c_probe()
- i2c_set_bus_speed() Set the I2C bus speed
- i2c_get_bus_speed() Get the current bus speed
- i2c_recv_byte() Receive one byte of data.
- i2c_send_byte() Send one byteof data
- i2c_read_byte() Read single byte of data
- i2c_read() Read multiple bytes of data
- i2c_write_byte Write single byte of data
- i2c_write() Write multiple bytes of data
This driver is verified by reading the DDR SPD data.
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Change-Id: I2d7fe53950e8b12fab19d0293020523ff8b74e13
- allwinner: H616: Add reserved-memory node to DT
When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure
we tell the non-secure world about the memory region it uses.
Add a reserved-memory node to the DT, which covers the area that BL31
could occupy. The "no-map" property will prevent OSes from mapping
the area, so there would be no speculative accesses.
Change-Id: I808f3e1a8089da53bbe4fc6435a808e9159831e1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
ENABLE_PIE (position independent executable) is default on K3
platform to handle variant RAM configurations in the system. This,
unfortunately does cause confusion while reading the code, so, lets
make things explicit by selecting 0x0 as the "SEC_SRAM_BASE" out of
which we compute the BL31_BASE depending on usage.
Lets also document a warning while at it to help folks copying code
over to a custom K3 platform and optimizing size by disabling PIE to
modify the defaults.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I8e67a9210e907e266ff6a78ba4d02e3259bb2b21
- plat: ti: k3: board: Lets cast our macros
Lets cast our macros to the right types and reduce a few MISRA
warnings.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I0dc06072713fe7c9440eca0635094c5f3ceb7f1c
- plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computing
We compute BL31_END - BL31_START on the fly, which is basically
BL31_SIZE. Lets just use the BL31_SIZE directly so that we dont
complicate PIE relocations when actual address is +ve and -ve offsets
relative to link address.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I5e14906381d2d059163800d39798eb39c42da4ec
- plat: ti: k3: platform_def.h: Define the correct number of max table entries
Since we are using static xlat tables, we need to account for exact
count of table entries we are actually using.
peripherals usart, gic, gtc, sec_proxy_rt, scfg and data account for 6 entries
and are constant, however, we also need to account for:
bl31 full range, codebase, ro_data as additional 3 region
With USE_COHERENT_MEM we do add in 1 extra region as well.
This implies that we will have upto 9 or 10 regions based on
USE_COHERENT_MEM usage. Vs we currently define 8 regions.
This gets exposed with DEBUG=1 and assert checks trigger, which for some
reason completely escaped testing previously.
ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:97
BACKTRACE: START: assert
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I962cdfc779b4eb3b914fe1c46023d50bc289e6bc
- plat: ti: k3: board: lite: Increase SRAM size to account for additional table
We actually have additional table entries than what we accounted for in
our size. MAX_XLAT_TABLES is 8, but really we could be using upto 10
depending on the platform. So, we need an extra 8K space in.
This gets exposed with DEBUG=1 and assert checks trigger, which for some
reason completely escaped testing previously.
ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:97
BACKTRACE: START: assert
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I5c5d04440ef1fccfaf2317066f3abbc0ec645903
- allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.
The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.
Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- allwinner: Add H616 SoC ID
Change-Id: I557fd05401e24204952135cf3ca26479a43ad1f1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- allwinner: Express memmap more dynamically
In preparation for changing the memory map, express the locations of the
various code and data pieces more dynamically, allowing SoCs to override
the memmap later.
Also prepare for the SCP region to become optional.
No functional change.
Change-Id: I7ac01e309be2f23bde2ac2050d8d5b5e3d6efea2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- allwinner: Move sunxi_cpu_power_off_self() into platforms
The code to power the current core off when SCPI is not available is now
different for the two supported SoC families.
To make adding new platforms easier, move sunxi_cpu_power_off_self()
into the SoC directory, so we don't need to carry definitions for both
methods for all SoCs.
On the H6 we just need to trigger the CPUIDLE hardware, so can get rid
of all the code to program the ARISC, which is now only needed for the
A64 version.
Change-Id: Id2a1ac7dcb375e2fd021b441575ce86b4d7edf2c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- allwinner: Move SEPARATE_NOBITS_REGION to platforms
For the existing SoCs we support, we use SEPARATE_NOBITS_REGION, to move
some parts of the data into separate memory regions (to save on the SRAM
A2 we are loaded into).
For the upcoming H616 platform this is of no concern (we run in DRAM),
so make this flag a platform choice instead.
Change-Id: Ic01d49578c6274660f8f112bd23680d3eca3be7a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- doc: allwinner: Reorder sections, document memory mapping
Update the Allwinner platform documentation.
Reorder the section, to have the build instructions first, followed by
hints about the installation.
Add some ASCII art about the layout of our virtual memory map, which
uses a non-trivial condensed virtual address space.
Change-Id: Iaaa79b4366012394e15e4c1b26c212b5efb6ed6a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- Merge "allwinner: Use CPUIDLE hardware when available" into integration
- Merge "allwinner: A64: Limit FDT checks to reduce code size" into integration
- allwinner: A64: Limit FDT checks to reduce code size
The upcoming refactoring to support the new H616 SoCs will push the A64
build over the edge, by using more than the 48KB of SRAM available.
To reduce the code size, set some libfdt options that aim to reduce
sanity checks (for saving code space):
- ASSUME_LATEST: only allow v17 DTBs (as created by dtc)
- ASSUME_NO_ROLLBACK: don't prepare for failed DT additions
- ASSUME_LIBFDT_ORDER: assume sane ordering, as done by dtc
Change-Id: I12c93ec09e7587c5ae71e54947f817c32ce5fd6d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- Merge "plat/allwinner: do not setup 'disabled' regulators" into integration
- Add Makalu ELP CPU lib
Add basic support for Makalu ELP processor core.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7b1ddbb8dd43326ecb8ff188f6f8fcf239826a93
- Merge changes I500ddbe9,I9c10dac9,I53bfff85,I06f7594d,I24bff8d4, ... into integration
* changes:
nxp lx2160a-aqds: new plat based on soc lx2160a
NXP lx2160a-rdb: new plat based on SoC lx2160a
nxp lx2162aqds: new plat based on soc lx2160a
nxp: errata handling at soc level for lx2160a
nxp: make file for loading additional ddr image
nxp: adding support of soc lx2160a
nxp: deflt hdr files for soc & their platforms
nxp: platform files for bl2 and bl31 setup
nxp: warm reset support to retain ddr content
nxp: nv storage api on platforms
nxp: supports two mode of trusted board boot
nxp: fip-handler for additional fip_fuse.bin
nxp: fip-handler for additional ddr-fip.bin
nxp: image loader for loading fip image
nxp: svp & sip smc handling
nxp: psci platform functions used by lib/psci
nxp: helper function used by plat & common code
nxp: add data handler used by bl31
nxp: adding the driver.mk file
nxp-tool: for creating pbl file from bl2
nxp: adding the smmu driver
nxp: cot using nxp internal and mbedtls
nxp:driver for crypto h/w accelerator caam
nxp:add driver support for sd and emmc
nxp:add qspi driver
nxp: add flexspi driver support
nxp: adding gic apis for nxp soc
nxp: gpio driver support
nxp: added csu driver
nxp: driver pmu for nxp soc
nxp: ddr driver enablement for nxp layerscape soc
nxp: i2c driver support.
NXP: Driver for NXP Security Monitor
NXP: SFP driver support for NXP SoC
NXP: Interconnect API based on ARM CCN-CCI driver
NXP: TZC API to configure ddr region
NXP: Timer API added to enable ARM generic timer
nxp: add dcfg driver
nxp:add console driver for nxp platform
tools: add mechanism to allow platform specific image UUID
tbbr-cot: conditional definition for the macro
tbbr-cot: fix the issue of compiling time define
cert_create: updated tool for platform defined certs, keys & extensions
tbbr-tools: enable override TRUSTED_KEY_CERT
- Merge "rpi4: Switch to gicv2.mk and GICV2_SOURCES" into integration
- nxp lx2160a-aqds: new plat based on soc lx2160a
New NXP platform lx2160a-qds:
- Based SoC lx2160a
- Board specific tuning for DDR init.
- Board specific Flash details.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I500ddbe9e56c4af5f955da6ecbd4ddc5fbe89a12
- NXP lx2160a-rdb: new plat based on SoC lx2160a
New NXP platform lx2160a-rdb(Reference Design Board):
- Based SoC lx2160a
- Board specific tuning for DDR init.
- Board specific Flash details.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9c10dac9d5e67d44a2d94a7a27812220fdcc6ae3
- nxp lx2162aqds: new plat based on soc lx2160a
New NXP platform lx2162aqds:
- Based SoC lx2160a
- Board specific tuning for DDR init.
- Board specific Flash details.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I53bfff85398313082db77c77625cb2d40cd9b1b1
- nxp: errata handling at soc level for lx2160a
SoC erratas are handled as part of this commit.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I06f7594d19cc7fc89fe036a8a255300458cb36dd
- nxp: make file for loading additional ddr image
- NXP SoC lx2160a needs additional ddr_fip.bin.
- There are three types of ddr image that can be created:
-- ddr_fip.mk for creating fip_ddr.bin image for normal boot.
-- ddr_fip_sb.mk for creating fip_ddr_sec.bin image for NXP CSF based
CoT/secure boot.
-- ddr_fip_tbbr.mk for creating fip_ddr_sec.bin image for MBEDTLS
CoT/secure boot.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I24bff8d489f72da99f64cb79b2114faa9423ce8c
- nxp: adding support of soc lx2160a
* NXP SoC is 16 A-72 core SoC.
* SoC specific defines are defined in:
- soc.def
- soc.h
* Called for BL2 and BL31 setup, SoC specific setup are implemented in:
- soc.c
* platform specific helper functions implemented at:
- aarch64/lx2160a_helpers.S
* platform specific functions used by 'plat/nxp/commpon/psci',
etc. are implemented at:
- aarch64/lx2160a.S
* platform specific implementation for handling PSCI_SYSTEM_RESET2:
- aarch64/lx2160a_warm_rst.S
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ib40086f9d9079ed9b22967baff518c6df9f408b8
- nxp: deflt hdr files for soc & their platforms
- Default header files for:
-- plat/nxp/soc-lxxxx/include/soc.h uses:
--- soc_default_base_addr.h
--- soc_default_base_macros.h
-- plat/nxp/soc-lxxxx/<$PLAT>/platform_def.h uses:
--- plat_default_def.h: Every macro define can be overidden.
-- include/common/tbbr/tbbr_img_def.h uses:
--- plat_tbbr_img_def.h: platform specific new FIP image macros.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ic50003e27e87891be3cd18bdb4e14a1c7272d492
- nxp: platform files for bl2 and bl31 setup
For NXP platforms:
- Setup files for BL2 and BL31
- Other supporting files.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I36a1183a0652701bdede9e02d41eb976accbb017
- nxp: warm reset support to retain ddr content
NXP: Added warm reset handler to handle SMC PSCI_SYSTEM_RESET2
raised from kernel (> 5.4).
As part of first cold boot, DDR training data is stored in NV storage.
As part of this SMC handling, following things are done:
- DDR is put in self-refresh mode to retain the content of DDR.
- Reset cause is saved.
- Reset is triggered.
On next boot to last warm-reset, DDR training is restored from
the NV storage.
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I8e4fb0824887af49e959c93825e2ab0ba887fc9d
- nxp: nv storage api on platforms
NV storage API(s) for NXP platforms, supported on:
- flexspi-nor
- SecMon - General Purpose Registers at Low-Power section,
retains their content if backed by coined battery.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Id65dee4f28e7d6d2024407030039de33ebe0fa05
- nxp: supports two mode of trusted board boot
NXP SoC supports two TBB mode:
- MBED_TLS based
-- ROTK key hash is placed as part of the BL2 binary at section:
--- .rodata.nxp_rotpk_hash
-- Supporting non-volatile counter via SFP.
-- platform function used by TFA common authentication code.
- NXP CSF based
-- ROTK key deployment vary from MBEDTLS
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ib0f0bf024fd93de906c5d4f609383ae9e02b2fbc
- nxp: fip-handler for additional fip_fuse.bin
All of the NXP SoC, needs fip_fuse image to be
loaded additionally as part of preparation for Trusted board boot
- fip_fuse.bin contains an image for auto fuse provisioning.
- Auto fuse provisioning is based on the input file with values for:
-- SRK Hash
-- OTPMK
-- misc. refer board manual for more details.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I26d4024fefe352d967ca120191f784f1f47aa9d1
- nxp: fip-handler for additional ddr-fip.bin
Few of the NXP SoC like LX2160A, needs ddr-phy images to be
loaded additionally before DDR initialization
- fip_ddr.bin is created containing upto 6 ddr images.
- With TRUSTED_BOARD_BOOT = 1, fip_ddr.bin is authenticated
first before loading and starting DDR initialization.
- To successfully compile this image, platform-defined header files
needs to be defined:
-- include/common/tbbr/tbbr_img_def.h uses:
--- plat_tbbr_img_def.h: platform specific new FIP image macros.
-- include/tools/share/firmware_image_package.h uses:
--- plat_def_fip_uuid.h: platform specific new UUID macros.
---- Added UUID for DDR images to create FIP-DDR.
---- Added UUID for FUSE provisioning images to create FIP-fuse.
-- include/tools/share/tbbr_oid.h uses:
--- platform_oid.h: platform specific new OID macros.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Icbcf1673a8c398aae98680b5016f4276b4864b91
- nxp: image loader for loading fip image
function load_img(), is dependent on:
- Recursively calling load_image() defined in common/bl_common.c
- for each image in the fip.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I57ca4b666cd1b0b992b7c0fc2a4260b558c0e2a9
- nxp: svp & sip smc handling
SMC call handling at EL3 due SIP and SVC calls.
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: If86ee43477fc3b6116623928a3299d4e9015df8c
- nxp: psci platform functions used by lib/psci
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9853263ed38fb2a9f04b9dc7d768942e32074719
- nxp: helper function used by plat & common code
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Idafd8b0d94edf3515e8317431274d77289b7a1d0
- nxp: add data handler used by bl31
bl31-data file written in assembly helps to manage data at bl31.
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ic3ace03364648cc1174bb05b5b334b9ccdaaa4ed
- nxp: adding the driver.mk file
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ic6c3a173f9f1f7b85244fc4484e247fdbb438b9c
- nxp-tool: for creating pbl file from bl2
NXP tool to create pbl from bl2 binary:
- RCW is prepended to BL2.bin
- If TRUSTED_BOARD_BOOT=1, pre-append the CSF header
to be understood by NXP boot-rom.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Iddc7336a045222e2073ddad86358ebc4440b8bcf
- nxp: adding the smmu driver
NXP SMMU driver API for NXP SoC.
- Currently it supports by-passing SMMU, called only when NXP CAAM
is enabled.
- (TBD) AMQ based SMMU access control: Access Management Qualifiers (AMQ)
advertised by a bus master for a given transaction.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I23a12928ddedb1a2cf4b396606e35c67e016e331
- nxp: cot using nxp internal and mbedtls
Chain of trust(CoT) is enabled on NXP SoC in two ways:
- Using MbedTLS, parsing X509 Certificates.
- Using NXP internal method parsing CSF header
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I78fb28516dfcfa667bebf8a1951ffb24bcab8de4
- nxp:driver for crypto h/w accelerator caam
NXP has hardware crypto accelerator called CAAM.
- Work with Job ring
- Jobs are submitted to CAAM in the form of 64 word
descriptor.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I02bcfce68143b8630e1833a74c4b126972f4323d
- nxp:add driver support for sd and emmc
SD & eMMC driver support for NXP SoC.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I245fecd2c791697238b5667c46bf5466379695ce
- nxp:add qspi driver
NXP QuadSPI driver support NXP SoC.
- Supporting QSPI flash
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I928cbec8ea31f4d8f9e320ac9c5105f7ab0ecb73
- nxp: add flexspi driver support
Flexspi driver now introduces read/write/erase APIs for complete flash
size, FAST-READ are by default used and IP bus is used for erase, read
and write using flexspi APIs.
Framework layer is currently embedded in driver itself using flash_info
defines.
Test cases are also added to confirm flash functionality currently under
DEBUG flag.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Change-Id: I755c0f763f6297a35cad6885f84640de50f51bb0
- nxp: adding gic apis for nxp soc
GIC api used by NXP SoC is based on:
- arm provided drivers: /drivers/arm/gic
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: If3d470256e5bd078614f191e56062c4fbd97f8bd
- nxp: gpio driver support
NXP General Purpose Input/Output driver support for
NXP platforms.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9a3574f1d5d12e4a65ff60f640d4e77e2defd6d4
- nxp: added csu driver
NXP Central Security Unit(CSU) for NXP SoC.
CSU is used for:
- Access permissions for peripheral that donot have their own
access control.
- Locking of individual CSU settings until the next POR
- General purpose security related control bits
Refer NXP SoC manuals fro more details.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I07a4729c79c5e2597f8b2a782e87e09f7f30c2ca
- nxp: driver pmu for nxp soc
Driver for NXP IP for Power Management Unit.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I855657eddab357cb182419b188ed8861c46a1b19
- nxp: ddr driver enablement for nxp layerscape soc
DDR driver for NXP layerscape SoC(s):
- lx2160aqds
- lx2162aqds
- lx2160ardb
- Other Board with SoC(s) like ls1046a, ls1043a etc;
-- These other boards are not verified yet.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ic84a63cb30eba054f432d479862cd4d1097cbbaf
- nxp: i2c driver support.
NXP I2C driver support for NXP SoC(s).
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I234b76f9fa1b30dd13aa087001411370cc6c8dd0
- NXP: Driver for NXP Security Monitor
NXP Security Monitor IP provides hardware anchored
- current security state of the SoC.
- Tamper detect etc.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I8ff809fe2f3fd013844ab3d4a8733f53c2b06c81
- NXP: SFP driver support for NXP SoC
NXP Security Fuse Processor is used to read and write
fuses.
- Fuses once written, are cannot be un-done.
- Used as trust anchor for monotonic counter,
different platform keys etc.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I347e806dd87078150fbbbfc28355bb44d9eacb9c
- NXP: Interconnect API based on ARM CCN-CCI driver
CCN API(s) to be used NXP SoC(s) are added.
These API(s) based on ARM CCN driver
- driver/arm/ccn
CCI API(s) to be used NXP SoC(s) are added.
These API(s) based on ARM CCI driver
- driver/arm/cci
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I7682c4c9bd42f63542b3ffd3cb6c5d2effe4ae0a
- NXP: TZC API to configure ddr region
NXP TZC-400 API(s) to configure ddr regions are based on:
- drivers/arm/tzc
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I524433ff9fafe1170b13e99b7de01fe957b6d305
- NXP: Timer API added to enable ARM generic timer
NXP Timer Apis are based on:
- drivers/delay_timer
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cbccf4c082a10affee1143390905b9cc99c3382
- nxp: add dcfg driver
NXP SoC needs Device Configuration driver to
fetch the current SoC configuration.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ie17cca01a8eb9a6f5feebb093756f577692432bf
- nxp:add console driver for nxp platform
NXP SoCs, supports two types of UART controller:
- PL011 - using ARM drivers sources
- 16550 - using TI drivers source
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Iacbcefd2b6e5d96f83fa00ad25b4f63a4c822bb4
- tools: add mechanism to allow platform specific image UUID
Generic framework is added to include platform defined UUID.
This framework is added for the following:
- All NXP SoC based platforms needed additional fip-fuse.bin
- NXP SoC lx2160a based platforms requires additional fip-ddr.bin
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ibe05d9c596256e34077287a490dfcd5b731ef2cf
- tbbr-cot: conditional definition for the macro
Conditional definition for the macro MAX_NUMBER_IDS.
This will allow to update this definition by the platform
specific implementation.
Since, NXP SoC lx2160a based platforms requires additional
FIP DDR to be loaded before initializing the DDR.
It requires addition of defines for DDR image IDs.
A dedicated header plat_tbbr_img_def.h is added to the platform
folder - plat/nxp/common/include/default/
Inclusion of this header file will depend on the compile time
flag PLAT_TBBR_IMG_DEF.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I4faba74dce578e2a34acbc8915ff75d7b8368cee
- tbbr-cot: fix the issue of compiling time define
Incorrect value is picked for TF_MBEDTLS_USE_RSA defination,
even if the TF_MBEDTLS_RSA is enabled.
Due to which PK_DER_LEN is defined incorrectly.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2ca4ca121e0287b88ea689c885ddcd45a34a3e91
- cert_create: updated tool for platform defined certs, keys & extensions
Changes to 'tools/cert_create' folder, to include platform defined
certificates, keys, and extensions.
NXP SoC lx2160a : based platforms requires additional
FIP DDR to be loaded before initializing the DDR.
To enable chain of trust on these platforms, FIP DDR
image needs to be authenticated, additionally.
Platform specific folder 'tools/nxp/cert_create_helper'
is added to support platform specific macros and definitions.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I4752a30a9ff3aa1d403e9babe3a07ba0e6b2bf8f
- tbbr-tools: enable override TRUSTED_KEY_CERT
Platforms, which requires additional images to be
verified using TBBR; such that their key certificate
is tied to TRUSTED_KEY_CERT.
For such platforms, if make commands runs twice:
- Once with targets as bl2 & fip.bin, and
- Again to build the target as the additional image.
then, if path to the TRUSTED_KEY_CERT varies in the
makefile with make-target of the additional image, then
there would be two location where "trusted_key.crt" will
be created.
This patch helps overriding the TRUSTED_KEY_CERT from any .mk
in the platform's makefile structure.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I775a2c409035504b21b0bbe5a4f9046898163eed
- allwinner: Use CPUIDLE hardware when available
This works even on SoCs that do not have an ARISC, and it avoids
clobbering whatever ARISC firmware might be running.
Change-Id: I9f2fed597189bb387de79e8e76a7da3375e1ee91
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- Merge "fdt: Use proper #address-cells and #size-cells for reserved-memory" into integration
- fdt: Use proper #address-cells and #size-cells for reserved-memory
The devicetree binding document[1] for the /reserved-memory node demands
that the number of address and size-cells in the reserved-memory node
must match those values in the root node. So far we were forcing a
64-bit address along with a 32-bit size.
Adjust the code to query the cells values from the root node, and
populate the newly created /reserved-memory node accordingly.
This fixes the fdt_add_reserved_memory() function when called on a
devicetree which does not use the 2/1 pair. Linux is picky about this
and will bail out the parsing routine, effectively ignoring the
reserved-memory node:
[ 0.000000] OF: fdt: Reserved memory: unsupported node format, ignoring
[1] Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
in the Linux kernel source tree
Change-Id: Ie126ebab4f3fedd48e12c9ed4bd8fa123acc86d3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- plat: imx8mm: Add in BL2 with FIP
Adds bl2 with FIP to the build required for mbed Linux booting where
we do:
BootROM -> SPL -> BL2 -> OPTEE -> u-boot
If NEED_BL2 is specified then BL2 will be built and BL31 will have
its address range modified upwards to accommodate. BL31 must be
loaded from a FIP in this case.
If NEED_BL2 is not specified then the current BL31 boot flow is
unaffected and u-boot SPL will load and execute BL31 directly.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I655343b3b689b1fc57cfbedda4d3dc2fbd549a96
- plat: imx8mm: Enable Trusted Boot
This patch enables Trusted Boot on the i.MX8MM with BL2 doing image
verification from a FIP prior to hand-over to BL31.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I3c22783a5c49544d0bace8ef3724784b9b7cc64a
- plat: imx8mm: Add image load logic for TBBR FIP booting
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I0557ce6d0aa5ab321cac1ee25280b96762024396
- plat: imx8mm: Add initial defintions to facilitate FIP layout
Adds a number of definitions consistent with the established WaRP7
equivalents specifying number of io_handles and block devices.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: If1d7ef1ad3ac3dfc860f949392c7534ce8d206e3
- plat: imx8mm: Add image io-storage logic for TBBR FIP booting
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I9833a54d0938d70886ac88b1922b17edf1dee8e0
- plat: imx8mm: Add imx8mm_private.h to the build
Allows for exporting of FIP related methods cleanly in a private header.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I8523f1370312ed22ff7ca710cd916be52f725e3c
- stm32mp1: add TZC400 interrupt management
TZC400 is configured to raise an interrupt in case of faulty access.
Call the new added tzc400_it_handler, in case this interrupt occurs.
Change-Id: Iaf4fa408a8eff99498042e11e2d6177bad39868c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
- stm32mp1: use TZC400 macro to describe filters
On STM32MP15, only filters 0 and 1 are used.
Use TZC_400_REGION_ATTR_FILTER_BIT() macro for those 2 filters 0 and 1
instead of U(3).
Change-Id: Ibc61823842ade680f59d5b66b8db59b6a30080e4
Signed-off-by: Yann Gautier <yann.gautier@st.com>
- tzc400: add support for interrupts
A new function tzc400_it_handler() is created to manage TZC400
interrupts. The required helpers to read and clear interrupts are added
as well.
In case DEBUG is enabled, more information about the faulty access
(address, NSAID, type of access) is displayed.
Change-Id: Ie9ab1c199a8f12b2c9472d7120efbdf35711284a
Signed-off-by: Yann Gautier <yann.gautier@st.com>
- Merge "SPM: Fix error codes size in SPMD handler" into integration
- rpi4: Switch to gicv2.mk and GICV2_SOURCES
Addresses the deprecation warning produced by
drivers/arm/gic/common/gic_common.c.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I1a3ff4835d0f94c74b405db10622e99875ded82b
- Merge "plat: xilinx: versal: Mark IPI calls secure/non-secure" into integration
- plat: xilinx: versal: Mark IPI calls secure/non-secure
BIT24 of IPI command header is used to determine if caller is
secure or non-secure.
Mark BIT24 of IPI command header as non-secure if SMC caller
is non-secure.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iec25af8f4b202093f58e858ee47cd9cd46890267
- SPM: Fix error codes size in SPMD handler
FF-A specification states that error codes should be typed int32_t.
SPMD's uses uint64_t for return values, which if assigned with a signed
type would have sign extension, and change the size of the return from
32-bit to 64-bit.
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I288ab2ffec8330a2fe1f21df14e22c34bd83ced3
- plat/allwinner: do not setup 'disabled' regulators
If a PMIC regulator has its DT node disabled, leave the regulator off.
Change-Id: I895f740328e8f11d485829c3a89a9b9f8e5644be
Signed-off-by: Roman Beranek <roman.beranek@prusa3d.com>
- Merge "Bug fix in tspd interrupt handling when TSP_NS_INTR_ASYNC_PREEMPT is enabled" into integration
- Merge "tools_share/uuid: Add EFI_GUID representation" into integration
- Merge "plat: xilinx: versal: Remove cortex-a53 compilation" into integration
- Bug fix in tspd interrupt handling when TSP_NS_INTR_ASYNC_PREEMPT is enabled
Typically, interrupts for a specific security state get handled in the
same security execption level if the execution is in the same security
state. For example, if a non-secure interrupt gets fired when CPU is
executing in NS-EL2 it gets handled in the non-secure world.
However, interrupts belonging to the opposite security state typically
demand a world(context) switch. This is inline with the security
principle which states a secure interrupt has to be handled in the
secure world. Hence, the TSPD in EL3 expects the context(handle) for a
secure interrupt to be non-secure and vice versa.
The function "tspd_sel1_interrupt_handler" is the handler registered
for S-EL1 interrupts by the TSPD. Based on the above assumption, it
provides an assertion to validate if the interrupt originated from
non-secure world and upon success arranges entry into the TSP at
'tsp_sel1_intr_entry' for handling the interrupt.
However, a race condition between non-secure and secure interrupts can
lead to a scenario where the above assumptions do not hold true and
further leading to following assert fail.
This patch fixes the bug which causes this assert fail:
ASSERT: services/spd/tspd/tspd_main.c:105
BACKTRACE: START: assert
0: EL3: 0x400c128
1: EL3: 0x400faf8
2: EL3: 0x40099a4
3: EL3: 0x4010d54
BACKTRACE: END: assert
Change-Id: I359d30fb5dbb1429a4a3c3fff37fdc64c07e9414
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
- Merge "plat: xilinx: Add timeout while waiting for IPI Ack" into integration
- tools_share/uuid: Add EFI_GUID representation
The UEFI specification details the represenatation
for the EFI_GUID type. Add this representation to the
uuid_helper_t union type so that GUID definitions
can be shared verbatim between UEFI and TF-A header
files.
Change-Id: Ie44ac141f70dd0025e186581d26dce1c1c29fce6
Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
- Merge "mmc:prevent accessing to the released space in case of wrong usage" into integration
- arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms
The speculation barrier feature (`FEAT_SB`) was introduced with and
made mandatory in the Armv8.5-A extension. It was retroactively made
optional in prior extensions, but the checks in our code-base do not
reflect that, assuming that it is only available in Armv8.5-A or later.
This change introduces the `ENABLE_FEAT_SB` definition, which derives
support for the `sb` instruction in the assembler from the feature
flags passed to it. Note that we assume that if this feature is enabled
then all the cores in the system support it - enabling speculation
barriers for only a subset of the cores is unsupported.
Signed-off-by: Chris Kay <chris.kay@arm.com>
Change-Id: I978ed38829385b221b10ba56d49b78f4756e20ea
- Merge "tzc400: correct FAIL_CONTROL Privileged bit" into integration
- mmc:prevent accessing to the released space in case of wrong usage
1.Since in mmc_init, the most of mmc_device_info passed in are temporary variables.
In order to avoid referencing the released space on the stack when maybe MISUSED,
it`s better to use global variables to store mmc_device_info in mmc.c
2.Delete redundant;
Signed-off-by: deqi.hu@siengine.com
Change-Id: I51ae90e7f878b19b4963508b3f7ec66339015ebc
- Merge changes from topic "od/ffa_spmc_pwr" into integration
* changes:
SPM: declare third cactus instance as UP SP
SPMD: lock the g_spmd_pm structure
FF-A: implement FFA_SECONDARY_EP_REGISTER
- plat: xilinx: versal: Remove cortex-a53 compilation
Versal is a72 based that's why there is no reason to build low level
assemble code for a53.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Iff9cf2582102d951825b87fd9af18e831ca717d6
- Merge changes from topic "matterhorn_elp" into integration
* changes:
plat: tc0: add matterhorn_elp_arm library to tc0
cpus: add Matterhorn ELP ARM cpu library
- SPM: declare third cactus instance as UP SP
The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many ECs as the number of PEs.
An EC is pinned to a corresponding physical CPU.
-An UniProcessor (UP) SP instantiates a single EC. The EC is migrated to
the physical CPU from which the FF-A call is originating.
This change permits exercising the latter case within the TF-A-tests
framework.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I7fae0e7b873f349b34e57de5cea496210123aea0
- SPMD: lock the g_spmd_pm structure
Add a lock and spin lock/unlock calls when accessing the fields of the
SPMD PM structure.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9bab705564dc1ba003c29512b1f9be5f126fbb0d
- FF-A: implement FFA_SECONDARY_EP_REGISTER
Remove the former impdef SPMD service for SPMC entry point
registration. Replace with FFA_SECONDARY_EP_REGISTER ABI
providing a single entry point address into the SPMC for
primary and secondary cold boot.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I067adeec25fc12cdae90c15a616903b4ac4d4d83
- Merge changes from topic "linux_as_bl33" into integration
* changes:
plat/arm: Remove ARM_LINUX_KERNEL_AS_BL33 relying on RESET_TO_BL31
plat/arm: Always allow ARM_LINUX_KERNEL_AS_BL33
- doc: update maintainer list for Arm platforms
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I24a1697d0e0ec9289d272f0e96a252894faf12ef
- doc: re-format maintainer.rst file rendering
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I9fafeb966eeec35527647282b953d88f6aa383be
- plat: tc0: add matterhorn_elp_arm library to tc0
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: Ie199c60553477c43d1665548ae78cdfd1aa7ffcf
- cpus: add Matterhorn ELP ARM cpu library
Change-Id: Ie1acde619a5b21e09717c0e80befb6d53fd16607
Signed-off-by: Usama Arif <usama.arif@arm.com>
- Merge changes I9c9ed516,I2788eaf6 into integration
* changes:
qemu/qemu_sbsa: fix memory type of secure NOR flash
qemu/qemu_sbsa: spm_mm supports 512 cores
- Merge "plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices" into integration
- driver: brcm: add USB driver
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Change-Id: I456aa7a641fffa8ea4e833615af3effec42a31b2
- Merge "plat/rockchip: Use common gicv2.mk" into integration
- plat/rockchip: Use common gicv2.mk
Compiling BL31 for the Rockchip platform now produces a message about
the deprecation of gic_common.c.
Follow the advice and use include gicv2.mk instead.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I396b977d57975dba27cfed801ad5264bbbde2b5e
- Merge "mediatek: mt8192: fix MISSING_BREAK" into integration
- tzc400: correct FAIL_CONTROL Privileged bit
When bit 20 of TZC400 Fail control register [1] is set to 1, it means
Privileged access, the macros FAIL_CONTROL_PRIV_PRIV and
FAIL_CONTROL_PRIV_UNPRIV are then updated to reflect this.
[1] https://developer.arm.com/documentation/ddi0504/c/programmers-model/register-descriptions/fail-control-register?lang=en
Change-Id: I01e522fded5cf66c9827293ddcf543c79f9e509e
Signed-off-by: Yann Gautier <yann.gautier@st.com>
- mediatek: mt8192: fix MISSING_BREAK
The case for value "VCOREFS_SMC_CMD_INIT" is not
terminated by a "break" statement.
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I56cc7c1648e101c0da6e77e592e6edbd5d37724e
- Merge "SDEI: updata the affinity of shared event" into integration
- SDEI: updata the affinity of shared event
when updata routing of an SDEI event, if the registration flags
is SDEI_REGF_RM_PE, need to updata the affinity of shared event.
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Change-Id: Ie5d7cc4199253f6af1c28b407f712caac3092d06
- Merge changes I76eee5c5,Ie45ab1d8,Iddcb83d3,I4425777d,I5be2837c, ... into integration
* changes:
drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()
drivers/gicv3: add debug log for maximum INTID of SPI and eSPI
drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET()
drivers/gicv3: fix logical issue for num_eints
drivers/gicv3: fix potential GICD context override with ESPI enabled
drivers/gicv3: use mpidr to probe GICR for current CPU
- Merge "Print newline after hex address in aarch64 el3_panic function" into integration
- Print newline after hex address in aarch64 el3_panic function
Make the aarch64's el3_panic() function print a newline character after
PC address, otherwise the output can get mangled in one line with output
from other firmware. Here is an example of how the output of el3_panic()
got mangled with Linux' console output:
ERROR: Unhandled External Abort received on 0x80000001 at EL3!
ERROR: exception reason=1 syndrome=0x92000210
PANIC at PC : 0x0000000004027400[13438.473133] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[13438.479255] rcu: 1-...0: (4 ticks this GP) idle=35e/1/0x4000000000000000 softirq=146459/146459 fqs=2625
The aarch32 version of this function already does this.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I9f0d032c6cd1e2be7a1837f9c8e8244d30633993
- Merge "docs: Add GIC600AE FVP model version information" into integration
- Merge "mediatek: mt8192: Add MPU Support for SCP/PCIe" into integration
- Merge changes I4bd4612a,Id13a06d4,I0ea7f610,Ie6a7063b into integration
* changes:
mediatek: mt8192: Add Vcore DVFS driver
mediatek: mt8192: Add SPM suspend driver
mediatek: mt8192: supports mcusys off when system suspend
mediatek: mt8192: Add lpm driver
- mediatek: mt8192: Add MPU Support for SCP/PCIe
1 Only enable domain D0 and D1:PCIe access 0xC0000000~0xC4000000;
2 Only enable domain D0 and D3(SCP) access 0x50000000~0x51400000;
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ic4f9e6d85bfd1cebdb24ffc1d14309c89c103b2a
- mediatek: mt8192: Add Vcore DVFS driver
Change-Id: I4bd4612a7c7727a5be70957ae940e5f51c7ca5e6
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
- mediatek: mt8192: Add SPM suspend driver
Supports dram/mainpll/26m off when system suspend
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: Id13a06d4132f00fb60066de75920ecac18306e32
- mediatek: mt8192: supports mcusys off when system suspend
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I0ea7f61085ea9ba26c580107ef0cb9940a25f5e2
- mediatek: mt8192: Add lpm driver
Low Power Management (LPM) helps find a suitable configuration
for letting system entering idle or suspend with the most
resources off.
Change-Id: Ie6a7063b666cf338cff5bc972c9025b26de482eb
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
- plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices
Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp
devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are
0x7d, 0x78 and 0x7f.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I566f707116d83475de7c87a6004ca96bf7bccebe
- Merge "fdts: enable virtIO P9 device for morello fvp platform" into integration
- Merge "Add Makalu CPU lib" into integration
- Merge "lib/extensions/ras: fix bug of binary search" into integration
- fdts: enable virtIO P9 device for morello fvp platform
Signed-off-by: sah01 <sahil@arm.com>
Change-Id: Ic11d739c0bf2076354716cc06fbe25e9000a21e7
- Merge "Enable v8.6 AMU enhancements (FEAT_AMUv1p1)" into integration
- plat: xilinx: Add timeout while waiting for IPI Ack
Return timeout error if, IPI is not acked in specified timeout.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Change-Id: I27be3d4d4eb5bc57f6a84c839e2586278c0aec19
- Add Makalu CPU lib
Add basic support for Makalu CPU.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I4e85d425eedea499adf585eb8ab548931185043d
- Merge changes from topic "trng-svc" into integration
* changes:
plat/arm: juno: Use TRNG entropy source for SMCCC TRNG interface
plat/arm: juno: Condition Juno entropy source with CRC instructions
- docs: Add GIC600AE FVP model version information
Added GIC600AE FVP model version information.
Change-Id: I15d25fbdb8e09900976d5993032ec049f8db79f2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
- qemu/qemu_sbsa: fix memory type of secure NOR flash
This commit fixes the wrong memory type, secure NOR flash
shall be mapped as MT_DEVICE.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I9c9ed51675d84ded675bb56b2e4ec7a08184c602
- qemu/qemu_sbsa: spm_mm supports 512 cores
sbsa-ref in QEMU may create up to 512 cores.
This commit prepares the MP information to support 512 cores.
The number of xlat tables for spm_mm is also increased.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I2788eaf6d14e188e9b5d1102d359b2899e02df7c
- Merge "plat/qemu: trigger reboot with secure pl061" into integration
- Enable v8.6 AMU enhancements (FEAT_AMUv1p1)
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0. This patch enables support for this
feature in EL3 firmware.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217
- Merge changes I23f600b5,Icf9ffdf2,Iee7a51d1,I99afc312,I4bf8e8c0, ... into integration
* changes:
plat/marvell/armada: cleanup MSS SRAM if used for copy
plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
plat/marvell/armada/common/mss: use MSS SRAM in secure mode
include/drivers/marvell/mochi: add detection of secure mode
plat/marvell: fix SPD handling in dram port
marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1
drivers/marvell/mochi: add support for cn913x in PCIe EP mode
drivers/marvell/mochi: add missing stream IDs configurations
plat/marvell/armada/a8k: support HW RNG by SMC
drivers/rambus: add TRNG-IP-76 driver
- plat/marvell/armada: cleanup MSS SRAM if used for copy
This patch cleans up the MSS SRAM if it was used for MSS image
copy (secure boot mode).
Change-Id: I23f600b512050f75e63d59541b9c21cef21ed313
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30099
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
- plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
Map IO WIN to CP1 and CP2 at all stages including the BLE.
Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly.
This patch allows access to CP1/CP2 internal registers at
BLE stage if CP1/CP2 are connected.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Icf9ffdf2e9e3cdc2a153429ffd914cc0005f9eca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/36939
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
- plat/marvell/armada/common/mss: use MSS SRAM in secure mode
The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA.
In secure boot mode the MSS DMA is unable to directly load
the MSS FW image from DRAM to IRAM.
This patch adds support for using the MSS SRAM as intermediate
storage. The MSS FW image is loaded by application CPU into the
MSS SRAM first, then transferred to MSS IRAM by MSS DMA.
Such change allows the CP MSS image load in secure mode.
Change-Id: Iee7a51d157743a0bdf8acb668ee3d599f760a712
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaszczyk@marvell.com>
- driver: brcm: add mdio driver
Change-Id: Id873670f68a4c584e3b7b586cab28565bb5a1c27
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
- Merge "libc: memset: Fix MISRA issues" into integration
- libc: memset: Fix MISRA issues
MISRA complained about "0"s not being followed by an "U" (please note
my protest about this!) and about values not being explicitly compared
to 0 (fair enough).
Also use explicit pointer types.
Fix those issues to make the CI happy.
Change-Id: I4d11e49c14f16223a71c78b0fc3e68ba9a1382d3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- Merge "plat:xilinx:zynqmp: Remove the custom crash implementation" into integration
- plat:xilinx:zynqmp: Remove the custom crash implementation
Removing the custom crash implementation and use
plat/common/aarch64/crash_console_helpers.S.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I045d42eb62bcaf7d1e18fbe9ab9fb9470e800215
- Merge "allwinner: Allow conditional compilation of SCPI and native PSCI ops" into integration
- Merge "lib: cpus: aarch32: sanity check pointers before use" into integration
- Merge "nand: stm32_fmc_nand: remove dead code" into integration
- lib: cpus: aarch32: sanity check pointers before use
This is the AARCH32 update of patch [1].
[1] 601e3ed209eb ("lib: cpus: sanity check pointers before use")
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I43dbe00a5802a7e1c6f877e22d1c66ec8275c6fa
- Merge changes Ie5c48303,I5d363c46 into integration
* changes:
tzc400: adjust filter flag if it is set to FILTER_BIT_ALL
tzc400: fix logical error in FILTER_BIT definitions
- Merge changes from topic "sunxi-split-psci" into integration
* changes:
allwinner: Split native and SCPI-based PSCI implementations
allwinner: psci: Improve system shutdown/reset sequence
allwinner: psci: Drop .pwr_domain_pwr_down_wfi callback
allwinner: Separate code to power off self and other CPUs
- Merge changes I8ea4ea58,I1f0b4aab,I2cccad40 into integration
* changes:
marvell: uart: a3720: Increase TX FIFO EMPTY timeout from 2ms to 3ms
marvell: uart: a3720: Update delay code to be compatible with 1200 MHz CPU
marvell: uart: a3720: Fix comments in console_a3700_core_init() function
- Merge "qti: spmi_arb: Fix NUM_APID and REG_APID_MAP() argument" into integration
- Merge "docs: stm32mp1: correct formatting issues" into integration
- Merge "Revert "spmd: ensure SIMD context is saved/restored on SPMC entry/exit"" into integration
- Merge "plat/arm/css: rename rd_n1e1_edge_scmi_plat_info array" into integration
- Revert "spmd: ensure SIMD context is saved/restored on SPMC entry/exit"
This reverts commit bedb13f509ac68adaf9baa9b5f24eede912e801d.
SIMD context is now saved in S-EL2 as opposed to EL3, see commit:
https://review.trustedfirmware.org/c/hafnium/hafnium/+/8321
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Ic81416464ffada1a6348d0abdcf3adc7c1879e61
- plat/arm/css: rename rd_n1e1_edge_scmi_plat_info array
Rename rd_n1e1_edge_scmi_plat_info array to plat_rd_scmi_info as the
same array is used to provide SCMI platform info across mulitple RD
platforms and is not resitricted to only RD-N1 and RD-E1 platforms.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I42ba33e0afa3003c731ce513c6a5754b602ec01f
- plat/arm: juno: Use TRNG entropy source for SMCCC TRNG interface
Now that we have a framework for the SMCCC TRNG interface, and the
existing Juno entropy code has been prepared, add the few remaining bits
to implement this interface for the Juno Trusted Entropy Source.
We retire the existing Juno specific RNG interface, and use the generic
one for the stack canary generation.
Change-Id: Ib6a6e5568cb8e0059d71740e2d18d6817b07127d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- docs: stm32mp1: correct formatting issues
Add blank lines before lists and code example.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I901646e0be74227af983079d0cbe05c6a217fab6
- marvell: uart: a3720: Increase TX FIFO EMPTY timeout from 2ms to 3ms
TX FIFO has space for 32 characters. With default UART baudrate 115200 it
takes more than 2ms to transmit all 32 characters, so wait at least 3ms
before flushing TX FIFO.
If WTMI firmware transmitted something via UART before TF-A was booted,
some characters may still wait in TX FIFO when TF-A is initializing UART
driver. So wait at least 3ms to ensure that HW has enough time to transmit
all characters waiting in TX FIFO.
This fixes an issue where sometimes characters transmitted on UART by our
custom WTMI image are lost.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8ea4ea58e4ba3e0c0d7f47e679171b9b94442f19
- marvell: uart: a3720: Update delay code to be compatible with 1200 MHz CPU
Console initialization function needs to wait at least minimal specified
time. The fastest Armada 3720 CPU is 1200 MHz so increase loop delay to
wait at least for 100 us on 1200 MHz variant too. The slowest Armada 3720
CPU is 600 MHz and in this case delay loop would take just 2 times more,
which is not a problem.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I1f0b4aabd0e08b7696feec631419f7f7c7ec17d2
- marvell: uart: a3720: Fix comments in console_a3700_core_init() function
The delay loop executes 3 instructions. These 3 instructions are executed
in 2 processor ticks and 30000 iterations on a 600 MHz CPU should yield
approximately 100 us. This means we are waiting 2 ms, not 20 ms, for TX
FIFO to be empty.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2cccad405bcc73cd6d1062adc0205c405c16c15f
- plat/arm: juno: Condition Juno entropy source with CRC instructions
The Juno Trusted Entropy Source has a bias, which makes the generated
raw numbers fail a FIPS 140-2 statistic test.
To improve the quality of the numbers, we can use the CPU's CRC
instructions, which do a decent job on conditioning the bits.
This adds a *very* simple version of arm_acle.h, which is typically
provided by the compiler, and contains the CRC instrinsics definitions
we need. We need the original version by using -nostdinc.
Change-Id: I83d3e6902d6a1164aacd5060ac13a38f0057bd1a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- Merge "spmd: ensure SIMD context is saved/restored on SPMC entry/exit" into integration
- Merge "nxp: added the makefile helper macros" into integration
- nxp: added the makefile helper macros
NXP specifc macro SET_NXP_MAKE_FLAG is added.
NXP has pool of multiple IPs. This macro helps:
- In soc.mk, this macro help the selected IP source files to be included
for that SoC.
-- The set of IPs required for one NXP SoC is different to the set of IPs
required by another NXP SoC.
- For the same SoC,
-- For one feature, the IP may be required in both BL2 and BL31.
-- Without the above feature, that IP may be required in one.
This macro help in selecting the inclusion of source and header files to:
--- BL2 only
--- BL31 only
--- COMM (used by BL2 and BL31)
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cdb13b89aa815fc5219cf8bfb9666d0a9f78765
- spmd: ensure SIMD context is saved/restored on SPMC entry/exit
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I8ed58ec5f97e05d91451020a2739464bb8e428b3
- Merge "plat/arm: juno: Refactor juno_getentropy()" into integration
- Merge "bl32: Enable TRNG service build" into integration
- Merge "plat/arm/rdn2: update TZC base address" into integration
- nand: stm32_fmc_nand: remove dead code
The FMC driver in TF-A only supports NAND Mode 0 timings.
The timings are then hard-coded as macros, leading to some parts of code
unreachable.
This issue was found by Coverity scan: CID 366361.
Change-Id: I864c51ce11b9ef74ad82b3301f56f46a2e0f70ca
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
- Merge changes from topic "mp/strto_libc" into integration
* changes:
libc: Import strtoull from FreeBSD project
libc: Import strtoll from FreeBSD project
libc: Import strtoul from FreeBSD project
libc: Import strtol from FreeBSD project
- Merge "morello: Modify morello_plat_info structure" into integration
- plat/arm: juno: Refactor juno_getentropy()
Currently we use the Juno's TRNG hardware entropy source to initialise
the stack canary. The current function allows to fill a buffer of any
size, but we will actually only ever request 16 bytes, as this is what
the hardware implements. Out of this, we only need at most 64 bits for
the canary.
In preparation for the introduction of the SMCCC TRNG interface, we
can simplify this Juno specific interface by making it compatible with
the generic one: We just deliver 64 bits of entropy on each call.
This reduces the complexity of the code. As the raw entropy register
readouts seem to be biased, it makes sense to do some conditioning
inside the juno_getentropy() function already.
Also initialise the TRNG hardware, if not already done.
Change-Id: I11b977ddc5417d52ac38709a9a7b61499eee481f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- bl32: Enable TRNG service build
The Trusted Random Number Generator service is using the standard SMC
service dispatcher, running in BL31. For that reason we list the files
implementing the service in bl31.mk.
However when building for a 32-bit TF-A runtime, sp_min.mk is the
Makefile snippet used, so we have to add the files into there as well.
This fixes 32-bit builds of platforms that provide the TRNG service.
Change-Id: I8be61522300d36477a9ee0a9ce159a140390b254
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- include/drivers/marvell/mochi: add detection of secure mode
Change-Id: I99afc312617df86ae68eb30302203a03877ca748
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/22541
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaszczyk@marvell.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
- plat/marvell: fix SPD handling in dram port
The DRAM port code issues a dummy write to SPD page-0 i2c address
in order to select this page for the forthcoming read transaction.
If the write buffer length supplied to i2c_write is not zero, this
call is translated to 2 bus transations:
- set the target offset
- write the data to the target
However no actual data should be transferred to SPD page-0 in order
to select it. Actually, the second transation never receives an ACK
from the target device, which caused the following error report:
ERROR: Status 30 in write transaction
This patch sets the buffer length in page-0 select writes to zero,
leading to bypass the data transfer to the target device.
Issuing the target offset command to SPD page-0 address effectively
selects this page for the read operation.
Change-Id: I4bf8e8c09da115ee875f934bc8fbc9349b995017
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/24387
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Moti Buskila <motib@marvell.com>
- marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1
Change CP110 XOR (DMA) to use WIN1 which is used for PCI-EP address
space only and using this window bypasses the need for translation
in the SMMU which has performance impact.
Change-Id: I98d99da59e904e6721cfa263ce44ad178a0fa956
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/20389
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
- drivers/marvell/mochi: add support for cn913x in PCIe EP mode
Change-Id: I4dc33d1eb59395605f64e5aad5cafa10c53265cc
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/20453
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
- drivers/marvell/mochi: add missing stream IDs configurations
- Add setup of DMA stream IDs in AP807/AP806 drivers
Change-Id: I23ffe86002db4753f812c63c31431a3d04056d07
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
- plat/marvell/armada/a8k: support HW RNG by SMC
Add initialization for TRNG-IP-76 driver and support SMC call
0xC200FF11 used for reading HW RNG value by secondary bootloader
software for KASLR support.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I1d644f67457b28d347523f8a7bfc4eacc45cba68
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/32688
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
- drivers/rambus: add TRNG-IP-76 driver
Add Rambus (InsideSecure) TRNG-IP-76 HW RNG driver.
This IP is part of Marvell Armada CP110/CP115 die integrated
to Armada 7k/8K/CN913x SoCs
Change-Id: I9c5f510ad6728c7ed168da43d85b19d5852cd873
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
- plat/arm/rdn2: update TZC base address
Update TZC base address to align with the recent changes in the platform
memory map.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I0d0ad528a2e236607c744979e1ddc5c6d426687a
- Merge "services: TRNG: Fix -O0 compilation" into integration
- services: TRNG: Fix -O0 compilation
The code to check for the presence of the TRNG service relies on
toolchain garbage collection, which is not enabled with -O0.
Add #ifdef guards around the call to the TRNG service handler to
cover builds without optimisation as well.
Change-Id: I08ece2005ea1c8fa96afa13904a851dec6b24216
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- Merge changes from topic "GIC-work" into integration
* changes:
plat/arm: fvp: Protect GICR frames for fused/unused cores
doc: Build option to protect GICR frame
plat/arm: fvp: Do not map GIC region in BL1 and BL2
- plat/arm: fvp: Protect GICR frames for fused/unused cores
Currently, BLs are mapping the GIC memory region as read-write
for all cores on boot-up.
This opens up the security hole where the active core can write
the GICR frame of fused/inactive core. To avoid this issue, disable
the GICR frame of all inactive cores as below:
1. After primary CPU boots up, map GICR region of all cores as
read-only.
2. After primary CPU boots up, map its GICR region as read-write
and initialize its redistributor interface.
3. After secondary CPU boots up, map its GICR region as read-write
and initialize its redistributor interface.
4. All unused/fused core's redistributor regions remain read-only and
write attempt to such protected regions results in an exception.
As mentioned above, this patch offers only the GICR memory-mapped
region protection considering there is no facility at the GIC IP
level to avoid writing the redistributor area.
These changes are currently done in BL31 of Arm FVP and guarded under
the flag 'FVP_GICR_REGION_PROTECTION'.
As of now, this patch is tested manually as below:
1. Disable the FVP cores (core 1, 2, 3) with core 0 as an active core.
2. Verify data abort triggered by manually updating the ‘GICR_CTLR’
register of core 1’s(fused) redistributor from core 0(active).
Change-Id: I86c99c7b41bae137b2011cf2ac17fad0a26e776d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
- doc: Build option to protect GICR frame
Added a build option 'FVP_GICR_REGION_PROTECTION' to make
redistributor frame of fused/unused cores as read only.
Change-Id: Ie85f86e2465b93321a92a888ce8712a3144e4ccb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
- plat/arm: fvp: Do not map GIC region in BL1 and BL2
GIC memory region is not getting used in BL1 and BL2.
Hence avoid its mapping in BL1 and BL2 that freed some
page table entries to map other memory regions in the
future.
Retains mapping of CCN interconnect region in BL1 and BL2
overlapped with the GIC memory region.
Change-Id: I880dd0690f94b140e59e4ff0c0d436961b9cb0a7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
- Merge "fdts: use scmi_dvfs clock index 1 for cores 4-7" into integration
- fdts: use scmi_dvfs clock index 1 for cores 4-7
This allows Matterhorn cores to operate at their optimal OPPs.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I2e1b784da10154a1f1f65dd0e3a39213e7683116
- plat/arm: Remove ARM_LINUX_KERNEL_AS_BL33 relying on RESET_TO_BL31
So far the ARM platform Makefile would require that RESET_TO_BL31 is set
when we ask for the ARM_LINUX_KERNEL_AS_BL33 feature.
There is no real technical reason for that, and the one place in the
code where this was needed has been fixed.
Remove the requirement of those two options to be always enabled
together.
This enables the direct kernel boot feature for the Foundation FVP
(as described in the documentation), which requires a BL1/FIP
combination to boot, so cannot use RESET_TO_BL31.
Change-Id: I6814797b6431b6614d684bab3c5830bfd9481851
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- plat/arm: Always allow ARM_LINUX_KERNEL_AS_BL33
At the moment we have the somewhat artifical limitation of
ARM_LINUX_KERNEL_AS_BL33 only being used together with RESET_TO_BL31.
However there does not seem to be a good technical reason for that,
it was probably just to differentate between two different boot flows.
Move the initial register setup for ARM_LINUX_KERNEL_AS_BL33 out of the
RESET_TO_BL31 #ifdef, so that we initialise the registers in any case.
This allows to use a preloaded kernel image when using BL1 and FIP.
Change-Id: I832df272d3829f077661f4ee6d3dd9a276a0118f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- tzc400: adjust filter flag if it is set to FILTER_BIT_ALL
TZC_400_REGION_ATTR_FILTER_BIT_ALL is a simple constant definition, so
it can't get the real filter number to construct the bit flag for all
existing filters. If the platform doesn't have 4 filters, passing
FILTER_BIT_ALL to tzc400_configure_region() will cause assertion or
misconfiguration. So adjust the bit flag against the real filter
number.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Ie5c48303485f3b5015772961ee7c34746121ee84
- tzc400: fix logical error in FILTER_BIT definitions
The filters parameter passed to tzc400_configure_region() is supposed
to be filter bit flag without bit shift, so the macros
TZC_400_REGION_ATTR_FILTER_BIT and TZC_400_REGION_ATTR_FILTER_BIT_ALL
should always construct the value without any shift.
It is not a functional issue for TZC_REGION_ATTR_F_EN_SHIFT is lucky
to be 0.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I5d363c462b8517256523f637e670eefa56722afd
- morello: Modify morello_plat_info structure
The structure has been modified to specify the memory
size in bytes instead of Gigabytes.
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I3384677d79af4f3cf55d3c353b6c20bb827b5ae7
- Merge "ddr: stm32mp1_ddr: correct SELFREF_TO_X32 mask" into integration
- Merge "rainier: remove cpu workaround for errata 1542419" into integration
- Merge "Add TRNG Firmware Interface service" into integration
- Add TRNG Firmware Interface service
This adds the TRNG Firmware Interface Service to the standard
service dispatcher. This includes a method for dispatching entropy
requests to platforms and includes an entropy pool implementation to
avoid dropping any entropy requested from the platform.
Change-Id: I71cadb3cb377a507652eca9e0d68714c973026e9
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- rainier: remove cpu workaround for errata 1542419
This patch removes the Neoverse N1 CPU errata workaround for
bug 1542419 as the bug is not present in Rainier R0P0 core.
Change-Id: Icaca299b13ef830b2ee5129576aae655a6288e69
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
- ddr: stm32mp1_ddr: correct SELFREF_TO_X32 mask
In DDR controller PWRTMG register, the mask for field SELFREF_TO_X32 is
wrong. This field is from bit 16 to 23.
Change-Id: Id336fb08c88f0a153df186dd819e41af72febb88
Signed-off-by: Yann Gautier <yann.gautier@st.com>
- plat/qemu: trigger reboot with secure pl061
Secure pl061 qemu driver allows to rize the GPIO pin
from the secure world to reboot and power down
virtual machine.
Do not define secure-gpio for sbsa-ref platform due to
reboot is done via sbsa-ec watchdog.
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Change-Id: I508d7c5cf4c75cb169b34b00682a76f6761d3869
- qti: spmi_arb: Fix NUM_APID and REG_APID_MAP() argument
The NUM_APID value was derived from kernel device tree sources, but I
made a conversion mistake: the amount of bytes in the APID map is the
total size of the "core" register range (0x1100) minus the offset of the
APID map in that range (0x900). This is of course 0x1100 - 0x900 = 0x800
and not 0x200, so the amount of 4-byte integers it can fit is not 0x80
but 0x200. Fix this and make the math more explicit so it can be more
easily factored out and adjusted if that becomes necessary for a future
SoC.
Also fix a dangerous typo in REG_APID_MAP() where the macro would
reference a random variable `i` rather than its argument (`apid`), and
we just got lucky that the only caller in the current code happened to
pass in a variable called `i` as that argument.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I049dd044fa5aeb65be0e7b12150afd6eb4bac0fa
- libc: Import strtoull from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.
Also made small changes to fit into TF-A project. Added the source
files to the libc makefile
[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution
Change-Id: I2e94a0b227ec39f6f4530dc50bb477999d27730f
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
- libc: Import strtoll from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.
Also made small changes to fit into TF-A project. Added the source
files to the libc makefile
[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution
Change-Id: I9cb581574d46de73c3d6917ebf78935fc5ac075a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
- libc: Import strtoul from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.
Also made small changes to fit into TF-A project. Added the source
files to the libc makefile
[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution
Change-Id: I8c3b92751d1ce226c966f7c81fedd83f0846865e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
- libc: Import strtol from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.
Also made small changes to fit into TF-A project. Added the source
files to the libc makefile
[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution
Change-Id: Ica95bf5da722913834fe90bf3fe743aa34e01e80
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
- Merge changes from topic "RD_INFRA_POWER_MODING" into integration
* changes:
plat/arm/board: enable AMU for RD-N2
plat/arm/board: enable AMU for RD-V1
plat/arm/sgi: allow all PSCI callbacks on RD-V1
- Merge "plat/arm:juno: fix parallel build issue for romlib config" into integration
- Merge "product/tc0: Enable Theodul DSU in TC platform" into integration
- drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()
ESPI register offset should also be shifted right by REG##R_SHIFT to
keep consistent.
It is not a functional issue, for GICD_OFFSET_64() is only used for
GICD_IROUTER<E>, and IROUTER_SHIFT is 0.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I76eee5c50e4300890e78e80bddde135ce88daa2d
- drivers/gicv3: add debug log for maximum INTID of SPI and eSPI
Add debug log for the maximum supported INTID of SPI and eSPI on the
current GIC implementation.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Ie45ab1d85b39658c4ca4bc54ee433ac44e41d03f
- drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET()
The GICv3 architecture allows GICD_TYPER.ITLinesNumber to be 31, so
the maximum possible value for num_ints is 1024. The value must be
limited to (MAX_SPI_ID + 1), or GICD_OFFSET() will consider it as ESPI
INTID and return wrong register address.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Iddcb83d3e5d241b39f4176c19c2bceaa2c3dd653
- drivers/gicv3: fix logical issue for num_eints
In function gicv3_spis_config_defaults(), the variable num_ints is set
to (maximum SPI INTID + 1), while num_eints is set to (maximum ESPI
INTID). It introduces not only inconsistency to the code, but also
logical bug in the "for" loops, for the INTID of num_eints is also
valid and the check should be inclusive.
Fix this by setting num_eints to (maximum ESPI INTID + 1) as well.
Fix similar issues in gicv3_distif_save() and
gicv3_distif_init_restore().
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I4425777d17e84e85f38853603340bd348640154f
- drivers/gicv3: fix potential GICD context override with ESPI enabled
RESTORE/SAVE_GICD_EREGS uses (int_id - (MIN_ESPI_ID - MIN_SPI_ID)) to
get the context array index for ESPI, which will override the space of
standard SPI starting from (MIN_SPI_ID + MIN_SPI_ID).
However, using TOTAL_SPI_INTR_NUM to replace the above MIN_SPI_ID
cannot totally fix the issue, for TOTAL_SPI_INTR_NUM is not well
aligned and the array index will be rounded down by the shifting
operation if being shifted more than 2 bits. It will cause buffer
override again when the existing maximum SPI reaches 1019.
So round up TOTAL_SPI_INTR_NUM with (1 << REG##R_SHIFT) for GICD
context arrays.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I5be2837c42f381a62f8d46a4ecd778009b1fe059
- drivers/gicv3: use mpidr to probe GICR for current CPU
In function gicv3_rdistif_probe(), line #1322 implies
gicv3_driver_data->mpidr_to_core_pos() may be null, but the original
code uses this interface to get current CPU index unconditionally.
It is better to use MPIDR to probe GICR which does not depend on
gicv3_driver_data->mpidr_to_core_pos().
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I64add055385040fe0a56b977e2299608e2309a6e
- product/tc0: Enable Theodul DSU in TC platform
Increase the core count and add respective entries in DTS.
Add Klein assembly file to cpu sources for core initialization.
Add SCMI entries for cores.
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
Change-Id: I14dc1d87df6dcc8d560ade833ce1f92507054747
- plat/arm:juno: fix parallel build issue for romlib config
When building TF-A with USE_ROMLIB=1 and -j make options, the build fails with the following error:
make[1]: *** No rule to make target '/build/juno/debug/romlib/romlib.bin', needed by 'bl1_romlib.bin'.
This patch fixes that issue.
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
Change-Id: I0cca416f3f50f400759164e0735c2d6b520ebf84
- Merge "Fix exception handlers in BL31: Use DSB to synchronize pending EA" into integration
- Merge changes from topic "marvell-armada-docs" into integration
* changes:
docs: marvell: Replace ESPRESSObin-Ultra TF-A build example by full example how to build production release of Marvell firmware image
docs: marvell: Fix description of flash-image.bin image
docs: marvell: Add information into CLOCKSPRESET option how to identify CPU frequency
docs: marvell: Reformat DDR_TOPOLOGY option and mention EspressoBin-Ultra board
docs: marvell: Move Supported Marvell platforms to PLAT build option
- Merge changes from topic "marvell-a3k-separate-flash-and-uart" into integration
* changes:
plat: marvell: armada: a3k: Do not use 'echo -e' in Makefile
docs: marvell: Update info about BOOTDEV=SATA
- Merge changes from topic "marvell-a3k-separate-flash-and-uart" into integration
* changes:
docs: marvell: Update info about WTMI_IMG option
plat: marvell: armada: a3k: Remove unused variable WTMI_SYSINIT_IMG from Makefile
plat: marvell: armada: Show informative build messages and blank lines
plat: marvell: armada: Move definition of mrvl_flash target to common marvell_common.mk file
plat: marvell: armada: a3k: Use $(Q) instead of @
plat: marvell: armada: a3k: Add a new target mrvl_uart which builds UART image
plat: marvell: armada: a3k: Build UART image files directly in $(BUILD_UART) subdirectory
plat: marvell: armada: a3k: Build intermediate files in $(BUILD_PLAT) directory
plat: marvell: armada: a3k: Correctly set DDR_TOPOLOGY and CLOCKSPRESET for WTMI
plat: marvell: armada: a3k: Allow use of the system Crypto++ library
docs: marvell: Update info about WTP and MV_DDR_PATH parameters
plat: marvell: armada: a3k: Add checks that WTP, MV_DDR_PATH and CRYPTOPP_PATH are correctly defined
docs: marvell: Update mv-ddr-marvell and A3700-utils-marvell branches
- docs: marvell: Replace ESPRESSObin-Ultra TF-A build example by full example how to build production release of Marvell firmware image
ESPRESSObin-Ultra TF-A build example was now just a copy+paste of previous
mentioned example. It produced debug binary with custom log level, which
was not described. So rather replace this duplicate build example by a full
example with all steps how to build production release of Marvell firmware
image for EspressoBin with 1GHz CPU and 1GB DDR4 RAM.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ief1b8bc96a3035ebd8421bd68dca5eb5c8d8fd52
- docs: marvell: Fix description of flash-image.bin image
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I192acab2a7f42cd80069faeac2d7823a05558dc6
- docs: marvell: Add information into CLOCKSPRESET option how to identify CPU frequency
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5310c30051703bbf9f377762a00eb6a8188c6fa1
- docs: marvell: Reformat DDR_TOPOLOGY option and mention EspressoBin-Ultra board
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I96c2d9d5bc6c69a1a66a29bf586a23375d63ab5a
- docs: marvell: Move Supported Marvell platforms to PLAT build option
Reformat list of boards, remove unsupported OcteonTX2 and mention
supported Turris MOX board.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I22cea7f77fd078554c7f0ed4108781626209e563
- Merge changes from topic "sunxi-split-psci" into integration
* changes:
allwinner: Leave CPU power alone during BL31 setup
allwinner: psci: Invert check in .validate_ns_entrypoint
allwinner: psci: Drop MPIDR check from .pwr_domain_on
allwinner: psci: Drop .get_node_hw_state callback
- plat/arm/board: enable AMU for RD-N2
AMU counters are used for monitoring the CPU performance. RD-N2 platform
has architected AMU available for each core. Enable the use of AMU by
non-secure OS for supporting the use of counters for processor
performance control (ACPI CPPC).
Change-Id: I5cc749cf63c18fc5c7563dd754c2f42990a97e23
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
- plat/arm/board: enable AMU for RD-V1
AMU counters are used for monitoring the CPU performance. RD-V1 platform
has architected AMU available for each core. Enable the use of AMU by
non-secure OS for supporting the use of counters for processor
performance control (ACPI CPPC).
Change-Id: I4003d21407953f65b3ce99eaa8f496d6052546e0
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
- plat/arm/sgi: allow all PSCI callbacks on RD-V1
Some of the PSCI platform callbacks were restricted on RD-V1 platform
because the idle was not functional. Now that it is functional, remove
all the restrictions on the use PSCI platform callbacks.
Change-Id: I4cb97cb54de7ee166c30f28df8fea653b6b425c7
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
- plat: marvell: armada: a3k: Do not use 'echo -e' in Makefile
It does not have to be supported by the current shell used in Makefile.
Replace it by a simple echo with implicit newline.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I97fe44986ac36d3079d5258c67f0c9184537e7f0
- docs: marvell: Update info about BOOTDEV=SATA
Information is taken from the post https://lists.denx.de/pipermail/u-boot/2017-July/299351.html
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5f608e135ec56685a3e2b986a52670540d48a4bf
- docs: marvell: Update info about WTMI_IMG option
Default WTMI_IMG value was documented incorrectly. Also WTMI_IMG name may
be misleading as this option does not specify full WTMI image, just a main
loop (e.g. fuse.bin or custom RTOS image) without hardware initialization
code (DDR, CPU and clocks).
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I3de4a27ce2165b962fa628c992fd8f80151efd7c
- plat: marvell: armada: a3k: Remove unused variable WTMI_SYSINIT_IMG from Makefile
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I322c8aa65437abb61385f58b700a06b3e2e22e4f
- plat: marvell: armada: Show informative build messages and blank lines
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ibc15db07c581eca29c1b1fbfb145cee50dc42605
- plat: marvell: armada: Move definition of mrvl_flash target to common marvell_common.mk file
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: If545b3812787cc97b95dbd61ed51c37d30c5d412
- plat: marvell: armada: a3k: Use $(Q) instead of @
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I09fd734510ec7019505263ff0ea381fab36944fa
- plat: marvell: armada: a3k: Add a new target mrvl_uart which builds UART image
This change separates building of flash and UART images, so it is possible
to build only one of these images. Also this change allows make to build
them in parallel.
Target mrvl_flash now builds only flash image and mrvl_uart only UART
image. This change reflects it also in the documentation.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ie9ce4538d52188dd26d99dfeeb5ad171a5b818f3
- plat: marvell: armada: a3k: Build UART image files directly in $(BUILD_UART) subdirectory
This removes need to move files and also allows to build uart and flash
images in parallel.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I13bea547d7849615e1c1e11d333c8c99e568d3f6
- plat: marvell: armada: a3k: Build intermediate files in $(BUILD_PLAT) directory
Currently a3700_common.mk makefile builds intermediate files in TF-A top
level directory and also outside of the TF-A tree. This change fixes this
issue and builds all intermediate files in $(BUILD_PLAT) directory.
Part of this change is also removal of 'rm' and 'mv' commands as there is
no need to remove or move intermediate files from outside of the TF-A build
tree.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I72e3a3024bd3fdba1b991a220184d750029491e9
- plat: marvell: armada: a3k: Correctly set DDR_TOPOLOGY and CLOCKSPRESET for WTMI
When building WTMI image we need to correctly set DDR_TOPOLOGY and
CLOCKSPRESET variables which WTMI build system expect. Otherwise it use
default values.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ib83002194c8a6c64a2014899ac049bd319e1652f
- plat: marvell: armada: a3k: Allow use of the system Crypto++ library
This change introduces two new A3720 parameters, CRYPTOPP_LIBDIR and
CRYPTOPP_INCDIR, which can be used to specify directory paths to
pre-compiled Crypto++ library and header files.
When both new parameters are specified then the source code of Crypto++ via
CRYPTOPP_PATH parameter is not needed. And therefore it allows TF-A build
process to use system Crypto++ library.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6d440f86153373b11b8d098bb68eb7325e86b20b
- Fix exception handlers in BL31: Use DSB to synchronize pending EA
For SoCs which do not implement RAS, use DSB as a barrier to
synchronize pending external aborts at the entry and exit of
exception handlers. This is needed to isolate the SErrors to
appropriate context.
However, this introduces an unintended side effect as discussed
in the https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/3440
A summary of the side effect and a quick workaround is provided as
part of this patch and summarized here:
The explicit DSB at the entry of various exception vectors in BL31
for handling exceptions from lower ELs can inadvertently trigger an
SError exception in EL3 due to pending asyncrhonouus aborts in lower
ELs. This will end up being handled by serror_sp_elx in EL3 which will
ultimately panic and die.
The way to workaround is to update a flag to indicate if the exception
truly came from EL3. This flag is allocated in the cpu_context
structure. This is not a bullet proof solution to the problem at hand
because we assume the instructions following "isb" that help to update
the flag (lines 100-102 & 139-141) execute without causing further
exceptions.
Change-Id: I4d345b07d746a727459435ddd6abb37fda24a9bf
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
- Merge "tools: cert_create: Create only requested certificates" into integration
- Merge "fdts: Fix stdout-path in various platforms" into integration
- docs: marvell: Update info about WTP and MV_DDR_PATH parameters
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Id5e36b7ba3a840cb3598c580e806b52d8e8dd70f
- plat: marvell: armada: a3k: Add checks that WTP, MV_DDR_PATH and CRYPTOPP_PATH are correctly defined
These variables must contain a path to a valid directory (not a file) which
really exists. Also WTP and MV_DDR_PATH must point to either a valid Marvell
release tarball or git repository.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I1ad80c41092cf3ea6a625426df62b7d9d6f37815
- Merge "cert-tool: avoid duplicates in extension stack" into integration
- fdts: Fix stdout-path in various platforms
The value of stdout-path is a string and as a result, we can't use a
label as a reference to the serial0 node. This change fixes the
stdout-path property for N1SDP, Morello and TC0 by pointing to the
right alias.
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Change-Id: I3d403389a424569be56327fab4140fec06f96d37
- Merge changes from topic "scmi-msg" into integration
* changes:
doc: maintainers: add scmi server
drivers: move scmi-msg out of st
- cert-tool: avoid duplicates in extension stack
This bug manifests itself as a segfault triggered by a double-free.
I noticed that right before the double-free, the sk list contained 2
elements with the same address.
(gdb) p sk_X509_EXTENSION_value(sk, 1)
$34 = (X509_EXTENSION *) 0x431ad0
(gdb) p sk_X509_EXTENSION_value(sk, 0)
$35 = (X509_EXTENSION *) 0x431ad0
(gdb) p sk_X509_EXTENSION_num(sk)
$36 = 2
This caused confusion; this should never happen.
I figured that this was caused by a ext_new_xxxx function freeing
something before it is added to the list, so I put a breakpoint on
each of them to step through. I was suprised to find that none of my
breakpoints triggered for the second element of the iteration through
the outer loop just before the double-free.
Looking through the code, I noticed that it's possible to avoid doing
a ext_new_xxxx, when either:
* ext->type == NVCOUNTER and ext->arg == NULL
* ext->type == HASH and ext->arg == NULL and ext->optional == false
So I put a breakpoint on both.
It turns out that it was the HASH version, but I added a fix for both.
The fix for the Hash case is simple, as it was a mistake. The fix for
the NVCOUNTER case, however, is a bit more subtle. The NVCOUNTER may
be optional, and when it's optional we can skip it. The other case,
when the NVCOUNTER is required (not optinal), the `check_cmd_params`
function has already verified that the `ext->arg` must be non-NULL.
We assert that before processing it to covert any possible segfaults
into more descriptive errors.
This should no longer cause double-frees by adding the same ext twice.
Change-Id: Idae2a24ecd964b0a3929e6193c7f85ec769f6470
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
- tools: cert_create: Create only requested certificates
The certification tool creates all the certificates mentioned
statically in the code rather than taking explicit certificate
requests from the command line parameters.
Code is optimized to avoid unnecessary attempts to create
non-requested certificates.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I78feac25bc701bf8f08c6aa5a2e1590bec92d0f2
- Merge "Fix documentation typos and misspellings" into integration
- Merge changes from topic "tp-feat-rng" into integration
* changes:
plat/qemu: Use RNDR in stack protector
Makefile: Add FEAT_RNG support define
Define registers for FEAT_RNG support
- docs: marvell: Update mv-ddr-marvell and A3700-utils-marvell branches
Marvell finally started providing the latest version of mv-ddr-marvell and
A3700-utils-marvell code in master branch of their git repositories.
Reflect this in build instructions.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I08d1189dac60eb2a28335c68f611c1da634106f6
- Merge changes I635cf82e,Iee3b4e0d into integration
* changes:
Makefile: Fix ${FIP_NAME} to be rebuilt only when needed
Makefile: Do not mark file targets as .PHONY target
- Merge "plat/arm: css: Turn ON/OFF redistributor in sync with GIC CPU interface ON/OFF" into integration
- doc: maintainers: add scmi server
Add maintainer entry for scmi server
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I673d7395a8cea3b553832e330c8a8ce37f8c2a5c
- allwinner: Allow conditional compilation of SCPI and native PSCI ops
Now that we have split the native and the SCPI version of the PSCI ops,
we can introduce build options to compile in either or both of them.
If one version is not compiled in, some stub functions make sure the
common code still compiles and makes the right decisions.
By default both version are enabled (as before), but one of them can be
disabled on the make command line, or via a platform specific Makefile.
Change-Id: I0c019d8700c0208365eacf57809fb8bc608eb9c0
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
- allwinner: Split native and SCPI-based PSCI implementations
In order to keep SCP firmware as optional, the original, limited native
PSCI implementation was kept around as a fallback. This turned out to be
a good decision, as some newer SoCs omit the ARISC, and thus cannot run
SCP firmware.
However, keeping the two implementations in one file makes things
unnecessarily messy. First, it is difficult to compile out the
SCPI-based implementation where it is not applicable. Second the check
is done in each callback, while scpi_available is only updated at boot.
This makes the individual callbacks unnecessarily complicated.
It is cleaner to provide two entirely separate implementations in two
separate files. The native implementation does not support any kind of
CPU suspend, so its callbacks are greatly simplified. One function,
sunxi_validate_ns_entrypoint, is shared between the two implementations.
Finally, the logic for choosing between implementations is kept in a
third file, to provide for platforms where only one implementation is
applicable and the other is compiled out.
Change-Id: I4914f07d8e693dbce218e0e2394bef15c42945f8
Signed-off-by: Samuel Holland <samuel@sholland.org>
- allwinner: psci: Improve system shutdown/reset sequence
- When the SCPI shutdown/reset command returns success, the SCP is
still waiting for the CPU to enter WFI. Do that.
- Peform board-level poweroff before CPU poweroff. If there is a PMIC
available, it will turn everything off including the CPUs, so doing
CPU poweroff first is a waste of cycles.
- During poweroff, attempt to turn off the local CPU using the ARISC.
This should use slightly less power than just an infinite WFI.
- Drop the WFI in the reset failure path. The panic will hang anyway.
Change-Id: I897efecb3fe4e77a56041b97dd273156ec51ef8e
Signed-off-by: Samuel Holland <samuel@sholland.org>
- allwinner: psci: Drop .pwr_domain_pwr_down_wfi callback
When operating on the local cpu, sunxi_cpu_power_off_self() only "arms"
the ARISC to perform the power-off process; the SCP waits for the CPU to
enter WFI before acutally powering it off. Since this matches the
expected split between .pwr_domain_off and .pwr_domain_pwr_down_wfi, we
can move the sunxi_cpu_power_off_self() call to sunxi_pwr_domain_off().
Since that change makes sunxi_pwr_down_wfi() equivalent to the default
implementation, the callback is no longer needed.
Change-Id: I7d65f66c550d1c69fa5e9945affd7a25b3d3ef42
Signed-off-by: Samuel Holland <samuel@sholland.org>
- allwinner: Separate code to power off self and other CPUs
Currently, sunxi_cpu_off() has two separate code paths: one for the
local CPU, and one for other CPUs. Let's split them in to two functions.
This actually simplifies things, because all callers either operate on
the local CPU only (sunxi_pwr_down_wfi()) or other CPUs only
(sunxi_cpu_power_off_others()). This avoids needing a second MPIDR read
to choose the appropriate code path.
Change-Id: I55de85025235cc95466bfa106831fc4c2368f527
Signed-off-by: Samuel Holland <samuel@sholland.org>
- allwinner: Leave CPU power alone during BL31 setup
Disabling secondary CPUs during boot is unnecessary because the other
CPUs are already in reset, and it saves an entirely insignificant amount
of power. Let's remove this bit of code that was added mostly "because
we can", and along with it remove an unconditional dependency on the CPU
ops functions.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ia77a1b722da6ba989c3992b656a6cde3f2238fd7
- allwinner: psci: Invert check in .validate_ns_entrypoint
Checking the exceptional case and letting the success case fall through
is not only more idiomatic, but it also allows adding more exceptional
cases in the future, such as a check for overlapping secure DRAM.
Change-Id: I720441a6a8853fd7f211ebe851f14d921a6db03d
Signed-off-by: Samuel Holland <samuel@sholland.org>
- allwinner: psci: Drop MPIDR check from .pwr_domain_on
This duplicated the logic in psci_validate_mpidr() which was already
called from psci_cpu_on().
Change-Id: I96ee92f1ce3e9cc2985b4e229ba86ebd27b79915
Signed-off-by: Samuel Holland <samuel@sholland.org>
- allwinner: psci: Drop .get_node_hw_state callback
This optional PSCI function was only implemented when SCPI was
available. However, the underlying SCPI function is not able to fulfill
the necessary contract. First, the SCPI protocol has no way to represent
HW_STANDBY at the CPU power level. Second, the SCPI implementation
maintains its own logical view of power states, and its implementation
of SCPI_CMD_GET_CSS_POWER_STATE does not actually query the hardware.
Thus it cannot provide "the physical view of power state", as required
for this function by the PSCI specification.
Since the function is optional, drop it.
Change-Id: I5f3a0810ac19ddeb3c0c5d35aeb09f09a0b80c1d
Signed-off-by: Samuel Holland <samuel@sholland.org>
- Merge "docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions" into integration
- Merge "stm32mp1: correct plat_crash_console_flush()" into integration
- Merge "DebugFS: Check channel index before calling clone function" into integration
- stm32mp1: correct plat_crash_console_flush()
The base address of UART peripheral should be given in R0, not in R1.
Otherwise the console_stm32_core_flush issues an assert message.
This issue was highlighted with recent changes in console flush functions.
Change-Id: Iead01986fdbbf30ad2fd9fa515a1d2b611b4e591
Signed-off-by: Yann Gautier <yann.gautier@st.com>
- Merge changes I2add6b4b,I9b296372,I7af2f1d1 into integration
* changes:
libc/snprintf: use macro to reduce duplicated code
libc/snprintf: add support to print "%" character
libc/printf: add support to print "%" character
- DebugFS: Check channel index before calling clone function
To avoid a potential out-of-bounds access, check whether
a device exists on a channel before calling the corresponding
clone function.
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
Change-Id: Ia0dd66b331d3fa8a33109a02369e1bc9ae0fdd5b
- Fix documentation typos and misspellings
Fix some typos and misspellings in TF-A documentation.
Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: Id72553ce7b2f0bed9821604fbc8df4d4949909fa
- Merge changes I44ef50da,I9802e9a3 into integration
* changes:
plat/arm/css/sgi: Fix assert expression issue
plat/arm/css/sgi: Fix bl32 receive event - 0xC4000061 issue
- Merge "plat: xilinx: versal: Remove code duplication" into integration
- plat/arm/css/sgi: Fix assert expression issue
Violation of MISRA-C Rule 14.4
Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: I44ef50dadb54fb056a91f3de962b6e63ba6d7ac4
- plat/arm/css/sgi: Fix bl32 receive event - 0xC4000061 issue
The issue is that, when interrupt is triggered and RAS handler
is entered, after interrupt handler finishes, TF-A will re-enter
bl32 and then crash.
sdei_dispatch_event() may return failing result in some cases,
for example kernel may not have registered a handler or RAS event
may happen early during boot. We restore the NS context when
sdei_dispatch_event() returns failing result.
error log :
Received delegated event
X0 : 0xC4000061
X1 : 0x0
X2 : 0x0
X3 : 0x0
Received event - 0xC4000061 on cpu 0
UnRecognized Event - 0xC4000061
Failed delegated event 0xC4000061, Status Invalid Parameter
Unhandled Exception in EL3.
x30 = 0x000000000401f700
x0 = 0xfffffffffffffffe
x1 = 0xfffffffffffffffe
x2 = 0x00000000600003c0
Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: I9802e9a32eee0ac3b5a8bcc0362d0b0e3b71dc9f
- Merge changes Ic9bacaf3,I99a18dbb,I34803060,I3ed55aa4,Ic8eed072, ... into integration
* changes:
doc: renesas: Update RZ/G2 code owner list
plat: renesas: rzg: DT memory node enhancements
renesas: rzg: emmc: Enable RZ/G2M support
plat: renesas: rzg: Add HopeRun HiHope RZ/G2M board support
drivers: renesas: rzg: Add HiHope RZ/G2M board support
tools: renesas: Add tool support for RZ/G2 platforms
- Merge changes I19e4e7f5,I226b6e33 into integration
* changes:
marvell: uart: a3720: Fix macro name for 6th bit of Status Register
marvell: uart: a3720: Implement console_a3700_core_getc
- Merge changes from topic "qemu-sbsa-topology-psci" into integration
* changes:
qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller
qemu/qemu_sbsa: topology is different from qemu so add handling
qemu/common : change DEVICE2 definition for MMU
qemu/aarch64/plat_helpers.S : calculate the position shift
- plat/arm: css: Turn ON/OFF redistributor in sync with GIC CPU interface ON/OFF
Turn ON/OFF GIC redistributor in sync with GIC CPU interface ON/OFF.
Issue :
The Linux prompt hangs when all the cores in a cluster are turned OFF
and we try to turn ON a core in that cluster. Previously when TF-A turns
ON a core, TF-A first turns ON the redistributor followed by the core.
This did not match the flow when turning OFF a core, as TF-A did not
turn OFF redistributor when the corresponding core[s] are disabled.
This hang is resolved by disabling redistributor as cores are disabled,
keeping them in sync.
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
Change-Id: Ifd04fdcfd47b45e00f874f15b098471883d023f0
- plat: xilinx: versal: Remove code duplication
Some switch cases uses same operation. So, club switch cases
which uses same operation and remove duplicate code.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I260b474c0ff3f2ca102c32d4af2e4abba2b8f57c
- libc/snprintf: use macro to reduce duplicated code
Add macro CHECK_AND_PUT_CHAR to check buffer capacity, save one
character to buffer, and then increase character counter by one in one
single statement, so that 4 similar code pieces can be cleaned.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I2add6b4bd6c24ea3c0d2499a44924e3e8db0f4d1
- libc/snprintf: add support to print "%" character
Enable snprintf()/vsnprintf() in TF-A to print "%" character as C
standard, which may be used in platform porting to print percentage
information.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I9b296372a1002046eabac1df5e8eb99a27efd4a8
- libc/printf: add support to print "%" character
Enable printf() in TF-A to print "%" character as C standard, which
may be used in platform porting to print percentage information.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I7af2f1d153548e426f423fce15dc48b0da56c622
- drivers: move scmi-msg out of st
Make the scmi-msg driver reused by others.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I5bc35fd4dab70f45c09b8aab65af4209cf23b124
- qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller
This allows PSCI in TF-A to signal platform power states to QEMU
via a controller in secure space.
This required a sbsa-ref specific version of PSCI functions for the
platform. Also adjusted the MMU range to also include the new EC.
Add a new MMU region for the embedded controller and increase the
size of xlat tables by one for the new region.
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Iece8a88947f11e82ab8988e460a8a66ad175a5ee
- qemu/qemu_sbsa: topology is different from qemu so add handling
sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512
cores in upto 64 clusters. Implement a qemu_sbsa specific topology file
and increase the BL31_SIZE to accommodate the bigger table sizes. Change
platform_def.h for new topology. Correct PLATFORM_CPU_PER_CLUSTER_SHIFT so
plat_helpers.S calculates correct result.
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Idc5d70394c0956b759ad2c86f9fda8f293f2cfa7
- qemu/common : change DEVICE2 definition for MMU
DEVICE2 is not currently used on qemu platform but is needed for
a future patch for qemu_sbsa platform. Change its definition to
RW and add it to all levels of arm-tf similar to DEVICE1 definition.
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: I03495471bfd423b61ad44ec4953fb25f76aa54bf
- qemu/aarch64/plat_helpers.S : calculate the position shift
Rather than re-create this file in multiple qemu variants instead
caclulate the shift needed to convert MPIDR to position.
Add a new PLATFORM_CPU_PER_CLUSTER_SHIFT define in platform_def.h
for both qemu and qemu_sbsa to enable this calculation.
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: I0e3a86354aa716d95150a3a34b15287cd70c8fd2
- Merge "fdts: stm32mp1: add support for Linux Automation MC-1 board" into integration
- plat/qemu: Use RNDR in stack protector
When getting a stack protector canary value, check
if cpu supports FEAT_RNG and use that. Fallback to
old method of using a (hardcoded value ^ timer).
Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
Change-Id: I8181acf8e31661d4cc82bc3a4078f8751909e725
- fdts: stm32mp1: add support for Linux Automation MC-1 board
The Linux Automation MC-1 is a SBC built around the Octavo Systems
OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and
PMIC. The board has eMMC and a SD slot for storage.
The SDRAM calibration values are taken as is from the DKx boards, which
seem to be suitable for operation at German room temperature.
This is deemed ok for now, but for use in the field, the SiP will likely
need to have its timings determined in a climate chamber.
Change-Id: I5f43a61930151ae9d1df2ea7d0f6f9697c813ce0
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
- marvell: uart: a3720: Fix macro name for 6th bit of Status Register
This patch does not change code, it only updates comments and macro name
for 6th bit of Status Register. So TF-A binary stay same.
6th bit of the Status Register is named TX EMPTY and is set to 1 when both
Transmitter Holding Register (THR) or Transmitter Shift Register (TSR) are
empty. It is when all characters were already transmitted.
There is also TX FIFO EMPTY bit in the Status Register which is set to 1
only when THR is empty.
In both console_a3700_core_init() and console_a3700_core_flush() functions
we should wait until both THR and TSR are empty therefore we should check
6th bit of the Status Register.
So current code is correct, just had misleading macro names and comments.
This change fixes this "documentation" issue, fixes macro name for 6th bit
of the Status Register and also updates comments.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I19e4e7f53a90bcfb318e6dd1b1249b6cbf81c4d3
- marvell: uart: a3720: Implement console_a3700_core_getc
Implementation is simple, just check if there is a pending character in
RX FIFO via RXRDY bit of Status Register and if yes, read it from
UART_RX_REG register.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I226b6e336f44f5d0ca8dcb68e49a68e8f2f49708
- Merge changes I3c0a402f,I9ce5b9df,I08719015,If541278f,I99f1a697 into integration
* changes:
doc: renesas: Update code owner for Renesas platforms
doc: renesas: Document platforms based on RZ/G2 SoC's
renesas: rzg: Add PFC support for RZ/G2M
renesas: rzg: Add QoS support for RZ/G2M
renesas: rzg: Add support for DRAM initialization
- Makefile: Add FEAT_RNG support define
Define ENABLE_FEAT_RNG that describes whether the
armv8.5 FEAT_RNG is supported in this build. This
allows conditional inclusion of code targetting
RNDR and RNDRRS registers.
Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
Change-Id: Idd632f8b9bc20ea3d8793f55ead88fa12cb08821
- Define registers for FEAT_RNG support
Add ISAR0 feature register read helper, location
of FEAT_RNG bits, feature support helper and the
rndr/rndrrs register read helpers.
Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
Change-Id: I2a785a36f62a917548e55892ce92fa8b72fcb99d
- Merge changes from topic "certtool-memleak" into integration
* changes:
Use preallocated parts of the HASH struct
Free arguments copied with strdup
Free keys after use
Free X509_EXTENSIONs
- Merge "tools: don't clean when building" into integration
- Merge changes I36e4d672,I47610cee into integration
* changes:
Workaround for Cortex N1 erratum 1946160
Workaround for Cortex A78 erratum 1951500
- Merge changes Ie8922309,I1001bea1,I66265e5e,I2cc0ceda,I04805d72, ... into integration
* changes:
plat: renesas: common: Include ulcb_cpld.h conditionally
plat: renesas: Move to common
plat: renesas: aarch64: Move to common
drivers: renesas: Move ddr/qos/qos header files
drivers: renesas: rpc: Move to common
drivers: renesas: avs: Move to common
drivers: renesas: auth: Move to common
drivers: renesas: dma: Move to common
drivers: renesas: watchdog: Move to common
drivers: renesas: rom: Move to common
drivers: renesas: delay: Move to common
drivers: renesas: console: Move to common
drivers: renesas: pwrc: Move to common
drivers: renesas: io: Move to common
drivers: renesas: eMMC: Move to common
- Merge changes Id2b1822c,Ia9a563a1,I11f65d49,If9318a51,I46801b56, ... into integration
* changes:
drivers: renesas: Move plat common sources
plat: renesas: Move headers and assembly files to common folder
plat: renesas: rcar: include: Code cleanup
plat: renesas:rcar: Fix checkpatch warnings
plat: renesas: rcar: Fix checkpatch warnings
plat: renesas:rcar: Code cleanup
plat: renesas: rcar: Fix coding style
- Merge "docs: update fvp version to be used for rdv1 platform" into integration
- docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions
The supported MARVELL_PLATFORM list is updated to include the recently added
a80x0_puzzle platform (IEI Puzzle-M801).
Additionally building instructions are added for the GST ESPRESSObin-Ultra
board (1 GB, DDR4 RAM variant), which has been tested successfully and booted
TF-A on the board.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Change-Id: Ie5724df27c1ee2e8f6a52664520579e872471e93
- lib/extensions/ras: fix bug of binary search
In ras_interrupt_handler(), binary search end was set to the size of
the ras_interrupt_mappings array, which would cause out of bound
access when the input intr_raw is larger than all the elements in
ras_interrupt_mappings.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Id2cff73177134b09d4d8beb596c3429b98ec5066
- Workaround for Cortex N1 erratum 1946160
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST
before acquire atomic instructions without release semantics. This
issue is present starting from r0p0 but this workaround applies to
revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no
workaround.
SDEN can be found here:
https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
- Workaround for Cortex A78 erratum 1951500
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This workaround
works on revisions r1p0 and r1p1, in r0p0 there is no workaround.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
- doc: renesas: Update RZ/G2 code owner list
Add Lad Prabhakar as the code owner for the newly added
RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ic9bacaf31d653e1e553fa70043053805f56a2b84
- plat: renesas: rzg: DT memory node enhancements
Add DT node support for channel 0 where physical memory is split
between 32bit space and 64bit space.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I99a18dbb14cdb54100a836c16445242e430794e3
- renesas: rzg: emmc: Enable RZ/G2M support
Enable eMMC driver support for RZ/G2M SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I34803060c5b592ac24720b11d4a8cd3f9f40caee
- plat: renesas: rzg: Add HopeRun HiHope RZ/G2M board support
The HiHope RZ/G2M board from HopeRun consists of main board
(HopeRun HiHope RZ/G2M main board) and sub board(HopeRun
HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits
below the HiHope RZ/G2M main board.
This patch adds the required board support to boot HopeRun HiHope
RZ/G2M board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I3ed55aa4a2cc5c9d9cd6440e087bcd93186520c7
- drivers: renesas: rzg: Add HiHope RZ/G2M board support
Add support for HiHope RZ/G2M board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ic8eed0729a42aeee94fc96d16b15b928232488a3
- tools: renesas: Add tool support for RZ/G2 platforms
Add tool support for creating bootparam and cert_header images
for RZ/G2 SoC based platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Iab8ba6eda442c8d75f23c5633b8178f86339e4c9
- doc: renesas: Update code owner for Renesas platforms
Add Marek Vasut as the code owner for the common code shared by
both Renesas R-Car and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I3c0a402f4663ffcf4d2df408a3ccd4d1a8629b3a
- doc: renesas: Document platforms based on RZ/G2 SoC's
Document the platforms based on RZ/G2 SoC's.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I9ce5b9df3573b1198c5c7be79b5471d54573609a
- renesas: rzg: Add PFC support for RZ/G2M
Add pin control support for RZ/G2M SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I08719015cab1ec59e2270523980a0a3e26e72c01
- renesas: rzg: Add QoS support for RZ/G2M
Add QoS support for RZ/G2M SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: If541278fd629761cc83398bba71e63f09d9dbee6
- docs: update fvp version to be used for rdv1 platform
Move RD-V1 platform to use version of FVP_RD_Daniel from 11.10 build 36
to 11.13 build 10
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I9622c03d342bb780234dec8ffe4ab11d8069acab
- tools: don't clean when building
Don't depend on clean when building, as the user is capable of cleaning
if required and this introduces a race where "all" depends on both the
compile and the clean in parallel. It's quite possible for some of the
compile to happen in parallel with the clean, which results in the link
failing as objects just built are missing.
Change-Id: I710711eea7483cafa13251c5d94ec693148bd001
Signed-off-by: Ross Burton <ross.burton@arm.com>
- renesas: rzg: Add support for DRAM initialization
Add support for initializing DRAM on RZ/G2M SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I99f1a6971a061a44687af498d55306a93e4fc8f7
- plat: renesas: common: Include ulcb_cpld.h conditionally
Include header ulcb_cpld.h in plat_pm.c only if RCAR_GEN3_ULCB
is enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ie89223097c608265c50e32778e8df28feed82480
- plat: renesas: Move to common
Move rcar plat code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I1001bea1a8a9232a03ddbf6931ca3c764ba1e181
- plat: renesas: aarch64: Move to common
Move plat aarch64 code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I66265e5e68bfcf5c3534965fb3549a145c782b47
- drivers: renesas: Move ddr/qos/qos header files
Move DDR/QoS/PFC header files, so that the same code
can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I2cc0ceda8d05b6b8d95a69afdc233dc0d098e850
- drivers: renesas: rpc: Move to common
Move rpc driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I04805d720d95b8edcc14e652f897fadc7f432197
- drivers: renesas: avs: Move to common
Move avs driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I85d9fa8b6abf158ce2521f1696478f7c5339fc42
- drivers: renesas: auth: Move to common
Move authentication driver code to common directory, so that the
same code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I02592dfc714998bf89b9feaa78f685ae36be6f59
- drivers: renesas: dma: Move to common
Move dma driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Idce2e2f4e098cfc17219f963373d20ebf74e5b7c
- drivers: renesas: watchdog: Move to common
Move watch driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I235f2cde325a0feeadbfc4b7ee02e8b1186f7ea1
- drivers: renesas: rom: Move to common
Move rom driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I399dfb5eff186db76d26fa9c54bea88bee66789c
- drivers: renesas: delay: Move to common
Move delay driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I5e806bd0e0a0a4b436048513b7089db90ff9805f
- drivers: renesas: console: Move to common
Move console/scif driver code to common directory, so that the
same code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I0b15e4f4ffaaa99e77bcee32b1dad648eeadcd9b
- drivers: renesas: pwrc: Move to common
Move pwrc driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I75d91a44d872fe2296b15c700efacd5721385363
- drivers: renesas: io: Move to common
Move io driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ic661e415c91a1fbfd5eee3bba86466037e51574b
- drivers: renesas: eMMC: Move to common
Move eMMC driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I7f3055709337327d1a1c9f563c14ad1626adb355
- drivers: renesas: Move plat common sources
Move plat common sources to common directory, so that same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Id2b1822c97cc50e3febaffc2e5f42b4d53809a17
- plat: renesas: Move headers and assembly files to common folder
Create a common directory and move the header and assembly files
so that the common code can be used by both Renesas R-Car Gen3 and
RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ia9a563a1c3c9f8c6f0d3cb82622deb2e155d7f6c
- plat: renesas: rcar: include: Code cleanup
This patch fixes checkpatch warnings and replaces TAB with
space after #define macros.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
- plat: renesas:rcar: Fix checkpatch warnings
Fix checkpatch warnings.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: If9318a5113fbd6ae8b5c4bfb409da9e393673258
- plat: renesas: rcar: Fix checkpatch warnings
Fix checkpatch warnings.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I46801b563c887dc0a66e224ab4971e6503641529
- plat: renesas:rcar: Code cleanup
Sort the header includes alphabetically, fix typos and drop unneeded TAB
and replace it with space
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ieff84434877f58ec26c8351611059ad4e11a4e28
- plat: renesas: rcar: Fix coding style
Sort the header includes alphabetically and fix checkpatch warnings.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I08fd0d12ee1d8d61391e8afc33f8c67fcf70c4e5
- Merge "qemu/qemu_sbsa: enable secure variable storage" into integration
- qemu/qemu_sbsa: enable secure variable storage
This implements support for UEFI secure variable storage
using standalone MM framework on qemu_sbsa platform.
Non-secure shared memory between UEFI and standalone MM
is allocated at the top of DRAM.
DRAM size of qemu_sbsa varies depends on the QEMU parameter,
so the non-secure shared memory is allocated by trusted firmware
and passed the base address and size to UEFI through device tree
"/reserved-memory" node.
Change-Id: I367191f408eb9850b7ec7761ee346b014c539767
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
- Merge "Workaround for Cortex A78 erratum 1941498" into integration
- Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
- Merge "zynqmp: pm: Add support for PS and system reset on WDT restart" into integration
- zynqmp: pm: Add support for PS and system reset on WDT restart
Add ability to support PS and System reset after idling the APU,
by reading the restart scope from the PMU.
Signed-off-by: Will Wong <willw@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I23c01725d8ebb71ad34be02ab204411b93620702
- Merge "plat: marvell: armada: a3k: improve 4GB DRAM usage from 3.375 GB to 3.75 GB" into integration
- Merge "zynqmp: pm: Update PM version and support PM version check" into integration
- Merge changes from topic "renaming_daniel" into integration
* changes:
plat/arm: rename rddanielxlr to rdv1mc
plat/arm: rename rddaniel to rdv1
- zynqmp: pm: Update PM version and support PM version check
ATF is not checking PM version. Add version check in such
a way that it is compatible with current and newer version
of PM.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ia095d118121e6f75e8d320e87d5e2018068fa079
- Merge "plat: xilinx: Fix non-MISRA compliant code" into integration
- plat: marvell: armada: a3k: improve 4GB DRAM usage from 3.375 GB to 3.75 GB
The current configuration of CPU windows on Armada 37x0 with 4 GB DRAM
can only utilize 3.375 GB of memory. This is because there are only 5
configuration windows, configured as such (in hexadecimal, also showing
ranges not configurable by CPU windows):
0 - 80000000 | 2 GB | DDR | CPU window 0
80000000 - C0000000 | 1 GB | DDR | CPU window 1
C0000000 - D0000000 | 256 MB | DDR | CPU window 2
D0000000 - D2000000 | 32 MB | | Internal regs
empty space | | |
D8000000 - D8010000 | 64 KB | | CCI regs
empty space | | |
E0000000 - E8000000 | 128 MB | DDR | CPU window 3
E8000000 - F0000000 | 128 MB | PCIe | CPU window 4
empty space | | |
FFF00000 - end | 64 KB | | Boot ROM
This can be improved by taking into account that:
- CCI window can be moved (the base address is only hardcoded in TF-A;
U-Boot and Linux will not break with changing of this address)
- PCIe window can be moved (upstream U-Boot can change device-tree
ranges of PCIe if PCIe window is moved)
Change the layout after the Internal regs as such:
D2000000 - F2000000 | 512 MB | DDR | CPU window 3
F2000000 - FA000000 | 128 MB | PCIe | CPU window 4
empty space | | |
FE000000 - FE010000 | 64 KB | | CCI regs
empty space | | |
FFF00000 - end | 64 KB | | Boot ROM
(Note that CCI regs base address is moved from D8000000 to FE000000 in
all cases, not only for the configuration with 4 GB of DRAM. This is
because TF-A is built with this address as a constant, so we cannot
change this address at runtime only on some boards.)
This yields 3.75 GB of usable RAM.
Moreover U-Boot can theoretically reconfigure the PCIe window to DDR if
it discovers that no PCIe card is connected. This can add another 128 MB
of DRAM (resulting only in 128 MB of DRAM not being used).
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I4ca1999f852f90055fac8b2c4f7e80275a13ad7e
- Merge changes I46cd4d9b,Iba009587,I41d146e8,Ic66ceab3,Iff46838a, ... into integration
* changes:
drivers: renesas: rcar: io: Code cleanup
drivers: renesas: rcar: pwrc: Code cleanup
drivers: renesas: rcar: common: Code cleanup
drivers: renesas: rcar: watchdog: Fix typo
drivers: renesas: rcar: scif: Fix coding style
drivers: renesas: rcar: iic_dvfs: Fix coding style
- Merge "cadence: Change logic in uart driver" into integration
- Merge changes I07c35829,Iec7dd019,Ic7406aa8,I4eac94f0 into integration
* changes:
drivers: renesas: rcar: dma: Fix coding style
drivers: renesas: rcar: delay: Fix checkpatch warnings
drivers: renesas: rcar: avs: Fix checkpatch warnings
drivers: renesas: rcar: auth: Use space instead of TAB
- cadence: Change logic in uart driver
Write char if fifo is empty. If this is done like this all chars are
printed. Because origin code just put that chars to fifo and in case of
reset messages were missing.
Before this change chars are put to fifo and only check before adding if
fifo is full. The patch is changing this logic that it is adding char only
when fifo is empty to make sure that in case of reset (by another SW for
example) all chars are printed. Maybe one char can be missed but for IP
itself it is much easier to send just one char compare to full fifo.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Ic24c2c1252bce24be2aed68ee29477ca4a549e5f
- drivers: renesas: rcar: io: Code cleanup
This patch fixes checkpatch warnings and arrange header
as per TF-A coding style.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I46cd4d9b2851202324fe714e776cf3ad2ee1d923
- drivers: renesas: rcar: pwrc: Code cleanup
This patches fixes checkpatch warnings, replace TAB with space
after #define macros and arrange header as per TF-A coding style.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Iba009587e0b499b3ae58876be390602ae14175b2
- drivers: renesas: rcar: common: Code cleanup
This patch fixes the below checkpatch warnings
Line 13: WARNING: please, no spaces at the start of a line
Line 15: WARNING: please, no spaces at the start of a line
Line 18: WARNING: Missing a blank line after declarations
Line 24: WARNING: please, no spaces at the start of a line
Line 26: WARNING: please, no spaces at the start of a line
Line 29: WARNING: Missing a blank line after declarations
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I41d146e86889640d11e88c0717039353ddceff0d
- drivers: renesas: rcar: watchdog: Fix typo
Fix the typo "occured" -> "occurred"
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ic66ceab364f7dc926dc6a6db641ca173601cd031
- drivers: renesas: rcar: scif: Fix coding style
Replace TAB with space after #define macros and update comments as per
TF-A coding style.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Iff46838a41f991f7dd9dc6fb043e9e482ea0b11d
- drivers: renesas: rcar: iic_dvfs: Fix coding style
Sort the header includes alphabetically, fix typos and drop unneeded TAB
and replace it with space
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I62e2658b0309c0985dd32ff023b8b16bd7f2be8e
- drivers: renesas: rcar: dma: Fix coding style
Sort the headers alphabetically and replace TAB with a space
after #define.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I07c358294b7c02cbfa360112bbbde0eb5f2b50f5
- drivers: renesas: rcar: delay: Fix checkpatch warnings
Fix checkpatch warnings.
There are no functional changes.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Iec7dd019bd38e84eccd8cc17189745fdef1911bb
- drivers: renesas: rcar: avs: Fix checkpatch warnings
Fix checkpatch warnings.
There are no functional changes.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ic7406aa88e121914270a8d192f170c9c4244578a
- drivers: renesas: rcar: auth: Use space instead of TAB
Use space instead of TAB after #define's. Also updated
header files as per TF-A coding style.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I4eac94f0bc79f24b8ac7165ec48f1e1de95d7205
- plat/arm: rename rddanielxlr to rdv1mc
Reference Design platform RD-Daniel-ConfigXLR has been renamed to
RD-V1-MC. Correspondingly, remove all uses of 'rddanielxlr' and replace
it with 'rdv1mc' where appropriate.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I5d91c69738397b19ced43949b4080c74678e604c
- plat/arm: rename rddaniel to rdv1
Reference Design platform RD-Daniel has been renamed to RD-V1.
Correspondingly, remove all uses of 'rddaniel' and replace it with
'rdv1' where appropriate.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I1702bab39c501f8c0a09df131cb2394d54c83bcf
- plat: xilinx: Fix non-MISRA compliant code
This patch fixes the non compliant code like missing braces for
conditional single statement bodies.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I95b410ae5950f85dc913c4448fcd0a97e0fd490c
- Makefile: Fix ${FIP_NAME} to be rebuilt only when needed
Currently ${FIP_DEPS} as prerequisite for ${BUILD_PLAT}/${FIP_NAME}
contains .PHONY targets check_$(1) and therefore ${BUILD_PLAT}/${FIP_NAME}
is always rebuilt even when other file target prerequisites are not
changed.
These changes fix above issue and ${BUILD_PLAT}/${FIP_NAME} target is
rebuilt only when its prerequisites are changed.
There are 3 changes:
Content of check_$(1) target is moved into check_$(1)_cmd variable so it
can be easily reused.
.PHONY check_$(1) targets are not put into ${FIP_DEPS} and ${FWU_FIP_DEPS}
dependencies anymore and required checks which are in ${CHECK_FIP_CMD} and
${CHECK_FWU_FIP_CMD} variables are executed as part of targets
${BUILD_PLAT}/${FIP_NAME} and ${BUILD_PLAT}/${FWU_FIP_NAME} itself.
To ensure that ${BUILD_PLAT}/${FIP_NAME} and ${BUILD_PLAT}/${FWU_FIP_NAME}
are rebuilt even when additional dependency file image added by
TOOL_ADD_IMG is changed, this file image (if exists) is added as file
dependency to ${FIP_DEPS} and ${FWU_FIP_DEPS}. If it does not exist then
FORCE target is added to ensure that FIP/FWU_FIP is rebuilt. Command
${CHECK_FIP_CMD}/${CHECK_FWU_FIP_CMD} will then thrown an error message if
the file is required but not present.
So this change ensures that if BL33 image is updated then final FIP image
is updated too. And if BL33 image is not specified or does not exist and is
required to be present then check_$(1)_cmd call from ${CHECK_FIP_CMD} would
ensure that error message is thrown during build.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I635cf82e2b667ff57e2af83500d4aca71d235e3e
- Makefile: Do not mark file targets as .PHONY target
Only non-file targets should be set a .PHONY. Otherwise if file target is
set as .PHONY then targets which depends on those file .PHONY targets would
be always rebuilt even when their prerequisites are not changed.
File target which needs to be always rebuilt can be specified in Make
system via having a prerequisite on some .PHONY target, instead of marking
whole target as .PHONY. In Makefile projects it is common to create empty
.PHONY target named FORCE for this purpose.
This patch changes all file targets which are set as .PHONY to depends on
new .PHONY target FORCE, to ensure that these file targets are always
rebuilt (as before). Basically they are those targets which calls external
make subprocess.
After FORCE target is specified in main Makefile, remove it from other
Makefile files to prevent duplicate definitions.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iee3b4e0de93879b95eb29a1745a041538412e69e
- Merge "AArch64: Fix assertions in processing dynamic relocations" into integration
- Merge "drivers: renesas: rcar: eMMC driver code clean up" into integration
- Merge "plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor" into integration
- Merge changes from topic "xilinx-sd-tap-delay" into integration
* changes:
plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay
plat: zynqmp: Check for DLL status before doing reset
- AArch64: Fix assertions in processing dynamic relocations
This patch provides the following changes in fixup_gdt_reloc()
function:
- Fixes assertions in processing dynamic relocations, when
relocation entries not matching R_AARCH64_RELATIVE type are found.
Linker might generate entries of relocation type R_AARCH64_NONE
(code 0), which should be ignored to make the code boot. Similar
issue was fixed in OP-TEE (see optee_os/ldelf/ta_elf_rel.c
commit 7a4dc765c133125428136a496a7644c6fec9b3c2)
- Fixes bug when "b.ge" (signed greater than or equal) condition
codes were used instead of "b.hs" (greater than or equal) for
comparison of absolute addresses.
- Adds optimisation which skips fixing Global Object Table (GOT)
entries when offset value is 0.
Change-Id: I35e34e055b7476843903859be947b883a1feb1b5
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
- plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor
Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which,
when enabled, adds code to the PSCI reset handler to try to do system
reset by the WTMI firmware running on the Cortex-M3 secure coprocessor.
(This function is exposed via the mailbox interface.)
The reason is that the Turris MOX board has a HW bug which causes reset
to hang unpredictably. This issue can be solved by putting the board in
a specific state before reset.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I3f60b9f244f334adcd33d6db6a361fbc8b8d209f
- Merge "Plat AXG: Fix PLAT_MAX_PWR_LVL value" into integration
- Merge changes from topic "zynqmp-new-apis" into integration
* changes:
xilinx: zynqmp: Add support for Error Management
zynqmp:pm: Adds new zynqmp-pm api SMC call for efuse
zynqmp : pm : Adds new zynqmp-pm api SMC call for register access
- xilinx: zynqmp: Add support for Error Management
Adding the EM specific smc handler for the EM-related requests.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I98122d49604a01a2f6bd1e509a5896ee68069dd0
- zynqmp:pm: Adds new zynqmp-pm api SMC call for efuse
This patch adds new api to access zynqmp efuse memory
Signed-off-by: VNSL Durga <vnsl.durga.challa@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I0971ab6549552a6f96412431388d19b822db00ab
- zynqmp : pm : Adds new zynqmp-pm api SMC call for register access
This patch adds new zynqmp-pm api to provide read/write access to
CSU or PMU global registers.
Signed-off-by: Kalyani Akula <kalyania@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I4fd52eb732fc3e6a8bccd96cad7dc090b2161042
- Merge "marvell: uart: a3720: Implement console_a3700_core_flush" into integration
- Plat AXG: Fix PLAT_MAX_PWR_LVL value
This patch fixes AXG platform build error:
plat/amlogic/axg/axg_pm.c: In function 'axg_pwr_domain_off':
plat/amlogic/axg/axg_pm.c:124:43: error: array subscript 2
is above array bounds of 'const plat_local_state_t[2]'
{aka 'const unsigned char[2]'}
by changing PLAT_MAX_PWR_LVL from MPIDR_AFFLVL1 to MPIDR_AFFLVL2
in plat\amlogic\axg\include\platform_def.h.
Change-Id: I9a701e8f26231e62f844920aec5830664f3fb324
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
- Merge changes I8cd2c1c9,I697711ee,I4a0ec150,I4f8064b9,Ie22cb2a3, ... into integration
* changes:
ti: k3: Introduce lite device board support
ti: k3: common: sec_proxy: Introduce sec_proxy_lite definition
ti: k3: Move USE_COHERENT_MEM only for the generic board
ti: k3: drivers: ti_sci: Update ti_sci_msg_req_reboot to include domain
ti: k3: common: sec_proxy: Fill non-message data fields with 0x0
ti: k3: common: Make plat_get_syscnt_freq2 check CNT_FID0 GTC reg
ti: k3: common: Enable A72 erratum 1319367
ti: k3: common: Enable A53 erratum 1530924
maintainers: Update maintainers for TI port
- marvell: uart: a3720: Implement console_a3700_core_flush
Implementation is simple, just wait for the TX FIFO to be empty.
Without this patch TF-A on A3720 truncate the last line:
NOTICE: BL31: Built : 16:1
With this patch TF-A on A3720 print correctly also the last line:
NOTICE: BL31: Built : 19:03:31, Dec 23 2020
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2f2ea42beab66ba132afdb400ca7898c5419db09
- ti: k3: Introduce lite device board support
Add device support for the 'lite' K3 devices. These will use modified
device addresses and allow for fewer cores to save memory.
Note: This family of devices are characterized by a single cluster
of ARMv8 processor upto a max of 4 processors and lack of a level 3
cache.
The first generation of this family is introduced with AM642.
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I8cd2c1c9a9434646d0c72fca3162dd5bc9bd692a
- ti: k3: common: sec_proxy: Introduce sec_proxy_lite definition
There are two communication scheme that have been enabled to communicate
with Secure Proxy in TI.
a) A full fledged prioritized communication scheme, which involves upto
5 threads from the perspective of the host software
b) A much simpler "lite" version which is just a two thread scheme
involving just a transmit and receive thread scheme.
The (a) system is specifically useful when the SoC is massive
involving multiple processor systems and where the potential for
priority inversion is clearly a system usecase killer. However, this
comes with the baggage of significant die area for larger number of
instances of secure proxy, ring accelerator and backing memories
for queued messages. Example SoCs using this scheme would be:
AM654[1], J721E[2], J7200[3] etc.
The (b) scheme(aka the lite scheme) is introduced on smaller SoCs
where memory and area concerns are paramount. The tradeoff of
priority loss is acceptable given the reduced number of processors
communicating with the central system controller. This brings about
a very significant area and memory usage savings while the loss of
communication priority has no demonstrable impact. Example SoC using
this scheme would be: AM642[4]
While we can detect using JTAG ID and conceptually handle things
dynamically, adding such a scheme involves a lot of unused data (cost
of ATF memory footprint), pointer lookups (performance cost) and still
due to follow on patches, does'nt negate the need for a different
build configuration. However, (a) and (b) family of SoCs share the
same scheme and addresses etc, this helps minimize our churn quite a
bit
Instead of introducing a complex data structure lookup scheme, lets
keep things simple by first introducing the pieces necessary for an
alternate communication scheme, then introduce a second platform
representing the "lite" family of K3 processors.
NOTE: This is only possible since ATF uses just two (secure) threads
for actual communication with the central system controller. This is
sufficient for the function that ATF uses.
The (a) scheme and the (b) scheme also varies w.r.t the base addresses
used, even though the memory window assigned for them have remained
consistent. We introduce the delta as part of this change as well.
This is expected to remain consistent as a standard in TI SoCs.
References:
[1] See AM65x Technical Reference Manual (SPRUID7, April 2018)
for further details: https://www.ti.com/lit/pdf/spruid7
[2] See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: https://www.ti.com/lit/pdf/spruil1
[3] See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1
[4] See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I697711ee0e6601965015ddf950fdfdec8e759bfc
- ti: k3: Move USE_COHERENT_MEM only for the generic board
commit 65f7b81728d0 ("ti: k3: common: Use coherent memory for shared data")
introduced WARMBOOT_ENABLE_DCACHE_EARLY and USE_COHERENT_MEM to handle
multiple clusters across L3 cache systems. This is represented by
"generic" board in k3 platform.
On "lite" platforms, however, system level coherency is lacking since
we don't have a global monitor or an L3 cache controller. Though, at
a cluster level, ARM CPU level coherency is very much possible since
the max number of clusters permitted in lite platform configuration is
"1".
However, we need to be able to disable USE_COHERENT_MEM for the lite
configuration due to the lack of system level coherency.
See docs/getting_started/build-options.rst for further information.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I4a0ec150b3f9ea12369254aef834a6cbe82d6be6
- ti: k3: drivers: ti_sci: Update ti_sci_msg_req_reboot to include domain
The ti_sci_msg_req_reboot message payload has been extended to include
a domain field, and this should be zero to reset the entire SoC with
System Firmwares newer than v2020.04. Add the domain field to the
ti_sci_msg_req_reboot message structure for completeness. Set it up
to zero to fix the reboot issues with newer firmwares.
This takes care of the specific ABI that changed and has an impact on
ATF function.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I4f8064b9d6555687822dc2b2b8ec97609286fa0b
- ti: k3: common: sec_proxy: Fill non-message data fields with 0x0
Sec proxy data buffer is 60 bytes with the last of the registers
indicating transmission completion. This however poses a bit
of a challenge.
The backing memory for sec_proxy is regular memory, and all sec proxy
does is to trigger a burst of all 60 bytes of data over to the target
thread backing ring accelerator. It doesn't do a memory scrub when
it moves data out in the burst. When we transmit multiple messages,
remnants of previous message is also transmitted which results in
some random data being set in TISCI fields of messages that have been
expanded forward.
The entire concept of backward compatibility hinges on the fact that
the unused message fields remain 0x0 allowing for 0x0 value to be
specially considered when backward compatibility of message extension
is done.
So, instead of just writing the completion register, we continue
to fill the message buffer up with 0x0 (note: for partial message
involving completion, we already do this).
This allows us to scale and introduce ABI changes back into TF-A only
as needed.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ie22cb2a319f4aa80aef23ffc7e059207e5d4c640
- ti: k3: common: Make plat_get_syscnt_freq2 check CNT_FID0 GTC reg
ARM's generic timer[1] picks up it's graycode from GTC. However, the
frequency of the GTC is supposed to be programmed in CNTFID0[2]
register.
In K3, architecture, GTC provides a central time to many parts of the
SoC including graycode to the generic timer in the ARMv8 subsystem.
However, due to the central nature and the need to enable the counter
early in the boot process, the R5 based bootloader enables GTC and
programs it's frequency based on central needs of the system. This
may not be a constant 200MHz based on the system. The bootloader is
supposed to program the FID0 register with the correct frequency it
has sourced for GTC from the central system controller, and TF-A is
supposed to use that as the frequency for it's local timer.
A mismatch in programmed frequency and what we program for generic
timer will, as we can imagine, all kind of weird mayhem.
So, check the CNTFID0 register, if it is 0, warn and use the default
frequency to continue the boot process.
While at it, we can also check CNTCR register to provide some basic
diagnostics to make sure that we don't have OS folks scratch their
heads. Even though this is used during cpu online operations, the cost
of this additional check is minimal enough for us not to use #ifdeffery
with DEBUG flags.
[1] https://developer.arm.com/documentation/100095/0002/generic-timer/generic-timer-register-summary/aarch64-generic-timer-register-summary
[2] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntfid0
[3] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntcr
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ib03e06788580f3540dcb1a11677d0d6d398b2c9f
- ti: k3: common: Enable A72 erratum 1319367
The CatB erratum ARM_ERRATA_A72_1319367 applies to all TI A72
platforms as well.
See the following for further information:
https://developer.arm.com/documentation/epm012079/11/
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I80c6262b9cdadcb12f6dfd5a21272989ba257719
- ti: k3: common: Enable A53 erratum 1530924
The CatB erratum ARM_ERRATA_A53_1530924 applies to all TI A53
platforms as well.
See the following for further information:
https://developer.arm.com/documentation/epm048406/2100
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ic095424ce510139e060b38cfb84509d2cc573cad
- maintainers: Update maintainers for TI port
Andrew is no longer with TI unfortunately, so stepping up to provide
maintainer for supported TI platforms.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ia1be294631421913bcbc3d346947195cb442d437
- Merge changes from topic "zynqmp-update-pinctrl-api" into integration
* changes:
zynqmp: pm: Reimplement pinctrl get/set config parameter EEMI API calls
zynqmp: pm: Reimplement pinctrl set/get function EEMI API
zynqmp: pm: Implement pinctrl request/release EEMI API
zynqmp: pm: Update return type in query functions
- Merge "PSCI: fix limit of 256 CPUs caused by cast to unsigned char" into integration
- Merge changes I65450c63,I71d0aa82,Ia395eb32,I4aaed371 into integration
* changes:
mediatek: mt8192: add rtc power off sequence
mediatek: mt8192: Fix non-MISRA compliant code
mediatek: mt8192: Fix non-MISRA compliant code
mediatek: mt8192: Add MPU support
- Merge changes I3703868b,Ie77476db into integration
* changes:
allwinner: Add SPC security setup for H6
allwinner: Add R_PRCM security setup for H6
- Merge "allwinner: Fix non-default PRELOADED_BL33_BASE" into integration
- Merge "allwinner: Enable workaround for Cortex-A53 erratum 1530924" into integration
- Merge changes I0c5f32e8,Id49c124c,Idcfe933d into integration
* changes:
allwinner: Use RSB for the PMIC connection on H6
allwinner: Return the PMIC to I2C mode after use
allwinner: Always use a 3MHz RSB bus clock
- PSCI: fix limit of 256 CPUs caused by cast to unsigned char
In psci_setup.c psci_init_pwr_domain_node() takes an unsigned
char as node_idx which limits it to initialising only the first
256 CPUs. As the calling function does not check for a limit of
256 I think this is a bug so change the unsigned char to
uint16_t and change the cast from the calling site in
populate_power_domain_tree().
Also update the non_cpu_pwr_domain_node structure lock_index
to uint16_t and update the function signature for psci_lock_init()
appropriately.
Finally add a define PSCI_MAX_CPUS_INDEX to psci_private.h and add
a CASSERT to psci_setup.c to make sure PLATFORM_CORE_COUNT cannot
exceed the index value.
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: I9e26842277db7483fd698b46bbac62aa86e71b45
- Merge changes from topic "tc0_optee_sp" into integration
* changes:
fdts: tc0: Add reserved-memory node for OP-TEE
plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
docs: arm: Add OPTEE_SP_FW_CONFIG
plat: tc0: enable opteed support
plat: arm: Increase SP max size
- drivers: renesas: rcar: eMMC driver code clean up
Fix checkpatch warnings and MISRA defects.
There are no functional changes.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I349a8eaa7bd6182746ba5104ee9fe48a709c24fd
- Merge "Workaround for Cortex A76 erratum 1946160" into integration
- Workaround for Cortex A76 erratum 1946160
Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions
of the A76 processor core. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This issue is
present in revisions r0p0 - r4p1 but this workaround only applies to
revisions r3p0 - r4p1, there is no workaround for older versions.
SDEN can be found here:
https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327
- Merge "plat/arm/rdn2: update gic redistributor base address" into integration
- mediatek: mt8192: add rtc power off sequence
add mt6359p rtc power off sequence and enable k_eosc mode
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.com>
Change-Id: I65450c63c44ccb5082541dbbe28b8aa0a95ecc56
- mediatek: mt8192: Fix non-MISRA compliant code
CID 364146: Control flow issues (DEADCODE)
Since the value of PSTATE_PWR_LVL_MASK and the value the of PLAT_MAX_PWR_LVL
are equal on mt8192, the following equation never hold.
if (aff_lvl > PLAT_MAX_PWR_LVL) {
return PSCI_E_INVALID_PARAMS;
}
Remove the deadcode to comply with MISRA standard.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I71d0aa826eded8c3b5af961e733167ae40699398
- mediatek: mt8192: Fix non-MISRA compliant code
CID 364144: Integer handling issues (NO_EFFECT)
The unsigned value is always greater-than-or-equal-to-zero.
Remove such check.
Change-Id: Ia395eb32f55a7098d2581ce7f548b7e1112beaa0
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
- mediatek: mt8192: Add MPU support
1 Add Domain1(PCIe device) protect address: 0x80000000~0x83FF0000.
2 Add Domain2(SSPM/SPM/DPM/MCUPM) protect address: 0x40000000~0x1FFFF0000.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I4aaed37150076ae5943484c4adadac999a3d1762
- plat/arm/rdn2: update gic redistributor base address
RD-N2 platform has been updated to use six GIC ITS blocks. This results
in change in base address of the GIC Redistributor to accomodate two
new GIC ITS blocks. Update the base address of GICR to reflect the same.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I740a547328fb9a9f25d7a09c08e61bdbc8bf781c
- Merge "Add support for FEAT_MTPMU for Armv8.6" into integration
- zynqmp: pm: Reimplement pinctrl get/set config parameter EEMI API calls
Functions are reimplemented to issue system-level pinctrl EEMI calls
to the PMU-FW rather than using MMIO read/write. Macros and functions
that appear to be unused after the change is made are removed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I51f2285a79f202cb2ca9f031044002e16dd1e92f
- zynqmp: pm: Reimplement pinctrl set/get function EEMI API
Functions are reimplemented to issue system-level pinctrl EEMI calls
to the PMU-FW rather than using MMIO read/write. Macros and functions
that appear to be unused after the change is made are removed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I21b8fda855aa69090b85d6aaf411e19560201cb5
- zynqmp: pm: Implement pinctrl request/release EEMI API
The calls are just passed through to the PMU-FW. Before issuing
other pinctrl functions the pin should be successfully requested.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibce280edebedf779b3962009c274d0b3d928e0e4
- zynqmp: pm: Update return type in query functions
In pm_query_data() function return type is stored in response so
there is no use of return type. Update return type of function
pm_query_data() from enum pm_ret_status to void. Similarly
update return type of pm_api_clock_get_name() and
pm_api_pinctrl_get_function_name() functions.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Id811926f0b4ebcc472480bb94f3b88109eb036cd
- fdts: tc0: Add reserved-memory node for OP-TEE
Add reserved-memory region for OP-TEE and mark as no-map. This memory
region is used by OP-TEE as non-secure shared RAM.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I5a22999a8c5550024d0f47e848d35924017df245
- plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
This patch adds support to enable OP-TEE as S-EL1 SP with SPMC at S-EL2
- create SPMC manifest file with OP-TEE as SP
- add support for ARM_SPMC_MANIFEST_DTS build option
- add optee entry with ffa as method in tc0.dts
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ia9b5c22c6f605d3886914bbac8ac45e8365671cb
- docs: arm: Add OPTEE_SP_FW_CONFIG
This adds documentation for device tree build flag OPTEE_SP_FW_CONFIG.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ie45f075cf04182701007f87aa0c8912cd567157a
- plat: tc0: enable opteed support
Enable SPD=opteed support for tc0 platform.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ieb038d645c68fbe6b5a211c7279569e21b476fc3
- plat: arm: Increase SP max size
Increase SP max size for latest OP-TEE build with debug and
stats enabled.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I4593884e0deb39ada10009f6876d815136f8ee65
- allwinner: Use RSB for the PMIC connection on H6
RSB is faster and more efficient, and it has a simpler driver. As long
as the PMIC is returned to I2C mode after use, the rich OS can later use
either bus.
Change-Id: I0c5f32e88a090c8c5cccb81bd24596b301ab9da7
Signed-off-by: Samuel Holland <samuel@sholland.org>
- allwinner: Return the PMIC to I2C mode after use
This gives the rich OS the flexibility to choose between I2C and RSB
communication. Since a runtime address can only be assigned once after
entering RSB mode, it also lets the rich OS choose any runtime address.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id49c124c5e925985fc31c0ba38c7fb6c941aafa8
- allwinner: Always use a 3MHz RSB bus clock
None of the other drivers (Linux, U-Boot, Crust) need to lower the bus
clock frequency to switch the PMIC to RSB mode. That logic is not needed
here, either. The hardware takes care of running this transaction at the
correct bus frequency.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Idcfe933df4da75d5fd5a4f3e362da40ac26bdad1
- allwinner: Enable workaround for Cortex-A53 erratum 1530924
BL31 reports the following warning during boot:
WARNING: BL31: cortex_a53: CPU workaround for 1530924 was missing!
Resolve this by enabling the workaround on the affected platforms.
Change-Id: Ia1d5075370be5ae67b7bece96ec0069d9692b14c
Signed-off-by: Samuel Holland <samuel@sholland.org>
- allwinner: Fix non-default PRELOADED_BL33_BASE
While the Allwinner platform code nominally supported a custom
PRELOADED_BL33_BASE, some references to the BL33 load address used
another constant: PLAT_SUNXI_NS_IMAGE_OFFSET. To allow the DTB search
code to work if a U-Boot BL33 is loaded to a custom address,
consistently use PRELOADED_BL33_BASE. And to avoid this confusion in
the future, remove the other constant.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie6b97ae1fdec95d784676aef39200bef161471b0
- allwinner: Add SPC security setup for H6
The H6 has a "secure port controller" similar to the A64/H5, but with
more ports and a different register layout. Split the platform-specific
parts out into a header, and add the missing MMIO base address.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I3703868bc595459ecf9568b9d1605cb1be014bf5
- allwinner: Add R_PRCM security setup for H6
H6 has a reorganized R_PRCM compared to A64/H5, with the security switch
at a different offset. Until now, we did not notice, because the switch
has no effect unless the secure mode e-fuse is blown.
Since we are adding more platform-specific CCU registers, move them to
their own header, and out of the memory map (where they do not belong).
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie77476db0515080954eaa2e32bf6c3de657cda86
- Merge "TF-A: Add build option for Arm Feature Modifiers" into integration
- Merge changes from topic "rdevans" into integration
* changes:
doc: Update list of supported FVP platforms
board/rdn2: add board support for rdn2 platform
plat/arm/sgi: adapt to changes in memory map
plat/arm/sgi: add platform id value for rdn2 platform
plat/arm/sgi: platform definitions for upcoming platforms
plat/arm/sgi: refactor header file inclusions
plat/arm/sgi: refactor the inclusion of memory mapping
- Add support for FEAT_MTPMU for Armv8.6
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happening on other threads.
If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit
leaving it to effective state of 0 regardless of any write to it.
This patch introduces the DISABLE_MTPMU flag, which allows to diable
multithread event count from EL3 (or EL2). The flag is disabled
by default so the behavior is consistent with those architectures
that do not implement FEAT_MTPMU.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
- TF-A: Add build option for Arm Feature Modifiers
This patch adds a new ARM_ARCH_FEATURE build option
to add support for compiler's feature modifiers.
It has the form '[no]feature+...' and defaults to
'none'. This option translates into compiler option
'-march=armvX[.Y]-a+[no]feature+...'.
Change-Id: I37742f270a898f5d6968e146cbcc04cbf53ef2ad
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
- plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay
This patch disable the ITAPDLYENA bit for ITAP delay value zero.
As per IP design, it is recommended to disable the ITAPDLYENA bit
before auto-tuning.
Also disable OTAPDLYENA bit always as there is one issue in RTL
where SD0_OTAPDLYENA has been wrongly connected to both SD0 and SD1
controllers. Hence it is recommended to disable OTAPDLYENA bit always
for both the controllers.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Acked-by: Srinivas Goud <srinivas.goud@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Icf035cb63510ac7bec4e9d523a622f145eaf0989
- plat: zynqmp: Check for DLL status before doing reset
This patch check for the DLL status before doing the DLL reset.
If DLL reset is already issued then skip the reset inside ATF
otherwise DLL reset will be issued.
By doing this way, all the following cases will be supported.
1. Patched ATF + Patched Linux base.
2. Older ATF + Patched Linux base.
3. Patched ATF + Older Linux base.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I53a0a27521330f1543275cc9cb44cd1dfc569c65
- Merge "xilinx: versal: fix static failure" into integration
- xilinx: versal: fix static failure
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Icef550072296d6aba89a0827dd72d0b86047556f
- Merge changes from topic "versal-bug-fixes-and-new-apis" into integration
* changes:
plat: xilinx: versal: Add support of register notifier
plat: xilinx: versal: Add support to get clock rate value
plat: xilinx: versal: Add support of set max latency for the device
plat: versal: Add InitFinalize API call
xilinx: versal: Updated Response of QueryData API call
plat:xilinx:versal: Use defaults when PDI is without sw partitions
plat: xilinx: Mask unnecessary bytes of return error code
xilinx: versal: Skip store/restore of GIC during CPU idle
plat: versal: Update API list in feature check
xilinx: versal: Do not pass ACPU0 always in set_wakeup_source()
- Merge changes from topic "secure_no_primary" into integration
* changes:
spm: provide number of vCPUs and VM size for first SP
spm: remove chosen node from SPMC manifests
spm: move OP-TEE SP manifest DTS to FVP platform
spm: update OP-TEE SP manifest with device-regions node
spm: remove device-memory node from SPMC manifests
- Merge "docs: Update the FIP generation process using SP images" into integration
- docs: Update the FIP generation process using SP images
Updated the documentation for the FIP generation process using
SP images.
Change-Id: I4df7f379f08f33adba6f5c82904291576972e106
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
- doc: Update list of supported FVP platforms
Updated the list of supported FVP platforms with support for RD-N2 FVP.
Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
- board/rdn2: add board support for rdn2 platform
Add the initial board support for RD-N2 platform.
Change-Id: I8325885bf248dd92191d6fc92a2da91c23118f8c
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
- plat/arm/sgi: adapt to changes in memory map
Upcoming RD platforms will have an updated memory map for the various
pheripherals on the system. So, for the newer platforms, handle the
memory mapping and other platform specific functionality separately
from the existing platforms.
Change-Id: Iab1355a4c8ea1f6db4f79fcdd6eed907903b6a18
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
- plat/arm/sgi: add platform id value for rdn2 platform
In preparation for adding the board support for RD-N2 platform, add
macros to define the platform id and the corresponding SCMI platform
info for the RD-N2 platform.
Change-Id: Ie764ae618732b39e316f7ed080421f5d79adab21
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
- plat/arm/sgi: platform definitions for upcoming platforms
Upcoming RD platforms have changes in the SOC address map from that
of the existing platforms. As a prepartory step to add support for the
upcoming platforms, create platform definitions for those platforms.
Change-Id: Ic5df9fed02c44e65ec260bbb5efc1b8dbd919a56
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
- plat/arm/sgi: refactor header file inclusions
Upcoming RD platforms have deviations in various definitions of
platform macros from that of the exisiting platforms. In preparation
for adding support for those upcoming RD platforms, refactor the
header file inclusion to allow newer platforms to use a different
set of platform macros.
Change-Id: Ic80283ddadafaa7f766f300652cb0d4e507efdb6
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
- plat/arm/sgi: refactor the inclusion of memory mapping
Upcoming RD platforms have a different memory map from those of the
existing platforms. So make the build of the existing mmap entries to be
usable only for existing platforms and let upcoming platforms define
a different set of mmap entries.
Change-Id: Id1ef0293efe8749c78a99237e78d32573c7233aa
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
- Merge "rcar_gen3: drivers: console: Treat log as device memory" into integration
- Merge changes from topic "zynqmp-bug-fixes" into integration
* changes:
zynqmp: pm: Update flags in common clk divisor node
zynqmp: pm_api_clock: Copy only the valid bytes
- rcar_gen3: drivers: console: Treat log as device memory
The BL31 log driver is registered before the xlat tables are initialized,
at that point the log memory is configured as device memory and can only
be accessed with up-to-32bit aligned accesses. Adjust the driver to do
just that.
The memset() call has to be replaced by a loop of 32bit writes to the log,
the memcpy() is trivial to replace with a single 32bit write of the entire
TLOG word. In the end, this even simplifies the code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie9152e782e67d93e7236069a294df812e2b873bf
[...]1 file changed
