| commit | 2382685ee729c5391d3952f61f065cf369927af2 | [log] [tgz] |
|---|---|---|
| author | Zhong,Fangjian <fangjian.zhong@intel.com> | Thu Aug 09 11:54:07 2018 +0800 |
| committer | Zhong,Fangjian <fangjian.zhong@intel.com> | Mon Sep 30 13:57:24 2019 +0800 |
| tree | b740d8cebd5f0ac0d88174ea23a01d8215b38267 | |
| parent | 1985661f617b22a089a307682b1a3848db2e11e0 [diff] |
[arch][x86] Add x86 cache operation functions Accroding to Intel Software Developer's Manual, in the L1 data cache and L2/L3 unified caches, the MESI (modified, exclusive, shared, invalid) cache protocol maintains consistency with caches of other processors. With MESI support, nothing to do when sync cache range. To peripheral, invalidate and clean cache range are used to ensure data shared between processor and peripheral always synced. Bug: 119111590 Change-Id: I66583bf9aa7da9644ea4bd4f1ce0565d3be14987
The LK embedded kernel. An SMP-aware kernel designed for small systems.
See https://github.com/littlekernel/lk for the latest version.
See https://github.com/littlekernel/lk/wiki for documentation.
This will get you a interactive prompt into LK which is running in qemu arm machine ‘virt’ emulation. type ‘help’ for commands.
note 1: for ubuntu: sudo apt-get install gcc-arm-none-eabi or fetch a prebuilt toolchain from http://newos.org/toolchains/arm-eabi-5.3.0-Linux-x86_64.tar.xz