tree b740d8cebd5f0ac0d88174ea23a01d8215b38267
parent 1985661f617b22a089a307682b1a3848db2e11e0
author Zhong,Fangjian <fangjian.zhong@intel.com> 1533786847 +0800
committer Zhong,Fangjian <fangjian.zhong@intel.com> 1569823044 +0800

[arch][x86] Add x86 cache operation functions

Accroding to Intel Software Developer's Manual, in the L1 data cache and
L2/L3 unified caches, the MESI (modified, exclusive, shared, invalid)
cache protocol maintains consistency with caches of other processors.

With MESI support, nothing to do when sync cache range.

To peripheral, invalidate and clean cache range are used to ensure
data shared between processor and peripheral always synced.

Bug: 119111590
Change-Id: I66583bf9aa7da9644ea4bd4f1ce0565d3be14987