| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc %s -mtriple=riscv64 -mattr=+v -riscv-enable-subreg-liveness -run-pass=riscv-init-undef -o - | FileCheck %s |
| |
| ... |
| --- |
| name: test_M4_sub_vrm1_0 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M4_sub_vrm1_0 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_0 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_1 |
| ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm4 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vr = IMPLICIT_DEF |
| %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_0 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm4 = IMPLICIT_DEF |
| early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5/* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M4_sub_vrm1_1 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M4_sub_vrm1_1 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_1 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_0 |
| ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm4 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vr = IMPLICIT_DEF |
| %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_1 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm4 = IMPLICIT_DEF |
| early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M4_sub_vrm1_2 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M4_sub_vrm1_2 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_2 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_3 |
| ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm4 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vr = IMPLICIT_DEF |
| %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_2 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm4 = IMPLICIT_DEF |
| early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M4_sub_vrm1_3 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M4_sub_vrm1_3 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_3 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_2 |
| ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm4 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vr = IMPLICIT_DEF |
| %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_3 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm4 = IMPLICIT_DEF |
| early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M4_sub_vrm2_0 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M4_sub_vrm2_0 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_0 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1 |
| ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm4 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vrm2 = IMPLICIT_DEF |
| %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm2_0 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm4 = IMPLICIT_DEF |
| early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M4_sub_vrm2_1 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M4_sub_vrm2_1 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_1 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0 |
| ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm4 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vrm2 = IMPLICIT_DEF |
| %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm2_1 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm4 = IMPLICIT_DEF |
| early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| |
| --- |
| name: test_M8_sub_vrm1_0 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm1_0 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_0 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 |
| ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_1 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vr = IMPLICIT_DEF |
| %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_0 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M8_sub_vrm1_1 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm1_1 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_1 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 |
| ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_0 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vr = IMPLICIT_DEF |
| %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_1 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M8_sub_vrm1_2 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm1_2 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_2 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 |
| ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_3 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vr = IMPLICIT_DEF |
| %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_2 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M8_sub_vrm1_3 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm1_3 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_3 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 |
| ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_2 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vr = IMPLICIT_DEF |
| %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_3 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M8_sub_vrm1_4 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm1_4 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_4 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_3 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 |
| ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_5 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vr = IMPLICIT_DEF |
| %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_4 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M8_sub_vrm1_5 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm1_5 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_5 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_3 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 |
| ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_4 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vr = IMPLICIT_DEF |
| %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_5 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M8_sub_vrm1_6 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm1_6 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_6 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_2 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 |
| ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_7 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vr = IMPLICIT_DEF |
| %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_6 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M8_sub_vrm1_7 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm1_7 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_7 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_2 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 |
| ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_6 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vr = IMPLICIT_DEF |
| %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_7 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M8_sub_vrm2_0 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm2_0 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_0 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vrm2 = IMPLICIT_DEF |
| %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_0 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M8_sub_vrm2_1 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm2_1 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_1 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vrm2 = IMPLICIT_DEF |
| %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_1 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M8_sub_vrm2_2 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm2_2 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_2 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_3 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vrm2 = IMPLICIT_DEF |
| %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_2 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M8_sub_vrm2_3 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm2_3 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_3 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 |
| ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_2 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vrm2 = IMPLICIT_DEF |
| %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_3 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M8_sub_vrm4_0 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm4_0 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M4_]], %subreg.sub_vrm4_0 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vrm4 = IMPLICIT_DEF |
| %5:vrm4 = PseudoVLE32_V_M4 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm4_0 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |
| |
| --- |
| name: test_M8_sub_vrm4_1 |
| body: | |
| bb.0.entry: |
| ; CHECK-LABEL: name: test_M8_sub_vrm4_1 |
| ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 |
| ; CHECK-NEXT: %pt:vrm4 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ |
| ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M4_]], %subreg.sub_vrm4_1 |
| ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 |
| ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 |
| ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 |
| ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 |
| ; CHECK-NEXT: $x10 = COPY [[COPY]] |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %1:vrm8 = IMPLICIT_DEF |
| %7:gpr = ADDI $x0, 8 |
| %pt:vrm4 = IMPLICIT_DEF |
| %5:vrm4 = PseudoVLE32_V_M4 %pt, killed %7:gpr, 0, 5, 0 |
| %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm4_1 |
| dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype |
| %pt2:vrm8 = IMPLICIT_DEF |
| early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype |
| %2:gpr = ADDI $x0, 0 |
| PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype |
| %3:gpr = COPY $x0 |
| $x10 = COPY %3 |
| PseudoRET implicit $x10 |
| |
| ... |