src/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV64D %s

---
name:            implicit_def_gpr
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    ; RV64D-LABEL: name: implicit_def_gpr
    ; RV64D: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
    ; RV64D-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[DEF]], [[DEF]]
    ; RV64D-NEXT: $x10 = COPY [[ADD]]
    %0:gprb(s64) = G_IMPLICIT_DEF
    %1:gprb(s64) = G_ADD %0, %0
    $x10 = COPY %1(s64)
...
---
name:            implicit_def_copy_gpr
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    ; RV64D-LABEL: name: implicit_def_copy_gpr
    ; RV64D: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
    ; RV64D-NEXT: $x10 = COPY [[DEF]]
    %0:gprb(s64) = G_IMPLICIT_DEF
    %1:gprb(s64) = COPY %0(s64)
    $x10 = COPY %1(s64)
...

---
name:            implicit_def_fpr
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    ; RV64D-LABEL: name: implicit_def_fpr
    ; RV64D: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF
    ; RV64D-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[DEF]], [[DEF]], 7
    ; RV64D-NEXT: $f10_d = COPY [[FADD_D]]
    %0:fprb(s64) = G_IMPLICIT_DEF
    %1:fprb(s64) = G_FADD %0, %0
    $f10_d = COPY %1(s64)
...
---
name:            implicit_def_copy_fpr
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    ; RV64D-LABEL: name: implicit_def_copy_fpr
    ; RV64D: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF
    ; RV64D-NEXT: $f10_d = COPY [[DEF]]
    %0:fprb(s64) = G_IMPLICIT_DEF
    %1:fprb(s64) = COPY %0(s64)
    $f10_d = COPY %1(s64)
...