| # RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=GCN |
| # RUN: llc -mtriple=amdgcn -mcpu=gfx940 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=GCN |
| |
| --- |
| # GCN-LABEL: name: dpp64_old_impdef |
| # GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp %1, 0, %0, 337, 15, 15, 1, implicit $mode, implicit $exec |
| --- |
| name: dpp64_old_impdef |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| %0:vreg_64_align2 = IMPLICIT_DEF |
| %1:vreg_64_align2 = IMPLICIT_DEF |
| %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO %1, %0, 337, 15, 15, 1, implicit $exec |
| %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec |
| ... |
| |
| # GCN-LABEL: name: dpp64_old_undef |
| # GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp undef %1:vreg_64_align2, 0, undef %2:vreg_64_align2, 337, 15, 15, 1, implicit $mode, implicit $exec |
| --- |
| name: dpp64_old_undef |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64_align2, undef %0:vreg_64_align2, 337, 15, 15, 1, implicit $exec |
| %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec |
| ... |
| |
| # GCN-LABEL: name: dpp64_old_is_0 |
| # GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp %4, 0, undef %2:vreg_64_align2, 337, 15, 15, 1, implicit $mode, implicit $exec |
| name: dpp64_old_is_0 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| %1:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec |
| %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1, undef %0:vreg_64_align2, 337, 15, 15, 1, implicit $exec |
| %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec |
| ... |
| |
| # DPP64 does not support all control values and must be split to become legal |
| # GCN-LABEL: name: dpp64_illegal_ctrl |
| # GCN: %4:vgpr_32 = V_MOV_B32_dpp undef %1.sub0:vreg_64_align2, undef %2.sub0:vreg_64_align2, 1, 15, 15, 1, implicit $exec |
| # GCN: %5:vgpr_32 = V_MOV_B32_dpp undef %1.sub1:vreg_64_align2, undef %2.sub1:vreg_64_align2, 1, 15, 15, 1, implicit $exec |
| # GCN: %0:vreg_64_align2 = REG_SEQUENCE %4, %subreg.sub0, %5, %subreg.sub1 |
| # GCN: %3:vreg_64_align2 = V_CEIL_F64_e32 %0, implicit $mode, implicit $exec |
| name: dpp64_illegal_ctrl |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64_align2, undef %0:vreg_64_align2, 1, 15, 15, 1, implicit $exec |
| %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec |
| ... |