[ARM]Decoding MSR with unpredictable destination register causes an assert
This patch handling:
Enable parsing of raw encodings of system registers .
Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing.
Disassemble msr/mrs with unpredictable sysregs as SoftFail.
Fix regression due to SoftFailing some encodings.
Patch by Chris Ryder
Differential revision:https://reviews.llvm.org/D43374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326803 91177308-0d34-0410-b5e6-96231b3b80d8
5 files changed
