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  1. 1d739ff [x86] Switch EFLAGS copy lowering to use reg-reg form of testing for by Chandler Carruth · 5 weeks ago master
  2. 395a261 [x86] Fix PR37100 by teaching the EFLAGS copy lowering to rewrite uses by Chandler Carruth · 5 weeks ago
  3. 4798aaa [X86] In X86FlagsCopyLowering, when rewriting a memory setcc we need to emit an explicit MOV8mr instruction. by Craig Topper · 6 weeks ago
  4. de88e07 [FastISel] Disable local value sinking by default by Reid Kleckner · 6 weeks ago
  5. b44908e [x86] Model the direction flag (DF) separately from the rest of EFLAGS. by Chandler Carruth · 6 weeks ago
  6. de96739 Introduce a pass to begin more systematically fixing PR36028 and similar issues. by Chandler Carruth · 6 weeks ago
  7. 6ffc243 Align stubs for external and common global variables to pointer size. by Rafael Espindola · 7 weeks ago
  8. ef38d15 [x86] Expose more of the condition conversion routines in the public API by Chandler Carruth · 7 weeks ago
  9. e8594d5 [MemorySSA] Be less aggressive with @llvm.lifetime.start by Pirama Arumuga Nainar · 6 weeks ago
  10. 111055a Merge commit 95561668f063 by Pirama Arumuga Nainar · 6 weeks ago llvm-svn.328901 llvm-svn.328903
  11. 0bcee32 Revert "[GlobalsAA] Fix a pretty terrible bug that has been in GlobalsAA for" by Pirama Arumuga Nainar · 6 weeks ago
  12. 9556166 [WebAssembly] Register wasm passes with the PassRegistry by Jacob Gravelle · 7 weeks ago
  13. f9ed632 [Hexagon] Fix testcase by Krzysztof Parzyszek · 7 weeks ago
  14. f3e8da1 [Hexagon] Reduce excessive indentation in .s output by Krzysztof Parzyszek · 7 weeks ago
  15. 5a53d2f [Hexagon] Avoid creating invalid offsets in packetizer by Krzysztof Parzyszek · 7 weeks ago
  16. f4abfed [X86][BtVer2] Fixed the number of micro opcodes for AVX vector converts and by Andrea Di Biagio · 7 weeks ago
  17. 9541cc2 DataFlowSanitizer: wrappers of functions with local linkage should have the same linkage as the function being wrapped by Peter Collingbourne · 7 weeks ago
  18. eed988e [MIR] Adding support for Named Virtual Registers in MIR. by Puyan Lotfi · 7 weeks ago
  19. 292151b [X86][BtVer2] Fix the number of uOps for horizontal operations. by Andrea Di Biagio · 7 weeks ago
  20. 788c75b [NVPTX] Enable StructuredCFG for NVPTX by Tim Shen · 7 weeks ago