Merge tag 'jdk-11.0.13-ga' Added tag jdk-11.0.13-ga for changeset 71f2c751 Bug: 205944740 Test: forrest Change-Id: I0dad66f22136a2be92cccbae3c5877625ad1e8d1
diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..7745062 --- /dev/null +++ b/.gitattributes
@@ -0,0 +1 @@ +* -text
diff --git a/.github/workflows/submit.yml b/.github/workflows/submit.yml new file mode 100644 index 0000000..5c5bbed --- /dev/null +++ b/.github/workflows/submit.yml
@@ -0,0 +1,1513 @@ +name: Pre-submit tests + +on: + push: + branches-ignore: + - master + - pr/* + workflow_dispatch: + inputs: + platforms: + description: "Platform(s) to execute on" + required: true + default: "Linux additional (hotspot only), Linux x64, Linux x86, Windows x64, macOS x64" + +jobs: + prerequisites: + name: Prerequisites + runs-on: "ubuntu-20.04" + outputs: + should_run: ${{ steps.check_submit.outputs.should_run }} + bundle_id: ${{ steps.check_bundle_id.outputs.bundle_id }} + platform_linux_additional: ${{ steps.check_platforms.outputs.platform_linux_additional }} + platform_linux_x64: ${{ steps.check_platforms.outputs.platform_linux_x64 }} + platform_linux_x86: ${{ steps.check_platforms.outputs.platform_linux_x86 }} + platform_windows_x64: ${{ steps.check_platforms.outputs.platform_windows_x64 }} + platform_macos_x64: ${{ steps.check_platforms.outputs.platform_macos_x64 }} + dependencies: ${{ steps.check_deps.outputs.dependencies }} + + steps: + - name: Check if submit tests should actually run depending on secrets and manual triggering + id: check_submit + run: echo "::set-output name=should_run::${{ github.event.inputs.platforms != '' || (!secrets.JDK_SUBMIT_FILTER || startsWith(github.ref, 'refs/heads/submit/')) }}" + + - name: Check which platforms should be included + id: check_platforms + run: | + echo "::set-output name=platform_linux_additional::${{ contains(github.event.inputs.platforms, 'linux additional (hotspot only)') || (github.event.inputs.platforms == '' && (secrets.JDK_SUBMIT_PLATFORMS == '' || contains(secrets.JDK_SUBMIT_PLATFORMS, 'linux additional (hotspot only)'))) }}" + echo "::set-output name=platform_linux_x64::${{ contains(github.event.inputs.platforms, 'linux x64') || (github.event.inputs.platforms == '' && (secrets.JDK_SUBMIT_PLATFORMS == '' || contains(secrets.JDK_SUBMIT_PLATFORMS, 'linux x64'))) }}" + echo "::set-output name=platform_linux_x86::${{ contains(github.event.inputs.platforms, 'linux x86') || (github.event.inputs.platforms == '' && (secrets.JDK_SUBMIT_PLATFORMS == '' || contains(secrets.JDK_SUBMIT_PLATFORMS, 'linux x86'))) }}" + echo "::set-output name=platform_windows_x64::${{ contains(github.event.inputs.platforms, 'windows x64') || (github.event.inputs.platforms == '' && (secrets.JDK_SUBMIT_PLATFORMS == '' || contains(secrets.JDK_SUBMIT_PLATFORMS, 'windows x64'))) }}" + echo "::set-output name=platform_macos_x64::${{ contains(github.event.inputs.platforms, 'macos x64') || (github.event.inputs.platforms == '' && (secrets.JDK_SUBMIT_PLATFORMS == '' || contains(secrets.JDK_SUBMIT_PLATFORMS, 'macos x64'))) }}" + if: steps.check_submit.outputs.should_run != 'false' + + - name: Determine unique bundle identifier + id: check_bundle_id + run: echo "::set-output name=bundle_id::${GITHUB_ACTOR}_${GITHUB_SHA:0:8}" + if: steps.check_submit.outputs.should_run != 'false' + + - name: Checkout the source + uses: actions/checkout@v2 + with: + path: jdk + if: steps.check_submit.outputs.should_run != 'false' + + - name: Determine versions and locations to be used for dependencies + id: check_deps + run: "echo ::set-output name=dependencies::`cat make/autoconf/version-numbers make/conf/test-dependencies | sed -e '1i {' -e 's/#.*//g' -e 's/\"//g' -e 's/\\(.*\\)=\\(.*\\)/\"\\1\": \"\\2\",/g' -e '$s/,\\s\\{0,\\}$/\\}/'`" + working-directory: jdk + if: steps.check_submit.outputs.should_run != 'false' + + - name: Print extracted dependencies to the log + run: "echo '${{ steps.check_deps.outputs.dependencies }}'" + if: steps.check_submit.outputs.should_run != 'false' + + - name: Determine the jtreg ref to checkout + run: "echo JTREG_REF=jtreg${{ fromJson(steps.check_deps.outputs.dependencies).JTREG_VERSION }}-${{ fromJson(steps.check_deps.outputs.dependencies).JTREG_BUILD }} >> $GITHUB_ENV" + if: steps.check_submit.outputs.should_run != 'false' + + - name: Determine the jtreg version to build + run: echo "BUILD_VERSION=${{ fromJson(steps.check_deps.outputs.dependencies).JTREG_VERSION }}" >> $GITHUB_ENV + if: steps.check_submit.outputs.should_run != 'false' + + - name: Determine the jtreg build number to build + run: echo "BUILD_NUMBER=${{ fromJson(steps.check_deps.outputs.dependencies).JTREG_BUILD }}" >> $GITHUB_ENV + if: steps.check_submit.outputs.should_run != 'false' + + - name: Check if a jtreg image is present in the cache + id: jtreg + uses: actions/cache@v2 + with: + path: ~/jtreg/ + key: jtreg-${{ env.JTREG_REF }}-v1 + if: steps.check_submit.outputs.should_run != 'false' + + - name: Checkout the jtreg source + uses: actions/checkout@v2 + with: + repository: "openjdk/jtreg" + ref: ${{ env.JTREG_REF }} + path: jtreg + if: steps.check_submit.outputs.should_run != 'false' && steps.jtreg.outputs.cache-hit != 'true' + + - name: Build jtreg + run: bash make/build-all.sh ${JAVA_HOME_8_X64} + working-directory: jtreg + if: steps.check_submit.outputs.should_run != 'false' && steps.jtreg.outputs.cache-hit != 'true' + + - name: Move jtreg image to destination folder + run: mv build/images/jtreg ~/ + working-directory: jtreg + if: steps.check_submit.outputs.should_run != 'false' && steps.jtreg.outputs.cache-hit != 'true' + + - name: Store jtreg for use by later steps + uses: actions/upload-artifact@v2 + with: + name: transient_jtreg_${{ steps.check_bundle_id.outputs.bundle_id }} + path: ~/jtreg/ + if: steps.check_submit.outputs.should_run != 'false' + + linux_x64_build: + name: Linux x64 + runs-on: "ubuntu-20.04" + needs: prerequisites + if: needs.prerequisites.outputs.should_run != 'false' && (needs.prerequisites.outputs.platform_linux_x64 != 'false' || needs.prerequisites.outputs.platform_linux_additional == 'true') + + strategy: + fail-fast: false + matrix: + flavor: + - build release + - build debug + include: + - flavor: build debug + flags: --enable-debug + artifact: -debug + + env: + JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_FEATURE }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_INTERIM }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_UPDATE }}" + BOOT_JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).BOOT_JDK_VERSION }}" + BOOT_JDK_FILENAME: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_FILENAME }}" + BOOT_JDK_URL: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_URL }}" + BOOT_JDK_SHA256: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_SHA256 }}" + + steps: + - name: Checkout the source + uses: actions/checkout@v2 + with: + path: jdk + + - name: Restore boot JDK from cache + id: bootjdk + uses: actions/cache@v2 + with: + path: ~/bootjdk/${{ env.BOOT_JDK_VERSION }} + key: bootjdk-${{ runner.os }}-${{ env.BOOT_JDK_VERSION }}-${{ env.BOOT_JDK_SHA256 }}-v1 + + - name: Download boot JDK + run: | + mkdir -p "${HOME}/bootjdk/${BOOT_JDK_VERSION}" + wget -O "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" "${BOOT_JDK_URL}" + echo "${BOOT_JDK_SHA256} ${HOME}/bootjdk/${BOOT_JDK_FILENAME}" | sha256sum -c >/dev/null - + tar -xf "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" -C "${HOME}/bootjdk/${BOOT_JDK_VERSION}" + mv "${HOME}/bootjdk/${BOOT_JDK_VERSION}/"*/* "${HOME}/bootjdk/${BOOT_JDK_VERSION}/" + if: steps.bootjdk.outputs.cache-hit != 'true' + + - name: Restore jtreg artifact + id: jtreg_restore + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + continue-on-error: true + + - name: Restore jtreg artifact (retry) + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + if: steps.jtreg_restore.outcome == 'failure' + + - name: Fix jtreg permissions + run: chmod -R a+rx ${HOME}/jtreg/ + + - name: Install dependencies + run: | + sudo apt-get update + sudo apt-get install gcc-9=9.3.0-17ubuntu1~20.04 g++-9=9.3.0-17ubuntu1~20.04 libxrandr-dev libxtst-dev libcups2-dev libasound2-dev + sudo update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-9 100 --slave /usr/bin/g++ g++ /usr/bin/g++-9 + + - name: Configure + run: > + bash configure + --with-conf-name=linux-x64 + ${{ matrix.flags }} + --with-version-opt=${GITHUB_ACTOR}-${GITHUB_SHA} + --with-version-build=0 + --with-boot-jdk=${HOME}/bootjdk/${BOOT_JDK_VERSION} + --with-jtreg=${HOME}/jtreg + --with-default-make-target="product-bundles test-bundles" + --with-zlib=system + --with-jvm-features=shenandoahgc + --enable-jtreg-failure-handler + working-directory: jdk + + - name: Build + run: make CONF_NAME=linux-x64 + working-directory: jdk + + - name: Persist test bundles + uses: actions/upload-artifact@v2 + with: + name: transient_jdk-linux-x64${{ matrix.artifact }}_${{ needs.prerequisites.outputs.bundle_id }} + path: | + jdk/build/linux-x64/bundles/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin${{ matrix.artifact }}.tar.gz + jdk/build/linux-x64/bundles/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin-tests${{ matrix.artifact }}.tar.gz + + linux_x64_test: + name: Linux x64 + runs-on: "ubuntu-20.04" + needs: + - prerequisites + - linux_x64_build + + strategy: + fail-fast: false + matrix: + test: + - jdk/tier1 part 1 + - jdk/tier1 part 2 + - jdk/tier1 part 3 + - langtools/tier1 + - hs/tier1 common + - hs/tier1 compiler + - hs/tier1 gc + - hs/tier1 runtime + - hs/tier1 serviceability + include: + - test: jdk/tier1 part 1 + suites: test/jdk/:tier1_part1 + - test: jdk/tier1 part 2 + suites: test/jdk/:tier1_part2 + - test: jdk/tier1 part 3 + suites: test/jdk/:tier1_part3 + - test: langtools/tier1 + suites: test/langtools/:tier1 + - test: hs/tier1 common + suites: test/hotspot/jtreg/:tier1_common + artifact: -debug + - test: hs/tier1 compiler + suites: test/hotspot/jtreg/:tier1_compiler + artifact: -debug + - test: hs/tier1 gc + suites: test/hotspot/jtreg/:tier1_gc + artifact: -debug + - test: hs/tier1 runtime + suites: test/hotspot/jtreg/:tier1_runtime + artifact: -debug + - test: hs/tier1 serviceability + suites: test/hotspot/jtreg/:tier1_serviceability + artifact: -debug + + env: + JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_FEATURE }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_INTERIM }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_UPDATE }}" + BOOT_JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).BOOT_JDK_VERSION }}" + BOOT_JDK_FILENAME: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_FILENAME }}" + BOOT_JDK_URL: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_URL }}" + BOOT_JDK_SHA256: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_SHA256 }}" + + steps: + - name: Checkout the source + uses: actions/checkout@v2 + + - name: Restore boot JDK from cache + id: bootjdk + uses: actions/cache@v2 + with: + path: ~/bootjdk/${{ env.BOOT_JDK_VERSION }} + key: bootjdk-${{ runner.os }}-${{ env.BOOT_JDK_VERSION }}-${{ env.BOOT_JDK_SHA256 }}-v1 + + - name: Download boot JDK + run: | + mkdir -p "${HOME}/bootjdk/${BOOT_JDK_VERSION}" + wget -O "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" "${BOOT_JDK_URL}" + echo "${BOOT_JDK_SHA256} ${HOME}/bootjdk/${BOOT_JDK_FILENAME}" | sha256sum -c >/dev/null - + tar -xf "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" -C "${HOME}/bootjdk/${BOOT_JDK_VERSION}" + mv "${HOME}/bootjdk/${BOOT_JDK_VERSION}/"*/* "${HOME}/bootjdk/${BOOT_JDK_VERSION}/" + if: steps.bootjdk.outputs.cache-hit != 'true' + + - name: Restore jtreg artifact + id: jtreg_restore + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + continue-on-error: true + + - name: Restore jtreg artifact (retry) + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + if: steps.jtreg_restore.outcome == 'failure' + + - name: Restore build artifacts + id: build_restore + uses: actions/download-artifact@v2 + with: + name: transient_jdk-linux-x64${{ matrix.artifact }}_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jdk-linux-x64${{ matrix.artifact }} + continue-on-error: true + + - name: Restore build artifacts (retry) + uses: actions/download-artifact@v2 + with: + name: transient_jdk-linux-x64${{ matrix.artifact }}_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jdk-linux-x64${{ matrix.artifact }} + if: steps.build_restore.outcome == 'failure' + + - name: Unpack jdk + run: | + mkdir -p "${HOME}/jdk-linux-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin${{ matrix.artifact }}" + tar -xf "${HOME}/jdk-linux-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin${{ matrix.artifact }}.tar.gz" -C "${HOME}/jdk-linux-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin${{ matrix.artifact }}" + + - name: Unpack tests + run: | + mkdir -p "${HOME}/jdk-linux-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin-tests${{ matrix.artifact }}" + tar -xf "${HOME}/jdk-linux-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin-tests${{ matrix.artifact }}.tar.gz" -C "${HOME}/jdk-linux-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin-tests${{ matrix.artifact }}" + + - name: Find root of jdk image dir + run: | + imageroot=`find ${HOME}/jdk-linux-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin${{ matrix.artifact }} -name release -type f` + echo "imageroot=`dirname ${imageroot}`" >> $GITHUB_ENV + + - name: Run tests + run: > + JDK_IMAGE_DIR=${{ env.imageroot }} + TEST_IMAGE_DIR=${HOME}/jdk-linux-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin-tests${{ matrix.artifact }} + BOOT_JDK=${HOME}/bootjdk/${BOOT_JDK_VERSION} + JT_HOME=${HOME}/jtreg + make run-test-prebuilt + CONF_NAME=run-test-prebuilt + LOG_CMDLINES=true + JTREG_VERBOSE=fail,error,time + TEST="${{ matrix.suites }}" + TEST_OPTS_JAVA_OPTIONS= + JTREG_KEYWORDS="!headful" + JTREG="JAVA_OPTIONS=-XX:-CreateCoredumpOnCrash" + + - name: Check that all tests executed successfully + if: always() + run: > + if ! grep --include=test-summary.txt -lqr build/*/test-results -e "TEST SUCCESS" ; then + cat build/*/test-results/*/text/newfailures.txt ; + exit 1 ; + fi + + - name: Create suitable test log artifact name + if: always() + run: echo "logsuffix=`echo ${{ matrix.test }} | sed -e 's!/!_!'g -e 's! !_!'g`" >> $GITHUB_ENV + + - name: Package test results + if: always() + working-directory: build/run-test-prebuilt/test-results/ + run: > + zip -r9 + "$HOME/linux-x64${{ matrix.artifact }}_testresults_${{ env.logsuffix }}.zip" + . + continue-on-error: true + + - name: Package test support + if: always() + working-directory: build/run-test-prebuilt/test-support/ + run: > + zip -r9 + "$HOME/linux-x64${{ matrix.artifact }}_testsupport_${{ env.logsuffix }}.zip" + . + -i *.jtr + -i */hs_err*.log + -i */replay*.log + continue-on-error: true + + - name: Persist test results + if: always() + uses: actions/upload-artifact@v2 + with: + path: ~/linux-x64${{ matrix.artifact }}_testresults_${{ env.logsuffix }}.zip + continue-on-error: true + + - name: Persist test outputs + if: always() + uses: actions/upload-artifact@v2 + with: + path: ~/linux-x64${{ matrix.artifact }}_testsupport_${{ env.logsuffix }}.zip + continue-on-error: true + + linux_additional_build: + name: Linux additional + runs-on: "ubuntu-20.04" + needs: + - prerequisites + - linux_x64_build + if: needs.prerequisites.outputs.should_run != 'false' && needs.prerequisites.outputs.platform_linux_additional != 'false' + + strategy: + fail-fast: false + matrix: + flavor: + - hs x64 build only + - hs x64 zero build only + - hs x64 minimal build only + - hs x64 optimized build only + - hs aarch64 build only + - hs arm build only + - hs s390x build only + - hs ppc64le build only + include: + - flavor: hs x64 build only + flags: --enable-debug --disable-precompiled-headers + - flavor: hs x64 shenandoah build only + flags: --enable-debug --disable-precompiled-headers --with-jvm-features=shenandoahgc + - flavor: hs x64 zero build only + flags: --enable-debug --disable-precompiled-headers --with-jvm-variants=zero + - flavor: hs x64 minimal build only + flags: --enable-debug --disable-precompiled-headers --with-jvm-variants=minimal + - flavor: hs x64 optimized build only + flags: --with-debug-level=optimized --disable-precompiled-headers + - flavor: hs aarch64 build only + flags: --enable-debug --disable-precompiled-headers + debian-arch: arm64 + gnu-arch: aarch64 + - flavor: hs aarch64 shenandoah build only + flags: --enable-debug --disable-precompiled-headers --with-jvm-features=shenandoahgc + debian-arch: arm64 + gnu-arch: aarch64 + - flavor: hs arm build only + flags: --enable-debug --disable-precompiled-headers + debian-arch: armhf + gnu-arch: arm + gnu-flavor: eabihf + - flavor: hs s390x build only + flags: --enable-debug --disable-precompiled-headers + debian-arch: s390x + gnu-arch: s390x + - flavor: hs ppc64le build only + flags: --enable-debug --disable-precompiled-headers + debian-arch: ppc64el + gnu-arch: powerpc64le + + env: + JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_FEATURE }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_INTERIM }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_UPDATE }}" + BOOT_JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).BOOT_JDK_VERSION }}" + BOOT_JDK_FILENAME: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_FILENAME }}" + BOOT_JDK_URL: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_URL }}" + BOOT_JDK_SHA256: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_SHA256 }}" + + steps: + - name: Checkout the source + uses: actions/checkout@v2 + with: + path: jdk + + - name: Restore boot JDK from cache + id: bootjdk + uses: actions/cache@v2 + with: + path: ~/bootjdk/${{ env.BOOT_JDK_VERSION }} + key: bootjdk-${{ runner.os }}-${{ env.BOOT_JDK_VERSION }}-${{ env.BOOT_JDK_SHA256 }}-v1 + + - name: Download boot JDK + run: | + mkdir -p "${HOME}/bootjdk/${BOOT_JDK_VERSION}" + wget -O "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" "${BOOT_JDK_URL}" + echo "${BOOT_JDK_SHA256} ${HOME}/bootjdk/${BOOT_JDK_FILENAME}" | sha256sum -c >/dev/null - + tar -xf "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" -C "${HOME}/bootjdk/${BOOT_JDK_VERSION}" + mv "${HOME}/bootjdk/${BOOT_JDK_VERSION}/"*/* "${HOME}/bootjdk/${BOOT_JDK_VERSION}/" + if: steps.bootjdk.outputs.cache-hit != 'true' + + - name: Restore build JDK + id: build_restore + uses: actions/download-artifact@v2 + with: + name: transient_jdk-linux-x64_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jdk-linux-x64 + continue-on-error: true + + - name: Restore build JDK (retry) + uses: actions/download-artifact@v2 + with: + name: transient_jdk-linux-x64_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jdk-linux-x64 + if: steps.build_restore.outcome == 'failure' + + - name: Unpack build JDK + run: | + mkdir -p "${HOME}/jdk-linux-x64/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin" + tar -xf "${HOME}/jdk-linux-x64/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin.tar.gz" -C "${HOME}/jdk-linux-x64/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin" + + - name: Find root of build JDK image dir + run: | + build_jdk_root=`find ${HOME}/jdk-linux-x64/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x64_bin -name release -type f` + echo "build_jdk_root=`dirname ${build_jdk_root}`" >> $GITHUB_ENV + + - name: Update apt + run: sudo apt-get update + + - name: Install native host dependencies + run: | + sudo apt-get install gcc-9=9.3.0-17ubuntu1~20.04 g++-9=9.3.0-17ubuntu1~20.04 libxrandr-dev libxtst-dev libcups2-dev libasound2-dev + sudo update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-9 100 --slave /usr/bin/g++ g++ /usr/bin/g++-9 + if: matrix.debian-arch == '' + + - name: Install cross-compilation host dependencies + run: sudo apt-get install gcc-9-${{ matrix.gnu-arch }}-linux-gnu${{ matrix.gnu-flavor}}=9.3.0-17ubuntu1~20.04cross2 g++-9-${{ matrix.gnu-arch }}-linux-gnu${{ matrix.gnu-flavor}}=9.3.0-17ubuntu1~20.04cross2 + if: matrix.debian-arch != '' + + - name: Cache sysroot + id: cache-sysroot + uses: actions/cache@v2 + with: + path: ~/sysroot-${{ matrix.debian-arch }}/ + key: sysroot-${{ matrix.debian-arch }}-${{ hashFiles('jdk/.github/workflows/submit.yml') }} + if: matrix.debian-arch != '' + + - name: Install sysroot host dependencies + run: sudo apt-get install debootstrap qemu-user-static + if: matrix.debian-arch != '' && steps.cache-sysroot.outputs.cache-hit != 'true' + + - name: Create sysroot + run: > + sudo qemu-debootstrap + --arch=${{ matrix.debian-arch }} + --verbose + --include=fakeroot,symlinks,build-essential,libx11-dev,libxext-dev,libxrender-dev,libxrandr-dev,libxtst-dev,libxt-dev,libcups2-dev,libfontconfig1-dev,libasound2-dev,libfreetype6-dev,libpng-dev + --resolve-deps + buster + ~/sysroot-${{ matrix.debian-arch }} + http://httpredir.debian.org/debian/ + if: matrix.debian-arch != '' && steps.cache-sysroot.outputs.cache-hit != 'true' + + - name: Prepare sysroot for caching + run: | + sudo chroot ~/sysroot-${{ matrix.debian-arch }} symlinks -cr . + sudo chown ${USER} -R ~/sysroot-${{ matrix.debian-arch }} + rm -rf ~/sysroot-${{ matrix.debian-arch }}/{dev,proc,run,sys} + if: matrix.debian-arch != '' && steps.cache-sysroot.outputs.cache-hit != 'true' + + - name: Configure cross compiler + run: | + echo "CC=${{ matrix.gnu-arch }}-linux-gnu${{ matrix.gnu-flavor}}-gcc-9" >> $GITHUB_ENV + echo "CXX=${{ matrix.gnu-arch }}-linux-gnu${{ matrix.gnu-flavor}}-g++-9" >> $GITHUB_ENV + if: matrix.debian-arch != '' + + - name: Configure cross specific flags + run: > + echo "cross_flags= + --openjdk-target=${{ matrix.gnu-arch }}-linux-gnu${{ matrix.gnu-flavor}} + --with-sysroot=${HOME}/sysroot-${{ matrix.debian-arch }}/ + " >> $GITHUB_ENV + if: matrix.debian-arch != '' + + - name: Configure + run: > + bash configure + --with-conf-name=linux-${{ matrix.gnu-arch }}-hotspot + ${{ matrix.flags }} + ${{ env.cross_flags }} + --with-version-opt=${GITHUB_ACTOR}-${GITHUB_SHA} + --with-version-build=0 + --with-boot-jdk=${HOME}/bootjdk/${BOOT_JDK_VERSION} + --with-build-jdk=${{ env.build_jdk_root }} + --with-default-make-target="hotspot" + --with-zlib=system + working-directory: jdk + + - name: Build + run: make CONF_NAME=linux-${{ matrix.gnu-arch }}-hotspot + working-directory: jdk + + linux_x86_build: + name: Linux x86 + runs-on: "ubuntu-20.04" + needs: prerequisites + if: needs.prerequisites.outputs.should_run != 'false' && needs.prerequisites.outputs.platform_linux_x86 != 'false' + + strategy: + fail-fast: false + matrix: + flavor: + - build release + - build debug + include: + - flavor: build debug + flags: --enable-debug + artifact: -debug + + # Reduced 32-bit build uses the same boot JDK as 64-bit build + env: + JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_FEATURE }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_INTERIM }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_UPDATE }}" + BOOT_JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).BOOT_JDK_VERSION }}" + BOOT_JDK_FILENAME: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_FILENAME }}" + BOOT_JDK_URL: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_URL }}" + BOOT_JDK_SHA256: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_SHA256 }}" + + steps: + - name: Checkout the source + uses: actions/checkout@v2 + with: + path: jdk + + - name: Restore boot JDK from cache + id: bootjdk + uses: actions/cache@v2 + with: + path: ~/bootjdk/${{ env.BOOT_JDK_VERSION }} + key: bootjdk-${{ runner.os }}-${{ env.BOOT_JDK_VERSION }}-${{ env.BOOT_JDK_SHA256 }}-v1 + + - name: Download boot JDK + run: | + mkdir -p "${HOME}/bootjdk/${BOOT_JDK_VERSION}" + wget -O "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" "${BOOT_JDK_URL}" + echo "${BOOT_JDK_SHA256} ${HOME}/bootjdk/${BOOT_JDK_FILENAME}" | sha256sum -c >/dev/null - + tar -xf "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" -C "${HOME}/bootjdk/${BOOT_JDK_VERSION}" + mv "${HOME}/bootjdk/${BOOT_JDK_VERSION}/"*/* "${HOME}/bootjdk/${BOOT_JDK_VERSION}/" + if: steps.bootjdk.outputs.cache-hit != 'true' + + - name: Restore jtreg artifact + id: jtreg_restore + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + continue-on-error: true + + - name: Restore jtreg artifact (retry) + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + if: steps.jtreg_restore.outcome == 'failure' + + - name: Fix jtreg permissions + run: chmod -R a+rx ${HOME}/jtreg/ + + # Roll in the multilib environment and its dependencies. + # Some multilib libraries do not have proper inter-dependencies, so we have to + # install their dependencies manually. Additionally, upgrading apt solves + # the libc6 installation bugs until base image catches up, see JDK-8260460. + - name: Install dependencies + run: | + sudo dpkg --add-architecture i386 + sudo apt-get update + sudo apt-get install --only-upgrade apt + sudo apt-get install gcc-9-multilib g++-9-multilib libfreetype6-dev:i386 libxrandr-dev:i386 libxtst-dev:i386 libtiff-dev:i386 libcupsimage2-dev:i386 libcups2-dev:i386 libasound2-dev:i386 + sudo update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-9 100 --slave /usr/bin/g++ g++ /usr/bin/g++-9 + + - name: Configure + run: > + bash configure + --with-conf-name=linux-x86 + --with-target-bits=32 + ${{ matrix.flags }} + --with-version-opt=${GITHUB_ACTOR}-${GITHUB_SHA} + --with-version-build=0 + --with-boot-jdk=${HOME}/bootjdk/${BOOT_JDK_VERSION} + --with-jtreg=${HOME}/jtreg + --with-default-make-target="product-bundles test-bundles" + --with-zlib=system + --with-jvm-features=shenandoahgc + --enable-jtreg-failure-handler + working-directory: jdk + + - name: Build + run: make CONF_NAME=linux-x86 + working-directory: jdk + + - name: Persist test bundles + uses: actions/upload-artifact@v2 + with: + name: transient_jdk-linux-x86${{ matrix.artifact }}_${{ needs.prerequisites.outputs.bundle_id }} + path: | + jdk/build/linux-x86/bundles/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x86_bin${{ matrix.artifact }}.tar.gz + jdk/build/linux-x86/bundles/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x86_bin-tests${{ matrix.artifact }}.tar.gz + + linux_x86_test: + name: Linux x86 + runs-on: "ubuntu-20.04" + needs: + - prerequisites + - linux_x86_build + + strategy: + fail-fast: false + matrix: + test: + - jdk/tier1 part 1 + - jdk/tier1 part 2 + - jdk/tier1 part 3 + - langtools/tier1 + - hs/tier1 common + - hs/tier1 compiler + - hs/tier1 gc + - hs/tier1 runtime + - hs/tier1 serviceability + include: + - test: jdk/tier1 part 1 + suites: test/jdk/:tier1_part1 + - test: jdk/tier1 part 2 + suites: test/jdk/:tier1_part2 + - test: jdk/tier1 part 3 + suites: test/jdk/:tier1_part3 + - test: langtools/tier1 + suites: test/langtools/:tier1 + - test: hs/tier1 common + suites: test/hotspot/jtreg/:tier1_common + artifact: -debug + - test: hs/tier1 compiler + suites: test/hotspot/jtreg/:tier1_compiler + artifact: -debug + - test: hs/tier1 gc + suites: test/hotspot/jtreg/:tier1_gc + artifact: -debug + - test: hs/tier1 runtime + suites: test/hotspot/jtreg/:tier1_runtime + artifact: -debug + - test: hs/tier1 serviceability + suites: test/hotspot/jtreg/:tier1_serviceability + artifact: -debug + + # Reduced 32-bit build uses the same boot JDK as 64-bit build + env: + JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_FEATURE }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_INTERIM }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_UPDATE }}" + BOOT_JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).BOOT_JDK_VERSION }}" + BOOT_JDK_FILENAME: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_FILENAME }}" + BOOT_JDK_URL: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_URL }}" + BOOT_JDK_SHA256: "${{ fromJson(needs.prerequisites.outputs.dependencies).LINUX_X64_BOOT_JDK_SHA256 }}" + + steps: + - name: Checkout the source + uses: actions/checkout@v2 + + - name: Restore boot JDK from cache + id: bootjdk + uses: actions/cache@v2 + with: + path: ~/bootjdk/${{ env.BOOT_JDK_VERSION }} + key: bootjdk-${{ runner.os }}-${{ env.BOOT_JDK_VERSION }}-${{ env.BOOT_JDK_SHA256 }}-v1 + + - name: Download boot JDK + run: | + mkdir -p "${HOME}/bootjdk/${BOOT_JDK_VERSION}" + wget -O "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" "${BOOT_JDK_URL}" + echo "${BOOT_JDK_SHA256} ${HOME}/bootjdk/${BOOT_JDK_FILENAME}" | sha256sum -c >/dev/null - + tar -xf "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" -C "${HOME}/bootjdk/${BOOT_JDK_VERSION}" + mv "${HOME}/bootjdk/${BOOT_JDK_VERSION}/"*/* "${HOME}/bootjdk/${BOOT_JDK_VERSION}/" + if: steps.bootjdk.outputs.cache-hit != 'true' + + - name: Restore jtreg artifact + id: jtreg_restore + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + continue-on-error: true + + - name: Restore jtreg artifact (retry) + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + if: steps.jtreg_restore.outcome == 'failure' + + - name: Restore build artifacts + id: build_restore + uses: actions/download-artifact@v2 + with: + name: transient_jdk-linux-x86${{ matrix.artifact }}_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jdk-linux-x86${{ matrix.artifact }} + continue-on-error: true + + - name: Restore build artifacts (retry) + uses: actions/download-artifact@v2 + with: + name: transient_jdk-linux-x86${{ matrix.artifact }}_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jdk-linux-x86${{ matrix.artifact }} + if: steps.build_restore.outcome == 'failure' + + - name: Unpack jdk + run: | + mkdir -p "${HOME}/jdk-linux-x86${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x86_bin${{ matrix.artifact }}" + tar -xf "${HOME}/jdk-linux-x86${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x86_bin${{ matrix.artifact }}.tar.gz" -C "${HOME}/jdk-linux-x86${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x86_bin${{ matrix.artifact }}" + + - name: Unpack tests + run: | + mkdir -p "${HOME}/jdk-linux-x86${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x86_bin-tests${{ matrix.artifact }}" + tar -xf "${HOME}/jdk-linux-x86${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x86_bin-tests${{ matrix.artifact }}.tar.gz" -C "${HOME}/jdk-linux-x86${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x86_bin-tests${{ matrix.artifact }}" + + - name: Find root of jdk image dir + run: | + imageroot=`find ${HOME}/jdk-linux-x86${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x86_bin${{ matrix.artifact }} -name release -type f` + echo "imageroot=`dirname ${imageroot}`" >> $GITHUB_ENV + + - name: Run tests + run: > + JDK_IMAGE_DIR=${{ env.imageroot }} + TEST_IMAGE_DIR=${HOME}/jdk-linux-x86${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_linux-x86_bin-tests${{ matrix.artifact }} + BOOT_JDK=${HOME}/bootjdk/${BOOT_JDK_VERSION} + JT_HOME=${HOME}/jtreg + make run-test-prebuilt + CONF_NAME=run-test-prebuilt + LOG_CMDLINES=true + JTREG_VERBOSE=fail,error,time + TEST="${{ matrix.suites }}" + TEST_OPTS_JAVA_OPTIONS= + JTREG_KEYWORDS="!headful" + JTREG="JAVA_OPTIONS=-XX:-CreateCoredumpOnCrash" + + - name: Check that all tests executed successfully + if: always() + run: > + if ! grep --include=test-summary.txt -lqr build/*/test-results -e "TEST SUCCESS" ; then + cat build/*/test-results/*/text/newfailures.txt ; + exit 1 ; + fi + + - name: Create suitable test log artifact name + if: always() + run: echo "logsuffix=`echo ${{ matrix.test }} | sed -e 's!/!_!'g -e 's! !_!'g`" >> $GITHUB_ENV + + - name: Package test results + if: always() + working-directory: build/run-test-prebuilt/test-results/ + run: > + zip -r9 + "$HOME/linux-x86${{ matrix.artifact }}_testresults_${{ env.logsuffix }}.zip" + . + continue-on-error: true + + - name: Package test support + if: always() + working-directory: build/run-test-prebuilt/test-support/ + run: > + zip -r9 + "$HOME/linux-x86${{ matrix.artifact }}_testsupport_${{ env.logsuffix }}.zip" + . + -i *.jtr + -i */hs_err*.log + -i */replay*.log + continue-on-error: true + + - name: Persist test results + if: always() + uses: actions/upload-artifact@v2 + with: + path: ~/linux-x86${{ matrix.artifact }}_testresults_${{ env.logsuffix }}.zip + continue-on-error: true + + - name: Persist test outputs + if: always() + uses: actions/upload-artifact@v2 + with: + path: ~/linux-x86${{ matrix.artifact }}_testsupport_${{ env.logsuffix }}.zip + continue-on-error: true + + windows_x64_build: + name: Windows x64 + runs-on: "windows-2019" + needs: prerequisites + if: needs.prerequisites.outputs.should_run != 'false' && needs.prerequisites.outputs.platform_windows_x64 != 'false' + + strategy: + fail-fast: false + matrix: + flavor: + - build release + - build debug + include: + - flavor: build debug + flags: --enable-debug + artifact: -debug + + env: + JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_FEATURE }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_INTERIM }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_UPDATE }}" + BOOT_JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).BOOT_JDK_VERSION }}" + BOOT_JDK_FILENAME: "${{ fromJson(needs.prerequisites.outputs.dependencies).WINDOWS_X64_BOOT_JDK_FILENAME }}" + BOOT_JDK_URL: "${{ fromJson(needs.prerequisites.outputs.dependencies).WINDOWS_X64_BOOT_JDK_URL }}" + BOOT_JDK_SHA256: "${{ fromJson(needs.prerequisites.outputs.dependencies).WINDOWS_X64_BOOT_JDK_SHA256 }}" + + steps: + - name: Restore cygwin packages from cache + id: cygwin + uses: actions/cache@v2 + with: + path: ~/cygwin/packages + key: cygwin-packages-${{ runner.os }}-v1 + + - name: Install cygwin + run: | + New-Item -Force -ItemType directory -Path "$HOME\cygwin" + & curl -L "https://www.cygwin.com/setup-x86_64.exe" -o "$HOME/cygwin/setup-x86_64.exe" + Start-Process -FilePath "$HOME\cygwin\setup-x86_64.exe" -ArgumentList "--quiet-mode --packages autoconf,make,zip,unzip --root $HOME\cygwin\cygwin64 --local-package-dir $HOME\cygwin\packages --site http://mirrors.kernel.org/sourceware/cygwin --no-desktop --no-shortcuts --no-startmenu --no-admin" -Wait -NoNewWindow + + - name: Checkout the source + uses: actions/checkout@v2 + with: + path: jdk + + - name: Restore boot JDK from cache + id: bootjdk + uses: actions/cache@v2 + with: + path: ~/bootjdk/${{ env.BOOT_JDK_VERSION }} + key: bootjdk-${{ runner.os }}-${{ env.BOOT_JDK_VERSION }}-${{ env.BOOT_JDK_SHA256 }}-v1 + + - name: Download boot JDK + run: | + mkdir -p "$HOME\bootjdk\$env:BOOT_JDK_VERSION" + & curl -L "$env:BOOT_JDK_URL" -o "$HOME/bootjdk/$env:BOOT_JDK_FILENAME" + $FileHash = Get-FileHash -Algorithm SHA256 "$HOME/bootjdk/$env:BOOT_JDK_FILENAME" + $FileHash.Hash -eq $env:BOOT_JDK_SHA256 + & tar -xf "$HOME/bootjdk/$env:BOOT_JDK_FILENAME" -C "$HOME/bootjdk/$env:BOOT_JDK_VERSION" + Get-ChildItem "$HOME\bootjdk\$env:BOOT_JDK_VERSION\*\*" | Move-Item -Destination "$HOME\bootjdk\$env:BOOT_JDK_VERSION" + if: steps.bootjdk.outputs.cache-hit != 'true' + + - name: Restore jtreg artifact + id: jtreg_restore + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + continue-on-error: true + + - name: Restore jtreg artifact (retry) + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + if: steps.jtreg_restore.outcome == 'failure' + + - name: Ensure a specific version of MSVC is installed + run: > + Start-Process -FilePath 'C:\Program Files (x86)\Microsoft Visual Studio\Installer\vs_installer.exe' -Wait -NoNewWindow -ArgumentList + 'modify --installPath "C:\Program Files (x86)\Microsoft Visual Studio\2019\Enterprise" --quiet + --add Microsoft.VisualStudio.Component.VC.14.28.x86.x64' + + - name: Configure + run: > + $env:Path = "$HOME\cygwin\cygwin64\bin;$HOME\cygwin\cygwin64\bin;$env:Path" ; + $env:Path = $env:Path -split ";" -match "C:\\Windows|PowerShell|cygwin" -join ";" ; + $env:BOOT_JDK = cygpath "$HOME/bootjdk/$env:BOOT_JDK_VERSION" ; + $env:JT_HOME = cygpath "$HOME/jtreg" ; + & bash configure + --with-conf-name=windows-x64 + --with-msvc-toolset-version=14.28 + ${{ matrix.flags }} + --with-version-opt="$env:GITHUB_ACTOR-$env:GITHUB_SHA" + --with-version-build=0 + --with-boot-jdk="$env:BOOT_JDK" + --with-jtreg="$env:JT_HOME" + --with-default-make-target="product-bundles test-bundles" + --with-jvm-features=shenandoahgc + --enable-jtreg-failure-handler + working-directory: jdk + + - name: Build + run: | + $env:Path = "$HOME\cygwin\cygwin64\bin;$HOME\cygwin\cygwin64\bin;$env:Path" ; + $env:Path = $env:Path -split ";" -match "C:\\Windows|PowerShell|cygwin" -join ";" ; + & make CONF_NAME=windows-x64 + working-directory: jdk + + - name: Persist test bundles + uses: actions/upload-artifact@v2 + with: + name: transient_jdk-windows-x64${{ matrix.artifact }}_${{ needs.prerequisites.outputs.bundle_id }} + path: | + jdk/build/windows-x64/bundles/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin${{ matrix.artifact }}.zip + jdk/build/windows-x64/bundles/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin-tests${{ matrix.artifact }}.tar.gz + jdk/build/windows-x64/bundles/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin${{ matrix.artifact }}-symbols.tar.gz + + windows_x64_test: + name: Windows x64 + runs-on: "windows-2019" + needs: + - prerequisites + - windows_x64_build + + strategy: + fail-fast: false + matrix: + test: + - jdk/tier1 part 1 + - jdk/tier1 part 2 + - jdk/tier1 part 3 + - langtools/tier1 + - hs/tier1 common + - hs/tier1 compiler + - hs/tier1 gc + - hs/tier1 runtime + - hs/tier1 serviceability + include: + - test: jdk/tier1 part 1 + suites: test/jdk/:tier1_part1 + - test: jdk/tier1 part 2 + suites: test/jdk/:tier1_part2 + - test: jdk/tier1 part 3 + suites: test/jdk/:tier1_part3 + - test: langtools/tier1 + suites: test/langtools/:tier1 + - test: hs/tier1 common + suites: test/hotspot/jtreg/:tier1_common + artifact: -debug + - test: hs/tier1 compiler + suites: test/hotspot/jtreg/:tier1_compiler + artifact: -debug + - test: hs/tier1 gc + suites: test/hotspot/jtreg/:tier1_gc + artifact: -debug + - test: hs/tier1 runtime + suites: test/hotspot/jtreg/:tier1_runtime + artifact: -debug + - test: hs/tier1 serviceability + suites: test/hotspot/jtreg/:tier1_serviceability + artifact: -debug + + env: + JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_FEATURE }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_INTERIM }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_UPDATE }}" + BOOT_JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).BOOT_JDK_VERSION }}" + BOOT_JDK_FILENAME: "${{ fromJson(needs.prerequisites.outputs.dependencies).WINDOWS_X64_BOOT_JDK_FILENAME }}" + BOOT_JDK_URL: "${{ fromJson(needs.prerequisites.outputs.dependencies).WINDOWS_X64_BOOT_JDK_URL }}" + BOOT_JDK_SHA256: "${{ fromJson(needs.prerequisites.outputs.dependencies).WINDOWS_X64_BOOT_JDK_SHA256 }}" + + steps: + - name: Checkout the source + uses: actions/checkout@v2 + + - name: Restore boot JDK from cache + id: bootjdk + uses: actions/cache@v2 + with: + path: ~/bootjdk/${{ env.BOOT_JDK_VERSION }} + key: bootjdk-${{ runner.os }}-${{ env.BOOT_JDK_VERSION }}-${{ env.BOOT_JDK_SHA256 }}-v1 + + - name: Download boot JDK + run: | + mkdir -p "$HOME\bootjdk\$env:BOOT_JDK_VERSION" + & curl -L "$env:BOOT_JDK_URL" -o "$HOME/bootjdk/$env:BOOT_JDK_FILENAME" + $FileHash = Get-FileHash -Algorithm SHA256 "$HOME/bootjdk/$env:BOOT_JDK_FILENAME" + $FileHash.Hash -eq $env:BOOT_JDK_SHA256 + & tar -xf "$HOME/bootjdk/$env:BOOT_JDK_FILENAME" -C "$HOME/bootjdk/$env:BOOT_JDK_VERSION" + Get-ChildItem "$HOME\bootjdk\$env:BOOT_JDK_VERSION\*\*" | Move-Item -Destination "$HOME\bootjdk\$env:BOOT_JDK_VERSION" + if: steps.bootjdk.outputs.cache-hit != 'true' + + - name: Restore cygwin packages from cache + id: cygwin + uses: actions/cache@v2 + with: + path: ~/cygwin/packages + key: cygwin-packages-${{ runner.os }}-v1 + + - name: Install cygwin + run: | + New-Item -Force -ItemType directory -Path "$HOME\cygwin" + & curl -L "https://www.cygwin.com/setup-x86_64.exe" -o "$HOME/cygwin/setup-x86_64.exe" + Start-Process -FilePath "$HOME\cygwin\setup-x86_64.exe" -ArgumentList "--quiet-mode --packages autoconf,make,zip,unzip --root $HOME\cygwin\cygwin64 --local-package-dir $HOME\cygwin\packages --site http://mirrors.kernel.org/sourceware/cygwin --no-desktop --no-shortcuts --no-startmenu --no-admin" -Wait -NoNewWindow + + - name: Restore jtreg artifact + id: jtreg_restore + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + continue-on-error: true + + - name: Restore jtreg artifact (retry) + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + if: steps.jtreg_restore.outcome == 'failure' + + - name: Restore build artifacts + id: build_restore + uses: actions/download-artifact@v2 + with: + name: transient_jdk-windows-x64${{ matrix.artifact }}_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jdk-windows-x64${{ matrix.artifact }} + continue-on-error: true + + - name: Restore build artifacts (retry) + uses: actions/download-artifact@v2 + with: + name: transient_jdk-windows-x64${{ matrix.artifact }}_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jdk-windows-x64${{ matrix.artifact }} + if: steps.build_restore.outcome == 'failure' + + - name: Unpack jdk + run: | + mkdir -p "${HOME}/jdk-windows-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin${{ matrix.artifact }}" + tar -xf "${HOME}/jdk-windows-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin${{ matrix.artifact }}.zip" -C "${HOME}/jdk-windows-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin${{ matrix.artifact }}" + + - name: Unpack symbols + run: | + mkdir -p "${HOME}/jdk-windows-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin${{ matrix.artifact }}-symbols" + tar -xf "${HOME}/jdk-windows-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin${{ matrix.artifact }}-symbols.tar.gz" -C "${HOME}/jdk-windows-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin${{ matrix.artifact }}-symbols" + + - name: Unpack tests + run: | + mkdir -p "${HOME}/jdk-windows-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin-tests${{ matrix.artifact }}" + tar -xf "${HOME}/jdk-windows-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin-tests${{ matrix.artifact }}.tar.gz" -C "${HOME}/jdk-windows-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin-tests${{ matrix.artifact }}" + + - name: Find root of jdk image dir + run: echo ("imageroot=" + (Get-ChildItem -Path $HOME/jdk-windows-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin${{ matrix.artifact }} -Filter release -Recurse -ErrorAction SilentlyContinue -Force).DirectoryName) | Out-File -FilePath $env:GITHUB_ENV -Encoding utf8 + + - name: Run tests + run: > + $env:Path = "$HOME\cygwin\cygwin64\bin;$HOME\cygwin\cygwin64\bin;$env:Path" ; + $env:Path = $env:Path -split ";" -match "C:\\Windows|PowerShell|cygwin" -join ";" ; + $env:JDK_IMAGE_DIR = cygpath "${{ env.imageroot }}" ; + $env:SYMBOLS_IMAGE_DIR = cygpath "${{ env.imageroot }}" ; + $env:TEST_IMAGE_DIR = cygpath "$HOME/jdk-windows-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_windows-x64_bin-tests${{ matrix.artifact }}" ; + $env:BOOT_JDK = cygpath "$HOME/bootjdk/$env:BOOT_JDK_VERSION" ; + $env:JT_HOME = cygpath "$HOME/jtreg" ; + & make run-test-prebuilt + CONF_NAME=run-test-prebuilt + LOG_CMDLINES=true + JTREG_VERBOSE=fail,error,time + TEST=${{ matrix.suites }} + TEST_OPTS_JAVA_OPTIONS= + JTREG_KEYWORDS="!headful" + JTREG="JAVA_OPTIONS=-XX:-CreateCoredumpOnCrash" + + - name: Check that all tests executed successfully + if: always() + run: > + if ((Get-ChildItem -Path build\*\test-results\test-summary.txt -Recurse | Select-String -Pattern "TEST SUCCESS" ).Count -eq 0) { + Get-Content -Path build\*\test-results\*\*\newfailures.txt ; + exit 1 + } + + - name: Create suitable test log artifact name + if: always() + run: echo ("logsuffix=" + ("${{ matrix.test }}" -replace "/", "_" -replace " ", "_")) | Out-File -FilePath $env:GITHUB_ENV -Encoding utf8 + + - name: Package test results + if: always() + working-directory: build/run-test-prebuilt/test-results/ + run: > + $env:Path = "$HOME\cygwin\cygwin64\bin;$env:Path" ; + zip -r9 + "$HOME/windows-x64${{ matrix.artifact }}_testresults_${{ env.logsuffix }}.zip" + . + continue-on-error: true + + - name: Package test support + if: always() + working-directory: build/run-test-prebuilt/test-support/ + run: > + $env:Path = "$HOME\cygwin\cygwin64\bin;$env:Path" ; + zip -r9 + "$HOME/windows-x64${{ matrix.artifact }}_testsupport_${{ env.logsuffix }}.zip" + . + -i *.jtr + -i */hs_err*.log + -i */replay*.log + continue-on-error: true + + - name: Persist test results + if: always() + uses: actions/upload-artifact@v2 + with: + path: ~/windows-x64${{ matrix.artifact }}_testresults_${{ env.logsuffix }}.zip + continue-on-error: true + + - name: Persist test outputs + if: always() + uses: actions/upload-artifact@v2 + with: + path: ~/windows-x64${{ matrix.artifact }}_testsupport_${{ env.logsuffix }}.zip + continue-on-error: true + + macos_x64_build: + name: macOS x64 + runs-on: "macos-10.15" + needs: prerequisites + if: needs.prerequisites.outputs.should_run != 'false' && needs.prerequisites.outputs.platform_macos_x64 != 'false' + + strategy: + fail-fast: false + matrix: + flavor: + - build release + - build debug + include: + - flavor: build release + - flavor: build debug + flags: --enable-debug + artifact: -debug + + env: + JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_FEATURE }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_INTERIM }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_UPDATE }}" + BOOT_JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).BOOT_JDK_VERSION }}" + BOOT_JDK_FILENAME: "${{ fromJson(needs.prerequisites.outputs.dependencies).MACOS_X64_BOOT_JDK_FILENAME }}" + BOOT_JDK_URL: "${{ fromJson(needs.prerequisites.outputs.dependencies).MACOS_X64_BOOT_JDK_URL }}" + BOOT_JDK_SHA256: "${{ fromJson(needs.prerequisites.outputs.dependencies).MACOS_X64_BOOT_JDK_SHA256 }}" + + steps: + - name: Checkout the source + uses: actions/checkout@v2 + with: + path: jdk + + - name: Restore boot JDK from cache + id: bootjdk + uses: actions/cache@v2 + with: + path: ~/bootjdk/${{ env.BOOT_JDK_VERSION }} + key: bootjdk-${{ runner.os }}-${{ env.BOOT_JDK_VERSION }}-${{ env.BOOT_JDK_SHA256 }}-v1 + + - name: Download boot JDK + run: | + mkdir -p ${HOME}/bootjdk/${BOOT_JDK_VERSION} || true + wget -O "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" "${BOOT_JDK_URL}" + echo "${BOOT_JDK_SHA256} ${HOME}/bootjdk/${BOOT_JDK_FILENAME}" | shasum -a 256 -c >/dev/null - + tar -xf "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" -C "${HOME}/bootjdk/${BOOT_JDK_VERSION}" + mv "${HOME}/bootjdk/${BOOT_JDK_VERSION}/"*/* "${HOME}/bootjdk/${BOOT_JDK_VERSION}/" + if: steps.bootjdk.outputs.cache-hit != 'true' + + - name: Restore jtreg artifact + id: jtreg_restore + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + continue-on-error: true + + - name: Restore jtreg artifact (retry) + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + if: steps.jtreg_restore.outcome == 'failure' + + - name: Fix jtreg permissions + run: chmod -R a+rx ${HOME}/jtreg/ + + - name: Install dependencies + run: brew install make + + - name: Select Xcode version + run: sudo xcode-select --switch /Applications/Xcode_11.3.1.app/Contents/Developer + + - name: Configure + run: > + bash configure + --with-conf-name=macos-x64 + ${{ matrix.flags }} + --with-version-opt=${GITHUB_ACTOR}-${GITHUB_SHA} + --with-version-build=0 + --with-boot-jdk=${HOME}/bootjdk/${BOOT_JDK_VERSION}/Contents/Home + --with-jtreg=${HOME}/jtreg + --with-default-make-target="product-bundles test-bundles" + --with-zlib=system + --with-jvm-features=shenandoahgc + --enable-jtreg-failure-handler + working-directory: jdk + + - name: Build + run: make CONF_NAME=macos-x64 + working-directory: jdk + + - name: Persist test bundles + uses: actions/upload-artifact@v2 + with: + name: transient_jdk-macos-x64${{ matrix.artifact }}_${{ needs.prerequisites.outputs.bundle_id }} + path: | + jdk/build/macos-x64/bundles/jdk-${{ env.JDK_VERSION }}-internal+0_osx-x64_bin${{ matrix.artifact }}.tar.gz + jdk/build/macos-x64/bundles/jdk-${{ env.JDK_VERSION }}-internal+0_osx-x64_bin-tests${{ matrix.artifact }}.tar.gz + + macos_x64_test: + name: macOS x64 + runs-on: "macos-10.15" + needs: + - prerequisites + - macos_x64_build + + strategy: + fail-fast: false + matrix: + test: + - jdk/tier1 part 1 + - jdk/tier1 part 2 + - jdk/tier1 part 3 + - langtools/tier1 + - hs/tier1 common + - hs/tier1 compiler + - hs/tier1 gc + - hs/tier1 runtime + - hs/tier1 serviceability + include: + - test: jdk/tier1 part 1 + suites: test/jdk/:tier1_part1 + - test: jdk/tier1 part 2 + suites: test/jdk/:tier1_part2 + - test: jdk/tier1 part 3 + suites: test/jdk/:tier1_part3 + - test: langtools/tier1 + suites: test/langtools/:tier1 + - test: hs/tier1 common + suites: test/hotspot/jtreg/:tier1_common + artifact: -debug + - test: hs/tier1 compiler + suites: test/hotspot/jtreg/:tier1_compiler + artifact: -debug + - test: hs/tier1 gc + suites: test/hotspot/jtreg/:tier1_gc + artifact: -debug + - test: hs/tier1 runtime + suites: test/hotspot/jtreg/:tier1_runtime + artifact: -debug + - test: hs/tier1 serviceability + suites: test/hotspot/jtreg/:tier1_serviceability + artifact: -debug + + env: + JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_FEATURE }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_INTERIM }}.${{ fromJson(needs.prerequisites.outputs.dependencies).DEFAULT_VERSION_UPDATE }}" + BOOT_JDK_VERSION: "${{ fromJson(needs.prerequisites.outputs.dependencies).BOOT_JDK_VERSION }}" + BOOT_JDK_FILENAME: "${{ fromJson(needs.prerequisites.outputs.dependencies).MACOS_X64_BOOT_JDK_FILENAME }}" + BOOT_JDK_URL: "${{ fromJson(needs.prerequisites.outputs.dependencies).MACOS_X64_BOOT_JDK_URL }}" + BOOT_JDK_SHA256: "${{ fromJson(needs.prerequisites.outputs.dependencies).MACOS_X64_BOOT_JDK_SHA256 }}" + + steps: + - name: Checkout the source + uses: actions/checkout@v2 + + - name: Restore boot JDK from cache + id: bootjdk + uses: actions/cache@v2 + with: + path: ~/bootjdk/${{ env.BOOT_JDK_VERSION }} + key: bootjdk-${{ runner.os }}-${{ env.BOOT_JDK_VERSION }}-${{ env.BOOT_JDK_SHA256 }}-v1 + + - name: Download boot JDK + run: | + mkdir -p ${HOME}/bootjdk/${BOOT_JDK_VERSION} || true + wget -O "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" "${BOOT_JDK_URL}" + echo "${BOOT_JDK_SHA256} ${HOME}/bootjdk/${BOOT_JDK_FILENAME}" | shasum -a 256 -c >/dev/null - + tar -xf "${HOME}/bootjdk/${BOOT_JDK_FILENAME}" -C "${HOME}/bootjdk/${BOOT_JDK_VERSION}" + mv "${HOME}/bootjdk/${BOOT_JDK_VERSION}/"*/* "${HOME}/bootjdk/${BOOT_JDK_VERSION}/" + if: steps.bootjdk.outputs.cache-hit != 'true' + + - name: Restore jtreg artifact + id: jtreg_restore + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + continue-on-error: true + + - name: Restore jtreg artifact (retry) + uses: actions/download-artifact@v2 + with: + name: transient_jtreg_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jtreg/ + if: steps.jtreg_restore.outcome == 'failure' + + - name: Restore build artifacts + id: build_restore + uses: actions/download-artifact@v2 + with: + name: transient_jdk-macos-x64${{ matrix.artifact }}_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jdk-macos-x64${{ matrix.artifact }} + continue-on-error: true + + - name: Restore build artifacts (retry) + uses: actions/download-artifact@v2 + with: + name: transient_jdk-macos-x64${{ matrix.artifact }}_${{ needs.prerequisites.outputs.bundle_id }} + path: ~/jdk-macos-x64${{ matrix.artifact }} + if: steps.build_restore.outcome == 'failure' + + - name: Unpack jdk + run: | + mkdir -p "${HOME}/jdk-macos-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_osx-x64_bin${{ matrix.artifact }}" + tar -xf "${HOME}/jdk-macos-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_osx-x64_bin${{ matrix.artifact }}.tar.gz" -C "${HOME}/jdk-macos-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_osx-x64_bin${{ matrix.artifact }}" + + - name: Unpack tests + run: | + mkdir -p "${HOME}/jdk-macos-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_osx-x64_bin-tests${{ matrix.artifact }}" + tar -xf "${HOME}/jdk-macos-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_osx-x64_bin-tests${{ matrix.artifact }}.tar.gz" -C "${HOME}/jdk-macos-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_osx-x64_bin-tests${{ matrix.artifact }}" + + - name: Install dependencies + run: brew install make + + - name: Select Xcode version + run: sudo xcode-select --switch /Applications/Xcode_11.3.1.app/Contents/Developer + + - name: Find root of jdk image dir + run: | + imageroot=`find ${HOME}/jdk-macos-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_osx-x64_bin${{ matrix.artifact }} -name release -type f` + echo "imageroot=`dirname ${imageroot}`" >> $GITHUB_ENV + + - name: Run tests + run: > + JDK_IMAGE_DIR=${{ env.imageroot }} + TEST_IMAGE_DIR=${HOME}/jdk-macos-x64${{ matrix.artifact }}/jdk-${{ env.JDK_VERSION }}-internal+0_osx-x64_bin-tests${{ matrix.artifact }} + BOOT_JDK=${HOME}/bootjdk/${BOOT_JDK_VERSION}/Contents/Home + JT_HOME=${HOME}/jtreg + gmake run-test-prebuilt + CONF_NAME=run-test-prebuilt + LOG_CMDLINES=true + JTREG_VERBOSE=fail,error,time + TEST=${{ matrix.suites }} + TEST_OPTS_JAVA_OPTIONS= + JTREG_KEYWORDS="!headful" + JTREG="JAVA_OPTIONS=-XX:-CreateCoredumpOnCrash" + + - name: Check that all tests executed successfully + if: always() + run: > + if ! grep --include=test-summary.txt -lqr build/*/test-results -e "TEST SUCCESS" ; then + cat build/*/test-results/*/text/newfailures.txt ; + exit 1 ; + fi + + - name: Create suitable test log artifact name + if: always() + run: echo "logsuffix=`echo ${{ matrix.test }} | sed -e 's!/!_!'g -e 's! !_!'g`" >> $GITHUB_ENV + + - name: Package test results + if: always() + working-directory: build/run-test-prebuilt/test-results/ + run: > + zip -r9 + "$HOME/macos-x64${{ matrix.artifact }}_testresults_${{ env.logsuffix }}.zip" + . + continue-on-error: true + + - name: Package test support + if: always() + working-directory: build/run-test-prebuilt/test-support/ + run: > + zip -r9 + "$HOME/macos-x64${{ matrix.artifact }}_testsupport_${{ env.logsuffix }}.zip" + . + -i *.jtr + -i */hs_err*.log + -i */replay*.log + continue-on-error: true + + - name: Persist test results + if: always() + uses: actions/upload-artifact@v2 + with: + path: ~/macos-x64${{ matrix.artifact }}_testresults_${{ env.logsuffix }}.zip + continue-on-error: true + + - name: Persist test outputs + if: always() + uses: actions/upload-artifact@v2 + with: + path: ~/macos-x64${{ matrix.artifact }}_testsupport_${{ env.logsuffix }}.zip + continue-on-error: true + + artifacts: + name: Post-process artifacts + runs-on: "ubuntu-20.04" + if: always() + continue-on-error: true + needs: + - prerequisites + - linux_additional_build + - linux_x64_test + - linux_x86_test + - windows_x64_test + - macos_x64_test + + steps: + - name: Determine current artifacts endpoint + id: actions_runtime + uses: actions/github-script@v3 + with: + script: "return { url: process.env['ACTIONS_RUNTIME_URL'], token: process.env['ACTIONS_RUNTIME_TOKEN'] }" + + - name: Display current artifacts + run: > + curl -s -H 'Accept: application/json;api-version=6.0-preview' + -H 'Authorization: Bearer ${{ fromJson(steps.actions_runtime.outputs.result).token }}' + '${{ fromJson(steps.actions_runtime.outputs.result).url }}_apis/pipelines/workflows/${{ github.run_id }}/artifacts?api-version=6.0-preview' + + - name: Delete transient artifacts + run: > + for url in ` + curl -s -H 'Accept: application/json;api-version=6.0-preview' + -H 'Authorization: Bearer ${{ fromJson(steps.actions_runtime.outputs.result).token }}' + '${{ fromJson(steps.actions_runtime.outputs.result).url }}_apis/pipelines/workflows/${{ github.run_id }}/artifacts?api-version=6.0-preview' | + jq -r -c '.value | map(select(.name|startswith("transient_"))) | .[].url'`; do + curl -s -H 'Accept: application/json;api-version=6.0-preview' + -H 'Authorization: Bearer ${{ fromJson(steps.actions_runtime.outputs.result).token }}' + -X DELETE "${url}"; + done + + - name: Fetch remaining artifacts (test results) + uses: actions/download-artifact@v2 + with: + path: test-results + + - name: Delete remaining artifacts + run: > + for url in ` + curl -s -H 'Accept: application/json;api-version=6.0-preview' + -H 'Authorization: Bearer ${{ fromJson(steps.actions_runtime.outputs.result).token }}' + '${{ fromJson(steps.actions_runtime.outputs.result).url }}_apis/pipelines/workflows/${{ github.run_id }}/artifacts?api-version=6.0-preview' | + jq -r -c '.value | .[].url'`; do + curl -s -H 'Accept: application/json;api-version=6.0-preview' + -H 'Authorization: Bearer ${{ fromJson(steps.actions_runtime.outputs.result).token }}' + -X DELETE "${url}"; + done + + - name: Upload a combined test results artifact + uses: actions/upload-artifact@v2 + with: + name: test-results_${{ needs.prerequisites.outputs.bundle_id }} + path: test-results
diff --git a/.hgtags b/.hgtags index 71a3d45..faac1d5 100644 --- a/.hgtags +++ b/.hgtags
@@ -548,6 +548,7 @@ 3b6fc7cd594608b7125eb0b75bdc05132e7b5f39 jdk-11.0.4+3 e442b78d7687744475676724bd27b1d52f096d38 jdk-11.0.4+4 371ce104ac19a12012dfe3749240b0309bfc86ee jdk-11.0.4+5 +3594cd8691f224cc7f8909c2fb14eaea0e190097 jdk-11.0.5+0 9ab8738bf30663e01924f40e04d6d04751271b77 jdk-11.0.4+6 640251cdca0577fd8aa4a51ddb7c71c3b874033c jdk-11.0.4+7 ce601e800f56af59edfda40e19a92a8d3121a1cd jdk-11.0.4+8 @@ -555,3 +556,97 @@ 3f5829d9d7629ba3893456e20731949a570cc277 jdk-11.0.4+10 6a4d57474e1c971cccf4165b3d9d023928510010 jdk-11.0.4+11 6a4d57474e1c971cccf4165b3d9d023928510010 jdk-11.0.4-ga +3ba9c532128b1feccf59ab8ce812b1fce2b6f681 jdk-11.0.5+1 +b249a2a2034e3392c647c61d401a41ac7237d635 jdk-11.0.5+2 +d84dae4fba034adc749e3f28fc444b3d95b8f670 jdk-11.0.5+3 +315e873712092d48fbfa23885bdf2c6fd654c1ab jdk-11.0.5+4 +d43c5ab1a337b94fffee1cab871543da06f8113c jdk-11.0.5+5 +7431ec494a2988fa69742812168c3119805a7855 jdk-11.0.6+0 +deaef57bf366fdab908b97a9760d0fa6e273abcd jdk-11.0.5+6 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+4fd46d208f0a4b55924af8e0c2fb6bcf46e18ec6 jdk-11.0.9.1+0 +27723943c0dd65a191cbefe031cec001521e4b13 jdk-11.0.9.1+1 +31affc22b3b5f5d43783ffadf57f22848bad9db8 jdk-11.0.9.1-ga +f3168de4eb0dd74bf8e81537f62742bde5e412c3 jdk-11.0.10+1 +a35aa07b57bab3690224e3af939ee085d50eb476 jdk-11.0.10+2 +bca12c00a776f8cee7a0eeaf788499b9eab9cf9d jdk-11.0.10+3 +9504fa6f98f5aad0aa1ac36d5bff3260a32020c8 jdk-11.0.10+4 +5f5c3544ccb4d0bbc638e665524b292860dd9515 jdk-11.0.10+5 +cbd009b79ac52cca36b5bda2cf1ef033a1288a3e jdk-11.0.11+0 +4b9bc2a1dde0631958393125997855382325964d jdk-11.0.10+6 +c45f74d45787a857d35b5a66c9b0304c91a9c5d0 jdk-11.0.10+7 +43428f69099f6f87f6e1922deacbf13e1adb751f jdk-11.0.10+8 +8b3498547395ee80a6e731078056b2aeb3e3c5e8 jdk-11.0.10+9 +8b3498547395ee80a6e731078056b2aeb3e3c5e8 jdk-11.0.10-ga +4ed322bf6b0098353ceaecf35662fadf457cd81d jdk-11.0.11+1 +b68647c6ecc1e73111d8047448d75966f255460f jdk-11.0.11+2 +14cc036b17a5f4be5b0643e6b24ed32563684ab9 jdk-11.0.11+3 +c4405735470a92e2c45490b89a8099252f3481d2 jdk-11.0.11+4 +38430a8a4488582612c6a87ab58d109cc5217e8b jdk-11.0.11+5 +595a965d85afdd01c30dbc7b2efd75f4cb202816 jdk-11.0.12+0 +e41ae00add1d76a8f25adb558933382947ea840d jdk-11.0.11+6 +14f9928caac31368d27f13e4e21ca25c1e0be950 jdk-11.0.11+7 +9f0347b029d3a0349f23befcfb68ee02d85d9034 jdk-11.0.11+8 +15862747ee15445292b4b9949b4f0f4badba4812 jdk-11.0.11+9 +15862747ee15445292b4b9949b4f0f4badba4812 jdk-11.0.11-ga +5720ffa08f8514b9f0ea8b3a49e05a872c9c0efe jdk-11.0.12+1 +70a4031a8bef3e693f34864fdd482429c73dc76a jdk-11.0.12+2 +873a691b1ae4fa8b55ca5d08fa21aca3a4904fb8 jdk-11.0.12+3 +40d1e784e1937aaea696a9654cc2d944d3d78996 jdk-11.0.12+4 +6aa6f6860508fca3a97aea1de7a36574498d22bf jdk-11.0.12+5 +91e81ac088545abdc3eaaa707853d31a6cf99af3 jdk-11.0.12+6 +f412f2537f1502a9697a9684c77bea8d848db1ab jdk-11.0.12+7 +f412f2537f1502a9697a9684c77bea8d848db1ab jdk-11.0.12-ga
diff --git a/.jcheck/conf b/.jcheck/conf index ad4189d..887b27d 100644 --- a/.jcheck/conf +++ b/.jcheck/conf
@@ -1,2 +1,31 @@ -project=jdk10 -bugids=dup +[general] +project=jdk-updates +jbs=JDK +version=11.0.13 + +[checks] +error=author,committer,reviewers,merge,issues,executable,symlink,message,hg-tag,whitespace + +[repository] +tags=(?:jdk-(?:[1-9]([0-9]*)(?:\.(?:0|[1-9][0-9]*)){0,4})(?:\+(?:(?:[0-9]+))|(?:-ga)))|(?:jdk[4-9](?:u\d{1,3})?-(?:(?:b\d{2,3})|(?:ga)))|(?:hs\d\d(?:\.\d{1,2})?-b\d\d) +branches= + +[census] +version=0 +domain=openjdk.org + +[checks "whitespace"] +files=.*\.cpp|.*\.hpp|.*\.c|.*\.h|.*\.java + +[checks "merge"] +message=Merge + +[checks "reviewers"] +reviewers=1 +ignore=duke + +[checks "committer"] +role=committer + +[checks "issues"] +pattern=^([124-8][0-9]{6}): (\S.*)$
diff --git a/doc/building.html b/doc/building.html index d6f7b5a..0310d90 100644 --- a/doc/building.html +++ b/doc/building.html
@@ -68,10 +68,12 @@ </ul></li> <li><a href="#running-tests">Running Tests</a></li> <li><a href="#cross-compiling">Cross-compiling</a><ul> +<li><a href="#cross-compiling-the-easy-way-with-openjdk-devkits">Cross compiling the easy way with OpenJDK devkits</a></li> <li><a href="#boot-jdk-and-build-jdk">Boot JDK and Build JDK</a></li> <li><a href="#specifying-the-target-platform">Specifying the Target Platform</a></li> <li><a href="#toolchain-considerations">Toolchain Considerations</a></li> <li><a href="#native-libraries">Native Libraries</a></li> +<li><a href="#creating-and-using-sysroots-with-qemu-deboostrap">Creating And Using Sysroots With qemu-deboostrap</a></li> <li><a href="#building-for-armaarch64">Building for ARM/aarch64</a></li> <li><a href="#verifying-the-build">Verifying the Build</a></li> </ul></li> @@ -91,12 +93,10 @@ <li><a href="#getting-help">Getting Help</a></li> </ul></li> <li><a href="#hints-and-suggestions-for-advanced-users">Hints and Suggestions for Advanced Users</a><ul> -<li><a href="#setting-up-a-forest-for-pushing-changes-defpath">Setting Up a Forest for Pushing Changes (defpath)</a></li> <li><a href="#bash-completion">Bash Completion</a></li> <li><a href="#using-multiple-configurations">Using Multiple Configurations</a></li> <li><a href="#handling-reconfigurations">Handling Reconfigurations</a></li> <li><a href="#using-fine-grained-make-targets">Using Fine-Grained Make Targets</a></li> -<li><a href="#learn-about-mercurial">Learn About Mercurial</a></li> </ul></li> <li><a href="#understanding-the-build-system">Understanding the Build System</a><ul> <li><a href="#configurations">Configurations</a></li> @@ -110,10 +110,10 @@ </ul> </nav> <h2 id="tldr-instructions-for-the-impatient">TL;DR (Instructions for the Impatient)</h2> -<p>If you are eager to try out building the JDK, these simple steps works most of the time. They assume that you have installed Mercurial (and Cygwin if running on Windows) and cloned the top-level JDK repository that you want to build.</p> +<p>If you are eager to try out building the JDK, these simple steps works most of the time. They assume that you have installed Git (and Cygwin if running on Windows) and cloned the top-level JDK repository that you want to build.</p> <ol type="1"> <li><p><a href="#getting-the-source-code">Get the complete source code</a>:<br /> -<code>hg clone http://hg.openjdk.java.net/jdk/jdk</code></p></li> +<code>git clone https://git.openjdk.java.net/jdk/</code></p></li> <li><p><a href="#running-configure">Run configure</a>:<br /> <code>bash configure</code></p> <p>If <code>configure</code> fails due to missing dependencies (to either the <a href="#native-compiler-toolchain-requirements">toolchain</a>, <a href="#build-tools-requirements">build tools</a>, <a href="#external-library-requirements">external libraries</a> or the <a href="#boot-jdk-requirements">boot JDK</a>), most of the time it prints a suggestion on how to resolve the situation on your platform. Follow the instructions, and try running <code>bash configure</code> again.</p></li> @@ -129,8 +129,8 @@ <p>The JDK is a complex software project. Building it requires a certain amount of technical expertise, a fair number of dependencies on external software, and reasonably powerful hardware.</p> <p>If you just want to use the JDK and not build it yourself, this document is not for you. See for instance <a href="http://openjdk.java.net/install">OpenJDK installation</a> for some methods of installing a prebuilt JDK.</p> <h2 id="getting-the-source-code">Getting the Source Code</h2> -<p>Make sure you are getting the correct version. As of JDK 10, the source is no longer split into separate repositories so you only need to clone one single repository. At the <a href="http://hg.openjdk.java.net/">OpenJDK Mercurial server</a> you can see a list of all available forests. If you want to build an older version, e.g. JDK 8, it is recommended that you get the <code>jdk8u</code> forest, which contains incremental updates, instead of the <code>jdk8</code> forest, which was frozen at JDK 8 GA.</p> -<p>If you are new to Mercurial, a good place to start is the <a href="http://www.mercurial-scm.org/guide">Mercurial Beginner's Guide</a>. The rest of this document assumes a working knowledge of Mercurial.</p> +<p>Make sure you are getting the correct version. As of JDK 10, the source is no longer split into separate repositories so you only need to clone one single repository. At the <a href="https://git.openjdk.java.net/">OpenJDK Git site</a> you can see a list of all available repositories. If you want to build an older version, e.g. JDK 8, it is recommended that you get the <code>jdk8u</code> forest, which contains incremental updates, instead of the <code>jdk8</code> forest, which was frozen at JDK 8 GA.</p> +<p>If you are new to Git, a good place to start is the book <a href="https://git-scm.com/book/en/v2">Pro Git</a>. The rest of this document assumes a working knowledge of Git.</p> <h3 id="special-considerations">Special Considerations</h3> <p>For a smooth building experience, it is recommended that you follow these rules on where and how to check out the source code.</p> <ul> @@ -141,7 +141,11 @@ <ul> <li><p>Create the directory that is going to contain the top directory of the JDK clone by using the <code>mkdir</code> command in the Cygwin bash shell. That is, do <em>not</em> create it using Windows Explorer. This will ensure that it will have proper Cygwin attributes, and that it's children will inherit those attributes.</p></li> <li><p>Do not put the JDK clone in a path under your Cygwin home directory. This is especially important if your user name contains spaces and/or mixed upper and lower case letters.</p></li> -<li><p>Clone the JDK repository using the Cygwin command line <code>hg</code> client as instructed in this document. That is, do <em>not</em> use another Mercurial client such as TortoiseHg.</p></li> +<li><p>You need to install a git client. You have two choices, Cygwin git or Git for Windows. Unfortunately there are pros and cons with each choice.</p> +<ul> +<li><p>The Cygwin <code>git</code> client has no line ending issues and understands Cygwin paths (which are used throughout the JDK build system). However, it does not currently work well with the Skara CLI tooling. Please see the <a href="https://wiki.openjdk.java.net/display/SKARA/Skara#Skara-Git">Skara wiki on Git clients</a> for up-to-date information about the Skara git client support.</p></li> +<li><p>The <a href="https://gitforwindows.org">Git for Windows</a> client has issues with line endings, and do not understand Cygwin paths. It does work well with the Skara CLI tooling, however. To alleviate the line ending problems, make sure you set <code>core.autocrlf</code> to <code>false</code> (this is asked during installation).</p></li> +</ul></li> </ul> <p>Failure to follow this procedure might result in hard-to-debug build problems.</p></li> </ul> @@ -191,7 +195,7 @@ <p>Windows XP is not a supported platform, but all newer Windows should be able to build the JDK.</p> <p>On Windows, it is important that you pay attention to the instructions in the <a href="#special-considerations">Special Considerations</a>.</p> <p>Windows is the only non-POSIX OS supported by the JDK, and as such, requires some extra care. A POSIX support layer is required to build on Windows. Currently, the only supported such layer is Cygwin. (Msys is no longer supported due to a too old bash; msys2 and the new Windows Subsystem for Linux (WSL) would likely be possible to support in a future version but that would require effort to implement.)</p> -<p>Internally in the build system, all paths are represented as Unix-style paths, e.g. <code>/cygdrive/c/hg/jdk9/Makefile</code> rather than <code>C:\hg\jdk9\Makefile</code>. This rule also applies to input to the build system, e.g. in arguments to <code>configure</code>. So, use <code>--with-msvcr-dll=/cygdrive/c/msvcr100.dll</code> rather than <code>--with-msvcr-dll=c:\msvcr100.dll</code>. For details on this conversion, see the section on <a href="#fixpath">Fixpath</a>.</p> +<p>Internally in the build system, all paths are represented as Unix-style paths, e.g. <code>/cygdrive/c/git/jdk/Makefile</code> rather than <code>C:\git\jdk\Makefile</code>. This rule also applies to input to the build system, e.g. in arguments to <code>configure</code>. So, use <code>--with-msvcr-dll=/cygdrive/c/msvcr100.dll</code> rather than <code>--with-msvcr-dll=c:\msvcr100.dll</code>. For details on this conversion, see the section on <a href="#fixpath">Fixpath</a>.</p> <h4 id="cygwin">Cygwin</h4> <p>A functioning <a href="http://www.cygwin.com/">Cygwin</a> environment is thus required for building the JDK on Windows. If you have a 64-bit OS, we strongly recommend using the 64-bit version of Cygwin.</p> <p><strong>Note:</strong> Cygwin has a model of continuously updating all packages without any easy way to install or revert to a specific version of a package. This means that whenever you add or update a package in Cygwin, you might (inadvertently) update tools that are used by the JDK build process, and that can cause unexpected build problems.</p> @@ -277,7 +281,7 @@ </tr> <tr class="even"> <td style="text-align: left;">Windows</td> -<td style="text-align: left;">Microsoft Visual Studio 2017 update 15.5.5</td> +<td style="text-align: left;">Microsoft Visual Studio 2017 update 15.9.16</td> </tr> </tbody> </table> @@ -353,7 +357,7 @@ $ CC -V CC: Sun C++ 5.13 SunOS_i386 151846-10 2015/10/30</code></pre> <h3 id="microsoft-visual-studio">Microsoft Visual Studio</h3> -<p>The minimum accepted version of Visual Studio is 2010. Older versions will not be accepted by <code>configure</code>. The maximum accepted version of Visual Studio is 2017. Versions older than 2017 are unlikely to continue working for long.</p> +<p>The minimum accepted version of Visual Studio is 2010. Older versions will not be accepted by <code>configure</code>. The maximum accepted version of Visual Studio is 2019. Versions older than 2017 are unlikely to continue working for long.</p> <p>If you have multiple versions of Visual Studio installed, <code>configure</code> will by default pick the latest. You can request a specific version to be used by setting <code>--with-toolchain-version</code>, e.g. <code>--with-toolchain-version=2015</code>.</p> <p>If you get <code>LINK: fatal error LNK1123: failure during conversion to COFF: file invalid</code> when building using Visual Studio 2010, you have encountered <a href="http://support.microsoft.com/kb/2757355">KB2757355</a>, a bug triggered by a specific installation order. However, the solution suggested by the KB article does not always resolve the problem. See <a href="https://stackoverflow.com/questions/10888391">this stackoverflow discussion</a> for other suggestions.</p> <h3 id="ibm-xl-cc">IBM XL C/C++</h3> @@ -369,10 +373,10 @@ <p>On Linux you can also get a JDK from the Linux distribution. On apt-based distros (like Debian and Ubuntu), <code>sudo apt-get install openjdk-<VERSION>-jdk</code> is typically enough to install a JDK <VERSION>. On rpm-based distros (like Fedora and Red Hat), try <code>sudo yum install java-<VERSION>-openjdk-devel</code>.</p> <h2 id="external-library-requirements">External Library Requirements</h2> <p>Different platforms require different external libraries. In general, libraries are not optional - that is, they are either required or not used.</p> -<p>If a required library is not detected by <code>configure</code>, you need to provide the path to it. There are two forms of the <code>configure</code> arguments to point to an external library: <code>--with-<LIB>=<path></code> or <code>--with-<LIB>-include=<path to include> --with-<LIB>-lib=<path to lib></code>. The first variant is more concise, but require the include files an library files to reside in a default hierarchy under this directory. In most cases, it works fine.</p> +<p>If a required library is not detected by <code>configure</code>, you need to provide the path to it. There are two forms of the <code>configure</code> arguments to point to an external library: <code>--with-<LIB>=<path></code> or <code>--with-<LIB>-include=<path to include> --with-<LIB>-lib=<path to lib></code>. The first variant is more concise, but require the include files and library files to reside in a default hierarchy under this directory. In most cases, it works fine.</p> <p>As a fallback, the second version allows you to point to the include directory and the lib directory separately.</p> <h3 id="freetype">FreeType</h3> -<p>FreeType2 from <a href="http://www.freetype.org/">The FreeType Project</a> is not required on any platform. The exception is on Unix-based platforms when configuring such that the build artifacts will reference a system installed library, rather than bundling the JDK’s own copy.</p> +<p>FreeType2 from <a href="http://www.freetype.org/">The FreeType Project</a> is not required on any platform. The exception is on Unix-based platforms when configuring such that the build artifacts will reference a system installed library, rather than bundling the JDK's own copy.</p> <ul> <li>To install on an apt-based Linux, try running <code>sudo apt-get install libfreetype6-dev</code>.</li> <li>To install on an rpm-based Linux, try running <code>sudo yum install freetype-devel</code>.</li> @@ -433,7 +437,7 @@ <p>To build the JDK, you need a "configuration", which consists of a directory where to store the build output, coupled with information about the platform, the specific build machine, and choices that affect how the JDK is built.</p> <p>The configuration is created by the <code>configure</code> script. The basic invocation of the <code>configure</code> script looks like this:</p> <pre><code>bash configure [options]</code></pre> -<p>This will create an output directory containing the configuration and setup an area for the build result. This directory typically looks like <code>build/linux-x64-normal-server-release</code>, but the actual name depends on your specific configuration. (It can also be set directly, see <a href="#using-multiple-configurations">Using Multiple Configurations</a>). This directory is referred to as <code>$BUILD</code> in this documentation.</p> +<p>This will create an output directory containing the configuration and setup an area for the build result. This directory typically looks like <code>build/linux-x64-server-release</code>, but the actual name depends on your specific configuration. (It can also be set directly, see <a href="#using-multiple-configurations">Using Multiple Configurations</a>). This directory is referred to as <code>$BUILD</code> in this documentation.</p> <p><code>configure</code> will try to figure out what system you are running on and where all necessary build components are. If you have all prerequisites for building installed, it should find everything. If it fails to detect any component automatically, it will exit and inform you about the problem.</p> <p>Some command line examples:</p> <ul> @@ -565,6 +569,47 @@ <p>This requires a more complex setup and build procedure. This section assumes you are familiar with cross-compiling in general, and will only deal with the particularities of cross-compiling the JDK. If you are new to cross-compiling, please see the <a href="https://en.wikipedia.org/wiki/Cross_compiler#External_links">external links at Wikipedia</a> for a good start on reading materials.</p> <p>Cross-compiling the JDK requires you to be able to build both for the build platform and for the target platform. The reason for the former is that we need to build and execute tools during the build process, both native tools and Java tools.</p> <p>If all you want to do is to compile a 32-bit version, for the same OS, on a 64-bit machine, consider using <code>--with-target-bits=32</code> instead of doing a full-blown cross-compilation. (While this surely is possible, it's a lot more work and will take much longer to build.)</p> +<h3 id="cross-compiling-the-easy-way-with-openjdk-devkits">Cross compiling the easy way with OpenJDK devkits</h3> +<p>The OpenJDK build system provides out-of-the box support for creating and using so called devkits. A <code>devkit</code> is basically a collection of a cross-compiling toolchain and a sysroot environment which can easily be used together with the <code>--with-devkit</code> configure option to cross compile the OpenJDK. On Linux/x86_64, the following command:</p> +<pre><code>bash configure --with-devkit=<devkit-path> --openjdk-target=ppc64-linux-gnu && make</code></pre> +<p>will configure and build OpenJDK for Linux/ppc64 assuming that <code><devkit-path></code> points to a Linux/x86_64 to Linux/ppc64 devkit.</p> +<p>Devkits can be created from the <code>make/devkit</code> directory by executing:</p> +<pre><code>make [ TARGETS="<TARGET_TRIPLET>+" ] [ BASE_OS=<OS> ] [ BASE_OS_VERSION=<VER> ]</code></pre> +<p>where <code>TARGETS</code> contains one or more <code>TARGET_TRIPLET</code>s of the form described in <a href="https://sourceware.org/autobook/autobook/autobook_17.html">section 3.4 of the GNU Autobook</a>. If no targets are given, a native toolchain for the current platform will be created. Currently, at least the following targets are known to work:</p> +<table> +<thead> +<tr class="header"> +<th>Supported devkit targets</th> +</tr> +</thead> +<tbody> +<tr class="odd"> +<td>x86_64-linux-gnu</td> +</tr> +<tr class="even"> +<td>aarch64-linux-gnu</td> +</tr> +<tr class="odd"> +<td>arm-linux-gnueabihf</td> +</tr> +<tr class="even"> +<td>ppc64-linux-gnu</td> +</tr> +<tr class="odd"> +<td>ppc64le-linux-gnu</td> +</tr> +<tr class="even"> +<td>s390x-linux-gnu</td> +</tr> +</tbody> +</table> +<p><code>BASE_OS</code> must be one of "OEL6" for Oracle Enterprise Linux 6 or "Fedora" (if not specified "OEL6" will be the default). If the base OS is "Fedora" the corresponding Fedora release can be specified with the help of the <code>BASE_OS_VERSION</code> option (with "27" as default version). If the build is successful, the new devkits can be found in the <code>build/devkit/result</code> subdirectory:</p> +<pre><code>cd make/devkit +make TARGETS="ppc64le-linux-gnu aarch64-linux-gnu" BASE_OS=Fedora BASE_OS_VERSION=21 +ls -1 ../../build/devkit/result/ +x86_64-linux-gnu-to-aarch64-linux-gnu +x86_64-linux-gnu-to-ppc64le-linux-gnu</code></pre> +<p>Notice that devkits are not only useful for targeting different build platforms. Because they contain the full build dependencies for a system (i.e. compiler and root file system), they can easily be used to build well-known, reliable and reproducible build environments. You can for example create and use a devkit with GCC 7.3 and a Fedora 12 sysroot environment (with glibc 2.11) on Ubuntu 14.04 (which doesn't have GCC 7.3 by default) to produce OpenJDK binaries which will run on all Linux systems with runtime libraries newer than the ones from Fedora 12 (e.g. Ubuntu 16.04, SLES 11 or RHEL 6).</p> <h3 id="boot-jdk-and-build-jdk">Boot JDK and Build JDK</h3> <p>When cross-compiling, make sure you use a boot JDK that runs on the <em>build</em> system, and not on the <em>target</em> system.</p> <p>To be able to build, we need a "Build JDK", which is a JDK built from the current sources (that is, the same as the end result of the entire build process), but able to run on the <em>build</em> system, and not the <em>target</em> system. (In contrast, the Boot JDK should be from an older release, e.g. JDK 8 when building JDK 9.)</p> @@ -634,6 +679,72 @@ cp: cannot stat `arm-linux-gnueabihf/libXt.so': No such file or directory</code></pre></li> <li><p>If the X11 libraries are not properly detected by <code>configure</code>, you can point them out by <code>--with-x</code>.</p></li> </ul> +<h3 id="creating-and-using-sysroots-with-qemu-deboostrap">Creating And Using Sysroots With qemu-deboostrap</h3> +<p>Fortunately, you can create sysroots for foreign architectures with tools provided by your OS. On Debian/Ubuntu systems, one could use <code>qemu-deboostrap</code> to create the <em>target</em> system chroot, which would have the native libraries and headers specific to that <em>target</em> system. After that, we can use the cross-compiler on the <em>build</em> system, pointing into chroot to get the build dependencies right. This allows building for foreign architectures with native compilation speed.</p> +<p>For example, cross-compiling to AArch64 from x86_64 could be done like this:</p> +<ul> +<li><p>Install cross-compiler on the <em>build</em> system:</p> +<pre><code>apt install g++-aarch64-linux-gnu gcc-aarch64-linux-gnu</code></pre></li> +<li><p>Create chroot on the <em>build</em> system, configuring it for <em>target</em> system:</p> +<pre><code>sudo qemu-debootstrap --arch=arm64 --verbose \ + --include=fakeroot,build-essential,libx11-dev,libxext-dev,libxrender-dev,libxtst-dev,libxt-dev,libcups2-dev,libfontconfig1-dev,libasound2-dev,libfreetype6-dev,libpng12-dev \ + --resolve-deps jessie /chroots/arm64 http://httpredir.debian.org/debian/</code></pre></li> +<li><p>Configure and build with newly created chroot as sysroot/toolchain-path:</p> +<pre><code>CC=aarch64-linux-gnu-gcc CXX=aarch64-linux-gnu-g++ sh ./configure --openjdk-target=aarch64-linux-gnu --with-sysroot=/chroots/arm64/ --with-toolchain-path=/chroots/arm64/ +make images +ls build/linux-aarch64-normal-server-release/</code></pre></li> +</ul> +<p>The build does not create new files in that chroot, so it can be reused for multiple builds without additional cleanup.</p> +<p>Architectures that are known to successfully cross-compile like this are:</p> +<table> +<thead> +<tr class="header"> +<th style="text-align: left;">Target</th> +<th style="text-align: left;"><code>CC</code></th> +<th style="text-align: left;"><code>CXX</code></th> +<th><code>--arch=...</code></th> +<th><code>--openjdk-target=...</code></th> +</tr> +</thead> +<tbody> +<tr class="odd"> +<td style="text-align: left;">x86</td> +<td style="text-align: left;">default</td> +<td style="text-align: left;">default</td> +<td>i386</td> +<td>i386-linux-gnu</td> +</tr> +<tr class="even"> +<td style="text-align: left;">armhf</td> +<td style="text-align: left;">gcc-arm-linux-gnueabihf</td> +<td style="text-align: left;">g++-arm-linux-gnueabihf</td> +<td>armhf</td> +<td>arm-linux-gnueabihf</td> +</tr> +<tr class="odd"> +<td style="text-align: left;">aarch64</td> +<td style="text-align: left;">gcc-aarch64-linux-gnu</td> +<td style="text-align: left;">g++-aarch64-linux-gnu</td> +<td>arm64</td> +<td>aarch64-linux-gnu</td> +</tr> +<tr class="even"> +<td style="text-align: left;">ppc64el</td> +<td style="text-align: left;">gcc-powerpc64le-linux-gnu</td> +<td style="text-align: left;">g++-powerpc64le-linux-gnu</td> +<td>ppc64el</td> +<td>powerpc64le-linux-gnu</td> +</tr> +<tr class="odd"> +<td style="text-align: left;">s390x</td> +<td style="text-align: left;">gcc-s390x-linux-gnu</td> +<td style="text-align: left;">g++-s390x-linux-gnu</td> +<td>s390x</td> +<td>s390x-linux-gnu</td> +</tr> +</tbody> +</table> +<p>Additional architectures might be supported by Debian/Ubuntu Ports.</p> <h3 id="building-for-armaarch64">Building for ARM/aarch64</h3> <p>A common cross-compilation target is the ARM CPU. When building for ARM, it is useful to set the ABI profile. A number of pre-defined ABI profiles are available using <code>--with-abi-profile</code>: arm-vfp-sflt, arm-vfp-hflt, arm-sflt, armv5-vfp-sflt, armv6-vfp-hflt. Note that soft-float ABIs are no longer properly supported by the JDK.</p> <p>The JDK contains two different ports for the aarch64 platform, one is the original aarch64 port from the <a href="http://openjdk.java.net/projects/aarch64-port">AArch64 Port Project</a> and one is a 64-bit version of the Oracle contributed ARM port. When targeting aarch64, by the default the original aarch64 port is used. To select the Oracle ARM 64 port, use <code>--with-cpu-port=arm64</code>. Also set the corresponding value (<code>aarch64</code> or <code>arm64</code>) to --with-abi-profile, to ensure a consistent build.</p> @@ -680,14 +791,14 @@ === Output from failing command(s) repeated here === * For target hotspot_variant-server_libjvm_objs_psMemoryPool.o: -/localhome/hg/jdk9-sandbox/hotspot/src/share/vm/services/psMemoryPool.cpp:1:1: error: 'failhere' does not name a type +/localhome/git/jdk-sandbox/hotspot/src/share/vm/services/psMemoryPool.cpp:1:1: error: 'failhere' does not name a type ... (rest of output omitted) -* All command lines available in /localhome/hg/jdk9-sandbox/build/linux-x64/make-support/failure-logs. +* All command lines available in /localhome/git/jdk-sandbox/build/linux-x64/make-support/failure-logs. === End of repeated output === === Make failed targets repeated here === -lib/CompileJvm.gmk:207: recipe for target '/localhome/hg/jdk9-sandbox/build/linux-x64/hotspot/variant-server/libjvm/objs/psMemoryPool.o' failed +lib/CompileJvm.gmk:207: recipe for target '/localhome/git/jdk-sandbox/build/linux-x64/hotspot/variant-server/libjvm/objs/psMemoryPool.o' failed make/Main.gmk:263: recipe for target 'hotspot-server-libs' failed === End of repeated output === @@ -710,11 +821,11 @@ <p>Verify that the summary at the end looks correct. Are you indeed using the Boot JDK and native toolchain that you expect?</p> <p>By default, the JDK has a strict approach where warnings from the compiler is considered errors which fail the build. For very new or very old compiler versions, this can trigger new classes of warnings, which thus fails the build. Run <code>configure</code> with <code>--disable-warnings-as-errors</code> to turn of this behavior. (The warnings will still show, but not make the build fail.)</p> <h4 id="problems-with-incremental-rebuilds">Problems with Incremental Rebuilds</h4> -<p>Incremental rebuilds mean that when you modify part of the product, only the affected parts get rebuilt. While this works great in most cases, and significantly speed up the development process, from time to time complex interdependencies will result in an incorrect build result. This is the most common cause for unexpected build problems, together with inconsistencies between the different Mercurial repositories in the forest.</p> +<p>Incremental rebuilds mean that when you modify part of the product, only the affected parts get rebuilt. While this works great in most cases, and significantly speed up the development process, from time to time complex interdependencies will result in an incorrect build result. This is the most common cause for unexpected build problems.</p> <p>Here are a suggested list of things to try if you are having unexpected build problems. Each step requires more time than the one before, so try them in order. Most issues will be solved at step 1 or 2.</p> <ol type="1"> -<li><p>Make sure your forest is up-to-date</p> -<p>Run <code>bash get_source.sh</code> to make sure you have the latest version of all repositories.</p></li> +<li><p>Make sure your repository is up-to-date</p> +<p>Run <code>git pull origin master</code> to make sure you have the latest changes.</p></li> <li><p>Clean build results</p> <p>The simplest way to fix incremental rebuild issues is to run <code>make clean</code>. This will remove all build results, but not the configuration or any build system support artifacts. In most cases, this will solve build errors resulting from incremental build mismatches.</p></li> <li><p>Completely clean the build directory.</p> @@ -723,8 +834,8 @@ make dist-clean bash configure $(cat current-configuration) make</code></pre></li> -<li><p>Re-clone the Mercurial forest</p> -<p>Sometimes the Mercurial repositories themselves gets in a state that causes the product to be un-buildable. In such a case, the simplest solution is often the "sledgehammer approach": delete the entire forest, and re-clone it. If you have local changes, save them first to a different location using <code>hg export</code>.</p></li> +<li><p>Re-clone the Git repository</p> +<p>Sometimes the Git repository gets in a state that causes the product to be un-buildable. In such a case, the simplest solution is often the "sledgehammer approach": delete the entire repository, and re-clone it. If you have local changes, save them first to a different location using <code>git format-patch</code>.</p></li> </ol> <h3 id="specific-build-issues">Specific Build Issues</h3> <h4 id="clock-skew">Clock Skew</h4> @@ -746,20 +857,6 @@ <p>If none of the suggestions in this document helps you, or if you find what you believe is a bug in the build system, please contact the Build Group by sending a mail to <a href="mailto:build-dev@openjdk.java.net">build-dev@openjdk.java.net</a>. Please include the relevant parts of the configure and/or build log.</p> <p>If you need general help or advice about developing for the JDK, you can also contact the Adoption Group. See the section on <a href="#contributing-to-openjdk">Contributing to OpenJDK</a> for more information.</p> <h2 id="hints-and-suggestions-for-advanced-users">Hints and Suggestions for Advanced Users</h2> -<h3 id="setting-up-a-forest-for-pushing-changes-defpath">Setting Up a Forest for Pushing Changes (defpath)</h3> -<p>To help you prepare a proper push path for a Mercurial repository, there exists a useful tool known as <a href="http://openjdk.java.net/projects/code-tools/defpath">defpath</a>. It will help you setup a proper push path for pushing changes to the JDK.</p> -<p>Install the extension by cloning <code>http://hg.openjdk.java.net/code-tools/defpath</code> and updating your <code>.hgrc</code> file. Here's one way to do this:</p> -<pre><code>cd ~ -mkdir hg-ext -cd hg-ext -hg clone http://hg.openjdk.java.net/code-tools/defpath -cat << EOT >> ~/.hgrc -[extensions] -defpath=~/hg-ext/defpath/defpath.py -EOT</code></pre> -<p>You can now setup a proper push path using:</p> -<pre><code>hg defpath -d -u <your OpenJDK username></code></pre> -<p>If you also have the <code>trees</code> extension installed in Mercurial, you will automatically get a <code>tdefpath</code> command, which is even more useful. By running <code>hg tdefpath -du <username></code> in the top repository of your forest, all repos will get setup automatically. This is the recommended usage.</p> <h3 id="bash-completion">Bash Completion</h3> <p>The <code>configure</code> and <code>make</code> commands tries to play nice with bash command-line completion (using <code><tab></code> or <code><tab><tab></code>). To use this functionality, make sure you enable completion in your <code>~/.bashrc</code> (see instructions for bash in your operating system).</p> <p>Make completion will work out of the box, and will complete valid make targets. For instance, typing <code>make jdk-i<tab></code> will complete to <code>make jdk-image</code>.</p> @@ -813,14 +910,6 @@ <h4 id="rebuilding-part-of-java.base-jdk_filter">Rebuilding Part of java.base (JDK_FILTER)</h4> <p>If you are modifying files in <code>java.base</code>, which is the by far largest module in the JDK, then you need to rebuild all those files whenever a single file has changed. (This inefficiency will hopefully be addressed in JDK 10.)</p> <p>As a hack, you can use the make control variable <code>JDK_FILTER</code> to specify a pattern that will be used to limit the set of files being recompiled. For instance, <code>make java.base JDK_FILTER=javax/crypto</code> (or, to combine methods, <code>make java.base-java-only JDK_FILTER=javax/crypto</code>) will limit the compilation to files in the <code>javax.crypto</code> package.</p> -<h3 id="learn-about-mercurial">Learn About Mercurial</h3> -<p>To become an efficient JDK developer, it is recommended that you invest in learning Mercurial properly. Here are some links that can get you started:</p> -<ul> -<li><a href="http://www.mercurial-scm.org/wiki/GitConcepts">Mercurial for git users</a></li> -<li><a href="http://www.mercurial-scm.org/wiki/Tutorial">The official Mercurial tutorial</a></li> -<li><a href="http://hginit.com/">hg init</a></li> -<li><a href="http://hgbook.red-bean.com/read/">Mercurial: The Definitive Guide</a></li> -</ul> <h2 id="understanding-the-build-system">Understanding the Build System</h2> <p>This section will give you a more technical description on the details of the build system.</p> <h3 id="configurations">Configurations</h3>
diff --git a/doc/building.md b/doc/building.md index e5990a7..c15389b 100644 --- a/doc/building.md +++ b/doc/building.md
@@ -3,11 +3,11 @@ ## TL;DR (Instructions for the Impatient) If you are eager to try out building the JDK, these simple steps works most of -the time. They assume that you have installed Mercurial (and Cygwin if running +the time. They assume that you have installed Git (and Cygwin if running on Windows) and cloned the top-level JDK repository that you want to build. 1. [Get the complete source code](#getting-the-source-code): \ - `hg clone http://hg.openjdk.java.net/jdk/jdk` + `git clone https://git.openjdk.java.net/jdk/` 2. [Run configure](#running-configure): \ `bash configure` @@ -47,14 +47,14 @@ Make sure you are getting the correct version. As of JDK 10, the source is no longer split into separate repositories so you only need to clone one single -repository. At the [OpenJDK Mercurial server](http://hg.openjdk.java.net/) you -can see a list of all available forests. If you want to build an older version, +repository. At the [OpenJDK Git site](https://git.openjdk.java.net/) you +can see a list of all available repositories. If you want to build an older version, e.g. JDK 8, it is recommended that you get the `jdk8u` forest, which contains incremental updates, instead of the `jdk8` forest, which was frozen at JDK 8 GA. -If you are new to Mercurial, a good place to start is the [Mercurial Beginner's -Guide](http://www.mercurial-scm.org/guide). The rest of this document assumes a -working knowledge of Mercurial. +If you are new to Git, a good place to start is the book [Pro +Git](https://git-scm.com/book/en/v2). The rest of this document +assumes a working knowledge of Git. ### Special Considerations @@ -89,9 +89,21 @@ directory. This is especially important if your user name contains spaces and/or mixed upper and lower case letters. - * Clone the JDK repository using the Cygwin command line `hg` client - as instructed in this document. That is, do *not* use another Mercurial - client such as TortoiseHg. + * You need to install a git client. You have two choices, Cygwin git or + Git for Windows. Unfortunately there are pros and cons with each choice. + + * The Cygwin `git` client has no line ending issues and understands + Cygwin paths (which are used throughout the JDK build system). + However, it does not currently work well with the Skara CLI tooling. + Please see the [Skara wiki on Git clients]( + https://wiki.openjdk.java.net/display/SKARA/Skara#Skara-Git) for + up-to-date information about the Skara git client support. + + * The [Git for Windows](https://gitforwindows.org) client has issues + with line endings, and do not understand Cygwin paths. It does work + well with the Skara CLI tooling, however. To alleviate the line ending + problems, make sure you set `core.autocrlf` to `false` (this is asked + during installation). Failure to follow this procedure might result in hard-to-debug build problems. @@ -171,7 +183,7 @@ require effort to implement.) Internally in the build system, all paths are represented as Unix-style paths, -e.g. `/cygdrive/c/hg/jdk9/Makefile` rather than `C:\hg\jdk9\Makefile`. This +e.g. `/cygdrive/c/git/jdk/Makefile` rather than `C:\git\jdk\Makefile`. This rule also applies to input to the build system, e.g. in arguments to `configure`. So, use `--with-msvcr-dll=/cygdrive/c/msvcr100.dll` rather than `--with-msvcr-dll=c:\msvcr100.dll`. For details on this conversion, see the section @@ -293,7 +305,7 @@ Linux gcc 7.3.0 macOS Apple Xcode 9.4 (using clang 9.1.0) Solaris Oracle Solaris Studio 12.4 (with compiler version 5.13) - Windows Microsoft Visual Studio 2017 update 15.5.5 + Windows Microsoft Visual Studio 2017 update 15.9.16 ### gcc @@ -371,7 +383,7 @@ The minimum accepted version of Visual Studio is 2010. Older versions will not be accepted by `configure`. The maximum accepted version of Visual Studio is -2017. Versions older than 2017 are unlikely to continue working for long. +2019. Versions older than 2017 are unlikely to continue working for long. If you have multiple versions of Visual Studio installed, `configure` will by default pick the latest. You can request a specific version to be used by @@ -436,8 +448,8 @@ path to it. There are two forms of the `configure` arguments to point to an external library: `--with-<LIB>=<path>` or `--with-<LIB>-include=<path to include> --with-<LIB>-lib=<path to lib>`. The first variant is more concise, -but require the include files an library files to reside in a default hierarchy -under this directory. In most cases, it works fine. +but require the include files and library files to reside in a default +hierarchy under this directory. In most cases, it works fine. As a fallback, the second version allows you to point to the include directory and the lib directory separately. @@ -447,7 +459,7 @@ FreeType2 from [The FreeType Project](http://www.freetype.org/) is not required on any platform. The exception is on Unix-based platforms when configuring such that the build artifacts will reference a system installed library, -rather than bundling the JDK’s own copy. +rather than bundling the JDK's own copy. * To install on an apt-based Linux, try running `sudo apt-get install libfreetype6-dev`. @@ -586,8 +598,8 @@ This will create an output directory containing the configuration and setup an area for the build result. This directory typically looks like -`build/linux-x64-normal-server-release`, but the actual name depends on your -specific configuration. (It can also be set directly, see [Using Multiple +`build/linux-x64-server-release`, but the actual name depends on your specific +configuration. (It can also be set directly, see [Using Multiple Configurations](#using-multiple-configurations)). This directory is referred to as `$BUILD` in this documentation. @@ -875,6 +887,64 @@ full-blown cross-compilation. (While this surely is possible, it's a lot more work and will take much longer to build.) +### Cross compiling the easy way with OpenJDK devkits + +The OpenJDK build system provides out-of-the box support for creating and using +so called devkits. A `devkit` is basically a collection of a cross-compiling +toolchain and a sysroot environment which can easily be used together with the +`--with-devkit` configure option to cross compile the OpenJDK. On Linux/x86_64, +the following command: +``` +bash configure --with-devkit=<devkit-path> --openjdk-target=ppc64-linux-gnu && make +``` + +will configure and build OpenJDK for Linux/ppc64 assuming that `<devkit-path>` +points to a Linux/x86_64 to Linux/ppc64 devkit. + +Devkits can be created from the `make/devkit` directory by executing: +``` +make [ TARGETS="<TARGET_TRIPLET>+" ] [ BASE_OS=<OS> ] [ BASE_OS_VERSION=<VER> ] +``` + +where `TARGETS` contains one or more `TARGET_TRIPLET`s of the form +described in [section 3.4 of the GNU Autobook]( +https://sourceware.org/autobook/autobook/autobook_17.html). If no +targets are given, a native toolchain for the current platform will be +created. Currently, at least the following targets are known to work: + + Supported devkit targets + ------------------------ + x86_64-linux-gnu + aarch64-linux-gnu + arm-linux-gnueabihf + ppc64-linux-gnu + ppc64le-linux-gnu + s390x-linux-gnu + +`BASE_OS` must be one of "OEL6" for Oracle Enterprise Linux 6 or +"Fedora" (if not specified "OEL6" will be the default). If the base OS +is "Fedora" the corresponding Fedora release can be specified with the +help of the `BASE_OS_VERSION` option (with "27" as default version). +If the build is successful, the new devkits can be found in the +`build/devkit/result` subdirectory: +``` +cd make/devkit +make TARGETS="ppc64le-linux-gnu aarch64-linux-gnu" BASE_OS=Fedora BASE_OS_VERSION=21 +ls -1 ../../build/devkit/result/ +x86_64-linux-gnu-to-aarch64-linux-gnu +x86_64-linux-gnu-to-ppc64le-linux-gnu +``` + +Notice that devkits are not only useful for targeting different build +platforms. Because they contain the full build dependencies for a +system (i.e. compiler and root file system), they can easily be used +to build well-known, reliable and reproducible build environments. You +can for example create and use a devkit with GCC 7.3 and a Fedora 12 +sysroot environment (with glibc 2.11) on Ubuntu 14.04 (which doesn't +have GCC 7.3 by default) to produce OpenJDK binaries which will run on +all Linux systems with runtime libraries newer than the ones from +Fedora 12 (e.g. Ubuntu 16.04, SLES 11 or RHEL 6). + ### Boot JDK and Build JDK When cross-compiling, make sure you use a boot JDK that runs on the *build* @@ -1018,6 +1088,51 @@ * If the X11 libraries are not properly detected by `configure`, you can point them out by `--with-x`. +### Creating And Using Sysroots With qemu-deboostrap + +Fortunately, you can create sysroots for foreign architectures with tools +provided by your OS. On Debian/Ubuntu systems, one could use `qemu-deboostrap` to +create the *target* system chroot, which would have the native libraries and headers +specific to that *target* system. After that, we can use the cross-compiler on the *build* +system, pointing into chroot to get the build dependencies right. This allows building +for foreign architectures with native compilation speed. + +For example, cross-compiling to AArch64 from x86_64 could be done like this: + + * Install cross-compiler on the *build* system: +``` +apt install g++-aarch64-linux-gnu gcc-aarch64-linux-gnu +``` + + * Create chroot on the *build* system, configuring it for *target* system: +``` +sudo qemu-debootstrap --arch=arm64 --verbose \ + --include=fakeroot,build-essential,libx11-dev,libxext-dev,libxrender-dev,libxtst-dev,libxt-dev,libcups2-dev,libfontconfig1-dev,libasound2-dev,libfreetype6-dev,libpng12-dev \ + --resolve-deps jessie /chroots/arm64 http://httpredir.debian.org/debian/ +``` + + * Configure and build with newly created chroot as sysroot/toolchain-path: +``` +CC=aarch64-linux-gnu-gcc CXX=aarch64-linux-gnu-g++ sh ./configure --openjdk-target=aarch64-linux-gnu --with-sysroot=/chroots/arm64/ --with-toolchain-path=/chroots/arm64/ +make images +ls build/linux-aarch64-normal-server-release/ +``` + +The build does not create new files in that chroot, so it can be reused for multiple builds +without additional cleanup. + +Architectures that are known to successfully cross-compile like this are: + + Target `CC` `CXX` `--arch=...` `--openjdk-target=...` + ------------ ------------------------- --------------------------- ------------ ---------------------- + x86 default default i386 i386-linux-gnu + armhf gcc-arm-linux-gnueabihf g++-arm-linux-gnueabihf armhf arm-linux-gnueabihf + aarch64 gcc-aarch64-linux-gnu g++-aarch64-linux-gnu arm64 aarch64-linux-gnu + ppc64el gcc-powerpc64le-linux-gnu g++-powerpc64le-linux-gnu ppc64el powerpc64le-linux-gnu + s390x gcc-s390x-linux-gnu g++-s390x-linux-gnu s390x s390x-linux-gnu + +Additional architectures might be supported by Debian/Ubuntu Ports. + ### Building for ARM/aarch64 A common cross-compilation target is the ARM CPU. When building for ARM, it is @@ -1158,14 +1273,14 @@ === Output from failing command(s) repeated here === * For target hotspot_variant-server_libjvm_objs_psMemoryPool.o: -/localhome/hg/jdk9-sandbox/hotspot/src/share/vm/services/psMemoryPool.cpp:1:1: error: 'failhere' does not name a type +/localhome/git/jdk-sandbox/hotspot/src/share/vm/services/psMemoryPool.cpp:1:1: error: 'failhere' does not name a type ... (rest of output omitted) -* All command lines available in /localhome/hg/jdk9-sandbox/build/linux-x64/make-support/failure-logs. +* All command lines available in /localhome/git/jdk-sandbox/build/linux-x64/make-support/failure-logs. === End of repeated output === === Make failed targets repeated here === -lib/CompileJvm.gmk:207: recipe for target '/localhome/hg/jdk9-sandbox/build/linux-x64/hotspot/variant-server/libjvm/objs/psMemoryPool.o' failed +lib/CompileJvm.gmk:207: recipe for target '/localhome/git/jdk-sandbox/build/linux-x64/hotspot/variant-server/libjvm/objs/psMemoryPool.o' failed make/Main.gmk:263: recipe for target 'hotspot-server-libs' failed === End of repeated output === @@ -1255,17 +1370,15 @@ affected parts get rebuilt. While this works great in most cases, and significantly speed up the development process, from time to time complex interdependencies will result in an incorrect build result. This is the most -common cause for unexpected build problems, together with inconsistencies -between the different Mercurial repositories in the forest. +common cause for unexpected build problems. Here are a suggested list of things to try if you are having unexpected build problems. Each step requires more time than the one before, so try them in order. Most issues will be solved at step 1 or 2. - 1. Make sure your forest is up-to-date + 1. Make sure your repository is up-to-date - Run `bash get_source.sh` to make sure you have the latest version of all - repositories. + Run `git pull origin master` to make sure you have the latest changes. 2. Clean build results @@ -1290,13 +1403,13 @@ make ``` - 4. Re-clone the Mercurial forest + 4. Re-clone the Git repository - Sometimes the Mercurial repositories themselves gets in a state that causes - the product to be un-buildable. In such a case, the simplest solution is - often the "sledgehammer approach": delete the entire forest, and re-clone - it. If you have local changes, save them first to a different location - using `hg export`. + Sometimes the Git repository gets in a state that causes the product + to be un-buildable. In such a case, the simplest solution is often the + "sledgehammer approach": delete the entire repository, and re-clone it. + If you have local changes, save them first to a different location using + `git format-patch`. ### Specific Build Issues @@ -1347,38 +1460,6 @@ ## Hints and Suggestions for Advanced Users -### Setting Up a Forest for Pushing Changes (defpath) - -To help you prepare a proper push path for a Mercurial repository, there exists -a useful tool known as [defpath]( -http://openjdk.java.net/projects/code-tools/defpath). It will help you setup a -proper push path for pushing changes to the JDK. - -Install the extension by cloning -`http://hg.openjdk.java.net/code-tools/defpath` and updating your `.hgrc` file. -Here's one way to do this: - -``` -cd ~ -mkdir hg-ext -cd hg-ext -hg clone http://hg.openjdk.java.net/code-tools/defpath -cat << EOT >> ~/.hgrc -[extensions] -defpath=~/hg-ext/defpath/defpath.py -EOT -``` - -You can now setup a proper push path using: -``` -hg defpath -d -u <your OpenJDK username> -``` - -If you also have the `trees` extension installed in Mercurial, you will -automatically get a `tdefpath` command, which is even more useful. By running -`hg tdefpath -du <username>` in the top repository of your forest, all repos -will get setup automatically. This is the recommended usage. - ### Bash Completion The `configure` and `make` commands tries to play nice with bash command-line @@ -1521,16 +1602,6 @@ `make java.base-java-only JDK_FILTER=javax/crypto`) will limit the compilation to files in the `javax.crypto` package. -### Learn About Mercurial - -To become an efficient JDK developer, it is recommended that you invest in -learning Mercurial properly. Here are some links that can get you started: - - * [Mercurial for git users](http://www.mercurial-scm.org/wiki/GitConcepts) - * [The official Mercurial tutorial](http://www.mercurial-scm.org/wiki/Tutorial) - * [hg init](http://hginit.com/) - * [Mercurial: The Definitive Guide](http://hgbook.red-bean.com/read/) - ## Understanding the Build System This section will give you a more technical description on the details of the
diff --git a/doc/ide.html b/doc/ide.html new file mode 100644 index 0000000..1730eb0 --- /dev/null +++ b/doc/ide.html
@@ -0,0 +1,54 @@ +<!DOCTYPE html> +<html xmlns="http://www.w3.org/1999/xhtml" lang="" xml:lang=""> +<head> + <meta charset="utf-8" /> + <meta name="generator" content="pandoc" /> + <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" /> + <title>IDE support in the JDK</title> + <style type="text/css"> + code{white-space: pre-wrap;} + span.smallcaps{font-variant: small-caps;} + span.underline{text-decoration: underline;} + div.column{display: inline-block; vertical-align: top; width: 50%;} + </style> + <link rel="stylesheet" href="../make/data/docs-resources/resources/jdk-default.css" /> + <!--[if lt IE 9]> + <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script> + <![endif]--> +</head> +<body> +<header id="title-block-header"> +<h1 class="title">IDE support in the JDK</h1> +</header> +<nav id="TOC"> +<ul> +<li><a href="#introduction">Introduction</a><ul> +<li><a href="#ide-support-for-native-code">IDE support for native code</a></li> +<li><a href="#ide-support-for-java-code">IDE support for Java code</a></li> +</ul></li> +</ul> +</nav> +<h2 id="introduction">Introduction</h2> +<p>When you are familiar with building and testing the JDK, you may want to configure an IDE to work with the source code. The instructions differ a bit depending on whether you are interested in working with the native (C/C++) or the Java code.</p> +<h3 id="ide-support-for-native-code">IDE support for native code</h3> +<p>There are a few ways to generate IDE configuration for the native sources, depending on which IDE to use.</p> +<h4 id="visual-studio-code">Visual Studio Code</h4> +<p>The make system can generate a <a href="https://code.visualstudio.com">Visual Studio Code</a> workspace that has C/C++ source indexing configured correctly, as well as launcher targets for tests and the Java launcher. After configuring, a workspace for the configuration can be generated using:</p> +<pre class="shell"><code>make vscode-project</code></pre> +<p>This creates a file called <code>jdk.code-workspace</code> in the build output folder. The full location will be printed after the workspace has been generated. To use it, choose <code>File -> Open Workspace...</code> in Visual Studio Code.</p> +<h5 id="alternative-indexers">Alternative indexers</h5> +<p>The main <code>vscode-project</code> target configures the default C++ support in Visual Studio Code. There are also other source indexers that can be installed, that may provide additional features. It's currently possible to generate configuration for two such indexers, <a href="https://clang.llvm.org/extra/clangd/">clangd</a> and <a href="https://github.com/Andersbakken/rtags">rtags</a>. These can be configured by appending the name of the indexer to the make target, such as:</p> +<pre class="shell"><code>make vscode-project-clangd</code></pre> +<p>Additional instructions for configuring the given indexer will be displayed after the workspace has been generated.</p> +<h4 id="visual-studio">Visual Studio</h4> +<p>This section is a work in progress.</p> +<pre class="shell"><code>make ide-project</code></pre> +<h4 id="compilation-database">Compilation Database</h4> +<p>The make system can generate generic native code indexing support in the form of a <a href="https://clang.llvm.org/docs/JSONCompilationDatabase.html">Compilation Database</a> that can be used by many different IDEs and source code indexers.</p> +<pre class="shell"><code>make compile-commands</code></pre> +<p>It's also possible to generate the Compilation Database for the HotSpot source code only, which is a bit faster as it includes less information.</p> +<pre class="shell"><code>make compile-commands-hotspot</code></pre> +<h3 id="ide-support-for-java-code">IDE support for Java code</h3> +<p>This section is a work in progress.</p> +</body> +</html>
diff --git a/doc/ide.md b/doc/ide.md new file mode 100644 index 0000000..4a692ef --- /dev/null +++ b/doc/ide.md
@@ -0,0 +1,73 @@ +% IDE support in the JDK + +## Introduction + +When you are familiar with building and testing the JDK, you may want to +configure an IDE to work with the source code. The instructions differ a bit +depending on whether you are interested in working with the native (C/C++) or +the Java code. + +### IDE support for native code + +There are a few ways to generate IDE configuration for the native sources, +depending on which IDE to use. + +#### Visual Studio Code + +The make system can generate a [Visual Studio Code](https://code.visualstudio.com) +workspace that has C/C++ source indexing configured correctly, as well as +launcher targets for tests and the Java launcher. After configuring, a workspace +for the configuration can be generated using: + +```shell +make vscode-project +``` + +This creates a file called `jdk.code-workspace` in the build output folder. The +full location will be printed after the workspace has been generated. To use it, +choose `File -> Open Workspace...` in Visual Studio Code. + +##### Alternative indexers + +The main `vscode-project` target configures the default C++ support in Visual +Studio Code. There are also other source indexers that can be installed, that +may provide additional features. It's currently possible to generate +configuration for two such indexers, [clangd](https://clang.llvm.org/extra/clangd/) +and [rtags](https://github.com/Andersbakken/rtags). These can be configured by +appending the name of the indexer to the make target, such as: + +```shell +make vscode-project-clangd +``` + +Additional instructions for configuring the given indexer will be displayed +after the workspace has been generated. + +#### Visual Studio + +This section is a work in progress. + +```shell +make ide-project +``` + +#### Compilation Database + +The make system can generate generic native code indexing support in the form of +a [Compilation Database](https://clang.llvm.org/docs/JSONCompilationDatabase.html) +that can be used by many different IDEs and source code indexers. + +```shell +make compile-commands +``` + +It's also possible to generate the Compilation Database for the HotSpot source +code only, which is a bit faster as it includes less information. + +```shell +make compile-commands-hotspot +``` + +### IDE support for Java code + +This section is a work in progress. \ No newline at end of file
diff --git a/doc/testing.html b/doc/testing.html index 1c5a4cc..6c8cc32 100644 --- a/doc/testing.html +++ b/doc/testing.html
@@ -11,14 +11,14 @@ span.underline{text-decoration: underline;} div.column{display: inline-block; vertical-align: top; width: 50%;} </style> - <link rel="stylesheet" href="../make/data/docs-resources/resources/jdk-default.css"> + <link rel="stylesheet" href="../make/data/docs-resources/resources/jdk-default.css" /> <!--[if lt IE 9]> <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script> <![endif]--> <style type="text/css">pre, code, tt { color: #1d6ae5; }</style> </head> <body> -<header> +<header id="title-block-header"> <h1 class="title">Testing the JDK</h1> </header> <nav id="TOC"> @@ -32,9 +32,14 @@ </ul></li> <li><a href="#test-results-and-summary">Test results and summary</a></li> <li><a href="#test-suite-control">Test suite control</a><ul> +<li><a href="#general-keywords-test_opts">General keywords (TEST_OPTS)</a></li> <li><a href="#jtreg-keywords">JTReg keywords</a></li> <li><a href="#gtest-keywords">Gtest keywords</a></li> </ul></li> +<li><a href="#notes-for-specific-tests">Notes for Specific Tests</a><ul> +<li><a href="#docker-tests">Docker Tests</a></li> +<li><a href="#client-ui-tests">Client UI Tests</a></li> +</ul></li> </ul> </nav> <h2 id="using-the-run-test-framework">Using the run-test framework</h2> @@ -86,11 +91,24 @@ <p>To separate multiple keyword=value pairs, use <code>;</code> (semicolon). Since the shell normally eats <code>;</code>, the recommended usage is to write the assignment inside qoutes, e.g. <code>JTREG="...;..."</code>. This will also make sure spaces are preserved, as in <code>JTREG="VM_OPTIONS=-XshowSettings -Xlog:gc+ref=debug"</code>.</p> <p>(Other ways are possible, e.g. using backslash: <code>JTREG=JOBS=1\;TIMEOUT=8</code>. Also, as a special technique, the string <code>%20</code> will be replaced with space for certain options, e.g. <code>JTREG=VM_OPTIONS=-XshowSettings%20-Xlog:gc+ref=debug</code>. This can be useful if you have layers of scripts and have trouble getting proper quoting of command line arguments through.)</p> <p>As far as possible, the names of the keywords have been standardized between test suites.</p> -<h3 id="jtreg-keywords">JTReg keywords</h3> +<h3 id="general-keywords-test_opts">General keywords (TEST_OPTS)</h3> +<p>Some keywords are valid across different test suites. If you want to run tests from multiple test suites, or just don’t want to care which test suite specific control variable to use, then you can use the general TEST_OPTS control variable.</p> +<p>There are also some keywords that applies globally to the test runner system, not to any specific test suites. These are also available as TEST_OPTS keywords.</p> <h4 id="jobs">JOBS</h4> +<p>Currently only applies to JTReg.</p> +<h4 id="timeout_factor">TIMEOUT_FACTOR</h4> +<p>Currently only applies to JTReg.</p> +<h4 id="vm_options">VM_OPTIONS</h4> +<p>Applies to JTReg, GTest and Micro.</p> +<h4 id="java_options">JAVA_OPTIONS</h4> +<p>Applies to JTReg, GTest and Micro.</p> +<h4 id="aot_modules">AOT_MODULES</h4> +<p>Applies to JTReg and GTest.</p> +<h3 id="jtreg-keywords">JTReg keywords</h3> +<h4 id="jobs-1">JOBS</h4> <p>The test concurrency (<code>-concurrency</code>).</p> <p>Defaults to TEST_JOBS (if set by <code>--with-test-jobs=</code>), otherwise it defaults to JOBS, except for Hotspot, where the default is <em>number of CPU cores/2</em>, but never more than 12.</p> -<h4 id="timeout">TIMEOUT</h4> +<h4 id="timeout_factor-1">TIMEOUT_FACTOR</h4> <p>The timeout factor (<code>-timeoutFactor</code>).</p> <p>Defaults to 4.</p> <h4 id="test_mode">TEST_MODE</h4> @@ -109,13 +127,21 @@ <p>Limit memory consumption (<code>-Xmx</code> and <code>-vmoption:-Xmx</code>, or none).</p> <p>Limit memory consumption for JTReg test framework and VM under test. Set to 0 to disable the limits.</p> <p>Defaults to 512m, except for hotspot, where it defaults to 0 (no limit).</p> +<h4 id="keywords">KEYWORDS</h4> +<p>JTReg kewords sent to JTReg using <code>-k</code>. Please be careful in making sure that spaces and special characters (like <code>!</code>) are properly quoted. To avoid some issues, the special value <code>%20</code> can be used instead of space.</p> +<h4 id="extra_problem_lists">EXTRA_PROBLEM_LISTS</h4> +<p>Use additional problem lists file or files, in addition to the default ProblemList.txt located at the JTReg test roots.</p> +<p>If multiple file names are specified, they should be separated by space (or, to help avoid quoting issues, the special value <code>%20</code>).</p> +<p>The file names should be either absolute, or relative to the JTReg test root of the tests to be run.</p> <h4 id="options">OPTIONS</h4> <p>Additional options to the JTReg test framework.</p> <p>Use <code>JTREG="OPTIONS=--help all"</code> to see all available JTReg options.</p> -<h4 id="java_options">JAVA_OPTIONS</h4> +<h4 id="java_options-1">JAVA_OPTIONS</h4> <p>Additional Java options to JTReg (<code>-javaoption</code>).</p> -<h4 id="vm_options">VM_OPTIONS</h4> +<h4 id="vm_options-1">VM_OPTIONS</h4> <p>Additional VM options to JTReg (<code>-vmoption</code>).</p> +<h4 id="aot_modules-1">AOT_MODULES</h4> +<p>Generate AOT modules before testing for the specified module, or set of modules. If multiple modules are specified, they should be separated by space (or, to help avoid quoting issues, the special value <code>%20</code>).</p> <h3 id="gtest-keywords">Gtest keywords</h3> <h4 id="repeat">REPEAT</h4> <p>The number of times to repeat the tests (<code>--gtest_repeat</code>).</p> @@ -123,5 +149,23 @@ <h4 id="options-1">OPTIONS</h4> <p>Additional options to the Gtest test framework.</p> <p>Use <code>GTEST="OPTIONS=--help"</code> to see all available Gtest options.</p> +<h4 id="aot_modules-2">AOT_MODULES</h4> +<p>Generate AOT modules before testing for the specified module, or set of modules. If multiple modules are specified, they should be separated by space (or, to help avoid quoting issues, the special value <code>%20</code>).</p> +<h2 id="notes-for-specific-tests">Notes for Specific Tests</h2> +<h3 id="docker-tests">Docker Tests</h3> +<p>Docker tests with default parameters may fail on systems with glibc versions not compatible with the one used in the default docker image (e.g., Oracle Linux 7.6 for x86). For example, they pass on Ubuntu 16.04 but fail on Ubuntu 18.04 if run like this on x86:</p> +<pre><code>$ make run-test TEST="jtreg:test/hotspot/jtreg/containers/docker"</code></pre> +<p>To run these tests correctly, additional parameters for the correct docker image are required on Ubuntu 18.04 by using <code>JAVA_OPTIONS</code>.</p> +<pre><code>$ make run-test TEST="jtreg:test/hotspot/jtreg/containers/docker" JTREG="JAVA_OPTIONS=-Djdk.test.docker.image.name=ubuntu -Djdk.test.docker.image.version=latest"</code></pre> +<h3 id="client-ui-tests">Client UI Tests</h3> +<p>Some Client UI tests use key sequences which may be reserved by the operating system. Usually that causes the test failure. So it is highly recommended to disable system key shortcuts prior testing. The steps to access and disable system key shortcuts for various platforms are provided below.</p> +<h4 id="macos">MacOS</h4> +<p>Choose Apple menu; System Preferences, click Keyboard, then click Shortcuts; select or deselect desired shortcut.</p> +<p>For example, test/jdk/javax/swing/TooltipManager/JMenuItemToolTipKeyBindingsTest/JMenuItemToolTipKeyBindingsTest.java fails on MacOS because it uses <code>CTRL + F1</code> key sequence to show or hide tooltip message but the key combination is reserved by the operating system. To run the test correctly the default global key shortcut should be disabled using the steps described above, and then deselect “Turn keyboard access on or off” option which is responsible for <code>CTRL + F1</code> combination.</p> +<h4 id="linux">Linux</h4> +<p>Open the Activities overview and start typing Settings; Choose Settings, click Devices, then click Keyboard; set or override desired shortcut.</p> +<h4 id="windows">Windows</h4> +<p>Type <code>gpedit</code> in the Search and then click Edit group policy; navigate to User Configuration -> Administrative Templates -> Windows Components -> File Explorer; in the right-side pane look for “Turn off Windows key hotkeys” and double click on it; enable or disable hotkeys.</p> +<p>Note: restart is required to make the settings take effect.</p> </body> </html>
diff --git a/doc/testing.md b/doc/testing.md index 7aa40a6..fe2b1c7 100644 --- a/doc/testing.md +++ b/doc/testing.md
@@ -162,6 +162,35 @@ As far as possible, the names of the keywords have been standardized between test suites. +### General keywords (TEST_OPTS) + +Some keywords are valid across different test suites. If you want to run +tests from multiple test suites, or just don't want to care which test suite specific +control variable to use, then you can use the general TEST_OPTS control variable. + +There are also some keywords that applies globally to the test runner system, +not to any specific test suites. These are also available as TEST_OPTS keywords. + +#### JOBS + +Currently only applies to JTReg. + +#### TIMEOUT_FACTOR + +Currently only applies to JTReg. + +#### VM_OPTIONS + +Applies to JTReg, GTest and Micro. + +#### JAVA_OPTIONS + +Applies to JTReg, GTest and Micro. + +#### AOT_MODULES + +Applies to JTReg and GTest. + ### JTReg keywords #### JOBS @@ -171,7 +200,7 @@ JOBS, except for Hotspot, where the default is *number of CPU cores/2*, but never more than 12. -#### TIMEOUT +#### TIMEOUT_FACTOR The timeout factor (`-timeoutFactor`). Defaults to 4. @@ -205,6 +234,24 @@ Defaults to 512m, except for hotspot, where it defaults to 0 (no limit). +#### KEYWORDS + +JTReg kewords sent to JTReg using `-k`. Please be careful in making sure that +spaces and special characters (like `!`) are properly quoted. To avoid some +issues, the special value `%20` can be used instead of space. + +#### EXTRA_PROBLEM_LISTS + +Use additional problem lists file or files, in addition to the default +ProblemList.txt located at the JTReg test roots. + +If multiple file names are specified, they should be separated by space (or, to +help avoid quoting issues, the special value `%20`). + +The file names should be either absolute, or relative to the JTReg test root of +the tests to be run. + + #### OPTIONS Additional options to the JTReg test framework. @@ -216,6 +263,12 @@ #### VM_OPTIONS Additional VM options to JTReg (`-vmoption`). +#### AOT_MODULES + +Generate AOT modules before testing for the specified module, or set of +modules. If multiple modules are specified, they should be separated by space +(or, to help avoid quoting issues, the special value `%20`). + ### Gtest keywords #### REPEAT @@ -230,6 +283,56 @@ Use `GTEST="OPTIONS=--help"` to see all available Gtest options. +#### AOT_MODULES + +Generate AOT modules before testing for the specified module, or set of +modules. If multiple modules are specified, they should be separated by space +(or, to help avoid quoting issues, the special value `%20`). + +## Notes for Specific Tests + +### Docker Tests + +Docker tests with default parameters may fail on systems with glibc versions not +compatible with the one used in the default docker image (e.g., Oracle Linux 7.6 for x86). +For example, they pass on Ubuntu 16.04 but fail on Ubuntu 18.04 if run like this on x86: + + $ make run-test TEST="jtreg:test/hotspot/jtreg/containers/docker" + +To run these tests correctly, additional parameters for the correct docker image are +required on Ubuntu 18.04 by using `JAVA_OPTIONS`. + + $ make run-test TEST="jtreg:test/hotspot/jtreg/containers/docker" JTREG="JAVA_OPTIONS=-Djdk.test.docker.image.name=ubuntu -Djdk.test.docker.image.version=latest" + +### Client UI Tests + +Some Client UI tests use key sequences which may be reserved by the operating +system. Usually that causes the test failure. So it is highly recommended to disable +system key shortcuts prior testing. The steps to access and disable system key shortcuts +for various platforms are provided below. + +#### MacOS +Choose Apple menu; System Preferences, click Keyboard, then click Shortcuts; +select or deselect desired shortcut. + +For example, test/jdk/javax/swing/TooltipManager/JMenuItemToolTipKeyBindingsTest/JMenuItemToolTipKeyBindingsTest.java fails +on MacOS because it uses `CTRL + F1` key sequence to show or hide tooltip message +but the key combination is reserved by the operating system. To run the test correctly +the default global key shortcut should be disabled using the steps described above, and then deselect +"Turn keyboard access on or off" option which is responsible for `CTRL + F1` combination. + +#### Linux +Open the Activities overview and start typing Settings; Choose Settings, click Devices, +then click Keyboard; set or override desired shortcut. + +#### Windows +Type `gpedit` in the Search and then click Edit group policy; navigate to +User Configuration -> Administrative Templates -> Windows Components -> File Explorer; +in the right-side pane look for "Turn off Windows key hotkeys" and double click on it; +enable or disable hotkeys. + +Note: restart is required to make the settings take effect. + --- # Override some definitions in the global css file that are not optimal for # this document.
diff --git a/make/Bundles.gmk b/make/Bundles.gmk index 5f14492..56d7dc8 100644 --- a/make/Bundles.gmk +++ b/make/Bundles.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2016, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -50,6 +50,7 @@ # files or directories may contain spaces. # BASE_DIRS : Base directories for the root dir in the bundle. # SUBDIR : Optional name of root dir in bundle. +# OUTPUTDIR : Optionally override output dir SetupBundleFile = $(NamedParamsMacroTemplate) define SetupBundleFileBody @@ -70,8 +71,11 @@ $$(call SetIfEmpty, $1_UNZIP_DEBUGINFO, false) - $(BUNDLES_OUTPUTDIR)/$$($1_BUNDLE_NAME): $$($1_FILES) - # If any of the files contain a space in the file name, CacheFind + $$(call SetIfEmpty, $1_OUTPUTDIR, $$(BUNDLES_OUTPUTDIR)) + + $$($1_OUTPUTDIR)/$$($1_BUNDLE_NAME): $$($1_FILES) + $$(call LogWarn, Creating $$($1_BUNDLE_NAME)) + # If any of the files contain a space in the file name, FindFiles # will have replaced it with ?. Tar does not accept that so need to # switch it back. $$(foreach d, $$($1_BASE_DIRS), \ @@ -121,6 +125,13 @@ && $(TAR) cf - -$(TAR_INCLUDE_PARAM) $$($1_$$d_LIST_FILE) \ $(TAR_IGNORE_EXIT_VALUE) ) \ | ( $(CD) $(SUPPORT_OUTPUTDIR)/bundles/$1/$$($1_SUBDIR) && $(TAR) xf - )$$(NEWLINE) ) + # Rename stripped pdb files + ifeq ($(OPENJDK_TARGET_OS)+$(SHIP_DEBUG_SYMBOLS), windows+public) + for f in `$(FIND) $(SUPPORT_OUTPUTDIR)/bundles/$1/$$($1_SUBDIR) -name "*.stripped.pdb"`; do \ + $(ECHO) Renaming $$$${f} to $$$${f%stripped.pdb}pdb $(LOG_INFO); \ + $(MV) $$$${f} $$$${f%stripped.pdb}pdb; \ + done + endif # Unzip any zipped debuginfo files ifeq ($$($1_UNZIP_DEBUGINFO), true) for f in `$(FIND) $(SUPPORT_OUTPUTDIR)/bundles/$1/$$($1_SUBDIR) -name "*.diz"`; do \ @@ -137,7 +148,7 @@ endif endif - $1 += $(BUNDLES_OUTPUTDIR)/$$($1_BUNDLE_NAME) + $1 += $$($1_OUTPUTDIR)/$$($1_BUNDLE_NAME) endef @@ -152,6 +163,12 @@ JRE_IMAGE_HOMEDIR := $(JRE_MACOSX_CONTENTS_DIR)/Home JDK_BUNDLE_SUBDIR := JRE_BUNDLE_SUBDIR := + # In certain situations, the JDK_IMAGE_DIR points to an image without the + # the symbols and demos. If so, the symobls and demos can be found in a + # separate image. These variables allow for overriding from a custom makefile. + JDK_SYMBOLS_IMAGE_DIR ?= $(JDK_IMAGE_DIR) + JDK_DEMOS_IMAGE_DIR ?= $(JDK_IMAGE_DIR) + JDK_DEMOS_IMAGE_HOMEDIR ?= $(JDK_DEMOS_IMAGE_DIR)/$(JDK_MACOSX_CONTENTS_SUBDIR)/Home else JDK_IMAGE_HOMEDIR := $(JDK_IMAGE_DIR) JRE_IMAGE_HOMEDIR := $(JRE_IMAGE_DIR) @@ -161,23 +178,56 @@ JDK_BUNDLE_SUBDIR := $(JDK_BUNDLE_SUBDIR)/$(DEBUG_LEVEL) JRE_BUNDLE_SUBDIR := $(JRE_BUNDLE_SUBDIR)/$(DEBUG_LEVEL) endif + # In certain situations, the JDK_IMAGE_DIR points to an image without the + # the symbols and demos. If so, the symobls and demos can be found in a + # separate image. These variables allow for overriding from a custom makefile. + JDK_SYMBOLS_IMAGE_DIR ?= $(JDK_IMAGE_DIR) + JDK_DEMOS_IMAGE_DIR ?= $(JDK_IMAGE_DIR) + JDK_DEMOS_IMAGE_HOMEDIR ?= $(JDK_DEMOS_IMAGE_DIR) endif ################################################################################ -ifneq ($(filter product-bundles legacy-bundles, $(MAKECMDGOALS)), ) - $(eval $(call FillCacheFind, $(IMAGES_OUTPUTDIR))) +ifneq ($(filter product-bundles% legacy-bundles, $(MAKECMDGOALS)), ) - SYMBOLS_EXCLUDE_PATTERN := %.debuginfo %.diz %.pdb %.map + SYMBOLS_EXCLUDE_PATTERN := %.debuginfo %.diz %.map - ALL_JDK_FILES := $(call CacheFind, $(JDK_IMAGE_DIR)) + # There may be files with spaces in the names, so use ShellFindFiles + # explicitly. + ALL_JDK_FILES := $(call ShellFindFiles, $(JDK_IMAGE_DIR)) + ifneq ($(JDK_IMAGE_DIR), $(JDK_SYMBOLS_IMAGE_DIR)) + ALL_JDK_SYMBOLS_FILES := $(call ShellFindFiles, $(JDK_SYMBOLS_IMAGE_DIR)) + else + ALL_JDK_SYMBOLS_FILES := $(ALL_JDK_FILES) + endif + ifneq ($(JDK_IMAGE_DIR), $(JDK_DEMOS_IMAGE_DIR)) + ALL_JDK_DEMOS_FILES := $(call ShellFindFiles, $(JDK_DEMOS_IMAGE_DIR)) + else + ALL_JDK_DEMOS_FILES := $(ALL_JDK_FILES) + endif # Create special filter rules when dealing with unzipped .dSYM directories on # macosx ifeq ($(OPENJDK_TARGET_OS), macosx) ifeq ($(ZIP_EXTERNAL_DEBUG_SYMBOLS), false) JDK_SYMBOLS_EXCLUDE_PATTERN := $(addprefix %, \ - $(call containing, .dSYM/, $(patsubst $(JDK_IMAGE_DIR)/%, %, $(ALL_JDK_FILES)))) + $(call containing, .dSYM/, $(patsubst $(JDK_IMAGE_DIR)/%, %, \ + $(ALL_JDK_SYMBOLS_FILES)))) + endif + endif + + # Create special filter rules when dealing with debug symbols on windows + ifeq ($(OPENJDK_TARGET_OS), windows) + ifeq ($(SHIP_DEBUG_SYMBOLS), ) + JDK_SYMBOLS_EXCLUDE_PATTERN := %.pdb + else + ifeq ($(SHIP_DEBUG_SYMBOLS), public) + JDK_SYMBOLS_EXCLUDE_PATTERN := \ + $(filter-out \ + %.stripped.pdb, \ + $(filter %.pdb, $(ALL_JDK_FILES)) \ + ) + endif endif endif @@ -190,22 +240,24 @@ , \ $(ALL_JDK_FILES) \ ) + JDK_SYMBOLS_BUNDLE_FILES := \ $(filter \ $(JDK_SYMBOLS_EXCLUDE_PATTERN) \ $(SYMBOLS_EXCLUDE_PATTERN) \ , \ $(filter-out \ - $(JDK_IMAGE_HOMEDIR)/demo/% \ + $(JDK_IMAGE_HOMEDIR)/demo/% %.stripped.pdb \ , \ - $(ALL_JDK_FILES) \ + $(ALL_JDK_SYMBOLS_FILES) \ ) \ ) \ - $(call CacheFind, $(SYMBOLS_IMAGE_DIR)) + $(call FindFiles, $(SYMBOLS_IMAGE_DIR)) - TEST_DEMOS_BUNDLE_FILES := $(filter $(JDK_IMAGE_HOMEDIR)/demo/%, $(ALL_JDK_FILES)) + TEST_DEMOS_BUNDLE_FILES := $(filter $(JDK_DEMOS_IMAGE_HOMEDIR)/demo/%, \ + $(ALL_JDK_DEMOS_FILES)) - ALL_JRE_FILES := $(call CacheFind, $(JRE_IMAGE_DIR)) + ALL_JRE_FILES := $(call ShellFindFiles, $(JRE_IMAGE_DIR)) # Create special filter rules when dealing with unzipped .dSYM directories on # macosx @@ -216,39 +268,128 @@ endif endif + # Create special filter rules when dealing with debug symbols on windows + ifeq ($(OPENJDK_TARGET_OS), windows) + ifeq ($(SHIP_DEBUG_SYMBOLS), ) + JRE_SYMBOLS_EXCLUDE_PATTERN := %.pdb + else + ifeq ($(SHIP_DEBUG_SYMBOLS), public) + JRE_SYMBOLS_EXCLUDE_PATTERN := \ + $(filter-out \ + %.stripped.pdb, \ + $(filter %.pdb, $(ALL_JRE_FILES)) \ + ) + endif + endif + endif + JRE_BUNDLE_FILES := $(filter-out \ $(JRE_SYMBOLS_EXCLUDE_PATTERN) \ $(SYMBOLS_EXCLUDE_PATTERN), \ $(ALL_JRE_FILES)) - $(eval $(call SetupBundleFile, BUILD_JDK_BUNDLE, \ - BUNDLE_NAME := $(JDK_BUNDLE_NAME), \ - FILES := $(JDK_BUNDLE_FILES), \ - SPECIAL_INCLUDES := $(JDK_SPECIAL_INCLUDES), \ - BASE_DIRS := $(JDK_IMAGE_DIR), \ - SUBDIR := $(JDK_BUNDLE_SUBDIR), \ - )) + # On Macosx release builds, when there is a code signing certificate available, + # the final bundle layout can be signed. + SIGN_BUNDLE := false + ifeq ($(OPENJDK_TARGET_OS)-$(DEBUG_LEVEL), macosx-release) + ifneq ($(CODESIGN), ) + SIGN_BUNDLE := true + endif + endif - PRODUCT_TARGETS += $(BUILD_JDK_BUNDLE) + ifeq ($(SIGN_BUNDLE), true) + # Macosx release build and code signing available. - $(eval $(call SetupBundleFile, BUILD_JRE_BUNDLE, \ - BUNDLE_NAME := $(JRE_BUNDLE_NAME), \ - FILES := $(JRE_BUNDLE_FILES), \ - BASE_DIRS := $(JRE_IMAGE_DIR), \ - SUBDIR := $(JRE_BUNDLE_SUBDIR), \ - )) + ################################################################################ + # JDK bundle + $(eval $(call SetupCopyFiles, CREATE_JDK_BUNDLE_DIR_SIGNED, \ + SRC := $(JDK_IMAGE_DIR), \ + FILES := $(JDK_BUNDLE_FILES), \ + DEST := $(JDK_MACOSX_BUNDLE_DIR_SIGNED), \ + )) - LEGACY_TARGETS += $(BUILD_JRE_BUNDLE) + JDK_SIGNED_CODE_RESOURCES := \ + $(JDK_MACOSX_BUNDLE_DIR_SIGNED)/$(JDK_MACOSX_CONTENTS_SUBDIR)/_CodeSignature/CodeResources - $(eval $(call SetupBundleFile, BUILD_JDK_SYMBOLS_BUNDLE, \ - BUNDLE_NAME := $(JDK_SYMBOLS_BUNDLE_NAME), \ - FILES := $(JDK_SYMBOLS_BUNDLE_FILES), \ - BASE_DIRS := $(JDK_IMAGE_DIR) $(wildcard $(SYMBOLS_IMAGE_DIR)), \ - SUBDIR := $(JDK_BUNDLE_SUBDIR), \ - UNZIP_DEBUGINFO := true, \ - )) + $(JDK_SIGNED_CODE_RESOURCES): $(CREATE_JDK_BUNDLE_DIR_SIGNED) + $(call LogWarn, Signing $(JDK_BUNDLE_NAME)) + $(CODESIGN) -s "$(MACOSX_CODESIGN_IDENTITY)" \ + --timestamp --options runtime --deep --force \ + $(JDK_MACOSX_BUNDLE_DIR_SIGNED)/$(JDK_MACOSX_BUNDLE_TOP_DIR) $(LOG_DEBUG) + $(TOUCH) $@ - PRODUCT_TARGETS += $(BUILD_JDK_SYMBOLS_BUNDLE) + $(eval $(call SetupBundleFile, BUILD_JDK_BUNDLE, \ + BUNDLE_NAME := $(JDK_BUNDLE_NAME), \ + FILES := \ + $(CREATE_JDK_BUNDLE_DIR_SIGNED) \ + $(JDK_SIGNED_CODE_RESOURCES), \ + BASE_DIRS := $(JDK_MACOSX_BUNDLE_DIR_SIGNED), \ + SUBDIR := $(JDK_BUNDLE_SUBDIR), \ + )) + + PRODUCT_TARGETS += $(BUILD_JDK_BUNDLE) + + ################################################################################ + # JRE bundle + $(eval $(call SetupCopyFiles, CREATE_JRE_BUNDLE_DIR_SIGNED, \ + SRC := $(JRE_IMAGE_DIR), \ + FILES := $(JRE_BUNDLE_FILES), \ + DEST := $(JRE_MACOSX_BUNDLE_DIR_SIGNED), \ + )) + + JRE_SIGNED_CODE_RESOURCES := \ + $(JRE_MACOSX_BUNDLE_DIR_SIGNED)/$(JRE_MACOSX_CONTENTS_SUBDIR)/_CodeSignature/CodeResources + + $(JRE_SIGNED_CODE_RESOURCES): $(CREATE_JRE_BUNDLE_DIR_SIGNED) + $(call LogWarn, Signing $(JRE_BUNDLE_NAME)) + $(CODESIGN) -s "$(MACOSX_CODESIGN_IDENTITY)" \ + --timestamp --options runtime --deep --force \ + $(JRE_MACOSX_BUNDLE_DIR_SIGNED)/$(JRE_MACOSX_BUNDLE_TOP_DIR) $(LOG_DEBUG) + $(TOUCH) $@ + + $(eval $(call SetupBundleFile, BUILD_JRE_BUNDLE, \ + BUNDLE_NAME := $(JRE_BUNDLE_NAME), \ + FILES := \ + $(CREATE_JRE_BUNDLE_DIR_SIGNED) \ + $(JRE_SIGNED_CODE_RESOURCES), \ + BASE_DIRS := $(JRE_MACOSX_BUNDLE_DIR_SIGNED), \ + SUBDIR := $(JRE_BUNDLE_SUBDIR), \ + )) + + LEGACY_TARGETS += $(BUILD_JRE_BUNDLE) + else + # Not a Macosx release build or code signing not available. + $(eval $(call SetupBundleFile, BUILD_JDK_BUNDLE, \ + BUNDLE_NAME := $(JDK_BUNDLE_NAME), \ + FILES := $(JDK_BUNDLE_FILES), \ + SPECIAL_INCLUDES := $(JDK_SPECIAL_INCLUDES), \ + BASE_DIRS := $(JDK_IMAGE_DIR), \ + SUBDIR := $(JDK_BUNDLE_SUBDIR), \ + )) + + PRODUCT_TARGETS += $(BUILD_JDK_BUNDLE) + + $(eval $(call SetupBundleFile, BUILD_JRE_BUNDLE, \ + BUNDLE_NAME := $(JRE_BUNDLE_NAME), \ + FILES := $(JRE_BUNDLE_FILES), \ + BASE_DIRS := $(JRE_IMAGE_DIR), \ + SUBDIR := $(JRE_BUNDLE_SUBDIR), \ + )) + + LEGACY_TARGETS += $(BUILD_JRE_BUNDLE) + endif + + ifeq ($(COPY_DEBUG_SYMBOLS), true) + $(eval $(call SetupBundleFile, BUILD_JDK_SYMBOLS_BUNDLE, \ + BUNDLE_NAME := $(JDK_SYMBOLS_BUNDLE_NAME), \ + FILES := $(JDK_SYMBOLS_BUNDLE_FILES), \ + BASE_DIRS := $(JDK_SYMBOLS_IMAGE_DIR) $(wildcard $(SYMBOLS_IMAGE_DIR)), \ + SUBDIR := $(JDK_BUNDLE_SUBDIR), \ + UNZIP_DEBUGINFO := true, \ + )) + + PRODUCT_TARGETS += $(BUILD_JDK_SYMBOLS_BUNDLE) + endif # The demo bundle is only created to support client tests. Ideally it should # be built with the main test bundle, but since the prerequisites match @@ -256,7 +397,7 @@ $(eval $(call SetupBundleFile, BUILD_TEST_DEMOS_BUNDLE, \ BUNDLE_NAME := $(TEST_DEMOS_BUNDLE_NAME), \ FILES := $(TEST_DEMOS_BUNDLE_FILES), \ - BASE_DIRS := $(JDK_IMAGE_DIR), \ + BASE_DIRS := $(JDK_DEMOS_IMAGE_DIR), \ SUBDIR := $(JDK_BUNDLE_SUBDIR), \ )) @@ -266,7 +407,7 @@ ################################################################################ ifneq ($(filter test-bundles, $(MAKECMDGOALS)), ) - TEST_BUNDLE_FILES := $(call CacheFind, $(TEST_IMAGE_DIR)) + TEST_BUNDLE_FILES := $(call FindFiles, $(TEST_IMAGE_DIR)) $(eval $(call SetupBundleFile, BUILD_TEST_BUNDLE, \ BUNDLE_NAME := $(TEST_BUNDLE_NAME), \ @@ -280,7 +421,7 @@ ################################################################################ ifneq ($(filter docs-bundles, $(MAKECMDGOALS)), ) - DOCS_BUNDLE_FILES := $(call CacheFind, $(DOCS_IMAGE_DIR)) + DOCS_BUNDLE_FILES := $(call FindFiles, $(DOCS_IMAGE_DIR)) $(eval $(call SetupBundleFile, BUILD_DOCS_BUNDLE, \ BUNDLE_NAME := $(DOCS_BUNDLE_NAME), \ @@ -294,6 +435,27 @@ ################################################################################ +ifneq ($(filter static-libs-bundles, $(MAKECMDGOALS)), ) + STATIC_LIBS_BUNDLE_FILES := $(call FindFiles, $(STATIC_LIBS_IMAGE_DIR)) + + ifeq ($(OPENJDK_TARGET_OS)-$(DEBUG_LEVEL), macosx-release) + STATIC_LIBS_BUNDLE_SUBDIR := $(JDK_MACOSX_CONTENTS_SUBDIR)/Home + else + STATIC_LIBS_BUNDLE_SUBDIR := $(JDK_BUNDLE_SUBDIR) + endif + + $(eval $(call SetupBundleFile, BUILD_STATIC_LIBS_BUNDLE, \ + BUNDLE_NAME := $(STATIC_LIBS_BUNDLE_NAME), \ + FILES := $(STATIC_LIBS_BUNDLE_FILES), \ + BASE_DIRS := $(STATIC_LIBS_IMAGE_DIR), \ + SUBDIR := $(STATIC_LIBS_BUNDLE_SUBDIR), \ + )) + + STATIC_LIBS_TARGETS += $(BUILD_STATIC_LIBS_BUNDLE) +endif + +################################################################################ + # Hook to include the corresponding custom file, if present. $(eval $(call IncludeCustomExtension, Bundles.gmk)) @@ -303,5 +465,7 @@ legacy-bundles: $(LEGACY_TARGETS) test-bundles: $(TEST_TARGETS) docs-bundles: $(DOCS_TARGETS) +static-libs-bundles: $(STATIC_LIBS_TARGETS) -.PHONY: all default product-bundles test-bundles docs-bundles +.PHONY: all default product-bundles test-bundles docs-bundles \ + static-libs-bundles
diff --git a/make/CompileCommands.gmk b/make/CompileCommands.gmk new file mode 100644 index 0000000..ad72983 --- /dev/null +++ b/make/CompileCommands.gmk
@@ -0,0 +1,60 @@ +# +# Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. +# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. +# +# This code is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 only, as +# published by the Free Software Foundation. Oracle designates this +# particular file as subject to the "Classpath" exception as provided +# by Oracle in the LICENSE file that accompanied this code. +# +# This code is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# version 2 for more details (a copy is included in the LICENSE file that +# accompanied this code). +# +# You should have received a copy of the GNU General Public License version +# 2 along with this work; if not, write to the Free Software Foundation, +# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +# +# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +# or visit www.oracle.com if you need additional information or have any +# questions. +# + +default: all + +include $(SPEC) +include MakeBase.gmk + +# When FIXPATH is set, let it process the file to make sure all paths are usable +# by system native tools. The FIXPATH tool assumes arguments preceeded by an @ +# character points to a text file containing further arguments (similar to a +# linker). It replaces any such arguments with a different temporary filename, +# whose contents has been processed to make any paths native. To obtain a +# properly processed compile_commands.json, FIXPATH is then made to invoke an +# AWK script with the unprocessed json file as the only argument, prepended with +# an @ character. The AWK script simply copies the contents of this processed +# file. +# +# The sed command encloses the fragments inside brackets and removes the final +# trailing comma. +$(OUTPUTDIR)/compile_commands.json: $(wildcard $(MAKESUPPORT_OUTPUTDIR)/compile-commands/*.json) + $(call LogWarn, Updating compile_commands.json) + $(RM) $@ + $(FIND) $(MAKESUPPORT_OUTPUTDIR)/compile-commands/ -name \*.json | \ + $(SORT) | $(XARGS) $(CAT) >> $@.tmp + $(if $(FIXPATH),$(FIXPATH) $(AWK) 'BEGIN { \ + tmpfile = substr(ARGV[2],2); \ + cmd = "$(CP) " "\047" tmpfile "\047" " $@.tmp"; \ + system(cmd); \ + }' -- @$@.tmp) + $(SED) -e '1s/^/[\$(NEWLINE)/' -e '$(DOLLAR)s/,\s\{0,\}$(DOLLAR)/\$(NEWLINE)]/' $@.tmp > $@ + $(RM) $@.tmp + +TARGETS += $(OUTPUTDIR)/compile_commands.json + +all: $(TARGETS) + +.PHONY: all
diff --git a/make/CompileDemos.gmk b/make/CompileDemos.gmk index 16a02ba..64ecf48 100644 --- a/make/CompileDemos.gmk +++ b/make/CompileDemos.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2016, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -43,7 +43,7 @@ # Prepare the find cache. DEMO_SRC_DIRS += $(TOPDIR)/src/demo -$(eval $(call FillCacheFind, $(wildcard $(DEMO_SRC_DIRS)))) +$(call FillFindCache, $(DEMO_SRC_DIRS)) # Append demo goals to this variable. TARGETS = @@ -237,11 +237,11 @@ ifeq ($(OPENJDK_TARGET_OS), solaris) TARGETS += $(patsubst $(DEMO_SHARE_SRC)/nbproject/%, \ $(SUPPORT_OUTPUTDIR)/demos/image/nbproject/%, \ - $(call CacheFind, $(DEMO_SHARE_SRC)/nbproject)) + $(call FindFiles, $(DEMO_SHARE_SRC)/nbproject)) else TARGETS += $(patsubst $(DEMO_SHARE_SRC)/nbproject/%, \ $(SUPPORT_OUTPUTDIR)/demos/image/nbproject/%, \ - $(call CacheFind, $(DEMO_SHARE_SRC)/nbproject)) + $(call FindFiles, $(DEMO_SHARE_SRC)/nbproject)) endif ################################################################################ @@ -250,7 +250,7 @@ $(eval $(call SetupCopyFiles, COPY_TO_TEST_IMAGE, \ SRC := $(SUPPORT_OUTPUTDIR)/demos/image, \ DEST := $(TEST_IMAGE_DIR)/jdk/demos, \ - FILES := $(call CacheFind, $(SUPPORT_OUTPUTDIR)/demos/image), \ + FILES := $(call FindFiles, $(SUPPORT_OUTPUTDIR)/demos/image), \ )) IMAGES_TARGETS := $(COPY_TO_TEST_IMAGE)
diff --git a/make/CompileJavaModules.gmk b/make/CompileJavaModules.gmk index 646aa1a..40c7e06 100644 --- a/make/CompileJavaModules.gmk +++ b/make/CompileJavaModules.gmk
@@ -321,7 +321,7 @@ ################################################################################ -jdk.internal.le_COPY += .properties +jdk.internal.le_COPY += .properties .caps .txt ################################################################################ @@ -644,7 +644,7 @@ ifneq ($(wildcard $(IMPORT_MODULES_CLASSES)/$(MODULE)), ) $(JDK_OUTPUTDIR)/modules/$(MODULE)/_imported.marker: \ - $(call CacheFind, $(IMPORT_MODULES_CLASSES)/$(MODULE)) + $(call FindFiles, $(IMPORT_MODULES_CLASSES)/$(MODULE)) $(call MakeDir, $(@D)) # Do not delete marker and build meta data files $(RM) -r $(filter-out $(@D)/_%, $(wildcard $(@D)/*))
diff --git a/make/CompileToolsJdk.gmk b/make/CompileToolsJdk.gmk index 1496640..030e823 100644 --- a/make/CompileToolsJdk.gmk +++ b/make/CompileToolsJdk.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -39,7 +39,7 @@ # Use += to be able to add to this from a custom extension BUILD_TOOLS_SRC_DIRS += \ $(TOPDIR)/make/jdk/src/classes \ - $(BUILDTOOLS_OUTPUTDIR)/interim_cldrconverter_classes \ + $(BUILDTOOLS_OUTPUTDIR)/interim_tzdb_classes \ # $(eval $(call SetupJavaCompilation,BUILD_TOOLS_JDK, \ @@ -55,6 +55,7 @@ ADD_JAVAC_FLAGS := \ --add-exports java.desktop/sun.awt=ALL-UNNAMED \ --add-exports java.base/sun.text=ALL-UNNAMED \ + --add-exports java.base/sun.security.util=ALL-UNNAMED \ , \ ))
diff --git a/make/CopyImportModules.gmk b/make/CopyImportModules.gmk index 3ea6a13..e71d29c 100644 --- a/make/CopyImportModules.gmk +++ b/make/CopyImportModules.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2015, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -35,7 +35,7 @@ CMDS_DIR := $(wildcard $(addsuffix /$(MODULE), $(IMPORT_MODULES_CMDS))) CONF_DIR := $(wildcard $(addsuffix /$(MODULE), $(IMPORT_MODULES_CONF))) -$(eval $(call FillCacheFind, $(LIBS_DIR) $(CMDS_DIR) $(CONF_DIR))) +$(call FillFindCache, $(LIBS_DIR) $(CMDS_DIR) $(CONF_DIR)) ifneq ($(LIBS_DIR), ) ifeq ($(OPENJDK_TARGET_OS), windows) @@ -45,21 +45,21 @@ SRC := $(LIBS_DIR), \ DEST := $(JDK_OUTPUTDIR)/bin, \ FILES := $(filter $(TO_BIN_FILTER), \ - $(call CacheFind, $(LIBS_DIR))) \ + $(call FindFiles, $(LIBS_DIR))) \ )) $(eval $(call SetupCopyFiles, COPY_LIBS_TO_LIB, \ SRC := $(LIBS_DIR), \ DEST := $(JDK_OUTPUTDIR)/lib, \ FILES := $(filter-out $(TO_BIN_FILTER), \ - $(call CacheFind, $(LIBS_DIR))) \ + $(call FindFiles, $(LIBS_DIR))) \ )) TARGETS += $(COPY_LIBS_TO_BIN) $(COPY_LIBS_TO_LIB) else $(eval $(call SetupCopyFiles, COPY_LIBS, \ SRC := $(LIBS_DIR), \ DEST := $(JDK_OUTPUTDIR)/lib, \ - FILES := $(filter %$(SHARED_LIBRARY_SUFFIX), $(call CacheFind, $(LIBS_DIR))), \ + FILES := $(filter %$(SHARED_LIBRARY_SUFFIX), $(call FindFiles, $(LIBS_DIR))), \ )) # Use relative links if the import dir is inside the OUTPUTDIR, otherwise @@ -75,7 +75,7 @@ $(eval $(call SetupCopyFiles, LINK_LIBS, \ SRC := $(LIBS_DIR), \ DEST := $(JDK_OUTPUTDIR)/lib, \ - FILES := $(filter-out %$(SHARED_LIBRARY_SUFFIX), $(call CacheFind, $(LIBS_DIR))), \ + FILES := $(filter-out %$(SHARED_LIBRARY_SUFFIX), $(call FindFiles, $(LIBS_DIR))), \ MACRO := $(LINK_MACRO), \ LOG_ACTION := $(LOG_ACTION), \ )) @@ -87,7 +87,7 @@ $(eval $(call SetupCopyFiles, COPY_CMDS, \ SRC := $(CMDS_DIR), \ DEST := $(JDK_OUTPUTDIR)/bin, \ - FILES := $(call CacheFind, $(CMDS_DIR)), \ + FILES := $(call FindFiles, $(CMDS_DIR)), \ )) TARGETS += $(COPY_CMDS) endif @@ -96,7 +96,7 @@ $(eval $(call SetupCopyFiles, COPY_CONF, \ SRC := $(CONF_DIR), \ DEST := $(JDK_OUTPUTDIR)/lib, \ - FILES := $(call CacheFind, $(CONF_DIR)), \ + FILES := $(call FindFiles, $(CONF_DIR)), \ )) TARGETS += $(COPY_CONF) endif
diff --git a/make/CopyInterimCLDRConverter.gmk b/make/CopyInterimCLDRConverter.gmk deleted file mode 100644 index eabd832..0000000 --- a/make/CopyInterimCLDRConverter.gmk +++ /dev/null
@@ -1,52 +0,0 @@ -# -# Copyright (c) 2015, Oracle and/or its affiliates. All rights reserved. -# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -# -# This code is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License version 2 only, as -# published by the Free Software Foundation. Oracle designates this -# particular file as subject to the "Classpath" exception as provided -# by Oracle in the LICENSE file that accompanied this code. -# -# This code is distributed in the hope that it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# version 2 for more details (a copy is included in the LICENSE file that -# accompanied this code). -# -# You should have received a copy of the GNU General Public License version -# 2 along with this work; if not, write to the Free Software Foundation, -# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -# -# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -# or visit www.oracle.com if you need additional information or have any -# questions. -# - -default: all - -include $(SPEC) -include MakeBase.gmk - -########################################################################################## - -### CLDRConverter needs the JRE time zone names from the java.base source. - -define cldrconverter_copytznames - $(MKDIR) -p '$(@D)' - $(RM) '$@' - $(SED) -e "s/package sun.util.resources/package build.tools.cldrconverter/" \ - -e "s/extends TimeZoneNamesBundle//" \ - -e "s/protected final/static final/" \ - < $(<) > $@ -endef - -$(eval $(call SetupCopyFiles,COPY_INTERIM_CLDRCONVERTER, \ - SRC := $(TOPDIR)/src/java.base/share/classes/sun/util/resources, \ - DEST := $(BUILDTOOLS_OUTPUTDIR)/interim_cldrconverter_classes/build/tools/cldrconverter, \ - FILES := TimeZoneNames.java, \ - MACRO := cldrconverter_copytznames)) - -########################################################################################## - -all: $(COPY_INTERIM_CLDRCONVERTER)
diff --git a/make/CopyInterimTZDB.gmk b/make/CopyInterimTZDB.gmk new file mode 100644 index 0000000..6ce4186 --- /dev/null +++ b/make/CopyInterimTZDB.gmk
@@ -0,0 +1,50 @@ +# +# Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved. +# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. +# +# This code is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 only, as +# published by the Free Software Foundation. Oracle designates this +# particular file as subject to the "Classpath" exception as provided +# by Oracle in the LICENSE file that accompanied this code. +# +# This code is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# version 2 for more details (a copy is included in the LICENSE file that +# accompanied this code). +# +# You should have received a copy of the GNU General Public License version +# 2 along with this work; if not, write to the Free Software Foundation, +# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +# +# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +# or visit www.oracle.com if you need additional information or have any +# questions. +# + +default: all + +include $(SPEC) +include MakeBase.gmk + +########################################################################################## + +### TZDB tool needs files from java.time.zone package + +define tzdb_copyfiles + $(call MakeTargetDir) + $(RM) '$@' + $(SED) -e "s/package java.time.zone/package build.tools.tzdb/" \ + < $(<) > $@ +endef + +$(eval $(call SetupCopyFiles,COPY_INTERIM_TZDB, \ + SRC := $(TOPDIR)/src/java.base/share/classes/java/time/zone, \ + DEST := $(BUILDTOOLS_OUTPUTDIR)/interim_tzdb_classes/build/tools/tzdb, \ + FILES := ZoneRules.java ZoneOffsetTransition.java ZoneOffsetTransitionRule.java Ser.java, \ + MACRO := tzdb_copyfiles)) + +########################################################################################## + +all: $(COPY_INTERIM_TZDB)
diff --git a/make/CreateBuildJdkCopy.gmk b/make/CreateBuildJdkCopy.gmk index 2f12d97..3f6321a 100644 --- a/make/CreateBuildJdkCopy.gmk +++ b/make/CreateBuildJdkCopy.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2015, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -39,7 +39,7 @@ COPY_CLASSES_TARGET := $(BUILDJDK_OUTPUTDIR)/jdk/modules/java.base/_the.buildjdk-copy-marker -$(COPY_CLASSES_TARGET): $(call CacheFind, $(wildcard \ +$(COPY_CLASSES_TARGET): $(call FindFiles, $(wildcard \ $(addprefix $(JDK_OUTPUTDIR)/modules/, $(MODULES_TO_COPY)))) $(ECHO) $(LOG_INFO) "Copying java modules to buildjdk: $(MODULES_TO_COPY)" $(RM) -r $(BUILDJDK_OUTPUTDIR)/jdk/modules @@ -56,7 +56,7 @@ $(eval $(call SetupCopyFiles, COPY_SUPPORT_HEADERS, \ SRC := $(OUTPUTDIR), \ DEST := $(BUILDJDK_OUTPUTDIR), \ - FILES := $(call CacheFind, $(wildcard \ + FILES := $(call FindFiles, $(wildcard \ $(addprefix $(SUPPORT_OUTPUTDIR)/headers/, $(MODULES_TO_COPY)))), \ ))
diff --git a/make/CreateJmods.gmk b/make/CreateJmods.gmk index 42ec04e..c2a8b8b 100644 --- a/make/CreateJmods.gmk +++ b/make/CreateJmods.gmk
@@ -1,4 +1,5 @@ -# Copyright (c) 2014, 2017, Oracle and/or its affiliates. All rights reserved. +# +# Copyright (c) 2014, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -51,33 +52,79 @@ MAN_DIR ?= $(firstword $(wildcard $(addsuffix /$(MODULE), \ $(SUPPORT_OUTPUTDIR)/modules_man $(IMPORT_MODULES_MAN)))) -$(eval $(call FillCacheFind, \ +$(call FillFindCache, \ $(LIBS_DIR) $(CMDS_DIR) $(CONF_DIR) $(CLASSES_DIR) \ -)) +) ifneq ($(LIBS_DIR), ) - JMOD_FLAGS += --libs $(LIBS_DIR) - DEPS += $(call CacheFind, $(LIBS_DIR)) + DEPS += $(call FindFiles, $(LIBS_DIR)) + ifeq ($(OPENJDK_TARGET_OS)+$(SHIP_DEBUG_SYMBOLS), windows+public) + # For public debug symbols on Windows, we have to use stripped pdbs and rename them + rename_stripped = $(patsubst %.stripped.pdb,%.pdb,$1) + LIBS_DIR_FILTERED := $(subst modules_libs,modules_libs_filtered, $(LIBS_DIR)) + FILES_LIBS := $(filter-out %.pdb, $(call FindFiles, $(LIBS_DIR))) \ + $(filter %.stripped.pdb, $(call FindFiles, $(LIBS_DIR))) + $(eval $(call SetupCopyFiles, COPY_FILTERED_LIBS, \ + SRC := $(LIBS_DIR), \ + DEST := $(LIBS_DIR_FILTERED), \ + FILES := $(FILES_LIBS), \ + NAME_MACRO := rename_stripped, \ + )) + DEPS += $(COPY_FILTERED_LIBS) + JMOD_FLAGS += --libs $(LIBS_DIR_FILTERED) + else + JMOD_FLAGS += --libs $(LIBS_DIR) + endif endif ifneq ($(CMDS_DIR), ) - JMOD_FLAGS += --cmds $(CMDS_DIR) - DEPS += $(call CacheFind, $(CMDS_DIR)) + DEPS += $(call FindFiles, $(CMDS_DIR)) + ifeq ($(OPENJDK_TARGET_OS)+$(SHIP_DEBUG_SYMBOLS), windows+public) + # For public debug symbols on Windows, we have to use stripped pdbs, rename them + # and filter out a few launcher pdbs where there's a lib that goes by the same name + rename_stripped = $(patsubst %.stripped.pdb,%.pdb,$1) + CMDS_DIR_FILTERED := $(subst modules_cmds,modules_cmds_filtered, $(CMDS_DIR)) + FILES_CMDS := $(filter-out %.pdb, $(call FindFiles, $(CMDS_DIR))) \ + $(filter-out %jimage.stripped.pdb %jpackage.stripped.pdb %java.stripped.pdb, \ + $(filter %.stripped.pdb, $(call FindFiles, $(CMDS_DIR)))) + $(eval $(call SetupCopyFiles, COPY_FILTERED_CMDS, \ + SRC := $(CMDS_DIR), \ + DEST := $(CMDS_DIR_FILTERED), \ + FILES := $(FILES_CMDS), \ + NAME_MACRO := rename_stripped, \ + )) + DEPS += $(COPY_FILTERED_CMDS) + JMOD_FLAGS += --cmds $(CMDS_DIR_FILTERED) + else ifeq ($(OPENJDK_TARGET_OS)+$(SHIP_DEBUG_SYMBOLS), windows+full) + # For full debug symbols on Windows, we have to filter out a few launcher pdbs + # where there's a lib that goes by the same name + CMDS_DIR_FILTERED := $(subst modules_cmds,modules_cmds_filtered, $(CMDS_DIR)) + $(eval $(call SetupCopyFiles, COPY_FILTERED_CMDS, \ + SRC := $(CMDS_DIR), \ + DEST := $(CMDS_DIR_FILTERED), \ + FILES := $(filter-out %jimage.pdb %jpackage.pdb %java.pdb, \ + $(call FindFiles, $(CMDS_DIR))), \ + )) + DEPS += $(COPY_FILTERED_CMDS) + JMOD_FLAGS += --cmds $(CMDS_DIR_FILTERED) + else + JMOD_FLAGS += --cmds $(CMDS_DIR) + endif endif ifneq ($(CONF_DIR), ) JMOD_FLAGS += --config $(CONF_DIR) - DEPS += $(call CacheFind, $(CONF_DIR)) + DEPS += $(call FindFiles, $(CONF_DIR)) endif ifneq ($(CLASSES_DIR), ) JMOD_FLAGS += --class-path $(CLASSES_DIR) - DEPS += $(call CacheFind, $(CLASSES_DIR)) + DEPS += $(call FindFiles, $(CLASSES_DIR)) endif ifneq ($(INCLUDE_HEADERS_DIR), ) JMOD_FLAGS += --header-files $(INCLUDE_HEADERS_DIR) - DEPS += $(call CacheFind, $(INCLUDE_HEADERS_DIR)) + DEPS += $(call FindFiles, $(INCLUDE_HEADERS_DIR)) endif ifneq ($(MAN_DIR), ) JMOD_FLAGS += --man-pages $(MAN_DIR) - DEPS += $(call CacheFind, $(MAN_DIR)) + DEPS += $(call FindFiles, $(MAN_DIR)) endif # If a specific modules_legal dir exists for this module, only pick up files @@ -91,7 +138,7 @@ ) LEGAL_NOTICES_PATH := $(call PathList, $(LEGAL_NOTICES)) -DEPS += $(call CacheFind, $(LEGAL_NOTICES)) +DEPS += $(call FindFiles, $(LEGAL_NOTICES)) JMOD_FLAGS += --legal-notices $(LEGAL_NOTICES_PATH) @@ -145,7 +192,7 @@ # the actual command. Filter that out using wildcard before adding to DEPS. DEPS += $(wildcard $(JMOD_CMD)) ifeq ($(EXTERNAL_BUILDJDK), false) - DEPS += $(call CacheFind, $(JDK_OUTPUTDIR)/modules/jdk.jlink/jdk/tools/jmod) + DEPS += $(call FindFiles, $(JDK_OUTPUTDIR)/modules/jdk.jlink/jdk/tools/jmod) endif # If creating interim versions of jmods, certain files need to be filtered out @@ -154,7 +201,15 @@ DEPS := $(filter-out $(SUPPORT_OUTPUTDIR)/modules_libs/java.base/classlist, $(DEPS)) endif -JMOD_FLAGS += --exclude '**{_the.*,_*.marker,*.diz,*.debuginfo,*.dSYM/**,*.dSYM,*.pdb,*.map}' +ifeq ($(OPENJDK_TARGET_OS), windows) + ifeq ($(SHIP_DEBUG_SYMBOLS), ) + JMOD_FLAGS += --exclude '**{_the.*,_*.marker,*.diz,*.pdb,*.map}' + else + JMOD_FLAGS += --exclude '**{_the.*,_*.marker,*.diz,*.map}' + endif +else + JMOD_FLAGS += --exclude '**{_the.*,_*.marker,*.diz,*.debuginfo,*.dSYM/**,*.dSYM}' +endif # Create jmods in a temp dir and then move them into place to keep the # module path in $(IMAGES_OUTPUTDIR)/jmods valid at all times.
diff --git a/make/Docs.gmk b/make/Docs.gmk index 3b98ef1..5eae5c6 100644 --- a/make/Docs.gmk +++ b/make/Docs.gmk
@@ -168,14 +168,6 @@ font-family: DejaVu Sans, Arial, Helvetica, sans-serif; \ font-weight: normal;">$(DRAFT_TEXT)</div> -JDK_INDEX_CONTENT := \ - <!DOCTYPE html> \ - <html lang="en"> \ - <head> \ - <meta http-equiv="refresh" content="0;url=api/index.html"> \ - </head> \ - </html> - ################################################################################ # JDK javadoc titles/text snippets @@ -341,7 +333,7 @@ $$(SUPPORT_OUTPUTDIR)/docs/$1.vardeps) # Get a list of all files in all the source dirs for all included modules - $1_SOURCE_DEPS := $$(call CacheFind, $$(wildcard $$(foreach module, \ + $1_SOURCE_DEPS := $$(call FindFiles, $$(wildcard $$(foreach module, \ $$($1_ALL_MODULES), $$(call FindModuleSrcDirs, $$(module))))) # Javadoc creates a lot of files but use index.html as a marker @@ -485,18 +477,11 @@ ################################################################################ -JDK_INDEX_HTML := $(DOCS_OUTPUTDIR)/index.html - -$(JDK_INDEX_HTML): - $(ECHO) '$(JDK_INDEX_CONTENT)' > $@ - -JDK_INDEX_TARGETS += $(JDK_INDEX_HTML) - -# Copy the global resources +# Copy the global resources, including the top-level redirect index.html GLOBAL_SPECS_RESOURCES_DIR := $(TOPDIR)/make/data/docs-resources/ $(eval $(call SetupCopyFiles, COPY_GLOBAL_RESOURCES, \ SRC := $(GLOBAL_SPECS_RESOURCES_DIR), \ - FILES := $(call CacheFind, $(GLOBAL_SPECS_RESOURCES_DIR)), \ + FILES := $(call FindFiles, $(GLOBAL_SPECS_RESOURCES_DIR)), \ DEST := $(DOCS_OUTPUTDIR), \ )) JDK_INDEX_TARGETS += $(COPY_GLOBAL_RESOURCES) @@ -521,10 +506,10 @@ $(foreach m, $(ALL_MODULES), \ $(eval SPECS_$m := $(call FindModuleSpecsDirs, $m)) \ $(foreach d, $(SPECS_$m), \ - $(if $(filter $(COPY_SPEC_FILTER), $(call CacheFind, $d)), \ + $(if $(filter $(COPY_SPEC_FILTER), $(call FindFiles, $d)), \ $(eval $(call SetupCopyFiles, COPY_$m, \ SRC := $d, \ - FILES := $(filter $(COPY_SPEC_FILTER), $(call CacheFind, $d)), \ + FILES := $(filter $(COPY_SPEC_FILTER), $(call FindFiles, $d)), \ DEST := $(DOCS_OUTPUTDIR)/specs/, \ )) \ $(eval JDK_SPECS_TARGETS += $(COPY_$m)) \ @@ -541,11 +526,11 @@ $(foreach m, $(ALL_MODULES), \ $(eval SPECS_$m := $(call FindModuleSpecsDirs, $m)) \ $(foreach d, $(SPECS_$m), \ - $(if $(filter %.md, $(call CacheFind, $d)), \ + $(if $(filter %.md, $(call FindFiles, $d)), \ $(eval $m_$d_NAME := CONVERT_MARKDOWN_$m_$(strip $(call RelativePath, $d, $(TOPDIR)))) \ $(eval $(call SetupProcessMarkdown, $($m_$d_NAME), \ SRC := $d, \ - FILES := $(filter %.md, $(call CacheFind, $d)), \ + FILES := $(filter %.md, $(call FindFiles, $d)), \ DEST := $(DOCS_OUTPUTDIR)/specs/, \ CSS := $(GLOBAL_SPECS_DEFAULT_CSS_FILE), \ )) \
diff --git a/make/ExplodedImageOptimize.gmk b/make/ExplodedImageOptimize.gmk index dedac6d..78d4189 100644 --- a/make/ExplodedImageOptimize.gmk +++ b/make/ExplodedImageOptimize.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -38,7 +38,7 @@ $(PACKAGES_ATTRIBUTE_TARGET): $(ALL_MODULEINFO_CLASSES) $(BUILD_JIGSAW_CLASSES) $(call LogInfo, Optimizing the exploded image) - $(TOOL_ADD_PACKAGES_ATTRIBUTE) $(JDK_OUTPUTDIR) + $(call ExecuteWithLog, $@, $(TOOL_ADD_PACKAGES_ATTRIBUTE) $(JDK_OUTPUTDIR)) $(TOUCH) $@ TARGETS := $(PACKAGES_ATTRIBUTE_TARGET)
diff --git a/make/GenerateLinkOptData.gmk b/make/GenerateLinkOptData.gmk index 7358589..fa55ce2 100644 --- a/make/GenerateLinkOptData.gmk +++ b/make/GenerateLinkOptData.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2016, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -84,6 +84,17 @@ TARGETS += $(COPY_CLASSLIST) +# In case of shipping public debug symbols on windows, there is another temporary +# location from where jmods are compiled - need to deploy classlist there, too. +ifeq ($(OPENJDK_TARGET_OS)+$(SHIP_DEBUG_SYMBOLS), windows+public) + $(eval $(call SetupCopyFiles, COPY_CLASSLIST_TO_FILTERED, \ + FILES := $(CLASSLIST_FILE), \ + DEST := $(SUPPORT_OUTPUTDIR)/modules_libs_filtered/java.base, \ + )) + + TARGETS += $(COPY_CLASSLIST_TO_FILTERED) +endif + # Copy the default_jli_trace.txt file into jdk.jlink $(eval $(call SetupCopyFiles, COPY_JLI_TRACE, \ FILES := $(JLI_TRACE_FILE), \
diff --git a/make/GensrcModuleInfo.gmk b/make/GensrcModuleInfo.gmk deleted file mode 100644 index 25ade7f..0000000 --- a/make/GensrcModuleInfo.gmk +++ /dev/null
@@ -1,102 +0,0 @@ -# -# Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved. -# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -# -# This code is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License version 2 only, as -# published by the Free Software Foundation. Oracle designates this -# particular file as subject to the "Classpath" exception as provided -# by Oracle in the LICENSE file that accompanied this code. -# -# This code is distributed in the hope that it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# version 2 for more details (a copy is included in the LICENSE file that -# accompanied this code). -# -# You should have received a copy of the GNU General Public License version -# 2 along with this work; if not, write to the Free Software Foundation, -# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -# -# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -# or visit www.oracle.com if you need additional information or have any -# questions. -# - -################################################################################ -# This file makes modifications to module-info.java files based on the build -# configuration. -# -# Depending on build platform, imported modules and optional parts of the build -# being active, some modules need to have extra exports, provides or uses -# declarations added to them. These optional extras are defined in .extra files: -# -# src/<module>/<share,platform>/classes/module-info.java.extra -# -# The contents of the .extra files are simply extra lines that could fit into -# the module-info file. -# -# This makefile is called once for each from-module with the variable -# MODULE naming the from-module. -# -# The modified module-info.java files are put in the gensrc directory where -# they will automatically override the static versions in the src tree. -# -################################################################################ - -default: all - -include $(SPEC) -include MakeBase.gmk -include Modules.gmk - -################################################################################ -# Define this here since jdk/make/Tools.gmk cannot be included from the top -# make directory. Should probably move some tools away from the jdk repo. -TOOL_GENMODULEINFOSOURCE = $(JAVA_SMALL) \ - $(INTERIM_LANGTOOLS_ARGS) \ - -cp "$(BUILDTOOLS_OUTPUTDIR)/jdk_tools_classes" \ - build.tools.module.GenModuleInfoSource - -################################################################################ - -# Name of modification file. -MOD_FILENAME := module-info.java.extra - -# Construct all possible src directories for the module. -MODULE_CLASSES_DIRS := $(call FindModuleSrcDirs, $(MODULE)) - -# Find all the .extra files in the src dirs. -MOD_FILES := $(wildcard $(foreach f, $(MOD_FILENAME), $(addsuffix /$(f), \ - $(MODULE_CLASSES_DIRS)))) - -ifneq ($(MOD_FILES), ) - # Only make this call if modification files are found for this module - ALL_MODULES := $(call FindAllModules) - - $(SUPPORT_OUTPUTDIR)/gensrc/$(MODULE)/module-info.java: \ - $(firstword $(call FindAllModuleInfos, $(MODULE))) \ - $(BUILD_TOOLS_JDK) \ - $(MOD_FILES) \ - $(call DependOnVariable, ALL_MODULES) - $(MKDIR) -p $(@D) - $(RM) $@ $@.tmp - $(TOOL_GENMODULEINFOSOURCE) -o $@.tmp \ - --source-file $< \ - --modules $(call CommaList, $(ALL_MODULES)) \ - $(MOD_FILES) - $(MV) $@.tmp $@ - - TARGETS += $(SUPPORT_OUTPUTDIR)/gensrc/$(MODULE)/module-info.java - -else - # If no modifications are found for this module, remove any module-info.java - # created by a previous build since that is no longer valid. - ifneq ($(wildcard $(SUPPORT_OUTPUTDIR)/gensrc/$(MODULE)/module-info.java), ) - $(shell $(RM) $(SUPPORT_OUTPUTDIR)/gensrc/$(MODULE)/module-info.java) - endif -endif - -################################################################################ - -all: $(TARGETS)
diff --git a/make/GraalBuilderImage.gmk b/make/GraalBuilderImage.gmk new file mode 100644 index 0000000..b10d53a --- /dev/null +++ b/make/GraalBuilderImage.gmk
@@ -0,0 +1,57 @@ +# +# Copyright (c) 2020, Red Hat Inc. +# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. +# +# This code is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 only, as +# published by the Free Software Foundation. Oracle designates this +# particular file as subject to the "Classpath" exception as provided +# by Oracle in the LICENSE file that accompanied this code. +# +# This code is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# version 2 for more details (a copy is included in the LICENSE file that +# accompanied this code). +# +# You should have received a copy of the GNU General Public License version +# 2 along with this work; if not, write to the Free Software Foundation, +# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +# +# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +# or visit www.oracle.com if you need additional information or have any +# questions. +# + +# This makefile creates a jdk image overlayed with statically linked core +# libraries. + +default: all + +include $(SPEC) +include MakeBase.gmk + +################################################################################ + +TARGETS := + +$(eval $(call SetupCopyFiles, COPY_JDK_IMG, \ + SRC := $(JDK_IMAGE_DIR)/, \ + DEST := $(GRAAL_BUILDER_IMAGE_DIR)/, \ + FILES := $(call FindFiles, $(JDK_IMAGE_DIR)/), \ +)) +TARGETS += $(COPY_JDK_IMG) + +$(eval $(call SetupCopyFiles, COPY_STATIC_LIBS, \ + SRC := $(STATIC_LIBS_IMAGE_DIR)/lib, \ + DEST := $(GRAAL_BUILDER_IMAGE_DIR)/lib, \ + FILES := $(filter %$(STATIC_LIBRARY_SUFFIX), \ + $(call FindFiles, $(STATIC_LIBS_IMAGE_DIR)/lib)), \ +)) +TARGETS += $(COPY_STATIC_LIBS) + +################################################################################ + +all: $(TARGETS) + +.PHONY: all
diff --git a/make/Help.gmk b/make/Help.gmk index 461d343..2a4b61b 100644 --- a/make/Help.gmk +++ b/make/Help.gmk
@@ -43,7 +43,7 @@ $(info $(_) make images # Create a complete jdk image) $(info $(_) # (alias for product-images)) $(info $(_) make <name>-image # Build just the image for any of: ) - $(info $(_) # jdk, test, docs, symbols, legacy-jre) + $(info $(_) # jdk, test, docs, symbols, legacy-jre, static-libs) $(info $(_) make <phase> # Build the specified phase and everything it depends on) $(info $(_) # (gensrc, java, copy, libs, launchers, gendata, rmic)) $(info $(_) make *-only # Applies to most targets and disables building the) @@ -119,7 +119,7 @@ run-test-prebuilt: @( cd $(topdir) && \ $(MAKE) --no-print-directory -r -R -I make/common/ -f make/RunTestsPrebuilt.gmk \ - run-test-prebuilt TEST="$(TEST)" ) + run-test-prebuilt CUSTOM_MAKE_DIR=$(CUSTOM_MAKE_DIR) TEST="$(TEST)" ) ALL_GLOBAL_TARGETS := help print-configurations run-test-prebuilt
diff --git a/make/Images.gmk b/make/Images.gmk index 10e3dc2..524f76d 100644 --- a/make/Images.gmk +++ b/make/Images.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2014, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2014, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -276,21 +276,14 @@ ifeq ($(GCOV_ENABLED), true) - GCOV_FIND_EXPR := -type f -name "*.gcno" - - $(eval $(call SetupCopyFiles,COPY_HOTSPOT_GCOV_GCNO, \ + $(eval $(call SetupCopyFiles,COPY_GCOV_GCNO, \ SRC := $(OUTPUTDIR), \ DEST := $(SYMBOLS_IMAGE_DIR)/gcov, \ - FILES := $(shell $(FIND) $(HOTSPOT_OUTPUTDIR) $(GCOV_FIND_EXPR)))) + FILES := $(call FindFiles, $(HOTSPOT_OUTPUTDIR) \ + $(SUPPORT_OUTPUTDIR)/native, *.gcno) \ + )) - SYMBOLS_TARGETS += $(COPY_HOTSPOT_GCOV_GCNO) - - $(eval $(call SetupCopyFiles,COPY_JDK_GCOV_GCNO, \ - SRC := $(OUTPUTDIR), \ - DEST := $(SYMBOLS_IMAGE_DIR)/gcov, \ - FILES := $(shell $(FIND) $(SUPPORT_OUTPUTDIR)/native $(GCOV_FIND_EXPR)))) - - SYMBOLS_TARGETS += $(COPY_JDK_GCOV_GCNO) + SYMBOLS_TARGETS += $(COPY_GCOV_GCNO) endif @@ -308,6 +301,7 @@ else LIBS_TARGET_SUBDIR := lib endif +CMDS_TARGET_SUBDIR := bin # Param 1 - dir to find debuginfo files in FindDebuginfoFiles = \ @@ -323,13 +317,16 @@ # On Macosx, if debug symbols have not been zipped, find all files inside *.dSYM # dirs. ifeq ($(OPENJDK_TARGET_OS), macosx) - $(eval $(call FillCacheFind, \ - $(SUPPORT_OUTPUTDIR)/modules_cmds $(SUPPORT_OUTPUTDIR)/modules_libs)) + $(call FillFindCache, \ + $(SUPPORT_OUTPUTDIR)/modules_libs $(SUPPORT_OUTPUTDIR)/modules_cmds) FindDebuginfoFiles = \ - $(if $(wildcard $1), $(call containing, .dSYM/, $(call CacheFind, $1))) + $(if $(wildcard $1), $(call containing, .dSYM/, $(call FindFiles, $1))) endif endif +FILTERED_PDBS := %jimage.stripped.pdb %jpackage.stripped.pdb %java.stripped.pdb \ + %jimage.pdb %jpackage.pdb %java.pdb %jimage.map %jpackage.map %java.map + # Param 1 - either JDK or JRE SetupCopyDebuginfo = \ $(foreach m, $(ALL_$1_MODULES), \ @@ -340,6 +337,13 @@ $(SUPPORT_OUTPUTDIR)/modules_libs/$m), \ )) \ $(eval $1_TARGETS += $$(COPY_$1_LIBS_DEBUGINFO_$m)) \ + $(eval $(call SetupCopyFiles, COPY_$1_CMDS_DEBUGINFO_$m, \ + SRC := $(SUPPORT_OUTPUTDIR)/modules_cmds/$m, \ + DEST := $($1_IMAGE_DIR)/$(CMDS_TARGET_SUBDIR), \ + FILES := $(filter-out $(FILTERED_PDBS), $(call FindDebuginfoFiles, \ + $(SUPPORT_OUTPUTDIR)/modules_cmds/$m)), \ + )) \ + $(eval $1_TARGETS += $$(COPY_$1_CMDS_DEBUGINFO_$m)) \ ) # No space before argument to avoid having to put $(strip ) everywhere in
diff --git a/make/InitSupport.gmk b/make/InitSupport.gmk index 8f2d2b9..baefc89 100644 --- a/make/InitSupport.gmk +++ b/make/InitSupport.gmk
@@ -421,8 +421,8 @@ $(if $(filter all, $(LOG_REPORT)), \ $(GREP) -v -e "^Note: including file:" < $(logfile) || true $(NEWLINE) \ , \ - ($(GREP) -v -e "^Note: including file:" < $(logfile) || true) | $(HEAD) -n 12 $(NEWLINE) \ - if test `$(WC) -l < $(logfile)` -gt 12; then \ + ($(GREP) -v -e "^Note: including file:" < $(logfile) || true) | $(HEAD) -n 15 $(NEWLINE) \ + if test `$(WC) -l < $(logfile)` -gt 15; then \ $(ECHO) " ... (rest of output omitted)" ; \ fi $(NEWLINE) \ ) \
diff --git a/make/MacBundles.gmk b/make/MacBundles.gmk index fcd102f..d25a88f 100644 --- a/make/MacBundles.gmk +++ b/make/MacBundles.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -52,26 +52,24 @@ $(eval $(call SetupCopyFiles, COPY_JDK_IMAGE, \ SRC := $(JDK_IMAGE_DIR), \ DEST := $(JDK_MACOSX_CONTENTS_DIR)/Home, \ - FILES := $(call CacheFind, $(JDK_IMAGE_DIR)), \ + FILES := $(call FindFiles, $(JDK_IMAGE_DIR)), \ )) $(eval $(call SetupCopyFiles, COPY_JRE_IMAGE, \ SRC := $(JRE_IMAGE_DIR), \ DEST := $(JRE_MACOSX_CONTENTS_DIR)/Home, \ - FILES := $(call CacheFind, $(JRE_IMAGE_DIR)), \ + FILES := $(call FindFiles, $(JRE_IMAGE_DIR)), \ )) - $(JDK_MACOSX_CONTENTS_DIR)/MacOS/libjli.dylib: - $(call LogInfo, Creating link $(patsubst $(OUTPUTDIR)/%,%,$@)) - $(MKDIR) -p $(@D) - $(RM) $@ - $(LN) -s ../Home/lib/jli/libjli.dylib $@ + $(eval $(call SetupCopyFiles, COPY_LIBJLI_JDK, \ + FILES := $(JDK_IMAGE_DIR)/lib/jli/libjli.dylib, \ + DEST := $(JDK_MACOSX_CONTENTS_DIR)/MacOS, \ + )) - $(JRE_MACOSX_CONTENTS_DIR)/MacOS/libjli.dylib: - $(call LogInfo, Creating link $(patsubst $(OUTPUTDIR)/%,%,$@)) - $(MKDIR) -p $(@D) - $(RM) $@ - $(LN) -s ../Home/lib/jli/libjli.dylib $@ + $(eval $(call SetupCopyFiles, COPY_LIBJLI_JRE, \ + FILES := $(JRE_IMAGE_DIR)/lib/jli/libjli.dylib, \ + DEST := $(JRE_MACOSX_CONTENTS_DIR)/MacOS, \ + )) $(eval $(call SetupTextFileProcessing, BUILD_JDK_PLIST, \ SOURCE_FILES := $(MACOSX_PLIST_SRC)/JDK-Info.plist, \ @@ -97,13 +95,19 @@ @@VENDOR@@ => $(BUNDLE_VENDOR) , \ )) - jdk-bundle: $(COPY_JDK_IMAGE) $(JDK_MACOSX_CONTENTS_DIR)/MacOS/libjli.dylib \ - $(BUILD_JDK_PLIST) + $(SUPPORT_OUTPUTDIR)/images/_jdk_bundle_attribute_set: $(COPY_JDK_IMAGE) $(SETFILE) -a B $(dir $(JDK_MACOSX_CONTENTS_DIR)) + $(TOUCH) $@ - jre-bundle: $(COPY_JRE_IMAGE) $(JRE_MACOSX_CONTENTS_DIR)/MacOS/libjli.dylib \ - $(BUILD_JRE_PLIST) + $(SUPPORT_OUTPUTDIR)/images/_jre_bundle_attribute_set: $(COPY_JRE_IMAGE) $(SETFILE) -a B $(dir $(JRE_MACOSX_CONTENTS_DIR)) + $(TOUCH) $@ + + jdk-bundle: $(COPY_JDK_IMAGE) $(COPY_LIBJLI_JDK) \ + $(BUILD_JDK_PLIST) $(SUPPORT_OUTPUTDIR)/images/_jdk_bundle_attribute_set + + jre-bundle: $(COPY_JRE_IMAGE) $(COPY_LIBJLI_JRE) \ + $(BUILD_JRE_PLIST) $(SUPPORT_OUTPUTDIR)/images/_jre_bundle_attribute_set else # Not macosx
diff --git a/make/Main.gmk b/make/Main.gmk index 00097d1..6b4b0ac 100644 --- a/make/Main.gmk +++ b/make/Main.gmk
@@ -1,5 +1,5 @@ -# -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. + +# Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -78,8 +78,8 @@ interim-rmic: +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f CompileInterimRmic.gmk) - interim-cldrconverter: - +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f CopyInterimCLDRConverter.gmk) + interim-tzdb: + +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f CopyInterimTZDB.gmk) buildtools-jdk: +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f CompileToolsJdk.gmk) @@ -92,7 +92,7 @@ endif ALL_TARGETS += buildtools-langtools interim-langtools \ - interim-rmic interim-cldrconverter buildtools-jdk buildtools-modules \ + interim-rmic interim-tzdb buildtools-jdk buildtools-modules \ buildtools-hotspot ################################################################################ @@ -136,7 +136,7 @@ define DeclareModuleInfoRecipe $1-gensrc-moduleinfo: +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) \ - -f GensrcModuleInfo.gmk MODULE=$1) + -f gensrc/GensrcModuleInfo.gmk MODULE=$1) $1-gensrc: $1-gensrc-moduleinfo endef @@ -222,6 +222,21 @@ ALL_TARGETS += $(LIBS_TARGETS) ################################################################################ +# Targets for compiling static versions of certain native libraries. These do +# not end up in the jmods or the normal JDK image, but are instead bundled into +# a special deliverable. +$(eval $(call DeclareRecipesForPhase, STATIC_LIBS, \ + TARGET_SUFFIX := static-libs, \ + FILE_PREFIX := Lib, \ + MAKE_SUBDIR := lib, \ + CHECK_MODULES := $(ALL_MODULES), \ + USE_WRAPPER := true, \ + EXTRA_ARGS := STATIC_LIBS=true, \ +)) + +ALL_TARGETS += $(STATIC_LIBS_TARGETS) + +################################################################################ # Targets for compiling native executables $(eval $(call DeclareRecipesForPhase, LAUNCHER, \ TARGET_SUFFIX := launchers, \ @@ -263,6 +278,52 @@ $(HOTSPOT_VARIANT_LIBS_TARGETS) hotspot-ide-project ################################################################################ +# Generate libs and launcher targets for creating compile_commands.json fragments +define DeclareCompileCommandsRecipe + $1-compile-commands: + $$(call LogInfo, Generating compile_commands.json fragments for $1) + +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f Main.gmk $1-only \ + GENERATE_COMPILE_COMMANDS_ONLY=true) + + COMPILE_COMMANDS_TARGETS_$2 += $1-compile-commands +endef + +$(foreach t, $(HOTSPOT_VARIANT_LIBS_TARGETS), \ + $(eval $(call DeclareCompileCommandsRecipe,$t,HOTSPOT)) \ +) + +$(foreach t, $(LIBS_TARGETS) $(LAUNCHER_TARGETS), \ + $(eval $(call DeclareCompileCommandsRecipe,$t,JDK)) \ +) + +compile-commands compile-commands-hotspot: + +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f CompileCommands.gmk) + +ALL_TARGETS += $(COMPILE_COMMANDS_TARGETS_HOTSPOT) $(COMPILE_COMMANDS_TARGETS_JDK) +ALL_TARGETS += compile-commands compile-commands-hotspot + +################################################################################ +# VS Code projects +vscode-project: + +($(CD) $(TOPDIR)/make/vscode && $(MAKE) $(MAKE_ARGS) -f CreateVSCodeProject.gmk \ + VSCODE_INDEXER=cpptools) + +vscode-project-clangd: + +($(CD) $(TOPDIR)/make/vscode && $(MAKE) $(MAKE_ARGS) -f CreateVSCodeProject.gmk \ + VSCODE_INDEXER=clangd) + +vscode-project-rtags: + +($(CD) $(TOPDIR)/make/vscode && $(MAKE) $(MAKE_ARGS) -f CreateVSCodeProject.gmk \ + VSCODE_INDEXER=rtags) + +vscode-project-ccls: + +($(CD) $(TOPDIR)/make/vscode && $(MAKE) $(MAKE_ARGS) -f CreateVSCodeProject.gmk \ + VSCODE_INDEXER=ccls) + +ALL_TARGETS += vscode-project vscode-project-clangd vscode-project-rtags \ + vscode-project-ccls + +################################################################################ # Build demos targets demos-jdk: @@ -334,6 +395,9 @@ symbols-image: +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f Images.gmk symbols) +static-libs-image: + +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f StaticLibsImage.gmk) + mac-jdk-bundle: +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f MacBundles.gmk jdk-bundle) @@ -346,10 +410,13 @@ exploded-image-optimize: +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f ExplodedImageOptimize.gmk) +graal-builder-image: + +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f GraalBuilderImage.gmk) + ALL_TARGETS += store-source-revision create-source-revision-tracker bootcycle-images zip-security \ zip-source jrtfs-jar jdk-image legacy-jre-image \ - symbols-image mac-jdk-bundle mac-legacy-jre-bundle \ - release-file exploded-image-optimize + symbols-image static-libs-image mac-jdk-bundle mac-legacy-jre-bundle \ + release-file exploded-image-optimize graal-builder-image ################################################################################ # Docs targets @@ -559,8 +626,12 @@ test-make: ($(CD) $(TOPDIR)/test/make && $(MAKE) $(MAKE_ARGS) -f TestMake.gmk $(TEST_TARGET)) +test-compile-commands: + ($(CD) $(TOPDIR)/test/make && $(MAKE) $(MAKE_ARGS) -f TestMake.gmk test-compile-commands) + ALL_TARGETS += test test-hotspot-jtreg test-hotspot-jtreg-native \ - test-hotspot-internal test-hotspot-gtest test-jdk-jtreg-native test-make + test-hotspot-internal test-hotspot-gtest test-jdk-jtreg-native test-make \ + test-compile-commands ################################################################################ # Bundles @@ -577,7 +648,11 @@ docs-bundles: +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f Bundles.gmk docs-bundles) -ALL_TARGETS += product-bundles legacy-bundles test-bundles docs-bundles +static-libs-bundles: + +($(CD) $(TOPDIR)/make && $(MAKE) $(MAKE_ARGS) -f Bundles.gmk static-libs-bundles) + +ALL_TARGETS += product-bundles legacy-bundles test-bundles docs-bundles \ + static-libs-bundles ################################################################################ # Install targets @@ -610,7 +685,7 @@ interim-langtools: $(INTERIM_LANGTOOLS_GENSRC_TARGETS) - buildtools-jdk: interim-langtools interim-cldrconverter + buildtools-jdk: interim-langtools interim-tzdb buildtools-hotspot: interim-langtools @@ -632,7 +707,7 @@ # Declare dependencies between hotspot-<variant>* targets $(foreach v, $(JVM_VARIANTS), \ - $(eval hotspot-$v: hotspot-$v-gensrc hotspot-$v-libs) \ + $(eval hotspot-$v-gensrc: java.base-copy) \ $(eval hotspot-$v-libs: hotspot-$v-gensrc java.base-copy) \ ) @@ -642,10 +717,14 @@ # If not already set, set the JVM variant target so that the JVM will be built. JVM_MAIN_LIB_TARGETS ?= hotspot-$(JVM_VARIANT_MAIN)-libs + JVM_MAIN_GENSRC_TARGETS ?= hotspot-$(JVM_VARIANT_MAIN)-gensrc # Building one JVM variant is enough to start building the other libs $(LIBS_TARGETS): $(JVM_MAIN_LIB_TARGETS) + # Static libs depend on hotspot gensrc + $(STATIC_LIBS_TARGETS): $(JVM_MAIN_GENSRC_TARGETS) + $(LAUNCHER_TARGETS): java.base-libs ifeq ($(STATIC_BUILD), true) @@ -694,16 +773,17 @@ # copied and processed. java.desktop-gensrc-src: java.base-gensrc java.base-copy - # The annotation processing for jdk.internal.vm.ci and jdk.internal.vm.compiler - # needs classes from the current JDK. - jdk.internal.vm.ci-gensrc-src: $(addsuffix -java, \ - $(call FindTransitiveDepsForModule, jdk.internal.vm.ci)) + # The annotation processing for jdk.internal.vm.compiler + # and jdk.internal.vm.compiler.management needs classes from the current JDK. jdk.internal.vm.compiler-gensrc-src: $(addsuffix -java, \ $(call FindTransitiveDepsForModule, jdk.internal.vm.compiler)) + jdk.internal.vm.compiler.management-gensrc-src: $(addsuffix -java, \ + $(call FindTransitiveDepsForModule, jdk.internal.vm.compiler.management)) - # For jdk.internal.vm.compiler, the gensrc step is generating a module-info.java.extra + # For these modules, the gensrc step is generating a module-info.java.extra # file to be processed by the gensrc-moduleinfo target. jdk.internal.vm.compiler-gensrc-moduleinfo: jdk.internal.vm.compiler-gensrc-src + jdk.internal.vm.compiler.management-gensrc-moduleinfo: jdk.internal.vm.compiler.management-gensrc-src jdk.jdeps-gendata: java rmic @@ -738,6 +818,31 @@ $(foreach m, $(ALL_MODULES), $(eval $m-jmod: $($(m)_JMOD_DEPS))) $(foreach m, $(INTERIM_IMAGE_MODULES), $(eval $m-interim-jmod: $($(m)_JMOD_DEPS))) + # Setup the minimal set of generated native source dependencies for hotspot + $(foreach v, $(JVM_VARIANTS), \ + $(eval hotspot-$v-libs-compile-commands: hotspot-$v-gensrc) \ + $(foreach m, $(filter java.desktop jdk.hotspot.agent, $(GENSRC_MODULES)), \ + $(eval hotspot-$v-libs-compile-commands: $m-gensrc)) \ + ) + + # For the full JDK compile commands, create all possible generated sources + $(foreach m, $(GENSRC_MODULES), $(eval $m-libs-compile-commands: $m-gensrc)) + $(foreach m, $(filter $(JAVA_MODULES), $(LIBS_MODULES)), $(eval $m-libs-compile-commands: $m-java)) + + $(COMPILE_COMMANDS_TARGETS_HOTSPOT): clean-compile-commands + $(COMPILE_COMMANDS_TARGETS_JDK): clean-compile-commands + compile-commands-hotspot: $(COMPILE_COMMANDS_TARGETS_HOTSPOT) + compile-commands: $(COMPILE_COMMANDS_TARGETS_HOTSPOT) $(COMPILE_COMMANDS_TARGETS_JDK) + + # The -static-libs targets depend on -java as well as java.base-copy. + $(foreach m, $(filter $(JAVA_MODULES), $(STATIC_LIBS_MODULES)), \ + $(eval $m-static-libs: $m-java java.base-copy)) + + vscode-project: compile-commands + vscode-project-clangd: compile-commands + vscode-project-rtags: compile-commands + vscode-project-ccls: compile-commands + # Jmods cannot be created until we have the jmod tool ready to run. During # a normal build we run it from the exploded image, but when cross compiling # it's run from the buildjdk, which is either created at build time or user @@ -800,6 +905,10 @@ legacy-jre-image: jmods release-file symbols-image: $(LIBS_TARGETS) $(LAUNCHER_TARGETS) + static-libs-image: $(STATIC_LIBS_TARGETS) + + graal-builder-image: jdk-image static-libs-image + mac-jdk-bundle: jdk-image mac-legacy-jre-bundle: legacy-jre-image @@ -852,6 +961,8 @@ test-make: clean-test-make + test-compile-commands: compile-commands + build-test-lib: exploded-image-optimize build-test-failure-handler: interim-langtools @@ -891,6 +1002,8 @@ docs-bundles: docs-image + static-libs-bundles: static-libs-image + generate-summary: jmods buildtools-modules update-x11wrappers: java.base-copy buildtools-jdk @@ -905,6 +1018,10 @@ buildtools: buildtools-langtools interim-langtools interim-rmic \ buildtools-jdk $(JVM_TOOLS_TARGETS) +# Declare dependencies from hotspot-<variant> targets +$(foreach v, $(JVM_VARIANTS), \ + $(eval hotspot-$v: hotspot-$v-gensrc hotspot-$v-libs) \ +) hotspot: $(HOTSPOT_VARIANT_TARGETS) # Create targets hotspot-libs and hotspot-gensrc. @@ -925,6 +1042,8 @@ libs: $(LIBS_TARGETS) +static-libs: $(STATIC_LIBS_TARGETS) + launchers: $(LAUNCHER_TARGETS) jmods: $(JMOD_TARGETS) @@ -1031,10 +1150,10 @@ all-images: product-images test-image docs-image # all-bundles packages all our deliverables as tar.gz bundles. -all-bundles: product-bundles test-bundles docs-bundles +all-bundles: product-bundles test-bundles docs-bundles static-libs-bundles ALL_TARGETS += buildtools hotspot hotspot-libs hotspot-gensrc gensrc gendata \ - copy java rmic libs launchers jmods \ + copy java rmic libs static-libs launchers jmods \ jdk.jdwp.agent-gensrc $(ALL_MODULES) demos \ exploded-image-base exploded-image \ create-buildjdk docs-jdk-api docs-javase-api docs-reference-api docs-jdk \ @@ -1081,12 +1200,15 @@ # Remove everything, except the output from configure. clean: $(CLEAN_DIR_TARGETS) - ($(CD) $(OUTPUTDIR) && $(RM) -r build*.log*) + ($(CD) $(OUTPUTDIR) && $(RM) -r build*.log* compile_commands.json) $(ECHO) Cleaned all build artifacts. clean-docs: $(call CleanDocs) +clean-compile-commands: + $(call CleanMakeSupportDir,compile-commands) + $(CLEAN_DIR_TARGETS): $(call CleanDir,$(patsubst clean-%, %, $@)) @@ -1128,9 +1250,9 @@ ) $(ECHO) Cleaned everything, you will have to re-run configure. -ALL_TARGETS += clean clean-docs dist-clean $(CLEAN_DIR_TARGETS) $(CLEAN_SUPPORT_DIR_TARGETS) \ - $(CLEAN_TEST_TARGETS) $(CLEAN_PHASE_TARGETS) $(CLEAN_MODULE_TARGETS) \ - $(CLEAN_MODULE_PHASE_TARGETS) +ALL_TARGETS += clean clean-docs clean-compile-commands dist-clean $(CLEAN_DIR_TARGETS) \ + $(CLEAN_SUPPORT_DIR_TARGETS) $(CLEAN_TEST_TARGETS) $(CLEAN_PHASE_TARGETS) \ + $(CLEAN_MODULE_TARGETS) $(CLEAN_MODULE_PHASE_TARGETS) ################################################################################ # Declare *-only targets for each normal target
diff --git a/make/MainSupport.gmk b/make/MainSupport.gmk index c7710ec..f373e63 100644 --- a/make/MainSupport.gmk +++ b/make/MainSupport.gmk
@@ -65,6 +65,13 @@ @$(PRINTF) " done\n" endef +define CleanMakeSupportDir + @$(PRINTF) "Cleaning $(strip $1) make support artifacts ..." + @$(PRINTF) "\n" $(LOG_DEBUG) + $(RM) -r $(MAKESUPPORT_OUTPUTDIR)/$(strip $1) + @$(PRINTF) " done\n" +endef + define CleanTest @$(PRINTF) "Cleaning test $(strip $1) ..." @$(PRINTF) "\n" $(LOG_DEBUG) @@ -137,7 +144,7 @@ $$(addprefix -I, $$(PHASE_MAKEDIRS) \ $$(addsuffix /$$($1_MAKE_SUBDIR), $$(PHASE_MAKEDIRS)) \ ) \ - MODULE=$2 MAKEFILE_PREFIX=$$($1_FILE_PREFIX)) + MODULE=$2 MAKEFILE_PREFIX=$$($1_FILE_PREFIX) $$($1_EXTRA_ARGS)) else +($(CD) $$(dir $$(firstword $$(wildcard $$(addsuffix \ /$$($1_MAKE_SUBDIR)/$$($1_FILE_PREFIX)-$2.gmk, $$(PHASE_MAKEDIRS))))) \ @@ -146,7 +153,7 @@ $$(addprefix -I, $$(PHASE_MAKEDIRS) \ $$(addsuffix /$$($1_MAKE_SUBDIR), $$(PHASE_MAKEDIRS)) \ ) \ - MODULE=$2 \ + MODULE=$2 $$($1_EXTRA_ARGS) \ ) endif @@ -186,12 +193,13 @@ # CHECK_MODULES : List of modules to try # MULTIPLE_MAKEFILES : Set to true to handle makefiles for the same module and # phase in multiple repos +# EXTRA_ARGS : Add extra make args to each makefile call # Exported variables: # $1_MODULES : All modules that had rules generated # $1_TARGETS : All targets generated define DeclareRecipesForPhase - $(foreach i,2 3 4 5 6 7, $(if $(strip $($i)),$(strip $1)_$(strip $($i)))$(NEWLINE)) - $(if $(8),$(error Internal makefile error: Too many arguments to \ + $(foreach i,2 3 4 5 6 7 8, $(if $(strip $($i)),$(strip $1)_$(strip $($i)))$(NEWLINE)) + $(if $(9),$(error Internal makefile error: Too many arguments to \ DeclareRecipesForPhase, please update MakeHelper.gmk)) $$(foreach m, $$($(strip $1)_CHECK_MODULES), \
diff --git a/make/ModuleWrapper.gmk b/make/ModuleWrapper.gmk index dd6a8af..5f9c5fc 100644 --- a/make/ModuleWrapper.gmk +++ b/make/ModuleWrapper.gmk
@@ -100,5 +100,9 @@ $(TARGETS)), \ )) -all: $(TARGETS) $(COPY_LIBS_TO_BIN) $(COPY_LIBS_TO_LIB) \ - $(COPY_INCLUDE) $(COPY_CMDS) $(COPY_CONF) $(LINK_LIBS_TO_LIB) +ifeq ($(GENERATE_COMPILE_COMMANDS_ONLY), true) + all: $(filter $(MAKESUPPORT_OUTPUTDIR)/compile-commands/%, $(TARGETS)) +else + all: $(TARGETS) $(COPY_LIBS_TO_BIN) $(COPY_LIBS_TO_LIB) \ + $(COPY_INCLUDE) $(COPY_CMDS) $(COPY_CONF) $(LINK_LIBS_TO_LIB) +endif
diff --git a/make/RunTests.gmk b/make/RunTests.gmk index 1ffe735..05153cb 100644 --- a/make/RunTests.gmk +++ b/make/RunTests.gmk
@@ -44,11 +44,23 @@ TEST_JOBS_FACTOR_MACHINE ?= 1 ifeq ($(TEST_JOBS), 0) - # Concurrency based on min(cores / 2, 12) * TEST_JOBS_FACTOR + CORES_DIVIDER := 2 + ifeq ($(OPENJDK_TARGET_CPU_ARCH), sparc) + # For smaller SPARC machines we see reasonable scaling of throughput up to + # cpus/4 without affecting test reliability. On the bigger machines, cpus/4 + # causes intermittent timeouts. + ifeq ($(shell $(EXPR) $(NUM_CORES) \> 16), 1) + CORES_DIVIDER := 5 + else + CORES_DIVIDER := 4 + endif + endif + MEMORY_DIVIDER := 2048 TEST_JOBS := $(shell $(AWK) \ 'BEGIN { \ - c = $(NUM_CORES) / 2; \ - if (c > 12) c = 12; \ + c = $(NUM_CORES) / $(CORES_DIVIDER); \ + m = $(MEMORY_SIZE) / $(MEMORY_DIVIDER); \ + if (c > m) c = m; \ c = c * $(TEST_JOBS_FACTOR); \ c = c * $(TEST_JOBS_FACTOR_JDL); \ c = c * $(TEST_JOBS_FACTOR_MACHINE); \ @@ -70,8 +82,8 @@ endif $(eval $(call ParseKeywordVariable, TEST_OPTS, \ - KEYWORDS := JOBS TIMEOUT, \ - STRING_KEYWORDS := VM_OPTIONS, \ + SINGLE_KEYWORDS := JOBS TIMEOUT_FACTOR, \ + STRING_KEYWORDS := VM_OPTIONS JAVA_OPTIONS AOT_MODULES, \ )) # Helper function to propagate TEST_OPTS values. @@ -90,10 +102,14 @@ ifndef _NT_SYMBOL_PATH # Can't use PathList here as it adds quotes around the value. _NT_SYMBOL_PATH := \ - $(subst $(SPACE),;, $(foreach p, $(sort $(dir $(wildcard \ - $(addprefix $(SYMBOLS_IMAGE_DIR)/bin/, *.pdb */*.pdb)))), $(call FixPath, $p))) + $(subst $(SPACE),;,$(strip \ + $(foreach p, $(sort $(dir $(wildcard \ + $(addprefix $(SYMBOLS_IMAGE_DIR)/bin/, *.pdb */*.pdb)))), \ + $(call FixPath, $p) \ + ) \ + )) export _NT_SYMBOL_PATH - $(info _NT_SYMBOL_PATH $(_NT_SYMBOL_PATH)) + $(info _NT_SYMBOL_PATH=$(_NT_SYMBOL_PATH)) endif endif @@ -125,8 +141,118 @@ -timeoutHandlerTimeout:0 endif -GTEST_LAUNCHER_DIRS := $(patsubst %/gtestLauncher, %, $(wildcard $(TEST_IMAGE_DIR)/hotspot/gtest/*/gtestLauncher)) -GTEST_VARIANTS := $(strip $(patsubst $(TEST_IMAGE_DIR)/hotspot/gtest/%, %, $(GTEST_LAUNCHER_DIRS))) +GTEST_LAUNCHER_DIRS := $(patsubst %/gtestLauncher, %, \ + $(wildcard $(TEST_IMAGE_DIR)/hotspot/gtest/*/gtestLauncher)) +GTEST_VARIANTS := $(strip $(patsubst $(TEST_IMAGE_DIR)/hotspot/gtest/%, %, \ + $(GTEST_LAUNCHER_DIRS))) + +################################################################################ +# Optionally create AOT libraries for specified modules before running tests. +# Note, this could not be done during JDK build time. +################################################################################ + +# Note, this could not be done during JDK build time. + +# Parameter 1 is the name of the rule. +# +# Remaining parameters are named arguments. +# MODULE The module to generate a library for +# BIN Output directory in which to put the library +# VM_OPTIONS List of JVM arguments to use when creating library +# OPTIONS_VAR Name of variable to put AOT java options in +# PREREQS_VAR Name of variable to put all AOT prerequisite rule targets in +# for test rules to depend on +# +SetupAotModule = $(NamedParamsMacroTemplate) +define SetupAotModuleBody + $1_AOT_LIB := $$($1_BIN)/$$(call SHARED_LIBRARY,$$($1_MODULE)) + $1_AOT_CCLIST := $$(wildcard $$(TOPDIR)/test/hotspot/jtreg/compiler/aot/scripts/$$($1_MODULE)-list.txt) + + # Create jaotc flags. + # VM flags which don't affect AOT code generation are filtered out: + # -Xcomp, -XX:+-TieredCompilation + $1_JAOTC_OPTS := \ + -J-Xmx4g --info \ + $$(addprefix -J, $$(filter-out -Xcomp %TieredCompilation, $$($1_VM_OPTIONS))) \ + $$(addprefix --compile-commands$(SPACE), $$($1_AOT_CCLIST)) \ + --linker-path $$(LD_JAOTC) \ + # + + ifneq ($$(filter -ea, $$($1_VM_OPTIONS)), ) + $1_JAOTC_OPTS += --compile-with-assertions + endif + + $$($1_AOT_LIB): $$(JDK_IMAGE_DIR)/release \ + $$(call DependOnVariable, $1_JAOTC_OPTS) \ + $$(call DependOnVariable, JDK_IMAGE_DIR) + $$(call LogWarn, Generating $$(patsubst $$(OUTPUTDIR)/%, %, $$@)) + $$(call MakeTargetDir) + $$(call ExecuteWithLog, $$@, ( \ + $$(FIXPATH) $$(JDK_IMAGE_DIR)/bin/jaotc \ + $$($1_JAOTC_OPTS) --output $$@ --module $$($1_MODULE) \ + )) + $$(call ExecuteWithLog, $$@.check, ( \ + $$(FIXPATH) $$(JDK_IMAGE_DIR)/bin/java \ + $$($1_VM_OPTIONS) -XX:+UnlockDiagnosticVMOptions \ + -XX:+PrintAOT -XX:+UseAOTStrictLoading \ + -XX:AOTLibrary=$$@ -version \ + > $$@.verify-aot \ + )) + + $1_AOT_OPTIONS += -XX:AOTLibrary=$$($1_AOT_LIB) + $1_AOT_TARGETS += $$($1_AOT_LIB) +endef + +# Parameter 1 is the name of the rule. +# +# Remaining parameters are named arguments. +# MODULES The modules to generate a library for +# VM_OPTIONS List of JVM arguments to use when creating libraries +# +# After calling this, the following variables are defined +# $1_AOT_OPTIONS List of all java options needed to use the AOT libraries +# $1_AOT_TARGETS List of all targets that the test rule will need to depend on +# +SetupAot = $(NamedParamsMacroTemplate) +define SetupAotBody + $$(info Running with AOTd libraries for $$($1_MODULES)) + # Put aot libraries in a separate directory so they are not deleted between + # test runs and may be reused between make invocations. + $$(foreach m, $$($1_MODULES), \ + $$(eval $$(call SetupAotModule, $1_$$m, \ + MODULE := $$m, \ + BIN := $$(TEST_SUPPORT_DIR)/aot/$1, \ + VM_OPTIONS := $$($1_VM_OPTIONS), \ + )) \ + $$(eval $1_AOT_OPTIONS += $$($1_$$m_AOT_OPTIONS)) \ + $$(eval $1_AOT_TARGETS += $$($1_$$m_AOT_TARGETS)) \ + ) +endef + +################################################################################ +# Setup global test running parameters +################################################################################ + +# Each factor variable comes in 3 variants. The first one is reserved for users +# to use on command line. The other two are for predifined configurations in JDL +# and for machine specific configurations respectively. +TEST_JOBS_FACTOR ?= 1 +TEST_JOBS_FACTOR_JDL ?= 1 +TEST_JOBS_FACTOR_MACHINE ?= 1 + +ifeq ($(TEST_JOBS), 0) + # Concurrency based on min(cores / 2, 12) * TEST_JOBS_FACTOR + TEST_JOBS := $(shell $(AWK) \ + 'BEGIN { \ + c = $(NUM_CORES) / 2; \ + if (c > 12) c = 12; \ + c = c * $(TEST_JOBS_FACTOR); \ + c = c * $(TEST_JOBS_FACTOR_JDL); \ + c = c * $(TEST_JOBS_FACTOR_MACHINE); \ + if (c < 1) c = 1; \ + printf "%.0f", c; \ + }') +endif ################################################################################ # Parse control variables @@ -135,17 +261,24 @@ ifneq ($(TEST_OPTS), ) # Inform the user $(info Running tests using TEST_OPTS control variable '$(TEST_OPTS)') - - $(eval $(call SetTestOpt,VM_OPTIONS,JTREG)) - $(eval $(call SetTestOpt,VM_OPTIONS,GTEST)) - - $(eval $(call SetTestOpt,JOBS,JTREG)) - $(eval $(call SetTestOpt,TIMEOUT,JTREG)) endif +$(eval $(call SetTestOpt,VM_OPTIONS,JTREG)) +$(eval $(call SetTestOpt,JAVA_OPTIONS,JTREG)) +$(eval $(call SetTestOpt,VM_OPTIONS,GTEST)) +$(eval $(call SetTestOpt,JAVA_OPTIONS,GTEST)) + +$(eval $(call SetTestOpt,AOT_MODULES,JTREG)) +$(eval $(call SetTestOpt,AOT_MODULES,GTEST)) + +$(eval $(call SetTestOpt,JOBS,JTREG)) +$(eval $(call SetTestOpt,TIMEOUT_FACTOR,JTREG)) + $(eval $(call ParseKeywordVariable, JTREG, \ - KEYWORDS := JOBS TIMEOUT TEST_MODE ASSERT VERBOSE RETAIN MAX_MEM, \ - STRING_KEYWORDS := OPTIONS JAVA_OPTIONS VM_OPTIONS, \ + SINGLE_KEYWORDS := JOBS TIMEOUT_FACTOR TEST_MODE ASSERT VERBOSE RETAIN \ + MAX_MEM, \ + STRING_KEYWORDS := OPTIONS JAVA_OPTIONS VM_OPTIONS KEYWORDS \ + EXTRA_PROBLEM_LISTS AOT_MODULES, \ )) ifneq ($(JTREG), ) @@ -154,8 +287,8 @@ endif $(eval $(call ParseKeywordVariable, GTEST, \ - KEYWORDS := REPEAT, \ - STRING_KEYWORDS := OPTIONS VM_OPTIONS, \ + SINGLE_KEYWORDS := REPEAT, \ + STRING_KEYWORDS := OPTIONS VM_OPTIONS JAVA_OPTIONS AOT_MODULES, \ )) ifneq ($(GTEST), ) @@ -293,7 +426,7 @@ # Helper function to determine if a test specification is a special test # -# It is a special test if it is "special:" followed by a test name. +# It is a special test if it is "special:" followed by a test name, define ParseSpecialTestSelection $(if $(filter special:%, $1), \ $1 \ @@ -384,19 +517,28 @@ $1_GTEST_REPEAT :=--gtest_repeat=$$(GTEST_REPEAT) endif - run-test-$1: + ifneq ($$(GTEST_AOT_MODULES), ) + $$(eval $$(call SetupAot, $1, \ + MODULES := $$(GTEST_AOT_MODULES), \ + VM_OPTIONS := $$(GTEST_VM_OPTIONS) $$(GTEST_JAVA_OPTIONS), \ + )) + endif + + run-test-$1: $$($1_AOT_TARGETS) $$(call LogWarn) $$(call LogWarn, Running test '$$($1_TEST)') $$(call MakeDir, $$($1_TEST_RESULTS_DIR) $$($1_TEST_SUPPORT_DIR)) - $$(call ExecuteWithLog, $$($1_TEST_SUPPORT_DIR)/gtest, \ + $$(call ExecuteWithLog, $$($1_TEST_SUPPORT_DIR)/gtest, ( \ $$(FIXPATH) $$(TEST_IMAGE_DIR)/hotspot/gtest/$$($1_VARIANT)/gtestLauncher \ - -jdk $(JDK_IMAGE_DIR) $$($1_GTEST_FILTER) \ - --gtest_output=xml:$$($1_TEST_RESULTS_DIR)/gtest.xml \ - $$($1_GTEST_REPEAT) $$(GTEST_OPTIONS) $$(GTEST_VM_OPTIONS) \ + -jdk $(JDK_IMAGE_DIR) $$($1_GTEST_FILTER) \ + --gtest_output=xml:$$($1_TEST_RESULTS_DIR)/gtest.xml \ + --gtest_catch_exceptions=0 \ + $$($1_GTEST_REPEAT) $$(GTEST_OPTIONS) $$(GTEST_VM_OPTIONS) \ + $$(GTEST_JAVA_OPTIONS) $$($1_AOT_OPTIONS) \ > >($(TEE) $$($1_TEST_RESULTS_DIR)/gtest.txt) \ && $$(ECHO) $$$$? > $$($1_EXITCODE) \ || $$(ECHO) $$$$? > $$($1_EXITCODE) \ - ) + )) $1_RESULT_FILE := $$($1_TEST_RESULTS_DIR)/gtest.txt @@ -463,12 +605,11 @@ $1_TEST_NAME := $$(strip $$(patsubst jtreg:%, %, $$($1_TEST))) - $1_COMPONENT := \ + $1_TEST_ROOT := \ $$(strip $$(foreach root, $$(JTREG_TESTROOTS), \ - $$(if $$(filter $$(root)%, $$(JTREG_TOPDIR)/$$($1_TEST_NAME)), \ - $$(lastword $$(subst /, $$(SPACE), $$(root))) \ - ) \ + $$(if $$(filter $$(root)%, $$(JTREG_TOPDIR)/$$($1_TEST_NAME)), $$(root)) \ )) + $1_COMPONENT := $$(lastword $$(subst /, $$(SPACE), $$($1_TEST_ROOT))) # This will work only as long as just hotspot has the additional "jtreg" directory ifeq ($$($1_COMPONENT), jtreg) $1_COMPONENT := hotspot @@ -491,6 +632,9 @@ $$(eval $$(call SetJtregValue,$1,JTREG_BASIC_OPTIONS)) $$(eval $$(call SetJtregValue,$1,JTREG_PROBLEM_LIST)) + # Only the problem list for the current test root should be used. + $1_JTREG_PROBLEM_LIST := $$(filter $$($1_TEST_ROOT)%, $$($1_JTREG_PROBLEM_LIST)) + ifneq ($(TEST_JOBS), 0) $$(eval $$(call SetJtregValue,$1,JTREG_JOBS,$$(TEST_JOBS))) else @@ -501,7 +645,12 @@ # we may end up with a lot of JVM's $1_JTREG_MAX_RAM_PERCENTAGE := $$(shell $$(EXPR) 25 / $$($1_JTREG_JOBS)) - JTREG_TIMEOUT ?= 4 + # SPARC is in general slower per core so need to scale up timeouts a bit. + ifeq ($(OPENJDK_TARGET_CPU_ARCH), sparc) + JTREG_TIMEOUT_FACTOR ?= 8 + else + JTREG_TIMEOUT_FACTOR ?= 4 + endif JTREG_VERBOSE ?= fail,error,summary JTREG_RETAIN ?= fail,error @@ -510,12 +659,16 @@ $1_JTREG_LAUNCHER_OPTIONS += -Xmx$$($1_JTREG_MAX_MEM) endif + # Make sure the tmp dir is normalized as some tests will react badly otherwise + $1_TEST_TMP_DIR := $$(abspath $$($1_TEST_SUPPORT_DIR)/tmp) + $1_JTREG_BASIC_OPTIONS += -$$($1_JTREG_TEST_MODE) \ -verbose:$$(JTREG_VERBOSE) -retain:$$(JTREG_RETAIN) \ - -concurrency:$$($1_JTREG_JOBS) -timeoutFactor:$$(JTREG_TIMEOUT) \ - -vmoption:-XX:MaxRAMPercentage=$$($1_JTREG_MAX_RAM_PERCENTAGE) + -concurrency:$$($1_JTREG_JOBS) -timeoutFactor:$$(JTREG_TIMEOUT_FACTOR) \ + -vmoption:-XX:MaxRAMPercentage=$$($1_JTREG_MAX_RAM_PERCENTAGE) \ + -vmoption:-Djava.io.tmpdir="$$($1_TEST_TMP_DIR)" - $1_JTREG_BASIC_OPTIONS += -automatic -keywords:\!ignore -ignore:quiet + $1_JTREG_BASIC_OPTIONS += -automatic -ignore:quiet # Make it possible to specify the JIB_DATA_DIR for tests using the # JIB Artifact resolver @@ -545,24 +698,56 @@ $1_JTREG_BASIC_OPTIONS += $$(addprefix -exclude:, $$($1_JTREG_PROBLEM_LIST)) endif - ifneq ($$(JIB_JAR), ) - $1_JTREG_BASIC_OPTIONS += -cpa:$$(JIB_JAR) + ifneq ($$(JTREG_EXTRA_PROBLEM_LISTS), ) + # Accept both absolute paths as well as relative to the current test root. + $1_JTREG_BASIC_OPTIONS += $$(addprefix -exclude:, $$(wildcard \ + $$(JTREG_EXTRA_PROBLEM_LISTS) \ + $$(addprefix $$($1_TEST_ROOT)/, $$(JTREG_EXTRA_PROBLEM_LISTS)) \ + )) endif - $1_JTREG_BASIC_OPTIONS += -e:TEST_IMAGE_GRAAL_DIR=${TEST_IMAGE_DIR}/hotspot/jtreg/graal + ifneq ($$(JIB_HOME), ) + $1_JTREG_BASIC_OPTIONS += -e:JIB_HOME=$$(JIB_HOME) + endif + + $1_JTREG_BASIC_OPTIONS += -e:TEST_IMAGE_DIR=$(TEST_IMAGE_DIR) + $1_JTREG_BASIC_OPTIONS += -e:TEST_IMAGE_GRAAL_DIR=$(TEST_IMAGE_DIR)/hotspot/jtreg/graal ifneq ($$(JTREG_FAILURE_HANDLER_OPTIONS), ) $1_JTREG_LAUNCHER_OPTIONS += -Djava.library.path="$(JTREG_FAILURE_HANDLER_DIR)" endif + ifneq ($$(JTREG_KEYWORDS), ) + # The keywords string may contain problematic characters and may be quoted + # already when it arrives here. Remove any existing quotes and replace them + # with one set of single quotes. + $1_JTREG_KEYWORDS := \ + $$(strip $$(subst $$(SQUOTE),,$$(subst $$(DQUOTE),,$$(JTREG_KEYWORDS)))) + ifneq ($$($1_JTREG_KEYWORDS), ) + $1_JTREG_BASIC_OPTIONS += -k:'$$($1_JTREG_KEYWORDS)' + endif + endif + + ifneq ($$(JTREG_AOT_MODULES), ) + $$(eval $$(call SetupAot, $1, \ + MODULES := $$(JTREG_AOT_MODULES), \ + VM_OPTIONS := $$(JTREG_VM_OPTIONS) $$(JTREG_JAVA_OPTIONS), \ + )) + endif + + ifneq ($$($1_AOT_OPTIONS), ) + $1_JTREG_BASIC_OPTIONS += -vmoptions:"$$($1_AOT_OPTIONS)" + endif + clean-workdir-$1: $$(RM) -r $$($1_TEST_SUPPORT_DIR) - run-test-$1: clean-workdir-$1 + run-test-$1: clean-workdir-$1 $$($1_AOT_TARGETS) $$(call LogWarn) $$(call LogWarn, Running test '$$($1_TEST)') - $$(call MakeDir, $$($1_TEST_RESULTS_DIR) $$($1_TEST_SUPPORT_DIR)) - $$(call ExecuteWithLog, $$($1_TEST_SUPPORT_DIR)/jtreg, \ + $$(call MakeDir, $$($1_TEST_RESULTS_DIR) $$($1_TEST_SUPPORT_DIR) \ + $$($1_TEST_TMP_DIR)) + $$(call ExecuteWithLog, $$($1_TEST_SUPPORT_DIR)/jtreg, ( \ $$(JAVA) $$($1_JTREG_LAUNCHER_OPTIONS) \ -Dprogram=jtreg -jar $$(JT_HOME)/lib/jtreg.jar \ $$($1_JTREG_BASIC_OPTIONS) \ @@ -575,7 +760,7 @@ $$($1_TEST_NAME) \ && $$(ECHO) $$$$? > $$($1_EXITCODE) \ || $$(ECHO) $$$$? > $$($1_EXITCODE) \ - ) + )) $1_RESULT_FILE := $$($1_TEST_RESULTS_DIR)/text/stats.txt @@ -645,16 +830,16 @@ $$(error Invalid special test specification: $$($1_TEST_NAME)) endif - run-test-$1: + run-test-$1: $(TEST_PREREQS) $$(call LogWarn) $$(call LogWarn, Running test '$$($1_TEST)') $$(call MakeDir, $$($1_TEST_RESULTS_DIR) $$($1_TEST_SUPPORT_DIR)) - $$(call ExecuteWithLog, $$($1_TEST_SUPPORT_DIR)/test-execution, \ + $$(call ExecuteWithLog, $$($1_TEST_SUPPORT_DIR)/test-execution, ( \ $$($1_TEST_COMMAND_LINE) \ > >($(TEE) $$($1_TEST_RESULTS_DIR)/test-output.txt) \ && $$(ECHO) $$$$? > $$($1_EXITCODE) \ || $$(ECHO) $$$$? > $$($1_EXITCODE) \ - ) + )) $1_RESULT_FILE := $$($1_TEST_RESULTS_DIR)/gtest.txt
diff --git a/make/RunTestsPrebuilt.gmk b/make/RunTestsPrebuilt.gmk index 2660e76..737f9ce 100644 --- a/make/RunTestsPrebuilt.gmk +++ b/make/RunTestsPrebuilt.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2017, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -49,10 +49,11 @@ # given. # Note: No spaces are allowed around the arguments. # -# $1: The name of the argument +# $1: The name of the variable # $2: The default value, if any, or OPTIONAL (do not provide a default but # do not exit if it is missing) # $3: If NO_CHECK, disable checking for target file/directory existence +# If MKDIR, create the default directory define SetupVariable ifeq ($$($1), ) ifeq ($2, ) @@ -75,10 +76,17 @@ endif # If $1 has a value (is not optional), and $3 is not set (to NO_CHECK), # and if wildcard is empty, then complain that the file is missing. - ifeq ($$(strip $$(if $$($1), , OPTIONAL) $$(wildcard $$($1)) $3), ) - $$(info Error: Prebuilt variable $1 points to missing file/directory:) - $$(info '$$($1)') - $$(error Cannot continue.) + ifeq ($3, MKDIR) + ifneq ($$(findstring $$(LOG), info debug trace), ) + $$(info Creating directory for $1) + endif + $$(shell mkdir -p $$($1)) + else ifneq ($3, NO_CHECK) + ifeq ($$(strip $$(if $$($1), , OPTIONAL) $$(wildcard $$($1))), ) + $$(info Error: Prebuilt variable $1 points to missing file/directory:) + $$(info '$$($1)') + $$(error Cannot continue.) + endif endif endef @@ -87,12 +95,12 @@ # $1: The output file name # $2..$N: The lines to output to the file define CreateNewSpec - $(if $(strip $(26)), \ + $(if $(strip $(31)), \ $(error Internal makefile error: \ Too many arguments to macro, please update CreateNewSpec in RunTestsPrebuilt.gmk) \ ) \ $(shell $(RM) $1) \ - $(foreach i, $(call sequence, 2, 25), \ + $(foreach i, $(call sequence, 2, 30), \ $(if $(strip $($i)), \ $(call AppendFile, $(strip $($i)), $1) \ ) \ @@ -106,14 +114,14 @@ # Verify that user has given correct additional input. # These variables are absolutely necessary -$(eval $(call SetupVariable,OUTPUTDIR)) +$(eval $(call SetupVariable,OUTPUTDIR,$(TOPDIR)/build/run-test-prebuilt,MKDIR)) $(eval $(call SetupVariable,BOOT_JDK)) $(eval $(call SetupVariable,JT_HOME)) # These can have default values based on the ones above $(eval $(call SetupVariable,JDK_IMAGE_DIR,$(OUTPUTDIR)/images/jdk)) $(eval $(call SetupVariable,TEST_IMAGE_DIR,$(OUTPUTDIR)/images/test)) -$(eval $(call SetupVariable,SYMBOLS_IMAGE_DIR,$(OUTPUTDIR)/images/symbols)) +$(eval $(call SetupVariable,SYMBOLS_IMAGE_DIR,$(OUTPUTDIR)/images/symbols,NO_CHECK)) # Provide default values for tools that we need $(eval $(call SetupVariable,MAKE,make,NO_CHECK)) @@ -202,8 +210,8 @@ ifeq ($(OPENJDK_TARGET_OS), windows) ifeq ($(wildcard $(TEST_IMAGE_DIR)/bin/fixpath.exe), ) - $$(info Error: fixpath is missing from test image '$(TEST_IMAGE_DIR)') - $$(error Cannot continue.) + $(info Error: fixpath is missing from test image '$(TEST_IMAGE_DIR)') + $(error Cannot continue.) endif FIXPATH := $(TEST_IMAGE_DIR)/bin/fixpath.exe -c PATH_SEP:=; @@ -212,17 +220,59 @@ PATH_SEP:=: endif -# Check number of cores +# Check number of cores and memory in MB ifeq ($(OPENJDK_TARGET_OS), linux) - NUM_CORES := $(shell $(CAT) /proc/cpuinfo | $(GREP) -c processor) + NUM_CORES := $(shell $(CAT) /proc/cpuinfo | $(GREP) -c processor) + MEMORY_SIZE := $(shell \ + $(EXPR) `$(CAT) /proc/meminfo | $(GREP) MemTotal | $(AWK) '{print $$2}'` / 1024 \ + ) else ifeq ($(OPENJDK_TARGET_OS), macosx) - NUM_CORES := $(shell /usr/sbin/sysctl -n hw.ncpu) + NUM_CORES := $(shell /usr/sbin/sysctl -n hw.ncpu) + MEMORY_SIZE := $(shell $(EXPR) `/usr/sbin/sysctl -n hw.memsize` / 1024 / 1024) else ifeq ($(OPENJDK_TARGET_OS), solaris) - NUM_CORES := $(shell LC_MESSAGES=C /usr/sbin/psrinfo -v | $(GREP) -c on-line) + NUM_CORES := $(shell LC_MESSAGES=C /usr/sbin/psrinfo -v | $(GREP) -c on-line) + MEMORY_SIZE := $(shell \ + /usr/sbin/prtconf 2> /dev/null | $(GREP) "^Memory [Ss]ize" | $(AWK) '{print $$3}' \ + ) else ifeq ($(OPENJDK_TARGET_OS), windows) - NUM_CORES := $(NUMBER_OF_PROCESSORS) + NUM_CORES := $(NUMBER_OF_PROCESSORS) + MEMORY_SIZE := $(shell \ + $(EXPR) `wmic computersystem get totalphysicalmemory -value \ + | $(GREP) = | $(SED) 's/\\r//g' \ + | $(CUT) -d "=" -f 2-` / 1024 / 1024 \ + ) +endif +ifeq ($(NUM_CORES), ) + $(warn Could not find number of CPUs, assuming 1) + NUM_CORES := 1 +endif +ifeq ($(MEMORY_SIZE), ) + $(warn Could not find memory size, assuming 1024 MB) + MEMORY_SIZE := 1024 +endif + +# Setup LD for AOT support +ifneq ($(DEVKIT_HOME), ) + ifeq ($(OPENJDK_TARGET_OS), windows) + LD_JAOTC := $(DEVKIT_HOME)/VC/bin/x64/link.exe + LIBRARY_PREFIX := + SHARED_LIBRARY_SUFFIX := .dll + else ifeq ($(OPENJDK_TARGET_OS), linux) + LD_JAOTC := $(DEVKIT_HOME)/bin/ld + LIBRARY_PREFIX := lib + SHARED_LIBRARY_SUFFIX := .so + else ifeq ($(OPENJDK_TARGET_OS), macosx) + LD_JAOTC := $(DEVKIT_HOME)/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/ld + LIBRARY_PREFIX := lib + SHARED_LIBRARY_SUFFIX := .dylib + else ifeq ($(OPENJDK_TARGET_OS), solaris) + # Prefer system linker for AOT on Solaris. + LD_JAOTC := ld + LIBRARY_PREFIX := lib + SHARED_LIBRARY_SUFFIX := .so + endif else - NUM_CORES := 1 + LD := ld endif ################################################################################ @@ -260,6 +310,10 @@ OPENJDK_TARGET_CPU_BITS := $(OPENJDK_TARGET_CPU_BITS), \ OPENJDK_TARGET_CPU_ENDIAN := $(OPENJDK_TARGET_CPU_ENDIAN), \ NUM_CORES := $(NUM_CORES), \ + MEMORY_SIZE := $(MEMORY_SIZE), \ + LD_JAOTC := $(LD_JAOTC), \ + LIBRARY_PREFIX := $(LIBRARY_PREFIX), \ + SHARED_LIBRARY_SUFFIX := $(SHARED_LIBRARY_SUFFIX), \ include $(TOPDIR)/make/RunTestsPrebuiltSpec.gmk, \ $(CUSTOM_NEW_SPEC_LINE), \ ) @@ -276,9 +330,6 @@ @$(RM) -f $(MAKESUPPORT_OUTPUTDIR)/exit-with-error @cd $(TOPDIR) && $(MAKE) $(MAKE_ARGS) -f make/RunTests.gmk run-test \ TEST="$(TEST)" - @if test -f $(MAKESUPPORT_OUTPUTDIR)/exit-with-error ; then \ - exit 1 ; \ - fi all: run-test-prebuilt
diff --git a/make/RunTestsPrebuiltSpec.gmk b/make/RunTestsPrebuiltSpec.gmk index fd76562..6d07505 100644 --- a/make/RunTestsPrebuiltSpec.gmk +++ b/make/RunTestsPrebuiltSpec.gmk
@@ -124,7 +124,7 @@ JMOD := $(FIXPATH) $(JMOD_CMD) JARSIGNER := $(FIXPATH) $(JARSIGNER_CMD) -BUILD_JAVA := $(JAVA) +BUILD_JAVA := $(JDK_IMAGE_DIR)/bin/JAVA ################################################################################ # Some common tools. Assume most common name and no path. AWK := awk @@ -172,3 +172,21 @@ EXPR := expr FILE := file HG := hg + +# On Solaris gnu versions of some tools are required. +ifeq ($(OPENJDK_BUILD_OS), solaris) + AWK := gawk + GREP := ggrep + EGREP := ggrep -E + FGREP := grep -F + SED := gsed + TAR := gtar +endif + +ifeq ($(OPENJDK_BUILD_OS), windows) + CYGPATH := cygpath +endif + +################################################################################ +# Simple macros from spec.gmk.in +SHARED_LIBRARY=$(LIBRARY_PREFIX)$1$(SHARED_LIBRARY_SUFFIX)
diff --git a/make/StaticLibsImage.gmk b/make/StaticLibsImage.gmk new file mode 100644 index 0000000..21c4608 --- /dev/null +++ b/make/StaticLibsImage.gmk
@@ -0,0 +1,56 @@ +# +# Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved. +# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. +# +# This code is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 only, as +# published by the Free Software Foundation. Oracle designates this +# particular file as subject to the "Classpath" exception as provided +# by Oracle in the LICENSE file that accompanied this code. +# +# This code is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# version 2 for more details (a copy is included in the LICENSE file that +# accompanied this code). +# +# You should have received a copy of the GNU General Public License version +# 2 along with this work; if not, write to the Free Software Foundation, +# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +# +# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +# or visit www.oracle.com if you need additional information or have any +# questions. +# + +# This makefile creates an image of the optional static versions of certain JDK +# libraries. + +default: all + +include $(SPEC) +include MakeBase.gmk +include Modules.gmk + +ALL_MODULES = $(call FindAllModules) + +################################################################################ + +TARGETS := + +$(foreach m, $(ALL_MODULES), \ + $(eval $(call SetupCopyFiles, COPY_STATIC_LIBS_$m, \ + FLATTEN := true, \ + SRC := $(SUPPORT_OUTPUTDIR)/native/$m, \ + DEST := $(STATIC_LIBS_IMAGE_DIR)/lib, \ + FILES := $(filter %$(STATIC_LIBRARY_SUFFIX), \ + $(call FindFiles, $(SUPPORT_OUTPUTDIR)/native/$m/*/static)), \ + )) \ + $(eval TARGETS += $$(COPY_STATIC_LIBS_$m)) \ +) + +################################################################################ + +all: $(TARGETS) + +.PHONY: all
diff --git a/make/TestImage.gmk b/make/TestImage.gmk index 75595a7..059a1d9 100644 --- a/make/TestImage.gmk +++ b/make/TestImage.gmk
@@ -37,10 +37,22 @@ $(call install-file) endif -prepare-test-image: $(FIXPATH_COPY) +BUILD_INFO_PROPERTIES := $(TEST_IMAGE_DIR)/build-info.properties + +FIXPATH_ECHO := $(FIXPATH) $(call FixPath, $(ECHO)) + +$(BUILD_INFO_PROPERTIES): + $(call MakeTargetDir) + $(ECHO) "# Build info properties for JDK tests" > $@ + $(FIXPATH_ECHO) "build.workspace.root=$(WORKSPACE_ROOT)" >> $@ + $(FIXPATH_ECHO) "build.output.root=$(OUTPUTDIR)" >> $@ + +prepare-test-image: $(FIXPATH_COPY) $(BUILD_INFO_PROPERTIES) $(call MakeDir, $(TEST_IMAGE_DIR)) $(ECHO) > $(TEST_IMAGE_DIR)/Readme.txt 'JDK test image' +################################################################################ + all: prepare-test-image .PHONY: default all prepare-test-image
diff --git a/make/ToolsJdk.gmk b/make/ToolsJdk.gmk index 05158f8..3c87cb3 100644 --- a/make/ToolsJdk.gmk +++ b/make/ToolsJdk.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -74,11 +74,15 @@ build.tools.tzdb.TzdbZoneRulesCompiler TOOL_BLACKLISTED_CERTS = $(JAVA_SMALL) -cp $(BUILDTOOLS_OUTPUTDIR)/jdk_tools_classes \ + --add-exports java.base/sun.security.util=ALL-UNNAMED \ build.tools.blacklistedcertsconverter.BlacklistedCertsConverter TOOL_MAKEJAVASECURITY = $(JAVA_SMALL) -cp $(BUILDTOOLS_OUTPUTDIR)/jdk_tools_classes \ build.tools.makejavasecurity.MakeJavaSecurity +TOOL_GENERATECACERTS = $(JAVA_SMALL) -cp $(BUILDTOOLS_OUTPUTDIR)/jdk_tools_classes \ + build.tools.generatecacerts.GenerateCacerts + # TODO: There are references to the jdwpgen.jar in jdk/make/netbeans/jdwpgen/build.xml # and nbproject/project.properties in the same dir. Needs to be looked at.
diff --git a/make/UpdateBuildDocs.gmk b/make/UpdateBuildDocs.gmk index 51f7a65..ed09e7c 100644 --- a/make/UpdateBuildDocs.gmk +++ b/make/UpdateBuildDocs.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2017, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -45,21 +45,21 @@ DOCS_DIR := $(TOPDIR)/doc -$(eval $(call SetupProcessMarkdown, building, \ - FILES := $(DOCS_DIR)/building.md, \ +$(eval $(call SetupProcessMarkdown, md_docs, \ + FILES := $(call FindFiles, $(DOCS_DIR), *.md), \ DEST := $(DOCS_DIR), \ CSS := $(GLOBAL_SPECS_DEFAULT_CSS_FILE), \ OPTIONS := --toc, \ )) -TARGETS += $(building) +TARGETS += $(md_docs) -$(eval $(call SetupProcessMarkdown, testing, \ - FILES := $(DOCS_DIR)/testing.md, \ +$(eval $(call SetupProcessMarkdown, ide, \ + FILES := $(DOCS_DIR)/ide.md, \ DEST := $(DOCS_DIR), \ CSS := $(GLOBAL_SPECS_DEFAULT_CSS_FILE), \ OPTIONS := --toc, \ )) -TARGETS += $(testing) +TARGETS += $(ide) ################################################################################
diff --git a/make/ZipSource.gmk b/make/ZipSource.gmk index f2aefeb..b4aabda 100644 --- a/make/ZipSource.gmk +++ b/make/ZipSource.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2014, 2016, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2014, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -87,6 +87,7 @@ EXCLUDE_FILES := $(SRC_ZIP_EXCLUDE_FILES), \ SUFFIXES := .java, \ ZIP := $(SUPPORT_OUTPUTDIR)/src.zip, \ + FOLLOW_SYMLINKS := true, \ )) do-zip: $(BUILD_SRC_ZIP)
diff --git a/make/autoconf/basics.m4 b/make/autoconf/basics.m4 index e685e11..1b793d7 100644 --- a/make/autoconf/basics.m4 +++ b/make/autoconf/basics.m4
@@ -645,6 +645,14 @@ BASIC_FIXUP_PATH(CURDIR) BASIC_FIXUP_PATH(TOPDIR) + if test "x$CUSTOM_ROOT" != x; then + BASIC_FIXUP_PATH(CUSTOM_ROOT) + WORKSPACE_ROOT="${CUSTOM_ROOT}" + else + WORKSPACE_ROOT="${TOPDIR}" + fi + AC_SUBST(WORKSPACE_ROOT) + # Locate the directory of this script. AUTOCONF_DIR=$TOPDIR/make/autoconf @@ -867,11 +875,7 @@ AC_MSG_RESULT([in build directory with custom name]) fi - if test "x$CUSTOM_ROOT" != x; then - OUTPUTDIR="${CUSTOM_ROOT}/build/${CONF_NAME}" - else - OUTPUTDIR="${TOPDIR}/build/${CONF_NAME}" - fi + OUTPUTDIR="${WORKSPACE_ROOT}/build/${CONF_NAME}" $MKDIR -p "$OUTPUTDIR" if test ! -d "$OUTPUTDIR"; then AC_MSG_ERROR([Could not create build directory $OUTPUTDIR]) @@ -1212,17 +1216,41 @@ BASIC_REQUIRE_PROGS(MIG, mig) BASIC_REQUIRE_PROGS(XATTR, xattr) BASIC_PATH_PROGS(CODESIGN, codesign) + if test "x$CODESIGN" != "x"; then - # Verify that the openjdk_codesign certificate is present - AC_MSG_CHECKING([if openjdk_codesign certificate is present]) + # Check for user provided code signing identity. + # If no identity was provided, fall back to "openjdk_codesign". + AC_ARG_WITH([macosx-codesign-identity], [AS_HELP_STRING([--with-macosx-codesign-identity], + [specify the code signing identity])], + [MACOSX_CODESIGN_IDENTITY=$with_macosx_codesign_identity], + [MACOSX_CODESIGN_IDENTITY=openjdk_codesign] + ) + + AC_SUBST(MACOSX_CODESIGN_IDENTITY) + + # Verify that the codesign certificate is present + AC_MSG_CHECKING([if codesign certificate is present]) $RM codesign-testfile $TOUCH codesign-testfile - $CODESIGN -s openjdk_codesign codesign-testfile 2>&AS_MESSAGE_LOG_FD >&AS_MESSAGE_LOG_FD || CODESIGN= + $CODESIGN -s "$MACOSX_CODESIGN_IDENTITY" codesign-testfile 2>&AS_MESSAGE_LOG_FD \ + >&AS_MESSAGE_LOG_FD || CODESIGN= $RM codesign-testfile if test "x$CODESIGN" = x; then AC_MSG_RESULT([no]) else AC_MSG_RESULT([yes]) + # Verify that the codesign has --option runtime + AC_MSG_CHECKING([if codesign has --option runtime]) + $RM codesign-testfile + $TOUCH codesign-testfile + $CODESIGN --option runtime -s "$MACOSX_CODESIGN_IDENTITY" codesign-testfile \ + 2>&AS_MESSAGE_LOG_FD >&AS_MESSAGE_LOG_FD || CODESIGN= + $RM codesign-testfile + if test "x$CODESIGN" = x; then + AC_MSG_ERROR([codesign does not have --option runtime. macOS 10.13.6 and above is required.]) + else + AC_MSG_RESULT([yes]) + fi fi fi BASIC_REQUIRE_PROGS(SETFILE, SetFile)
diff --git a/make/autoconf/build-performance.m4 b/make/autoconf/build-performance.m4 index 7279914..0731da2 100644 --- a/make/autoconf/build-performance.m4 +++ b/make/autoconf/build-performance.m4
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2016, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -42,8 +42,11 @@ NUM_CORES=`/usr/sbin/sysctl -n hw.ncpu` FOUND_CORES=yes elif test "x$OPENJDK_BUILD_OS" = xaix ; then - NUM_CORES=`/usr/sbin/prtconf | grep "^Number Of Processors" | awk '{ print [$]4 }'` - FOUND_CORES=yes + NUM_LCPU=`lparstat -m 2> /dev/null | $GREP -o "lcpu=[[0-9]]*" | $CUT -d "=" -f 2` + if test -n "$NUM_LCPU"; then + NUM_CORES=$NUM_LCPU + FOUND_CORES=yes + fi elif test -n "$NUMBER_OF_PROCESSORS"; then # On windows, look in the env NUM_CORES=$NUMBER_OF_PROCESSORS
diff --git a/make/autoconf/buildjdk-spec.gmk.in b/make/autoconf/buildjdk-spec.gmk.in index b01d00b..670989d 100644 --- a/make/autoconf/buildjdk-spec.gmk.in +++ b/make/autoconf/buildjdk-spec.gmk.in
@@ -75,6 +75,8 @@ JVM_ASFLAGS := @OPENJDK_BUILD_JVM_ASFLAGS@ JVM_LIBS := @OPENJDK_BUILD_JVM_LIBS@ +FDLIBM_CFLAGS := @OPENJDK_BUILD_FDLIBM_CFLAGS@ + # The compiler for the build platform is likely not warning compatible with the official # compiler. WARNINGS_AS_ERRORS := false
diff --git a/make/autoconf/configure.ac b/make/autoconf/configure.ac index 2b99cf1..6672d26 100644 --- a/make/autoconf/configure.ac +++ b/make/autoconf/configure.ac
@@ -1,5 +1,5 @@ -SRC# -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -98,6 +98,9 @@ # With basic setup done, call the custom early hook. CUSTOM_EARLY_HOOK +# This only needs debug level to be setup +JDKOPT_ALLOW_ABSOLUTE_PATHS_IN_OUTPUT + # Check if we have devkits, extra paths or sysroot set. BASIC_SETUP_DEVKIT
diff --git a/make/autoconf/flags-cflags.m4 b/make/autoconf/flags-cflags.m4 index 2507845..a5c91ea 100644 --- a/make/autoconf/flags-cflags.m4 +++ b/make/autoconf/flags-cflags.m4
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -169,19 +169,7 @@ gcc) DISABLE_WARNING_PREFIX="-Wno-" CFLAGS_WARNINGS_ARE_ERRORS="-Werror" - # Repeate the check for the BUILD_CC and BUILD_CXX. Need to also reset - # CFLAGS since any target specific flags will likely not work with the - # build compiler - CC_OLD="$CC" - CXX_OLD="$CXX" - CC="$BUILD_CC" - CXX="$BUILD_CXX" - CFLAGS_OLD="$CFLAGS" - CFLAGS="" BUILD_CC_DISABLE_WARNING_PREFIX="-Wno-" - CC="$CC_OLD" - CXX="$CXX_OLD" - CFLAGS="$CFLAGS_OLD" ;; clang) DISABLE_WARNING_PREFIX="-Wno-" @@ -221,6 +209,20 @@ ;; esac fi + + # Extra flags needed when building optional static versions of certain + # JDK libraries. + STATIC_LIBS_CFLAGS="-DSTATIC_BUILD=1" + if test "x$TOOLCHAIN_TYPE" = xgcc || test "x$TOOLCHAIN_TYPE" = xclang; then + STATIC_LIBS_CFLAGS="$STATIC_LIBS_CFLAGS -ffunction-sections -fdata-sections" + fi + if test "x$TOOLCHAIN_TYPE" = xgcc; then + # Disable relax-relocation to enable compatibility with older linkers + RELAX_RELOCATIONS_FLAG="-Xassembler -mrelax-relocations=no" + FLAGS_COMPILER_CHECK_ARGUMENTS(ARGUMENT: [${RELAX_RELOCATIONS_FLAG}], + IF_TRUE: [STATIC_LIBS_CFLAGS="$STATIC_LIBS_CFLAGS ${RELAX_RELOCATIONS_FLAG}"]) + fi + AC_SUBST(STATIC_LIBS_CFLAGS) ]) AC_DEFUN([FLAGS_SETUP_OPTIMIZATION], @@ -362,6 +364,17 @@ FLAGS_SETUP_CFLAGS_CPU_DEP([TARGET]) + # Repeat the check for the BUILD_CC and BUILD_CXX. Need to also reset CFLAGS + # since any target specific flags will likely not work with the build compiler. + CC_OLD="$CC" + CXX_OLD="$CXX" + CFLAGS_OLD="$CFLAGS" + CXXFLAGS_OLD="$CXXFLAGS" + CC="$BUILD_CC" + CXX="$BUILD_CXX" + CFLAGS="" + CXXFLAGS="" + FLAGS_OS=$OPENJDK_BUILD_OS FLAGS_OS_TYPE=$OPENJDK_BUILD_OS_TYPE FLAGS_CPU=$OPENJDK_BUILD_CPU @@ -371,21 +384,12 @@ FLAGS_CPU_LEGACY=$OPENJDK_BUILD_CPU_LEGACY FLAGS_CPU_LEGACY_LIB=$OPENJDK_BUILD_CPU_LEGACY_LIB - FLAGS_SETUP_CFLAGS_CPU_DEP([BUILD], [OPENJDK_BUILD_]) + FLAGS_SETUP_CFLAGS_CPU_DEP([BUILD], [OPENJDK_BUILD_], [BUILD_]) - COMPILER_FP_CONTRACT_OFF_FLAG="-ffp-contract=off" - # Check that the compiler supports -ffp-contract=off flag - # Set FDLIBM_CFLAGS to -ffp-contract=off if it does. Empty - # otherwise. - # These flags are required for GCC-based builds of - # fdlibm with optimization without losing precision. - # Notably, -ffp-contract=off needs to be added for GCC >= 4.6. - if test "x$TOOLCHAIN_TYPE" = xgcc || test "x$TOOLCHAIN_TYPE" = xclang; then - FLAGS_COMPILER_CHECK_ARGUMENTS(ARGUMENT: [${COMPILER_FP_CONTRACT_OFF_FLAG}], - IF_TRUE: [FDLIBM_CFLAGS=${COMPILER_FP_CONTRACT_OFF_FLAG}], - IF_FALSE: [FDLIBM_CFLAGS=""]) - fi - AC_SUBST(FDLIBM_CFLAGS) + CC="$CC_OLD" + CXX="$CXX_OLD" + CFLAGS="$CFLAGS_OLD" + CXXFLAGS="$CXXFLAGS_OLD" # Tests are only ever compiled for TARGET CFLAGS_TESTLIB="$CFLAGS_JDKLIB" @@ -496,15 +500,14 @@ if test "x$TOOLCHAIN_TYPE" = xgcc; then TOOLCHAIN_CFLAGS_JVM="$TOOLCHAIN_CFLAGS_JVM -fcheck-new -fstack-protector" TOOLCHAIN_CFLAGS_JDK="-pipe -fstack-protector" - TOOLCHAIN_CFLAGS_JDK_CONLY="-fno-strict-aliasing" # technically NOT for CXX (but since this gives *worse* performance, use no-strict-aliasing everywhere!) - - CXXSTD_CXXFLAG="-std=gnu++98" - FLAGS_CXX_COMPILER_CHECK_ARGUMENTS(ARGUMENT: [$CXXSTD_CXXFLAG -Werror], - IF_FALSE: [CXXSTD_CXXFLAG=""]) - TOOLCHAIN_CFLAGS_JDK_CXXONLY="$CXXSTD_CXXFLAG" - TOOLCHAIN_CFLAGS_JVM="$TOOLCHAIN_CFLAGS_JVM $CXXSTD_CXXFLAG" - ADLC_CXXFLAG="$CXXSTD_CXXFLAG" - + # reduce lib size on s390x in link step, this needs also special compile flags + if test "x$OPENJDK_TARGET_CPU" = xs390x; then + TOOLCHAIN_CFLAGS_JVM="$TOOLCHAIN_CFLAGS_JVM -ffunction-sections -fdata-sections" + TOOLCHAIN_CFLAGS_JDK="$TOOLCHAIN_CFLAGS_JDK -ffunction-sections -fdata-sections" + fi + # technically NOT for CXX (but since this gives *worse* performance, use + # no-strict-aliasing everywhere!) + TOOLCHAIN_CFLAGS_JDK_CONLY="-fno-strict-aliasing" elif test "x$TOOLCHAIN_TYPE" = xclang; then # Restrict the debug information created by Clang to avoid @@ -595,6 +598,7 @@ # Where does this really belong?? if test "x$TOOLCHAIN_TYPE" = xgcc || test "x$TOOLCHAIN_TYPE" = xclang; then PICFLAG="-fPIC" + PIEFLAG="-fPIE" elif test "x$TOOLCHAIN_TYPE" = xsolstudio; then PICFLAG="-KPIC" elif test "x$TOOLCHAIN_TYPE" = xxlc; then @@ -646,15 +650,13 @@ OS_CFLAGS_JVM="$OS_CFLAGS_JVM -DNEEDS_LIBRT" fi fi - - # EXPORT - AC_SUBST(ADLC_CXXFLAG) ]) ################################################################################ # $1 - Either BUILD or TARGET to pick the correct OS/CPU variables to check # conditionals against. # $2 - Optional prefix for each variable defined. +# $3 - Optional prefix for compiler variables (either BUILD_ or nothing). AC_DEFUN([FLAGS_SETUP_CFLAGS_CPU_DEP], [ #### CPU DEFINES, these should (in theory) be independent on toolchain @@ -713,9 +715,21 @@ # CFLAGS PER CPU if test "x$TOOLCHAIN_TYPE" = xgcc || test "x$TOOLCHAIN_TYPE" = xclang; then # COMMON to gcc and clang + AC_MSG_CHECKING([if $1 is x86]) if test "x$FLAGS_CPU" = xx86; then - # Force compatibility with i586 on 32 bit intel platforms. - $1_CFLAGS_CPU="-march=i586" + AC_MSG_RESULT([yes]) + AC_MSG_CHECKING([if control flow protection is enabled by additional compiler flags]) + if echo "${EXTRA_CFLAGS}${EXTRA_CXXFLAGS}${EXTRA_ASFLAGS}" | ${GREP} -q 'fcf-protection' ; then + # cf-protection requires CMOV and thus i686 + $1_CFLAGS_CPU="-march=i686" + AC_MSG_RESULT([yes, forcing ${$1_CFLAGS_CPU}]) + else + # Force compatibility with i586 on 32 bit intel platforms. + $1_CFLAGS_CPU="-march=i586" + AC_MSG_RESULT([no, forcing ${$1_CFLAGS_CPU}]) + fi + else + AC_MSG_RESULT([no]) fi fi @@ -748,6 +762,13 @@ $1_CFLAGS_CPU_JDK="${$1_CFLAGS_CPU_JDK} -fno-omit-frame-pointer" fi + $1_CXXSTD_CXXFLAG="-std=gnu++98" + FLAGS_CXX_COMPILER_CHECK_ARGUMENTS(ARGUMENT: [${$1_CXXSTD_CXXFLAG} -Werror], + PREFIX: $3, IF_FALSE: [$1_CXXSTD_CXXFLAG=""]) + $1_TOOLCHAIN_CFLAGS_JDK_CXXONLY="${$1_CXXSTD_CXXFLAG}" + $1_TOOLCHAIN_CFLAGS_JVM="${$1_TOOLCHAIN_CFLAGS_JVM} ${$1_CXXSTD_CXXFLAG}" + $2ADLC_CXXFLAG="${$1_CXXSTD_CXXFLAG}" + elif test "x$TOOLCHAIN_TYPE" = xclang; then if test "x$FLAGS_OS" = xlinux; then # ppc test not really needed for clang @@ -784,20 +805,44 @@ fi if test "x$TOOLCHAIN_TYPE" = xgcc; then - TOOLCHAIN_CHECK_COMPILER_VERSION(VERSION: 6, PREFIX: $2, IF_AT_LEAST: FLAGS_SETUP_GCC6_COMPILER_FLAGS($1)) + FLAGS_SETUP_GCC6_COMPILER_FLAGS($1, $3) $1_TOOLCHAIN_CFLAGS="${$1_GCC6_CFLAGS}" $1_WARNING_CFLAGS_JVM="-Wno-format-zero-length -Wtype-limits -Wuninitialized" fi + # Prevent the __FILE__ macro from generating absolute paths into the built + # binaries. Depending on toolchain, different mitigations are possible. + # * GCC and Clang of new enough versions have -fmacro-prefix-map. + # * For most other toolchains, supplying all source files and -I flags as + # relative paths fixes the issue. + FILE_MACRO_CFLAGS= + if test "x$ALLOW_ABSOLUTE_PATHS_IN_OUTPUT" = "xfalse"; then + if test "x$TOOLCHAIN_TYPE" = xgcc || test "x$TOOLCHAIN_TYPE" = xclang; then + # Check if compiler supports -fmacro-prefix-map. If so, use that to make + # the __FILE__ macro resolve to paths relative to the workspace root. + workspace_root_trailing_slash="${WORKSPACE_ROOT%/}/" + FILE_MACRO_CFLAGS="-fmacro-prefix-map=${workspace_root_trailing_slash}=" + FLAGS_COMPILER_CHECK_ARGUMENTS(ARGUMENT: [${FILE_MACRO_CFLAGS}], + PREFIX: $3, + IF_FALSE: [ + FILE_MACRO_CFLAGS= + ] + ) + fi + fi + AC_SUBST(FILE_MACRO_CFLAGS) + # EXPORT to API - CFLAGS_JVM_COMMON="$ALWAYS_CFLAGS_JVM $ALWAYS_DEFINES_JVM $TOOLCHAIN_CFLAGS_JVM \ + CFLAGS_JVM_COMMON="$ALWAYS_CFLAGS_JVM $ALWAYS_DEFINES_JVM \ + $TOOLCHAIN_CFLAGS_JVM ${$1_TOOLCHAIN_CFLAGS_JVM} \ $OS_CFLAGS $OS_CFLAGS_JVM $CFLAGS_OS_DEF_JVM $DEBUG_CFLAGS_JVM \ - $WARNING_CFLAGS $WARNING_CFLAGS_JVM $JVM_PICFLAG" + $WARNING_CFLAGS $WARNING_CFLAGS_JVM $JVM_PICFLAG $FILE_MACRO_CFLAGS" CFLAGS_JDK_COMMON="$ALWAYS_CFLAGS_JDK $ALWAYS_DEFINES_JDK $TOOLCHAIN_CFLAGS_JDK \ $OS_CFLAGS $CFLAGS_OS_DEF_JDK $DEBUG_CFLAGS_JDK $DEBUG_OPTIONS_FLAGS_JDK \ - $WARNING_CFLAGS $WARNING_CFLAGS_JDK $DEBUG_SYMBOLS_CFLAGS_JDK" + $WARNING_CFLAGS $WARNING_CFLAGS_JDK $DEBUG_SYMBOLS_CFLAGS_JDK \ + $FILE_MACRO_CFLAGS" # Use ${$2EXTRA_CFLAGS} to block EXTRA_CFLAGS to be added to build flags. # (Currently we don't have any OPENJDK_BUILD_EXTRA_CFLAGS, but that might @@ -805,7 +850,9 @@ CFLAGS_JDK_COMMON_CONLY="$TOOLCHAIN_CFLAGS_JDK_CONLY \ $WARNING_CFLAGS_JDK_CONLY ${$2EXTRA_CFLAGS}" - CFLAGS_JDK_COMMON_CXXONLY="$ALWAYS_DEFINES_JDK_CXXONLY $TOOLCHAIN_CFLAGS_JDK_CXXONLY \ + CFLAGS_JDK_COMMON_CXXONLY="$ALWAYS_DEFINES_JDK_CXXONLY \ + $TOOLCHAIN_CFLAGS_JDK_CXXONLY \ + ${$1_TOOLCHAIN_CFLAGS_JDK_CXXONLY} \ $WARNING_CFLAGS_JDK_CXXONLY ${$2EXTRA_CXXFLAGS}" $1_CFLAGS_JVM="${$1_DEFINES_CPU_JVM} ${$1_CFLAGS_CPU} ${$1_CFLAGS_CPU_JVM} ${$1_TOOLCHAIN_CFLAGS} ${$1_WARNING_CFLAGS_JVM}" @@ -813,21 +860,40 @@ $2JVM_CFLAGS="$CFLAGS_JVM_COMMON ${$1_CFLAGS_JVM} ${$2EXTRA_CXXFLAGS}" - $2CFLAGS_JDKEXE="$CFLAGS_JDK_COMMON $CFLAGS_JDK_COMMON_CONLY ${$1_CFLAGS_JDK}" - $2CXXFLAGS_JDKEXE="$CFLAGS_JDK_COMMON $CFLAGS_JDK_COMMON_CXXONLY ${$1_CFLAGS_JDK}" - $2CFLAGS_JDKLIB="${$2CFLAGS_JDKEXE} $JDK_PICFLAG ${$1_CFLAGS_CPU_JDK_LIBONLY}" - $2CXXFLAGS_JDKLIB="${$2CXXFLAGS_JDKEXE} $JDK_PICFLAG ${$1_CFLAGS_CPU_JDK_LIBONLY}" + $2CFLAGS_JDKEXE="$CFLAGS_JDK_COMMON $CFLAGS_JDK_COMMON_CONLY ${$1_CFLAGS_JDK} $PIEFLAG" + $2CXXFLAGS_JDKEXE="$CFLAGS_JDK_COMMON $CFLAGS_JDK_COMMON_CXXONLY ${$1_CFLAGS_JDK} $PIEFLAG" + $2CFLAGS_JDKLIB="$CFLAGS_JDK_COMMON $CFLAGS_JDK_COMMON_CONLY ${$1_CFLAGS_JDK} \ + $JDK_PICFLAG ${$1_CFLAGS_CPU_JDK_LIBONLY}" + $2CXXFLAGS_JDKLIB="$CFLAGS_JDK_COMMON $CFLAGS_JDK_COMMON_CXXONLY ${$1_CFLAGS_JDK} \ + $JDK_PICFLAG ${$1_CFLAGS_CPU_JDK_LIBONLY}" AC_SUBST($2JVM_CFLAGS) AC_SUBST($2CFLAGS_JDKLIB) AC_SUBST($2CFLAGS_JDKEXE) AC_SUBST($2CXXFLAGS_JDKLIB) AC_SUBST($2CXXFLAGS_JDKEXE) + AC_SUBST($2ADLC_CXXFLAG) + + COMPILER_FP_CONTRACT_OFF_FLAG="-ffp-contract=off" + # Check that the compiler supports -ffp-contract=off flag + # Set FDLIBM_CFLAGS to -ffp-contract=off if it does. Empty + # otherwise. + # These flags are required for GCC-based builds of + # fdlibm with optimization without losing precision. + # Notably, -ffp-contract=off needs to be added for GCC >= 4.6. + if test "x$TOOLCHAIN_TYPE" = xgcc || test "x$TOOLCHAIN_TYPE" = xclang; then + FLAGS_COMPILER_CHECK_ARGUMENTS(ARGUMENT: [${COMPILER_FP_CONTRACT_OFF_FLAG}], + PREFIX: $3, + IF_TRUE: [$2FDLIBM_CFLAGS=${COMPILER_FP_CONTRACT_OFF_FLAG}], + IF_FALSE: [$2FDLIBM_CFLAGS=""]) + fi + AC_SUBST($2FDLIBM_CFLAGS) ]) # FLAGS_SETUP_GCC6_COMPILER_FLAGS([PREFIX]) # Arguments: # $1 - Prefix for each variable defined. +# $2 - Prefix for compiler variables (either BUILD_ or nothing). AC_DEFUN([FLAGS_SETUP_GCC6_COMPILER_FLAGS], [ # These flags are required for GCC 6 builds as undefined behaviour in OpenJDK code @@ -835,14 +901,11 @@ # Notably, value range propagation now assumes that the this pointer of C++ # member functions is non-null. NO_DELETE_NULL_POINTER_CHECKS_CFLAG="-fno-delete-null-pointer-checks" - dnl Argument check is disabled until FLAGS_COMPILER_CHECK_ARGUMENTS handles cross-compilation - dnl FLAGS_COMPILER_CHECK_ARGUMENTS(ARGUMENT: [$NO_DELETE_NULL_POINTER_CHECKS_CFLAG -Werror], - dnl IF_FALSE: [NO_DELETE_NULL_POINTER_CHECKS_CFLAG=""]) + FLAGS_COMPILER_CHECK_ARGUMENTS(ARGUMENT: [$NO_DELETE_NULL_POINTER_CHECKS_CFLAG -Werror], + PREFIX: $2, IF_FALSE: [NO_DELETE_NULL_POINTER_CHECKS_CFLAG=""]) NO_LIFETIME_DSE_CFLAG="-fno-lifetime-dse" - dnl Argument check is disabled until FLAGS_COMPILER_CHECK_ARGUMENTS handles cross-compilation - dnl FLAGS_COMPILER_CHECK_ARGUMENTS(ARGUMENT: [$NO_LIFETIME_DSE_CFLAG -Werror], - dnl IF_FALSE: [NO_LIFETIME_DSE_CFLAG=""]) - AC_MSG_NOTICE([GCC >= 6 detected; adding ${NO_DELETE_NULL_POINTER_CHECKS_CFLAG} and ${NO_LIFETIME_DSE_CFLAG}]) + FLAGS_COMPILER_CHECK_ARGUMENTS(ARGUMENT: [$NO_LIFETIME_DSE_CFLAG -Werror], + PREFIX: $2, IF_FALSE: [NO_LIFETIME_DSE_CFLAG=""]) $1_GCC6_CFLAGS="${NO_DELETE_NULL_POINTER_CHECKS_CFLAG} ${NO_LIFETIME_DSE_CFLAG}" ])
diff --git a/make/autoconf/flags-ldflags.m4 b/make/autoconf/flags-ldflags.m4 index 00aa25e..8d2bf89 100644 --- a/make/autoconf/flags-ldflags.m4 +++ b/make/autoconf/flags-ldflags.m4
@@ -72,12 +72,15 @@ fi # Add -z defs, to forbid undefined symbols in object files. - BASIC_LDFLAGS="$BASIC_LDFLAGS -Wl,-z,defs" + # add -z,relro (mark relocations read only) for all libs + # add -z,now ("full relro" - more of the Global Offset Table GOT is marked read only) + BASIC_LDFLAGS="$BASIC_LDFLAGS -Wl,-z,defs -Wl,-z,relro -Wl,-z,now" + # s390x : remove unused code+data in link step + if test "x$OPENJDK_TARGET_CPU" = xs390x; then + BASIC_LDFLAGS="$BASIC_LDFLAGS -Wl,--gc-sections" + fi - BASIC_LDFLAGS_JVM_ONLY="-Wl,-z,noexecstack -Wl,-O1 -Wl,-z,relro" - - BASIC_LDFLAGS_JDK_LIB_ONLY="-Wl,-z,noexecstack" - LIBJSIG_NOEXECSTACK_LDFLAGS="-Wl,-z,noexecstack" + BASIC_LDFLAGS_JVM_ONLY="-Wl,-O1" elif test "x$TOOLCHAIN_TYPE" = xclang; then BASIC_LDFLAGS_JVM_ONLY="-mno-omit-leaf-frame-pointer -mstack-alignment=16 \ @@ -103,13 +106,19 @@ BASIC_LDFLAGS_JVM_ONLY="-opt:icf,8 -subsystem:windows" fi + if test "x$TOOLCHAIN_TYPE" = xgcc || test "x$TOOLCHAIN_TYPE" = xclang; then + if test -n "$HAS_NOEXECSTACK"; then + BASIC_LDFLAGS="$BASIC_LDFLAGS -Wl,-z,noexecstack" + fi + fi + # Setup OS-dependent LDFLAGS if test "x$TOOLCHAIN_TYPE" = xclang || test "x$TOOLCHAIN_TYPE" = xgcc; then if test "x$OPENJDK_TARGET_OS" = xmacosx; then # Assume clang or gcc. # FIXME: We should really generalize SET_SHARED_LIBRARY_ORIGIN instead. OS_LDFLAGS_JVM_ONLY="-Wl,-rpath,@loader_path/. -Wl,-rpath,@loader_path/.." - OS_LDFLAGS_JDK_ONLY="-mmacosx-version-min=$MACOSX_VERSION_MIN" + OS_LDFLAGS="-mmacosx-version-min=$MACOSX_VERSION_MIN" fi fi if test "x$TOOLCHAIN_TYPE" = xclang; then @@ -125,13 +134,6 @@ if test "x$OPENJDK_TARGET_OS" = xlinux; then if test x$DEBUG_LEVEL = xrelease; then DEBUGLEVEL_LDFLAGS_JDK_ONLY="$DEBUGLEVEL_LDFLAGS_JDK_ONLY -Wl,-O1" - else - # mark relocations read only on (fast/slow) debug builds - DEBUGLEVEL_LDFLAGS_JDK_ONLY="-Wl,-z,relro" - fi - if test x$DEBUG_LEVEL = xslowdebug; then - # do relocations at load - DEBUGLEVEL_LDFLAGS="-Wl,-z,now" fi fi @@ -147,6 +149,17 @@ # Setup LDFLAGS for linking executables if test "x$TOOLCHAIN_TYPE" = xgcc; then EXECUTABLE_LDFLAGS="$EXECUTABLE_LDFLAGS -Wl,--allow-shlib-undefined" + # Enabling pie on 32 bit builds prevents the JVM from allocating a continuous + # java heap. + if test "x$OPENJDK_TARGET_CPU_BITS" != "x32"; then + EXECUTABLE_LDFLAGS="$EXECUTABLE_LDFLAGS -pie" + fi + fi + + if test "x$ALLOW_ABSOLUTE_PATHS_IN_OUTPUT" = "xfalse"; then + if test "x$TOOLCHAIN_TYPE" = xmicrosoft; then + BASIC_LDFLAGS="$BASIC_LDFLAGS -pdbaltpath:%_PDB%" + fi fi # Export some intermediate variables for compatibility @@ -203,13 +216,13 @@ # Export variables according to old definitions, prefix with $2 if present. LDFLAGS_JDK_COMMON="$BASIC_LDFLAGS $BASIC_LDFLAGS_JDK_ONLY \ - $OS_LDFLAGS_JDK_ONLY $DEBUGLEVEL_LDFLAGS_JDK_ONLY ${$2EXTRA_LDFLAGS}" + $OS_LDFLAGS $DEBUGLEVEL_LDFLAGS_JDK_ONLY ${$2EXTRA_LDFLAGS}" $2LDFLAGS_JDKLIB="$LDFLAGS_JDK_COMMON $BASIC_LDFLAGS_JDK_LIB_ONLY \ ${$1_LDFLAGS_JDK_LIBPATH} $SHARED_LIBRARY_FLAGS" $2LDFLAGS_JDKEXE="$LDFLAGS_JDK_COMMON $EXECUTABLE_LDFLAGS \ ${$1_CPU_EXECUTABLE_LDFLAGS}" - $2JVM_LDFLAGS="$BASIC_LDFLAGS $BASIC_LDFLAGS_JVM_ONLY $OS_LDFLAGS_JVM_ONLY \ + $2JVM_LDFLAGS="$BASIC_LDFLAGS $BASIC_LDFLAGS_JVM_ONLY $OS_LDFLAGS $OS_LDFLAGS_JVM_ONLY \ $DEBUGLEVEL_LDFLAGS $DEBUGLEVEL_LDFLAGS_JVM_ONLY $BASIC_LDFLAGS_ONLYCXX \ ${$1_CPU_LDFLAGS} ${$1_CPU_LDFLAGS_JVM_ONLY} ${$2EXTRA_LDFLAGS}"
diff --git a/make/autoconf/flags-other.m4 b/make/autoconf/flags-other.m4 index ffd093e..5c9155b 100644 --- a/make/autoconf/flags-other.m4 +++ b/make/autoconf/flags-other.m4
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -31,9 +31,7 @@ AC_DEFUN([FLAGS_SETUP_ARFLAGS], [ # FIXME: figure out if we should select AR flags depending on OS or toolchain. - if test "x$OPENJDK_TARGET_OS" = xmacosx; then - ARFLAGS="-r -mmacosx-version-min=$MACOSX_VERSION_MIN" - elif test "x$OPENJDK_TARGET_OS" = xaix; then + if test "x$OPENJDK_TARGET_OS" = xaix; then ARFLAGS="-X64" elif test "x$OPENJDK_TARGET_OS" = xwindows; then # lib.exe is used as AR to create static libraries. @@ -109,6 +107,16 @@ [ if test "x$OPENJDK_TARGET_OS" = xmacosx; then JVM_BASIC_ASFLAGS="-x assembler-with-cpp -mno-omit-leaf-frame-pointer -mstack-alignment=16" + + # Fix linker warning. + # Code taken from make/autoconf/flags-cflags.m4 and adapted. + JVM_BASIC_ASFLAGS+=" -DMAC_OS_X_VERSION_MIN_REQUIRED=$MACOSX_VERSION_MIN_NODOTS \ + -mmacosx-version-min=$MACOSX_VERSION_MIN" + + if test -n "$MACOSX_VERSION_MAX"; then + JVM_BASIC_ASFLAGS+=" $OS_CFLAGS \ + -DMAC_OS_X_VERSION_MAX_ALLOWED=$MACOSX_VERSION_MAX_NODOTS" + fi fi ])
diff --git a/make/autoconf/flags.m4 b/make/autoconf/flags.m4 index 472e7a6..6f55353 100644 --- a/make/autoconf/flags.m4 +++ b/make/autoconf/flags.m4
@@ -162,6 +162,10 @@ AC_MSG_WARN([Ignoring LDFLAGS($LDFLAGS) found in environment. Use --with-extra-ldflags]) fi + if test "x$ASFLAGS" != "x"; then + AC_MSG_WARN([Ignoring ASFLAGS($ASFLAGS) found in environment. Use --with-extra-asflags]) + fi + AC_ARG_WITH(extra-cflags, [AS_HELP_STRING([--with-extra-cflags], [extra flags to be used when compiling jdk c-files])]) @@ -171,9 +175,13 @@ AC_ARG_WITH(extra-ldflags, [AS_HELP_STRING([--with-extra-ldflags], [extra flags to be used when linking jdk])]) + AC_ARG_WITH(extra-asflags, [AS_HELP_STRING([--with-extra-asflags], + [extra flags to be passed to the assembler])]) + USER_CFLAGS="$with_extra_cflags" USER_CXXFLAGS="$with_extra_cxxflags" USER_LDFLAGS="$with_extra_ldflags" + USER_ASFLAGS="$with_extra_asflags" ]) # Setup the sysroot flags and add them to global CFLAGS and LDFLAGS so @@ -216,10 +224,12 @@ # We also need -iframework<path>/System/Library/Frameworks $1SYSROOT_CFLAGS="[$]$1SYSROOT_CFLAGS -iframework [$]$1SYSROOT/System/Library/Frameworks" $1SYSROOT_LDFLAGS="[$]$1SYSROOT_LDFLAGS -iframework [$]$1SYSROOT/System/Library/Frameworks" - # These always need to be set, or we can't find the frameworks embedded in JavaVM.framework - # set this here so it doesn't have to be peppered throughout the forest - $1SYSROOT_CFLAGS="[$]$1SYSROOT_CFLAGS -F [$]$1SYSROOT/System/Library/Frameworks/JavaVM.framework/Frameworks" - $1SYSROOT_LDFLAGS="[$]$1SYSROOT_LDFLAGS -F [$]$1SYSROOT/System/Library/Frameworks/JavaVM.framework/Frameworks" + if test -d "[$]$1SYSROOT/System/Library/Frameworks/JavaVM.framework/Frameworks" ; then + # These always need to be set on macOS 10.X, or we can't find the frameworks embedded in JavaVM.framework + # set this here so it doesn't have to be peppered throughout the forest + $1SYSROOT_CFLAGS="[$]$1SYSROOT_CFLAGS -F [$]$1SYSROOT/System/Library/Frameworks/JavaVM.framework/Frameworks" + $1SYSROOT_LDFLAGS="[$]$1SYSROOT_LDFLAGS -F [$]$1SYSROOT/System/Library/Frameworks/JavaVM.framework/Frameworks" + fi fi AC_SUBST($1SYSROOT_CFLAGS) @@ -265,10 +275,12 @@ EXTRA_CFLAGS="$MACHINE_FLAG $USER_CFLAGS" EXTRA_CXXFLAGS="$MACHINE_FLAG $USER_CXXFLAGS" EXTRA_LDFLAGS="$MACHINE_FLAG $USER_LDFLAGS" + EXTRA_ASFLAGS="$USER_ASFLAGS" AC_SUBST(EXTRA_CFLAGS) AC_SUBST(EXTRA_CXXFLAGS) AC_SUBST(EXTRA_LDFLAGS) + AC_SUBST(EXTRA_ASFLAGS) # For autoconf testing to work, the global flags must also be stored in the # "unnamed" CFLAGS etc. @@ -335,8 +347,12 @@ CC_OUT_OPTION='-o$(SPACE)' # When linking, how to specify the output LD_OUT_OPTION='-o$(SPACE)' - # When archiving, how to specify the to be create static archive for object files. - AR_OUT_OPTION='rcs$(SPACE)' + # When archiving, how to specify the destination static archive. + if test "x$OPENJDK_TARGET_OS" = xmacosx; then + AR_OUT_OPTION='-r -cs$(SPACE)' + else + AR_OUT_OPTION='-rcs$(SPACE)' + fi fi AC_SUBST(CC_OUT_OPTION) AC_SUBST(LD_OUT_OPTION) @@ -402,17 +418,20 @@ # ------------------------------------------------------------ # Check that the C compiler supports an argument BASIC_DEFUN_NAMED([FLAGS_C_COMPILER_CHECK_ARGUMENTS], - [*ARGUMENT IF_TRUE IF_FALSE], [$@], + [*ARGUMENT IF_TRUE IF_FALSE PREFIX], [$@], [ - AC_MSG_CHECKING([if the C compiler supports "ARG_ARGUMENT"]) + AC_MSG_CHECKING([if ARG_PREFIX[CC] supports "ARG_ARGUMENT"]) supports=yes saved_cflags="$CFLAGS" + saved_cc="$CC" CFLAGS="$CFLAGS ARG_ARGUMENT" + CC="$ARG_PREFIX[CC]" AC_LANG_PUSH([C]) AC_COMPILE_IFELSE([AC_LANG_SOURCE([[int i;]])], [], [supports=no]) AC_LANG_POP([C]) + CC="$saved_cc" CFLAGS="$saved_cflags" AC_MSG_RESULT([$supports]) @@ -430,17 +449,20 @@ # ------------------------------------------------------------ # Check that the C++ compiler supports an argument BASIC_DEFUN_NAMED([FLAGS_CXX_COMPILER_CHECK_ARGUMENTS], - [*ARGUMENT IF_TRUE IF_FALSE], [$@], + [*ARGUMENT IF_TRUE IF_FALSE PREFIX], [$@], [ - AC_MSG_CHECKING([if the C++ compiler supports "ARG_ARGUMENT"]) + AC_MSG_CHECKING([if ARG_PREFIX[CXX] supports "ARG_ARGUMENT"]) supports=yes saved_cxxflags="$CXXFLAGS" + saved_cxx="$CXX" CXXFLAGS="$CXXFLAG ARG_ARGUMENT" + CXX="$ARG_PREFIX[CXX]" AC_LANG_PUSH([C++]) AC_COMPILE_IFELSE([AC_LANG_SOURCE([[int i;]])], [], [supports=no]) AC_LANG_POP([C++]) + CXX="$saved_cxx" CXXFLAGS="$saved_cxxflags" AC_MSG_RESULT([$supports]) @@ -458,18 +480,22 @@ # ------------------------------------------------------------ # Check that the C and C++ compilers support an argument BASIC_DEFUN_NAMED([FLAGS_COMPILER_CHECK_ARGUMENTS], - [*ARGUMENT IF_TRUE IF_FALSE], [$@], + [*ARGUMENT IF_TRUE IF_FALSE PREFIX], [$@], [ FLAGS_C_COMPILER_CHECK_ARGUMENTS(ARGUMENT: [ARG_ARGUMENT], - IF_TRUE: [C_COMP_SUPPORTS="yes"], - IF_FALSE: [C_COMP_SUPPORTS="no"]) + IF_TRUE: [C_COMP_SUPPORTS="yes"], + IF_FALSE: [C_COMP_SUPPORTS="no"], + PREFIX: [ARG_PREFIX]) FLAGS_CXX_COMPILER_CHECK_ARGUMENTS(ARGUMENT: [ARG_ARGUMENT], - IF_TRUE: [CXX_COMP_SUPPORTS="yes"], - IF_FALSE: [CXX_COMP_SUPPORTS="no"]) + IF_TRUE: [CXX_COMP_SUPPORTS="yes"], + IF_FALSE: [CXX_COMP_SUPPORTS="no"], + PREFIX: [ARG_PREFIX]) - AC_MSG_CHECKING([if both compilers support "ARG_ARGUMENT"]) + AC_MSG_CHECKING([if both ARG_PREFIX[CC] and ARG_PREFIX[CXX] support "ARG_ARGUMENT"]) supports=no - if test "x$C_COMP_SUPPORTS" = "xyes" -a "x$CXX_COMP_SUPPORTS" = "xyes"; then supports=yes; fi + if test "x$C_COMP_SUPPORTS" = "xyes" -a "x$CXX_COMP_SUPPORTS" = "xyes"; then + supports=yes; + fi AC_MSG_RESULT([$supports]) if test "x$supports" = "xyes" ; then
diff --git a/make/autoconf/help.m4 b/make/autoconf/help.m4 index eebfc68..bc05fc8 100644 --- a/make/autoconf/help.m4 +++ b/make/autoconf/help.m4
@@ -99,6 +99,8 @@ PKGHANDLER_COMMAND="sudo apt-get install libfontconfig1-dev" ;; freetype) PKGHANDLER_COMMAND="sudo apt-get install libfreetype6-dev" ;; + harfbuzz) + PKGHANDLER_COMMAND="sudo apt-get install libharfbuzz-dev" ;; ffi) PKGHANDLER_COMMAND="sudo apt-get install libffi-dev" ;; x11) @@ -124,6 +126,8 @@ PKGHANDLER_COMMAND="sudo yum install fontconfig-devel" ;; freetype) PKGHANDLER_COMMAND="sudo yum install freetype-devel" ;; + harfbuzz) + PKGHANDLER_COMMAND="sudo yum install harfbuzz-devel" ;; x11) PKGHANDLER_COMMAND="sudo yum install libXtst-devel libXt-devel libXrender-devel libXrandr-devel libXi-devel" ;; ccache)
diff --git a/make/autoconf/hotspot.m4 b/make/autoconf/hotspot.m4 index 1d4c710..d598b98 100644 --- a/make/autoconf/hotspot.m4 +++ b/make/autoconf/hotspot.m4
@@ -25,7 +25,7 @@ # All valid JVM features, regardless of platform VALID_JVM_FEATURES="compiler1 compiler2 zero minimal dtrace jvmti jvmci \ - graal vm-structs jni-check services management cmsgc epsilongc g1gc parallelgc serialgc zgc nmt cds \ + graal vm-structs jni-check services management cmsgc epsilongc g1gc parallelgc serialgc shenandoahgc zgc nmt cds \ static-build link-time-opt aot jfr" # Deprecated JVM features (these are ignored, but with a warning) @@ -47,8 +47,8 @@ [ [ [[ " $JVM_VARIANTS " =~ " $1 " ]] ] ]) ############################################################################### -# Check if the specified JVM features are explicitly enabled. To be used in -# shell if constructs, like this: +# Check if the specified JVM feature is enabled. To be used in shell if +# constructs, like this: # if HOTSPOT_CHECK_JVM_FEATURE(jvmti); then # # Only valid to use after HOTSPOT_SETUP_JVM_FEATURES has setup features. @@ -59,6 +59,20 @@ [ [ [[ " $JVM_FEATURES " =~ " $1 " ]] ] ]) ############################################################################### +# Check if the specified JVM feature is explicitly disabled. To be used in +# shell if constructs, like this: +# if HOTSPOT_IS_JVM_FEATURE_DISABLED(jvmci); then +# +# This function is internal to hotspot.m4, and is only used when constructing +# the valid set of enabled JVM features. Users outside of hotspot.m4 should just +# use HOTSPOT_CHECK_JVM_FEATURE to check if a feature is enabled or not. + +# Definition kept in one line to allow inlining in if statements. +# Additional [] needed to keep m4 from mangling shell constructs. +AC_DEFUN([HOTSPOT_IS_JVM_FEATURE_DISABLED], +[ [ [[ " $DISABLED_JVM_FEATURES " =~ " $1 " ]] ] ]) + +############################################################################### # Check which variants of the JVM that we want to build. Available variants are: # server: normal interpreter, and a tiered C1/C2 compiler # client: normal interpreter, and C1 (no C2 compiler) @@ -338,6 +352,19 @@ fi fi + # Only enable Shenandoah on supported arches, and only if requested + AC_MSG_CHECKING([if shenandoah can be built]) + if HOTSPOT_CHECK_JVM_FEATURE(shenandoahgc); then + if test "x$OPENJDK_TARGET_CPU_ARCH" = "xx86" || test "x$OPENJDK_TARGET_CPU" = "xaarch64" ; then + AC_MSG_RESULT([yes]) + else + DISABLED_JVM_FEATURES="$DISABLED_JVM_FEATURES shenandoahgc" + AC_MSG_RESULT([no, platform not supported]) + fi + else + DISABLED_JVM_FEATURES="$DISABLED_JVM_FEATURES shenandoahgc" + fi + # Only enable ZGC on supported platforms AC_MSG_CHECKING([if zgc can be built]) if test "x$OPENJDK_TARGET_OS" = "xlinux" && test "x$OPENJDK_TARGET_CPU" = "xx86_64"; then @@ -349,7 +376,7 @@ # Disable unsupported GCs for Zero if HOTSPOT_CHECK_JVM_VARIANT(zero); then - DISABLED_JVM_FEATURES="$DISABLED_JVM_FEATURES epsilongc g1gc zgc" + DISABLED_JVM_FEATURES="$DISABLED_JVM_FEATURES epsilongc g1gc shenandoahgc zgc" fi # Turn on additional features based on other parts of configure @@ -377,8 +404,7 @@ AC_MSG_CHECKING([if jvmci module jdk.internal.vm.ci should be built]) # Check if jvmci is diabled - DISABLE_JVMCI=`$ECHO $DISABLED_JVM_FEATURES | $GREP jvmci` - if test "x$DISABLE_JVMCI" = "xjvmci"; then + if HOTSPOT_IS_JVM_FEATURE_DISABLED(jvmci); then AC_MSG_RESULT([no, forced]) JVM_FEATURES_jvmci="" INCLUDE_JVMCI="false" @@ -404,8 +430,7 @@ AC_MSG_CHECKING([if graal module jdk.internal.vm.compiler should be built]) # Check if graal is diabled - DISABLE_GRAAL=`$ECHO $DISABLED_JVM_FEATURES | $GREP graal` - if test "x$DISABLE_GRAAL" = "xgraal"; then + if HOTSPOT_IS_JVM_FEATURE_DISABLED(graal); then AC_MSG_RESULT([no, forced]) JVM_FEATURES_graal="" INCLUDE_GRAAL="false" @@ -437,8 +462,7 @@ AC_SUBST(INCLUDE_GRAAL) # Disable aot with '--with-jvm-features=-aot' - DISABLE_AOT=`$ECHO $DISABLED_JVM_FEATURES | $GREP aot` - if test "x$DISABLE_AOT" = "xaot"; then + if HOTSPOT_IS_JVM_FEATURE_DISABLED(aot); then ENABLE_AOT="false" fi @@ -462,7 +486,7 @@ JVM_FEATURES_aot="aot" fi else - if test "x$enable_aot" = "xno" || test "x$DISABLE_AOT" = "xaot"; then + if test "x$enable_aot" = "xno" || HOTSPOT_IS_JVM_FEATURE_DISABLED(aot); then AC_MSG_RESULT([no, forced]) else AC_MSG_RESULT([no]) @@ -483,7 +507,7 @@ fi # All variants but minimal (and custom) get these features - NON_MINIMAL_FEATURES="$NON_MINIMAL_FEATURES cmsgc g1gc parallelgc serialgc epsilongc jni-check jvmti management nmt services vm-structs zgc" + NON_MINIMAL_FEATURES="$NON_MINIMAL_FEATURES cmsgc g1gc parallelgc serialgc epsilongc shenandoahgc jni-check jvmti management nmt services vm-structs zgc" AC_MSG_CHECKING([if cds should be enabled]) if test "x$ENABLE_CDS" = "xtrue"; then
diff --git a/make/autoconf/jdk-options.m4 b/make/autoconf/jdk-options.m4 index 5caccbd..9d64b31 100644 --- a/make/autoconf/jdk-options.m4 +++ b/make/autoconf/jdk-options.m4
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -283,7 +283,7 @@ AC_DEFUN_ONCE([JDKOPT_SETUP_DEBUG_SYMBOLS], [ # - # NATIVE_DEBUG_SYMBOLS + # Native debug symbols. # This must be done after the toolchain is setup, since we're looking at objcopy. # AC_MSG_CHECKING([what type of native debug symbols to use]) @@ -291,28 +291,43 @@ [AS_HELP_STRING([--with-native-debug-symbols], [set the native debug symbol configuration (none, internal, external, zipped) @<:@varying@:>@])], [ - if test "x$OPENJDK_TARGET_OS" = xaix; then - if test "x$withval" = xexternal || test "x$withval" = xzipped; then - AC_MSG_ERROR([AIX only supports the parameters 'none' and 'internal' for --with-native-debug-symbols]) + if test "x$OPENJDK_TARGET_OS" = xwindows; then + if test "x$withval" = xinternal; then + AC_MSG_ERROR([Windows does not support the parameter 'internal' for --with-native-debug-symbols]) fi fi ], [ - if test "x$OPENJDK_TARGET_OS" = xaix; then - # AIX doesn't support 'external' so use 'internal' as default - with_native_debug_symbols="internal" + if test "x$STATIC_BUILD" = xtrue; then + with_native_debug_symbols="none" else - if test "x$STATIC_BUILD" = xtrue; then - with_native_debug_symbols="none" - else - with_native_debug_symbols="external" - fi + with_native_debug_symbols="external" fi ]) - NATIVE_DEBUG_SYMBOLS=$with_native_debug_symbols - AC_MSG_RESULT([$NATIVE_DEBUG_SYMBOLS]) + AC_MSG_RESULT([$with_native_debug_symbols]) - if test "x$NATIVE_DEBUG_SYMBOLS" = xzipped; then + if test "x$with_native_debug_symbols" = xnone; then + COMPILE_WITH_DEBUG_SYMBOLS=false + COPY_DEBUG_SYMBOLS=false + ZIP_EXTERNAL_DEBUG_SYMBOLS=false + elif test "x$with_native_debug_symbols" = xinternal; then + COMPILE_WITH_DEBUG_SYMBOLS=true + COPY_DEBUG_SYMBOLS=false + ZIP_EXTERNAL_DEBUG_SYMBOLS=false + elif test "x$with_native_debug_symbols" = xexternal; then + + if test "x$OPENJDK_TARGET_OS" = xsolaris || test "x$OPENJDK_TARGET_OS" = xlinux; then + if test "x$OBJCOPY" = x; then + # enabling of enable-debug-symbols and can't find objcopy + # this is an error + AC_MSG_ERROR([Unable to find objcopy, cannot enable native debug symbols]) + fi + fi + + COMPILE_WITH_DEBUG_SYMBOLS=true + COPY_DEBUG_SYMBOLS=true + ZIP_EXTERNAL_DEBUG_SYMBOLS=false + elif test "x$with_native_debug_symbols" = xzipped; then if test "x$OPENJDK_TARGET_OS" = xsolaris || test "x$OPENJDK_TARGET_OS" = xlinux; then if test "x$OBJCOPY" = x; then @@ -325,27 +340,6 @@ COMPILE_WITH_DEBUG_SYMBOLS=true COPY_DEBUG_SYMBOLS=true ZIP_EXTERNAL_DEBUG_SYMBOLS=true - elif test "x$NATIVE_DEBUG_SYMBOLS" = xnone; then - COMPILE_WITH_DEBUG_SYMBOLS=false - COPY_DEBUG_SYMBOLS=false - ZIP_EXTERNAL_DEBUG_SYMBOLS=false - elif test "x$NATIVE_DEBUG_SYMBOLS" = xinternal; then - COMPILE_WITH_DEBUG_SYMBOLS=true - COPY_DEBUG_SYMBOLS=false - ZIP_EXTERNAL_DEBUG_SYMBOLS=false - elif test "x$NATIVE_DEBUG_SYMBOLS" = xexternal; then - - if test "x$OPENJDK_TARGET_OS" = xsolaris || test "x$OPENJDK_TARGET_OS" = xlinux; then - if test "x$OBJCOPY" = x; then - # enabling of enable-debug-symbols and can't find objcopy - # this is an error - AC_MSG_ERROR([Unable to find objcopy, cannot enable native debug symbols]) - fi - fi - - COMPILE_WITH_DEBUG_SYMBOLS=true - COPY_DEBUG_SYMBOLS=true - ZIP_EXTERNAL_DEBUG_SYMBOLS=false else AC_MSG_ERROR([Allowed native debug symbols are: none, internal, external, zipped]) fi @@ -363,6 +357,33 @@ AC_SUBST(COMPILE_WITH_DEBUG_SYMBOLS) AC_SUBST(COPY_DEBUG_SYMBOLS) AC_SUBST(ZIP_EXTERNAL_DEBUG_SYMBOLS) + + # Should we add external native debug symbols to the shipped bundles? + AC_MSG_CHECKING([if we should add external native debug symbols to the shipped bundles]) + AC_ARG_WITH([external-symbols-in-bundles], + [AS_HELP_STRING([--with-external-symbols-in-bundles], + [which type of external native debug symbol information shall be shipped in product bundles (none, public, full) + (e.g. ship full/stripped pdbs on Windows) @<:@none@:>@])]) + + if test "x$with_external_symbols_in_bundles" = x || test "x$with_external_symbols_in_bundles" = xnone ; then + AC_MSG_RESULT([no]) + elif test "x$with_external_symbols_in_bundles" = xfull || test "x$with_external_symbols_in_bundles" = xpublic ; then + if test "x$OPENJDK_TARGET_OS" != xwindows ; then + AC_MSG_ERROR([--with-external-symbols-in-bundles currently only works on windows!]) + elif test "x$COPY_DEBUG_SYMBOLS" != xtrue ; then + AC_MSG_ERROR([--with-external-symbols-in-bundles only works when --with-native-debug-symbols=external is used!]) + elif test "x$with_external_symbols_in_bundles" = xfull ; then + AC_MSG_RESULT([full]) + SHIP_DEBUG_SYMBOLS=full + else + AC_MSG_RESULT([public]) + SHIP_DEBUG_SYMBOLS=public + fi + else + AC_MSG_ERROR([$with_external_symbols_in_bundles is an unknown value for --with-external-symbols-in-bundles]) + fi + + AC_SUBST(SHIP_DEBUG_SYMBOLS) ]) ################################################################################ @@ -630,3 +651,35 @@ AC_SUBST(BUILD_MANPAGES) ]) + +################################################################################ +# +# Disallow any output from containing absolute paths from the build system. +# This setting defaults to allowed on debug builds and not allowed on release +# builds. +# +AC_DEFUN([JDKOPT_ALLOW_ABSOLUTE_PATHS_IN_OUTPUT], +[ + AC_ARG_ENABLE([absolute-paths-in-output], + [AS_HELP_STRING([--disable-absolute-paths-in-output], + [Set to disable to prevent any absolute paths from the build to end up in + any of the build output. @<:@disabled in release builds, otherwise enabled@:>@]) + ]) + + AC_MSG_CHECKING([if absolute paths should be allowed in the build output]) + if test "x$enable_absolute_paths_in_output" = "xno"; then + AC_MSG_RESULT([no, forced]) + ALLOW_ABSOLUTE_PATHS_IN_OUTPUT="false" + elif test "x$enable_absolute_paths_in_output" = "xyes"; then + AC_MSG_RESULT([yes, forced]) + ALLOW_ABSOLUTE_PATHS_IN_OUTPUT="true" + elif test "x$DEBUG_LEVEL" = "xrelease"; then + AC_MSG_RESULT([no, release build]) + ALLOW_ABSOLUTE_PATHS_IN_OUTPUT="false" + else + AC_MSG_RESULT([yes, debug build]) + ALLOW_ABSOLUTE_PATHS_IN_OUTPUT="true" + fi + + AC_SUBST(ALLOW_ABSOLUTE_PATHS_IN_OUTPUT) +])
diff --git a/make/autoconf/jdk-version.m4 b/make/autoconf/jdk-version.m4 index 6a72718..ede4e00 100644 --- a/make/autoconf/jdk-version.m4 +++ b/make/autoconf/jdk-version.m4
@@ -143,7 +143,9 @@ AC_MSG_ERROR([--with-vendor-url must have a value]) elif [ ! [[ $with_vendor_url =~ ^[[:print:]]*$ ]] ]; then AC_MSG_ERROR([--with-vendor-url contains non-printing characters: $with_vendor_url]) - else + elif test "x$with_vendor_url" != x; then + # Only set VENDOR_URL if '--with-vendor-url' was used and is not empty. + # Otherwise we will use the value from "version-numbers" included above. VENDOR_URL="$with_vendor_url" fi AC_SUBST(VENDOR_URL) @@ -155,7 +157,9 @@ AC_MSG_ERROR([--with-vendor-bug-url must have a value]) elif [ ! [[ $with_vendor_bug_url =~ ^[[:print:]]*$ ]] ]; then AC_MSG_ERROR([--with-vendor-bug-url contains non-printing characters: $with_vendor_bug_url]) - else + elif test "x$with_vendor_bug_url" != x; then + # Only set VENDOR_URL_BUG if '--with-vendor-bug-url' was used and is not empty. + # Otherwise we will use the value from "version-numbers" included above. VENDOR_URL_BUG="$with_vendor_bug_url" fi AC_SUBST(VENDOR_URL_BUG) @@ -167,7 +171,9 @@ AC_MSG_ERROR([--with-vendor-vm-bug-url must have a value]) elif [ ! [[ $with_vendor_vm_bug_url =~ ^[[:print:]]*$ ]] ]; then AC_MSG_ERROR([--with-vendor-vm-bug-url contains non-printing characters: $with_vendor_vm_bug_url]) - else + elif test "x$with_vendor_vm_bug_url" != x; then + # Only set VENDOR_URL_VM_BUG if '--with-vendor-vm-bug-url' was used and is not empty. + # Otherwise we will use the value from "version-numbers" included above. VENDOR_URL_VM_BUG="$with_vendor_vm_bug_url" fi AC_SUBST(VENDOR_URL_VM_BUG)
diff --git a/make/autoconf/lib-bundled.m4 b/make/autoconf/lib-bundled.m4 index 0680a99..f5c11d4 100644 --- a/make/autoconf/lib-bundled.m4 +++ b/make/autoconf/lib-bundled.m4
@@ -37,6 +37,7 @@ LIB_SETUP_LIBPNG LIB_SETUP_ZLIB LIB_SETUP_LCMS + LIB_SETUP_HARFBUZZ ]) ################################################################################ @@ -260,3 +261,43 @@ AC_SUBST(LCMS_CFLAGS) AC_SUBST(LCMS_LIBS) ]) + +################################################################################ +# Setup harfbuzz +################################################################################ +AC_DEFUN_ONCE([LIB_SETUP_HARFBUZZ], +[ + AC_ARG_WITH(harfbuzz, [AS_HELP_STRING([--with-harfbuzz], + [use harfbuzz from build system or OpenJDK source (system, bundled) @<:@bundled@:>@])]) + + AC_MSG_CHECKING([for which harfbuzz to use]) + + DEFAULT_HARFBUZZ=bundled + # If user didn't specify, use DEFAULT_HARFBUZZ + if test "x${with_harfbuzz}" = "x"; then + with_harfbuzz=${DEFAULT_HARFBUZZ} + fi + + if test "x${with_harfbuzz}" = "xbundled"; then + USE_EXTERNAL_HARFBUZZ=false + HARFBUZZ_CFLAGS="" + HARFBUZZ_LIBS="" + AC_MSG_RESULT([bundled]) + elif test "x${with_harfbuzz}" = "xsystem"; then + AC_MSG_RESULT([system]) + PKG_CHECK_MODULES([HARFBUZZ], [harfbuzz], [HARFBUZZ_FOUND=yes], [HARFBUZZ_FOUND=no]) + if test "x${HARFBUZZ_FOUND}" = "xyes"; then + # PKG_CHECK_MODULES will set HARFBUZZ_CFLAGS and HARFBUZZ_LIBS + USE_EXTERNAL_HARFBUZZ=true + else + HELP_MSG_MISSING_DEPENDENCY([harfbuzz]) + AC_MSG_ERROR([--with-harfbuzz=system specified, but no harfbuzz found! $HELP_MSG]) + fi + else + AC_MSG_ERROR([Invalid value for --with-harfbuzz: ${with_harfbuzz}, use 'system' or 'bundled']) + fi + + AC_SUBST(USE_EXTERNAL_HARFBUZZ) + AC_SUBST(HARFBUZZ_CFLAGS) + AC_SUBST(HARFBUZZ_LIBS) +])
diff --git a/make/autoconf/lib-ffi.m4 b/make/autoconf/lib-ffi.m4 index 2a714f3..70fc749 100644 --- a/make/autoconf/lib-ffi.m4 +++ b/make/autoconf/lib-ffi.m4
@@ -85,6 +85,20 @@ [LIBFFI_FOUND=no] ) fi + # on macos we need a special case for system's libffi as + # headers are located only in sdk in $SYSROOT and in ffi subfolder + if test "x$LIBFFI_FOUND" = xno; then + if test "x$SYSROOT" != "x"; then + AC_CHECK_HEADER([$SYSROOT/usr/include/ffi/ffi.h], + [ + LIBFFI_FOUND=yes + LIBFFI_CFLAGS="-I${SYSROOT}/usr/include/ffi" + LIBFFI_LIBS=-lffi + ], + [LIBFFI_FOUND=no] + ) + fi + fi if test "x$LIBFFI_FOUND" = xno; then HELP_MSG_MISSING_DEPENDENCY([ffi]) AC_MSG_ERROR([Could not find libffi! $HELP_MSG])
diff --git a/make/autoconf/lib-freetype.m4 b/make/autoconf/lib-freetype.m4 index d3cb515..99e9ebe 100644 --- a/make/autoconf/lib-freetype.m4 +++ b/make/autoconf/lib-freetype.m4
@@ -173,6 +173,16 @@ FREETYPE_BASE_DIR="$SYSROOT/usr" LIB_CHECK_POTENTIAL_FREETYPE([$FREETYPE_BASE_DIR/include], [$FREETYPE_BASE_DIR/lib], [well-known location]) + if test "x$FOUND_FREETYPE" != "xyes" ; then + LIB_CHECK_POTENTIAL_FREETYPE([$FREETYPE_BASE_DIR/include], + [$FREETYPE_BASE_DIR/lib/$OPENJDK_TARGET_CPU-$OPENJDK_TARGET_OS-$OPENJDK_TARGET_ABI], [well-known location]) + fi + + if test "x$FOUND_FREETYPE" != "xyes" ; then + LIB_CHECK_POTENTIAL_FREETYPE([$FREETYPE_BASE_DIR/include], + [$FREETYPE_BASE_DIR/lib/$OPENJDK_TARGET_CPU_AUTOCONF-$OPENJDK_TARGET_OS-$OPENJDK_TARGET_ABI], [well-known location]) + fi + if (test "x$FOUND_FREETYPE" != "xyes"); then FREETYPE_BASE_DIR="$SYSROOT/usr/X11" LIB_CHECK_POTENTIAL_FREETYPE([$FREETYPE_BASE_DIR/include], [$FREETYPE_BASE_DIR/lib], [well-known location])
diff --git a/make/autoconf/lib-x11.m4 b/make/autoconf/lib-x11.m4 index df3eb0f..d862c02 100644 --- a/make/autoconf/lib-x11.m4 +++ b/make/autoconf/lib-x11.m4
@@ -68,6 +68,10 @@ x_libraries="$SYSROOT/usr/lib64" elif test -f "$SYSROOT/usr/lib/libX11.so"; then x_libraries="$SYSROOT/usr/lib" + elif test -f "$SYSROOT/usr/lib/$OPENJDK_TARGET_CPU-$OPENJDK_TARGET_OS-$OPENJDK_TARGET_ABI/libX11.so"; then + x_libraries="$SYSROOT/usr/lib/$OPENJDK_TARGET_CPU-$OPENJDK_TARGET_OS-$OPENJDK_TARGET_ABI/libX11.so" + elif test -f "$SYSROOT/usr/lib/$OPENJDK_TARGET_CPU_AUTOCONF-$OPENJDK_TARGET_OS-$OPENJDK_TARGET_ABI/libX11.so"; then + x_libraries="$SYSROOT/usr/lib/$OPENJDK_TARGET_CPU_AUTOCONF-$OPENJDK_TARGET_OS-$OPENJDK_TARGET_ABI/libX11.so" fi fi fi @@ -117,7 +121,7 @@ if test "x$X11_HEADERS_OK" = xno; then HELP_MSG_MISSING_DEPENDENCY([x11]) - AC_MSG_ERROR([Could not find all X11 headers (shape.h Xrender.h Xrander.h XTest.h Intrinsic.h). $HELP_MSG]) + AC_MSG_ERROR([Could not find all X11 headers (shape.h Xrender.h Xrandr.h XTest.h Intrinsic.h). $HELP_MSG]) fi # If XLinearGradient isn't available in Xrender.h, signal that it needs to be
diff --git a/make/autoconf/libraries.m4 b/make/autoconf/libraries.m4 index ab40c8b..a73c0f3 100644 --- a/make/autoconf/libraries.m4 +++ b/make/autoconf/libraries.m4
@@ -130,6 +130,11 @@ BASIC_JVM_LIBS="$BASIC_JVM_LIBS -lthread" fi + # perfstat lib + if test "x$OPENJDK_TARGET_OS" = xaix; then + BASIC_JVM_LIBS="$BASIC_JVM_LIBS -lperfstat" + fi + if test "x$OPENJDK_TARGET_OS" = xsolaris; then BASIC_JVM_LIBS="$BASIC_JVM_LIBS -lsocket -lsched -ldoor -ldemangle -lnsl \ -lrt -lkstat"
diff --git a/make/autoconf/platform.m4 b/make/autoconf/platform.m4 index e06c11a..edbb54d 100644 --- a/make/autoconf/platform.m4 +++ b/make/autoconf/platform.m4
@@ -196,6 +196,33 @@ esac ]) +# Support macro for PLATFORM_EXTRACT_TARGET_AND_BUILD. +# Converts autoconf style OS name to OpenJDK style, into +# VAR_ABI. +AC_DEFUN([PLATFORM_EXTRACT_VARS_FROM_ABI], +[ + case "$1" in + *linux*-musl) + VAR_ABI=musl + ;; + *linux*-gnu) + VAR_ABI=gnu + ;; + *linux*-gnueabi) + VAR_ABI=gnueabi + ;; + *linux*-gnueabihf) + VAR_ABI=gnueabihf + ;; + *linux*-gnuabi64) + VAR_ABI=gnuabi64 + ;; + *) + VAR_ABI=default + ;; + esac +]) + # Expects $host_os $host_cpu $build_os and $build_cpu # and $with_target_bits to have been setup! # @@ -216,6 +243,7 @@ # Convert the autoconf OS/CPU value to our own data, into the VAR_OS/CPU variables. PLATFORM_EXTRACT_VARS_FROM_OS($build_os) PLATFORM_EXTRACT_VARS_FROM_CPU($build_cpu) + PLATFORM_EXTRACT_VARS_FROM_ABI($build_os) # ..and setup our own variables. (Do this explicitly to facilitate searching) OPENJDK_BUILD_OS="$VAR_OS" if test "x$VAR_OS_TYPE" != x; then @@ -232,6 +260,8 @@ OPENJDK_BUILD_CPU_ARCH="$VAR_CPU_ARCH" OPENJDK_BUILD_CPU_BITS="$VAR_CPU_BITS" OPENJDK_BUILD_CPU_ENDIAN="$VAR_CPU_ENDIAN" + OPENJDK_BUILD_CPU_AUTOCONF="$build_cpu" + OPENJDK_BUILD_ABI="$VAR_ABI" AC_SUBST(OPENJDK_BUILD_OS) AC_SUBST(OPENJDK_BUILD_OS_TYPE) AC_SUBST(OPENJDK_BUILD_OS_ENV) @@ -239,6 +269,8 @@ AC_SUBST(OPENJDK_BUILD_CPU_ARCH) AC_SUBST(OPENJDK_BUILD_CPU_BITS) AC_SUBST(OPENJDK_BUILD_CPU_ENDIAN) + AC_SUBST(OPENJDK_BUILD_CPU_AUTOCONF) + AC_SUBST(OPENJDK_BUILD_ABI) AC_MSG_CHECKING([openjdk-build os-cpu]) AC_MSG_RESULT([$OPENJDK_BUILD_OS-$OPENJDK_BUILD_CPU]) @@ -246,6 +278,7 @@ # Convert the autoconf OS/CPU value to our own data, into the VAR_OS/CPU variables. PLATFORM_EXTRACT_VARS_FROM_OS($host_os) PLATFORM_EXTRACT_VARS_FROM_CPU($host_cpu) + PLATFORM_EXTRACT_VARS_FROM_ABI($host_os) # ... and setup our own variables. (Do this explicitly to facilitate searching) OPENJDK_TARGET_OS="$VAR_OS" if test "x$VAR_OS_TYPE" != x; then @@ -262,7 +295,9 @@ OPENJDK_TARGET_CPU_ARCH="$VAR_CPU_ARCH" OPENJDK_TARGET_CPU_BITS="$VAR_CPU_BITS" OPENJDK_TARGET_CPU_ENDIAN="$VAR_CPU_ENDIAN" + OPENJDK_TARGET_CPU_AUTOCONF="$host_cpu" OPENJDK_TARGET_OS_UPPERCASE=`$ECHO $OPENJDK_TARGET_OS | $TR 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + OPENJDK_TARGET_ABI="$VAR_ABI" AC_SUBST(OPENJDK_TARGET_OS) AC_SUBST(OPENJDK_TARGET_OS_TYPE) @@ -272,6 +307,8 @@ AC_SUBST(OPENJDK_TARGET_CPU_ARCH) AC_SUBST(OPENJDK_TARGET_CPU_BITS) AC_SUBST(OPENJDK_TARGET_CPU_ENDIAN) + AC_SUBST(OPENJDK_TARGET_CPU_AUTOCONF) + AC_SUBST(OPENJDK_TARGET_ABI) AC_MSG_CHECKING([openjdk-target os-cpu]) AC_MSG_RESULT([$OPENJDK_TARGET_OS-$OPENJDK_TARGET_CPU])
diff --git a/make/autoconf/spec.gmk.in b/make/autoconf/spec.gmk.in index 390b9d6..39b4439 100644 --- a/make/autoconf/spec.gmk.in +++ b/make/autoconf/spec.gmk.in
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -130,8 +130,9 @@ # The top-level directory of the source repository TOPDIR:=@TOPDIR@ - - +# Usually the top level directory, but could be something else if a custom +# root is defined. +WORKSPACE_ROOT:=@WORKSPACE_ROOT@ IMPORT_MODULES_CLASSES:=@IMPORT_MODULES_CLASSES@ IMPORT_MODULES_CMDS:=@IMPORT_MODULES_CMDS@ IMPORT_MODULES_LIBS:=@IMPORT_MODULES_LIBS@ @@ -229,7 +230,8 @@ # Only export "VENDOR" to the build if COMPANY_NAME contains a real value. # Otherwise the default value for VENDOR, which is used to set the "java.vendor" # and "java.vm.vendor" properties is hard-coded into the source code (i.e. in - # System.c in the jdk for "vm.vendor" and vm_version.cpp in the VM for "java.vm.vendor") + # VersionProps.java.template in the jdk for "java.vendor" and + # vm_version.cpp in the VM for "java.vm.vendor") ifneq ($(COMPANY_NAME), N/A) VERSION_CFLAGS += -DVENDOR='"$(COMPANY_NAME)"' endif @@ -285,6 +287,9 @@ # Only build headless support or not ENABLE_HEADLESS_ONLY := @ENABLE_HEADLESS_ONLY@ +# Ship debug symbols (e.g. pdbs on Windows) +SHIP_DEBUG_SYMBOLS := @SHIP_DEBUG_SYMBOLS@ + ENABLE_FULL_DOCS := @ENABLE_FULL_DOCS@ # JDK_OUTPUTDIR specifies where a working jvm is built. @@ -314,6 +319,8 @@ BUILD_MANPAGES := @BUILD_MANPAGES@ +ALLOW_ABSOLUTE_PATHS_IN_OUTPUT := @ALLOW_ABSOLUTE_PATHS_IN_OUTPUT@ + # The boot jdk to use. This is overridden in bootcycle-spec.gmk. Make sure to keep # it in sync. BOOT_JDK:=@BOOT_JDK@ @@ -357,6 +364,9 @@ ENABLE_LIBFFI_BUNDLING:=@ENABLE_LIBFFI_BUNDLING@ LIBFFI_LIB_FILE:=@LIBFFI_LIB_FILE@ GRAALUNIT_LIB := @GRAALUNIT_LIB@ +FILE_MACRO_CFLAGS := @FILE_MACRO_CFLAGS@ + +STATIC_LIBS_CFLAGS := @STATIC_LIBS_CFLAGS@ PACKAGE_PATH=@PACKAGE_PATH@ @@ -372,7 +382,7 @@ export ASAN_ENABLED:=@ASAN_ENABLED@ export DEVKIT_LIB_DIR:=@DEVKIT_LIB_DIR@ ifeq ($(ASAN_ENABLED), yes) - export ASAN_OPTIONS="handle_segv=0 detect_leaks=0" + export ASAN_OPTIONS=handle_segv=0 detect_leaks=0 ifneq ($(DEVKIT_LIB_DIR),) export LD_LIBRARY_PATH:=$(LD_LIBRARY_PATH):$(DEVKIT_LIB_DIR) endif @@ -387,6 +397,9 @@ # The highest allowed version of macosx MACOSX_VERSION_MAX=@MACOSX_VERSION_MAX@ +# The macosx code signing identity to use +MACOSX_CODESIGN_IDENTITY=@MACOSX_CODESIGN_IDENTITY@ + # Toolchain type: gcc, clang, solstudio, lxc, microsoft... TOOLCHAIN_TYPE:=@TOOLCHAIN_TYPE@ TOOLCHAIN_VERSION := @TOOLCHAIN_VERSION@ @@ -462,6 +475,7 @@ EXTRA_CFLAGS = @EXTRA_CFLAGS@ EXTRA_CXXFLAGS = @EXTRA_CXXFLAGS@ EXTRA_LDFLAGS = @EXTRA_LDFLAGS@ +EXTRA_ASFLAGS = @EXTRA_ASFLAGS@ CXX:=@FIXPATH@ @CCACHE@ @ICECC@ @CXX@ @@ -470,6 +484,9 @@ # The linker can be gcc or ld on unix systems, or link.exe on windows systems. LD:=@FIXPATH@ @LD@ +# Linker used by the jaotc tool for AOT compilation. +LD_JAOTC:=@LD_JAOTC@ + # Xcode SDK path SDKROOT:=@SDKROOT@ @@ -600,7 +617,7 @@ JAVAC=@FIXPATH@ $(JAVAC_CMD) JAVADOC=@FIXPATH@ $(JAVADOC_CMD) JAR=@FIXPATH@ $(JAR_CMD) -JLINK = @FIXPATH@ $(JLINK_CMD) $(JAVA_TOOL_FLAGS_SMALL) +JLINK = @FIXPATH@ $(JLINK_CMD) JMOD = @FIXPATH@ $(JMOD_CMD) $(JAVA_TOOL_FLAGS_SMALL) JARSIGNER=@FIXPATH@ $(JARSIGNER_CMD) # A specific java binary with specific options can be used to run @@ -731,7 +748,7 @@ XATTR:=@XATTR@ JT_HOME:=@JT_HOME@ JTREGEXE:=@JTREGEXE@ -JIB_JAR:=@JIB_JAR@ +JIB_HOME:=@JIB_HOME@ XCODEBUILD=@XCODEBUILD@ DTRACE := @DTRACE@ FIXPATH:=@FIXPATH@ @@ -815,6 +832,10 @@ LCMS_CFLAGS:=@LCMS_CFLAGS@ LCMS_LIBS:=@LCMS_LIBS@ +USE_EXTERNAL_HARFBUZZ:=@USE_EXTERNAL_HARFBUZZ@ +HARFBUZZ_CFLAGS:=@HARFBUZZ_CFLAGS@ +HARFBUZZ_LIBS:=@HARFBUZZ_LIBS@ + USE_EXTERNAL_LIBPNG:=@USE_EXTERNAL_LIBPNG@ PNG_LIBS:=@PNG_LIBS@ PNG_CFLAGS:=@PNG_CFLAGS@ @@ -858,13 +879,27 @@ # Output docs directly into image DOCS_OUTPUTDIR := $(DOCS_IMAGE_DIR) +# Static libs image +STATIC_LIBS_IMAGE_SUBDIR := static-libs +STATIC_LIBS_IMAGE_DIR := $(IMAGES_OUTPUTDIR)/$(STATIC_LIBS_IMAGE_SUBDIR) + +# Graal builder image +GRAAL_BUILDER_IMAGE_SUBDIR := graal-builder-jdk +GRAAL_BUILDER_IMAGE_DIR := $(IMAGES_OUTPUTDIR)/$(GRAAL_BUILDER_IMAGE_SUBDIR) + # Macosx bundles directory definitions JDK_MACOSX_BUNDLE_SUBDIR=jdk-bundle JRE_MACOSX_BUNDLE_SUBDIR=jre-bundle +JDK_MACOSX_BUNDLE_SUBDIR_SIGNED=jdk-bundle-signed +JRE_MACOSX_BUNDLE_SUBDIR_SIGNED=jre-bundle-signed JDK_MACOSX_BUNDLE_DIR=$(IMAGES_OUTPUTDIR)/$(JDK_MACOSX_BUNDLE_SUBDIR) JRE_MACOSX_BUNDLE_DIR=$(IMAGES_OUTPUTDIR)/$(JRE_MACOSX_BUNDLE_SUBDIR) -JDK_MACOSX_CONTENTS_SUBDIR=jdk-$(VERSION_NUMBER).jdk/Contents -JRE_MACOSX_CONTENTS_SUBDIR=jre-$(VERSION_NUMBER).jre/Contents +JDK_MACOSX_BUNDLE_DIR_SIGNED=$(IMAGES_OUTPUTDIR)/$(JDK_MACOSX_BUNDLE_SUBDIR_SIGNED) +JRE_MACOSX_BUNDLE_DIR_SIGNED=$(IMAGES_OUTPUTDIR)/$(JRE_MACOSX_BUNDLE_SUBDIR_SIGNED) +JDK_MACOSX_BUNDLE_TOP_DIR=jdk-$(VERSION_NUMBER).jdk +JRE_MACOSX_BUNDLE_TOP_DIR=jre-$(VERSION_NUMBER).jre +JDK_MACOSX_CONTENTS_SUBDIR=$(JDK_MACOSX_BUNDLE_TOP_DIR)/Contents +JRE_MACOSX_CONTENTS_SUBDIR=$(JRE_MACOSX_BUNDLE_TOP_DIR)/Contents JDK_MACOSX_CONTENTS_DIR=$(JDK_MACOSX_BUNDLE_DIR)/$(JDK_MACOSX_CONTENTS_SUBDIR) JRE_MACOSX_CONTENTS_DIR=$(JRE_MACOSX_BUNDLE_DIR)/$(JRE_MACOSX_CONTENTS_SUBDIR) @@ -886,6 +921,7 @@ TEST_DEMOS_BUNDLE_NAME := jdk-$(BASE_NAME)_bin-tests-demos$(DEBUG_PART).tar.gz TEST_BUNDLE_NAME := jdk-$(BASE_NAME)_bin-tests$(DEBUG_PART).tar.gz DOCS_BUNDLE_NAME := jdk-$(BASE_NAME)_doc-api-spec$(DEBUG_PART).tar.gz +STATIC_LIBS_BUNDLE_NAME := jdk-$(BASE_NAME)_bin-static-libs$(DEBUG_PART).tar.gz JDK_BUNDLE := $(BUNDLES_OUTPUTDIR)/$(JDK_BUNDLE_NAME) JRE_BUNDLE := $(BUNDLES_OUTPUTDIR)/$(JRE_BUNDLE_NAME)
diff --git a/make/autoconf/toolchain.m4 b/make/autoconf/toolchain.m4 index 91fabcd..3c0286d 100644 --- a/make/autoconf/toolchain.m4 +++ b/make/autoconf/toolchain.m4
@@ -429,9 +429,10 @@ # There is no specific version flag, but all output starts with a version string. # First line typically looks something like: # Microsoft (R) 32-bit C/C++ Optimizing Compiler Version 16.00.40219.01 for 80x86 + # but the compiler name may vary depending on locale. COMPILER_VERSION_OUTPUT=`$COMPILER 2>&1 | $HEAD -n 1 | $TR -d '\r'` # Check that this is likely to be Microsoft CL.EXE. - $ECHO "$COMPILER_VERSION_OUTPUT" | $GREP "Microsoft.*Compiler" > /dev/null + $ECHO "$COMPILER_VERSION_OUTPUT" | $GREP "Microsoft" > /dev/null if test $? -ne 0; then AC_MSG_NOTICE([The $COMPILER_NAME compiler (located as $COMPILER) does not seem to be the required $TOOLCHAIN_TYPE compiler.]) AC_MSG_NOTICE([The result from running it was: "$COMPILER_VERSION_OUTPUT"]) @@ -460,7 +461,7 @@ COMPILER_VERSION_STRING=`$ECHO $COMPILER_VERSION_OUTPUT | \ $SED -e 's/ *Copyright .*//'` COMPILER_VERSION_NUMBER=`$ECHO $COMPILER_VERSION_OUTPUT | \ - $SED -e 's/^.* \(@<:@1-9@:>@\.@<:@0-9.@:>@*\)@<:@^0-9.@:>@.*$/\1/'` + $SED -e 's/^.* \(@<:@1-9@:>@<:@0-9@:>@*\.@<:@0-9.@:>@*\)@<:@^0-9.@:>@.*$/\1/'` elif test "x$TOOLCHAIN_TYPE" = xclang; then # clang --version output typically looks like # Apple LLVM version 5.0 (clang-500.2.79) (based on LLVM 3.3svn) @@ -589,7 +590,7 @@ AC_DEFUN([TOOLCHAIN_EXTRACT_LD_VERSION], [ LINKER=[$]$1 - LINKER_NAME=$2 + LINKER_NAME="$2" if test "x$TOOLCHAIN_TYPE" = xsolstudio; then # cc -Wl,-V output typically looks like @@ -709,12 +710,18 @@ AC_MSG_RESULT([yes]) fi LDCXX="$LD" + # jaotc being a windows program expects the linker to be supplied with exe suffix. + LD_JAOTC="$LD$EXE_SUFFIX" else # All other toolchains use the compiler to link. LD="$CC" LDCXX="$CXX" + # jaotc expects 'ld' as the linker rather than the compiler. + BASIC_CHECK_TOOLS([LD_JAOTC], ld) + BASIC_FIXUP_EXECUTABLE(LD_JAOTC) fi AC_SUBST(LD) + AC_SUBST(LD_JAOTC) # FIXME: it should be CXXLD, according to standard (cf CXXCPP) AC_SUBST(LDCXX) @@ -941,9 +948,14 @@ # FIXME: we should list the discovered compilers as an exclude pattern! # If we do that, we can do this detection before POST_DETECTION, and still # find the build compilers in the tools dir, if needed. - BASIC_REQUIRE_PROGS(BUILD_CC, [cl cc gcc]) + if test "x$OPENJDK_BUILD_OS" = xmacosx; then + BASIC_REQUIRE_PROGS(BUILD_CC, [clang cl cc gcc]) + BASIC_REQUIRE_PROGS(BUILD_CXX, [clang++ cl CC g++]) + else + BASIC_REQUIRE_PROGS(BUILD_CC, [cl cc gcc]) + BASIC_REQUIRE_PROGS(BUILD_CXX, [cl CC g++]) + fi BASIC_FIXUP_EXECUTABLE(BUILD_CC) - BASIC_REQUIRE_PROGS(BUILD_CXX, [cl CC g++]) BASIC_FIXUP_EXECUTABLE(BUILD_CXX) BASIC_PATH_PROGS(BUILD_NM, nm gcc-nm) BASIC_FIXUP_EXECUTABLE(BUILD_NM) @@ -1022,6 +1034,12 @@ # This is later checked when setting flags. fi + if test "x$TOOLCHAIN_TYPE" = xgcc || test "x$TOOLCHAIN_TYPE" = xclang; then + # Check if linker has -z noexecstack. + HAS_NOEXECSTACK=`$CC -Wl,--help 2>/dev/null | $GREP 'z noexecstack'` + # This is later checked when setting flags. + fi + # Setup hotspot lecagy names for toolchains HOTSPOT_TOOLCHAIN_TYPE=$TOOLCHAIN_TYPE if test "x$TOOLCHAIN_TYPE" = xclang; then @@ -1144,5 +1162,5 @@ fi fi - AC_SUBST(JIB_JAR) + AC_SUBST(JIB_HOME) ])
diff --git a/make/autoconf/toolchain_windows.m4 b/make/autoconf/toolchain_windows.m4 index 22a73c4..0fafb09 100644 --- a/make/autoconf/toolchain_windows.m4 +++ b/make/autoconf/toolchain_windows.m4
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -25,7 +25,7 @@ ################################################################################ # The order of these defines the priority by which we try to find them. -VALID_VS_VERSIONS="2017 2013 2015 2012 2010" +VALID_VS_VERSIONS="2017 2019 2013 2015 2012 2010" VS_DESCRIPTION_2010="Microsoft Visual Studio 2010" VS_VERSION_INTERNAL_2010=100 @@ -87,6 +87,21 @@ VS_VS_PLATFORM_NAME_2017="v141" VS_SDK_PLATFORM_NAME_2017= VS_SUPPORTED_2017=true +VS_TOOLSET_SUPPORTED_2017=true + +VS_DESCRIPTION_2019="Microsoft Visual Studio 2019" +VS_VERSION_INTERNAL_2019=141 +VS_MSVCR_2019=vcruntime140.dll +VS_MSVCP_2019=msvcp140.dll +VS_ENVVAR_2019="VS160COMNTOOLS" +VS_USE_UCRT_2019="true" +VS_VS_INSTALLDIR_2019="Microsoft Visual Studio/2019" +VS_EDITIONS_2019="BuildTools Community Professional Enterprise" +VS_SDK_INSTALLDIR_2019= +VS_VS_PLATFORM_NAME_2019="v142" +VS_SDK_PLATFORM_NAME_2019= +VS_SUPPORTED_2019=false +VS_TOOLSET_SUPPORTED_2019=false ################################################################################ @@ -98,7 +113,7 @@ METHOD="$3" BASIC_WINDOWS_REWRITE_AS_UNIX_PATH(VS_BASE) - # In VS 2017, the default installation is in a subdir named after the edition. + # In VS 2017 and VS 2019, the default installation is in a subdir named after the edition. # Find the first one present and use that. if test "x$VS_EDITIONS" != x; then for edition in $VS_EDITIONS; do @@ -177,6 +192,15 @@ # build environment and assigns it to VS_ENV_CMD AC_DEFUN([TOOLCHAIN_FIND_VISUAL_STUDIO_BAT_FILE], [ + # VS2017 provides the option to install previous minor versions of the MSVC + # toolsets. It is not possible to directly download earlier minor versions of + # VS2017 and in order to build with a previous minor compiler toolset version, + # it is now possible to compile with earlier minor versions by passing + # -vcvars_ver=<toolset_version> argument to vcvarsall.bat. + AC_ARG_WITH(msvc-toolset-version, [AS_HELP_STRING([--with-msvc-toolset-version], + [specific MSVC toolset version to use, passed as -vcvars_ver argument to + pass to vcvarsall.bat (Windows only)])]) + VS_VERSION="$1" eval VS_COMNTOOLS_VAR="\${VS_ENVVAR_${VS_VERSION}}" eval VS_COMNTOOLS="\$${VS_COMNTOOLS_VAR}" @@ -184,6 +208,9 @@ eval VS_EDITIONS="\${VS_EDITIONS_${VS_VERSION}}" eval SDK_INSTALL_DIR="\${VS_SDK_INSTALLDIR_${VS_VERSION}}" eval VS_ENV_ARGS="\${VS_ENV_ARGS_${VS_VERSION}}" + eval VS_TOOLSET_SUPPORTED="\${VS_TOOLSET_SUPPORTED_${VS_VERSION}}" + + VS_ENV_CMD="" # When using --with-tools-dir, assume it points to the correct and default # version of Visual Studio or that --with-toolchain-version was also set. @@ -202,8 +229,6 @@ fi fi - VS_ENV_CMD="" - if test "x$VS_COMNTOOLS" != x; then TOOLCHAIN_CHECK_POSSIBLE_VISUAL_STUDIO_ROOT([${VS_VERSION}], [$VS_COMNTOOLS/../..], [$VS_COMNTOOLS_VAR variable]) @@ -241,6 +266,12 @@ TOOLCHAIN_CHECK_POSSIBLE_WIN_SDK_ROOT([${VS_VERSION}], [C:/Program Files (x86)/$SDK_INSTALL_DIR], [well-known name]) fi + + if test "x$VS_TOOLSET_SUPPORTED" != x; then + if test "x$with_msvc_toolset_version" != x; then + VS_ENV_ARGS="$VS_ENV_ARGS -vcvars_ver=$with_msvc_toolset_version" + fi + fi ]) ################################################################################ @@ -397,6 +428,8 @@ >> $EXTRACT_VC_ENV_BAT_FILE $ECHO "$WINPATH_BASH -c 'echo VCINSTALLDIR="'\"$VCINSTALLDIR \" >> set-vs-env.sh' \ >> $EXTRACT_VC_ENV_BAT_FILE + $ECHO "$WINPATH_BASH -c 'echo VCToolsRedistDir="'\"$VCToolsRedistDir \" >> set-vs-env.sh' \ + >> $EXTRACT_VC_ENV_BAT_FILE $ECHO "$WINPATH_BASH -c 'echo WindowsSdkDir="'\"$WindowsSdkDir \" >> set-vs-env.sh' \ >> $EXTRACT_VC_ENV_BAT_FILE $ECHO "$WINPATH_BASH -c 'echo WINDOWSSDKDIR="'\"$WINDOWSSDKDIR \" >> set-vs-env.sh' \ @@ -442,6 +475,7 @@ VS_INCLUDE=`$ECHO "$VS_INCLUDE" | $SED -e 's/\\\\*;* *$//'` VS_LIB=`$ECHO "$VS_LIB" | $SED 's/\\\\*;* *$//'` VCINSTALLDIR=`$ECHO "$VCINSTALLDIR" | $SED 's/\\\\* *$//'` + VCToolsRedistDir=`$ECHO "$VCToolsRedistDir" | $SED 's/\\\\* *$//'` WindowsSdkDir=`$ECHO "$WindowsSdkDir" | $SED 's/\\\\* *$//'` WINDOWSSDKDIR=`$ECHO "$WINDOWSSDKDIR" | $SED 's/\\\\* *$//'` if test -z "$WINDOWSSDKDIR"; then @@ -561,11 +595,13 @@ POSSIBLE_MSVC_DLL="$CYGWIN_VC_INSTALL_DIR/redist/x86/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME" fi else - # Probe: Using well-known location from VS 2017 + CYGWIN_VC_TOOLS_REDIST_DIR="$VCToolsRedistDir" + BASIC_FIXUP_PATH(CYGWIN_VC_TOOLS_REDIST_DIR) + # Probe: Using well-known location from VS 2017 and VS 2019 if test "x$OPENJDK_TARGET_CPU_BITS" = x64; then - POSSIBLE_MSVC_DLL="`ls $CYGWIN_VC_INSTALL_DIR/Redist/MSVC/*/x64/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME`" + POSSIBLE_MSVC_DLL="`ls $CYGWIN_VC_TOOLS_REDIST_DIR/x64/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME`" else - POSSIBLE_MSVC_DLL="`ls $CYGWIN_VC_INSTALL_DIR/Redist/MSVC/*/x86/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME`" + POSSIBLE_MSVC_DLL="`ls $CYGWIN_VC_TOOLS_REDIST_DIR/x86/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME`" fi fi # In case any of the above finds more than one file, loop over them. @@ -693,7 +729,7 @@ if test "x$USE_UCRT" = "xtrue"; then AC_MSG_CHECKING([for UCRT DLL dir]) if test "x$with_ucrt_dll_dir" != x; then - if test -z "$(ls -d "$with_ucrt_dll_dir/*.dll" 2> /dev/null)"; then + if test -z "$(ls -d "$with_ucrt_dll_dir/"*.dll 2> /dev/null)"; then AC_MSG_RESULT([no]) AC_MSG_ERROR([Could not find any dlls in $with_ucrt_dll_dir]) else @@ -713,8 +749,16 @@ fi UCRT_DLL_DIR="$CYGWIN_WINDOWSSDKDIR/Redist/ucrt/DLLs/$dll_subdir" if test -z "$(ls -d "$UCRT_DLL_DIR/"*.dll 2> /dev/null)"; then - AC_MSG_RESULT([no]) - AC_MSG_ERROR([Could not find any dlls in $UCRT_DLL_DIR]) + # Try with version subdir + UCRT_DLL_DIR="`ls -d $CYGWIN_WINDOWSSDKDIR/Redist/*/ucrt/DLLs/$dll_subdir \ + 2> /dev/null | $SORT -d | $HEAD -n1`" + if test -z "$UCRT_DLL_DIR" \ + || test -z "$(ls -d "$UCRT_DLL_DIR/"*.dll 2> /dev/null)"; then + AC_MSG_RESULT([no]) + AC_MSG_ERROR([Could not find any dlls in $UCRT_DLL_DIR]) + else + AC_MSG_RESULT($UCRT_DLL_DIR) + fi else AC_MSG_RESULT($UCRT_DLL_DIR) fi
diff --git a/make/autoconf/version-numbers b/make/autoconf/version-numbers index 69e5e83..0b32476 100644 --- a/make/autoconf/version-numbers +++ b/make/autoconf/version-numbers
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -23,19 +23,21 @@ # questions. # -# Default version numbers to use unless overridden by configure +# Default version, product, and vendor information to use, +# unless overridden by configure DEFAULT_VERSION_FEATURE=11 DEFAULT_VERSION_INTERIM=0 -DEFAULT_VERSION_UPDATE=4 +DEFAULT_VERSION_UPDATE=13 DEFAULT_VERSION_PATCH=0 DEFAULT_VERSION_EXTRA1=0 DEFAULT_VERSION_EXTRA2=0 DEFAULT_VERSION_EXTRA3=0 -DEFAULT_VERSION_DATE=2019-07-16 +DEFAULT_VERSION_DATE=2021-10-19 DEFAULT_VERSION_CLASSFILE_MAJOR=55 # "`$EXPR $DEFAULT_VERSION_FEATURE + 44`" DEFAULT_VERSION_CLASSFILE_MINOR=0 DEFAULT_ACCEPTABLE_BOOT_VERSIONS="10 11" +DEFAULT_PROMOTED_VERSION_PRE= LAUNCHER_NAME=openjdk PRODUCT_NAME=OpenJDK @@ -43,6 +45,9 @@ JDK_RC_PLATFORM_NAME=Platform COMPANY_NAME=N/A HOTSPOT_VM_DISTRO="OpenJDK" +VENDOR_URL=https://openjdk.java.net/ +VENDOR_URL_BUG=https://bugreport.java.com/bugreport/ +VENDOR_URL_VM_BUG=https://bugreport.java.com/bugreport/crash.jsp # Might need better names for these MACOSX_BUNDLE_NAME_BASE="OpenJDK"
diff --git a/make/common/JarArchive.gmk b/make/common/JarArchive.gmk index b648791..e1ec142 100644 --- a/make/common/JarArchive.gmk +++ b/make/common/JarArchive.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2016, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -122,9 +122,9 @@ ifeq ($$($1_DEPENDENCIES), ) # Add all source roots to the find cache since we are likely going to run find # on these more than once. The cache will only be updated if necessary. - $$(eval $$(call FillCacheFind, $$($1_FIND_LIST))) + $$(call FillFindCache, $$($1_FIND_LIST)) $1_DEPENDENCIES:=$$(filter $$(addprefix %,$$($1_SUFFIXES)), \ - $$(call CacheFind,$$($1_SRCS))) + $$(call FindFiles,$$($1_SRCS))) ifneq (,$$($1_GREP_INCLUDE_PATTERNS)) $1_DEPENDENCIES:=$$(filter $$(addsuffix %,$$($1_GREP_INCLUDE_PATTERNS)),$$($1_DEPENDENCIES)) endif @@ -135,7 +135,7 @@ $1_DEPENDENCIES+=$$(wildcard $$(foreach src, $$($1_SRCS), \ $$(addprefix $$(src)/, $$($1_EXTRA_FILES))) $$($1_EXTRA_FILES)) ifeq (,$$($1_SKIP_METAINF)) - $1_DEPENDENCIES+=$$(call CacheFind,$$(wildcard $$(addsuffix /META-INF,$$($1_SRCS)))) + $1_DEPENDENCIES+=$$(call FindFiles,$$(wildcard $$(addsuffix /META-INF,$$($1_SRCS)))) endif endif # The dependency list should never be empty
diff --git a/make/common/JavaCompilation.gmk b/make/common/JavaCompilation.gmk index a1cdd92..aed23b1 100644 --- a/make/common/JavaCompilation.gmk +++ b/make/common/JavaCompilation.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -221,13 +221,12 @@ ) \ ) $$(call MakeDir,$$($1_BIN)) - # Add all source roots to the find cache since we are likely going to run find - # on these more than once. The cache will only be updated if necessary. - $$(eval $$(call FillCacheFind, $$($1_SRC))) - # Find all files in the source trees. Preserve order of source roots so that - # the first version in case of multiple instances of the same file is selected. - # CacheFind does not preserve order so need to call it for each root. - $1_ALL_SRCS += $$($1_EXTRA_FILES) $$(foreach s, $$($1_SRC), $$(call CacheFind, $$s)) + # Order src files according to the order of the src dirs. Correct ordering is + # needed for correct overriding between different source roots. + $1_ALL_SRC_RAW := $$(call FindFiles, $$($1_SRC)) + $1_ALL_SRCS := $$($1_EXTRA_FILES) \ + $$(foreach d, $$($1_SRC), $$(filter $$d%, $$($1_ALL_SRC_RAW))) + # Extract the java files. $1_SRCS := $$(filter %.java, $$($1_ALL_SRCS))
diff --git a/make/common/JdkNativeCompilation.gmk b/make/common/JdkNativeCompilation.gmk index bf09d48..b86df0f 100644 --- a/make/common/JdkNativeCompilation.gmk +++ b/make/common/JdkNativeCompilation.gmk
@@ -47,6 +47,36 @@ $(TOPDIR)/src/$(strip $1)/$(OPENJDK_TARGET_OS_TYPE)/native/$(strip $2) \ $(TOPDIR)/src/$(strip $1)/share/native/$(strip $2))) +# Find a library. Used for declaring dependencies on libraries in different +# modules. +# Param 1 - module name +# Param 2 - library name +# Param 3 - optional subdir for library +FindLib = \ + $(call FindLibDirForModule, \ + $(strip $1))$(strip $3)/$(LIBRARY_PREFIX)$(strip $2)$(SHARED_LIBRARY_SUFFIX) + +# Find a static library +# Param 1 - module name +# Param 2 - library name +# Param 3 - optional subdir for library +FindStaticLib = \ + $(addprefix $(SUPPORT_OUTPUTDIR)/native/, \ + $(strip $1)$(strip $3)/$(LIBRARY_PREFIX)$(strip $2)$(STATIC_LIBRARY_SUFFIX)) + +# If only generating compile_commands.json, make these return empty to avoid +# declaring dependencies. +ifeq ($(GENERATE_COMPILE_COMMANDS_ONLY), true) + FindLib = + FindStaticLib = +endif +# If building static versions of libraries, make these return empty to avoid +# declaring dependencies. +ifeq ($(STATIC_LIBS), true) + FindLib = + FindStaticLib = +endif + GetJavaHeaderDir = \ $(wildcard $(SUPPORT_OUTPUTDIR)/headers/$(strip $1))
diff --git a/make/common/MakeBase.gmk b/make/common/MakeBase.gmk index d511836..a040eff 100644 --- a/make/common/MakeBase.gmk +++ b/make/common/MakeBase.gmk
@@ -64,10 +64,12 @@ endef -# In GNU Make 4.0 and higher, there is a file function for writing to files. +# Certain features only work in newer version of GNU Make. The build will still +# function in 3.81, but will be less performant. ifeq (4.0, $(firstword $(sort 4.0 $(MAKE_VERSION)))) HAS_FILE_FUNCTION := true CORRECT_FUNCTION_IN_RECIPE_EVALUATION := true + RWILDCARD_WORKS := true endif ############################## @@ -466,8 +468,8 @@ ################################################################################ # Replace question marks with space in string. This macro needs to be called on -# files from CacheFind in case any of them contains space in their file name, -# since CacheFind replaces space with ?. +# files from FindFiles in case any of them contains space in their file name, +# since FindFiles replaces space with ?. # Param 1 - String to replace in DecodeSpace = \ $(subst ?,$(SPACE),$(strip $1)) @@ -611,7 +613,8 @@ # $2 - Directory to compute the relative path from RelativePath = \ $(eval $1_prefix := $(call FindCommonPathPrefix, $1, $2)) \ - $(eval $1_dotdots := $(call DirToDotDot, $(patsubst $($(strip $1)_prefix)/%, %, $2))) \ + $(eval $1_dotdots := $(call DirToDotDot, $(patsubst $($(strip $1)_prefix)%, %, $2))) \ + $(eval $1_dotdots := $(if $($(strip $1)_dotdots),$($(strip $1)_dotdots),.)) \ $(eval $1_suffix := $(patsubst $($(strip $1)_prefix)/%, %, $1)) \ $($(strip $1)_dotdots)/$($(strip $1)_suffix) @@ -685,73 +688,116 @@ ################################################################################ -ifneq ($(DISABLE_CACHE_FIND), true) - # In Cygwin, finds are very costly, both because of expensive forks and because - # of bad file system caching. Find is used extensively in $(shell) commands to - # find source files. This makes rerunning make with no or few changes rather - # expensive. To speed this up, these two macros are used to cache the results - # of simple find commands for reuse. - # - # Runs a find and stores both the directories where it was run and the results. - # This macro can be called multiple times to add to the cache. Only finds files - # with no filters. - # - # Files containing space will get spaces replaced with ? because GNU Make - # cannot handle lists of files with space in them. By using ?, make will match - # the wildcard to space in many situations so we don't need to replace back - # to space on every use. While not a complete solution it does allow some uses - # of CacheFind to function with spaces in file names, including for - # SetupCopyFiles. - # - # Needs to be called with $(eval ) - # - # Even if the performance benifit is negligible on other platforms, keep the - # functionality active unless explicitly disabled to exercise it more. - # - # Initialize FIND_CACHE_DIRS with := to make it a non recursively-expanded variable - FIND_CACHE_DIRS := - # Param 1 - Dirs to find in - # Param 2 - (optional) specialization. Normally "-a \( ... \)" expression. - define FillCacheFind - # Filter out already cached dirs. The - is needed when FIND_CACHE_DIRS is empty - # since filter out will then return empty. - FIND_CACHE_NEW_DIRS := $$(filter-out $$(addsuffix /%,\ - - $(FIND_CACHE_DIRS)) $(FIND_CACHE_DIRS), $1) - ifneq ($$(FIND_CACHE_NEW_DIRS), ) - # Remove any trailing slash from dirs in the cache dir list - FIND_CACHE_DIRS += $$(patsubst %/,%, $$(FIND_CACHE_NEW_DIRS)) - FIND_CACHE := $$(sort $$(FIND_CACHE) \ - $$(shell $(FIND) $$(wildcard $$(FIND_CACHE_NEW_DIRS)) \ - \( -type f -o -type l \) $2 | $(TR) ' ' '?')) - endif - endef - - # Mimics find by looking in the cache if all of the directories have been cached. - # Otherwise reverts to shell find. This is safe to call on all platforms, even if - # cache is deactivated. - # - # $1 can be either a directory or a file. If it's a directory, make - # sure we have exactly one trailing slash before the wildcard. - # The extra - is needed when FIND_CACHE_DIRS is empty but should be harmless. - # - # Param 1 - Dirs to find in - # Param 2 - (optional) specialization. Normally "-a \( ... \)" expression. - define CacheFind - $(if $(filter-out $(addsuffix /%,- $(FIND_CACHE_DIRS)) $(FIND_CACHE_DIRS),$1), \ - $(if $(wildcard $1), $(shell $(FIND) $(wildcard $1) \( -type f -o -type l \) $2 \ - | $(TR) ' ' '?')), \ - $(filter $(addsuffix /%,$(patsubst %/,%,$1)) $1,$(FIND_CACHE))) - endef - -else - # If CacheFind is disabled, just run the find command. - # Param 1 - Dirs to find in - # Param 2 - (optional) specialization. Normally "-a \( ... \)" expression. - define CacheFind - $(if $(wildcard $1, \ - $(shell $(FIND) $(wildcard $1) \( -type f -o -type l \) $2 | $(TR) ' ' '?') \ +# Recursive wildcard function. Walks down directories recursively and matches +# files with the search patterns. Patterns use standard file wildcards (* and +# ?). +# +# $1 - Directories to start search in +# $2 - Search patterns +rwildcard = \ + $(strip \ + $(foreach d, \ + $(patsubst %/,%,$(sort $(dir $(wildcard $(addsuffix /*/*, $(strip $1)))))), \ + $(call rwildcard,$d,$2) \ + ) \ + $(call DoubleDollar, $(wildcard $(foreach p, $2, $(addsuffix /$(strip $p), $(strip $1))))) \ ) - endef + +# Find non directories using recursive wildcard function. This function may +# be used directly when a small amount of directories is expected to be +# searched and caching is not expected to be of use. +# +# $1 - Directory to start search in +# $2 - Optional search patterns, defaults to '*'. +WildcardFindFiles = \ + $(sort $(strip \ + $(eval WildcardFindFiles_result := $(call rwildcard,$(patsubst %/,%,$1),$(if $(strip $2),$2,*))) \ + $(filter-out $(patsubst %/,%,$(sort $(dir $(WildcardFindFiles_result)))), \ + $(WildcardFindFiles_result) \ + ) \ + )) + +# Find non directories using the find utility in the shell. Safe to call for +# non existing directories, or directories containing wildcards. +# +# Files containing space will get spaces replaced with ? because GNU Make +# cannot handle lists of files with space in them. By using ?, make will match +# the wildcard to space in many situations so we don't need to replace back +# to space on every use. While not a complete solution it does allow some uses +# of FindFiles to function with spaces in file names, including for +# SetupCopyFiles. Unfortunately this does not work for WildcardFindFiles so +# if files with spaces are anticipated, use ShellFindFiles directly. +# +# $1 - Directories to start search in. +# $2 - Optional search patterns, empty means find everything. Patterns use +# standard file wildcards (* and ?) and should not be quoted. +# $3 - Optional options to find. +ShellFindFiles = \ + $(if $(wildcard $1), \ + $(sort \ + $(shell $(FIND) $3 $(patsubst %/,%,$(wildcard $1)) \( -type f -o -type l \) \ + $(if $(strip $2), -a \( -name "$(firstword $2)" \ + $(foreach p, $(filter-out $(firstword $2), $2), -o -name "$(p)") \)) \ + | $(TR) ' ' '?' \ + ) \ + ) \ + ) + +# Find non directories using the method most likely to work best for the +# current build host +# +# $1 - Directory to start search in +# $2 - Optional search patterns, defaults to '*'. +ifeq ($(OPENJDK_BUILD_OS)-$(RWILDCARD_WORKS), windows-true) + DirectFindFiles = $(WildcardFindFiles) +else + DirectFindFiles = $(ShellFindFiles) +endif + +# Finds files using a cache that is populated by FillFindCache below. If any of +# the directories given have not been cached, DirectFindFiles is used for +# everything. Caching is especially useful in Cygwin, where file finds are very +# costly. +# +# $1 - Directories to start search in. +# $2 - Optional search patterns. If used, no caching is done. +CacheFindFiles_CACHED_DIRS := +CacheFindFiles_CACHED_FILES := +CacheFindFiles = \ + $(if $2, \ + $(call DirectFindFiles, $1, $2) \ + , \ + $(if $(filter-out $(addsuffix /%, $(CacheFindFiles_CACHED_DIRS)) \ + $(CacheFindFiles_CACHED_DIRS), $1), \ + $(call DirectFindFiles, $1) \ + , \ + $(filter $(addsuffix /%,$(patsubst %/,%,$1)) $1,$(CacheFindFiles_CACHED_FILES)) \ + ) \ + ) + +# Explicitly adds files to the find cache used by CacheFindFiles. +# +# $1 - Directories to start search in +FillFindCache = \ + $(eval CacheFindFiles_NEW_DIRS := $$(filter-out $$(addsuffix /%,\ + $$(CacheFindFiles_CACHED_DIRS)) $$(CacheFindFiles_CACHED_DIRS), $1)) \ + $(if $(CacheFindFiles_NEW_DIRS), \ + $(eval CacheFindFiles_CACHED_DIRS += $$(patsubst %/,%,$$(CacheFindFiles_NEW_DIRS))) \ + $(eval CacheFindFiles_CACHED_FILES := $$(sort $$(CacheFindFiles_CACHED_FILES) \ + $$(call DirectFindFiles, $$(CacheFindFiles_NEW_DIRS)))) \ + ) + +# Findfiles is the default macro that should be used to find files in the file +# system. This function does not always support files with spaces in the names. +# If files with spaces are anticipated, use ShellFindFiles directly. +# +# $1 - Directories to start search in. +# $2 - Optional search patterns, empty means find everything. Patterns use +# standard file wildcards (* and ?) and should not be quoted. +ifeq ($(DISABLE_CACHE_FIND), true) + FindFiles = $(DirectFindFiles) +else + FindFiles = $(CacheFindFiles) endif ################################################################################ @@ -842,7 +888,7 @@ # Parameter 1 is the name of the rule, and is also the name of the variable. # # Remaining parameters are named arguments. These include: -# KEYWORDS A list of valid keywords +# SINGLE_KEYWORDS A list of valid keywords with single string values # STRING_KEYWORDS A list of valid keywords, processed as string. This means # that '%20' will be replaced by ' ' to allow for multi-word strings. # @@ -856,7 +902,7 @@ $$(eval mangled_part_eval := $$(call DoubleDollar, $$(mangled_part))) \ $$(eval part := $$$$(subst ||||,$$$$(SPACE),$$$$(mangled_part_eval))) \ $$(eval $1_NO_MATCH := true) \ - $$(foreach keyword, $$($1_KEYWORDS), \ + $$(foreach keyword, $$($1_SINGLE_KEYWORDS), \ $$(eval keyword_eval := $$(call DoubleDollar, $$(keyword))) \ $$(if $$(filter $$(keyword)=%, $$(part)), \ $$(eval $(strip $1)_$$$$(keyword_eval) := $$$$(strip $$$$(patsubst $$$$(keyword_eval)=%, %, $$$$(part)))) \ @@ -871,11 +917,11 @@ ) \ ) \ $$(if $$($1_NO_MATCH), \ - $$(if $$(filter $$(part), $$($1_KEYWORDS) $$($1_STRING_KEYWORDS)), \ + $$(if $$(filter $$(part), $$($1_SINGLE_KEYWORDS) $$($1_STRING_KEYWORDS)), \ $$(info Keyword $$(part) for $1 needs to be assigned a value.) \ , \ $$(info $$(part) is not a valid keyword for $1.) \ - $$(info Valid keywords: $$($1_KEYWORDS) $$($1_STRING_KEYWORDS).) \ + $$(info Valid keywords: $$($1_SINGLE_KEYWORDS) $$($1_STRING_KEYWORDS).) \ ) \ $$(error Cannot continue) \ ) \ @@ -938,6 +984,22 @@ endif ################################################################################ +# FixPathList +# +# On Windows, converts a cygwin/unix style path list (colon-separated) into +# the native format (mixed mode, semicolon-separated). On other platforms, +# return the path list unchanged. +################################################################################ +ifeq ($(OPENJDK_TARGET_OS), windows) + FixPathList = \ + $(subst @,$(SPACE),$(subst $(SPACE),;,$(foreach entry,$(subst :,$(SPACE),\ + $(subst $(SPACE),@,$(strip $1))),$(call FixPath, $(entry))))) +else + FixPathList = \ + $1 +endif + +################################################################################ # DependOnVariable # # This macro takes a variable name and puts the value in a file only if the @@ -974,15 +1036,16 @@ # Param 2 - (optional) name of file to store value in DependOnVariableHelper = \ $(strip \ - $(eval -include $(call DependOnVariableFileName, $1, $2)) \ + $(eval $1_filename := $(call DependOnVariableFileName, $1, $2)) \ + $(if $(wildcard $($1_filename)), $(eval include $($1_filename))) \ $(if $(call equals, $(strip $($1)), $(strip $($1_old))),,\ - $(call MakeDir, $(dir $(call DependOnVariableFileName, $1, $2))) \ + $(call MakeDir, $(dir $($1_filename))) \ $(if $(findstring $(LOG_LEVEL), trace), \ $(info NewVariable $1: >$(strip $($1))<) \ $(info OldVariable $1: >$(strip $($1_old))<)) \ $(call WriteFile, $1_old:=$(call DoubleDollar,$(call EscapeHash,$($1))), \ - $(call DependOnVariableFileName, $1, $2))) \ - $(call DependOnVariableFileName, $1, $2) \ + $($1_filename))) \ + $($1_filename) \ ) # Main macro
diff --git a/make/common/Modules.gmk b/make/common/Modules.gmk index a69a6de..41533e5 100644 --- a/make/common/Modules.gmk +++ b/make/common/Modules.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2014, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2014, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -63,6 +63,7 @@ jdk.management \ jdk.management.jfr \ jdk.management.agent \ + jdk.naming.ldap \ jdk.net \ jdk.sctp \ jdk.unsupported \ @@ -165,6 +166,7 @@ jdk.management.agent \ jdk.management.jfr \ jdk.naming.dns \ + jdk.naming.ldap \ jdk.naming.rmi \ jdk.net \ jdk.pack \
diff --git a/make/common/NativeCompilation.gmk b/make/common/NativeCompilation.gmk index 467c26b..490a7f4 100644 --- a/make/common/NativeCompilation.gmk +++ b/make/common/NativeCompilation.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -60,6 +60,29 @@ endef ################################################################################ +# Creates a recipe that creates a compile_commands.json fragment. Remove any +# occurences of FIXPATH programs from the command to show the actual invocation. +# +# Param 1: Name of file to create +# Param 2: Working directory +# Param 3: Source file +# Param 4: Compile command +# Param 5: Object name +################################################################################ +define WriteCompileCommandsFragment + $(call LogInfo, Creating compile commands fragment for $(notdir $3)) + $(call MakeDir, $(dir $1)) + $(call WriteFile,{ \ + "directory": "$(strip $2)"$(COMMA) \ + "file": "$(strip $3)"$(COMMA) \ + "command": "$(strip $(subst $(DQUOTE),\$(DQUOTE),$(subst \,\\,\ + $(subst $(FIXPATH),,$4))))"$(COMMA) \ + "output": "$(strip $5)" \ + }$(COMMA), \ + $1) +endef + +################################################################################ # Define a native toolchain configuration that can be used by # SetupNativeCompilation calls # @@ -184,6 +207,96 @@ # ################################################################################ +# When absolute paths are not allowed in the output, and the compiler does not +# support any options to avoid it, we need to rewrite compile commands to use +# relative paths. By doing this, the __FILE__ macro will resolve to relative +# paths. The relevant input paths on the command line are the -I flags and the +# path to the source file itself. +# +# The macro MakeCommandRelative is used to rewrite the command line like this: +# 'CD $(WORKSPACE_ROOT) && <cmd>' +# and changes all paths in cmd to be relative to the workspace root. This only +# works properly if the build dir is inside the workspace root. If it's not, +# relative paths are still calculated, but depending on the distance between the +# dirs, paths in the build dir may end up as essentially absolute anyway. +# +# The fix-deps-file macro is used to adjust the contents of the generated make +# dependency files to contain paths compatible with make. +# +ifeq ($(ALLOW_ABSOLUTE_PATHS_IN_OUTPUT)-$(FILE_MACRO_CFLAGS), false-) + # Need to handle -I flags as both '-Ifoo' and '-I foo'. + MakeCommandRelative = \ + $(CD) $(WORKSPACE_ROOT) && \ + $(foreach o, $1, \ + $(if $(filter $(WORKSPACE_ROOT)/% $(OUTPUTDIR)/%, $o), \ + $(call RelativePath, $o, $(WORKSPACE_ROOT)) \ + , \ + $(if $(filter -I$(WORKSPACE_ROOT)/%, $o), \ + -I$(call RelativePath, $(patsubst -I%, %, $o), $(WORKSPACE_ROOT)) \ + , \ + $o \ + ) \ + ) \ + ) + + # When compiling with relative paths, the deps file may come out with relative + # paths, and that path may start with './'. First remove any leading ./, then + # add WORKSPACE_ROOT to any line not starting with /, while allowing for + # leading spaces. There may also be multiple entries on the same line, so start + # with splitting such lines. + # Non GNU sed (BSD on macosx) cannot substitue in literal \n using regex. + # Instead use a bash escaped literal newline. To avoid having unmatched quotes + # ruin the ability for an editor to properly syntax highlight this file, define + # that newline sequence as a separate variable and add the closing quote behind + # a comment. + sed_newline := \'$$'\n''#' + ifeq ($(TOOLCHAIN_TYPE), solstudio) + define fix-deps-file + $(SED) -e 's|\./|$(WORKSPACE_ROOT)/|g' $1.tmp > $1 + endef + else + define fix-deps-file + $(SED) \ + -e 's|\([^ ]\) \{1,\}\([^\\:]\)|\1 \\$(sed_newline) \2|g' \ + $1.tmp \ + | $(SED) \ + -e 's|^\([ ]*\)\./|\1|' \ + -e '/^[ ]*[^/ ]/s|^\([ ]*\)|\1$(WORKSPACE_ROOT)/|' \ + > $1 + endef + endif +else + # By default the MakeCommandRelative macro does nothing. + MakeCommandRelative = $1 + + # Even with absolute paths on the command line, the Solaris studio compiler + # doesn't output the full path to the object file in the generated deps files. + # For other toolchains, no adjustment is needed. + ifeq ($(TOOLCHAIN_TYPE), solstudio) + define fix-deps-file + $(SED) 's|^$$(@F):|$$@:|' $1.tmp > $1 + endef + else + define fix-deps-file + $(MV) $1.tmp $1 + endef + endif +endif + +################################################################################ +# GetEntitlementsFile +# Find entitlements file for executable when signing on macosx. If no +# specialized file is found, returns the default file. +# $1 Executable to find entitlements file for. +ENTITLEMENTS_DIR := $(TOPDIR)/make/data/macosxsigning +DEFAULT_ENTITLEMENTS_FILE := $(ENTITLEMENTS_DIR)/default.plist + +GetEntitlementsFile = \ + $(foreach f, $(ENTITLEMENTS_DIR)/$(strip $(notdir $1)).plist, \ + $(if $(wildcard $f), $f, $(DEFAULT_ENTITLEMENTS_FILE)) \ + ) + +################################################################################ # Create the recipe needed to compile a single native source file. # # Parameter 1 is the name of the rule, based on the name of the library/ @@ -193,7 +306,6 @@ # Remaining parameters are named arguments: # FILE - The full path of the source file to compiler # BASE - The name of the rule for the entire binary to build ($1) -# DISABLE_THIS_FILE_DEFINE - Set to true to disable the THIS_FILE define. # SetupCompileNativeFile = $(NamedParamsMacroTemplate) define SetupCompileNativeFileBody @@ -203,17 +315,18 @@ $1_OBJ := $$($$($1_BASE)_OBJECT_DIR)/$$(call replace_with_obj_extension, \ $$($1_FILENAME)) + # Generate the corresponding compile_commands.json fragment. + $1_OBJ_JSON = $$(MAKESUPPORT_OUTPUTDIR)/compile-commands/$$(subst /,_,$$(subst \ + $$(OUTPUTDIR)/,,$$($1_OBJ))).json + $$($1_BASE)_ALL_OBJS_JSON += $$($1_OBJ_JSON) + # Only continue if this object file hasn't been processed already. This lets # the first found source file override any other with the same name. - ifeq ($$(findstring $$($1_OBJ), $$($$($1_BASE)_OBJS_SO_FAR)), ) - $$($1_BASE)_OBJS_SO_FAR += $$($1_OBJ) + ifeq ($$($1_OBJ_PROCESSED), ) + $1_OBJ_PROCESSED := true # This is the definite source file to use for $1_FILENAME. $1_SRC_FILE := $$($1_FILE) - ifneq ($$($1_DISABLE_THIS_FILE_DEFINE), true) - $1_THIS_FILE = -DTHIS_FILE='"$$(<F)"' - endif - ifeq ($$($1_OPTIMIZATION), ) $1_OPT_CFLAGS := $$($$($1_BASE)_OPT_CFLAGS) $1_OPT_CXXFLAGS := $$($$($1_BASE)_OPT_CXXFLAGS) @@ -256,13 +369,13 @@ ifneq ($$(filter %.c, $$($1_FILENAME)), ) # Compile as a C file $1_FLAGS := $(CFLAGS_CCACHE) $$($1_USE_PCH_FLAGS) $$($1_BASE_CFLAGS) \ - $$($1_OPT_CFLAGS) $$($1_CFLAGS) $$($1_THIS_FILE) -c + $$($1_OPT_CFLAGS) $$($1_CFLAGS) -c $1_COMPILER := $$($$($1_BASE)_CC) $1_DEP_FLAG := $(C_FLAG_DEPS) else ifneq ($$(filter %.m, $$($1_FILENAME)), ) # Compile as an Objective-C file $1_FLAGS := -x objective-c $(CFLAGS_CCACHE) $$($1_USE_PCH_FLAGS) \ - $$($1_BASE_CFLAGS) $$($1_OPT_CFLAGS) $$($1_CFLAGS) $$($1_THIS_FILE) -c + $$($1_BASE_CFLAGS) $$($1_OPT_CFLAGS) $$($1_CFLAGS) -c $1_COMPILER := $$($$($1_BASE)_CC) $1_DEP_FLAG := $(C_FLAG_DEPS) else ifneq ($$(filter %.s %.S, $$($1_FILENAME)), ) @@ -273,7 +386,7 @@ else ifneq ($$(filter %.cpp %.cc %.mm, $$($1_FILENAME)), ) # Compile as a C++ or Objective-C++ file $1_FLAGS := $(CFLAGS_CCACHE) $$($1_USE_PCH_FLAGS) $$($1_BASE_CXXFLAGS) \ - $$($1_OPT_CXXFLAGS) $$($1_CXXFLAGS) $$($1_THIS_FILE) -c + $$($1_OPT_CXXFLAGS) $$($1_CXXFLAGS) -c $1_COMPILER := $$($$($1_BASE)_CXX) $1_DEP_FLAG := $(CXX_FLAG_DEPS) else @@ -282,14 +395,18 @@ ifeq ($$(filter %.s %.S, $$($1_FILENAME)), ) # And this is the dependency file for this obj file. - $1_DEP := $$(patsubst %$(OBJ_SUFFIX),%.d,$$($1_OBJ)) + $1_DEPS_FILE := $$(patsubst %$(OBJ_SUFFIX),%.d,$$($1_OBJ)) # The dependency target file lists all dependencies as empty targets to # avoid make error "No rule to make target" for removed files - $1_DEP_TARGETS := $$(patsubst %$(OBJ_SUFFIX),%.d.targets,$$($1_OBJ)) + $1_DEPS_TARGETS_FILE := $$(patsubst %$(OBJ_SUFFIX),%.d.targets,$$($1_OBJ)) - # Include previously generated dependency information. (if it exists) - -include $$($1_DEP) - -include $$($1_DEP_TARGETS) + # Only try to load individual dependency information files if the global + # file hasn't been loaded (could happen if make was interrupted). + ifneq ($$($$($1_BASE)_DEPS_FILE_LOADED), true) + # Include previously generated dependency information. (if it exists) + -include $$($1_DEPS_FILE) + -include $$($1_DEPS_TARGETS_FILE) + endif endif ifneq ($$(strip $$($1_CFLAGS) $$($1_CXXFLAGS) $$($1_OPTIMIZATION)), ) @@ -297,28 +414,29 @@ $1_VARDEPS_FILE := $$(call DependOnVariable, $1_VARDEPS, $$($1_OBJ).vardeps) endif - $$($1_OBJ): $$($1_SRC_FILE) $$($$($1_BASE)_COMPILE_VARDEPS_FILE) \ - $$($$($1_BASE)_EXTRA_DEPS) $$($1_VARDEPS_FILE) | $$($$($1_BASE)_BUILD_INFO) + $1_OBJ_DEPS := $$($1_SRC_FILE) $$($$($1_BASE)_COMPILE_VARDEPS_FILE) \ + $$($$($1_BASE)_EXTRA_DEPS) $$($1_VARDEPS_FILE) + $1_COMPILE_OPTIONS := $$($1_FLAGS) $(CC_OUT_OPTION)$$($1_OBJ) $$($1_SRC_FILE) + + $$($1_OBJ_JSON): $$($1_OBJ_DEPS) + $$(call WriteCompileCommandsFragment, $$@, $$(PWD), $$($1_SRC_FILE), \ + $$($1_COMPILER) $$($1_COMPILE_OPTIONS), $$($1_OBJ)) + + $$($1_OBJ): $$($1_OBJ_DEPS) | $$($$($1_BASE)_BUILD_INFO) $$(call LogInfo, Compiling $$($1_FILENAME) (for $$($$($1_BASE)_BASENAME))) $$(call MakeDir, $$(@D)) ifneq ($(TOOLCHAIN_TYPE), microsoft) - ifeq ($(TOOLCHAIN_TYPE)$$(filter %.s, $$($1_FILENAME)), solstudio) - # The Solaris studio compiler doesn't output the full path to the - # object file in the generated deps files. Fixing it with sed. If - # compiling assembly, don't try this. - $$(call ExecuteWithLog, $$@, \ - $$($1_COMPILER) $$($1_FLAGS) $$($1_DEP_FLAG) $$($1_DEP).tmp \ - $(CC_OUT_OPTION)$$($1_OBJ) $$($1_SRC_FILE)) - $(SED) 's|^$$(@F):|$$@:|' $$($1_DEP).tmp > $$($1_DEP) - else - $$(call ExecuteWithLog, $$@, \ - $$($1_COMPILER) $$($1_FLAGS) $$($1_DEP_FLAG) $$($1_DEP) \ - $(CC_OUT_OPTION)$$($1_OBJ) $$($1_SRC_FILE)) - endif - # Create a dependency target file from the dependency file. - # Solution suggested by http://make.mad-scientist.net/papers/advanced-auto-dependency-generation/ - ifneq ($$($1_DEP), ) - $(SED) $(DEPENDENCY_TARGET_SED_PATTERN) $$($1_DEP) > $$($1_DEP_TARGETS) + $$(call ExecuteWithLog, $$@, $$(call MakeCommandRelative, \ + $$($1_COMPILER) $$($1_DEP_FLAG) \ + $$(addsuffix .tmp, $$($1_DEPS_FILE)) \ + $$($1_COMPILE_OPTIONS))) + ifneq ($$($1_DEPS_FILE), ) + $$(call fix-deps-file, $$($1_DEPS_FILE)) + # Create a dependency target file from the dependency file. + # Solution suggested by: + # http://make.mad-scientist.net/papers/advanced-auto-dependency-generation/ + $(SED) $(DEPENDENCY_TARGET_SED_PATTERN) $$($1_DEPS_FILE) \ + > $$($1_DEPS_TARGETS_FILE) endif else # The Visual Studio compiler lacks a feature for generating make @@ -328,15 +446,15 @@ # Keep as much as possible on one execution line for best performance # on Windows. No need to save exit code from compilation since # pipefail is always active on Windows. - $$(call ExecuteWithLog, $$@, \ - $$($1_COMPILER) $$($1_FLAGS) -showIncludes \ - $(CC_OUT_OPTION)$$($1_OBJ) $$($1_SRC_FILE)) \ + $$(call ExecuteWithLog, $$@, $$(call MakeCommandRelative, \ + $$($1_COMPILER) -showIncludes $$($1_COMPILE_OPTIONS))) \ | $(TR) -d '\r' | $(GREP) -v -e "^Note: including file:" \ -e "^$$($1_FILENAME)$$$$" || test "$$$$?" = "1" ; \ - $(ECHO) $$@: \\ > $$($1_DEP) ; \ + $(ECHO) $$@: \\ > $$($1_DEPS_FILE) ; \ $(SED) $(WINDOWS_SHOWINCLUDE_SED_PATTERN) $$($1_OBJ).log \ - | $(SORT) -u >> $$($1_DEP) ; \ - $(SED) $(DEPENDENCY_TARGET_SED_PATTERN) $$($1_DEP) > $$($1_DEP_TARGETS) + | $(SORT) -u >> $$($1_DEPS_FILE) ; \ + $(ECHO) >> $$($1_DEPS_FILE) ; \ + $(SED) $(DEPENDENCY_TARGET_SED_PATTERN) $$($1_DEPS_FILE) > $$($1_DEPS_TARGETS_FILE) endif endif endef @@ -415,6 +533,28 @@ endif endif + $$(call SetIfEmpty, $1_COMPILE_WITH_DEBUG_SYMBOLS, $$(COMPILE_WITH_DEBUG_SYMBOLS)) + + # STATIC_LIBS is set from Main.gmk when building static versions of certain + # native libraries. + ifeq ($(STATIC_LIBS), true) + $1_TYPE := STATIC_LIBRARY + # The static versions need to be redirected to different output dirs, both + # to not interfere with the main build as well as to not end up inside the + # jmods. + $1_OBJECT_DIR := $$($1_OBJECT_DIR)/static + $1_OUTPUT_DIR := $$($1_OBJECT_DIR) + # For release builds where debug symbols are configured to be moved to + # separate debuginfo files, disable debug symbols for static libs instead. + # We don't currently support this configuration and we don't want symbol + # information in release builds unless explicitly asked to provide it. + ifeq ($(DEBUG_LEVEL), release) + ifeq ($(COPY_DEBUG_SYMBOLS), true) + $1_COMPILE_WITH_DEBUG_SYMBOLS := false + endif + endif + endif + ifeq ($$($1_TYPE), EXECUTABLE) $1_PREFIX := ifeq ($$($1_SUFFIX), ) @@ -456,6 +596,9 @@ $1_NOSUFFIX := $$($1_PREFIX)$$($1_NAME) $1_SAFE_NAME := $$(strip $$(subst /,_, $1)) +# Need to make sure TARGET is first on list + $1 := $$($1_TARGET) + # Setup the toolchain to be used $$(call SetIfEmpty, $1_TOOLCHAIN, TOOLCHAIN_DEFAULT) $$(call SetIfEmpty, $1_CC, $$($$($1_TOOLCHAIN)_CC)) @@ -476,7 +619,7 @@ $$(error SRC specified to SetupNativeCompilation $1 contains missing directory $$d))) # Find all files in the source trees. Preserve order. - $1_SRCS := $$(foreach s, $$($1_SRC), $$(call CacheFind, $$(s))) + $1_SRCS := $$(foreach s, $$($1_SRC), $$(call FindFiles, $$(s))) $1_SRCS := $$(filter $$(NATIVE_SOURCE_EXTENSIONS), $$($1_SRCS)) # Extract the C/C++ files. ifneq ($$($1_EXCLUDE_PATTERNS), ) @@ -550,6 +693,9 @@ $1_EXTRA_CFLAGS += $$($1_CFLAGS_$(OPENJDK_TARGET_OS)_release) $1_EXTRA_CFLAGS += $$($1_CFLAGS_$(OPENJDK_TARGET_OS)_$(OPENJDK_TARGET_CPU)_release) endif + ifeq ($(STATIC_LIBS), true) + $1_EXTRA_CFLAGS += $$(STATIC_LIBS_CFLAGS) + endif # Pickup extra OPENJDK_TARGET_OS_TYPE and/or OPENJDK_TARGET_OS dependent variables for CXXFLAGS. $1_EXTRA_CXXFLAGS := $$($1_CXXFLAGS_$(OPENJDK_TARGET_OS_TYPE)) $$($1_CXXFLAGS_$(OPENJDK_TARGET_OS)) @@ -563,6 +709,9 @@ $1_EXTRA_CXXFLAGS += $$($1_CXXFLAGS_$(OPENJDK_TARGET_OS_TYPE)_release) $1_EXTRA_CXXFLAGS += $$($1_CXXFLAGS_$(OPENJDK_TARGET_OS)_release) endif + ifeq ($(STATIC_LIBS), true) + $1_EXTRA_CXXFLAGS += $$(STATIC_LIB_CFLAGS) + endif # If no C++ flags are explicitly set, default to using the C flags. # After that, we can set additional C++ flags that should not interfere @@ -574,7 +723,7 @@ $1_EXTRA_CXXFLAGS := $$($1_EXTRA_CFLAGS) endif - ifeq ($(COMPILE_WITH_DEBUG_SYMBOLS), true) + ifeq ($$($1_COMPILE_WITH_DEBUG_SYMBOLS), true) $1_EXTRA_CFLAGS += $$(CFLAGS_DEBUG_SYMBOLS) $1_EXTRA_CXXFLAGS += $$(CFLAGS_DEBUG_SYMBOLS) $1_EXTRA_ASFLAGS += $$(ASFLAGS_DEBUG_SYMBOLS) @@ -660,7 +809,6 @@ FILE := $$($1_GENERATED_PCH_SRC), \ BASE := $1, \ EXTRA_CXXFLAGS := -Fp$$($1_PCH_FILE) -Yc$$(notdir $$($1_PRECOMPILED_HEADER)), \ - DISABLE_THIS_FILE_DEFINE := true, \ )) $1_USE_PCH_FLAGS := \ @@ -683,27 +831,67 @@ $1_PCH_FILE := $$($1_OBJECT_DIR)/precompiled/$$(notdir $$($1_PRECOMPILED_HEADER)).pch $1_USE_PCH_FLAGS := -include-pch $$($1_PCH_FILE) endif - $1_PCH_DEP := $$($1_PCH_FILE).d - $1_PCH_DEP_TARGETS := $$($1_PCH_FILE).d.targets + $1_PCH_DEPS_FILE := $$($1_PCH_FILE).d + $1_PCH_DEPS_TARGETS_FILE := $$($1_PCH_FILE).d.targets - -include $$($1_PCH_DEP) - -include $$($1_PCH_DEP_TARGETS) + -include $$($1_PCH_DEPS_FILE) + -include $$($1_PCH_DEPS_TARGETS_FILE) + + $1_PCH_COMMAND := $$($1_CC) $$($1_CFLAGS) $$($1_EXTRA_CFLAGS) $$($1_SYSROOT_CFLAGS) \ + $$($1_OPT_CFLAGS) -x c++-header -c $(C_FLAG_DEPS) \ + $$(addsuffix .tmp, $$($1_PCH_DEPS_FILE)) $$($1_PCH_FILE): $$($1_PRECOMPILED_HEADER) $$($1_COMPILE_VARDEPS_FILE) $$(call LogInfo, Generating precompiled header) $$(call MakeDir, $$(@D)) - $$(call ExecuteWithLog, $$@, \ - $$($1_CC) $$($1_CFLAGS) $$($1_EXTRA_CFLAGS) $$($1_SYSROOT_CFLAGS) \ - $$($1_OPT_CFLAGS) \ - -x c++-header -c $(C_FLAG_DEPS) $$($1_PCH_DEP) $$< -o $$@) - $(SED) $(DEPENDENCY_TARGET_SED_PATTERN) $$($1_PCH_DEP) > $$($1_PCH_DEP_TARGETS) + $$(call ExecuteWithLog, $$@, $$(call MakeCommandRelative, \ + $$($1_PCH_COMMAND) $$< -o $$@)) + $$(call fix-deps-file, $$($1_PCH_DEPS_FILE)) + $(SED) $(DEPENDENCY_TARGET_SED_PATTERN) $$($1_PCH_DEPS_FILE) \ + > $$($1_PCH_DEPS_TARGETS_FILE) $$($1_ALL_OBJS): $$($1_PCH_FILE) + # Generate the corresponding compile_commands.json fragment. + $1_PCH_FILE_JSON := $$(MAKESUPPORT_OUTPUTDIR)/compile-commands/$$(subst /,_,$$(subst \ + $$(OUTPUTDIR)/,,$$($1_PCH_FILE))).json + $1_ALL_OBJS_JSON += $$($1_PCH_FILE_JSON) + + $$($1_PCH_FILE_JSON): $$($1_PRECOMPILED_HEADER) $$($1_COMPILE_VARDEPS_FILE) + $$(call WriteCompileCommandsFragment, $$@, $$(PWD), $$<, \ + $$($1_PCH_COMMAND) $$< -o $$($1_PCH_FILE), $$($1_PCH_FILE)) endif endif endif + # Create a rule to collect all the individual make dependency files into a + # single makefile. + $1_DEPS_FILE := $$($1_OBJECT_DIR)/$1.d + + $$($1_DEPS_FILE): $$($1_ALL_OBJS) + $(RM) $$@ + # CD into dir to reduce risk of hitting command length limits, which + # could otherwise happen if TOPDIR is a very long path. + $(CD) $$($1_OBJECT_DIR) && $(CAT) *.d > $$@.tmp + $(CD) $$($1_OBJECT_DIR) && $(CAT) *.d.targets | $(SORT) -u >> $$@.tmp + # After generating the file, which happens after all objects have been + # compiled, copy it to .old extension. On the next make invocation, this + # .old file will be included by make. + $(CP) $$@.tmp $$@.old + $(MV) $$@.tmp $$@ + + $1 += $$($1_DEPS_FILE) + + # The include must be on the .old file, which represents the state from the + # previous invocation of make. The file being included must not have a rule + # defined for it as otherwise make will think it has to run the rule before + # being able to include the file, which would be wrong since we specifically + # need the file as it was generated by a previous make invocation. + ifneq ($$(wildcard $$($1_DEPS_FILE).old), ) + $1_DEPS_FILE_LOADED := true + -include $$($1_DEPS_FILE).old + endif + # Now call SetupCompileNativeFile for each source file we are going to compile. $$(foreach file, $$($1_SRCS), \ $$(eval $$(call SetupCompileNativeFile, $1_$$(notdir $$(file)),\ @@ -730,10 +918,10 @@ ifeq ($(OPENJDK_TARGET_OS), windows) ifneq ($$($1_VERSIONINFO_RESOURCE), ) $1_RES := $$($1_OBJECT_DIR)/$$($1_BASENAME).res - $1_RES_DEP := $$($1_RES).d - $1_RES_DEP_TARGETS := $$($1_RES).d.targets - -include $$($1_RES_DEP) - -include $$($1_RES_DEP_TARGETS) + $1_RES_DEPS_FILE := $$($1_RES).d + $1_RES_DEPS_TARGETS_FILE := $$($1_RES).d.targets + -include $$($1_RES_DEPS_FILE) + -include $$($1_RES_DEPS_TARGETS_FILE) $1_RES_VARDEPS := $$($1_RC) $$($1_RC_FLAGS) $1_RES_VARDEPS_FILE := $$(call DependOnVariable, $1_RES_VARDEPS, \ @@ -742,24 +930,27 @@ $$($1_RES): $$($1_VERSIONINFO_RESOURCE) $$($1_RES_VARDEPS_FILE) $$(call LogInfo, Compiling resource $$(notdir $$($1_VERSIONINFO_RESOURCE)) (for $$($1_BASENAME))) $$(call MakeDir, $$(@D) $$($1_OBJECT_DIR)) - $$(call ExecuteWithLog, $$@, \ + $$(call ExecuteWithLog, $$@, $$(call MakeCommandRelative, \ $$($1_RC) $$($1_RC_FLAGS) $$($1_SYSROOT_CFLAGS) $(CC_OUT_OPTION)$$@ \ - $$($1_VERSIONINFO_RESOURCE) 2>&1 ) + $$($1_VERSIONINFO_RESOURCE) 2>&1 )) # Windows RC compiler does not support -showIncludes, so we mis-use CL # for this. Filter out RC specific arguments that are unknown to CL. # For some unknown reason, in this case CL actually outputs the show # includes to stderr so need to redirect it to hide the output from the # main log. - $$(call ExecuteWithLog, $$($1_RES_DEP).obj, \ + $$(call ExecuteWithLog, $$($1_RES_DEPS_FILE).obj, \ $$($1_CC) $$(filter-out -l%, $$($1_RC_FLAGS)) \ $$($1_SYSROOT_CFLAGS) -showIncludes -nologo -TC \ - $(CC_OUT_OPTION)$$($1_RES_DEP).obj -P -Fi$$($1_RES_DEP).pp \ + $(CC_OUT_OPTION)$$($1_RES_DEPS_FILE).obj -P -Fi$$($1_RES_DEPS_FILE).pp \ $$($1_VERSIONINFO_RESOURCE)) 2>&1 \ | $(TR) -d '\r' | $(GREP) -v -e "^Note: including file:" \ -e "^$$(notdir $$($1_VERSIONINFO_RESOURCE))$$$$" || test "$$$$?" = "1" ; \ - $(ECHO) $$($1_RES): \\ > $$($1_RES_DEP) ; \ - $(SED) $(WINDOWS_SHOWINCLUDE_SED_PATTERN) $$($1_RES_DEP).obj.log >> $$($1_RES_DEP) ; \ - $(SED) $(DEPENDENCY_TARGET_SED_PATTERN) $$($1_RES_DEP) > $$($1_RES_DEP_TARGETS) + $(ECHO) $$($1_RES): \\ > $$($1_RES_DEPS_FILE) ; \ + $(SED) $(WINDOWS_SHOWINCLUDE_SED_PATTERN) $$($1_RES_DEPS_FILE).obj.log \ + >> $$($1_RES_DEPS_FILE) ; \ + $(ECHO) >> $$($1_RES_DEPS_FILE) ;\ + $(SED) $(DEPENDENCY_TARGET_SED_PATTERN) $$($1_RES_DEPS_FILE) \ + > $$($1_RES_DEPS_TARGETS_FILE) endif endif @@ -786,9 +977,6 @@ $1_EXTRA_LDFLAGS += $(call SET_SHARED_LIBRARY_MAPFILE,$$($1_REAL_MAPFILE)) endif - # Need to make sure TARGET is first on list - $1 := $$($1_TARGET) - ifneq ($$($1_COPY_DEBUG_SYMBOLS), false) $1_COPY_DEBUG_SYMBOLS := $(COPY_DEBUG_SYMBOLS) endif @@ -805,6 +993,9 @@ ifeq ($(OPENJDK_TARGET_OS), windows) $1_EXTRA_LDFLAGS += -debug "-pdb:$$($1_OUTPUT_DIR)/$$($1_NOSUFFIX).pdb" \ "-map:$$($1_OUTPUT_DIR)/$$($1_NOSUFFIX).map" + ifeq ($(SHIP_DEBUG_SYMBOLS), public) + $1_EXTRA_LDFLAGS += "-pdbstripped:$$($1_OUTPUT_DIR)/$$($1_NOSUFFIX).stripped.pdb" + endif $1_DEBUGINFO_FILES := $$($1_OUTPUT_DIR)/$$($1_NOSUFFIX).pdb \ $$($1_OUTPUT_DIR)/$$($1_NOSUFFIX).map @@ -817,6 +1008,13 @@ $(CD) $$($1_OUTPUT_DIR) && \ $$($1_OBJCOPY) --add-gnu-debuglink=$$($1_DEBUGINFO_FILES) $$($1_TARGET) + else ifeq ($(OPENJDK_TARGET_OS), aix) + # AIX does not provide the equivalent of OBJCOPY to extract debug symbols, + # so we copy the compiled object with symbols to the .debuginfo file, which + # happens prior to the STRIP_CMD on the original target object file. + $1_DEBUGINFO_FILES := $$($1_OUTPUT_DIR)/$$($1_NOSUFFIX).debuginfo + $1_CREATE_DEBUGINFO_CMDS := $(CP) $$($1_TARGET) $$($1_DEBUGINFO_FILES) + else ifeq ($(OPENJDK_TARGET_OS), macosx) $1_DEBUGINFO_FILES := \ $$($1_OUTPUT_DIR)/$$($1_BASENAME).dSYM/Contents/Info.plist \ @@ -936,7 +1134,7 @@ $1_VARDEPS := $$($1_LD) $$($1_SYSROOT_LDFLAGS) $$($1_LDFLAGS) $$($1_EXTRA_LDFLAGS) \ $$(GLOBAL_LIBS) $$($1_LIBS) $$($1_EXTRA_LIBS) $$($1_MT) \ - $$($1_CODESIGN) $$($1_CREATE_DEBUGINFO_CMDS) $$($1_MANIFEST_VERSION) \ + $$($1_CREATE_DEBUGINFO_CMDS) $$($1_MANIFEST_VERSION) \ $$($1_STRIP_CMD) $1_VARDEPS_FILE := $$(call DependOnVariable, $1_VARDEPS, \ $$($1_OBJECT_DIR)/$$($1_NOSUFFIX).vardeps) @@ -1015,11 +1213,14 @@ # This only works if the openjdk_codesign identity is present on the system. Let # silently fail otherwise. ifneq ($(CODESIGN), ) - ifneq ($$($1_CODESIGN), ) - $(CODESIGN) -s openjdk_codesign $$@ - endif + $(CODESIGN) -s "$(MACOSX_CODESIGN_IDENTITY)" --timestamp --options runtime \ + --entitlements $$(call GetEntitlementsFile, $$@) $$@ endif endif + + ifeq ($(GENERATE_COMPILE_COMMANDS_ONLY), true) + $1 := $$($1_ALL_OBJS_JSON) + endif endef endif # _NATIVE_COMPILATION_GMK
diff --git a/make/common/TestFilesCompilation.gmk b/make/common/TestFilesCompilation.gmk index e90921e..d4d9c6f 100644 --- a/make/common/TestFilesCompilation.gmk +++ b/make/common/TestFilesCompilation.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2015, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2015, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -75,7 +75,7 @@ # Locate all files with the matching prefix $1_FILE_LIST := \ - $$(shell $$(FIND) $$($1_SOURCE_DIRS) -type f -name "$$($1_PREFIX)*.c") + $$(call FindFiles, $$($1_SOURCE_DIRS), $$($1_PREFIX)*.c $$($1_PREFIX)*.m) $1_EXCLUDE_PATTERN := $$(addprefix %/, $$($1_EXCLUDE)) $1_FILTERED_FILE_LIST := $$(filter-out $$($1_EXCLUDE_PATTERN), $$($1_FILE_LIST))
diff --git a/make/common/TextFileProcessing.gmk b/make/common/TextFileProcessing.gmk index 3fad067..04bd9e5 100644 --- a/make/common/TextFileProcessing.gmk +++ b/make/common/TextFileProcessing.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2013, 2014, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2013, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -103,7 +103,7 @@ $$(error SOURCE_DIRS contains directory $$(src) outside \ SOURCE_BASE_DIR $$($1_SOURCE_BASE_DIR) (in $1)))) endif - $1_SOURCE_FILES := $$(sort $$(call CacheFind,$$($1_SOURCE_DIRS))) + $1_SOURCE_FILES := $$(sort $$(call FindFiles,$$($1_SOURCE_DIRS))) $1_EXCLUDE_FILES:=$$(foreach i,$$($1_SOURCE_DIRS),$$(addprefix $$i/,$$($1_EXCLUDE_FILES))) $1_INCLUDE_FILES:=$$(foreach i,$$($1_SOURCE_DIRS),$$(addprefix $$i/,$$($1_INCLUDE_FILES))) $1_SOURCE_FILES := $$(filter-out $$($1_EXCLUDE_FILES),$$($1_SOURCE_FILES)) @@ -155,9 +155,10 @@ # Convert the REPLACEMENTS syntax ( A => B ; C => D ; ...) to a sed command # line (-e "s/A/B/g" -e "s/C/D/g" ...), basically by replacing '=>' with '/' # and ';' with '/g" -e "s/', and adjusting for edge cases. + # '&' has special meaning in sed so needs to be escaped. $1_REPLACEMENTS_COMMAND_LINE := $(SED) -e 's$$($1_SEP)$$(subst $$(SPACE);$$(SPACE),$$($1_SEP)g' \ -e 's$$($1_SEP),$$(subst $$(SPACE)=>$$(SPACE),$$($1_SEP),$$(subst $$(SPACE)=>$$(SPACE);$$(SPACE),$$($1_SEP)$$($1_SEP)g' \ - -e 's$$($1_SEP),$$(strip $$($1_REPLACEMENTS)))))$$($1_SEP)g' + -e 's$$($1_SEP),$$(subst &,\&,$$(strip $$($1_REPLACEMENTS))))))$$($1_SEP)g' else # We don't have any replacements, just pipe the file through cat. $1_REPLACEMENTS_COMMAND_LINE := $(CAT)
diff --git a/make/common/ZipArchive.gmk b/make/common/ZipArchive.gmk index 4ced471..de0b3e0 100644 --- a/make/common/ZipArchive.gmk +++ b/make/common/ZipArchive.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2014, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -48,6 +48,8 @@ # src dir # SUFFIXES # EXTRA_DEPS +# FOLLOW_SYMLINKS - Set to explicitly follow symlinks. Affects performance of +# finding files. # ZIP_OPTIONS extra options to pass to zip SetupZipArchive = $(NamedParamsMacroTemplate) define SetupZipArchiveBody @@ -63,7 +65,13 @@ endif # Find all files in the source tree. - $1_ALL_SRCS := $$(call not-containing,_the.,$$(call CacheFind,$$($1_FIND_LIST))) + # If asked to, follow symlinks in this find since that is what zip does. To do + # this, we need to call ShellFindFiles directly. + ifeq ($$($1_FOLLOW_SYMLINKS), true) + $1_ALL_SRCS := $$(call not-containing,_the.,$$(call ShellFindFiles,$$($1_FIND_LIST), , -L)) + else + $1_ALL_SRCS := $$(call not-containing,_the.,$$(call FindFiles,$$($1_FIND_LIST))) + endif # Filter on suffixes if set ifneq ($$($1_SUFFIXES),)
diff --git a/make/conf/jib-profiles.js b/make/conf/jib-profiles.js index 20a92a1..f5a77ab 100644 --- a/make/conf/jib-profiles.js +++ b/make/conf/jib-profiles.js
@@ -240,7 +240,7 @@ // These are the base setttings for all the main build profiles. common.main_profile_base = { dependencies: ["boot_jdk", "gnumake", "jtreg", "jib", "autoconf"], - default_make_targets: ["product-bundles", "test-bundles"], + default_make_targets: ["product-bundles", "test-bundles", "static-libs-bundles"], configure_args: concat(["--enable-jtreg-failure-handler"], "--with-exclude-translations=de,es,fr,it,ko,pt_BR,sv,ca,tr,cs,sk,ja_JP_A,ja_JP_HA,ja_JP_HI,ja_JP_I,zh_TW,zh_HK", "--disable-manpages", @@ -312,6 +312,14 @@ subdir: jdk_subdir, exploded: "images/jdk" }, + static_libs: { + local: "bundles/\\(jdk.*bin-static-libs.tar.gz\\)", + remote: [ + "bundles/" + pf + "/jdk-" + data.version + "_" + pf + "_bin-static-libs.tar.gz", + "bundles/" + pf + "/\\1" + ], + subdir: jdk_subdir, + }, } }; }; @@ -353,6 +361,14 @@ subdir: jdk_subdir, exploded: "images/jdk" }, + static_libs: { + local: "bundles/\\(jdk.*bin-static-libs-debug.tar.gz\\)", + remote: [ + "bundles/" + pf + "/jdk-" + data.version + "_" + pf + "_bin-static-libs-debug.tar.gz", + "bundles/" + pf + "/\\1" + ], + subdir: jdk_subdir, + }, } }; }; @@ -522,7 +538,7 @@ .forEach(function (name) { var maketestName = name + "-testmake"; profiles[maketestName] = concatObjects(profiles[name], testmakeBase); - profiles[maketestName].default_make_targets = [ "test-make" ]; + profiles[maketestName].default_make_targets = [ "test-make", "test-compile-commands" ]; }); // Profiles for building the zero jvm variant. These are used for verification. @@ -747,16 +763,16 @@ "run-test-prebuilt": { target_os: input.build_os, target_cpu: input.build_cpu, - src: "src.conf", - dependencies: [ "jtreg", "gnumake", "boot_jdk", "jib", testedProfile + ".jdk", - testedProfile + ".test", "src.full" + dependencies: [ + "jtreg", "gnumake", "boot_jdk", "devkit", "jib", testedProfile + ".jdk", + testedProfile + ".test" ], - work_dir: input.get("src.full", "install_path") + "/test", + src: "src.conf", + make_args: [ "run-test-prebuilt", "LOG_CMDLINES=true" ], environment: { - "JT_JAVA": common.boot_jdk_home, - "PRODUCT_HOME": input.get(testedProfile + ".jdk", "home_path"), - "TEST_IMAGE_DIR": input.get(testedProfile + ".test", "home_path"), - "TEST_OUTPUT_DIR": input.src_top_dir + "BOOT_JDK": common.boot_jdk_home, + "JDK_IMAGE_DIR": input.get(testedProfile + ".jdk", "home_path"), + "TEST_IMAGE_DIR": input.get(testedProfile + ".test", "home_path") }, labels: "test" } @@ -782,7 +798,6 @@ // This gives us a guaranteed working version of lldb for the jtreg failure handler. if (input.build_os == "macosx") { macosxRunTestExtra = { - dependencies: [ "devkit" ], environment_path: input.get("devkit", "install_path") + "/Xcode.app/Contents/Developer/usr/bin" }; @@ -794,13 +809,34 @@ windowsRunTestPrebuiltExtra = { dependencies: [ testedProfile + ".jdk_symbols" ], environment: { - "PRODUCT_SYMBOLS_HOME": input.get(testedProfile + ".jdk_symbols", "home_path"), + "SYMBOLS_IMAGE_DIR": input.get(testedProfile + ".jdk_symbols", "home_path"), } }; profiles["run-test-prebuilt"] = concatObjects(profiles["run-test-prebuilt"], windowsRunTestPrebuiltExtra); } + // The profile run-test-prebuilt defines src.conf as the src bundle. When + // running in Mach 5, this reduces the time it takes to populate the + // considerably. But with just src.conf, we cannot actually run any tests, + // so if running from a workspace with just src.conf in it, we need to also + // get src.full as a dependency, and define the work_dir (where make gets + // run) to be in the src.full install path. By running in the install path, + // the same cached installation of the full src can be reused for multiple + // test tasks. Care must however be taken not to polute that work dir by + // setting the appropriate make variables to control output directories. + // + // Use the existance of the top level README as indication of if this is + // the full source or just src.conf. + if (!new java.io.File(__DIR__, "../../README").exists()) { + var runTestPrebuiltSrcFullExtra = { + dependencies: "src.full", + work_dir: input.get("src.full", "install_path"), + } + profiles["run-test-prebuilt"] = concatObjects(profiles["run-test-prebuilt"], + runTestPrebuiltSrcFullExtra); + } + // Generate the missing platform attributes profiles = generatePlatformAttributes(profiles); profiles = generateDefaultMakeTargetsConfigureArg(common, profiles); @@ -821,14 +857,14 @@ macosx_x64: "Xcode9.4-MacOSX10.13+1.0", solaris_x64: "SS12u4-Solaris11u1+1.0", solaris_sparcv9: "SS12u4-Solaris11u1+1.1", - windows_x64: "VS2017-15.5.5+1.0", + windows_x64: "VS2017-15.9.16+1.0", linux_aarch64: (input.profile != null && input.profile.indexOf("arm64") >= 0 ? "gcc-linaro-aarch64-linux-gnu-4.8-2013.11_linux+1.0" - : "gcc7.3.0-Fedora27+1.0"), + : "gcc7.3.0-Fedora27+1.1"), linux_arm: (input.profile != null && input.profile.indexOf("hflt") >= 0 ? "gcc-linaro-arm-linux-gnueabihf-raspbian-2012.09-20120921_linux+1.0" - : (input.profile.indexOf("arm32") >= 0 - ? "gcc7.3.0-Fedora27+1.0" + : (input.profile != null && input.profile.indexOf("arm32") >= 0 + ? "gcc7.3.0-Fedora27+1.1" : "arm-linaro-4.7+1.0" ) ) @@ -862,7 +898,10 @@ organization: common.organization, ext: "tar.gz", module: "devkit-" + devkit_platform, - revision: devkit_platform_revisions[devkit_platform] + revision: devkit_platform_revisions[devkit_platform], + environment: { + "DEVKIT_HOME": input.get("devkit", "home_path"), + } }, build_devkit: { @@ -879,11 +918,12 @@ }, jtreg: { - server: "javare", - revision: "4.2", - build_number: "b13", + server: "jpg", + product: "jtreg", + version: "5.1", + build_number: "b01", checksum_file: "MD5_VALUES", - file: "jtreg_bin-4.2.zip", + file: "bundles/jtreg_bin-5.1.zip", environment_name: "JT_HOME", environment_path: input.get("jtreg", "install_path") + "/jtreg/bin" }, @@ -941,9 +981,9 @@ ext: "zip", classifier: "distribution", revision: "3.0-SNAPSHOT", - environment_name: "JIB_JAR", + environment_name: "JIB_HOME", environment_value: input.get("jib", "install_path") - + "/jib-3.0-SNAPSHOT-distribution/lib/jib-3.0-SNAPSHOT.jar" + + "/jib-3.0-SNAPSHOT-distribution" }, ant: { @@ -963,14 +1003,6 @@ }, }; - // Need to add a value for the Visual Studio tools variable to make - // jaot be able to pick up the Visual Studio linker in testing. - if (input.target_os == "windows") { - dependencies.devkit.environment = { - VS120COMNTOOLS: input.get("devkit", "install_path") + "/Common7/Tools" - }; - } - return dependencies; }; @@ -1129,15 +1161,15 @@ * @param patch Override patch version * @returns {String} The numeric version string */ -var getVersion = function (feature, interim, update, patch) { +var getVersion = function (feature, interim, update, patch, extra1, extra2, extra3) { var version_numbers = getVersionNumbers(); var version = (feature != null ? feature : version_numbers.get("DEFAULT_VERSION_FEATURE")) + "." + (interim != null ? interim : version_numbers.get("DEFAULT_VERSION_INTERIM")) + "." + (update != null ? update : version_numbers.get("DEFAULT_VERSION_UPDATE")) + "." + (patch != null ? patch : version_numbers.get("DEFAULT_VERSION_PATCH")) - + "." + version_numbers.get("DEFAULT_VERSION_EXTRA1") - + "." + version_numbers.get("DEFAULT_VERSION_EXTRA2") - + "." + version_numbers.get("DEFAULT_VERSION_EXTRA3"); + + "." + (extra1 != null ? extra1 : version_numbers.get("DEFAULT_VERSION_EXTRA1")) + + "." + (extra2 != null ? extra2 : version_numbers.get("DEFAULT_VERSION_EXTRA2")) + + "." + (extra3 != null ? extra3 : version_numbers.get("DEFAULT_VERSION_EXTRA3")); while (version.match(".*\\.0$")) { version = version.substring(0, version.length - 2); } @@ -1152,10 +1184,16 @@ var args = ["--with-version-build=" + common.build_number]; if (input.build_type == "promoted") { args = concat(args, - // This needs to be changed when we start building release candidates - // with-version-pre must be set to ea for 'ea' and empty for fcs build - "--with-version-pre=", + "--with-version-pre=" + version_numbers.get("DEFAULT_PROMOTED_VERSION_PRE"), "--without-version-opt"); + } else if (input.build_type == "ci") { + var optString = input.build_id_data.ciBuildNumber; + var preString = input.build_id_data.projectName; + if (preString == "jdk") { + preString = version_numbers.get("DEFAULT_PROMOTED_VERSION_PRE"); + } + args = concat(args, "--with-version-pre=" + preString, + "--with-version-opt=" + optString); } else { args = concat(args, "--with-version-opt=" + common.build_id); }
diff --git a/make/conf/test-dependencies b/make/conf/test-dependencies new file mode 100644 index 0000000..aad8327 --- /dev/null +++ b/make/conf/test-dependencies
@@ -0,0 +1,43 @@ +# +# Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved. +# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. +# +# This code is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 only, as +# published by the Free Software Foundation. Oracle designates this +# particular file as subject to the "Classpath" exception as provided +# by Oracle in the LICENSE file that accompanied this code. +# +# This code is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# version 2 for more details (a copy is included in the LICENSE file that +# accompanied this code). +# +# You should have received a copy of the GNU General Public License version +# 2 along with this work; if not, write to the Free Software Foundation, +# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +# +# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +# or visit www.oracle.com if you need additional information or have any +# questions. +# + +# Versions and download locations for dependencies used by pre-submit testing. + +BOOT_JDK_VERSION=11 +JTREG_VERSION=5.1 +JTREG_BUILD=b01 +GTEST_VERSION=1.8.1 + +LINUX_X64_BOOT_JDK_FILENAME=openjdk-11_linux-x64_bin.tar.gz +LINUX_X64_BOOT_JDK_URL=https://github.com/adoptium/temurin11-binaries/releases/download/jdk-11.0.12%2B7/OpenJDK11U-jdk_x64_linux_hotspot_11.0.12_7.tar.gz +LINUX_X64_BOOT_JDK_SHA256=8770f600fc3b89bf331213c7aa21f8eedd9ca5d96036d1cd48cb2748a3dbefd2 + +WINDOWS_X64_BOOT_JDK_FILENAME=openjdk-11_windows-x64_bin.zip +WINDOWS_X64_BOOT_JDK_URL=https://github.com/adoptium/temurin11-binaries/releases/download/jdk-11.0.12%2B7/OpenJDK11U-jdk_x64_windows_hotspot_11.0.12_7.zip +WINDOWS_X64_BOOT_JDK_SHA256=c54123dd4b0d6473221539e7003b8ca1c1757c5588c46465565b03bf8781f807 + +MACOS_X64_BOOT_JDK_FILENAME=openjdk-11_osx-x64_bin.tar.gz +MACOS_X64_BOOT_JDK_URL=https://github.com/adoptium/temurin11-binaries/releases/download/jdk-11.0.12%2B7/OpenJDK11U-jdk_x64_mac_hotspot_11.0.12_7.tar.gz +MACOS_X64_BOOT_JDK_SHA256=13d056ee9a57bf2d5b3af4504c8f8cf7a246c4dff78f96b70dd05dad98075855
diff --git a/make/copy/Copy-java.base.gmk b/make/copy/Copy-java.base.gmk index 11b3510..1964932 100644 --- a/make/copy/Copy-java.base.gmk +++ b/make/copy/Copy-java.base.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2014, 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2014, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -162,17 +162,17 @@ ################################################################################ -ifeq ($(CACERTS_FILE), ) - CACERTS_FILE := $(TOPDIR)/src/java.base/share/lib/security/cacerts -endif - +# CACERTS_FILE is optionally set in configure to override the default cacerts +# which is otherwise generated in Gendata-java.base.gmk CACERTS_DST := $(LIB_DST_DIR)/security/cacerts $(CACERTS_DST): $(CACERTS_FILE) $(call LogInfo, Copying $(patsubst $(OUTPUTDIR)/%, %, $@)) $(call install-file) -TARGETS += $(CACERTS_DST) +ifneq ($(CACERTS_FILE), ) + TARGETS += $(CACERTS_DST) +endif ################################################################################
diff --git a/make/copy/Copy-java.desktop.gmk b/make/copy/Copy-java.desktop.gmk index a5e1f98..a6ca1e7 100644 --- a/make/copy/Copy-java.desktop.gmk +++ b/make/copy/Copy-java.desktop.gmk
@@ -73,6 +73,10 @@ LEGAL_EXCLUDES += freetype.md endif +ifeq ($(USE_EXTERNAL_HARFBUZZ), true) + LEGAL_EXCLUDES += harfbuzz.md +endif + $(eval $(call SetupCopyLegalFiles, COPY_LEGAL, \ EXCLUDES := $(LEGAL_EXCLUDES), \ ))
diff --git a/make/copy/CopyCommon.gmk b/make/copy/CopyCommon.gmk index 6450cb1..ce28156 100644 --- a/make/copy/CopyCommon.gmk +++ b/make/copy/CopyCommon.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -40,7 +40,7 @@ $(eval $(call SetupCopyFiles, COPY_EXPORTED_INCLUDE, \ SRC := $(INCLUDE_SOURCE_DIR), \ DEST := $(INCLUDE_TARGET_DIR), \ - FILES := $(filter %.h, $(call CacheFind, $(INCLUDE_SOURCE_DIR))), \ + FILES := $(filter %.h, $(call FindFiles, $(INCLUDE_SOURCE_DIR))), \ )) TARGETS += $(COPY_EXPORTED_INCLUDE) @@ -56,7 +56,7 @@ $(eval $(call SetupCopyFiles, COPY_EXPORTED_INCLUDE_OS, \ SRC := $(INCLUDE_SOURCE_OS_DIR), \ DEST := $(INCLUDE_TARGET_DIR)/$(OPENJDK_TARGET_OS_INCLUDE_SUBDIR), \ - FILES := $(filter %.h, $(call CacheFind, $(INCLUDE_SOURCE_OS_DIR))), \ + FILES := $(filter %.h, $(call FindFiles, $(INCLUDE_SOURCE_OS_DIR))), \ )) TARGETS += $(COPY_EXPORTED_INCLUDE_OS)
diff --git a/make/data/blacklistedcertsconverter/blacklisted.certs.pem b/make/data/blacklistedcertsconverter/blacklisted.certs.pem index 191e94e..688becb 100644 --- a/make/data/blacklistedcertsconverter/blacklisted.certs.pem +++ b/make/data/blacklistedcertsconverter/blacklisted.certs.pem
@@ -1,8 +1,7 @@ #! java BlacklistedCertsConverter SHA-256 -# The line above must be the first line of the blacklisted.certs.pem -# file inside src/share/lib/security/. It will be ignored if added in -# src/closed/share/lib/security/blacklisted.certs.pem. +# The line above must be the first line of this file. Do not +# remove it. // Subject: CN=Digisign Server ID (Enrich), // OU=457608-K,
diff --git a/make/data/bundle/JDK-Info.plist b/make/data/bundle/JDK-Info.plist index d057e83..e37b492 100644 --- a/make/data/bundle/JDK-Info.plist +++ b/make/data/bundle/JDK-Info.plist
@@ -22,6 +22,8 @@ <string>????</string> <key>CFBundleVersion</key> <string>@@VERSION@@</string> + <key>NSMicrophoneUsageDescription</key> + <string>The application is requesting access to the microphone.</string> <key>JavaVM</key> <dict> <key>JVMCapabilities</key>
diff --git a/make/data/bundle/JRE-Info.plist b/make/data/bundle/JRE-Info.plist index b9d045e..0081b24 100644 --- a/make/data/bundle/JRE-Info.plist +++ b/make/data/bundle/JRE-Info.plist
@@ -22,6 +22,8 @@ <string>????</string> <key>CFBundleVersion</key> <string>@@VERSION@@</string> + <key>NSMicrophoneUsageDescription</key> + <string>The application is requesting access to the microphone.</string> <key>JavaVM</key> <dict> <key>JVMMinimumFrameworkVersion</key>
diff --git a/make/data/cacerts/README b/make/data/cacerts/README new file mode 100644 index 0000000..25d2d77 --- /dev/null +++ b/make/data/cacerts/README
@@ -0,0 +1,10 @@ +Each file in this directory (except for this README) contains a CA certificate in PEM format. It can be generated with + +keytool -J-Duser.timezone=GMT -printcert -file ca.cert | sed -n '1,4p;8,10p' +keytool -printcert -file ca.cert -rfc + +Please note the textual part before the "-----BEGIN CERTIFICATE-----" line is just a suggestion and not arbitrary. + +After any change in this directory, please remember to update the content of `test/jdk/sun/security/lib/cacerts/VerifyCACerts.java` as well. + +All changes to this directory need to be approved by the Security group.
diff --git a/make/data/cacerts/actalisauthenticationrootca b/make/data/cacerts/actalisauthenticationrootca new file mode 100644 index 0000000..9c1d9a9 --- /dev/null +++ b/make/data/cacerts/actalisauthenticationrootca
@@ -0,0 +1,40 @@ +Owner: CN=Actalis Authentication Root CA, O=Actalis S.p.A./03358520967, L=Milan, C=IT +Issuer: CN=Actalis Authentication Root CA, O=Actalis S.p.A./03358520967, L=Milan, C=IT +Serial number: 570a119742c4e3cc +Valid from: Thu Sep 22 11:22:02 GMT 2011 until: Sun Sep 22 11:22:02 GMT 2030 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFuzCCA6OgAwIBAgIIVwoRl0LE48wwDQYJKoZIhvcNAQELBQAwazELMAkGA1UE +BhMCSVQxDjAMBgNVBAcMBU1pbGFuMSMwIQYDVQQKDBpBY3RhbGlzIFMucC5BLi8w +MzM1ODUyMDk2NzEnMCUGA1UEAwweQWN0YWxpcyBBdXRoZW50aWNhdGlvbiBSb290 +IENBMB4XDTExMDkyMjExMjIwMloXDTMwMDkyMjExMjIwMlowazELMAkGA1UEBhMC +SVQxDjAMBgNVBAcMBU1pbGFuMSMwIQYDVQQKDBpBY3RhbGlzIFMucC5BLi8wMzM1 +ODUyMDk2NzEnMCUGA1UEAwweQWN0YWxpcyBBdXRoZW50aWNhdGlvbiBSb290IENB +MIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEAp8bEpSmkLO/lGMWwUKNv +UTufClrJwkg4CsIcoBh/kbWHuUA/3R1oHwiD1S0eiKD4j1aPbZkCkpAW1V8IbInX +4ay8IMKx4INRimlNAJZaby/ARH6jDuSRzVju3PvHHkVH3Se5CAGfpiEd9UEtL0z9 +KK3giq0itFZljoZUj5NDKd45RnijMCO6zfB9E1fAXdKDa0hMxKufgFpbOr3JpyI/ +gCczWw63igxdBzcIy2zSekciRDXFzMwujt0q7bd9Zg1fYVEiVRvjRuPjPdA1Yprb +rxTIW6HMiRvhMCb8oJsfgadHHwTrozmSBp+Z07/T6k9QnBn+locePGX2oxgkg4YQ +51Q+qDp2JE+BIcXjDwL4k5RHILv+1A7TaLndxHqEguNTVHnd25zS8gebLra8Pu2F +be8lEfKXGkJh90qX6IuxEAf6ZYGyojnP9zz/GPvG8VqLWeICrHuS0E4UT1lF9gxe +KF+w6D9Fz8+vm2/7hNN3WpVvrJSEnu68wEqPSpP4RCHiMUVhUE4Q2OM1fEwZtN4F +v6MGn8i1zeQf1xcGDXqVdFUNaBr8EBtiZJ1t4JWgw5QHVw0U5r0F+7if5t+L4sbn +fpb2U8WANFAoWPASUHEXMLrmeGO89LKtmyuy/uE5jF66CyCU3nuDuP/jVo23Eek7 +jPKxwV2dpAtMK9myGPW1n0sCAwEAAaNjMGEwHQYDVR0OBBYEFFLYiDrIn3hm7Ynz +ezhwlMkCAjbQMA8GA1UdEwEB/wQFMAMBAf8wHwYDVR0jBBgwFoAUUtiIOsifeGbt +ifN7OHCUyQICNtAwDgYDVR0PAQH/BAQDAgEGMA0GCSqGSIb3DQEBCwUAA4ICAQAL +e3KHwGCmSUyIWOYdiPcUZEim2FgKDk8TNd81HdTtBjHIgT5q1d07GjLukD0R0i70 +jsNjLiNmsGe+b7bAEzlgqqI0JZN1Ut6nna0Oh4lScWoWPBkdg/iaKWW+9D+a2fDz +WochcYBNy+A4mz+7+uAwTc+G02UQGRjRlwKxK3JCaKygvU5a2hi/a5iB0P2avl4V +SM0RFbnAKVy06Ij3Pjaut2L9HmLecHgQHEhb2rykOLpn7VU+Xlff1ANATIGk0k9j +pwlCCRT8AKnCgHNPLsBA2RF7SOp6AsDT6ygBJlh0wcBzIm2Tlf05fbsq4/aC4yyX +X04fkZT6/iyj2HYauE2yOE+b+h1IYHkm4vP9qdCa6HCPSXrW5b0KDtst842/6+Ok +fcvHlXHo2qN8xcL4dJIEG4aspCJTQLas/kx2z/uUMsA1n3Y/buWQbqCmJqK4LL7R +K4X9p2jIugErsWx0Hbhzlefut8cl8ABMALJ+tguLHPPAUJ4lueAI3jZm/zel0btU +ZCzJJ7VLkn5l/9Mt4blOvH+kQSGQQXemOR/qnuOf0GZvBeyqdn6/axag67XH/JJU +LysRJyU3eExRarDzzFhdFPFqSBX/wge2sY0PjlxQRrM9vwGYT7JZVEc+NHt4bVaT +LnPqZih4zR0Uv6CPLy64Lo7yFIrM6bV8+2ydDKXhlg== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/addtrustexternalca b/make/data/cacerts/addtrustexternalca new file mode 100644 index 0000000..ad84cad --- /dev/null +++ b/make/data/cacerts/addtrustexternalca
@@ -0,0 +1,32 @@ +Owner: CN=AddTrust External CA Root, OU=AddTrust External TTP Network, O=AddTrust AB, C=SE +Issuer: CN=AddTrust External CA Root, OU=AddTrust External TTP Network, O=AddTrust AB, C=SE +Serial number: 1 +Valid from: Tue May 30 10:48:38 GMT 2000 until: Sat May 30 10:48:38 GMT 2020 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIENjCCAx6gAwIBAgIBATANBgkqhkiG9w0BAQUFADBvMQswCQYDVQQGEwJTRTEU +MBIGA1UEChMLQWRkVHJ1c3QgQUIxJjAkBgNVBAsTHUFkZFRydXN0IEV4dGVybmFs +IFRUUCBOZXR3b3JrMSIwIAYDVQQDExlBZGRUcnVzdCBFeHRlcm5hbCBDQSBSb290 +MB4XDTAwMDUzMDEwNDgzOFoXDTIwMDUzMDEwNDgzOFowbzELMAkGA1UEBhMCU0Ux +FDASBgNVBAoTC0FkZFRydXN0IEFCMSYwJAYDVQQLEx1BZGRUcnVzdCBFeHRlcm5h +bCBUVFAgTmV0d29yazEiMCAGA1UEAxMZQWRkVHJ1c3QgRXh0ZXJuYWwgQ0EgUm9v +dDCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBALf3GjPm8gAELTngTlvt +H7xsD821+iO2zt6bETOXpClMfZOfvUq8k+0DGuOPz+VtUFrWlymUWoCwSXrbLpX9 +uMq/NzgtHj6RQa1wVsfwTz/oMp50ysiQVOnGXw94nZpAPA6sYapeFI+eh6FqUNzX +mk6vBbOmcZSccbNQYArHE504B4YCqOmoaSYYkKtMsE8jqzpPhNjfzp/haW+710LX +a0Tkx63ubUFfclpxCDezeWWkWaCUN/cALw3CknLa0Dhy2xSoRcRdKn23tNbE7qzN +E0S3ySvdQwAl+mG5aWpYIxG3pzOPVnVZ9c0p10a3CitlttNCbxWyuHv77+ldU9U0 +WicCAwEAAaOB3DCB2TAdBgNVHQ4EFgQUrb2YejS0Jvf6xCZU7wO94CTLVBowCwYD +VR0PBAQDAgEGMA8GA1UdEwEB/wQFMAMBAf8wgZkGA1UdIwSBkTCBjoAUrb2YejS0 +Jvf6xCZU7wO94CTLVBqhc6RxMG8xCzAJBgNVBAYTAlNFMRQwEgYDVQQKEwtBZGRU +cnVzdCBBQjEmMCQGA1UECxMdQWRkVHJ1c3QgRXh0ZXJuYWwgVFRQIE5ldHdvcmsx +IjAgBgNVBAMTGUFkZFRydXN0IEV4dGVybmFsIENBIFJvb3SCAQEwDQYJKoZIhvcN +AQEFBQADggEBALCb4IUlwtYj4g+WBpKdQZic2YR5gdkeWxQHIzZlj7DYd7usQWxH +YINRsPkyPef89iYTx4AWpb9a/IfPeHmJIZriTAcKhjW88t5RxNKWt9x+Tu5w/Rw5 +6wwCURQtjr0W4MHfRnXnJK3s9EK0hZNwEGe6nQY1ShjTK3rMUUKhemPR5ruhxSvC +Nr4TDea9Y355e6cJDUCrat2PisP29owaQgVR1EX1n6diIWgVIEM8med8vSTYqZEX +c4g/VhsxOBi0cQ+azcgOno4uG+GMmIPLHzHxREzGBHNJdmAPx/i9F4BrLunMTA5a +mnkPIAou1Z5jJh5VkpTYghdae9C8x49OhgQ= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/addtrustqualifiedca b/make/data/cacerts/addtrustqualifiedca new file mode 100644 index 0000000..0c62d44 --- /dev/null +++ b/make/data/cacerts/addtrustqualifiedca
@@ -0,0 +1,32 @@ +Owner: CN=AddTrust Qualified CA Root, OU=AddTrust TTP Network, O=AddTrust AB, C=SE +Issuer: CN=AddTrust Qualified CA Root, OU=AddTrust TTP Network, O=AddTrust AB, C=SE +Serial number: 1 +Valid from: Tue May 30 10:44:50 GMT 2000 until: Sat May 30 10:44:50 GMT 2020 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEHjCCAwagAwIBAgIBATANBgkqhkiG9w0BAQUFADBnMQswCQYDVQQGEwJTRTEU +MBIGA1UEChMLQWRkVHJ1c3QgQUIxHTAbBgNVBAsTFEFkZFRydXN0IFRUUCBOZXR3 +b3JrMSMwIQYDVQQDExpBZGRUcnVzdCBRdWFsaWZpZWQgQ0EgUm9vdDAeFw0wMDA1 +MzAxMDQ0NTBaFw0yMDA1MzAxMDQ0NTBaMGcxCzAJBgNVBAYTAlNFMRQwEgYDVQQK +EwtBZGRUcnVzdCBBQjEdMBsGA1UECxMUQWRkVHJ1c3QgVFRQIE5ldHdvcmsxIzAh +BgNVBAMTGkFkZFRydXN0IFF1YWxpZmllZCBDQSBSb290MIIBIjANBgkqhkiG9w0B +AQEFAAOCAQ8AMIIBCgKCAQEA5B6a/twJWoekn0e+EV+vhDTbYjx5eLfpMLXsDBwq +xBb/4Oxx64r1EW7tTw2R0hIYLUkVAcKkIhPHEWT/IhKauY5cLwjPcWqzZwFZ8V1G +87B4pfYOQnrjfxvM0PC3KP0q6p6zsLkEqv32x7SxuCqg+1jxGaBvcCV+PmlKfw8i +2O+tCBGaKZnhqkRFmhJePp1tUvznoD1oL/BLcHwTOK28FSXx1s6rosAx1i+f4P8U +WfyEk9mHfExUE+uf0S0R+Bg6Ot4l2ffTQO2kBhLEO+GRwVY18BTcZTYJbqukB8c1 +0cIDMzZbdSZtQvESa0NvS3GU+jQd7RNuyoB/mC9suWXY6QIDAQABo4HUMIHRMB0G +A1UdDgQWBBQ5lYtii1zJ1IC6WA+XPxUIQ8yYpzALBgNVHQ8EBAMCAQYwDwYDVR0T +AQH/BAUwAwEB/zCBkQYDVR0jBIGJMIGGgBQ5lYtii1zJ1IC6WA+XPxUIQ8yYp6Fr +pGkwZzELMAkGA1UEBhMCU0UxFDASBgNVBAoTC0FkZFRydXN0IEFCMR0wGwYDVQQL +ExRBZGRUcnVzdCBUVFAgTmV0d29yazEjMCEGA1UEAxMaQWRkVHJ1c3QgUXVhbGlm +aWVkIENBIFJvb3SCAQEwDQYJKoZIhvcNAQEFBQADggEBABmrder4i2VhlRO6aQTv +hsoToMeqT2QbPxj2qC0sVY8FtzDqQmodwCVRLae/DLPt7wh/bDxGGuoYQ992zPlm +hpwsaPXpF/gxsxjE1kh9I0xowX67ARRvxdlu3rsEQmr49lx95dr6h+sNNVJn0J6X +dgWTP5XHAeZpVTh/EGGZyeNfpso+gmNIquIISD6q8rKFYqa0p9m9N5xotS1WfbC3 +P6CxB9bpT9zeRXEwMn8bLgn5v1Kh7sKAPgZcLlVAwRv1cEWw3F369nJad9Jjzc9Y +iQBCYz95OdBEsIJuQRno3eDBiFrRHnGTHyQwdOUeqN48Jzd/g66ed8/wMLH/S5no +xqE= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/affirmtrustcommercialca b/make/data/cacerts/affirmtrustcommercialca new file mode 100644 index 0000000..5caddfd --- /dev/null +++ b/make/data/cacerts/affirmtrustcommercialca
@@ -0,0 +1,27 @@ +Owner: CN=AffirmTrust Commercial, O=AffirmTrust, C=US +Issuer: CN=AffirmTrust Commercial, O=AffirmTrust, C=US +Serial number: 7777062726a9b17c +Valid from: Fri Jan 29 14:06:06 GMT 2010 until: Tue Dec 31 14:06:06 GMT 2030 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDTDCCAjSgAwIBAgIId3cGJyapsXwwDQYJKoZIhvcNAQELBQAwRDELMAkGA1UE +BhMCVVMxFDASBgNVBAoMC0FmZmlybVRydXN0MR8wHQYDVQQDDBZBZmZpcm1UcnVz +dCBDb21tZXJjaWFsMB4XDTEwMDEyOTE0MDYwNloXDTMwMTIzMTE0MDYwNlowRDEL +MAkGA1UEBhMCVVMxFDASBgNVBAoMC0FmZmlybVRydXN0MR8wHQYDVQQDDBZBZmZp +cm1UcnVzdCBDb21tZXJjaWFsMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKC +AQEA9htPZwcroRX1BiLLHwGy43NFBkRJLLtJJRTWzsO3qyxPxkEylFf6EqdbDuKP +Hx6GGaeqtS25Xw2Kwq+FNXkyLbscYjfysVtKPcrNcV/pQr6U6Mje+SJIZMblq8Yr +ba0F8PrVC8+a5fBQpIs7R6UjW3p6+DM/uO+Zl+MgwdYoic+U+7lF7eNAFxHUdPAL +MeIrJmqbTFeurCA+ukV6BfO9m2kVrn1OIGPENXY6BwLJN/3HR+7o8XYdcxXyl6S1 +yHp52UKqK39c/s4mT6NmgTWvRLpUHhwwMmWd5jyTXlBOeuM61G7MGvv50jeuJCqr +VwMiKA1JdX+3KNp1v47j3A55MQIDAQABo0IwQDAdBgNVHQ4EFgQUnZPGU4teyq8/ +nx4P5ZmVvCT2lI8wDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwDQYJ +KoZIhvcNAQELBQADggEBAFis9AQOzcAN/wr91LoWXym9e2iZWEnStB03TX8nfUYG +XUPGhi4+c7ImfU+TqbbEKpqrIZcUsd6M06uJFdhrJNTxFq7YpFzUf1GO7RgBsZNj +vbz4YYCanrHOQnDiqX0GJX0nof5v7LMeJNrjS1UaADs1tDvZ110w/YETifLCBivt +Z8SOyUOyXGsViQK8YvxO8rUzqrJv0wqiUOP2O+guRMLbZjipM1ZI8W0bM40NjD9g +N53Tym1+NH4Nn3J2ixufcv1SNUFFApYvHLKac0khsUlHRUe072o0EclNmsxZt9YC +nlpOZbWUrhvfKbAW8b8Angc6F2S1BLUjIZkKlTuXfO8= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/affirmtrustnetworkingca b/make/data/cacerts/affirmtrustnetworkingca new file mode 100644 index 0000000..c773326 --- /dev/null +++ b/make/data/cacerts/affirmtrustnetworkingca
@@ -0,0 +1,27 @@ +Owner: CN=AffirmTrust Networking, O=AffirmTrust, C=US +Issuer: CN=AffirmTrust Networking, O=AffirmTrust, C=US +Serial number: 7c4f04391cd4992d +Valid from: Fri Jan 29 14:08:24 GMT 2010 until: Tue Dec 31 14:08:24 GMT 2030 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDTDCCAjSgAwIBAgIIfE8EORzUmS0wDQYJKoZIhvcNAQEFBQAwRDELMAkGA1UE +BhMCVVMxFDASBgNVBAoMC0FmZmlybVRydXN0MR8wHQYDVQQDDBZBZmZpcm1UcnVz +dCBOZXR3b3JraW5nMB4XDTEwMDEyOTE0MDgyNFoXDTMwMTIzMTE0MDgyNFowRDEL +MAkGA1UEBhMCVVMxFDASBgNVBAoMC0FmZmlybVRydXN0MR8wHQYDVQQDDBZBZmZp +cm1UcnVzdCBOZXR3b3JraW5nMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKC +AQEAtITMMxcua5Rsa2FSoOujz3mUTOWUgJnLVWREZY9nZOIG41w3SfYvm4SEHi3y +YJ0wTsyEheIszx6e/jarM3c1RNg1lho9Nuh6DtjVR6FqaYvZ/Ls6rnla1fTWcbua +kCNrmreIdIcMHl+5ni36q1Mr3Lt2PpNMCAiMHqIjHNRqrSK6mQEubWXLviRmVSRL +QESxG9fhwoXA3hA/Pe24/PHxI1Pcv2WXb9n5QHGNfb2V1M6+oF4nI979ptAmDgAp +6zxG8D1gvz9Q0twmQVGeFDdCBKNwV6gbh+0t+nvujArjqWaJGctB+d1ENmHP4ndG +yH329JKBNv3bNPFyfvMMFr20FQIDAQABo0IwQDAdBgNVHQ4EFgQUBx/S55zawm6i +QLSwelAQUHTEyL0wDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwDQYJ +KoZIhvcNAQEFBQADggEBAIlXshZ6qML91tmbmzTCnLQyFE2npN/svqe++EPbkTfO +tDIuUFUaNU52Q3Eg75N3ThVwLofDwR1t3Mu1J9QsVtFSUzpE0nPIxBsFZVpikpzu +QY0x2+c06lkh1QF612S4ZDnNye2v7UsDSKegmQGA3GWjNq5lWUhPgkvIZfFXHeVZ +Lgo/bNjR9eUJtGxUAArgFU2HdW23WJZa3W3SAKD0m0i+wzekujbgfIeFlxoVot4u +olu9rxj5kFDNcFn4J2dHy8egBzp90SxdbBk6ZrV9/ZFvgrG+CJPbFEfxojfHRZ48 +x3evZKiT3/Zpg4Jg8klCNO1aAFSFHBY2kgxc+qatv9s= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/affirmtrustpremiumca b/make/data/cacerts/affirmtrustpremiumca new file mode 100644 index 0000000..275b495 --- /dev/null +++ b/make/data/cacerts/affirmtrustpremiumca
@@ -0,0 +1,38 @@ +Owner: CN=AffirmTrust Premium, O=AffirmTrust, C=US +Issuer: CN=AffirmTrust Premium, O=AffirmTrust, C=US +Serial number: 6d8c1446b1a60aee +Valid from: Fri Jan 29 14:10:36 GMT 2010 until: Mon Dec 31 14:10:36 GMT 2040 +Signature algorithm name: SHA384withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFRjCCAy6gAwIBAgIIbYwURrGmCu4wDQYJKoZIhvcNAQEMBQAwQTELMAkGA1UE +BhMCVVMxFDASBgNVBAoMC0FmZmlybVRydXN0MRwwGgYDVQQDDBNBZmZpcm1UcnVz +dCBQcmVtaXVtMB4XDTEwMDEyOTE0MTAzNloXDTQwMTIzMTE0MTAzNlowQTELMAkG +A1UEBhMCVVMxFDASBgNVBAoMC0FmZmlybVRydXN0MRwwGgYDVQQDDBNBZmZpcm1U +cnVzdCBQcmVtaXVtMIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEAxBLf +qV/+Qd3d9Z+K4/as4Tx4mrzY8H96oDMq3I0gW64tb+eT2TZwamjPjlGjhVtnBKAQ +JG9dKILBl1fYSCkTtuG+kU3fhQxTGJoeJKJPj/CihQvL9Cl/0qRY7iZNyaqoe5rZ ++jjeRFcV5fiMyNlI4g0WJx0eyIOFJbe6qlVBzAMiSy2RjYvmia9mx+n/K+k8rNrS +s8PhaJyJ+HoAVt70VZVs+7pk3WKL3wt3MutizCaam7uqYoNMtAZ6MMgpv+0GTZe5 +HMQxK9VfvFMSF5yZVylmd2EhMQcuJUmdGPLu8ytxjLW6OQdJd/zvLpKQBY0tL3d7 +70O/Nbua2Plzpyzy0FfuKE4mX4+QaAkvuPjcBukumj5Rp9EixAqnOEhss/n/fauG +V+O61oV4d7pD6kh/9ti+I20ev9E2bFhc8e6kGVQa9QPSdubhjL08s9NIS+LI+H+S +qHZGnEJlPqQewQcDWkYtuJfzt9WyVSHvutxMAJf7FJUnM7/oQ0dG0giZFmA7mn7S +5u046uwBHjxIVkkJx0w3AJ6IDsBz4W9m6XJHMD4Q5QsDyZpCAGzFlH5hxIrff4Ia +C1nEWTJ3s7xgaVY5/bQGeyzWZDbZvUjthB9+pSKPKrhC9IK31FOQeE4tGv2Bb0TX +OwF0lkLgAOIua+rF7nKsu7/+6qqo+Nz2snmKtmcCAwEAAaNCMEAwHQYDVR0OBBYE +FJ3AZ6YMItkm9UWrpmVSESfYRaxjMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/ +BAQDAgEGMA0GCSqGSIb3DQEBDAUAA4ICAQCzV00QYk465KzquByvMiPIs0laUZx2 +KI15qldGF9X1Uva3ROgIRL8YhNILgM3FEv0AVQVhh0HctSSePMTYyPtwni94loMg +Nt58D2kTiKV1NpgIpsbfrM7jWNa3Pt668+s0QNiigfV4Py/VpfzZotReBA4Xrf5B +8OWycvpEgjNC6C1Y91aMYj+6QrCcDFx+LmUmXFNPALJ4fqENmS2NuB2OosSw/WDQ +MKSOyARiqcTtNd56l+0OOF6SL5Nwpamcb6d9Ex1+xghIsV5n61EIJenmJWtSKZGc +0jlzCFfemQa0W50QBuHCAKi4HEoCChTQwUHK+4w1IX2COPKpVJEZNZOUbWo6xbLQ +u4mGk+ibyQ86p3q4ofB4Rvr8Ny/lioTz3/4E2aFooC8k4gmVBtWVyuEklut89pMF +u+1z6S3RdTnX5yTb2E5fQ4+e0BQ5v1VwSJlXMbSc7kqYA5YwH2AG7hsj/oFgIxpH +YoWlzBk0gG+zrBrjn/B7SK3VAdlntqlyk+otZrWyuOQ9PLLvTIzq6we/qzWaVYa8 +GKa1qF60g2xraUDTn9zxw2lrueFtCfTxqlB2Cnp9ehehVZZCmTEJ3WARjQUwfuaO +RtGdFNrHF+QFlozEJLUbzxQHskD4o55BhrwE0GuWyCqANP2/7waj3VjFhT0+j/6e +KeC2uAloGRwYQw== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/affirmtrustpremiumeccca b/make/data/cacerts/affirmtrustpremiumeccca new file mode 100644 index 0000000..d0fcc1e --- /dev/null +++ b/make/data/cacerts/affirmtrustpremiumeccca
@@ -0,0 +1,20 @@ +Owner: CN=AffirmTrust Premium ECC, O=AffirmTrust, C=US +Issuer: CN=AffirmTrust Premium ECC, O=AffirmTrust, C=US +Serial number: 7497258ac73f7a54 +Valid from: Fri Jan 29 14:20:24 GMT 2010 until: Mon Dec 31 14:20:24 GMT 2040 +Signature algorithm name: SHA384withECDSA +Subject Public Key Algorithm: 384-bit EC (secp384r1) key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIB/jCCAYWgAwIBAgIIdJclisc/elQwCgYIKoZIzj0EAwMwRTELMAkGA1UEBhMC +VVMxFDASBgNVBAoMC0FmZmlybVRydXN0MSAwHgYDVQQDDBdBZmZpcm1UcnVzdCBQ +cmVtaXVtIEVDQzAeFw0xMDAxMjkxNDIwMjRaFw00MDEyMzExNDIwMjRaMEUxCzAJ +BgNVBAYTAlVTMRQwEgYDVQQKDAtBZmZpcm1UcnVzdDEgMB4GA1UEAwwXQWZmaXJt +VHJ1c3QgUHJlbWl1bSBFQ0MwdjAQBgcqhkjOPQIBBgUrgQQAIgNiAAQNMF4bFZ0D +0KF5Nbc6PJJ6yhUczWLznCZcBz3lVPqj1swS6vQUX+iOGasvLkjmrBhDeKzQN8O9 +ss0s5kfiGuZjuD0uL3jET9v0D6RoTFVya5UdThhClXjMNzyR4ptlKymjQjBAMB0G +A1UdDgQWBBSaryl6wBE1NSZRMADDav5A1a7WPDAPBgNVHRMBAf8EBTADAQH/MA4G +A1UdDwEB/wQEAwIBBjAKBggqhkjOPQQDAwNnADBkAjAXCfOHiFBar8jAQr9HX/Vs +aobgxCd05DhT1wV/GzTjxi+zygk8N53X57hG8f2h4nECMEJZh0PUUd+60wkyWs6I +flc9nF9Ca/UHLbXwgpP5WW+uZPpY5Yse42O+tYHNbwKMeQ== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/amazonrootca1 b/make/data/cacerts/amazonrootca1 new file mode 100644 index 0000000..9431a65 --- /dev/null +++ b/make/data/cacerts/amazonrootca1
@@ -0,0 +1,27 @@ +Owner: CN=Amazon Root CA 1, O=Amazon, C=US +Issuer: CN=Amazon Root CA 1, O=Amazon, C=US +Serial number: 66c9fcf99bf8c0a39e2f0788a43e696365bca +Valid from: Tue May 26 00:00:00 GMT 2015 until: Sun Jan 17 00:00:00 GMT 2038 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDQTCCAimgAwIBAgITBmyfz5m/jAo54vB4ikPmljZbyjANBgkqhkiG9w0BAQsF +ADA5MQswCQYDVQQGEwJVUzEPMA0GA1UEChMGQW1hem9uMRkwFwYDVQQDExBBbWF6 +b24gUm9vdCBDQSAxMB4XDTE1MDUyNjAwMDAwMFoXDTM4MDExNzAwMDAwMFowOTEL +MAkGA1UEBhMCVVMxDzANBgNVBAoTBkFtYXpvbjEZMBcGA1UEAxMQQW1hem9uIFJv +b3QgQ0EgMTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBALJ4gHHKeNXj +ca9HgFB0fW7Y14h29Jlo91ghYPl0hAEvrAIthtOgQ3pOsqTQNroBvo3bSMgHFzZM +9O6II8c+6zf1tRn4SWiw3te5djgdYZ6k/oI2peVKVuRF4fn9tBb6dNqcmzU5L/qw +IFAGbHrQgLKm+a/sRxmPUDgH3KKHOVj4utWp+UhnMJbulHheb4mjUcAwhmahRWa6 +VOujw5H5SNz/0egwLX0tdHA114gk957EWW67c4cX8jJGKLhD+rcdqsq08p8kDi1L +93FcXmn/6pUCyziKrlA4b9v7LWIbxcceVOF34GfID5yHI9Y/QCB/IIDEgEw+OyQm +jgSubJrIqg0CAwEAAaNCMEAwDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMC +AYYwHQYDVR0OBBYEFIQYzIU07LwMlJQuCFmcx7IQTgoIMA0GCSqGSIb3DQEBCwUA +A4IBAQCY8jdaQZChGsV2USggNiMOruYou6r4lK5IpDB/G/wkjUu0yKGX9rbxenDI +U5PMCCjjmCXPI6T53iHTfIUJrU6adTrCC2qJeHZERxhlbI1Bjjt/msv0tadQ1wUs +N+gDS63pYaACbvXy8MWy7Vu33PqUXHeeE6V/Uq2V8viTO96LXFvKWlJbYK8U90vv +o/ufQJVtMVT8QtPHRh8jrdkPSHCa2XV4cdFyQzR1bldZwgJcJmApzyMZFo6IQ6XU +5MsI+yMRQ+hDKXJioaldXgjUkK642M4UwtBV8ob2xJNDd2ZhwLnoQdeXeGADbkpy +rqXRfboQnoZsG4q5WTP468SQvvG5 +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/amazonrootca2 b/make/data/cacerts/amazonrootca2 new file mode 100644 index 0000000..95e6f32 --- /dev/null +++ b/make/data/cacerts/amazonrootca2
@@ -0,0 +1,38 @@ +Owner: CN=Amazon Root CA 2, O=Amazon, C=US +Issuer: CN=Amazon Root CA 2, O=Amazon, C=US +Serial number: 66c9fd29635869f0a0fe58678f85b26bb8a37 +Valid from: Tue May 26 00:00:00 GMT 2015 until: Sat May 26 00:00:00 GMT 2040 +Signature algorithm name: SHA384withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFQTCCAymgAwIBAgITBmyf0pY1hp8KD+WGePhbJruKNzANBgkqhkiG9w0BAQwF +ADA5MQswCQYDVQQGEwJVUzEPMA0GA1UEChMGQW1hem9uMRkwFwYDVQQDExBBbWF6 +b24gUm9vdCBDQSAyMB4XDTE1MDUyNjAwMDAwMFoXDTQwMDUyNjAwMDAwMFowOTEL +MAkGA1UEBhMCVVMxDzANBgNVBAoTBkFtYXpvbjEZMBcGA1UEAxMQQW1hem9uIFJv +b3QgQ0EgMjCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAK2Wny2cSkxK +gXlRmeyKy2tgURO8TW0G/LAIjd0ZEGrHJgw12MBvIITplLGbhQPDW9tK6Mj4kHbZ +W0/jTOgGNk3Mmqw9DJArktQGGWCsN0R5hYGCrVo34A3MnaZMUnbqQ523BNFQ9lXg +1dKmSYXpN+nKfq5clU1Imj+uIFptiJXZNLhSGkOQsL9sBbm2eLfq0OQ6PBJTYv9K +8nu+NQWpEjTj82R0Yiw9AElaKP4yRLuH3WUnAnE72kr3H9rN9yFVkE8P7K6C4Z9r +2UXTu/Bfh+08LDmG2j/e7HJV63mjrdvdfLC6HM783k81ds8P+HgfajZRRidhW+me +z/CiVX18JYpvL7TFz4QuK/0NURBs+18bvBt+xa47mAExkv8LV/SasrlX6avvDXbR +8O70zoan4G7ptGmh32n2M8ZpLpcTnqWHsFcQgTfJU7O7f/aS0ZzQGPSSbtqDT6Zj +mUyl+17vIWR6IF9sZIUVyzfpYgwLKhbcAS4y2j5L9Z469hdAlO+ekQiG+r5jqFoz +7Mt0Q5X5bGlSNscpb/xVA1wf+5+9R+vnSUeVC06JIglJ4PVhHvG/LopyboBZ/1c6 ++XUyo05f7O0oYtlNc/LMgRdg7c3r3NunysV+Ar3yVAhU/bQtCSwXVEqY0VThUWcI +0u1ufm8/0i2BWSlmy5A5lREedCf+3euvAgMBAAGjQjBAMA8GA1UdEwEB/wQFMAMB +Af8wDgYDVR0PAQH/BAQDAgGGMB0GA1UdDgQWBBSwDPBMMPQFWAJI/TPlUq9LhONm +UjANBgkqhkiG9w0BAQwFAAOCAgEAqqiAjw54o+Ci1M3m9Zh6O+oAA7CXDpO8Wqj2 +LIxyh6mx/H9z/WNxeKWHWc8w4Q0QshNabYL1auaAn6AFC2jkR2vHat+2/XcycuUY ++gn0oJMsXdKMdYV2ZZAMA3m3MSNjrXiDCYZohMr/+c8mmpJ5581LxedhpxfL86kS +k5Nrp+gvU5LEYFiwzAJRGFuFjWJZY7attN6a+yb3ACfAXVU3dJnJUH/jWS5E4ywl +7uxMMne0nxrpS10gxdr9HIcWxkPo1LsmmkVwXqkLN1PiRnsn/eBG8om3zEK2yygm +btmlyTrIQRNg91CMFa6ybRoVGld45pIq2WWQgj9sAq+uEjonljYE1x2igGOpm/Hl +urR8FLBOybEfdF849lHqm/osohHUqS0nGkWxr7JOcQ3AWEbWaQbLU8uz/mtBzUF+ +fUwPfHJ5elnNXkoOrJupmHN5fLT0zLm4BwyydFy4x2+IoZCn9Kr5v2c69BoVYh63 +n749sSmvZ6ES8lgQGVMDMBu4Gon2nL2XA46jCfMdiyHxtN/kHNGfZQIG6lzWE7OE +76KlXIx3KadowGuuQNKotOrN8I1LOJwZmhsoVLiJkO/KdYE+HvJkJMcYr07/R54H +9jVlpNMKVv/1F2Rs76giJUmTtt8AF9pYfl3uxRuw0dFfIRDH+fO6AgonB8Xx1sfT +4PsJYGw= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/amazonrootca3 b/make/data/cacerts/amazonrootca3 new file mode 100644 index 0000000..96a5c63 --- /dev/null +++ b/make/data/cacerts/amazonrootca3
@@ -0,0 +1,19 @@ +Owner: CN=Amazon Root CA 3, O=Amazon, C=US +Issuer: CN=Amazon Root CA 3, O=Amazon, C=US +Serial number: 66c9fd5749736663f3b0b9ad9e89e7603f24a +Valid from: Tue May 26 00:00:00 GMT 2015 until: Sat May 26 00:00:00 GMT 2040 +Signature algorithm name: SHA256withECDSA +Subject Public Key Algorithm: 256-bit EC key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIBtjCCAVugAwIBAgITBmyf1XSXNmY/Owua2eiedgPySjAKBggqhkjOPQQDAjA5 +MQswCQYDVQQGEwJVUzEPMA0GA1UEChMGQW1hem9uMRkwFwYDVQQDExBBbWF6b24g +Um9vdCBDQSAzMB4XDTE1MDUyNjAwMDAwMFoXDTQwMDUyNjAwMDAwMFowOTELMAkG +A1UEBhMCVVMxDzANBgNVBAoTBkFtYXpvbjEZMBcGA1UEAxMQQW1hem9uIFJvb3Qg +Q0EgMzBZMBMGByqGSM49AgEGCCqGSM49AwEHA0IABCmXp8ZBf8ANm+gBG1bG8lKl +ui2yEujSLtf6ycXYqm0fc4E7O5hrOXwzpcVOho6AF2hiRVd9RFgdszflZwjrZt6j +QjBAMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQDAgGGMB0GA1UdDgQWBBSr +ttvXBp43rDCGB5Fwx5zEGbF4wDAKBggqhkjOPQQDAgNJADBGAiEA4IWSoxe3jfkr +BqWTrBqYaGFy+uGh0PsceGCmQ5nFuMQCIQCcAu/xlJyzlvnrxir4tiz+OpAUFteM +YyRIHN8wfdVoOw== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/amazonrootca4 b/make/data/cacerts/amazonrootca4 new file mode 100644 index 0000000..9a59ca2 --- /dev/null +++ b/make/data/cacerts/amazonrootca4
@@ -0,0 +1,20 @@ +Owner: CN=Amazon Root CA 4, O=Amazon, C=US +Issuer: CN=Amazon Root CA 4, O=Amazon, C=US +Serial number: 66c9fd7c1bb104c2943e5717b7b2cc81ac10e +Valid from: Tue May 26 00:00:00 GMT 2015 until: Sat May 26 00:00:00 GMT 2040 +Signature algorithm name: SHA384withECDSA +Subject Public Key Algorithm: 384-bit EC key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIB8jCCAXigAwIBAgITBmyf18G7EEwpQ+Vxe3ssyBrBDjAKBggqhkjOPQQDAzA5 +MQswCQYDVQQGEwJVUzEPMA0GA1UEChMGQW1hem9uMRkwFwYDVQQDExBBbWF6b24g +Um9vdCBDQSA0MB4XDTE1MDUyNjAwMDAwMFoXDTQwMDUyNjAwMDAwMFowOTELMAkG +A1UEBhMCVVMxDzANBgNVBAoTBkFtYXpvbjEZMBcGA1UEAxMQQW1hem9uIFJvb3Qg +Q0EgNDB2MBAGByqGSM49AgEGBSuBBAAiA2IABNKrijdPo1MN/sGKe0uoe0ZLY7Bi +9i0b2whxIdIA6GO9mif78DluXeo9pcmBqqNbIJhFXRbb/egQbeOc4OO9X4Ri83Bk +M6DLJC9wuoihKqB1+IGuYgbEgds5bimwHvouXKNCMEAwDwYDVR0TAQH/BAUwAwEB +/zAOBgNVHQ8BAf8EBAMCAYYwHQYDVR0OBBYEFNPsxzplbszh2naaVvuc84ZtV+WB +MAoGCCqGSM49BAMDA2gAMGUCMDqLIfG9fhGt0O9Yli/W651+kI0rz2ZVwyzjKKlw +CkcO8DdZEv8tmZQoTipPNU0zWgIxAOp1AE47xDqUEpHJWEadIRNyp4iciuRMStuW +1KyLa2tJElMzrdfkviT8tQp21KW8EA== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/baltimorecybertrustca b/make/data/cacerts/baltimorecybertrustca new file mode 100644 index 0000000..b3cf654 --- /dev/null +++ b/make/data/cacerts/baltimorecybertrustca
@@ -0,0 +1,28 @@ +Owner: CN=Baltimore CyberTrust Root, OU=CyberTrust, O=Baltimore, C=IE +Issuer: CN=Baltimore CyberTrust Root, OU=CyberTrust, O=Baltimore, C=IE +Serial number: 20000b9 +Valid from: Fri May 12 18:46:00 GMT 2000 until: Mon May 12 23:59:00 GMT 2025 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDdzCCAl+gAwIBAgIEAgAAuTANBgkqhkiG9w0BAQUFADBaMQswCQYDVQQGEwJJ +RTESMBAGA1UEChMJQmFsdGltb3JlMRMwEQYDVQQLEwpDeWJlclRydXN0MSIwIAYD +VQQDExlCYWx0aW1vcmUgQ3liZXJUcnVzdCBSb290MB4XDTAwMDUxMjE4NDYwMFoX +DTI1MDUxMjIzNTkwMFowWjELMAkGA1UEBhMCSUUxEjAQBgNVBAoTCUJhbHRpbW9y +ZTETMBEGA1UECxMKQ3liZXJUcnVzdDEiMCAGA1UEAxMZQmFsdGltb3JlIEN5YmVy +VHJ1c3QgUm9vdDCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAKMEuyKr +mD1X6CZymrV51Cni4eiVgLGw41uOKymaZN+hXe2wCQVt2yguzmKiYv60iNoS6zjr +IZ3AQSsBUnuId9Mcj8e6uYi1agnnc+gRQKfRzMpijS3ljwumUNKoUMMo6vWrJYeK +mpYcqWe4PwzV9/lSEy/CG9VwcPCPwBLKBsua4dnKM3p31vjsufFoREJIE9LAwqSu +XmD+tqYF/LTdB1kC1FkYmGP1pWPgkAx9XbIGevOF6uvUA65ehD5f/xXtabz5OTZy +dc93Uk3zyZAsuT3lySNTPx8kmCFcB5kpvcY67Oduhjprl3RjM71oGDHweI12v/ye +jl0qhqdNkNwnGjkCAwEAAaNFMEMwHQYDVR0OBBYEFOWdWTCCR1jMrPoIVDaGezq1 +BE3wMBIGA1UdEwEB/wQIMAYBAf8CAQMwDgYDVR0PAQH/BAQDAgEGMA0GCSqGSIb3 +DQEBBQUAA4IBAQCFDF2O5G9RaEIFoN27TyclhAO992T9Ldcw46QQF+vaKSm2eT92 +9hkTI7gQCvlYpNRhcL0EYWoSihfVCr3FvDB81ukMJY2GQE/szKN+OMY3EU/t3Wgx +jkzSswF07r51XgdIGn9w/xZchMB5hbgF/X++ZRGjD8ACtPhSNzkE1akxehi/oCr0 +Epn3o0WC4zxe9Z2etciefC7IpJ5OCBRLbf1wbWsaY71k5h+3zvDyny67G7fyUIhz +ksLi4xaNmjICq44Y3ekQEe5+NauQrz4wlHrQMz2nZQ/1/I6eYs9HRCwBXbsdtTLS +R9I4LtD+gdwyah617jzV/OeBHRnDJELqYzmp +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/buypassclass2ca b/make/data/cacerts/buypassclass2ca new file mode 100644 index 0000000..a2e9b2f --- /dev/null +++ b/make/data/cacerts/buypassclass2ca
@@ -0,0 +1,38 @@ +Owner: CN=Buypass Class 2 Root CA, O=Buypass AS-983163327, C=NO +Issuer: CN=Buypass Class 2 Root CA, O=Buypass AS-983163327, C=NO +Serial number: 2 +Valid from: Tue Oct 26 08:38:03 GMT 2010 until: Fri Oct 26 08:38:03 GMT 2040 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFWTCCA0GgAwIBAgIBAjANBgkqhkiG9w0BAQsFADBOMQswCQYDVQQGEwJOTzEd +MBsGA1UECgwUQnV5cGFzcyBBUy05ODMxNjMzMjcxIDAeBgNVBAMMF0J1eXBhc3Mg +Q2xhc3MgMiBSb290IENBMB4XDTEwMTAyNjA4MzgwM1oXDTQwMTAyNjA4MzgwM1ow +TjELMAkGA1UEBhMCTk8xHTAbBgNVBAoMFEJ1eXBhc3MgQVMtOTgzMTYzMzI3MSAw +HgYDVQQDDBdCdXlwYXNzIENsYXNzIDIgUm9vdCBDQTCCAiIwDQYJKoZIhvcNAQEB +BQADggIPADCCAgoCggIBANfHXvfBB9R3+0Mh9PT1aeTuMgHbo4Yf5FkNuud1g1Lr +6hxhFUi7HQfKjK6w3Jad6sNgkoaCKHOcVgb/S2TwDCo3SbXlzwx87vFKu3MwZfPV +L4O2fuPn9Z6rYPnT8Z2SdIrkHJasW4DptfQxh6NR/Md+oW+OU3fUl8FVM5I+GC91 +1K2GScuVr1QGbNgGE41b/+EmGVnAJLqBcXmQRFBoJJRfuLMR8SlBYaNByyM21cHx +MlAQTn/0hpPshNOOvEu/XAFOBz3cFIqUCqTqc/sLUegTBxj6DvEr0VQVfTzh97QZ +QmdiXnfgolXsttlpF9U6r0TtSsWe5HonfOV116rLJeffawrbD02TTqigzXsu8lkB +arcNuAeBfos4GzjmCleZPe4h6KP1DBbdi+w0jpwqHAAVF41og9JwnxgIzRFo1clr +Us3ERo/ctfPYV3Me6ZQ5BL/T3jjetFPsaRyifsSP5BtwrfKi+fv3FmRmaZ9JUaLi +FRhnBkp/1Wy1TbMz4GHrXb7pmA8y1x1LPC5aAVKRCfLf6o3YBkBjqhHk/sM3nhRS +P/TizPJhk9H9Z2vXUq6/aKtAQ6BXNVN48FP4YUIHZMbXb5tMOA1jrGKvNouicwoN +9SG9dKpN6nIDSdvHXx1iY8f93ZHsM+71bbRuMGjeyNYmsHVee7QHIJihdjK4TWxP +AgMBAAGjQjBAMA8GA1UdEwEB/wQFMAMBAf8wHQYDVR0OBBYEFMmAd+BikoL1Rpzz +uvdMw964o605MA4GA1UdDwEB/wQEAwIBBjANBgkqhkiG9w0BAQsFAAOCAgEAU18h +9bqwOlI5LJKwbADJ784g7wbylp7ppHR/ehb8t/W2+xUbP6umwHJdELFx7rxP462s +A20ucS6vxOOto70MEae0/0qyexAQH6dXQbLArvQsWdZHEIjzIVEpMMpghq9Gqx3t +OluwlN5E40EIosHsHdb9T7bWR9AUC8rmyrV7d35BH16Dx7aMOZawP5aBQW9gkOLo ++fsicdl9sz1Gv7SEr5AcD48Saq/v7h56rgJKihcrdv6sVIkkLE8/trKnToyokZf7 +KcZ7XC25y2a2t6hbElGFtQl+Ynhw/qlqYLYdDnkM/crqJIByw5c/8nerQyIKx+u2 +DISCLIBrQYoIwOula9+ZEsuK1V6ADJHgJgg2SMX6OBE1/yWDLfJ6v9r9jv6ly0Us +H8SIU653DtmadsWOLB2jutXsMq7Aqqz30XpN69QH4kj3Io6wpJ9qzo6ysmD0oyLQ +I+uUWnpp3Q+/QFesa1lQ2aOZ4W7+jQF5JyMV3pKdewlNWudLSDBaGOYKbeaP4NK7 +5t98biGCwWg5TbSYWGZizEqQXsP6JwSxeRV0mcy+rSDeJmAc61ZRpqPq5KM/p/9h +3PFaTWwyI0PurKju7koSCTxdccK+efrCh2gdC/1cacwG0Jp9VJkqyTkaGa9LKkPz +Y11aWOIv4x3kqdbQCtCev9eBCfHJxyYNrJgWVqA= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/buypassclass3ca b/make/data/cacerts/buypassclass3ca new file mode 100644 index 0000000..f74c6c2 --- /dev/null +++ b/make/data/cacerts/buypassclass3ca
@@ -0,0 +1,38 @@ +Owner: CN=Buypass Class 3 Root CA, O=Buypass AS-983163327, C=NO +Issuer: CN=Buypass Class 3 Root CA, O=Buypass AS-983163327, C=NO +Serial number: 2 +Valid from: Tue Oct 26 08:28:58 GMT 2010 until: Fri Oct 26 08:28:58 GMT 2040 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFWTCCA0GgAwIBAgIBAjANBgkqhkiG9w0BAQsFADBOMQswCQYDVQQGEwJOTzEd +MBsGA1UECgwUQnV5cGFzcyBBUy05ODMxNjMzMjcxIDAeBgNVBAMMF0J1eXBhc3Mg +Q2xhc3MgMyBSb290IENBMB4XDTEwMTAyNjA4Mjg1OFoXDTQwMTAyNjA4Mjg1OFow +TjELMAkGA1UEBhMCTk8xHTAbBgNVBAoMFEJ1eXBhc3MgQVMtOTgzMTYzMzI3MSAw +HgYDVQQDDBdCdXlwYXNzIENsYXNzIDMgUm9vdCBDQTCCAiIwDQYJKoZIhvcNAQEB +BQADggIPADCCAgoCggIBAKXaCpUWUOOV8l6ddjEGMnqb8RB2uACatVI2zSRHsJ8Y +ZLya9vrVediQYkwiL944PdbgqOkcLNt4EemOaFEVcsfzM4fkoF0LXOBXByow9c3E +N3coTRiR5r/VUv1xLXA+58bEiuPwKAv0dpihi4dVsjoT/Lc+JzeOIuOoTyrvYLs9 +tznDDgFHmV0ST9tD+leh7fmdvhFHJlsTmKtdFoqwNxxXnUX/iJY2v7vKB3tvh2PX +0DJq1l1sDPGzbjniazEuOQAnFN44wOwZZoYS6J1yFhNkUsepNxz9gjDthBgd9K5c +/3ATAOux9TN6S9ZV+AWNS2mw9bMoNlwUxFFzTWsL8TQH2xc519woe2v1n/MuwU8X +KhDzzMro6/1rqy6any2CbgTUUgGTLT2G/H783+9CHaZr77kgxve9oKeV/afmiSTY +zIw0bOIjL9kSGiG5VZFvC5F5GQytQIgLcOJ60g7YaEi7ghM5EFjp2CoHxhLbWNvS +O1UQRwUVZ2J+GGOmRj8JDlQyXr8NYnon74Do29lLBlo3WiXQCBJ31G8JUJc9yB3D +34xFMFbG02SrZvPAXpacw8Tvw3xrizp5f7NJzz3iiZ+gMEuFuZyUJHmPfWupRWgP +K9Dx2hzLabjKSWJtyNBjYt1gD1iqj6G8BaVmos8bdrKEZLFMOVLAMLrwjEsCsLa3 +AgMBAAGjQjBAMA8GA1UdEwEB/wQFMAMBAf8wHQYDVR0OBBYEFEe4zf/lb+74suwv +Tg75JbCOPGvDMA4GA1UdDwEB/wQEAwIBBjANBgkqhkiG9w0BAQsFAAOCAgEAACAj +QTUEkMJAYmDv4jVM1z+s4jSQuKFvdvoWFqRINyzpkMLyPPgKn9iB5btb2iUspKdV +cSQy9sgL8rxq+JOssgfCX5/bzMiKqr5qb+FJEMwx14C7u8jYog5kV+qi9cKpMRXS +IGrs/CIBKM+GuIAeqcwRpTzyFrNHnfzSgCHEy9BHcEGhyoMZCCxt8l13nIoUE9Q2 +HJLw5QY33KbmkJs4j1xrG0aGQ0JfPgEHU1RdZX33inOhmlRaHylDFCfChQ+1iHsa +O5S3HWCntZznKWlXWpuTekMwGwPXYshApqr8ZORK15FTAaggiG6cX0S5y2CBNOxv +033aSF/rtJC8LakcC6wc1aJoIIAE1vyxjy+7SjENSoYc6+I2KSb12tjE8nVhz36u +dmNKekBlk4f4HoCMhuWG1o8O/FMsYOgWYRqiPkN7zTlgVGr18okmAWiDSKIz6MkE +kbIRNBE+6tBDGR8Dk5AM/1E9V/RBbuHLoL7ryWPNbczk+DaqaJ3tvV2XcEQNtg41 +3OEMXbugUZTLfhbrES+jkkXITHHZvMmZUldGL1DPvTVp9D0VzgalLA8+9oG6lLvD +u79leNKGef9JOxqDDPDeeOzI8k1MGt6CKfjBWtrt7uYnXuhF0J0cUahoq0Tj0Itq +4/g7u9xN12TyUb7mqqta6THuBrxzvxNiCp/HuZc= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/camerfirmachambersca b/make/data/cacerts/camerfirmachambersca new file mode 100644 index 0000000..70d793e --- /dev/null +++ b/make/data/cacerts/camerfirmachambersca
@@ -0,0 +1,49 @@ +Owner: CN=Chambers of Commerce Root - 2008, O=AC Camerfirma S.A., SERIALNUMBER=A82743287, L=Madrid (see current address at www.camerfirma.com/address), C=EU +Issuer: CN=Chambers of Commerce Root - 2008, O=AC Camerfirma S.A., SERIALNUMBER=A82743287, L=Madrid (see current address at www.camerfirma.com/address), C=EU +Serial number: a3da427ea4b1aeda +Valid from: Fri Aug 01 12:29:50 GMT 2008 until: Sat Jul 31 12:29:50 GMT 2038 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIHTzCCBTegAwIBAgIJAKPaQn6ksa7aMA0GCSqGSIb3DQEBBQUAMIGuMQswCQYD +VQQGEwJFVTFDMEEGA1UEBxM6TWFkcmlkIChzZWUgY3VycmVudCBhZGRyZXNzIGF0 +IHd3dy5jYW1lcmZpcm1hLmNvbS9hZGRyZXNzKTESMBAGA1UEBRMJQTgyNzQzMjg3 +MRswGQYDVQQKExJBQyBDYW1lcmZpcm1hIFMuQS4xKTAnBgNVBAMTIENoYW1iZXJz +IG9mIENvbW1lcmNlIFJvb3QgLSAyMDA4MB4XDTA4MDgwMTEyMjk1MFoXDTM4MDcz +MTEyMjk1MFowga4xCzAJBgNVBAYTAkVVMUMwQQYDVQQHEzpNYWRyaWQgKHNlZSBj +dXJyZW50IGFkZHJlc3MgYXQgd3d3LmNhbWVyZmlybWEuY29tL2FkZHJlc3MpMRIw +EAYDVQQFEwlBODI3NDMyODcxGzAZBgNVBAoTEkFDIENhbWVyZmlybWEgUy5BLjEp +MCcGA1UEAxMgQ2hhbWJlcnMgb2YgQ29tbWVyY2UgUm9vdCAtIDIwMDgwggIiMA0G +CSqGSIb3DQEBAQUAA4ICDwAwggIKAoICAQCvAMtwNyuAWko6bHiUfaN/Gh/2NdW9 +28sNRHI+JrKQUrpjOyhYb6WzbZSm891kDFX29ufyIiKAXuFixrYp4YFs8r/lfTJq +VKAyGVn+H4vXPWCGhSRv4xGzdz4gljUha7MI2XAuZPeEklPWDrCQiorjh40G072Q +DuKZoRuGDtqaCrsLYVAGUvGef3bsyw/QHg3PmTA9HMRFEFis1tPo1+XqxQEHd9ZR +5gN/ikilTWh1uem8nk4ZcfUyS5xtYBkL+8ydddy/Js2Pk3g5eXNeJQ7KXOt3EgfL +ZEFHcpOrUMPrCXZkNNI5t3YRCQ12RcSprj1qr7V9ZS+UWBDsXHyvfuK2GNnQm05a +Sd+pZgvMPMZ4fKecHePOjlO+Bd5gD2vlGts/4+EhySnB8esHnFIbAURRPHsl18Tl +UlRdJQfKFiC4reRB7noI/plvg6aRArBsNlVq5331lubKgdaX8ZSD6e2wsWsSaR6s ++12pxZjptFtYer49okQ6Y1nUCyXeG0+95QGezdIp1Z8XGQpvvwyQ0wlf2eOKNcx5 +Wk0ZN5K3xMGtr/R5JJqyAQuxr1yW84Ay+1w9mPGgP0revq+ULtlVmhduYJ1jbLhj +ya6BXBg14JC7vjxPNyK5fuvPnnchpj04gftI2jE9K+OJ9dC1vX7gUMQSibMjmhAx +hduub+84Mxh2EQIDAQABo4IBbDCCAWgwEgYDVR0TAQH/BAgwBgEB/wIBDDAdBgNV +HQ4EFgQU+SSsD7K1+HnA+mCIG8TZTQKeFxkwgeMGA1UdIwSB2zCB2IAU+SSsD7K1 ++HnA+mCIG8TZTQKeFxmhgbSkgbEwga4xCzAJBgNVBAYTAkVVMUMwQQYDVQQHEzpN +YWRyaWQgKHNlZSBjdXJyZW50IGFkZHJlc3MgYXQgd3d3LmNhbWVyZmlybWEuY29t +L2FkZHJlc3MpMRIwEAYDVQQFEwlBODI3NDMyODcxGzAZBgNVBAoTEkFDIENhbWVy +ZmlybWEgUy5BLjEpMCcGA1UEAxMgQ2hhbWJlcnMgb2YgQ29tbWVyY2UgUm9vdCAt +IDIwMDiCCQCj2kJ+pLGu2jAOBgNVHQ8BAf8EBAMCAQYwPQYDVR0gBDYwNDAyBgRV +HSAAMCowKAYIKwYBBQUHAgEWHGh0dHA6Ly9wb2xpY3kuY2FtZXJmaXJtYS5jb20w +DQYJKoZIhvcNAQEFBQADggIBAJASryI1wqM58C7e6bXpeHxIvj99RZJe6dqxGfwW +PJ+0W2aeaufDuV2I6A+tzyMP3iU6XsxPpcG1Lawk0lgH3qLPaYRgM+gQDROpI9CF +5Y57pp49chNyM/WqfcZjHwj0/gF/JM8rLFQJ3uIrbZLGOU8W6jx+ekbURWpGqOt1 +glanq6B8aBMz9p0w8G8nOSQjKpD9kCk18pPfNKXG9/jvjA9iSnyu0/VU+I22mlaH +FoI6M6taIgj3grrqLuBHmrS1RaMFO9ncLkVAO+rcf+g769HsJtg1pDDFOqxXnrN2 +pSB7+R5KBWIBpih1YJeSDW4+TTdDDZIVnBgizVGZoCkaPF+KMjNbMMeJL0eYD6MD +xvbxrN8y8NmBGuScvfaAFPDRLLmF9dijscilIeUcE5fuDr3fKanvNFNb0+RqE4QG +tjICxFKuItLcsiFCGtpA8CnJ7AoMXOLQusxI0zcKzBIKinmwPQN/aUv0NCB9szTq +jktk9T79syNnFQ0EuPAtwQlRPLJsFfClI9eDdOTlLsn+mCdCxqvGnrDQWzilm1De +fhiYtUU79nm06PcaewaD+9CL2rvHvRirCG88gGtAPxkZumWK5r7VXNM21+9AUiRg +OGcEMeyP84LG3rlV8zsxkVrctQgVrXYlCg17LofiDKYGvCYQbTed7N14jHyAxfDZ +d0jQ +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/camerfirmachamberscommerceca b/make/data/cacerts/camerfirmachamberscommerceca new file mode 100644 index 0000000..b92255f --- /dev/null +++ b/make/data/cacerts/camerfirmachamberscommerceca
@@ -0,0 +1,35 @@ +Owner: CN=Chambers of Commerce Root, OU=http://www.chambersign.org, O=AC Camerfirma SA CIF A82743287, C=EU +Issuer: CN=Chambers of Commerce Root, OU=http://www.chambersign.org, O=AC Camerfirma SA CIF A82743287, C=EU +Serial number: 0 +Valid from: Tue Sep 30 16:13:43 GMT 2003 until: Wed Sep 30 16:13:44 GMT 2037 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEvTCCA6WgAwIBAgIBADANBgkqhkiG9w0BAQUFADB/MQswCQYDVQQGEwJFVTEn +MCUGA1UEChMeQUMgQ2FtZXJmaXJtYSBTQSBDSUYgQTgyNzQzMjg3MSMwIQYDVQQL +ExpodHRwOi8vd3d3LmNoYW1iZXJzaWduLm9yZzEiMCAGA1UEAxMZQ2hhbWJlcnMg +b2YgQ29tbWVyY2UgUm9vdDAeFw0wMzA5MzAxNjEzNDNaFw0zNzA5MzAxNjEzNDRa +MH8xCzAJBgNVBAYTAkVVMScwJQYDVQQKEx5BQyBDYW1lcmZpcm1hIFNBIENJRiBB +ODI3NDMyODcxIzAhBgNVBAsTGmh0dHA6Ly93d3cuY2hhbWJlcnNpZ24ub3JnMSIw +IAYDVQQDExlDaGFtYmVycyBvZiBDb21tZXJjZSBSb290MIIBIDANBgkqhkiG9w0B +AQEFAAOCAQ0AMIIBCAKCAQEAtzZV5aVdGDDg2olUkfzIx1L4L1DZ77F1c2VHfRtb +unXF/KGIJPov7coISjlUxFF6tdpg6jg8gbLL8bvZkSM/SAFwdakFKq0fcfPJVD0d +BmpAPrMMhe5cG3nCYsS4No41XQEMIwRHNaqbYE6gZj3LJgqcQKH0XZi/caulAGgq +7YN6D6IUtdQis4CwPAxaUWktWBiP7Zme8a7ileb2R6jWDA+wWFjbw2Y3npuRVDM3 +0pQcakjJyfKl2qUMI/cjDpwyVV5xnIQFUZot/eZOKjRa3spAN2cMVCFVd9oKDMyX +roDclDZK9D7ONhMeU+SsTjoF7Nuucpw4i9A5O4kKPnf+dQIBA6OCAUQwggFAMBIG +A1UdEwEB/wQIMAYBAf8CAQwwPAYDVR0fBDUwMzAxoC+gLYYraHR0cDovL2NybC5j +aGFtYmVyc2lnbi5vcmcvY2hhbWJlcnNyb290LmNybDAdBgNVHQ4EFgQU45T1sU3p +26EpW1eLTXYGduHRooowDgYDVR0PAQH/BAQDAgEGMBEGCWCGSAGG+EIBAQQEAwIA +BzAnBgNVHREEIDAegRxjaGFtYmVyc3Jvb3RAY2hhbWJlcnNpZ24ub3JnMCcGA1Ud +EgQgMB6BHGNoYW1iZXJzcm9vdEBjaGFtYmVyc2lnbi5vcmcwWAYDVR0gBFEwTzBN +BgsrBgEEAYGHLgoDATA+MDwGCCsGAQUFBwIBFjBodHRwOi8vY3BzLmNoYW1iZXJz +aWduLm9yZy9jcHMvY2hhbWJlcnNyb290Lmh0bWwwDQYJKoZIhvcNAQEFBQADggEB +AAxBl8IahsAifJ/7kPMa0QOx7xP5IV8EnNrJpY0nbJaHkb5BkAFyk+cefV/2icZd +p0AJPaxJRUXcLo0waLIJuvvDL8y6C98/d3tGfToSJI6WjzwFCm/SlCgdbQzALogi +1djPHRPH8EjX1wWnz8dHnjs8NMiAT9QUu/wNUPf6s+xCX6ndbcj0dc97wXImsQEc +XCz9ek60AcUFV7nnPKoF2YjpB0ZBzu9Bga5Y34OirsrXdx/nADydb47kMgkdTXg0 +eDQ8lJsm7U9xxhl6vSAiSFr+S30Dt+dYvsYyTnQeaN2oaFuzPu5ifdmA6Ap1erfu +tGWaIZDgqtCYvDi1czyL+Nw= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/camerfirmachambersignca b/make/data/cacerts/camerfirmachambersignca new file mode 100644 index 0000000..935eea9 --- /dev/null +++ b/make/data/cacerts/camerfirmachambersignca
@@ -0,0 +1,48 @@ +Owner: CN=Global Chambersign Root - 2008, O=AC Camerfirma S.A., SERIALNUMBER=A82743287, L=Madrid (see current address at www.camerfirma.com/address), C=EU +Issuer: CN=Global Chambersign Root - 2008, O=AC Camerfirma S.A., SERIALNUMBER=A82743287, L=Madrid (see current address at www.camerfirma.com/address), C=EU +Serial number: c9cdd3e9d57d23ce +Valid from: Fri Aug 01 12:31:40 GMT 2008 until: Sat Jul 31 12:31:40 GMT 2038 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIHSTCCBTGgAwIBAgIJAMnN0+nVfSPOMA0GCSqGSIb3DQEBBQUAMIGsMQswCQYD +VQQGEwJFVTFDMEEGA1UEBxM6TWFkcmlkIChzZWUgY3VycmVudCBhZGRyZXNzIGF0 +IHd3dy5jYW1lcmZpcm1hLmNvbS9hZGRyZXNzKTESMBAGA1UEBRMJQTgyNzQzMjg3 +MRswGQYDVQQKExJBQyBDYW1lcmZpcm1hIFMuQS4xJzAlBgNVBAMTHkdsb2JhbCBD +aGFtYmVyc2lnbiBSb290IC0gMjAwODAeFw0wODA4MDExMjMxNDBaFw0zODA3MzEx +MjMxNDBaMIGsMQswCQYDVQQGEwJFVTFDMEEGA1UEBxM6TWFkcmlkIChzZWUgY3Vy +cmVudCBhZGRyZXNzIGF0IHd3dy5jYW1lcmZpcm1hLmNvbS9hZGRyZXNzKTESMBAG +A1UEBRMJQTgyNzQzMjg3MRswGQYDVQQKExJBQyBDYW1lcmZpcm1hIFMuQS4xJzAl +BgNVBAMTHkdsb2JhbCBDaGFtYmVyc2lnbiBSb290IC0gMjAwODCCAiIwDQYJKoZI +hvcNAQEBBQADggIPADCCAgoCggIBAMDfVtPkOpt2RbQT2//BthmLN0EYlVJH6xed +KYiONWwGMi5HYvNJBL99RDaxccy9Wglz1dmFRP+RVyXfXjaOcNFccUMd2drvXNL7 +G706tcuto8xEpw2uIRU/uXpbknXYpBI4iRmKt4DS4jJvVpyR1ogQC7N0ZJJ0YPP2 +zxhPYLIj0Mc7zmFLmY/CDNBAspjcDahOo7kKrmCgrUVSY7pmvWjg+b4aqIG7HkF4 +ddPB/gBVsIdU6CeQNR1MM62X/JcumIS/LMmjv9GYERTtY/jKmIhYF5ntRQOXfjyG +HoiMvvKRhI9lNNgATH23MRdaKXoKGCQwoze1eqkBfSbW+Q6OWfH9GzO1KTsXO0G2 +Id3UwD2ln58fQ1DJu7xsepeY7s2MH/ucUa6LcL0nn3HAa6x9kGbo1106DbDVwo3V +yJ2dwW3Q0L9R5OP4wzg2rtandeavhENdk5IMagfeOx2YItaswTXbo6Al/3K1dh3e +beksZixShNBFks4c5eUzHdwHU1SjqoI7mjcv3N2gZOnm3b2u/GSFHTynyQbehP9r +6GsaPMWis0L7iwk+XwhSx2LE1AVxv8Rk5Pihg+g+EpuoHtQ2TS9x9o0o9oOpE9Jh +wZG7SMA0j0GMS0zbaRL/UJScIINZc+18ofLx/d33SdNDWKBWY8o9PeU1VlnpDsog +zCtLkykPAgMBAAGjggFqMIIBZjASBgNVHRMBAf8ECDAGAQH/AgEMMB0GA1UdDgQW +BBS5CcqcHtvTbDprru1U8VuTBjUuXjCB4QYDVR0jBIHZMIHWgBS5CcqcHtvTbDpr +ru1U8VuTBjUuXqGBsqSBrzCBrDELMAkGA1UEBhMCRVUxQzBBBgNVBAcTOk1hZHJp +ZCAoc2VlIGN1cnJlbnQgYWRkcmVzcyBhdCB3d3cuY2FtZXJmaXJtYS5jb20vYWRk +cmVzcykxEjAQBgNVBAUTCUE4Mjc0MzI4NzEbMBkGA1UEChMSQUMgQ2FtZXJmaXJt +YSBTLkEuMScwJQYDVQQDEx5HbG9iYWwgQ2hhbWJlcnNpZ24gUm9vdCAtIDIwMDiC +CQDJzdPp1X0jzjAOBgNVHQ8BAf8EBAMCAQYwPQYDVR0gBDYwNDAyBgRVHSAAMCow +KAYIKwYBBQUHAgEWHGh0dHA6Ly9wb2xpY3kuY2FtZXJmaXJtYS5jb20wDQYJKoZI +hvcNAQEFBQADggIBAICIf3DekijZBZRG/5BXqfEv3xoNa/p8DhxJJHkn2EaqbylZ +UohwEurdPfWbU1Rv4WCiqAm57OtZfMY18dwY6fFn5a+6ReAJ3spED8IXDneRRXoz +X1+WLGiLwUePmJs9wOzL9dWCkoQ10b42OFZyMVtHLaoXpGNR6woBrX/sdZ7LoR/x +fxKxueRkf2fWIyr0uDldmOghp+G9PUIadJpwr2hsUF1Jz//7Dl3mLEfXgTpZALVz +a2Mg9jFFCDkO9HB+QHBaP9BrQql0PSgvAm11cpUJjUhjxsYjV5KTXjXBjfkK9yyd +Yhz2rXzdpjEetrHHfoUm+qRqtdpjMNHvkzeyZi99Bffnt0uYlDXA2TopwZ2yUDMd +SqlapskD7+3056huirRXhOukP9DuqqqHW2Pok+JrqNS4cnhrG+055F3Lm6qH1U9O +AP7Zap88MQ8oAgF9mOinsKJknnn4SPIVqczmyETrP3iZ8ntxPjzxmKfFGBI/5rso +M0LpRQp8bfKGeS/Fghl9CYl8slR2iK7ewfPM4W7bMdaTrpmg7yVqc5iJWzouE4ge +v8CSlDQb4ye3ix5vQv/n6TebUB0tovkC7stYWDpxvGjjqsGvHCgfotwjZT+B6q6Z +09gwzxMNTxXJhLynSC34MCN32EZLeW32jO06f2ARePTpm67VVMB0gNELQp/B +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/certumca b/make/data/cacerts/certumca new file mode 100644 index 0000000..4149653 --- /dev/null +++ b/make/data/cacerts/certumca
@@ -0,0 +1,26 @@ +Owner: CN=Certum CA, O=Unizeto Sp. z o.o., C=PL +Issuer: CN=Certum CA, O=Unizeto Sp. z o.o., C=PL +Serial number: 10020 +Valid from: Tue Jun 11 10:46:39 GMT 2002 until: Fri Jun 11 10:46:39 GMT 2027 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDDDCCAfSgAwIBAgIDAQAgMA0GCSqGSIb3DQEBBQUAMD4xCzAJBgNVBAYTAlBM +MRswGQYDVQQKExJVbml6ZXRvIFNwLiB6IG8uby4xEjAQBgNVBAMTCUNlcnR1bSBD +QTAeFw0wMjA2MTExMDQ2MzlaFw0yNzA2MTExMDQ2MzlaMD4xCzAJBgNVBAYTAlBM +MRswGQYDVQQKExJVbml6ZXRvIFNwLiB6IG8uby4xEjAQBgNVBAMTCUNlcnR1bSBD +QTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAM6xwS7TT3zNJc4YPk/E +jG+AanPIW1H4m9LcuwBcsaD8dQPugfCI7iNS6eYVM42sLQnFdvkrOYCJ5JdLkKWo +ePhzQ3ukYbDYWMzhbGZ+nPMJXlVjhNWo7/OxLjBos8Q82KxujZlakE403Daaj4GI +ULdtlkIJ89eVgw1BS7Bqa/j8D35in2fE7SZfECYPCE/wpFcozo+47UX2bu4lXapu +Ob7kky/ZR6By6/qmW6/KUz/iDsaWVhFu9+lmqSbYf5VT7QqFiLpPKaVCjF62/IUg +AKpoC6EahQGcxEZjgoi2IrHu/qpGWX7PNSzVttpd90gzFFS269lvzs2I1qsb2pY7 +HVkCAwEAAaMTMBEwDwYDVR0TAQH/BAUwAwEB/zANBgkqhkiG9w0BAQUFAAOCAQEA +uI3O7+cUus/usESSbLQ5PqKEbq24IXfS1HeCh+YgQYHu4vgRt2PRFze+GXYkHAQa +TOs9qmdvLdTN/mUxcMUbpgIKumB7bVjCmkn+YzILa+M6wKyrO7Do0wlRjBCDxjTg +xSvgGrZgFCdsMneMvLJymM/NzD+5yCRCFNZX/OYmQ6kd5YCQzgNUKD73P9P4Te1q +CjqTE5s7FCMTY5w/0YcneeVMUeMBrYVdGjux1XMQpNPyvG5k9VpWkKjHDkx0Dy5x +O/fIR/RpbxXyEV6DHpx8Uq79AtoSqFlnGNu8cN2bsWntgM6JQEhqDjXKKWYVIZQs +6GAqm4VKQPNriiTsBhYscw== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/certumtrustednetworkca b/make/data/cacerts/certumtrustednetworkca new file mode 100644 index 0000000..db35af8 --- /dev/null +++ b/make/data/cacerts/certumtrustednetworkca
@@ -0,0 +1,29 @@ +Owner: CN=Certum Trusted Network CA, OU=Certum Certification Authority, O=Unizeto Technologies S.A., C=PL +Issuer: CN=Certum Trusted Network CA, OU=Certum Certification Authority, O=Unizeto Technologies S.A., C=PL +Serial number: 444c0 +Valid from: Wed Oct 22 12:07:37 GMT 2008 until: Mon Dec 31 12:07:37 GMT 2029 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDuzCCAqOgAwIBAgIDBETAMA0GCSqGSIb3DQEBBQUAMH4xCzAJBgNVBAYTAlBM +MSIwIAYDVQQKExlVbml6ZXRvIFRlY2hub2xvZ2llcyBTLkEuMScwJQYDVQQLEx5D +ZXJ0dW0gQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkxIjAgBgNVBAMTGUNlcnR1bSBU +cnVzdGVkIE5ldHdvcmsgQ0EwHhcNMDgxMDIyMTIwNzM3WhcNMjkxMjMxMTIwNzM3 +WjB+MQswCQYDVQQGEwJQTDEiMCAGA1UEChMZVW5pemV0byBUZWNobm9sb2dpZXMg +Uy5BLjEnMCUGA1UECxMeQ2VydHVtIENlcnRpZmljYXRpb24gQXV0aG9yaXR5MSIw +IAYDVQQDExlDZXJ0dW0gVHJ1c3RlZCBOZXR3b3JrIENBMIIBIjANBgkqhkiG9w0B +AQEFAAOCAQ8AMIIBCgKCAQEA4/t9o3K6wvDJFIf1awFO4W5AB7ptJ11/91sts1rH +UV+rpDKmYYe2bg+G0jACl/jXaVehGDldamR5xgFZrDwxSjh80gTSSyjoIF87B6LM +TXPb865Px1bVWqeWifrzq2jUI4ZZJ88JJ7ysbnKDHDBy3+Ci6dLhdHUZvSqeexVU +BBvXQzmtVSjF4hq79MDkrjhJM8x2hZ85RdKknvISjFH4fOQtf/WsX+sWn7Et0brM +kUJ3TCXJkDhv2/DM+44el1k+1WBO5gUo7Ul5E0u6SNsv+XLTOcr+H9g0cvW0QM8x +AcPs3hEtF10fuFDRXhmnad4HMyjKUJX5p1TLVIZQRan5SQIDAQABo0IwQDAPBgNV +HRMBAf8EBTADAQH/MB0GA1UdDgQWBBQIds3LB/8k9sXN7buQvOKEN0Z19zAOBgNV +HQ8BAf8EBAMCAQYwDQYJKoZIhvcNAQEFBQADggEBAKaorSLOAT2mo/9i0Eidi15y +sHhE49wcrwn9I0j6vSrEuVUEtRCjjSfeC4Jj0O7eDDd5QVsisrCaQVymcODU0HfL +I9MA4GxWL+FpDQ3Zqr8hgVDZBqWo/5U30Kr+4rP1mS1FhIrlQgnXdAIv94nYmem8 +J9RHjboNRhx3zxSkHLmkMcScKHQDNP8zGSal6Q10tz6XxnboJ5ajZt3hrvJBW8qY +VoNzcOSGGtIxQbovvi0TWnZvTuhOgQ4/WwMioBK+ZlgRSssDxLQqKi2WF+A5VLxI +03YnnZotBqbJ7DnSq9ufmgsnAjUpsUCV5/nonFWIGUbWtzT1fs45mtk48VH3Tyw= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/chunghwaepkirootca b/make/data/cacerts/chunghwaepkirootca new file mode 100644 index 0000000..a755a44 --- /dev/null +++ b/make/data/cacerts/chunghwaepkirootca
@@ -0,0 +1,40 @@ +Owner: OU=ePKI Root Certification Authority, O="Chunghwa Telecom Co., Ltd.", C=TW +Issuer: OU=ePKI Root Certification Authority, O="Chunghwa Telecom Co., Ltd.", C=TW +Serial number: 15c8bd65475cafb897005ee406d2bc9d +Valid from: Mon Dec 20 02:31:27 GMT 2004 until: Wed Dec 20 02:31:27 GMT 2034 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFsDCCA5igAwIBAgIQFci9ZUdcr7iXAF7kBtK8nTANBgkqhkiG9w0BAQUFADBe +MQswCQYDVQQGEwJUVzEjMCEGA1UECgwaQ2h1bmdod2EgVGVsZWNvbSBDby4sIEx0 +ZC4xKjAoBgNVBAsMIWVQS0kgUm9vdCBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTAe +Fw0wNDEyMjAwMjMxMjdaFw0zNDEyMjAwMjMxMjdaMF4xCzAJBgNVBAYTAlRXMSMw +IQYDVQQKDBpDaHVuZ2h3YSBUZWxlY29tIENvLiwgTHRkLjEqMCgGA1UECwwhZVBL +SSBSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MIICIjANBgkqhkiG9w0BAQEF +AAOCAg8AMIICCgKCAgEA4SUP7o3biDN1Z82tH306Tm2d0y8U82N0ywEhajfqhFAH +SyZbCUNsIZ5qyNUD9WBpj8zwIuQf5/dqIjG3LBXy4P4AakP/h2XGtRrBp0xtInAh +ijHyl3SJCRImHJ7K2RKilTza6We/CKBk49ZCt0Xvl/T29de1ShUCWH2YWEtgvM3X +DZoTM1PRYfl61dd4s5oz9wCGzh1NlDivqOx4UXCKXBCDUSH3ET00hl7lSM2XgYI1 +TBnsZfZrxQWh7kcT1rMhJ5QQCtkkO7q+RBNGMD+XPNjX12ruOzjjK9SXDrkb5wdJ +fzcq+Xd4z1TtW0ado4AOkUPB1ltfFLqfpo0kR0BZv3I4sjZsN/+Z0V0OWQqraffA +sgRFelQArr5T9rXn4fg8ozHSqf4hUmTFpmfwdQcGlBSBVcYn5AGPF8Fqcde+S/uU +WH1+ETOxQvdibBjWzwloPn9s9h6PYq2lY9sJpx8iQkEeb5mKPtf5P0B6ebClAZLS +nT0IFaUQAS2zMnaolQ2zepr7BxB4EW/hj8e6DyUadCrlHJhBmd8hh+iVBmoKs2pH +dmX2Os+PYhcZewoozRrSgx4hxyy/vv9haLdnG7t4TY3OZ+XkwY63I2binZB1NJip +NiuKmpS5nezMirH4JYlcWrYvjB9teSSnUmjDhDXiZo1jDiVN1Rmy5nk3pyKdVDEC +AwEAAaNqMGgwHQYDVR0OBBYEFB4M97Zn8uGSJglFwFU5Lnc/QkqiMAwGA1UdEwQF +MAMBAf8wOQYEZyoHAAQxMC8wLQIBADAJBgUrDgMCGgUAMAcGBWcqAwAABBRFsMLH +ClZ87lt4DJX5GFPBphzYEDANBgkqhkiG9w0BAQUFAAOCAgEACbODU1kBPpVJufGB +uvl2ICO1J2B01GqZNF5sAFPZn/KmsSQHRGoqxqWOeBLoR9lYGxMqXnmbnwoqZ6Yl +PwZpVnPDimZI+ymBV3QGypzqKOg4ZyYr8dW1P2WT+DZdjo2NQCCHGervJ8A9tDkP +JXtoUHRVnAxZfVo9QZQlUgjgRywVMRnVvwdVxrsStZf0X4OFunHB2WyBEXYKCrC/ +gpf36j36+uwtqSiUO1bd0lEursC9CBWMd1I0ltabrNMdjmEPNXubrjlpC2JgQCA2 +j6/7Nu4tCEoduL+bXPjqpRugc6bY+G7gMwRfaKonh+3ZwZCc7b3jajWvY9+rGNm6 +5ulK6lCKD2GTHuItGeIwlDWSXQ62B68ZgI9HkFFLLk3dheLSClIKF5r8GrBQAuUB +o2M3IUxExJtRmREOc5wGj1QupyheRDmHVi03vYVElOEMSyycw5KFNGHLD7ibSkNS +/jQ6fbjpKdx2qcgw+BRxgMYeNkh0IkFch4LoGHGLQYlE535YW6i4jRPpp2zDR+2z +Gp1iro2C6pSe3VkQw63d4k3jMdXH7OjysP6SHhYKGvzZ8/gntsm+HbRsZJB/9OTE +W9c3rkIO3aQab3yIVMUWbuF6aC74Or8NpDyJO3inTmODBCEIZ43ygknQW/2xzQ+D +hNQ+IIX3Sj0rnP0qCglN6oH4EZw= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/comodoaaaca b/make/data/cacerts/comodoaaaca new file mode 100644 index 0000000..76fc7fc --- /dev/null +++ b/make/data/cacerts/comodoaaaca
@@ -0,0 +1,32 @@ +Owner: CN=AAA Certificate Services, O=Comodo CA Limited, L=Salford, ST=Greater Manchester, C=GB +Issuer: CN=AAA Certificate Services, O=Comodo CA Limited, L=Salford, ST=Greater Manchester, C=GB +Serial number: 1 +Valid from: Thu Jan 01 00:00:00 GMT 2004 until: Sun Dec 31 23:59:59 GMT 2028 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEMjCCAxqgAwIBAgIBATANBgkqhkiG9w0BAQUFADB7MQswCQYDVQQGEwJHQjEb +MBkGA1UECAwSR3JlYXRlciBNYW5jaGVzdGVyMRAwDgYDVQQHDAdTYWxmb3JkMRow +GAYDVQQKDBFDb21vZG8gQ0EgTGltaXRlZDEhMB8GA1UEAwwYQUFBIENlcnRpZmlj +YXRlIFNlcnZpY2VzMB4XDTA0MDEwMTAwMDAwMFoXDTI4MTIzMTIzNTk1OVowezEL +MAkGA1UEBhMCR0IxGzAZBgNVBAgMEkdyZWF0ZXIgTWFuY2hlc3RlcjEQMA4GA1UE +BwwHU2FsZm9yZDEaMBgGA1UECgwRQ29tb2RvIENBIExpbWl0ZWQxITAfBgNVBAMM +GEFBQSBDZXJ0aWZpY2F0ZSBTZXJ2aWNlczCCASIwDQYJKoZIhvcNAQEBBQADggEP +ADCCAQoCggEBAL5AnfRu4ep2hxxNRUSOvkbIgwadwSr+GB+O5AL686tdUIoWMQua +BtDFcCLNSS1UY8y2bmhGC1Pqy0wkwLxyTurxFa70VJoSCsN6sjNg4tqJVfMiWPPe +3M/vg4aijJRPn2jymJBGhCfHdr/jzDUsi14HZGWCwEiwqJH5YZ92IFCokcdmtet4 +YgNW8IoaE+oxox6gmf049vYnMlhvB/VruPsUK6+3qszWY19zjNoFmag4qMsXeDZR +rOme9Hg6jc8P2ULimAyrL58OAd7vn5lJ8S3frHRNG5i1R8XlKdH5kBjHYpy+g8cm +ez6KJcfA3Z3mNWgQIJ2P2N7Sw4ScDV7oL8kCAwEAAaOBwDCBvTAdBgNVHQ4EFgQU +oBEKIz6W8Qfs4q8p74Klf9AwpLQwDgYDVR0PAQH/BAQDAgEGMA8GA1UdEwEB/wQF +MAMBAf8wewYDVR0fBHQwcjA4oDagNIYyaHR0cDovL2NybC5jb21vZG9jYS5jb20v +QUFBQ2VydGlmaWNhdGVTZXJ2aWNlcy5jcmwwNqA0oDKGMGh0dHA6Ly9jcmwuY29t +b2RvLm5ldC9BQUFDZXJ0aWZpY2F0ZVNlcnZpY2VzLmNybDANBgkqhkiG9w0BAQUF +AAOCAQEACFb8AvCb6P+k+tZ7xkSAzk/ExfYAWMymtrwUSWgEdujm7l3sAg9g1o1Q +GE8mTgHj5rCl7r+8dFRBv/38ErjHT1r0iWAFf2C3BUrz9vHCv8S5dIa2LX1rzNLz +Rt0vxuBqw8M0Ayx9lt1awg6nCpnBBYurDC/zXDrPbDdVCYfeU0BsWO/8tqtlbgT2 +G9w84FoVxp7Z8VlIMCFlA2zs6SFz7JsDoeA3raAVGI/6ugLOpyypEBMs1OUIJqsi +l2D4kF501KKaU73yqWjgom7C12yxow+ev+to51byrvLjKzg6CYG1a4XXvi3tPxq3 +smPi9WIsgtRqAEFQ8TmDn5XpNpaYbg== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/comodoeccca b/make/data/cacerts/comodoeccca new file mode 100644 index 0000000..19f9f0b --- /dev/null +++ b/make/data/cacerts/comodoeccca
@@ -0,0 +1,23 @@ +Owner: CN=COMODO ECC Certification Authority, O=COMODO CA Limited, L=Salford, ST=Greater Manchester, C=GB +Issuer: CN=COMODO ECC Certification Authority, O=COMODO CA Limited, L=Salford, ST=Greater Manchester, C=GB +Serial number: 1f47afaa62007050544c019e9b63992a +Valid from: Thu Mar 06 00:00:00 GMT 2008 until: Mon Jan 18 23:59:59 GMT 2038 +Signature algorithm name: SHA384withECDSA +Subject Public Key Algorithm: 384-bit EC (secp384r1) key +Version: 3 +-----BEGIN CERTIFICATE----- +MIICiTCCAg+gAwIBAgIQH0evqmIAcFBUTAGem2OZKjAKBggqhkjOPQQDAzCBhTEL +MAkGA1UEBhMCR0IxGzAZBgNVBAgTEkdyZWF0ZXIgTWFuY2hlc3RlcjEQMA4GA1UE +BxMHU2FsZm9yZDEaMBgGA1UEChMRQ09NT0RPIENBIExpbWl0ZWQxKzApBgNVBAMT +IkNPTU9ETyBFQ0MgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkwHhcNMDgwMzA2MDAw +MDAwWhcNMzgwMTE4MjM1OTU5WjCBhTELMAkGA1UEBhMCR0IxGzAZBgNVBAgTEkdy +ZWF0ZXIgTWFuY2hlc3RlcjEQMA4GA1UEBxMHU2FsZm9yZDEaMBgGA1UEChMRQ09N +T0RPIENBIExpbWl0ZWQxKzApBgNVBAMTIkNPTU9ETyBFQ0MgQ2VydGlmaWNhdGlv +biBBdXRob3JpdHkwdjAQBgcqhkjOPQIBBgUrgQQAIgNiAAQDR3svdcmCFYX7deSR +FtSrYpn1PlILBs5BAH+X4QokPB0BBO490o0JlwzgdeT6+3eKKvUDYEs2ixYjFq0J +cfRK9ChQtP6IHG4/bC8vCVlbpVsLM5niwz2J+Wos77LTBumjQjBAMB0GA1UdDgQW +BBR1cacZSBm8nZ3qQUfflMRId5nTeTAOBgNVHQ8BAf8EBAMCAQYwDwYDVR0TAQH/ +BAUwAwEB/zAKBggqhkjOPQQDAwNoADBlAjEA7wNbeqy3eApyt4jf/7VGFAkK+qDm +fQjGGoe9GKhzvSbKYAydzpmfz1wPMOG+FDHqAjAU9JM8SaczepBGR7NjfRObTrdv +GDeAU/7dIOA1mjbRxwG55tzd8/8dLDoWV9mSOdY= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/comodorsaca b/make/data/cacerts/comodorsaca new file mode 100644 index 0000000..f396f6d --- /dev/null +++ b/make/data/cacerts/comodorsaca
@@ -0,0 +1,41 @@ +Owner: CN=COMODO RSA Certification Authority, O=COMODO CA Limited, L=Salford, ST=Greater Manchester, C=GB +Issuer: CN=COMODO RSA Certification Authority, O=COMODO CA Limited, L=Salford, ST=Greater Manchester, C=GB +Serial number: 4caaf9cadb636fe01ff74ed85b03869d +Valid from: Tue Jan 19 00:00:00 GMT 2010 until: Mon Jan 18 23:59:59 GMT 2038 +Signature algorithm name: SHA384withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIF2DCCA8CgAwIBAgIQTKr5yttjb+Af907YWwOGnTANBgkqhkiG9w0BAQwFADCB +hTELMAkGA1UEBhMCR0IxGzAZBgNVBAgTEkdyZWF0ZXIgTWFuY2hlc3RlcjEQMA4G +A1UEBxMHU2FsZm9yZDEaMBgGA1UEChMRQ09NT0RPIENBIExpbWl0ZWQxKzApBgNV +BAMTIkNPTU9ETyBSU0EgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkwHhcNMTAwMTE5 +MDAwMDAwWhcNMzgwMTE4MjM1OTU5WjCBhTELMAkGA1UEBhMCR0IxGzAZBgNVBAgT +EkdyZWF0ZXIgTWFuY2hlc3RlcjEQMA4GA1UEBxMHU2FsZm9yZDEaMBgGA1UEChMR +Q09NT0RPIENBIExpbWl0ZWQxKzApBgNVBAMTIkNPTU9ETyBSU0EgQ2VydGlmaWNh +dGlvbiBBdXRob3JpdHkwggIiMA0GCSqGSIb3DQEBAQUAA4ICDwAwggIKAoICAQCR +6FSS0gpWsawNJN3Fz0RndJkrN6N9I3AAcbxT38T6KhKPS38QVr2fcHK3YX/JSw8X +pz3jsARh7v8Rl8f0hj4K+j5c+ZPmNHrZFGvnnLOFoIJ6dq9xkNfs/Q36nGz637CC +9BR++b7Epi9Pf5l/tfxnQ3K9DADWietrLNPtj5gcFKt+5eNu/Nio5JIk2kNrYrhV +/erBvGy2i/MOjZrkm2xpmfh4SDBF1a3hDTxFYPwyllEnvGfDyi62a+pGx8cgoLEf +Zd5ICLqkTqnyg0Y3hOvozIFIQ2dOciqbXL1MGyiKXCJ7tKuY2e7gUYPDCUZObT6Z ++pUX2nwzV0E8jVHtC7ZcryxjGt9XyD+86V3Em69FmeKjWiS0uqlWPc9vqv9JWL7w +qP/0uK3pN/u6uPQLOvnoQ0IeidiEyxPx2bvhiWC4jChWrBQdnArncevPDt09qZah +SL0896+1DSJMwBGB7FY79tOi4lu3sgQiUpWAk2nojkxl8ZEDLXB0AuqLZxUpaVIC +u9ffUGpVRr+goyhhf3DQw6KqLCGqR84onAZFdr+CGCe01a60y1Dma/RMhnEw6abf +Fobg2P9A3fvQQoh/ozM6LlweQRGBY84YcWsr7KaKtzFcOmpH4MN5WdYgGq/yapiq +crxXStJLnbsQ/LBMQeXtHT1eKJ2czL+zUdqnR+WEUwIDAQABo0IwQDAdBgNVHQ4E +FgQUu69+Aj36pvE8hI6t7jiY7NkyMtQwDgYDVR0PAQH/BAQDAgEGMA8GA1UdEwEB +/wQFMAMBAf8wDQYJKoZIhvcNAQEMBQADggIBAArx1UaEt65Ru2yyTUEUAJNMnMvl +wFTPoCWOAvn9sKIN9SCYPBMtrFaisNZ+EZLpLrqeLppysb0ZRGxhNaKatBYSaVqM +4dc+pBroLwP0rmEdEBsqpIt6xf4FpuHA1sj+nq6PK7o9mfjYcwlYRm6mnPTXJ9OV +2jeDchzTc+CiR5kDOF3VSXkAKRzH7JsgHAckaVd4sjn8OoSgtZx8jb8uk2Intzna +FxiuvTwJaP+EmzzV1gsD41eeFPfR60/IvYcjt7ZJQ3mFXLrrkguhxuhoqEwWsRqZ +CuhTLJK7oQkYdQxlqHvLI7cawiiFwxv/0Cti76R7CZGYZ4wUAc1oBmpjIXUDgIiK +boHGhfKppC3n9KUkEEeDys30jXlYsQab5xoq2Z0B15R97QNKyvDb6KkBPvVWmcke +jkk9u+UJueBPSZI9FoJAzMxZxuY67RIuaTxslbH9qh17f4a+Hg4yRvv7E491f0yL +S0Zj/gA0QHDBw7mh3aZw4gSzQbzpgJHqZJx64SIDqZxubw5lT2yHh17zbqD5daWb +QOhTsiedSrnAdyGN/4fy3ryM7xfft0kL0fJuMAsaDk527RH89elWsn2/x20Kk4yl +0MC2Hb46TpSi125sC8KKfPog88Tk5c0NqMuRkrF8hey1FGlmDoLnzc7ILaZRfyHB +NVOFBkpdn627G190 +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/digicertassuredidg2 b/make/data/cacerts/digicertassuredidg2 new file mode 100644 index 0000000..8b53c2c --- /dev/null +++ b/make/data/cacerts/digicertassuredidg2
@@ -0,0 +1,29 @@ +Owner: CN=DigiCert Assured ID Root G2, OU=www.digicert.com, O=DigiCert Inc, C=US +Issuer: CN=DigiCert Assured ID Root G2, OU=www.digicert.com, O=DigiCert Inc, C=US +Serial number: b931c3ad63967ea6723bfc3af9af44b +Valid from: Thu Aug 01 12:00:00 GMT 2013 until: Fri Jan 15 12:00:00 GMT 2038 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDljCCAn6gAwIBAgIQC5McOtY5Z+pnI7/Dr5r0SzANBgkqhkiG9w0BAQsFADBl +MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3 +d3cuZGlnaWNlcnQuY29tMSQwIgYDVQQDExtEaWdpQ2VydCBBc3N1cmVkIElEIFJv +b3QgRzIwHhcNMTMwODAxMTIwMDAwWhcNMzgwMTE1MTIwMDAwWjBlMQswCQYDVQQG +EwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3d3cuZGlnaWNl +cnQuY29tMSQwIgYDVQQDExtEaWdpQ2VydCBBc3N1cmVkIElEIFJvb3QgRzIwggEi +MA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDZ5ygvUj82ckmIkzTz+GoeMVSA +n61UQbVH35ao1K+ALbkKz3X9iaV9JPrjIgwrvJUXCzO/GU1BBpAAvQxNEP4Htecc +biJVMWWXvdMX0h5i89vqbFCMP4QMls+3ywPgym2hFEwbid3tALBSfK+RbLE4E9Hp +EgjAALAcKxHad3A2m67OeYfcgnDmCXRwVWmvo2ifv922ebPynXApVfSr/5Vh88lA +bx3RvpO704gqu52/clpWcTs/1PPRCv4o76Pu2ZmvA9OPYLfykqGxvYmJHzDNw6Yu +YjOuFgJ3RFrngQo8p0Quebg/BLxcoIfhG69Rjs3sLPr4/m3wOnyqi+RnlTGNAgMB +AAGjQjBAMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQDAgGGMB0GA1UdDgQW +BBTOw0q5mVXyuNtgv6l+vVa1lzan1jANBgkqhkiG9w0BAQsFAAOCAQEAyqVVjOPI +QW5pJ6d1Ee88hjZv0p3GeDgdaZaikmkuOGybfQTUiaWxMTeKySHMq2zNixya1r9I +0jJmwYrA8y8678Dj1JGG0VDjA9tzd29KOVPt3ibHtX2vK0LRdWLjSisCx1BL4Gni +lmwORGYQRI+tBev4eaymG+g3NJ1TyWGqolKvSnAWhsI6yLETcDbYz+70CjTVW0z9 +B5yiutkBclzzTcHdDrEcDcRjvq30FPuJ7KJBDkzMyFdA0G4Dqs0MjomZmWzwPDCv +ON9vvKO+KSAnq3T/EyJ43pdSVR6DtVQgA+6uwE9W3jfMw3+qBCe703e4YtsXfJwo +IhNzbM8m9Yop5w== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/digicertassuredidg3 b/make/data/cacerts/digicertassuredidg3 new file mode 100644 index 0000000..120e0a5 --- /dev/null +++ b/make/data/cacerts/digicertassuredidg3
@@ -0,0 +1,22 @@ +Owner: CN=DigiCert Assured ID Root G3, OU=www.digicert.com, O=DigiCert Inc, C=US +Issuer: CN=DigiCert Assured ID Root G3, OU=www.digicert.com, O=DigiCert Inc, C=US +Serial number: ba15afa1ddfa0b54944afcd24a06cec +Valid from: Thu Aug 01 12:00:00 GMT 2013 until: Fri Jan 15 12:00:00 GMT 2038 +Signature algorithm name: SHA384withECDSA +Subject Public Key Algorithm: 384-bit EC (secp384r1) key +Version: 3 +-----BEGIN CERTIFICATE----- +MIICRjCCAc2gAwIBAgIQC6Fa+h3foLVJRK/NJKBs7DAKBggqhkjOPQQDAzBlMQsw +CQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3d3cu +ZGlnaWNlcnQuY29tMSQwIgYDVQQDExtEaWdpQ2VydCBBc3N1cmVkIElEIFJvb3Qg +RzMwHhcNMTMwODAxMTIwMDAwWhcNMzgwMTE1MTIwMDAwWjBlMQswCQYDVQQGEwJV +UzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3d3cuZGlnaWNlcnQu +Y29tMSQwIgYDVQQDExtEaWdpQ2VydCBBc3N1cmVkIElEIFJvb3QgRzMwdjAQBgcq +hkjOPQIBBgUrgQQAIgNiAAQZ57ysRGXtzbg/WPuNsVepRC0FFfLvC/8QdJ+1YlJf +Zn4f5dwbRXkLzMZTCp2NXQLZqVneAlr2lSoOjThKiknGvMYDOAdfVdp+CW7if17Q +RSAPWXYQ1qAk8C3eNvJsKTmjQjBAMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/ +BAQDAgGGMB0GA1UdDgQWBBTL0L2p4ZgFUaFNN6KDec6NHSrkhDAKBggqhkjOPQQD +AwNnADBkAjAlpIFFAmsSS3V0T8gj43DydXLefInwz5FyYZ5eEJJZVrmDxxDnOOlY +JjZ91eQ0hjkCMHw2U/Aw5WJjOpnitqM7mzT6HtoQknFekROn3aRukswy1vUhZscv +6pZjamVFkpUBtA== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/digicertassuredidrootca b/make/data/cacerts/digicertassuredidrootca new file mode 100644 index 0000000..41edfc5 --- /dev/null +++ b/make/data/cacerts/digicertassuredidrootca
@@ -0,0 +1,29 @@ +Owner: CN=DigiCert Assured ID Root CA, OU=www.digicert.com, O=DigiCert Inc, C=US +Issuer: CN=DigiCert Assured ID Root CA, OU=www.digicert.com, O=DigiCert Inc, C=US +Serial number: ce7e0e517d846fe8fe560fc1bf03039 +Valid from: Fri Nov 10 00:00:00 GMT 2006 until: Mon Nov 10 00:00:00 GMT 2031 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDtzCCAp+gAwIBAgIQDOfg5RfYRv6P5WD8G/AwOTANBgkqhkiG9w0BAQUFADBl +MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3 +d3cuZGlnaWNlcnQuY29tMSQwIgYDVQQDExtEaWdpQ2VydCBBc3N1cmVkIElEIFJv +b3QgQ0EwHhcNMDYxMTEwMDAwMDAwWhcNMzExMTEwMDAwMDAwWjBlMQswCQYDVQQG +EwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3d3cuZGlnaWNl +cnQuY29tMSQwIgYDVQQDExtEaWdpQ2VydCBBc3N1cmVkIElEIFJvb3QgQ0EwggEi +MA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQCtDhXO5EOAXLGH87dg+XESpa7c +JpSIqvTO9SA5KFhgDPiA2qkVlTJhPLWxKISKityfCgyDF3qPkKyK53lTXDGEKvYP +mDI2dsze3Tyoou9q+yHyUmHfnyDXH+Kx2f4YZNISW1/5WBg1vEfNoTb5a3/UsDg+ +wRvDjDPZ2C8Y/igPs6eD1sNuRMBhNZYW/lmci3Zt1/GiSw0r/wty2p5g0I6QNcZ4 +VYcgoc/lbQrISXwxmDNsIumH0DJaoroTghHtORedmTpyoeb6pNnVFzF1roV9Iq4/ +AUaG9ih5yLHa5FcXxH4cDrC0kqZWs72yl+2qp/C3xag/lRbQ/6GW6whfGHdPAgMB +AAGjYzBhMA4GA1UdDwEB/wQEAwIBhjAPBgNVHRMBAf8EBTADAQH/MB0GA1UdDgQW +BBRF66Kv9JLLgjEtUYunpyGd823IDzAfBgNVHSMEGDAWgBRF66Kv9JLLgjEtUYun +pyGd823IDzANBgkqhkiG9w0BAQUFAAOCAQEAog683+Lt8ONyc3pklL/3cmbYMuRC +dWKuh+vy1dneVrOfzM4UKLkNl2BcEkxY5NM9g0lFWJc1aRqoR+pWxnmrEthngYTf +fwk8lOa4JiwgvT2zKIn3X/8i4peEH+ll74fg38FnSbNd67IJKusm7Xi+fT8r87cm +NW1fiQG2SVufAQWbqz0lwcy2f8Lxb4bG+mRo64EtlOtCt/qMHt1i8b5QZ7dsvfPx +H2sMNgcWfzd8qVttevESRmCD1ycEvkvOl77DZypoEd+A5wwzZr8TDRRu838fYxAe ++o0bJW1sj6W3YQGx0qMmoRBxna3iw/nDmVG3KwcIzi7mULKn+gpFL6Lw8g== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/digicertglobalrootca b/make/data/cacerts/digicertglobalrootca new file mode 100644 index 0000000..2838b8e --- /dev/null +++ b/make/data/cacerts/digicertglobalrootca
@@ -0,0 +1,29 @@ +Owner: CN=DigiCert Global Root CA, OU=www.digicert.com, O=DigiCert Inc, C=US +Issuer: CN=DigiCert Global Root CA, OU=www.digicert.com, O=DigiCert Inc, C=US +Serial number: 83be056904246b1a1756ac95991c74a +Valid from: Fri Nov 10 00:00:00 GMT 2006 until: Mon Nov 10 00:00:00 GMT 2031 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDrzCCApegAwIBAgIQCDvgVpBCRrGhdWrJWZHHSjANBgkqhkiG9w0BAQUFADBh +MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3 +d3cuZGlnaWNlcnQuY29tMSAwHgYDVQQDExdEaWdpQ2VydCBHbG9iYWwgUm9vdCBD +QTAeFw0wNjExMTAwMDAwMDBaFw0zMTExMTAwMDAwMDBaMGExCzAJBgNVBAYTAlVT +MRUwEwYDVQQKEwxEaWdpQ2VydCBJbmMxGTAXBgNVBAsTEHd3dy5kaWdpY2VydC5j +b20xIDAeBgNVBAMTF0RpZ2lDZXJ0IEdsb2JhbCBSb290IENBMIIBIjANBgkqhkiG +9w0BAQEFAAOCAQ8AMIIBCgKCAQEA4jvhEXLeqKTTo1eqUKKPC3eQyaKl7hLOllsB +CSDMAZOnTjC3U/dDxGkAV53ijSLdhwZAAIEJzs4bg7/fzTtxRuLWZscFs3YnFo97 +nh6Vfe63SKMI2tavegw5BmV/Sl0fvBf4q77uKNd0f3p4mVmFaG5cIzJLv07A6Fpt +43C/dxC//AH2hdmoRBBYMql1GNXRor5H4idq9Joz+EkIYIvUX7Q6hL+hqkpMfT7P +T19sdl6gSzeRntwi5m3OFBqOasv+zbMUZBfHWymeMr/y7vrTC0LUq7dBMtoM1O/4 +gdW7jVg/tRvoSSiicNoxBN33shbyTApOB6jtSj1etX+jkMOvJwIDAQABo2MwYTAO +BgNVHQ8BAf8EBAMCAYYwDwYDVR0TAQH/BAUwAwEB/zAdBgNVHQ4EFgQUA95QNVbR +TLtm8KPiGxvDl7I90VUwHwYDVR0jBBgwFoAUA95QNVbRTLtm8KPiGxvDl7I90VUw +DQYJKoZIhvcNAQEFBQADggEBAMucN6pIExIK+t1EnE9SsPTfrgT1eXkIoyQY/Esr +hMAtudXH/vTBH1jLuG2cenTnmCmrEbXjcKChzUyImZOMkXDiqw8cvpOp/2PV5Adg +06O/nVsJ8dWO41P0jmP6P6fbtGbfYmbW0W5BjfIttep3Sp+dWOIrWcBAI+0tKIJF +PnlUkiaY4IBIqDfv8NZ5YBberOgOzW6sRBc4L0na4UU+Krk2U886UAb3LujEV0ls +YSEY1QSteDwsOoBrp+uvFRTp2InBuThs4pFsiv9kuXclVzDAGySj4dzp30d8tbQk +CAUw7C29C79Fv1C5qfPrmAESrciIxpg0X40KPMbp1ZWVbd4= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/digicertglobalrootg2 b/make/data/cacerts/digicertglobalrootg2 new file mode 100644 index 0000000..99bc121 --- /dev/null +++ b/make/data/cacerts/digicertglobalrootg2
@@ -0,0 +1,29 @@ +Owner: CN=DigiCert Global Root G2, OU=www.digicert.com, O=DigiCert Inc, C=US +Issuer: CN=DigiCert Global Root G2, OU=www.digicert.com, O=DigiCert Inc, C=US +Serial number: 33af1e6a711a9a0bb2864b11d09fae5 +Valid from: Thu Aug 01 12:00:00 GMT 2013 until: Fri Jan 15 12:00:00 GMT 2038 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDjjCCAnagAwIBAgIQAzrx5qcRqaC7KGSxHQn65TANBgkqhkiG9w0BAQsFADBh +MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3 +d3cuZGlnaWNlcnQuY29tMSAwHgYDVQQDExdEaWdpQ2VydCBHbG9iYWwgUm9vdCBH +MjAeFw0xMzA4MDExMjAwMDBaFw0zODAxMTUxMjAwMDBaMGExCzAJBgNVBAYTAlVT +MRUwEwYDVQQKEwxEaWdpQ2VydCBJbmMxGTAXBgNVBAsTEHd3dy5kaWdpY2VydC5j +b20xIDAeBgNVBAMTF0RpZ2lDZXJ0IEdsb2JhbCBSb290IEcyMIIBIjANBgkqhkiG +9w0BAQEFAAOCAQ8AMIIBCgKCAQEAuzfNNNx7a8myaJCtSnX/RrohCgiN9RlUyfuI +2/Ou8jqJkTx65qsGGmvPrC3oXgkkRLpimn7Wo6h+4FR1IAWsULecYxpsMNzaHxmx +1x7e/dfgy5SDN67sH0NO3Xss0r0upS/kqbitOtSZpLYl6ZtrAGCSYP9PIUkY92eQ +q2EGnI/yuum06ZIya7XzV+hdG82MHauVBJVJ8zUtluNJbd134/tJS7SsVQepj5Wz +tCO7TG1F8PapspUwtP1MVYwnSlcUfIKdzXOS0xZKBgyMUNGPHgm+F6HmIcr9g+UQ +vIOlCsRnKPZzFBQ9RnbDhxSJITRNrw9FDKZJobq7nMWxM4MphQIDAQABo0IwQDAP +BgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQEAwIBhjAdBgNVHQ4EFgQUTiJUIBiV +5uNu5g/6+rkS7QYXjzkwDQYJKoZIhvcNAQELBQADggEBAGBnKJRvDkhj6zHd6mcY +1Yl9PMWLSn/pvtsrF9+wX3N3KjITOYFnQoQj8kVnNeyIv/iPsGEMNKSuIEyExtv4 +NeF22d+mQrvHRAiGfzZ0JFrabA0UWTW98kndth/Jsw1HKj2ZL7tcu7XUIOGZX1NG +Fdtom/DzMNU+MeKNhJ7jitralj41E6Vf8PlwUHBHQRFXGU7Aj64GxJUTFy8bJZ91 +8rGOmaFvE7FBcf6IKshPECBV1/MUReXgRPTqh5Uykw7+U0b6LJ3/iyK5S9kJRaTe +pLiaWN0bfVKfjllDiIGknibVb63dDcY3fe0Dkhvld1927jyNxF1WW6LZZm6zNTfl +MrY= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/digicertglobalrootg3 b/make/data/cacerts/digicertglobalrootg3 new file mode 100644 index 0000000..fbcfd3f --- /dev/null +++ b/make/data/cacerts/digicertglobalrootg3
@@ -0,0 +1,22 @@ +Owner: CN=DigiCert Global Root G3, OU=www.digicert.com, O=DigiCert Inc, C=US +Issuer: CN=DigiCert Global Root G3, OU=www.digicert.com, O=DigiCert Inc, C=US +Serial number: 55556bcf25ea43535c3a40fd5ab4572 +Valid from: Thu Aug 01 12:00:00 GMT 2013 until: Fri Jan 15 12:00:00 GMT 2038 +Signature algorithm name: SHA384withECDSA +Subject Public Key Algorithm: 384-bit EC (secp384r1) key +Version: 3 +-----BEGIN CERTIFICATE----- +MIICPzCCAcWgAwIBAgIQBVVWvPJepDU1w6QP1atFcjAKBggqhkjOPQQDAzBhMQsw +CQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3d3cu +ZGlnaWNlcnQuY29tMSAwHgYDVQQDExdEaWdpQ2VydCBHbG9iYWwgUm9vdCBHMzAe +Fw0xMzA4MDExMjAwMDBaFw0zODAxMTUxMjAwMDBaMGExCzAJBgNVBAYTAlVTMRUw +EwYDVQQKEwxEaWdpQ2VydCBJbmMxGTAXBgNVBAsTEHd3dy5kaWdpY2VydC5jb20x +IDAeBgNVBAMTF0RpZ2lDZXJ0IEdsb2JhbCBSb290IEczMHYwEAYHKoZIzj0CAQYF +K4EEACIDYgAE3afZu4q4C/sLfyHS8L6+c/MzXRq8NOrexpu80JX28MzQC7phW1FG +fp4tn+6OYwwX7Adw9c+ELkCDnOg/QW07rdOkFFk2eJ0DQ+4QE2xy3q6Ip6FrtUPO +Z9wj/wMco+I+o0IwQDAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQEAwIBhjAd +BgNVHQ4EFgQUs9tIpPmhxdiuNkHMEWNpYim8S8YwCgYIKoZIzj0EAwMDaAAwZQIx +AK288mw/EkrRLTnDCgmXc/SINoyIJ7vmiI1Qhadj+Z4y3maTD/HMsQmP3Wyr+mt/ +oAIwOWZbwmSNuJ5Q3KjVSaLtx9zRSX8XAbjIho9OjIgrqJqpisXRAL34VOKa5Vt8 +sycX +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/digicerthighassuranceevrootca b/make/data/cacerts/digicerthighassuranceevrootca new file mode 100644 index 0000000..13e6d85 --- /dev/null +++ b/make/data/cacerts/digicerthighassuranceevrootca
@@ -0,0 +1,30 @@ +Owner: CN=DigiCert High Assurance EV Root CA, OU=www.digicert.com, O=DigiCert Inc, C=US +Issuer: CN=DigiCert High Assurance EV Root CA, OU=www.digicert.com, O=DigiCert Inc, C=US +Serial number: 2ac5c266a0b409b8f0b79f2ae462577 +Valid from: Fri Nov 10 00:00:00 GMT 2006 until: Mon Nov 10 00:00:00 GMT 2031 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDxTCCAq2gAwIBAgIQAqxcJmoLQJuPC3nyrkYldzANBgkqhkiG9w0BAQUFADBs +MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3 +d3cuZGlnaWNlcnQuY29tMSswKQYDVQQDEyJEaWdpQ2VydCBIaWdoIEFzc3VyYW5j +ZSBFViBSb290IENBMB4XDTA2MTExMDAwMDAwMFoXDTMxMTExMDAwMDAwMFowbDEL +MAkGA1UEBhMCVVMxFTATBgNVBAoTDERpZ2lDZXJ0IEluYzEZMBcGA1UECxMQd3d3 +LmRpZ2ljZXJ0LmNvbTErMCkGA1UEAxMiRGlnaUNlcnQgSGlnaCBBc3N1cmFuY2Ug +RVYgUm9vdCBDQTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAMbM5XPm ++9S75S0tMqbf5YE/yc0lSbZxKsPVlDRnogocsF9ppkCxxLeyj9CYpKlBWTrT3JTW +PNt0OKRKzE0lgvdKpVMSOO7zSW1xkX5jtqumX8OkhPhPYlG++MXs2ziS4wblCJEM +xChBVfvLWokVfnHoNb9Ncgk9vjo4UFt3MRuNs8ckRZqnrG0AFFoEt7oT61EKmEFB +Ik5lYYeBQVCmeVyJ3hlKV9Uu5l0cUyx+mM0aBhakaHPQNAQTXKFx01p8VdteZOE3 +hzBWBOURtCmAEvF5OYiiAhF8J2a3iLd48soKqDirCmTCv2ZdlYTBoSUeh10aUAsg +EsxBu24LUTi4S8sCAwEAAaNjMGEwDgYDVR0PAQH/BAQDAgGGMA8GA1UdEwEB/wQF +MAMBAf8wHQYDVR0OBBYEFLE+w2kD+L9HAdSYJhoIAu9jZCvDMB8GA1UdIwQYMBaA +FLE+w2kD+L9HAdSYJhoIAu9jZCvDMA0GCSqGSIb3DQEBBQUAA4IBAQAcGgaX3Nec +nzyIZgYIVyHbIUf4KmeqvxgydkAQV8GK83rZEWWONfqe/EW1ntlMMUu4kehDLI6z +eM7b41N5cdblIZQB2lWHmiRk9opmzN6cN82oNLFpmyPInngiK3BD41VHMWEZ71jF +hS9OMPagMRYjyOfiZRYzy78aG6A9+MpeizGLYAiJLQwGXFK3xPkKmNEVX58Svnw2 +Yzi9RKR/5CYrCsSXaQ3pjOLAEFe4yHYSkVXySGnYvCoCWw9E1CAx2/S6cCZdkGCe +vEsXCS+0yx5DaMkHJ8HSXPfqIbloEpw8nL+e/IBcm2PN7EeqJSdnoDfzAIJ9VNep ++OkuE6N36B9K +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/digicerttrustedrootg4 b/make/data/cacerts/digicerttrustedrootg4 new file mode 100644 index 0000000..3079e55 --- /dev/null +++ b/make/data/cacerts/digicerttrustedrootg4
@@ -0,0 +1,39 @@ +Owner: CN=DigiCert Trusted Root G4, OU=www.digicert.com, O=DigiCert Inc, C=US +Issuer: CN=DigiCert Trusted Root G4, OU=www.digicert.com, O=DigiCert Inc, C=US +Serial number: 59b1b579e8e2132e23907bda777755c +Valid from: Thu Aug 01 12:00:00 GMT 2013 until: Fri Jan 15 12:00:00 GMT 2038 +Signature algorithm name: SHA384withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFkDCCA3igAwIBAgIQBZsbV56OITLiOQe9p3d1XDANBgkqhkiG9w0BAQwFADBi +MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3 +d3cuZGlnaWNlcnQuY29tMSEwHwYDVQQDExhEaWdpQ2VydCBUcnVzdGVkIFJvb3Qg +RzQwHhcNMTMwODAxMTIwMDAwWhcNMzgwMTE1MTIwMDAwWjBiMQswCQYDVQQGEwJV +UzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3d3cuZGlnaWNlcnQu +Y29tMSEwHwYDVQQDExhEaWdpQ2VydCBUcnVzdGVkIFJvb3QgRzQwggIiMA0GCSqG +SIb3DQEBAQUAA4ICDwAwggIKAoICAQC/5pBzaN675F1KPDAiMGkz7MKnJS7JIT3y +ithZwuEppz1Yq3aaza57G4QNxDAf8xukOBbrVsaXbR2rsnnyyhHS5F/WBTxSD1If +xp4VpX6+n6lXFllVcq9ok3DCsrp1mWpzMpTREEQQLt+C8weE5nQ7bXHiLQwb7iDV +ySAdYyktzuxeTsiT+CFhmzTrBcZe7FsavOvJz82sNEBfsXpm7nfISKhmV1efVFiO +DCu3T6cw2Vbuyntd463JT17lNecxy9qTXtyOj4DatpGYQJB5w3jHtrHEtWoYOAMQ +jdjUN6QuBX2I9YI+EJFwq1WCQTLX2wRzKm6RAXwhTNS8rhsDdV14Ztk6MUSaM0C/ +CNdaSaTC5qmgZ92kJ7yhTzm1EVgX9yRcRo9k98FpiHaYdj1ZXUJ2h4mXaXpI8OCi +EhtmmnTK3kse5w5jrubU75KSOp493ADkRSWJtppEGSt+wJS00mFt6zPZxd9LBADM +fRyVw4/3IbKyEbe7f/LVjHAsQWCqsWMYRJUadmJ+9oCw++hkpjPRiQfhvbfmQ6QY +uKZ3AeEPlAwhHbJUKSWJbOUOUlFHdL4mrLZBdd56rF+NP8m800ERElvlEFDrMcXK +chYiCd98THU/Y+whX8QgUWtvsauGi0/C1kVfnSD8oR7FwI+isX4KJpn15GkvmB0t +9dmpsh3lGwIDAQABo0IwQDAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQEAwIB +hjAdBgNVHQ4EFgQU7NfjgtJxXWRM3y5nP+e6mK4cD08wDQYJKoZIhvcNAQEMBQAD +ggIBALth2X2pbL4XxJEbw6GiAI3jZGgPVs93rnD5/ZpKmbnJeFwMDF/k5hQpVgs2 +SV1EY+CtnJYYZhsjDT156W1r1lT40jzBQ0CuHVD1UvyQO7uYmWlrx8GnqGikJ9yd ++SeuMIW59mdNOj6PWTkiU0TryF0Dyu1Qen1iIQqAyHNm0aAFYF/opbSnr6j3bTWc +fFqK1qI4mfN4i/RN0iAL3gTujJtHgXINwBQy7zBZLq7gcfJW5GqXb5JQbZaNaHqa +sjYUegbyJLkJEVDXCLG4iXqEI2FCKeWjzaIgQdfRnGTZ6iahixTXTBmyUEFxPT9N +cCOGDErcgdLMMpSEDQgJlxxPwO5rIHQw0uA5NBCFIRUBCOhVMt5xSdkoF1BN5r5N +0XWs0Mr7QbhDparTwwVETyw2m+L64kW4I1NsBm9nVX9GtUw/bihaeSbSpKhil9Ie +4u1Ki7wb/UdKDd9nZn6yW0HQO+T0O/QEY+nvwlQAUaCKKsnOeMzV6ocEGLPOr0mI +r/OSmbaz5mEP0oUA51Aa5BuVnRmhuZyxm7EAHu/QD09CbMkKvO5D+jpxpchNJqU1 +/YldvIViHTLSoCtU7ZpXwdv6EM8Zt4tKG48BtieVU+i2iW1bvGjUI+iLUaJW+fCm +gKDWHrO8Dw9TdSmq6hN35N6MgSGtBxBHEa2HPQfRdbzP82Z+ +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/dtrustclass3ca2 b/make/data/cacerts/dtrustclass3ca2 new file mode 100644 index 0000000..321c8fd --- /dev/null +++ b/make/data/cacerts/dtrustclass3ca2
@@ -0,0 +1,32 @@ +Owner: CN=D-TRUST Root Class 3 CA 2 2009, O=D-Trust GmbH, C=DE +Issuer: CN=D-TRUST Root Class 3 CA 2 2009, O=D-Trust GmbH, C=DE +Serial number: 983f3 +Valid from: Thu Nov 05 08:35:58 GMT 2009 until: Mon Nov 05 08:35:58 GMT 2029 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEMzCCAxugAwIBAgIDCYPzMA0GCSqGSIb3DQEBCwUAME0xCzAJBgNVBAYTAkRF +MRUwEwYDVQQKDAxELVRydXN0IEdtYkgxJzAlBgNVBAMMHkQtVFJVU1QgUm9vdCBD +bGFzcyAzIENBIDIgMjAwOTAeFw0wOTExMDUwODM1NThaFw0yOTExMDUwODM1NTha +ME0xCzAJBgNVBAYTAkRFMRUwEwYDVQQKDAxELVRydXN0IEdtYkgxJzAlBgNVBAMM +HkQtVFJVU1QgUm9vdCBDbGFzcyAzIENBIDIgMjAwOTCCASIwDQYJKoZIhvcNAQEB +BQADggEPADCCAQoCggEBANOySs96R+91myP6Oi/WUEWJNTrGa9v+2wBoqOADER03 +UAifTUpolDWzU9GUY6cgVq/eUXjsKj3zSEhQPgrfRlWLJ23DEE0NkVJD2IfgXU42 +tSHKXzlABF9bfsyjxiupQB7ZNoTWSPOSHjRGICTBpFGOShrvUD9pXRl/RcPHAY9R +ySPocq60vFYJfxLLHLGvKZAKyVXMD9O0Gu1HNVpK7ZxzBCHQqr0ME7UAyiZsxGsM +lFqVlNpQmvH/pStmMaTJOKDfHR+4CS7zp+hnUquVH+BGPtikw8paxTGA6Eian5Rp +/hnd2HN8gcqW3o7tszIFZYQ05ub9VxC1X3a/L7AQDcUCAwEAAaOCARowggEWMA8G +A1UdEwEB/wQFMAMBAf8wHQYDVR0OBBYEFP3aFMSfMN4hvR5COfyrYyNJ4PGEMA4G +A1UdDwEB/wQEAwIBBjCB0wYDVR0fBIHLMIHIMIGAoH6gfIZ6bGRhcDovL2RpcmVj +dG9yeS5kLXRydXN0Lm5ldC9DTj1ELVRSVVNUJTIwUm9vdCUyMENsYXNzJTIwMyUy +MENBJTIwMiUyMDIwMDksTz1ELVRydXN0JTIwR21iSCxDPURFP2NlcnRpZmljYXRl +cmV2b2NhdGlvbmxpc3QwQ6BBoD+GPWh0dHA6Ly93d3cuZC10cnVzdC5uZXQvY3Js +L2QtdHJ1c3Rfcm9vdF9jbGFzc18zX2NhXzJfMjAwOS5jcmwwDQYJKoZIhvcNAQEL +BQADggEBAH+X2zDI36ScfSF6gHDOFBJpiBSVYEQBrLLpME+bUMJm2H6NMLVwMeni +acfzcNsgFYbQDfC+rAF1hM5+n02/t2A7nPPKHeJeaNijnZflQGDSNiH+0LS4F9p0 +o3/U37CYAqxva2ssJSRyoWXuJVrl5jLn8t+rSfrzkGkj2wTZ51xY/GXUl77M/C4K +zCUqNQT4YJEVdT1B/yMfGchs64JTBKbkTCJNjYy6zltz7GRUUG3RnFX7acM2w4y8 +PIWmawomDeCTmGCufsYkl4phX5GOZpIJhzbNi5stPvZR1FDUWSi9g/LMKHtThm3Y +Johw1+qRzT65ysCQblrGXnRl11z+o+I= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/dtrustclass3ca2ev b/make/data/cacerts/dtrustclass3ca2ev new file mode 100644 index 0000000..191a188 --- /dev/null +++ b/make/data/cacerts/dtrustclass3ca2ev
@@ -0,0 +1,32 @@ +Owner: CN=D-TRUST Root Class 3 CA 2 EV 2009, O=D-Trust GmbH, C=DE +Issuer: CN=D-TRUST Root Class 3 CA 2 EV 2009, O=D-Trust GmbH, C=DE +Serial number: 983f4 +Valid from: Thu Nov 05 08:50:46 GMT 2009 until: Mon Nov 05 08:50:46 GMT 2029 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEQzCCAyugAwIBAgIDCYP0MA0GCSqGSIb3DQEBCwUAMFAxCzAJBgNVBAYTAkRF +MRUwEwYDVQQKDAxELVRydXN0IEdtYkgxKjAoBgNVBAMMIUQtVFJVU1QgUm9vdCBD +bGFzcyAzIENBIDIgRVYgMjAwOTAeFw0wOTExMDUwODUwNDZaFw0yOTExMDUwODUw +NDZaMFAxCzAJBgNVBAYTAkRFMRUwEwYDVQQKDAxELVRydXN0IEdtYkgxKjAoBgNV +BAMMIUQtVFJVU1QgUm9vdCBDbGFzcyAzIENBIDIgRVYgMjAwOTCCASIwDQYJKoZI +hvcNAQEBBQADggEPADCCAQoCggEBAJnxhDRwui+3MKCOvXwEz75ivJn9gpfSegpn +ljgJ9hBOlSJzmY3aFS3nBfwZcyK3jpgAvDw9rKFs+9Z5JUut8Mxk2og+KbgPCdM0 +3TP1YtHhzRnp7hhPTFiu4h7WDFsVWtg6uMQYZB7jM7K1iXdODL/ZlGsTl28So/6Z +qQTMFexgaDbtCHu39b+T7WYxg4zGcTSHThfqr4uRjRxWQa4iN1438h3Z0S0NL2lR +p75mpoo6Kr3HGrHhFPC+Oh25z1uxav60sUYgovseO3Dvk5h9jHOW8sXvhXCtKSb8 +HgQ+HKDYD8tSg2J87otTlZCpV6LqYQXY+U3EJ/pure3511H3a6UCAwEAAaOCASQw +ggEgMA8GA1UdEwEB/wQFMAMBAf8wHQYDVR0OBBYEFNOUikxiEyoZLsyvcop9Ntea +HNxnMA4GA1UdDwEB/wQEAwIBBjCB3QYDVR0fBIHVMIHSMIGHoIGEoIGBhn9sZGFw +Oi8vZGlyZWN0b3J5LmQtdHJ1c3QubmV0L0NOPUQtVFJVU1QlMjBSb290JTIwQ2xh +c3MlMjAzJTIwQ0ElMjAyJTIwRVYlMjAyMDA5LE89RC1UcnVzdCUyMEdtYkgsQz1E +RT9jZXJ0aWZpY2F0ZXJldm9jYXRpb25saXN0MEagRKBChkBodHRwOi8vd3d3LmQt +dHJ1c3QubmV0L2NybC9kLXRydXN0X3Jvb3RfY2xhc3NfM19jYV8yX2V2XzIwMDku +Y3JsMA0GCSqGSIb3DQEBCwUAA4IBAQA07XtaPKSUiO8aEXUHL7P+PPoeUSbrh/Yp +3uDx1MYkCenBz1UbtDDZzhr+BlGmFaQt77JLvyAoJUnRpjZ3NOhk31KxEcdzes05 +nsKtjHEh8lprr988TlWvsoRlFIm5d8sqMb7Po23Pb0iUMkZv53GMoKaEGTcH8gNF +CSuGdXzfX2lXANtu2KZyIktQ1HWYVt+3GP9DQ1CuekR78HlR10M9p9OB0/DJT7na +xpeG0ILD5EJt/rDiZE4OJudANCa1CInXCGNjOCd1HjPqbqjdn5lPdE2BiYBL3ZqX +KVwvvoFBuYz/6n1gBp7N1z3TLqMVvKjmJuVvw9y4AyHqnxbxLFS1 +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/entrust2048ca b/make/data/cacerts/entrust2048ca new file mode 100644 index 0000000..0dd198d --- /dev/null +++ b/make/data/cacerts/entrust2048ca
@@ -0,0 +1,32 @@ +Owner: CN=Entrust.net Certification Authority (2048), OU=(c) 1999 Entrust.net Limited, OU=www.entrust.net/CPS_2048 incorp. by ref. (limits liab.), O=Entrust.net +Issuer: CN=Entrust.net Certification Authority (2048), OU=(c) 1999 Entrust.net Limited, OU=www.entrust.net/CPS_2048 incorp. by ref. (limits liab.), O=Entrust.net +Serial number: 3863def8 +Valid from: Fri Dec 24 17:50:51 GMT 1999 until: Tue Jul 24 14:15:12 GMT 2029 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEKjCCAxKgAwIBAgIEOGPe+DANBgkqhkiG9w0BAQUFADCBtDEUMBIGA1UEChML +RW50cnVzdC5uZXQxQDA+BgNVBAsUN3d3dy5lbnRydXN0Lm5ldC9DUFNfMjA0OCBp +bmNvcnAuIGJ5IHJlZi4gKGxpbWl0cyBsaWFiLikxJTAjBgNVBAsTHChjKSAxOTk5 +IEVudHJ1c3QubmV0IExpbWl0ZWQxMzAxBgNVBAMTKkVudHJ1c3QubmV0IENlcnRp +ZmljYXRpb24gQXV0aG9yaXR5ICgyMDQ4KTAeFw05OTEyMjQxNzUwNTFaFw0yOTA3 +MjQxNDE1MTJaMIG0MRQwEgYDVQQKEwtFbnRydXN0Lm5ldDFAMD4GA1UECxQ3d3d3 +LmVudHJ1c3QubmV0L0NQU18yMDQ4IGluY29ycC4gYnkgcmVmLiAobGltaXRzIGxp +YWIuKTElMCMGA1UECxMcKGMpIDE5OTkgRW50cnVzdC5uZXQgTGltaXRlZDEzMDEG +A1UEAxMqRW50cnVzdC5uZXQgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkgKDIwNDgp +MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEArU1LqRKGsuqjIAcVFmQq +K0vRvwtKTY7tgHalZ7d4QMBzQshowNtTK91euHaYNZOLGp18EzoOH1u3Hs/lJBQe +sYGpjX24zGtLA/ECDNyrpUAkAH90lKGdCCmziAv1h3edVc3kw37XamSrhRSGlVuX +MlBvPci6Zgzj/L24ScF2iUkZ/cCovYmjZy/Gn7xxGWC4LeksyZB2ZnuU4q941mVT +XTzWnLLPKQP5L6RQstRIzgUyVYr9smRMDuSYB3Xbf9+5CFVghTAp+XtIpGmG4zU/ +HoZdenoVve8AjhUiVBcAkCaTvA5JaJG/+EfTnZVCwQ5N328mz8MYIWJmQ3DW1cAH +4QIDAQABo0IwQDAOBgNVHQ8BAf8EBAMCAQYwDwYDVR0TAQH/BAUwAwEB/zAdBgNV +HQ4EFgQUVeSB0RGAvtiJuQijMfmhJAkWuXAwDQYJKoZIhvcNAQEFBQADggEBADub +j1abMOdTmXx6eadNl9cZlZD7Bh/KM3xGY4+WZiT6QBshJ8rmcnPyT/4xmf3IDExo +U8aAghOY+rat2l098c5u9hURlIIM7j+VrxGrD9cv3h8Dj1csHsm7mhpElesYT6Yf +zX1XEC+bBAlahLVu2B064dae0Wx5XnkcFMXj0EyTO2U87d89vqbllRrDtRnDvV5b +u/8j72gZyxKTJ1wDLW8w0B62GqzeWvfRqqgnpv55gcR5mTNXuhKwqeBCbJPKVt7+ +bYQLCIt+jerXmCHG8+c8eS9enNFMFY3h7CI3zJpDC5fcgJCNs2ebb0gIFVbPv/Er +fF6adulZkMV8gzURZVE= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/entrustevca b/make/data/cacerts/entrustevca new file mode 100644 index 0000000..6c2c509 --- /dev/null +++ b/make/data/cacerts/entrustevca
@@ -0,0 +1,34 @@ +Owner: CN=Entrust Root Certification Authority, OU="(c) 2006 Entrust, Inc.", OU=www.entrust.net/CPS is incorporated by reference, O="Entrust, Inc.", C=US +Issuer: CN=Entrust Root Certification Authority, OU="(c) 2006 Entrust, Inc.", OU=www.entrust.net/CPS is incorporated by reference, O="Entrust, Inc.", C=US +Serial number: 456b5054 +Valid from: Mon Nov 27 20:23:42 GMT 2006 until: Fri Nov 27 20:53:42 GMT 2026 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEkTCCA3mgAwIBAgIERWtQVDANBgkqhkiG9w0BAQUFADCBsDELMAkGA1UEBhMC +VVMxFjAUBgNVBAoTDUVudHJ1c3QsIEluYy4xOTA3BgNVBAsTMHd3dy5lbnRydXN0 +Lm5ldC9DUFMgaXMgaW5jb3Jwb3JhdGVkIGJ5IHJlZmVyZW5jZTEfMB0GA1UECxMW +KGMpIDIwMDYgRW50cnVzdCwgSW5jLjEtMCsGA1UEAxMkRW50cnVzdCBSb290IENl +cnRpZmljYXRpb24gQXV0aG9yaXR5MB4XDTA2MTEyNzIwMjM0MloXDTI2MTEyNzIw +NTM0MlowgbAxCzAJBgNVBAYTAlVTMRYwFAYDVQQKEw1FbnRydXN0LCBJbmMuMTkw +NwYDVQQLEzB3d3cuZW50cnVzdC5uZXQvQ1BTIGlzIGluY29ycG9yYXRlZCBieSBy +ZWZlcmVuY2UxHzAdBgNVBAsTFihjKSAyMDA2IEVudHJ1c3QsIEluYy4xLTArBgNV +BAMTJEVudHJ1c3QgUm9vdCBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTCCASIwDQYJ +KoZIhvcNAQEBBQADggEPADCCAQoCggEBALaVtkNC+sZtKm9I35RMOVcF7sN5EUFo +Nu3s/poBj6E4KPz3EEZmLk0eGrEaTsbRwJWIsMn/MYszA9u3g3s+IIRe7bJWKKf4 +4LlAcTfFy0cOlypowCKVYhXbR9n10Cv/gkvJrT7eTNuQgFA/CYqEAOwwCj0Yzfv9 +KlmaI5UXLEWeH25DeW0MXJj+SKfFI0dcXv1u5x609mhF0YaDW6KKjbHjKYD+JXGI +rb68j6xSlkuqUY3kEzEZ6E5Nn9uss2rVvDlUccp6en+Q3X0dgNmBu1kmwhH+5pPi +94DkZfs0Nw4pgHBNrziGLp5/V6+eF67rHMsoIV+2HNjnogQi+dPa2MsCAwEAAaOB +sDCBrTAOBgNVHQ8BAf8EBAMCAQYwDwYDVR0TAQH/BAUwAwEB/zArBgNVHRAEJDAi +gA8yMDA2MTEyNzIwMjM0MlqBDzIwMjYxMTI3MjA1MzQyWjAfBgNVHSMEGDAWgBRo +kORnpKZTgMeGZqTx90tD+4S9bTAdBgNVHQ4EFgQUaJDkZ6SmU4DHhmak8fdLQ/uE +vW0wHQYJKoZIhvZ9B0EABBAwDhsIVjcuMTo0LjADAgSQMA0GCSqGSIb3DQEBBQUA +A4IBAQCT1DCw1wMgKtD5Y+iRDAUgqV8ZyntyTtSx29CW+1RaGSwMCPeyvIWonX9t +O1KzKtvn1ISMY/YPyyYBkVBs9F8U4pN0wBOeMDpQ47RgxRzwIkSNcUesyBrJ6Zua +AGAT/3B+XxFNSRuzFVJ7yVTav52Vr2ua2J7p8eRDjeIRRDq/r72DQnNSi6q7pynP +9WQcCk3RvKqsnyrQ/39/2n3qse0wJcGE2jTSW3iDVuycNsMm4hH2Z0kdkquM++v/ +eu6FSqdQgPCnXEqULl8FmTxSQeDNtGPPAUO6nIPcj2A781q0tHuu2guQOHXvgR1m +0vdXcDazv/wor3ElhVsT/h5/WrQ8 +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/entrustrootcaec1 b/make/data/cacerts/entrustrootcaec1 new file mode 100644 index 0000000..58d29d5 --- /dev/null +++ b/make/data/cacerts/entrustrootcaec1
@@ -0,0 +1,25 @@ +Owner: CN=Entrust Root Certification Authority - EC1, OU="(c) 2012 Entrust, Inc. - for authorized use only", OU=See www.entrust.net/legal-terms, O="Entrust, Inc.", C=US +Issuer: CN=Entrust Root Certification Authority - EC1, OU="(c) 2012 Entrust, Inc. - for authorized use only", OU=See www.entrust.net/legal-terms, O="Entrust, Inc.", C=US +Serial number: a68b79290000000050d091f9 +Valid from: Tue Dec 18 15:25:36 GMT 2012 until: Fri Dec 18 15:55:36 GMT 2037 +Signature algorithm name: SHA384withECDSA +Subject Public Key Algorithm: 384-bit EC (secp384r1) key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIC+TCCAoCgAwIBAgINAKaLeSkAAAAAUNCR+TAKBggqhkjOPQQDAzCBvzELMAkG +A1UEBhMCVVMxFjAUBgNVBAoTDUVudHJ1c3QsIEluYy4xKDAmBgNVBAsTH1NlZSB3 +d3cuZW50cnVzdC5uZXQvbGVnYWwtdGVybXMxOTA3BgNVBAsTMChjKSAyMDEyIEVu +dHJ1c3QsIEluYy4gLSBmb3IgYXV0aG9yaXplZCB1c2Ugb25seTEzMDEGA1UEAxMq +RW50cnVzdCBSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5IC0gRUMxMB4XDTEy +MTIxODE1MjUzNloXDTM3MTIxODE1NTUzNlowgb8xCzAJBgNVBAYTAlVTMRYwFAYD +VQQKEw1FbnRydXN0LCBJbmMuMSgwJgYDVQQLEx9TZWUgd3d3LmVudHJ1c3QubmV0 +L2xlZ2FsLXRlcm1zMTkwNwYDVQQLEzAoYykgMjAxMiBFbnRydXN0LCBJbmMuIC0g +Zm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxMzAxBgNVBAMTKkVudHJ1c3QgUm9vdCBD +ZXJ0aWZpY2F0aW9uIEF1dGhvcml0eSAtIEVDMTB2MBAGByqGSM49AgEGBSuBBAAi +A2IABIQTydC6bUF74mzQ61VfZgIaJPRbiWlH47jCffHyAsWfoPZb1YsGGYZPUxBt +ByQnoaD41UcZYUx9ypMn6nQM72+WCf5j7HBdNq1nd67JnXxVRDqiY1Ef9eNi1KlH +Bz7MIKNCMEAwDgYDVR0PAQH/BAQDAgEGMA8GA1UdEwEB/wQFMAMBAf8wHQYDVR0O +BBYEFLdj5xrdjekIplWDpOBqUEFlEUJJMAoGCCqGSM49BAMDA2cAMGQCMGF52OVC +R98crlOZF7ZvHH3hvxGU0QOIdeSNiaSKd0bebWHvAvX7td/M/k7//qnmpwIwW5nX +hTcGtXsI/esni0qU+eH6p44mCOh8kmhtc9hvJqwhAriZtyZBWyVgrtBIGu4G +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/entrustrootcag2 b/make/data/cacerts/entrustrootcag2 new file mode 100644 index 0000000..48ac892 --- /dev/null +++ b/make/data/cacerts/entrustrootcag2
@@ -0,0 +1,32 @@ +Owner: CN=Entrust Root Certification Authority - G2, OU="(c) 2009 Entrust, Inc. - for authorized use only", OU=See www.entrust.net/legal-terms, O="Entrust, Inc.", C=US +Issuer: CN=Entrust Root Certification Authority - G2, OU="(c) 2009 Entrust, Inc. - for authorized use only", OU=See www.entrust.net/legal-terms, O="Entrust, Inc.", C=US +Serial number: 4a538c28 +Valid from: Tue Jul 07 17:25:54 GMT 2009 until: Sat Dec 07 17:55:54 GMT 2030 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEPjCCAyagAwIBAgIESlOMKDANBgkqhkiG9w0BAQsFADCBvjELMAkGA1UEBhMC +VVMxFjAUBgNVBAoTDUVudHJ1c3QsIEluYy4xKDAmBgNVBAsTH1NlZSB3d3cuZW50 +cnVzdC5uZXQvbGVnYWwtdGVybXMxOTA3BgNVBAsTMChjKSAyMDA5IEVudHJ1c3Qs +IEluYy4gLSBmb3IgYXV0aG9yaXplZCB1c2Ugb25seTEyMDAGA1UEAxMpRW50cnVz +dCBSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5IC0gRzIwHhcNMDkwNzA3MTcy +NTU0WhcNMzAxMjA3MTc1NTU0WjCBvjELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUVu +dHJ1c3QsIEluYy4xKDAmBgNVBAsTH1NlZSB3d3cuZW50cnVzdC5uZXQvbGVnYWwt +dGVybXMxOTA3BgNVBAsTMChjKSAyMDA5IEVudHJ1c3QsIEluYy4gLSBmb3IgYXV0 +aG9yaXplZCB1c2Ugb25seTEyMDAGA1UEAxMpRW50cnVzdCBSb290IENlcnRpZmlj +YXRpb24gQXV0aG9yaXR5IC0gRzIwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEK +AoIBAQC6hLZy254Ma+KZ6TABp3bqMriVQRrJ2mFOWHLP/vaCeb9zYQYKpSfYs1/T +RU4cctZOMvJyig/3gxnQaoCAAEUesMfnmr8SVycco2gvCoe9amsOXmXzHHfV1IWN +cCG0szLni6LVhjkCsbjSR87kyUnEO6fe+1R9V77w6G7CebI6C1XiUJgWMhNcL3hW +wcKUs/Ja5CeanyTXxuzQmyWC48zCxEXFjJd6BmsqEZ+pCm5IO2/b1BEZQvePB7/1 +U1+cPvQXLOZprE4yTGJ36rfo5bs0vBmLrpxR57d+tVOxMyLlbc9wPBr64ptntoP0 +jaWvYkxN4FisZDQSA/i2jZRjJKRxAgMBAAGjQjBAMA4GA1UdDwEB/wQEAwIBBjAP +BgNVHRMBAf8EBTADAQH/MB0GA1UdDgQWBBRqciZ60B7vfec7aVHUbI2fkBJmqzAN +BgkqhkiG9w0BAQsFAAOCAQEAeZ8dlsa2eT8ijYfThwMEYGprmi5ZiXMRrEPR9RP/ +jTkrwPK9T3CMqS/qF8QLVJ7UG5aYMzyorWKiAHarWWluBh1+xLlEjZivEtRh2woZ +Rkfz6/djwUAFQKXSt/S1mja/qYh2iARVBCuch38aNzx+LaUa2NSJXsq9rD1s2G2v +1fN2D807iDginWyTmsQ9v4IbZT+mD12q/OWyFcq1rca8PdCE6OoGcrBNOTJ4vz4R +nAuknZoh8/CbCzB428Hch0P+vGOaysXCHMnHjf87ElgI5rY97HosTvuDls4MPGmH +VHOkc8KT/1EQrBVUAdj8BbGJoX90g5pJ19xOe4pIb4tF9g== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/entrustrootcag4 b/make/data/cacerts/entrustrootcag4 new file mode 100644 index 0000000..67a1475 --- /dev/null +++ b/make/data/cacerts/entrustrootcag4
@@ -0,0 +1,43 @@ +Owner: CN=Entrust Root Certification Authority - G4, OU="(c) 2015 Entrust, Inc. - for authorized use only", OU=See www.entrust.net/legal-terms, O="Entrust, Inc.", C=US +Issuer: CN=Entrust Root Certification Authority - G4, OU="(c) 2015 Entrust, Inc. - for authorized use only", OU=See www.entrust.net/legal-terms, O="Entrust, Inc.", C=US +Serial number: d9b5437fafa9390f000000005565ad58 +Valid from: Wed May 27 11:11:16 GMT 2015 until: Sun Dec 27 11:41:16 GMT 2037 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIGSzCCBDOgAwIBAgIRANm1Q3+vqTkPAAAAAFVlrVgwDQYJKoZIhvcNAQELBQAw +gb4xCzAJBgNVBAYTAlVTMRYwFAYDVQQKEw1FbnRydXN0LCBJbmMuMSgwJgYDVQQL +Ex9TZWUgd3d3LmVudHJ1c3QubmV0L2xlZ2FsLXRlcm1zMTkwNwYDVQQLEzAoYykg +MjAxNSBFbnRydXN0LCBJbmMuIC0gZm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxMjAw +BgNVBAMTKUVudHJ1c3QgUm9vdCBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eSAtIEc0 +MB4XDTE1MDUyNzExMTExNloXDTM3MTIyNzExNDExNlowgb4xCzAJBgNVBAYTAlVT +MRYwFAYDVQQKEw1FbnRydXN0LCBJbmMuMSgwJgYDVQQLEx9TZWUgd3d3LmVudHJ1 +c3QubmV0L2xlZ2FsLXRlcm1zMTkwNwYDVQQLEzAoYykgMjAxNSBFbnRydXN0LCBJ +bmMuIC0gZm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxMjAwBgNVBAMTKUVudHJ1c3Qg +Um9vdCBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eSAtIEc0MIICIjANBgkqhkiG9w0B +AQEFAAOCAg8AMIICCgKCAgEAsewsQu7i0TD/pZJH4i3DumSXbcr3DbVZwbPLqGgZ +2K+EbTBwXX7zLtJTmeH+H17ZSK9dE43b/2MzTdMAArzE+NEGCJR5WIoV3imz/f3E +T+iq4qA7ec2/a0My3dl0ELn39GjUu9CH1apLiipvKgS1sqbHoHrmSKvS0VnM1n4j +5pds8ELl3FFLFUHtSUrJ3hCX1nbB76W1NhSXNdh4IjVS70O92yfbYVaCNNzLiGAM +C1rlLAHGVK/XqsEQe9IFWrhAnoanw5CGAlZSCXqc0ieCU0plUmr1POeo8pyvi73T +DtTUXm6Hnmo9RR3RXRv06QqsYJn7ibT/mCzPfB3pAqoEmh643IhuJbNsZvc8kPNX +wbMv9W3y+8qh+CmdRouzavbmZwe+LGcKKh9asj5XxNMhIWNlUpEbsZmOeX7m640A +2Vqq6nPopIICR5b+W45UYaPrL0swsIsjdXJ8ITzI9vF01Bx7owVV7rtNOzK+mndm +nqxpkCIHH2E6lr7lmk/MBTwoWdPBDFSoWWG9yHJM6Nyfh3+9nEg2XpWjDrk4JFX8 +dWbrAuMINClKxuMrLzOg2qOGpRKX/YAr2hRC45K9PvJdXmd0LhyIRyk0X+IyqJwl +N4y6mACXi0mWHv0liqzc2thddG5msP9E36EYxr5ILzeUePiVSj9/E15dWf10hkNj +c0kCAwEAAaNCMEAwDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwHQYD +VR0OBBYEFJ84xFYjwznooHFs6FRM5Og6sb9nMA0GCSqGSIb3DQEBCwUAA4ICAQAS +5UKme4sPDORGpbZgQIeMJX6tuGguW8ZAdjwD+MlZ9POrYs4QjbRaZIxowLByQzTS +Gwv2LFPSypBLhmb8qoMi9IsabyZIrHZ3CL/FmFz0Jomee8O5ZDIBf9PD3Vht7LGr +hFV0d4QEJ1JrhkzO3bll/9bGXp+aEJlLdWr+aumXIOTkdnrG0CSqkM0gkLpHZPt/ +B7NTeLUKYvJzQ85BK4FqLoUWlFPUa19yIqtRLULVAJyZv967lDtX/Zr1hstWO1uI +AeV8KEsD+UmDfLJ/fOPtjqF/YFOOVZ1QNBIPt5d7bIdKROf1beyAN/BYGW5KaHbw +H5Lk6rWS02FREAutp9lfx1/cH6NcjKF+m7ee01ZvZl4HliDtC3T7Zk6LERXpgUl+ +b7DUUH8i119lAg2m9IUe2K4GS0qn0jFmwvjO5QimpAKWRGhXxNUzzxkvFMSUHHuk +2fCfDrGA4tGeEWSpiBE6doLlYsKA2KSD7ZPvfC+QsDJMlhVoSFLUmQjAJOgc47Ol +IQ6SwJAfzyBfyjs4x7dtOvPmRLgOMWuIjnDrnBdSqEGULoe256YSxXXfW8AKbnuk +5F6G+TaU33fD6Q3AOfF5u0aOq0NZJ7cguyPpVkAh7DE9ZapD8j3fcEThuk0mEDuY +n/PIjhs4ViFqUZPTkcpG2om3PVODLAgfi49T3f+sHw== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/geotrustglobalca b/make/data/cacerts/geotrustglobalca new file mode 100644 index 0000000..7f8bf9a --- /dev/null +++ b/make/data/cacerts/geotrustglobalca
@@ -0,0 +1,27 @@ +Owner: CN=GeoTrust Global CA, O=GeoTrust Inc., C=US +Issuer: CN=GeoTrust Global CA, O=GeoTrust Inc., C=US +Serial number: 23456 +Valid from: Tue May 21 04:00:00 GMT 2002 until: Sat May 21 04:00:00 GMT 2022 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDVDCCAjygAwIBAgIDAjRWMA0GCSqGSIb3DQEBBQUAMEIxCzAJBgNVBAYTAlVT +MRYwFAYDVQQKEw1HZW9UcnVzdCBJbmMuMRswGQYDVQQDExJHZW9UcnVzdCBHbG9i +YWwgQ0EwHhcNMDIwNTIxMDQwMDAwWhcNMjIwNTIxMDQwMDAwWjBCMQswCQYDVQQG +EwJVUzEWMBQGA1UEChMNR2VvVHJ1c3QgSW5jLjEbMBkGA1UEAxMSR2VvVHJ1c3Qg +R2xvYmFsIENBMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA2swYYzD9 +9BcjGlZ+W988bDjkcbd4kdS8odhM+KhDtgPpTSEHCIjaWC9mOSm9BXiLnTjoBbdq +fnGk5sRgprDvgOSJKA+eJdbtg/OtppHHmMlCGDUUna2YRpIuT8rxh0PBFpVXLVDv +iS2Aelet8u5fa9IAjbkU+BQVNdnARqN7csiRv8lVK83Qlz6cJmTM386DGXHKTubU +1XupGc1V3sjs0l44U+VcT4wt/lAjNvxm5suOpDkZALeVAjmRCw7+OC7RHQWa9k0+ +bw8HHa8sHo9gOeL6NlMTOdReJivbPagUvTLrGAMoUgRx5aszPeE4uwc2hGKceeoW +MPRfwCvocWvk+QIDAQABo1MwUTAPBgNVHRMBAf8EBTADAQH/MB0GA1UdDgQWBBTA +ephojYn7qwVkDBF9qn1luMrMTjAfBgNVHSMEGDAWgBTAephojYn7qwVkDBF9qn1l +uMrMTjANBgkqhkiG9w0BAQUFAAOCAQEANeMpauUvXVSOKVCUn5kaFOSPeCpilKIn +Z57QzxpeR+nBsqTP3UEaBU6bS+5Kb1VSsyShNwrrZHYqLizz/Tt1kL/6cdjHPTfS +tQWVYrmm3ok9Nns4d0iXrKYgjy6myQzCsplFAMfOEVEiIuCl6rYVSAlk6l5PdPcF +PseKUgzbFbS9bZvlxrFUaKnjaZC2mqUPuLk/IH2uSrW4nOQdtqvmlKXBx4Ot2/Un +hw4EbNX/3aBd7YdStysVAq45pmp06drE57xNNB6pXE0zX5IJL4hmXXeXxx12E6nV +5fEWCRE11azbJHFwLJhWC9kXtNHjUStedejV0NxPNO3CBWaAocvmMw== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/geotrustprimaryca b/make/data/cacerts/geotrustprimaryca new file mode 100644 index 0000000..0f680ca --- /dev/null +++ b/make/data/cacerts/geotrustprimaryca
@@ -0,0 +1,28 @@ +Owner: CN=GeoTrust Primary Certification Authority, O=GeoTrust Inc., C=US +Issuer: CN=GeoTrust Primary Certification Authority, O=GeoTrust Inc., C=US +Serial number: 18acb56afd69b6153a636cafdafac4a1 +Valid from: Mon Nov 27 00:00:00 GMT 2006 until: Wed Jul 16 23:59:59 GMT 2036 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDfDCCAmSgAwIBAgIQGKy1av1pthU6Y2yv2vrEoTANBgkqhkiG9w0BAQUFADBY +MQswCQYDVQQGEwJVUzEWMBQGA1UEChMNR2VvVHJ1c3QgSW5jLjExMC8GA1UEAxMo +R2VvVHJ1c3QgUHJpbWFyeSBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTAeFw0wNjEx +MjcwMDAwMDBaFw0zNjA3MTYyMzU5NTlaMFgxCzAJBgNVBAYTAlVTMRYwFAYDVQQK +Ew1HZW9UcnVzdCBJbmMuMTEwLwYDVQQDEyhHZW9UcnVzdCBQcmltYXJ5IENlcnRp +ZmljYXRpb24gQXV0aG9yaXR5MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKC +AQEAvrgVe//UfH1nrYNke8hCUy3f9oQIIGHWAVlqnEQRr+92/ZV+zmEwu3qDXwK9 +AWbK7hWNb6EwnL2hhZ6UOvNWiAAxz9juapYC2e0DjPt1befquFUWBRaa9OBesYjA +ZIVcFU2Ix7e64HXprQU9nceJSOC7KMgD4TCTZF5SwFlwIjVXiIrxlQqD17wxcwE0 +7e9GceBrAqg1cmuXm2bgyxx5X9gaBGgeRwLmnWDiNpcB3841kt++Z8dtd1k7j53W +kBWUvEI0EME5+bEnPn7WinXFsq+W06Lem+SYvn3h6YGttm/81w7a4DSwDRp35+MI +mO9Y+pyEtzavwt+s0vQQBnBxNQIDAQABo0IwQDAPBgNVHRMBAf8EBTADAQH/MA4G +A1UdDwEB/wQEAwIBBjAdBgNVHQ4EFgQULNVQQZcVi/CPNmFbSvtr2ZnJM5IwDQYJ +KoZIhvcNAQEFBQADggEBAFpwfyzdtzRP9YZRqSa+S7iq8XEN3GHHoOo0Hnp3DwQ1 +6CePbJC/kRYkRj5KTs4rFtULUh38H2eiAkUxT87z+gOneZ1TatnaYzr4gNfTmeGl +4b7UVXGYNTq+k+qurUKykG/g/CFNNWMziUnWm07Kx+dOCQD32sfvmWKZd7aVIl6K +oKv0uHiYyjgZmclynnjNS6yvGaBzEi38wkG6gZHaFloxt/m0cYASSJlyc1pZU8Fj +UjPtp8nSOQJw+uCxQmYpqptR7TBUIhRf2asdweSU8Pj1K/fqynhG1riR/aYNKxoU +AT6A8EKglQdebc3MS6RFjasS6LPeWuWgfOgPIh1a6Vk= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/geotrustprimarycag2 b/make/data/cacerts/geotrustprimarycag2 new file mode 100644 index 0000000..0d1020a --- /dev/null +++ b/make/data/cacerts/geotrustprimarycag2
@@ -0,0 +1,24 @@ +Owner: CN=GeoTrust Primary Certification Authority - G2, OU=(c) 2007 GeoTrust Inc. - For authorized use only, O=GeoTrust Inc., C=US +Issuer: CN=GeoTrust Primary Certification Authority - G2, OU=(c) 2007 GeoTrust Inc. - For authorized use only, O=GeoTrust Inc., C=US +Serial number: 3cb2f4480a00e2feeb243b5e603ec36b +Valid from: Mon Nov 05 00:00:00 GMT 2007 until: Mon Jan 18 23:59:59 GMT 2038 +Signature algorithm name: SHA384withECDSA +Subject Public Key Algorithm: 384-bit EC (secp384r1) key +Version: 3 +-----BEGIN CERTIFICATE----- +MIICrjCCAjWgAwIBAgIQPLL0SAoA4v7rJDteYD7DazAKBggqhkjOPQQDAzCBmDEL +MAkGA1UEBhMCVVMxFjAUBgNVBAoTDUdlb1RydXN0IEluYy4xOTA3BgNVBAsTMChj +KSAyMDA3IEdlb1RydXN0IEluYy4gLSBGb3IgYXV0aG9yaXplZCB1c2Ugb25seTE2 +MDQGA1UEAxMtR2VvVHJ1c3QgUHJpbWFyeSBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0 +eSAtIEcyMB4XDTA3MTEwNTAwMDAwMFoXDTM4MDExODIzNTk1OVowgZgxCzAJBgNV +BAYTAlVTMRYwFAYDVQQKEw1HZW9UcnVzdCBJbmMuMTkwNwYDVQQLEzAoYykgMjAw +NyBHZW9UcnVzdCBJbmMuIC0gRm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxNjA0BgNV +BAMTLUdlb1RydXN0IFByaW1hcnkgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkgLSBH +MjB2MBAGByqGSM49AgEGBSuBBAAiA2IABBWx6P0DFUPlrOuHNxFi79KDNlJ9RVcL +So17VDs6bl8VAsBQps8lL33KSLjHUGMcKiEIfJo22Av+0SbFWDEwKCXzXV2juLal +tJLtbCyf691DiaI8S0iRHVDsJt/WYC69IaNCMEAwDwYDVR0TAQH/BAUwAwEB/zAO +BgNVHQ8BAf8EBAMCAQYwHQYDVR0OBBYEFBVfNVdRVfslsq0DafwBo/q+EVXVMAoG +CCqGSM49BAMDA2cAMGQCMGSWWaboCd6LuvpaiIjwH5HTRqjySkwCY/tsXzjbLkGT +qQ7mndwxHLKgpxgceeHHNgIwOlavmnRs9vuD4DPTCF+hnMJbn0bWtsuRBmOiBucz +rD6ogRLQy7rQkgu2npaqBA+K +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/geotrustprimarycag3 b/make/data/cacerts/geotrustprimarycag3 new file mode 100644 index 0000000..1ccb56f --- /dev/null +++ b/make/data/cacerts/geotrustprimarycag3
@@ -0,0 +1,31 @@ +Owner: CN=GeoTrust Primary Certification Authority - G3, OU=(c) 2008 GeoTrust Inc. - For authorized use only, O=GeoTrust Inc., C=US +Issuer: CN=GeoTrust Primary Certification Authority - G3, OU=(c) 2008 GeoTrust Inc. - For authorized use only, O=GeoTrust Inc., C=US +Serial number: 15ac6e9419b2794b41f627a9c3180f1f +Valid from: Wed Apr 02 00:00:00 GMT 2008 until: Tue Dec 01 23:59:59 GMT 2037 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIID/jCCAuagAwIBAgIQFaxulBmyeUtB9iepwxgPHzANBgkqhkiG9w0BAQsFADCB +mDELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUdlb1RydXN0IEluYy4xOTA3BgNVBAsT +MChjKSAyMDA4IEdlb1RydXN0IEluYy4gLSBGb3IgYXV0aG9yaXplZCB1c2Ugb25s +eTE2MDQGA1UEAxMtR2VvVHJ1c3QgUHJpbWFyeSBDZXJ0aWZpY2F0aW9uIEF1dGhv +cml0eSAtIEczMB4XDTA4MDQwMjAwMDAwMFoXDTM3MTIwMTIzNTk1OVowgZgxCzAJ +BgNVBAYTAlVTMRYwFAYDVQQKEw1HZW9UcnVzdCBJbmMuMTkwNwYDVQQLEzAoYykg +MjAwOCBHZW9UcnVzdCBJbmMuIC0gRm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxNjA0 +BgNVBAMTLUdlb1RydXN0IFByaW1hcnkgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkg +LSBHMzCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBANziXmJYHTNXOTIz ++uvLh4yn1ErdBojqZI4xmKU4kB6Yzy5jK/BGvESyiaHAKAxJcCGVn2TAppMSAmUm +hsalifD614SgcK9PGpc/BkTVyetyEH3kMSj7HGHmKAdEc5IiaacDiGydY8hS2pgn +5whMcD60yRLBxWeDXTPzAxHsatBT4tG6NmCUgLthY2xbF37fQJQeqw3CIShwiP/W +JmxsYAQlTlV+fe+/lEjetx3dcI0FX4ilm/LC7urRQEFtYjgdVgbFA0dRIBn8exAL +DmKudlW/X3e+PkkBUz2YJQN2JFodtNuJ6nnltrM7P7pMKEF/BqxqjsHQ9gUdfeZC +huOl1UcCAwEAAaNCMEAwDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYw +HQYDVR0OBBYEFMR5yo6hTgMdHNxr2zFblD4/MH8tMA0GCSqGSIb3DQEBCwUAA4IB +AQAtxRPPVoB7eni9n64smefv2t+UXglpp+duaIy9cr5HqQ6XErhK8WTTOd8lNNTB +zU6B8A8ExCSzNJbGpqow32hhc9f5joWJ7w5elShKKiePEI4ufIbEAp7aDHdlDkQN +kv39sxY2+hENHYwOB4lqKVb3cvTdFZx3NWZXqxNT2I7BQMXXExZacse3aQHEerGD +AWh9jUGhlBjBJVz88P6DAod8DQ3PLghcSkANPuyBYeYk28rgDi0Hsj5W3I31QYUH +SJsMC8tJP33st/3LjWeJGqvtux6jAAgIFyqCXDFdRootD4abdNlF+9RAsXqqaC2G +spki4cErx5z481+oghLrGREt +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/geotrustuniversalca b/make/data/cacerts/geotrustuniversalca new file mode 100644 index 0000000..6e049bf --- /dev/null +++ b/make/data/cacerts/geotrustuniversalca
@@ -0,0 +1,38 @@ +Owner: CN=GeoTrust Universal CA, O=GeoTrust Inc., C=US +Issuer: CN=GeoTrust Universal CA, O=GeoTrust Inc., C=US +Serial number: 1 +Valid from: Thu Mar 04 05:00:00 GMT 2004 until: Sun Mar 04 05:00:00 GMT 2029 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFaDCCA1CgAwIBAgIBATANBgkqhkiG9w0BAQUFADBFMQswCQYDVQQGEwJVUzEW +MBQGA1UEChMNR2VvVHJ1c3QgSW5jLjEeMBwGA1UEAxMVR2VvVHJ1c3QgVW5pdmVy +c2FsIENBMB4XDTA0MDMwNDA1MDAwMFoXDTI5MDMwNDA1MDAwMFowRTELMAkGA1UE +BhMCVVMxFjAUBgNVBAoTDUdlb1RydXN0IEluYy4xHjAcBgNVBAMTFUdlb1RydXN0 +IFVuaXZlcnNhbCBDQTCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAKYV +VaCjxuAfjJ0hUNfBvitbtaSeodlyWL0AG0y/YckUHUWCq8YdgNY96xCcOq9tJPi8 +cQGeBvV8Xx7BDlXKg5pZMK4ZyzBIle0iN430SppyZj6tlcDgFgDgEB8rMQ7XlFTT +QjOgNB0eRXbdT8oYN+yFFXoZCPzVx5zw8qkuEKmS5j1YPakWaDwvdSEYfyh3peFh +F7em6fgemdtzbvQKoiFs7tqqhZJmr/Z6a4LauiIINQ/PQvE1+mrufislzDoR5G2v +c7J2Ha3QsnhnGqQ5HFELZ1aD/ThdDc7d8Lsrlh/eezJS/R27tQahsiFepdaVaH/w +mZ7cRQg+59IJDTWU3YBOU5fXtQlEIGQWFwMCTFMNaN7VqnJNk22CDtucvc+081xd +VHppCZbW2xHBjXWotM85yM48vCR85mLK4b19p71XZQvk/iXttmkQ3CgaRr0BHdCX +teGYO8A3ZNY9lO4L4fUorgtWv3GLIylBjobFS1J72HGrH4oVpjuDWtdYAVHGTEHZ +f9hBZ3KiKN9gg6meyHv8U3NyWfWTehd2Ds735VzZC1U0oqpbtWpU5xPKV+yXbfRe +Bi9Fi1jUIxaS5BZuKGNZMN9QAZxjiRqf2xeUgnA3wySemkfWWspOqGmJch+RbNt+ +nhutxx9z3SxPGWX9f5NAEC7S8O08ni4oPmkmM8V7AgMBAAGjYzBhMA8GA1UdEwEB +/wQFMAMBAf8wHQYDVR0OBBYEFNq7LqqwDLiIJlF0XG0D08DYj3rWMB8GA1UdIwQY +MBaAFNq7LqqwDLiIJlF0XG0D08DYj3rWMA4GA1UdDwEB/wQEAwIBhjANBgkqhkiG +9w0BAQUFAAOCAgEAMXjmx7XfuJRAyXHEqDXsRh3ChfMoWIawC/yOsjmPRFWrZIRc +aanQmjg8+uUfNeVE44B5lGiku8SfPeE0zTBGi1QrlaXv9z+ZhP015s8xxtxqv6fX +IwjhmF7DWgh2qaavdy+3YL1ERmrvl/9zlcGO6JP7/TG37FcREUWbMPEaiDnBTzyn +ANXH/KttgCJwpQzgXQQpAvvLoJHRfNbDflDVnVi+QTjruXU8FdmbyUqDWcDaU/0z +uzYYm4UPFd3uLax2k7nZAY1IEKj79TiG8dsKxr2EoyNB3tZ3b4XUhRxQ4K5RirqN +Pnbiucon8l+f725ZDQbYKxek0nxru18UGkiPGkzns0ccjkxFKyDuSN/n3QmOGKja +QI2SJhFTYXNd673nxE0pN2HrrDktZy4W1vUAg4WhzH92xH3kt0tm7wNFYGm2DFKW +koRepqO1pD4r2czYG0eq8kTaT/kD6PAUyz/zg97QwVTjt+gKN02LIFkDMBmhLMi9 +ER/frslKxfMnZmaGrGiR/9nmUxwPi1xpZQomyB40w11Re9epnAahNt3ViZS82eQt +DF4JbAiXfKM9fJP/P6EUp8+1Xevb2xzEdt+Iub1FBZUbrvxGakyvSOPOrg/Sfuvm +bJxPgWp6ZKy7PtXny3YuxadIwVyQD8vIP/rmMuGNG2+k5o7Y+SlIis5z/iw= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/globalsignca b/make/data/cacerts/globalsignca new file mode 100644 index 0000000..48a7dec --- /dev/null +++ b/make/data/cacerts/globalsignca
@@ -0,0 +1,28 @@ +Owner: CN=GlobalSign Root CA, OU=Root CA, O=GlobalSign nv-sa, C=BE +Issuer: CN=GlobalSign Root CA, OU=Root CA, O=GlobalSign nv-sa, C=BE +Serial number: 40000000001154b5ac394 +Valid from: Tue Sep 01 12:00:00 GMT 1998 until: Fri Jan 28 12:00:00 GMT 2028 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDdTCCAl2gAwIBAgILBAAAAAABFUtaw5QwDQYJKoZIhvcNAQEFBQAwVzELMAkG +A1UEBhMCQkUxGTAXBgNVBAoTEEdsb2JhbFNpZ24gbnYtc2ExEDAOBgNVBAsTB1Jv +b3QgQ0ExGzAZBgNVBAMTEkdsb2JhbFNpZ24gUm9vdCBDQTAeFw05ODA5MDExMjAw +MDBaFw0yODAxMjgxMjAwMDBaMFcxCzAJBgNVBAYTAkJFMRkwFwYDVQQKExBHbG9i +YWxTaWduIG52LXNhMRAwDgYDVQQLEwdSb290IENBMRswGQYDVQQDExJHbG9iYWxT +aWduIFJvb3QgQ0EwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDaDuaZ +jc6j40+Kfvvxi4Mla+pIH/EqsLmVEQS98GPR4mdmzxzdzxtIK+6NiY6arymAZavp +xy0Sy6scTHAHoT0KMM0VjU/43dSMUBUc71DuxC73/OlS8pF94G3VNTCOXkNz8kHp +1Wrjsok6Vjk4bwY8iGlbKk3Fp1S4bInMm/k8yuX9ifUSPJJ4ltbcdG6TRGHRjcdG +snUOhugZitVtbNV4FpWi6cgKOOvyJBNPc1STE4U6G7weNLWLBYy5d4ux2x8gkasJ +U26Qzns3dLlwR5EiUWMWea6xrkEmCMgZK9FGqkjWZCrXgzT/LCrBbBlDSgeF59N8 +9iFo7+ryUp9/k5DPAgMBAAGjQjBAMA4GA1UdDwEB/wQEAwIBBjAPBgNVHRMBAf8E +BTADAQH/MB0GA1UdDgQWBBRge2YaRQ2XyolQL30EzTSo//z9SzANBgkqhkiG9w0B +AQUFAAOCAQEA1nPnfE920I2/7LqivjTFKDK1fPxsnCwrvQmeU79rXqoRSLblCKOz +yj1hTdNGCbM+w6DjY1Ub8rrvrTnhQ7k4o+YviiY776BQVvnGCv04zcQLcFGUl5gE +38NflNUVyRRBnMRddWQVDf9VMOyGj/8N7yy5Y0b2qvzfvGn9LhJIZJrglfCm7ymP +AbEVtQwdpf5pLGkkeB6zpxxxYu7KyJesF12KwvhHhm4qxFYxldBniYUr+WymXUad +DKqC5JlR3XC321Y9YeRq4VzW9v493kHMB65jUr9TU/Qr6cf9tveCX4XSQRjbgbME +HMUfpIBvFSDJ3gyICh3WZlXi/EjJKSZp4A== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/globalsigneccrootcar4 b/make/data/cacerts/globalsigneccrootcar4 new file mode 100644 index 0000000..135c0c0 --- /dev/null +++ b/make/data/cacerts/globalsigneccrootcar4
@@ -0,0 +1,20 @@ +Owner: CN=GlobalSign, O=GlobalSign, OU=GlobalSign ECC Root CA - R4 +Issuer: CN=GlobalSign, O=GlobalSign, OU=GlobalSign ECC Root CA - R4 +Serial number: 2a38a41c960a04de42b228a50be8349802 +Valid from: Tue Nov 13 00:00:00 GMT 2012 until: Tue Jan 19 03:14:07 GMT 2038 +Signature algorithm name: SHA256withECDSA +Subject Public Key Algorithm: 256-bit EC (secp256r1) key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIB4TCCAYegAwIBAgIRKjikHJYKBN5CsiilC+g0mAIwCgYIKoZIzj0EAwIwUDEk +MCIGA1UECxMbR2xvYmFsU2lnbiBFQ0MgUm9vdCBDQSAtIFI0MRMwEQYDVQQKEwpH +bG9iYWxTaWduMRMwEQYDVQQDEwpHbG9iYWxTaWduMB4XDTEyMTExMzAwMDAwMFoX +DTM4MDExOTAzMTQwN1owUDEkMCIGA1UECxMbR2xvYmFsU2lnbiBFQ0MgUm9vdCBD +QSAtIFI0MRMwEQYDVQQKEwpHbG9iYWxTaWduMRMwEQYDVQQDEwpHbG9iYWxTaWdu +MFkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDQgAEuMZ5049sJQ6fLjkZHAOkrprlOQcJ +FspjsbmG+IpXwVfOQvpzofdlQv8ewQCybnMO/8ch5RikqtlxP6jUuc6MHaNCMEAw +DgYDVR0PAQH/BAQDAgEGMA8GA1UdEwEB/wQFMAMBAf8wHQYDVR0OBBYEFFSwe61F +uOJAf/sKbvu+M8k8o4TVMAoGCCqGSM49BAMCA0gAMEUCIQDckqGgE6bPA7DmxCGX +kPoUVy0D7O48027KqGx2vKLeuwIgJ6iFJzWbVsaj8kfSt24bAgAXqmemFZHe+pTs +ewv4n4Q= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/globalsigneccrootcar5 b/make/data/cacerts/globalsigneccrootcar5 new file mode 100644 index 0000000..7156e83 --- /dev/null +++ b/make/data/cacerts/globalsigneccrootcar5
@@ -0,0 +1,21 @@ +Owner: CN=GlobalSign, O=GlobalSign, OU=GlobalSign ECC Root CA - R5 +Issuer: CN=GlobalSign, O=GlobalSign, OU=GlobalSign ECC Root CA - R5 +Serial number: 605949e0262ebb55f90a778a71f94ad86c +Valid from: Tue Nov 13 00:00:00 GMT 2012 until: Tue Jan 19 03:14:07 GMT 2038 +Signature algorithm name: SHA384withECDSA +Subject Public Key Algorithm: 384-bit EC (secp384r1) key +Version: 3 +-----BEGIN CERTIFICATE----- +MIICHjCCAaSgAwIBAgIRYFlJ4CYuu1X5CneKcflK2GwwCgYIKoZIzj0EAwMwUDEk +MCIGA1UECxMbR2xvYmFsU2lnbiBFQ0MgUm9vdCBDQSAtIFI1MRMwEQYDVQQKEwpH +bG9iYWxTaWduMRMwEQYDVQQDEwpHbG9iYWxTaWduMB4XDTEyMTExMzAwMDAwMFoX +DTM4MDExOTAzMTQwN1owUDEkMCIGA1UECxMbR2xvYmFsU2lnbiBFQ0MgUm9vdCBD +QSAtIFI1MRMwEQYDVQQKEwpHbG9iYWxTaWduMRMwEQYDVQQDEwpHbG9iYWxTaWdu +MHYwEAYHKoZIzj0CAQYFK4EEACIDYgAER0UOlvt9Xb/pOdEh+J8LttV7HpI6SFkc +8GIxLcB6KP4ap1yztsyX50XUWPrRd21DosCHZTQKH3rd6zwzocWdTaRvQZU4f8ke +hOvRnkmSh5SHDDqFSmafnVmTTZdhBoZKo0IwQDAOBgNVHQ8BAf8EBAMCAQYwDwYD +VR0TAQH/BAUwAwEB/zAdBgNVHQ4EFgQUPeYpSJvqB8ohREom3m7e0oPQn1kwCgYI +KoZIzj0EAwMDaAAwZQIxAOVpEslu28YxuglB4Zf4+/2a4n0Sye18ZNPLBSWLVtmg +515dTguDnFt2KaAJJiFqYgIwcdK1j1zqO+F4CYWodZI7yFz9SO8NdCKoCOJuxUnO +xwy8p2Fp8fc74SrL+SvzZpA3 +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/globalsignr2ca b/make/data/cacerts/globalsignr2ca new file mode 100644 index 0000000..746d1fa --- /dev/null +++ b/make/data/cacerts/globalsignr2ca
@@ -0,0 +1,29 @@ +Owner: CN=GlobalSign, O=GlobalSign, OU=GlobalSign Root CA - R2 +Issuer: CN=GlobalSign, O=GlobalSign, OU=GlobalSign Root CA - R2 +Serial number: 400000000010f8626e60d +Valid from: Fri Dec 15 08:00:00 GMT 2006 until: Wed Dec 15 08:00:00 GMT 2021 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDujCCAqKgAwIBAgILBAAAAAABD4Ym5g0wDQYJKoZIhvcNAQEFBQAwTDEgMB4G +A1UECxMXR2xvYmFsU2lnbiBSb290IENBIC0gUjIxEzARBgNVBAoTCkdsb2JhbFNp +Z24xEzARBgNVBAMTCkdsb2JhbFNpZ24wHhcNMDYxMjE1MDgwMDAwWhcNMjExMjE1 +MDgwMDAwWjBMMSAwHgYDVQQLExdHbG9iYWxTaWduIFJvb3QgQ0EgLSBSMjETMBEG +A1UEChMKR2xvYmFsU2lnbjETMBEGA1UEAxMKR2xvYmFsU2lnbjCCASIwDQYJKoZI +hvcNAQEBBQADggEPADCCAQoCggEBAKbPJA6+Lm8omUVCxKs+IVSbC9N/hHD6ErPL +v4dfxn+G07IwXNb9rfF73OX4YJYJkhD10FPe+3t+c4isUoh7SqbKSaZeqKeMWhG8 +eoLrvozps6yWJQeXSpkqBy+0Hne/ig+1AnwblrjFuTosvNYSuetZfeLQBoZfXklq +tTleiDTsvHgMCJiEbKjNS7SgfQx5TfC4LcshytVsW33hoCmEofnTlEnLJGKRILzd +C9XZzPnqJworc5HGnRusyMvo4KD0L5CLTfuwNhv2GXqF4G3yYROIXJ/gkwpRl4pa +zq+r1feqCapgvdzZX99yqWATXgAByUr6P6TqBwMhAo6CygPCm48CAwEAAaOBnDCB +mTAOBgNVHQ8BAf8EBAMCAQYwDwYDVR0TAQH/BAUwAwEB/zAdBgNVHQ4EFgQUm+IH +V2ccHsBqBt5ZtJot39wZhi4wNgYDVR0fBC8wLTAroCmgJ4YlaHR0cDovL2NybC5n +bG9iYWxzaWduLm5ldC9yb290LXIyLmNybDAfBgNVHSMEGDAWgBSb4gdXZxwewGoG +3lm0mi3f3BmGLjANBgkqhkiG9w0BAQUFAAOCAQEAmYFThxxol4aR7OBKuEQLq4Gs +J0/WwbgcQ3izDJr86iw8bmEbTUsp9Z8FHSbBuOmDAGJFtqkIk7mpM0sYmsL4h4hO +291xNBrBVNpGP+DTKqttVCL1OmLNIG+6KYnX3ZHu01yiPqFbQfXf5WRDLenVOavS +ot+3i9DAgBkcRcAtjOj4LaR0VknFBbVPFd5uRHg5h6h+u/N5GJG79G+dwfCMNYxd +AfvDbbnvRG15RjF+Cv6pgsH/76tuIMRQyV+dTZsXjAzlAcmgQWpzU/qlULRuJQ/7 +TBj0/VLZjmmx6BEP3ojY+x1J96relc8geMJgEtslQIxq/H5COEBkEveegeGTLg== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/globalsignr3ca b/make/data/cacerts/globalsignr3ca new file mode 100644 index 0000000..44dce02 --- /dev/null +++ b/make/data/cacerts/globalsignr3ca
@@ -0,0 +1,28 @@ +Owner: CN=GlobalSign, O=GlobalSign, OU=GlobalSign Root CA - R3 +Issuer: CN=GlobalSign, O=GlobalSign, OU=GlobalSign Root CA - R3 +Serial number: 4000000000121585308a2 +Valid from: Wed Mar 18 10:00:00 GMT 2009 until: Sun Mar 18 10:00:00 GMT 2029 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDXzCCAkegAwIBAgILBAAAAAABIVhTCKIwDQYJKoZIhvcNAQELBQAwTDEgMB4G +A1UECxMXR2xvYmFsU2lnbiBSb290IENBIC0gUjMxEzARBgNVBAoTCkdsb2JhbFNp +Z24xEzARBgNVBAMTCkdsb2JhbFNpZ24wHhcNMDkwMzE4MTAwMDAwWhcNMjkwMzE4 +MTAwMDAwWjBMMSAwHgYDVQQLExdHbG9iYWxTaWduIFJvb3QgQ0EgLSBSMzETMBEG +A1UEChMKR2xvYmFsU2lnbjETMBEGA1UEAxMKR2xvYmFsU2lnbjCCASIwDQYJKoZI +hvcNAQEBBQADggEPADCCAQoCggEBAMwldpB5BngiFvXAg7aEyiie/QV2EcWtiHL8 +RgJDx7KKnQRfJMsuS+FggkbhUqsMgUdwbN1k0ev1LKMPgj0MK66X17YUhhB5uzsT +gHeMCOFJ0mpiLx9e+pZo34knlTifBtc+ycsmWQ1z3rDI6SYOgxXG71uL0gRgykmm +KPZpO/bLyCiR5Z2KYVc3rHQU3HTgOu5yLy6c+9C7v/U9AOEGM+iCK65TpjoWc4zd +QQ4gOsC0p6Hpsk+QLjJg6VfLuQSSaGjlOCZgdbKfd/+RFO+uIEn8rUAVSNECMWEZ +XriX7613t2Saer9fwRPvm2L7DWzgVGkWqQPabumDk3F2xmmFghcCAwEAAaNCMEAw +DgYDVR0PAQH/BAQDAgEGMA8GA1UdEwEB/wQFMAMBAf8wHQYDVR0OBBYEFI/wS3+o +LkUkrk1Q+mOai97i3Ru8MA0GCSqGSIb3DQEBCwUAA4IBAQBLQNvAUKr+yAzv95ZU +RUm7lgAJQayzE4aGKAczymvmdLm6AC2upArT9fHxD4q/c2dKg8dEe3jgr25sbwMp +jjM5RcOO5LlXbKr8EpbsU8Yt5CRsuZRj+9xTaGdWPoO4zzUhw8lo/s7awlOqzJCK +6fBdRoyV3XpYKBovHd7NADdBj+1EbddTKJd+82cEHhXXipa0095MJ6RMG3NzdvQX +mcIfeg7jLQitChws/zyrVQ4PkX4268NXSb7hLi18YIvDQVETI53O9zJrlAGomecs +Mx86OyXShkDOOyyGeMlhLxS67ttVb9+E7gUJTb0o2HLO02JQZR7rkpeDMdmztcpH +WD9f +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/globalsignrootcar6 b/make/data/cacerts/globalsignrootcar6 new file mode 100644 index 0000000..50f748d --- /dev/null +++ b/make/data/cacerts/globalsignrootcar6
@@ -0,0 +1,39 @@ +Owner: CN=GlobalSign, O=GlobalSign, OU=GlobalSign Root CA - R6 +Issuer: CN=GlobalSign, O=GlobalSign, OU=GlobalSign Root CA - R6 +Serial number: 45e6bb038333c3856548e6ff4551 +Valid from: Wed Dec 10 00:00:00 GMT 2014 until: Sun Dec 10 00:00:00 GMT 2034 +Signature algorithm name: SHA384withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFgzCCA2ugAwIBAgIORea7A4Mzw4VlSOb/RVEwDQYJKoZIhvcNAQEMBQAwTDEg +MB4GA1UECxMXR2xvYmFsU2lnbiBSb290IENBIC0gUjYxEzARBgNVBAoTCkdsb2Jh +bFNpZ24xEzARBgNVBAMTCkdsb2JhbFNpZ24wHhcNMTQxMjEwMDAwMDAwWhcNMzQx +MjEwMDAwMDAwWjBMMSAwHgYDVQQLExdHbG9iYWxTaWduIFJvb3QgQ0EgLSBSNjET +MBEGA1UEChMKR2xvYmFsU2lnbjETMBEGA1UEAxMKR2xvYmFsU2lnbjCCAiIwDQYJ +KoZIhvcNAQEBBQADggIPADCCAgoCggIBAJUH6HPKZvnsFMp7PPcNCPG0RQssgrRI +xutbPK6DuEGSMxSkb3/pKszGsIhrxbaJ0cay/xTOURQh7ErdG1rG1ofuTToVBu1k +ZguSgMpE3nOUTvOniX9PeGMIyBJQbUJmL025eShNUhqKGoC3GYEOfsSKvGRMIRxD +aNc9PIrFsmbVkJq3MQbFvuJtMgamHvm566qjuL++gmNQ0PAYid/kD3n16qIfKtJw +LnvnvJO7bVPiSHyMEAc4/2ayd2F+4OqMPKq0pPbzlUoSB239jLKJz9CgYXfIWHSw +1CM69106yqLbnQneXUQtkPGBzVeS+n68UARjNN9rkxi+azayOeSsJDa38O+2HBNX +k7besvjihbdzorg1qkXy4J02oW9UivFyVm4uiMVRQkQVlO6jxTiWm05OWgtH8wY2 +SXcwvHE35absIQh1/OZhFj931dmRl4QKbNQCTXTAFO39OfuD8l4UoQSwC+n+7o/h +bguyCLNhZglqsQY6ZZZZwPA1/cnaKI0aEYdwgQqomnUdnjqGBQCe24DWJfncBZ4n +WUx2OVvq+aWh2IMP0f/fMBH5hc8zSPXKbWQULHpYT9NLCEnFlWQaYw55PfWzjMpY +rZxCRXluDocZXFSxZba/jJvcE+kNb7gu3GduyYsRtYQUigAZcIN5kZeR1Bonvzce +MgfYFGM8KEyvAgMBAAGjYzBhMA4GA1UdDwEB/wQEAwIBBjAPBgNVHRMBAf8EBTAD +AQH/MB0GA1UdDgQWBBSubAWjkxPioufi1xzWx/B/yGdToDAfBgNVHSMEGDAWgBSu +bAWjkxPioufi1xzWx/B/yGdToDANBgkqhkiG9w0BAQwFAAOCAgEAgyXt6NH9lVLN +nsAEoJFp5lzQhN7craJP6Ed41mWYqVuoPId8AorRbrcWc+ZfwFSY1XS+wc3iEZGt +Ixg93eFyRJa0lV7Ae46ZeBZDE1ZXs6KzO7V33EByrKPrmzU+sQghoefEQzd5Mr61 +55wsTLxDKZmOMNOsIeDjHfrYBzN2VAAiKrlNIC5waNrlU/yDXNOd8v9EDERm8tLj +vUYAGm0CuiVdjaExUd1URhxN25mW7xocBFymFe944Hn+Xds+qkxV/ZoVqW/hpvvf +cDDpw+5CRu3CkwWJ+n1jez/QcYF8AOiYrg54NMMl+68KnyBr3TsTjxKM4kEaSHpz +oHdpx7Zcf4LIHv5YGygrqGytXm3ABdJ7t+uA/iU3/gKbaKxCXcPu9czc8FB10jZp +nOZ7BN9uBmm23goJSFmH63sUYHpkqmlD75HHTOwY3WzvUy2MmeFe8nI+z1TIvWfs +pA9MRf/TuTAjB0yPEL+GltmZWrSZVxykzLsViVO6LAUP5MSeGbEYNNVMnbrt9x+v +JJUEeKgDu+6B5dpffItKoZB0JaezPkvILFa9x8jvOOJckvB595yEunQtYQEgfn7R +8k8HWV+LLUNS60YMlOH1Zkd5d9VUWx+tJDfLRVpOoERIyNiwmcUVhAn21klJwGW4 +5hpxbqCo8YLoRT5s1gLXCmeDBVrJpBA= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/godaddyclass2ca b/make/data/cacerts/godaddyclass2ca new file mode 100644 index 0000000..a5f5746 --- /dev/null +++ b/make/data/cacerts/godaddyclass2ca
@@ -0,0 +1,31 @@ +Owner: OU=Go Daddy Class 2 Certification Authority, O="The Go Daddy Group, Inc.", C=US +Issuer: OU=Go Daddy Class 2 Certification Authority, O="The Go Daddy Group, Inc.", C=US +Serial number: 0 +Valid from: Tue Jun 29 17:06:20 GMT 2004 until: Thu Jun 29 17:06:20 GMT 2034 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEADCCAuigAwIBAgIBADANBgkqhkiG9w0BAQUFADBjMQswCQYDVQQGEwJVUzEh +MB8GA1UEChMYVGhlIEdvIERhZGR5IEdyb3VwLCBJbmMuMTEwLwYDVQQLEyhHbyBE +YWRkeSBDbGFzcyAyIENlcnRpZmljYXRpb24gQXV0aG9yaXR5MB4XDTA0MDYyOTE3 +MDYyMFoXDTM0MDYyOTE3MDYyMFowYzELMAkGA1UEBhMCVVMxITAfBgNVBAoTGFRo +ZSBHbyBEYWRkeSBHcm91cCwgSW5jLjExMC8GA1UECxMoR28gRGFkZHkgQ2xhc3Mg +MiBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTCCASAwDQYJKoZIhvcNAQEBBQADggEN +ADCCAQgCggEBAN6d1+pXGEmhW+vXX0iG6r7d/+TvZxz0ZWizV3GgXne77ZtJ6XCA +PVYYYwhv2vLM0D9/AlQiVBDYsoHUwHU9S3/Hd8M+eKsaA7Ugay9qK7HFiH7Eux6w +wdhFJ2+qN1j3hybX2C32qRe3H3I2TqYXP2WYktsqbl2i/ojgC95/5Y0V4evLOtXi +EqITLdiOr18SPaAIBQi2XKVlOARFmR6jYGB0xUGlcmIbYsUfb18aQr4CUWWoriMY +avx4A6lNf4DD+qta/KFApMoZFv6yyO9ecw3ud72a9nmYvLEHZ6IVDd2gWMZEewo+ +YihfukEHU1jPEX44dMX4/7VpkI+EdOqXG68CAQOjgcAwgb0wHQYDVR0OBBYEFNLE +sNKR1EwRcbNhyz2h/t2oatTjMIGNBgNVHSMEgYUwgYKAFNLEsNKR1EwRcbNhyz2h +/t2oatTjoWekZTBjMQswCQYDVQQGEwJVUzEhMB8GA1UEChMYVGhlIEdvIERhZGR5 +IEdyb3VwLCBJbmMuMTEwLwYDVQQLEyhHbyBEYWRkeSBDbGFzcyAyIENlcnRpZmlj +YXRpb24gQXV0aG9yaXR5ggEAMAwGA1UdEwQFMAMBAf8wDQYJKoZIhvcNAQEFBQAD +ggEBADJL87LKPpH8EsahB4yOd6AzBhRckB4Y9wimPQoZ+YeAEW5p5JYXMP80kWNy +OO7MHAGjHZQopDH2esRU1/blMVgDoszOYtuURXO1v0XJJLXVggKtI3lpjbi2Tc7P +TMozI+gciKqdi0FuFskg5YmezTvacPd+mSYgFFQlq25zheabIZ0KbIIOqPjCDPoQ +HmyW74cNxA9hi63ugyuV+I6ShHI56yDqg+2DzZduCLzrTia2cyvk0/ZM/iZx4mER +dEr/VxqHD3VILs9RaRegAhJhldXRQLIQTO7ErBBDpqWeCtWVYpoNz4iCxTIM5Cuf +ReYNnyicsbkqWletNw+vHX/bvZ8= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/godaddyrootg2ca b/make/data/cacerts/godaddyrootg2ca new file mode 100644 index 0000000..5d60b36 --- /dev/null +++ b/make/data/cacerts/godaddyrootg2ca
@@ -0,0 +1,30 @@ +Owner: CN=Go Daddy Root Certificate Authority - G2, O="GoDaddy.com, Inc.", L=Scottsdale, ST=Arizona, C=US +Issuer: CN=Go Daddy Root Certificate Authority - G2, O="GoDaddy.com, Inc.", L=Scottsdale, ST=Arizona, C=US +Serial number: 0 +Valid from: Tue Sep 01 00:00:00 GMT 2009 until: Thu Dec 31 23:59:59 GMT 2037 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDxTCCAq2gAwIBAgIBADANBgkqhkiG9w0BAQsFADCBgzELMAkGA1UEBhMCVVMx +EDAOBgNVBAgTB0FyaXpvbmExEzARBgNVBAcTClNjb3R0c2RhbGUxGjAYBgNVBAoT +EUdvRGFkZHkuY29tLCBJbmMuMTEwLwYDVQQDEyhHbyBEYWRkeSBSb290IENlcnRp +ZmljYXRlIEF1dGhvcml0eSAtIEcyMB4XDTA5MDkwMTAwMDAwMFoXDTM3MTIzMTIz +NTk1OVowgYMxCzAJBgNVBAYTAlVTMRAwDgYDVQQIEwdBcml6b25hMRMwEQYDVQQH +EwpTY290dHNkYWxlMRowGAYDVQQKExFHb0RhZGR5LmNvbSwgSW5jLjExMC8GA1UE +AxMoR28gRGFkZHkgUm9vdCBDZXJ0aWZpY2F0ZSBBdXRob3JpdHkgLSBHMjCCASIw +DQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAL9xYgjx+lk09xvJGKP3gElY6SKD +E6bFIEMBO4Tx5oVJnyfq9oQbTqC023CYxzIBsQU+B07u9PpPL1kwIuerGVZr4oAH +/PMWdYA5UXvl+TW2dE6pjYIT5LY/qQOD+qK+ihVqf94Lw7YZFAXK6sOoBJQ7Rnwy +DfMAZiLIjWltNowRGLfTshxgtDj6AozO091GB94KPutdfMh8+7ArU6SSYmlRJQVh +GkSBjCypQ5Yj36w6gZoOKcUcqeldHraenjAKOc7xiID7S13MMuyFYkMlNAJWJwGR +tDtwKj9useiciAF9n9T521NtYJ2/LOdYq7hfRvzOxBsDPAnrSTFcaUaz4EcCAwEA +AaNCMEAwDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwHQYDVR0OBBYE +FDqahQcQZyi27/a9BUFuIMGU2g/eMA0GCSqGSIb3DQEBCwUAA4IBAQCZ21151fmX +WWcDYfF+OwYxdS2hII5PZYe096acvNjpL9DbWu7PdIxztDhC2gV7+AJ1uP2lsdeu +9tfeE8tTEH6KRtGX+rcuKxGrkLAngPnon1rpN5+r5N9ss4UXnT3ZJE95kTXWXwTr +gIOrmgIttRD02JDHBHNA7XIloKmf7J6raBKZV8aPEjoJpL1E/QYVN8Gb5DKj7Tjo +2GTzLH4U/ALqn83/B2gX2yKQOC16jdFU8WnjXzPKej17CuPKf1855eJ1usV2GDPO +LPAvTK33sefOT6jEm0pUBsV/fdUID+Ic/n4XuKxe9tQWskMJDE32p2u0mYRlynqI +4uJEvlz36hz1 +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/haricaeccrootca2015 b/make/data/cacerts/haricaeccrootca2015 new file mode 100644 index 0000000..8a0b70b --- /dev/null +++ b/make/data/cacerts/haricaeccrootca2015
@@ -0,0 +1,24 @@ +Owner: CN=Hellenic Academic and Research Institutions ECC RootCA 2015, O=Hellenic Academic and Research Institutions Cert. Authority, L=Athens, C=GR +Issuer: CN=Hellenic Academic and Research Institutions ECC RootCA 2015, O=Hellenic Academic and Research Institutions Cert. Authority, L=Athens, C=GR +Serial number: 0 +Valid from: Tue Jul 07 10:37:12 GMT 2015 until: Sat Jun 30 10:37:12 GMT 2040 +Signature algorithm name: SHA256withECDSA +Subject Public Key Algorithm: 384-bit EC key +Version: 3 +-----BEGIN CERTIFICATE----- +MIICwzCCAkqgAwIBAgIBADAKBggqhkjOPQQDAjCBqjELMAkGA1UEBhMCR1IxDzAN +BgNVBAcTBkF0aGVuczFEMEIGA1UEChM7SGVsbGVuaWMgQWNhZGVtaWMgYW5kIFJl +c2VhcmNoIEluc3RpdHV0aW9ucyBDZXJ0LiBBdXRob3JpdHkxRDBCBgNVBAMTO0hl +bGxlbmljIEFjYWRlbWljIGFuZCBSZXNlYXJjaCBJbnN0aXR1dGlvbnMgRUNDIFJv +b3RDQSAyMDE1MB4XDTE1MDcwNzEwMzcxMloXDTQwMDYzMDEwMzcxMlowgaoxCzAJ +BgNVBAYTAkdSMQ8wDQYDVQQHEwZBdGhlbnMxRDBCBgNVBAoTO0hlbGxlbmljIEFj +YWRlbWljIGFuZCBSZXNlYXJjaCBJbnN0aXR1dGlvbnMgQ2VydC4gQXV0aG9yaXR5 +MUQwQgYDVQQDEztIZWxsZW5pYyBBY2FkZW1pYyBhbmQgUmVzZWFyY2ggSW5zdGl0 +dXRpb25zIEVDQyBSb290Q0EgMjAxNTB2MBAGByqGSM49AgEGBSuBBAAiA2IABJKg +QehLgoRc4vgxEZmGZE4JJS+dQS8KrjVPdJWyUWRrjWvmP3CV8AVER6ZyOFB2lQJa +jq4onvktTpnvLEhvTCUp6NFxW98dwXU3tNf6e3pCnGoKVlp8aQuqgAkkbH7BRqNC +MEAwDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwHQYDVR0OBBYEFLQi +C4KZJAEOnLvkDv2/+5cgk5kqMAoGCCqGSM49BAMCA2cAMGQCMGfOFmI4oqxiRaep +lSTAGiecMjvAwNW6qef4BENThe5SId6d9SWDPp5YSy/XZxMOIQIwBeF1Ad5o7Sof +TUwJCA3sS61kFyjndc5FZXIhF8siQQ6ME5g4mlRtm8rifOoCWCKR +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/haricarootca2015 b/make/data/cacerts/haricarootca2015 new file mode 100644 index 0000000..b75ed0c --- /dev/null +++ b/make/data/cacerts/haricarootca2015
@@ -0,0 +1,42 @@ +Owner: CN=Hellenic Academic and Research Institutions RootCA 2015, O=Hellenic Academic and Research Institutions Cert. Authority, L=Athens, C=GR +Issuer: CN=Hellenic Academic and Research Institutions RootCA 2015, O=Hellenic Academic and Research Institutions Cert. Authority, L=Athens, C=GR +Serial number: 0 +Valid from: Tue Jul 07 10:11:21 GMT 2015 until: Sat Jun 30 10:11:21 GMT 2040 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIGCzCCA/OgAwIBAgIBADANBgkqhkiG9w0BAQsFADCBpjELMAkGA1UEBhMCR1Ix +DzANBgNVBAcTBkF0aGVuczFEMEIGA1UEChM7SGVsbGVuaWMgQWNhZGVtaWMgYW5k +IFJlc2VhcmNoIEluc3RpdHV0aW9ucyBDZXJ0LiBBdXRob3JpdHkxQDA+BgNVBAMT +N0hlbGxlbmljIEFjYWRlbWljIGFuZCBSZXNlYXJjaCBJbnN0aXR1dGlvbnMgUm9v +dENBIDIwMTUwHhcNMTUwNzA3MTAxMTIxWhcNNDAwNjMwMTAxMTIxWjCBpjELMAkG +A1UEBhMCR1IxDzANBgNVBAcTBkF0aGVuczFEMEIGA1UEChM7SGVsbGVuaWMgQWNh +ZGVtaWMgYW5kIFJlc2VhcmNoIEluc3RpdHV0aW9ucyBDZXJ0LiBBdXRob3JpdHkx +QDA+BgNVBAMTN0hlbGxlbmljIEFjYWRlbWljIGFuZCBSZXNlYXJjaCBJbnN0aXR1 +dGlvbnMgUm9vdENBIDIwMTUwggIiMA0GCSqGSIb3DQEBAQUAA4ICDwAwggIKAoIC +AQDC+Kk/G4n8PDwEXT2QNrCROnk8ZlrvbTkBSRq0t89/TSNTt5AA4xMqKKYx8ZEA +4yjsriFBzh/a/X0SWwGDD7mwX5nh8hKDgE0GPt+sr+ehiGsxr/CL0BgzuNtFajT0 +AoAkKAoCFZVedioNmToUW/bLy1O8E00BiDeUJRtCvCLYjqOWXjrZMts+6PAQZe10 +4S+nfK8nNLspfZu2zwnI5dMK/IhlZXQK3HMcXM1AsRzUtoSMTFDPaI6oWa7CJ06C +ojXdFPQf/7J31Ycvqm59JCfnxssm5uX+Zwdj2EUN3TpZZTlYepKZcj2chF6IIbjV +9Cz82XBST3i4vTwri5WY9bPRaM8gFH5MXF/ni+X1NYEZN9cRCLdmvtNKzoNXADrD +gfgXy5I2XdGj2HUb4Ysn6npIQf1FGQatJ5lOwXBH3bWfgVMS5bGMSF0xQxfjjMZ6 +Y5ZLKTBOhE5iGV48zpeQpX8B653g+IuJ3SWYPZK2fu/Z8VFRfS0myGlZYeCsargq +NhEEelC9MoS+L9xy1dcdFkfkR2YgP/SWxa+OAXqlD3pk9Q0Yh9muiNX6hME6wGko +LfINaFGq46V3xqSQDqE3izEjR8EJCOtu93ib14L8hCCZSRm2Ekax+0VVFqmjZayc +Bw/qa9wfLgZy7IaIEuQt218FL+TwA9MmM+eAws1CoRc0CwIDAQABo0IwQDAPBgNV +HRMBAf8EBTADAQH/MA4GA1UdDwEB/wQEAwIBBjAdBgNVHQ4EFgQUcRVnyMjJvXVd +ctA4GGqd83EkVAswDQYJKoZIhvcNAQELBQADggIBAHW7bVRLqhBYRjTyYtcWNl0I +XtVsyIe9tC5G8jH4fOpCtZMWVdyhDBKg2mF+D1hYc2Ryx+hFjtyp8iY/xnmMsVMI +M4GwVhO+5lFc2JsKT0ucVlMC6U/2DWDqTUJV6HwbISHTGzrMd/K4kPFox/la/vot +9L/J9UUbzjgQKjeKeaO04wlshYaT/4mWJ3iBj2fjRnRUjtkNaeJK9E10A/+yd+2V +Z5fkscWrv2oj6NSU4kQoYsRL4vDY4ilrGnB+JGGTe08DMiUNRSQrlrRGar9KC/ea +j8GsGsVn82800vpzY4zvFrCopEYq+OsS7HK07/grfoxSwIuEVPkvPuNVqNxmsdnh +X9izjFk0WaSrT2y7HxjbdavYy5LNlDhhDgcGH0tGEPEVvo2FXDtKK4F5D7Rpn0lQ +l033DlZdwJVqwjbDG2jJ9SrcR5q+ss7FJej6A7na+RZukYT1HCjI/CbM1xyQVqdf +bzoEvM14iQuODy+jqk+iGxI9FghAD/FGTNeqewjBCvVtJ94Cj8rDtSvK6evIIVM4 +pcw72Hc3MKJP2W/R8kCtQXoXxdZKNYm3QdV8hn9VTYNKpXMgwDqvkPGaJI7ZjnHK +e7iG2rKPmT4dEw0SEe7Uq/DpFXYC5ODfqiAeW2GFZECpkJcNrVPSWh2HagCXZWK0 +vm9qp/UsQu0yrbYhnr68 +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/identrustcommercial b/make/data/cacerts/identrustcommercial new file mode 100644 index 0000000..8623d4b --- /dev/null +++ b/make/data/cacerts/identrustcommercial
@@ -0,0 +1,38 @@ +Owner: CN=IdenTrust Commercial Root CA 1, O=IdenTrust, C=US +Issuer: CN=IdenTrust Commercial Root CA 1, O=IdenTrust, C=US +Serial number: a0142800000014523c844b500000002 +Valid from: Thu Jan 16 18:12:23 GMT 2014 until: Mon Jan 16 18:12:23 GMT 2034 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFYDCCA0igAwIBAgIQCgFCgAAAAUUjyES1AAAAAjANBgkqhkiG9w0BAQsFADBK +MQswCQYDVQQGEwJVUzESMBAGA1UEChMJSWRlblRydXN0MScwJQYDVQQDEx5JZGVu +VHJ1c3QgQ29tbWVyY2lhbCBSb290IENBIDEwHhcNMTQwMTE2MTgxMjIzWhcNMzQw +MTE2MTgxMjIzWjBKMQswCQYDVQQGEwJVUzESMBAGA1UEChMJSWRlblRydXN0MScw +JQYDVQQDEx5JZGVuVHJ1c3QgQ29tbWVyY2lhbCBSb290IENBIDEwggIiMA0GCSqG +SIb3DQEBAQUAA4ICDwAwggIKAoICAQCnUBneP5k91DNG8W9RYYKyqU+PZ4ldhNlT +3Qwo2dfw/66VQ3KZ+bVdfIrBQuExUHTRgQ18zZshq0PirK1ehm7zCYofWjK9ouuU ++ehcCuz/mNKvcbO0U59Oh++SvL3sTzIwiEsXXlfEU8L2ApeN2WIrvyQfYo3fw7gp +S0l4PJNgiCL8mdo2yMKi1CxUAGc1bnO/AljwpN3lsKImesrgNqUZFvX9t++uP0D1 +bVoE/c40yiTcdCMbXTMTEl3EASX2MN0CXZ/g1Ue9tOsbobtJSdifWwLziuQkkORi +T0/Br4sOdBeo0XKIanoBScy0RnnGF7HamB4HWfp1IYVl3ZBWzvurpWCdxJ35UrCL +vYf5jysjCiN2O/cz4ckA82n5S6LgTrx+kzmEB/dEcH7+B1rlsazRGMzyNeVJSQjK +Vsk9+w8YfYs7wRPCTY/JTw436R+hDmrfYi7LNQZReSzIJTj0+kuniVyc0uMNOYZK +dHzVWYfCP04MXFL0PfdSgvHqo6z9STQaKPNBiDoT7uje/5kdX7rL6B7yuVBgwDHT +c+XvvqDtMwt0viAgxGds8AgDelWAf0ZOlqf0Hj7h9tgJ4TNkK2PXMl6f+cB7D3hv +l7yTmvmcEpB4eoCHFddydJxVdHixuuFucAS6T6C6aMN7/zHwcz09lCqxC0EOoP5N +iGVreTO01wIDAQABo0IwQDAOBgNVHQ8BAf8EBAMCAQYwDwYDVR0TAQH/BAUwAwEB +/zAdBgNVHQ4EFgQU7UQZwNPwBovupHu+QucmVMiONnYwDQYJKoZIhvcNAQELBQAD +ggIBAA2ukDL2pkt8RHYZYR4nKM1eVO8lvOMIkPkp165oCOGUAFjvLi5+U1KMtlwH +6oi6mYtQlNeCgN9hCQCTrQ0U5s7B8jeUeLBfnLOic7iPBZM4zY0+sLj7wM+x8uwt +LRvM7Kqas6pgghstO8OEPVeKlh6cdbjTMM1gCIOQ045U8U1mwF10A0Cj7oV+wh93 +nAbowacYXVKV7cndJZ5t+qntozo00Fl72u1Q8zW/7esUTTHHYPTa8Yec4kjixsU3 ++wYQ+nVZZjFHKdp2mhzpgq7vmrlR94gjmmmVYjzlVYA211QC//G5Xc7UI2/YRYRK +W2XviQzdFKcgyxilJbQN+QHwotL0AMh0jqEqSI5l2xPE4iUXfeu+h1sXIFRRk0pT +AwvsXcoz7WL9RccvW9xYoIA55vrX/hMUpu09lEpCdNTDd1lzzY9GvlU47/rokTLq +l1gEIt44w8y8bckzOmoKaT+gyOpyj4xjhiO9bTyWnpXgSUyqorkqG5w2gXjtw+hG +4iZZRHUe2XWJUc0QhJ1hYMtd+ZciTY6Y5uN/9lu7rs3KSoFrXgvzUeF0K+l+J6fZ +mUlO+KWA2yUPHGNiiskzZ2s8EIPGrd6ozRaOjfAHN3Gf8qv8QfXBi+wAN10J5U6A +7/qxXDgGpRtK4dw4LTzcqx+QGtVKnO7RcGzM7vRX+Bi6hG6H +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/identrustpublicca b/make/data/cacerts/identrustpublicca new file mode 100644 index 0000000..f4034ea --- /dev/null +++ b/make/data/cacerts/identrustpublicca
@@ -0,0 +1,38 @@ +Owner: CN=IdenTrust Public Sector Root CA 1, O=IdenTrust, C=US +Issuer: CN=IdenTrust Public Sector Root CA 1, O=IdenTrust, C=US +Serial number: a0142800000014523cf467c00000002 +Valid from: Thu Jan 16 17:53:32 GMT 2014 until: Mon Jan 16 17:53:32 GMT 2034 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFZjCCA06gAwIBAgIQCgFCgAAAAUUjz0Z8AAAAAjANBgkqhkiG9w0BAQsFADBN +MQswCQYDVQQGEwJVUzESMBAGA1UEChMJSWRlblRydXN0MSowKAYDVQQDEyFJZGVu +VHJ1c3QgUHVibGljIFNlY3RvciBSb290IENBIDEwHhcNMTQwMTE2MTc1MzMyWhcN +MzQwMTE2MTc1MzMyWjBNMQswCQYDVQQGEwJVUzESMBAGA1UEChMJSWRlblRydXN0 +MSowKAYDVQQDEyFJZGVuVHJ1c3QgUHVibGljIFNlY3RvciBSb290IENBIDEwggIi +MA0GCSqGSIb3DQEBAQUAA4ICDwAwggIKAoICAQC2IpT8pEiv6EdrCvsnduTyP4o7 +ekosMSqMjbCpwzFrqHd2hCa2rIFCDQjrVVi7evi8ZX3yoG2LqEfpYnYeEe4IFNGy +RBb06tD6Hi9e28tzQa68ALBKK0CyrOE7S8ItneShm+waOh7wCLPQ5CQ1B5+ctMlS +bdsHyo+1W/CD80/HLaXIrcuVIKQxKFdYWuSNG5qrng0M8gozOSI5Cpcu81N3uURF +/YTLNiCBWS2ab21ISGHKTN9T0a9SvESfqy9rg3LvdYDaBjMbXcjaY8ZNzaxmMc3R +3j6HEDbhuaR672BQssvKplbgN6+rNBM5Jeg5ZuSYeqoSmJxZZoY+rfGwyj4GD3vw +EUs3oERte8uojHH01bWRNszwFcYr3lEXsZdMUD2xlVl8BX0tIdUAvwFnol57plzy +9yLxkA2T26pEUWbMfXYD62qoKjgZl3YNa4ph+bz27nb9cCvdKTz4Ch5bQhyLVi9V +GxyhLrXHFub4qjySjmm2AcG1hp2JDws4lFTo6tyePSW8Uybt1as5qsVATFSrsrTZ +2fjXctscvG29ZV/viDUqZi/u9rNl8DONfJhBaUYPQxxp+pu10GFqzcpL2UyQRqsV +WaFHVCkugyhfHMKiq3IXAAaOReyL4jM9f9oZRORicsPfIsbyVtTdX5Vy7W1f90gD +W/3FKqD2cyOEEBsB5wIDAQABo0IwQDAOBgNVHQ8BAf8EBAMCAQYwDwYDVR0TAQH/ +BAUwAwEB/zAdBgNVHQ4EFgQU43HgntinQtnbcZFrlJPrw6PRFKMwDQYJKoZIhvcN +AQELBQADggIBAEf63QqwEZE4rU1d9+UOl1QZgkiHVIyqZJnYWv6IAcVYpZmxI1Qj +t2odIFflAWJBF9MJ23XLblSQdf4an4EKwt3X9wnQW3IV5B4Jaj0z8yGa5hV+rVHV +DRDtfULAj+7AmgjVQdZcDiFpboBhDhXAuM/FSRJSzL46zNQuOAXeNf0fb7iAaJg9 +TaDKQGXSc3z1i9kKlT/YPyNtGtEqJBnZhbMX73huqVjRI9PHE+1yJX9dsXNw0H8G +lwmEKYBhHfpe/3OsoOOJuBxxFcbeMX8S3OFtm6/n6J91eEyrRjuazr8FGF1NFTwW +mhlQBJqymm9li1JfPFgEKCXAZmExfrngdbkaqIHWchezxQMxNRF4eKLg6TCMf4Df +WN88uieW4oA0beOY02QnrEh+KHdcxiVhJfiFDGX6xDIvpZgF5PgLZxYWxoK4Mhn5 ++bl53B/N66+rDt0b20XkeucC4pVd/GnwU2lhlXV5C15V5jgclKlZM57IcXR5f1GJ +tshquDDIajjDbp7hNxbqBWJMWxJH7ae0s1hWx0nzfxJoCTFx8G34Tkf71oXuxVhA +GaQdp/lLQzfcaFpPz+vCZHTetBXZ9FRUGi8c15dxVJCO2SCdUyt/q4/i6jC8UDfv +8Ue1fXwsBOxonbRJRBD0ckscZOf85muQ3Wl9af0AVqW3rLatt8o+Ae+c +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/letsencryptisrgx1 b/make/data/cacerts/letsencryptisrgx1 new file mode 100644 index 0000000..9364e1d --- /dev/null +++ b/make/data/cacerts/letsencryptisrgx1
@@ -0,0 +1,38 @@ +Owner: CN=ISRG Root X1, O=Internet Security Research Group, C=US +Issuer: CN=ISRG Root X1, O=Internet Security Research Group, C=US +Serial number: 8210cfb0d240e3594463e0bb63828b00 +Valid from: Thu Jun 04 11:04:38 GMT 2015 until: Mon Jun 04 11:04:38 GMT 2035 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFazCCA1OgAwIBAgIRAIIQz7DSQONZRGPgu2OCiwAwDQYJKoZIhvcNAQELBQAw +TzELMAkGA1UEBhMCVVMxKTAnBgNVBAoTIEludGVybmV0IFNlY3VyaXR5IFJlc2Vh +cmNoIEdyb3VwMRUwEwYDVQQDEwxJU1JHIFJvb3QgWDEwHhcNMTUwNjA0MTEwNDM4 +WhcNMzUwNjA0MTEwNDM4WjBPMQswCQYDVQQGEwJVUzEpMCcGA1UEChMgSW50ZXJu +ZXQgU2VjdXJpdHkgUmVzZWFyY2ggR3JvdXAxFTATBgNVBAMTDElTUkcgUm9vdCBY +MTCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAK3oJHP0FDfzm54rVygc +h77ct984kIxuPOZXoHj3dcKi/vVqbvYATyjb3miGbESTtrFj/RQSa78f0uoxmyF+ +0TM8ukj13Xnfs7j/EvEhmkvBioZxaUpmZmyPfjxwv60pIgbz5MDmgK7iS4+3mX6U +A5/TR5d8mUgjU+g4rk8Kb4Mu0UlXjIB0ttov0DiNewNwIRt18jA8+o+u3dpjq+sW +T8KOEUt+zwvo/7V3LvSye0rgTBIlDHCNAymg4VMk7BPZ7hm/ELNKjD+Jo2FR3qyH +B5T0Y3HsLuJvW5iB4YlcNHlsdu87kGJ55tukmi8mxdAQ4Q7e2RCOFvu396j3x+UC +B5iPNgiV5+I3lg02dZ77DnKxHZu8A/lJBdiB3QW0KtZB6awBdpUKD9jf1b0SHzUv +KBds0pjBqAlkd25HN7rOrFleaJ1/ctaJxQZBKT5ZPt0m9STJEadao0xAH0ahmbWn +OlFuhjuefXKnEgV4We0+UXgVCwOPjdAvBbI+e0ocS3MFEvzG6uBQE3xDk3SzynTn +jh8BCNAw1FtxNrQHusEwMFxIt4I7mKZ9YIqioymCzLq9gwQbooMDQaHWBfEbwrbw +qHyGO0aoSCqI3Haadr8faqU9GY/rOPNk3sgrDQoo//fb4hVC1CLQJ13hef4Y53CI +rU7m2Ys6xt0nUW7/vGT1M0NPAgMBAAGjQjBAMA4GA1UdDwEB/wQEAwIBBjAPBgNV +HRMBAf8EBTADAQH/MB0GA1UdDgQWBBR5tFnme7bl5AFzgAiIyBpY9umbbjANBgkq +hkiG9w0BAQsFAAOCAgEAVR9YqbyyqFDQDLHYGmkgJykIrGF1XIpu+ILlaS/V9lZL +ubhzEFnTIZd+50xx+7LSYK05qAvqFyFWhfFQDlnrzuBZ6brJFe+GnY+EgPbk6ZGQ +3BebYhtF8GaV0nxvwuo77x/Py9auJ/GpsMiu/X1+mvoiBOv/2X/qkSsisRcOj/KK +NFtY2PwByVS5uCbMiogziUwthDyC3+6WVwW6LLv3xLfHTjuCvjHIInNzktHCgKQ5 +ORAzI4JMPJ+GslWYHb4phowim57iaztXOoJwTdwJx4nLCgdNbOhdjsnvzqvHu7Ur +TkXWStAmzOVyyghqpZXjFaH3pO3JLF+l+/+sKAIuvtd7u+Nxe5AW0wdeRlN8NwdC +jNPElpzVmbUq4JUagEiuTDkHzsxHpFKVK7q4+63SM1N95R1NbdWhscdCb+ZAJzVc +oyi3B43njTOQ5yOf+1CceWxG1bQVs5ZufpsMljq4Ui0/1lvh+wjChP4kqKOJ2qxq +4RgqsahDYVvTH9w7jXbyLeiNdd8XM2w9U/t7y0Ff/9yi0GE44Za4rF2LN9d11TPA +mRGunUHBcnWEvgJBQl9nJEiU0Zsnvgc/ubhPgXRR4Xq37Z0j4r7g1SgEEzwxA57d +emyPxgcYxn/eR44/KJ4EBs+lVDR3veyJm+kXQ99b21/+jh5Xos1AnX5iItreGCc= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/luxtrustglobalroot2ca b/make/data/cacerts/luxtrustglobalroot2ca new file mode 100644 index 0000000..e04c399 --- /dev/null +++ b/make/data/cacerts/luxtrustglobalroot2ca
@@ -0,0 +1,40 @@ +Owner: CN=LuxTrust Global Root 2, O=LuxTrust S.A., C=LU +Issuer: CN=LuxTrust Global Root 2, O=LuxTrust S.A., C=LU +Serial number: a7ea6df4b449eda6a24859ee6b815d3167fbbb1 +Valid from: Thu Mar 05 13:21:57 GMT 2015 until: Mon Mar 05 13:21:57 GMT 2035 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFwzCCA6ugAwIBAgIUCn6m30tEntpqJIWe5rgV0xZ/u7EwDQYJKoZIhvcNAQEL +BQAwRjELMAkGA1UEBhMCTFUxFjAUBgNVBAoMDUx1eFRydXN0IFMuQS4xHzAdBgNV +BAMMFkx1eFRydXN0IEdsb2JhbCBSb290IDIwHhcNMTUwMzA1MTMyMTU3WhcNMzUw +MzA1MTMyMTU3WjBGMQswCQYDVQQGEwJMVTEWMBQGA1UECgwNTHV4VHJ1c3QgUy5B +LjEfMB0GA1UEAwwWTHV4VHJ1c3QgR2xvYmFsIFJvb3QgMjCCAiIwDQYJKoZIhvcN +AQEBBQADggIPADCCAgoCggIBANeFl78RmOnwYoNMPIf5U2o3C/IPPIfOb9wmKb3F +ibrJgz337spbxm1Jc7TJRqMbNBM/wYlFV/TZsfs2ZUv7COJIcRHIbjuend+JZTem +hfY7RBi2xjcwYkSSl2l9QjAk5A0MiWtj3sXh306pFGxT4GHO9hcvHTy95iJMHZP1 +EMShduxq3sVs35a0VkBCwGKSMKEtFZSg0iAGCW5qbeXrt77U8PEVfIvmTroTzEsn +Xpk8F12PgX8zPU/TPxvsXD/wPEx1bvKm1Z3aLQdjAsZy6ZS8TEmVT4hSyNvoaYL4 +zDRbIvCGp4m9SAptZoFtyMhk+wHh9OHe2Z7d21vUKpkmFRseTJIpgp7VkoGSQXAZ +96Tlk0u8d2cx3Rz9MXANF5kM+Qw5GSoXtTBxVdUPrljhPS80m8+f9niFwpN6cj5m +j5wWEWCPnolvZ77gR1o7DJpni89Gxq44o/KnvObWhWszJHAiS8sIm7vI+AIpHb4g +DEa/a4ebsypmQjVGbKq6rfmYe+lQVRQxv7HaLe2ArWgk+2mr2HETMOZns4dA/Yl+ +8kPREd8vZS9kzl8UubG/Mb2HeFpZZYiq/FkySIbWTLkpS5XTdvN3JW1CHDiDTf2j +X5t/Lax5Gw5CMZdjpPuKadUiDTSQMC6otOBttpSsvItO13D8xTiOZCXhTTmQzsmH +hFhxAgMBAAGjgagwgaUwDwYDVR0TAQH/BAUwAwEB/zBCBgNVHSAEOzA5MDcGByuB +KwEBAQowLDAqBggrBgEFBQcCARYeaHR0cHM6Ly9yZXBvc2l0b3J5Lmx1eHRydXN0 +Lmx1MA4GA1UdDwEB/wQEAwIBBjAfBgNVHSMEGDAWgBT/GCh2+UgFLKGu8SsbK7JT ++Et8szAdBgNVHQ4EFgQU/xgodvlIBSyhrvErGyuyU/hLfLMwDQYJKoZIhvcNAQEL +BQADggIBAGoZFO1uecEsh9QNcH7X9njJCwROxLHOk3D+sFTAMs2ZMGQXvw/l4jP9 +BzZAcg4atmpZ1gDlaCDdLnINH2pkMSCEfUmmWjfrRcmF9dTHF5kH5ptV5AzoqbTO +jFu1EVzPig4N1qx3gf4ynCSecs5U89BvolbW7MM3LGVYvlcAGvI1+ut7MV3CwRI9 +loGIlonBWVx65n9wNOeD4rHh4bhY79SV5GCc8JaXcozrhAIuZY+kt9J/Z93I055c +qqmkoCUUBpvsT34tC38ddfEz2O3OuHVtPlu5mB0xDVbYQw8wkbIEa91WvpWAVWe+ +2M2D2RjuLg+GLZKecBPs3lHJQ3gCpU3I+V/EkVhGFndadKpAvAefMLmx9xIX3eP/ +JEAdemrRTxgKqpAd60Ae36EeRJIQmvKN4dFLRp7oRUKX6kWZ8+xm1QL68qZKJKre +zrnK+T+Tb/mjuuqlPpmt/f97mfVl7vBZKGfXkJWkE4SphMHozs51k2MavDzq1WQf +LSoSOcbDWjLtR5EWDrw4wVDej8oqkDQc7kGUnF4ZLvhFSZl0kbAEb+MEWrGrKqv+ +x9CWttrhSmQGbmBNvUJO/3jaJMobtNeWOWyu8Q6qp31IiyBMz2TWuJdGsE7RKlY6 +oJO9r4Ak4Ap+58rVyuiFVdw2KuGUaJPHZnJED4AhMmwlxyOAgwrr +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/luxtrustglobalrootca b/make/data/cacerts/luxtrustglobalrootca new file mode 100644 index 0000000..7fb3d81 --- /dev/null +++ b/make/data/cacerts/luxtrustglobalrootca
@@ -0,0 +1,28 @@ +Owner: CN=LuxTrust Global Root, O=LuxTrust s.a., C=LU +Issuer: CN=LuxTrust Global Root, O=LuxTrust s.a., C=LU +Serial number: bb8 +Valid from: Thu Mar 17 09:51:37 GMT 2011 until: Wed Mar 17 09:51:37 GMT 2021 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDZDCCAkygAwIBAgICC7gwDQYJKoZIhvcNAQELBQAwRDELMAkGA1UEBhMCTFUx +FjAUBgNVBAoTDUx1eFRydXN0IHMuYS4xHTAbBgNVBAMTFEx1eFRydXN0IEdsb2Jh +bCBSb290MB4XDTExMDMxNzA5NTEzN1oXDTIxMDMxNzA5NTEzN1owRDELMAkGA1UE +BhMCTFUxFjAUBgNVBAoTDUx1eFRydXN0IHMuYS4xHTAbBgNVBAMTFEx1eFRydXN0 +IEdsb2JhbCBSb290MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAsn+n +QPAiygz267Hxyw6VV0B1r6A/Ps7sqjJX5hmxZ0OYWmt8s7j6eJyqpoSyYBuAQc5j +zR8XCJmk9e8+EsdMsFeaXHhAePxFjdqRZ9w6Ubltc+a3OY52OrQfBfVpVfmTz3iI +Sr6qm9d7R1tGBEyCFqY19vx039a0r9jitScRdFmiwmYsaArhmIiIPIoFdRTjuK7z +CISbasE/MRivJ6VLm6T9eTHemD0OYcqHmMH4ijCc+j4z1aXEAwfh95Z0GAAnOCfR +K6qq4UFFi2/xJcLcopeVx0IUM115hCNq52XAV6DYXaljAeew5Ivo+MVjuOVsdJA9 +x3f8K7p56aTGEnin/wIDAQABo2AwXjAMBgNVHRMEBTADAQH/MA4GA1UdDwEB/wQE +AwIBBjAfBgNVHSMEGDAWgBQXFYWJCS8kh28/HRvk8pZ5g0gTzjAdBgNVHQ4EFgQU +FxWFiQkvJIdvPx0b5PKWeYNIE84wDQYJKoZIhvcNAQELBQADggEBAFrwHNDUUM9B +fua4nX3DcNBeNv9ujnov3kgR1TQuPLdFwlQlp+HBHjeDtpSutkVIA+qVvuucarQ3 +XB8u02uCgUNbCj8RVWOs+nwIAjegPDkEM/6XMshS5dklTbDG7mgfcKpzzlcD3H0K +DTPy0lrfCmw7zBFRlxqkIaKFNQLXgCLShLL4wKpov9XrqsMLq6F8K/f1O4fhVFfs +BSTveUJO84ton+Ruy4KZycwq3FPCH3CDqyEPVrRI/98HIrOM+R2mBN8tAza53W/+ +MYhm/2xtRDSvCHc+JtJy9LtHVpM8mGPhM7uZI5K1g3noHZ9nrWLWidb2/CfeMifL +hNp3hSGhEiE= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/quovadisrootca b/make/data/cacerts/quovadisrootca new file mode 100644 index 0000000..0c195ff --- /dev/null +++ b/make/data/cacerts/quovadisrootca
@@ -0,0 +1,41 @@ +Owner: CN=QuoVadis Root Certification Authority, OU=Root Certification Authority, O=QuoVadis Limited, C=BM +Issuer: CN=QuoVadis Root Certification Authority, OU=Root Certification Authority, O=QuoVadis Limited, C=BM +Serial number: 3ab6508b +Valid from: Mon Mar 19 18:33:33 GMT 2001 until: Wed Mar 17 18:33:33 GMT 2021 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIF0DCCBLigAwIBAgIEOrZQizANBgkqhkiG9w0BAQUFADB/MQswCQYDVQQGEwJC +TTEZMBcGA1UEChMQUXVvVmFkaXMgTGltaXRlZDElMCMGA1UECxMcUm9vdCBDZXJ0 +aWZpY2F0aW9uIEF1dGhvcml0eTEuMCwGA1UEAxMlUXVvVmFkaXMgUm9vdCBDZXJ0 +aWZpY2F0aW9uIEF1dGhvcml0eTAeFw0wMTAzMTkxODMzMzNaFw0yMTAzMTcxODMz +MzNaMH8xCzAJBgNVBAYTAkJNMRkwFwYDVQQKExBRdW9WYWRpcyBMaW1pdGVkMSUw +IwYDVQQLExxSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MS4wLAYDVQQDEyVR +dW9WYWRpcyBSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MIIBIjANBgkqhkiG +9w0BAQEFAAOCAQ8AMIIBCgKCAQEAv2G1lVO6V/z68mcLOhrfEYBklbTRvM16z/Yp +li4kVEAkOPcahdxYTMukJ0KX0J+DisPkBgNbAKVRHnAEdOLB1Dqr1607BxgFjv2D +rOpm2RgbaIr1VxqYuvXtdj182d6UajtLF8HVj71lODqV0D1VNk7feVcxKh7YWWVJ +WCCYfqtffp/p1k3sg3Spx2zY7ilKhSoGFPlU5tPaZQeLYzcS19Dsw3sgQUSj7cug +F+FxZc4dZjH3dgEZyH0DWLaVSR2mEiboxgx24ONmy+pdpibu5cxfvWenAScOospU +xbF6lR1xHkopigPcakXBpBlebzbNw6Kwt/5cOOJSvPhEQ+aQuwIDAQABo4ICUjCC +Ak4wPQYIKwYBBQUHAQEEMTAvMC0GCCsGAQUFBzABhiFodHRwczovL29jc3AucXVv +dmFkaXNvZmZzaG9yZS5jb20wDwYDVR0TAQH/BAUwAwEB/zCCARoGA1UdIASCAREw +ggENMIIBCQYJKwYBBAG+WAABMIH7MIHUBggrBgEFBQcCAjCBxxqBxFJlbGlhbmNl +IG9uIHRoZSBRdW9WYWRpcyBSb290IENlcnRpZmljYXRlIGJ5IGFueSBwYXJ0eSBh +c3N1bWVzIGFjY2VwdGFuY2Ugb2YgdGhlIHRoZW4gYXBwbGljYWJsZSBzdGFuZGFy +ZCB0ZXJtcyBhbmQgY29uZGl0aW9ucyBvZiB1c2UsIGNlcnRpZmljYXRpb24gcHJh +Y3RpY2VzLCBhbmQgdGhlIFF1b1ZhZGlzIENlcnRpZmljYXRlIFBvbGljeS4wIgYI +KwYBBQUHAgEWFmh0dHA6Ly93d3cucXVvdmFkaXMuYm0wHQYDVR0OBBYEFItLbe3T +KbkGGew5Oanwl4Rqy+/fMIGuBgNVHSMEgaYwgaOAFItLbe3TKbkGGew5Oanwl4Rq +y+/foYGEpIGBMH8xCzAJBgNVBAYTAkJNMRkwFwYDVQQKExBRdW9WYWRpcyBMaW1p +dGVkMSUwIwYDVQQLExxSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MS4wLAYD +VQQDEyVRdW9WYWRpcyBSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5ggQ6tlCL +MA4GA1UdDwEB/wQEAwIBBjANBgkqhkiG9w0BAQUFAAOCAQEAitQUtf70mpKnGdSk +fnIYj9lofFIk3WdvOXrEql494liwTXCYhGHoG+NpGA7O+0dQoE7/8CQfvbLO9Sf8 +7C9TqnN7Az10buYWnuulLsS/VidQK2K6vkscPFVcQR0kvoIgR13VRH56FmjffU1R +cHhXHTMe/QKZnAzNCgVPx7uOpHX6Sm2xgI4JVrmcGmD+XcHXetwReNDWXcG31a0y +mQM6isxUJTkxgXsTIlG6Rmyhu576BGxJJnSP0nPrzDCi5upZIof4l/UO/erMkqQW +xFIY6iHOsfHmhIHluqmGKPJDWl0Snawe2ajlCmqnf6CHKc/yiU3U7MXi5nrQNiOK +SnQ2+Q== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/quovadisrootca1g3 b/make/data/cacerts/quovadisrootca1g3 new file mode 100644 index 0000000..26e23ab --- /dev/null +++ b/make/data/cacerts/quovadisrootca1g3
@@ -0,0 +1,38 @@ +Owner: CN=QuoVadis Root CA 1 G3, O=QuoVadis Limited, C=BM +Issuer: CN=QuoVadis Root CA 1 G3, O=QuoVadis Limited, C=BM +Serial number: 78585f2ead2c194be3370735341328b596d46593 +Valid from: Thu Jan 12 17:27:44 GMT 2012 until: Sun Jan 12 17:27:44 GMT 2042 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFYDCCA0igAwIBAgIUeFhfLq0sGUvjNwc1NBMotZbUZZMwDQYJKoZIhvcNAQEL +BQAwSDELMAkGA1UEBhMCQk0xGTAXBgNVBAoTEFF1b1ZhZGlzIExpbWl0ZWQxHjAc +BgNVBAMTFVF1b1ZhZGlzIFJvb3QgQ0EgMSBHMzAeFw0xMjAxMTIxNzI3NDRaFw00 +MjAxMTIxNzI3NDRaMEgxCzAJBgNVBAYTAkJNMRkwFwYDVQQKExBRdW9WYWRpcyBM +aW1pdGVkMR4wHAYDVQQDExVRdW9WYWRpcyBSb290IENBIDEgRzMwggIiMA0GCSqG +SIb3DQEBAQUAA4ICDwAwggIKAoICAQCgvlAQjunybEC0BJyFuTHK3C3kEakEPBtV +wedYMB0ktMPvhd6MLOHBPd+C5k+tR4ds7FtJwUrVu4/sh6x/gpqG7D0DmVIB0jWe +rNrwU8lmPNSsAgHaJNM7qAJGr6Qc4/hzWHa39g6QDbXwz8z6+cZM5cOGMAqNF341 +68Xfuw6cwI2H44g4hWf6Pser4BOcBRiYz5P1sZK0/CPTz9XEJ0ngnjybCKOLXSoh +4Pw5qlPafX7PGglTvF0FBM+hSo+LdoINofjSxxR3W5A2B4GbPgb6Ul5jxaYA/qXp +UhtStZI5cgMJYr2wYBZupt0lwgNm3fME0UDiTouG9G/lg6AnhF4EwfWQvTA9xO+o +abw4m6SkltFi2mnAAZauy8RRNOoMqv8hjlmPSlzkYZqn0ukqeI1RPToV7qJZjqlc +3sX5kCLliEVx3ZGZbHqfPT2YfF72vhZooF6uCyP8Wg+qInYtyaEQHeTTRCOQiJ/G +KubX9ZqzWB4vMIkIG1SitZgj7Ah3HJVdYdHLiZxfokqRmu8hqkkWCKi9YSgxyXSt +hfbZxbGL0eUQMk1fiyA6PEkfM4VZDdvLCXVDaXP7a3F98N/ETH3Goy7IlXnLc6KO +Tk0k+17kBL5yG6YnLUlamXrXXAkgt3+UuU/xDRxeiEIbEbfnkduebPRq34wGmAOt +zCjvpUfzUwIDAQABo0IwQDAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQEAwIB +BjAdBgNVHQ4EFgQUo5fW816iEOGrRZ88F2Q87gFwnMwwDQYJKoZIhvcNAQELBQAD +ggIBABj6W3X8PnrHX3fHyt/PX8MSxEBd1DKquGrX1RUVRpgjpeaQWxiZTOOtQqOC +MTaIzen7xASWSIsBx40Bz1szBpZGZnQdT+3Btrm0DWHMY37XLneMlhwqI2hrhVd2 +cDMT/uFPpiN3GPoajOi9ZcnPP/TJF9zrx7zABC4tRi9pZsMbj/7sPtPKlL92CiUN +qXsCHKnQO18LwIE6PWThv6ctTr1NxNgpxiIY0MWscgKCP6o6ojoilzHdCGPDdRS5 +YCgtW2jgFqlmgiNR9etT2DGbe+m3nUvriBbP+V04ikkwj+3x6xn0dxoxGE1nVGwv +b2X52z3sIexe9PSLymBlVNFxZPT5pqOBMzYzcfCkeF9OrYMh3jRJjehZrJ3ydlo2 +8hP0r+AJx2EqbPfgna67hkooby7utHnNkDPDs3b69fBsnQGQ+p6Q9pxyz0fawx/k +NSBT8lTR32GDpgLiJTjehTItXnOQUl1CxM49S+H5GYQd1aJQzEH7QRTDvdbJWqNj +ZgKAvQU6O0ec7AAmTPWIUb+oI38YB7AL7YsmoWTTYUrrXJ/es69nA7Mf3W1daWhp +q1467HxpvMc7hU6eFbm0FU/DlXpY18ls6Wy58yljXrQs8C097Vpl4KlbQMJImYFt +nh8GKjwStIsPm6Ik8KaN1nrgS7ZklmOVhMJKzRwuJIczYOXD +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/quovadisrootca2 b/make/data/cacerts/quovadisrootca2 new file mode 100644 index 0000000..c5b1f07 --- /dev/null +++ b/make/data/cacerts/quovadisrootca2
@@ -0,0 +1,40 @@ +Owner: CN=QuoVadis Root CA 2, O=QuoVadis Limited, C=BM +Issuer: CN=QuoVadis Root CA 2, O=QuoVadis Limited, C=BM +Serial number: 509 +Valid from: Fri Nov 24 18:27:00 GMT 2006 until: Mon Nov 24 18:23:33 GMT 2031 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFtzCCA5+gAwIBAgICBQkwDQYJKoZIhvcNAQEFBQAwRTELMAkGA1UEBhMCQk0x +GTAXBgNVBAoTEFF1b1ZhZGlzIExpbWl0ZWQxGzAZBgNVBAMTElF1b1ZhZGlzIFJv +b3QgQ0EgMjAeFw0wNjExMjQxODI3MDBaFw0zMTExMjQxODIzMzNaMEUxCzAJBgNV +BAYTAkJNMRkwFwYDVQQKExBRdW9WYWRpcyBMaW1pdGVkMRswGQYDVQQDExJRdW9W +YWRpcyBSb290IENBIDIwggIiMA0GCSqGSIb3DQEBAQUAA4ICDwAwggIKAoICAQCa +GMpLlA0ALa8DKYrwD4HIrkwZhR0In6spRIXzL4GtMh6QRr+jhiYaHv5+HBg6XJxg +Fyo6dIMzMH1hVBHL7avg5tKifvVrbxi3Cgst/ek+7wrGsxDp3MJGF/hd/aTa/55J +WpzmM+Yklvc/ulsrHHo1wtZn/qtmUIttKGAr79dgw8eTvI02kfN/+NsRE8Scd3bB +rrcCaoF6qUWD4gXmuVbBlDePSHFjIuwXZQeVikvfj8ZaCuWw419eaxGrDPmF60Tp ++ARz8un+XJiM9XOva7R+zdRcAitMOeGylZUtQofX1bOQQ7dsE/He3fbE+Ik/0XX1 +ksOR1YqI0JDs3G3eicJlcZaLDQP9nL9bFqyS2+r+eXyt66/3FsvbzSUr5R/7mp/i +Ucw6UwxI5g69ybR2BlLmEROFcmMDBOAENisgGQLodKcftslWZvB1JdxnwQ5hYIiz +PtGo/KPaHbDRsSNU30R2be1B2MGyIrZTHN81Hdyhdyox5C315eXbyOD/5YDXC2Og +/zOhD7osFRXql7PSorW+8oyWHhqPHWykYTe5hnMz15eWniN9gqRMgeKh0bpnX5UH +oycR7hYQe7xFSkyyBNKr79X9DFHOUGoIMfmR2gyPZFwDwzqLID9ujWc9Otb+fVuI +yV77zGHcizN300QyNQliBJIWENieJ0f7OyHj+OsdWwIDAQABo4GwMIGtMA8GA1Ud +EwEB/wQFMAMBAf8wCwYDVR0PBAQDAgEGMB0GA1UdDgQWBBQahGK8SEwzJQTU7tD2 +A8QZRtGUazBuBgNVHSMEZzBlgBQahGK8SEwzJQTU7tD2A8QZRtGUa6FJpEcwRTEL +MAkGA1UEBhMCQk0xGTAXBgNVBAoTEFF1b1ZhZGlzIExpbWl0ZWQxGzAZBgNVBAMT +ElF1b1ZhZGlzIFJvb3QgQ0EgMoICBQkwDQYJKoZIhvcNAQEFBQADggIBAD4KFk2f +BluornFdLwUvZ+YTRYPENvbzwCYMDbVHZF34tHLJRqUDGCdViXh9duqWNIAXINzn +g/iN/Ae42l9NLmeyhP3ZRPx3UIHmfLTJDQtyU/h2BwdBR5YM++CCJpNVjP4iH2Bl +fF/nJrP3MpCYUNQ3cVX2kiF495V5+vgtJodmVjB3pjd4M1IQWK4/YY7yarHvGH5K +WWPKjaJW1acvvFYfzznB4vsKqBUsfU16Y8Zsl0Q80m/DShcK+JDSV6IZUaUtl0Ha +B0+pUNqQjZRG4T7wlP0QADj1O+hA4bRuVhogzG9Yje0uRY/W6ZM/57Es3zrWIozc +hLsib9D45MY56QSIPMO661V6bYCZJPVsAfv4l7CUW+v90m/xd2gNNWQjrLhVoQPR +TUIZ3Ph1WVaj+ahJefivDrkRoHy3au000LYmYjgahwz46P0u05B/B5EqHdZ+XIWD +mbA4CD/pXvk1B+TJYm5Xf6dQlfe6yJvmjqIBxdZmv3lh8zwc4bmCXF2gw+nYSL0Z +ohEUGW6yhhtoPkg3Goi3XZZenMfvJ2II4pEZXNLxId26F0KCl3GBUzGpn/Z9Yr9y +4aOTHcyKJloJONDO1w2AFrR4pTqHTI2KpdVGl/IsELm8VCLAAVBpQ570su9t+Oza +8eOx79+Rj1QqCyXBJhnEUhAFZdWCEOrCMc0u +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/quovadisrootca2g3 b/make/data/cacerts/quovadisrootca2g3 new file mode 100644 index 0000000..6d370f5 --- /dev/null +++ b/make/data/cacerts/quovadisrootca2g3
@@ -0,0 +1,38 @@ +Owner: CN=QuoVadis Root CA 2 G3, O=QuoVadis Limited, C=BM +Issuer: CN=QuoVadis Root CA 2 G3, O=QuoVadis Limited, C=BM +Serial number: 445734245b81899b35f2ceb82b3b5ba726f07528 +Valid from: Thu Jan 12 18:59:32 GMT 2012 until: Sun Jan 12 18:59:32 GMT 2042 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFYDCCA0igAwIBAgIURFc0JFuBiZs18s64KztbpybwdSgwDQYJKoZIhvcNAQEL +BQAwSDELMAkGA1UEBhMCQk0xGTAXBgNVBAoTEFF1b1ZhZGlzIExpbWl0ZWQxHjAc +BgNVBAMTFVF1b1ZhZGlzIFJvb3QgQ0EgMiBHMzAeFw0xMjAxMTIxODU5MzJaFw00 +MjAxMTIxODU5MzJaMEgxCzAJBgNVBAYTAkJNMRkwFwYDVQQKExBRdW9WYWRpcyBM +aW1pdGVkMR4wHAYDVQQDExVRdW9WYWRpcyBSb290IENBIDIgRzMwggIiMA0GCSqG +SIb3DQEBAQUAA4ICDwAwggIKAoICAQChriWyARjcV4g/Ruv5r+LrI3HimtFhZiFf +qq8nUeVuGxbULX1QsFN3vXg6YOJkApt8hpvWGo6t/x8Vf9WVHhLL5hSEBMHfNrMW +n4rjyduYNM7YMxcoRvynyfDStNVNCXJJ+fKH46nafaF9a7I6JaltUkSs+L5u+9ym +c5GQYaYDFCDy54ejiK2toIz/pgslUiXnFgHVy7g1gQyjO/Dh4fxaXc6AcW34Sas+ +O7q414AB+6XrW7PFXmAqMaCvN+ggOp+oMiwMzAkd056OXbxMmO7FGmh77FOm6RQ1 +o9/NgJ8MSPsc9PG/Srj61YxxSscfrf5BmrODXfKEVu+lV0POKa2Mq1W/xPtbAd0j +IaFYAI7D0GoT7RPjEiuA3GfmlbLNHiJuKvhB1PLKFAeNilUSxmn1uIZoL1NesNKq +IcGY5jDjZ1XHm26sGahVpkUG0CM62+tlXSoREfA7T8pt9DTEceT/AFr2XK4jYIVz +8eQQsSWu1ZK7E8EM4DnatDlXtas1qnIhO4M15zHfeiFuuDIIfR0ykRVKYnLP43eh +vNURG3YBZwjgQQvD6xVu+KQZ2aKrr+InUlYrAoosFCT5v0ICvybIxo/gbjh9Uy3l +7ZizlWNof/k19N+IxWA1ksB8aRxhlRbQ694Lrz4EEEVlWFA4r0jyWbYW8jwNkALG +cC4BrTwV1wIDAQABo0IwQDAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQEAwIB +BjAdBgNVHQ4EFgQU7edvdlq/YOxJW8ald7tyFnGbxD0wDQYJKoZIhvcNAQELBQAD +ggIBAJHfgD9DCX5xwvfrs4iP4VGyvD11+ShdyLyZm3tdquXK4Qr36LLTn91nMX66 +AarHakE7kNQIXLJgapDwyM4DYvmL7ftuKtwGTTwpD4kWilhMSA/ohGHqPHKmd+RC +roijQ1h5fq7KpVMNqT1wvSAZYaRsOPxDMuHBR//47PERIjKWnML2W2mWeyAMQ0Ga +W/ZZGYjeVYg3UQt4XAoeo0L9x52ID8DyeAIkVJOviYeIyUqAHerQbj5hLja7NQ4n +lv1mNDthcnPxFlxHBlRJAHpYErAK74X9sbgzdWqTHBLmYF5vHX/JHyPLhGGfHoJE ++V+tYlUkmlKY7VHnoX6XOuYvHxHaU4AshZ6rNRDbIl9qxV6XU/IyAgkwo1jwDQHV +csaxfGl7w/U2Rcxhbl5MlMVerugOXou/983g7aEOGzPuVBj+D77vfoRrQ+NwmNtd +dbINWQeFFSM51vHfqSYP1kjHs6Yi9TM3WpVHn3u6GBVv/9YUZINJ0gpnIdsPNWNg +KCLjsZWDzYWm3S8P52dSbrsvhXz1SnPnxT7AvSESBT/8twNJAlvIJebiVDj1eYeM +HVOyToV7BjjHLPj4sHKNJeV3UvQDHEimUF+IIDBu8oJDqz2XhOdT+yHBTw8imoa4 +WSr2Rz0ZiC3oheGe7IUIarFsNMkd7EgrO3jtZsSOeWmD3n+M +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/quovadisrootca3 b/make/data/cacerts/quovadisrootca3 new file mode 100644 index 0000000..0452ad9 --- /dev/null +++ b/make/data/cacerts/quovadisrootca3
@@ -0,0 +1,45 @@ +Owner: CN=QuoVadis Root CA 3, O=QuoVadis Limited, C=BM +Issuer: CN=QuoVadis Root CA 3, O=QuoVadis Limited, C=BM +Serial number: 5c6 +Valid from: Fri Nov 24 19:11:23 GMT 2006 until: Mon Nov 24 19:06:44 GMT 2031 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIGnTCCBIWgAwIBAgICBcYwDQYJKoZIhvcNAQEFBQAwRTELMAkGA1UEBhMCQk0x +GTAXBgNVBAoTEFF1b1ZhZGlzIExpbWl0ZWQxGzAZBgNVBAMTElF1b1ZhZGlzIFJv +b3QgQ0EgMzAeFw0wNjExMjQxOTExMjNaFw0zMTExMjQxOTA2NDRaMEUxCzAJBgNV +BAYTAkJNMRkwFwYDVQQKExBRdW9WYWRpcyBMaW1pdGVkMRswGQYDVQQDExJRdW9W +YWRpcyBSb290IENBIDMwggIiMA0GCSqGSIb3DQEBAQUAA4ICDwAwggIKAoICAQDM +V0IWVJzmmNPTTe7+7cefQzlKZbPoFog02w1ZkXTPkrgEQK0CSzGrvI2RaNggDhoB +4hp7Thdd4oq3P5kazethq8Jlph+3t723j/z9cI8LoGe+AaJZz3HmDyl2/7FWeUUr +H556VOijKTVopAFPD6QuN+8bv+OPEKhyq1hX51SGyMnzW9os2l2ObjyjPtr7guXd +8lyyBTNvijbO0BNO/79KDDRMpsMhvVAEVeuxu537RR5kFd5VAYwCdrXLoT9Cabwv +vWhDFlaJKjdhkf2mrk7AyxRllDdLkgbvBNDInIjbC3uBr7E9KsRlOni27tyAsdLT +mZw67mtaa7ONt9XOnMK+pUsvFrGeaDsGb659n/je7Mwpp5ijJUMv7/FfJuGITfhe +btfZFG4ZM2mnO4SJk8RTVROhUXhA+LjJou57ulJCg54U7QVSWllWp5f8nT8KKdjc +T5EOE7zelaTfi5m+rJsziO+1ga8bxiJTyPbH7pcUsMV8eFLI8M5ud2CEpukqdiDt +WAEXMJPpGovgc2PZapKUSU60rUqFxKMiMPwJ7Wgic6aIDFUhWMXhOp8q3crhkODZ +c6tsgLjoC2SToJyMGf+z0gzskSaHirOi4XCPLArlzW1oUevaPwV/izLmE1xr/l9A +4iLItLRkT9a6fUg+qGkM17uGcclzuD87nSVL2v9A6wIDAQABo4IBlTCCAZEwDwYD +VR0TAQH/BAUwAwEB/zCB4QYDVR0gBIHZMIHWMIHTBgkrBgEEAb5YAAMwgcUwgZMG +CCsGAQUFBwICMIGGGoGDQW55IHVzZSBvZiB0aGlzIENlcnRpZmljYXRlIGNvbnN0 +aXR1dGVzIGFjY2VwdGFuY2Ugb2YgdGhlIFF1b1ZhZGlzIFJvb3QgQ0EgMyBDZXJ0 +aWZpY2F0ZSBQb2xpY3kgLyBDZXJ0aWZpY2F0aW9uIFByYWN0aWNlIFN0YXRlbWVu +dC4wLQYIKwYBBQUHAgEWIWh0dHA6Ly93d3cucXVvdmFkaXNnbG9iYWwuY29tL2Nw +czALBgNVHQ8EBAMCAQYwHQYDVR0OBBYEFPLAE+CCQz777i9nMpY1XNu4ywLQMG4G +A1UdIwRnMGWAFPLAE+CCQz777i9nMpY1XNu4ywLQoUmkRzBFMQswCQYDVQQGEwJC +TTEZMBcGA1UEChMQUXVvVmFkaXMgTGltaXRlZDEbMBkGA1UEAxMSUXVvVmFkaXMg +Um9vdCBDQSAzggIFxjANBgkqhkiG9w0BAQUFAAOCAgEAT62gLEz6wPJv92ZVqyM0 +7ucp2sNbtrCD2dDQ4iH782CnO11gUyeim/YIIirnv6By5ZwkajGxkHon24QRiSem +d1o417+shvzuXYO8BsbRd2sPbSQvS3pspweWyuOEn62Iix2rFo1bZhfZFvSLgNLd ++LJ2w/w4E6oM3kJpK27zPOuAJ9v1pkQNn1pVWQvVDVJIxa6f8i+AxeoyUDUSly7B +4f/xI4hROJ/yZlZ25w9Rl6VSDE1JUZU2Pb+iSwwQHYaZTKrzchGT5Or2m9qoXadN +t54CrnMAyNojA+j56hl0YgCUyyIgvpSnWbWCar6ZeXqp8kokUvd0/bpO5qgdAm6x +DYBEwa7TIzdfu4V8K5Iu6H6li92Z4b8nby1dqnuH/grdS/yO9SbkbnBCbjPsMZ57 +k8HkyWkaPcBrTiJt7qtYTcbQQcEr6k8Sh17rRdhs9ZgC06DYVYoGmRmioHfRMJ6s +zHXug/WwYjnPbFfiTNKRCw51KBuav/0aQ/HKd/s7j2G4aSgWQgRecCocIdiP4b0j +Wy10QJLZYxkNc91pvGJHvOB0K7Lrfb5BG7XARsWhIstfTsEokt4YutUqKLsRixeT +mJlglFwjz1onl14LBQaTNx47aTbrqZ5hHY8y2o4M1nQ+ewkk2gF3R8Q7zTSMmfXK +4SVhM7JZG+Ju1zdXtg2pEto= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/quovadisrootca3g3 b/make/data/cacerts/quovadisrootca3g3 new file mode 100644 index 0000000..b4eccae --- /dev/null +++ b/make/data/cacerts/quovadisrootca3g3
@@ -0,0 +1,38 @@ +Owner: CN=QuoVadis Root CA 3 G3, O=QuoVadis Limited, C=BM +Issuer: CN=QuoVadis Root CA 3 G3, O=QuoVadis Limited, C=BM +Serial number: 2ef59b0228a7db7affd5a3a9eebd03a0cf126a1d +Valid from: Thu Jan 12 20:26:32 GMT 2012 until: Sun Jan 12 20:26:32 GMT 2042 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFYDCCA0igAwIBAgIULvWbAiin23r/1aOp7r0DoM8Sah0wDQYJKoZIhvcNAQEL +BQAwSDELMAkGA1UEBhMCQk0xGTAXBgNVBAoTEFF1b1ZhZGlzIExpbWl0ZWQxHjAc +BgNVBAMTFVF1b1ZhZGlzIFJvb3QgQ0EgMyBHMzAeFw0xMjAxMTIyMDI2MzJaFw00 +MjAxMTIyMDI2MzJaMEgxCzAJBgNVBAYTAkJNMRkwFwYDVQQKExBRdW9WYWRpcyBM +aW1pdGVkMR4wHAYDVQQDExVRdW9WYWRpcyBSb290IENBIDMgRzMwggIiMA0GCSqG +SIb3DQEBAQUAA4ICDwAwggIKAoICAQCzyw4QZ47qFJenMioKVjZ/aEzHs286IxSR +/xl/pcqs7rN2nXrpixurazHb+gtTTK/FpRp5PIpM/6zfJd5O2YIyC0TeytuMrKNu +FoM7pmRLMon7FhY4futD4tN0SsJiCnMK3UmzV9KwCoWdcTzeo8vAMvMBOSBDGzXR +U7Ox7sWTaYI+FrUoRqHe6okJ7UO4BUaKhvVZR74bbwEhELn9qdIoyhA5CcoTNs+c +ra1AdHkrAj80//ogaX3T7mH1urPnMNA3I4ZyYUUpSFlob3emLoG+B01vr87ERROR +FHAGjx+f+IdpsQ7vw4kZ6+ocYfx6bIrc1gMLnia6Et3UVDmrJqMz6nWB2i3ND0/k +A9HvFZcba5DFApCTZgIhsUfei5pKgLlVj7WiL8DWM2fafsSntARE60f75li59wzw +eyuxwHApw0BiLTtIadwjPEjrewl5qW3aqDCYz4ByA4imW0aucnl8CAMhZa634Ryl +sSqiMd5mBPfAdOhx3v89WcyWJhKLhZVXGqtrdQtEPREoPHtht+KPZ0/l7DxMYIBp +VzgeAVuNVejH38DMdyM0SXV89pgR6y3e7UEuFAUCf+D+IOs15xGsIs5XPd7JMG0Q +A4XN8f+MFrXBsj6IbGB/kE+V9/YtrQE5BwT6dYB9v0lQ7e/JxHwc64B+27bQ3RP+ +ydOc17KXqQIDAQABo0IwQDAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQEAwIB +BjAdBgNVHQ4EFgQUxhfQvKjqAkPyGwaZXSuQILnXnOQwDQYJKoZIhvcNAQELBQAD +ggIBADRh2Va1EodVTd2jNTFGu6QHcrxfYWLopfsLN7E8trP6KZ1/AvWkyaiTt3px +KGmPc+FSkNrVvjrlt3ZqVoAh313m6Tqe5T72omnHKgqwGEfcIHB9UqM+WXzBusnI +FUBhynLWcKzSt/Ac5IYp8M7vaGPQtSCKFWGafoaYtMnCdvvMujAWzKNhxnQT5Wvv +oxXqA/4Ti2Tk08HS6IT7SdEQTXlm66r99I0xHnAUrdzeZxNMgRVhvLfZkXdxGYFg +u/BYpbWcC/ePIlUnwEsBbTuZDdQdm2NnL9DuDcpmvJRPpq3t/O5jrFc/ZSXPsoaP +0Aj/uHYUbt7lJ+yreLVTubY/6CD50qi+YUbKh4yE8/nxoGibIh6BJpsQBJFxwAYf +3KDTuVan45gtf4Od34wrnDKOMpTwATwiKp9Dwi7DmDkHOHv8XgBCH/MyJnmDhPbl +8MFREsALHgQjDFSlTC9JxUrRtm5gDWv8a4uFJGS3iQ6rJUdbPM9+Sb3H6QrG2vd+ +DhcI00iX0HGS8A85PjRqHH3Y8iKuu2n0M7SmSFXRDw4m6Oy2Cy2nhTXN/VnIn9HN +PlopNLk9hM6xZdRZkZFWdSHBd575euFgndOtBBj0fOtek49TSiIp+EgrPk2GrFt/ +ywaZWWDYWGWVjUTR939+J399roD1B0y2PpxxVJkES/1Y+Zj0 +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/secomscrootca1 b/make/data/cacerts/secomscrootca1 new file mode 100644 index 0000000..d300e31 --- /dev/null +++ b/make/data/cacerts/secomscrootca1
@@ -0,0 +1,27 @@ +Owner: OU=Security Communication RootCA1, O=SECOM Trust.net, C=JP +Issuer: OU=Security Communication RootCA1, O=SECOM Trust.net, C=JP +Serial number: 0 +Valid from: Tue Sep 30 04:20:49 GMT 2003 until: Sat Sep 30 04:20:49 GMT 2023 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDWjCCAkKgAwIBAgIBADANBgkqhkiG9w0BAQUFADBQMQswCQYDVQQGEwJKUDEY +MBYGA1UEChMPU0VDT00gVHJ1c3QubmV0MScwJQYDVQQLEx5TZWN1cml0eSBDb21t +dW5pY2F0aW9uIFJvb3RDQTEwHhcNMDMwOTMwMDQyMDQ5WhcNMjMwOTMwMDQyMDQ5 +WjBQMQswCQYDVQQGEwJKUDEYMBYGA1UEChMPU0VDT00gVHJ1c3QubmV0MScwJQYD +VQQLEx5TZWN1cml0eSBDb21tdW5pY2F0aW9uIFJvb3RDQTEwggEiMA0GCSqGSIb3 +DQEBAQUAA4IBDwAwggEKAoIBAQCzs/5/022x7xZ8V6UMbXaKL0u/ZPtM7orw8yl8 +9f/uKuDp6bpbZCKamm8sOiZpUQWZJtzVHGpxxpp9Hp3dfGzGjGdnSj74cbAZJ6kJ +DKaVv0uMDPpVmDvY6CKhS3E4eayXkmmziX7qIWgGmBSWh9JhNrxtJ1aeV+7AwFb9 +Ms+k2Y7CI9eNqPPYJayX5HA49LY6tJ07lyZDo6G8SVlyTCMwhwFY9k6+HGhWZq/N +QV3Is00qVUarH9oe4kA92819uZKAnDfdDJZkndwi92SL32HeFZRSFaB9UslLqCHJ +xrHty8OVYNEP8Ktw+N/LTX7s1vqr2b1/VPKl6Xn62dZ2JChzAgMBAAGjPzA9MB0G +A1UdDgQWBBSgc0mZaNyFW2XjmygvV5+9M7wHSDALBgNVHQ8EBAMCAQYwDwYDVR0T +AQH/BAUwAwEB/zANBgkqhkiG9w0BAQUFAAOCAQEAaECpqLvkT115swW1F7NgE+vG +kl3g0dNq/vu+m22/xwVtWSDEHPC32oRYAmP6SBbvT6UL90qY8j+eG61Ha2POCEfr +Uj94nK9NrvjVT8+amCoQQTlSxN3Zmw7vkwGusi7KaEIkQmywszo+zenaSMQVy+n5 +Bw+SUEmK3TGXX8npN6o7WWWXlDLJs58+OmJYxUmtYg5xpTKqL8aJdkNAExNnPaJU +JRDL8Try2frbSVa7pv6nQTXD4IhhyYjH3zYQIphZ6rBK+1YWc26sTfcioU+tHXot +RSflMMFe8toTyyVCUZVHA4xsIcx0Qu1T/zOLjw9XARYvz6buyXAiFL39vmwLAw== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/secomscrootca2 b/make/data/cacerts/secomscrootca2 new file mode 100644 index 0000000..d80846d --- /dev/null +++ b/make/data/cacerts/secomscrootca2
@@ -0,0 +1,28 @@ +Owner: OU=Security Communication RootCA2, O="SECOM Trust Systems CO.,LTD.", C=JP +Issuer: OU=Security Communication RootCA2, O="SECOM Trust Systems CO.,LTD.", C=JP +Serial number: 0 +Valid from: Fri May 29 05:00:39 GMT 2009 until: Tue May 29 05:00:39 GMT 2029 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDdzCCAl+gAwIBAgIBADANBgkqhkiG9w0BAQsFADBdMQswCQYDVQQGEwJKUDEl +MCMGA1UEChMcU0VDT00gVHJ1c3QgU3lzdGVtcyBDTy4sTFRELjEnMCUGA1UECxMe +U2VjdXJpdHkgQ29tbXVuaWNhdGlvbiBSb290Q0EyMB4XDTA5MDUyOTA1MDAzOVoX +DTI5MDUyOTA1MDAzOVowXTELMAkGA1UEBhMCSlAxJTAjBgNVBAoTHFNFQ09NIFRy +dXN0IFN5c3RlbXMgQ08uLExURC4xJzAlBgNVBAsTHlNlY3VyaXR5IENvbW11bmlj +YXRpb24gUm9vdENBMjCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBANAV +OVKxUrO6xVmCxF1SrjpDZYBLx/KWvNs2l9amZIyoXvDjChz335c9S672XewhtUGr +zbl+dp+++T42NKA7wfYxEUV0kz1XgMX5iZnK5atq1LXaQZAQwdbWQonCv/Q4EpVM +VAX3NuRFg3sUZdbcDE3R3n4MqzvEFb46VqZab3ZpUql6ucjrappdUtAtCms1FgkQ +hNBqyjoGADdH5H5XTz+L62e4iKrFvlNVspHEfbmwhRkGeC7bYRr6hfVKkaHnFtWO +ojnflLhwHyg/i/xAXmODPIMqGplrz95Zajv8bxbXH/1KEOtOghY6rCcMU/Gt1SSw +awNQwS08Ft1ENCcadfsCAwEAAaNCMEAwHQYDVR0OBBYEFAqFqXdlBZh8QIH4D5cs +OPEK7DzPMA4GA1UdDwEB/wQEAwIBBjAPBgNVHRMBAf8EBTADAQH/MA0GCSqGSIb3 +DQEBCwUAA4IBAQBMOqNErLlFsceTfsgLCkLfZOoc7llsCLqJX2rKSpWeeo8HxdpF +coJxDjrSzG+ntKEju/Ykn8sX/oymzsLS28yN/HH8AynBbF0zX2S2ZTuJbxh2ePXc +okgfGT+Ok+vx+hfuzU7jBBJV1uXk3fs+BXziHV7Gp7yXT2g69ekuCkO2r1dcYmh8 +t/2jioSgrGK+KwmHNPBqAbubKVY8/gA3zyNs8U6qtnRGEmyR7jTV7JqR50S+kDFy +1UkC9gLl9B/rfNmWVan/7Ir5mUf/NVoCqgTLiluHcSmRvaS0eg29mvVXIwAHIRc/ +SjnRBUkLp7Y3gaVdjKozXoEofKd9J+sAro03 +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/securetrustca b/make/data/cacerts/securetrustca new file mode 100644 index 0000000..a08e246 --- /dev/null +++ b/make/data/cacerts/securetrustca
@@ -0,0 +1,29 @@ +Owner: CN=SecureTrust CA, O=SecureTrust Corporation, C=US +Issuer: CN=SecureTrust CA, O=SecureTrust Corporation, C=US +Serial number: cf08e5c0816a5ad427ff0eb271859d0 +Valid from: Tue Nov 07 19:31:18 GMT 2006 until: Mon Dec 31 19:40:55 GMT 2029 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDuDCCAqCgAwIBAgIQDPCOXAgWpa1Cf/DrJxhZ0DANBgkqhkiG9w0BAQUFADBI +MQswCQYDVQQGEwJVUzEgMB4GA1UEChMXU2VjdXJlVHJ1c3QgQ29ycG9yYXRpb24x +FzAVBgNVBAMTDlNlY3VyZVRydXN0IENBMB4XDTA2MTEwNzE5MzExOFoXDTI5MTIz +MTE5NDA1NVowSDELMAkGA1UEBhMCVVMxIDAeBgNVBAoTF1NlY3VyZVRydXN0IENv +cnBvcmF0aW9uMRcwFQYDVQQDEw5TZWN1cmVUcnVzdCBDQTCCASIwDQYJKoZIhvcN +AQEBBQADggEPADCCAQoCggEBAKukgeWVzfX2FI7CT8rU4niVWJxB4Q2ZQCQXOZEz +Zum+4YOvYlyJ0fwkW2Gz4BERQRwdbvC4u/jep4G6pkjGnx29vo6pQT64lO0pGtSO +0gMdA+9tDWccV9cGrcrI9f4Or2YlSASWC12juhbDCE/RRvgUXPLIXgGZbf2IzIao +wW8xQmxSPmjL8xk037uHGFaAJsTQ3MBv396gwpEWoGQRS0S8Hvbn+mPeZqx2pHGj +7DaUaHp3pLHnDi+BeuK1cobvomuL8A/b01k/unK8RCSc43Oz969XL0Imnal0ugBS +8kvNU3xHCzaFDmapCJcWNFfBZveA4+1wVMeT4C4oFVmHursCAwEAAaOBnTCBmjAT +BgkrBgEEAYI3FAIEBh4EAEMAQTALBgNVHQ8EBAMCAYYwDwYDVR0TAQH/BAUwAwEB +/zAdBgNVHQ4EFgQUQjK2FvoE/f5dS3rD/fdMQB1aQ68wNAYDVR0fBC0wKzApoCeg +JYYjaHR0cDovL2NybC5zZWN1cmV0cnVzdC5jb20vU1RDQS5jcmwwEAYJKwYBBAGC +NxUBBAMCAQAwDQYJKoZIhvcNAQEFBQADggEBADDtT0rhWDpSclu1pqNlGKa7UTt3 +6Z3q059c4EVlew3KW+JwULKUBRSuSceNQQcSc5R+DCMh/bwQf2AQWnL1mA6s7Ll/ +3XpvXdMc9P+IBWlCqQVxyLesJugutIxq/3HcuLHfmbx8IVQr5Fiiu1cprp6poxkm +D5kuCLDv/WnPmRoJjeOnnyvJNjR7JLN4TJUXpAYmHrZkUjZfYGfZnMUFdAvnZyPS +CPyI6a6Lf+Ew9Dd+/cYy2i2eRDAwbO4H3tI0/NL/QPZL9GZGBlSm8jIKYyYwa5vR +3ItHuuG51WLQoqD0ZwV4KWMabwTW+MZMo5qxN7SN5ShLHZ4swrhovO0C7jE= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/sslrooteccca b/make/data/cacerts/sslrooteccca new file mode 100644 index 0000000..9943012 --- /dev/null +++ b/make/data/cacerts/sslrooteccca
@@ -0,0 +1,23 @@ +Owner: CN=SSL.com Root Certification Authority ECC, O=SSL Corporation, L=Houston, ST=Texas, C=US +Issuer: CN=SSL.com Root Certification Authority ECC, O=SSL Corporation, L=Houston, ST=Texas, C=US +Serial number: 75e6dfcbc1685ba8 +Valid from: Fri Feb 12 18:14:03 GMT 2016 until: Tue Feb 12 18:14:03 GMT 2041 +Signature algorithm name: SHA256withECDSA +Subject Public Key Algorithm: 384-bit EC key +Version: 3 +-----BEGIN CERTIFICATE----- +MIICjTCCAhSgAwIBAgIIdebfy8FoW6gwCgYIKoZIzj0EAwIwfDELMAkGA1UEBhMC +VVMxDjAMBgNVBAgMBVRleGFzMRAwDgYDVQQHDAdIb3VzdG9uMRgwFgYDVQQKDA9T +U0wgQ29ycG9yYXRpb24xMTAvBgNVBAMMKFNTTC5jb20gUm9vdCBDZXJ0aWZpY2F0 +aW9uIEF1dGhvcml0eSBFQ0MwHhcNMTYwMjEyMTgxNDAzWhcNNDEwMjEyMTgxNDAz +WjB8MQswCQYDVQQGEwJVUzEOMAwGA1UECAwFVGV4YXMxEDAOBgNVBAcMB0hvdXN0 +b24xGDAWBgNVBAoMD1NTTCBDb3Jwb3JhdGlvbjExMC8GA1UEAwwoU1NMLmNvbSBS +b290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5IEVDQzB2MBAGByqGSM49AgEGBSuB +BAAiA2IABEVuqVDEpiM2nl8ojRfLliJkP9x6jh3MCLOicSS6jkm5BBtHllirLZXI +7Z4INcgn64mMU1jrYor+8FsPazFSY0E7ic3s7LaNGdM0B9y7xgZ/wkWV7Mt/qCPg +CemB+vNH06NjMGEwHQYDVR0OBBYEFILRhXMw5zUE044CkvvlpNHEIejNMA8GA1Ud +EwEB/wQFMAMBAf8wHwYDVR0jBBgwFoAUgtGFczDnNQTTjgKS++Wk0cQh6M0wDgYD +VR0PAQH/BAQDAgGGMAoGCCqGSM49BAMCA2cAMGQCMG/n61kRpGDPYbCWe+0F+S8T +kdzt5fxQaxFGRrMcIQBiu77D5+jNB5n5DQtdcj7EqgIwH7y6C+IwJPt8bYBVCpk+ +gA0z5Wajs6O7pdWLjwkspl1+4vAHCGht0nxpbl/f5Wpl +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/sslrootevrsaca b/make/data/cacerts/sslrootevrsaca new file mode 100644 index 0000000..c009aa0 --- /dev/null +++ b/make/data/cacerts/sslrootevrsaca
@@ -0,0 +1,41 @@ +Owner: CN=SSL.com EV Root Certification Authority RSA R2, O=SSL Corporation, L=Houston, ST=Texas, C=US +Issuer: CN=SSL.com EV Root Certification Authority RSA R2, O=SSL Corporation, L=Houston, ST=Texas, C=US +Serial number: 56b629cd34bc78f6 +Valid from: Wed May 31 18:14:37 GMT 2017 until: Fri May 30 18:14:37 GMT 2042 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIF6zCCA9OgAwIBAgIIVrYpzTS8ePYwDQYJKoZIhvcNAQELBQAwgYIxCzAJBgNV +BAYTAlVTMQ4wDAYDVQQIDAVUZXhhczEQMA4GA1UEBwwHSG91c3RvbjEYMBYGA1UE +CgwPU1NMIENvcnBvcmF0aW9uMTcwNQYDVQQDDC5TU0wuY29tIEVWIFJvb3QgQ2Vy +dGlmaWNhdGlvbiBBdXRob3JpdHkgUlNBIFIyMB4XDTE3MDUzMTE4MTQzN1oXDTQy +MDUzMDE4MTQzN1owgYIxCzAJBgNVBAYTAlVTMQ4wDAYDVQQIDAVUZXhhczEQMA4G +A1UEBwwHSG91c3RvbjEYMBYGA1UECgwPU1NMIENvcnBvcmF0aW9uMTcwNQYDVQQD +DC5TU0wuY29tIEVWIFJvb3QgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkgUlNBIFIy +MIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEAjzZlQOHWTcDXtOlG2mvq +M0fNTPl9fb69LT3w23jhhqXZuglXaO1XPqDQCEGD5yhBJB/jchXQARr7XnAjssuf +OePPxU7Gkm0mxnu7s9onnQqG6YE3Bf7wcXHswxzpY6IXFJ3vG2fThVUCAtZJycxa +4bH3bzKfydQ7iEGonL3Lq9ttewkfokxykNorCPzPPFTOZw+oz12WGQvE43LrrdF9 +HSfvkusQv1vrO6/PgN3B0pYEW3p+pKk8OHakYo6gOV7qd89dAFmPZiw+B6KjBSYR +aZfqhbcPlgtLyEDhULouisv3D5oi53+aNxPN8k0TayHRwMwi8qFG9kRpnMphNQcA +b9ZhCBHqurj26bNg5U257J8UZslXWNvNh2n4ioYSA0e/ZhN2rHd9NCSFg83XqpyQ +Gp8hLH94t2S42Oim9HizVcuE0jLEeK6jj2HdzghTreyI/BXkmg3mnxp3zkyPuBQV +PWKchjgGAGYS5Fl2WlPAApiiECtoRHuOec4zSnaqW4EWG7WK2NAAe15itAnWhmMO +pgWVSbooi4iTsjQc2KRVbrcc0N6ZVTsj9CLg+SlmJuwgUHfbSguPvuUCYHBBXtSu +UDkiFCbLsjtzdFVHB3mBOagwE0TlBIqulhMlQg+5U8Sb/M3kHN48+qvWBkofZ6aY +MBzdLNvcGJVXZsb/XItW9XcCAwEAAaNjMGEwDwYDVR0TAQH/BAUwAwEB/zAfBgNV +HSMEGDAWgBT5YLvU49U09rj1BoAlp3PbRmmonjAdBgNVHQ4EFgQU+WC71OPVNPa4 +9QaAJadz20ZpqJ4wDgYDVR0PAQH/BAQDAgGGMA0GCSqGSIb3DQEBCwUAA4ICAQBW +s47LCp1Jjr+kxJG7ZhcFUZh1++VQLHqe8RT6q9OKPv+RKY9ji9i0qVQBDb6Thi/5 +Sm3HXvVX+cpVHBK+Rw82xd9qt9t1wkclf7nxY/hoLVUE0fKNsKTPvDxeH3jnpaAg +cLAExbf3cqfeIg29MyVGjGSSJuM+LmOW2puMPfgYCdcDzH2GguDKBAdRUNf/ktUM +79qGn5nX67evaOI5JpS6aLe/g9Pqemc9YmeuJeVy6OLk7K4S9ksrPJ/psEDzOFSz +/bdoyNrGj1E8svuR3Bznm53htw1yj+KkxKl4+esUrMZDBcJlOSgYAsOCsp0FvmXt +ll9ldDz7CTUue5wT/RsPXcdtgTpWD8w74a8CLyKsRspGPKAcTNZEtF4uXBVmCeEm +Kf7GUmG6sXP/wwyc5WxqlD8UykAWlYTzWamsX0xhk23RO8yilQwipmdnRC652dKK +QbNmC1r7fSOl8hqw/96bg5Qu0T/fkreRrwU7ZcegbLHNYhLDkBvjJc40vG93drEQ +w/cFGsDWr3RiSBd3kmmQYRzelYB0VI8YHMPzA9C/pEN1hlMYegouCRw2n5H9gooi +S9EOUCXdywMMF8mDAAhONU2Ki+3wApRmLER/y5UnlhetCTCstnEXbosX9hwJ1C07 +mKVx01QT2WDz9UtmT/rx7iASjbSsV7FFY6GsdqnC+w== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/sslrootrsaca b/make/data/cacerts/sslrootrsaca new file mode 100644 index 0000000..b798275 --- /dev/null +++ b/make/data/cacerts/sslrootrsaca
@@ -0,0 +1,41 @@ +Owner: CN=SSL.com Root Certification Authority RSA, O=SSL Corporation, L=Houston, ST=Texas, C=US +Issuer: CN=SSL.com Root Certification Authority RSA, O=SSL Corporation, L=Houston, ST=Texas, C=US +Serial number: 7b2c9bd316803299 +Valid from: Fri Feb 12 17:39:39 GMT 2016 until: Tue Feb 12 17:39:39 GMT 2041 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIF3TCCA8WgAwIBAgIIeyyb0xaAMpkwDQYJKoZIhvcNAQELBQAwfDELMAkGA1UE +BhMCVVMxDjAMBgNVBAgMBVRleGFzMRAwDgYDVQQHDAdIb3VzdG9uMRgwFgYDVQQK +DA9TU0wgQ29ycG9yYXRpb24xMTAvBgNVBAMMKFNTTC5jb20gUm9vdCBDZXJ0aWZp +Y2F0aW9uIEF1dGhvcml0eSBSU0EwHhcNMTYwMjEyMTczOTM5WhcNNDEwMjEyMTcz +OTM5WjB8MQswCQYDVQQGEwJVUzEOMAwGA1UECAwFVGV4YXMxEDAOBgNVBAcMB0hv +dXN0b24xGDAWBgNVBAoMD1NTTCBDb3Jwb3JhdGlvbjExMC8GA1UEAwwoU1NMLmNv +bSBSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5IFJTQTCCAiIwDQYJKoZIhvcN +AQEBBQADggIPADCCAgoCggIBAPkP3aMrfcvQKv7sZ4Wm5y4bunfh4/WvpOz6Sl2R +xFdHaxh3a3by/ZPkPQ/CFp4LZsNWlJ4Xg4XOVu/yFv0AYvUiCVToZRdOQbngT0aX +qhvIuG5iXmmxX9sqAn78bMrzQdjt0Oj8P2FI7bADFB0QDksZ4LtO7IZl/zbzXmcC +C52GVWH9ejjt/uIZALdvoVBidXQ8oPrIJZK0bnoix/geoeOy3ZExqysdBP+lSgQ3 +6YWkMyv94tZVNHwZpEpox7Ko07fKoZOI68GXvIz5HdkihCR0xwQ9aqkpk8zruFvh +/l8lqjRYyMEjVJ0bmBHDOJx+PYZspQ9AhnwC9FwCTyjLrnGfDzrIM/4RJTXq/LrF +YD3ZfBjVsqnTdXgDciLKOsMf7yzlLqn6niy2UUb9rwPW6mBo6oUWNmuF6R7As93E +JNyAKoFBbZQ+yODJgUEAnl6/f8UImKIYLEJAs/lvOCdLToD0PYFH4Ih86hzOtXVc +US4cK38acijnALXRdMbX5J+tB5O2UzU1/Dfkw/ZdFr4hc96SCvigY2q8lpJqPvi8 +ZVWb3vUNiSYE/CUapiVpy8JtynziWV+XrOvvLsi81xtZPCvM8hnIk2snYxnP/Okm ++Mpxm3+T/jRnhE6Z6/yzeAkzcLpmpnbtG3PrGqUNxCITIJRWCk4sbE6x/c+cCbqi +M+2HAgMBAAGjYzBhMB0GA1UdDgQWBBTdBAkHovV6fVJTEpKV7jiAJQ2mWTAPBgNV +HRMBAf8EBTADAQH/MB8GA1UdIwQYMBaAFN0ECQei9Xp9UlMSkpXuOIAlDaZZMA4G +A1UdDwEB/wQEAwIBhjANBgkqhkiG9w0BAQsFAAOCAgEAIBgRlCn7Jp0cHh5wYfGV +cpNxJK1ok1iOMq8bs3AD/CUrdIWQPXhq9LmLpZc7tRiRux6n+UBbkflVma8eEdBc +Hadm47GUBwwyOabqG7B52B2ccETjit3E+ZUfijhDPwGFpUenPUayvOUiaPd7nNgs +PgohyC0zrL/FgZkxdMF1ccW+sfAjRfSda/wZY52jvATGGAslu1OJD7OAUN5F7kR/ +q5R4ZJjT9ijdh9hwZXT7DrkT66cPYakylszeu+1jTBi7qUD3oFRuIIhxdRjqerQ0 +cuAjJ3dctpDqhiVAq+8zD8ufgr6iIPv2tS0a5sKFsXQP+8hlAqRSAUfdSSLBv9jr +a6x+3uxjMxW3IwiPxg+NQVrdjsW5j+VFP3jbutIbQLH+cU0/4IGiul607BXgk90I +H37hVZkLId6Tngr75qNJvTYw/ud3sqB1l7UtgYgXZSD32pAAn8lSzDLKNXz1PQ/Y +K9f1JmzJBjSWFupwWRoyeXkLtoh/D1JIPb9s2KJELtFOt3JY04kTlf5Eq/jXixtu +nLwsoFvVagCvXzfh1foQC5ichucmj87w7G6KVwuA406ywKBjYZC6VWg3dGq2ktuf +oYYitmUnDuy2n0Jg5GfCtdpBC8TTi2EbvPofkSvXRAdeuims2cXp71NIWuuA8ShY +Ic2wBlX7Jz9TkHCpBB5XJ7k= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/starfieldclass2ca b/make/data/cacerts/starfieldclass2ca new file mode 100644 index 0000000..d87e609 --- /dev/null +++ b/make/data/cacerts/starfieldclass2ca
@@ -0,0 +1,31 @@ +Owner: OU=Starfield Class 2 Certification Authority, O="Starfield Technologies, Inc.", C=US +Issuer: OU=Starfield Class 2 Certification Authority, O="Starfield Technologies, Inc.", C=US +Serial number: 0 +Valid from: Tue Jun 29 17:39:16 GMT 2004 until: Thu Jun 29 17:39:16 GMT 2034 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEDzCCAvegAwIBAgIBADANBgkqhkiG9w0BAQUFADBoMQswCQYDVQQGEwJVUzEl +MCMGA1UEChMcU3RhcmZpZWxkIFRlY2hub2xvZ2llcywgSW5jLjEyMDAGA1UECxMp +U3RhcmZpZWxkIENsYXNzIDIgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkwHhcNMDQw +NjI5MTczOTE2WhcNMzQwNjI5MTczOTE2WjBoMQswCQYDVQQGEwJVUzElMCMGA1UE +ChMcU3RhcmZpZWxkIFRlY2hub2xvZ2llcywgSW5jLjEyMDAGA1UECxMpU3RhcmZp +ZWxkIENsYXNzIDIgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkwggEgMA0GCSqGSIb3 +DQEBAQUAA4IBDQAwggEIAoIBAQC3Msj+6XGmBIWtDBFk385N78gDGIc/oav7PKaf +8MOh2tTYbitTkPskpD6E8J7oX+zlJ0T1KKY/e97gKvDIr1MvnsoFAZMej2YcOadN ++lq2cwQlZut3f+dZxkqZJRRU6ybH838Z1TBwj6+wRir/resp7defqgSHo9T5iaU0 +X9tDkYI22WY8sbi5gv2cOj4QyDvvBmVmepsZGD3/cVE8MC5fvj13c7JdBmzDI1aa +K4UmkhynArPkPw2vCHmCuDY96pzTNbO8acr1zJ3o/WSNF4Azbl5KXZnJHoe0nRrA +1W4TNSNe35tfPe/W93bC6j67eA0cQmdrBNj41tpvi/JEoAGrAgEDo4HFMIHCMB0G +A1UdDgQWBBS/X7fRzt0fhvRbVazc1xDCDqmI5zCBkgYDVR0jBIGKMIGHgBS/X7fR +zt0fhvRbVazc1xDCDqmI56FspGowaDELMAkGA1UEBhMCVVMxJTAjBgNVBAoTHFN0 +YXJmaWVsZCBUZWNobm9sb2dpZXMsIEluYy4xMjAwBgNVBAsTKVN0YXJmaWVsZCBD +bGFzcyAyIENlcnRpZmljYXRpb24gQXV0aG9yaXR5ggEAMAwGA1UdEwQFMAMBAf8w +DQYJKoZIhvcNAQEFBQADggEBAAWdP4id0ckaVaGsafPzWdqbAYcaT1epoXkJKtv3 +L7IezMdeatiDh6GX70k1PncGQVhiv45YuApnP+yz3SFmH8lU+nLMPUxA2IGvd56D +eruix/U0F47ZEUD0/CwqTRV/p2JdLiXTAAsgGh1o+Re49L2L7ShZ3U0WixeDyLJl +xy16paq8U4Zt3VekyvggQQto8PT7dL5WXXp59fkdheMtlb71cZBDzI0fmgAKhynp +VSJYACPq4xJDKVtHCN2MQWplBqjlIapBtJUhlbl90TSrE9atvNziPTnNvT51cKEY +WQPJIrSPnNVeKtelttQKbfi3QBFGmh95DmK/D5fs4C8fF5Q= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/starfieldrootg2ca b/make/data/cacerts/starfieldrootg2ca new file mode 100644 index 0000000..bea888c --- /dev/null +++ b/make/data/cacerts/starfieldrootg2ca
@@ -0,0 +1,30 @@ +Owner: CN=Starfield Root Certificate Authority - G2, O="Starfield Technologies, Inc.", L=Scottsdale, ST=Arizona, C=US +Issuer: CN=Starfield Root Certificate Authority - G2, O="Starfield Technologies, Inc.", L=Scottsdale, ST=Arizona, C=US +Serial number: 0 +Valid from: Tue Sep 01 00:00:00 GMT 2009 until: Thu Dec 31 23:59:59 GMT 2037 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIID3TCCAsWgAwIBAgIBADANBgkqhkiG9w0BAQsFADCBjzELMAkGA1UEBhMCVVMx +EDAOBgNVBAgTB0FyaXpvbmExEzARBgNVBAcTClNjb3R0c2RhbGUxJTAjBgNVBAoT +HFN0YXJmaWVsZCBUZWNobm9sb2dpZXMsIEluYy4xMjAwBgNVBAMTKVN0YXJmaWVs +ZCBSb290IENlcnRpZmljYXRlIEF1dGhvcml0eSAtIEcyMB4XDTA5MDkwMTAwMDAw +MFoXDTM3MTIzMTIzNTk1OVowgY8xCzAJBgNVBAYTAlVTMRAwDgYDVQQIEwdBcml6 +b25hMRMwEQYDVQQHEwpTY290dHNkYWxlMSUwIwYDVQQKExxTdGFyZmllbGQgVGVj +aG5vbG9naWVzLCBJbmMuMTIwMAYDVQQDEylTdGFyZmllbGQgUm9vdCBDZXJ0aWZp +Y2F0ZSBBdXRob3JpdHkgLSBHMjCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoC +ggEBAL3twQP89o/8ArFvW59I2Z154qK3A2FWGMNHttfKPTUuiUP3oWmb3ooa/RMg +nLRJdzIpVv257IzdIvpy3Cdhl+72WoTsbhm5iSzchFvVdPtrX8WJpRBSiUZV9Lh1 +HOZ/5FSuS/hVclcCGfgXcVnrHigHdMWdSL5stPSksPNkN3mSwOxGXn/hbVNMYq/N +Hwtjuzqd+/x5AJhhdM8mgkBj87JyahkNmcrUDnXMN/uLicFZ8WJ/X7NfZTD4p7dN +dloedl40wOiWVpmKs/B/pM293DIxfJHP4F8R+GuqSVzRmZTRouNjWwl2tVZi4Ut0 +HZbUJtQIBFnQmA4O5t78w+wfkPECAwEAAaNCMEAwDwYDVR0TAQH/BAUwAwEB/zAO +BgNVHQ8BAf8EBAMCAQYwHQYDVR0OBBYEFHwMMh+n2TB/xH1oo2Kooc6rB1snMA0G +CSqGSIb3DQEBCwUAA4IBAQARWfolTwNvlJk7mh+ChTnUdgWUXuEok21iXQnCoKjU +sHU48TRqneSfioYmUeYs0cYtbpUgSpIB7LiKZ3sx4mcujJUDJi5DnUox9g61DLu3 +4jd/IroAow57UvtruzvE03lRTs2Q9GcHGcg8RnoNAX3FWOdt5oUwF5okxBDgBPfg +8n/Uqgr/Qh037ZTlZFkSIHc40zI+OIF1lnP6aI+xy84fxez6nH7PfrHxBy22/L/K +pL/QlwVKvOoYKAKQvVR4CSFx09F9HdkWsKlhPdAKACL8x3vLCWRFCztAgfd9fDL1 +mMpYjn0q7pBZc2T5NnReJaH1ZgUufzkVqSr7UIuOhWn0 +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/starfieldservicesrootg2ca b/make/data/cacerts/starfieldservicesrootg2ca new file mode 100644 index 0000000..7303f09 --- /dev/null +++ b/make/data/cacerts/starfieldservicesrootg2ca
@@ -0,0 +1,31 @@ +Owner: CN=Starfield Services Root Certificate Authority - G2, O="Starfield Technologies, Inc.", L=Scottsdale, ST=Arizona, C=US +Issuer: CN=Starfield Services Root Certificate Authority - G2, O="Starfield Technologies, Inc.", L=Scottsdale, ST=Arizona, C=US +Serial number: 0 +Valid from: Tue Sep 01 00:00:00 GMT 2009 until: Thu Dec 31 23:59:59 GMT 2037 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIID7zCCAtegAwIBAgIBADANBgkqhkiG9w0BAQsFADCBmDELMAkGA1UEBhMCVVMx +EDAOBgNVBAgTB0FyaXpvbmExEzARBgNVBAcTClNjb3R0c2RhbGUxJTAjBgNVBAoT +HFN0YXJmaWVsZCBUZWNobm9sb2dpZXMsIEluYy4xOzA5BgNVBAMTMlN0YXJmaWVs +ZCBTZXJ2aWNlcyBSb290IENlcnRpZmljYXRlIEF1dGhvcml0eSAtIEcyMB4XDTA5 +MDkwMTAwMDAwMFoXDTM3MTIzMTIzNTk1OVowgZgxCzAJBgNVBAYTAlVTMRAwDgYD +VQQIEwdBcml6b25hMRMwEQYDVQQHEwpTY290dHNkYWxlMSUwIwYDVQQKExxTdGFy +ZmllbGQgVGVjaG5vbG9naWVzLCBJbmMuMTswOQYDVQQDEzJTdGFyZmllbGQgU2Vy +dmljZXMgUm9vdCBDZXJ0aWZpY2F0ZSBBdXRob3JpdHkgLSBHMjCCASIwDQYJKoZI +hvcNAQEBBQADggEPADCCAQoCggEBANUMOsQq+U7i9b4Zl1+OiFOxHz/Lz58gE20p +OsgPfTz3a3Y4Y9k2YKibXlwAgLIvWX/2h/klQ4bnaRtSmpDhcePYLQ1Ob/bISdm2 +8xpWriu2dBTrz/sm4xq6HZYuajtYlIlHVv8loJNwU4PahHQUw2eeBGg6345AWh1K +Ts9DkTvnVtYAcMtS7nt9rjrnvDH5RfbCYM8TWQIrgMw0R9+53pBlbQLPLJGmpufe +hRhJfGZOozptqbXuNC66DQO4M99H67FrjSXZm86B0UVGMpZwh94CDklDhbZsc7tk +6mFBrMnUVN+HL8cisibMn1lUaJ/8viovxFUcdUBgF4UCVTmLfwUCAwEAAaNCMEAw +DwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwHQYDVR0OBBYEFJxfAN+q +AdcwKziIorhtSpzyEZGDMA0GCSqGSIb3DQEBCwUAA4IBAQBLNqaEd2ndOxmfZyMI +bw5hyf2E3F/YNoHN2BtBLZ9g3ccaaNnRbobhiCPPE95Dz+I0swSdHynVv/heyNXB +ve6SbzJ08pGCL72CQnqtKrcgfU28elUSwhXqvfdqlS5sdJ/PHLTyxQGjhdByPq1z +qwubdQxtRbeOlKyWN7Wg0I8VRw7j6IPdj/3vQQF3zCepYoUz8jcI73HPdwbeyBkd +iEDPfUYd/x7H4c7/I9vG+o1VTqkC50cRRj70/b17KSa7qWFiNyi2LSr2EIZkyXCn +0q23KXB56jzaYyWf/Wi3MOxw+3WKt21gZ7IeyLnp2KhvAotnDU0mV3HaIPzBSlCN +sSi6 +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/swisssigngoldg2ca b/make/data/cacerts/swisssigngoldg2ca new file mode 100644 index 0000000..3558909 --- /dev/null +++ b/make/data/cacerts/swisssigngoldg2ca
@@ -0,0 +1,40 @@ +Owner: CN=SwissSign Gold CA - G2, O=SwissSign AG, C=CH +Issuer: CN=SwissSign Gold CA - G2, O=SwissSign AG, C=CH +Serial number: bb401c43f55e4fb0 +Valid from: Wed Oct 25 08:30:35 GMT 2006 until: Sat Oct 25 08:30:35 GMT 2036 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFujCCA6KgAwIBAgIJALtAHEP1Xk+wMA0GCSqGSIb3DQEBBQUAMEUxCzAJBgNV +BAYTAkNIMRUwEwYDVQQKEwxTd2lzc1NpZ24gQUcxHzAdBgNVBAMTFlN3aXNzU2ln +biBHb2xkIENBIC0gRzIwHhcNMDYxMDI1MDgzMDM1WhcNMzYxMDI1MDgzMDM1WjBF +MQswCQYDVQQGEwJDSDEVMBMGA1UEChMMU3dpc3NTaWduIEFHMR8wHQYDVQQDExZT +d2lzc1NpZ24gR29sZCBDQSAtIEcyMIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIIC +CgKCAgEAr+TufoskDhJuqVAtFkQ7kpJcyrhdhJJCEyq8ZVeCQD5XJM1QiyUqt2/8 +76LQwB8CJEoTlo8jE+YoWACjR8cGp4QjK7u9lit/VcyLwVcfDmJlD909Vopz2q5+ +bbqBHH5CjCA12UNNhPqE21Is8w4ndwtrvxEvcnifLtg+5hg3Wipy+dpikJKVyh+c +6bM8K8vzARO/Ws/BtQpgvd21mWRTuKCWs2/iJneRjOBiEAKfNA+k1ZIzUd6+jbqE +emA8atufK+ze3gE/bk3lUIbLtK/tREDFylqM2tIrfKjuvqblCqoOpd8FUrdVxyJd +MmqXl2MT28nbeTZ7hTpKxVKJ+STnnXepgv9VHKVxaSvRAiTysybUa9oEVeXBCsdt +MDeQKuSeFDNeFhdVxVu1yzSJkvGdJo+hB9TGsnhQ2wwMC3wLjEHXuendjIj3o02y +MszYF9rNt85mndT9Xv+9lz4pded+p2JYryU0pUHHPbwNUMoDAw8IWh+Vc3hiv69y +FGkOpeUDDniOJihC8AcLYiAQZzlG+qkDzAQ4embvIIO1jEpWjpEA/I5cgt6IoMPi +aG59je883WX0XaxR7ySArqpWl2/5rX3aYT+YdzylkbYcjCbaZaIJbcHiVOO5ykxM +gI93e2CaHt+28kgeDrpOVG2Y4OGiGqJ3UM/EY5LsRxmd6+ZrzsECAwEAAaOBrDCB +qTAOBgNVHQ8BAf8EBAMCAQYwDwYDVR0TAQH/BAUwAwEB/zAdBgNVHQ4EFgQUWyV7 +lqRlUX64OfPAeGZe6Drn8O4wHwYDVR0jBBgwFoAUWyV7lqRlUX64OfPAeGZe6Drn +8O4wRgYDVR0gBD8wPTA7BglghXQBWQECAQEwLjAsBggrBgEFBQcCARYgaHR0cDov +L3JlcG9zaXRvcnkuc3dpc3NzaWduLmNvbS8wDQYJKoZIhvcNAQEFBQADggIBACe6 +45R88a7A3hfm5djV9VSwg/S7zV4Fe0+fdWavPOhWfvxyeDgD2StiGwC5+OlgzczO +UYrHUDFu4Up+GC9pWbY9ZIEr44OE5iKHjn3g7gKZYbge9LgriBIWhMIxkziWMaa5 +O1M/wySTVltpkuzFwbs4AOPsF6m43Md8AYOfMke6UiI0HTJ6CVanfCU2qT1L2sCC +bwq7EsiHSycR+R4tx5M/nttfJmtS2S6K8RTGRI0Vqbe/vd6mGu6uLftIdxf+u+yv +GPUqUfA5hJeVbG4bwyvEdGB5JbAKJ9/fXtI5z0V9QkvfsywexcZdylU6oJxpmo/a +77KwPJ+HbBIrZXAVUjEaJM9vMSNQH4xPjyPDdEFjHFWoFN0+4FFQz/EbMFYOkrCC +hdiDyyJkvC24JdVUorgG6q2SpCSgwYa1ShNqR88uC1aVVMvOmttqtKay20EIhid3 +92qgQmwLOM7XdVAyksLfKzAiSNDVQTglXaTpXZ/GlHXQRf0wl0OPkKsKx4ZzYEpp +Ld6leNcG2mqeSz53OiATIgHQv2ieY2BrNU0LbbqhPcCT4H8js1WtciVORvnSFu+w +ZMEBnunKoGqYDs/YYPIvSbjkQuE4NRb0yG5P94FW6LqjviOvrv1vA+ACOzB2+htt +Qc8Bsem4yWb02ybzOqR08kkkW8mw0FfB+j564ZfJ +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/swisssignplatinumg2ca b/make/data/cacerts/swisssignplatinumg2ca new file mode 100644 index 0000000..774bef8 --- /dev/null +++ b/make/data/cacerts/swisssignplatinumg2ca
@@ -0,0 +1,40 @@ +Owner: CN=SwissSign Platinum CA - G2, O=SwissSign AG, C=CH +Issuer: CN=SwissSign Platinum CA - G2, O=SwissSign AG, C=CH +Serial number: 4eb200670c035d4f +Valid from: Wed Oct 25 08:36:00 GMT 2006 until: Sat Oct 25 08:36:00 GMT 2036 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFwTCCA6mgAwIBAgIITrIAZwwDXU8wDQYJKoZIhvcNAQEFBQAwSTELMAkGA1UE +BhMCQ0gxFTATBgNVBAoTDFN3aXNzU2lnbiBBRzEjMCEGA1UEAxMaU3dpc3NTaWdu +IFBsYXRpbnVtIENBIC0gRzIwHhcNMDYxMDI1MDgzNjAwWhcNMzYxMDI1MDgzNjAw +WjBJMQswCQYDVQQGEwJDSDEVMBMGA1UEChMMU3dpc3NTaWduIEFHMSMwIQYDVQQD +ExpTd2lzc1NpZ24gUGxhdGludW0gQ0EgLSBHMjCCAiIwDQYJKoZIhvcNAQEBBQAD +ggIPADCCAgoCggIBAMrfogLi2vj8Bxax3mCq3pZcZB/HL37PZ/pEQtZ2Y5Wu669y +IIpFR4ZieIbWIDkm9K6j/SPnpZy1IiEZtzeTIsBQnIJ71NUERFzLtMKfkr4k2Htn +IuJpX+UFeNSH2XFwMyVTtIc7KZAoNppVRDBopIOXfw0enHb/FZ1glwCNioUD7IC+ +6ixuEFGSzH7VozPY1kneWCqv9hbrS3uQMpe5up1Y8fhXSQQeol0GcN1x2/ndi5ob +jM89o03Oy3z2u5yg+gnOI2Ky6Q0f4nIoj5+saCB9bzuohTEJfwvH6GXp43gOCWcw +izSC+13gzJ2BbWLuCB4ELE6b7P6pT1/9aXjvCR+htL/68++QHkwFix7qepF6w9fl ++zC8bBsQWJj3Gl/QKTIDE0ZNYWqFTFJ0LwYfexHihJfGmfNtf9dng34TaNhxKFrY +zt3oEBSa/m0jh26OWnA81Y0JAKeqvLAxN23IhBQeW71FYyBrS3SMvds6DsHPWhaP +pZjydomyExI7C3d3rLvlPClKknLKYRorXkzig3R3+jVIeoVNjZpTxN94ypeRSCtF +KwH3HBqi7Ri6Cr2D+m+8jVeTO9TUps4e8aCxzqv9KyiaTxvXw3LbpMS/XUz13XuW +ae5ogObnmLo2t/5u7Su9IPhlGdpVCX4l3P5hYnL5fhgC72O00Puv5TtjjGePAgMB +AAGjgawwgakwDgYDVR0PAQH/BAQDAgEGMA8GA1UdEwEB/wQFMAMBAf8wHQYDVR0O +BBYEFFCvzAeHFUdvOMW0ZdHelarp35zMMB8GA1UdIwQYMBaAFFCvzAeHFUdvOMW0 +ZdHelarp35zMMEYGA1UdIAQ/MD0wOwYJYIV0AVkBAQEBMC4wLAYIKwYBBQUHAgEW +IGh0dHA6Ly9yZXBvc2l0b3J5LnN3aXNzc2lnbi5jb20vMA0GCSqGSIb3DQEBBQUA +A4ICAQAIhab1Fgz8RBrBY+D5VUYI/HAcQiiWjrfFwUF1TglxeeVtlspLpYhg0DB0 +uMoI3LQwnkAHFmtllXcBrqS3NQuB2nEVqXQXOHtYyvkv+8Bldo1bAbl93oI9ZLi+ +FHSjClTTLJUYFzX1UWs/j6KWYTl4a0vlpqD4U99REJNi54Av4tHgvI42Rncz7Lj7 +jposiU0xEQ8mngS7twSNC/K5/FqdOxa3L8iYq/6KUFkuozv8KV2LwUvJ4ooTHbG/ +u0IdUt1O2BReEMYxB+9xJ/cbOQncguqLs5WGXv312l0xpuAxtpTmREl0xRbl9x8D +YSjFyMsSoEJL+WuICI20MhjzdZ/EfwBPBZWcoxcCw7NTm6ogOSkrZvqdr16zktK1 +puEa+S1BaYEUtLS17Yk9zvupnTVCRLEcFHOBzyoBNZox1S2PbYTfgE1X4z/FhHXa +icYwu+uPyyIIoK6q8QNsOktNCaUOcsZWayFCTiMlFGiudgp8DAdwZPmaL/YFOSbG +DI8Zf0NebvRbFS/bYV3mZy8/CJT5YLSYMdp08YSTcU1f+2BY0fvEwW2JorsgH51x +kcsymxM9Pn2SUjWskpSi0xjCfMfqr3YFFt1nJ8J+HAciIfNAChs0B0QTwoRqjt8Z +Wr9/6x3iGjjRXK9HkmuAtTClyY3YqzGBH9/CZjfTk6mFhnll0g== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/swisssignsilverg2ca b/make/data/cacerts/swisssignsilverg2ca new file mode 100644 index 0000000..7a1eed1 --- /dev/null +++ b/make/data/cacerts/swisssignsilverg2ca
@@ -0,0 +1,40 @@ +Owner: CN=SwissSign Silver CA - G2, O=SwissSign AG, C=CH +Issuer: CN=SwissSign Silver CA - G2, O=SwissSign AG, C=CH +Serial number: 4f1bd42f54bb2f4b +Valid from: Wed Oct 25 08:32:46 GMT 2006 until: Sat Oct 25 08:32:46 GMT 2036 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFvTCCA6WgAwIBAgIITxvUL1S7L0swDQYJKoZIhvcNAQEFBQAwRzELMAkGA1UE +BhMCQ0gxFTATBgNVBAoTDFN3aXNzU2lnbiBBRzEhMB8GA1UEAxMYU3dpc3NTaWdu +IFNpbHZlciBDQSAtIEcyMB4XDTA2MTAyNTA4MzI0NloXDTM2MTAyNTA4MzI0Nlow +RzELMAkGA1UEBhMCQ0gxFTATBgNVBAoTDFN3aXNzU2lnbiBBRzEhMB8GA1UEAxMY +U3dpc3NTaWduIFNpbHZlciBDQSAtIEcyMIICIjANBgkqhkiG9w0BAQEFAAOCAg8A +MIICCgKCAgEAxPGHf9N4Mfc4yfjDmUO8x/e8N+dOcbpLj6VzHVxumK4DV644N0Mv +Fz0fyM5oEMF4rhkDKxD6LHmD9ui5aLlV8gREpzn5/ASLHvGiTSf5YXu6t+WiE7br +YT7QbNHm+/pe7R20nqA1W6GSy/BJkv6FCgU+5tkL4k+73JU3/JHpMjUi0R86TieF +nbAVlDLaYQ1HTWBCrpJH6INaUFjpiou5XaHc3ZlKHzZnu0jkg7Y360g6rw9njxcH +6ATK72oxh9TAtvmUcXtnZLi2kUpCe2UuMGoM9ZDulebyzYLs2aFK7PayS+VFheZt +eJMELpyCbTapxDFkH4aDCyr0NQp4yVXPQbBH6TCfmb5hqAaEuSh6XzjZG6k4sIN/ +c8HDO0gqgg8hm7jMqDXDhBuDsz6+pJVpATqJAHgE2cn0mRmrVn5bi4Y5FZGkECwJ +MoBgs5PAKrYYC51+jUnyEEp/+dVGLxmSo5mnJqy7jDzmDrxHB9xzUfFwZC8I+bRH +HTBsROopN4WSaGa8gzj+ezku01DwH/teYLappvonQfGbGHLy9YR0SslnxFSuSGTf +jNFusB3hB48IHpmccelM2KX3RxIfdNFRnobzwqIjQAtz20um53MGjMGg6cFZrEb6 +5i/4z3GcRm25xBWNOHkDRUjvxF3XCO6HOSKGsg0PWEP3calILv3q1h8CAwEAAaOB +rDCBqTAOBgNVHQ8BAf8EBAMCAQYwDwYDVR0TAQH/BAUwAwEB/zAdBgNVHQ4EFgQU +F6DNweRBtjpbO8tFnb0cwpj6hlgwHwYDVR0jBBgwFoAUF6DNweRBtjpbO8tFnb0c +wpj6hlgwRgYDVR0gBD8wPTA7BglghXQBWQEDAQEwLjAsBggrBgEFBQcCARYgaHR0 +cDovL3JlcG9zaXRvcnkuc3dpc3NzaWduLmNvbS8wDQYJKoZIhvcNAQEFBQADggIB +AHPGgeAn0i0P4JUw4ppBf1AsX19iYamGamkYDHRJ1l2E6kFSGG9YrVBWIGrGvShp +WJHckRE1qTodvBqlYJ7YH39FkWnZfrt4csEGDyrOj4VwYaygzQu4OSlWhDJOhrs9 +xCrZ1x9y7v5RoSJBsXECYxqCsGKrXlcSH9/L3XWgwF15kIwb4FDm3jH+mHtwX6WQ +2K34ArZv02DdQEsixT2tOnqfGhpHkXkzuoLcMmkDlm4fS/Bx/uNncqCxv1yL5PqZ +IseEuRuNI5c/7SXgz2W79WEE790eslpBIlqhn10s6FvJbakMDHiqYMZWjwFaDGi8 +aRl5xB9+lwW/xekkUV7U1UtT7dkjWjYDZaPBA61BMPNGG4WQr2W11bHkFlt4dR2X +em1ZqSqPe97Dh4kQmUlzeMg9vVE1dCrV8X5pGyq7O70luJpaPXJhkGaH7gzWTdQR +dAtq/gsD/KNVV4n+SsuuWxcFyPKNIzFTONItaj+CuY0IavdeQXRuwxF+B6wpYJE/ +OMpXEA29MC/HpeZBoNquBYeaoKRlbEwJDIm6uNO5wJOKMPqN5ZprFQFOZ6raYlY+ +hAhm0sQ2fac+EPyI4NSA5QC9qvNOBqN6avlicuMJT+ubDgEj8Z+7fNzcbBGXJbLy +tGMU0gYqZ4yD9c7qB9iaah7s5Aq7KkzrCWA5zspi2C5u +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/teliasonerarootcav1 b/make/data/cacerts/teliasonerarootcav1 new file mode 100644 index 0000000..26512c9 --- /dev/null +++ b/make/data/cacerts/teliasonerarootcav1
@@ -0,0 +1,37 @@ +Owner: CN=TeliaSonera Root CA v1, O=TeliaSonera +Issuer: CN=TeliaSonera Root CA v1, O=TeliaSonera +Serial number: 95be16a0f72e46f17b398272fa8bcd96 +Valid from: Thu Oct 18 12:00:50 GMT 2007 until: Mon Oct 18 12:00:50 GMT 2032 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIFODCCAyCgAwIBAgIRAJW+FqD3LkbxezmCcvqLzZYwDQYJKoZIhvcNAQEFBQAw +NzEUMBIGA1UECgwLVGVsaWFTb25lcmExHzAdBgNVBAMMFlRlbGlhU29uZXJhIFJv +b3QgQ0EgdjEwHhcNMDcxMDE4MTIwMDUwWhcNMzIxMDE4MTIwMDUwWjA3MRQwEgYD +VQQKDAtUZWxpYVNvbmVyYTEfMB0GA1UEAwwWVGVsaWFTb25lcmEgUm9vdCBDQSB2 +MTCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAMK+6yfwIaPzaSZVfp3F +VRaRXP3vIb9TgHot0pGMYzHw7CTww6XScnwQbfQ3t+XmfHnqjLWCi65ItqwA3GV1 +7CpNX8GH9SBlK4GoRz6JI5UwFpB/6FcHSOcZrr9FZ7E3GwYq/t75rH2D+1665I+X +Z75Ljo1kB1c4VWk0Nj0TSO9P4tNmHqTPGrdeNjPUtAa9GAH9d4RQAEX1jF3oI7x+ +/jXh7VB7qTCNGdMJjmhnXb88lxhTuylixcpecsHHltTbLaC0H2kD7OriUPEMPPCs +81Mt8Bz17Ww5OXOAFshSsCPN4D7c3TxHoLs1iuKYaIu+5b9y7tL6pe0S7fyYGKkm +dtwoSxAgHNN/Fnct7W+A90m7UwW7XWjH1Mh1Fj+JWov3F0fUTPHSiXk+TT2YqGHe +Oh7S+F4D4MHJHIzTjU3TlTazN19jY5szFPAtJmtTfImMMsJu7D0hADnJoWjiUIMu +sDor8zagrC/kb2HCUQk5PotTubtn2txTuXZZNp1D5SDgPTJghSJRt8czu90VL6R4 +pgd7gUY2BIbdeTXHlSw7sKMXNeVzH7RcWe/a6hBle3rQf5+ztCo3O3CLm1u5K7fs +slESl1MpWtTwEhDcTwK7EpIvYtQ/aUN8Ddb8WHUBiJ1YFkveupD/RwGJBmr2X7KQ +arMCpgKIv7NHfirZ1fpoeDVNAgMBAAGjPzA9MA8GA1UdEwEB/wQFMAMBAf8wCwYD +VR0PBAQDAgEGMB0GA1UdDgQWBBTwj1k4ALP1j5qWDNXr+nuqF+gTEjANBgkqhkiG +9w0BAQUFAAOCAgEAvuRcYk4k9AwI//DTDGjkk0kiP0Qnb7tt3oNmzqjMDfz1mgbl +dxSR651Be5kqhOX//CHBXfDkH1e3damhXwIm/9fH907eT/j3HEbAek9ALCI18Bmx +0GtnLLCo4MBANzX2hFxc469CeP6nyQ1Q6g2EdvZR74NTxnr/DlZJLo961gzmJ1Tj +TQpgcmLNkQfWpb/ImWvtxBnmq0wROMVvMeJuScg/doAmAyYp4Db29iBT4xdwNBed +Y2gea+zDTYa4EzAvXUYNR0PVG6pZDrlcjQZIrXSHX8f8MVRBE+LHIQ6e4B4N4cB7 +Q4WQxYpYxmUKeFfyxiMPAdkgS94P+5KFdSpcc41teyWRyu5FrgZLAMzTsVlQ2jqI +OylDRl6XK1TOU2+NSueW+r9xDkKLfP0ooNBIytrEgUy7onOTJsjrDNYmiLbAJM+7 +vVvrdX3pCI6GMyx5dwlppYn8s3CQh3aP0yK7Qs69cwsgJirQmz1wHiRszYd2qReW +t88NkvuOGKmYSdGe/mBEciG5Ge3C9THxOUiIkCR1VBatzvT4aRRkOfujuLpwQMcn +HL/EVlP6Y2XQ8xwOFvVrhlhNGNTkDY6lnVuR3HYkUD/GKvvZt5y11ubQ2egZixVx +SK236thZiNSQvxaz2emsWWFUyBy6ysHK4bkgTI86k4mloMy/0/Z1pHWWbVY= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/thawteprimaryrootca b/make/data/cacerts/thawteprimaryrootca new file mode 100644 index 0000000..9dc4dd8 --- /dev/null +++ b/make/data/cacerts/thawteprimaryrootca
@@ -0,0 +1,32 @@ +Owner: CN=thawte Primary Root CA, OU="(c) 2006 thawte, Inc. - For authorized use only", OU=Certification Services Division, O="thawte, Inc.", C=US +Issuer: CN=thawte Primary Root CA, OU="(c) 2006 thawte, Inc. - For authorized use only", OU=Certification Services Division, O="thawte, Inc.", C=US +Serial number: 344ed55720d5edec49f42fce37db2b6d +Valid from: Fri Nov 17 00:00:00 GMT 2006 until: Wed Jul 16 23:59:59 GMT 2036 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEIDCCAwigAwIBAgIQNE7VVyDV7exJ9C/ON9srbTANBgkqhkiG9w0BAQUFADCB +qTELMAkGA1UEBhMCVVMxFTATBgNVBAoTDHRoYXd0ZSwgSW5jLjEoMCYGA1UECxMf +Q2VydGlmaWNhdGlvbiBTZXJ2aWNlcyBEaXZpc2lvbjE4MDYGA1UECxMvKGMpIDIw +MDYgdGhhd3RlLCBJbmMuIC0gRm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxHzAdBgNV +BAMTFnRoYXd0ZSBQcmltYXJ5IFJvb3QgQ0EwHhcNMDYxMTE3MDAwMDAwWhcNMzYw +NzE2MjM1OTU5WjCBqTELMAkGA1UEBhMCVVMxFTATBgNVBAoTDHRoYXd0ZSwgSW5j +LjEoMCYGA1UECxMfQ2VydGlmaWNhdGlvbiBTZXJ2aWNlcyBEaXZpc2lvbjE4MDYG +A1UECxMvKGMpIDIwMDYgdGhhd3RlLCBJbmMuIC0gRm9yIGF1dGhvcml6ZWQgdXNl +IG9ubHkxHzAdBgNVBAMTFnRoYXd0ZSBQcmltYXJ5IFJvb3QgQ0EwggEiMA0GCSqG +SIb3DQEBAQUAA4IBDwAwggEKAoIBAQCsoPD7gFnUnMekz52hWXMJEEUMDSxuaPFs +W0hoSVk3/AszGcJ3f8wQLZU0HObrTQmnHNK4yZc2AreJ1CRfBsDMRJSUjQJib+ta +3RGNKJpchJAQeg29dGYvajig4tVUROsdB58Hum/u6f1OCyn1PoSgAfGcq/gcfomk +6KHYcWUNo1F77rzSImANuVud37r8UVsLr5iy6S7pBOhih94ryNdOwUxkHt3Ph1i6 +Sk/KaAcdHJ1KxtUvkcx8cXIcxcBn6zL9yZJclNqFwJu/U30rCfSMnZEfl2pSy94J +NqR32HuHUETVPm4pafs5SSYeCaWAe0At6+gnhcn+Yf1+5nyXHdWdAgMBAAGjQjBA +MA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQDAgEGMB0GA1UdDgQWBBR7W0XP +r87Lev0xkhpqtvNG61dIUDANBgkqhkiG9w0BAQUFAAOCAQEAeRHAS7ORtvzw6WfU +DW5FvlXok9LOAz/t2iWwHVfLHjp2oEzsUHboZHIMpKnxuIvW1oeEuzLlQRHAd9mz +YJ3rG9XRbkREqaYB7FViHXe4XI5ISXycO1cRrK1zN44veFyQaEfZYGDm/Ac9IiAX +xPcW6cTYcvnIc3zfFi8VqT79aie2oetaupgf1eNNZAqdE8hhuvU5HIe6uL17In/2 +/qxAeeWsEG89jxt5dovEN7MhGITlNgDrYyCZuen+MwS7QcjBAvlEYyCegc5C09Y/ +LHbTY5xZ3Y+m4Q6gLkH3LpVHz7z9M/P2C2F+fpErgUfCJzDupxBdN49cOSvkBPB7 +jVaMaA== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/thawteprimaryrootcag2 b/make/data/cacerts/thawteprimaryrootcag2 new file mode 100644 index 0000000..d604e2f --- /dev/null +++ b/make/data/cacerts/thawteprimaryrootcag2
@@ -0,0 +1,23 @@ +Owner: CN=thawte Primary Root CA - G2, OU="(c) 2007 thawte, Inc. - For authorized use only", O="thawte, Inc.", C=US +Issuer: CN=thawte Primary Root CA - G2, OU="(c) 2007 thawte, Inc. - For authorized use only", O="thawte, Inc.", C=US +Serial number: 35fc265cd9844fc93d263d579baed756 +Valid from: Mon Nov 05 00:00:00 GMT 2007 until: Mon Jan 18 23:59:59 GMT 2038 +Signature algorithm name: SHA384withECDSA +Subject Public Key Algorithm: 384-bit EC (secp384r1) key +Version: 3 +-----BEGIN CERTIFICATE----- +MIICiDCCAg2gAwIBAgIQNfwmXNmET8k9Jj1Xm67XVjAKBggqhkjOPQQDAzCBhDEL +MAkGA1UEBhMCVVMxFTATBgNVBAoTDHRoYXd0ZSwgSW5jLjE4MDYGA1UECxMvKGMp +IDIwMDcgdGhhd3RlLCBJbmMuIC0gRm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxJDAi +BgNVBAMTG3RoYXd0ZSBQcmltYXJ5IFJvb3QgQ0EgLSBHMjAeFw0wNzExMDUwMDAw +MDBaFw0zODAxMTgyMzU5NTlaMIGEMQswCQYDVQQGEwJVUzEVMBMGA1UEChMMdGhh +d3RlLCBJbmMuMTgwNgYDVQQLEy8oYykgMjAwNyB0aGF3dGUsIEluYy4gLSBGb3Ig +YXV0aG9yaXplZCB1c2Ugb25seTEkMCIGA1UEAxMbdGhhd3RlIFByaW1hcnkgUm9v +dCBDQSAtIEcyMHYwEAYHKoZIzj0CAQYFK4EEACIDYgAEotWcgnuVnfFSeIf+iha/ +BebfowJPDQfGAFG6DAJSLSKkQjnE/o/qycG+1E3/n3qe4rF8mq2nhglzh9HnmuN6 +papu+7qzcMBniKI11KOasf2twu8x+qi58/sIxpHR+ymVo0IwQDAPBgNVHRMBAf8E +BTADAQH/MA4GA1UdDwEB/wQEAwIBBjAdBgNVHQ4EFgQUmtgAMADna3+FGO6Lts6K +DPgR4bswCgYIKoZIzj0EAwMDaQAwZgIxAN344FdHW6fmCsO99YCKlzUNG4k8VIZ3 +KMqh9HneteY4sPBlcIx/AlTCv//YoT7ZzwIxAMSNlPzcU9LcnXgWHxUzI1NS41ox +XZ3Krr0TKUQNJ1uo52icEvdYPy5yAlejj6EULg== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/thawteprimaryrootcag3 b/make/data/cacerts/thawteprimaryrootcag3 new file mode 100644 index 0000000..396fc17 --- /dev/null +++ b/make/data/cacerts/thawteprimaryrootcag3
@@ -0,0 +1,32 @@ +Owner: CN=thawte Primary Root CA - G3, OU="(c) 2008 thawte, Inc. - For authorized use only", OU=Certification Services Division, O="thawte, Inc.", C=US +Issuer: CN=thawte Primary Root CA - G3, OU="(c) 2008 thawte, Inc. - For authorized use only", OU=Certification Services Division, O="thawte, Inc.", C=US +Serial number: 600197b746a7eab4b49ad64b2ff790fb +Valid from: Wed Apr 02 00:00:00 GMT 2008 until: Tue Dec 01 23:59:59 GMT 2037 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEKjCCAxKgAwIBAgIQYAGXt0an6rS0mtZLL/eQ+zANBgkqhkiG9w0BAQsFADCB +rjELMAkGA1UEBhMCVVMxFTATBgNVBAoTDHRoYXd0ZSwgSW5jLjEoMCYGA1UECxMf +Q2VydGlmaWNhdGlvbiBTZXJ2aWNlcyBEaXZpc2lvbjE4MDYGA1UECxMvKGMpIDIw +MDggdGhhd3RlLCBJbmMuIC0gRm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxJDAiBgNV +BAMTG3RoYXd0ZSBQcmltYXJ5IFJvb3QgQ0EgLSBHMzAeFw0wODA0MDIwMDAwMDBa +Fw0zNzEyMDEyMzU5NTlaMIGuMQswCQYDVQQGEwJVUzEVMBMGA1UEChMMdGhhd3Rl +LCBJbmMuMSgwJgYDVQQLEx9DZXJ0aWZpY2F0aW9uIFNlcnZpY2VzIERpdmlzaW9u +MTgwNgYDVQQLEy8oYykgMjAwOCB0aGF3dGUsIEluYy4gLSBGb3IgYXV0aG9yaXpl +ZCB1c2Ugb25seTEkMCIGA1UEAxMbdGhhd3RlIFByaW1hcnkgUm9vdCBDQSAtIEcz +MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAsr8nLPvb2FvdeHsbnndm +gcs+vHyu86YnmjSjaDFxODNi5PNxZnmxqWWjpYvVj2AtP0LMqmsywCPLLEHd5N/8 +YZzic7IilRFDGF/Eth9XbAoFWCLINkw6fKXRz4aviKdEAhN0cXMKQlkC+BsUa0Lf +b1+6a4KinVvnSr0eAXLbS3ToO39/fR8EtCab4LRarEc9VbjXsCZSKAExQGbY2SS9 +9irY7CFJXJv2eul/VTV+lmuNk5Mny5K76qxAwJ/C+IDPXfRa3M50hqY+bAtTyr2S +zhkGcuYMXDhpxwTWvGzOW/b3aJzcJRVIiKHpqfiYnODz1TEoYRFsZ5aNOZnLwkUk +OQIDAQABo0IwQDAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQEAwIBBjAdBgNV +HQ4EFgQUrWyqlGCc7eT/+j4KdCtjA/e2Wb8wDQYJKoZIhvcNAQELBQADggEBABpA +2JVlrAmSicY59BDlqQ5mU1143vokkbvnRFHfxhY0Cu9qRFHqKweKA3rD6z8KLFIW +oCtDuSWQP3CpMyVtRRooOyfPqsMpQhvfO0zAMzRbQYi/aytlryjvsvXDqmbOe1bu +t8jLZ8HJnBoYuMTDSQPxYA5QzUbF83d597YV4Djbxy8ooAw/dyZ02SUS2jHaGh7c +KUGRIjxpp7sC8rZcJwOJ9Abqm+RyguOhCcHpABnTPtRwa7pxpqpYrvS76Wy274fM +m7v/OeZWYdMKp8RcTGB7BXcmer/YB1IsYvdwY9k5vG8cwnncdimvzsUsZAReiDZu +MdRAGmI0Nj81Aa6sY6A= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/ttelesecglobalrootclass2ca b/make/data/cacerts/ttelesecglobalrootclass2ca new file mode 100644 index 0000000..1e057df --- /dev/null +++ b/make/data/cacerts/ttelesecglobalrootclass2ca
@@ -0,0 +1,30 @@ +Owner: CN=T-TeleSec GlobalRoot Class 2, OU=T-Systems Trust Center, O=T-Systems Enterprise Services GmbH, C=DE +Issuer: CN=T-TeleSec GlobalRoot Class 2, OU=T-Systems Trust Center, O=T-Systems Enterprise Services GmbH, C=DE +Serial number: 1 +Valid from: Wed Oct 01 10:40:14 GMT 2008 until: Sat Oct 01 23:59:59 GMT 2033 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDwzCCAqugAwIBAgIBATANBgkqhkiG9w0BAQsFADCBgjELMAkGA1UEBhMCREUx +KzApBgNVBAoMIlQtU3lzdGVtcyBFbnRlcnByaXNlIFNlcnZpY2VzIEdtYkgxHzAd +BgNVBAsMFlQtU3lzdGVtcyBUcnVzdCBDZW50ZXIxJTAjBgNVBAMMHFQtVGVsZVNl +YyBHbG9iYWxSb290IENsYXNzIDIwHhcNMDgxMDAxMTA0MDE0WhcNMzMxMDAxMjM1 +OTU5WjCBgjELMAkGA1UEBhMCREUxKzApBgNVBAoMIlQtU3lzdGVtcyBFbnRlcnBy +aXNlIFNlcnZpY2VzIEdtYkgxHzAdBgNVBAsMFlQtU3lzdGVtcyBUcnVzdCBDZW50 +ZXIxJTAjBgNVBAMMHFQtVGVsZVNlYyBHbG9iYWxSb290IENsYXNzIDIwggEiMA0G +CSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQCqX9obX+hzkeXaXPSi5kfl82hVYAUd +AqSzm1nzHoqvNK38DcLZSBnuaY/JIPwhqgcZ7bBcrGXHX+0CfHt8LRvWurmAwhiC +FoT6ZrAIxlQjgeTNuUk/9k9uN0goOA/FvudocP05l03Sx5iRUKrERLMjfTlH6VJi +1hKTXrcxlkIF+3anHqP1wvzpesVsqXFP6st4vGCvx9702cu+fjOlbpSD8DT6Iavq +jnKgP6TeMFvvhk1qlVtDRKgQFRzlAVfFmPHmBiiRqiDFt1MmUUOyCxGVWOHAD3bZ +wI18gfNycJ5v/hqO2V81xrJvNHy+SE/iWjnX2J14np+GPgNeGYtEotXHAgMBAAGj +QjBAMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQDAgEGMB0GA1UdDgQWBBS/ +WSA2AHmgoCJrjNXyYdK4LMuCSjANBgkqhkiG9w0BAQsFAAOCAQEAMQOiYQsfdOhy +NsZt+U2e+iKo4YFWz827n+qrkRk4r6p8FU3ztqONpfSO9kSpp+ghla0+AGIWiPAC +uvxhI+YzmzB6azZie60EI4RYZeLbK4rnJVM3YlNfvNoBYimipidx5joifsFvHZVw +IEoHNN/q/xWA5brXethbdXwFeilHfkCoMRN3zUA7tFFHei4R40cR3p1m0IvVVGb6 +g1XqfMIpiRvpb7PO4gWEyS8+eIVibslfwXhjdFjASBgMmTnrpMwatXlajRWc2BQN +9noHV8cigwUtPJslJj0Ys6lDfMjIq2SPDqO/nBudMNva0Bkuqjzx+zOAduTNrRlP +BSeOE6Fuwg== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/ttelesecglobalrootclass3ca b/make/data/cacerts/ttelesecglobalrootclass3ca new file mode 100644 index 0000000..8985014 --- /dev/null +++ b/make/data/cacerts/ttelesecglobalrootclass3ca
@@ -0,0 +1,30 @@ +Owner: CN=T-TeleSec GlobalRoot Class 3, OU=T-Systems Trust Center, O=T-Systems Enterprise Services GmbH, C=DE +Issuer: CN=T-TeleSec GlobalRoot Class 3, OU=T-Systems Trust Center, O=T-Systems Enterprise Services GmbH, C=DE +Serial number: 1 +Valid from: Wed Oct 01 10:29:56 GMT 2008 until: Sat Oct 01 23:59:59 GMT 2033 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDwzCCAqugAwIBAgIBATANBgkqhkiG9w0BAQsFADCBgjELMAkGA1UEBhMCREUx +KzApBgNVBAoMIlQtU3lzdGVtcyBFbnRlcnByaXNlIFNlcnZpY2VzIEdtYkgxHzAd +BgNVBAsMFlQtU3lzdGVtcyBUcnVzdCBDZW50ZXIxJTAjBgNVBAMMHFQtVGVsZVNl +YyBHbG9iYWxSb290IENsYXNzIDMwHhcNMDgxMDAxMTAyOTU2WhcNMzMxMDAxMjM1 +OTU5WjCBgjELMAkGA1UEBhMCREUxKzApBgNVBAoMIlQtU3lzdGVtcyBFbnRlcnBy +aXNlIFNlcnZpY2VzIEdtYkgxHzAdBgNVBAsMFlQtU3lzdGVtcyBUcnVzdCBDZW50 +ZXIxJTAjBgNVBAMMHFQtVGVsZVNlYyBHbG9iYWxSb290IENsYXNzIDMwggEiMA0G +CSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQC9dZPwYiJvJK7genasfb3ZJNW4t/zN +8ELg63iIVl6bmlQdTQyK9tPPcPRStdiTBONGhnFBSivwKixVA9ZIw+A5OO3yXDw/ +RLyTPWGrTs0NvvAgJ1gORH8EGoel15YUNpDQSXuhdfsaa3Ox+M6pCSzyU9XDFES4 +hqX2iys52qMzVNn6chr3IhUciJFrf2blw2qAsCTz34ZFiP0Zf3WHHx+xGwpzJFu5 +ZeAsVMhg02YXP+HMVDNzkQI6pn97djmiH5a2OK61yJN0HZ65tOVgnS9W0eDrXltM +EnAMbEQgqxHY9Bn20pxSN+f6tsIxO0rUFJmtxxr1XV/6B7h8DR/Wgx6zAgMBAAGj +QjBAMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQDAgEGMB0GA1UdDgQWBBS1 +A/d2O2GCahKqGFPrAyGUv/7OyjANBgkqhkiG9w0BAQsFAAOCAQEAVj3vlNW92nOy +WL6ukK2YJ5f+AbGwUgC4TeQbIXQbfsDuXmkqJa9c1h3a0nnJ85cp4IaH3gRZD/FZ +1GSFS5mvJQQeyUapl96Cshtwn5z2r3Ex3XsFpSzTucpH9sry9uetuUg/vBa3wW30 +6gmv7PO15wWeph6KU1HWk4HMdJP2udqmJQV0eVp+QD6CSyYRMG7hP0HHRwA11fXT +91Q+gT3aSWqas+8QPebrb9HIIkfLzM8BMZLZGOMivgkeGj5asuRrDFR6fUNOuIml +e9eiPZaGzPImNC1qkp2aGtAw4l1OBLBfiyB+d8E9lYLRRpo7PHi4b6HQDWSieB4p +TpPDpFQUWw== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/usertrusteccca b/make/data/cacerts/usertrusteccca new file mode 100644 index 0000000..9af9c94 --- /dev/null +++ b/make/data/cacerts/usertrusteccca
@@ -0,0 +1,23 @@ +Owner: CN=USERTrust ECC Certification Authority, O=The USERTRUST Network, L=Jersey City, ST=New Jersey, C=US +Issuer: CN=USERTrust ECC Certification Authority, O=The USERTRUST Network, L=Jersey City, ST=New Jersey, C=US +Serial number: 5c8b99c55a94c5d27156decd8980cc26 +Valid from: Mon Feb 01 00:00:00 GMT 2010 until: Mon Jan 18 23:59:59 GMT 2038 +Signature algorithm name: SHA384withECDSA +Subject Public Key Algorithm: 384-bit EC (secp384r1) key +Version: 3 +-----BEGIN CERTIFICATE----- +MIICjzCCAhWgAwIBAgIQXIuZxVqUxdJxVt7NiYDMJjAKBggqhkjOPQQDAzCBiDEL +MAkGA1UEBhMCVVMxEzARBgNVBAgTCk5ldyBKZXJzZXkxFDASBgNVBAcTC0plcnNl +eSBDaXR5MR4wHAYDVQQKExVUaGUgVVNFUlRSVVNUIE5ldHdvcmsxLjAsBgNVBAMT +JVVTRVJUcnVzdCBFQ0MgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkwHhcNMTAwMjAx +MDAwMDAwWhcNMzgwMTE4MjM1OTU5WjCBiDELMAkGA1UEBhMCVVMxEzARBgNVBAgT +Ck5ldyBKZXJzZXkxFDASBgNVBAcTC0plcnNleSBDaXR5MR4wHAYDVQQKExVUaGUg +VVNFUlRSVVNUIE5ldHdvcmsxLjAsBgNVBAMTJVVTRVJUcnVzdCBFQ0MgQ2VydGlm +aWNhdGlvbiBBdXRob3JpdHkwdjAQBgcqhkjOPQIBBgUrgQQAIgNiAAQarFRaqflo +I+d61SRvU8Za2EurxtW20eZzca7dnNYMYf3boIkDuAUU7FfO7l0/4iGzzvfUinng +o4N+LZfQYcTxmdwlkWOrfzCjtHDix6EznPO/LlxTsV+zfTJ/ijTjeXmjQjBAMB0G +A1UdDgQWBBQ64QmG1M8ZwpZ2dEl23OA1xmNjmjAOBgNVHQ8BAf8EBAMCAQYwDwYD +VR0TAQH/BAUwAwEB/zAKBggqhkjOPQQDAwNoADBlAjA2Z6EWCNzklwBBHU6+4WMB +zzuqQhFkoJ2UOQIReVx7Hfpkue4WQrO/isIJxOzksU0CMQDpKmFHjFJKS04YcPbW +RNZu9YO6bVi9JNlWSOrvxKJGgYhqOkbRqZtNyWHa0V1Xahg= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/usertrustrsaca b/make/data/cacerts/usertrustrsaca new file mode 100644 index 0000000..fe9ae79 --- /dev/null +++ b/make/data/cacerts/usertrustrsaca
@@ -0,0 +1,41 @@ +Owner: CN=USERTrust RSA Certification Authority, O=The USERTRUST Network, L=Jersey City, ST=New Jersey, C=US +Issuer: CN=USERTrust RSA Certification Authority, O=The USERTRUST Network, L=Jersey City, ST=New Jersey, C=US +Serial number: 1fd6d30fca3ca51a81bbc640e35032d +Valid from: Mon Feb 01 00:00:00 GMT 2010 until: Mon Jan 18 23:59:59 GMT 2038 +Signature algorithm name: SHA384withRSA +Subject Public Key Algorithm: 4096-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIF3jCCA8agAwIBAgIQAf1tMPyjylGoG7xkDjUDLTANBgkqhkiG9w0BAQwFADCB +iDELMAkGA1UEBhMCVVMxEzARBgNVBAgTCk5ldyBKZXJzZXkxFDASBgNVBAcTC0pl +cnNleSBDaXR5MR4wHAYDVQQKExVUaGUgVVNFUlRSVVNUIE5ldHdvcmsxLjAsBgNV +BAMTJVVTRVJUcnVzdCBSU0EgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkwHhcNMTAw +MjAxMDAwMDAwWhcNMzgwMTE4MjM1OTU5WjCBiDELMAkGA1UEBhMCVVMxEzARBgNV +BAgTCk5ldyBKZXJzZXkxFDASBgNVBAcTC0plcnNleSBDaXR5MR4wHAYDVQQKExVU +aGUgVVNFUlRSVVNUIE5ldHdvcmsxLjAsBgNVBAMTJVVTRVJUcnVzdCBSU0EgQ2Vy +dGlmaWNhdGlvbiBBdXRob3JpdHkwggIiMA0GCSqGSIb3DQEBAQUAA4ICDwAwggIK +AoICAQCAEmUXNg7D2wiz0KxXDXbtzSfTTK1Qg2HiqiBNCS1kCdzOiZ/MPans9s/B +3PHTsdZ7NygRK0faOca8Ohm0X6a9fZ2jY0K2dvKpOyuR+OJv0OwWIJAJPuLodMkY +tJHUYmTbf6MG8YgYapAiPLz+E/CHFHv25B+O1ORRxhFnRghRy4YUVD+8M/5+bJz/ +Fp0YvVGONaanZshyZ9shZrHUm3gDwFA66Mzw3LyeTP6vBZY1H1dat//O+T23LLb2 +VN3I5xI6Ta5MirdcmrS3ID3KfyI0rn47aGYBROcBTkZTmzNg95S+UzeQc0PzMsNT +79uq/nROacdrjGCT3sTHDN/hMq7MkztReJVni+49Vv4M0GkPGw/zJSZrM233bkf6 +c0Plfg6lZrEpfDKEY1WJxA3Bk1QwGROs0303p+tdOmw1XNtB1xLaqUkL39iAigmT +Yo61Zs8liM2EuLE/pDkP2QKe6xJMlXzzawWpXhaDzLhn4ugTncxbgtNMs+1b/97l +c6wjOy0AvzVVdAlJ2ElYGn+SNuZRkg7zJn0cTRe8yexDJtC/QV9AqURE9JnnV4ee +UB9XVKg+/XRjL7FQZQnmWEIuQxpMtPAlR1n6BB6T1CZGSlCBst6+eLf8ZxXhyVeE +Hg9j1uliutZfVS7qXMYoCAQlObgOK6nyTJccBz8NUvXt7y+CDwIDAQABo0IwQDAd +BgNVHQ4EFgQUU3m/WqorSs9UgOHYm8Cd8rIDZsswDgYDVR0PAQH/BAQDAgEGMA8G +A1UdEwEB/wQFMAMBAf8wDQYJKoZIhvcNAQEMBQADggIBAFzUfA3P9wF9QZllDHPF +Up/L+M+ZBn8b2kMVn54CVVeWFPFSPCeHlCjtHzoBN6J2/FNQwISbxmtOuowhT6KO +VWKR82kV2LyI48SqC/3vqOlLVSoGIG1VeCkZ7l8wXEskEVX/JJpuXior7gtNn3/3 +ATiUFJVDBwn7YKnuHKsSjKCaXqeYalltiz8I+8jRRa8YFWSQEg9zKC7F4iRO/Fjs +8PRF/iKz6y+O0tlFYQXBl2+odnKPi4w2r78NBc5xjeambx9spnFixdjQg3IM8WcR +iQycE0xyNN+81XHfqnHd4blsjDwSXWXavVcStkNr/+XeTWYRUc+ZruwXtuhxkYze +Sf7dNXGiFSeUHM9h4ya7b6NnJSFd5t0dCy5oGzuCr+yDZ4XUmFF0sbmZgIn/f3gZ +XHlKYC6SQK5MNyosycdiyA5d9zZbyuAlJQG03RoHnHcAP9Dc1ew91Pq7P8yF1m9/ +qS3fuQL39ZeatTXaw2ewh0qpKJ4jjv9cJ2vhsE/zB+4ALtRZh8tSQZXq9EfX7mRB +VXyNWQKV3WKdwrnuWih0hKWbt5DHDAff9Yk2dDLWKMGwsAvgnEzDHNb842m1R0aB +L6KCq9NjRHDEjf8tM7qtj3u1cIiuPhnPQCjY/MiQu12ZIvVS5ljFH4gxQ+6IHdfG +jjxDah2nGN59PRbxYvnKkKj9 +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/utnuserfirstobjectca b/make/data/cacerts/utnuserfirstobjectca new file mode 100644 index 0000000..80a0b5c --- /dev/null +++ b/make/data/cacerts/utnuserfirstobjectca
@@ -0,0 +1,33 @@ +Owner: CN=UTN-USERFirst-Object, OU=http://www.usertrust.com, O=The USERTRUST Network, L=Salt Lake City, ST=UT, C=US +Issuer: CN=UTN-USERFirst-Object, OU=http://www.usertrust.com, O=The USERTRUST Network, L=Salt Lake City, ST=UT, C=US +Serial number: 44be0c8b500024b411d3362de0b35f1b +Valid from: Fri Jul 09 18:31:20 GMT 1999 until: Tue Jul 09 18:40:36 GMT 2019 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEZjCCA06gAwIBAgIQRL4Mi1AAJLQR0zYt4LNfGzANBgkqhkiG9w0BAQUFADCB +lTELMAkGA1UEBhMCVVMxCzAJBgNVBAgTAlVUMRcwFQYDVQQHEw5TYWx0IExha2Ug +Q2l0eTEeMBwGA1UEChMVVGhlIFVTRVJUUlVTVCBOZXR3b3JrMSEwHwYDVQQLExho +dHRwOi8vd3d3LnVzZXJ0cnVzdC5jb20xHTAbBgNVBAMTFFVUTi1VU0VSRmlyc3Qt +T2JqZWN0MB4XDTk5MDcwOTE4MzEyMFoXDTE5MDcwOTE4NDAzNlowgZUxCzAJBgNV +BAYTAlVTMQswCQYDVQQIEwJVVDEXMBUGA1UEBxMOU2FsdCBMYWtlIENpdHkxHjAc +BgNVBAoTFVRoZSBVU0VSVFJVU1QgTmV0d29yazEhMB8GA1UECxMYaHR0cDovL3d3 +dy51c2VydHJ1c3QuY29tMR0wGwYDVQQDExRVVE4tVVNFUkZpcnN0LU9iamVjdDCC +ASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAM6qgT+jo2F4qjEAVZURnicP +HxzfOpuCaDDASmEd8S8O+r5596Uj71VRloTN2+O5bj4x2AogZ8f02b+U60cEPgLO +KqJdhwQJ9jCdGIqXsqoc/EHSoTbL+z2RuufZcDX65OeQw5ujm9M89RKZd7G3CeBo +5hy485RjiGpq/gt2yb70IuRnuasaXnfBhQfdDWy/7gbHd2pBnqcP1/vulBe3/IW+ +pKvEHDHd17bR5PDv3xaPslKT16HUiaEHLr/hARJCHhrh2JU022R5KP+6LhHC5ehb +kkj7RwvCbNqtMoNB86XlQXD9ZZBt+vpRxPm9lisZBCzTbafc8H9vg2XiaquHhnUC +AwEAAaOBrzCBrDALBgNVHQ8EBAMCAcYwDwYDVR0TAQH/BAUwAwEB/zAdBgNVHQ4E +FgQU2u1kdBScFDyr3ZmpvVsoTYs8ydgwQgYDVR0fBDswOTA3oDWgM4YxaHR0cDov +L2NybC51c2VydHJ1c3QuY29tL1VUTi1VU0VSRmlyc3QtT2JqZWN0LmNybDApBgNV +HSUEIjAgBggrBgEFBQcDAwYIKwYBBQUHAwgGCisGAQQBgjcKAwQwDQYJKoZIhvcN +AQEFBQADggEBAAgfUrE3RHjb/c652pWWmKpVZIC1WkDdIaXFwfNfLEzIR1pp6ujw +NTX00CXzyKakh0q9G7FzCL3Uw8q2NbtZhncxzaeAFK4T7/yxSPlrJSUtUbYsbUXB +mMiKVl0+7kNOPmsnjtA6S4ULX9Ptaqd1y9Fahy85dRNacrACgZ++8A+EVCBibGnU +4U3GDZlDAQ0Slox4nb9QorFEqmrPF3rPbw/U+CRVX/A0FklmPlBGyWNxODFiuGK5 +81OtbLUrohKqGU8J2l7nk8aOFAj+8DCAGKCGhU3IfdeLA/5u1fedFqySLKAj5ZyR +Uh+U3xeUc8OzwcFxBSAAeL0TUh2oPs0AH8g= +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/verisignclass3g3ca b/make/data/cacerts/verisignclass3g3ca new file mode 100644 index 0000000..b9c36ed --- /dev/null +++ b/make/data/cacerts/verisignclass3g3ca
@@ -0,0 +1,31 @@ +Owner: CN=VeriSign Class 3 Public Primary Certification Authority - G3, OU="(c) 1999 VeriSign, Inc. - For authorized use only", OU=VeriSign Trust Network, O="VeriSign, Inc.", C=US +Issuer: CN=VeriSign Class 3 Public Primary Certification Authority - G3, OU="(c) 1999 VeriSign, Inc. - For authorized use only", OU=VeriSign Trust Network, O="VeriSign, Inc.", C=US +Serial number: 9b7e0649a33e62b9d5ee90487129ef57 +Valid from: Fri Oct 01 00:00:00 GMT 1999 until: Wed Jul 16 23:59:59 GMT 2036 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 1 +-----BEGIN CERTIFICATE----- +MIIEGjCCAwICEQCbfgZJoz5iudXukEhxKe9XMA0GCSqGSIb3DQEBBQUAMIHKMQsw +CQYDVQQGEwJVUzEXMBUGA1UEChMOVmVyaVNpZ24sIEluYy4xHzAdBgNVBAsTFlZl +cmlTaWduIFRydXN0IE5ldHdvcmsxOjA4BgNVBAsTMShjKSAxOTk5IFZlcmlTaWdu +LCBJbmMuIC0gRm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxRTBDBgNVBAMTPFZlcmlT +aWduIENsYXNzIDMgUHVibGljIFByaW1hcnkgQ2VydGlmaWNhdGlvbiBBdXRob3Jp +dHkgLSBHMzAeFw05OTEwMDEwMDAwMDBaFw0zNjA3MTYyMzU5NTlaMIHKMQswCQYD +VQQGEwJVUzEXMBUGA1UEChMOVmVyaVNpZ24sIEluYy4xHzAdBgNVBAsTFlZlcmlT +aWduIFRydXN0IE5ldHdvcmsxOjA4BgNVBAsTMShjKSAxOTk5IFZlcmlTaWduLCBJ +bmMuIC0gRm9yIGF1dGhvcml6ZWQgdXNlIG9ubHkxRTBDBgNVBAMTPFZlcmlTaWdu +IENsYXNzIDMgUHVibGljIFByaW1hcnkgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkg +LSBHMzCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAMu6nFL8eB8aHm8b +N3O9+MlrlBIwT/A2R/XQkQr1F8ilYcEWQE37imGQ5XYgwREGfassbqb1EUGO+i2t +KmFZpGcmTNDovFJbcCAEWNF6yaRpvIMXZK0Fi7zQWM6NjPXr8EJJC52XJ2cybuGu +kxUccLwgTS8Y3pKI6GyFVxEa6X7jJhFUokWWVYPKMIno3Nij7SqAP395ZVc+FSBm +CC+Vk7+qRy+oRpfwEuL+wgorUeZ25rdGt+INpsyow0xZVYnm6FNcHOqd8GIWC6fJ +Xwzw3sJ2zq/3avL6QaaiMxTJ5Xpj055iN9WFZZ4O5lMkdBteHRJTW8cs54NJOxWu +imi5V5cCAwEAATANBgkqhkiG9w0BAQUFAAOCAQEAERSWwauSCPc/L8my/uRan2Te +2yFPhpk0djZX3dAVL8WtfxUfN2JzPtTnX84XA9s1+ivbrmAJXx5fj267Cz3qWhMe +DGBvtcC1IyIuBwvLqXTLR7sdwdela8wv0kL9Sd2nic9TutoAWii/gt/4uhMdUIaC +/Y4wjylGsB49Ndo4YhYYSq3mtlFs3q9i6wHQHiT+eo8SGhJouPtmmRQURVyu565p +F4ErWjfJXir0xuKhXFSbplQAz/DxwceYMBo7Nhbbo27q/a2ywtrvAkcTisDxszGt +TxzhT5yvDwyd93gN2PQ1VoDat20Xj50egWTh/sVFuq1ruQp6Tk9LhO5L8X3dEQ== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/verisignclass3g4ca b/make/data/cacerts/verisignclass3g4ca new file mode 100644 index 0000000..b52ee80 --- /dev/null +++ b/make/data/cacerts/verisignclass3g4ca
@@ -0,0 +1,28 @@ +Owner: CN=VeriSign Class 3 Public Primary Certification Authority - G4, OU="(c) 2007 VeriSign, Inc. - For authorized use only", OU=VeriSign Trust Network, O="VeriSign, Inc.", C=US +Issuer: CN=VeriSign Class 3 Public Primary Certification Authority - G4, OU="(c) 2007 VeriSign, Inc. - For authorized use only", OU=VeriSign Trust Network, O="VeriSign, Inc.", C=US +Serial number: 2f80fe238c0e220f486712289187acb3 +Valid from: Mon Nov 05 00:00:00 GMT 2007 until: Mon Jan 18 23:59:59 GMT 2038 +Signature algorithm name: SHA384withECDSA +Subject Public Key Algorithm: 384-bit EC (secp384r1) key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIDhDCCAwqgAwIBAgIQL4D+I4wOIg9IZxIokYesszAKBggqhkjOPQQDAzCByjEL +MAkGA1UEBhMCVVMxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMR8wHQYDVQQLExZW +ZXJpU2lnbiBUcnVzdCBOZXR3b3JrMTowOAYDVQQLEzEoYykgMjAwNyBWZXJpU2ln +biwgSW5jLiAtIEZvciBhdXRob3JpemVkIHVzZSBvbmx5MUUwQwYDVQQDEzxWZXJp +U2lnbiBDbGFzcyAzIFB1YmxpYyBQcmltYXJ5IENlcnRpZmljYXRpb24gQXV0aG9y +aXR5IC0gRzQwHhcNMDcxMTA1MDAwMDAwWhcNMzgwMTE4MjM1OTU5WjCByjELMAkG +A1UEBhMCVVMxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMR8wHQYDVQQLExZWZXJp +U2lnbiBUcnVzdCBOZXR3b3JrMTowOAYDVQQLEzEoYykgMjAwNyBWZXJpU2lnbiwg +SW5jLiAtIEZvciBhdXRob3JpemVkIHVzZSBvbmx5MUUwQwYDVQQDEzxWZXJpU2ln +biBDbGFzcyAzIFB1YmxpYyBQcmltYXJ5IENlcnRpZmljYXRpb24gQXV0aG9yaXR5 +IC0gRzQwdjAQBgcqhkjOPQIBBgUrgQQAIgNiAASnVnp8Utpkmw4tXNherJI9/gHm +GUo9FANL+mAnINmDiWn6VMaaGF5VKmTeBvaNSjutEDxlPZCIBIngMGGzrl0Bp3ve +fLK+ymVhAIau2o970ImtTR1ZmkGxvEeA3J5iw/mjgbIwga8wDwYDVR0TAQH/BAUw +AwEB/zAOBgNVHQ8BAf8EBAMCAQYwbQYIKwYBBQUHAQwEYTBfoV2gWzBZMFcwVRYJ +aW1hZ2UvZ2lmMCEwHzAHBgUrDgMCGgQUj+XTGoasjY5rw8+AatRIGCx7GS4wJRYj +aHR0cDovL2xvZ28udmVyaXNpZ24uY29tL3ZzbG9nby5naWYwHQYDVR0OBBYEFLMW +kf3upm7ktS5Jj4d4gYDs5bG1MAoGCCqGSM49BAMDA2gAMGUCMGYhDBgmYFo4e1ZC +4Kf8NoRRkSAsdk1DPcQdhCPQrNZ8NQbOzWm9kA3bbEhCHQ6qQgIxAJw9SDkjOVga +FRJZap7v1VmyHVIsmXHNxynfGyphe3HR3vPA5Q06Sqotp9iGKt0uEA== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/verisignclass3g5ca b/make/data/cacerts/verisignclass3g5ca new file mode 100644 index 0000000..417c891 --- /dev/null +++ b/make/data/cacerts/verisignclass3g5ca
@@ -0,0 +1,35 @@ +Owner: CN=VeriSign Class 3 Public Primary Certification Authority - G5, OU="(c) 2006 VeriSign, Inc. - For authorized use only", OU=VeriSign Trust Network, O="VeriSign, Inc.", C=US +Issuer: CN=VeriSign Class 3 Public Primary Certification Authority - G5, OU="(c) 2006 VeriSign, Inc. - For authorized use only", OU=VeriSign Trust Network, O="VeriSign, Inc.", C=US +Serial number: 18dad19e267de8bb4a2158cdcc6b3b4a +Valid from: Wed Nov 08 00:00:00 GMT 2006 until: Wed Jul 16 23:59:59 GMT 2036 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIE0zCCA7ugAwIBAgIQGNrRniZ96LtKIVjNzGs7SjANBgkqhkiG9w0BAQUFADCB +yjELMAkGA1UEBhMCVVMxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMR8wHQYDVQQL +ExZWZXJpU2lnbiBUcnVzdCBOZXR3b3JrMTowOAYDVQQLEzEoYykgMjAwNiBWZXJp +U2lnbiwgSW5jLiAtIEZvciBhdXRob3JpemVkIHVzZSBvbmx5MUUwQwYDVQQDEzxW +ZXJpU2lnbiBDbGFzcyAzIFB1YmxpYyBQcmltYXJ5IENlcnRpZmljYXRpb24gQXV0 +aG9yaXR5IC0gRzUwHhcNMDYxMTA4MDAwMDAwWhcNMzYwNzE2MjM1OTU5WjCByjEL +MAkGA1UEBhMCVVMxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMR8wHQYDVQQLExZW +ZXJpU2lnbiBUcnVzdCBOZXR3b3JrMTowOAYDVQQLEzEoYykgMjAwNiBWZXJpU2ln +biwgSW5jLiAtIEZvciBhdXRob3JpemVkIHVzZSBvbmx5MUUwQwYDVQQDEzxWZXJp +U2lnbiBDbGFzcyAzIFB1YmxpYyBQcmltYXJ5IENlcnRpZmljYXRpb24gQXV0aG9y +aXR5IC0gRzUwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQCvJAgIKXo1 +nmAMqudLO07cfLw8RRy7K+D+KQL5VwijZIUVJ/XxrcgxiV0i6CqqpkKzj/i5Vbex +t0uz/o9+B1fs70PbZmIVYc9gDaTY3vjgw2IIPVQT60nKWVSFJuUrjxuf6/WhkcIz +SdhDY2pSS9KP6HBRTdGJaXvHcPaz3BJ023tdS1bTlr8Vd6Gw9KIl8q8ckmcY5fQG +BO+QueQA5N06tRn/Arr0PO7gi+s3i+z016zy9vA9r911kTMZHRxAy3QkGSGT2RT+ +rCpSx4/VBEnkjWNHiDxpg8v+R70rfk/Fla4OndTRQ8Bnc+MUCH7lP59zuDMKz10/ +NIeWiu5T6CUVAgMBAAGjgbIwga8wDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8BAf8E +BAMCAQYwbQYIKwYBBQUHAQwEYTBfoV2gWzBZMFcwVRYJaW1hZ2UvZ2lmMCEwHzAH +BgUrDgMCGgQUj+XTGoasjY5rw8+AatRIGCx7GS4wJRYjaHR0cDovL2xvZ28udmVy +aXNpZ24uY29tL3ZzbG9nby5naWYwHQYDVR0OBBYEFH/TZafC3ey78DAJ80M5+gKv +MzEzMA0GCSqGSIb3DQEBBQUAA4IBAQCTJEowX2LP2BqYLz3q3JktvXf2pXkiOOzE +p6B4Eq1iDkVwZMXnl2YtmAl+X6/WzChl8gGqCBpH3vn5fJJaCGkgDdk+bW48DW7Y +5gaRQBi5+MHt39tBquCWIMnNZBU4gcmU7qKEKQsTb47bDN0lAtukixlE0kF6BWlK +WE9gyn6CagsCqiUXObXbf+eEZSqVir2G3l6BFoMtEMze/aiCKm0oHw0LxOXnGiYZ +4fQRbxC1lfznQgUy286dUV4otp6F01vvpX1FQHKOtw5rDgb7MzVIcbidJ4vEZV8N +hnacRHr2lVz2XTIIM6RUthg/aFzyQkqFOFSDX9HoLPKsEdao7WNq +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/verisignuniversalrootca b/make/data/cacerts/verisignuniversalrootca new file mode 100644 index 0000000..f364256 --- /dev/null +++ b/make/data/cacerts/verisignuniversalrootca
@@ -0,0 +1,35 @@ +Owner: CN=VeriSign Universal Root Certification Authority, OU="(c) 2008 VeriSign, Inc. - For authorized use only", OU=VeriSign Trust Network, O="VeriSign, Inc.", C=US +Issuer: CN=VeriSign Universal Root Certification Authority, OU="(c) 2008 VeriSign, Inc. - For authorized use only", OU=VeriSign Trust Network, O="VeriSign, Inc.", C=US +Serial number: 401ac46421b31321030ebbe4121ac51d +Valid from: Wed Apr 02 00:00:00 GMT 2008 until: Tue Dec 01 23:59:59 GMT 2037 +Signature algorithm name: SHA256withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEuTCCA6GgAwIBAgIQQBrEZCGzEyEDDrvkEhrFHTANBgkqhkiG9w0BAQsFADCB +vTELMAkGA1UEBhMCVVMxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMR8wHQYDVQQL +ExZWZXJpU2lnbiBUcnVzdCBOZXR3b3JrMTowOAYDVQQLEzEoYykgMjAwOCBWZXJp +U2lnbiwgSW5jLiAtIEZvciBhdXRob3JpemVkIHVzZSBvbmx5MTgwNgYDVQQDEy9W +ZXJpU2lnbiBVbml2ZXJzYWwgUm9vdCBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTAe +Fw0wODA0MDIwMDAwMDBaFw0zNzEyMDEyMzU5NTlaMIG9MQswCQYDVQQGEwJVUzEX +MBUGA1UEChMOVmVyaVNpZ24sIEluYy4xHzAdBgNVBAsTFlZlcmlTaWduIFRydXN0 +IE5ldHdvcmsxOjA4BgNVBAsTMShjKSAyMDA4IFZlcmlTaWduLCBJbmMuIC0gRm9y +IGF1dGhvcml6ZWQgdXNlIG9ubHkxODA2BgNVBAMTL1ZlcmlTaWduIFVuaXZlcnNh +bCBSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MIIBIjANBgkqhkiG9w0BAQEF +AAOCAQ8AMIIBCgKCAQEAx2E3XrEBNNti1xWb/1hajCMj1mCOkdeQmIN65lgZOIzF +9uVkhbSicfvtvbnazU0AtMgtc6XHaXGVHzk8skQHnOgO+k1KxCHfKWGPMiJhgsWH +H26MfF8WIFFE0XBPV+rjHOPMee5Y2A7Cs0WTwCznmhcrewA3ekEzeOEz4vMQGn+H +LL729fdC4uW/h2KJXwBL38Xd5HVEMkE6HnFuacsLdUYI0crSK5XQz/u5QGtkjFdN +/BMReYTtXlT2NJ8IAfMQJQYXStrxHXpma5hgZqTZ79IugvHw7wnqRMkVauIDbjPT +rJ9VAMf2CGqUuV/c4DPxhGD5WycRtPwW8rtWaoAljQIDAQABo4GyMIGvMA8GA1Ud +EwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQDAgEGMG0GCCsGAQUFBwEMBGEwX6FdoFsw +WTBXMFUWCWltYWdlL2dpZjAhMB8wBwYFKw4DAhoEFI/l0xqGrI2Oa8PPgGrUSBgs +exkuMCUWI2h0dHA6Ly9sb2dvLnZlcmlzaWduLmNvbS92c2xvZ28uZ2lmMB0GA1Ud +DgQWBBS2d/ppSEefUxLVwuoHMnYH0ZcHGTANBgkqhkiG9w0BAQsFAAOCAQEASvj4 +sAPmLGd75JR3Y8xuTPl9Dg3cyLk1uXBPY/ok+myDjEedO2Pzmvl2MpWRsXe8rJq+ +seQxIcaBlVZaDrHC1LGmWazxY8u4TB1ZkErvkBYoH1quEPuBUDgMbMzxPcP1Y+Oz +4yHJJDnp/RVmRvQbEdBNc6N9Rvk97ahfYtTxP/jgdFcrGJ2BtMQo2pSXpXDrrB2+ +BxHw1dvd5Yzw1TKwg+ZX4o+/vqGqvz0dtdQ46tewXDpPaj+PwGZsY6rp2aQW9IHR +lRQOfc2VNNnSj3BzgXucfr2YYdhFh5iQxeuGMMY1v/D/w1WIg0vvBZIGcfK4mJO3 +7M2CYfE45k+XmCpajQ== +-----END CERTIFICATE-----
diff --git a/make/data/cacerts/xrampglobalca b/make/data/cacerts/xrampglobalca new file mode 100644 index 0000000..347f143 --- /dev/null +++ b/make/data/cacerts/xrampglobalca
@@ -0,0 +1,32 @@ +Owner: CN=XRamp Global Certification Authority, O=XRamp Security Services Inc, OU=www.xrampsecurity.com, C=US +Issuer: CN=XRamp Global Certification Authority, O=XRamp Security Services Inc, OU=www.xrampsecurity.com, C=US +Serial number: 50946cec18ead59c4dd597ef758fa0ad +Valid from: Mon Nov 01 17:14:04 GMT 2004 until: Mon Jan 01 05:37:19 GMT 2035 +Signature algorithm name: SHA1withRSA +Subject Public Key Algorithm: 2048-bit RSA key +Version: 3 +-----BEGIN CERTIFICATE----- +MIIEMDCCAxigAwIBAgIQUJRs7Bjq1ZxN1ZfvdY+grTANBgkqhkiG9w0BAQUFADCB +gjELMAkGA1UEBhMCVVMxHjAcBgNVBAsTFXd3dy54cmFtcHNlY3VyaXR5LmNvbTEk +MCIGA1UEChMbWFJhbXAgU2VjdXJpdHkgU2VydmljZXMgSW5jMS0wKwYDVQQDEyRY +UmFtcCBHbG9iYWwgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkwHhcNMDQxMTAxMTcx +NDA0WhcNMzUwMTAxMDUzNzE5WjCBgjELMAkGA1UEBhMCVVMxHjAcBgNVBAsTFXd3 +dy54cmFtcHNlY3VyaXR5LmNvbTEkMCIGA1UEChMbWFJhbXAgU2VjdXJpdHkgU2Vy +dmljZXMgSW5jMS0wKwYDVQQDEyRYUmFtcCBHbG9iYWwgQ2VydGlmaWNhdGlvbiBB +dXRob3JpdHkwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQCYJB69FbS6 +38eMpSe2OAtp87ZOqCwuIR1cRN8hXX4jdP5efrRKt6atH67gBhbim1vZZ3RrXYCP +KZ2GG9mcDZhtdhAoWORlsH9KmHmf4MMxfoArtYzAQDsRhtDLooY2YKTVMIJt2W7Q +DxIEM5dfT2Fa8OT5kavnHTu86M/0ay00fOJIYRyO82FEzG+gSqmUsE3a56k0enI4 +qEHMPJQRfevIpoy3hsvKMzvZPTeL+3o+hiznc9cKV6xkmxnr9A8ECIqsAxcZZPRa +JSKNNCyy9mgdEm3Tih4U2sSPpuIjhdV6Db1q4Ons7Be7QhtnqiXtRYMh/MHJfNVi +PvryxS3T/dRlAgMBAAGjgZ8wgZwwEwYJKwYBBAGCNxQCBAYeBABDAEEwCwYDVR0P +BAQDAgGGMA8GA1UdEwEB/wQFMAMBAf8wHQYDVR0OBBYEFMZPoj0GY4QJnM5i5ASs +jVy16bYbMDYGA1UdHwQvMC0wK6ApoCeGJWh0dHA6Ly9jcmwueHJhbXBzZWN1cml0 +eS5jb20vWEdDQS5jcmwwEAYJKwYBBAGCNxUBBAMCAQEwDQYJKoZIhvcNAQEFBQAD +ggEBAJEVOQMBG2f7Shz5CmBbodpNl2L5JFMn14JkTpAuw0kbK5rc/Kh4ZzXxHfAR +vbdI4xD2Dd8/0sm2qlWkSLoC295ZLhVbO50WfUfXN+pfTXYSNrsf16GBBEYgoyxt +qZ4Bfj8pzgCT3/3JknOJiWSe5yvkHJEs0rnOfc5vMZnT5r7SHpDwCRR5XCOrTdLa +IR9NmXmd4c8nnxCbHIgNsIpkQTG4DmyQJKSbXHGPurt+HBvbaoAPIbzp26a3QPSy +i6mx5O+aGtA9aZnuqCij4Tyz8LIRnM98QObd50N9otg6tamN8jSZxNQQ4Qb9CYQQ +O+7ETPTsJ3xCwnR8gooJybQDJbw= +-----END CERTIFICATE-----
diff --git a/make/data/charsetmapping/IBM943.c2b b/make/data/charsetmapping/IBM943.c2b new file mode 100644 index 0000000..f5424fd --- /dev/null +++ b/make/data/charsetmapping/IBM943.c2b
@@ -0,0 +1,49 @@ +# +# source: 34B003AF.RPMAP130 +# c->b only entries +# +815C 2015 +8160 FF5E +8161 2225 +817C FF0D +88A0 555E +898B 7130 +89A8 9DD7 +8A9A 5699 +8BA0 4FE0 +8BEB 8EC0 +8C71 7E6B +8C74 8346 +8CB2 9E7C +8D8D 9EB4 +8DF2 6805 +8EC6 5C62 +8F4A 7E61 +8FD3 8523 +8FDD 91AC +90E4 87EC +917E 6414 +9189 7626 +91CB 9A52 +925C 7C1E +92CD 6451 +9355 5861 +935E 985A +9398 79B1 +93C0 7006 +9458 56CA +948D 525D +94AC 6F51 +94AE 91B1 +966A 9830 +96CB 9EB5 +9789 840A +9858 881F +9BA0 5C5B +9DB7 6522 +9E94 688E +E379 7E48 +E445 8141 +E8F6 9839 +FA55 FFE4 +FA59 F86F
diff --git a/make/data/charsetmapping/MS950.map b/make/data/charsetmapping/MS950.map index 56cf04a..7062ec1 100644 --- a/make/data/charsetmapping/MS950.map +++ b/make/data/charsetmapping/MS950.map
@@ -23,10 +23,10 @@ # 0xF9FD -> u256F -> 0xA2A3 # 0xA2CC -> u5341 -> 0xA451 # 0xA2CE -> u5345 -> 0xA4CA -# 0xF9F9 -> u2550 -> 0xA2A4 -# 0xF9E9 -> u255E -> 0xA2A5 -# 0xF9EA -> u256A -> 0xA2A6 -# 0xF9EB -> u2561 -> 0xA2A7 +# 0xA2A4 -> u2550 -> 0xF9F9 +# 0xA2A5 -> u255E -> 0xF9E9 +# 0xA2A6 -> u256A -> 0xF9EA +# 0xA2A7 -> u2561 -> 0xF9EB # # Column #1 is the cp950 code (in hex) # Column #2 is the Unicode (in hex as 0xXXXX)
diff --git a/make/data/charsetmapping/MS950.nr b/make/data/charsetmapping/MS950.nr index 41c9d08..0308687 100644 --- a/make/data/charsetmapping/MS950.nr +++ b/make/data/charsetmapping/MS950.nr
@@ -6,13 +6,13 @@ # (we don't need a MS950.c2b, the entries of MS950.c2b-irreversible # are added in MS950.b2c already) # -0xF9FA 0x256D +0xA2A4 0x2550 +0xA2A5 0x255E +0xA2A6 0x256A +0xA2A7 0x2561 +0xA2CC 0x5341 +0xA2CE 0x5345 +0xF9FA 0x256D 0xF9FB 0x256E 0xF9FC 0x2570 0xF9FD 0x256F -0xA2CC 0x5341 -0xA2CE 0x5345 -0xF9F9 0x2550 -0xF9E9 0x255E -0xF9EA 0x256A -0xF9EB 0x2561
diff --git a/make/data/charsetmapping/SingleByte-X.java.template b/make/data/charsetmapping/SingleByte-X.java.template index 2acb1ef..537d218 100644 --- a/make/data/charsetmapping/SingleByte-X.java.template +++ b/make/data/charsetmapping/SingleByte-X.java.template
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2008, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -48,7 +48,7 @@ } public CharsetDecoder newDecoder() { - return new SingleByte.Decoder(this, b2c, $ASCIICOMPATIBLE$); + return new SingleByte.Decoder(this, b2c, $ASCIICOMPATIBLE$, $LATIN1DECODABLE$); } public CharsetEncoder newEncoder() {
diff --git a/make/data/charsetmapping/charsets b/make/data/charsetmapping/charsets index ba4a8ea..7c94629 100644 --- a/make/data/charsetmapping/charsets +++ b/make/data/charsetmapping/charsets
@@ -1,5 +1,5 @@ # -# Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -282,6 +282,7 @@ alias iso-ir-226 alias ISO_8859-16:2001 alias ISO_8859-16 + alias ISO8859_16 alias latin10 alias l10 alias csISO885916 @@ -702,7 +703,7 @@ charset x-eucJP-Open EUC_JP_Open package sun.nio.cs.ext type template - hisname EUC_JP_Solari + hisname EUC_JP_Solaris ascii true alias EUC_JP_Solaris # JDK historical alias eucJP-open @@ -1396,7 +1397,7 @@ charset x-IBM834 IBM834 # EBCDIC DBCS-only Korean package sun.nio.cs.ext - type source + type template alias cp834 alias ibm834 alias 834 @@ -1490,7 +1491,7 @@ charset x-IBM949C IBM949C package sun.nio.cs.ext - type source + type template alias cp949C # JDK historical alias ibm949C alias ibm-949C
diff --git a/make/data/charsetmapping/stdcs-windows b/make/data/charsetmapping/stdcs-windows index 42da33d..6542de2 100644 --- a/make/data/charsetmapping/stdcs-windows +++ b/make/data/charsetmapping/stdcs-windows
@@ -2,6 +2,7 @@ # generate these charsets into sun.nio.cs # GBK +GB18030 Johab MS1255 MS1256
diff --git a/make/data/currency/CurrencyData.properties b/make/data/currency/CurrencyData.properties index 28c5748..a4ad6d6 100644 --- a/make/data/currency/CurrencyData.properties +++ b/make/data/currency/CurrencyData.properties
@@ -1,5 +1,5 @@ # -# Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -50,7 +50,7 @@ LVL428-LYD434-MAD504-MDL498-MGA969-MGF450-MKD807-MMK104-MNT496-MOP446-MRO478-MRU929-\ MTL470-MUR480-MVR462-MWK454-MXN484-MXV979-MYR458-MZM508-MZN943-NAD516-NGN566-\ NIO558-NLG528-NOK578-NPR524-NZD554-OMR512-PAB590-PEN604-PGK598-PHP608-\ - PKR586-PLN985-PTE620-PYG600-QAR634-ROL946-RON946-RSD941-RUB643-RUR810-RWF646-SAR682-\ + PKR586-PLN985-PTE620-PYG600-QAR634-ROL642-RON946-RSD941-RUB643-RUR810-RWF646-SAR682-\ SBD090-SCR690-SDD736-SDG938-SEK752-SGD702-SHP654-SIT705-SKK703-SLL694-SOS706-\ SRD968-SRG740-SSP728-STD678-STN930-SVC222-SYP760-SZL748-THB764-TJS972-TMM795-TMT934-TND788-TOP776-\ TPE626-TRL792-TRY949-TTD780-TWD901-TZS834-UAH980-UGX800-USD840-USN997-USS998-UYI940-\ @@ -588,7 +588,7 @@ minor0=\ ADP-BEF-BIF-BYB-BYR-CLP-DJF-ESP-GNF-\ - GRD-ISK-ITL-JPY-KMF-KRW-LUF-MGF-PYG-PTE-RWF-\ + GRD-ISK-ITL-JPY-KMF-KRW-LUF-MGF-PYG-PTE-ROL-RWF-\ TPE-TRL-UGX-UYI-VND-VUV-XAF-XOF-XPF minor3=\ BHD-IQD-JOD-KWD-LYD-OMR-TND
diff --git a/make/data/docs-resources/index.html b/make/data/docs-resources/index.html new file mode 100644 index 0000000..460525d --- /dev/null +++ b/make/data/docs-resources/index.html
@@ -0,0 +1,33 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN"> +<!-- + Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. + DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + + This code is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License version 2 only, as + published by the Free Software Foundation. Oracle designates this + particular file as subject to the "Classpath" exception as provided + by Oracle in the LICENSE file that accompanied this code. + + This code is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + version 2 for more details (a copy is included in the LICENSE file that + accompanied this code). + + You should have received a copy of the GNU General Public License version + 2 along with this work; if not, write to the Free Software Foundation, + Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + + Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + or visit www.oracle.com if you need additional information or have any + questions. +--> +<html lang="en"> +<head> +<meta http-equiv="refresh" content="0;url=api/index.html"> +<title>Java API Documentation redirect</title> +</head> +<body> +</body> +</html>
diff --git a/make/data/fontconfig/aix.fontconfig.properties b/make/data/fontconfig/aix.fontconfig.properties index f21f10a..def633f 100644 --- a/make/data/fontconfig/aix.fontconfig.properties +++ b/make/data/fontconfig/aix.fontconfig.properties
@@ -1,6 +1,6 @@ # # -# Copyright (c) 2013 SAP SE. All rights reserved. +# Copyright (c) 2013, 2019 SAP SE. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -48,12 +48,12 @@ dialog.plain.japanese-x0208=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 dialog.plain.japanese-x0201=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 dialog.plain.japanese-udc=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -dialog.plain.japanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +dialog.plain.japanese-iso10646=-monotype-wt sans j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialog.plain.korean=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -dialog.plain.korean-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +dialog.plain.korean-iso10646=-monotype-wt sans k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialog.plain.chinese=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -dialog.plain.chinese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -dialog.plain.taiwanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +dialog.plain.chinese-iso10646=-monotype-wt sans sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +dialog.plain.taiwanese-iso10646=-monotype-wt sans tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialog.bold.latin-1=-*-helvetica-bold-r-normal--*-%d-100-100-p-*-iso8859-1 dialog.bold.thai=-ibm-thaihelvetica-medium-r-normal--*-%d-75-75-p-*-ucs2.thai-0 @@ -61,12 +61,12 @@ dialog.bold.japanese-x0208=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 dialog.bold.japanese-x0201=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 dialog.bold.japanese-udc=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -dialog.bold.japanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +dialog.bold.japanese-iso10646=-monotype-wt sans j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialog.bold.korean=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -dialog.bold.korean-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +dialog.bold.korean-iso10646=-monotype-wt sans k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialog.bold.chinese=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -dialog.bold.chinese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -dialog.bold.taiwanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +dialog.bold.chinese-iso10646=-monotype-wt sans sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +dialog.bold.taiwanese-iso10646=-monotype-wt sans tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialog.italic.latin-1=-*-helvetica-medium-o-normal--*-%d-100-100-p-*-iso8859-1 dialog.italic.thai=-ibm-thaihelvetica-medium-r-normal--*-%d-75-75-p-*-ucs2.thai-0 @@ -74,12 +74,12 @@ dialog.italic.japanese-x0208=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 dialog.italic.japanese-x0201=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 dialog.italic.japanese-udc=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -dialog.italic.japanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +dialog.italic.japanese-iso10646=-monotype-wt sans j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialog.italic.korean=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -dialog.italic.korean-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +dialog.italic.korean-iso10646=-monotype-wt sans k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialog.italic.chinese=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -dialog.italic.chinese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -dialog.italic.taiwanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +dialog.italic.chinese-iso10646=-monotype-wt sans sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +dialog.italic.taiwanese-iso10646=-monotype-wt sans tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialog.bolditalic.latin-1=-*-helvetica-bold-o-normal--*-%d-100-100-p-*-iso8859-1 dialog.bolditalic.thai=-ibm-thaihelvetica-medium-r-normal--*-%d-75-75-p-*-ucs2.thai-0 @@ -87,12 +87,12 @@ dialog.bolditalic.japanese-x0208=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 dialog.bolditalic.japanese-x0201=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 dialog.bolditalic.japanese-udc=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -dialog.bolditalic.japanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +dialog.bolditalic.japanese-iso10646=-monotype-wt sans j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialog.bolditalic.korean=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -dialog.bolditalic.korean-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +dialog.bolditalic.korean-iso10646=-monotype-wt sans k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialog.bolditalic.chinese=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -dialog.bolditalic.chinese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -dialog.bolditalic.taiwanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +dialog.bolditalic.chinese-iso10646=-monotype-wt sans sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +dialog.bolditalic.taiwanese-iso10646=-monotype-wt sans tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialoginput.plain.latin-1=-*-courier-medium-r-normal--*-%d-100-100-m-*-iso8859-1 dialoginput.plain.thai=-ibm-thaicourier-medium-r-normal--*-%d-75-75-m-*-ucs2.thai-0 @@ -100,12 +100,12 @@ dialoginput.plain.japanese-x0208=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 dialoginput.plain.japanese-x0201=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 dialoginput.plain.japanese-udc=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -dialoginput.plain.japanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +dialoginput.plain.japanese-iso10646=-monotype-wt sans duo j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialoginput.plain.korean=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -dialoginput.plain.korean-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +dialoginput.plain.korean-iso10646=-monotype-wt sans duo k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialoginput.plain.chinese=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -dialoginput.plain.chinese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -dialoginput.plain.taiwanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +dialoginput.plain.chinese-iso10646=-monotype-wt sans duo sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +dialoginput.plain.taiwanese-iso10646=-monotype-wt sans duo tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialoginput.bold.latin-1=-*-courier-bold-r-normal--*-%d-100-100-m-*-iso8859-1 dialoginput.bold.thai=-ibm-thaicourier-medium-r-normal--*-%d-75-75-m-*-ucs2.thai-0 @@ -113,12 +113,12 @@ dialoginput.bold.japanese-x0208=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 dialoginput.bold.japanese-x0201=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 dialoginput.bold.japanese-udc=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -dialoginput.bold.japanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +dialoginput.bold.japanese-iso10646=-monotype-wt sans duo j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialoginput.bold.korean=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -dialoginput.bold.korean-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +dialoginput.bold.korean-iso10646=-monotype-wt sans duo k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialoginput.bold.chinese=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -dialoginput.bold.chinese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -dialoginput.bold.taiwanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +dialoginput.bold.chinese-iso10646=-monotype-wt sans duo sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +dialoginput.bold.taiwanese-iso10646=-monotype-wt sans duo tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialoginput.italic.latin-1=-*-courier-medium-o-normal--*-%d-100-100-m-*-iso8859-1 dialoginput.italic.thai=-ibm-thaicourier-medium-r-normal--*-%d-75-75-m-*-ucs2.thai-0 @@ -126,12 +126,12 @@ dialoginput.italic.japanese-x0208=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 dialoginput.italic.japanese-x0201=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 dialoginput.italic.japanese-udc=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -dialoginput.italic.japanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +dialoginput.italic.japanese-iso10646=-monotype-wt sans duo j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialoginput.italic.korean=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -dialoginput.italic.korean-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +dialoginput.italic.korean-iso10646=-monotype-wt sans duo k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialoginput.italic.chinese=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -dialoginput.italic.chinese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -dialoginput.italic.taiwanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +dialoginput.italic.chinese-iso10646=-monotype-wt sans duo sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +dialoginput.italic.taiwanese-iso10646=-monotype-wt sans duo tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialoginput.bolditalic.latin-1=-*-courier-bold-o-normal--*-%d-100-100-m-*-iso8859-1 dialoginput.bolditalic.thai=-ibm-thaicourier-medium-r-normal--*-%d-75-75-m-*-ucs2.thai-0 @@ -139,12 +139,12 @@ dialoginput.bolditalic.japanese-x0208=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 dialoginput.bolditalic.japanese-x0201=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 dialoginput.bolditalic.japanese-udc=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -dialoginput.bolditalic.japanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +dialoginput.bolditalic.japanese-iso10646=-monotype-wt sans duo j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialoginput.bolditalic.korean=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -dialoginput.bolditalic.korean-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +dialoginput.bolditalic.korean-iso10646=-monotype-wt sans duo k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 dialoginput.bolditalic.chinese=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -dialoginput.bolditalic.chinese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -dialoginput.bolditalic.taiwanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +dialoginput.bolditalic.chinese-iso10646=-monotype-wt sans duo sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +dialoginput.bolditalic.taiwanese-iso10646=-monotype-wt sans duo tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 sansserif.plain.latin-1=-*-helvetica-medium-r-normal--*-%d-100-100-p-*-iso8859-1 sansserif.plain.thai=-ibm-thaihelvetica-medium-r-normal--*-%d-75-75-p-*-ucs2.thai-0 @@ -152,12 +152,12 @@ sansserif.plain.japanese-x0208=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 sansserif.plain.japanese-x0201=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 sansserif.plain.japanese-udc=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -sansserif.plain.japanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +sansserif.plain.japanese-iso10646=-monotype-wt sans j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 sansserif.plain.korean=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -sansserif.plain.korean-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +sansserif.plain.korean-iso10646=-monotype-wt sans k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 sansserif.plain.chinese=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -sansserif.plain.chinese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -sansserif.plain.taiwanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +sansserif.plain.chinese-iso10646=-monotype-wt sans sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +sansserif.plain.taiwanese-iso10646=-monotype-wt sans tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 sansserif.bold.latin-1=-*-helvetica-bold-r-normal--*-%d-100-100-p-*-iso8859-1 sansserif.bold.thai=-ibm-thaihelvetica-medium-r-normal--*-%d-75-75-p-*-ucs2.thai-0 @@ -165,12 +165,12 @@ sansserif.bold.japanese-x0208=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 sansserif.bold.japanese-x0201=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 sansserif.bold.japanese-udc=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -sansserif.bold.japanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +sansserif.bold.japanese-iso10646=-monotype-wt sans j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 sansserif.bold.korean=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -sansserif.bold.korean-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +sansserif.bold.korean-iso10646=-monotype-wt sans k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 sansserif.bold.chinese=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -sansserif.bold.chinese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -sansserif.bold.taiwanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +sansserif.bold.chinese-iso10646=-monotype-wt sans sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +sansserif.bold.taiwanese-iso10646=-monotype-wt sans tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 sansserif.italic.latin-1=-*-helvetica-medium-o-normal--*-%d-100-100-p-*-iso8859-1 sansserif.italic.thai=-ibm-thaihelvetica-medium-r-normal--*-%d-75-75-p-*-ucs2.thai-0 @@ -178,12 +178,12 @@ sansserif.italic.japanese-x0208=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 sansserif.italic.japanese-x0201=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 sansserif.italic.japanese-udc=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -sansserif.italic.japanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +sansserif.italic.japanese-iso10646=-monotype-wt sans j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 sansserif.italic.korean=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -sansserif.italic.korean-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +sansserif.italic.korean-iso10646=-monotype-wt sans k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 sansserif.italic.chinese=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -sansserif.italic.chinese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -sansserif.italic.taiwanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +sansserif.italic.chinese-iso10646=-monotype-wt sans sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +sansserif.italic.taiwanese-iso10646=-monotype-wt sans tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 sansserif.bolditalic.latin-1=-*-helvetica-bold-o-normal--*-%d-100-100-p-*-iso8859-1 sansserif.bolditalic.thai=-ibm-thaihelvetica-medium-r-normal--*-%d-75-75-p-*-ucs2.thai-0 @@ -191,12 +191,12 @@ sansserif.bolditalic.japanese-x0208=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 sansserif.bolditalic.japanese-x0201=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 sansserif.bolditalic.japanese-udc=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -sansserif.bolditalic.japanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +sansserif.bolditalic.japanese-iso10646=-monotype-wt sans j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 sansserif.bolditalic.korean=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -sansserif.bolditalic.korean-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +sansserif.bolditalic.korean-iso10646=-monotype-wt sans k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 sansserif.bolditalic.chinese=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -sansserif.bolditalic.chinese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -sansserif.bolditalic.taiwanese-iso10646=-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +sansserif.bolditalic.chinese-iso10646=-monotype-wt sans sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +sansserif.bolditalic.taiwanese-iso10646=-monotype-wt sans tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 serif.plain.latin-1=-*-times new roman-medium-r-normal--*-%d-100-100-p-*-iso8859-1 serif.plain.thai=-ibm-thaitimes-medium-r-normal--*-%d-75-75-p-*-ucs2.thai-0 @@ -204,12 +204,12 @@ serif.plain.japanese-x0208=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 serif.plain.japanese-x0201=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 serif.plain.japanese-udc=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -serif.plain.japanese-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +serif.plain.japanese-iso10646=-monotype-wt serif j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 serif.plain.korean=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -serif.plain.korean-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +serif.plain.korean-iso10646=-monotype-wt serif k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 serif.plain.chinese=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -serif.plain.chinese-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -serif.plain.taiwanese-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +serif.plain.chinese-iso10646=-monotype-wt serif sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +serif.plain.taiwanese-iso10646=-monotype-wt serif tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 serif.bold.latin-1=-*-times new roman-bold-r-normal--*-%d-100-100-p-*-iso8859-1 serif.bold.thai=-ibm-thaitimes-medium-r-normal--*-%d-75-75-p-*-ucs2.thai-0 @@ -217,12 +217,12 @@ serif.bold.japanese-x0208=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 serif.bold.japanese-x0201=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 serif.bold.japanese-udc=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -serif.bold.japanese-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +serif.bold.japanese-iso10646=-monotype-wt serif j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 serif.bold.korean=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -serif.bold.korean-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +serif.bold.korean-iso10646=-monotype-wt serif k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 serif.bold.chinese=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -serif.bold.chinese-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -serif.bold.taiwanese-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +serif.bold.chinese-iso10646=-monotype-wt serif sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +serif.bold.taiwanese-iso10646=-monotype-wt serif tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 serif.italic.latin-1=-*-times new roman-medium-i-normal--*-%d-100-100-p-*-iso8859-1 @@ -231,12 +231,12 @@ serif.italic.japanese-x0208=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 serif.italic.japanese-x0201=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 serif.italic.japanese-udc=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -serif.italic.japanese-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +serif.italic.japanese-iso10646=-monotype-wt serif j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 serif.italic.korean=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -serif.italic.korean-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +serif.italic.korean-iso10646=-monotype-wt serif k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 serif.italic.chinese=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -serif.italic.chinese-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -serif.italic.taiwanese-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +serif.italic.chinese-iso10646=-monotype-wt serif sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +serif.italic.taiwanese-iso10646=-monotype-wt serif tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 serif.bolditalic.latin-1=-*-times new roman-bold-i-normal--*-%d-100-100-p-*-iso8859-1 serif.bolditalic.thai=-ibm-thaitimes-medium-r-normal--*-%d-75-75-p-*-ucs2.thai-0 @@ -244,12 +244,12 @@ serif.bolditalic.japanese-x0208=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 serif.bolditalic.japanese-x0201=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 serif.bolditalic.japanese-udc=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -serif.bolditalic.japanese-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +serif.bolditalic.japanese-iso10646=-monotype-wt serif j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 serif.bolditalic.korean=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -serif.bolditalic.korean-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +serif.bolditalic.korean-iso10646=-monotype-wt serif k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 serif.bolditalic.chinese=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -serif.bolditalic.chinese-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -serif.bolditalic.taiwanese-iso10646=-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +serif.bolditalic.chinese-iso10646=-monotype-wt serif sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +serif.bolditalic.taiwanese-iso10646=-monotype-wt serif tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 monospaced.plain.latin-1=-*-courier-medium-r-normal--*-%d-100-100-m-*-iso8859-1 monospaced.plain.thai=-ibm-thaicourier-medium-r-normal--*-%d-75-75-m-*-ucs2.thai-0 @@ -257,12 +257,12 @@ monospaced.plain.japanese-x0208=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 monospaced.plain.japanese-x0201=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 monospaced.plain.japanese-udc=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -monospaced.plain.japanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +monospaced.plain.japanese-iso10646=-monotype-wt sans duo j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 monospaced.plain.korean=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -monospaced.plain.korean-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +monospaced.plain.korean-iso10646=-monotype-wt sans duo k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 monospaced.plain.chinese=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -monospaced.plain.chinese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -monospaced.plain.taiwanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +monospaced.plain.chinese-iso10646=-monotype-wt sans duo sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +monospaced.plain.taiwanese-iso10646=-monotype-wt sans duo tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 monospaced.bold.latin-1=-*-courier-bold-r-normal--*-%d-100-100-m-*-iso8859-1 monospaced.bold.thai=-ibm-thaicourier-medium-r-normal--*-%d-75-75-m-*-ucs2.thai-0 @@ -270,12 +270,12 @@ monospaced.bold.japanese-x0208=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 monospaced.bold.japanese-x0201=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 monospaced.bold.japanese-udc=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -monospaced.bold.japanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +monospaced.bold.japanese-iso10646=-monotype-wt sans duo j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 monospaced.bold.korean=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -monospaced.bold.korean-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +monospaced.bold.korean-iso10646=-monotype-wt sans duo k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 monospaced.bold.chinese=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -monospaced.bold.chinese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -monospaced.bold.taiwanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +monospaced.bold.chinese-iso10646=-monotype-wt sans duo sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +monospaced.bold.taiwanese-iso10646=-monotype-wt sans duo tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 monospaced.italic.latin-1=-*-courier-medium-o-normal--*-%d-100-100-m-*-iso8859-1 monospaced.italic.thai=-ibm-thaicourier-medium-r-normal--*-%d-75-75-m-*-ucs2.thai-0 @@ -283,12 +283,12 @@ monospaced.italic.japanese-x0208=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 monospaced.italic.japanese-x0201=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 monospaced.italic.japanese-udc=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -monospaced.italic.japanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +monospaced.italic.japanese-iso10646=-monotype-wt sans duo j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 monospaced.italic.korean=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -monospaced.italic.korean-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +monospaced.italic.korean-iso10646=-monotype-wt sans duo k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 monospaced.italic.chinese=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -monospaced.italic.chinese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -monospaced.italic.taiwanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +monospaced.italic.chinese-iso10646=-monotype-wt sans duo sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +monospaced.italic.taiwanese-iso10646=-monotype-wt sans duo tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 monospaced.bolditalic.latin-1=-*-courier-bold-o-normal--*-%d-100-100-m-*-iso8859-1 monospaced.bolditalic.thai=-ibm-thaicourier-medium-r-normal--*-%d-75-75-m-*-ucs2.thai-0 @@ -296,12 +296,12 @@ monospaced.bolditalic.japanese-x0208=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0 monospaced.bolditalic.japanese-x0201=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0 monospaced.bolditalic.japanese-udc=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp -monospaced.bolditalic.japanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0 +monospaced.bolditalic.japanese-iso10646=-monotype-wt sans duo j-medium-r-normal--*-%d-75-75-*-*-iso10646-1 monospaced.bolditalic.korean=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0 -monospaced.bolditalic.korean-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0 +monospaced.bolditalic.korean-iso10646=-monotype-wt sans duo k-medium-r-normal--*-%d-75-75-*-*-iso10646-1 monospaced.bolditalic.chinese=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0 -monospaced.bolditalic.chinese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0 -monospaced.bolditalic.taiwanese-iso10646=-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0 +monospaced.bolditalic.chinese-iso10646=-monotype-wt sans duo sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1 +monospaced.bolditalic.taiwanese-iso10646=-monotype-wt sans duo tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1 # Search Sequences @@ -353,33 +353,33 @@ filename.-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0=/usr/lpp/X11/lib/X11/fonts/TrueType/tnrwt_j.ttf filename.-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0=/usr/lpp/X11/lib/X11/fonts/TrueType/tnrwt_j.ttf filename.-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp=/usr/lpp/X11/lib/X11/fonts/TrueType/tnrwt_j.ttf -filename.-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0=/usr/lpp/X11/lib/X11/fonts/TrueType/tnrwt_j.ttf +filename.-monotype-wt_serif_j-medium-r-normal--*-%d-75-75-*-*-iso10646-1=/usr/lpp/X11/lib/X11/fonts/TrueType/wt__j__b.ttf filename.-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0=/usr/lpp/X11/lib/X11/fonts/TrueType/tnrwt_k.ttf -filename.-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0=/usr/lpp/X11/lib/X11/fonts/TrueType/tnrwt_k.ttf +filename.-monotype-wt_serif_k-medium-r-normal--*-%d-75-75-*-*-iso10646-1=/usr/lpp/X11/lib/X11/fonts/TrueType/wt__k__b.ttf filename.-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0=/usr/lpp/X11/lib/X11/fonts/TrueType/tnrwt_s.ttf -filename.-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0=/usr/lpp/X11/lib/X11/fonts/TrueType/tnrwt_s.ttf +filename.-monotype-wt_serif_sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1=/usr/lpp/X11/lib/X11/fonts/TrueType/wt__s__b.ttf filename.-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0=/usr/lpp/X11/lib/X11/fonts/TrueType/tnrwt_s.ttf -filename.-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0=/usr/lpp/X11/lib/X11/fonts/TrueType/tnrwt_s.ttf -filename.-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0=/usr/lpp/X11/lib/X11/fonts/TrueType/tnrwt_t.ttf +filename.-monotype-wt_serif_sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1=/usr/lpp/X11/lib/X11/fonts/TrueType/wt__s__b.ttf +filename.-monotype-wt_serif_tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1=/usr/lpp/X11/lib/X11/fonts/TrueType/wt__tt_b.ttf filename.-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsansdj.ttf filename.-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsansdj.ttf filename.-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsansdj.ttf -filename.-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsansdj.ttf +filename.-monotype-wt_sans_duo_j-medium-r-normal--*-%d-75-75-*-*-iso10646-1=/usr/lpp/X11/lib/X11/fonts/TrueType/wtsdj__b.ttf filename.-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsansdk.ttf -filename.-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsansdk.ttf +filename.-monotype-wt_sans_duo_k-medium-r-normal--*-%d-75-75-*-*-iso10646-1=/usr/lpp/X11/lib/X11/fonts/TrueType/wtsdk__b.ttf filename.-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsansds.ttf -filename.-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsansds.ttf -filename.-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsansdt.ttf +filename.-monotype-wt_sans_duo_sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1=/usr/lpp/X11/lib/X11/fonts/TrueType/wtsds__b.ttf +filename.-monotype-wt_sans_duo_tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1=/usr/lpp/X11/lib/X11/fonts/TrueType/wtsdtt_b.ttf filename.-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0208.1983-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsans_j.ttf filename.-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-jisx0201.1976-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsans_j.ttf filename.-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ibm-udcjp=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsans_j.ttf -filename.-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_japan-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsans_j.ttf +filename.-monotype-wt_sans_j-medium-r-normal--*-%d-75-75-*-*-iso10646-1=/usr/lpp/X11/lib/X11/fonts/TrueType/wts_j__b.ttf filename.-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ksc5601.1987-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsans_k.ttf -filename.-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_korea-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsans_k.ttf +filename.-monotype-wt_sans_k-medium-r-normal--*-%d-75-75-*-*-iso10646-1=/usr/lpp/X11/lib/X11/fonts/TrueType/wts_k__b.ttf filename.-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-gb2312.1980-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsans_s.ttf -filename.-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_china-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsans_s.ttf -filename.-monotype-sanswt-medium-r-normal--*-%d-75-75-*-*-ucs2.cjk_taiwan-0=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsans_t.ttf +filename.-monotype-wt_sans_sc-medium-r-normal--*-%d-75-75-*-*-iso10646-1=/usr/lpp/X11/lib/X11/fonts/TrueType/wts_s__b.ttf +filename.-monotype-wt_sans_tw-medium-r-normal--*-%d-75-75-*-*-iso10646-1=/usr/lpp/X11/lib/X11/fonts/TrueType/wts_tt_b.ttf filename.-monotype-timesnewromanwt-medium-r-normal--*-%d-75-75-*-*-iso8859-15=/usr/lpp/X11/lib/X11/fonts/TrueType/tnrwt_j.ttf filename.-monotype-sansmonowt-medium-r-normal--*-%d-75-75-*-*-iso8859-15=/usr/lpp/X11/lib/X11/fonts/TrueType/mtsansdj.ttf
diff --git a/make/data/fontconfig/windows.fontconfig.properties b/make/data/fontconfig/windows.fontconfig.properties index c189449..5be779b 100644 --- a/make/data/fontconfig/windows.fontconfig.properties +++ b/make/data/fontconfig/windows.fontconfig.properties
@@ -1,6 +1,6 @@ # # -# Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -37,7 +37,18 @@ allfonts.chinese-hkscs=MingLiU_HKSCS allfonts.chinese-ms950-extb=MingLiU-ExtB allfonts.devanagari=Mangal +allfonts.bengali=Vrinda +allfonts.gujarati=Shruti +allfonts.gurmukhi=Raavi allfonts.kannada=Tunga +allfonts.malayalam=Kartika +allfonts.oriya=Kalinga +allfonts.sinhala=Iskoola Pota +allfonts.tamil=Latha +allfonts.telugu=Gautami +allfonts.khmer=Khmer UI +allfonts.mongolian=Mongolian Baiti +allfonts.myanmar=Myanmar Text allfonts.dingbats=Wingdings allfonts.symbol=Symbol allfonts.symbols=Segoe UI Symbol @@ -219,7 +230,7 @@ sequence.dialoginput.x-MS950-HKSCS-XP=alphabetic,chinese-ms950,chinese-hkscs,dingbats,symbol,chinese-ms950-extb sequence.allfonts.UTF-8.hi=alphabetic/1252,devanagari,dingbats,symbol -sequence.allfonts.UTF-8.ja=alphabetic,japanese,devanagari,dingbats,symbol +sequence.allfonts.UTF-8.ja=alphabetic,japanese,dingbats,symbol sequence.allfonts.windows-1255=hebrew,alphabetic/1252,dingbats,symbol @@ -239,7 +250,10 @@ sequence.fallback=symbols,\ chinese-ms950,chinese-hkscs,chinese-ms936,chinese-gb18030,\ - japanese,korean,chinese-ms950-extb,chinese-ms936-extb,georgian,kannada + japanese,korean,chinese-ms950-extb,chinese-ms936-extb,\ + georgian,devanagari,bengali,gujarati,gurmukhi,kannada,\ + malayalam,oriya,sinhala,tamil,telugu,thai,khmer,mongolian,\ + myanmar # Exclusion Ranges @@ -293,9 +307,20 @@ filename.Batang=batang.TTC filename.GulimChe=gulim.TTC -filename.DokChampa=dokchamp.ttf +filename.Gautami=gautami.ttf +filename.Iskoola_Pota=iskpota.ttf +filename.Kalinga=kalinga.ttf +filename.Kartika=kartika.ttf +filename.Latha=latha.ttf filename.Mangal=MANGAL.TTF +filename.Raavi=raavi.ttf +filename.Shruti=shruti.ttf filename.Tunga=TUNGA.TTF +filename.Vrinda=vrinda.ttf +filename.DokChampa=dokchamp.ttf +filename.Khmer_UI=KhmerUI.ttf +filename.Mongolian_Baiti=monbaiti.ttf +filename.Myanmar_Text=mmrtext.ttf filename.Symbol=SYMBOL.TTF filename.Wingdings=WINGDING.TTF
diff --git a/make/data/lsrdata/language-subtag-registry.txt b/make/data/lsrdata/language-subtag-registry.txt index 67b3705..cc59e9d 100644 --- a/make/data/lsrdata/language-subtag-registry.txt +++ b/make/data/lsrdata/language-subtag-registry.txt
@@ -1,4 +1,4 @@ -File-Date: 2018-11-30 +File-Date: 2020-09-29 %% Type: language Subtag: aa @@ -1530,7 +1530,7 @@ %% Type: language Subtag: adb -Description: Adabe +Description: Atauran Added: 2009-07-29 %% Type: language @@ -2096,6 +2096,8 @@ Subtag: ais Description: Nataoran Amis Added: 2009-07-29 +Deprecated: 2019-04-16 +Comments: see ami, szy %% Type: language Subtag: ait @@ -2633,6 +2635,7 @@ Type: language Subtag: ant Description: Antakarinya +Description: Antikarinya Added: 2009-07-29 %% Type: language @@ -2704,6 +2707,7 @@ Subtag: aoh Description: Arma Added: 2009-07-29 +Deprecated: 2020-03-28 %% Type: language Subtag: aoi @@ -3094,6 +3098,8 @@ Subtag: asd Description: Asas Added: 2009-07-29 +Deprecated: 2019-04-16 +Preferred-Value: snz %% Type: language Subtag: ase @@ -3765,6 +3771,7 @@ Subtag: ayy Description: Tayabas Ayta Added: 2009-07-29 +Deprecated: 2020-03-28 %% Type: language Subtag: ayz @@ -4080,6 +4087,7 @@ Subtag: bbz Description: Babalia Creole Arabic Added: 2009-07-29 +Deprecated: 2020-03-28 Macrolanguage: ar %% Type: language @@ -4135,7 +4143,7 @@ %% Type: language Subtag: bck -Description: Bunaba +Description: Bunuba Added: 2009-07-29 %% Type: language @@ -5750,6 +5758,7 @@ Subtag: bpb Description: Barbacoas Added: 2009-07-29 +Deprecated: 2020-03-28 %% Type: language Subtag: bpd @@ -6006,7 +6015,7 @@ %% Type: language Subtag: brf -Description: Bera +Description: Bira Added: 2009-07-29 %% Type: language @@ -6930,7 +6939,7 @@ %% Type: language Subtag: bym -Description: Bidyara +Description: Bidjara Added: 2009-07-29 %% Type: language @@ -7369,6 +7378,7 @@ Subtag: cca Description: Cauca Added: 2009-07-29 +Deprecated: 2020-03-28 %% Type: language Subtag: ccc @@ -7475,6 +7485,7 @@ Subtag: cdg Description: Chamari Added: 2009-07-29 +Deprecated: 2020-03-28 %% Type: language Subtag: cdh @@ -7564,6 +7575,11 @@ Added: 2009-07-29 %% Type: language +Subtag: cey +Description: Ekai Chin +Added: 2019-04-16 +%% +Type: language Subtag: cfa Description: Dijim-Bwilim Added: 2009-07-29 @@ -7865,6 +7881,11 @@ Added: 2009-07-29 %% Type: language +Subtag: ckm +Description: Chakavian +Added: 2020-03-28 +%% +Type: language Subtag: ckn Description: Kaang Chin Added: 2013-09-10 @@ -8111,6 +8132,13 @@ Added: 2009-07-29 %% Type: language +Subtag: cnp +Description: Northern Ping Chinese +Description: Northern Pinghua +Added: 2020-03-28 +Macrolanguage: zh +%% +Type: language Subtag: cnr Description: Montenegrin Added: 2018-01-23 @@ -8554,6 +8582,13 @@ Added: 2009-07-29 %% Type: language +Subtag: csp +Description: Southern Ping Chinese +Description: Southern Pinghua +Added: 2020-03-28 +Macrolanguage: zh +%% +Type: language Subtag: csq Description: Croatia Sign Language Added: 2009-07-29 @@ -9308,6 +9343,7 @@ Type: language Subtag: dgr Description: Dogrib +Description: Tłı̨chǫ Added: 2005-10-16 %% Type: language @@ -9324,6 +9360,7 @@ Subtag: dgu Description: Degaru Added: 2009-07-29 +Deprecated: 2020-03-28 %% Type: language Subtag: dgw @@ -9439,6 +9476,7 @@ Type: language Subtag: dif Description: Dieri +Description: Diyari Added: 2009-07-29 %% Type: language @@ -9515,6 +9553,8 @@ Subtag: dit Description: Dirari Added: 2009-07-29 +Deprecated: 2019-04-29 +Preferred-Value: dif %% Type: language Subtag: diu @@ -9560,6 +9600,7 @@ Type: language Subtag: djd Description: Djamindjung +Description: Ngaliwurru Added: 2009-07-29 %% Type: language @@ -9603,6 +9644,7 @@ %% Type: language Subtag: djn +Description: Jawoyn Description: Djauan Added: 2009-07-29 %% @@ -9705,6 +9747,11 @@ Added: 2009-07-29 %% Type: language +Subtag: dmf +Description: Medefaidrin +Added: 2020-03-28 +%% +Type: language Subtag: dmg Description: Upper Kinabatangan Added: 2009-07-29 @@ -10026,6 +10073,8 @@ Subtag: drr Description: Dororo Added: 2009-07-29 +Deprecated: 2020-03-28 +Preferred-Value: kzk %% Type: language Subtag: drs @@ -10191,6 +10240,8 @@ Subtag: dud Description: Hun-Saare Added: 2009-07-29 +Deprecated: 2019-04-16 +Comments: see uth, uss %% Type: language Subtag: due @@ -10313,6 +10364,11 @@ Added: 2009-07-29 %% Type: language +Subtag: dwk +Description: Dawik Kui +Added: 2020-03-28 +%% +Type: language Subtag: dwl Description: Walo Kumbe Dogon Added: 2009-07-29 @@ -10382,6 +10438,7 @@ Type: language Subtag: dyn Description: Dyangadi +Description: Dhanggatti Added: 2009-07-29 %% Type: language @@ -10396,6 +10453,7 @@ %% Type: language Subtag: dyy +Description: Djabugay Description: Dyaabugay Added: 2009-07-29 %% @@ -10436,6 +10494,11 @@ Added: 2013-09-10 %% Type: language +Subtag: ebc +Description: Beginci +Added: 2020-03-28 +%% +Type: language Subtag: ebg Description: Ebughu Added: 2009-07-29 @@ -10557,6 +10620,7 @@ Subtag: ekc Description: Eastern Karnic Added: 2013-09-10 +Deprecated: 2020-03-28 %% Type: language Subtag: eke @@ -11196,6 +11260,11 @@ Added: 2009-07-29 %% Type: language +Subtag: fif +Description: Faifi +Added: 2020-06-08 +%% +Type: language Subtag: fil Description: Filipino Description: Pilipino @@ -11672,7 +11741,7 @@ %% Type: language Subtag: gbd -Description: Karadjeri +Description: Karajarri Added: 2009-07-29 %% Type: language @@ -11862,6 +11931,7 @@ Type: language Subtag: gdh Description: Gadjerawang +Description: Gajirrabeng Added: 2009-07-29 %% Type: language @@ -11951,6 +12021,11 @@ Added: 2009-07-29 %% Type: language +Subtag: gef +Description: Gerai +Added: 2020-03-28 +%% +Type: language Subtag: geg Description: Gengle Added: 2009-07-29 @@ -12056,7 +12131,7 @@ %% Type: language Subtag: gge -Description: Guragone +Description: Gurr-goni Added: 2009-07-29 %% Type: language @@ -12169,7 +12244,7 @@ %% Type: language Subtag: gia -Description: Kitja +Description: Kija Added: 2009-07-29 %% Type: language @@ -12362,6 +12437,8 @@ Subtag: gli Description: Guliguli Added: 2009-07-29 +Deprecated: 2020-03-28 +Preferred-Value: kzk %% Type: language Subtag: glj @@ -12457,6 +12534,12 @@ Scope: collection %% Type: language +Subtag: gmr +Description: Mirning +Description: Mirniny +Added: 2020-03-28 +%% +Type: language Subtag: gmu Description: Gumalu Added: 2009-07-29 @@ -12955,7 +13038,7 @@ %% Type: language Subtag: gue -Description: Gurinji +Description: Gurindji Added: 2009-07-29 %% Type: language @@ -13136,6 +13219,7 @@ %% Type: language Subtag: gwc +Description: Gawri Description: Kalami Added: 2009-07-29 %% @@ -13840,6 +13924,11 @@ Added: 2009-07-29 %% Type: language +Subtag: hng +Description: Hungu +Added: 2020-03-28 +%% +Type: language Subtag: hnh Description: ǁAni Added: 2009-07-29 @@ -14121,6 +14210,7 @@ Type: language Subtag: huc Description: ǂHua +Description: ǂʼAmkhoe Added: 2009-07-29 %% Type: language @@ -15292,6 +15382,7 @@ Type: language Subtag: jay Description: Yan-nhangu +Description: Nhangu Added: 2009-07-29 %% Type: language @@ -15488,6 +15579,7 @@ %% Type: language Subtag: jig +Description: Jingulu Description: Djingili Added: 2009-07-29 %% @@ -15889,6 +15981,7 @@ Type: language Subtag: kaa Description: Kara-Kalpak +Description: Karakalpak Added: 2005-10-16 %% Type: language @@ -17046,8 +17139,9 @@ %% Type: language Subtag: kjf -Description: Khalaj +Description: Khalaj [Indo-Iranian] Added: 2009-07-29 +Deprecated: 2020-03-28 %% Type: language Subtag: kjg @@ -17222,11 +17316,12 @@ Type: language Subtag: kkp Description: Gugubera +Description: Koko-Bera Added: 2009-07-29 %% Type: language Subtag: kkq -Description: Kaiku +Description: Kaeku Added: 2009-07-29 %% Type: language @@ -17266,6 +17361,7 @@ %% Type: language Subtag: kky +Description: Guugu Yimidhirr Description: Guguyimidjir Added: 2009-07-29 %% @@ -17321,7 +17417,7 @@ %% Type: language Subtag: klj -Description: Turkic Khalaj +Description: Khalaj Added: 2009-07-29 %% Type: language @@ -18320,6 +18416,7 @@ Type: language Subtag: ktd Description: Kokata +Description: Kukatha Added: 2009-07-29 %% Type: language @@ -18473,6 +18570,7 @@ Type: language Subtag: kui Description: Kuikúro-Kalapálo +Description: Kalapalo Added: 2009-07-29 %% Type: language @@ -18884,6 +18982,8 @@ Subtag: kxl Description: Nepali Kurux Added: 2009-07-29 +Deprecated: 2020-03-28 +Preferred-Value: kru %% Type: language Subtag: kxm @@ -18929,6 +19029,8 @@ Subtag: kxu Description: Kui (India) Added: 2009-07-29 +Deprecated: 2020-03-28 +Comments: see dwk, uki %% Type: language Subtag: kxv @@ -19341,6 +19443,7 @@ Subtag: lba Description: Lui Added: 2009-07-29 +Deprecated: 2019-04-16 %% Type: language Subtag: lbb @@ -19396,7 +19499,7 @@ %% Type: language Subtag: lbn -Description: Lamet +Description: Rmeet Added: 2009-07-29 %% Type: language @@ -19446,6 +19549,7 @@ %% Type: language Subtag: lby +Description: Lamalama Description: Lamu-Lamu Added: 2009-07-29 %% @@ -20162,6 +20266,8 @@ Subtag: llo Description: Khlor Added: 2009-07-29 +Deprecated: 2019-04-16 +Preferred-Value: ngt %% Type: language Subtag: llp @@ -20309,6 +20415,7 @@ Subtag: lmz Description: Lumbee Added: 2009-07-29 +Deprecated: 2020-03-28 %% Type: language Subtag: lna @@ -20654,6 +20761,11 @@ Macrolanguage: luy %% Type: language +Subtag: lsn +Description: Tibetan Sign Language +Added: 2019-04-16 +%% +Type: language Subtag: lso Description: Laos Sign Language Added: 2009-07-29 @@ -20680,6 +20792,11 @@ Added: 2009-07-29 %% Type: language +Subtag: lsv +Description: Sivia Sign Language +Added: 2019-04-16 +%% +Type: language Subtag: lsy Description: Mauritian Sign Language Added: 2010-03-11 @@ -20848,6 +20965,11 @@ Added: 2009-07-29 %% Type: language +Subtag: lvi +Description: Lavi +Added: 2019-04-16 +%% +Type: language Subtag: lvk Description: Lavukaleve Added: 2009-07-29 @@ -21454,7 +21576,7 @@ %% Type: language Subtag: mec -Description: Mara +Description: Marra Added: 2009-07-29 %% Type: language @@ -21523,7 +21645,7 @@ %% Type: language Subtag: mep -Description: Miriwung +Description: Miriwoong Added: 2009-07-29 %% Type: language @@ -21660,7 +21782,7 @@ %% Type: language Subtag: mfr -Description: Marithiel +Description: Marrithiyel Added: 2009-07-29 %% Type: language @@ -22745,6 +22867,7 @@ %% Type: language Subtag: moe +Description: Innu Description: Montagnais Added: 2009-07-29 %% @@ -22853,12 +22976,13 @@ %% Type: language Subtag: mpb +Description: Malak Malak Description: Mullukmulluk Added: 2009-07-29 %% Type: language Subtag: mpc -Description: Mangarayi +Description: Mangarrayi Added: 2009-07-29 %% Type: language @@ -22889,6 +23013,7 @@ Type: language Subtag: mpj Description: Martu Wangka +Description: Wangkajunga Added: 2009-07-29 %% Type: language @@ -24015,6 +24140,8 @@ Subtag: myd Description: Maramba Added: 2009-07-29 +Deprecated: 2019-04-16 +Preferred-Value: aog %% Type: language Subtag: mye @@ -24040,6 +24167,7 @@ Subtag: myi Description: Mina (India) Added: 2009-07-29 +Deprecated: 2019-04-16 %% Type: language Subtag: myj @@ -24375,7 +24503,7 @@ %% Type: language Subtag: nay -Description: Narrinyeri +Description: Ngarrindjeri Added: 2009-07-29 %% Type: language @@ -24432,7 +24560,7 @@ %% Type: language Subtag: nbj -Description: Ngarinman +Description: Ngarinyman Added: 2009-07-29 %% Type: language @@ -24467,7 +24595,7 @@ %% Type: language Subtag: nbr -Description: Numana-Nunku-Gbantu-Numbu +Description: Numana Added: 2009-07-29 %% Type: language @@ -24559,7 +24687,7 @@ %% Type: language Subtag: nck -Description: Nakara +Description: Na-kara Added: 2009-07-29 %% Type: language @@ -24931,7 +25059,7 @@ %% Type: language Subtag: ngh -Description: Nǀu +Description: Nǁng Added: 2009-07-29 %% Type: language @@ -25176,7 +25304,7 @@ %% Type: language Subtag: nig -Description: Ngalakan +Description: Ngalakgan Added: 2009-07-29 %% Type: language @@ -25798,6 +25926,8 @@ Subtag: nns Description: Ningye Added: 2009-07-29 +Deprecated: 2019-04-16 +Preferred-Value: nbr %% Type: language Subtag: nnt @@ -26149,6 +26279,11 @@ Added: 2009-07-29 %% Type: language +Subtag: nsb +Description: Lower Nossob +Added: 2020-03-28 +%% +Type: language Subtag: nsc Description: Nshi Added: 2009-07-29 @@ -26617,6 +26752,8 @@ Subtag: nxu Description: Narau Added: 2009-07-29 +Deprecated: 2020-03-28 +Preferred-Value: bpp %% Type: language Subtag: nxx @@ -26658,7 +26795,7 @@ %% Type: language Subtag: nyh -Description: Nyigina +Description: Nyikina Added: 2009-07-29 %% Type: language @@ -26713,7 +26850,7 @@ %% Type: language Subtag: nys -Description: Nyunga +Description: Nyungar Added: 2009-07-29 %% Type: language @@ -28116,7 +28253,7 @@ %% Type: language Subtag: pfe -Description: Peere +Description: Pere Added: 2009-07-29 %% Type: language @@ -28522,6 +28659,7 @@ Subtag: plp Description: Palpa Added: 2009-07-29 +Deprecated: 2020-03-28 %% Type: language Subtag: plq @@ -28707,6 +28845,11 @@ Added: 2009-07-29 %% Type: language +Subtag: pnd +Description: Mpinda +Added: 2019-04-16 +%% +Type: language Subtag: pne Description: Western Penan Added: 2009-07-29 @@ -28794,6 +28937,7 @@ %% Type: language Subtag: pnw +Description: Banyjima Description: Panytyima Added: 2009-07-29 %% @@ -29251,7 +29395,8 @@ %% Type: language Subtag: pti -Description: Pintiini +Description: Pindiini +Description: Wangkatha Added: 2009-07-29 %% Type: language @@ -30133,6 +30278,7 @@ %% Type: language Subtag: ril +Description: Riang Lang Description: Riang (Myanmar) Added: 2009-07-29 %% @@ -30153,7 +30299,7 @@ %% Type: language Subtag: rit -Description: Ritarungo +Description: Ritharrngu Added: 2009-07-29 %% Type: language @@ -30219,7 +30365,7 @@ %% Type: language Subtag: rmb -Description: Rembarunga +Description: Rembarrnga Added: 2009-07-29 %% Type: language @@ -30641,6 +30787,7 @@ Type: language Subtag: rxw Description: Karuwali +Description: Garuwali Added: 2013-09-10 %% Type: language @@ -31073,6 +31220,8 @@ Subtag: sdm Description: Semandang Added: 2009-07-29 +Deprecated: 2020-03-28 +Comments: see ebc, gef, sdq %% Type: language Subtag: sdn @@ -31091,6 +31240,11 @@ Added: 2009-07-29 %% Type: language +Subtag: sdq +Description: Semandang +Added: 2020-03-28 +%% +Type: language Subtag: sdr Description: Oraon Sadri Added: 2009-07-29 @@ -32206,7 +32360,7 @@ %% Type: language Subtag: snz -Description: Sinsauru +Description: Kou Added: 2009-07-29 %% Type: language @@ -32883,6 +33037,7 @@ Subtag: suj Description: Shubi Added: 2009-07-29 +Comments: see also xsj %% Type: language Subtag: suk @@ -33312,6 +33467,11 @@ Added: 2009-07-29 %% Type: language +Subtag: szy +Description: Sakizaya +Added: 2019-04-16 +%% +Type: language Subtag: taa Description: Lower Tanana Added: 2009-07-29 @@ -33437,6 +33597,7 @@ Subtag: tbb Description: Tapeba Added: 2009-07-29 +Deprecated: 2020-03-28 %% Type: language Subtag: tbc @@ -33465,6 +33626,7 @@ %% Type: language Subtag: tbh +Description: Dharawal Description: Thurawal Added: 2009-07-29 %% @@ -33644,6 +33806,7 @@ Type: language Subtag: tcs Description: Torres Strait Creole +Description: Yumplatok Added: 2009-07-29 %% Type: language @@ -34067,6 +34230,7 @@ %% Type: language Subtag: thd +Description: Kuuk Thaayorre Description: Thayore Added: 2009-07-29 %% @@ -34151,6 +34315,8 @@ Subtag: thw Description: Thudam Added: 2009-07-29 +Deprecated: 2020-06-08 +Preferred-Value: ola %% Type: language Subtag: thx @@ -34310,6 +34476,11 @@ Added: 2009-07-29 %% Type: language +Subtag: tjj +Description: Tjungundji +Added: 2019-04-16 +%% +Type: language Subtag: tjl Description: Tai Laing Added: 2012-08-12 @@ -34330,6 +34501,11 @@ Added: 2009-07-29 %% Type: language +Subtag: tjp +Description: Tjupany +Added: 2019-04-16 +%% +Type: language Subtag: tjs Description: Southern Tujia Added: 2009-07-29 @@ -35679,6 +35855,11 @@ Added: 2009-07-29 %% Type: language +Subtag: tvx +Description: Taivoan +Added: 2019-04-16 +%% +Type: language Subtag: tvy Description: Timor Pidgin Added: 2009-07-29 @@ -36157,6 +36338,11 @@ Added: 2009-07-29 %% Type: language +Subtag: uki +Description: Kui (India) +Added: 2020-03-28 +%% +Type: language Subtag: ukk Description: Muak Sa-aak Added: 2017-02-23 @@ -36188,6 +36374,11 @@ Added: 2009-07-29 %% Type: language +Subtag: ukv +Description: Kuku +Added: 2020-03-28 +%% +Type: language Subtag: ukw Description: Ukwuani-Aboh-Ndoni Added: 2009-07-29 @@ -36230,7 +36421,7 @@ %% Type: language Subtag: ulk -Description: Meriam +Description: Meriam Mir Added: 2009-07-29 %% Type: language @@ -36280,6 +36471,7 @@ %% Type: language Subtag: umg +Description: Morrobalama Description: Umbuygamu Added: 2009-07-29 %% @@ -36550,6 +36742,11 @@ Added: 2009-07-29 %% Type: language +Subtag: uss +Description: us-Saare +Added: 2019-04-16 +%% +Type: language Subtag: usu Description: Uya Added: 2009-07-29 @@ -36565,6 +36762,11 @@ Added: 2009-07-29 %% Type: language +Subtag: uth +Description: ut-Hun +Added: 2019-04-16 +%% +Type: language Subtag: utp Description: Amba (Solomon Islands) Added: 2009-07-29 @@ -37178,7 +37380,7 @@ %% Type: language Subtag: waq -Description: Wageman +Description: Wagiman Added: 2009-07-29 %% Type: language @@ -37301,7 +37503,7 @@ %% Type: language Subtag: wbt -Description: Wanman +Description: Warnman Added: 2009-07-29 %% Type: language @@ -37448,6 +37650,7 @@ %% Type: language Subtag: wgg +Description: Wangkangurru Description: Wangganguru Added: 2009-07-29 %% @@ -37521,7 +37724,7 @@ %% Type: language Subtag: wig -Description: Wik-Ngathana +Description: Wik Ngathan Added: 2009-07-29 %% Type: language @@ -37625,6 +37828,11 @@ Added: 2009-07-29 %% Type: language +Subtag: wkr +Description: Keerray-Woorroong +Added: 2019-04-16 +%% +Type: language Subtag: wku Description: Kunduvadi Added: 2009-07-29 @@ -37660,6 +37868,11 @@ Added: 2009-07-29 %% Type: language +Subtag: wlh +Description: Welaun +Added: 2020-03-28 +%% +Type: language Subtag: wli Description: Waioli Added: 2009-07-29 @@ -37857,10 +38070,12 @@ Type: language Subtag: wny Description: Wanyi +Description: Waanyi Added: 2012-08-12 %% Type: language Subtag: woa +Description: Kuwema Description: Tyaraity Added: 2009-07-29 %% @@ -37951,6 +38166,7 @@ %% Type: language Subtag: wrb +Description: Waluwarra Description: Warluwara Added: 2009-07-29 %% @@ -37962,11 +38178,12 @@ Type: language Subtag: wrg Description: Warungu +Description: Gudjal Added: 2009-07-29 %% Type: language Subtag: wrh -Description: Wiradhuri +Description: Wiradjuri Added: 2009-07-29 %% Type: language @@ -38439,6 +38656,7 @@ %% Type: language Subtag: xby +Description: Batjala Description: Batyala Added: 2013-09-10 %% @@ -38998,7 +39216,7 @@ %% Type: language Subtag: xmh -Description: Kuku-Muminh +Description: Kugu-Muminh Added: 2009-07-29 %% Type: language @@ -39127,6 +39345,11 @@ Added: 2013-09-10 %% Type: language +Subtag: xnm +Description: Ngumbarl +Added: 2020-03-28 +%% +Type: language Subtag: xnn Description: Northern Kankanay Added: 2009-07-29 @@ -39229,22 +39452,45 @@ Added: 2013-09-10 %% Type: language +Subtag: xpb +Description: Northeastern Tasmanian +Description: Pyemmairrener +Added: 2020-03-28 +%% +Type: language Subtag: xpc Description: Pecheneg Added: 2009-07-29 %% Type: language +Subtag: xpd +Description: Oyster Bay Tasmanian +Added: 2020-03-28 +%% +Type: language Subtag: xpe Description: Liberia Kpelle Added: 2009-07-29 Macrolanguage: kpe %% Type: language +Subtag: xpf +Description: Southeast Tasmanian +Description: Nuenonne +Added: 2020-03-28 +%% +Type: language Subtag: xpg Description: Phrygian Added: 2009-07-29 %% Type: language +Subtag: xph +Description: North Midlands Tasmanian +Description: Tyerrenoterpanner +Added: 2020-03-28 +%% +Type: language Subtag: xpi Description: Pictish Added: 2009-07-29 @@ -39260,6 +39506,11 @@ Added: 2009-07-29 %% Type: language +Subtag: xpl +Description: Port Sorell Tasmanian +Added: 2020-03-28 +%% +Type: language Subtag: xpm Description: Pumpokol Added: 2009-07-29 @@ -39305,11 +39556,34 @@ Added: 2009-07-29 %% Type: language +Subtag: xpv +Description: Northern Tasmanian +Description: Tommeginne +Added: 2020-03-28 +%% +Type: language +Subtag: xpw +Description: Northwestern Tasmanian +Description: Peerapper +Added: 2020-03-28 +%% +Type: language +Subtag: xpx +Description: Southwestern Tasmanian +Description: Toogee +Added: 2020-03-28 +%% +Type: language Subtag: xpy Description: Puyo Added: 2009-07-29 %% Type: language +Subtag: xpz +Description: Bruny Island Tasmanian +Added: 2020-03-28 +%% +Type: language Subtag: xqa Description: Karakhanid Added: 2009-07-29 @@ -39363,6 +39637,8 @@ Subtag: xrq Description: Karranga Added: 2013-09-10 +Deprecated: 2020-03-28 +Preferred-Value: dmw %% Type: language Subtag: xrr @@ -39423,8 +39699,7 @@ Subtag: xsj Description: Subi Added: 2009-07-29 -Deprecated: 2015-02-12 -Preferred-Value: suj +Comments: see also suj %% Type: language Subtag: xsl @@ -39596,6 +39871,8 @@ Subtag: xtz Description: Tasmanian Added: 2009-07-29 +Deprecated: 2020-03-28 +Comments: see xpb, xpd, xpf, xph, xpl, xpv, xpw, xpx, xpz %% Type: language Subtag: xua @@ -39625,6 +39902,7 @@ Type: language Subtag: xul Description: Ngunawal +Description: Nunukul Added: 2013-09-10 %% Type: language @@ -40258,6 +40536,7 @@ %% Type: language Subtag: yin +Description: Riang Lai Description: Yinchia Added: 2009-07-29 %% @@ -41216,6 +41495,11 @@ Added: 2009-07-29 %% Type: language +Subtag: zba +Description: Balaibalan +Added: 2020-03-28 +%% +Type: language Subtag: zbc Description: Central Berawan Added: 2009-07-29 @@ -41381,6 +41665,8 @@ Subtag: zir Description: Ziriya Added: 2009-07-29 +Deprecated: 2020-03-28 +Preferred-Value: scv %% Type: language Subtag: ziw @@ -41562,12 +41848,13 @@ %% Type: language Subtag: zml -Description: Madngele +Description: Matngala Added: 2009-07-29 %% Type: language Subtag: zmm Description: Marimanindji +Description: Marramaninyshi Added: 2009-07-29 %% Type: language @@ -42357,6 +42644,7 @@ Subtag: bbz Description: Babalia Creole Arabic Added: 2009-07-29 +Deprecated: 2020-03-28 Preferred-Value: bbz Prefix: ar Macrolanguage: ar @@ -42474,6 +42762,15 @@ Macrolanguage: zh %% Type: extlang +Subtag: cnp +Description: Northern Ping Chinese +Description: Northern Pinghua +Added: 2020-03-28 +Preferred-Value: cnp +Prefix: zh +Macrolanguage: zh +%% +Type: extlang Subtag: coa Description: Cocos Islands Malay Added: 2009-07-29 @@ -42541,6 +42838,15 @@ Prefix: sgn %% Type: extlang +Subtag: csp +Description: Southern Ping Chinese +Description: Southern Pinghua +Added: 2020-03-28 +Preferred-Value: csp +Prefix: zh +Macrolanguage: zh +%% +Type: extlang Subtag: csq Description: Croatia Sign Language Added: 2009-07-29 @@ -43008,6 +43314,7 @@ Description: Lyons Sign Language Added: 2009-07-29 Deprecated: 2018-03-08 +Preferred-Value: lsg Prefix: sgn %% Type: extlang @@ -43018,6 +43325,13 @@ Prefix: sgn %% Type: extlang +Subtag: lsn +Description: Tibetan Sign Language +Added: 2019-04-16 +Preferred-Value: lsn +Prefix: sgn +%% +Type: extlang Subtag: lso Description: Laos Sign Language Added: 2009-07-29 @@ -43040,6 +43354,13 @@ Prefix: sgn %% Type: extlang +Subtag: lsv +Description: Sivia Sign Language +Added: 2019-04-16 +Preferred-Value: lsv +Prefix: sgn +%% +Type: extlang Subtag: lsy Description: Mauritian Sign Language Added: 2010-03-11 @@ -43406,6 +43727,7 @@ Description: Rennellese Sign Language Added: 2009-07-29 Deprecated: 2017-02-23 +Preferred-Value: rsi Prefix: sgn %% Type: extlang @@ -43760,6 +44082,7 @@ Description: Yiddish Sign Language Added: 2009-07-29 Deprecated: 2015-02-12 +Preferred-Value: yds Prefix: sgn %% Type: extlang @@ -43963,6 +44286,11 @@ Added: 2005-10-16 %% Type: script +Subtag: Chrs +Description: Chorasmian +Added: 2019-09-11 +%% +Type: script Subtag: Cirt Description: Cirth Added: 2005-10-16 @@ -43999,6 +44327,11 @@ Added: 2005-10-16 %% Type: script +Subtag: Diak +Description: Dives Akuru +Added: 2019-09-11 +%% +Type: script Subtag: Dogr Description: Dogra Added: 2017-01-13 @@ -44795,6 +45128,11 @@ Added: 2011-08-16 %% Type: script +Subtag: Toto +Description: Toto +Added: 2020-05-12 +%% +Type: script Subtag: Ugar Description: Ugaritic Added: 2005-10-16 @@ -44836,6 +45174,11 @@ Added: 2005-10-16 %% Type: script +Subtag: Yezi +Description: Yezidi +Added: 2019-09-11 +%% +Type: script Subtag: Yiii Description: Yi Added: 2005-10-16 @@ -45680,7 +46023,7 @@ %% Type: region Subtag: MK -Description: The Former Yugoslav Republic of Macedonia +Description: North Macedonia Added: 2005-10-16 %% Type: region @@ -46492,6 +46835,12 @@ Letras in 1943 and generally used in Brazil until 2009 %% Type: variant +Subtag: akuapem +Description: Akuapem Twi +Added: 2017-06-05 +Prefix: tw +%% +Type: variant Subtag: alalc97 Description: ALA-LC Romanization, 1997 edition Added: 2009-12-09 @@ -46510,12 +46859,6 @@ continuum in Eastern Suriname and Western French Guiana %% Type: variant -Subtag: akuapem -Description: Akuapem Twi -Added: 2017-06-05 -Prefix: tw -%% -Type: variant Subtag: ao1990 Description: Portuguese Language Orthographic Agreement of 1990 (Acordo Ortográfico da Língua Portuguesa de 1990) @@ -46537,16 +46880,16 @@ Description: Eastern Armenian Added: 2006-09-18 Deprecated: 2018-03-24 -Preferred-Value: hy Prefix: hy +Comments: Preferred tag is hy %% Type: variant Subtag: arevmda Description: Western Armenian Added: 2006-09-18 Deprecated: 2018-03-24 -Preferred-Value: hyw Prefix: hy +Comments: Preferred tag is hyw %% Type: variant Subtag: asante @@ -46642,6 +46985,12 @@ Comments: Jargon embedded in American English %% Type: variant +Subtag: bornholm +Description: Bornholmsk +Added: 2019-03-27 +Prefix: da +%% +Type: variant Subtag: cisaup Description: Cisalpine Added: 2018-04-22 @@ -46985,6 +47334,16 @@ Creole continuum in Eastern Suriname and Western French Guiana %% Type: variant +Subtag: peano +Description: Latino Sine Flexione +Description: Interlingua de API +Description: Interlingua de Peano +Prefix: la +Comments: Peano’s Interlingua, created in 1903 by Giuseppe Peano as an + international auxiliary language +Added: 2020-03-12 +%% +Type: variant Subtag: petr1708 Description: Petrine orthography Added: 2010-10-10 @@ -47122,6 +47481,23 @@ Miensk 2005). %% Type: variant +Subtag: tongyong +Description: Tongyong Pinyin romanization +Added: 2020-06-08 +Prefix: zh-Latn +Comments: Former official transcription standard for Mandarin Chinese in + Taiwan. +%% +Type: variant +Subtag: tunumiit +Description: Tunumiisiut +Description: East Greenlandic +Description: Østgrønlandsk +Added: 2020-07-16 +Prefix: kl +Comments: Also known as Tunumiit oraasiat +%% +Type: variant Subtag: uccor Description: Unified Cornish orthography of Revived Cornish Added: 2008-10-14 @@ -47174,6 +47550,14 @@ "idioms" of the Romansh language. %% Type: variant +Subtag: vecdruka +Description: Latvian orthography used before 1920s ("vecā druka") +Added: 2020-09-26 +Prefix: lv +Comments: The subtag represents the old orthography of the Latvian + language used during c. 1600s–1920s. +%% +Type: variant Subtag: vivaraup Description: Vivaro-Alpine Added: 2018-04-22
diff --git a/make/data/macosxsigning/default.plist b/make/data/macosxsigning/default.plist new file mode 100644 index 0000000..01b1b8d --- /dev/null +++ b/make/data/macosxsigning/default.plist
@@ -0,0 +1,16 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd"> +<plist version="1.0"> +<dict> + <key>com.apple.security.cs.allow-jit</key> + <true/> + <key>com.apple.security.cs.allow-unsigned-executable-memory</key> + <true/> + <key>com.apple.security.cs.disable-library-validation</key> + <true/> + <key>com.apple.security.cs.allow-dyld-environment-variables</key> + <true/> + <key>com.apple.security.cs.debugger</key> + <true/> +</dict> +</plist>
diff --git a/make/data/macosxsigning/java.plist b/make/data/macosxsigning/java.plist new file mode 100644 index 0000000..b6f2a13 --- /dev/null +++ b/make/data/macosxsigning/java.plist
@@ -0,0 +1,18 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd"> +<plist version="1.0"> +<dict> + <key>com.apple.security.cs.allow-jit</key> + <true/> + <key>com.apple.security.cs.allow-unsigned-executable-memory</key> + <true/> + <key>com.apple.security.cs.disable-library-validation</key> + <true/> + <key>com.apple.security.cs.allow-dyld-environment-variables</key> + <true/> + <key>com.apple.security.cs.debugger</key> + <true/> + <key>com.apple.security.device.audio-input</key> + <true/> +</dict> +</plist>
diff --git a/make/data/macosxsigning/jspawnhelper.plist b/make/data/macosxsigning/jspawnhelper.plist new file mode 100644 index 0000000..484f4e0 --- /dev/null +++ b/make/data/macosxsigning/jspawnhelper.plist
@@ -0,0 +1,8 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd"> +<plist version="1.0"> + <dict> + <key>com.apple.security.cs.allow-dyld-environment-variables</key> + <true/> + </dict> +</plist>
diff --git a/make/data/publicsuffixlist/VERSION b/make/data/publicsuffixlist/VERSION index ada4668..3367b24 100644 --- a/make/data/publicsuffixlist/VERSION +++ b/make/data/publicsuffixlist/VERSION
@@ -1,2 +1,2 @@ -Github: https://raw.githubusercontent.com/publicsuffix/list/ce0d1a5fba657e55adea3abde4b7f1e50636ff10/public_suffix_list.dat -Date: 2019-01-28 +Github: https://raw.githubusercontent.com/publicsuffix/list/cbbba1d234670453df9c930dfbf510c0474d4301/public_suffix_list.dat +Date: 2020-04-24
diff --git a/make/data/publicsuffixlist/public_suffix_list.dat b/make/data/publicsuffixlist/public_suffix_list.dat index fbe8c24..27fe1ee 100644 --- a/make/data/publicsuffixlist/public_suffix_list.dat +++ b/make/data/publicsuffixlist/public_suffix_list.dat
@@ -79,7 +79,6 @@ express.aero federation.aero flight.aero -freight.aero fuel.aero gliding.aero government.aero @@ -155,8 +154,13 @@ net.al org.al -// am : https://en.wikipedia.org/wiki/.am +// am : https://www.amnic.net/policy/en/Policy_EN.pdf am +co.am +com.am +commune.am +net.am +org.am // ao : https://en.wikipedia.org/wiki/.ao // http://www.dns.ao/REGISTR.DOC @@ -208,6 +212,7 @@ co.at gv.at or.at +sth.ac.at // au : https://en.wikipedia.org/wiki/.au // http://www.auda.org.au/ @@ -235,6 +240,8 @@ wa.au // 3LDs act.edu.au +catholic.edu.au +// eq.edu.au - Removed at the request of the Queensland Department of Education nsw.edu.au nt.edu.au qld.edu.au @@ -250,6 +257,9 @@ tas.gov.au vic.gov.au wa.gov.au +// 4LDs +education.tas.edu.au +schools.nsw.edu.au // aw : https://en.wikipedia.org/wiki/.aw aw @@ -581,6 +591,7 @@ sorocaba.br srv.br taxi.br +tc.br teo.br the.br tmp.br @@ -708,11 +719,13 @@ *.ck !www.ck -// cl : https://en.wikipedia.org/wiki/.cl +// cl : https://www.nic.cl +// Confirmed by .CL registry <hsalgado@nic.cl> cl -gov.cl -gob.cl +aprendemas.cl co.cl +gob.cl +gov.cl mil.cl // cm : https://en.wikipedia.org/wiki/.cm plus bug 981927 @@ -971,8 +984,19 @@ // TODO: Check for updates (expected to be phased out around Q1/2009) aland.fi -// fj : https://en.wikipedia.org/wiki/.fj -*.fj +// fj : http://domains.fj/ +// Submitted by registry <garth.miller@cocca.org.nz> 2020-02-11 +fj +ac.fj +biz.fj +com.fj +gov.fj +info.fj +mil.fj +name.fj +net.fj +org.fj +pro.fj // fk : https://en.wikipedia.org/wiki/.fk *.fk @@ -984,17 +1008,16 @@ fo // fr : http://www.afnic.fr/ -// domaines descriptifs : http://www.afnic.fr/obtenir/chartes/nommage-fr/annexe-descriptifs +// domaines descriptifs : https://www.afnic.fr/medias/documents/Cadre_legal/Afnic_Naming_Policy_12122016_VEN.pdf fr -com.fr asso.fr +com.fr +gouv.fr nom.fr prd.fr -presse.fr tm.fr -// domaines sectoriels : http://www.afnic.fr/obtenir/chartes/nommage-fr/annexe-sectoriels +// domaines sectoriels : https://www.afnic.fr/en/products-and-services/the-fr-tld/sector-based-fr-domains-4.html aeroport.fr -assedic.fr avocat.fr avoues.fr cci.fr @@ -1002,7 +1025,6 @@ chirurgiens-dentistes.fr experts-comptables.fr geometre-expert.fr -gouv.fr greta.fr huissier-justice.fr medecin.fr @@ -1359,7 +1381,7 @@ gov.it edu.it // Reserved geo-names (regions and provinces): -// http://www.nic.it/sites/default/files/docs/Regulation_assignation_v7.1.pdf +// https://www.nic.it/sites/default/files/archivio/docs/Regulation_assignation_v7.1.pdf // Regions abr.it abruzzo.it @@ -4330,8 +4352,6 @@ norfolk.museum north.museum nrw.museum -nuernberg.museum -nuremberg.museum nyc.museum nyny.museum oceanographic.museum @@ -5879,26 +5899,19 @@ in.rs org.rs -// ru : https://cctld.ru/en/domains/domens_ru/reserved/ +// ru : https://cctld.ru/files/pdf/docs/en/rules_ru-rf.pdf +// Submitted by George Georgievsky <gug@cctld.ru> ru -ac.ru -edu.ru -gov.ru -int.ru -mil.ru -test.ru -// rw : http://www.nic.rw/cgi-bin/policy.pl +// rw : https://www.ricta.org.rw/sites/default/files/resources/registry_registrar_contract_0.pdf rw -gov.rw -net.rw -edu.rw ac.rw -com.rw co.rw -int.rw +coop.rw +gov.rw mil.rw -gouv.rw +net.rw +org.rw // sa : http://www.nic.net.sa/ sa @@ -6033,15 +6046,28 @@ perso.sn univ.sn -// so : http://www.soregistry.com/ +// so : http://sonic.so/policies/ so com.so +edu.so +gov.so +me.so net.so org.so // sr : https://en.wikipedia.org/wiki/.sr sr +// ss : https://registry.nic.ss/ +// Submitted by registry <technical@nic.ss> +ss +biz.ss +com.ss +edu.ss +gov.ss +net.ss +org.ss + // st : http://www.nic.st/html/policyrules/ st co.st @@ -6188,34 +6214,33 @@ edu.to mil.to -// subTLDs: https://www.nic.tr/forms/eng/policies.pdf -// and: https://www.nic.tr/forms/politikalar.pdf -// Submitted by <mehmetgurevin@gmail.com> +// tr : https://nic.tr/ +// https://nic.tr/forms/eng/policies.pdf +// https://nic.tr/index.php?USRACTN=PRICELST tr -com.tr -info.tr -biz.tr -net.tr -org.tr -web.tr -gen.tr -tv.tr av.tr -dr.tr bbs.tr -name.tr -tel.tr -gov.tr bel.tr -pol.tr +biz.tr +com.tr +dr.tr +edu.tr +gen.tr +gov.tr +info.tr mil.tr k12.tr -edu.tr kep.tr - +name.tr +net.tr +org.tr +pol.tr +tel.tr +tsk.tr +tv.tr +web.tr // Used by Northern Cyprus nc.tr - // Used by government agencies of Northern Cyprus gov.nc.tr @@ -6496,7 +6521,7 @@ k12.or.us k12.pa.us k12.pr.us -k12.ri.us +// k12.ri.us Removed at request of Kim Cournoyer <netsupport@staff.ri.net> k12.sc.us // k12.sd.us Bug 934131 - Removed at request of James Booze <James.Booze@k12.sd.us> k12.tn.us @@ -6783,8 +6808,16 @@ مصر // xn--e1a4c ("eu", Cyrillic) : EU +// https://eurid.eu ею +// xn--qxa6a ("eu", Greek) : EU +// https://eurid.eu +ευ + +// xn--mgbah1a3hjkrd ("Mauritania", Arabic) : MR +موريتانيا + // xn--node ("ge", Georgian Mkhedruli) : GE გე @@ -6938,7 +6971,8 @@ ак.срб // xn--p1ai ("rf", Russian-Cyrillic) : RU -// http://www.cctld.ru/en/docs/rulesrf.php +// https://cctld.ru/files/pdf/docs/en/rules_ru-rf.pdf +// Submitted by George Georgievsky <gug@cctld.ru> рф // xn--wgbl6a ("Qatar", Arabic) : QA @@ -7011,7 +7045,7 @@ // ye : http://www.y.net.ye/services/domain_name.htm *.ye -// za : http://www.zadna.org.za/content/page/domain-information +// za : https://www.zadna.org.za/content/page/domain-information/ ac.za agric.za alt.za @@ -7023,6 +7057,7 @@ mil.za net.za ngo.za +nic.za nis.za nom.za org.za @@ -7056,9 +7091,9 @@ // newGTLDs -// List of new gTLDs imported from https://newgtlds.icann.org/newgtlds.csv on 2018-05-08T19:40:37Z -// This list is auto-generated, don't edit it manually. +// List of new gTLDs imported from https://www.icann.org/resources/registries/gtlds/v2/gtlds.json on 2020-04-02T18:20:31Z +// This list is auto-generated, don't edit it manually. // aaa : 2015-02-26 American Automobile Association, Inc. aaa @@ -7104,10 +7139,7 @@ // aco : 2015-01-08 ACO Severin Ahlmann GmbH & Co. KG aco -// active : 2014-05-01 Active Network, LLC -active - -// actor : 2013-12-12 United TLD Holdco Ltd. +// actor : 2013-12-12 Dog Beach, LLC actor // adac : 2015-07-16 Allgemeiner Deutscher Automobil-Club e.V. (ADAC) @@ -7149,7 +7181,7 @@ // airbus : 2015-07-30 Airbus S.A.S. airbus -// airforce : 2014-03-06 United TLD Holdco Ltd. +// airforce : 2014-03-06 Dog Beach, LLC airforce // airtel : 2014-10-24 Bharti Airtel Limited @@ -7182,6 +7214,9 @@ // alstom : 2015-07-30 ALSTOM alstom +// amazon : 2019-12-19 Amazon Registry Services, Inc. +amazon + // americanexpress : 2015-07-31 American Express Travel Related Services Company, Inc. americanexpress @@ -7233,10 +7268,10 @@ // aramco : 2014-11-20 Aramco Services Company aramco -// archi : 2014-02-06 Afilias plc +// archi : 2014-02-06 Afilias Limited archi -// army : 2014-03-06 United TLD Holdco Ltd. +// army : 2014-03-06 Dog Beach, LLC army // art : 2016-03-24 UK Creative Ideas Limited @@ -7254,10 +7289,10 @@ // athleta : 2015-07-30 The Gap, Inc. athleta -// attorney : 2014-03-20 United TLD Holdco Ltd. +// attorney : 2014-03-20 Dog Beach, LLC attorney -// auction : 2014-03-20 United TLD Holdco Ltd. +// auction : 2014-03-20 Dog Beach, LLC auction // audi : 2015-05-21 AUDI Aktiengesellschaft @@ -7281,7 +7316,7 @@ // autos : 2014-01-09 DERAutos, LLC autos -// avianca : 2015-01-08 Aerovias del Continente Americano S.A. Avianca +// avianca : 2015-01-08 Avianca Holdings S.A. avianca // aws : 2015-06-25 Amazon Registry Services, Inc. @@ -7293,7 +7328,7 @@ // azure : 2014-12-18 Microsoft Corporation azure -// baby : 2015-04-09 Johnson & Johnson Services, Inc. +// baby : 2015-04-09 XYZ.COM LLC baby // baidu : 2015-01-08 Baidu, Inc. @@ -7305,7 +7340,7 @@ // bananarepublic : 2015-07-31 The Gap, Inc. bananarepublic -// band : 2014-06-12 United TLD Holdco Ltd. +// band : 2014-06-12 Dog Beach, LLC band // bank : 2014-09-25 fTLD Registry Services LLC @@ -7359,7 +7394,7 @@ // beats : 2015-05-14 Beats Electronics, LLC beats -// beauty : 2015-12-03 L'Oréal +// beauty : 2015-12-03 XYZ.COM LLC beauty // beer : 2014-01-09 Minds + Machines Group Limited @@ -7377,7 +7412,7 @@ // bestbuy : 2015-07-31 BBY Solutions, Inc. bestbuy -// bet : 2015-05-07 Afilias plc +// bet : 2015-05-07 Afilias Limited bet // bharti : 2014-01-09 Bharti Enterprises (Holding) Private Limited @@ -7398,18 +7433,15 @@ // bingo : 2014-12-04 Binky Moon, LLC bingo -// bio : 2014-03-06 Afilias plc +// bio : 2014-03-06 Afilias Limited bio -// black : 2014-01-16 Afilias plc +// black : 2014-01-16 Afilias Limited black // blackfriday : 2014-01-16 Uniregistry, Corp. blackfriday -// blanco : 2015-07-16 BLANCO GmbH + Co KG -blanco - // blockbuster : 2015-07-30 Dish DBS Corporation blockbuster @@ -7419,7 +7451,7 @@ // bloomberg : 2014-07-17 Bloomberg IP Holdings LLC bloomberg -// blue : 2013-11-07 Afilias plc +// blue : 2013-11-07 Afilias Limited blue // bms : 2014-10-30 Bristol-Myers Squibb Company @@ -7428,9 +7460,6 @@ // bmw : 2014-01-09 Bayerische Motoren Werke Aktiengesellschaft bmw -// bnl : 2014-07-24 Banca Nazionale del Lavoro -bnl - // bnpparibas : 2014-05-29 BNP Paribas bnpparibas @@ -7446,7 +7475,7 @@ // bom : 2014-10-16 Núcleo de Informação e Coordenação do Ponto BR - NIC.br bom -// bond : 2014-06-05 Bond University Limited +// bond : 2014-06-05 ShortDot SA bond // boo : 2014-01-30 Charleston Road Registry Inc. @@ -7473,7 +7502,7 @@ // boutique : 2013-11-14 Binky Moon, LLC boutique -// box : 2015-11-12 NS1 Limited +// box : 2015-11-12 .BOX INC. box // bradesco : 2014-12-18 Banco Bradesco S.A. @@ -7578,9 +7607,6 @@ // cars : 2014-11-13 Cars Registry Limited cars -// cartier : 2014-06-23 Richemont DNS Inc. -cartier - // casa : 2013-11-21 Minds + Machines Group Limited casa @@ -7638,7 +7664,7 @@ // channel : 2014-05-08 Charleston Road Registry Inc. channel -// charity : 2018-04-11 Corn Lake, LLC +// charity : 2018-04-11 Binky Moon, LLC charity // chase : 2015-04-30 JPMorgan Chase Bank, National Association @@ -7659,9 +7685,6 @@ // chrome : 2014-07-24 Charleston Road Registry Inc. chrome -// chrysler : 2015-07-30 FCA US LLC. -chrysler - // church : 2014-02-06 Binky Moon, LLC church @@ -7728,7 +7751,7 @@ // college : 2014-01-16 XYZ.COM LLC college -// cologne : 2014-02-05 punkt.wien GmbH +// cologne : 2014-02-05 dotKoeln GmbH cologne // comcast : 2015-07-23 Comcast IP Holdings I, LLC @@ -7743,7 +7766,7 @@ // company : 2013-11-07 Binky Moon, LLC company -// compare : 2015-10-08 iSelect Ltd +// compare : 2015-10-08 Registry Services, LLC compare // computer : 2013-10-24 Binky Moon, LLC @@ -7758,10 +7781,10 @@ // construction : 2013-09-16 Binky Moon, LLC construction -// consulting : 2013-12-05 United TLD Holdco Ltd. +// consulting : 2013-12-05 Dog Beach, LLC consulting -// contact : 2015-01-08 Top Level Spectrum, Inc. +// contact : 2015-01-08 Dog Beach, LLC contact // contractors : 2013-09-10 Binky Moon, LLC @@ -7791,6 +7814,9 @@ // courses : 2014-12-04 OPEN UNIVERSITIES AUSTRALIA PTY LTD courses +// cpa : 2019-06-10 American Institute of Certified Public Accountants +cpa + // credit : 2014-03-20 Binky Moon, LLC credit @@ -7818,13 +7844,13 @@ // csc : 2014-09-25 Alliance-One Services, Inc. csc -// cuisinella : 2014-04-03 SALM S.A.S. +// cuisinella : 2014-04-03 SCHMIDT GROUPE S.A.S. cuisinella // cymru : 2014-05-08 Nominet UK cymru -// cyou : 2015-01-22 Beijing Gamease Age Digital Technology Co., Ltd. +// cyou : 2015-01-22 ShortDot SA cyou // dabur : 2014-02-06 Dabur India Limited @@ -7833,7 +7859,7 @@ // dad : 2014-01-23 Charleston Road Registry Inc. dad -// dance : 2013-10-24 United TLD Holdco Ltd. +// dance : 2013-10-24 Dog Beach, LLC dance // data : 2016-06-02 Dish DBS Corporation @@ -7860,13 +7886,13 @@ // deal : 2015-06-25 Amazon Registry Services, Inc. deal -// dealer : 2014-12-22 Dealer Dot Com, Inc. +// dealer : 2014-12-22 Intercap Registry Inc. dealer // deals : 2014-05-22 Binky Moon, LLC deals -// degree : 2014-03-06 United TLD Holdco Ltd. +// degree : 2014-03-06 Dog Beach, LLC degree // delivery : 2014-09-11 Binky Moon, LLC @@ -7881,13 +7907,13 @@ // delta : 2015-02-19 Delta Air Lines, Inc. delta -// democrat : 2013-10-24 United TLD Holdco Ltd. +// democrat : 2013-10-24 Dog Beach, LLC democrat // dental : 2014-03-20 Binky Moon, LLC dental -// dentist : 2014-03-20 United TLD Holdco Ltd. +// dentist : 2014-03-20 Dog Beach, LLC dentist // desi : 2013-11-14 Desi Networks LLC @@ -7938,15 +7964,9 @@ // doctor : 2016-06-02 Binky Moon, LLC doctor -// dodge : 2015-07-30 FCA US LLC. -dodge - // dog : 2014-12-04 Binky Moon, LLC dog -// doha : 2014-09-18 Communications Regulatory Authority (CRA) -doha - // domains : 2013-10-17 Binky Moon, LLC domains @@ -7971,9 +7991,6 @@ // dunlop : 2015-07-02 The Goodyear Tire & Rubber Company dunlop -// duns : 2015-08-06 The Dun & Bradstreet Corporation -duns - // dupont : 2015-06-25 E. I. du Pont de Nemours and Company dupont @@ -7983,7 +8000,7 @@ // dvag : 2014-06-23 Deutsche Vermögensberatung Aktiengesellschaft DVAG dvag -// dvr : 2016-05-26 Hughes Satellite Systems Corporation +// dvr : 2016-05-26 DISH Technologies L.L.C. dvr // earth : 2014-12-04 Interlink Co., Ltd. @@ -8010,7 +8027,7 @@ // energy : 2014-09-11 Binky Moon, LLC energy -// engineer : 2014-03-06 United TLD Holdco Ltd. +// engineer : 2014-03-06 Dog Beach, LLC engineer // engineering : 2014-03-06 Binky Moon, LLC @@ -8019,9 +8036,6 @@ // enterprises : 2013-09-20 Binky Moon, LLC enterprises -// epost : 2015-07-23 Deutsche Post AG -epost - // epson : 2014-12-04 Seiko Epson Corporation epson @@ -8055,9 +8069,6 @@ // events : 2013-12-05 Binky Moon, LLC events -// everbank : 2014-05-15 EverBank -everbank - // exchange : 2014-03-06 Binky Moon, LLC exchange @@ -8085,13 +8096,13 @@ // faith : 2014-11-20 dot Faith Limited faith -// family : 2015-04-02 United TLD Holdco Ltd. +// family : 2015-04-02 Dog Beach, LLC family -// fan : 2014-03-06 Asiamix Digital Limited +// fan : 2014-03-06 Dog Beach, LLC fan -// fans : 2014-11-07 Asiamix Digital Limited +// fans : 2014-11-07 ZDNS International Limited fans // farm : 2013-11-07 Binky Moon, LLC @@ -8196,7 +8207,7 @@ // forex : 2014-12-11 Dotforex Registry Limited forex -// forsale : 2014-05-22 United TLD Holdco Ltd. +// forsale : 2014-05-22 Dog Beach, LLC forsale // forum : 2015-04-02 Fegistry, LLC @@ -8244,7 +8255,7 @@ // furniture : 2014-03-20 Binky Moon, LLC furniture -// futbol : 2013-09-20 United TLD Holdco Ltd. +// futbol : 2013-09-20 Dog Beach, LLC futbol // fyi : 2015-04-02 Binky Moon, LLC @@ -8265,7 +8276,7 @@ // game : 2015-05-28 Uniregistry, Corp. game -// games : 2015-05-28 United TLD Holdco Ltd. +// games : 2015-05-28 Dog Beach, LLC games // gap : 2015-07-31 The Gap, Inc. @@ -8274,6 +8285,9 @@ // garden : 2014-06-26 Minds + Machines Group Limited garden +// gay : 2019-05-23 Top Level Design, LLC +gay + // gbiz : 2014-07-17 Charleston Road Registry Inc. gbiz @@ -8301,7 +8315,7 @@ // gifts : 2014-07-03 Binky Moon, LLC gifts -// gives : 2014-03-06 United TLD Holdco Ltd. +// gives : 2014-03-06 Dog Beach, LLC gives // giving : 2014-11-13 Giving Limited @@ -8328,7 +8342,7 @@ // gmbh : 2016-01-29 Binky Moon, LLC gmbh -// gmo : 2014-01-09 GMO Internet Pte. Ltd. +// gmo : 2014-01-09 GMO Internet, Inc. gmo // gmx : 2014-04-24 1&1 Mail & Media GmbH @@ -8373,7 +8387,7 @@ // gratis : 2014-03-20 Binky Moon, LLC gratis -// green : 2014-05-08 Afilias plc +// green : 2014-05-08 Afilias Limited green // gripe : 2014-03-06 Binky Moon, LLC @@ -8403,7 +8417,7 @@ // guru : 2013-08-27 Binky Moon, LLC guru -// hair : 2015-12-03 L'Oréal +// hair : 2015-12-03 XYZ.COM LLC hair // hamburg : 2014-02-20 Hamburg Top-Level-Domain GmbH @@ -8412,7 +8426,7 @@ // hangout : 2014-11-13 Charleston Road Registry Inc. hangout -// haus : 2013-12-05 United TLD Holdco Ltd. +// haus : 2013-12-05 Dog Beach, LLC haus // hbo : 2015-07-30 HBO Registry Services, Inc. @@ -8484,9 +8498,6 @@ // honda : 2014-12-18 Honda Motor Co., Ltd. honda -// honeywell : 2015-07-23 Honeywell GTLD LLC -honeywell - // horse : 2013-11-21 Minds + Machines Group Limited horse @@ -8559,10 +8570,10 @@ // immo : 2014-07-10 Binky Moon, LLC immo -// immobilien : 2013-11-07 United TLD Holdco Ltd. +// immobilien : 2013-11-07 Dog Beach, LLC immobilien -// inc : 2018-03-10 GTLD Limited +// inc : 2018-03-10 Intercap Registry Inc. inc // industries : 2013-12-05 Binky Moon, LLC @@ -8604,9 +8615,6 @@ // irish : 2014-08-07 Binky Moon, LLC irish -// iselect : 2015-02-11 iSelect Ltd -iselect - // ismaili : 2015-08-06 Fondation Aga Khan (Aga Khan Foundation) ismaili @@ -8679,7 +8687,7 @@ // juniper : 2015-07-30 JUNIPER NETWORKS, INC. juniper -// kaufen : 2013-11-07 United TLD Holdco Ltd. +// kaufen : 2013-11-07 Dog Beach, LLC kaufen // kddi : 2014-09-12 KDDI CORPORATION @@ -8700,7 +8708,7 @@ // kia : 2015-07-09 KIA MOTORS CORPORATION kia -// kim : 2013-09-23 Afilias plc +// kim : 2013-09-23 Afilias Limited kim // kinder : 2014-11-07 Ferrero Trading Lux S.A. @@ -8715,7 +8723,7 @@ // kiwi : 2013-09-20 DOT KIWI LIMITED kiwi -// koeln : 2014-01-09 punkt.wien GmbH +// koeln : 2014-01-09 dotKoeln GmbH koeln // komatsu : 2015-01-08 Komatsu Ltd. @@ -8745,9 +8753,6 @@ // lacaixa : 2014-01-09 Fundación Bancaria Caixa d’Estalvis i Pensions de Barcelona, “la Caixa” lacaixa -// ladbrokes : 2015-08-06 LADBROKES INTERNATIONAL PLC -ladbrokes - // lamborghini : 2015-06-04 Automobili Lamborghini S.p.A. lamborghini @@ -8760,9 +8765,6 @@ // lancia : 2015-07-31 Fiat Chrysler Automobiles N.V. lancia -// lancome : 2015-07-23 L'Oréal -lancome - // land : 2013-09-10 Binky Moon, LLC land @@ -8784,10 +8786,10 @@ // latrobe : 2014-06-16 La Trobe University latrobe -// law : 2015-01-22 Minds + Machines Group Limited +// law : 2015-01-22 LW TLD Limited law -// lawyer : 2014-03-20 United TLD Holdco Ltd. +// lawyer : 2014-03-20 Dog Beach, LLC lawyer // lds : 2014-03-20 IRI Domain Management, LLC ("Applicant") @@ -8811,12 +8813,9 @@ // lexus : 2015-04-23 TOYOTA MOTOR CORPORATION lexus -// lgbt : 2014-05-08 Afilias plc +// lgbt : 2014-05-08 Afilias Limited lgbt -// liaison : 2014-10-02 Liaison Technologies, Incorporated -liaison - // lidl : 2014-09-18 Schwarz Domains und Services GmbH & Co. KG lidl @@ -8856,7 +8855,7 @@ // lipsy : 2015-06-25 Lipsy Ltd lipsy -// live : 2014-12-04 United TLD Holdco Ltd. +// live : 2014-12-04 Dog Beach, LLC live // living : 2015-07-30 Lifestyle Domain Holdings, Inc. @@ -8865,9 +8864,12 @@ // lixil : 2015-03-19 LIXIL Group Corporation lixil -// llc : 2017-12-14 Afilias plc +// llc : 2017-12-14 Afilias Limited llc +// llp : 2019-08-26 Dot Registry LLC +llp + // loan : 2014-11-20 dot Loan Limited loan @@ -8892,7 +8894,7 @@ // lotte : 2014-11-07 Lotte Holdings Co., Ltd. lotte -// lotto : 2014-04-10 Afilias plc +// lotto : 2014-04-10 Afilias Limited lotto // love : 2014-12-22 Merchant Law Group LLP @@ -8934,7 +8936,7 @@ // maison : 2013-12-05 Binky Moon, LLC maison -// makeup : 2015-01-15 L'Oréal +// makeup : 2015-01-15 XYZ.COM LLC makeup // man : 2014-12-04 MAN SE @@ -8949,7 +8951,7 @@ // map : 2016-06-09 Charleston Road Registry Inc. map -// market : 2014-03-06 United TLD Holdco Ltd. +// market : 2014-03-06 Dog Beach, LLC market // marketing : 2013-11-07 Binky Moon, LLC @@ -8997,7 +8999,7 @@ // men : 2015-02-26 Exclusive Registry Limited men -// menu : 2013-09-11 Wedding TLD2, LLC +// menu : 2013-09-11 Dot Menu Registry, LLC menu // merckmsd : 2016-07-14 MSD Registry Holdings, Inc. @@ -9036,10 +9038,7 @@ // mobile : 2016-06-02 Dish DBS Corporation mobile -// mobily : 2014-12-18 GreenTech Consultancy Company W.L.L. -mobily - -// moda : 2013-11-07 United TLD Holdco Ltd. +// moda : 2013-11-07 Dog Beach, LLC moda // moe : 2013-11-13 Interlink Co., Ltd. @@ -9057,16 +9056,13 @@ // money : 2014-10-16 Binky Moon, LLC money -// monster : 2015-09-11 Monster Worldwide, Inc. +// monster : 2015-09-11 XYZ.COM LLC monster -// mopar : 2015-07-30 FCA US LLC. -mopar - // mormon : 2013-12-05 IRI Domain Management, LLC ("Applicant") mormon -// mortgage : 2014-03-20 United TLD Holdco Ltd. +// mortgage : 2014-03-20 Dog Beach, LLC mortgage // moscow : 2013-12-19 Foundation for Assistance for Internet Technologies and Infrastructure Development (FAITID) @@ -9084,9 +9080,6 @@ // movie : 2015-02-05 Binky Moon, LLC movie -// movistar : 2014-10-16 Telefónica S.A. -movistar - // msd : 2015-07-23 MSD Registry Holdings, Inc. msd @@ -9102,9 +9095,6 @@ // nab : 2015-08-20 National Australia Bank Limited nab -// nadex : 2014-12-11 Nadex Domains, Inc. -nadex - // nagoya : 2013-10-24 GMO Registry, Inc. nagoya @@ -9114,7 +9104,7 @@ // natura : 2015-03-12 NATURA COSMÉTICOS S.A. natura -// navy : 2014-03-06 United TLD Holdco Ltd. +// navy : 2014-03-06 Dog Beach, LLC navy // nba : 2015-07-31 NBA REGISTRY, LLC @@ -9141,7 +9131,7 @@ // newholland : 2015-09-03 CNH Industrial N.V. newholland -// news : 2014-12-18 United TLD Holdco Ltd. +// news : 2014-12-18 Dog Beach, LLC news // next : 2015-06-18 Next plc @@ -9171,7 +9161,7 @@ // nikon : 2015-05-21 NIKON CORPORATION nikon -// ninja : 2013-11-07 United TLD Holdco Ltd. +// ninja : 2013-11-07 Dog Beach, LLC ninja // nissan : 2014-03-27 NISSAN MOTOR CO., LTD. @@ -9255,7 +9245,7 @@ // onyourside : 2015-07-23 Nationwide Mutual Insurance Company onyourside -// ooo : 2014-01-09 INFIBEAM INCORPORATION LIMITED +// ooo : 2014-01-09 INFIBEAM AVENUES LIMITED ooo // open : 2015-07-31 American Express Travel Related Services Company, Inc. @@ -9267,7 +9257,7 @@ // orange : 2015-03-12 Orange Brand Services Limited orange -// organic : 2014-03-27 Afilias plc +// organic : 2014-03-27 Afilias Limited organic // origins : 2015-10-01 The Estée Lauder Companies Inc. @@ -9282,7 +9272,7 @@ // ott : 2015-06-04 Dish DBS Corporation ott -// ovh : 2014-01-16 OVH SAS +// ovh : 2014-01-16 MédiaBC ovh // page : 2014-12-04 Charleston Road Registry Inc. @@ -9315,7 +9305,7 @@ // pccw : 2015-05-14 PCCW Enterprises Limited pccw -// pet : 2015-05-07 Afilias plc +// pet : 2015-05-07 Afilias Limited pet // pfizer : 2015-09-11 Pfizer Inc. @@ -9345,9 +9335,6 @@ // physio : 2014-05-01 PhysBiz Pty Ltd physio -// piaget : 2014-10-16 Richemont DNS Inc. -piaget - // pics : 2013-11-14 Uniregistry, Corp. pics @@ -9366,7 +9353,7 @@ // ping : 2015-06-11 Ping Registry Provider, Inc. ping -// pink : 2013-10-01 Afilias plc +// pink : 2013-10-01 Afilias Limited pink // pioneer : 2015-07-16 Pioneer Corporation @@ -9381,7 +9368,7 @@ // play : 2015-03-05 Charleston Road Registry Inc. play -// playstation : 2015-07-02 Sony Computer Entertainment Inc. +// playstation : 2015-07-02 Sony Interactive Entertainment Inc. playstation // plumbing : 2013-09-10 Binky Moon, LLC @@ -9396,7 +9383,7 @@ // pohl : 2014-06-23 Deutsche Vermögensberatung Aktiengesellschaft DVAG pohl -// poker : 2014-07-03 Afilias plc +// poker : 2014-07-03 Afilias Limited poker // politie : 2015-08-20 Politie Nederland @@ -9429,7 +9416,7 @@ // progressive : 2015-07-23 Progressive Casualty Insurance Company progressive -// promo : 2014-12-18 Afilias plc +// promo : 2014-12-18 Afilias Limited promo // properties : 2013-12-05 Binky Moon, LLC @@ -9447,7 +9434,7 @@ // prudential : 2015-07-30 Prudential Financial, Inc. prudential -// pub : 2013-12-12 United TLD Holdco Ltd. +// pub : 2013-12-12 Dog Beach, LLC pub // pwc : 2015-10-29 PricewaterhouseCoopers LLP @@ -9459,7 +9446,7 @@ // quebec : 2013-12-19 PointQuébec Inc quebec -// quest : 2015-03-26 Quest ION Limited +// quest : 2015-03-26 XYZ.COM LLC quest // qvc : 2015-07-30 QVC, Inc. @@ -9489,7 +9476,7 @@ // recipes : 2013-10-17 Binky Moon, LLC recipes -// red : 2013-11-07 Afilias plc +// red : 2013-11-07 Afilias Limited red // redstone : 2014-10-31 Redstone Haute Couture Co., Ltd. @@ -9498,7 +9485,7 @@ // redumbrella : 2015-03-26 Travelers TLD, LLC redumbrella -// rehab : 2014-03-06 United TLD Holdco Ltd. +// rehab : 2014-03-06 Dog Beach, LLC rehab // reise : 2014-03-13 Binky Moon, LLC @@ -9513,7 +9500,7 @@ // reliance : 2015-04-02 Reliance Industries Limited reliance -// ren : 2013-12-12 Beijing Qianxiang Wangjing Technology Development Co., Ltd. +// ren : 2013-12-12 ZDNS International Limited ren // rent : 2014-12-04 XYZ.COM LLC @@ -9528,7 +9515,7 @@ // report : 2013-12-05 Binky Moon, LLC report -// republican : 2014-03-20 United TLD Holdco Ltd. +// republican : 2014-03-20 Dog Beach, LLC republican // rest : 2013-12-19 Punto 2012 Sociedad Anonima Promotora de Inversion de Capital Variable @@ -9540,7 +9527,7 @@ // review : 2014-11-20 dot Review Limited review -// reviews : 2013-09-13 United TLD Holdco Ltd. +// reviews : 2013-09-13 Dog Beach, LLC reviews // rexroth : 2015-06-18 Robert Bosch GMBH @@ -9564,7 +9551,7 @@ // rio : 2014-02-27 Empresa Municipal de Informática SA - IPLANRIO rio -// rip : 2014-07-10 United TLD Holdco Ltd. +// rip : 2014-07-10 Dog Beach, LLC rip // rmit : 2015-11-19 Royal Melbourne Institute of Technology @@ -9573,7 +9560,7 @@ // rocher : 2014-12-18 Ferrero Trading Lux S.A. rocher -// rocks : 2013-11-14 United TLD Holdco Ltd. +// rocks : 2013-11-14 Dog Beach, LLC rocks // rodeo : 2013-12-19 Minds + Machines Group Limited @@ -9615,7 +9602,7 @@ // sakura : 2014-12-18 SAKURA Internet Inc. sakura -// sale : 2014-10-16 United TLD Holdco Ltd. +// sale : 2014-10-16 Dog Beach, LLC sale // salon : 2014-12-11 Binky Moon, LLC @@ -9666,7 +9653,7 @@ // schaeffler : 2015-08-06 Schaeffler Technologies AG & Co. KG schaeffler -// schmidt : 2014-04-03 SALM S.A.S. +// schmidt : 2014-04-03 SCHMIDT GROUPE S.A.S. schmidt // scholarships : 2014-04-24 Scholarships.com, LLC @@ -9708,7 +9695,7 @@ // seek : 2014-12-04 Seek Limited seek -// select : 2015-10-08 iSelect Ltd +// select : 2015-10-08 Registry Services, LLC select // sener : 2014-10-24 Sener Ingeniería y Sistemas, S.A. @@ -9750,7 +9737,7 @@ // shia : 2014-09-04 Asia Green IT System Bilgisayar San. ve Tic. Ltd. Sti. shia -// shiksha : 2013-11-14 Afilias plc +// shiksha : 2013-11-14 Afilias Limited shiksha // shoes : 2013-10-02 Binky Moon, LLC @@ -9786,10 +9773,10 @@ // site : 2015-01-15 DotSite Inc. site -// ski : 2015-04-09 Afilias plc +// ski : 2015-04-09 Afilias Limited ski -// skin : 2015-01-15 L'Oréal +// skin : 2015-01-15 XYZ.COM LLC skin // sky : 2014-06-19 Sky International AG @@ -9798,7 +9785,7 @@ // skype : 2014-12-18 Microsoft Corporation skype -// sling : 2015-07-30 Hughes Satellite Systems Corporation +// sling : 2015-07-30 DISH Technologies L.L.C. sling // smart : 2015-07-09 Smart Communications, Inc. (SMART) @@ -9813,13 +9800,13 @@ // soccer : 2015-03-26 Binky Moon, LLC soccer -// social : 2013-11-07 United TLD Holdco Ltd. +// social : 2013-11-07 Dog Beach, LLC social -// softbank : 2015-07-02 SoftBank Corp. +// softbank : 2015-07-02 SoftBank Group Corp. softbank -// software : 2014-03-20 United TLD Holdco Ltd. +// software : 2014-03-20 Dog Beach, LLC software // sohu : 2013-12-19 Sohu.com Limited @@ -9840,12 +9827,12 @@ // soy : 2014-01-23 Charleston Road Registry Inc. soy +// spa : 2019-09-19 Asia Spa and Wellness Promotion Council Limited +spa + // space : 2014-04-03 DotSpace Inc. space -// spiegel : 2014-02-05 SPIEGEL-Verlag Rudolf Augstein GmbH & Co. KG -spiegel - // sport : 2017-11-16 Global Association of International Sports Federations (GAISF) sport @@ -9858,9 +9845,6 @@ // srl : 2015-05-07 InterNetX, Corp srl -// srt : 2015-07-30 FCA US LLC. -srt - // stada : 2014-11-13 STADA Arzneimittel AG stada @@ -9870,9 +9854,6 @@ // star : 2015-01-08 Star India Private Limited star -// starhub : 2015-02-05 StarHub Ltd -starhub - // statebank : 2015-03-12 STATE BANK OF INDIA statebank @@ -9897,7 +9878,7 @@ // stream : 2016-01-08 dot Stream Limited stream -// studio : 2015-02-11 United TLD Holdco Ltd. +// studio : 2015-02-11 Dog Beach, LLC studio // study : 2014-12-11 OPEN UNIVERSITIES AUSTRALIA PTY LTD @@ -9990,9 +9971,6 @@ // technology : 2013-09-13 Binky Moon, LLC technology -// telefonica : 2014-10-16 Telefónica S.A. -telefonica - // temasek : 2014-08-07 Temasek Holdings (Private) Limited temasek @@ -10086,7 +10064,7 @@ // training : 2013-11-07 Binky Moon, LLC training -// travel : Dog Beach, LLC +// travel : 2015-10-09 Dog Beach, LLC travel // travelchannel : 2015-07-02 Lifestyle Domain Holdings, Inc. @@ -10125,16 +10103,13 @@ // ubs : 2014-12-11 UBS AG ubs -// uconnect : 2015-07-30 FCA US LLC. -uconnect - // unicom : 2015-10-15 China United Network Communications Corporation Limited unicom // university : 2014-03-06 Binky Moon, LLC university -// uno : 2013-09-11 Dot Latin LLC +// uno : 2013-09-11 DotSite Inc. uno // uol : 2014-05-01 UBN INTERNET LTDA. @@ -10161,16 +10136,16 @@ // verisign : 2015-08-13 VeriSign, Inc. verisign -// versicherung : 2014-03-20 TLD-BOX Registrydienstleistungen GmbH +// versicherung : 2014-03-20 tldbox GmbH versicherung -// vet : 2014-03-06 United TLD Holdco Ltd. +// vet : 2014-03-06 Dog Beach, LLC vet // viajes : 2013-10-17 Binky Moon, LLC viajes -// video : 2014-10-16 United TLD Holdco Ltd. +// video : 2014-10-16 Dog Beach, LLC video // vig : 2015-05-14 VIENNA INSURANCE GROUP AG Wiener Versicherung Gruppe @@ -10197,9 +10172,6 @@ // vision : 2013-12-05 Binky Moon, LLC vision -// vistaprint : 2014-09-18 Vistaprint Limited -vistaprint - // viva : 2014-11-07 Saudi Telecom Company viva @@ -10248,9 +10220,6 @@ // wanggou : 2014-12-18 Amazon Registry Services, Inc. wanggou -// warman : 2015-06-18 Weir Group IP Limited -warman - // watch : 2013-11-14 Binky Moon, LLC watch @@ -10365,7 +10334,7 @@ // xn--3bst00m : 2013-09-13 Eagle Horizon Limited 集团 -// xn--3ds443g : 2013-09-08 TLD REGISTRY LIMITED +// xn--3ds443g : 2013-09-08 TLD REGISTRY LIMITED OY 在线 // xn--3oq18vl8pn36a : 2015-07-02 Volkswagen (China) Investment Co., Ltd. @@ -10380,7 +10349,7 @@ // xn--45q11c : 2013-11-21 Zodiac Gemini Ltd 八卦 -// xn--4gbrim : 2013-10-04 Suhub Electronic Establishment +// xn--4gbrim : 2013-10-04 Fans TLD Limited موقع // xn--55qw42g : 2013-11-08 China Organizational Name Administration Center @@ -10395,7 +10364,7 @@ // xn--5tzm5g : 2014-12-22 Global Website TLD Asia Limited 网站 -// xn--6frz82g : 2013-09-23 Afilias plc +// xn--6frz82g : 2013-09-23 Afilias Limited 移动 // xn--6qq986b3xl : 2013-09-13 Tycoon Treasure Limited @@ -10440,10 +10409,13 @@ // xn--cck2b3b : 2015-02-26 Amazon Registry Services, Inc. ストア +// xn--cckwcxetd : 2019-12-19 Amazon Registry Services, Inc. +アマゾン + // xn--cg4bki : 2013-09-27 SAMSUNG SDS CO., LTD 삼성 -// xn--czr694b : 2014-01-16 Dot Trademark TLD Holding Company Limited +// xn--czr694b : 2014-01-16 Internet DotTrademark Organisation Limited 商标 // xn--czrs0t : 2013-12-19 Binky Moon, LLC @@ -10461,16 +10433,13 @@ // xn--efvy88h : 2014-08-22 Guangzhou YU Wei Information Technology Co., Ltd. 新闻 -// xn--estv75g : 2015-02-19 Industrial and Commercial Bank of China Limited -工行 - // xn--fct429k : 2015-04-09 Amazon Registry Services, Inc. 家電 // xn--fhbei : 2015-01-15 VeriSign Sarl كوم -// xn--fiq228c5hs : 2013-09-08 TLD REGISTRY LIMITED +// xn--fiq228c5hs : 2013-09-08 TLD REGISTRY LIMITED OY 中文网 // xn--fiq64b : 2013-10-14 CITIC Group Corporation @@ -10500,7 +10469,7 @@ // xn--i1b6b1a6a2e : 2013-11-14 Public Interest Registry संगठन -// xn--imr513n : 2014-12-11 Dot Trademark TLD Holding Company Limited +// xn--imr513n : 2014-12-11 Internet DotTrademark Organisation Limited 餐厅 // xn--io0a7i : 2013-11-14 China Internet Network Information Center (CNNIC) @@ -10509,6 +10478,9 @@ // xn--j1aef : 2015-01-15 VeriSign Sarl ком +// xn--jlq480n2rg : 2019-12-19 Amazon Registry Services, Inc. +亚马逊 + // xn--jlq61u9w7b : 2015-01-08 Nokia Corporation 诺基亚 @@ -10536,9 +10508,6 @@ // xn--mgbab2bd : 2013-10-31 CORE Association بازار -// xn--mgbb9fbpob : 2014-12-18 GreenTech Consultancy Company W.L.L. -موبايلي - // xn--mgbca7dzdo : 2015-07-30 Abu Dhabi Systems and Information Centre ابوظبي @@ -10572,7 +10541,7 @@ // xn--nyqy26a : 2014-11-07 Stable Tone Limited 健康 -// xn--otu796d : 2017-08-06 Dot Trademark TLD Holding Company Limited +// xn--otu796d : 2017-08-06 Jiang Yu Liang Cai Technology Company Limited 招聘 // xn--p1acf : 2013-12-12 Rusnames Limited @@ -10647,7 +10616,7 @@ // yamaxun : 2014-12-18 Amazon Registry Services, Inc. yamaxun -// yandex : 2014-04-10 YANDEX, LLC +// yandex : 2014-04-10 Yandex Europe B.V. yandex // yodobashi : 2014-11-20 YODOBASHI CAMERA CO.,LTD. @@ -10680,9 +10649,6 @@ // zip : 2014-05-08 Charleston Road Registry Inc. zip -// zippo : 2015-07-02 Zadco Company -zippo - // zone : 2013-11-14 Binky Moon, LLC zone @@ -10700,15 +10666,29 @@ inf.ua ltd.ua +// Adobe : https://www.adobe.com/ +// Submitted by Ian Boston <boston@adobe.com> +adobeaemcloud.com +adobeaemcloud.net +*.dev.adobeaemcloud.com + // Agnat sp. z o.o. : https://domena.pl // Submitted by Przemyslaw Plewa <it-admin@domena.pl> beep.pl +// alboto.ca : http://alboto.ca +// Submitted by Anton Avramov <avramov@alboto.ca> +barsy.ca + // Alces Software Ltd : http://alces-software.com // Submitted by Mark J. Titorenko <mark.titorenko@alces-software.com> *.compute.estate *.alces.network +// Altervista: https://www.altervista.org +// Submitted by Carlo Cannas <tech_staff@altervista.it> +altervista.org + // alwaysdata : https://www.alwaysdata.com // Submitted by Cyril <admin@alwaysdata.com> alwaysdata.net @@ -10809,6 +10789,10 @@ s3-website.eu-west-3.amazonaws.com s3-website.us-east-2.amazonaws.com +// Amsterdam Wireless: https://www.amsterdamwireless.nl/ +// Submitted by Imre Jonk <hostmaster@amsterdamwireless.nl> +amsw.nl + // Amune : https://amune.org/ // Submitted by Team Amune <cert@amune.org> t3l3p0rt.net @@ -10822,6 +10806,12 @@ // Submitted by Thomas Orozco <thomas@aptible.com> on-aptible.com +// ASEINet : https://www.aseinet.com/ +// Submitted by Asei SEKIGUCHI <mail@aseinet.com> +user.aseinet.ne.jp +gv.vc +d.gv.vc + // Asociación Amigos de la Informática "Euskalamiga" : http://encounter.eus/ // Submitted by Hector Martin <marcan@euskalencounter.org> user.party.eus @@ -10837,11 +10827,6 @@ // Submitted by Vincent Tseng <vincenttseng@asustor.com> myasustor.com -// Automattic Inc. : https://automattic.com/ -// Submitted by Alex Concha <alex.concha@automattic.com> -go-vip.co -wpcomstaging.com - // AVM : https://avm.de // Submitted by Andreas Weise <a.weise@avm.de> myfritz.net @@ -10851,10 +10836,22 @@ *.awdev.ca *.advisor.ws +// b-data GmbH : https://www.b-data.io +// Submitted by Olivier Benz <olivier.benz@b-data.ch> +b-data.io + // backplane : https://www.backplane.io // Submitted by Anthony Voutas <anthony@backplane.io> backplaneapp.io +// Balena : https://www.balena.io +// Submitted by Petros Angelatos <petrosagg@balena.io> +balena-devices.com + +// Banzai Cloud +// Submitted by Gabor Kozma <info@banzaicloud.com> +app.banzaicloud.io + // BetaInABox // Submitted by Adrian <adrian@betainabox.com> betainabox.com @@ -10890,6 +10887,7 @@ // Bytemark Hosting : https://www.bytemark.co.uk // Submitted by Paul Cammish <paul.cammish@bytemark.co.uk> +uk0.bigv.io dh.bytemark.co.uk vm.bytemark.co.uk @@ -10897,6 +10895,12 @@ // Submitted by Marcus Popp <admin@callidomus.com> mycd.eu +// Carrd : https://carrd.co +// Submitted by AJ <aj@carrd.co> +carrd.co +crd.co +uwu.ai + // CentralNic : http://www.centralnic.com/names/domains // Submitted by registry <gavin.brown@centralnic.com> ae.org @@ -10958,6 +10962,11 @@ // Submitted by Alex Stoddard <alex.stoddard@citrix.com> xenapponazure.com +// Civilized Discourse Construction Kit, Inc. : https://www.discourse.org/ +// Submitted by Rishabh Nambiar & Michael Brown <team@discourse.org> +discourse.group +discourse.team + // ClearVox : http://www.clearvox.nl/ // Submitted by Leon Rowland <leon@clearvox.nl> virtueeldomein.nl @@ -10966,10 +10975,20 @@ // Submitted by Quentin Adam <noc@clever-cloud.com> cleverapps.io +// Clerk : https://www.clerk.dev +// Submitted by Colin Sidoti <colin@clerk.dev> +*.lcl.dev +*.stg.dev + +// Clic2000 : https://clic2000.fr +// Submitted by Mathilde Blanchemanche <mathilde@clic2000.fr> +clic2000.net + // Cloud66 : https://www.cloud66.com/ // Submitted by Khash Sajadi <khash@cloud66.com> c66.me cloud66.ws +cloud66.zone // CloudAccess.net : https://www.cloudaccess.net/ // Submitted by Pawel Panek <noc@cloudaccess.net> @@ -10984,6 +11003,19 @@ cloudcontrolled.com cloudcontrolapp.com +// Cloudera, Inc. : https://www.cloudera.com/ +// Submitted by Philip Langdale <security@cloudera.com> +cloudera.site + +// Cloudflare, Inc. : https://www.cloudflare.com/ +// Submitted by Jake Riesterer <publicsuffixlist@cloudflare.com> +trycloudflare.com +workers.dev + +// Clovyr : https://clovyr.io +// Submitted by Patrick Nielsen <patrick@clovyr.io> +wnext.app + // co.ca : http://registry.co.ca/ co.ca @@ -11034,6 +11066,15 @@ webhosting.be hosting-cluster.nl +// Coordination Center for TLD RU and XN--P1AI : https://cctld.ru/en/domains/domens_ru/reserved/ +// Submitted by George Georgievsky <gug@cctld.ru> +ac.ru +edu.ru +gov.ru +int.ru +mil.ru +test.ru + // COSIMO GmbH : http://www.cosimo.de // Submitted by Rene Marticke <rmarticke@cosimo.de> dyn.cosidns.de @@ -11058,6 +11099,18 @@ // Submitted by Jonathan Rudenberg <jonathan@cupcake.io> cupcake.is +// Curv UG : https://curv-labs.de/ +// Submitted by Marvin Wiesner <Marvin@curv-labs.de> +curv.dev + +// Customer OCI - Oracle Dyn https://cloud.oracle.com/home https://dyn.com/dns/ +// Submitted by Gregory Drake <support@dyn.com> +// Note: This is intended to also include customer-oci.com due to wildcards implicitly including the current label +*.customer-oci.com +*.oci.customer-oci.com +*.ocp.customer-oci.com +*.ocs.customer-oci.com + // cyon GmbH : https://www.cyon.ch/ // Submitted by Dominic Luechinger <dol@cyon.ch> cyon.link @@ -11085,11 +11138,23 @@ reg.dk store.dk +// dappnode.io : https://dappnode.io/ +// Submitted by Abel Boldu / DAppNode Team <community@dappnode.io> +dyndns.dappnode.io + // dapps.earth : https://dapps.earth/ // Submitted by Daniil Burdakov <icqkill@gmail.com> *.dapps.earth *.bzz.dapps.earth +// Dark, Inc. : https://darklang.com +// Submitted by Paul Biggar <ops@darklang.com> +builtwithdark.com + +// Datawire, Inc : https://www.datawire.io +// Submitted by Richard Li <secalert@datawire.io> +edgestack.me + // Debian : https://www.debian.org/ // Submitted by Peter Palfrader / Debian Sysadmin Team <dsa-publicsuffixlist@debian.org> debian.net @@ -11463,10 +11528,19 @@ // Submitted by Vladimir Dudr <info@e4you.cz> e4.cz +// En root‽ : https://en-root.org +// Submitted by Emmanuel Raviart <emmanuel@raviart.com> +en-root.fr + // Enalean SAS: https://www.enalean.com // Submitted by Thomas Cottier <thomas.cottier@enalean.com> mytuleap.com +// ECG Robotics, Inc: https://ecgrobotics.org +// Submitted by <frc1533@ecgrobotics.org> +onred.one +staging.onred.one + // Enonic : http://enonic.com/ // Submitted by Erik Kaareng-Sunde <esu@enonic.com> enonic.io @@ -11550,6 +11624,10 @@ mymailer.com.tw url.tw +// Fabrica Technologies, Inc. : https://www.fabrica.dev/ +// Submitted by Eric Jiang <eric@fabrica.dev> +onfabrica.com + // Facebook, Inc. // Submitted by Peter Ruibal <public-suffix@fb.com> apps.fbsbx.com @@ -11633,9 +11711,11 @@ // Fancy Bits, LLC : http://getchannels.com // Submitted by Aman Gupta <aman@getchannels.com> channelsdvr.net +u.channelsdvr.net // Fastly Inc. : http://www.fastly.com/ // Submitted by Fastly Security <security@fastly.com> +fastly-terrarium.com fastlylb.net map.fastlylb.net freetls.fastly.net @@ -11650,6 +11730,10 @@ // Submitted by Likhachev Vasiliy <lihachev@fastvps.ru> fastpanel.direct fastvps-server.com +myfast.space +myfast.host +fastvps.site +fastvps.host // Featherhead : https://featherhead.xyz/ // Submitted by Simon Menke <simon@featherhead.xyz> @@ -11663,6 +11747,13 @@ app.os.fedoraproject.org app.os.stg.fedoraproject.org +// FearWorks Media Ltd. : https://fearworksmedia.co.uk +// submitted by Keith Fairley <domains@fearworksmedia.co.uk> +conn.uk +copro.uk +couk.me +ukco.me + // Fermax : https://fermax.com/ // submitted by Koen Van Isterdael <k.vanisterdael@fermax.be> mydobiss.com @@ -11670,6 +11761,12 @@ // Filegear Inc. : https://www.filegear.com // Submitted by Jason Zhu <jason@owtware.com> filegear.me +filegear-au.me +filegear-de.me +filegear-gb.me +filegear-ie.me +filegear-jp.me +filegear-sg.me // Firebase, Inc. // Submitted by Chris Raynor <chris@firebase.com> @@ -11677,9 +11774,12 @@ // Flynn : https://flynn.io // Submitted by Jonathan Rudenberg <jonathan@flynn.io> -flynnhub.com flynnhosting.net +// Frederik Braun https://frederik-braun.com +// Submitted by Frederik Braun <fb@frederik-braun.com> +0e.vc + // Freebox : http://www.freebox.fr // Submitted by Romain Fliedel <rfliedel@freebox.fr> freebox-os.com @@ -11708,6 +11808,16 @@ // Submitted by David Illsley <david.illsley@digital.cabinet-office.gov.uk> service.gov.uk +// Gehirn Inc. : https://www.gehirn.co.jp/ +// Submitted by Kohei YOSHIDA <tech@gehirn.co.jp> +gehirn.ne.jp +usercontent.jp + +// Gentlent, Inc. : https://www.gentlent.com +// Submitted by Tom Klein <tom@gentlent.com> +gentapps.com +lab.ms + // GitHub, Inc. // Submitted by Patrick Toomey <security@github.com> github.io @@ -11717,6 +11827,19 @@ // Submitted by Alex Hanselka <alex@gitlab.com> gitlab.io +// Glitch, Inc : https://glitch.com +// Submitted by Mads Hartmann <mads@glitch.com> +glitch.me + +// GMO Pepabo, Inc. : https://pepabo.com/ +// Submitted by dojineko <admin@pepabo.com> +lolipop.io + +// GOV.UK Platform as a Service : https://www.cloud.service.gov.uk/ +// Submitted by Tom Whitwell <tom.whitwell@digital.cabinet-office.gov.uk> +cloudapps.digital +london.cloudapps.digital + // UKHomeOffice : https://www.gov.uk/government/organisations/home-office // Submitted by Jon Shanks <jon.shanks@digital.homeoffice.gov.uk> homeoffice.gov.uk @@ -11734,8 +11857,10 @@ // Submitted by Eduardo Vela <evn@google.com> run.app a.run.app +web.app *.0emm.com appspot.com +*.r.appspot.com blogspot.ae blogspot.al blogspot.am @@ -11820,6 +11945,27 @@ withgoogle.com withyoutube.com +// Aaron Marais' Gitlab pages: https://lab.aaronleem.co.za +// Submitted by Aaron Marais <its_me@aaronleem.co.za> +graphox.us + +// Group 53, LLC : https://www.group53.com +// Submitted by Tyler Todd <noc@nova53.net> +awsmppl.com + +// Hakaran group: http://hakaran.cz +// Submited by Arseniy Sokolov <security@hakaran.cz> +fin.ci +free.hr +caa.li +ua.rs +conf.se + +// Handshake : https://handshake.org +// Submitted by Mike Damm <md@md.vc> +hs.zone +hs.run + // Hashbang : https://hashbang.sh hashbang.sh @@ -11845,14 +11991,47 @@ development.run ravendb.run +// HOSTBIP REGISTRY : https://www.hostbip.com/ +// Submitted by Atanunu Igbunuroghene <publicsuffixlist@hostbip.com> +bpl.biz +orx.biz +ng.city +biz.gl +ng.ink +col.ng +firm.ng +gen.ng +ltd.ng +ngo.ng +ng.school +sch.so + +// Häkkinen.fi +// Submitted by Eero Häkkinen <Eero+psl@Häkkinen.fi> +häkkinen.fi + // Ici la Lune : http://www.icilalune.com/ // Submitted by Simon Morvan <simon@icilalune.com> +*.moonscale.io moonscale.net // iki.fi // Submitted by Hannu Aronsson <haa@iki.fi> iki.fi +// Individual Network Berlin e.V. : https://www.in-berlin.de/ +// Submitted by Christian Seitz <chris@in-berlin.de> +dyn-berlin.de +in-berlin.de +in-brb.de +in-butter.de +in-dsl.de +in-dsl.net +in-dsl.org +in-vpn.de +in-vpn.net +in-vpn.org + // info.at : http://www.info.at/ biz.at info.at @@ -11900,9 +12079,15 @@ ipifony.net // IServ GmbH : https://iserv.eu -// Submitted by Kim-Alexander Brodowski <kim.brodowski@iserv.eu> +// Submitted by Kim-Alexander Brodowski <info@iserv.eu> mein-iserv.de +schulserver.de test-iserv.de +iserv.dev + +// I-O DATA DEVICE, INC. : http://www.iodata.com/ +// Submitted by Yuji Minagawa <domains-admin@iodata.jp> +iobb.net // Jino : https://www.jino.ru // Submitted by Sergey Ulyashin <ulyashin@jino.ru> @@ -11921,14 +12106,28 @@ // Submitted by Stefan Keim <admin@js.org> js.org +// KaasHosting : http://www.kaashosting.nl/ +// Submitted by Wouter Bakker <hostmaster@kaashosting.nl> +kaas.gg +khplay.nl + // Keyweb AG : https://www.keyweb.de // Submitted by Martin Dannehl <postmaster@keymachine.de> keymachine.de +// KingHost : https://king.host +// Submitted by Felipe Keller Braz <felipebraz@kinghost.com.br> +kinghost.net +uni5.net + // KnightPoint Systems, LLC : http://www.knightpoint.com/ // Submitted by Roy Keene <rkeene@knightpoint.com> knightpoint.systems +// KUROKU LTD : https://kuroku.ltd/ +// Submitted by DisposaBoy <security@oya.to> +oya.to + // .KRD : http://nic.krd/data/krd/Registration%20Policy.pdf co.krd edu.krd @@ -11945,6 +12144,20 @@ lpages.co lpusercontent.com +// Lelux.fi : https://lelux.fi/ +// Submitted by Lelux Admin <publisuffix@lelux.site> +lelux.site + +// Lifetime Hosting : https://Lifetime.Hosting/ +// Submitted by Mike Fillator <support@lifetime.hosting> +co.business +co.education +co.events +co.financial +co.network +co.place +co.technology + // Lightmaker Property Manager, Inc. : https://app.lmpm.com/ // Submitted by Greg Holland <greg.holland@lmpm.com> app.lmpm.com @@ -11958,10 +12171,23 @@ linkyard.cloud linkyard-cloud.ch +// Linode : https://linode.com +// Submitted by <security@linode.com> +members.linode.com +nodebalancer.linode.com + // LiquidNet Ltd : http://www.liquidnetlimited.com/ // Submitted by Victor Velchev <admin@liquidnetlimited.com> we.bs +// Log'in Line : https://www.loginline.com/ +// Submitted by Rémi Mach <remi.mach@loginline.com> +loginline.app +loginline.dev +loginline.io +loginline.services +loginline.site + // LubMAN UMCS Sp. z o.o : https://lubman.pl/ // Submitted by Ireneusz Maliszewski <ireneusz.maliszewski@lubman.pl> krasnik.pl @@ -12041,8 +12267,8 @@ co.pl // Microsoft Corporation : http://microsoft.com -// Submitted by Justin Luk <juluk@microsoft.com> -azurecontainer.io +// Submitted by Mostafa Elzeiny <moelzein@microsoft.com> +*.azurecontainer.io azurewebsites.net azure-mobile.net cloudapp.net @@ -12061,9 +12287,34 @@ org.ru pp.ru +// Nabu Casa : https://www.nabucasa.com +// Submitted by Paulus Schoutsen <infra@nabucasa.com> +ui.nabu.casa + +// Names.of.London : https://names.of.london/ +// Submitted by James Stevens <registry@names.of.london> or <james@jrcs.net> +pony.club +of.fashion +on.fashion +of.football +in.london +of.london +for.men +and.mom +for.mom +for.one +for.sale +of.work +to.work + +// NCTU.ME : https://nctu.me/ +// Submitted by Tocknicsu <admin@nctu.me> +nctu.me + // Netlify : https://www.netlify.com // Submitted by Jessica Parsons <jessica@netlify.com> bitballoon.com +netlify.app netlify.com // Neustar Inc. @@ -12221,20 +12472,23 @@ nyc.mn // NymNom : https://nymnom.com/ -// Submitted by Dave McCormack <dave.mccormack@nymnom.com> +// Submitted by NymNom <psl@nymnom.com> nom.ae nom.af nom.ai nom.al nym.by +nom.bz nym.bz nom.cl +nym.ec nom.gd nom.ge nom.gl nym.gr nom.gt nym.gy +nym.hk nom.hn nym.ie nom.im @@ -12246,6 +12500,7 @@ nym.li nym.lt nym.lu +nom.lv nym.me nom.mk nym.mn @@ -12270,6 +12525,10 @@ nom.vc nom.vg +// Observable, Inc. : https://observablehq.com +// Submitted by Mike Bostock <dns@observablehq.com> +static.observableusercontent.com + // Octopodal Solutions, LLC. : https://ulterius.io/ // Submitted by Andrew Sampson <andrew@ulterius.io> cya.gg @@ -12290,6 +12549,10 @@ // Submitted by Yngve Pettersen <yngve@opera.com> operaunite.com +// Oursky Limited : https://skygear.io/ +// Submited by Skygear Developer <hello@skygear.io> +skygearapp.com + // OutSystems // Submitted by Duarte Santos <domain-admin@outsystemscloud.com> outsystemscloud.com @@ -12332,6 +12595,10 @@ // Submitted by Steve Leung <steveleung@peplink.com> mypep.link +// Perspecta : https://perspecta.com/ +// Submitted by Kenneth Van Alstyne <kvanalstyne@perspecta.com> +perspecta.cloud + // Planet-Work : https://www.planet-work.com/ // Submitted by Frédéric VANNIÈRE <f.vanniere@planet-work.com> on-web.fr @@ -12341,6 +12608,20 @@ *.platform.sh *.platformsh.site +// Platter: https://platter.dev +// Submitted by Patrick Flor <patrick@platter.dev> +platter-app.com +platter-app.dev +platterp.us + +// Port53 : https://port53.io/ +// Submitted by Maximilian Schieder <maxi@zeug.co> +dyn53.io + +// Positive Codes Technology Company : http://co.bn/faq.html +// Submitted by Zulfais <pc@co.bn> +co.bn + // prgmr.com : https://prgmr.com/ // Submitted by Sarah Newman <owner@prgmr.com> xen.prgmr.com @@ -12349,6 +12630,14 @@ // Submitted by registry <lendl@nic.at> priv.at +// privacytools.io : https://www.privacytools.io/ +// Submitted by Jonah Aragon <jonah@privacytools.io> +prvcy.page + +// Protocol Labs : https://protocol.ai/ +// Submitted by Michael Burns <noc@protocol.ai> +*.dweb.link + // Protonet GmbH : http://protonet.io // Submitted by Martin Meier <admin@protonet.io> protonet.io @@ -12358,6 +12647,18 @@ chirurgiens-dentistes-en-france.fr byen.site +// pubtls.org: https://www.pubtls.org +// Submitted by Kor Nielsen <kor@pubtls.org> +pubtls.org + +// Qualifio : https://qualifio.com/ +// Submitted by Xavier De Cock <xdecock@gmail.com> +qualifioapp.com + +// QuickBackend: https://www.quickbackend.com +// Submitted by Dani Biro <dani@pymet.com> +qbuser.com + // Redstar Consultants : https://www.redstarconsultants.com/ // Submitted by Jons Slemmer <jons@redstarconsultants.com> instantcloud.cn @@ -12370,6 +12671,11 @@ // Submitted by Daniel Dent (https://www.danieldent.com/) qa2.com +// QCX +// Submitted by Cassandra Beelen <cassandra@beelen.one> +qcx.io +*.sys.qcx.io + // QNAP System Inc : https://www.qnap.com // Submitted by Nick Chang <nickchang@qnap.com> dev-myqnapcloud.com @@ -12390,6 +12696,12 @@ rackmaze.com rackmaze.net +// Rancher Labs, Inc : https://rancher.com +// Submitted by Vincent Fiduccia <domains@rancher.com> +*.on-k3s.io +*.on-rancher.cloud +*.on-rio.io + // Read The Docs, Inc : https://www.readthedocs.org // Submitted by David Fischer <team@readthedocs.org> readthedocs.io @@ -12398,6 +12710,16 @@ // Submitted by Tim Kramer <tkramer@rhcloud.com> rhcloud.com +// Render : https://render.com +// Submitted by Anurag Goel <dev@render.com> +app.render.com +onrender.com + +// Repl.it : https://repl.it +// Submitted by Mason Clayton <mason@repl.it> +repl.co +repl.run + // Resin.io : https://resin.io // Submitted by Tim Perry <tim@resin.io> resindevice.io @@ -12413,6 +12735,10 @@ ptplus.fit wellbeingzone.co.uk +// Rochester Institute of Technology : http://www.rit.edu/ +// Submitted by Jennifer Herting <jchits@rit.edu> +git-pages.rit.edu + // Sandstorm Development Group, Inc. : https://sandcats.io/ // Submitted by Asheesh Laroia <asheesh@sandstorm.io> sandcats.io @@ -12426,6 +12752,10 @@ // Submitted by Hanno Böck <hanno@schokokeks.org> schokokeks.net +// Scottish Government: https://www.gov.scot +// Submitted by Martin Ellis <martin.ellis@gov.scot> +gov.scot + // Scry Security : http://www.scrysec.com // Submitted by Shante Adam <shante@skyhat.io> scrysec.com @@ -12443,10 +12773,9 @@ myfirewall.org spdns.org -// SensioLabs, SAS : https://sensiolabs.com/ -// Submitted by Fabien Potencier <fabien.potencier@sensiolabs.com> -*.s5y.io -*.sensiosite.cloud +// Senseering GmbH : https://www.senseering.de +// Submitted by Felix Mönckemeyer <f.moenckemeyer@senseering.de> +senseering.net // Service Online LLC : http://drs.ua/ // Submitted by Serhii Bulakh <support@drs.ua> @@ -12462,6 +12791,18 @@ // Submitted by Alex Bowers <alex@shopblocks.com> myshopblocks.com +// Shopit : https://www.shopitcommerce.com/ +// Submitted by Craig McMahon <craig@shopitcommerce.com> +shopitsite.com + +// shopware AG : https://shopware.com +// Submitted by Jens Küper <cloud@shopware.com> +shopware.store + +// Siemens Mobility GmbH +// Submitted by Oliver Graebner <security@mo-siemens.io> +mo-siemens.io + // SinaAppEngine : http://sae.sina.com.cn/ // Submitted by SinaAppEngine <saesupport@sinacloud.com> 1kapp.com @@ -12480,12 +12821,20 @@ alpha.bounty-full.com beta.bounty-full.com +// Stackhero : https://www.stackhero.io +// Submitted by Adrien Gillon <adrien+public-suffix-list@stackhero.io> +stackhero-network.com + // staticland : https://static.land // Submitted by Seth Vincent <sethvincent@gmail.com> static.land dev.static.land sites.static.land +// Sony Interactive Entertainment LLC : https://sie.com/ +// Submitted by David Coles <david.coles@sony.com> +playstation-cloud.com + // SourceLair PC : https://www.sourcelair.com // Submitted by Antonis Kalipetis <akalipetis@sourcelair.com> apps.lair.io @@ -12499,6 +12848,10 @@ // Submitted by Stefan Neufeind <info@speedpartner.de> customer.speedpartner.de +// Standard Library : https://stdlib.com +// Submitted by Jacob Lee <jacob@stdlib.com> +api.stdlib.com + // Storj Labs Inc. : https://storj.io/ // Submitted by Philip Hutchins <hostmaster@storj.io> storj.farm @@ -12507,10 +12860,29 @@ // Submitted by Silke Hofstra <syscom@snt.utwente.nl> utwente.io +// Student-Run Computing Facility : https://www.srcf.net/ +// Submitted by Edwin Balani <sysadmins@srcf.net> +soc.srcf.net +user.srcf.net + // Sub 6 Limited: http://www.sub6.com // Submitted by Dan Miller <dm@sub6.com> temp-dns.com +// Swisscom Application Cloud: https://developer.swisscom.com +// Submitted by Matthias.Winzeler <matthias.winzeler@swisscom.com> +applicationcloud.io +scapp.io + +// Symfony, SAS : https://symfony.com/ +// Submitted by Fabien Potencier <fabien@symfony.com> +*.s5y.io +*.sensiosite.cloud + +// Syncloud : https://syncloud.org +// Submitted by Boris Rybalkin <syncloud@syncloud.it> +syncloud.it + // Synology, Inc. : https://www.synology.com/ // Submitted by Rony Weng <ronyweng@synology.com> diskstation.me @@ -12527,6 +12899,7 @@ myds.me synology.me vpnplus.to +direct.quickconnect.to // TAIFUN Software AG : http://taifun-software.de // Submitted by Bjoern Henke <dev-server@taifun-software.de> @@ -12539,6 +12912,10 @@ med.pl sopot.pl +// Teckids e.V. : https://www.teckids.org +// Submitted by Dominik George <dominik.george@teckids.org> +edugit.org + // Telebit : https://telebit.cloud // Submitted by AJ ONeal <aj@telebit.cloud> telebit.app @@ -12551,11 +12928,17 @@ // Thingdust AG : https://thingdust.com/ // Submitted by Adrian Imboden <adi@thingdust.com> +thingdustdata.com cust.dev.thingdust.io cust.disrec.thingdust.io cust.prod.thingdust.io cust.testing.thingdust.io +// Tlon.io : https://tlon.io +// Submitted by Mark Staarink <mark@tlon.io> +arvo.network +azimuth.network + // TownNews.com : http://www.townnews.com // Submitted by Dustin Ward <dward@townnews.com> bloxcms.com @@ -12626,6 +13009,11 @@ virtualuser.de virtual-user.de +// urown.net : https://urown.net +// Submitted by Hostmaster <hostmaster@urown.net> +urown.cloud +dnsupdate.info + // .US // Submitted by Ed Moore <Ed.Moore@lib.de.us> lib.de.us @@ -12642,6 +13030,22 @@ // Submitted by Adnan RIHAN <hostmaster@v-info.info> v-info.info +// Voorloper.com: https://voorloper.com +// Submitted by Nathan van Bakel <info@voorloper.com> +voorloper.cloud + +// V.UA Domain Administrator : https://domain.v.ua/ +// Submitted by Serhii Rostilo <sergey@rostilo.kiev.ua> +v.ua + +// Waffle Computer Inc., Ltd. : https://docs.waffleinfo.com +// Submitted by Masayuki Note <masa@blade.wafflecell.com> +wafflecell.com + +// WebHare bv: https://www.webhare.com/ +// Submitted by Arnold Hendriks <info@webhare.com> +*.webhare.dev + // WeDeploy by Liferay, Inc. : https://www.wedeploy.com // Submitted by Henrique Vicente <security@wedeploy.com> wedeploy.io @@ -12653,8 +13057,23 @@ remotewd.com // Wikimedia Labs : https://wikitech.wikimedia.org -// Submitted by Yuvi Panda <yuvipanda@wikimedia.org> +// Submitted by Arturo Borrero Gonzalez <aborrero@wikimedia.org> wmflabs.org +toolforge.org +wmcloud.org + +// WISP : https://wisp.gg +// Submitted by Stepan Fedotov <stepan@wisp.gg> +panel.gg +daemon.panel.gg + +// WoltLab GmbH : https://www.woltlab.com +// Submitted by Tim Düsterhus <security@woltlab.cloud> +myforum.community +community-pro.de +diskussionsbereich.de +community-pro.net +meinforum.net // XenonCloud GbR: https://xenoncloud.net // Submitted by Julian Uphoff <publicsuffixlist@xenoncloud.net> @@ -12672,6 +13091,12 @@ demon.nl xs4all.space +// Yandex.Cloud LLC: https://cloud.yandex.com +// Submitted by Alexander Lodin <security+psl@yandex-team.ru> +yandexcloud.net +storage.yandexcloud.net +website.yandexcloud.net + // YesCourse Pty Ltd : https://yescourse.com // Submitted by Atul Bhouraskar <atul@yescourse.com> official.academy @@ -12704,8 +13129,18 @@ // Submitted by Olli Vanhoja <olli@zeit.co> now.sh -// Zone.id : https://zone.id/ -// Submitted by Su Hendro <admin@zone.id> -zone.id +// Zine EOOD : https://zine.bg/ +// Submitted by Martin Angelov <martin@zine.bg> +bss.design + +// Zitcom A/S : https://www.zitcom.dk +// Submitted by Emil Stahl <esp@zitcom.dk> +basicserver.io +virtualserver.io +enterprisecloud.nu + +// Mintere : https://mintere.com/ +// Submitted by Ben Aubin <security@mintere.com> +mintere.site // ===END PRIVATE DOMAINS===
diff --git a/make/data/symbols/java.base-7.sym.txt b/make/data/symbols/java.base-7.sym.txt index a3f3168..5d8369f 100644 --- a/make/data/symbols/java.base-7.sym.txt +++ b/make/data/symbols/java.base-7.sym.txt
@@ -1,5 +1,5 @@ # -# Copyright (c) 2015, 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2015, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -632,10 +632,37 @@ class name java/security/cert/X509Certificate -method name verify descriptor (Ljava/security/PublicKey;Ljava/security/Provider;)V +class name java/security/interfaces/RSAKey +-method name getParams descriptor ()Ljava/security/spec/AlgorithmParameterSpec; + -class name java/security/spec/DSAGenParameterSpec class name java/security/spec/MGF1ParameterSpec -field name SHA224 descriptor Ljava/security/spec/MGF1ParameterSpec; +-field name SHA512_224 descriptor Ljava/security/spec/MGF1ParameterSpec; +-field name SHA512_256 descriptor Ljava/security/spec/MGF1ParameterSpec; + +class name java/security/spec/PSSParameterSpec +-field name TRAILER_FIELD_BC descriptor I +-method name toString descriptor ()Ljava/lang/String; + +class name java/security/spec/RSAKeyGenParameterSpec +-method name <init> descriptor (ILjava/math/BigInteger;Ljava/security/spec/AlgorithmParameterSpec;)V +-method name getKeyParams descriptor ()Ljava/security/spec/AlgorithmParameterSpec; + +class name java/security/spec/RSAMultiPrimePrivateCrtKeySpec +-method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;[Ljava/security/spec/RSAOtherPrimeInfo;Ljava/security/spec/AlgorithmParameterSpec;)V + +class name java/security/spec/RSAPrivateCrtKeySpec +-method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/security/spec/AlgorithmParameterSpec;)V + +class name java/security/spec/RSAPrivateKeySpec +-method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/security/spec/AlgorithmParameterSpec;)V +-method name getParams descriptor ()Ljava/security/spec/AlgorithmParameterSpec; + +class name java/security/spec/RSAPublicKeySpec +-method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/security/spec/AlgorithmParameterSpec;)V +-method name getParams descriptor ()Ljava/security/spec/AlgorithmParameterSpec; class name java/text/Collator -method name getInstance descriptor (Ljava/util/Locale;)Ljava/text/Collator; @@ -1457,6 +1484,14 @@ -class name java/util/function/UnaryOperator +class name java/util/jar/Attributes$Name +-field name EXTENSION_INSTALLATION descriptor Ljava/util/jar/Attributes$Name; +-field name IMPLEMENTATION_VENDOR_ID descriptor Ljava/util/jar/Attributes$Name; +-field name IMPLEMENTATION_URL descriptor Ljava/util/jar/Attributes$Name; +field name EXTENSION_INSTALLATION descriptor Ljava/util/jar/Attributes$Name; flags 19 +field name IMPLEMENTATION_VENDOR_ID descriptor Ljava/util/jar/Attributes$Name; flags 19 +field name IMPLEMENTATION_URL descriptor Ljava/util/jar/Attributes$Name; flags 19 + class name java/util/jar/JarFile -method name stream descriptor ()Ljava/util/stream/Stream; @@ -1535,6 +1570,9 @@ class name java/util/zip/ZipFile -method name stream descriptor ()Ljava/util/stream/Stream; +class name javax/crypto/SealedObject +header extends java/lang/Object implements java/io/Serializable flags 21 + class name javax/crypto/SecretKey header extends java/lang/Object implements java/security/Key flags 601 @@ -1559,6 +1597,12 @@ -class name javax/net/ssl/SNIServerName +class name javax/net/ssl/SSLEngine +-method name getApplicationProtocol descriptor ()Ljava/lang/String; +-method name getHandshakeApplicationProtocol descriptor ()Ljava/lang/String; +-method name setHandshakeApplicationProtocolSelector descriptor (Ljava/util/function/BiFunction;)V +-method name getHandshakeApplicationProtocolSelector descriptor ()Ljava/util/function/BiFunction; + class name javax/net/ssl/SSLParameters -method name setServerNames descriptor (Ljava/util/List;)V -method name getServerNames descriptor ()Ljava/util/List; @@ -1566,6 +1610,14 @@ -method name getSNIMatchers descriptor ()Ljava/util/Collection; -method name setUseCipherSuitesOrder descriptor (Z)V -method name getUseCipherSuitesOrder descriptor ()Z +-method name getApplicationProtocols descriptor ()[Ljava/lang/String; +-method name setApplicationProtocols descriptor ([Ljava/lang/String;)V + +class name javax/net/ssl/SSLSocket +-method name getApplicationProtocol descriptor ()Ljava/lang/String; +-method name getHandshakeApplicationProtocol descriptor ()Ljava/lang/String; +-method name setHandshakeApplicationProtocolSelector descriptor (Ljava/util/function/BiFunction;)V +-method name getHandshakeApplicationProtocolSelector descriptor ()Ljava/util/function/BiFunction; class name javax/net/ssl/SSLSocketFactory -method name createSocket descriptor (Ljava/net/Socket;Ljava/io/InputStream;Z)Ljava/net/Socket;
diff --git a/make/data/symbols/java.base-8.sym.txt b/make/data/symbols/java.base-8.sym.txt index 5f3cc3e..051003c 100644 --- a/make/data/symbols/java.base-8.sym.txt +++ b/make/data/symbols/java.base-8.sym.txt
@@ -1,5 +1,5 @@ # -# Copyright (c) 2015, 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2015, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -8200,6 +8200,7 @@ class name java/security/interfaces/RSAKey header extends java/lang/Object flags 601 classAnnotations @Ljdk/Profile+Annotation;(value=I1) method name getModulus descriptor ()Ljava/math/BigInteger; flags 401 +method name getParams descriptor ()Ljava/security/spec/AlgorithmParameterSpec; flags 1 class name java/security/interfaces/RSAMultiPrimePrivateCrtKey header extends java/lang/Object implements java/security/interfaces/RSAPrivateKey flags 601 classAnnotations @Ljdk/Profile+Annotation;(value=I1) @@ -8363,6 +8364,8 @@ field name SHA256 descriptor Ljava/security/spec/MGF1ParameterSpec; flags 19 field name SHA384 descriptor Ljava/security/spec/MGF1ParameterSpec; flags 19 field name SHA512 descriptor Ljava/security/spec/MGF1ParameterSpec; flags 19 +field name SHA512_224 descriptor Ljava/security/spec/MGF1ParameterSpec; flags 19 +field name SHA512_256 descriptor Ljava/security/spec/MGF1ParameterSpec; flags 19 method name <init> descriptor (Ljava/lang/String;)V flags 1 method name getDigestAlgorithm descriptor ()Ljava/lang/String; flags 1 @@ -8375,6 +8378,7 @@ class name java/security/spec/PSSParameterSpec header extends java/lang/Object implements java/security/spec/AlgorithmParameterSpec flags 21 classAnnotations @Ljdk/Profile+Annotation;(value=I1) field name DEFAULT descriptor Ljava/security/spec/PSSParameterSpec; flags 19 +field name TRAILER_FIELD_BC descriptor I constantValue 1 flags 19 method name <init> descriptor (Ljava/lang/String;Ljava/lang/String;Ljava/security/spec/AlgorithmParameterSpec;II)V flags 1 method name <init> descriptor (I)V flags 1 method name getDigestAlgorithm descriptor ()Ljava/lang/String; flags 1 @@ -8382,6 +8386,7 @@ method name getMGFParameters descriptor ()Ljava/security/spec/AlgorithmParameterSpec; flags 1 method name getSaltLength descriptor ()I flags 1 method name getTrailerField descriptor ()I flags 1 +method name toString descriptor ()Ljava/lang/String; flags 1 class name java/security/spec/RSAKeyGenParameterSpec header extends java/lang/Object implements java/security/spec/AlgorithmParameterSpec flags 21 classAnnotations @Ljdk/Profile+Annotation;(value=I1) @@ -8390,6 +8395,8 @@ method name <init> descriptor (ILjava/math/BigInteger;)V flags 1 method name getKeysize descriptor ()I flags 1 method name getPublicExponent descriptor ()Ljava/math/BigInteger; flags 1 +method name <init> descriptor (ILjava/math/BigInteger;Ljava/security/spec/AlgorithmParameterSpec;)V flags 1 +method name getKeyParams descriptor ()Ljava/security/spec/AlgorithmParameterSpec; flags 1 class name java/security/spec/RSAMultiPrimePrivateCrtKeySpec header extends java/security/spec/RSAPrivateKeySpec flags 21 classAnnotations @Ljdk/Profile+Annotation;(value=I1) @@ -8401,6 +8408,7 @@ method name getPrimeExponentQ descriptor ()Ljava/math/BigInteger; flags 1 method name getCrtCoefficient descriptor ()Ljava/math/BigInteger; flags 1 method name getOtherPrimeInfo descriptor ()[Ljava/security/spec/RSAOtherPrimeInfo; flags 1 +method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;[Ljava/security/spec/RSAOtherPrimeInfo;Ljava/security/spec/AlgorithmParameterSpec;)V flags 1 class name java/security/spec/RSAOtherPrimeInfo header extends java/lang/Object flags 21 classAnnotations @Ljdk/Profile+Annotation;(value=I1) @@ -8418,18 +8426,23 @@ method name getPrimeExponentP descriptor ()Ljava/math/BigInteger; flags 1 method name getPrimeExponentQ descriptor ()Ljava/math/BigInteger; flags 1 method name getCrtCoefficient descriptor ()Ljava/math/BigInteger; flags 1 +method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/security/spec/AlgorithmParameterSpec;)V flags 1 class name java/security/spec/RSAPrivateKeySpec header extends java/lang/Object implements java/security/spec/KeySpec flags 21 classAnnotations @Ljdk/Profile+Annotation;(value=I1) method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;)V flags 1 method name getModulus descriptor ()Ljava/math/BigInteger; flags 1 method name getPrivateExponent descriptor ()Ljava/math/BigInteger; flags 1 +method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/security/spec/AlgorithmParameterSpec;)V flags 1 +method name getParams descriptor ()Ljava/security/spec/AlgorithmParameterSpec; flags 1 class name java/security/spec/RSAPublicKeySpec header extends java/lang/Object implements java/security/spec/KeySpec flags 21 classAnnotations @Ljdk/Profile+Annotation;(value=I1) method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;)V flags 1 method name getModulus descriptor ()Ljava/math/BigInteger; flags 1 method name getPublicExponent descriptor ()Ljava/math/BigInteger; flags 1 +method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/security/spec/AlgorithmParameterSpec;)V flags 1 +method name getParams descriptor ()Ljava/security/spec/AlgorithmParameterSpec; flags 1 class name java/security/spec/X509EncodedKeySpec header extends java/security/spec/EncodedKeySpec flags 21 classAnnotations @Ljdk/Profile+Annotation;(value=I1) @@ -10429,6 +10442,7 @@ method name getValue descriptor ()I flags 1 method name range descriptor (Ljava/time/temporal/TemporalField;)Ljava/time/temporal/ValueRange; flags 1 method name toString descriptor ()Ljava/lang/String; flags 1 +method name getDisplayName descriptor (Ljava/time/format/TextStyle;Ljava/util/Locale;)Ljava/lang/String; flags 1 class name java/time/chrono/MinguoChronology header extends java/time/chrono/AbstractChronology implements java/io/Serializable flags 31 classAnnotations @Ljdk/Profile+Annotation;(value=I1) @@ -15563,15 +15577,15 @@ field name SEALED descriptor Ljava/util/jar/Attributes$Name; flags 19 field name EXTENSION_LIST descriptor Ljava/util/jar/Attributes$Name; flags 19 field name EXTENSION_NAME descriptor Ljava/util/jar/Attributes$Name; flags 19 -field name EXTENSION_INSTALLATION descriptor Ljava/util/jar/Attributes$Name; flags 19 field name IMPLEMENTATION_TITLE descriptor Ljava/util/jar/Attributes$Name; flags 19 field name IMPLEMENTATION_VERSION descriptor Ljava/util/jar/Attributes$Name; flags 19 field name IMPLEMENTATION_VENDOR descriptor Ljava/util/jar/Attributes$Name; flags 19 -field name IMPLEMENTATION_VENDOR_ID descriptor Ljava/util/jar/Attributes$Name; flags 19 -field name IMPLEMENTATION_URL descriptor Ljava/util/jar/Attributes$Name; flags 19 field name SPECIFICATION_TITLE descriptor Ljava/util/jar/Attributes$Name; flags 19 field name SPECIFICATION_VERSION descriptor Ljava/util/jar/Attributes$Name; flags 19 field name SPECIFICATION_VENDOR descriptor Ljava/util/jar/Attributes$Name; flags 19 +field name EXTENSION_INSTALLATION descriptor Ljava/util/jar/Attributes$Name; flags 19 deprecated true runtimeAnnotations @Ljava/lang/Deprecated; +field name IMPLEMENTATION_VENDOR_ID descriptor Ljava/util/jar/Attributes$Name; flags 19 deprecated true runtimeAnnotations @Ljava/lang/Deprecated; +field name IMPLEMENTATION_URL descriptor Ljava/util/jar/Attributes$Name; flags 19 deprecated true runtimeAnnotations @Ljava/lang/Deprecated; method name <init> descriptor (Ljava/lang/String;)V flags 1 method name equals descriptor (Ljava/lang/Object;)Z flags 1 method name hashCode descriptor ()I flags 1 @@ -16698,6 +16712,7 @@ class name javax/crypto/SealedObject header extends java/lang/Object implements java/io/Serializable flags 21 +innerclass innerClass java/lang/invoke/MethodHandles$Lookup outerClass java/lang/invoke/MethodHandles innerClassName Lookup flags 19 field name encodedParams descriptor [B flags 4 method name <init> descriptor (Ljava/io/Serializable;Ljavax/crypto/Cipher;)V thrownTypes java/io/IOException,javax/crypto/IllegalBlockSizeException flags 1 method name <init> descriptor (Ljavax/crypto/SealedObject;)V flags 4 @@ -17086,6 +17101,10 @@ method name getEnableSessionCreation descriptor ()Z flags 401 method name getSSLParameters descriptor ()Ljavax/net/ssl/SSLParameters; flags 1 method name setSSLParameters descriptor (Ljavax/net/ssl/SSLParameters;)V flags 1 +method name getApplicationProtocol descriptor ()Ljava/lang/String; flags 1 +method name getHandshakeApplicationProtocol descriptor ()Ljava/lang/String; flags 1 +method name setHandshakeApplicationProtocolSelector descriptor (Ljava/util/function/BiFunction;)V flags 1 signature (Ljava/util/function/BiFunction<Ljavax/net/ssl/SSLEngine;Ljava/util/List<Ljava/lang/String;>;Ljava/lang/String;>;)V +method name getHandshakeApplicationProtocolSelector descriptor ()Ljava/util/function/BiFunction; flags 1 signature ()Ljava/util/function/BiFunction<Ljavax/net/ssl/SSLEngine;Ljava/util/List<Ljava/lang/String;>;Ljava/lang/String;>; class name javax/net/ssl/SSLEngineResult header extends java/lang/Object flags 21 classAnnotations @Ljdk/Profile+Annotation;(value=I1) @@ -17156,6 +17175,8 @@ method name getSNIMatchers descriptor ()Ljava/util/Collection; flags 11 signature ()Ljava/util/Collection<Ljavax/net/ssl/SNIMatcher;>; method name setUseCipherSuitesOrder descriptor (Z)V flags 11 method name getUseCipherSuitesOrder descriptor ()Z flags 11 +method name getApplicationProtocols descriptor ()[Ljava/lang/String; flags 1 +method name setApplicationProtocols descriptor ([Ljava/lang/String;)V flags 1 class name javax/net/ssl/SSLPeerUnverifiedException header extends javax/net/ssl/SSLException flags 21 classAnnotations @Ljdk/Profile+Annotation;(value=I1) @@ -17272,6 +17293,10 @@ method name getEnableSessionCreation descriptor ()Z flags 401 method name getSSLParameters descriptor ()Ljavax/net/ssl/SSLParameters; flags 1 method name setSSLParameters descriptor (Ljavax/net/ssl/SSLParameters;)V flags 1 +method name getApplicationProtocol descriptor ()Ljava/lang/String; flags 1 +method name getHandshakeApplicationProtocol descriptor ()Ljava/lang/String; flags 1 +method name setHandshakeApplicationProtocolSelector descriptor (Ljava/util/function/BiFunction;)V flags 1 signature (Ljava/util/function/BiFunction<Ljavax/net/ssl/SSLSocket;Ljava/util/List<Ljava/lang/String;>;Ljava/lang/String;>;)V +method name getHandshakeApplicationProtocolSelector descriptor ()Ljava/util/function/BiFunction; flags 1 signature ()Ljava/util/function/BiFunction<Ljavax/net/ssl/SSLSocket;Ljava/util/List<Ljava/lang/String;>;Ljava/lang/String;>; class name javax/net/ssl/SSLSocketFactory header extends javax/net/SocketFactory flags 421 classAnnotations @Ljdk/Profile+Annotation;(value=I1)
diff --git a/make/data/symbols/java.base-9.sym.txt b/make/data/symbols/java.base-9.sym.txt index bdaa9a3..99a4f8e 100644 --- a/make/data/symbols/java.base-9.sym.txt +++ b/make/data/symbols/java.base-9.sym.txt
@@ -1,5 +1,5 @@ # -# Copyright (c) 2015, 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2015, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -2083,13 +2083,42 @@ method name toString descriptor ()Ljava/lang/String; flags 1 method name clone descriptor ()Ljava/lang/Object; thrownTypes java/lang/CloneNotSupportedException flags 1041 +class name java/security/interfaces/RSAKey +-method name getParams descriptor ()Ljava/security/spec/AlgorithmParameterSpec; + class name java/security/spec/EncodedKeySpec method name <init> descriptor ([BLjava/lang/String;)V flags 4 method name getAlgorithm descriptor ()Ljava/lang/String; flags 1 +class name java/security/spec/MGF1ParameterSpec +-field name SHA512_224 descriptor Ljava/security/spec/MGF1ParameterSpec; +-field name SHA512_256 descriptor Ljava/security/spec/MGF1ParameterSpec; + class name java/security/spec/PKCS8EncodedKeySpec method name <init> descriptor ([BLjava/lang/String;)V flags 1 +class name java/security/spec/PSSParameterSpec +-field name TRAILER_FIELD_BC descriptor I +-method name toString descriptor ()Ljava/lang/String; + +class name java/security/spec/RSAKeyGenParameterSpec +-method name <init> descriptor (ILjava/math/BigInteger;Ljava/security/spec/AlgorithmParameterSpec;)V +-method name getKeyParams descriptor ()Ljava/security/spec/AlgorithmParameterSpec; + +class name java/security/spec/RSAMultiPrimePrivateCrtKeySpec +-method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;[Ljava/security/spec/RSAOtherPrimeInfo;Ljava/security/spec/AlgorithmParameterSpec;)V + +class name java/security/spec/RSAPrivateCrtKeySpec +-method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/security/spec/AlgorithmParameterSpec;)V + +class name java/security/spec/RSAPrivateKeySpec +-method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/security/spec/AlgorithmParameterSpec;)V +-method name getParams descriptor ()Ljava/security/spec/AlgorithmParameterSpec; + +class name java/security/spec/RSAPublicKeySpec +-method name <init> descriptor (Ljava/math/BigInteger;Ljava/math/BigInteger;Ljava/security/spec/AlgorithmParameterSpec;)V +-method name getParams descriptor ()Ljava/security/spec/AlgorithmParameterSpec; + class name java/security/spec/X509EncodedKeySpec method name <init> descriptor ([BLjava/lang/String;)V flags 1 @@ -2224,9 +2253,6 @@ class name java/time/chrono/IsoChronology method name epochSecond descriptor (IIIIIILjava/time/ZoneOffset;)J flags 1 -class name java/time/chrono/JapaneseEra -method name getDisplayName descriptor (Ljava/time/format/TextStyle;Ljava/util/Locale;)Ljava/lang/String; flags 1 - class name java/time/format/DateTimeFormatter header extends java/lang/Object flags 31 innerclass innerClass java/lang/invoke/MethodHandles$Lookup outerClass java/lang/invoke/MethodHandles innerClassName Lookup flags 19 @@ -3221,12 +3247,6 @@ innerclass innerClass java/lang/invoke/MethodHandles$Lookup outerClass java/lang/invoke/MethodHandles innerClassName Lookup flags 19 class name java/util/jar/Attributes$Name --field name EXTENSION_INSTALLATION descriptor Ljava/util/jar/Attributes$Name; --field name IMPLEMENTATION_VENDOR_ID descriptor Ljava/util/jar/Attributes$Name; --field name IMPLEMENTATION_URL descriptor Ljava/util/jar/Attributes$Name; -field name EXTENSION_INSTALLATION descriptor Ljava/util/jar/Attributes$Name; flags 19 deprecated true runtimeAnnotations @Ljava/lang/Deprecated; -field name IMPLEMENTATION_VENDOR_ID descriptor Ljava/util/jar/Attributes$Name; flags 19 deprecated true runtimeAnnotations @Ljava/lang/Deprecated; -field name IMPLEMENTATION_URL descriptor Ljava/util/jar/Attributes$Name; flags 19 deprecated true runtimeAnnotations @Ljava/lang/Deprecated; field name MULTI_RELEASE descriptor Ljava/util/jar/Attributes$Name; flags 19 class name java/util/jar/JarFile @@ -3381,6 +3401,9 @@ class name javax/crypto/ExemptionMechanism -method name finalize descriptor ()V +class name javax/crypto/SealedObject +header extends java/lang/Object implements java/io/Serializable flags 21 + class name javax/net/ssl/ExtendedSSLSession method name getStatusResponses descriptor ()Ljava/util/List; flags 1 signature ()Ljava/util/List<[B>; @@ -3388,12 +3411,6 @@ -method name getPeerCertificateChain descriptor ()[Ljavax/security/cert/X509Certificate; method name getPeerCertificateChain descriptor ()[Ljavax/security/cert/X509Certificate; thrownTypes javax/net/ssl/SSLPeerUnverifiedException flags 1 deprecated true runtimeAnnotations @Ljava/lang/Deprecated;(since="9") -class name javax/net/ssl/SSLEngine -method name getApplicationProtocol descriptor ()Ljava/lang/String; flags 1 -method name getHandshakeApplicationProtocol descriptor ()Ljava/lang/String; flags 1 -method name setHandshakeApplicationProtocolSelector descriptor (Ljava/util/function/BiFunction;)V flags 1 signature (Ljava/util/function/BiFunction<Ljavax/net/ssl/SSLEngine;Ljava/util/List<Ljava/lang/String;>;Ljava/lang/String;>;)V -method name getHandshakeApplicationProtocolSelector descriptor ()Ljava/util/function/BiFunction; flags 1 signature ()Ljava/util/function/BiFunction<Ljavax/net/ssl/SSLEngine;Ljava/util/List<Ljava/lang/String;>;Ljava/lang/String;>; - class name javax/net/ssl/SSLEngineResult header extends java/lang/Object flags 21 innerclass innerClass javax/net/ssl/SSLEngineResult$HandshakeStatus outerClass javax/net/ssl/SSLEngineResult innerClassName HandshakeStatus flags 4019 @@ -3409,19 +3426,11 @@ method name getEnableRetransmissions descriptor ()Z flags 1 method name setMaximumPacketSize descriptor (I)V flags 1 method name getMaximumPacketSize descriptor ()I flags 1 -method name getApplicationProtocols descriptor ()[Ljava/lang/String; flags 1 -method name setApplicationProtocols descriptor ([Ljava/lang/String;)V flags 1 class name javax/net/ssl/SSLSession -method name getPeerCertificateChain descriptor ()[Ljavax/security/cert/X509Certificate; method name getPeerCertificateChain descriptor ()[Ljavax/security/cert/X509Certificate; thrownTypes javax/net/ssl/SSLPeerUnverifiedException flags 401 deprecated true runtimeAnnotations @Ljava/lang/Deprecated;(since="9") -class name javax/net/ssl/SSLSocket -method name getApplicationProtocol descriptor ()Ljava/lang/String; flags 1 -method name getHandshakeApplicationProtocol descriptor ()Ljava/lang/String; flags 1 -method name setHandshakeApplicationProtocolSelector descriptor (Ljava/util/function/BiFunction;)V flags 1 signature (Ljava/util/function/BiFunction<Ljavax/net/ssl/SSLSocket;Ljava/util/List<Ljava/lang/String;>;Ljava/lang/String;>;)V -method name getHandshakeApplicationProtocolSelector descriptor ()Ljava/util/function/BiFunction; flags 1 signature ()Ljava/util/function/BiFunction<Ljavax/net/ssl/SSLSocket;Ljava/util/List<Ljava/lang/String;>;Ljava/lang/String;>; - class name javax/security/auth/Policy header extends java/lang/Object flags 421 deprecated true runtimeAnnotations @Ljava/lang/Deprecated;(since="1.4")
diff --git a/make/data/symbols/java.desktop-7.sym.txt b/make/data/symbols/java.desktop-7.sym.txt index 131531e..0163545 100644 --- a/make/data/symbols/java.desktop-7.sym.txt +++ b/make/data/symbols/java.desktop-7.sym.txt
@@ -1,5 +1,5 @@ # -# Copyright (c) 2015, 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2015, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -77,6 +77,9 @@ field name component descriptor Ljava/awt/Component; flags 1c field name tracker descriptor Ljava/awt/MediaTracker; flags 1c +class name javax/swing/JComboBox +-method name processKeyBinding descriptor (Ljavax/swing/KeyStroke;Ljava/awt/event/KeyEvent;IZ)Z + class name javax/swing/JComponent field name accessibleContext descriptor Ljavax/accessibility/AccessibleContext; flags 4 -method name hide descriptor ()V @@ -90,8 +93,12 @@ class name javax/swing/JDesktopPane -method name remove descriptor (Ljava/awt/Component;)V -class name javax/swing/JViewport --method name addNotify descriptor ()V +class name javax/swing/JList$AccessibleJList$AccessibleJListChild +method name getAccessibleAction descriptor ()Ljavax/accessibility/AccessibleAction; flags 1 + +class name javax/swing/plaf/basic/BasicRadioButtonUI +-method name installListeners descriptor (Ljavax/swing/AbstractButton;)V +-method name uninstallListeners descriptor (Ljavax/swing/AbstractButton;)V class name javax/swing/tree/DefaultMutableTreeNode -method name setParent descriptor (Ljavax/swing/tree/MutableTreeNode;)V
diff --git a/make/data/symbols/java.desktop-8.sym.txt b/make/data/symbols/java.desktop-8.sym.txt index 835cdde..3daa15e 100644 --- a/make/data/symbols/java.desktop-8.sym.txt +++ b/make/data/symbols/java.desktop-8.sym.txt
@@ -1,5 +1,5 @@ # -# Copyright (c) 2015, 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2015, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -13524,6 +13524,7 @@ method name createDefaultKeySelectionManager descriptor ()Ljavax/swing/JComboBox$KeySelectionManager; flags 4 method name paramString descriptor ()Ljava/lang/String; flags 4 method name getAccessibleContext descriptor ()Ljavax/accessibility/AccessibleContext; flags 1 +method name processKeyBinding descriptor (Ljavax/swing/KeyStroke;Ljava/awt/event/KeyEvent;IZ)Z flags 4 class name javax/swing/JComboBox$AccessibleJComboBox header extends javax/swing/JComponent$AccessibleJComponent implements javax/accessibility/AccessibleAction,javax/accessibility/AccessibleSelection flags 21 @@ -14604,7 +14605,6 @@ method name getLocale descriptor ()Ljava/util/Locale; flags 1 method name addPropertyChangeListener descriptor (Ljava/beans/PropertyChangeListener;)V flags 1 method name removePropertyChangeListener descriptor (Ljava/beans/PropertyChangeListener;)V flags 1 -method name getAccessibleAction descriptor ()Ljavax/accessibility/AccessibleAction; flags 1 method name getAccessibleComponent descriptor ()Ljavax/accessibility/AccessibleComponent; flags 1 method name getAccessibleSelection descriptor ()Ljavax/accessibility/AccessibleSelection; flags 1 method name getAccessibleText descriptor ()Ljavax/accessibility/AccessibleText; flags 1 @@ -16720,7 +16720,6 @@ method name getUIClassID descriptor ()Ljava/lang/String; flags 1 method name addImpl descriptor (Ljava/awt/Component;Ljava/lang/Object;I)V flags 4 method name remove descriptor (Ljava/awt/Component;)V flags 1 -method name addNotify descriptor ()V flags 1 method name scrollRectToVisible descriptor (Ljava/awt/Rectangle;)V flags 1 method name setBorder descriptor (Ljavax/swing/border/Border;)V flags 11 method name getInsets descriptor ()Ljava/awt/Insets; flags 11 @@ -20281,6 +20280,8 @@ method name paint descriptor (Ljava/awt/Graphics;Ljavax/swing/JComponent;)V flags 21 method name paintFocus descriptor (Ljava/awt/Graphics;Ljava/awt/Rectangle;Ljava/awt/Dimension;)V flags 4 method name getPreferredSize descriptor (Ljavax/swing/JComponent;)Ljava/awt/Dimension; flags 1 +method name installListeners descriptor (Ljavax/swing/AbstractButton;)V flags 4 +method name uninstallListeners descriptor (Ljavax/swing/AbstractButton;)V flags 4 class name javax/swing/plaf/basic/BasicRootPaneUI header extends javax/swing/plaf/RootPaneUI implements java/beans/PropertyChangeListener flags 21 classAnnotations @Ljdk/Profile+Annotation;(value=I4)
diff --git a/make/data/symbols/java.desktop-9.sym.txt b/make/data/symbols/java.desktop-9.sym.txt index 421eb34..cf0ab34 100644 --- a/make/data/symbols/java.desktop-9.sym.txt +++ b/make/data/symbols/java.desktop-9.sym.txt
@@ -1,5 +1,5 @@ # -# Copyright (c) 2015, 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2015, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -2524,7 +2524,6 @@ method name setAction descriptor (Ljavax/swing/Action;)V flags 1 runtimeAnnotations @Ljava/beans/BeanProperty;(visualUpdate=Ztrue,description="the\u005C;u0020;Action\u005C;u0020;instance\u005C;u0020;connected\u005C;u0020;with\u005C;u0020;this\u005C;u0020;ActionEvent\u005C;u0020;source") method name getSelectedObjects descriptor ()[Ljava/lang/Object; flags 1 runtimeAnnotations @Ljava/beans/BeanProperty;(bound=Zfalse) method name setEnabled descriptor (Z)V flags 1 runtimeAnnotations @Ljava/beans/BeanProperty;(description="The\u005C;u0020;enabled\u005C;u0020;state\u005C;u0020;of\u005C;u0020;the\u005C;u0020;component.",preferred=Ztrue) -method name processKeyBinding descriptor (Ljavax/swing/KeyStroke;Ljava/awt/event/KeyEvent;IZ)Z flags 4 method name setKeySelectionManager descriptor (Ljavax/swing/JComboBox$KeySelectionManager;)V flags 1 runtimeAnnotations @Ljava/beans/BeanProperty;(expert=Ztrue,bound=Zfalse,description="The\u005C;u0020;objects\u005C;u0020;that\u005C;u0020;changes\u005C;u0020;the\u005C;u0020;selection\u005C;u0020;when\u005C;u0020;a\u005C;u0020;key\u005C;u0020;is\u005C;u0020;pressed.") method name getItemCount descriptor ()I flags 1 runtimeAnnotations @Ljava/beans/BeanProperty;(bound=Zfalse) method name getAccessibleContext descriptor ()Ljavax/accessibility/AccessibleContext; flags 1 runtimeAnnotations @Ljava/beans/BeanProperty;(bound=Zfalse) @@ -3039,6 +3038,7 @@ header extends javax/accessibility/AccessibleContext implements javax/accessibility/Accessible,javax/accessibility/AccessibleComponent,javax/accessibility/AccessibleAction flags 21 innerclass innerClass javax/swing/JList$AccessibleJList outerClass javax/swing/JList innerClassName AccessibleJList flags 4 innerclass innerClass javax/swing/JList$AccessibleJList$AccessibleJListChild outerClass javax/swing/JList$AccessibleJList innerClassName AccessibleJListChild flags 4 +method name getAccessibleAction descriptor ()Ljavax/accessibility/AccessibleAction; flags 1 method name doAccessibleAction descriptor (I)Z flags 1 method name getAccessibleActionDescription descriptor (I)Ljava/lang/String; flags 1 method name getAccessibleActionCount descriptor ()I flags 1 @@ -3907,7 +3907,6 @@ innerclass innerClass javax/swing/JViewport$ViewListener outerClass javax/swing/JViewport innerClassName ViewListener flags 4 innerclass innerClass java/lang/invoke/MethodHandles$Lookup outerClass java/lang/invoke/MethodHandles innerClassName Lookup flags 19 -method name setUI descriptor (Ljavax/swing/plaf/ViewportUI;)V --method name addNotify descriptor ()V -method name getInsets descriptor (Ljava/awt/Insets;)Ljava/awt/Insets; -method name setScrollMode descriptor (I)V method name setUI descriptor (Ljavax/swing/plaf/ViewportUI;)V flags 1 runtimeAnnotations @Ljava/beans/BeanProperty;(hidden=Ztrue,visualUpdate=Ztrue,description="The\u005C;u0020;UI\u005C;u0020;object\u005C;u0020;that\u005C;u0020;implements\u005C;u0020;the\u005C;u0020;Component's\u005C;u0020;LookAndFeel.") @@ -4402,8 +4401,6 @@ class name javax/swing/plaf/basic/BasicRadioButtonUI header extends javax/swing/plaf/basic/BasicToggleButtonUI flags 21 innerclass innerClass java/lang/invoke/MethodHandles$Lookup outerClass java/lang/invoke/MethodHandles innerClassName Lookup flags 19 -method name installListeners descriptor (Ljavax/swing/AbstractButton;)V flags 4 -method name uninstallListeners descriptor (Ljavax/swing/AbstractButton;)V flags 4 class name javax/swing/plaf/basic/BasicScrollBarUI header extends javax/swing/plaf/ScrollBarUI implements java/awt/LayoutManager,javax/swing/SwingConstants flags 21
diff --git a/make/data/symbols/symbols b/make/data/symbols/symbols index ca0a74f..09f0c74 100644 --- a/make/data/symbols/symbols +++ b/make/data/symbols/symbols
@@ -27,7 +27,7 @@ # ########################################################## # #command used to generate this file: -#build.tools.symbolgenerator.CreateSymbols build-description-incremental symbols include.list +#build.tools.symbolgenerator.CreateSymbols build-description-incremental-file symbols include.list 8 jdk8-updated.classes <none> --normalize-method-flags # generate platforms 6:7:8:9:A platform version 8 files java.activation-8.sym.txt:java.base-8.sym.txt:java.compiler-8.sym.txt:java.corba-8.sym.txt:java.datatransfer-8.sym.txt:java.desktop-8.sym.txt:java.instrument-8.sym.txt:java.logging-8.sym.txt:java.management-8.sym.txt:java.management.rmi-8.sym.txt:java.naming-8.sym.txt:java.prefs-8.sym.txt:java.rmi-8.sym.txt:java.scripting-8.sym.txt:java.security.jgss-8.sym.txt:java.security.sasl-8.sym.txt:java.sql-8.sym.txt:java.sql.rowset-8.sym.txt:java.transaction-8.sym.txt:java.xml-8.sym.txt:java.xml.bind-8.sym.txt:java.xml.crypto-8.sym.txt:java.xml.ws-8.sym.txt:java.xml.ws.annotation-8.sym.txt:jdk.httpserver-8.sym.txt:jdk.management-8.sym.txt:jdk.scripting.nashorn-8.sym.txt:jdk.sctp-8.sym.txt:jdk.security.auth-8.sym.txt:jdk.security.jgss-8.sym.txt
diff --git a/make/data/tzdata/VERSION b/make/data/tzdata/VERSION index e3fa922..71632a7 100644 --- a/make/data/tzdata/VERSION +++ b/make/data/tzdata/VERSION
@@ -21,4 +21,4 @@ # or visit www.oracle.com if you need additional information or have any # questions. # -tzdata2018g +tzdata2021a
diff --git a/make/data/tzdata/africa b/make/data/tzdata/africa index e2ffac2..5de2e5f 100644 --- a/make/data/tzdata/africa +++ b/make/data/tzdata/africa
@@ -87,7 +87,7 @@ # Corrections are welcome. # Algeria -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Algeria 1916 only - Jun 14 23:00s 1:00 S Rule Algeria 1916 1919 - Oct Sun>=1 23:00s 0 - Rule Algeria 1917 only - Mar 24 23:00s 1:00 S @@ -110,10 +110,9 @@ Rule Algeria 1978 only - Sep 22 3:00 0 - Rule Algeria 1980 only - Apr 25 0:00 1:00 S Rule Algeria 1980 only - Oct 31 2:00 0 - -# Shanks & Pottenger give 0:09:20 for Paris Mean Time; go with Howse's -# more precise 0:09:21. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Africa/Algiers 0:12:12 - LMT 1891 Mar 15 0:01 +# See Europe/Paris for PMT-related transitions. +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Africa/Algiers 0:12:12 - LMT 1891 Mar 16 0:09:21 - PMT 1911 Mar 11 # Paris Mean Time 0:00 Algeria WE%sT 1940 Feb 25 2:00 1:00 Algeria CE%sT 1946 Oct 7 @@ -147,7 +146,7 @@ # For now, ignore that and follow the 1911-05-26 Portuguese decree # (see Europe/Lisbon). # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Atlantic/Cape_Verde -1:34:04 - LMT 1912 Jan 01 2:00u # Praia -2:00 - -02 1942 Sep -2:00 1:00 -01 1945 Oct 15 @@ -158,7 +157,7 @@ # See Africa/Lagos. # Chad -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Africa/Ndjamena 1:00:12 - LMT 1912 # N'Djamena 1:00 - WAT 1979 Oct 14 1:00 1:00 WAST 1980 Mar 8 @@ -174,7 +173,7 @@ # See Africa/Lagos. # Côte d'Ivoire / Ivory Coast -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Africa/Abidjan -0:16:08 - LMT 1912 0:00 - GMT Link Africa/Abidjan Africa/Bamako # Mali @@ -199,7 +198,7 @@ # Egypt was mean noon at the Great Pyramid, 2:04:30.5, but apparently this # did not apply to Cairo, Alexandria, or Port Said. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Egypt 1940 only - Jul 15 0:00 1:00 S Rule Egypt 1940 only - Oct 1 0:00 0 - Rule Egypt 1941 only - Apr 15 0:00 1:00 S @@ -379,7 +378,7 @@ Rule Egypt 2014 only - Jul 31 24:00 1:00 S Rule Egypt 2014 only - Sep lastThu 24:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Africa/Cairo 2:05:09 - LMT 1900 Oct 2:00 Egypt EE%sT @@ -387,6 +386,11 @@ # See Africa/Lagos. # Eritrea +# See Africa/Nairobi. + +# Eswatini (formerly Swaziland) +# See Africa/Johannesburg. + # Ethiopia # See Africa/Nairobi. # @@ -405,36 +409,87 @@ # Ghana -# From Paul Eggert (2018-01-30): -# Whitman says DST was observed from 1931 to "the present"; -# Shanks & Pottenger say 1936 to 1942 with 20 minutes of DST, -# with transitions on 09-01 and 12-31 at 00:00. -# Page 33 of Parish GCB, Colonial Reports - Annual. No. 1066. Gold -# Coast. Report for 1919. (March 1921), OCLC 784024077 -# http://libsysdigi.library.illinois.edu/ilharvest/africana/books2011-05/5530214/5530214_1919/5530214_1919_opt.pdf -# lists the Determination of the Time Ordinance, 1919, No. 18, -# "to advance the time observed locally by the space of twenty minutes -# during the last four months of each year; the object in view being -# to extend during those months the period of daylight-time available -# for evening recreation after office hours." -# Vanessa Ogle, The Global Transformation of Time, 1870-1950 (2015), p 33, -# writes "In 1919, the Gold Coast (Ghana as of 1957) made Greenwich -# time its legal time and simultaneously legalized a summer time of -# UTC - 00:20 minutes from March to October."; a footnote lists -# the ordinance as being dated 1919-11-24. -# The Crown Colonist, Volume 12 (1942), p 176, says "the Government -# intend advancing Gold Coast time half an hour ahead of G.M.T. -# The actual date of the alteration has not yet been announced." -# These sources are incomplete and contradictory. Possibly what is -# now Ghana observed different DST regimes in different years. For -# lack of better info, use Shanks except treat the minus sign as a -# typo, and assume DST started in 1920 not 1936. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -Rule Ghana 1920 1942 - Sep 1 0:00 0:20 - -Rule Ghana 1920 1942 - Dec 31 0:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Africa/Accra -0:00:52 - LMT 1918 - 0:00 Ghana GMT/+0020 +# From P Chan (2020-11-20): +# Interpretation Amendment Ordinance, 1915 (No.24 of 1915) [1915-11-02] +# Ordinances of the Gold Coast, Ashanti, Northern Territories 1915, p 69-71 +# https://books.google.com/books?id=ErA-AQAAIAAJ&pg=PA70 +# This Ordinance added "'Time' shall mean Greenwich Mean Time" to the +# Interpretation Ordinance, 1876. +# +# Determination of the Time Ordinance, 1919 (No. 18 of 1919) [1919-11-24] +# Ordinances of the Gold Coast, Ashanti, Northern Territories 1919, p 75-76 +# https://books.google.com/books?id=MbA-AQAAIAAJ&pg=PA75 +# This Ordinance removed the previous definition of time and introduced DST. +# +# Time Determination Ordinance (Cap. 214) +# The Laws of the Gold Coast (including Togoland Under British Mandate) +# Vol. II (1937), p 2328 +# https://books.google.com/books?id=Z7M-AQAAIAAJ&pg=PA2328 +# Revised edition of the 1919 Ordinance. +# +# Time Determination (Amendment) Ordinance, 1940 (No. 9 of 1940) [1940-04-06] +# Annual Volume of the Laws of the Gold Coast: +# Containing All Legislation Enacted During Year 1940, p 22 +# https://books.google.com/books?id=1ao-AQAAIAAJ&pg=PA22 +# This Ordinance changed the forward transition from September to May. +# +# Defence (Time Determination Ordinance Amendment) Regulations, 1942 +# (Regulations No. 6 of 1942) [1942-01-31, commenced on 1942-02-08] +# Annual Volume of the Laws of the Gold Coast: +# Containing All Legislation Enacted During Year 1942, p 48 +# https://books.google.com/books?id=Das-AQAAIAAJ&pg=PA48 +# These regulations advanced the [standard] time by thirty minutes. +# +# Defence (Time Determination Ordinance Amendment (No.2)) Regulations, +# 1942 (Regulations No. 28 of 1942) [1942-04-25] +# Annual Volume of the Laws of the Gold Coast: +# Containing All Legislation Enacted During Year 1942, p 87 +# https://books.google.com/books?id=Das-AQAAIAAJ&pg=PA87 +# These regulations abolished DST and changed the time to GMT+0:30. +# +# Defence (Revocation) (No.4) Regulations, 1945 (Regulations No. 45 of +# 1945) [1945-10-24, commenced on 1946-01-06] +# Annual Volume of the Laws of the Gold Coast: +# Containing All Legislation Enacted During Year 1945, p 256 +# https://books.google.com/books?id=9as-AQAAIAAJ&pg=PA256 +# These regulations revoked the previous two sets of Regulations. +# +# Time Determination (Amendment) Ordinance, 1945 (No. 18 of 1945) [1946-01-06] +# Annual Volume of the Laws of the Gold Coast: +# Containing All Legislation Enacted During Year 1945, p 69 +# https://books.google.com/books?id=9as-AQAAIAAJ&pg=PA69 +# This Ordinance abolished DST. +# +# Time Determination (Amendment) Ordinance, 1950 (No. 26 of 1950) [1950-07-22] +# Annual Volume of the Laws of the Gold Coast: +# Containing All Legislation Enacted During Year 1950, p 35 +# https://books.google.com/books?id=e60-AQAAIAAJ&pg=PA35 +# This Ordinance restored DST but with thirty minutes offset. +# +# Time Determination Ordinance (Cap. 264) +# The Laws of the Gold Coast, Vol. V (1954), p 380 +# https://books.google.com/books?id=Mqc-AQAAIAAJ&pg=PA380 +# Revised edition of the Time Determination Ordinance. +# +# Time Determination (Amendment) Ordinance, 1956 (No. 21 of 1956) [1956-08-29] +# Annual Volume of the Ordinances of the Gold Coast Enacted During the +# Year 1956, p 83 +# https://books.google.com/books?id=VLE-AQAAIAAJ&pg=PA83 +# This Ordinance abolished DST. + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule Ghana 1919 only - Nov 24 0:00 0:20 +0020 +Rule Ghana 1920 1942 - Jan 1 2:00 0 GMT +Rule Ghana 1920 1939 - Sep 1 2:00 0:20 +0020 +Rule Ghana 1940 1941 - May 1 2:00 0:20 +0020 +Rule Ghana 1950 1955 - Sep 1 2:00 0:30 +0030 +Rule Ghana 1951 1956 - Jan 1 2:00 0 GMT + +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Africa/Accra -0:00:52 - LMT 1915 Nov 2 + 0:00 Ghana %s 1942 Feb 8 + 0:30 - +0030 1946 Jan 6 + 0:00 Ghana %s # Guinea # See Africa/Abidjan. @@ -446,17 +501,60 @@ # evidently confusing the date of the Portuguese decree # (see Europe/Lisbon) with the date that it took effect. # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Africa/Bissau -1:02:20 - LMT 1912 Jan 1 1:00u -1:00 - -01 1975 0:00 - GMT # Kenya -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Africa/Nairobi 2:27:16 - LMT 1928 Jul - 3:00 - EAT 1930 - 2:30 - +0230 1940 - 2:45 - +0245 1960 + +# From P Chan (2020-10-24): +# +# The standard time of GMT+2:30 was adopted in the East Africa Protectorate.... +# [The Official Gazette, 1908-05-01, p 274] +# https://books.google.com/books?id=e-cAC-sjPSEC&pg=PA274 +# +# At midnight on 30 June 1928 the clocks throughout Kenya was put forward +# half an hour by the Alteration of Time Ordinance, 1928. +# https://gazettes.africa/archive/ke/1928/ke-government-gazette-dated-1928-05-11-no-28.pdf +# [Ordinance No. 11 of 1928, The Offical Gazette, 1928-06-26, p 813] +# https://books.google.com/books?id=2S0S6os32ZUC&pg=PA813 +# +# The 1928 ordinance was repealed by the Alteration of Time (repeal) Ordinance, +# 1929 and the time was restored to GMT+2:30 at midnight on 4 January 1930. +# [Ordinance No. 97 of 1929, The Official Gazette, 1929-12-31, p 2701] +# https://books.google.com/books?id=_g18jIZQlwwC&pg=PA2701 +# +# The Alteration of Time Ordinance, 1936 changed the time to GMT+2:45 +# and repealed the previous ordinance at midnight on 31 December 1936. +# [The Official Gazette, 1936-07-21, p 705] +# https://books.google.com/books?id=K7j41z0aC5wC&pg=PA705 +# +# The Defence (Amendment of Laws No. 120) Regulations changed the time +# to GMT+3 at midnight on 31 July 1942. +# [Kenya Official Gazette Supplement No. 32, 1942-07-21, p 331] +# https://books.google.com/books?hl=zh-TW&id=c_E-AQAAIAAJ&pg=PA331 +# The provision of the 1936 ordinance was not repealed and was later +# incorporated in the Interpretation and General Clauses Ordinance in 1948. +# Although it was overridden by the 1942 regulations. +# [The Laws of Kenya in force on 1948-09-21, Title I, Chapter 1, 31] +# https://dds.crl.edu/item/217517 (p.101) +# In 1950 the Interpretation and General Clauses Ordinance was amended to adopt +# GMT+3 permanently as the 1942 regulations were due to expire on 10 December. +# https://books.google.com/books?id=jvR8mUDAwR0C&pg=PA787 +# [Ordinance No. 44 of 1950, Kenya Ordinances 1950, Vol. XXIX, p 294] +# https://books.google.com/books?id=-_dQAQAAMAAJ&pg=PA294 + +# From Paul Eggert (2020-10-24): +# The 1908-05-01 announcement does not give an effective date, +# so just say "1908 May". + +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Africa/Nairobi 2:27:16 - LMT 1908 May + 2:30 - +0230 1928 Jun 30 24:00 + 3:00 - EAT 1930 Jan 4 24:00 + 2:30 - +0230 1936 Dec 31 24:00 + 2:45 - +0245 1942 Jul 31 24:00 3:00 - EAT Link Africa/Nairobi Africa/Addis_Ababa # Ethiopia Link Africa/Nairobi Africa/Asmara # Eritrea @@ -487,7 +585,7 @@ # Use the abbreviation "MMT" before 1972, as the more-accurate numeric # abbreviation "-004430" would be one byte over the POSIX limit. # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Africa/Monrovia -0:43:08 - LMT 1882 -0:43:08 - MMT 1919 Mar # Monrovia Mean Time -0:44:30 - MMT 1972 Jan 7 # approximately MMT @@ -519,7 +617,7 @@ # From Paul Eggert (2013-10-25): # For now, assume they're reverting to the pre-2012 rules of permanent UT +02. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Libya 1951 only - Oct 14 2:00 1:00 S Rule Libya 1952 only - Jan 1 0:00 0 - Rule Libya 1953 only - Oct 9 2:00 1:00 S @@ -537,7 +635,7 @@ Rule Libya 1997 only - Oct 4 0:00 0 - Rule Libya 2013 only - Mar lastFri 1:00 1:00 S Rule Libya 2013 only - Oct lastFri 2:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Africa/Tripoli 0:52:44 - LMT 1920 1:00 Libya CE%sT 1959 2:00 - EET 1982 @@ -642,12 +740,12 @@ # "The trial ended on March 29, 2009, when the clocks moved back by one hour # at 2am (or 02:00) local time..." -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Mauritius 1982 only - Oct 10 0:00 1:00 - Rule Mauritius 1983 only - Mar 21 0:00 0 - Rule Mauritius 2008 only - Oct lastSun 2:00 1:00 - Rule Mauritius 2009 only - Mar lastSun 2:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Indian/Mauritius 3:50:00 - LMT 1907 # Port Louis 4:00 Mauritius +04/+05 # Agalega Is, Rodriguez @@ -870,10 +968,68 @@ # From Mohamed Essedik Najd (2018-10-26): # Today, a Moroccan government council approved the perpetual addition # of 60 minutes to the regular Moroccan timezone. -# From Brian Inglis (2018-10-26): -# http://www.maroc.ma/fr/actualites/le-conseil-de-gouvernement-adopte-un-projet-de-decret-relatif-lheure-legale-stipulant-le +# From Matt Johnson (2018-10-28): +# http://www.sgg.gov.ma/Portals/1/BO/2018/BO_6720-bis_Ar.pdf +# +# From Maamar Abdelkader (2018-11-01): +# We usually move clocks back the previous week end and come back to the +1 +# the week end after.... The government does not announce yet the decision +# about this temporary change. But it s 99% sure that it will be the case, +# as in previous years. An unofficial survey was done these days, showing +# that 64% of asked people are ok for moving from +1 to +0 during Ramadan. +# https://leconomiste.com/article/1035870-enquete-l-economiste-sunergia-64-des-marocains-plebiscitent-le-gmt-pendant-ramadan -# RULE NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# From Naoufal Semlali (2019-04-16): +# Morocco will be on GMT starting from Sunday, May 5th 2019 at 3am. +# The switch to GMT+1 will occur on Sunday, June 9th 2019 at 2am.... +# http://fr.le360.ma/societe/voici-la-date-du-retour-a-lheure-legale-au-maroc-188222 + +# From Semlali Naoufal (2020-04-14): +# Following the announcement by the Moroccan government, the switch to +# GMT time will take place on Sunday, April 19, 2020 from 3 a.m. and +# the return to GMT+1 time will take place on Sunday, May 31, 2020 at 2 a.m.... +# https://maroc-diplomatique.net/maroc-le-retour-a-lheure-gmt-est-prevu-dimanche-prochain/ +# http://aujourdhui.ma/actualite/gmt1-retour-a-lheure-normale-dimanche-prochain-1 +# +# From Milamber (2020-05-31) +# In Morocco (where I live), the end of Ramadan (Arabic month) is followed by +# the Eid al-Fitr, and concretely it's 1 or 2 day offs for the people (with +# traditional visiting of family, big lunches/dinners, etc.). So for this +# year the astronomical calculations don't include the following 2 days off in +# the calc. These 2 days fall in a Sunday/Monday, so it's not acceptable by +# people to have a time shift during these 2 days off. Perhaps you can modify +# the (predicted) rules for next years: if the end of Ramadan is a (probable) +# Friday or Saturday (and so the 2 days off are on a weekend), the next time +# shift will be the next weekend. +# +# From Paul Eggert (2020-05-31): +# For now, guess that in the future Morocco will fall back at 03:00 +# the last Sunday before Ramadan, and spring forward at 02:00 the +# first Sunday after two days after Ramadan. To implement this, +# transition dates and times for 2019 through 2087 were determined by +# running the following program under GNU Emacs 26.3. (This algorithm +# also produces the correct transition dates for 2016 through 2018, +# though the times differ due to Morocco's time zone change in 2018.) +# (let ((islamic-year 1440)) +# (require 'cal-islam) +# (while (< islamic-year 1511) +# (let ((a (calendar-islamic-to-absolute (list 9 1 islamic-year))) +# (b (+ 2 (calendar-islamic-to-absolute (list 10 1 islamic-year)))) +# (sunday 0)) +# (while (/= sunday (mod (setq a (1- a)) 7))) +# (while (/= sunday (mod b 7)) +# (setq b (1+ b))) +# (setq a (calendar-gregorian-from-absolute a)) +# (setq b (calendar-gregorian-from-absolute b)) +# (insert +# (format +# (concat "Rule\tMorocco\t%d\tonly\t-\t%s\t%2d\t 3:00\t-1:00\t-\n" +# "Rule\tMorocco\t%d\tonly\t-\t%s\t%2d\t 2:00\t0\t-\n") +# (car (cdr (cdr a))) (calendar-month-name (car a) t) (car (cdr a)) +# (car (cdr (cdr b))) (calendar-month-name (car b) t) (car (cdr b))))) +# (setq islamic-year (+ 1 islamic-year)))) + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Morocco 1939 only - Sep 12 0:00 1:00 - Rule Morocco 1939 only - Nov 19 0:00 0 - Rule Morocco 1940 only - Feb 25 0:00 1:00 - @@ -915,13 +1071,159 @@ Rule Morocco 2017 only - Jul 2 2:00 1:00 - Rule Morocco 2018 only - May 13 3:00 0 - Rule Morocco 2018 only - Jun 17 2:00 1:00 - +Rule Morocco 2019 only - May 5 3:00 -1:00 - +Rule Morocco 2019 only - Jun 9 2:00 0 - +Rule Morocco 2020 only - Apr 19 3:00 -1:00 - +Rule Morocco 2020 only - May 31 2:00 0 - +Rule Morocco 2021 only - Apr 11 3:00 -1:00 - +Rule Morocco 2021 only - May 16 2:00 0 - +Rule Morocco 2022 only - Mar 27 3:00 -1:00 - +Rule Morocco 2022 only - May 8 2:00 0 - +Rule Morocco 2023 only - Mar 19 3:00 -1:00 - +Rule Morocco 2023 only - Apr 30 2:00 0 - +Rule Morocco 2024 only - Mar 10 3:00 -1:00 - +Rule Morocco 2024 only - Apr 14 2:00 0 - +Rule Morocco 2025 only - Feb 23 3:00 -1:00 - +Rule Morocco 2025 only - Apr 6 2:00 0 - +Rule Morocco 2026 only - Feb 15 3:00 -1:00 - +Rule Morocco 2026 only - Mar 22 2:00 0 - +Rule Morocco 2027 only - Feb 7 3:00 -1:00 - +Rule Morocco 2027 only - Mar 14 2:00 0 - +Rule Morocco 2028 only - Jan 23 3:00 -1:00 - +Rule Morocco 2028 only - Mar 5 2:00 0 - +Rule Morocco 2029 only - Jan 14 3:00 -1:00 - +Rule Morocco 2029 only - Feb 18 2:00 0 - +Rule Morocco 2029 only - Dec 30 3:00 -1:00 - +Rule Morocco 2030 only - Feb 10 2:00 0 - +Rule Morocco 2030 only - Dec 22 3:00 -1:00 - +Rule Morocco 2031 only - Feb 2 2:00 0 - +Rule Morocco 2031 only - Dec 14 3:00 -1:00 - +Rule Morocco 2032 only - Jan 18 2:00 0 - +Rule Morocco 2032 only - Nov 28 3:00 -1:00 - +Rule Morocco 2033 only - Jan 9 2:00 0 - +Rule Morocco 2033 only - Nov 20 3:00 -1:00 - +Rule Morocco 2033 only - Dec 25 2:00 0 - +Rule Morocco 2034 only - Nov 5 3:00 -1:00 - +Rule Morocco 2034 only - Dec 17 2:00 0 - +Rule Morocco 2035 only - Oct 28 3:00 -1:00 - +Rule Morocco 2035 only - Dec 9 2:00 0 - +Rule Morocco 2036 only - Oct 19 3:00 -1:00 - +Rule Morocco 2036 only - Nov 23 2:00 0 - +Rule Morocco 2037 only - Oct 4 3:00 -1:00 - +Rule Morocco 2037 only - Nov 15 2:00 0 - +Rule Morocco 2038 only - Sep 26 3:00 -1:00 - +Rule Morocco 2038 only - Nov 7 2:00 0 - +Rule Morocco 2039 only - Sep 18 3:00 -1:00 - +Rule Morocco 2039 only - Oct 23 2:00 0 - +Rule Morocco 2040 only - Sep 2 3:00 -1:00 - +Rule Morocco 2040 only - Oct 14 2:00 0 - +Rule Morocco 2041 only - Aug 25 3:00 -1:00 - +Rule Morocco 2041 only - Sep 29 2:00 0 - +Rule Morocco 2042 only - Aug 10 3:00 -1:00 - +Rule Morocco 2042 only - Sep 21 2:00 0 - +Rule Morocco 2043 only - Aug 2 3:00 -1:00 - +Rule Morocco 2043 only - Sep 13 2:00 0 - +Rule Morocco 2044 only - Jul 24 3:00 -1:00 - +Rule Morocco 2044 only - Aug 28 2:00 0 - +Rule Morocco 2045 only - Jul 9 3:00 -1:00 - +Rule Morocco 2045 only - Aug 20 2:00 0 - +Rule Morocco 2046 only - Jul 1 3:00 -1:00 - +Rule Morocco 2046 only - Aug 12 2:00 0 - +Rule Morocco 2047 only - Jun 23 3:00 -1:00 - +Rule Morocco 2047 only - Jul 28 2:00 0 - +Rule Morocco 2048 only - Jun 7 3:00 -1:00 - +Rule Morocco 2048 only - Jul 19 2:00 0 - +Rule Morocco 2049 only - May 30 3:00 -1:00 - +Rule Morocco 2049 only - Jul 4 2:00 0 - +Rule Morocco 2050 only - May 15 3:00 -1:00 - +Rule Morocco 2050 only - Jun 26 2:00 0 - +Rule Morocco 2051 only - May 7 3:00 -1:00 - +Rule Morocco 2051 only - Jun 18 2:00 0 - +Rule Morocco 2052 only - Apr 28 3:00 -1:00 - +Rule Morocco 2052 only - Jun 2 2:00 0 - +Rule Morocco 2053 only - Apr 13 3:00 -1:00 - +Rule Morocco 2053 only - May 25 2:00 0 - +Rule Morocco 2054 only - Apr 5 3:00 -1:00 - +Rule Morocco 2054 only - May 17 2:00 0 - +Rule Morocco 2055 only - Mar 28 3:00 -1:00 - +Rule Morocco 2055 only - May 2 2:00 0 - +Rule Morocco 2056 only - Mar 12 3:00 -1:00 - +Rule Morocco 2056 only - Apr 23 2:00 0 - +Rule Morocco 2057 only - Mar 4 3:00 -1:00 - +Rule Morocco 2057 only - Apr 8 2:00 0 - +Rule Morocco 2058 only - Feb 17 3:00 -1:00 - +Rule Morocco 2058 only - Mar 31 2:00 0 - +Rule Morocco 2059 only - Feb 9 3:00 -1:00 - +Rule Morocco 2059 only - Mar 23 2:00 0 - +Rule Morocco 2060 only - Feb 1 3:00 -1:00 - +Rule Morocco 2060 only - Mar 7 2:00 0 - +Rule Morocco 2061 only - Jan 16 3:00 -1:00 - +Rule Morocco 2061 only - Feb 27 2:00 0 - +Rule Morocco 2062 only - Jan 8 3:00 -1:00 - +Rule Morocco 2062 only - Feb 19 2:00 0 - +Rule Morocco 2062 only - Dec 31 3:00 -1:00 - +Rule Morocco 2063 only - Feb 4 2:00 0 - +Rule Morocco 2063 only - Dec 16 3:00 -1:00 - +Rule Morocco 2064 only - Jan 27 2:00 0 - +Rule Morocco 2064 only - Dec 7 3:00 -1:00 - +Rule Morocco 2065 only - Jan 11 2:00 0 - +Rule Morocco 2065 only - Nov 22 3:00 -1:00 - +Rule Morocco 2066 only - Jan 3 2:00 0 - +Rule Morocco 2066 only - Nov 14 3:00 -1:00 - +Rule Morocco 2066 only - Dec 26 2:00 0 - +Rule Morocco 2067 only - Nov 6 3:00 -1:00 - +Rule Morocco 2067 only - Dec 11 2:00 0 - +Rule Morocco 2068 only - Oct 21 3:00 -1:00 - +Rule Morocco 2068 only - Dec 2 2:00 0 - +Rule Morocco 2069 only - Oct 13 3:00 -1:00 - +Rule Morocco 2069 only - Nov 24 2:00 0 - +Rule Morocco 2070 only - Oct 5 3:00 -1:00 - +Rule Morocco 2070 only - Nov 9 2:00 0 - +Rule Morocco 2071 only - Sep 20 3:00 -1:00 - +Rule Morocco 2071 only - Nov 1 2:00 0 - +Rule Morocco 2072 only - Sep 11 3:00 -1:00 - +Rule Morocco 2072 only - Oct 16 2:00 0 - +Rule Morocco 2073 only - Aug 27 3:00 -1:00 - +Rule Morocco 2073 only - Oct 8 2:00 0 - +Rule Morocco 2074 only - Aug 19 3:00 -1:00 - +Rule Morocco 2074 only - Sep 30 2:00 0 - +Rule Morocco 2075 only - Aug 11 3:00 -1:00 - +Rule Morocco 2075 only - Sep 15 2:00 0 - +Rule Morocco 2076 only - Jul 26 3:00 -1:00 - +Rule Morocco 2076 only - Sep 6 2:00 0 - +Rule Morocco 2077 only - Jul 18 3:00 -1:00 - +Rule Morocco 2077 only - Aug 29 2:00 0 - +Rule Morocco 2078 only - Jul 10 3:00 -1:00 - +Rule Morocco 2078 only - Aug 14 2:00 0 - +Rule Morocco 2079 only - Jun 25 3:00 -1:00 - +Rule Morocco 2079 only - Aug 6 2:00 0 - +Rule Morocco 2080 only - Jun 16 3:00 -1:00 - +Rule Morocco 2080 only - Jul 21 2:00 0 - +Rule Morocco 2081 only - Jun 1 3:00 -1:00 - +Rule Morocco 2081 only - Jul 13 2:00 0 - +Rule Morocco 2082 only - May 24 3:00 -1:00 - +Rule Morocco 2082 only - Jul 5 2:00 0 - +Rule Morocco 2083 only - May 16 3:00 -1:00 - +Rule Morocco 2083 only - Jun 20 2:00 0 - +Rule Morocco 2084 only - Apr 30 3:00 -1:00 - +Rule Morocco 2084 only - Jun 11 2:00 0 - +Rule Morocco 2085 only - Apr 22 3:00 -1:00 - +Rule Morocco 2085 only - Jun 3 2:00 0 - +Rule Morocco 2086 only - Apr 14 3:00 -1:00 - +Rule Morocco 2086 only - May 19 2:00 0 - +Rule Morocco 2087 only - Mar 30 3:00 -1:00 - +Rule Morocco 2087 only - May 11 2:00 0 - +# For dates after the somewhat-arbitrary cutoff of 2087, assume that +# Morocco will no longer observe DST. At some point this table will +# need to be extended, though quite possibly Morocco will change the +# rules first. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Africa/Casablanca -0:30:20 - LMT 1913 Oct 26 0:00 Morocco +00/+01 1984 Mar 16 1:00 - +01 1986 - 0:00 Morocco +00/+01 2018 Oct 27 - 1:00 - +01 + 0:00 Morocco +00/+01 2018 Oct 28 3:00 + 1:00 Morocco +01/+00 # Western Sahara # @@ -936,8 +1238,8 @@ Zone Africa/El_Aaiun -0:52:48 - LMT 1934 Jan # El Aaiún -1:00 - -01 1976 Apr 14 - 0:00 Morocco +00/+01 2018 Oct 27 - 1:00 - +01 + 0:00 Morocco +00/+01 2018 Oct 28 3:00 + 1:00 Morocco +01/+00 # Mozambique # @@ -946,7 +1248,7 @@ # https://dre.pt/pdf1sdip/1911/05/12500/23132313.pdf # merely made it official? # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Africa/Maputo 2:10:20 - LMT 1903 Mar 2:00 - CAT Link Africa/Maputo Africa/Blantyre # Malawi @@ -1007,40 +1309,101 @@ # Use plain "WAT" and "CAT" for the time zone abbreviations, to be compatible # with Namibia's neighbors. -# RULE NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S # Vanguard section, for zic and other parsers that support negative DST. -#Rule Namibia 1994 only - Mar 21 0:00 -1:00 WAT -#Rule Namibia 1994 2017 - Sep Sun>=1 2:00 0 CAT -#Rule Namibia 1995 2017 - Apr Sun>=1 2:00 -1:00 WAT -# Rearguard section, for parsers that do not support negative DST. -Rule Namibia 1994 only - Mar 21 0:00 0 WAT -Rule Namibia 1994 2017 - Sep Sun>=1 2:00 1:00 CAT -Rule Namibia 1995 2017 - Apr Sun>=1 2:00 0 WAT +Rule Namibia 1994 only - Mar 21 0:00 -1:00 WAT +Rule Namibia 1994 2017 - Sep Sun>=1 2:00 0 CAT +Rule Namibia 1995 2017 - Apr Sun>=1 2:00 -1:00 WAT +# Rearguard section, for parsers lacking negative DST; see ziguard.awk. +#Rule Namibia 1994 only - Mar 21 0:00 0 WAT +#Rule Namibia 1994 2017 - Sep Sun>=1 2:00 1:00 CAT +#Rule Namibia 1995 2017 - Apr Sun>=1 2:00 0 WAT # End of rearguard section. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Africa/Windhoek 1:08:24 - LMT 1892 Feb 8 1:30 - +0130 1903 Mar 2:00 - SAST 1942 Sep 20 2:00 2:00 1:00 SAST 1943 Mar 21 2:00 2:00 - SAST 1990 Mar 21 # independence # Vanguard section, for zic and other parsers that support negative DST. -# 2:00 Namibia %s -# Rearguard section, for parsers that do not support negative DST. - 2:00 - CAT 1994 Mar 21 0:00 + 2:00 Namibia %s +# Rearguard section, for parsers lacking negative DST; see ziguard.awk. +# 2:00 - CAT 1994 Mar 21 0:00 # From Paul Eggert (2017-04-07): # The official date of the 2017 rule change was 2017-10-24. See: # http://www.lac.org.na/laws/annoSTAT/Namibian%20Time%20Act%209%20of%202017.pdf - 1:00 Namibia %s 2017 Oct 24 - 2:00 - CAT +# 1:00 Namibia %s 2017 Oct 24 +# 2:00 - CAT # End of rearguard section. # Niger # See Africa/Lagos. # Nigeria -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Africa/Lagos 0:13:36 - LMT 1919 Sep + +# From P Chan (2020-12-03): +# GMT was adopted as the standard time of Lagos on 1905-07-01. +# Lagos Weekly Record, 1905-06-24, p 3 +# http://ddsnext.crl.edu/titles/31558#?c=0&m=668&s=0&cv=2&r=0&xywh=1446%2C5221%2C1931%2C1235 +# says "It is officially notified that on and after the 1st of July 1905 +# Greenwich Mean Solar Time will be adopted thought the Colony and +# Protectorate, and that it will be necessary to put all clocks 13 minutes and +# 35 seconds back, recording local mean time." +# +# It seemed that Lagos returned to LMT on 1908-07-01. +# [The Lagos Standard], 1908-07-01, p 5 +# http://ddsnext.crl.edu/titles/31556#?c=0&m=78&s=0&cv=4&r=0&xywh=-92%2C3590%2C3944%2C2523 +# says "Scarcely have the people become accustomed to this new time, when +# another official notice has now appeared announcing that from and after the +# 1st July next, return will be made to local mean time." +# +# From P Chan (2020-11-27): +# On 1914-01-01, standard time of GMT+0:30 was adopted for the unified Nigeria. +# Colonial Reports - Annual. No. 878. Nigeria. Report for 1914. (April 1916), +# p 27 +# https://libsysdigi.library.illinois.edu/ilharvest/Africana/Books2011-05/3064634/3064634_1914/3064634_1914_opt.pdf#page=27 +# "On January 1st [1914], a universal standard time for Nigeria was adopted, +# viz., half an hour fast on Greenwich mean time, corresponding to the meridian +# 7 [degrees] 30' E. long." +# Lloyd's Register of Shipping (1915) says "Hitherto the time observed in Lagos +# was the local mean time. On 1st January, 1914, standard time for the whole of +# Nigeria was introduced ... Lagos time has been advanced about 16 minutes +# accordingly." +# +# In 1919, standard time was changed to GMT+1. +# Interpretation Ordinance (Cap 2) +# The Laws of Nigeria, Containing the Ordinances of Nigeria, in Force on the +# 1st Day of January, 1923, Vol.I [p 16] +# https://books.google.com/books?id=BOMrAQAAMAAJ&pg=PA16 +# "The expression 'Standard time' means standard time as used in Nigeria: +# namely, 60 minutes in advance of Greenwich mean time. (As amended by 18 of +# 1919, s. 2.)" +# From Tim Parenti (2020-12-10): +# The Lagos Weekly Record, 1919-09-20, p 3 details discussion on the first +# reading of this Bill by the Legislative Council of the Colony of Nigeria on +# Thursday 1919-08-28: +# http://ddsnext.crl.edu/titles/31558?terms&item_id=303484#?m=1118&c=1&s=0&cv=2&r=0&xywh=1261%2C3408%2C2994%2C1915 +# "The proposal is that the Globe should be divided into twelve zones East and +# West of Greenwich, of one hour each, Nigeria falling into the zone with a +# standard of one hour fast on Greenwich Mean Time. Nigeria standard time is +# now 30 minutes in advance of Greenwich Mean Time ... according to the new +# proposal, standard time will be advanced another 30 minutes". It was further +# proposed that the firing of the time guns likewise be adjusted by 30 minutes +# to compensate. +# From Tim Parenti (2020-12-10), per P Chan (2020-12-11): +# The text of Ordinance 18 of 1919, published in Nigeria Gazette, Vol 6, No 52, +# shows that the change was assented to the following day and took effect "on +# the 1st day of September, 1919." +# Nigeria Gazette and Supplements 1919 Jan-Dec, Reference: 73266B-40, +# img 245-246 +# https://microform.digital/boa/collections/77/volumes/539/nigeria-lagos-1887-1919 + +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Africa/Lagos 0:13:35 - LMT 1905 Jul 1 + 0:00 - GMT 1908 Jul 1 + 0:13:35 - LMT 1914 Jan 1 + 0:30 - +0030 1919 Sep 1 1:00 - WAT Link Africa/Lagos Africa/Bangui # Central African Republic Link Africa/Lagos Africa/Brazzaville # Rep. of the Congo @@ -1053,7 +1416,7 @@ Link Africa/Lagos Africa/Porto-Novo # Benin # Réunion -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Indian/Reunion 3:41:52 - LMT 1911 Jun # Saint-Denis 4:00 - +04 # @@ -1094,17 +1457,40 @@ # the switch is from 01:00 to 02:00 ... [Decree No. 25/2017] # http://www.mnec.gov.st/index.php/publicacoes/documentos/file/90-decreto-lei-n-25-2017 +# From Vadim Nasardinov (2018-12-29): +# São Tomé and Príncipe is about to do the following on Jan 1, 2019: +# https://www.stp-press.st/2018/12/05/governo-jesus-ja-decidiu-repor-hora-legal-sao-tomense/ +# +# From Michael Deckers (2018-12-30): +# https://www.legis-palop.org/download.jsp?idFile=102818 +# ... [The legal time of the country, which coincides with universal +# coordinated time, will be restituted at 2 o'clock on day 1 of January, 2019.] + Zone Africa/Sao_Tome 0:26:56 - LMT 1884 -0:36:45 - LMT 1912 Jan 1 00:00u # Lisbon MT 0:00 - GMT 2018 Jan 1 01:00 - 1:00 - WAT + 1:00 - WAT 2019 Jan 1 02:00 + 0:00 - GMT # Senegal # See Africa/Abidjan. # Seychelles -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Indian/Mahe 3:41:48 - LMT 1906 Jun # Victoria + +# From P Chan (2020-11-27): +# Standard Time was adopted on 1907-01-01. +# +# Standard Time Ordinance (Chapter 237) +# The Laws of Seychelles in Force on the 31st December, 1971, Vol. 6, p 571 +# https://books.google.com/books?id=efE-AQAAIAAJ&pg=PA571 +# +# From Tim Parenti (2020-12-05): +# A footnote on https://books.google.com/books?id=DYdDAQAAMAAJ&pg=PA1689 +# confirms that Ordinance No. 9 of 1906 "was brought into force on the 1st +# January, 1907." + +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Indian/Mahe 3:41:48 - LMT 1907 Jan 1 # Victoria 4:00 - +04 # From Paul Eggert (2001-05-30): # Aldabra, Farquhar, and Desroches, originally dependencies of the @@ -1120,15 +1506,15 @@ # See Africa/Nairobi. # South Africa -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule SA 1942 1943 - Sep Sun>=15 2:00 1:00 - Rule SA 1943 1944 - Mar Sun>=15 2:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Africa/Johannesburg 1:52:00 - LMT 1892 Feb 8 1:30 - SAST 1903 Mar 2:00 SA SAST Link Africa/Johannesburg Africa/Maseru # Lesotho -Link Africa/Johannesburg Africa/Mbabane # Swaziland +Link Africa/Johannesburg Africa/Mbabane # Eswatini # # Marion and Prince Edward Is # scientific station since 1947 @@ -1153,25 +1539,28 @@ # Abdalla of NTC, archived at: # https://mm.icann.org/pipermail/tz/2017-October/025333.html -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Sudan 1970 only - May 1 0:00 1:00 S Rule Sudan 1970 1985 - Oct 15 0:00 0 - Rule Sudan 1971 only - Apr 30 0:00 1:00 S Rule Sudan 1972 1985 - Apr lastSun 0:00 1:00 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Africa/Khartoum 2:10:08 - LMT 1931 2:00 Sudan CA%sT 2000 Jan 15 12:00 3:00 - EAT 2017 Nov 1 2:00 - CAT +# From Steffen Thorsen (2021-01-18): +# "South Sudan will change its time zone by setting the clock back 1 +# hour on February 1, 2021...." +# from https://eyeradio.org/south-sudan-adopts-new-time-zone-makuei/ + # South Sudan -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Africa/Juba 2:06:28 - LMT 1931 2:00 Sudan CA%sT 2000 Jan 15 12:00 - 3:00 - EAT - -# Swaziland -# See Africa/Johannesburg. + 3:00 - EAT 2021 Feb 1 00:00 + 2:00 - CAT # Tanzania # See Africa/Nairobi. @@ -1244,7 +1633,7 @@ # http://www.almadenahnews.com/newss/news.php?c=118&id=38036 # http://www.worldtimezone.com/dst_news/dst_news_tunis02.html -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Tunisia 1939 only - Apr 15 23:00s 1:00 S Rule Tunisia 1939 only - Nov 18 23:00s 0 - Rule Tunisia 1940 only - Feb 25 23:00s 1:00 S @@ -1271,10 +1660,8 @@ Rule Tunisia 2006 2008 - Mar lastSun 2:00s 1:00 S Rule Tunisia 2006 2008 - Oct lastSun 2:00s 0 - -# Shanks & Pottenger give 0:09:20 for Paris Mean Time; go with Howse's -# more precise 0:09:21. -# Shanks & Pottenger say the 1911 switch was on Mar 9; go with Howse's Mar 11. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# See Europe/Paris for PMT-related transitions. +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Africa/Tunis 0:40:44 - LMT 1881 May 12 0:09:21 - PMT 1911 Mar 11 # Paris Mean Time 1:00 Tunisia CE%sT
diff --git a/make/data/tzdata/antarctica b/make/data/tzdata/antarctica index d98afed..509fadc 100644 --- a/make/data/tzdata/antarctica +++ b/make/data/tzdata/antarctica
@@ -36,7 +36,7 @@ # for information. # Unless otherwise specified, we have no time zone information. -# FORMAT is '-00' and GMTOFF is 0 for locations while uninhabited. +# FORMAT is '-00' and STDOFF is 0 for locations while uninhabited. # Argentina - year-round bases # Belgrano II, Confin Coast, -770227-0343737, since 1972-02-05 @@ -93,15 +93,30 @@ # Australian Antarctica Division informed us that Casey changed time # zone to UTC+11 in "the morning of 22nd October 2016". -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Antarctica/Casey 0 - -00 1969 - 8:00 - +08 2009 Oct 18 2:00 +# From Steffen Thorsen (2020-10-02, as corrected): +# Based on information we have received from the Australian Antarctic +# Division, Casey station and Macquarie Island station will move to Tasmanian +# daylight savings time on Sunday 4 October. This will take effect from 0001 +# hrs on Sunday 4 October 2020 and will mean Casey and Macquarie Island will +# be on the same time zone as Hobart. Some past dates too for this 3 hour +# time change back and forth between UTC+8 and UTC+11 for Casey: +# - 2018 Oct 7 4:00 - 2019 Mar 17 3:00 - 2019 Oct 4 3:00 - 2020 Mar 8 3:00 +# and now - 2020 Oct 4 0:01 + +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Antarctica/Casey 0 - -00 1969 + 8:00 - +08 2009 Oct 18 2:00 11:00 - +11 2010 Mar 5 2:00 - 8:00 - +08 2011 Oct 28 2:00 + 8:00 - +08 2011 Oct 28 2:00 11:00 - +11 2012 Feb 21 17:00u - 8:00 - +08 2016 Oct 22 + 8:00 - +08 2016 Oct 22 11:00 - +11 2018 Mar 11 4:00 - 8:00 - +08 + 8:00 - +08 2018 Oct 7 4:00 + 11:00 - +11 2019 Mar 17 3:00 + 8:00 - +08 2019 Oct 4 3:00 + 11:00 - +11 2020 Mar 8 3:00 + 8:00 - +08 2020 Oct 4 0:01 + 11:00 - +11 Zone Antarctica/Davis 0 - -00 1957 Jan 13 7:00 - +07 1964 Nov 0 - -00 1969 Feb @@ -165,7 +180,7 @@ # St Paul Island - near Amsterdam, uninhabited # fishing stations operated variously 1819/1931 # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Indian/Kerguelen 0 - -00 1950 # Port-aux-Français 5:00 - +05 # @@ -176,7 +191,7 @@ # Another base at Port-Martin, 50km east, began operation in 1947. # It was destroyed by fire on 1952-01-14. # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Antarctica/DumontDUrville 0 - -00 1947 10:00 - +10 1952 Jan 14 0 - -00 1956 Nov @@ -204,7 +219,7 @@ # Syowa station, which is the first antarctic station of Japan, # was established on 1957-01-29. Since Syowa station is still the main # station of Japan, it's appropriate for the principal location. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Antarctica/Syowa 0 - -00 1957 Jan 29 3:00 - +03 # See: @@ -247,14 +262,14 @@ # suggested by Bengt-Inge Larsson comment them out for now, and approximate # with only UTC and CEST. Uncomment them when 2014b is more prevalent. # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S #Rule Troll 2005 max - Mar 1 1:00u 1:00 +01 Rule Troll 2005 max - Mar lastSun 1:00u 2:00 +02 #Rule Troll 2005 max - Oct lastSun 1:00u 1:00 +01 #Rule Troll 2004 max - Nov 7 1:00u 0:00 +00 # Remove the following line when uncommenting the above '#Rule' lines. Rule Troll 2004 max - Oct lastSun 1:00u 0:00 +00 -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Antarctica/Troll 0 - -00 2005 Feb 12 0:00 Troll %s @@ -328,7 +343,7 @@ # From Paul Eggert (2002-10-22) # <http://webexhibits.org/daylightsaving/g.html> says Rothera is -03 all year. # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Antarctica/Rothera 0 - -00 1976 Dec 1 -3:00 - -03
diff --git a/make/data/tzdata/asia b/make/data/tzdata/asia index 57255f2..143d8e8 100644 --- a/make/data/tzdata/asia +++ b/make/data/tzdata/asia
@@ -31,7 +31,7 @@ # tz@iana.org for general use in the future). For more, please see # the file CONTRIBUTING in the tz distribution. -# From Paul Eggert (2018-06-19): +# From Paul Eggert (2019-07-11): # # Unless otherwise specified, the source for data through 1990 is: # Thomas G. Shanks and Rique Pottenger, The International Atlas (6th edition), @@ -70,13 +70,13 @@ # 7:00 WIB west Indonesia (Waktu Indonesia Barat) # 8:00 WITA central Indonesia (Waktu Indonesia Tengah) # 8:00 CST China -# 8:00 PST PDT* Philippine Standard Time +# 8:00 HKT HKST Hong Kong (HKWT* for Winter Time in late 1941) +# 8:00 PST PDT* Philippines # 8:30 KST KDT Korea when at +0830 # 9:00 WIT east Indonesia (Waktu Indonesia Timur) # 9:00 JST JDT Japan # 9:00 KST KDT Korea when at +09 -# 9:30 ACST Australian Central Standard Time -# *I invented the abbreviation PDT; see "Philippines" below. +# *I invented the abbreviations HKWT and PDT; see below. # Otherwise, these tables typically use numeric abbreviations like +03 # and +0330 for integer hour and minute UT offsets. Although earlier # editions invented alphabetic time zone abbreviations for every @@ -93,7 +93,7 @@ ############################################################################### # These rules are stolen from the 'europe' file. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule EUAsia 1981 max - Mar lastSun 1:00u 1:00 S Rule EUAsia 1979 1995 - Sep lastSun 1:00u 0 - Rule EUAsia 1996 max - Oct lastSun 1:00u 0 - @@ -107,7 +107,7 @@ Rule RussiaAsia 1996 2010 - Oct lastSun 2:00s 0 - # Afghanistan -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Kabul 4:36:48 - LMT 1890 4:00 - +04 1945 4:30 - +0430 @@ -137,10 +137,10 @@ # or # (brief) # http://www.worldtimezone.com/dst_news/dst_news_armenia03.html -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Armenia 2011 only - Mar lastSun 2:00s 1:00 - Rule Armenia 2011 only - Oct lastSun 2:00s 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Yerevan 2:58:00 - LMT 1924 May 2 3:00 - +03 1957 Mar 4:00 RussiaAsia +04/+05 1991 Mar 31 2:00s @@ -163,10 +163,10 @@ # http://vestnikkavkaza.net/news/Azerbaijani-Cabinet-of-Ministers-cancels-daylight-saving-time.html # http://en.apa.az/xeber_azerbaijan_abolishes_daylight_savings_ti_240862.html -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Azer 1997 2015 - Mar lastSun 4:00 1:00 - Rule Azer 1997 2015 - Oct lastSun 5:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Baku 3:19:24 - LMT 1924 May 2 3:00 - +03 1957 Mar 4:00 RussiaAsia +04/+05 1991 Mar 31 2:00s @@ -250,11 +250,11 @@ # http://www.thedailystar.net/newDesign/latest_news.php?nid=22817 # http://www.worldtimezone.com/dst_news/dst_news_bangladesh06.html -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Dhaka 2009 only - Jun 19 23:00 1:00 - Rule Dhaka 2009 only - Dec 31 24:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Dhaka 6:01:40 - LMT 1890 5:53:20 - HMT 1941 Oct # Howrah Mean Time? 6:30 - +0630 1942 May 15 @@ -264,7 +264,7 @@ 6:00 Dhaka +06/+07 # Bhutan -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Thimphu 5:58:36 - LMT 1947 Aug 15 # or Thimbu 5:30 - +0530 1987 Oct 6:00 - +06 @@ -275,13 +275,13 @@ # We have no information as to when standard time was introduced; # assume it occurred in 1907, the same year as Mauritius (which # then contained the Chagos Archipelago). -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Indian/Chagos 4:49:40 - LMT 1907 5:00 - +05 1996 6:00 - +06 # Brunei -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Brunei 7:39:40 - LMT 1926 Mar # Bandar Seri Begawan 7:30 - +0730 1933 8:00 - +08 @@ -296,7 +296,7 @@ # of Greenwich." This refers to the period before Burma's transition to +0630, # a transition for which Shanks is the only source. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Yangon 6:24:47 - LMT 1880 # or Rangoon 6:24:47 - RMT 1920 # Rangoon local time 6:30 - +0630 1942 May @@ -309,6 +309,27 @@ # China +# From Phake Nick (2020-04-15): +# According to this news report: +# http://news.sina.com.cn/c/2004-09-01/19524201403.shtml +# on April 11, 1919, newspaper in Shanghai said clocks in Shanghai will spring +# forward for an hour starting from midnight of that Saturday. The report did +# not mention what happened in Shanghai thereafter, but it mentioned that a +# similar trial in Tianjin which ended at October 1st as citizens are told to +# recede the clock on September 30 from 12:00pm to 11:00pm. The trial at +# Tianjin got terminated in 1920. +# +# From Paul Eggert (2020-04-15): +# The Returns of Trade and Trade Reports, page 711, says "Daylight saving was +# given a trial during the year, and from the 12th April to the 1st October +# the clocks were all set one hour ahead of sun time. Though the scheme was +# generally esteemed a success, it was announced early in 1920 that it would +# not be repeated." +# +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule Shang 1919 only - Apr 12 24:00 1:00 D +Rule Shang 1919 only - Sep 30 24:00 0 S + # From Paul Eggert (2018-10-02): # The following comes from Table 1 of: # Li Yu. Research on the daylight saving movement in 1940s Shanghai. @@ -317,8 +338,91 @@ # The table lists dates only; I am guessing 00:00 and 24:00 transition times. # Also, the table lists the planned end of DST in 1949, but the corresponding # zone line cuts this off on May 28, when the Communists took power. + +# From Phake Nick (2020-04-15): # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# For the history of time in Shanghai between 1940-1942, the situation is +# actually slightly more complex than the table [below].... At the time, +# there were three different authorities in Shanghai, including Shanghai +# International Settlement, a settlement established by western countries with +# its own westernized form of government, Shanghai French Concession, similar +# to the international settlement but is controlled by French, and then the +# rest of the city of Shanghai, which have already been controlled by Japanese +# force through a puppet local government (Wang Jingwei regime). It was +# additionally complicated by the circumstances that, according to the 1940s +# Shanghai summer time essay cited in the database, some +# departments/businesses/people in the Shanghai city itself during that time +# period, refused to change their clock and instead only changed their opening +# hours. +# +# For example, as quoted in the article, in 1940, other than the authority +# itself, power, tram, bus companies, cinema, department stores, and other +# public service organizations have all decided to follow the summer time and +# spring forward the clock. On the other hand, the custom office refused to +# spring forward the clock because of worry on mechanical wear to the physical +# clock, postal office refused to spring forward because of disruption to +# business and log-keeping, although they did changed their office hour to +# match rest of the city. So is travel agents, and also weather +# observatory. It is said both time standards had their own supporters in the +# city at the time, those who prefer new time standard would have moved their +# clock while those who prefer the old time standard would keep their clock +# unchange, and there were different clocks that use different time standard +# in the city at the time for people who use different time standard to adjust +# their clock to their preferred time. +# +# a. For the 1940 May 31 spring forward, the essay claim that it was +# coordinared between the international settlement authority and the French +# concession authority and have gathered support from Hong Kong and Xiamen, +# that it would spring forward an hour from May 31 "midnight", and the essay +# claim "Hong Kong government implemented the spring forward in the same time +# on the same date as Shanghai". +# +# b. For the 1940 fall back, it was said that they initially intended to do +# so on September 30 00:59 at night, however they postponed it to October 12 +# after discussion with relevant parties. However schools restored to the +# original schedule ten days earlier. +# +# c. For the 1941 spring forward, it is said to start from March 15 +# "following the previous year's method", and in addition to that the essay +# cited an announcement in 1941 from the Wang regime which said the Special +# City of Shanghai under Wang regime control will follow the DST rule set by +# the Settlements, irrespective of the original DST plan announced by the Wang +# regime for other area under its control(April 1 to September 30). (no idea +# to situation before that announcement) +# +# d. For the 1941 fall back, it was said that the fall back would occurs at +# the end of September (A newspaper headline cited by the essay, published on +# October 1, 1941, have the headlines which said "French Concession would +# rewind to the old clock this morning), but it ultimately didn't happen due +# to disagreement between the international settlement authority and the +# French concession authority, and the fall back ultimately occurred on +# November 1. +# +# e. In 1941 December, Japan have officially started war with the United +# States and the United Kingdom, and in Shanghai they have marched into the +# international settlement, taken over its control +# +# f. For the 1942 spring forward, the essay said that the spring forward +# started on January 31. It said this time the custom office and postal +# department will also change their clocks, unlike before. +# +# g. The essay itself didn't cover any specific changes thereafter until the +# end of the war, it quoted a November 1942 command from the government of the +# Wang regime, which claim the daylight saving time applies year round during +# the war. However, the essay ambiguously said the period is "February 1 to +# September 30", which I don't really understand what is the meaning of such +# period in the context of year round implementation here.. More researches +# might be needed to show exactly what happened during that period of time. + +# From Phake Nick (2020-04-15): +# According to a Japanese tour bus pamphlet in Nanjing area believed to be +# from around year 1941: http://www.tt-museum.jp/tairiku_0280_nan1941.html , +# the schedule listed was in the format of Japanese time. Which indicate some +# use of the Japanese time (instead of syncing by DST) might have occurred in +# the Yangtze river delta area during that period of time although the scope +# of such use will need to be investigated to determine. +# +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Shang 1940 only - Jun 1 0:00 1:00 D Rule Shang 1940 only - Oct 12 24:00 0 S Rule Shang 1941 only - Mar 15 0:00 1:00 D @@ -381,7 +485,7 @@ # to begin on 17 April. # http://data.people.com.cn/pic/101p/1988/04/1988041201.jpg -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule PRC 1986 only - May 4 2:00 1:00 D Rule PRC 1986 1991 - Sep Sun>=11 2:00 0 S Rule PRC 1987 1991 - Apr Sun>=11 2:00 1:00 D @@ -584,7 +688,7 @@ # that the sort of users who prefer Asia/Urumqi now typically ignored the # +08 mandate back then. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] # Beijing time, used throughout China; represented by Shanghai. Zone Asia/Shanghai 8:05:43 - LMT 1901 8:00 Shang C%sT 1949 May 28 @@ -595,7 +699,7 @@ 6:00 - +06 -# Hong Kong (Xianggang) +# Hong Kong # Milne gives 7:36:41.7; round this. @@ -605,27 +709,134 @@ # it is not [an] observatory, but the official meteorological agency of HK, # and also serves as the official timing agency), there are some missing # and incorrect rules. Although the exact switch over time is missing, I -# think 3:30 is correct. The official DST record for Hong Kong can be -# obtained from -# http://www.hko.gov.hk/gts/time/Summertime.htm +# think 3:30 is correct. -# From Arthur David Olson (2009-10-28): +# From Phake Nick (2018-10-27): +# According to Singaporean newspaper +# http://eresources.nlb.gov.sg/newspapers/Digitised/Article/singfreepresswk19041102-1.2.37 +# the day that Hong Kong start using GMT+8 should be Oct 30, 1904. +# +# From Paul Eggert (2018-11-17): +# Hong Kong had a time ball near the Marine Police Station, Tsim Sha Tsui. +# "The ball was raised manually each day and dropped at exactly 1pm +# (except on Sundays and Government holidays)." +# Dyson AD. From Time Ball to Atomic Clock. Hong Kong Government. 1983. +# <https://www.hko.gov.hk/publica/gen_pub/timeball_atomic_clock.pdf> +# "From 1904 October 30 the time-ball at Hong Kong has been dropped by order +# of the Governor of the Colony at 17h 0m 0s G.M.T., which is 23m 18s.14 in +# advance of 1h 0m 0s of Hong Kong mean time." +# Hollis HP. Universal Time, Longitudes, and Geodesy. Mon Not R Astron Soc. +# 1905-02-10;65(4):405-6. https://doi.org/10.1093/mnras/65.4.382 +# +# From Joseph Myers (2018-11-18): +# An astronomer before 1925 referring to GMT would have been using the old +# astronomical convention where the day started at noon, not midnight. +# +# From Steve Allen (2018-11-17): +# Meteorological Observations made at the Hongkong Observatory in the year 1904 +# page 4 <https://books.google.com/books?id=kgw5AQAAMAAJ&pg=RA4-PA4> +# ... the log of drop times in Table II shows that on Sunday 1904-10-30 the +# ball was dropped. So that looks like a special case drop for the sake +# of broadcasting the new local time. +# +# From Phake Nick (2018-11-18): +# According to The Hong Kong Weekly Press, 1904-10-29, p.324, the +# governor of Hong Kong at the time stated that "We are further desired to +# make it known that the change will be effected by firing the gun and by the +# dropping of the Ball at 23min. 18sec. before one." +# From Paul Eggert (2018-11-18): +# See <https://mmis.hkpl.gov.hk> for this; unfortunately Flash is required. + +# From Phake Nick (2018-10-26): +# I went to check microfilm records stored at Hong Kong Public Library.... +# on September 30 1941, according to Ta Kung Pao (Hong Kong edition), it was +# stated that fallback would occur on the next day (the 1st)'s "03:00 am (Hong +# Kong Time 04:00 am)" and the clock will fall back for a half hour. (03:00 +# probably refer to the time commonly used in mainland China at the time given +# the paper's background) ... the sunrise/sunset time given by South China +# Morning Post for October 1st was indeed moved by half an hour compares to +# before. After that, in December, the battle to capture Hong Kong started and +# the library doesn't seems to have any record stored about press during that +# period of time. Some media resumed publication soon after that within the +# same month, but there were not much information about time there. Later they +# started including a radio program guide when they restored radio service, +# explicitly mentioning it use Tokyo standard time, and later added a note +# saying it's half an hour ahead of the old Hong Kong standard time, and it +# also seems to indicate that Hong Kong was not using GMT+8 when it was +# captured by Japan. +# +# Image of related sections on newspaper: +# * 1941-09-30, Ta Kung Pao (Hong Kong), "Winter Time start tomorrow". +# https://i.imgur.com/6waY51Z.jpg (Chinese) +# * 1941-09-29, South China Morning Post, Information on sunrise/sunset +# time and other things for September 30 and October 1. +# https://i.imgur.com/kCiUR78.jpg +# * 1942-02-05. The Hong Kong News, Radio Program Guide. +# https://i.imgur.com/eVvDMzS.jpg +# * 1941-06-14. Hong Kong Daily Press, Daylight Saving from 3am Tomorrow. +# https://i.imgur.com/05KkvtC.png +# * 1941-09-30, Hong Kong Daily Press, Winter Time Warning. +# https://i.imgur.com/dge4kFJ.png + +# From Paul Eggert (2019-07-11): +# "Hong Kong winter time" is considered to be daylight saving. +# "Hong Kong had adopted daylight saving on June 15 as a wartime measure, +# clocks moving forward one hour until October 1, when they would be put back +# by just half an hour for 'Hong Kong Winter time', so that daylight saving +# operated year round." -- Low Z. The longest day: when wartime Hong Kong +# introduced daylight saving. South China Morning Post. 2019-06-28. +# https://www.scmp.com/magazines/post-magazine/short-reads/article/3016281/longest-day-when-wartime-hong-kong-introduced + +# From P Chan (2018-12-31): +# * According to the Hong Kong Daylight-Saving Regulations, 1941, the +# 1941 spring-forward transition was at 03:00. +# http://sunzi.lib.hku.hk/hkgro/view/g1941/304271.pdf +# http://sunzi.lib.hku.hk/hkgro/view/g1941/305516.pdf +# * According to some articles from South China Morning Post, +08 was +# resumed on 1945-11-18 at 02:00. +# https://i.imgur.com/M2IsZ3c.png +# https://i.imgur.com/iOPqrVo.png +# https://i.imgur.com/fffcGDs.png +# * Some newspapers ... said the 1946 spring-forward transition was on +# 04-21 at 00:00. The Kung Sheung Evening News 1946-04-20 (Chinese) +# https://i.imgur.com/ZSzent0.png +# https://mmis.hkpl.gov.hk///c/portal/cover?c=QF757YsWv5%2FH7zGe%2FKF%2BFLYsuqGhRBfe p.4 +# The Kung Sheung Daily News 1946-04-21 (Chinese) +# https://i.imgur.com/7ecmRlcm.png +# https://mmis.hkpl.gov.hk///c/portal/cover?c=QF757YsWv5%2BQBGt1%2BwUj5qG2GqtwR3Wh p.4 +# * According to the Summer Time Ordinance (1946), the fallback +# transitions between 1946 and 1952 were at 03:30 Standard Time (+08) +# http://oelawhk.lib.hku.hk/archive/files/bb74b06a74d5294620a15de560ab33c6.pdf +# * Some other laws and regulations related to DST from 1953 to 1979 +# Summer Time Ordinance 1953 +# https://i.imgur.com/IOlJMav.jpg +# Summer Time (Amendment) Ordinance 1965 +# https://i.imgur.com/8rofeLa.jpg +# Interpretation and General Clauses Ordinance (1966) +# https://i.imgur.com/joy3msj.jpg +# Emergency (Summer Time) Regulation 1973 <https://i.imgur.com/OpRWrKz.jpg> +# Interpretation and General Clauses (Amendment) Ordinance 1977 +# https://i.imgur.com/RaNqnc4.jpg +# Resolution of the Legislative Council passed on 9 May 1979 +# https://www.legco.gov.hk/yr78-79/english/lc_sitg/hansard/h790509.pdf#page=39 + +# From Paul Eggert (2020-04-15): # Here are the dates given at -# http://www.hko.gov.hk/gts/time/Summertime.htm -# as of 2009-10-28: +# https://www.hko.gov.hk/en/gts/time/Summertime.htm +# as of 2020-02-10: # Year Period -# 1941 1 Apr to 30 Sep +# 1941 15 Jun to 30 Sep # 1942 Whole year # 1943 Whole year # 1944 Whole year # 1945 Whole year # 1946 20 Apr to 1 Dec -# 1947 13 Apr to 30 Dec +# 1947 13 Apr to 30 Nov # 1948 2 May to 31 Oct # 1949 3 Apr to 30 Oct # 1950 2 Apr to 29 Oct # 1951 1 Apr to 28 Oct -# 1952 6 Apr to 25 Oct +# 1952 6 Apr to 2 Nov # 1953 5 Apr to 1 Nov # 1954 21 Mar to 31 Oct # 1955 20 Mar to 6 Nov @@ -654,37 +865,31 @@ # 1978 Nil # 1979 13 May to 21 Oct # 1980 to Now Nil -# The page does not give start or end times of day. -# The page does not give a start date for 1942. -# The page does not givw an end date for 1945. -# The Japanese occupation of Hong Kong began on 1941-12-25. -# The Japanese surrender of Hong Kong was signed 1945-09-15. -# For lack of anything better, use start of those days as the transition times. +# The page does not give times of day for transitions, +# or dates for the 1942 and 1945 transitions. +# The Japanese occupation of Hong Kong began 1941-12-25. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -Rule HK 1941 only - Apr 1 3:30 1:00 S -Rule HK 1941 only - Sep 30 3:30 0 - -Rule HK 1946 only - Apr 20 3:30 1:00 S -Rule HK 1946 only - Dec 1 3:30 0 - -Rule HK 1947 only - Apr 13 3:30 1:00 S -Rule HK 1947 only - Dec 30 3:30 0 - -Rule HK 1948 only - May 2 3:30 1:00 S -Rule HK 1948 1951 - Oct lastSun 3:30 0 - -Rule HK 1952 only - Oct 25 3:30 0 - +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule HK 1946 only - Apr 21 0:00 1:00 S +Rule HK 1946 only - Dec 1 3:30s 0 - +Rule HK 1947 only - Apr 13 3:30s 1:00 S +Rule HK 1947 only - Nov 30 3:30s 0 - +Rule HK 1948 only - May 2 3:30s 1:00 S +Rule HK 1948 1952 - Oct Sun>=28 3:30s 0 - Rule HK 1949 1953 - Apr Sun>=1 3:30 1:00 S -Rule HK 1953 only - Nov 1 3:30 0 - +Rule HK 1953 1964 - Oct Sun>=31 3:30 0 - Rule HK 1954 1964 - Mar Sun>=18 3:30 1:00 S -Rule HK 1954 only - Oct 31 3:30 0 - -Rule HK 1955 1964 - Nov Sun>=1 3:30 0 - Rule HK 1965 1976 - Apr Sun>=16 3:30 1:00 S Rule HK 1965 1976 - Oct Sun>=16 3:30 0 - Rule HK 1973 only - Dec 30 3:30 1:00 S -Rule HK 1979 only - May Sun>=8 3:30 1:00 S -Rule HK 1979 only - Oct Sun>=16 3:30 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Asia/Hong_Kong 7:36:42 - LMT 1904 Oct 30 - 8:00 HK HK%sT 1941 Dec 25 - 9:00 - JST 1945 Sep 15 +Rule HK 1979 only - May 13 3:30 1:00 S +Rule HK 1979 only - Oct 21 3:30 0 - +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Asia/Hong_Kong 7:36:42 - LMT 1904 Oct 30 0:36:42 + 8:00 - HKT 1941 Jun 15 3:00 + 8:00 1:00 HKST 1941 Oct 1 4:00 + 8:00 0:30 HKWT 1941 Dec 25 + 9:00 - JST 1945 Nov 18 2:00 8:00 HK HK%sT ############################################################################### @@ -791,7 +996,7 @@ # until 1945-09-21 at 01:00, overriding Shanks & Pottenger. # Likewise, use Yu-Cheng Chuang's data for DST in Taiwan. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Taiwan 1946 only - May 15 0:00 1:00 D Rule Taiwan 1946 only - Oct 1 0:00 0 S Rule Taiwan 1947 only - Apr 15 0:00 1:00 D @@ -808,7 +1013,7 @@ Rule Taiwan 1979 only - Jul 1 0:00 1:00 D Rule Taiwan 1979 only - Oct 1 0:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] # Taipei or Taibei or T'ai-pei Zone Asia/Taipei 8:06:00 - LMT 1896 Jan 1 8:00 - CST 1937 Oct 1 @@ -917,7 +1122,7 @@ # The 1904 decree says that Macau changed from the meridian of # Fortaleza do Monte, presumably the basis for the 7:34:10 for LMT. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Macau 1942 1943 - Apr 30 23:00 1:00 - Rule Macau 1942 only - Nov 17 23:00 0 - Rule Macau 1943 only - Sep 30 23:00 0 S @@ -946,7 +1151,7 @@ Rule Macau 1979 only - May 13 03:30 1:00 D Rule Macau 1979 only - Oct Sun>=16 03:30 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Macau 7:34:10 - LMT 1904 Oct 30 8:00 - CST 1941 Dec 21 23:00 9:00 Macau +09/+10 1945 Sep 30 24:00 @@ -975,7 +1180,7 @@ # Cyprus to remain united in time. Cyprus Mail 2017-10-17. # https://cyprus-mail.com/2017/10/17/cyprus-remain-united-time/ -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Cyprus 1975 only - Apr 13 0:00 1:00 S Rule Cyprus 1975 only - Oct 12 0:00 0 - Rule Cyprus 1976 only - May 15 0:00 1:00 S @@ -985,7 +1190,7 @@ Rule Cyprus 1978 only - Oct 2 0:00 0 - Rule Cyprus 1979 1997 - Sep lastSun 0:00 0 - Rule Cyprus 1981 1998 - Mar lastSun 0:00 1:00 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Nicosia 2:13:28 - LMT 1921 Nov 14 2:00 Cyprus EE%sT 1998 Sep 2:00 EUAsia EE%sT @@ -1034,7 +1239,7 @@ # Byalokoz 1919 says Georgia was 2:59:11. # Go with Byalokoz. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Tbilisi 2:59:11 - LMT 1880 2:59:11 - TBMT 1924 May 2 # Tbilisi Mean Time 3:00 - +03 1957 Mar @@ -1071,7 +1276,7 @@ # which will be permanent, with no seasonal adjustment, will happen at # midnight on Saturday, September 16. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Dili 8:22:20 - LMT 1912 Jan 1 8:00 - +08 1942 Feb 21 23:00 9:00 - +09 1976 May 3 @@ -1080,6 +1285,16 @@ # India +# British astronomer Henry Park Hollis disliked India Standard Time's offset: +# "A new time system has been proposed for India, Further India, and Burmah. +# The scheme suggested is that the times of the meridians 5½ and 6½ hours +# east of Greenwich should be adopted in these territories. No reason is +# given why hourly meridians five hours and six hours east should not be +# chosen; a plan which would bring the time of India into harmony with +# that of almost the whole of the civilised world." +# Hollis HP. Universal Time, Longitudes, and Geodesy. Mon Not R Astron Soc. +# 1905-02-10;65(4):405-6. https://doi.org/10.1093/mnras/65.4.382 + # From Ian P. Beacock, in "A brief history of (modern) time", The Atlantic # https://www.theatlantic.com/technology/archive/2015/12/the-creation-of-modern-time/421419/ # (2015-12-22): @@ -1127,7 +1342,7 @@ # time for 1870-1941. Shanks is our only (and dubious) source for the # 1941-1945 data. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Kolkata 5:53:28 - LMT 1854 Jun 28 # Kolkata 5:53:20 - HMT 1870 # Howrah Mean Time? 5:21:10 - MMT 1906 Jan 1 # Madras local time @@ -1179,7 +1394,7 @@ # WITA - +08 - Waktu Indonesia Tengah (Indonesia central time) # WIT - +09 - Waktu Indonesia Timur (Indonesia eastern time) # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] # Java, Sumatra Zone Asia/Jakarta 7:07:12 - LMT 1867 Aug 10 # Shanks & Pottenger say the next transition was at 1924 Jan 1 0:13, @@ -1250,12 +1465,65 @@ # leap year calculation involved. There has never been any serious # plan to change that law.... # -# From Paul Eggert (2006-03-22): +# From Paul Eggert (2018-11-30): # Go with Shanks & Pottenger before Sept. 1991, and with Pournader thereafter. -# I used Ed Reingold's cal-persia in GNU Emacs 21.2 to check Persian dates, -# stopping after 2037 when 32-bit time_t's overflow. -# That cal-persia used Birashk's approximation, which disagrees with the solar -# calendar predictions for the year 2025, so I corrected those dates by hand. +# I used the following code in GNU Emacs 26.1 to generate the "Rule Iran" +# lines from 2008 through 2087. Emacs 26.1 uses Ed Reingold's +# cal-persia implementation of Birashk's approximation, which in the +# 2008-2087 range disagrees with the astronomical Persian calendar +# for Persian years 1404 (Gregorian 2025) and 1437 (Gregorian 2058), so +# the following code special-cases those years. See Table 15.1, page 264, of: +# Edward M. Reingold and Nachum Dershowitz, Calendrical Calculations: +# The Ultimate Edition, Cambridge University Press (2018). +# https://www.cambridge.org/fr/academic/subjects/computer-science/computing-general-interest/calendrical-calculations-ultimate-edition-4th-edition +# Page 258, footnote 2, of this book says there is some dispute over what will +# happen in 2091 (and some other years after that), so this code +# stops in 2087, as 2088 and 2089 agree with the "max" rule below. +# (cl-loop +# initially (require 'cal-persia) +# with first-persian-year = 1387 +# with last-persian-year = 1466 +# ;; Exceptional years in the above range, +# ;; from Reingold & Dershowitz Table 15.1, page 264: +# with exceptional-persian-years = '(1404 1437) +# with range-start = nil +# for persian-year from first-persian-year to last-persian-year +# do +# (let* +# ((exceptional-year-offset +# (if (member persian-year exceptional-persian-years) 1 0)) +# (beg-dst-absolute +# (+ (calendar-persian-to-absolute (list 1 1 persian-year)) +# exceptional-year-offset)) +# (end-dst-absolute +# (+ (calendar-persian-to-absolute (list 6 30 persian-year)) +# exceptional-year-offset)) +# (next-year-beg-dst-absolute +# (+ (calendar-persian-to-absolute (list 1 1 (1+ persian-year))) +# (if (member (1+ persian-year) exceptional-persian-years) 1 0))) +# (beg-dst (calendar-gregorian-from-absolute beg-dst-absolute)) +# (end-dst (calendar-gregorian-from-absolute end-dst-absolute)) +# (next-year-beg-dst (calendar-gregorian-from-absolute +# next-year-beg-dst-absolute)) +# (year (calendar-extract-year beg-dst)) +# (range-end (if range-start year "only"))) +# (setq range-start (or range-start year)) +# (when (or (/= (calendar-extract-day beg-dst) +# (calendar-extract-day next-year-beg-dst)) +# (= persian-year last-persian-year)) +# (insert +# (format +# "Rule\tIran\t%d\t%s\t-\t%s\t%2d\t24:00\t1:00\t-\n" +# range-start range-end +# (calendar-month-name (calendar-extract-month beg-dst) t) +# (calendar-extract-day beg-dst))) +# (insert +# (format +# "Rule\tIran\t%d\t%s\t-\t%s\t%2d\t24:00\t0\t-\n" +# range-start range-end +# (calendar-month-name (calendar-extract-month end-dst) t) +# (calendar-extract-day end-dst))) +# (setq range-start nil)))) # # From Oscar van Vlijmen (2005-03-30), writing about future # discrepancies between cal-persia and the Iranian calendar: @@ -1289,64 +1557,116 @@ # be changed back to its previous state on the 24 hours of the # thirtieth day of Shahrivar. # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -Rule Iran 1978 1980 - Mar 21 0:00 1:00 - -Rule Iran 1978 only - Oct 21 0:00 0 - -Rule Iran 1979 only - Sep 19 0:00 0 - -Rule Iran 1980 only - Sep 23 0:00 0 - -Rule Iran 1991 only - May 3 0:00 1:00 - -Rule Iran 1992 1995 - Mar 22 0:00 1:00 - -Rule Iran 1991 1995 - Sep 22 0:00 0 - -Rule Iran 1996 only - Mar 21 0:00 1:00 - -Rule Iran 1996 only - Sep 21 0:00 0 - -Rule Iran 1997 1999 - Mar 22 0:00 1:00 - -Rule Iran 1997 1999 - Sep 22 0:00 0 - -Rule Iran 2000 only - Mar 21 0:00 1:00 - -Rule Iran 2000 only - Sep 21 0:00 0 - -Rule Iran 2001 2003 - Mar 22 0:00 1:00 - -Rule Iran 2001 2003 - Sep 22 0:00 0 - -Rule Iran 2004 only - Mar 21 0:00 1:00 - -Rule Iran 2004 only - Sep 21 0:00 0 - -Rule Iran 2005 only - Mar 22 0:00 1:00 - -Rule Iran 2005 only - Sep 22 0:00 0 - -Rule Iran 2008 only - Mar 21 0:00 1:00 - -Rule Iran 2008 only - Sep 21 0:00 0 - -Rule Iran 2009 2011 - Mar 22 0:00 1:00 - -Rule Iran 2009 2011 - Sep 22 0:00 0 - -Rule Iran 2012 only - Mar 21 0:00 1:00 - -Rule Iran 2012 only - Sep 21 0:00 0 - -Rule Iran 2013 2015 - Mar 22 0:00 1:00 - -Rule Iran 2013 2015 - Sep 22 0:00 0 - -Rule Iran 2016 only - Mar 21 0:00 1:00 - -Rule Iran 2016 only - Sep 21 0:00 0 - -Rule Iran 2017 2019 - Mar 22 0:00 1:00 - -Rule Iran 2017 2019 - Sep 22 0:00 0 - -Rule Iran 2020 only - Mar 21 0:00 1:00 - -Rule Iran 2020 only - Sep 21 0:00 0 - -Rule Iran 2021 2023 - Mar 22 0:00 1:00 - -Rule Iran 2021 2023 - Sep 22 0:00 0 - -Rule Iran 2024 only - Mar 21 0:00 1:00 - -Rule Iran 2024 only - Sep 21 0:00 0 - -Rule Iran 2025 2027 - Mar 22 0:00 1:00 - -Rule Iran 2025 2027 - Sep 22 0:00 0 - -Rule Iran 2028 2029 - Mar 21 0:00 1:00 - -Rule Iran 2028 2029 - Sep 21 0:00 0 - -Rule Iran 2030 2031 - Mar 22 0:00 1:00 - -Rule Iran 2030 2031 - Sep 22 0:00 0 - -Rule Iran 2032 2033 - Mar 21 0:00 1:00 - -Rule Iran 2032 2033 - Sep 21 0:00 0 - -Rule Iran 2034 2035 - Mar 22 0:00 1:00 - -Rule Iran 2034 2035 - Sep 22 0:00 0 - +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule Iran 1978 1980 - Mar 20 24:00 1:00 - +Rule Iran 1978 only - Oct 20 24:00 0 - +Rule Iran 1979 only - Sep 18 24:00 0 - +Rule Iran 1980 only - Sep 22 24:00 0 - +Rule Iran 1991 only - May 2 24:00 1:00 - +Rule Iran 1992 1995 - Mar 21 24:00 1:00 - +Rule Iran 1991 1995 - Sep 21 24:00 0 - +Rule Iran 1996 only - Mar 20 24:00 1:00 - +Rule Iran 1996 only - Sep 20 24:00 0 - +Rule Iran 1997 1999 - Mar 21 24:00 1:00 - +Rule Iran 1997 1999 - Sep 21 24:00 0 - +Rule Iran 2000 only - Mar 20 24:00 1:00 - +Rule Iran 2000 only - Sep 20 24:00 0 - +Rule Iran 2001 2003 - Mar 21 24:00 1:00 - +Rule Iran 2001 2003 - Sep 21 24:00 0 - +Rule Iran 2004 only - Mar 20 24:00 1:00 - +Rule Iran 2004 only - Sep 20 24:00 0 - +Rule Iran 2005 only - Mar 21 24:00 1:00 - +Rule Iran 2005 only - Sep 21 24:00 0 - +Rule Iran 2008 only - Mar 20 24:00 1:00 - +Rule Iran 2008 only - Sep 20 24:00 0 - +Rule Iran 2009 2011 - Mar 21 24:00 1:00 - +Rule Iran 2009 2011 - Sep 21 24:00 0 - +Rule Iran 2012 only - Mar 20 24:00 1:00 - +Rule Iran 2012 only - Sep 20 24:00 0 - +Rule Iran 2013 2015 - Mar 21 24:00 1:00 - +Rule Iran 2013 2015 - Sep 21 24:00 0 - +Rule Iran 2016 only - Mar 20 24:00 1:00 - +Rule Iran 2016 only - Sep 20 24:00 0 - +Rule Iran 2017 2019 - Mar 21 24:00 1:00 - +Rule Iran 2017 2019 - Sep 21 24:00 0 - +Rule Iran 2020 only - Mar 20 24:00 1:00 - +Rule Iran 2020 only - Sep 20 24:00 0 - +Rule Iran 2021 2023 - Mar 21 24:00 1:00 - +Rule Iran 2021 2023 - Sep 21 24:00 0 - +Rule Iran 2024 only - Mar 20 24:00 1:00 - +Rule Iran 2024 only - Sep 20 24:00 0 - +Rule Iran 2025 2027 - Mar 21 24:00 1:00 - +Rule Iran 2025 2027 - Sep 21 24:00 0 - +Rule Iran 2028 2029 - Mar 20 24:00 1:00 - +Rule Iran 2028 2029 - Sep 20 24:00 0 - +Rule Iran 2030 2031 - Mar 21 24:00 1:00 - +Rule Iran 2030 2031 - Sep 21 24:00 0 - +Rule Iran 2032 2033 - Mar 20 24:00 1:00 - +Rule Iran 2032 2033 - Sep 20 24:00 0 - +Rule Iran 2034 2035 - Mar 21 24:00 1:00 - +Rule Iran 2034 2035 - Sep 21 24:00 0 - +Rule Iran 2036 2037 - Mar 20 24:00 1:00 - +Rule Iran 2036 2037 - Sep 20 24:00 0 - +Rule Iran 2038 2039 - Mar 21 24:00 1:00 - +Rule Iran 2038 2039 - Sep 21 24:00 0 - +Rule Iran 2040 2041 - Mar 20 24:00 1:00 - +Rule Iran 2040 2041 - Sep 20 24:00 0 - +Rule Iran 2042 2043 - Mar 21 24:00 1:00 - +Rule Iran 2042 2043 - Sep 21 24:00 0 - +Rule Iran 2044 2045 - Mar 20 24:00 1:00 - +Rule Iran 2044 2045 - Sep 20 24:00 0 - +Rule Iran 2046 2047 - Mar 21 24:00 1:00 - +Rule Iran 2046 2047 - Sep 21 24:00 0 - +Rule Iran 2048 2049 - Mar 20 24:00 1:00 - +Rule Iran 2048 2049 - Sep 20 24:00 0 - +Rule Iran 2050 2051 - Mar 21 24:00 1:00 - +Rule Iran 2050 2051 - Sep 21 24:00 0 - +Rule Iran 2052 2053 - Mar 20 24:00 1:00 - +Rule Iran 2052 2053 - Sep 20 24:00 0 - +Rule Iran 2054 2055 - Mar 21 24:00 1:00 - +Rule Iran 2054 2055 - Sep 21 24:00 0 - +Rule Iran 2056 2057 - Mar 20 24:00 1:00 - +Rule Iran 2056 2057 - Sep 20 24:00 0 - +Rule Iran 2058 2059 - Mar 21 24:00 1:00 - +Rule Iran 2058 2059 - Sep 21 24:00 0 - +Rule Iran 2060 2062 - Mar 20 24:00 1:00 - +Rule Iran 2060 2062 - Sep 20 24:00 0 - +Rule Iran 2063 only - Mar 21 24:00 1:00 - +Rule Iran 2063 only - Sep 21 24:00 0 - +Rule Iran 2064 2066 - Mar 20 24:00 1:00 - +Rule Iran 2064 2066 - Sep 20 24:00 0 - +Rule Iran 2067 only - Mar 21 24:00 1:00 - +Rule Iran 2067 only - Sep 21 24:00 0 - +Rule Iran 2068 2070 - Mar 20 24:00 1:00 - +Rule Iran 2068 2070 - Sep 20 24:00 0 - +Rule Iran 2071 only - Mar 21 24:00 1:00 - +Rule Iran 2071 only - Sep 21 24:00 0 - +Rule Iran 2072 2074 - Mar 20 24:00 1:00 - +Rule Iran 2072 2074 - Sep 20 24:00 0 - +Rule Iran 2075 only - Mar 21 24:00 1:00 - +Rule Iran 2075 only - Sep 21 24:00 0 - +Rule Iran 2076 2078 - Mar 20 24:00 1:00 - +Rule Iran 2076 2078 - Sep 20 24:00 0 - +Rule Iran 2079 only - Mar 21 24:00 1:00 - +Rule Iran 2079 only - Sep 21 24:00 0 - +Rule Iran 2080 2082 - Mar 20 24:00 1:00 - +Rule Iran 2080 2082 - Sep 20 24:00 0 - +Rule Iran 2083 only - Mar 21 24:00 1:00 - +Rule Iran 2083 only - Sep 21 24:00 0 - +Rule Iran 2084 2086 - Mar 20 24:00 1:00 - +Rule Iran 2084 2086 - Sep 20 24:00 0 - +Rule Iran 2087 only - Mar 21 24:00 1:00 - +Rule Iran 2087 only - Sep 21 24:00 0 - # -# The following rules are approximations starting in the year 2038. -# These are the best post-2037 approximations available, given the -# restrictions of a single rule using a Gregorian-based data format. +# The following rules are approximations starting in the year 2088. +# These are the best post-2088 approximations available, given the +# restrictions of a single rule using ordinary Gregorian dates. # At some point this table will need to be extended, though quite # possibly Iran will change the rules first. -Rule Iran 2036 max - Mar 21 0:00 1:00 - -Rule Iran 2036 max - Sep 21 0:00 0 - +Rule Iran 2088 max - Mar 20 24:00 1:00 - +Rule Iran 2088 max - Sep 20 24:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Tehran 3:25:44 - LMT 1916 3:25:44 - TMT 1946 # Tehran Mean Time 3:30 - +0330 1977 Nov @@ -1379,7 +1699,7 @@ # We have published a short article in English about the change: # https://www.timeanddate.com/news/time/iraq-dumps-daylight-saving.html -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Iraq 1982 only - May 1 0:00 1:00 - Rule Iraq 1982 1984 - Oct 1 0:00 0 - Rule Iraq 1983 only - Mar 31 0:00 1:00 - @@ -1391,7 +1711,7 @@ # Rule Iraq 1991 2007 - Apr 1 3:00s 1:00 - Rule Iraq 1991 2007 - Oct 1 3:00s 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Baghdad 2:57:40 - LMT 1890 2:57:36 - BMT 1918 # Baghdad Mean Time? 3:00 - +03 1982 May @@ -1402,6 +1722,10 @@ # Israel +# For more info about the motivation for DST in Israel, see: +# Barak Y. Israel's Daylight Saving Time controversy. Israel Affairs. +# 2020-08-11. https://doi.org/10.1080/13537121.2020.1806564 + # From Ephraim Silverberg (2001-01-11): # # I coined "IST/IDT" circa 1988. Until then there were three @@ -1422,53 +1746,210 @@ # high on my favorite-country list (and not only because my wife's # family is from India). -# From Shanks & Pottenger: -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -Rule Zion 1940 only - Jun 1 0:00 1:00 D -Rule Zion 1942 1944 - Nov 1 0:00 0 S -Rule Zion 1943 only - Apr 1 2:00 1:00 D -Rule Zion 1944 only - Apr 1 0:00 1:00 D -Rule Zion 1945 only - Apr 16 0:00 1:00 D -Rule Zion 1945 only - Nov 1 2:00 0 S -Rule Zion 1946 only - Apr 16 2:00 1:00 D -Rule Zion 1946 only - Nov 1 0:00 0 S -Rule Zion 1948 only - May 23 0:00 2:00 DD -Rule Zion 1948 only - Sep 1 0:00 1:00 D -Rule Zion 1948 1949 - Nov 1 2:00 0 S -Rule Zion 1949 only - May 1 0:00 1:00 D -Rule Zion 1950 only - Apr 16 0:00 1:00 D -Rule Zion 1950 only - Sep 15 3:00 0 S -Rule Zion 1951 only - Apr 1 0:00 1:00 D -Rule Zion 1951 only - Nov 11 3:00 0 S -Rule Zion 1952 only - Apr 20 2:00 1:00 D -Rule Zion 1952 only - Oct 19 3:00 0 S -Rule Zion 1953 only - Apr 12 2:00 1:00 D -Rule Zion 1953 only - Sep 13 3:00 0 S -Rule Zion 1954 only - Jun 13 0:00 1:00 D -Rule Zion 1954 only - Sep 12 0:00 0 S -Rule Zion 1955 only - Jun 11 2:00 1:00 D -Rule Zion 1955 only - Sep 11 0:00 0 S -Rule Zion 1956 only - Jun 3 0:00 1:00 D -Rule Zion 1956 only - Sep 30 3:00 0 S -Rule Zion 1957 only - Apr 29 2:00 1:00 D -Rule Zion 1957 only - Sep 22 0:00 0 S -Rule Zion 1974 only - Jul 7 0:00 1:00 D -Rule Zion 1974 only - Oct 13 0:00 0 S -Rule Zion 1975 only - Apr 20 0:00 1:00 D -Rule Zion 1975 only - Aug 31 0:00 0 S -Rule Zion 1985 only - Apr 14 0:00 1:00 D -Rule Zion 1985 only - Sep 15 0:00 0 S -Rule Zion 1986 only - May 18 0:00 1:00 D -Rule Zion 1986 only - Sep 7 0:00 0 S -Rule Zion 1987 only - Apr 15 0:00 1:00 D -Rule Zion 1987 only - Sep 13 0:00 0 S +# From P Chan (2020-10-27), with corrections: +# +# 1940-1946 Supplement No. 2 to the Palestine Gazette +# # issue page Order No. dated start end note +# 1 1010 729 67 of 1940 1940-05-22 1940-05-31* 1940-09-30* revoked by #2 +# 2 1013 758 73 of 1940 1940-05-31 1940-05-31 1940-09-30 +# 3 1055 1574 196 of 1940 1940-11-06 1940-11-16 1940-12-31 +# 4 1066 1811 208 of 1940 1940-12-17 1940-12-31 1941-12-31 +# 5 1156 1967 116 of 1941 1941-12-16 1941-12-31 1942-12-31* amended by #6 +# 6 1228 1608 86 of 1942 1942-10-14 1941-12-31 1942-10-31 +# 7 1256 279 21 of 1943 1943-03-18 1943-03-31 1943-10-31 +# 8 1323 249 19 of 1944 1944-03-13 1944-03-31 1944-10-31 +# 9 1402 328 20 of 1945 1945-04-05 1945-04-15 1945-10-31 +#10 1487 596 14 of 1946 1946-04-04 1946-04-15 1946-10-31 +# +# 1948 Iton Rishmi (Official Gazette of the Provisional Government) +# # issue page dated start end +#11 2 7 1948-05-20 1948-05-22 1948-10-31* +# ^This moved timezone to +04, replaced by #12 from 1948-08-31 24:00 GMT. +#12 17 (Annex B) 84 1948-08-22 1948-08-31 1948-10-31 +# +# 1949-2000 Kovetz HaTakanot (Collection of Regulations) +# # issue page dated start end note +#13 6 133 1949-03-23 1949-04-30 1949-10-31 +#14 80 755 1950-03-17 1950-04-15 1950-09-14 +#15 164 782 1951-03-22 1951-03-31 1951-09-29* amended by #16 +#16 206 1940 1951-09-23 ---------- 1951-10-22* amended by #17 +#17 212 78 1951-10-19 ---------- 1951-11-10 +#18 254 652 1952-03-03 1952-04-19 1952-09-27* amended by #19 +#19 300 11 1952-09-15 ---------- 1952-10-18 +#20 348 817 1953-03-03 1953-04-11 1953-09-12 +#21 420 385 1954-02-17 1954-06-12 1954-09-11 +#22 497 548 1955-01-14 1955-06-11 1955-09-10 +#23 591 608 1956-03-12 1956-06-02 1956-09-29 +#24 680 957 1957-02-08 1957-04-27 1957-09-21 +#25 3192 1418 1974-06-28 1974-07-06 1974-10-12 +#26 3322 1389 1975-04-03 1975-04-19 1975-08-30 +#27 4146 2089 1980-07-15 1980-08-02 1980-09-13 +#28 4604 1081 1984-02-22 1984-05-05* 1984-08-25* revoked by #29 +#29 4619 1312 1984-04-06 1984-05-05 1984-08-25 +#30 4744 475 1984-12-23 1985-04-13 1985-09-14* amended by #31 +#31 4851 1848 1985-08-18 ---------- 1985-08-31 +#32 4932 899 1986-04-22 1986-05-17 1986-09-06 +#33 5013 580 1987-02-15 1987-04-18* 1987-08-22* revoked by #34 +#34 5021 744 1987-03-30 1987-04-14 1987-09-12 +#35 5096 659 1988-02-14 1988-04-09 1988-09-03 +#36 5167 514 1989-02-03 1989-04-29 1989-09-02 +#37 5248 375 1990-01-23 1990-03-24 1990-08-25 +#38 5335 612 1991-02-10 1991-03-09* 1991-08-31 amended by #39 +# 1992-03-28 1992-09-05 +#39 5339 709 1991-03-04 1991-03-23 ---------- +#40 5506 503 1993-02-18 1993-04-02 1993-09-05 +# 1994-04-01 1994-08-28 +# 1995-03-31 1995-09-03 +#41 5731 438 1996-01-01 1996-03-14 1996-09-15 +# 1997-03-13* 1997-09-18* overridden by 1997 Temp Prov +# 1998-03-19* 1998-09-17* revoked by #42 +#42 5853 1243 1997-09-18 1998-03-19 1998-09-05 +#43 5937 77 1998-10-18 1999-04-02 1999-09-03 +# 2000-04-14* 2000-09-15* revoked by #44 +# 2001-04-13* 2001-09-14* revoked by #44 +#44 6024 39 2000-03-14 2000-04-14 2000-10-22* overridden by 2000 Temp Prov +# 2001-04-06* 2001-10-10* overridden by 2000 Temp Prov +# 2002-03-29* 2002-10-29* overridden by 2000 Temp Prov +# +# These are laws enacted by the Knesset since the Minister could only alter the +# transition dates at least six months in advanced under the 1992 Law. +# dated start end +# 1997 Temporary Provisions 1997-03-06 1997-03-20 1997-09-13 +# 2000 Temporary Provisions 2000-07-28 ---------- 2000-10-06 +# 2001-04-09 2001-09-24 +# 2002-03-29 2002-10-07 +# 2003-03-28 2003-10-03 +# 2004-04-07 2004-09-22 +# Note: +# Transition times in 1940-1957 (#1-#24) were midnight GMT, +# in 1974-1998 (#25-#42 and the 1997 Temporary Provisions) were midnight, +# in 1999-April 2000 (#43,#44) were 02:00, +# in the 2000 Temporary Provisions were 01:00. +# +# ----------------------------------------------------------------------------- +# Links: +# 1 https://findit.library.yale.edu/images_layout/view?parentoid=15537490&increment=687 +# 2 https://findit.library.yale.edu/images_layout/view?parentoid=15537490&increment=716 +# 3 https://findit.library.yale.edu/images_layout/view?parentoid=15537491&increment=721 +# 4 https://findit.library.yale.edu/images_layout/view?parentoid=15537491&increment=958 +# 5 https://findit.library.yale.edu/images_layout/view?parentoid=15537502&increment=558 +# 6 https://findit.library.yale.edu/images_layout/view?parentoid=15537511&increment=105 +# 7 https://findit.library.yale.edu/images_layout/view?parentoid=15537516&increment=278 +# 8 https://findit.library.yale.edu/images_layout/view?parentoid=15537522&increment=248 +# 9 https://findit.library.yale.edu/images_layout/view?parentoid=15537530&increment=329 +#10 https://findit.library.yale.edu/images_layout/view?parentoid=15537537&increment=601 +#11 https://www.nevo.co.il/law_word/law12/er-002.pdf#page=3 +#12 https://www.nevo.co.il/law_word/law12/er-017-t2.pdf#page=4 +#13 https://www.nevo.co.il/law_word/law06/tak-0006.pdf#page=3 +#14 https://www.nevo.co.il/law_word/law06/tak-0080.pdf#page=7 +#15 https://www.nevo.co.il/law_word/law06/tak-0164.pdf#page=10 +#16 https://www.nevo.co.il/law_word/law06/tak-0206.pdf#page=4 +#17 https://www.nevo.co.il/law_word/law06/tak-0212.pdf#page=2 +#18 https://www.nevo.co.il/law_word/law06/tak-0254.pdf#page=4 +#19 https://www.nevo.co.il/law_word/law06/tak-0300.pdf#page=5 +#20 https://www.nevo.co.il/law_word/law06/tak-0348.pdf#page=3 +#21 https://www.nevo.co.il/law_word/law06/tak-0420.pdf#page=5 +#22 https://www.nevo.co.il/law_word/law06/tak-0497.pdf#page=10 +#23 https://www.nevo.co.il/law_word/law06/tak-0591.pdf#page=6 +#24 https://www.nevo.co.il/law_word/law06/tak-0680.pdf#page=3 +#25 https://www.nevo.co.il/law_word/law06/tak-3192.pdf#page=2 +#26 https://www.nevo.co.il/law_word/law06/tak-3322.pdf#page=5 +#27 https://www.nevo.co.il/law_word/law06/tak-4146.pdf#page=2 +#28 https://www.nevo.co.il/law_word/law06/tak-4604.pdf#page=7 +#29 https://www.nevo.co.il/law_word/law06/tak-4619.pdf#page=2 +#30 https://www.nevo.co.il/law_word/law06/tak-4744.pdf#page=11 +#31 https://www.nevo.co.il/law_word/law06/tak-4851.pdf#page=2 +#32 https://www.nevo.co.il/law_word/law06/tak-4932.pdf#page=19 +#33 https://www.nevo.co.il/law_word/law06/tak-5013.pdf#page=8 +#34 https://www.nevo.co.il/law_word/law06/tak-5021.pdf#page=8 +#35 https://www.nevo.co.il/law_word/law06/tak-5096.pdf#page=3 +#36 https://www.nevo.co.il/law_word/law06/tak-5167.pdf#page=2 +#37 https://www.nevo.co.il/law_word/law06/tak-5248.pdf#page=7 +#38 https://www.nevo.co.il/law_word/law06/tak-5335.pdf#page=6 +#39 https://www.nevo.co.il/law_word/law06/tak-5339.pdf#page=7 +#40 https://www.nevo.co.il/law_word/law06/tak-5506.pdf#page=19 +#41 https://www.nevo.co.il/law_word/law06/tak-5731.pdf#page=2 +#42 https://www.nevo.co.il/law_word/law06/tak-5853.pdf#page=3 +#43 https://www.nevo.co.il/law_word/law06/tak-5937.pdf#page=9 +#44 https://www.nevo.co.il/law_word/law06/tak-6024.pdf#page=4 +# +# Time Determination (Temporary Provisions) Law, 1997 +# https://www.nevo.co.il/law_html/law19/p201_003.htm +# +# Time Determination (Temporary Provisions) Law, 2000 +# https://www.nevo.co.il/law_html/law19/p201_004.htm +# +# Time Determination Law, 1992 and amendments +# https://www.nevo.co.il/law_html/law01/p201_002.htm +# https://main.knesset.gov.il/Activity/Legislation/Laws/Pages/LawPrimary.aspx?lawitemid=2001174 + +# From Paul Eggert (2020-10-27): +# Several of the midnight transitions mentioned above are ambiguous; +# are they 00:00, 00:00s, 24:00, or 24:00s? When resolving these ambiguities, +# try to minimize changes from previous tzdb versions, for lack of better info. +# Commentary from previous versions is included below, to help explain this. + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule Zion 1940 only - May 31 24:00u 1:00 D +Rule Zion 1940 only - Sep 30 24:00u 0 S +Rule Zion 1940 only - Nov 16 24:00u 1:00 D +Rule Zion 1942 1946 - Oct 31 24:00u 0 S +Rule Zion 1943 1944 - Mar 31 24:00u 1:00 D +Rule Zion 1945 1946 - Apr 15 24:00u 1:00 D +Rule Zion 1948 only - May 22 24:00u 2:00 DD +Rule Zion 1948 only - Aug 31 24:00u 1:00 D +Rule Zion 1948 1949 - Oct 31 24:00u 0 S +Rule Zion 1949 only - Apr 30 24:00u 1:00 D +Rule Zion 1950 only - Apr 15 24:00u 1:00 D +Rule Zion 1950 only - Sep 14 24:00u 0 S +Rule Zion 1951 only - Mar 31 24:00u 1:00 D +Rule Zion 1951 only - Nov 10 24:00u 0 S +Rule Zion 1952 only - Apr 19 24:00u 1:00 D +Rule Zion 1952 only - Oct 18 24:00u 0 S +Rule Zion 1953 only - Apr 11 24:00u 1:00 D +Rule Zion 1953 only - Sep 12 24:00u 0 S +Rule Zion 1954 only - Jun 12 24:00u 1:00 D +Rule Zion 1954 only - Sep 11 24:00u 0 S +Rule Zion 1955 only - Jun 11 24:00u 1:00 D +Rule Zion 1955 only - Sep 10 24:00u 0 S +Rule Zion 1956 only - Jun 2 24:00u 1:00 D +Rule Zion 1956 only - Sep 29 24:00u 0 S +Rule Zion 1957 only - Apr 27 24:00u 1:00 D +Rule Zion 1957 only - Sep 21 24:00u 0 S +Rule Zion 1974 only - Jul 6 24:00 1:00 D +Rule Zion 1974 only - Oct 12 24:00 0 S +Rule Zion 1975 only - Apr 19 24:00 1:00 D +Rule Zion 1975 only - Aug 30 24:00 0 S + +# From Alois Treindl (2019-03-06): +# http://www.moin.gov.il/Documents/שעון%20קיץ/clock-50-years-7-2014.pdf +# From Isaac Starkman (2019-03-06): +# Summer time was in that period in 1980 and 1984, see +# https://www.ynet.co.il/articles/0,7340,L-3951073,00.html +# You can of course read it in translation. +# I checked the local newspapers for that years. +# It started on midnight and end at 01.00 am. +# From Paul Eggert (2019-03-06): +# Also see this thread about the moin.gov.il URL: +# https://mm.icann.org/pipermail/tz/2018-November/027194.html +Rule Zion 1980 only - Aug 2 24:00s 1:00 D +Rule Zion 1980 only - Sep 13 24:00s 0 S +Rule Zion 1984 only - May 5 24:00s 1:00 D +Rule Zion 1984 only - Aug 25 24:00s 0 S + +Rule Zion 1985 only - Apr 13 24:00 1:00 D +Rule Zion 1985 only - Aug 31 24:00 0 S +Rule Zion 1986 only - May 17 24:00 1:00 D +Rule Zion 1986 only - Sep 6 24:00 0 S +Rule Zion 1987 only - Apr 14 24:00 1:00 D +Rule Zion 1987 only - Sep 12 24:00 0 S # From Avigdor Finkelstein (2014-03-05): # I check the Parliament (Knesset) records and there it's stated that the # [1988] transition should take place on Saturday night, when the Sabbath # ends and changes to Sunday. -Rule Zion 1988 only - Apr 10 0:00 1:00 D -Rule Zion 1988 only - Sep 4 0:00 0 S +Rule Zion 1988 only - Apr 9 24:00 1:00 D +Rule Zion 1988 only - Sep 3 24:00 0 S # From Ephraim Silverberg # (1997-03-04, 1998-03-16, 1998-12-28, 2000-01-17, 2000-07-25, 2004-12-22, @@ -1497,15 +1978,15 @@ # (except in 2002) is three nights before Yom Kippur [Day of Atonement] # (the eve of the 7th of Tishrei in the lunar Hebrew calendar). -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -Rule Zion 1989 only - Apr 30 0:00 1:00 D -Rule Zion 1989 only - Sep 3 0:00 0 S -Rule Zion 1990 only - Mar 25 0:00 1:00 D -Rule Zion 1990 only - Aug 26 0:00 0 S -Rule Zion 1991 only - Mar 24 0:00 1:00 D -Rule Zion 1991 only - Sep 1 0:00 0 S -Rule Zion 1992 only - Mar 29 0:00 1:00 D -Rule Zion 1992 only - Sep 6 0:00 0 S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule Zion 1989 only - Apr 29 24:00 1:00 D +Rule Zion 1989 only - Sep 2 24:00 0 S +Rule Zion 1990 only - Mar 24 24:00 1:00 D +Rule Zion 1990 only - Aug 25 24:00 0 S +Rule Zion 1991 only - Mar 23 24:00 1:00 D +Rule Zion 1991 only - Aug 31 24:00 0 S +Rule Zion 1992 only - Mar 28 24:00 1:00 D +Rule Zion 1992 only - Sep 5 24:00 0 S Rule Zion 1993 only - Apr 2 0:00 1:00 D Rule Zion 1993 only - Sep 5 0:00 0 S @@ -1513,7 +1994,7 @@ # Ministry of Interior, Jerusalem, Israel. The spokeswoman can be reached by # calling the office directly at 972-2-6701447 or 972-2-6701448. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Zion 1994 only - Apr 1 0:00 1:00 D Rule Zion 1994 only - Aug 28 0:00 0 S Rule Zion 1995 only - Mar 31 0:00 1:00 D @@ -1533,11 +2014,11 @@ # # where YYYY is the relevant year. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -Rule Zion 1996 only - Mar 15 0:00 1:00 D -Rule Zion 1996 only - Sep 16 0:00 0 S -Rule Zion 1997 only - Mar 21 0:00 1:00 D -Rule Zion 1997 only - Sep 14 0:00 0 S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule Zion 1996 only - Mar 14 24:00 1:00 D +Rule Zion 1996 only - Sep 15 24:00 0 S +Rule Zion 1997 only - Mar 20 24:00 1:00 D +Rule Zion 1997 only - Sep 13 24:00 0 S Rule Zion 1998 only - Mar 20 0:00 1:00 D Rule Zion 1998 only - Sep 6 0:00 0 S Rule Zion 1999 only - Apr 2 2:00 1:00 D @@ -1556,7 +2037,7 @@ # # ftp://ftp.cs.huji.ac.il/pub/tz/announcements/2000-2004.ps.gz -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Zion 2000 only - Apr 14 2:00 1:00 D Rule Zion 2000 only - Oct 6 1:00 0 S Rule Zion 2001 only - Apr 9 1:00 1:00 D @@ -1578,48 +2059,32 @@ # # ftp://ftp.cs.huji.ac.il/pub/tz/announcements/2005+beyond.ps -# From Paul Eggert (2012-10-26): -# I used Ephraim Silverberg's dst-israel.el program -# <ftp://ftp.cs.huji.ac.il/pub/tz/software/dst-israel.el> (2005-02-20) -# along with Ed Reingold's cal-hebrew in GNU Emacs 21.4, -# to generate the transitions from 2005 through 2012. -# (I replaced "lastFri" with "Fri>=26" by hand.) -# The spring transitions all correspond to the following Rule: -# -# Rule Zion 2005 2012 - Mar Fri>=26 2:00 1:00 D -# -# but older zic implementations (e.g., Solaris 8) do not support -# "Fri>=26" to mean April 1 in years like 2005, so for now we list the -# springtime transitions explicitly. - -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -Rule Zion 2005 only - Apr 1 2:00 1:00 D +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule Zion 2005 2012 - Apr Fri<=1 2:00 1:00 D Rule Zion 2005 only - Oct 9 2:00 0 S -Rule Zion 2006 2010 - Mar Fri>=26 2:00 1:00 D Rule Zion 2006 only - Oct 1 2:00 0 S Rule Zion 2007 only - Sep 16 2:00 0 S Rule Zion 2008 only - Oct 5 2:00 0 S Rule Zion 2009 only - Sep 27 2:00 0 S Rule Zion 2010 only - Sep 12 2:00 0 S -Rule Zion 2011 only - Apr 1 2:00 1:00 D Rule Zion 2011 only - Oct 2 2:00 0 S -Rule Zion 2012 only - Mar Fri>=26 2:00 1:00 D Rule Zion 2012 only - Sep 23 2:00 0 S -# From Ephraim Silverberg (2013-06-27): -# On June 23, 2013, the Israeli government approved changes to the -# Time Decree Law. The next day, the changes passed the First Reading -# in the Knesset. The law is expected to pass the Second and Third -# (final) Readings by the beginning of September 2013. -# -# As of 2013, DST starts at 02:00 on the Friday before the last Sunday -# in March. DST ends at 02:00 on the last Sunday of October. +# From Ephraim Silverberg (2020-10-26): +# The current time law (2013) from the State of Israel can be viewed +# (in Hebrew) at: +# ftp://ftp.cs.huji.ac.il/pub/tz/israel/announcements/2013+law.pdf +# It translates to: +# Every year, in the period from the Friday before the last Sunday in +# the month of March at 02:00 a.m. until the last Sunday of the month +# of October at 02:00 a.m., Israel Time will be advanced an additional +# hour such that it will be UTC+3. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Zion 2013 max - Mar Fri>=23 2:00 1:00 D Rule Zion 2013 max - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Jerusalem 2:20:54 - LMT 1880 2:20:40 - JMT 1918 # Jerusalem Mean Time? 2:00 Zion I%sT @@ -1632,6 +2097,47 @@ # '9:00' and 'JST' is from Guy Harris. +# From Paul Eggert (2020-01-19): +# Starting in the 7th century, Japan generally followed an ancient Chinese +# timekeeping system that divided night and day into six hours each, +# with hour length depending on season. In 1873 the government +# started requiring the use of a Western style 24-hour clock. See: +# Yulia Frumer, "Making Time: Astronomical Time Measurement in Tokugawa Japan" +# <https://www.worldcat.org/oclc/1043907065>. As the tzdb code and +# data support only 24-hour clocks, its tables model timestamps before +# 1873 using Western-style local mean time. + +# From Hideyuki Suzuki (1998-11-09): +# 'Tokyo' usually stands for the former location of Tokyo Astronomical +# Observatory: 139° 44' 40.90" E (9h 18m 58.727s), 35° 39' 16.0" N. +# This data is from 'Rika Nenpyou (Chronological Scientific Tables) 1996' +# edited by National Astronomical Observatory of Japan.... +# JST (Japan Standard Time) has been used since 1888-01-01 00:00 (JST). +# The law is enacted on 1886-07-07. + +# From Hideyuki Suzuki (1998-11-16): +# The ordinance No. 51 (1886) established "standard time" in Japan, +# which stands for the time on 135° E. +# In the ordinance No. 167 (1895), "standard time" was renamed to "central +# standard time". And the same ordinance also established "western standard +# time", which stands for the time on 120° E.... But "western standard +# time" was abolished in the ordinance No. 529 (1937). In the ordinance No. +# 167, there is no mention regarding for what place western standard time is +# standard.... +# +# I wrote "ordinance" above, but I don't know how to translate. +# In Japanese it's "chokurei", which means ordinance from emperor. + +# From Yu-Cheng Chuang (2013-07-12): +# ...the Meiji Emperor announced Ordinance No. 167 of Meiji Year 28 "The clause +# about standard time" ... The adoption began from Jan 1, 1896. +# https://ja.wikisource.org/wiki/標準時ニ關スル件_(公布時) +# +# ...the Showa Emperor announced Ordinance No. 529 of Showa Year 12 ... which +# means the whole Japan territory, including later occupations, adopt Japan +# Central Time (UT+9). The adoption began on Oct 1, 1937. +# https://ja.wikisource.org/wiki/明治二十八年勅令第百六十七號標準時ニ關スル件中改正ノ件 + # From Paul Eggert (1995-03-06): # Today's _Asahi Evening News_ (page 4) reports that Japan had # daylight saving between 1948 and 1951, but "the system was discontinued @@ -1674,47 +2180,18 @@ # do in any POSIX or C platform. The "25:00" assumes zic from 2007 or later, # which should be safe now. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Japan 1948 only - May Sat>=1 24:00 1:00 D -Rule Japan 1948 1951 - Sep Sun>=9 1:00 0 S +Rule Japan 1948 1951 - Sep Sat>=8 25:00 0 S Rule Japan 1949 only - Apr Sat>=1 24:00 1:00 D Rule Japan 1950 1951 - May Sat>=1 24:00 1:00 D -# From Hideyuki Suzuki (1998-11-09): -# 'Tokyo' usually stands for the former location of Tokyo Astronomical -# Observatory: 139° 44' 40.90" E (9h 18m 58.727s), 35° 39' 16.0" N. -# This data is from 'Rika Nenpyou (Chronological Scientific Tables) 1996' -# edited by National Astronomical Observatory of Japan.... -# JST (Japan Standard Time) has been used since 1888-01-01 00:00 (JST). -# The law is enacted on 1886-07-07. - -# From Hideyuki Suzuki (1998-11-16): -# The ordinance No. 51 (1886) established "standard time" in Japan, -# which stands for the time on 135° E. -# In the ordinance No. 167 (1895), "standard time" was renamed to "central -# standard time". And the same ordinance also established "western standard -# time", which stands for the time on 120° E.... But "western standard -# time" was abolished in the ordinance No. 529 (1937). In the ordinance No. -# 167, there is no mention regarding for what place western standard time is -# standard.... -# -# I wrote "ordinance" above, but I don't know how to translate. -# In Japanese it's "chokurei", which means ordinance from emperor. - -# From Yu-Cheng Chuang (2013-07-12): -# ...the Meiji Emperor announced Ordinance No. 167 of Meiji Year 28 "The clause -# about standard time" ... The adoption began from Jan 1, 1896. -# https://ja.wikisource.org/wiki/標準時ニ關スル件_(公布時) -# -# ...the Showa Emperor announced Ordinance No. 529 of Showa Year 12 ... which -# means the whole Japan territory, including later occupations, adopt Japan -# Central Time (UT+9). The adoption began on Oct 1, 1937. -# https://ja.wikisource.org/wiki/明治二十八年勅令第百六十七號標準時ニ關スル件中改正ノ件 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Tokyo 9:18:59 - LMT 1887 Dec 31 15:00u 9:00 Japan J%sT -# Since 1938, all Japanese possessions have been like Asia/Tokyo. +# Since 1938, all Japanese possessions have been like Asia/Tokyo, +# except that Truk (Chuuk), Ponape (Pohnpei), and Jaluit (Kosrae) did not +# switch from +10 to +09 until 1941-04-01; see the 'australasia' file. # Jordan # @@ -1780,7 +2257,7 @@ # From Paul Eggert (2013-12-11): # As Steffen suggested, consider the past 21-month experiment to be DST. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Jordan 1973 only - Jun 6 0:00 1:00 S Rule Jordan 1973 1975 - Oct 1 0:00 0 - Rule Jordan 1974 1977 - May 1 0:00 1:00 S @@ -1812,7 +2289,7 @@ Rule Jordan 2013 only - Dec 20 0:00 0 - Rule Jordan 2014 max - Mar lastThu 24:00 1:00 S Rule Jordan 2014 max - Oct lastFri 0:00s 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Amman 2:23:44 - LMT 1931 2:00 Jordan EE%sT @@ -1853,8 +2330,8 @@ # text. # # According to Izvestia newspaper No. 68 (23334) from 1991-03-20 -# (page 6; available at http://libinfo.org/newsr/newsr2574.djvu via -# http://libinfo.org/index.php?id=58564) on 1991-03-31 at 2:00 during +# -- page 6; available at http://libinfo.org/newsr/newsr2574.djvu via +# http://libinfo.org/index.php?id=58564 -- on 1991-03-31 at 2:00 during # transition to "summer" time: # Republic of Georgia, Latvian SSR, Lithuanian SSR, SSR Moldova, # Estonian SSR; Komi ASSR; Kaliningrad oblast; Nenets autonomous okrug @@ -1870,7 +2347,7 @@ # Apparently there were last minute changes. Apparently Kazakh act No. 170 # was one of such changes. # -# https://ru.wikipedia.org/wiki/Декретное время +# https://ru.wikipedia.org/wiki/Декретное_время # claims that Sovetskaya Rossiya newspaper on 1991-03-29 published that # Nenets autonomous okrug, Komi and Kazakhstan (excluding Uralsk oblast) # were to not move clocks and Uralsk oblast was to move clocks @@ -2004,10 +2481,12 @@ # and in Byalokoz) lists Ural river (plus 10 versts on its left bank) in # the third time belt (before 1930 this means +03). -# From Paul Eggert (2016-12-06): -# The tables below reflect Golosunov's remarks, with exceptions as noted. +# From Alexander Konzurovski (2018-12-20): +# Qyzyolrda Region (Asia/Qyzylorda) is changing its time zone from +# UTC+6 to UTC+5 effective December 21st, 2018. The legal document is +# located here: http://adilet.zan.kz/rus/docs/P1800000817 (russian language). -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] # # Almaty (formerly Alma-Ata), representing most locations in Kazakhstan # This includes KZ-AKM, KZ-ALA, KZ-ALM, KZ-AST, KZ-BAY, KZ-VOS, KZ-ZHA, @@ -2019,8 +2498,6 @@ 6:00 RussiaAsia +06/+07 2004 Oct 31 2:00s 6:00 - +06 # Qyzylorda (aka Kyzylorda, Kizilorda, Kzyl-Orda, etc.) (KZ-KZY) -# This currently includes Qostanay (aka Kostanay, Kustanay) (KZ-KUS); -# see comments below. Zone Asia/Qyzylorda 4:21:52 - LMT 1924 May 2 4:00 - +04 1930 Jun 21 5:00 - +05 1981 Apr 1 @@ -2031,21 +2508,22 @@ 5:00 RussiaAsia +05/+06 1992 Jan 19 2:00s 6:00 RussiaAsia +06/+07 1992 Mar 29 2:00s 5:00 RussiaAsia +05/+06 2004 Oct 31 2:00s - 6:00 - +06 -# The following zone is like Asia/Qyzylorda except for being one -# hour earlier from 1991-09-29 to 1992-03-29. The 1991/2 rules for -# Qostanay are unclear partly because of the 1997 Turgai -# reorganization, so this zone is commented out for now. -#Zone Asia/Qostanay 4:14:20 - LMT 1924 May 2 -# 4:00 - +04 1930 Jun 21 -# 5:00 - +05 1981 Apr 1 -# 5:00 1:00 +06 1981 Oct 1 -# 6:00 - +06 1982 Apr 1 -# 5:00 RussiaAsia +05/+06 1991 Mar 31 2:00s -# 4:00 RussiaAsia +04/+05 1992 Jan 19 2:00s -# 5:00 RussiaAsia +05/+06 2004 Oct 31 2:00s -# 6:00 - +06 + 6:00 - +06 2018 Dec 21 0:00 + 5:00 - +05 # +# Qostanay (aka Kostanay, Kustanay) (KZ-KUS) +# The 1991/2 rules are unclear partly because of the 1997 Turgai +# reorganization. +Zone Asia/Qostanay 4:14:28 - LMT 1924 May 2 + 4:00 - +04 1930 Jun 21 + 5:00 - +05 1981 Apr 1 + 5:00 1:00 +06 1981 Oct 1 + 6:00 - +06 1982 Apr 1 + 5:00 RussiaAsia +05/+06 1991 Mar 31 2:00s + 4:00 RussiaAsia +04/+05 1992 Jan 19 2:00s + 5:00 RussiaAsia +05/+06 2004 Oct 31 2:00s + 6:00 - +06 + # Aqtöbe (aka Aktobe, formerly Aktyubinsk) (KZ-AKT) Zone Asia/Aqtobe 3:48:40 - LMT 1924 May 2 4:00 - +04 1930 Jun 21 @@ -2105,12 +2583,12 @@ # Our government cancels daylight saving time 6th of August 2005. # From 2005-08-12 our GMT-offset is +6, w/o any daylight saving. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Kyrgyz 1992 1996 - Apr Sun>=7 0:00s 1:00 - Rule Kyrgyz 1992 1996 - Sep lastSun 0:00 0 - Rule Kyrgyz 1997 2005 - Mar lastSun 2:30 1:00 - Rule Kyrgyz 1997 2004 - Oct lastSun 2:30 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Bishkek 4:58:24 - LMT 1924 May 2 5:00 - +05 1930 Jun 21 6:00 RussiaAsia +06/+07 1991 Mar 31 2:00s @@ -2139,21 +2617,43 @@ # started at June 1 in that year. For another example, the article in # 1988 said that DST started at 2:00 AM in that year. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -Rule ROK 1948 only - Jun 1 0:00 1:00 D -Rule ROK 1948 only - Sep 13 0:00 0 S -Rule ROK 1949 only - Apr 3 0:00 1:00 D -Rule ROK 1949 1951 - Sep Sun>=8 0:00 0 S -Rule ROK 1950 only - Apr 1 0:00 1:00 D -Rule ROK 1951 only - May 6 0:00 1:00 D -Rule ROK 1955 only - May 5 0:00 1:00 D -Rule ROK 1955 only - Sep 9 0:00 0 S -Rule ROK 1956 only - May 20 0:00 1:00 D -Rule ROK 1956 only - Sep 30 0:00 0 S -Rule ROK 1957 1960 - May Sun>=1 0:00 1:00 D -Rule ROK 1957 1960 - Sep Sun>=18 0:00 0 S -Rule ROK 1987 1988 - May Sun>=8 2:00 1:00 D -Rule ROK 1987 1988 - Oct Sun>=8 3:00 0 S +# From Phake Nick (2018-10-27): +# 1. According to official announcement from Korean government, the DST end +# date in South Korea should be +# 1955-09-08 without specifying time +# http://theme.archives.go.kr/next/common/viewEbook.do?singleData=N&archiveEventId=0027977557 +# 1956-09-29 without specifying time +# http://theme.archives.go.kr/next/common/viewEbook.do?singleData=N&archiveEventId=0027978341 +# 1957-09-21 24 o'clock +# http://theme.archives.go.kr/next/common/viewEbook.do?singleData=N&archiveEventId=0027979690#3 +# 1958-09-20 24 o'clock +# http://theme.archives.go.kr/next/common/viewEbook.do?singleData=N&archiveEventId=0027981189 +# 1959-09-19 24 o'clock +# http://theme.archives.go.kr/next/common/viewEbook.do?singleData=N&archiveEventId=0027982974#2 +# 1960-09-17 24 o'clock +# http://theme.archives.go.kr/next/common/viewEbook.do?singleData=N&archiveEventId=0028044104 +# ... +# 2.... https://namu.wiki/w/대한민국%20표준시 ... [says] +# when Korea was using GMT+8:30 as standard time, the international +# aviation/marine/meteorological industry in the country refused to +# follow and continued to use GMT+9:00 for interoperability. + + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule ROK 1948 only - Jun 1 0:00 1:00 D +Rule ROK 1948 only - Sep 12 24:00 0 S +Rule ROK 1949 only - Apr 3 0:00 1:00 D +Rule ROK 1949 1951 - Sep Sat>=7 24:00 0 S +Rule ROK 1950 only - Apr 1 0:00 1:00 D +Rule ROK 1951 only - May 6 0:00 1:00 D +Rule ROK 1955 only - May 5 0:00 1:00 D +Rule ROK 1955 only - Sep 8 24:00 0 S +Rule ROK 1956 only - May 20 0:00 1:00 D +Rule ROK 1956 only - Sep 29 24:00 0 S +Rule ROK 1957 1960 - May Sun>=1 0:00 1:00 D +Rule ROK 1957 1960 - Sep Sat>=17 24:00 0 S +Rule ROK 1987 1988 - May Sun>=8 2:00 1:00 D +Rule ROK 1987 1988 - Oct Sun>=8 3:00 0 S # From Paul Eggert (2016-08-23): # The Korean Wikipedia entry gives the following sources for UT offsets: @@ -2203,11 +2703,11 @@ # The BBC reported that the transition was from 23:30 to 24:00 today. # https://www.bbc.com/news/world-asia-44010705 -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Seoul 8:27:52 - LMT 1908 Apr 1 8:30 - KST 1912 Jan 1 9:00 - JST 1945 Sep 8 - 9:00 - KST 1954 Mar 21 + 9:00 ROK K%sT 1954 Mar 21 8:30 ROK K%sT 1961 Aug 10 9:00 ROK K%sT Zone Asia/Pyongyang 8:23:00 - LMT 1908 Apr 1 @@ -2227,7 +2727,7 @@ # Lebanon -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Lebanon 1920 only - Mar 28 0:00 1:00 S Rule Lebanon 1920 only - Oct 25 0:00 0 - Rule Lebanon 1921 only - Apr 3 0:00 1:00 S @@ -2252,19 +2752,19 @@ Rule Lebanon 1993 max - Mar lastSun 0:00 1:00 S Rule Lebanon 1993 1998 - Sep lastSun 0:00 0 - Rule Lebanon 1999 max - Oct lastSun 0:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Beirut 2:22:00 - LMT 1880 2:00 Lebanon EE%sT # Malaysia -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule NBorneo 1935 1941 - Sep 14 0:00 0:20 - Rule NBorneo 1935 1941 - Dec 14 0:00 0 - # # peninsular Malaysia # taken from Mok Ly Yng (2003-10-30) # http://www.math.nus.edu.sg/aslaksen/teaching/timezone.html -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Kuala_Lumpur 6:46:46 - LMT 1901 Jan 1 6:55:25 - SMT 1905 Jun 1 # Singapore M.T. 7:00 - +07 1933 Jan 1 @@ -2278,7 +2778,7 @@ # From Paul Eggert (2014-08-12): # The data entries here are mostly from Shanks & Pottenger, but the 1942, 1945 # and 1982 transition dates are from Mok Ly Yng. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Kuching 7:21:20 - LMT 1926 Mar 7:30 - +0730 1933 8:00 NBorneo +08/+0820 1942 Feb 16 @@ -2286,7 +2786,7 @@ 8:00 - +08 # Maldives -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Indian/Maldives 4:54:00 - LMT 1880 # Malé 4:54:00 - MMT 1960 # Malé Mean Time 5:00 - +05 @@ -2402,7 +2902,7 @@ # September daylight saving time ends. Source: # http://zasag.mn/news/view/8969 -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Mongol 1983 1984 - Apr 1 0:00 1:00 - Rule Mongol 1983 only - Oct 1 0:00 0 - # Shanks & Pottenger and IATA SSIM say 1990s switches occurred at 00:00, @@ -2429,7 +2929,7 @@ Rule Mongol 2015 2016 - Mar lastSat 2:00 1:00 - Rule Mongol 2015 2016 - Sep lastSat 0:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] # Hovd, a.k.a. Chovd, Dund-Us, Dzhargalant, Khovd, Jirgalanta Zone Asia/Hovd 6:06:36 - LMT 1905 Aug 6:00 - +06 1978 @@ -2447,7 +2947,7 @@ 8:00 Mongol +08/+09 # Nepal -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Kathmandu 5:41:16 - LMT 1920 5:30 - +0530 1986 5:45 - +0545 @@ -2590,14 +3090,14 @@ # "People laud PM's announcement to end DST" # http://www.app.com.pk/en_/index.php?option=com_content&task=view&id=99374&Itemid=2 -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Pakistan 2002 only - Apr Sun>=2 0:00 1:00 S Rule Pakistan 2002 only - Oct Sun>=2 0:00 0 - Rule Pakistan 2008 only - Jun 1 0:00 1:00 S Rule Pakistan 2008 2009 - Nov 1 0:00 0 - Rule Pakistan 2009 only - Apr 15 0:00 1:00 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Karachi 4:28:12 - LMT 1907 5:30 - +0530 1942 Sep 5:30 1:00 +0630 1945 Oct 15 @@ -2865,28 +3365,61 @@ # [T]he Palestinian cabinet decision (Mar 8th 2016) published on # http://www.palestinecabinet.gov.ps/WebSite/Upload/Decree/GOV_17/16032016134830.pdf # states that summer time will end on Oct 29th at 01:00. -# -# From Tim Parenti (2016-10-19): -# Predict fall transitions on October's last Saturday at 01:00 from now on. -# This is consistent with the 2016 transition as well as our spring -# predictions. -# -# From Paul Eggert (2016-10-19): -# It's also consistent with predictions in the following URLs today: -# https://www.timeanddate.com/time/change/gaza-strip/gaza -# https://www.timeanddate.com/time/change/west-bank/hebron # From Sharef Mustafa (2018-03-16): -# Palestine summer time will start on Mar 24th 2018 by advancing the -# clock by 60 minutes as per Palestinian cabinet decision published on -# the official website, though the decree did not specify the exact -# time of the time shift. +# Palestine summer time will start on Mar 24th 2018 ... # http://www.palestinecabinet.gov.ps/Website/AR/NDecrees/ViewFile.ashx?ID=e7a42ab7-ee23-435a-b9c8-a4f7e81f3817 -# -# From Paul Eggert (2018-03-16): -# For 2016 on, predict spring transitions on March's fourth Saturday at 01:00. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# From Even Scharning (2019-03-23): +# http://pnn.ps/news/401130 +# http://palweather.ps/ar/node/50136.html +# +# From Sharif Mustafa (2019-03-26): +# The Palestinian cabinet announced today that the switch to DST will +# be on Fri Mar 29th 2019 by advancing the clock by 60 minutes. +# http://palestinecabinet.gov.ps/Website/AR/NDecrees/ViewFile.ashx?ID=e54e9ea1-50ee-4137-84df-0d6c78da259b +# +# From Even Scharning (2019-04-10): +# Our source in Palestine said it happened Friday 29 at 00:00 local time.... + +# From Sharef Mustafa (2019-10-18): +# Palestine summer time will end on midnight Oct 26th 2019 ... +# +# From Steffen Thorsen (2020-10-20): +# Some sources such as these say, and display on clocks, that DST ended at +# midnight last year... +# https://www.amad.ps/ar/post/320006 +# +# From Tim Parenti (2020-10-20): +# The report of the Palestinian Cabinet meeting of 2019-10-14 confirms +# a decision on (translated): "The start of the winter time in Palestine, by +# delaying the clock by sixty minutes, starting from midnight on Friday / +# Saturday corresponding to 26/10/2019." +# http://www.palestinecabinet.gov.ps/portal/meeting/details/43948 + +# From Sharef Mustafa (2020-10-20): +# As per the palestinian cabinet announcement yesterday , the day light saving +# shall [end] on Oct 24th 2020 at 01:00AM by delaying the clock by 60 minutes. +# http://www.palestinecabinet.gov.ps/portal/Meeting/Details/51584 + +# From Tim Parenti (2020-10-20): +# Predict future fall transitions at 01:00 on the Saturday preceding October's +# last Sunday (i.e., Sat>=24). This is consistent with our predictions since +# 2016, although the time of the change differed slightly in 2019. + +# From Pierre Cashon (2020-10-20): +# The summer time this year started on March 28 at 00:00. +# https://wafa.ps/ar_page.aspx?id=GveQNZa872839351758aGveQNZ +# http://www.palestinecabinet.gov.ps/portal/meeting/details/50284 +# The winter time in 2015 started on October 23 at 01:00. +# https://wafa.ps/ar_page.aspx?id=CgpCdYa670694628582aCgpCdY +# http://www.palestinecabinet.gov.ps/portal/meeting/details/27583 +# +# From Paul Eggert (2019-04-10): +# For now, guess spring-ahead transitions are at 00:00 on the Saturday +# preceding March's last Sunday (i.e., Sat>=24). + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule EgyptAsia 1957 only - May 10 0:00 1:00 S Rule EgyptAsia 1957 1958 - Oct 1 0:00 0 - Rule EgyptAsia 1958 only - May 1 0:00 1:00 S @@ -2900,10 +3433,10 @@ Rule Palestine 2005 only - Oct 4 2:00 0 - Rule Palestine 2006 2007 - Apr 1 0:00 1:00 S Rule Palestine 2006 only - Sep 22 0:00 0 - -Rule Palestine 2007 only - Sep Thu>=8 2:00 0 - +Rule Palestine 2007 only - Sep 13 2:00 0 - Rule Palestine 2008 2009 - Mar lastFri 0:00 1:00 S Rule Palestine 2008 only - Sep 1 0:00 0 - -Rule Palestine 2009 only - Sep Fri>=1 1:00 0 - +Rule Palestine 2009 only - Sep 4 1:00 0 - Rule Palestine 2010 only - Mar 26 0:00 1:00 S Rule Palestine 2010 only - Aug 11 0:00 0 - Rule Palestine 2011 only - Apr 1 0:01 1:00 S @@ -2912,13 +3445,18 @@ Rule Palestine 2011 only - Sep 30 0:00 0 - Rule Palestine 2012 2014 - Mar lastThu 24:00 1:00 S Rule Palestine 2012 only - Sep 21 1:00 0 - -Rule Palestine 2013 only - Sep Fri>=21 0:00 0 - -Rule Palestine 2014 2015 - Oct Fri>=21 0:00 0 - -Rule Palestine 2015 only - Mar lastFri 24:00 1:00 S -Rule Palestine 2016 max - Mar Sat>=22 1:00 1:00 S -Rule Palestine 2016 max - Oct lastSat 1:00 0 - +Rule Palestine 2013 only - Sep 27 0:00 0 - +Rule Palestine 2014 only - Oct 24 0:00 0 - +Rule Palestine 2015 only - Mar 28 0:00 1:00 S +Rule Palestine 2015 only - Oct 23 1:00 0 - +Rule Palestine 2016 2018 - Mar Sat>=24 1:00 1:00 S +Rule Palestine 2016 2018 - Oct Sat>=24 1:00 0 - +Rule Palestine 2019 only - Mar 29 0:00 1:00 S +Rule Palestine 2019 only - Oct Sat>=24 0:00 0 - +Rule Palestine 2020 max - Mar Sat>=24 0:00 1:00 S +Rule Palestine 2020 max - Oct Sat>=24 1:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Gaza 2:17:52 - LMT 1900 Oct 2:00 Zion EET/EEST 1948 May 15 2:00 EgyptAsia EE%sT 1967 Jun 5 @@ -2943,6 +3481,11 @@ # no information # Philippines + +# From Paul Eggert (2018-11-18): +# The Spanish initially used American (west-of-Greenwich) time. +# It is unknown what time Manila kept when the British occupied it from +# 1762-10-06 through 1764-04; for now assume it kept American time. # On 1844-08-16, Narciso Clavería, governor-general of the # Philippines, issued a proclamation announcing that 1844-12-30 was to # be immediately followed by 1845-01-01; see R.H. van Gent's @@ -2980,14 +3523,14 @@ # influence of the sources. There is no current abbreviation for DST, # so use "PDT", the usual American style. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Phil 1936 only - Nov 1 0:00 1:00 D Rule Phil 1937 only - Feb 1 0:00 0 S Rule Phil 1954 only - Apr 12 0:00 1:00 D Rule Phil 1954 only - Jul 1 0:00 0 S Rule Phil 1978 only - Mar 22 0:00 1:00 D Rule Phil 1978 only - Sep 21 0:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Manila -15:56:00 - LMT 1844 Dec 31 8:04:00 - LMT 1899 May 11 8:00 Phil P%sT 1942 May @@ -2995,7 +3538,7 @@ 8:00 Phil P%sT # Qatar -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Qatar 3:26:08 - LMT 1920 # Al Dawhah / Doha 4:00 - +04 1972 Jun 3:00 - +03 @@ -3028,8 +3571,8 @@ # going to run on Higgins Time.' And so, until last year, it did." See: # Antar E. Dinner at When? Saudi Aramco World, 1969 March/April. 2-3. # http://archive.aramcoworld.com/issue/196902/dinner.at.when.htm -# newspapers.com says a similar story about Higgins was published in the Port -# Angeles (WA) Evening News, 1965-03-10, page 5, but I lack access to the text. +# Also see: Antar EN. Arabian flying is confusing. +# Port Angeles (WA) Evening News. 1965-03-10. page 3. # # The TZ database cannot represent quasi-solar time; airline time is the best # we can do. The 1946 foreign air news digest of the U.S. Civil Aeronautics @@ -3043,7 +3586,7 @@ # the country. Presumably this is documenting airline time. Ignore this, # as it's before our 1970 cutoff. # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Riyadh 3:06:52 - LMT 1947 Mar 14 3:00 - +03 Link Asia/Riyadh Asia/Aden # Yemen @@ -3052,7 +3595,7 @@ # Singapore # taken from Mok Ly Yng (2003-10-30) # http://www.math.nus.edu.sg/aslaksen/teaching/timezone.html -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Singapore 6:55:25 - LMT 1901 Jan 1 6:55:25 - SMT 1905 Jun 1 # Singapore M.T. 7:00 - +07 1933 Jan 1 @@ -3116,7 +3659,7 @@ # even worse. For now, let's use a numeric abbreviation; we can # switch to "SLST" if it catches on. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Colombo 5:19:24 - LMT 1880 5:19:32 - MMT 1906 # Moratuwa Mean Time 5:30 - +0530 1942 Jan 5 @@ -3128,7 +3671,7 @@ 5:30 - +0530 # Syria -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Syria 1920 1923 - Apr Sun>=15 2:00 1:00 S Rule Syria 1920 1923 - Oct Sun>=1 2:00 0 - Rule Syria 1962 only - Apr 29 2:00 1:00 S @@ -3286,13 +3829,13 @@ Rule Syria 2012 max - Mar lastFri 0:00 1:00 S Rule Syria 2009 max - Oct lastFri 0:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Damascus 2:25:12 - LMT 1920 # Dimashq 2:00 Syria EE%sT # Tajikistan # From Shanks & Pottenger. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Dushanbe 4:35:12 - LMT 1924 May 2 5:00 - +05 1930 Jun 21 6:00 RussiaAsia +06/+07 1991 Mar 31 2:00s @@ -3300,7 +3843,7 @@ 5:00 - +05 # Thailand -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Bangkok 6:42:04 - LMT 1880 6:42:04 - BMT 1920 Apr # Bangkok Mean Time 7:00 - +07 @@ -3309,7 +3852,7 @@ # Turkmenistan # From Shanks & Pottenger. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Ashgabat 3:53:32 - LMT 1924 May 2 # or Ashkhabad 4:00 - +04 1930 Jun 21 5:00 RussiaAsia +05/+06 1991 Mar 31 2:00 @@ -3317,14 +3860,14 @@ 5:00 - +05 # United Arab Emirates -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Dubai 3:41:12 - LMT 1920 4:00 - +04 Link Asia/Dubai Asia/Muscat # Oman # Uzbekistan # Byalokoz 1919 says Uzbekistan was 4:27:53. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Samarkand 4:27:53 - LMT 1924 May 2 4:00 - +04 1930 Jun 21 5:00 - +05 1981 Apr 1 @@ -3372,7 +3915,7 @@ # and in South Vietnam in particular (after 1954): # To 07:00 on 1911-05-01. # To 08:00 on 1942-12-31 at 23:00. -# To 09:00 in 1945-03-14 at 23:00. +# To 09:00 on 1945-03-14 at 23:00. # To 07:00 on 1945-09-02 in Vietnam. # To 08:00 on 1947-04-01 in French-controlled Indochina. # To 07:00 on 1955-07-01 in South Vietnam. @@ -3390,7 +3933,7 @@ # Lê Thành Lân: "Lịch hai thế kỷ (1802-2010) và các lịch vĩnh cửu", # NXB Thuận Hoá, Huế, 1995. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Asia/Ho_Chi_Minh 7:06:40 - LMT 1906 Jul 1 7:06:30 - PLMT 1911 May 1 # Phù Liễn MT 7:00 - +07 1942 Dec 31 23:00 @@ -3402,5 +3945,17 @@ 8:00 - +08 1975 Jun 13 7:00 - +07 +# From Paul Eggert (2019-02-19): +# +# The Ho Chi Minh entry suffices for most purposes as it agrees with all of +# Vietnam since 1975-06-13. Presumably clocks often changed in south Vietnam +# in the early 1970s as locations changed hands during the war; however the +# details are unknown and would likely be too voluminous for this database. +# +# For timestamps in north Vietnam back to 1970 (the tzdb cutoff), +# use Asia/Bangkok; see the VN entries in the file zone1970.tab. +# For timestamps before 1970, see Asia/Hanoi in the file 'backzone'. + + # Yemen # See Asia/Riyadh.
diff --git a/make/data/tzdata/australasia b/make/data/tzdata/australasia index 82e88c5..e28538e 100644 --- a/make/data/tzdata/australasia +++ b/make/data/tzdata/australasia
@@ -36,26 +36,23 @@ # Please see the notes below for the controversy about "EST" versus "AEST" etc. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -Rule Aus 1917 only - Jan 1 0:01 1:00 D -Rule Aus 1917 only - Mar 25 2:00 0 S -Rule Aus 1942 only - Jan 1 2:00 1:00 D -Rule Aus 1942 only - Mar 29 2:00 0 S -Rule Aus 1942 only - Sep 27 2:00 1:00 D -Rule Aus 1943 1944 - Mar lastSun 2:00 0 S -Rule Aus 1943 only - Oct 3 2:00 1:00 D -# Go with Whitman and the Australian National Standards Commission, which -# says W Australia didn't use DST in 1943/1944. Ignore Whitman's claim that -# 1944/1945 was just like 1943/1944. +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule Aus 1917 only - Jan 1 2:00s 1:00 D +Rule Aus 1917 only - Mar lastSun 2:00s 0 S +Rule Aus 1942 only - Jan 1 2:00s 1:00 D +Rule Aus 1942 only - Mar lastSun 2:00s 0 S +Rule Aus 1942 only - Sep 27 2:00s 1:00 D +Rule Aus 1943 1944 - Mar lastSun 2:00s 0 S +Rule Aus 1943 only - Oct 3 2:00s 1:00 D -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] # Northern Territory Zone Australia/Darwin 8:43:20 - LMT 1895 Feb 9:00 - ACST 1899 May 9:30 Aus AC%sT # Western Australia # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule AW 1974 only - Oct lastSun 2:00s 1:00 D Rule AW 1975 only - Mar Sun>=1 2:00s 0 S Rule AW 1983 only - Oct lastSun 2:00s 1:00 D @@ -93,7 +90,7 @@ # applies to all of the Whitsundays. # http://www.australia.gov.au/about-australia/australian-story/austn-islands # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule AQ 1971 only - Oct lastSun 2:00s 1:00 D Rule AQ 1972 only - Feb lastSun 2:00s 0 S Rule AQ 1989 1991 - Oct lastSun 2:00s 1:00 D @@ -109,7 +106,7 @@ 10:00 Holiday AE%sT # South Australia -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule AS 1971 1985 - Oct lastSun 2:00s 1:00 D Rule AS 1986 only - Oct 19 2:00s 1:00 D Rule AS 1987 2007 - Oct lastSun 2:00s 1:00 D @@ -125,7 +122,7 @@ Rule AS 2007 only - Mar lastSun 2:00s 0 S Rule AS 2008 max - Apr Sun>=1 2:00s 0 S Rule AS 2008 max - Oct Sun>=1 2:00s 1:00 D -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Australia/Adelaide 9:14:20 - LMT 1895 Feb 9:00 - ACST 1899 May 9:30 Aus AC%sT 1971 @@ -137,9 +134,13 @@ # http://www.bom.gov.au/climate/averages/tables/dst_times.shtml # says King Island didn't observe DST from WWII until late 1971. # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule AT 1916 only - Oct Sun>=1 2:00s 1:00 D +Rule AT 1917 only - Mar lastSun 2:00s 0 S +Rule AT 1917 1918 - Oct Sun>=22 2:00s 1:00 D +Rule AT 1918 1919 - Mar Sun>=1 2:00s 0 S Rule AT 1967 only - Oct Sun>=1 2:00s 1:00 D -Rule AT 1968 only - Mar lastSun 2:00s 0 S +Rule AT 1968 only - Mar Sun>=29 2:00s 0 S Rule AT 1968 1985 - Oct lastSun 2:00s 1:00 D Rule AT 1969 1971 - Mar Sun>=8 2:00s 0 S Rule AT 1972 only - Feb lastSun 2:00s 0 S @@ -157,20 +158,14 @@ Rule AT 2006 only - Apr Sun>=1 2:00s 0 S Rule AT 2007 only - Mar lastSun 2:00s 0 S Rule AT 2008 max - Apr Sun>=1 2:00s 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Australia/Hobart 9:49:16 - LMT 1895 Sep - 10:00 - AEST 1916 Oct 1 2:00 - 10:00 1:00 AEDT 1917 Feb + 10:00 AT AE%sT 1919 Oct 24 10:00 Aus AE%sT 1967 10:00 AT AE%sT -Zone Australia/Currie 9:35:28 - LMT 1895 Sep - 10:00 - AEST 1916 Oct 1 2:00 - 10:00 1:00 AEDT 1917 Feb - 10:00 Aus AE%sT 1971 Jul - 10:00 AT AE%sT # Victoria -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule AV 1971 1985 - Oct lastSun 2:00s 1:00 D Rule AV 1972 only - Feb lastSun 2:00s 0 S Rule AV 1973 1985 - Mar Sun>=1 2:00s 0 S @@ -185,13 +180,13 @@ Rule AV 2007 only - Mar lastSun 2:00s 0 S Rule AV 2008 max - Apr Sun>=1 2:00s 0 S Rule AV 2008 max - Oct Sun>=1 2:00s 1:00 D -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Australia/Melbourne 9:39:52 - LMT 1895 Feb 10:00 Aus AE%sT 1971 10:00 AV AE%sT # New South Wales -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule AN 1971 1985 - Oct lastSun 2:00s 1:00 D Rule AN 1972 only - Feb 27 2:00s 0 S Rule AN 1973 1981 - Mar Sun>=1 2:00s 0 S @@ -208,7 +203,7 @@ Rule AN 2007 only - Mar lastSun 2:00s 0 S Rule AN 2008 max - Apr Sun>=1 2:00s 0 S Rule AN 2008 max - Oct Sun>=1 2:00s 1:00 D -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Australia/Sydney 10:04:52 - LMT 1895 Feb 10:00 Aus AE%sT 1971 10:00 AN AE%sT @@ -220,7 +215,7 @@ 9:30 AS AC%sT # Lord Howe Island -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule LH 1981 1984 - Oct lastSun 2:00 1:00 - Rule LH 1982 1985 - Mar Sun>=1 2:00 0 - Rule LH 1985 only - Oct lastSun 2:00 0:30 - @@ -275,18 +270,19 @@ 10:00 Aus AE%sT 1919 Apr 1 0:00s 0 - -00 1948 Mar 25 10:00 Aus AE%sT 1967 - 10:00 AT AE%sT 2010 Apr 4 3:00 - 11:00 - +11 + 10:00 AT AE%sT 2010 + 10:00 1:00 AEDT 2011 + 10:00 AT AE%sT # Christmas -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Indian/Christmas 7:02:52 - LMT 1895 Feb 7:00 - +07 # Cocos (Keeling) Is # These islands were ruled by the Ross family from about 1830 to 1978. # We don't know when standard time was introduced; for now, we guess 1900. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Indian/Cocos 6:27:40 - LMT 1900 6:30 - +0630 @@ -390,15 +386,33 @@ # From Raymond Kumar (2018-07-13): # http://www.fijitimes.com/government-approves-2018-daylight-saving/ # ... The daylight saving period will end at 3am on Sunday January 13, 2019. -# -# From Paul Eggert (2018-07-15): -# For now, guess DST from 02:00 the first Sunday in November to 03:00 -# the first Sunday on or after January 13. January transitions reportedly -# depend on when school terms start. Although the guess is ad hoc, it matches -# transitions since late 2014 and seems more likely to match future -# practice than guessing no DST. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# From Paul Eggert (2019-08-06): +# Today Raymond Kumar reported the Government of Fiji Gazette Supplement No. 27 +# (2019-08-02) said that Fiji observes DST "commencing at 2.00 am on +# Sunday, 10 November 2019 and ending at 3.00 am on Sunday, 12 January 2020." +# For now, guess DST from 02:00 the second Sunday in November to 03:00 +# the first Sunday on or after January 12. January transitions reportedly +# depend on when school terms start. Although the guess is ad hoc, it matches +# transitions planned this year and seems more likely to match future practice +# than guessing no DST. +# From Michael Deckers (2019-08-06): +# https://www.laws.gov.fj/LawsAsMade/downloadfile/848 + +# From Raymond Kumar (2020-10-08): +# [DST in Fiji] is from December 20th 2020, till 17th January 2021. +# From Alan Mintz (2020-10-08): +# https://www.laws.gov.fj/LawsAsMade/GetFile/1071 +# From Tim Parenti (2020-10-08): +# https://www.fijivillage.com/news/Daylight-saving-from-Dec-20th-this-year-to-Jan-17th-2021-8rf4x5/ +# "Minister for Employment, Parveen Bala says they had never thought of +# stopping daylight saving. He says it was just to decide on when it should +# start and end. Bala says it is a short period..." +# Since the end date is still in line with our ongoing predictions, assume for +# now that the later-than-usual start date is a one-time departure from the +# recent second Sunday in November pattern. + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Fiji 1998 1999 - Nov Sun>=1 2:00 1:00 - Rule Fiji 1999 2000 - Feb lastSun 3:00 0 - Rule Fiji 2009 only - Nov 29 2:00 1:00 - @@ -407,14 +421,17 @@ Rule Fiji 2011 only - Mar Sun>=1 3:00 0 - Rule Fiji 2012 2013 - Jan Sun>=18 3:00 0 - Rule Fiji 2014 only - Jan Sun>=18 2:00 0 - -Rule Fiji 2014 max - Nov Sun>=1 2:00 1:00 - -Rule Fiji 2015 max - Jan Sun>=13 3:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +Rule Fiji 2014 2018 - Nov Sun>=1 2:00 1:00 - +Rule Fiji 2015 max - Jan Sun>=12 3:00 0 - +Rule Fiji 2019 only - Nov Sun>=8 2:00 1:00 - +Rule Fiji 2020 only - Dec 20 2:00 1:00 - +Rule Fiji 2021 max - Nov Sun>=8 2:00 1:00 - +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Fiji 11:55:44 - LMT 1915 Oct 26 # Suva 12:00 Fiji +12/+13 # French Polynesia -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Gambier -8:59:48 - LMT 1912 Oct # Rikitea -9:00 - -09 Zone Pacific/Marquesas -9:18:00 - LMT 1912 Oct @@ -425,15 +442,49 @@ # it is uninhabited. # Guam -# Zone NAME GMTOFF RULES FORMAT [UNTIL] + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +# http://guamlegislature.com/Public_Laws_5th/PL05-025.pdf +# http://documents.guam.gov/wp-content/uploads/E.O.-59-7-Guam-Daylight-Savings-Time-May-6-1959.pdf +Rule Guam 1959 only - Jun 27 2:00 1:00 D +# http://documents.guam.gov/wp-content/uploads/E.O.-61-5-Revocation-of-Daylight-Saving-Time-and-Restoratio.pdf +Rule Guam 1961 only - Jan 29 2:00 0 S +# http://documents.guam.gov/wp-content/uploads/E.O.-67-13-Guam-Daylight-Savings-Time.pdf +Rule Guam 1967 only - Sep 1 2:00 1:00 D +# http://documents.guam.gov/wp-content/uploads/E.O.-69-2-Repeal-of-Guam-Daylight-Saving-Time.pdf +Rule Guam 1969 only - Jan 26 0:01 0 S +# http://documents.guam.gov/wp-content/uploads/E.O.-69-10-Guam-Daylight-Saving-Time.pdf +Rule Guam 1969 only - Jun 22 2:00 1:00 D +Rule Guam 1969 only - Aug 31 2:00 0 S +# http://documents.guam.gov/wp-content/uploads/E.O.-70-10-Guam-Daylight-Saving-Time.pdf +# http://documents.guam.gov/wp-content/uploads/E.O.-70-30-End-of-Guam-Daylight-Saving-Time.pdf +# http://documents.guam.gov/wp-content/uploads/E.O.-71-5-Guam-Daylight-Savings-Time.pdf +Rule Guam 1970 1971 - Apr lastSun 2:00 1:00 D +Rule Guam 1970 1971 - Sep Sun>=1 2:00 0 S +# http://documents.guam.gov/wp-content/uploads/E.O.-73-28.-Guam-Day-light-Saving-Time.pdf +Rule Guam 1973 only - Dec 16 2:00 1:00 D +# http://documents.guam.gov/wp-content/uploads/E.O.-74-7-Guam-Daylight-Savings-Time-Rescinded.pdf +Rule Guam 1974 only - Feb 24 2:00 0 S +# http://documents.guam.gov/wp-content/uploads/E.O.-76-13-Daylight-Savings-Time.pdf +Rule Guam 1976 only - May 26 2:00 1:00 D +# http://documents.guam.gov/wp-content/uploads/E.O.-76-25-Revocation-of-E.O.-76-13.pdf +Rule Guam 1976 only - Aug 22 2:01 0 S +# http://documents.guam.gov/wp-content/uploads/E.O.-77-4-Daylight-Savings-Time.pdf +Rule Guam 1977 only - Apr 24 2:00 1:00 D +# http://documents.guam.gov/wp-content/uploads/E.O.-77-18-Guam-Standard-Time.pdf +Rule Guam 1977 only - Aug 28 2:00 0 S + +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Guam -14:21:00 - LMT 1844 Dec 31 9:39:00 - LMT 1901 # Agana - 10:00 - GST 2000 Dec 23 # Guam + 10:00 - GST 1941 Dec 10 # Guam + 9:00 - +09 1944 Jul 31 + 10:00 Guam G%sT 2000 Dec 23 10:00 - ChST # Chamorro Standard Time Link Pacific/Guam Pacific/Saipan # N Mariana Is # Kiribati -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Tarawa 11:32:04 - LMT 1901 # Bairiki 12:00 - +12 Zone Pacific/Enderbury -11:24:20 - LMT 1901 @@ -449,42 +500,67 @@ # See Pacific/Guam. # Marshall Is -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Pacific/Majuro 11:24:48 - LMT 1901 - 11:00 - +11 1969 Oct - 12:00 - +12 -Zone Pacific/Kwajalein 11:09:20 - LMT 1901 - 11:00 - +11 1969 Oct - -12:00 - -12 1993 Aug 20 - 12:00 - +12 +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Pacific/Majuro 11:24:48 - LMT 1901 + 11:00 - +11 1914 Oct + 9:00 - +09 1919 Feb 1 + 11:00 - +11 1937 + 10:00 - +10 1941 Apr 1 + 9:00 - +09 1944 Jan 30 + 11:00 - +11 1969 Oct + 12:00 - +12 +Zone Pacific/Kwajalein 11:09:20 - LMT 1901 + 11:00 - +11 1937 + 10:00 - +10 1941 Apr 1 + 9:00 - +09 1944 Feb 6 + 11:00 - +11 1969 Oct + -12:00 - -12 1993 Aug 20 24:00 + 12:00 - +12 # Micronesia -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Pacific/Chuuk 10:07:08 - LMT 1901 - 10:00 - +10 -Zone Pacific/Pohnpei 10:32:52 - LMT 1901 # Kolonia - 11:00 - +11 -Zone Pacific/Kosrae 10:51:56 - LMT 1901 - 11:00 - +11 1969 Oct - 12:00 - +12 1999 - 11:00 - +11 +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Pacific/Chuuk -13:52:52 - LMT 1844 Dec 31 + 10:07:08 - LMT 1901 + 10:00 - +10 1914 Oct + 9:00 - +09 1919 Feb 1 + 10:00 - +10 1941 Apr 1 + 9:00 - +09 1945 Aug + 10:00 - +10 +Zone Pacific/Pohnpei -13:27:08 - LMT 1844 Dec 31 # Kolonia + 10:32:52 - LMT 1901 + 11:00 - +11 1914 Oct + 9:00 - +09 1919 Feb 1 + 11:00 - +11 1937 + 10:00 - +10 1941 Apr 1 + 9:00 - +09 1945 Aug + 11:00 - +11 +Zone Pacific/Kosrae -13:08:04 - LMT 1844 Dec 31 + 10:51:56 - LMT 1901 + 11:00 - +11 1914 Oct + 9:00 - +09 1919 Feb 1 + 11:00 - +11 1937 + 10:00 - +10 1941 Apr 1 + 9:00 - +09 1945 Aug + 11:00 - +11 1969 Oct + 12:00 - +12 1999 + 11:00 - +11 # Nauru -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Nauru 11:07:40 - LMT 1921 Jan 15 # Uaobe - 11:30 - +1130 1942 Mar 15 - 9:00 - +09 1944 Aug 15 - 11:30 - +1130 1979 May + 11:30 - +1130 1942 Aug 29 + 9:00 - +09 1945 Sep 8 + 11:30 - +1130 1979 Feb 10 2:00 12:00 - +12 # New Caledonia -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule NC 1977 1978 - Dec Sun>=1 0:00 1:00 - Rule NC 1978 1979 - Feb 27 0:00 0 - Rule NC 1996 only - Dec 1 2:00s 1:00 - # Shanks & Pottenger say the following was at 2:00; go with IATA. Rule NC 1997 only - Mar 2 2:00s 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Noumea 11:05:48 - LMT 1912 Jan 13 # Nouméa 11:00 NC +11/+12 @@ -493,7 +569,7 @@ # New Zealand -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule NZ 1927 only - Nov 6 2:00 1:00 S Rule NZ 1928 only - Mar 4 2:00 0 M Rule NZ 1928 1933 - Oct Sun>=8 2:00 0:30 S @@ -523,7 +599,7 @@ Rule Chatham 2007 max - Sep lastSun 2:45s 1:00 - Rule NZ 2008 max - Apr Sun>=1 2:00s 0 S Rule Chatham 2008 max - Apr Sun>=1 2:45s 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Auckland 11:39:04 - LMT 1868 Nov 2 11:30 NZ NZ%sT 1946 Jan 1 12:00 NZ NZ%sT @@ -545,11 +621,11 @@ # Cook Is # From Shanks & Pottenger: -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Cook 1978 only - Nov 12 0:00 0:30 - Rule Cook 1979 1991 - Mar Sun>=1 0:00 0 - Rule Cook 1979 1990 - Oct lastSun 0:00 0:30 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Rarotonga -10:39:04 - LMT 1901 # Avarua -10:30 - -1030 1978 Nov 12 -10:00 Cook -10/-0930 @@ -558,28 +634,30 @@ # Niue -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Niue -11:19:40 - LMT 1901 # Alofi -11:20 - -1120 1951 -11:30 - -1130 1978 Oct 1 -11:00 - -11 # Norfolk -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Norfolk 11:11:52 - LMT 1901 # Kingston 11:12 - +1112 1951 - 11:30 - +1130 1974 Oct 27 02:00 - 11:30 1:00 +1230 1975 Mar 2 02:00 - 11:30 - +1130 2015 Oct 4 02:00 - 11:00 - +11 + 11:30 - +1130 1974 Oct 27 02:00s + 11:30 1:00 +1230 1975 Mar 2 02:00s + 11:30 - +1130 2015 Oct 4 02:00s + 11:00 - +11 2019 Jul + 11:00 AN +11/+12 # Palau (Belau) -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Pacific/Palau 8:57:56 - LMT 1901 # Koror - 9:00 - +09 +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Pacific/Palau -15:02:04 - LMT 1844 Dec 31 # Koror + 8:57:56 - LMT 1901 + 9:00 - +09 # Papua New Guinea -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Port_Moresby 9:48:40 - LMT 1880 9:48:32 - PMMT 1895 # Port Moresby Mean Time 10:00 - +10 @@ -609,7 +687,7 @@ 11:00 - +11 # Pitcairn -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Pitcairn -8:40:20 - LMT 1901 # Adamstown -8:30 - -0830 1998 Apr 27 0:00 -8:00 - -08 @@ -688,13 +766,13 @@ # That web page currently lists transitions for 2012/3 and 2013/4. # Assume the pattern instituted in 2012 will continue indefinitely. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule WS 2010 only - Sep lastSun 0:00 1 - Rule WS 2011 only - Apr Sat>=1 4:00 0 - Rule WS 2011 only - Sep lastSat 3:00 1 - Rule WS 2012 max - Apr Sun>=1 4:00 0 - Rule WS 2012 max - Sep lastSun 3:00 1 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Apia 12:33:04 - LMT 1892 Jul 5 -11:26:56 - LMT 1911 -11:30 - -1130 1950 @@ -703,7 +781,7 @@ # Solomon Is # excludes Bougainville, for which see Papua New Guinea -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Guadalcanal 10:39:48 - LMT 1912 Oct # Honiara 11:00 - +11 @@ -726,27 +804,27 @@ # was "11 hours slow on G.M.T." Go with Thorsen and assume Shanks & Pottenger # are off by an hour starting in 1901. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Fakaofo -11:24:56 - LMT 1901 -11:00 - -11 2011 Dec 30 13:00 - +13 # Tonga -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Tonga 1999 only - Oct 7 2:00s 1:00 - Rule Tonga 2000 only - Mar 19 2:00s 0 - Rule Tonga 2000 2001 - Nov Sun>=1 2:00 1:00 - Rule Tonga 2001 2002 - Jan lastSun 2:00 0 - Rule Tonga 2016 only - Nov Sun>=1 2:00 1:00 - Rule Tonga 2017 only - Jan Sun>=15 3:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Tongatapu 12:19:20 - LMT 1901 12:20 - +1220 1941 13:00 - +13 1999 13:00 Tonga +13/+14 # Tuvalu -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Funafuti 11:56:52 - LMT 1901 12:00 - +12 @@ -807,25 +885,48 @@ # uninhabited since World War II; was probably like Pacific/Kiritimati # Wake -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Wake 11:06:28 - LMT 1901 12:00 - +12 # Vanuatu -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -Rule Vanuatu 1983 only - Sep 25 0:00 1:00 - -Rule Vanuatu 1984 1991 - Mar Sun>=23 0:00 0 - -Rule Vanuatu 1984 only - Oct 23 0:00 1:00 - -Rule Vanuatu 1985 1991 - Sep Sun>=23 0:00 1:00 - -Rule Vanuatu 1992 1993 - Jan Sun>=23 0:00 0 - -Rule Vanuatu 1992 only - Oct Sun>=23 0:00 1:00 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] + +# From P Chan (2020-11-27): +# Joint Daylight Saving Regulation No 59 of 1973 +# New Hebrides Condominium Gazette No 336. December 1973 +# http://www.paclii.org/vu/other/VUNHGovGaz//1973/11.pdf#page=15 +# +# Joint Daylight Saving (Repeal) Regulation No 10 of 1974 +# New Hebrides Condominium Gazette No 336. March 1974 +# http://www.paclii.org/vu/other/VUNHGovGaz//1974/3.pdf#page=11 +# +# Summer Time Act No. 35 of 1982 [commenced 1983-09-01] +# http://www.paclii.org/vu/other/VUGovGaz/1982/32.pdf#page=48 +# +# Summer Time Act (Cap 157) +# Laws of the Republic of Vanuatu Revised Edition 1988 +# http://www.paclii.org/cgi-bin/sinodisp/vu/legis/consol_act1988/sta147/sta147.html +# +# Summer Time (Amendment) Act No. 6 of 1991 [commenced 1991-11-11] +# http://www.paclii.org/vu/legis/num_act/sta1991227/ +# +# Summer Time (Repeal) Act No. 4 of 1993 [commenced 1993-05-03] +# http://www.paclii.org/vu/other/VUGovGaz/1993/15.pdf#page=59 + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule Vanuatu 1973 only - Dec 22 12:00u 1:00 - +Rule Vanuatu 1974 only - Mar 30 12:00u 0 - +Rule Vanuatu 1983 1991 - Sep Sat>=22 24:00 1:00 - +Rule Vanuatu 1984 1991 - Mar Sat>=22 24:00 0 - +Rule Vanuatu 1992 1993 - Jan Sat>=22 24:00 0 - +Rule Vanuatu 1992 only - Oct Sat>=22 24:00 1:00 - +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Efate 11:13:16 - LMT 1912 Jan 13 # Vila 11:00 Vanuatu +11/+12 # Wallis and Futuna -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Wallis 12:15:20 - LMT 1901 12:00 - +12 @@ -838,7 +939,7 @@ # tz@iana.org for general use in the future). For more, please see # the file CONTRIBUTING in the tz distribution. -# From Paul Eggert (2017-02-10): +# From Paul Eggert (2018-11-18): # # Unless otherwise specified, the source for data through 1990 is: # Thomas G. Shanks and Rique Pottenger, The International Atlas (6th edition), @@ -863,6 +964,7 @@ # A reliable and entertaining source about time zones is # Derek Howse, Greenwich time and longitude, Philip Wilson Publishers (1997). # +# I invented the abbreviation marked "*". # The following abbreviations are from other sources. # Corrections are welcome! # std dst @@ -870,7 +972,7 @@ # 8:00 AWST AWDT Western Australia # 9:30 ACST ACDT Central Australia # 10:00 AEST AEDT Eastern Australia -# 10:00 GST Guam through 2000 +# 10:00 GST GDT* Guam through 2000 # 10:00 ChST Chamorro # 11:30 NZMT NZST New Zealand through 1945 # 12:00 NZST NZDT New Zealand 1946-present @@ -897,6 +999,25 @@ # Electronic Journal of Australian and New Zealand History (1997-03-03) # http://www.jcu.edu.au/aff/history/reviews/davison.htm +# From P Chan (2020-11-20): +# Daylight Saving Act 1916 (No. 40 of 1916) [1916-12-21, commenced 1917-01-01] +# http://classic.austlii.edu.au/au/legis/cth/num_act/dsa1916401916192/ +# +# Daylight Saving Repeal Act 1917 (No. 35 of 1917) [1917-09-25] +# http://classic.austlii.edu.au/au/legis/cth/num_act/dsra1917351917243/ +# +# Statutory Rules 1941, No. 323 [1941-12-24] +# https://www.legislation.gov.au/Details/C1941L00323 +# +# Statutory Rules 1942, No. 392 [1942-09-10] +# https://www.legislation.gov.au/Details/C1942L00392 +# +# Statutory Rules 1943, No. 241 [1943-09-29] +# https://www.legislation.gov.au/Details/C1943L00241 +# +# All transition times should be 02:00 standard time. + + # From Paul Eggert (2005-12-08): # Implementation Dates of Daylight Saving Time within Australia # http://www.bom.gov.au/climate/averages/tables/dst_times.shtml @@ -1210,6 +1331,22 @@ # in WA or its introduction in SA had anything to do with the genesis # of this time zone. My hunch is that it's been around since well # before 1975. I remember seeing it noted on road maps decades ago. +# +# From Gilmore Davidson (2019-04-08): +# https://www.abc.net.au/news/2019-04-08/this-remote-stretch-of-desert-has-its-own-custom-time-zone/10981000 +# ... include[s] a rough description of the geographical boundaries... +# "The time zone exists for about 340 kilometres and takes in the tiny +# roadhouse communities of Cocklebiddy, Madura, Eucla and Border Village." +# ... and an indication that the zone has definitely been in existence +# since before the 1970 cut-off of the database ... +# From Paul Eggert (2019-05-17): +# That ABC Esperance story by Christien de Garis also says: +# Although the Central Western Time Zone is not officially recognised (your +# phones won't automatically change), there is a sign instructing you which +# way to wind your clocks 45 minutes and scrawled underneath one of them in +# Texta is the word: 'Why'? +# "Good question," Mr Pike said. +# "I don't even know that, and it's been going for over 50 years." # From Paul Eggert (2006-12-15): # For lack of better info, assume the tradition dates back to the @@ -1273,6 +1410,27 @@ # Tasmania +# From P Chan (2020-11-20): +# Tasmania observed DST in 1916-1919. +# +# Daylight Saving Act, 1916 (7 Geo V, No 2) [1916-09-22] +# http://classic.austlii.edu.au/au/legis/tas/num_act/tdsa19167gvn2267/ +# +# Daylight Saving Amendment Act, 1917 (8 Geo V, No 5) [1917-10-01] +# http://classic.austlii.edu.au/au/legis/tas/num_act/tdsaa19178gvn5347/ +# +# Daylight Saving Act Repeal Act, 1919 (10 Geo V, No 9) [1919-10-24] +# http://classic.austlii.edu.au/au/legis/tas/num_act/tdsara191910gvn9339/ +# +# King Island is mentioned in the 1967 Act but not the 1968 Act. +# Therefore it possibly observed DST from 1968/69. +# +# Daylight Saving Act 1967 (No. 33 of 1967) [1967-09-22] +# http://classic.austlii.edu.au/au/legis/tas/num_act/dsa196733o1967211/ +# +# Daylight Saving Act 1968 (No. 42 of 1968) [1968-10-15] +# http://classic.austlii.edu.au/au/legis/tas/num_act/dsa196842o1968211/ + # The rules for 1967 through 1991 were reported by George Shepherd # via Simon Woodhead via Robert Elz (1991-03-06): # # The state of TASMANIA.. [Courtesy Tasmanian Dept of Premier + Cabinet ] @@ -1528,6 +1686,42 @@ ############################################################################### +# Bonin (Ogasawara) Islands and Marcus Island (Minami-Tori-shima) + +# From Wakaba (2019-01-28) via Phake Nick: +# National Diet Library of Japan has several reports by Japanese Government +# officers that describe the time used in islands when they visited there. +# According to them (and other sources such as newspapers), standard time UTC +# + 10 (JST + 1) and DST UTC + 11 (JST + 2) was used until its return to Japan +# at 1968-06-26 00:00 JST. The exact periods of DST are still unknown. +# I guessed Guam, Mariana, and Bonin and Marcus districts might have +# synchronized their DST periods, but reports imply they had their own +# decisions, i.e. there were three or more different time zones.... +# +# https://wiki.suikawiki.org/n/小笠原諸島の標準時 + +# From Phake Nick (2019-02-12): +# Because their last time change to return to Japanese time when they returned +# to Japanese rule was right before 1970, ... per the current tz database +# rule, the information doesn't warrant creation of a new timezone for Bonin +# Islands itself and is thus as an anecdotal note for interest purpose only. +# ... [The abovementioned link] described some special timekeeping phenomenon +# regarding Marcus island, another remote island currently owned by Japanese +# in the same administrative unit as Bonin Islands. Many reports claim that +# the American coastal guard on the American quarter of the island use its own +# coastal guard time, and most sources describe the time as UTC+11, being two +# hours faster than JST used by some Japanese personnel on the island. Some +# sites describe it as same as Wake Island/Guam time although it would be +# incorrect to be same as Guam. And then in a few Japanese governmental +# report from 1980s (from National Institute of Information and Communications +# Technology) regarding the construction of VLBI facility on the Marcus +# Island, it claimed that there are three time standards being used on the +# island at the time which include not just JST (UTC+9) or [US]CG time +# (UTC+11) but also a JMSDF time (UTC+10) (Japan Maritime Self-Defense +# Force). Unfortunately there are no other sources that mentioned such time +# and there are also no information on things like how the time was used. + + # Fiji # Howse writes (p 153) that in 1879 the British governor of Fiji @@ -1569,28 +1763,70 @@ # Kwajalein -# In comp.risks 14.87 (26 August 1993), Peter Neumann writes: -# I wonder what happened in Kwajalein, where there was NO Friday, -# 1993-08-20. Thursday night at midnight Kwajalein switched sides with -# respect to the International Date Line, to rejoin its fellow islands, -# going from 11:59 p.m. Thursday to 12:00 m. Saturday in a blink. +# From an AP article (1993-08-22): +# "The nearly 3,000 Americans living on this remote Pacific atoll have a good +# excuse for not remembering Saturday night: there wasn't one. Residents were +# going to bed Friday night and waking up Sunday morning because at midnight +# -- 8 A.M. Eastern daylight time on Saturday -- Kwajalein was jumping from +# one side of the international date line to the other." +# "In Marshall Islands, Friday is followed by Sunday", NY Times. 1993-08-22. +# https://www.nytimes.com/1993/08/22/world/in-marshall-islands-friday-is-followed-by-sunday.html + +# From Phake Nick (2018-10-27): +# <https://wiki.suikawiki.org/n/南洋群島の標準時> ... pointed out that +# currently tzdata say Pacific/Kwajalein switched from GMT+11 to GMT-12 in +# 1969 October without explanation, however an 1993 article from NYT say it +# synchorized its day with US mainland about 40 years ago and thus the switch +# should occur at around 1950s instead. +# +# From Paul Eggert (2018-11-18): +# The NYT (actually, AP) article is vague and possibly wrong about this. +# The article says the earlier switch was "40 years ago when the United States +# Army established a missile test range here". However, the Kwajalein Test +# Center was established on 1960-10-01 and was run by the US Navy. It was +# transferred to the US Army on 1964-07-01. See "Seize the High Ground" +# <https://history.army.mil/html/books/070/70-88-1/cmhPub_70-88-1.pdf>. +# Given that Shanks was right on the money about the 1993 change, I'm inclined +# to take Shanks's word for the 1969 change unless we find better evidence. # N Mariana Is, Guam +# From Phake Nick (2018-10-27): +# Guam Island was briefly annexed by Japan during ... year 1941-1944 ... +# however there are no detailed information about what time it use during that +# period. It would probably be reasonable to assume Guam use GMT+9 during +# that period of time like the surrounding area. + +# From Paul Eggert (2018-11-18): # Howse writes (p 153) "The Spaniards, on the other hand, reached the # Philippines and the Ladrones from America," and implies that the Ladrones # (now called the Marianas) kept American date for quite some time. # For now, we assume the Ladrones switched at the same time as the Philippines; # see Asia/Manila. - +# +# Use 1941-12-10 and 1944-07-31 for Guam WWII transitions, as the rough start +# and end of Japanese control of Agana. We don't know whether the Northern +# Marianas followed Guam's DST rules from 1959 through 1977; for now, assume +# they did as that avoids the need for a separate zone due to our 1970 cutoff. +# # US Public Law 106-564 (2000-12-23) made UT +10 the official standard time, # under the name "Chamorro Standard Time". There is no official abbreviation, # but Congressman Robert A. Underwood, author of the bill that became law, # wrote in a press release (2000-12-27) that he will seek the use of "ChST". +# See also the commentary for Micronesia. -# Micronesia + +# Marshall Is +# See the commentary for Micronesia. + + +# Micronesia (and nearby) + +# From Paul Eggert (2018-11-18): +# Like the Ladrones (see Guam commentary), assume the Spanish East Indies +# kept American time until the Philippines switched at the end of 1844. # Alan Eugene Davis writes (1996-03-16), # "I am certain, having lived there for the past decade, that 'Truk' @@ -1606,6 +1842,95 @@ # that Truk and Yap are UT +10, and Ponape and Kosrae are +11. # We don't know when Kosrae switched from +12; assume January 1 for now. +# From Phake Nick (2018-10-27): +# +# From a Japanese wiki site https://wiki.suikawiki.org/n/南洋群島の標準時 +# ... +# For "Southern Islands" (modern region of Mariana + Palau + Federation of +# Micronesia + Marshall Islands): +# +# A 1906 Japanese magazine shown the Caroline Islands and Mariana Islands +# who was occupied by Germany at the time as GMT+10, together with the like +# of German New Guinea. However there is a marking saying it have not been +# implemented (yet). No further information after that were found. +# +# Japan invaded those islands in 1914, and records shows that they were +# instructed to use JST at the time. +# +# 1915 January telecommunication record on the Jaluit Atoll shows they use +# the meridian of 170E as standard time (GMT+11:20), which is similar to the +# longitude of the atoll. +# 1915 February record say the 170E standard time is to be used until +# February 9 noon, and after February 9 noon they are to use JST. +# However these are time used within the Japanese Military at the time and +# probably does not reflect the time used by local resident at the time (that +# is if they keep their own time back then) +# +# In January 1919 the occupying force issued a command that split the area +# into three different timezone with meridian of 135E, 150E, 165E (JST+0, +1, +# +2), and the command was to become effective from February 1 of the same +# year. Despite the target of the command is still only for the occupying +# force itself, further publication have described the time as the standard +# time for the occupied area and thus it can probably be seen as such. +# * Area that use meridian of 135E: Palau and Yap civil administration area +# (Southern Islands Western Standard Time) +# * Area that use meridian of 150E: Truk (Chuuk) and Saipan civil +# administration area (Southern Islands Central Standard Time) +# * Area that use meridian of 165E: Ponape (Pohnpei) and Jaluit civil +# administration area (Southern Islands Eastern Standard Time). +# * In the next few years Japanese occupation of those islands have been +# formalized via League of Nation Mandate (South Pacific Mandate) and formal +# governance structure have been established, these district [become +# subprefectures] and timezone classification have been inherited as standard +# time of the area. +# * Saipan subprefecture include Mariana islands (exclude Guam which was +# occupied by America at the time), Palau and Yap subprefecture rule the +# Western Caroline Islands with 137E longitude as border, Truk and Ponape +# subprefecture rule the Eastern Caroline Islands with 154E as border, Ponape +# subprefecture also rule part of Marshall Islands to the west of 164E +# starting from (1918?) and Jaluit subprefecture rule the rest of the +# Marshall Islands. +# +# And then in year 1937, an announcement was made to change the time in the +# area into 2 timezones: +# * Area that use meridian of 135E: area administered by Palau, Yap and +# Saipan subprefecture (Southern Islands Western Standard Time) +# * Area that use meridian of 150E: area administered by Truk (Chuuk), +# Ponape (Pohnpei) and Jaluit subprefecture (Southern Islands Eastern +# Standard Time) +# +# Another announcement issued in 1941 say that on April 1 that year, +# standard time of the Southern Islands would be changed to use the meridian +# of 135E (GMT+9), and thus abolishing timezone different within the area. +# +# Then Pacific theater of WWII started and Japan slowly lose control on the +# island. The webpage I linked above contain no information during this +# period of time.... +# +# After the end of WWII, in 1946 February, a document written by the +# (former?) Japanese military personnel describe there are 3 hours time +# different between Caroline islands time/Wake island time and the Chungking +# time, which would mean the time being used there at the time was GMT+10. +# +# After that, the area become Trust Territories of the Pacific Islands +# under American administration from year 1947. The site listed some +# American/International books/maps/publications about time used in those +# area during this period of time but they doesn't seems to be reliable +# information so it would be the best if someone know where can more reliable +# information can be found. +# +# +# From Paul Eggert (2018-11-18): +# +# For the above, use vague dates like "1914" and "1945" for transitions that +# plausibly exist but for which the details are not known. The information +# for Wake is too sketchy to act on. +# +# The 1906 GMT+10 info about German-controlled islands might not have been +# done, so omit it from the data for now. +# +# The Jaluit info governs Kwajalein. + # Midway @@ -1623,6 +1948,29 @@ # started DST on June 3. Possibly DST was observed other years # in Midway, but we have no record of it. +# Nauru + +# From Phake Nick (2018-10-31): +# Currently, the tz database say Nauru use LMT until 1921, and then +# switched to GMT+11:30 for the next two decades. +# However, a number of timezone map published in America/Japan back then +# showed its timezone as GMT+11 per https://wiki.suikawiki.org/n/ナウルの標準時 +# And it would also be nice if the 1921 transition date could be sourced. +# ... +# The "Nauru Standard Time Act 1978 Time Change" +# http://ronlaw.gov.nr/nauru_lpms/files/gazettes/4b23a17d2030150404db7a5fa5872f52.pdf#page=3 +# based on "Nauru Standard Time Act 1978 Time Change" +# http://www.paclii.org/nr/legis/num_act/nsta1978207/ defined that "Nauru +# Alternative Time" (GMT+12) should be in effect from 1979 Feb. +# +# From Paul Eggert (2018-11-19): +# The 1921-01-15 introduction of standard time is in Shanks; it is also in +# "Standard Time Throughout the World", US National Bureau of Standards (1935), +# page 3, which does not give the UT offset. In response to a comment by +# Phake Nick I set the Nauru time of occupation by Japan to +# 1942-08-29/1945-09-08 by using dates from: +# https://en.wikipedia.org/wiki/Japanese_occupation_of_Nauru + # Norfolk # From Alexander Krivenyshev (2015-09-23): @@ -1631,12 +1979,24 @@ # ... at 12.30 am (by legal time in New South Wales) on 4 October 2015. # http://www.norfolkisland.gov.nf/nia/MediaRelease/Media%20Release%20Norfolk%20Island%20Standard%20Time%20Change.pdf -# From Paul Eggert (2015-09-23): +# From Paul Eggert (2019-08-28): # Transitions before 2015 are from timeanddate.com, which consulted # the Norfolk Island Museum and the Australian Bureau of Meteorology's # Norfolk Island station, and found no record of Norfolk observing DST # other than in 1974/5. See: # https://www.timeanddate.com/time/australia/norfolk-island.html +# However, disagree with timeanddate about the 1975-03-02 transition; +# timeanddate has 02:00 but 02:00s corresponds to what the NSW law said +# (thanks to Michael Deckers). + +# Norfolk started observing Australian DST in spring 2019. +# From Kyle Czech (2019-08-13): +# https://www.legislation.gov.au/Details/F2018L01702 +# From Michael Deckers (2019-08-14): +# https://www.legislation.gov.au/Details/F2019C00010 + +# Palau +# See commentary for Micronesia. # Pitcairn @@ -1802,6 +2162,9 @@ # From Paul Eggert (2003-03-23): # We have no other report of DST in Wake Island, so omit this info for now. +# See also the commentary for Micronesia. + + ############################################################################### # The International Date Line
diff --git a/make/data/tzdata/backward b/make/data/tzdata/backward index f30f30e..48482b7 100644 --- a/make/data/tzdata/backward +++ b/make/data/tzdata/backward
@@ -40,6 +40,7 @@ Link America/Argentina/Cordoba America/Cordoba Link America/Tijuana America/Ensenada Link America/Indiana/Indianapolis America/Fort_Wayne +Link America/Nuuk America/Godthab Link America/Indiana/Indianapolis America/Indianapolis Link America/Argentina/Jujuy America/Jujuy Link America/Indiana/Knox America/Knox_IN @@ -71,6 +72,7 @@ Link Europe/Oslo Atlantic/Jan_Mayen Link Australia/Sydney Australia/ACT Link Australia/Sydney Australia/Canberra +Link Australia/Hobart Australia/Currie Link Australia/Lord_Howe Australia/LHI Link Australia/Sydney Australia/NSW Link Australia/Darwin Australia/North @@ -100,6 +102,7 @@ Link America/Havana Cuba Link Africa/Cairo Egypt Link Europe/Dublin Eire +Link Etc/UTC Etc/UCT Link Europe/London Europe/Belfast Link Europe/Chisinau Europe/Tiraspol Link Europe/London GB @@ -134,7 +137,7 @@ Link Asia/Seoul ROK Link Asia/Singapore Singapore Link Europe/Istanbul Turkey -Link Etc/UCT UCT +Link Etc/UTC UCT Link America/Anchorage US/Alaska Link America/Adak US/Aleutian Link America/Phoenix US/Arizona
diff --git a/make/data/tzdata/etcetera b/make/data/tzdata/etcetera index db59378..a324e2c 100644 --- a/make/data/tzdata/etcetera +++ b/make/data/tzdata/etcetera
@@ -26,12 +26,11 @@ # This file is in the public domain, so clarified as of # 2009-05-17 by Arthur David Olson. -# These entries are mostly present for historical reasons, so that -# people in areas not otherwise covered by the tz files could "zic -l" -# to a timezone that was right for their area. These days, the -# tz files cover almost all the inhabited world, and the only practical -# need now for the entries that are not on UTC are for ships at sea -# that cannot use POSIX TZ settings. +# These entries are for uses not otherwise covered by the tz database. +# Their main practical use is for platforms like Android that lack +# support for POSIX-style TZ strings. On such platforms these entries +# can be useful if the timezone database is wrong or if a ship or +# aircraft at sea is not in a timezone. # Starting with POSIX 1003.1-2001, the entries below are all # unnecessary as settings for the TZ environment variable. E.g., @@ -42,7 +41,6 @@ Zone Etc/GMT 0 - GMT Zone Etc/UTC 0 - UTC -Zone Etc/UCT 0 - UCT # The following link uses older naming conventions, # but it belongs here, not in the file 'backward',
diff --git a/make/data/tzdata/europe b/make/data/tzdata/europe index e434b7e..eb9056e 100644 --- a/make/data/tzdata/europe +++ b/make/data/tzdata/europe
@@ -145,7 +145,7 @@ # position is 51° 28' 30" N, 0° 18' 45" W. The longitude should # be within about ±2". The Ordnance Survey grid reference is TQ172761. # -# [This yields GMTOFF = -0:01:15 for London LMT in the 18th century.] +# [This yields STDOFF = -0:01:15 for London LMT in the 18th century.] # From Paul Eggert (1993-11-18): # @@ -411,7 +411,7 @@ # http://www.irishstatutebook.ie/eli/1926/sro/919/made/en/print # http://www.irishstatutebook.ie/eli/1947/sro/71/made/en/print -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S # Summer Time Act, 1916 Rule GB-Eire 1916 only - May 21 2:00s 1:00 BST Rule GB-Eire 1916 only - Oct 1 2:00s 0 GMT @@ -523,7 +523,7 @@ # # Use Europe/London for Jersey, Guernsey, and the Isle of Man. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/London -0:01:15 - LMT 1847 Dec 1 0:00s 0:00 GB-Eire %s 1968 Oct 27 1:00 - BST 1971 Oct 31 2:00u @@ -552,16 +552,16 @@ # The following is like GB-Eire and EU, except with standard time in # summer and negative daylight saving time in winter. It is for when # negative SAVE values are used. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -#Rule Eire 1971 only - Oct 31 2:00u -1:00 - -#Rule Eire 1972 1980 - Mar Sun>=16 2:00u 0 - -#Rule Eire 1972 1980 - Oct Sun>=23 2:00u -1:00 - -#Rule Eire 1981 max - Mar lastSun 1:00u 0 - -#Rule Eire 1981 1989 - Oct Sun>=23 1:00u -1:00 - -#Rule Eire 1990 1995 - Oct Sun>=22 1:00u -1:00 - -#Rule Eire 1996 max - Oct lastSun 1:00u -1:00 - +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule Eire 1971 only - Oct 31 2:00u -1:00 - +Rule Eire 1972 1980 - Mar Sun>=16 2:00u 0 - +Rule Eire 1972 1980 - Oct Sun>=23 2:00u -1:00 - +Rule Eire 1981 max - Mar lastSun 1:00u 0 - +Rule Eire 1981 1989 - Oct Sun>=23 1:00u -1:00 - +Rule Eire 1990 1995 - Oct Sun>=22 1:00u -1:00 - +Rule Eire 1996 max - Oct lastSun 1:00u -1:00 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Dublin -0:25:00 - LMT 1880 Aug 2 -0:25:21 - DMT 1916 May 21 2:00s -0:25:21 1:00 IST 1916 Oct 1 2:00s @@ -572,12 +572,13 @@ 0:00 1:00 IST 1947 Nov 2 2:00s 0:00 - GMT 1948 Apr 18 2:00s 0:00 GB-Eire GMT/IST 1968 Oct 27 -# The next line is for when negative SAVE values are used. -# 1:00 Eire IST/GMT -# These three lines are for when SAVE values are always nonnegative. - 1:00 - IST 1971 Oct 31 2:00u - 0:00 GB-Eire GMT/IST 1996 - 0:00 EU GMT/IST +# Vanguard section, for zic and other parsers that support negative DST. + 1:00 Eire IST/GMT +# Rearguard section, for parsers lacking negative DST; see ziguard.awk. +# 1:00 - IST 1971 Oct 31 2:00u +# 0:00 GB-Eire GMT/IST 1996 +# 0:00 EU GMT/IST +# End of rearguard section. ############################################################################### @@ -588,7 +589,7 @@ # predecessor organization, the European Communities. # For brevity they are called "EU rules" elsewhere in this file. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule EU 1977 1980 - Apr Sun>=1 1:00u 1:00 S Rule EU 1977 only - Sep lastSun 1:00u 0 - Rule EU 1978 only - Oct 1 1:00u 0 - @@ -628,13 +629,13 @@ # corrected in version 2008d). The circumstantial evidence is simply the # tz database itself, as seen below: # -# Zone Europe/Paris 0:09:21 - LMT 1891 Mar 15 0:01 +# Zone Europe/Paris ... # 0:00 France WE%sT 1945 Sep 16 3:00 # -# Zone Europe/Monaco 0:29:32 - LMT 1891 Mar 15 +# Zone Europe/Monaco ... # 0:00 France WE%sT 1945 Sep 16 3:00 # -# Zone Europe/Belgrade 1:22:00 - LMT 1884 +# Zone Europe/Belgrade ... # 1:00 1:00 CEST 1945 Sep 16 2:00s # # Rule France 1945 only - Sep 16 3:00 0 - @@ -680,7 +681,7 @@ # # The 1917-1921 decree URLs are from Alexander Belopolsky (2016-08-23). -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Russia 1917 only - Jul 1 23:00 1:00 MST # Moscow Summer Time # # Decree No. 142 (1917-12-22) http://istmat.info/node/28137 @@ -760,7 +761,7 @@ # These are for backward compatibility with older versions. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone WET 0:00 EU WE%sT Zone CET 1:00 C-Eur CE%sT Zone MET 1:00 C-Eur ME%sT @@ -794,7 +795,7 @@ # Albania -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Albania 1940 only - Jun 16 0:00 1:00 S Rule Albania 1942 only - Nov 2 3:00 0 - Rule Albania 1943 only - Mar 29 2:00 1:00 S @@ -820,14 +821,14 @@ Rule Albania 1983 only - Apr 18 0:00 1:00 S Rule Albania 1983 only - Oct 1 0:00 0 - Rule Albania 1984 only - Apr 1 0:00 1:00 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Tirane 1:19:20 - LMT 1914 1:00 - CET 1940 Jun 16 1:00 Albania CE%sT 1984 Jul 1:00 EU CE%sT # Andorra -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Andorra 0:06:04 - LMT 1901 0:00 - WET 1946 Sep 30 1:00 - CET 1985 Mar 31 2:00 @@ -844,16 +845,21 @@ # Shanks & Pottenger give 02:00, the BEV 00:00. Go with the BEV, # and guess 02:00 for 1945-04-12. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# From Alois Triendl (2019-07-22): +# In 1946 the end of DST was on Monday, 7 October 1946, at 3:00 am. +# Shanks had this right. Source: Die Weltpresse, 5. Oktober 1946, page 5. + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Austria 1920 only - Apr 5 2:00s 1:00 S Rule Austria 1920 only - Sep 13 2:00s 0 - Rule Austria 1946 only - Apr 14 2:00s 1:00 S -Rule Austria 1946 1948 - Oct Sun>=1 2:00s 0 - +Rule Austria 1946 only - Oct 7 2:00s 0 - +Rule Austria 1947 1948 - Oct Sun>=1 2:00s 0 - Rule Austria 1947 only - Apr 6 2:00s 1:00 S Rule Austria 1948 only - Apr 18 2:00s 1:00 S Rule Austria 1980 only - Apr 6 0:00 1:00 S Rule Austria 1980 only - Sep 28 0:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Vienna 1:05:21 - LMT 1893 Apr 1:00 C-Eur CE%sT 1920 1:00 Austria CE%sT 1940 Apr 1 2:00s @@ -885,7 +891,7 @@ # Belarussian government decided against changing to winter time.... # http://eng.belta.by/all_news/society/Belarus-decides-against-adjusting-time-in-Russias-wake_i_76335.html # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Minsk 1:50:16 - LMT 1880 1:50 - MMT 1924 May 2 # Minsk Mean Time 2:00 - EET 1930 Jun 21 @@ -898,19 +904,39 @@ # Belgium # -# From Paul Eggert (1997-07-02): +# From Michael Deckers (2019-08-25): +# The exposition in the web page +# https://www.bestor.be/wiki/index.php/Voyager_dans_le_temps._L%E2%80%99introduction_de_la_norme_de_Greenwich_en_Belgique +# gives several contemporary sources from which one can conclude that +# the switch in Europe/Brussels on 1892-05-01 was from 00:17:30 to 00:00:00. +# +# From Paul Eggert (2019-08-28): +# This quote helps explain the late-1914 situation: +# In early November 1914, the Germans imposed the time zone used in central +# Europe and forced the inhabitants to set their watches and public clocks +# sixty minutes ahead. Many were reluctant to accept "German time" and +# continued to use "Belgian time" among themselves. Reflecting the spirit of +# resistance that arose in the population, a song made fun of this change.... +# The song ended: +# Putting your clock forward +# Will but hasten the happy hour +# When we kick out the Boches! +# See: Pluvinage G. Brussels on German time. Cahiers Bruxellois - +# Brusselse Cahiers. 2014;XLVI(1E):15-38. +# https://www.cairn.info/revue-cahiers-bruxellois-2014-1E-page-15.htm +# +# Entries from 1914 through 1917 are taken from "De tijd in België" +# <https://www.astro.oma.be/GENERAL/INFO/nli001a.html>. # Entries from 1918 through 1991 are taken from: # Annuaire de L'Observatoire Royal de Belgique, # Avenue Circulaire, 3, B-1180 BRUXELLES, CLVIIe année, 1991 # (Imprimerie HAYEZ, s.p.r.l., Rue Fin, 4, 1080 BRUXELLES, MCMXC), # pp 8-9. -# LMT before 1892 was 0:17:30, according to the official journal of Belgium: -# Moniteur Belge, Samedi 30 Avril 1892, N.121. -# Thanks to Pascal Delmoitie for these references. +# Thanks to Pascal Delmoitie for the 1918/1991 references. # The 1918 rules are listed for completeness; they apply to unoccupied Belgium. # Assume Brussels switched to WET in 1918 when the armistice took effect. # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Belgium 1918 only - Mar 9 0:00s 1:00 S Rule Belgium 1918 1919 - Oct Sat>=1 23:00s 0 - Rule Belgium 1919 only - Mar 1 23:00s 1:00 S @@ -949,9 +975,9 @@ Rule Belgium 1945 only - Sep 16 2:00s 0 - Rule Belgium 1946 only - May 19 2:00s 1:00 S Rule Belgium 1946 only - Oct 7 2:00s 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Brussels 0:17:30 - LMT 1880 - 0:17:30 - BMT 1892 May 1 12:00 # Brussels MT + 0:17:30 - BMT 1892 May 1 00:17:30 0:00 - WET 1914 Nov 8 1:00 - CET 1916 May 1 0:00 1:00 C-Eur CE%sT 1918 Nov 11 11:00u @@ -970,13 +996,13 @@ # EET -> EETDST is in 03:00 Local time in last Sunday of March ... # EETDST -> EET is in 04:00 Local time in last Sunday of October # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Bulg 1979 only - Mar 31 23:00 1:00 S Rule Bulg 1979 only - Oct 1 1:00 0 - Rule Bulg 1980 1982 - Apr Sat>=1 23:00 1:00 S Rule Bulg 1980 only - Sep 29 1:00 0 - Rule Bulg 1981 only - Sep 27 2:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Sofia 1:33:16 - LMT 1880 1:56:56 - IMT 1894 Nov 30 # Istanbul MT? 2:00 - EET 1942 Nov 2 3:00 @@ -1002,22 +1028,22 @@ # We know of no English-language name for historical Czech winter time; # abbreviate it as "GMT", as it happened to be GMT. # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Czech 1945 only - Apr Mon>=1 2:00s 1:00 S Rule Czech 1945 only - Oct 1 2:00s 0 - Rule Czech 1946 only - May 6 2:00s 1:00 S Rule Czech 1946 1949 - Oct Sun>=1 2:00s 0 - Rule Czech 1947 1948 - Apr Sun>=15 2:00s 1:00 S Rule Czech 1949 only - Apr 9 2:00s 1:00 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Prague 0:57:44 - LMT 1850 0:57:44 - PMT 1891 Oct # Prague Mean Time 1:00 C-Eur CE%sT 1945 May 9 1:00 Czech CE%sT 1946 Dec 1 3:00 # Vanguard section, for zic and other parsers that support negative DST. -# 1:00 -1:00 GMT 1947 Feb 23 2:00 -# Rearguard section, for parsers that do not support negative DST. - 0:00 - GMT 1947 Feb 23 2:00 + 1:00 -1:00 GMT 1947 Feb 23 2:00 +# Rearguard section, for parsers lacking negative DST; see ziguard.awk. +# 0:00 - GMT 1947 Feb 23 2:00 # End of rearguard section. 1:00 Czech CE%sT 1979 1:00 EU CE%sT @@ -1026,17 +1052,16 @@ # Denmark, Faroe Islands, and Greenland # From Jesper Nørgaard Welen (2005-04-26): -# http://www.hum.aau.dk/~poe/tid/tine/DanskTid.htm says that the law -# [introducing standard time] was in effect from 1894-01-01.... -# The page http://www.retsinfo.dk/_GETDOCI_/ACCN/A18930008330-REGL +# the law [introducing standard time] was in effect from 1894-01-01.... +# The page https://www.retsinformation.dk/eli/lta/1893/83 # confirms this, and states that the law was put forth 1893-03-29. # # The EU [actually, EEC and Euratom] treaty with effect from 1973: -# http://www.retsinfo.dk/_GETDOCI_/ACCN/A19722110030-REGL +# https://www.retsinformation.dk/eli/lta/1972/21100 # # This provoked a new law from 1974 to make possible summer time changes # in subsequent decrees with the law -# http://www.retsinfo.dk/_GETDOCI_/ACCN/A19740022330-REGL +# https://www.retsinformation.dk/eli/lta/1974/223 # # It seems however that no decree was set forward until 1980. I have # not found any decree, but in another related law, the effecting DST @@ -1048,7 +1073,7 @@ # The law is about the management of the extra hour, concerning # working hours reported and effect on obligatory-rest rules (which # was suspended on that night): -# http://www.retsinfo.dk/_GETDOCI_/ACCN/C19801120554-REGL +# https://web.archive.org/web/20140104053304/https://www.retsinformation.dk/Forms/R0710.aspx?id=60267 # From Jesper Nørgaard Welen (2005-06-11): # The Herning Folkeblad (1980-09-26) reported that the night between @@ -1058,7 +1083,7 @@ # Hence the "02:00" of the 1980 law refers to standard time, not # wall-clock time, and so the EU rules were in effect in 1980. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Denmark 1916 only - May 14 23:00 1:00 S Rule Denmark 1916 only - Sep 30 23:00 0 - Rule Denmark 1940 only - May 15 0:00 1:00 S @@ -1071,7 +1096,7 @@ Rule Denmark 1948 only - May 9 2:00s 1:00 S Rule Denmark 1948 only - Aug 8 2:00s 0 - # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Copenhagen 0:50:20 - LMT 1890 0:50:20 - CMT 1894 Jan 1 # Copenhagen MT 1:00 Denmark CE%sT 1942 Nov 2 2:00s @@ -1160,7 +1185,7 @@ # http://naalakkersuisut.gl/~/media/Nanoq/Files/Attached%20Files/Engelske-tekster/Legislation/Executive%20Order%20National%20Park.rtf # It is their only National Park. # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Thule 1991 1992 - Mar lastSun 2:00 1:00 D Rule Thule 1991 1992 - Sep lastSun 2:00 0 S Rule Thule 1993 2006 - Apr Sun>=1 2:00 1:00 D @@ -1168,19 +1193,22 @@ Rule Thule 2007 max - Mar Sun>=8 2:00 1:00 D Rule Thule 2007 max - Nov Sun>=1 2:00 0 S # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Danmarkshavn -1:14:40 - LMT 1916 Jul 28 -3:00 - -03 1980 Apr 6 2:00 -3:00 EU -03/-02 1996 0:00 - GMT +# +# Use the old name Scoresbysund, as the current name Ittoqqortoormiit +# exceeds tzdb's 14-letter limit and has no common English abbreviation. Zone America/Scoresbysund -1:27:52 - LMT 1916 Jul 28 # Ittoqqortoormiit -2:00 - -02 1980 Apr 6 2:00 -2:00 C-Eur -02/-01 1981 Mar 29 -1:00 EU -01/+00 -Zone America/Godthab -3:26:56 - LMT 1916 Jul 28 # Nuuk +Zone America/Nuuk -3:26:56 - LMT 1916 Jul 28 # Godthåb -3:00 - -03 1980 Apr 6 2:00 -3:00 EU -03/-02 -Zone America/Thule -4:35:08 - LMT 1916 Jul 28 # Pituffik air base +Zone America/Thule -4:35:08 - LMT 1916 Jul 28 # Pituffik -4:00 Thule A%sT # Estonia @@ -1234,7 +1262,7 @@ # From Urmet Jänes (2002-03-28): # The legislative reference is Government decree No. 84 on 2002-02-21. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Tallinn 1:39:00 - LMT 1880 1:39:00 - TMT 1918 Feb # Tallinn Mean Time 1:00 C-Eur CE%sT 1919 Jul @@ -1288,7 +1316,7 @@ # From Paul Eggert (2014-06-14): # Go with Oja over Shanks. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Finland 1942 only - Apr 2 24:00 1:00 S Rule Finland 1942 only - Oct 4 1:00 0 - Rule Finland 1981 1982 - Mar lastSun 2:00 1:00 S @@ -1297,7 +1325,7 @@ # Milne says Helsinki (Helsingfors) time was 1:39:49.2 (official document); # round to nearest. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Helsinki 1:39:49 - LMT 1878 May 31 1:39:49 - HMT 1921 May # Helsinki Mean Time 2:00 Finland EE%sT 1983 @@ -1320,10 +1348,58 @@ # Françoise Gauquelin, Problèmes de l'heure résolus en astrologie, # Guy Trédaniel, Paris 1987 +# From Michael Deckers (2020-06-11): +# the law of 1891 <https://gallica.bnf.fr/ark:/12148/bpt6k64415343.texteImage> +# was published on 1891-03-15, so it could only take force on 1891-03-16. + +# From Michael Deckers (2020-06-10): +# Le Gaulois, 1911-03-11, page 1/6, online at +# https://www.retronews.fr/societe/echo-de-presse/2018/01/29/1911-change-lheure-de-paris +# ... [ Instantly, all pressure driven clock dials halted... Nine minutes and +# twenty-one seconds later the hands resumed their circular motion. ] +# There are also precise reports about how the change was prepared in train +# stations: all the publicly visible clocks stopped at midnight railway time +# (or were covered), only the chief of service had a watch, labeled +# "Heure ancienne", that he kept running until it reached 00:04:21, when +# he announced "Heure nouvelle". See the "Le Petit Journal 1911-03-11". +# https://gallica.bnf.fr/ark:/12148/bpt6k6192911/f1.item.zoom +# +# From Michael Deckers (2020-06-12): +# That "all French clocks stopped" for 00:09:21 is a misreading of French +# newspapers; this sort of adjustment applies only to certain +# remote-controlled clocks ("pendules pneumatiques", of which there existed +# perhaps a dozen in Paris, and which simply could not be set back remotely), +# but not to all the clocks in all French towns and villages. For instance, +# the following story in the "Courrier de Saône-et-Loire" 1911-03-11, page 2: +# only works if legal time was stepped back (was not monotone): ... +# [One can observe that children who had been born at midnight less 5 +# minutes and who had died at midnight of the old time, would turn out to +# be dead before being born, time having been set back and having +# suppressed 9 minutes and 25 seconds of their existence, that is, more +# than they could spend.] +# +# From Paul Eggert (2020-06-12): +# French time in railway stations was legally five minutes behind civil time, +# which explains why railway "old time" ran to 00:04:21 instead of to 00:09:21. +# The law's text (which Michael Deckers noted is at +# <https://gallica.bnf.fr/ark:/12148/bpt6k2022333z/f2>) says only that +# at 1911-03-11 00:00 legal time was that of Paris mean time delayed by +# nine minutes and twenty-one seconds, and does not say how the +# transition from Paris mean time was to occur. +# +# tzdb has no way to represent stopped clocks. As the railway practice +# was to keep a watch running on "old time" to decide when to restart +# the other clocks, this could be modeled as a transition for "old time" at +# 00:09:21. However, since the law was ambiguous and clocks outside railway +# stations were probably done haphazardly with the popular impression being +# that the transition was done at 00:00 "old time", simply leave the time +# blank; this causes zic to default to 00:00 "old time" which is good enough. +# Do something similar for the 1891-03-16 transition. There are similar +# problems in Algiers, Monaco and Tunis. # # Shank & Pottenger seem to use '24:00' ambiguously; resolve it with Whitman. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule France 1916 only - Jun 14 23:00s 1:00 S Rule France 1916 1919 - Oct Sun>=1 23:00s 0 - Rule France 1917 only - Mar 24 23:00s 1:00 S @@ -1383,13 +1459,11 @@ # go with Excoffier's 28/3/76 0hUT and 25/9/76 23hUT. Rule France 1976 only - Mar 28 1:00 1:00 S Rule France 1976 only - Sep 26 1:00 0 - -# Shanks & Pottenger give 0:09:20 for Paris Mean Time, and Whitman 0:09:05, -# but Howse quotes the actual French legislation as saying 0:09:21. -# Go with Howse. Howse writes that the time in France was officially based +# Howse writes that the time in France was officially based # on PMT-0:09:21 until 1978-08-09, when the time base finally switched to UTC. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Europe/Paris 0:09:21 - LMT 1891 Mar 15 0:01 - 0:09:21 - PMT 1911 Mar 11 0:01 # Paris MT +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Europe/Paris 0:09:21 - LMT 1891 Mar 16 + 0:09:21 - PMT 1911 Mar 11 # Paris Mean Time # Shanks & Pottenger give 1940 Jun 14 0:00; go with Excoffier and Le Corre. 0:00 France WE%sT 1940 Jun 14 23:00 # Le Corre says Paris stuck with occupied-France time after the liberation; @@ -1418,7 +1492,7 @@ # this was equivalent to UT +03, not +04. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Germany 1946 only - Apr 14 2:00s 1:00 S Rule Germany 1946 only - Oct 7 2:00s 0 - Rule Germany 1947 1949 - Oct Sun>=1 2:00s 0 - @@ -1435,7 +1509,7 @@ Rule SovietZone 1945 only - Sep 24 3:00 1:00 S Rule SovietZone 1945 only - Nov 18 2:00s 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Berlin 0:53:28 - LMT 1893 Apr 1:00 C-Eur CE%sT 1945 May 24 2:00 1:00 SovietZone CE%sT 1946 @@ -1463,14 +1537,14 @@ # is in Europe. Our reference location Tbilisi is in the Asian part. # Gibraltar -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Gibraltar -0:21:24 - LMT 1880 Aug 2 0:00s 0:00 GB-Eire %s 1957 Apr 14 2:00 1:00 - CET 1982 1:00 EU CE%sT # Greece -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S # Whitman gives 1932 Jul 5 - Nov 1; go with Shanks & Pottenger. Rule Greece 1932 only - Jul 7 0:00 1:00 S Rule Greece 1932 only - Sep 1 0:00 0 - @@ -1494,7 +1568,7 @@ Rule Greece 1979 only - Sep 29 2:00 0 - Rule Greece 1980 only - Apr 1 0:00 1:00 S Rule Greece 1980 only - Sep 28 0:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Athens 1:34:52 - LMT 1895 Sep 14 1:34:52 - AMT 1916 Jul 28 0:01 # Athens MT 2:00 Greece EE%sT 1941 Apr 30 @@ -1505,38 +1579,73 @@ 2:00 EU EE%sT # Hungary -# From Paul Eggert (2014-07-15): -# Dates for 1916-1945 are taken from: -# Oross A. Jelen a múlt jövője: a nyári időszámítás Magyarországon 1916-1945. -# National Archives of Hungary (2012-10-29). -# http://mnl.gov.hu/a_het_dokumentuma/a_nyari_idoszamitas_magyarorszagon_19161945.html -# This source does not always give times, which are taken from Shanks -# & Pottenger (which disagree about the dates). -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -Rule Hungary 1918 only - Apr 1 3:00 1:00 S -Rule Hungary 1918 only - Sep 16 3:00 0 - -Rule Hungary 1919 only - Apr 15 3:00 1:00 S -Rule Hungary 1919 only - Nov 24 3:00 0 - + +# From Michael Deckers (2020-06-09): +# an Austrian encyclopedia of railroads of 1913, online at +# http://www.zeno.org/Roell-1912/A/Eisenbahnzeit +# says that the switch [to CET] happened on 1890-11-01. + +# From Géza Nyáry (2020-06-07): +# Data for 1918-1983 are based on the archive database of Library Hungaricana. +# The dates are collected from original, scanned governmental orders, +# bulletins, instructions and public press. +# [See URLs below.] + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +# https://library.hungaricana.hu/hu/view/OGYK_RT_1918/?pg=238 +# https://library.hungaricana.hu/hu/view/OGYK_RT_1919/?pg=808 +# https://library.hungaricana.hu/hu/view/OGYK_RT_1920/?pg=201 +Rule Hungary 1918 1919 - Apr 15 2:00 1:00 S +Rule Hungary 1918 1920 - Sep Mon>=15 3:00 0 - +Rule Hungary 1920 only - Apr 5 2:00 1:00 S +# https://library.hungaricana.hu/hu/view/OGYK_RT_1945/?pg=882 Rule Hungary 1945 only - May 1 23:00 1:00 S -Rule Hungary 1945 only - Nov 1 0:00 0 - +Rule Hungary 1945 only - Nov 1 1:00 0 - +# https://library.hungaricana.hu/hu/view/Delmagyarorszag_1946_03/?pg=49 Rule Hungary 1946 only - Mar 31 2:00s 1:00 S -Rule Hungary 1946 1949 - Oct Sun>=1 2:00s 0 - +# https://library.hungaricana.hu/hu/view/Delmagyarorszag_1946_09/?pg=54 +Rule Hungary 1946 only - Oct 7 2:00 0 - +# https://library.hungaricana.hu/hu/view/KulfBelfHirek_1947_04_1__001-123/?pg=90 +# https://library.hungaricana.hu/hu/view/DunantuliNaplo_1947_09/?pg=128 +# https://library.hungaricana.hu/hu/view/KulfBelfHirek_1948_03_3__001-123/?pg=304 +# https://library.hungaricana.hu/hu/view/Zala_1948_09/?pg=64 +# https://library.hungaricana.hu/hu/view/SatoraljaujhelyiLeveltar_ZempleniNepujsag_1948/?pg=53 +# https://library.hungaricana.hu/hu/view/SatoraljaujhelyiLeveltar_ZempleniNepujsag_1948/?pg=160 +# https://library.hungaricana.hu/hu/view/UjSzo_1949_01-04/?pg=102 +# https://library.hungaricana.hu/hu/view/KeletMagyarorszag_1949_03/?pg=96 +# https://library.hungaricana.hu/hu/view/Delmagyarorszag_1949_09/?pg=94 Rule Hungary 1947 1949 - Apr Sun>=4 2:00s 1:00 S -Rule Hungary 1950 only - Apr 17 2:00s 1:00 S -Rule Hungary 1950 only - Oct 23 2:00s 0 - -Rule Hungary 1954 1955 - May 23 0:00 1:00 S -Rule Hungary 1954 1955 - Oct 3 0:00 0 - -Rule Hungary 1956 only - Jun Sun>=1 0:00 1:00 S -Rule Hungary 1956 only - Sep lastSun 0:00 0 - -Rule Hungary 1957 only - Jun Sun>=1 1:00 1:00 S -Rule Hungary 1957 only - Sep lastSun 3:00 0 - -Rule Hungary 1980 only - Apr 6 1:00 1:00 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Europe/Budapest 1:16:20 - LMT 1890 Oct +Rule Hungary 1947 1949 - Oct Sun>=1 2:00s 0 - +# https://library.hungaricana.hu/hu/view/DTT_KOZL_TanacsokKozlonye_1954/?pg=513 +Rule Hungary 1954 only - May 23 0:00 1:00 S +Rule Hungary 1954 only - Oct 3 0:00 0 - +# https://library.hungaricana.hu/hu/view/DTT_KOZL_TanacsokKozlonye_1955/?pg=398 +Rule Hungary 1955 only - May 22 2:00 1:00 S +Rule Hungary 1955 only - Oct 2 3:00 0 - +# https://library.hungaricana.hu/hu/view/HevesMegyeiNepujsag_1956_06/?pg=0 +# https://library.hungaricana.hu/hu/view/EszakMagyarorszag_1956_06/?pg=6 +# https://library.hungaricana.hu/hu/view/SzolnokMegyeiNeplap_1957_04/?pg=120 +# https://library.hungaricana.hu/hu/view/PestMegyeiHirlap_1957_09/?pg=143 +Rule Hungary 1956 1957 - Jun Sun>=1 2:00 1:00 S +Rule Hungary 1956 1957 - Sep lastSun 3:00 0 - +# https://library.hungaricana.hu/hu/view/DTT_KOZL_TanacsokKozlonye_1980/?pg=189 +Rule Hungary 1980 only - Apr 6 0:00 1:00 S +Rule Hungary 1980 only - Sep 28 1:00 0 - +# https://library.hungaricana.hu/hu/view/DTT_KOZL_TanacsokKozlonye_1980/?pg=1227 +# https://library.hungaricana.hu/hu/view/Delmagyarorszag_1981_01/?pg=79 +# https://library.hungaricana.hu/hu/view/DTT_KOZL_TanacsokKozlonye_1982/?pg=115 +# https://library.hungaricana.hu/hu/view/DTT_KOZL_TanacsokKozlonye_1983/?pg=85 +Rule Hungary 1981 1983 - Mar lastSun 0:00 1:00 S +Rule Hungary 1981 1983 - Sep lastSun 1:00 0 - +# +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Europe/Budapest 1:16:20 - LMT 1890 Nov 1 1:00 C-Eur CE%sT 1918 - 1:00 Hungary CE%sT 1941 Apr 8 +# https://library.hungaricana.hu/hu/view/OGYK_RT_1941/?pg=1204 +# https://library.hungaricana.hu/hu/view/OGYK_RT_1942/?pg=3955 + 1:00 Hungary CE%sT 1941 Apr 7 23:00 1:00 C-Eur CE%sT 1945 - 1:00 Hungary CE%sT 1980 Sep 28 2:00s + 1:00 Hungary CE%sT 1984 1:00 EU CE%sT # Iceland @@ -1550,7 +1659,7 @@ # # From January 1st, 1908 the whole of Iceland was standardised at 1 hour # behind GMT. Previously, local mean solar time was used in different parts -# of Iceland, the almanak had been based on Reykjavik mean solar time which +# of Iceland, the almanak had been based on Reykjavík mean solar time which # was 1 hour and 28 minutes behind GMT. # # "first day of winter" referred to [below] means the first day of the 26 weeks @@ -1572,7 +1681,7 @@ # The information below is taken from the 1988 Almanak; see # http://www.almanak.hi.is/klukkan.html # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Iceland 1917 1919 - Feb 19 23:00 1:00 - Rule Iceland 1917 only - Oct 21 1:00 0 - Rule Iceland 1918 1919 - Nov 16 1:00 0 - @@ -1592,7 +1701,7 @@ Rule Iceland 1949 only - Oct 30 1:00s 0 - Rule Iceland 1950 1966 - Oct Sun>=22 1:00s 0 - Rule Iceland 1967 only - Oct 29 1:00s 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Atlantic/Reykjavik -1:28 - LMT 1908 -1:00 Iceland -01/+00 1968 Apr 7 1:00s 0:00 - GMT @@ -1606,6 +1715,25 @@ # But these events all occurred before the 1970 cutoff, # so record only the time in Rome. # +# From Stephen Trainor (2019-05-06): +# http://www.ac-ilsestante.it/MERIDIANE/ora_legale/ORA_LEGALE_ESTIVA_IN_ITALIA.htm +# ... the [1866] law went into effect on 12 December 1866, rather than +# the date of the decree (22 Sep 1866) +# https://web.archive.org/web/20070824155341/http://www.iav.it/planetario/didastro/didastro/english.htm +# ... "In Italy in 1866 there were 6 railway times (Torino, Verona, Firenze, +# Roma, Napoli, Palermo). On that year it was decided to unify them, adopting +# the average time of Rome (even if this city was not yet part of the +# kingdom). On the 12th December 1866, on the starting of the winter time +# table, it took effect in the railways, the post office and the telegraph, +# not only for the internal service but also for the public.... Milano set +# the public watches on the Rome time on the same day (12th December 1866), +# Torino and Bologna on the 1st January 1867, Venezia the 1st May 1880 and the +# last city was Cagliari in 1886." +# +# From Luigi Rosa (2019-05-07): +# this is the scan of the decree: +# http://www.radiomarconi.com/marconi/filopanti/1866c.jpg +# # From Michael Deckers (2016-10-24): # http://www.ac-ilsestante.it/MERIDIANE/ora_legale quotes a law of 1893-08-10 # ... [translated as] "The preceding dispositions will enter into @@ -1616,6 +1744,7 @@ # The authoritative source for time in Italy is the national metrological # institute, which has a summary page of historical DST data at # http://www.inrim.it/res/tf/ora_legale_i.shtml +# [now at http://oldsite.inrim.it/res/tf/ora_legale_i.shtml as of 2017] # (2016-10-24): # http://www.renzobaldini.it/le-ore-legali-in-italia/ # has still different data for 1944. It divides Italy in two, as @@ -1630,6 +1759,13 @@ # advanced to sixty minutes later starting at hour two on 1944-04-02; ... # Starting at hour three on the date 1944-09-17 standard time will be resumed. # +# From Alois Triendl (2019-07-02): +# I spent 6 Euros to buy two archive copies of Il Messaggero, a Roman paper, +# for 1 and 2 April 1944. The edition of 2 April has this note: "Tonight at 2 +# am, put forward the clock by one hour. Remember that in the night between +# today and Monday the 'ora legale' will come in force again." That makes it +# clear that in Rome the change was on Monday, 3 April 1944 at 2 am. +# # From Paul Eggert (2016-10-27): # Go with INRiM for DST rules, except as corrected by Inglis for 1944 # for the Kingdom of Italy. This is consistent with Renzo Baldini. @@ -1637,7 +1773,7 @@ # to 1944-06-04; although Rome was an open city during this period, it # was effectively controlled by Germany. # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Italy 1916 only - Jun 3 24:00 1:00 S Rule Italy 1916 1917 - Sep 30 24:00 0 - Rule Italy 1917 only - Mar 31 24:00 1:00 S @@ -1679,8 +1815,8 @@ Rule Italy 1977 1979 - May Sun>=22 0:00s 1:00 S Rule Italy 1978 only - Oct 1 0:00s 0 - Rule Italy 1979 only - Sep 30 0:00s 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Europe/Rome 0:49:56 - LMT 1866 Sep 22 +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Europe/Rome 0:49:56 - LMT 1866 Dec 12 0:49:56 - RMT 1893 Oct 31 23:49:56 # Rome Mean 1:00 Italy CE%sT 1943 Sep 10 1:00 C-Eur CE%sT 1944 Jun 4 @@ -1747,7 +1883,7 @@ # urged Lithuania and Estonia to adopt a similar time policy, but it # appears that they will not do so.... -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Latvia 1989 1996 - Mar lastSun 2:00s 1:00 S Rule Latvia 1989 1996 - Sep lastSun 2:00s 0 - @@ -1755,7 +1891,7 @@ # Byalokoz 1919 says Latvia was 1:36:34. # Go with Byalokoz. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Riga 1:36:34 - LMT 1880 1:36:34 - RMT 1918 Apr 15 2:00 # Riga MT 1:36:34 1:00 LST 1918 Sep 16 3:00 # Latvian ST @@ -1777,15 +1913,10 @@ # From Paul Eggert (2013-09-09): # Shanks & Pottenger say Vaduz is like Zurich. -# From Alois Treindl (2013-09-18): -# http://www.eliechtensteinensia.li/LIJ/1978/1938-1978/1941.pdf -# ... confirms on p. 6 that Liechtenstein followed Switzerland in 1941 and 1942. -# I ... translate only the last two paragraphs: -# ... during second world war, in the years 1941 and 1942, Liechtenstein -# introduced daylight saving time, adapting to Switzerland. From 1943 on -# central European time was in force throughout the year. -# From a report of the duke's government to the high council, -# regarding the introduction of a time law, of 31 May 1977. +# From Alois Treindl (2019-07-04): +# I was able to access the online archive of the Vaduz paper Vaterland ... +# I could confirm from the paper that Liechtenstein did in fact follow +# the same DST in 1941 and 1942 as Switzerland did. Link Europe/Zurich Europe/Vaduz @@ -1825,7 +1956,7 @@ # http://www.lrvk.lt/nut/11/n1749.htm -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Vilnius 1:41:16 - LMT 1880 1:24:00 - WMT 1917 # Warsaw Mean Time 1:35:36 - KMT 1919 Oct 10 # Kaunas Mean Time @@ -1845,7 +1976,7 @@ # Luxembourg # Whitman disagrees with most of these dates in minor ways; # go with Shanks & Pottenger. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Lux 1916 only - May 14 23:00 1:00 S Rule Lux 1916 only - Oct 1 1:00 0 - Rule Lux 1917 only - Apr 28 23:00 1:00 S @@ -1869,7 +2000,7 @@ Rule Lux 1927 only - Apr 9 23:00 1:00 S Rule Lux 1928 only - Apr 14 23:00 1:00 S Rule Lux 1929 only - Apr 20 23:00 1:00 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Luxembourg 0:24:36 - LMT 1904 Jun 1:00 Lux CE%sT 1918 Nov 25 0:00 Lux WE%sT 1929 Oct 6 2:00s @@ -1878,7 +2009,7 @@ 1:00 Belgium CE%sT 1977 1:00 EU CE%sT -# Macedonia +# North Macedonia # See Europe/Belgrade. # Malta @@ -1886,7 +2017,7 @@ # From Paul Eggert (2016-10-21): # Assume 1900-1972 was like Rome, overriding Shanks. # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Malta 1973 only - Mar 31 0:00s 1:00 S Rule Malta 1973 only - Sep 29 0:00s 0 - Rule Malta 1974 only - Apr 21 0:00s 1:00 S @@ -1894,7 +2025,7 @@ Rule Malta 1975 1979 - Apr Sun>=15 2:00 1:00 S Rule Malta 1975 1980 - Sep Sun>=15 2:00 0 - Rule Malta 1980 only - Mar 31 2:00 1:00 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Malta 0:58:04 - LMT 1893 Nov 2 0:00s # Valletta 1:00 Italy CE%sT 1973 Mar 31 1:00 Malta CE%sT 1981 @@ -1959,11 +2090,11 @@ # says the 2014-03-30 spring-forward transition was at 02:00 local time. # Guess that since 1997 Moldova has switched one hour before the EU. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Moldova 1997 max - Mar lastSun 2:00 1:00 S Rule Moldova 1997 max - Oct lastSun 3:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Chisinau 1:55:20 - LMT 1880 1:55 - CMT 1918 Feb 15 # Chisinau MT 1:44:24 - BMT 1931 Jul 24 # Bucharest MT @@ -1977,11 +2108,24 @@ 2:00 Moldova EE%sT # Monaco -# Shanks & Pottenger give 0:09:20 for Paris Mean Time; go with Howse's -# more precise 0:09:21. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Europe/Monaco 0:29:32 - LMT 1891 Mar 15 - 0:09:21 - PMT 1911 Mar 11 # Paris Mean Time +# +# From Michael Deckers (2020-06-12): +# In the "Journal de Monaco" of 1892-05-24, online at +# https://journaldemonaco.gouv.mc/var/jdm/storage/original/application/b1c67c12c5af11b41ea888fb048e4fe8.pdf +# we read: ... +# [In virtue of a Sovereign Ordinance of the May 13 of the current [year], +# legal time in the Principality will be set to, from the date of June 1, +# 1892 onwards, to the meridian of Paris, as in France.] +# In the "Journal de Monaco" of 1911-03-28, online at +# https://journaldemonaco.gouv.mc/var/jdm/storage/original/application/de74ffb7db53d4f599059fe8f0ed482a.pdf +# we read an ordinance of 1911-03-16: ... +# [Legal time in the Principality will be set, from the date of promulgation +# of the present ordinance, to legal time in France.... Consequently, legal +# time will be retarded by 9 minutes and 21 seconds.] +# +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Europe/Monaco 0:29:32 - LMT 1892 Jun 1 + 0:09:21 - PMT 1911 Mar 29 # Paris Mean Time 0:00 France WE%sT 1945 Sep 16 3:00 1:00 France CE%sT 1977 1:00 EU CE%sT @@ -2029,7 +2173,7 @@ # The data entries before 1945 are taken from # https://www.staff.science.uu.nl/~gent0113/wettijd/wettijd.htm -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Neth 1916 only - May 1 0:00 1:00 NST # Netherlands Summer Time Rule Neth 1916 only - Oct 1 0:00 0 AMT # Amsterdam Mean Time Rule Neth 1917 only - Apr 16 2:00s 1:00 NST @@ -2054,8 +2198,8 @@ Rule Neth 1945 only - Sep 16 2:00s 0 - # # Amsterdam Mean Time was +00:19:32.13, but the .13 is omitted -# below because the current format requires GMTOFF to be an integer. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# below because the current format requires STDOFF to be an integer. +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Amsterdam 0:19:32 - LMT 1835 0:19:32 Neth %s 1937 Jul 1 0:20 Neth +0020/+0120 1940 May 16 0:00 @@ -2066,7 +2210,7 @@ # Norway # http://met.no/met/met_lex/q_u/sommertid.html (2004-01) agrees with Shanks & # Pottenger. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Norway 1916 only - May 22 1:00 1:00 S Rule Norway 1916 only - Sep 30 0:00 0 - Rule Norway 1945 only - Apr 2 2:00s 1:00 S @@ -2074,7 +2218,7 @@ Rule Norway 1959 1964 - Mar Sun>=15 2:00s 1:00 S Rule Norway 1959 1965 - Sep Sun>=15 2:00s 0 - Rule Norway 1965 only - Apr 25 2:00s 1:00 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Oslo 0:43:00 - LMT 1895 Jan 1 1:00 Norway CE%sT 1940 Aug 10 23:00 1:00 C-Eur CE%sT 1945 Apr 2 2:00 @@ -2135,7 +2279,7 @@ # The 1919 dates and times can be found in Tygodnik Urzędowy nr 1 (1919-03-20), # <http://www.wbc.poznan.pl/publication/32156> pp 1-2. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Poland 1918 1919 - Sep 16 2:00s 0 - Rule Poland 1919 only - Apr 15 2:00s 1:00 S Rule Poland 1944 only - Apr 3 2:00s 1:00 S @@ -2165,7 +2309,7 @@ Rule Poland 1960 only - Apr 3 1:00s 1:00 S Rule Poland 1961 1964 - May lastSun 1:00s 1:00 S Rule Poland 1962 1964 - Sep lastSun 1:00s 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Warsaw 1:24:00 - LMT 1880 1:24:00 - WMT 1915 Aug 5 # Warsaw Mean Time 1:00 C-Eur CE%sT 1918 Sep 16 3:00 @@ -2206,7 +2350,7 @@ # Guess that the Azores changed to EU rules in 1992 (since that's when Portugal # harmonized with EU rules), and that they stayed +0:00 that winter. # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S # DSH writes that despite Decree 1,469 (1915), the change to the clocks was not # done every year, depending on what Spain did, because of railroad schedules. # Go with Shanks & Pottenger. @@ -2270,7 +2414,7 @@ Rule Port 1981 1982 - Mar lastSun 1:00s 1:00 S Rule Port 1983 only - Mar lastSun 2:00s 1:00 S # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Lisbon -0:36:45 - LMT 1884 -0:36:45 - LMT 1912 Jan 1 0:00u # Lisbon MT 0:00 Port WE%sT 1966 Apr 3 2:00 @@ -2319,7 +2463,7 @@ # assume that Romania and Moldova switched to EU rules in 1997, # the same year as Bulgaria. # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Romania 1932 only - May 21 0:00s 1:00 S Rule Romania 1932 1939 - Oct Sun>=1 0:00s 0 - Rule Romania 1933 1939 - Apr Sun>=2 0:00s 1:00 S @@ -2329,7 +2473,7 @@ Rule Romania 1980 only - Sep lastSun 1:00 0 - Rule Romania 1991 1993 - Mar lastSun 0:00s 1:00 S Rule Romania 1991 1993 - Sep lastSun 0:00s 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Bucharest 1:44:24 - LMT 1891 Oct 1:44:24 - BMT 1931 Jul 24 # Bucharest MT 2:00 Romania EE%sT 1981 Mar 29 2:00s @@ -2493,6 +2637,12 @@ # Europe/Kaliningrad covers... # 39 RU-KGD Kaliningrad Oblast +# From Paul Eggert (2019-07-25): +# Although Shanks lists 1945-01-01 as the date for transition from +# +01/+02 to +02/+03, more likely this is a placeholder. Guess that +# the transition occurred at 1945-04-10 00:00, which is about when +# Königsberg surrendered to Soviet troops. (Thanks to Alois Triendl.) + # From Paul Eggert (2016-03-18): # The 1989 transition is from USSR act No. 227 (1989-03-14). @@ -2509,8 +2659,8 @@ # Moscow on 1991-11-03, switched to Moscow-1 on 1992-01-19. Zone Europe/Kaliningrad 1:22:00 - LMT 1893 Apr - 1:00 C-Eur CE%sT 1945 - 2:00 Poland CE%sT 1946 + 1:00 C-Eur CE%sT 1945 Apr 10 + 2:00 Poland EE%sT 1946 Apr 7 3:00 Russia MSK/MSD 1989 Mar 26 2:00s 2:00 Russia EE%sT 2011 Mar 27 2:00s 3:00 - +03 2014 Oct 26 2:00s @@ -2765,6 +2915,19 @@ # The law has been published today on # http://publication.pravo.gov.ru/Document/View/0001201810110037 +# From Alexander Krivenyshev (2020-11-27): +# The State Duma approved (Nov 24, 2020) the transition of the Volgograd +# region to the Moscow time zone.... +# https://sozd.duma.gov.ru/bill/1012130-7 +# +# From Stepan Golosunov (2020-12-05): +# Currently proposed text for the second reading (expected on December 8) ... +# changes the date to December 27. https://v1.ru/text/gorod/2020/12/04/69601031/ +# +# From Stepan Golosunov (2020-12-22): +# The law was published today on +# http://publication.pravo.gov.ru/Document/View/0001202012220002 + Zone Europe/Volgograd 2:57:40 - LMT 1920 Jan 3 3:00 - +03 1930 Jun 21 4:00 - +04 1961 Nov 11 @@ -2774,7 +2937,8 @@ 3:00 Russia +03/+04 2011 Mar 27 2:00s 4:00 - +04 2014 Oct 26 2:00s 3:00 - +03 2018 Oct 28 2:00s - 4:00 - +04 + 4:00 - +04 2020 Dec 27 2:00s + 3:00 - +03 # From Paul Eggert (2016-11-11): # Europe/Saratov covers: @@ -3368,7 +3532,7 @@ # See Europe/Rome. # Serbia -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Belgrade 1:22:00 - LMT 1884 1:00 - CET 1941 Apr 18 23:00 1:00 C-Eur CE%sT 1945 @@ -3382,7 +3546,7 @@ Link Europe/Belgrade Europe/Ljubljana # Slovenia Link Europe/Belgrade Europe/Podgorica # Montenegro Link Europe/Belgrade Europe/Sarajevo # Bosnia and Herzegovina -Link Europe/Belgrade Europe/Skopje # Macedonia +Link Europe/Belgrade Europe/Skopje # North Macedonia Link Europe/Belgrade Europe/Zagreb # Croatia # Slovakia @@ -3411,14 +3575,14 @@ # fallback transition from the next day's 00:59... to 00:00. # From Michael Deckers (2016-12-15): -# The Royal Decree of 1900-06-26 quoted by Planesas, online at +# The Royal Decree of 1900-07-26 quoted by Planesas, online at # https://www.boe.es/datos/pdfs/BOE//1900/209/A00383-00384.pdf # says in its article 5 (my translation): # These dispositions will enter into force beginning with the # instant at which, according to the time indicated in article 1, # the 1st day of January of 1901 will begin. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Spain 1918 only - Apr 15 23:00 1:00 S Rule Spain 1918 1919 - Oct 6 24:00s 0 - Rule Spain 1919 only - Apr 6 23:00 1:00 S @@ -3474,7 +3638,7 @@ Rule SpainAfrica 1977 only - Sep 28 0:00 0 - Rule SpainAfrica 1978 only - Jun 1 0:00 1:00 S Rule SpainAfrica 1978 only - Aug 4 0:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Madrid -0:14:44 - LMT 1900 Dec 31 23:45:16 0:00 Spain WE%sT 1940 Mar 16 23:00 1:00 Spain CE%sT 1979 @@ -3542,7 +3706,7 @@ # # Source: The newspaper "Dagens Nyheter", 1916-10-01, page 7 upper left. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Stockholm 1:12:12 - LMT 1879 Jan 1 1:00:14 - SET 1900 Jan 1 # Swedish Time 1:00 - CET 1916 May 14 23:00 @@ -3555,7 +3719,7 @@ # By the end of the 18th century clocks and watches became commonplace # and their performance improved enormously. Communities began to keep # mean time in preference to apparent time - Geneva from 1780 .... -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S # From Whitman (who writes "Midnight?"): # Rule Swiss 1940 only - Nov 2 0:00 1:00 S # Rule Swiss 1940 only - Dec 31 0:00 0 - @@ -3642,10 +3806,10 @@ # 1853-07-16, though it probably occurred at some other date in Zurich, and # legal civil time probably changed at still some other transition date. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Swiss 1941 1942 - May Mon>=1 1:00 1:00 S Rule Swiss 1941 1942 - Oct Mon>=1 2:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Zurich 0:34:08 - LMT 1853 Jul 16 # See above comment. 0:29:46 - BMT 1894 Jun # Bern Mean Time 1:00 Swiss CE%sT 1981 @@ -3653,20 +3817,75 @@ # Turkey +# From Alois Treindl (2019-08-12): +# http://www.astrolojidergisi.com/yazsaati.htm has researched the time zone +# history of Turkey, based on newspaper archives and official documents. +# From Paul Eggert (2019-08-28): +# That source (Oya Vulaş, "Türkiye'de Yaz Saati Uygulamaları") +# is used for 1940/1972, where it seems more reliable than our other +# sources. + +# From Kıvanç Yazan (2019-08-12): +# http://www.resmigazete.gov.tr/arsiv/14539.pdf#page=24 +# 1973-06-03 01:00 -> 02:00, 1973-11-04 02:00 -> 01:00 +# +# http://www.resmigazete.gov.tr/arsiv/14829.pdf#page=1 +# 1974-03-31 02:00 -> 03:00, 1974-11-03 02:00 -> 01:00 +# +# http://www.resmigazete.gov.tr/arsiv/15161.pdf#page=1 +# 1975-03-22 02:00 -> 03:00, 1975-11-02 02:00 -> 01:00 +# +# http://www.resmigazete.gov.tr/arsiv/15535_1.pdf#page=1 +# 1976-03-21 02:00 -> 03:00, 1976-10-31 02:00 -> 01:00 +# +# http://www.resmigazete.gov.tr/arsiv/15778.pdf#page=5 +# 1977-04-03 02:00 -> 03:00, 1977-10-16 02:00 -> 01:00, +# 1978-04-02 02:00 -> 03:00 (not applied, see below) +# 1978-10-15 02:00 -> 01:00 (not applied, see below) +# 1979-04-01 02:00 -> 03:00 (not applied, see below) +# 1979-10-14 02:00 -> 01:00 (not applied, see below) +# +# http://www.resmigazete.gov.tr/arsiv/16245.pdf#page=17 +# This cancels the previous decision, and repeats it only for 1978. +# 1978-04-02 02:00 -> 03:00, 1978-10-15 02:00 -> 01:00 +# (not applied due to standard TZ change below) +# +# http://www.resmigazete.gov.tr/arsiv/16331.pdf#page=3 +# This decision changes the default longitude for Turkish time zone from 30 +# degrees East to 45 degrees East. This means a standard TZ change, from +2 +# to +3. This is published & applied on 1978-06-29. At that time, Turkey was +# already on summer time (already on 45E). Hence, this new law just meant an +# "continuous summer time". Note that this was reversed in a few years. +# +# http://www.resmigazete.gov.tr/arsiv/18119_1.pdf#page=1 +# 1983-07-31 02:00 -> 03:00 (note that this jumps TZ to +4) +# 1983-10-02 02:00 -> 01:00 (back to +3) +# +# http://www.resmigazete.gov.tr/arsiv/18561.pdf (page 1 and 34) +# At this time, Turkey is still on +3 with no spring-forward on early +# 1984. This decision is published on 10/31/1984. Page 1 declares +# the decision of reverting the "default longitude change". So the +# standard time should go back to +3 (30E). And page 34 explains when +# that will happen: 1984-11-01 02:00 -> 01:00. You can think of this +# as "end of continuous summer time, change of standard time zone". +# +# http://www.resmigazete.gov.tr/arsiv/18713.pdf#page=1 +# 1985-04-20 01:00 -> 02:00, 1985-09-28 02:00 -> 01:00 + # From Kıvanç Yazan (2016-09-25): # 1) For 1986-2006, DST started at 01:00 local and ended at 02:00 local, with # no exceptions. # 2) 1994's lastSun was overridden with Mar 20 ... # Here are official papers: -# http://www.resmigazete.gov.tr/arsiv/19032.pdf - page 2 for 1986 -# http://www.resmigazete.gov.tr/arsiv/19400.pdf - page 4 for 1987 -# http://www.resmigazete.gov.tr/arsiv/19752.pdf - page 15 for 1988 -# http://www.resmigazete.gov.tr/arsiv/20102.pdf - page 6 for 1989 -# http://www.resmigazete.gov.tr/arsiv/20464.pdf - page 1 for 1990 - 1992 -# http://www.resmigazete.gov.tr/arsiv/21531.pdf - page 15 for 1993 - 1995 -# http://www.resmigazete.gov.tr/arsiv/21879.pdf - page 1 for overriding 1994 -# http://www.resmigazete.gov.tr/arsiv/22588.pdf - page 1 for 1996, 1997 -# http://www.resmigazete.gov.tr/arsiv/23286.pdf - page 10 for 1998 - 2000 +# http://www.resmigazete.gov.tr/arsiv/19032.pdf#page=2 for 1986 +# http://www.resmigazete.gov.tr/arsiv/19400.pdf#page=4 for 1987 +# http://www.resmigazete.gov.tr/arsiv/19752.pdf#page=15 for 1988 +# http://www.resmigazete.gov.tr/arsiv/20102.pdf#page=6 for 1989 +# http://www.resmigazete.gov.tr/arsiv/20464.pdf#page=1 for 1990 - 1992 +# http://www.resmigazete.gov.tr/arsiv/21531.pdf#page=15 for 1993 - 1995 +# http://www.resmigazete.gov.tr/arsiv/21879.pdf#page=1 for overriding 1994 +# http://www.resmigazete.gov.tr/arsiv/22588.pdf#page=1 for 1996, 1997 +# http://www.resmigazete.gov.tr/arsiv/23286.pdf#page=10 for 1998 - 2000 # http://www.resmigazete.gov.tr/eskiler/2001/03/20010324.htm#2 - for 2001 # http://www.resmigazete.gov.tr/eskiler/2002/03/20020316.htm#2 - for 2002-2006 # From Paul Eggert (2016-09-25): @@ -3736,7 +3955,7 @@ # Although Google Translate misfires on that source, it looks like # Turkey reversed last month's decision, and so will stay at +03. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Turkey 1916 only - May 1 0:00 1:00 S Rule Turkey 1916 only - Oct 1 0:00 0 - Rule Turkey 1920 only - Mar 28 0:00 1:00 S @@ -3750,56 +3969,46 @@ Rule Turkey 1924 only - May 13 0:00 1:00 S Rule Turkey 1924 1925 - Oct 1 0:00 0 - Rule Turkey 1925 only - May 1 0:00 1:00 S -Rule Turkey 1940 only - Jun 30 0:00 1:00 S -Rule Turkey 1940 only - Oct 5 0:00 0 - +Rule Turkey 1940 only - Jul 1 0:00 1:00 S +Rule Turkey 1940 only - Oct 6 0:00 0 - Rule Turkey 1940 only - Dec 1 0:00 1:00 S Rule Turkey 1941 only - Sep 21 0:00 0 - Rule Turkey 1942 only - Apr 1 0:00 1:00 S -# Whitman omits the next two transition and gives 1945 Oct 1; -# go with Shanks & Pottenger. -Rule Turkey 1942 only - Nov 1 0:00 0 - -Rule Turkey 1945 only - Apr 2 0:00 1:00 S Rule Turkey 1945 only - Oct 8 0:00 0 - Rule Turkey 1946 only - Jun 1 0:00 1:00 S Rule Turkey 1946 only - Oct 1 0:00 0 - Rule Turkey 1947 1948 - Apr Sun>=16 0:00 1:00 S -Rule Turkey 1947 1950 - Oct Sun>=2 0:00 0 - +Rule Turkey 1947 1951 - Oct Sun>=2 0:00 0 - Rule Turkey 1949 only - Apr 10 0:00 1:00 S -Rule Turkey 1950 only - Apr 19 0:00 1:00 S +Rule Turkey 1950 only - Apr 16 0:00 1:00 S Rule Turkey 1951 only - Apr 22 0:00 1:00 S -Rule Turkey 1951 only - Oct 8 0:00 0 - +# DST for 15 months; unusual but we'll let it pass. Rule Turkey 1962 only - Jul 15 0:00 1:00 S -Rule Turkey 1962 only - Oct 8 0:00 0 - +Rule Turkey 1963 only - Oct 30 0:00 0 - Rule Turkey 1964 only - May 15 0:00 1:00 S Rule Turkey 1964 only - Oct 1 0:00 0 - -Rule Turkey 1970 1972 - May Sun>=2 0:00 1:00 S -Rule Turkey 1970 1972 - Oct Sun>=2 0:00 0 - Rule Turkey 1973 only - Jun 3 1:00 1:00 S -Rule Turkey 1973 only - Nov 4 3:00 0 - +Rule Turkey 1973 1976 - Oct Sun>=31 2:00 0 - Rule Turkey 1974 only - Mar 31 2:00 1:00 S -Rule Turkey 1974 only - Nov 3 5:00 0 - -Rule Turkey 1975 only - Mar 30 0:00 1:00 S -Rule Turkey 1975 1976 - Oct lastSun 0:00 0 - -Rule Turkey 1976 only - Jun 1 0:00 1:00 S -Rule Turkey 1977 1978 - Apr Sun>=1 0:00 1:00 S -Rule Turkey 1977 only - Oct 16 0:00 0 - -Rule Turkey 1979 1980 - Apr Sun>=1 3:00 1:00 S -Rule Turkey 1979 1982 - Oct Mon>=11 0:00 0 - -Rule Turkey 1981 1982 - Mar lastSun 3:00 1:00 S -Rule Turkey 1983 only - Jul 31 0:00 1:00 S -Rule Turkey 1983 only - Oct 2 0:00 0 - -Rule Turkey 1985 only - Apr 20 0:00 1:00 S -Rule Turkey 1985 only - Sep 28 0:00 0 - +Rule Turkey 1975 only - Mar 22 2:00 1:00 S +Rule Turkey 1976 only - Mar 21 2:00 1:00 S +Rule Turkey 1977 1978 - Apr Sun>=1 2:00 1:00 S +Rule Turkey 1977 1978 - Oct Sun>=15 2:00 0 - +Rule Turkey 1978 only - Jun 29 0:00 0 - +Rule Turkey 1983 only - Jul 31 2:00 1:00 S +Rule Turkey 1983 only - Oct 2 2:00 0 - +Rule Turkey 1985 only - Apr 20 1:00s 1:00 S +Rule Turkey 1985 only - Sep 28 1:00s 0 - Rule Turkey 1986 1993 - Mar lastSun 1:00s 1:00 S Rule Turkey 1986 1995 - Sep lastSun 1:00s 0 - Rule Turkey 1994 only - Mar 20 1:00s 1:00 S Rule Turkey 1995 2006 - Mar lastSun 1:00s 1:00 S Rule Turkey 1996 2006 - Oct lastSun 1:00s 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Europe/Istanbul 1:55:52 - LMT 1880 1:56:56 - IMT 1910 Oct # Istanbul Mean Time? - 2:00 Turkey EE%sT 1978 Oct 15 - 3:00 Turkey +03/+04 1985 Apr 20 + 2:00 Turkey EE%sT 1978 Jun 29 + 3:00 Turkey +03/+04 1984 Nov 1 2:00 2:00 Turkey EE%sT 2007 2:00 EU EE%sT 2011 Mar 27 1:00u 2:00 - EET 2011 Mar 28 1:00u @@ -3892,16 +4101,8 @@ # controversial, and some day "Kyiv" may become substantially more popular in # English; in the meantime, stick with the traditional English "Kiev" as that # means less disruption for our users. -# -# Anyway, none of the common English-language spellings (Kiev, Kyiv, Kieff, -# Kijeff, Kijev, Kiyef, Kiyeff) do justice to the common pronunciation in -# Ukrainian, namely [ˈkɪjiu̯] (IPA). This pronunciation has nothing like an -# English "v" or "f", and instead trails off with what an English-speaker -# would call a demure "oo" sound, and it would would be better anglicized as -# "Kuiyu". Here's a sound file, if you would like to do as the Kuiyuvians do: -# https://commons.wikimedia.org/wiki/File:Uk-Київ.ogg -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] # This represents most of Ukraine. See above for the spelling of "Kiev". Zone Europe/Kiev 2:02:04 - LMT 1880 2:02:04 - KMT 1924 May 2 # Kiev Mean Time @@ -3912,7 +4113,7 @@ 2:00 1:00 EEST 1991 Sep 29 3:00 2:00 E-Eur EE%sT 1995 2:00 EU EE%sT -# Ruthenia used CET 1990/1991. +# Transcarpathia used CET 1990/1991. # "Uzhhorod" is the transliteration of the Rusyn/Ukrainian pronunciation, but # "Uzhgorod" is more common in English. Zone Europe/Uzhgorod 1:29:12 - LMT 1890 Oct
diff --git a/make/data/tzdata/factory b/make/data/tzdata/factory index 6ef6bca..a05346a 100644 --- a/make/data/tzdata/factory +++ b/make/data/tzdata/factory
@@ -31,5 +31,5 @@ # time zone abbreviation "-00", indicating that the actual time zone # is unknown. -# Zone NAME GMTOFF RULES FORMAT +# Zone NAME STDOFF RULES FORMAT Zone Factory 0 - -00
diff --git a/make/data/tzdata/iso3166.tab b/make/data/tzdata/iso3166.tab index 38a3a1e..544b303 100644 --- a/make/data/tzdata/iso3166.tab +++ b/make/data/tzdata/iso3166.tab
@@ -32,8 +32,8 @@ # All text uses UTF-8 encoding. The columns of the table are as follows: # # 1. ISO 3166-1 alpha-2 country code, current as of -# ISO 3166-1 N905 (2016-11-15). See: Updates on ISO 3166-1 -# http://isotc.iso.org/livelink/livelink/Open/16944257 +# ISO 3166-1 N976 (2018-11-06). See: Updates on ISO 3166-1 +# https://isotc.iso.org/livelink/livelink/Open/16944257 # 2. The usual English name for the coded region, # chosen so that alphabetic sorting of subsets produces helpful lists. # This is not the same as the English name in the ISO 3166 tables. @@ -189,7 +189,7 @@ MF St Martin (French) MG Madagascar MH Marshall Islands -MK Macedonia +MK North Macedonia ML Mali MM Myanmar (Burma) MN Mongolia @@ -258,7 +258,7 @@ SV El Salvador SX St Maarten (Dutch) SY Syria -SZ Swaziland +SZ Eswatini (Swaziland) TC Turks & Caicos Is TD Chad TF French Southern & Antarctic Lands
diff --git a/make/data/tzdata/leapseconds b/make/data/tzdata/leapseconds index 8b539e6..6f19416 100644 --- a/make/data/tzdata/leapseconds +++ b/make/data/tzdata/leapseconds
@@ -26,33 +26,43 @@ # This file is in the public domain. # This file is generated automatically from the data in the public-domain -# leap-seconds.list file, which can be copied from +# NIST format leap-seconds.list file, which can be copied from # <ftp://ftp.nist.gov/pub/time/leap-seconds.list> -# or <ftp://ftp.boulder.nist.gov/pub/time/leap-seconds.list> -# or <ftp://tycho.usno.navy.mil/pub/ntp/leap-seconds.list>. +# or <ftp://ftp.boulder.nist.gov/pub/time/leap-seconds.list>. +# The NIST file is used instead of its IERS upstream counterpart +# <https://hpiers.obspm.fr/iers/bul/bulc/ntp/leap-seconds.list> +# because under US law the NIST file is public domain +# whereas the IERS file's copyright and license status is unclear. # For more about leap-seconds.list, please see # The NTP Timescale and Leap Seconds # <https://www.eecis.udel.edu/~mills/leap.html>. -# The International Earth Rotation and Reference Systems Service +# The rules for leap seconds are specified in Annex 1 (Time scales) of: +# Standard-frequency and time-signal emissions. +# International Telecommunication Union - Radiocommunication Sector +# (ITU-R) Recommendation TF.460-6 (02/2002) +# <https://www.itu.int/rec/R-REC-TF.460-6-200202-I/>. +# The International Earth Rotation and Reference Systems Service (IERS) # periodically uses leap seconds to keep UTC to within 0.9 s of UT1 -# (which measures the true angular orientation of the earth in space) +# (a proxy for Earth's angle in space as measured by astronomers) # and publishes leap second data in a copyrighted file # <https://hpiers.obspm.fr/iers/bul/bulc/Leap_Second.dat>. # See: Levine J. Coordinated Universal Time and the leap second. # URSI Radio Sci Bull. 2016;89(4):30-6. doi:10.23919/URSIRSB.2016.7909995 # <https://ieeexplore.ieee.org/document/7909995>. -# There were no leap seconds before 1972, because the official mechanism -# accounting for the discrepancy between atomic time and the earth's rotation -# did not exist. -# The correction (+ or -) is made at the given time, so lines -# will typically look like: -# Leap YEAR MON DAY 23:59:60 + R/S -# or -# Leap YEAR MON DAY 23:59:59 - R/S +# There were no leap seconds before 1972, as no official mechanism +# accounted for the discrepancy between atomic time (TAI) and the earth's +# rotation. The first ("1 Jan 1972") data line in leap-seconds.list +# does not denote a leap second; it denotes the start of the current definition +# of UTC. -# If the leap second is Rolling (R) the given time is local time (unused here). +# All leap-seconds are Stationary (S) at the given UTC time. +# The correction (+ or -) is made at the given time, so in the unlikely +# event of a negative leap second, a line would look like this: +# Leap YEAR MON DAY 23:59:59 - S +# Typical lines look like this: +# Leap YEAR MON DAY 23:59:60 + S Leap 1972 Jun 30 23:59:60 + S Leap 1972 Dec 31 23:59:60 + S Leap 1973 Dec 31 23:59:60 + S @@ -81,9 +91,15 @@ Leap 2015 Jun 30 23:59:60 + S Leap 2016 Dec 31 23:59:60 + S -# POSIX timestamps for the data in this file: -#updated 1467936000 -#expires 1561680000 +# UTC timestamp when this leap second list expires. +# Any additional leap seconds will come after this. +# This Expires line is commented out for now, +# so that pre-2020a zic implementations do not reject this file. +#Expires 2021 Dec 28 00:00:00 -# Updated through IERS Bulletin C56 -# File expires on: 28 June 2019 +# POSIX timestamps for the data in this file: +#updated 1467936000 (2016-07-08 00:00:00 UTC) +#expires 1640649600 (2021-12-28 00:00:00 UTC) + +# Updated through IERS Bulletin C61 +# File expires on: 28 December 2021
diff --git a/make/data/tzdata/northamerica b/make/data/tzdata/northamerica index 297a10a..610c606 100644 --- a/make/data/tzdata/northamerica +++ b/make/data/tzdata/northamerica
@@ -109,17 +109,40 @@ # For more about the first ten years of DST in the United States, see # Robert Garland, Ten years of daylight saving from the Pittsburgh standpoint # (Carnegie Library of Pittsburgh, 1927). -# http://www.clpgh.org/exhibit/dst.html +# https://web.archive.org/web/20160517155308/http://www.clpgh.org/exhibit/dst.html # # Shanks says that DST was called "War Time" in the US in 1918 and 1919. # However, DST was imposed by the Standard Time Act of 1918, which # was the first nationwide legal time standard, and apparently # time was just called "Standard Time" or "Daylight Saving Time". -# From Arthur David Olson: -# US Daylight Saving Time ended on the last Sunday of *October* in 1974. -# See, for example, the front page of the Saturday, 1974-10-26 -# and Sunday, 1974-10-27 editions of the Washington Post. +# From Paul Eggert (2019-06-04): +# Here is the legal basis for the US federal rules. +# * Public Law 65-106 (1918-03-19) implemented standard and daylight saving +# time for the first time across the US, springing forward on March's last +# Sunday and falling back on October's last Sunday. +# https://www.loc.gov/law/help/statutes-at-large/65th-congress/session-2/c65s2ch24.pdf +# * Public Law 66-40 (1919-08-20) repealed DST on October 1919's last Sunday. +# https://www.loc.gov/law/help/statutes-at-large/66th-congress/session-1/c66s1ch51.pdf +# * Public Law 77-403 (1942-01-20) started wartime DST on 1942-02-09. +# https://www.loc.gov/law/help/statutes-at-large/77th-congress/session-2/c77s2ch7.pdf +# * Public Law 79-187 (1945-09-25) ended wartime DST on 1945-09-30. +# https://www.loc.gov/law/help/statutes-at-large/79th-congress/session-1/c79s1ch388.pdf +# * Public Law 89-387 (1966-04-13) reinstituted a national standard for DST, +# from April's last Sunday to October's last Sunday, effective 1967. +# https://www.govinfo.gov/content/pkg/STATUTE-80/pdf/STATUTE-80-Pg107.pdf +# * Public Law 93-182 (1973-12-15) moved the 1974 spring-forward to 01-06. +# https://www.govinfo.gov/content/pkg/STATUTE-87/pdf/STATUTE-87-Pg707.pdf +# * Public Law 93-434 (1974-10-05) moved the 1975 spring-forward to +# February's last Sunday. +# https://www.govinfo.gov/content/pkg/STATUTE-88/pdf/STATUTE-88-Pg1209.pdf +# * Public Law 99-359 (1986-07-08) moved the spring-forward to April's first +# Sunday. +# https://www.govinfo.gov/content/pkg/STATUTE-100/pdf/STATUTE-100-Pg764.pdf +# * Public Law 109-58 (2005-08-08), effective 2007, moved the spring-forward +# to March's second Sunday and the fall-back to November's first Sunday. +# https://www.govinfo.gov/content/pkg/PLAW-109publ58/pdf/PLAW-109publ58.pdf +# All transitions are at 02:00 local time. # From Arthur David Olson: # Before the Uniform Time Act of 1966 took effect in 1967, observance of @@ -170,16 +193,16 @@ # U.S. government action. So even though the "US" rules have changed # in the latest release, other countries won't be affected. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule US 1918 1919 - Mar lastSun 2:00 1:00 D Rule US 1918 1919 - Oct lastSun 2:00 0 S Rule US 1942 only - Feb 9 2:00 1:00 W # War Rule US 1945 only - Aug 14 23:00u 1:00 P # Peace -Rule US 1945 only - Sep lastSun 2:00 0 S +Rule US 1945 only - Sep 30 2:00 0 S Rule US 1967 2006 - Oct lastSun 2:00 0 S Rule US 1967 1973 - Apr lastSun 2:00 1:00 D Rule US 1974 only - Jan 6 2:00 1:00 D -Rule US 1975 only - Feb 23 2:00 1:00 D +Rule US 1975 only - Feb lastSun 2:00 1:00 D Rule US 1976 1986 - Apr lastSun 2:00 1:00 D Rule US 1987 2006 - Apr Sun>=1 2:00 1:00 D Rule US 2007 max - Mar Sun>=8 2:00 1:00 D @@ -196,7 +219,7 @@ # increase the chances that they'll actually get compiled and to # avoid the need to duplicate the US rules in another file. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone EST -5:00 - EST Zone MST -7:00 - MST Zone HST -10:00 - HST @@ -347,13 +370,13 @@ # Eastern time (i.e., -4:56:01.6) just before the 1883 switch. Round to the # nearest second. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule NYC 1920 only - Mar lastSun 2:00 1:00 D Rule NYC 1920 only - Oct lastSun 2:00 0 S Rule NYC 1921 1966 - Apr lastSun 2:00 1:00 D Rule NYC 1921 1954 - Sep lastSun 2:00 0 S Rule NYC 1955 1966 - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/New_York -4:56:02 - LMT 1883 Nov 18 12:03:58 -5:00 US E%sT 1920 -5:00 NYC E%sT 1942 @@ -406,14 +429,39 @@ # From Paul Eggert (2015-12-25): # Assume this practice predates 1970, so Fort Pierre can use America/Chicago. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER +# From Paul Eggert (2015-04-06): +# In 1950s Nashville a public clock had dueling faces, one for conservatives +# and the other for liberals; the two sides didn't agree about the time of day. +# I haven't found a photo of this clock, nor have I tracked down the TIME +# magazine report cited below, but here's the story as told by the late +# American journalist John Seigenthaler, who was there: +# +# "The two [newspaper] owners held strongly contrasting political and +# ideological views. Evans was a New South liberal, Stahlman an Old South +# conservative, and their two papers frequently clashed editorially, often on +# the same day.... In the 1950s as the state legislature was grappling with +# the question of whether to approve daylight saving time for the entire state, +# TIME magazine reported: +# +# "'The Nashville Banner and The Nashville Tennessean rarely agree on anything +# but the time of day - and last week they couldn't agree on that.' +# +# "It was all too true. The clock on the front of the building had two faces - +# The Tennessean side of the building facing west, the other, east. When it +# was high noon Banner time, it was 11 a.m. Tennessean time." +# +# Seigenthaler J. For 100 years, Tennessean had it covered. +# The Tennessean 2007-05-11, republished 2015-04-06. +# https://www.tennessean.com/story/insider/extras/2015/04/06/archives-seigenthaler-for-100-years-the-tennessean-had-it-covered/25348545/ + +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule Chicago 1920 only - Jun 13 2:00 1:00 D Rule Chicago 1920 1921 - Oct lastSun 2:00 0 S Rule Chicago 1921 only - Mar lastSun 2:00 1:00 D Rule Chicago 1922 1966 - Apr lastSun 2:00 1:00 D Rule Chicago 1922 1954 - Sep lastSun 2:00 0 S Rule Chicago 1955 1966 - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Chicago -5:50:36 - LMT 1883 Nov 18 12:09:24 -6:00 US C%sT 1920 -6:00 Chicago C%sT 1936 Mar 1 2:00 @@ -475,13 +523,13 @@ # El Paso Times. 2018-10-24 06:40 -06. # https://www.elpasotimes.com/story/news/local/el-paso/2018/10/24/el-pasoans-were-time-rebels-fought-stay-mountain-zone/1744509002/ # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule Denver 1920 1921 - Mar lastSun 2:00 1:00 D Rule Denver 1920 only - Oct lastSun 2:00 0 S Rule Denver 1921 only - May 22 2:00 0 S Rule Denver 1965 1966 - Apr lastSun 2:00 1:00 D Rule Denver 1965 1966 - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Denver -6:59:56 - LMT 1883 Nov 18 12:00:04 -7:00 US M%sT 1920 -7:00 Denver M%sT 1942 @@ -528,13 +576,13 @@ # https://repository.uchastings.edu/cgi/viewcontent.cgi?article=1501&context=ca_ballot_props # https://repository.uchastings.edu/cgi/viewcontent.cgi?article=1636&context=ca_ballot_props # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule CA 1948 only - Mar 14 2:01 1:00 D Rule CA 1949 only - Jan 1 2:00 0 S Rule CA 1950 1966 - Apr lastSun 1:00 1:00 D Rule CA 1950 1961 - Sep lastSun 2:00 0 S Rule CA 1962 1966 - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Los_Angeles -7:52:58 - LMT 1883 Nov 18 12:07:02 -8:00 US P%sT 1946 -8:00 CA P%sT 1967 @@ -622,7 +670,27 @@ # between AKST and AKDT from now on.... # https://www.krbd.org/2015/10/30/annette-island-times-they-are-a-changing/ -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# From Ryan Stanley (2018-11-06): +# The Metlakatla community in Alaska has decided not to change its +# clock back an hour starting on November 4th, 2018 (day before yesterday). +# They will be gmtoff=-28800 year-round. +# https://www.facebook.com/141055983004923/photos/pb.141055983004923.-2207520000.1541465673./569081370202380/ + +# From Paul Eggert (2018-12-16): +# In a 2018-12-11 special election, Metlakatla voted to go back to +# Alaska time (including daylight saving time) starting next year. +# https://www.krbd.org/2018/12/12/metlakatla-to-follow-alaska-standard-time-allow-liquor-sales/ +# +# From Ryan Stanley (2019-01-11): +# The community will be changing back on the 20th of this month... +# From Tim Parenti (2019-01-11): +# Per an announcement on the Metlakatla community's official Facebook page, the +# "fall back" will be on Sunday 2019-01-20 at 02:00: +# https://www.facebook.com/141055983004923/photos/607150969728753/ +# So they won't be waiting for Alaska to join them on 2019-03-10, but will +# rather change their clocks twice in seven weeks. + +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Juneau 15:02:19 - LMT 1867 Oct 19 15:33:32 -8:57:41 - LMT 1900 Aug 20 12:00 -8:00 - PST 1942 @@ -648,6 +716,8 @@ -8:00 - PST 1969 -8:00 US P%sT 1983 Oct 30 2:00 -8:00 - PST 2015 Nov 1 2:00 + -9:00 US AK%sT 2018 Nov 4 2:00 + -8:00 - PST 2019 Jan 20 2:00 -9:00 US AK%sT Zone America/Yakutat 14:41:05 - LMT 1867 Oct 19 15:12:18 -9:18:55 - LMT 1900 Aug 20 12:00 @@ -740,7 +810,7 @@ # Note that 1933-05-21 was a Sunday. # We're left to guess the time of day when Act 163 was approved; guess noon. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Pacific/Honolulu -10:31:26 - LMT 1896 Jan 13 12:00 -10:30 - HST 1933 Apr 30 2:00 -10:30 1:00 HDT 1933 May 21 12:00 @@ -770,7 +840,7 @@ # Shanks says the 1944 experiment came to an end on 1944-03-17. # Go with the Arizona State Library instead. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Phoenix -7:28:18 - LMT 1883 Nov 18 11:31:42 -7:00 US M%sT 1944 Jan 1 0:01 -7:00 - MST 1944 Apr 1 0:01 @@ -796,7 +866,7 @@ # quarter of Idaho county) and eastern Oregon (most of Malheur County) # switched four weeks late in 1974. # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Boise -7:44:49 - LMT 1883 Nov 18 12:15:11 -8:00 US P%sT 1923 May 13 2:00 -7:00 US M%sT 1974 @@ -808,6 +878,22 @@ # For a map of Indiana's time zone regions, see: # https://en.wikipedia.org/wiki/Time_in_Indiana # +# From Paul Eggert (2018-11-30): +# A brief but entertaining history of time in Indiana describes a 1949 debate +# in the Indiana House where city legislators (who favored "fast time") +# tussled with farm legislators (who didn't) over a bill to outlaw DST: +# "Lacking enough votes, the city faction tries to filibuster until time runs +# out on the session at midnight, but rural champion Rep. Herbert Copeland, +# R-Madison, leans over the gallery railing and forces the official clock +# back to 9 p.m., breaking it in the process. The clock sticks on 9 as the +# debate rages on into the night. The filibuster finally dies out and the +# bill passes, while outside the chamber, clocks read 3:30 a.m. In the end, +# it doesn't matter which side won. The law has no enforcement powers and +# is simply ignored by fast-time communities." +# How Indiana went from 'God's time' to split zones and daylight-saving. +# Indianapolis Star. 2018-11-27 14:58 -05. +# https://www.indystar.com/story/news/politics/2018/11/27/indianapolis-indiana-time-zone-history-central-eastern-daylight-savings-time/2126300002/ +# # From Paul Eggert (2007-08-17): # Since 1970, most of Indiana has been like America/Indiana/Indianapolis, # with the following exceptions: @@ -848,11 +934,11 @@ # going to switch from Central to Eastern Time on March 11, 2007.... # http://www.indystar.com/apps/pbcs.dll/article?AID=/20070207/LOCAL190108/702070524/0/LOCAL -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule Indianapolis 1941 only - Jun 22 2:00 1:00 D Rule Indianapolis 1941 1954 - Sep lastSun 2:00 0 S Rule Indianapolis 1946 1954 - Apr lastSun 2:00 1:00 D -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Indiana/Indianapolis -5:44:38 - LMT 1883 Nov 18 12:15:22 -6:00 US C%sT 1920 -6:00 Indianapolis C%sT 1942 @@ -867,12 +953,12 @@ # # Eastern Crawford County, Indiana, left its clocks alone in 1974, # as well as from 1976 through 2005. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule Marengo 1951 only - Apr lastSun 2:00 1:00 D Rule Marengo 1951 only - Sep lastSun 2:00 0 S Rule Marengo 1954 1960 - Apr lastSun 2:00 1:00 D Rule Marengo 1954 1960 - Sep lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Indiana/Marengo -5:45:23 - LMT 1883 Nov 18 12:14:37 -6:00 US C%sT 1951 -6:00 Marengo C%sT 1961 Apr 30 2:00 @@ -886,7 +972,7 @@ # Daviess, Dubois, Knox, and Martin Counties, Indiana, # switched from eastern to central time in April 2006, then switched back # in November 2007. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule Vincennes 1946 only - Apr lastSun 2:00 1:00 D Rule Vincennes 1946 only - Sep lastSun 2:00 0 S Rule Vincennes 1953 1954 - Apr lastSun 2:00 1:00 D @@ -896,7 +982,7 @@ Rule Vincennes 1960 only - Oct lastSun 2:00 0 S Rule Vincennes 1961 only - Sep lastSun 2:00 0 S Rule Vincennes 1962 1963 - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Indiana/Vincennes -5:50:07 - LMT 1883 Nov 18 12:09:53 -6:00 US C%sT 1946 -6:00 Vincennes C%sT 1964 Apr 26 2:00 @@ -907,33 +993,33 @@ -5:00 US E%sT # # Perry County, Indiana, switched from eastern to central time in April 2006. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER -Rule Perry 1946 only - Apr lastSun 2:00 1:00 D -Rule Perry 1946 only - Sep lastSun 2:00 0 S -Rule Perry 1953 1954 - Apr lastSun 2:00 1:00 D -Rule Perry 1953 1959 - Sep lastSun 2:00 0 S +# From Alois Triendl (2019-07-09): +# The Indianapolis News, Friday 27 October 1967 states that Perry County +# returned to CST. It went again to EST on 27 April 1969, as documented by the +# Indianapolis star of Saturday 26 April. +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule Perry 1955 only - May 1 0:00 1:00 D +Rule Perry 1955 1960 - Sep lastSun 2:00 0 S Rule Perry 1956 1963 - Apr lastSun 2:00 1:00 D -Rule Perry 1960 only - Oct lastSun 2:00 0 S -Rule Perry 1961 only - Sep lastSun 2:00 0 S -Rule Perry 1962 1963 - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +Rule Perry 1961 1963 - Oct lastSun 2:00 0 S +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Indiana/Tell_City -5:47:03 - LMT 1883 Nov 18 12:12:57 -6:00 US C%sT 1946 -6:00 Perry C%sT 1964 Apr 26 2:00 - -5:00 - EST 1969 + -5:00 - EST 1967 Oct 29 2:00 + -6:00 US C%sT 1969 Apr 27 2:00 -5:00 US E%sT 1971 -5:00 - EST 2006 Apr 2 2:00 -6:00 US C%sT # # Pike County, Indiana moved from central to eastern time in 1977, # then switched back in 2006, then switched back again in 2007. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule Pike 1955 only - May 1 0:00 1:00 D Rule Pike 1955 1960 - Sep lastSun 2:00 0 S Rule Pike 1956 1964 - Apr lastSun 2:00 1:00 D Rule Pike 1961 1964 - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Indiana/Petersburg -5:49:07 - LMT 1883 Nov 18 12:10:53 -6:00 US C%sT 1955 -6:00 Pike C%sT 1965 Apr 25 2:00 @@ -949,13 +1035,13 @@ # An article on page A3 of the Sunday, 1991-10-27 Washington Post # notes that Starke County switched from Central time to Eastern time as of # 1991-10-27. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule Starke 1947 1961 - Apr lastSun 2:00 1:00 D Rule Starke 1947 1954 - Sep lastSun 2:00 0 S Rule Starke 1955 1956 - Oct lastSun 2:00 0 S Rule Starke 1957 1958 - Sep lastSun 2:00 0 S Rule Starke 1959 1961 - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Indiana/Knox -5:46:30 - LMT 1883 Nov 18 12:13:30 -6:00 US C%sT 1947 -6:00 Starke C%sT 1962 Apr 29 2:00 @@ -966,12 +1052,12 @@ # # Pulaski County, Indiana, switched from eastern to central time in # April 2006 and then switched back in March 2007. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule Pulaski 1946 1960 - Apr lastSun 2:00 1:00 D Rule Pulaski 1946 1954 - Sep lastSun 2:00 0 S Rule Pulaski 1955 1956 - Oct lastSun 2:00 0 S Rule Pulaski 1957 1960 - Sep lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Indiana/Winamac -5:46:25 - LMT 1883 Nov 18 12:13:35 -6:00 US C%sT 1946 -6:00 Pulaski C%sT 1961 Apr 30 2:00 @@ -982,7 +1068,7 @@ -5:00 US E%sT # # Switzerland County, Indiana, did not observe DST from 1973 through 2005. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Indiana/Vevay -5:40:16 - LMT 1883 Nov 18 12:19:44 -6:00 US C%sT 1954 Apr 25 2:00 -5:00 - EST 1969 @@ -997,17 +1083,28 @@ # clear how this matched civil time in Louisville, so for now continue # to assume Louisville switched at noon new local time, like New York. # +# From Michael Deckers (2019-08-06): +# From the contemporary source given by Alois Treindl, +# the switch in Louisville on 1946-04-28 was on 00:01 +# From Paul Eggert (2019-08-26): +# That source was the Louisville Courier-Journal, 1946-04-27, p 4. +# Shanks gives 02:00 for all 20th-century transition times in Louisville. +# Evidently this is wrong for spring 1946. Although also likely wrong +# for other dates, we have no data. +# # Part of Kentucky left its clocks alone in 1974. # This also includes Clark, Floyd, and Harrison counties in Indiana. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule Louisville 1921 only - May 1 2:00 1:00 D Rule Louisville 1921 only - Sep 1 2:00 0 S -Rule Louisville 1941 1961 - Apr lastSun 2:00 1:00 D +Rule Louisville 1941 only - Apr lastSun 2:00 1:00 D Rule Louisville 1941 only - Sep lastSun 2:00 0 S +Rule Louisville 1946 only - Apr lastSun 0:01 1:00 D Rule Louisville 1946 only - Jun 2 2:00 0 S +Rule Louisville 1950 1961 - Apr lastSun 2:00 1:00 D Rule Louisville 1950 1955 - Sep lastSun 2:00 0 S -Rule Louisville 1956 1960 - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +Rule Louisville 1956 1961 - Oct lastSun 2:00 0 S +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Kentucky/Louisville -5:43:02 - LMT 1883 Nov 18 12:16:58 -6:00 US C%sT 1921 -6:00 Louisville C%sT 1942 @@ -1096,41 +1193,44 @@ # one hour in 1914." This change is not in Shanks. We have no more # info, so omit this for now. # -# From Paul Eggert (2017-07-26): -# Although Shanks says Detroit observed DST in 1967 from 06-14 00:01 -# until 10-29 00:01, I now see multiple reports that this is incorrect. -# For example, according to a 50-year anniversary report about the 1967 -# Detroit riots and a major-league doubleheader on 1967-07-23, "By the time -# the last fly ball of the doubleheader settled into the glove of leftfielder -# Lenny Green, it was after 7 p.m. Detroit did not observe daylight saving -# time, so light was already starting to fail. Twilight was made even deeper -# by billowing columns of smoke that ascended in an unbroken wall north of the -# ballpark." See: Dow B. Detroit '67: As violence unfolded, Tigers played two -# at home vs. Yankees. Detroit Free Press 2017-07-23. -# https://www.freep.com/story/sports/mlb/tigers/2017/07/23/detroit-tigers-1967-riot-new-york-yankees/499951001/ +# From Paul Eggert (2019-07-06): +# Due to a complicated set of legal maneuvers, in 1967 Michigan did +# not start daylight saving time when the rest of the US did. +# Instead, it began DST on Jun 14 at 00:01. This was big news: +# the Detroit Free Press reported it at the top of Page 1 on +# 1967-06-14, in an article "State Adjusting to Switch to Fast Time" +# by Gary Blonston, above an article about Thurgood Marshall's +# confirmation to the US Supreme Court. Although Shanks says Detroit +# observed DST until 1967-10-29 00:01, that time of day seems to be +# incorrect, as the Free Press later said DST ended in Michigan at the +# same time as the rest of the US. Also, although Shanks reports no DST in +# Detroit in 1968, it did observe DST that year; in the November 1968 +# election Michigan voters narrowly repealed DST, effective 1969. # # Most of Michigan observed DST from 1973 on, but was a bit late in 1975. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule Detroit 1948 only - Apr lastSun 2:00 1:00 D Rule Detroit 1948 only - Sep lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Detroit -5:32:11 - LMT 1905 -6:00 - CST 1915 May 15 2:00 -5:00 - EST 1942 -5:00 US E%sT 1946 - -5:00 Detroit E%sT 1973 + -5:00 Detroit E%sT 1967 Jun 14 0:01 + -5:00 US E%sT 1969 + -5:00 - EST 1973 -5:00 US E%sT 1975 -5:00 - EST 1975 Apr 27 2:00 -5:00 US E%sT # # Dickinson, Gogebic, Iron, and Menominee Counties, Michigan, # switched from EST to CST/CDT in 1973. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER +# Rule NAME FROM TO - IN ON AT SAVE LETTER Rule Menominee 1946 only - Apr lastSun 2:00 1:00 D Rule Menominee 1946 only - Sep lastSun 2:00 0 S Rule Menominee 1966 only - Apr lastSun 2:00 1:00 D Rule Menominee 1966 only - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Menominee -5:50:27 - LMT 1885 Sep 18 12:00 -6:00 US C%sT 1946 -6:00 Menominee C%sT 1969 Apr 27 2:00 @@ -1167,6 +1267,12 @@ # # Other sources occasionally used include: # +# Milne J. Civil time. Geogr J. 1899 Feb;13(2):173-94 +# <https://www.jstor.org/stable/1774359>. +# +# Pearce C. The Great Daylight Saving Time Controversy. +# Australian Ebook Publisher. 2017. ISBN 978-1-925516-96-8. +# # Edward W. Whitman, World Time Differences, # Whitman Publishing Co, 2 Niagara Av, Ealing, London (undated), # which I found in the UCLA library. @@ -1175,9 +1281,6 @@ # <http://cs.ucla.edu/~eggert/The-Waste-of-Daylight-19th.pdf> # [PDF] (1914-03) # -# Milne J. Civil time. Geogr J. 1899 Feb;13(2):173-94 -# <https://www.jstor.org/stable/1774359>. -# # See the 'europe' file for Greenland. # Canada @@ -1292,7 +1395,7 @@ # Oct 31, to Oct 27, 1918 (and Sunday is a more likely transition day # than Thursday) in all Canadian rulesets. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Canada 1918 only - Apr 14 2:00 1:00 D Rule Canada 1918 only - Oct 27 2:00 0 S Rule Canada 1942 only - Feb 9 2:00 1:00 W # War @@ -1315,7 +1418,7 @@ # that follows the rules is the southeast corner, including Port Hope # Simpson and Mary's Harbour, but excluding, say, Black Tickle. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule StJohns 1917 only - Apr 8 2:00 1:00 D Rule StJohns 1917 only - Sep 17 2:00 0 S # Whitman gives 1919 Apr 5 and 1920 Apr 5; go with Shanks & Pottenger. @@ -1364,7 +1467,7 @@ Rule StJohns 2007 2010 - Nov Sun>=1 0:01 0 S # # St John's has an apostrophe, but Posix file names can't have apostrophes. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/St_Johns -3:30:52 - LMT 1884 -3:30:52 StJohns N%sT 1918 -3:30:52 Canada N%sT 1919 @@ -1377,7 +1480,7 @@ # most of east Labrador # The name 'Happy Valley-Goose Bay' is too long; use 'Goose Bay'. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Goose_Bay -4:01:40 - LMT 1884 # Happy Valley-Goose Bay -3:30:52 - NST 1918 -3:30:52 Canada N%sT 1919 @@ -1390,7 +1493,8 @@ -4:00 Canada A%sT -# west Labrador, Nova Scotia, Prince Edward I +# west Labrador, Nova Scotia, Prince Edward I, +# Îles-de-la-Madeleine, Listuguj reserve # From Brian Inglis (2015-07-20): # From the historical weather station records available at: @@ -1409,7 +1513,14 @@ # in Canada to observe DST in 1971 but not 1970; for now we'll assume # this is a typo. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# From Jeffery Nichols (2020-01-09): +# America/Halifax ... also applies to Îles-de-la-Madeleine and the Listuguj +# reserve in Quebec. Officially, this came into effect on January 1, 2007 +# (Legal Time Act, CQLR c T-5.1), but the legislative debates surrounding that +# bill say that it is "accommodating the customs and practices" of those +# regions, which suggests that they have always been in-line with Halifax. + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Halifax 1916 only - Apr 1 0:00 1:00 D Rule Halifax 1916 only - Oct 1 0:00 0 S Rule Halifax 1920 only - May 9 0:00 1:00 D @@ -1451,7 +1562,7 @@ Rule Halifax 1956 1959 - Sep lastSun 2:00 0 S Rule Halifax 1962 1973 - Apr lastSun 2:00 1:00 D Rule Halifax 1962 1973 - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Halifax -4:14:24 - LMT 1902 Jun 15 -4:00 Halifax A%sT 1918 -4:00 Canada A%sT 1919 @@ -1475,7 +1586,7 @@ # clear that this was the case since at least 1993. # For now, assume it started in 1993. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Moncton 1933 1935 - Jun Sun>=8 1:00 1:00 D Rule Moncton 1933 1935 - Sep Sun>=8 1:00 0 S Rule Moncton 1936 1938 - Jun Sun>=1 1:00 1:00 D @@ -1489,7 +1600,7 @@ Rule Moncton 1957 1972 - Oct lastSun 2:00 0 S Rule Moncton 1993 2006 - Apr Sun>=1 0:01 1:00 D Rule Moncton 1993 2006 - Oct lastSun 0:01 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Moncton -4:19:08 - LMT 1883 Dec 9 -5:00 - EST 1902 Jun 15 -4:00 Canada A%sT 1933 @@ -1502,23 +1613,24 @@ # Quebec -# From Paul Eggert (2015-03-24): +# From Paul Eggert (2020-01-10): # See America/Toronto for most of Quebec, including Montreal. +# See America/Halifax for the Îles de la Madeleine and the Listuguj reserve. # # Matthews and Vincent (1998) also write that Quebec east of the -63 # meridian is supposed to observe AST, but residents as far east as # Natashquan use EST/EDT, and residents east of Natashquan use AST. # The Quebec department of justice writes in # "The situation in Minganie and Basse-Côte-Nord" -# http://www.justice.gouv.qc.ca/english/publications/generale/temps-minganie-a.htm +# https://www.justice.gouv.qc.ca/en/department/ministre/functions-and-responsabilities/legal-time-in-quebec/the-situation-in-minganie-and-basse-cote-nord/ # that the coastal strip from just east of Natashquan to Blanc-Sablon # observes Atlantic standard time all year round. -# https://www.assnat.qc.ca/Media/Process.aspx?MediaId=ANQ.Vigie.Bll.DocumentGenerique_8845en -# says this common practice was codified into law as of 2007. +# This common practice was codified into law as of 2007; see Legal Time Act, +# CQLR c T-5.1 <http://legisquebec.gouv.qc.ca/en/ShowDoc/cs/T-5.1>. # For lack of better info, guess this practice began around 1970, contra to # Shanks & Pottenger who have this region observing AST/ADT. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Blanc-Sablon -3:48:28 - LMT 1884 -4:00 Canada A%sT 1970 -4:00 - AST @@ -1533,6 +1645,15 @@ # Nipigon (EST) and Rainy River (CST) are the largest that we know of. # Far west Ontario is like Winnipeg; far east Quebec is like Halifax. +# From Jeffery Nichols (2020-02-06): +# According to the [Shanks] atlas, those western Ontario zones are huge, +# covering most of Ontario northwest of Sault Ste Marie and Timmins. +# The zones seem to include towns bigger than the ones they're named after, +# like Dryden in America/Rainy_River and Wawa (and maybe Attawapiskat) in +# America/Nipigon. I assume it's too much trouble to change the name of the +# zone (like when you found out that America/Glace_Bay includes Sydney, Nova +# Scotia).... + # From Mark Brader (2003-07-26): # [According to the Toronto Star] Orillia, Ontario, adopted DST # effective Saturday, 1912-06-22, 22:00; the article mentions that @@ -1674,7 +1795,7 @@ # With some exceptions, the use of daylight saving may be said to be limited # to those cities and towns lying between Quebec city and Windsor, Ont. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Toronto 1919 only - Mar 30 23:30 1:00 D Rule Toronto 1919 only - Oct 26 0:00 0 S Rule Toronto 1920 only - May 2 2:00 1:00 D @@ -1686,19 +1807,10 @@ # was meant. Rule Toronto 1922 1926 - Sep Sun>=15 2:00 0 S Rule Toronto 1924 1927 - May Sun>=1 2:00 1:00 D -# The 1927-to-1939 rules can be expressed more simply as -# Rule Toronto 1927 1937 - Sep Sun>=25 2:00 0 S -# Rule Toronto 1928 1937 - Apr Sun>=25 2:00 1:00 D -# Rule Toronto 1938 1940 - Apr lastSun 2:00 1:00 D -# Rule Toronto 1938 1939 - Sep lastSun 2:00 0 S -# The rules below avoid use of Sun>=25 -# (which pre-2004 versions of zic cannot handle). -Rule Toronto 1927 1932 - Sep lastSun 2:00 0 S -Rule Toronto 1928 1931 - Apr lastSun 2:00 1:00 D -Rule Toronto 1932 only - May 1 2:00 1:00 D -Rule Toronto 1933 1940 - Apr lastSun 2:00 1:00 D -Rule Toronto 1933 only - Oct 1 2:00 0 S -Rule Toronto 1934 1939 - Sep lastSun 2:00 0 S +Rule Toronto 1927 1937 - Sep Sun>=25 2:00 0 S +Rule Toronto 1928 1937 - Apr Sun>=25 2:00 1:00 D +Rule Toronto 1938 1940 - Apr lastSun 2:00 1:00 D +Rule Toronto 1938 1939 - Sep lastSun 2:00 0 S Rule Toronto 1945 1946 - Sep lastSun 2:00 0 S Rule Toronto 1946 only - Apr lastSun 2:00 1:00 D Rule Toronto 1947 1949 - Apr lastSun 0:00 1:00 D @@ -1731,7 +1843,7 @@ # War,... [t]he cities agreed to implement DST during the summer # months for the remainder of the war years. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Toronto -5:17:32 - LMT 1895 -5:00 Canada E%sT 1919 -5:00 Toronto E%sT 1942 Feb 9 2:00s @@ -1781,7 +1893,7 @@ # starting 1966. Since 02:00s is clearly correct for 1967 on, assume # it was also 02:00s in 1966. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Winn 1916 only - Apr 23 0:00 1:00 D Rule Winn 1916 only - Sep 17 0:00 0 S Rule Winn 1918 only - Apr 14 2:00 1:00 D @@ -1806,7 +1918,7 @@ Rule Winn 1966 1986 - Apr lastSun 2:00s 1:00 D Rule Winn 1966 2005 - Oct lastSun 2:00s 0 S Rule Winn 1987 2005 - Apr Sun>=1 2:00s 1:00 D -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Winnipeg -6:28:36 - LMT 1887 Jul 16 -6:00 Winn C%sT 2006 -6:00 Canada C%sT @@ -1828,6 +1940,12 @@ # Willett (1914-03) notes that DST "has been in operation ... in the # City of Moose Jaw, Saskatchewan, for one year." +# From Paul Eggert (2019-07-25): +# Pearce's book says Regina observed DST in 1914-1917. No dates and times, +# unfortunately. It also says that in 1914 Saskatoon observed DST +# from 1 June to 6 July, and that DST was also tried out in Davidson, +# Melfort, and Prince Albert. + # From Paul Eggert (2006-03-22): # Shanks & Pottenger say that since 1970 this region has mostly been as Regina. # Some western towns (e.g. Swift Current) switched from MST/MDT to CST in 1972. @@ -1866,7 +1984,7 @@ # long and rather painful to read. # http://www.qp.gov.sk.ca/documents/English/Statutes/Statutes/T14.pdf -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Regina 1918 only - Apr 14 2:00 1:00 D Rule Regina 1918 only - Oct 27 2:00 0 S Rule Regina 1930 1934 - May Sun>=1 0:00 1:00 D @@ -1890,7 +2008,7 @@ Rule Swift 1959 1961 - Apr lastSun 2:00 1:00 D Rule Swift 1959 only - Oct lastSun 2:00 0 S Rule Swift 1960 1961 - Sep lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Regina -6:58:36 - LMT 1905 Sep -7:00 Regina M%sT 1960 Apr lastSun 2:00 -6:00 - CST @@ -1903,7 +2021,20 @@ # Alberta -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# From Alois Triendl (2019-07-19): +# There was no DST in Alberta in 1967... Calgary Herald, 29 April 1967. +# 1969, no DST, from Edmonton Journal 18 April 1969 +# +# From Paul Eggert (2019-07-25): +# Pearce's book says that Alberta's 1948 Daylight Saving Act required +# Mountain Standard Time without DST, and that "anyone who broke that law +# could be fined up to $25 and costs". There seems to be no record of +# anybody paying the fine. The law was not changed until an August 1971 +# plebiscite reinstituted DST in 1972. This story is also mentioned in: +# Boyer JP. Forcing Choice: The Risky Reward of Referendums. Dundum. 2017. +# ISBN 978-1459739123. + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Edm 1918 1919 - Apr Sun>=8 2:00 1:00 D Rule Edm 1918 only - Oct 27 2:00 0 S Rule Edm 1919 only - May 27 2:00 0 S @@ -1915,13 +2046,9 @@ Rule Edm 1945 only - Sep lastSun 2:00 0 S Rule Edm 1947 only - Apr lastSun 2:00 1:00 D Rule Edm 1947 only - Sep lastSun 2:00 0 S -Rule Edm 1967 only - Apr lastSun 2:00 1:00 D -Rule Edm 1967 only - Oct lastSun 2:00 0 S -Rule Edm 1969 only - Apr lastSun 2:00 1:00 D -Rule Edm 1969 only - Oct lastSun 2:00 0 S Rule Edm 1972 1986 - Apr lastSun 2:00 1:00 D Rule Edm 1972 2006 - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Edmonton -7:33:52 - LMT 1906 Sep -7:00 Edm M%sT 1987 -7:00 Canada M%sT @@ -2001,20 +2128,32 @@ # been on MST (-0700) like Dawson Creek since it advanced its clocks on # 2015-03-08. # -# From Paul Eggert (2015-09-23): +# From Paul Eggert (2019-07-25): # Shanks says Fort Nelson did not observe DST in 1946, unlike Vancouver. +# Alois Triendl confirmed this on 07-22, citing the 1946-04-27 Vancouver Daily +# Province. He also cited the 1946-09-28 Victoria Daily Times, which said +# that Vancouver, Victoria, etc. "change at midnight Saturday"; for now, +# guess they meant 02:00 Sunday since 02:00 was common practice in Vancouver. +# +# Early Vancouver, Volume Four, by Major J.S. Matthews, V.D., 2011 edition +# says that a 1922 plebiscite adopted DST, but a 1923 plebiscite rejected it. +# http://former.vancouver.ca/ctyclerk/archives/digitized/EarlyVan/SearchEarlyVan/Vol4pdf/MatthewsEarlyVancouverVol4_DaylightSavings.pdf +# A catalog entry for a newspaper clipping seems to indicate that Vancouver +# observed DST in 1941 from 07-07 through 09-27; see +# https://searcharchives.vancouver.ca/daylight-saving-1918-starts-again-july-7-1941-start-d-s-sept-27-end-of-d-s-1941 +# We have no further details, so omit them for now. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Vanc 1918 only - Apr 14 2:00 1:00 D Rule Vanc 1918 only - Oct 27 2:00 0 S Rule Vanc 1942 only - Feb 9 2:00 1:00 W # War Rule Vanc 1945 only - Aug 14 23:00u 1:00 P # Peace Rule Vanc 1945 only - Sep 30 2:00 0 S Rule Vanc 1946 1986 - Apr lastSun 2:00 1:00 D -Rule Vanc 1946 only - Oct 13 2:00 0 S +Rule Vanc 1946 only - Sep 29 2:00 0 S Rule Vanc 1947 1961 - Sep lastSun 2:00 0 S Rule Vanc 1962 2006 - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Vancouver -8:12:28 - LMT 1884 -8:00 Vanc P%sT 1987 -8:00 Canada P%sT @@ -2085,7 +2224,7 @@ # varying the manner of reckoning standard time. # # * Yukon Territory Commissioner's Order 1966-20 Interpretation Ordinance -# http://? - no online source found +# [no online source found] # # * Standard Time and Time Zones in Canada; Thomson, Malcolm M.; JRASC, # Vol. 64, pp.129-162; June 1970; SAO/NASA Astrophysics Data System (ADS) @@ -2118,7 +2257,7 @@ # to say eight hours behind Greenwich Time. # # * O.I.C. 1980/02 INTERPRETATION ACT -# http://? - no online source found +# https://mm.icann.org/pipermail/tz/attachments/20201125/d5adc93b/CAYTOIC1980-02DST1980-01-04-0001.pdf # # * Yukon Daylight Saving Time, YOIC 1987/56 # https://www.canlii.org/en/yk/laws/regu/yoic-1987-56/latest/yoic-1987-56.html @@ -2321,7 +2460,31 @@ # obtained in November 2008 should be ignored... # I apologize for reporting incorrect information in 2008. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# From Tim Parenti (2020-03-05): +# The government of Yukon announced [yesterday] the cessation of seasonal time +# changes. "After clocks are pushed ahead one hour on March 8, the territory +# will remain on [UTC-07]. ... [The government] found 93 per cent of +# respondents wanted to end seasonal time changes and, of that group, 70 per +# cent wanted 'permanent Pacific Daylight Saving Time.'" +# https://www.cbc.ca/news/canada/north/yukon-end-daylight-saving-time-1.5486358 +# +# Although the government press release prefers PDT, we prefer MST for +# consistency with nearby Dawson Creek, Creston, and Fort Nelson. +# https://yukon.ca/en/news/yukon-end-seasonal-time-change + +# From Andrew G. Smith (2020-09-24): +# Yukon has completed its regulatory change to be on UTC -7 year-round.... +# http://www.gov.yk.ca/legislation/regs/oic2020_125.pdf +# What we have done is re-defined Yukon Standard Time, as we are +# authorized to do under section 33 of our Interpretation Act: +# http://www.gov.yk.ca/legislation/acts/interpretation_c.pdf +# +# From Paul Eggert (2020-09-24): +# tzdb uses the obsolete YST abbreviation for standard time in Yukon through +# about 1970, and uses PST for standard time in Yukon since then. Consistent +# with that, use MST for -07, the new standard time in Yukon effective Nov. 1. + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule NT_YK 1918 only - Apr 14 2:00 1:00 D Rule NT_YK 1918 only - Oct 27 2:00 0 S Rule NT_YK 1919 only - May 25 2:00 1:00 D @@ -2334,7 +2497,7 @@ Rule NT_YK 1980 1986 - Apr lastSun 2:00 1:00 D Rule NT_YK 1980 2006 - Oct lastSun 2:00 0 S Rule NT_YK 1987 2006 - Apr Sun>=1 2:00 1:00 D -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] # aka Panniqtuuq Zone America/Pangnirtung 0 - -00 1921 # trading post est. -4:00 NT_YK A%sT 1995 Apr Sun>=1 2:00 @@ -2375,11 +2538,13 @@ Zone America/Whitehorse -9:00:12 - LMT 1900 Aug 20 -9:00 NT_YK Y%sT 1967 May 28 0:00 -8:00 NT_YK P%sT 1980 - -8:00 Canada P%sT + -8:00 Canada P%sT 2020 Nov 1 + -7:00 - MST Zone America/Dawson -9:17:40 - LMT 1900 Aug 20 -9:00 NT_YK Y%sT 1973 Oct 28 0:00 -8:00 NT_YK P%sT 1980 - -8:00 Canada P%sT + -8:00 Canada P%sT 2020 Nov 1 + -7:00 - MST ############################################################################### @@ -2481,7 +2646,7 @@ # From Paul Eggert (2001-03-03): # -# http://www.latimes.com/news/nation/20010303/t000018766.html +# https://www.latimes.com/archives/la-xpm-2001-mar-03-mn-32561-story.html # James F. Smith writes in today's LA Times # * Sonora will continue to observe standard time. # * Last week Mexico City's mayor Andrés Manuel López Obrador decreed that @@ -2593,7 +2758,7 @@ # 5- The islands, reefs and keys shall take their timezone from the # longitude they are located at. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Mexico 1939 only - Feb 5 0:00 1:00 D Rule Mexico 1939 only - Jun 25 0:00 0 S Rule Mexico 1940 only - Dec 9 0:00 1:00 D @@ -2608,7 +2773,7 @@ Rule Mexico 2001 only - Sep lastSun 2:00 0 S Rule Mexico 2002 max - Apr Sun>=1 2:00 1:00 D Rule Mexico 2002 max - Oct lastSun 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] # Quintana Roo; represented by Cancún Zone America/Cancun -5:47:04 - LMT 1922 Jan 1 0:12:56 -6:00 - CST 1981 Dec 23 @@ -2793,15 +2958,41 @@ # # For 1899 Milne gives -5:09:29.5; round that. # +# From P Chan (2020-11-27, corrected on 2020-12-02): +# There were two periods of DST observed in 1942-1945: 1942-05-01 +# midnight to 1944-12-31 midnight and 1945-02-01 to 1945-10-17 midnight. +# "midnight" should mean 24:00 from the context. +# +# War Time Order 1942 [1942-05-01] and War Time (No. 2) Order 1942 [1942-09-29] +# Appendix to the Statutes of 7 George VI. and the Year 1942. p 34, 43 +# https://books.google.com/books?id=5rlNAQAAIAAJ&pg=RA3-PA34 +# https://books.google.com/books?id=5rlNAQAAIAAJ&pg=RA3-PA43 +# +# War Time Order 1943 [1943-03-31] and War Time Order 1944 [1943-12-29] +# Appendix to the Statutes of 8 George VI. and the Year 1943. p 9-10, 28-29 +# https://books.google.com/books?id=5rlNAQAAIAAJ&pg=RA4-PA9 +# https://books.google.com/books?id=5rlNAQAAIAAJ&pg=RA4-PA28 +# +# War Time Order 1945 [1945-01-31] and the Order which revoke War Time Order +# 1945 [1945-10-16] Appendix to the Statutes of 9 George VI. and the Year +# 1945. p 160, 247-248 +# https://books.google.com/books?id=5rlNAQAAIAAJ&pg=RA6-PA160 +# https://books.google.com/books?id=5rlNAQAAIAAJ&pg=RA6-PA247 +# # From Sue Williams (2006-12-07): # The Bahamas announced about a month ago that they plan to change their DST # rules to sync with the U.S. starting in 2007.... # http://www.jonesbahamas.com/?c=45&a=10412 -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule Bahamas 1942 only - May 1 24:00 1:00 W +Rule Bahamas 1944 only - Dec 31 24:00 0 S +Rule Bahamas 1945 only - Feb 1 0:00 1:00 W +Rule Bahamas 1945 only - Aug 14 23:00u 1:00 P # Peace +Rule Bahamas 1945 only - Oct 17 24:00 0 S Rule Bahamas 1964 1975 - Oct lastSun 2:00 0 S Rule Bahamas 1964 1975 - Apr lastSun 2:00 1:00 D -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Nassau -5:09:30 - LMT 1912 Mar 2 -5:00 Bahamas E%sT 1976 -5:00 US E%sT @@ -2810,46 +3001,173 @@ # For 1899 Milne gives -3:58:29.2; round that. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Barb 1977 only - Jun 12 2:00 1:00 D Rule Barb 1977 1978 - Oct Sun>=1 2:00 0 S Rule Barb 1978 1980 - Apr Sun>=15 2:00 1:00 D Rule Barb 1979 only - Sep 30 2:00 0 S Rule Barb 1980 only - Sep 25 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Barbados -3:58:29 - LMT 1924 # Bridgetown -3:58:29 - BMT 1932 # Bridgetown Mean Time -4:00 Barb A%sT # Belize -# Whitman entirely disagrees with Shanks; go with Shanks & Pottenger. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -Rule Belize 1918 1942 - Oct Sun>=2 0:00 0:30 -0530 -Rule Belize 1919 1943 - Feb Sun>=9 0:00 0 CST + +# From P Chan (2020-11-03): +# Below are some laws related to the time in British Honduras/Belize: +# +# Definition of Time Ordinance, 1927 (No.4 of 1927) [1927-04-01] +# Ordinances of British Honduras Passed in the Year 1927, p 19-20 +# https://books.google.com/books?id=LqEpAQAAMAAJ&pg=RA3-PA19 +# +# Definition of Time (Amendment) Ordinance, 1942 (No. 5 of 1942) [1942-06-27] +# Ordinances of British Honduras Passed in the Year 1942, p 31-32 +# https://books.google.com/books?id=h6MpAQAAMAAJ&pg=RA6-PA95-IA44 +# +# Definition of Time Ordinance, 1945 (No. 19 of 1945) [1945-12-15] +# Ordinances of British Honduras Passed in the Year 1945, p 49-50 +# https://books.google.com/books?id=xaMpAQAAMAAJ&pg=RA2-PP1 +# +# Definition of Time Ordinance, 1947 (No. 1 of 1947) [1947-03-11] +# Ordinances of British Honduras Passed in the Year 1947, p 1-2 +# https://books.google.com/books?id=xaMpAQAAMAAJ&pg=RA3-PA1 +# +# Time (Definition of) Ordinance (Chapter 180) +# The Laws of British Honduras in Force on the 15th Day of September, 1958 , Volume IV, p 2580 +# https://books.google.com/books?id=v5QpAQAAMAAJ&pg=PA2580 +# +# Time (Definition of) (Amendment) Ordinance, 1968 (No. 13 of 1968) [1968-08-03] +# https://books.google.com/books?id=xij7KEB_58wC&pg=RA1-PA428-IA9 +# +# Definition of Time Act (Chapter 339) +# Law of Belize, Revised Edition 2000 +# http://www.belizelaw.org/web/lawadmin/PDF%20files/cap339.pdf + +# From Paul Eggert (2020-11-03): +# The transitions below are derived from P Chan's sources, except that the +# 1973 through 1983 transitions are from Shanks & Pottenger since we have +# no better data there. + +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule Belize 1918 1941 - Oct Sat>=1 24:00 0:30 -0530 +Rule Belize 1919 1942 - Feb Sat>=8 24:00 0 CST +Rule Belize 1942 only - Jun 27 24:00 1:00 CWT +Rule Belize 1945 only - Aug 14 23:00u 1:00 CPT +Rule Belize 1945 only - Dec 15 24:00 0 CST +Rule Belize 1947 1967 - Oct Sat>=1 24:00 0:30 -0530 +Rule Belize 1948 1968 - Feb Sat>=8 24:00 0 CST Rule Belize 1973 only - Dec 5 0:00 1:00 CDT Rule Belize 1974 only - Feb 9 0:00 0 CST Rule Belize 1982 only - Dec 18 0:00 1:00 CDT Rule Belize 1983 only - Feb 12 0:00 0 CST -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone America/Belize -5:52:48 - LMT 1912 Apr +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone America/Belize -5:52:48 - LMT 1912 Apr 1 -6:00 Belize %s # Bermuda +# From Paul Eggert (2020-11-24): # For 1899 Milne gives -4:19:18.3 as the meridian of the clock tower, -# Bermuda dockyard, Ireland I; round that. +# Bermuda dockyard, Ireland I. This agrees with standard offset given in the +# Daylight Saving Act, 1917 cited below. Round that to the nearest second. +# It is not known when this time became standard for Bermuda; guess 1890. +# The transition to -04 was specified by: +# 1930: The Time Zone Act, 1929 (1929: No. 39) [1929-11-08] +# https://books.google.com/books?id=7tdMAQAAIAAJ&pg=RA54-PP1 + +# From P Chan (2020-11-20): +# Most of the information can be found online from the Bermuda National +# Library - Digital Collection which includes The Royal Gazette (RG) until 1957 +# https://bnl.contentdm.oclc.org/digital/ +# I will cite the ID. For example, [10000] means +# https://bnl.contentdm.oclc.org/digital/collection/BermudaNP02/id/10000 +# +# 1917: Apr 5 midnight to Sep 30 midnight +# Daylight Saving Act, 1917 (1917 No. 13) [1917-04-02] +# Bermuda Acts and Resolves 1917, p 37-38 +# https://books.google.com/books?id=M-lCAQAAMAAJ&pg=PA36-IA2 +# RG, 1917-04-04, p 6 [42340] gives the spring forward date. +# +# 1918: Apr 13 midnight to Sep 15 midnight +# Daylight Saving Act, 1918 (1918 No. 9) [1918-04-06] +# Bermuda Acts and Resolves 1917, p 13 +# https://books.google.com/books?id=K-lCAQAAMAAJ&pg=RA1-PA7 +# +# Note that local mean time was still used before 1930. +# +# During WWII, DST was introduced by Defence Regulations +# 1942: Jan 11 02:00 to Oct 18 02:00 [113646], [115726] +# 1943: Mar 21 02:00 to Oct 31 02:00 [116704], [118193] +# 1944: Mar 12 02:00 to Nov 5 02:00 [119225], [121593] +# 1945: Mar 11 02:00 to Nov 4 02:00 [122369], [124461] +# RG, 1942-01-08, p 2, 1942-10-12, p 2 , 1943-03-06, p 2, 1943-09-03, p 1, +# 1944-02-29, p 6, 1944-09-20, p 2, 1945-02-13, p 2, 1945-11-03, p 1 +# +# In 1946, the House of Assembly rejected DST twice. [128686], [128076] +# RG, 1946-03-16 p 1,1946-04-13 p 1 +# +# 1947: third Sunday in May 02:00 to second Sunday in September 02:00 +# DST in 1947 was defined in the Daylight Saving Act, 1947 (1947: No. 12) +# which expired at the end of the year. [125784] ,[132405], [144454], [138226] +# RG, 1947-02-27, p 1, 1947-05-15, p 1, 1947-09-13, p 1, 1947-12-30, p 1 +# +# 1948-1952: fourth Sunday in May 02:00 to first Sunday in September 02:00 +# DST in 1948 was defined in the Daylight Saving Act, 1948 (1948 : No. 12) +# which was set to expired at the end of the year but it was extended until +# the end of 1952 and was not further extended. +# [129802], [139403], [146008], [135240], [144330], [139049], [143309], +# [148271], [149773], [153589], [153802], [155924] +# RG, 1948-04-13, p 1, 1948-05-22, p 1, 1948-09-04, p 1, 1949-05-21, p1, +# 1949-09-03, p 1, 1950-05-27 p 1, 1950-09-02, p 1, 1951-05-27, p 1, +# 1951-09-01, p 1, 1952-05-23, p 1, 1952-09-26, p 1, 1952-12-21, p 8 +# +# In 1953-1955, the House of Assembly rejected DST each year. [158996], +# [162620], [166720] RG, 1953-05-02, p 1, 1954-04-01 p 1, 1955-03-12, p 1 +# +# 1956: fourth Sunday in May 02:00 to last Sunday in October 02:00 +# Time Zone (Seasonal Variation) Act, 1956 (1956: No.44) [1956-05-25] +# Bermuda Public Acts 1956, p 331-332 +# https://books.google.com/books?id=Xs1AlmD_cEwC&pg=PA63 +# +# The extension of the Act was rejected by the House of Assembly. [176218] +# RG, 1956-12-13, p 1 +# +# From the Chronological Table of Public and Private Acts up to 1985, it seems +# that there does not exist other Acts related to DST before 1973. +# https://books.google.com/books?id=r9hMAQAAIAAJ&pg=RA23-PA1 +# Public Acts of the Legislature of the Islands of Bermuda, Together with +# Statutory Instruments in Force Thereunder, Vol VII # From Dan Jones, reporting in The Royal Gazette (2006-06-26): - # Next year, however, clocks in the US will go forward on the second Sunday # in March, until the first Sunday in November. And, after the Time Zone # (Seasonal Variation) Bill 2006 was passed in the House of Assembly on # Friday, the same thing will happen in Bermuda. # http://www.theroyalgazette.com/apps/pbcs.dll/article?AID=/20060529/NEWS/105290135 -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Atlantic/Bermuda -4:19:18 - LMT 1930 Jan 1 2:00 # Hamilton - -4:00 - AST 1974 Apr 28 2:00 +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S +Rule Bermuda 1917 only - Apr 5 24:00 1:00 - +Rule Bermuda 1917 only - Sep 30 24:00 0 - +Rule Bermuda 1918 only - Apr 13 24:00 1:00 - +Rule Bermuda 1918 only - Sep 15 24:00 0 S +Rule Bermuda 1942 only - Jan 11 2:00 1:00 D +Rule Bermuda 1942 only - Oct 18 2:00 0 S +Rule Bermuda 1943 only - Mar 21 2:00 1:00 D +Rule Bermuda 1943 only - Oct 31 2:00 0 S +Rule Bermuda 1944 1945 - Mar Sun>=8 2:00 1:00 D +Rule Bermuda 1944 1945 - Nov Sun>=1 2:00 0 S +Rule Bermuda 1947 only - May Sun>=15 2:00 1:00 D +Rule Bermuda 1947 only - Sep Sun>=8 2:00 0 S +Rule Bermuda 1948 1952 - May Sun>=22 2:00 1:00 D +Rule Bermuda 1948 1952 - Sep Sun>=1 2:00 0 S +Rule Bermuda 1956 only - May Sun>=22 2:00 1:00 D +Rule Bermuda 1956 only - Oct lastSun 2:00 0 S + +# Zone NAME STDOFF RULES FORMAT [UNTIL] +Zone Atlantic/Bermuda -4:19:18 - LMT 1890 # Hamilton + -4:19:18 Bermuda BMT/BST 1930 Jan 1 2:00 + -4:00 Bermuda A%sT 1974 Apr 28 2:00 -4:00 Canada A%sT 1976 -4:00 US A%sT @@ -2860,7 +3178,7 @@ # Milne gives -5:36:13.3 as San José mean time; round to nearest. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule CR 1979 1980 - Feb lastSun 0:00 1:00 D Rule CR 1979 1980 - Jun Sun>=1 0:00 0 S Rule CR 1991 1992 - Jan Sat>=15 0:00 1:00 D @@ -2869,7 +3187,7 @@ Rule CR 1991 only - Jul 1 0:00 0 S Rule CR 1992 only - Mar 15 0:00 0 S # There are too many San Josés elsewhere, so we'll use 'Costa Rica'. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Costa_Rica -5:36:13 - LMT 1890 # San José -5:36:13 - SJMT 1921 Jan 15 # San José Mean Time -6:00 CR C%sT @@ -3034,7 +3352,7 @@ # From Paul Eggert (2012-11-03): # For now, assume the future rule is first Sunday in November. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Cuba 1928 only - Jun 10 0:00 1:00 D Rule Cuba 1928 only - Oct 10 0:00 0 S Rule Cuba 1940 1942 - Jun Sun>=1 0:00 1:00 D @@ -3075,7 +3393,7 @@ Rule Cuba 2012 max - Nov Sun>=1 0:00s 0 S Rule Cuba 2013 max - Mar Sun>=8 0:00s 1:00 D -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Havana -5:29:28 - LMT 1890 -5:29:36 - HMT 1925 Jul 19 12:00 # Havana MT -5:00 Cuba C%sT @@ -3103,14 +3421,14 @@ # decided to revert. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule DR 1966 only - Oct 30 0:00 1:00 EDT Rule DR 1967 only - Feb 28 0:00 0 EST Rule DR 1969 1973 - Oct lastSun 0:00 0:30 -0430 Rule DR 1970 only - Feb 21 0:00 0 EST Rule DR 1971 only - Jan 20 0:00 0 EST Rule DR 1972 1974 - Jan 21 0:00 0 EST -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Santo_Domingo -4:39:36 - LMT 1890 -4:40 - SDMT 1933 Apr 1 12:00 # S. Dom. MT -5:00 DR %s 1974 Oct 27 @@ -3120,12 +3438,12 @@ # El Salvador -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Salv 1987 1988 - May Sun>=1 0:00 1:00 D Rule Salv 1987 1988 - Sep lastSun 0:00 0 S # There are too many San Salvadors elsewhere, so use America/El_Salvador # instead of America/San_Salvador. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/El_Salvador -5:56:48 - LMT 1921 # San Salvador -6:00 Salv C%sT @@ -3149,7 +3467,7 @@ # (2006-04-19), says DST ends at 24:00. See # http://www.sieca.org.gt/Sitio_publico/Energeticos/Doc/Medidas/Cambio_Horario_Nac_190406.pdf -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Guat 1973 only - Nov 25 0:00 1:00 D Rule Guat 1974 only - Feb 24 0:00 0 S Rule Guat 1983 only - May 21 0:00 1:00 D @@ -3158,7 +3476,7 @@ Rule Guat 1991 only - Sep 7 0:00 0 S Rule Guat 2006 only - Apr 30 0:00 1:00 D Rule Guat 2006 only - Oct 1 0:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Guatemala -6:02:04 - LMT 1918 Oct 5 -6:00 Guat C%sT @@ -3230,7 +3548,7 @@ # I have not been able to find a more authoritative source: # https://www.haitilibre.com/en/news-20319-haiti-notices-time-change-in-haiti.html -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Haiti 1983 only - May 8 0:00 1:00 D Rule Haiti 1984 1987 - Apr lastSun 0:00 1:00 D Rule Haiti 1983 1987 - Oct lastSun 0:00 0 S @@ -3244,7 +3562,7 @@ Rule Haiti 2012 2015 - Nov Sun>=1 2:00 0 S Rule Haiti 2017 max - Mar Sun>=8 2:00 1:00 D Rule Haiti 2017 max - Nov Sun>=1 2:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Port-au-Prince -4:49:20 - LMT 1890 -4:49 - PPMT 1917 Jan 24 12:00 # P-a-P MT -5:00 Haiti E%sT @@ -3278,12 +3596,12 @@ # http://www.laprensahn.com/pais_nota.php?id04962=7386 # So it seems that Honduras will not enter DST this year.... -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Hond 1987 1988 - May Sun>=1 0:00 1:00 D Rule Hond 1987 1988 - Sep lastSun 0:00 0 S Rule Hond 2006 only - May Sun>=1 0:00 1:00 D Rule Hond 2006 only - Aug Mon>=1 0:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Tegucigalpa -5:48:52 - LMT 1921 Apr -6:00 Hond C%sT # @@ -3304,7 +3622,7 @@ # Neita L. The politician in all of us. Jamaica Observer 2014-09-20 # http://www.jamaicaobserver.com/columns/The-politician-in-all-of-us_17573647 # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Jamaica -5:07:10 - LMT 1890 # Kingston -5:07:10 - KMT 1912 Feb # Kingston Mean Time -5:00 - EST 1974 @@ -3312,7 +3630,7 @@ -5:00 - EST # Martinique -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Martinique -4:04:20 - LMT 1890 # Fort-de-France -4:04:20 - FFMT 1911 May # Fort-de-France MT -4:00 - AST 1980 Apr 6 @@ -3369,14 +3687,14 @@ # The natural sun time is restored in all the national territory, in that the # time is returned one hour at 01:00 am of October 1 of 2006. # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Nic 1979 1980 - Mar Sun>=16 0:00 1:00 D Rule Nic 1979 1980 - Jun Mon>=23 0:00 0 S Rule Nic 2005 only - Apr 10 0:00 1:00 D Rule Nic 2005 only - Oct Sun>=1 0:00 0 S Rule Nic 2006 only - Apr 30 2:00 1:00 D Rule Nic 2006 only - Oct Sun>=1 1:00 0 S -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Managua -5:45:08 - LMT 1890 -5:45:12 - MMT 1934 Jun 23 # Managua Mean Time? -6:00 - CST 1973 May @@ -3388,7 +3706,7 @@ -6:00 Nic C%sT # Panama -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Panama -5:18:08 - LMT 1890 -5:19:36 - CMT 1908 Apr 22 # Colón Mean Time -5:00 - EST @@ -3396,7 +3714,7 @@ # Puerto Rico # There are too many San Juans elsewhere, so we'll use 'Puerto_Rico'. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Puerto_Rico -4:24:25 - LMT 1899 Mar 28 12:00 # San Juan -4:00 - AST 1942 May 3 -4:00 US A%sT 1946 @@ -3408,7 +3726,7 @@ # St Pierre and Miquelon # There are too many St Pierres elsewhere, so we'll use 'Miquelon'. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Miquelon -3:44:40 - LMT 1911 May 15 # St Pierre -4:00 - AST 1980 May -3:00 - -03 1987 @@ -3432,7 +3750,7 @@ # "Eastern Standard Times Begins 2007 # Clocks are set back one hour at 2:00 a.m. local Daylight Saving Time" # indicating that the normal ET rules are followed. -# + # From Paul Eggert (2014-08-19): # The 2014-08-13 Cabinet meeting decided to stay on UT -04 year-round. See: # http://tcweeklynews.com/daylight-savings-time-to-be-maintained-p5353-127.htm @@ -3447,19 +3765,42 @@ # during the summer months and Standard Time, also known as Local # Time, during the winter months with effect from April 2018 ... # https://www.gov.uk/government/news/turks-and-caicos-post-cabinet-meeting-statement--3 -# # From Paul Eggert (2017-08-26): # The date of effect of the spring 2018 change appears to be March 11, # which makes more sense. See: Hamilton D. Time change back # by March 2018 for TCI. Magnetic Media. 2017-08-25. # http://magneticmediatv.com/2017/08/time-change-back-by-march-2018-for-tci/ # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# From P Chan (2020-11-27): +# Standard Time Declaration Order 2015 (L.N. 15/2015) +# http://online.fliphtml5.com/fizd/czin/#p=2 +# +# Standard Time Declaration Order 2017 (L.N. 31/2017) +# http://online.fliphtml5.com/fizd/dmcu/#p=2 +# +# From Tim Parenti (2020-12-05): +# Although L.N. 31/2017 reads that it "shall come into operation at 2:00 a.m. +# on 11th March 2018", a precise interpretation here poses some problems. The +# order states that "the standard time to be observed throughout the Turks and +# Caicos Islands shall be the same time zone as the Eastern United States of +# America" and further clarifies "[f]or the avoidance of doubt" that it +# "applies to the Eastern Standard Time as well as any changes thereto for +# Daylight Saving Time." However, as clocks in Turks and Caicos approached +# 02:00 -04, and thus the declared implementation time, it was still 01:00 EST +# (-05), as DST in the Eastern US would not start until an hour later. +# +# Since it is unlikely that those on the islands switched their clocks twice in +# the span of an hour, we assume instead that the adoption of EDT actually took +# effect once clocks in the Eastern US had sprung forward, from 03:00 -04. +# This discrepancy only affects the time zone abbreviation and DST flag for the +# intervening hour, not wall clock times, as -04 was maintained throughout. + +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Grand_Turk -4:44:32 - LMT 1890 -5:07:10 - KMT 1912 Feb # Kingston Mean Time -5:00 - EST 1979 - -5:00 US E%sT 2015 Nov Sun>=1 2:00 - -4:00 - AST 2018 Mar 11 3:00 + -5:00 US E%sT 2015 Mar 8 2:00 + -4:00 - AST 2018 Mar 11 3:00 -5:00 US E%sT # British Virgin Is
diff --git a/make/data/tzdata/pacificnew b/make/data/tzdata/pacificnew deleted file mode 100644 index 020b599..0000000 --- a/make/data/tzdata/pacificnew +++ /dev/null
@@ -1,52 +0,0 @@ -# -# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -# -# This code is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License version 2 only, as -# published by the Free Software Foundation. Oracle designates this -# particular file as subject to the "Classpath" exception as provided -# by Oracle in the LICENSE file that accompanied this code. -# -# This code is distributed in the hope that it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# version 2 for more details (a copy is included in the LICENSE file that -# accompanied this code). -# -# You should have received a copy of the GNU General Public License version -# 2 along with this work; if not, write to the Free Software Foundation, -# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -# -# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -# or visit www.oracle.com if you need additional information or have any -# questions. -# -# tzdb data for proposed US election time (this file is obsolete) - -# This file is in the public domain, so clarified as of -# 2009-05-17 by Arthur David Olson. - -# From Arthur David Olson (1989-04-05): -# On 1989-04-05, the U. S. House of Representatives passed (238-154) a bill -# establishing "Pacific Presidential Election Time"; it was not acted on -# by the Senate or signed into law by the President. -# You might want to change the "PE" (Presidential Election) below to -# "Q" (Quadrennial) to maintain three-character zone abbreviations. -# If you're really conservative, you might want to change it to "D". -# Avoid "L" (Leap Year), which won't be true in 2100. - -# If Presidential Election Time is ever established, replace "XXXX" below -# with the year the law takes effect and uncomment the "##" lines. - -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -## Rule Twilite XXXX max - Apr Sun>=1 2:00 1:00 D -## Rule Twilite XXXX max uspres Oct lastSun 2:00 1:00 PE -## Rule Twilite XXXX max uspres Nov Sun>=7 2:00 0 S -## Rule Twilite XXXX max nonpres Oct lastSun 2:00 0 S - -# Zone NAME GMTOFF RULES/SAVE FORMAT [UNTIL] -## Zone America/Los_Angeles-PET -8:00 US P%sT XXXX -## -8:00 Twilite P%sT - -# For now... -Link America/Los_Angeles US/Pacific-New ##
diff --git a/make/data/tzdata/southamerica b/make/data/tzdata/southamerica index 3f01647..566dabf 100644 --- a/make/data/tzdata/southamerica +++ b/make/data/tzdata/southamerica
@@ -71,7 +71,7 @@ # I am sending modifications to the Argentine time zone table... # AR was chosen because they are the ISO letters that represent Argentina. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Arg 1930 only - Dec 1 0:00 1:00 - Rule Arg 1931 only - Apr 1 0:00 0 - Rule Arg 1931 only - Oct 15 0:00 1:00 - @@ -419,7 +419,7 @@ # plus is that this silences a zic complaint that there's no POSIX TZ # setting for timestamps past 2038. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] # # Buenos Aires (BA), Capital Federal (CF), Zone America/Argentina/Buenos_Aires -3:53:48 - LMT 1894 Oct 31 @@ -600,7 +600,7 @@ Link America/Curacao America/Aruba # Bolivia -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/La_Paz -4:32:36 - LMT 1890 -4:32:36 - CMT 1931 Oct 15 # Calamarca MT -4:32:36 1:00 BST 1932 Mar 21 # Bolivia ST @@ -792,7 +792,7 @@ # From Paul Eggert (2013-10-17): # For now, assume western Amazonas will change as well. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S # Decree 20,466 <http://pcdsh01.on.br/HV20466.htm> (1931-10-01) # Decree 21,896 <http://pcdsh01.on.br/HV21896.htm> (1932-01-10) Rule Brazil 1931 only - Oct 3 11:00 1:00 - @@ -943,14 +943,13 @@ # removed Tocantins. Rule Brazil 2013 2014 - Feb Sun>=15 0:00 0 - Rule Brazil 2015 only - Feb Sun>=22 0:00 0 - -Rule Brazil 2016 2022 - Feb Sun>=15 0:00 0 - +Rule Brazil 2016 2019 - Feb Sun>=15 0:00 0 - # From Steffen Thorsen (2017-12-18): # According to many media sources, next year's DST start in Brazil will move to -# the first Sunday of November, and it will stay like that for the years after. +# the first Sunday of November # ... https://www.timeanddate.com/news/time/brazil-delays-dst-2018.html # From Steffen Thorsen (2017-12-20): # http://www.planalto.gov.br/ccivil_03/_ato2015-2018/2017/decreto/D9242.htm -# # From Fábio Gomes (2018-10-04): # The Brazilian president just announced a new change on this year DST. # It was scheduled to start on November 4th and it was changed to November 18th. @@ -958,22 +957,21 @@ # The Brazilian government just announced that the change in DST was # canceled.... Maybe the president Michel Temer also woke up one hour # earlier today. :) -Rule Brazil 2018 max - Nov Sun>=1 0:00 1:00 - -Rule Brazil 2023 only - Feb Sun>=22 0:00 0 - -Rule Brazil 2024 2025 - Feb Sun>=15 0:00 0 - -Rule Brazil 2026 only - Feb Sun>=22 0:00 0 - -Rule Brazil 2027 2033 - Feb Sun>=15 0:00 0 - -Rule Brazil 2034 only - Feb Sun>=22 0:00 0 - -Rule Brazil 2035 2036 - Feb Sun>=15 0:00 0 - -Rule Brazil 2037 only - Feb Sun>=22 0:00 0 - -# From Arthur David Olson (2008-09-29): -# The next is wrong in some years but is better than nothing. -Rule Brazil 2038 max - Feb Sun>=15 0:00 0 - - -# The latest ruleset listed above says that the following states observe DST: +Rule Brazil 2018 only - Nov Sun>=1 0:00 1:00 - +# The last ruleset listed above says that the following states observed DST: # DF, ES, GO, MG, MS, MT, PR, RJ, RS, SC, SP. +# +# From Steffen Thorsen (2019-04-05): +# According to multiple sources the Brazilian president wants to get rid of DST. +# https://gmconline.com.br/noticias/politica/bolsonaro-horario-de-verao-deve-acabar-este-ano +# https://g1.globo.com/economia/noticia/2019/04/05/governo-anuncia-fim-do-horario-de-verao.ghtml +# From Marcus Diniz (2019-04-25): +# Brazil no longer has DST changes - decree signed today +# https://g1.globo.com/politica/noticia/2019/04/25/bolsonaro-assina-decreto-que-acaba-com-o-horario-de-verao.ghtml +# From Daniel Soares de Oliveira (2019-04-26): +# http://www.planalto.gov.br/ccivil_03/_Ato2019-2022/2019/Decreto/D9772.htm -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] # # Fernando de Noronha (administratively part of PE) Zone America/Noronha -2:09:40 - LMT 1914 @@ -1255,14 +1253,8 @@ # From Juan Correa (2016-12-04): # Magallanes region ... will keep DST (UTC -3) all year round.... # http://www.soychile.cl/Santiago/Sociedad/2016/12/04/433428/Bachelet-firmo-el-decreto-para-establecer-un-horario-unico-para-la-Region-de-Magallanes.aspx -# # From Deborah Goldsmith (2017-01-19): # http://www.diariooficial.interior.gob.cl/publicaciones/2017/01/17/41660/01/1169626.pdf -# From Paul Eggert (2017-01-19): -# The above says the Magallanes change expires 2019-05-11 at 24:00, -# so in theory, they will revert to -04/-03 after that, which means -# they will switch from -03 to -04 one hour after Santiago does that day. -# For now, assume that they will not revert. # From Juan Correa (2018-08-13): # As of moments ago, the Ministry of Energy in Chile has announced the new @@ -1281,8 +1273,15 @@ # https://twitter.com/MinEnergia/status/1029009354001973248 # "We will keep the new time policy unchanged for at least the next 4 years." # So we extend the new rules on Saturdays at 24:00 mainland time indefinitely. +# From Juan Correa (2019-02-04): +# http://www.diariooficial.interior.gob.cl/publicaciones/2018/11/23/42212/01/1498738.pdf +# From Paul Eggert (2019-09-01): +# The above says the Magallanes exception expires 2022-04-02 at 24:00, +# so in theory, they will revert to -04/-03 after that. +# For now, assume that they will not revert, +# since they have extended the expiration date once already. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Chile 1927 1931 - Sep 1 0:00 1:00 - Rule Chile 1928 1932 - Apr 1 0:00 0 - Rule Chile 1968 only - Nov 3 4:00u 1:00 - @@ -1321,7 +1320,7 @@ Rule Chile 2019 max - Sep Sun>=2 4:00u 1:00 - # IATA SSIM anomalies: (1992-02) says 1992-03-14; # (1996-09) says 1998-03-08. Ignore these. -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Santiago -4:42:46 - LMT 1890 -4:42:46 - SMT 1910 Jan 10 # Santiago Mean Time -5:00 - -05 1916 Jul 1 @@ -1370,7 +1369,7 @@ # Palmer has followed Chile. Prior to that, before the Falklands War, # Palmer used to be supplied from Argentina. # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Antarctica/Palmer 0 - -00 1965 -4:00 Arg -04/-03 1969 Oct 5 -3:00 Arg -03/-02 1982 May @@ -1382,10 +1381,10 @@ # Milne gives 4:56:16.4 for Bogotá time in 1899; round to nearest. He writes, # "A variation of fifteen minutes in the public clocks of Bogota is not rare." -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule CO 1992 only - May 3 0:00 1:00 - Rule CO 1993 only - Apr 4 0:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Bogota -4:56:16 - LMT 1884 Mar 13 -4:56:16 - BMT 1914 Nov 23 # Bogotá Mean Time -5:00 CO -05/-04 @@ -1410,7 +1409,7 @@ # Netherlands as Kingdom Islands. This won't affect their time zones # though, as far as we know. # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Curacao -4:35:47 - LMT 1912 Feb 12 # Willemstad -4:30 - -0430 1965 -4:00 - AST @@ -1442,11 +1441,11 @@ # (Not one step back), the clocks went back in 1993 and the experiment was not # repeated. For now, assume transitions were at 00:00 local time country-wide. # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Ecuador 1992 only - Nov 28 0:00 1:00 - Rule Ecuador 1993 only - Feb 5 0:00 0 - # -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Guayaquil -5:19:20 - LMT 1890 -5:14:00 - QMT 1931 # Quito Mean Time -5:00 Ecuador -05/-04 @@ -1536,7 +1535,7 @@ # For now we will assume permanent -03 for the Falklands # until advised differently (to apply for 2012 and beyond, after the 2011 # experiment was apparently successful.) -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Falk 1937 1938 - Sep lastSun 0:00 1:00 - Rule Falk 1938 1942 - Mar Sun>=19 0:00 0 - Rule Falk 1939 only - Oct 1 0:00 1:00 - @@ -1549,7 +1548,7 @@ Rule Falk 1986 2000 - Apr Sun>=16 0:00 0 - Rule Falk 2001 2010 - Apr Sun>=15 2:00 0 - Rule Falk 2001 2010 - Sep Sun>=1 2:00 1:00 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Atlantic/Stanley -3:51:24 - LMT 1890 -3:51:24 - SMT 1912 Mar 12 # Stanley Mean Time -4:00 Falk -04/-03 1983 May @@ -1558,13 +1557,13 @@ -3:00 - -03 # French Guiana -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Cayenne -3:29:20 - LMT 1911 Jul -4:00 - -04 1967 Oct -3:00 - -03 # Guyana -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Guyana -3:52:40 - LMT 1915 Mar # Georgetown -3:45 - -0345 1975 Jul 31 -3:00 - -03 1991 @@ -1582,7 +1581,7 @@ # No time of the day is established for the adjustment, so people normally # adjust their clocks at 0 hour of the given dates. # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Para 1975 1988 - Oct 1 0:00 1:00 - Rule Para 1975 1978 - Mar 1 0:00 0 - Rule Para 1979 1991 - Apr 1 0:00 0 - @@ -1658,7 +1657,7 @@ # http://www.presidencia.gov.py/archivos/documentos/DECRETO1264_ey9r8zai.pdf Rule Para 2013 max - Mar Sun>=22 0:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Asuncion -3:50:40 - LMT 1890 -3:50:40 - AMT 1931 Oct 10 # Asunción Mean Time -4:00 - -04 1972 Oct @@ -1675,7 +1674,7 @@ # From Paul Eggert (2006-03-22): # Shanks & Pottenger don't have this transition. Assume 1986 was like 1987. -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Peru 1938 only - Jan 1 0:00 1:00 - Rule Peru 1938 only - Apr 1 0:00 0 - Rule Peru 1938 1939 - Sep lastSun 0:00 1:00 - @@ -1687,13 +1686,13 @@ # IATA is ambiguous for 1993/1995; go with Shanks & Pottenger. Rule Peru 1994 only - Jan 1 0:00 1:00 - Rule Peru 1994 only - Apr 1 0:00 0 - -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Lima -5:08:12 - LMT 1890 -5:08:36 - LMT 1908 Jul 28 # Lima Mean Time? -5:00 Peru -05/-04 # South Georgia -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone Atlantic/South_Georgia -2:26:08 - LMT 1890 # Grytviken -2:00 - -02 @@ -1701,7 +1700,7 @@ # uninhabited; scientific personnel have wintered # Suriname -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Paramaribo -3:40:40 - LMT 1911 -3:40:52 - PMT 1935 # Paramaribo Mean Time -3:40:36 - PMT 1945 Oct # The capital moved? @@ -1709,7 +1708,7 @@ -3:00 - -03 # Trinidad and Tobago -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Port_of_Spain -4:06:04 - LMT 1912 Mar 2 -4:00 - AST @@ -1771,7 +1770,7 @@ # https://www.impo.com.uy/diariooficial/1926/03/10/2 # https://www.impo.com.uy/diariooficial/1926/03/18/2 # -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +# Rule NAME FROM TO - IN ON AT SAVE LETTER/S Rule Uruguay 1923 1925 - Oct 1 0:00 0:30 - Rule Uruguay 1924 1926 - Apr 1 0:00 0 - # From Tim Parenti (2018-02-15): @@ -1980,7 +1979,7 @@ # ... published in the official Gazette [2016-04-18], here: # http://historico.tsj.gob.ve/gaceta_ext/abril/1842016/E-1842016-4551.pdf -# Zone NAME GMTOFF RULES FORMAT [UNTIL] +# Zone NAME STDOFF RULES FORMAT [UNTIL] Zone America/Caracas -4:27:44 - LMT 1890 -4:27:40 - CMT 1912 Feb 12 # Caracas Mean Time? -4:30 - -0430 1965 Jan 1 0:00
diff --git a/make/data/tzdata/systemv b/make/data/tzdata/systemv deleted file mode 100644 index 63a48e8..0000000 --- a/make/data/tzdata/systemv +++ /dev/null
@@ -1,62 +0,0 @@ -# -# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -# -# This code is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License version 2 only, as -# published by the Free Software Foundation. Oracle designates this -# particular file as subject to the "Classpath" exception as provided -# by Oracle in the LICENSE file that accompanied this code. -# -# This code is distributed in the hope that it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# version 2 for more details (a copy is included in the LICENSE file that -# accompanied this code). -# -# You should have received a copy of the GNU General Public License version -# 2 along with this work; if not, write to the Free Software Foundation, -# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -# -# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -# or visit www.oracle.com if you need additional information or have any -# questions. -# -# tzdb data for System V rules (this file is obsolete) - -# This file is in the public domain, so clarified as of -# 2009-05-17 by Arthur David Olson. - -# Old rules, should the need arise. -# No attempt is made to handle Newfoundland, since it cannot be expressed -# using the System V "TZ" scheme (half-hour offset), or anything outside -# North America (no support for non-standard DST start/end dates), nor -# the changes in the DST rules in the US after 1976 (which occurred after -# the old rules were written). -# -# If you need the old rules, uncomment ## lines. -# Compile this *without* leap second correction for true conformance. - -# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S -Rule SystemV min 1973 - Apr lastSun 2:00 1:00 D -Rule SystemV min 1973 - Oct lastSun 2:00 0 S -Rule SystemV 1974 only - Jan 6 2:00 1:00 D -Rule SystemV 1974 only - Nov lastSun 2:00 0 S -Rule SystemV 1975 only - Feb 23 2:00 1:00 D -Rule SystemV 1975 only - Oct lastSun 2:00 0 S -Rule SystemV 1976 max - Apr lastSun 2:00 1:00 D -Rule SystemV 1976 max - Oct lastSun 2:00 0 S - -# Zone NAME GMTOFF RULES/SAVE FORMAT [UNTIL] -## Zone SystemV/AST4ADT -4:00 SystemV A%sT -## Zone SystemV/EST5EDT -5:00 SystemV E%sT -## Zone SystemV/CST6CDT -6:00 SystemV C%sT -## Zone SystemV/MST7MDT -7:00 SystemV M%sT -## Zone SystemV/PST8PDT -8:00 SystemV P%sT -## Zone SystemV/YST9YDT -9:00 SystemV Y%sT -## Zone SystemV/AST4 -4:00 - AST -## Zone SystemV/EST5 -5:00 - EST -## Zone SystemV/CST6 -6:00 - CST -## Zone SystemV/MST7 -7:00 - MST -## Zone SystemV/PST8 -8:00 - PST -## Zone SystemV/YST9 -9:00 - YST -## Zone SystemV/HST10 -10:00 - HST
diff --git a/make/data/tzdata/zone.tab b/make/data/tzdata/zone.tab index 2a98586..28db074 100644 --- a/make/data/tzdata/zone.tab +++ b/make/data/tzdata/zone.tab
@@ -79,8 +79,7 @@ AT +4813+01620 Europe/Vienna AU -3133+15905 Australia/Lord_Howe Lord Howe Island AU -5430+15857 Antarctica/Macquarie Macquarie Island -AU -4253+14719 Australia/Hobart Tasmania (most areas) -AU -3956+14352 Australia/Currie Tasmania (King Island) +AU -4253+14719 Australia/Hobart Tasmania AU -3749+14458 Australia/Melbourne Victoria AU -3352+15113 Australia/Sydney New South Wales (most areas) AU -3157+14127 Australia/Broken_Hill New South Wales (Yancowinna) @@ -153,9 +152,9 @@ CA +4906-11631 America/Creston MST - BC (Creston) CA +5946-12014 America/Dawson_Creek MST - BC (Dawson Cr, Ft St John) CA +5848-12242 America/Fort_Nelson MST - BC (Ft Nelson) +CA +6043-13503 America/Whitehorse MST - Yukon (east) +CA +6404-13925 America/Dawson MST - Yukon (west) CA +4916-12307 America/Vancouver Pacific - BC (most areas) -CA +6043-13503 America/Whitehorse Pacific - Yukon (south) -CA +6404-13925 America/Dawson Pacific - Yukon (north) CC -1210+09655 Indian/Cocos CD -0418+01518 Africa/Kinshasa Dem. Rep. of Congo (west) CD -1140+02728 Africa/Lubumbashi Dem. Rep. of Congo (east) @@ -212,7 +211,7 @@ GG +492717-0023210 Europe/Guernsey GH +0533-00013 Africa/Accra GI +3608-00521 Europe/Gibraltar -GL +6411-05144 America/Godthab Greenland (most areas) +GL +6411-05144 America/Nuuk Greenland (most areas) GL +7646-01840 America/Danmarkshavn National Park (east coast) GL +7029-02158 America/Scoresbysund Scoresbysund/Ittoqqortoormiit GL +7634-06847 America/Thule Thule/Pituffik @@ -262,6 +261,7 @@ KY +1918-08123 America/Cayman KZ +4315+07657 Asia/Almaty Kazakhstan (most areas) KZ +4448+06528 Asia/Qyzylorda Qyzylorda/Kyzylorda/Kzyl-Orda +KZ +5312+06337 Asia/Qostanay Qostanay/Kostanay/Kustanay KZ +5017+05710 Asia/Aqtobe Aqtobe/Aktobe KZ +4431+05016 Asia/Aqtau Mangghystau/Mankistau KZ +4707+05156 Asia/Atyrau Atyrau/Atirau/Gur'yev @@ -354,9 +354,12 @@ RS +4450+02030 Europe/Belgrade RU +5443+02030 Europe/Kaliningrad MSK-01 - Kaliningrad RU +554521+0373704 Europe/Moscow MSK+00 - Moscow area -RU +4457+03406 Europe/Simferopol MSK+00 - Crimea -RU +4844+04425 Europe/Volgograd MSK+00 - Volgograd +# The obsolescent zone.tab format cannot represent Europe/Simferopol well. +# Put it in RU section and list as UA. See "territorial claims" above. +# Programs should use zone1970.tab instead; see above. +UA +4457+03406 Europe/Simferopol Crimea RU +5836+04939 Europe/Kirov MSK+00 - Kirov +RU +4844+04425 Europe/Volgograd MSK+00 - Volgograd RU +4621+04803 Europe/Astrakhan MSK+01 - Astrakhan RU +5134+04602 Europe/Saratov MSK+01 - Saratov RU +5420+04824 Europe/Ulyanovsk MSK+01 - Ulyanovsk @@ -418,8 +421,8 @@ TW +2503+12130 Asia/Taipei TZ -0648+03917 Africa/Dar_es_Salaam UA +5026+03031 Europe/Kiev Ukraine (most areas) -UA +4837+02218 Europe/Uzhgorod Ruthenia -UA +4750+03510 Europe/Zaporozhye Zaporozh'ye/Zaporizhia; Lugansk/Luhansk (east) +UA +4837+02218 Europe/Uzhgorod Transcarpathia +UA +4750+03510 Europe/Zaporozhye Zaporozhye and east Lugansk UG +0019+03225 Africa/Kampala UM +2813-17722 Pacific/Midway Midway Islands UM +1917+16637 Pacific/Wake Wake Island
diff --git a/make/devkit/Makefile b/make/devkit/Makefile index df4596b..c1dc8c4 100644 --- a/make/devkit/Makefile +++ b/make/devkit/Makefile
@@ -41,9 +41,12 @@ # To build the full set of crosstools for additional platforms, use a command # line looking like this: # -# make cross_compile_target="aarch64-linux-gnu" BASE_OS=Fedora27 +# make TARGETS="aarch64-linux-gnu" BASE_OS=Fedora # or -# make cross_compile_target="arm-linux-gnueabihf" BASE_OS=Fedora27 +# make TARGETS="arm-linux-gnueabihf ppc64-linux-gnu" BASE_OS=Fedora BASE_OS_VERSION=17 +# +# to build several devkits for a specific OS version at once. +# You can find the final results under ../../build/devkit/result/<host>-to-<target> # # This is the makefile which iterates over all host and target platforms. # @@ -52,18 +55,18 @@ cpu := $(shell uname -p) # Figure out what platform this is building on. -me := $(cpu)-$(if $(findstring Linux,$(os)),unknown-linux-gnu) +me := $(cpu)-$(if $(findstring Linux,$(os)),linux-gnu) $(info Building on platform $(me)) # # By default just build for the current platform, which is assumed to be Linux # -ifeq ($(cross_compile_target), ) +ifeq ($(TARGETS), ) platforms := $(me) host_platforms := $(platforms) else - platforms := $(cross_compile_target) + platforms := $(TARGETS) host_platforms := $(me) endif target_platforms := $(platforms) @@ -79,37 +82,37 @@ OUTPUT_ROOT = $(abspath ../../build/devkit) RESULT = $(OUTPUT_ROOT)/result -submakevars = HOST=$@ BUILD=$(me) \ - RESULT=$(RESULT) PREFIX=$(RESULT)/$@ \ - OUTPUT_ROOT=$(OUTPUT_ROOT) +submakevars = HOST=$@ BUILD=$(me) RESULT=$(RESULT) OUTPUT_ROOT=$(OUTPUT_ROOT) + $(host_platforms) : @echo 'Building compilers for $@' @echo 'Targets: $(target_platforms)' for p in $(filter $@, $(target_platforms)) $(filter-out $@, $(target_platforms)); do \ - $(MAKE) -f Tools.gmk download-rpms $(submakevars) TARGET=$$p && \ + $(MAKE) -f Tools.gmk download-rpms $(submakevars) \ + TARGET=$$p PREFIX=$(RESULT)/$@-to-$$p && \ $(MAKE) -f Tools.gmk all $(submakevars) \ - TARGET=$$p || exit 1 ; \ + TARGET=$$p PREFIX=$(RESULT)/$@-to-$$p && \ + $(MAKE) -f Tools.gmk ccache $(submakevars) \ + TARGET=$@ PREFIX=$(RESULT)/$@-to-$$p BUILDDIR=$(OUTPUT_ROOT)/$@/$$p || exit 1 ; \ done - @echo 'Building ccache program for $@' - $(MAKE) -f Tools.gmk ccache $(submakevars) TARGET=$@ @echo 'All done"' today := $(shell date +%Y%m%d) define Mktar - $(1)_tar = $$(RESULT)/sdk-$(1)-$$(today).tar.gz - $$($(1)_tar) : PLATFORM = $(1) - TARFILES += $$($(1)_tar) - $$($(1)_tar) : $(1) $$(shell find $$(RESULT)/$(1)) + $(1)-to-$(2)_tar = $$(RESULT)/sdk-$(1)-to-$(2)-$$(today).tar.gz + $$($(1)-to-$(2)_tar) : PLATFORM = $(1)-to-$(2) + TARFILES += $$($(1)-to-$(2)_tar) + $$($(1)-to-$(2)_tar) : $$(shell find $$(RESULT)/$(1)-to-$(2) -type f) endef -$(foreach p,$(host_platforms),$(eval $(call Mktar,$(p)))) +$(foreach p,$(host_platforms),$(foreach t,$(target_platforms),$(eval $(call Mktar,$(p),$(t))))) tars : all $(TARFILES) onlytars : $(TARFILES) %.tar.gz : @echo 'Creating compiler package $@' - cd $(RESULT)/$(PLATFORM) && tar -czf $@ * + cd $(RESULT) && tar -czf $@ $(PLATFORM)/* touch $@ clean :
diff --git a/make/devkit/Tools.gmk b/make/devkit/Tools.gmk index 7969e60..2106991 100644 --- a/make/devkit/Tools.gmk +++ b/make/devkit/Tools.gmk
@@ -52,16 +52,25 @@ $(info ARCH=$(ARCH)) ifeq ($(BASE_OS), OEL6) - OEL_URL := http://yum.oracle.com/repo/OracleLinux/OL6/4/base/$(ARCH)/ + BASE_URL := http://yum.oracle.com/repo/OracleLinux/OL6/4/base/$(ARCH)/ LINUX_VERSION := OEL6.4 -else ifeq ($(BASE_OS), Fedora27) - ifeq ($(ARCH), aarch64) - FEDORA_TYPE=fedora-secondary - else - FEDORA_TYPE=fedora/linux +else ifeq ($(BASE_OS), Fedora) + DEFAULT_OS_VERSION := 27 + ifeq ($(BASE_OS_VERSION), ) + BASE_OS_VERSION := $(DEFAULT_OS_VERSION) endif - OEL_URL := https://dl.fedoraproject.org/pub/$(FEDORA_TYPE)/releases/27/Everything/$(ARCH)/os/Packages/ - LINUX_VERSION := Fedora 27 + ifeq ($(filter x86_64 armhfp, $(ARCH)), ) + FEDORA_TYPE := fedora-secondary + else + FEDORA_TYPE := fedora/linux + endif + ARCHIVED := $(shell [ $(BASE_OS_VERSION) -lt $(DEFAULT_OS_VERSION) ] && echo true) + ifeq ($(ARCHIVED),true) + BASE_URL := https://archives.fedoraproject.org/pub/archive/$(FEDORA_TYPE)/releases/$(BASE_OS_VERSION)/Everything/$(ARCH)/os/Packages/ + else + BASE_URL := https://dl.fedoraproject.org/pub/$(FEDORA_TYPE)/releases/$(BASE_OS_VERSION)/Everything/$(ARCH)/os/Packages/ + endif + LINUX_VERSION := Fedora_$(BASE_OS_VERSION) else $(error Unknown base OS $(BASE_OS)) endif @@ -137,13 +146,11 @@ endif # Define directories -RESULT := $(OUTPUT_ROOT)/result BUILDDIR := $(OUTPUT_ROOT)/$(HOST)/$(TARGET) -PREFIX := $(RESULT)/$(HOST) TARGETDIR := $(PREFIX)/$(TARGET) SYSROOT := $(TARGETDIR)/sysroot DOWNLOAD := $(OUTPUT_ROOT)/download -DOWNLOAD_RPMS := $(DOWNLOAD)/rpms +DOWNLOAD_RPMS := $(DOWNLOAD)/rpms/$(TARGET)-$(LINUX_VERSION) SRCDIR := $(OUTPUT_ROOT)/src # Marker file for unpacking rpms @@ -159,7 +166,7 @@ # Only run this if rpm dir is empty. ifeq ($(wildcard $(DOWNLOAD_RPMS)/*.rpm), ) cd $(DOWNLOAD_RPMS) && \ - wget -r -np -nd $(patsubst %, -A "*%*.rpm", $(RPM_LIST)) $(OEL_URL) + wget -r -np -nd $(patsubst %, -A "*%*.rpm", $(RPM_LIST)) $(BASE_URL) endif ########################################################################################## @@ -190,8 +197,8 @@ ########################################################################################## # Unpack RPMS +RPM_ARCHS := $(ARCH) noarch ifeq ($(ARCH),x86_64) - RPM_ARCHS := x86_64 noarch ifeq ($(BUILD),$(HOST)) ifeq ($(TARGET),$(HOST)) # When building the native compiler for x86_64, enable mixed mode. @@ -199,11 +206,9 @@ endif endif else ifeq ($(ARCH),i686) - RPM_ARCHS := i386 i686 noarch + RPM_ARCHS += i386 else ifeq ($(ARCH), armhfp) - RPM_ARCHS := $(ARCH) armv7hl noarch -else - RPM_ARCHS := $(ARCH) noarch + RPM_ARCHS += armv7hl endif RPM_FILE_LIST := $(sort $(foreach a, $(RPM_ARCHS), \ @@ -277,7 +282,7 @@ --host=$(HOST) --build=$(BUILD) \ --prefix=$(PREFIX) -PATHEXT = $(RESULT)/$(BUILD)/bin: +PATHEXT = $(PREFIX)/bin: PATHPRE = PATH=$(PATHEXT)$(PATH) NUM_CORES := $(shell cat /proc/cpuinfo | grep -c processor) @@ -427,6 +432,11 @@ $(BUILDDIR)/$(gcc_ver)/Makefile : CONFIG += --with-float=hard endif +ifneq ($(filter ppc64 ppc64le s390x, $(ARCH)), ) + # We only support 64-bit on these platforms anyway + CONFIG += --disable-multilib +endif + # Want: # c,c++ # shared libs @@ -552,7 +562,7 @@ ########################################################################################## -$(PREFIX)/devkit.info: FRC +$(PREFIX)/devkit.info: @echo 'Creating devkit.info in the root of the kit' rm -f $@ touch $@ @@ -611,7 +621,4 @@ # this is only built for host. so separate. ccache : $(ccache) -# Force target -FRC: - .PHONY : gcc all binutils bfdlib link_libs rpms libs sysroot
diff --git a/make/devkit/createWindowsDevkit2017.sh b/make/devkit/createWindowsDevkit2017.sh index 4f208da..0dda08d 100644 --- a/make/devkit/createWindowsDevkit2017.sh +++ b/make/devkit/createWindowsDevkit2017.sh
@@ -32,7 +32,6 @@ VS_VERSION_NUM_NODOT="150" VS_DLL_VERSION="140" SDK_VERSION="10" -SDK_FULL_VERSION="10.0.16299.0" MSVC_DIR="Microsoft.VC141.CRT" SCRIPT_DIR="$(cd "$(dirname $0)" > /dev/null && pwd)" @@ -120,6 +119,9 @@ SDK_INSTALL_DIR="$(cygpath "$PROGRAMFILES_X86/Windows Kits/$SDK_VERSION")" echo "SDK_INSTALL_DIR: $SDK_INSTALL_DIR" +SDK_FULL_VERSION="$(ls "$SDK_INSTALL_DIR/bin" | sort -r -n | head -n1)" +echo "Found SDK version: $SDK_FULL_VERSION" + if [ ! -d $DEVKIT_ROOT/$SDK_VERSION ]; then echo "Copying SDK..." mkdir -p $DEVKIT_ROOT/$SDK_VERSION/bin
diff --git a/make/devkit/createWindowsDevkit2019.sh b/make/devkit/createWindowsDevkit2019.sh new file mode 100644 index 0000000..ef37206 --- /dev/null +++ b/make/devkit/createWindowsDevkit2019.sh
@@ -0,0 +1,209 @@ +#!/bin/bash +# +# Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved. +# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. +# +# This code is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 only, as +# published by the Free Software Foundation. Oracle designates this +# particular file as subject to the "Classpath" exception as provided +# by Oracle in the LICENSE file that accompanied this code. +# +# This code is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# version 2 for more details (a copy is included in the LICENSE file that +# accompanied this code). +# +# You should have received a copy of the GNU General Public License version +# 2 along with this work; if not, write to the Free Software Foundation, +# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +# +# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +# or visit www.oracle.com if you need additional information or have any +# questions. +# + +# This script copies parts of a Visual Studio installation into a devkit +# suitable for building OpenJDK and OracleJDK. Needs to run in Cygwin or WSL. +# erik.joelsson@oracle.com + +VS_VERSION="2019" +VS_VERSION_NUM_NODOT="160" +VS_DLL_VERSION="140" +SDK_VERSION="10" +SDK_FULL_VERSION="10.0.17763.0" +MSVC_DIR="Microsoft.VC141.CRT" +MSVC_FULL_VERSION="14.12.27508" +REDIST_FULL_VERSION="14.20.27508" + +SCRIPT_DIR="$(cd "$(dirname $0)" > /dev/null && pwd)" +BUILD_DIR="${SCRIPT_DIR}/../../build/devkit" + +################################################################################ +# Prepare settings + +UNAME_SYSTEM=`uname -s` +UNAME_RELEASE=`uname -r` + +# Detect cygwin or WSL +IS_CYGWIN=`echo $UNAME_SYSTEM | grep -i CYGWIN` +IS_WSL=`echo $UNAME_RELEASE | grep Microsoft` +if test "x$IS_CYGWIN" != "x"; then + BUILD_ENV="cygwin" +elif test "x$IS_WSL" != "x"; then + BUILD_ENV="wsl" +else + echo "Unknown environment; only Cygwin and WSL are supported." + exit 1 +fi + +if test "x$BUILD_ENV" = "xcygwin"; then + WINDOWS_PATH_TO_UNIX_PATH="cygpath -u" +elif test "x$BUILD_ENV" = "xwsl"; then + WINDOWS_PATH_TO_UNIX_PATH="wslpath -u" +fi + +# Work around the insanely named ProgramFiles(x86) env variable +PROGRAMFILES_X86="$($WINDOWS_PATH_TO_UNIX_PATH "$(cmd.exe /c set | sed -n 's/^ProgramFiles(x86)=//p' | tr -d '\r')")" + +# Find Visual Studio installation dir +VSNNNCOMNTOOLS=`cmd.exe /c echo %VS${VS_VERSION_NUM_NODOT}COMNTOOLS% | tr -d '\r'` +if [ -d "$VSNNNCOMNTOOLS" ]; then + VS_INSTALL_DIR="$($WINDOWS_PATH_TO_UNIX_PATH "$VSNNNCOMNTOOLS/../..")" +else + VS_INSTALL_DIR="${PROGRAMFILES_X86}/Microsoft Visual Studio/2019" + VS_INSTALL_DIR="$(ls -d "${VS_INSTALL_DIR}/"{Community,Professional,Enterprise} 2>/dev/null | head -n1)" +fi +echo "VS_INSTALL_DIR: $VS_INSTALL_DIR" + +# Extract semantic version +POTENTIAL_INI_FILES="Common7/IDE/wdexpress.isolation.ini Common7/IDE/devenv.isolation.ini" +for f in $POTENTIAL_INI_FILES; do + if [ -f "$VS_INSTALL_DIR/$f" ]; then + VS_VERSION_SP="$(grep ^SemanticVersion= "$VS_INSTALL_DIR/$f")" + # Remove SemnaticVersion= + VS_VERSION_SP="${VS_VERSION_SP#*=}" + # Remove suffix of too detailed numbering starting with + + VS_VERSION_SP="${VS_VERSION_SP%+*}" + break + fi +done +if [ -z "$VS_VERSION_SP" ]; then + echo "Failed to find SP version" + exit 1 +fi +echo "Found Version SP: $VS_VERSION_SP" + +# Setup output dirs +DEVKIT_ROOT="${BUILD_DIR}/VS${VS_VERSION}-${VS_VERSION_SP}-devkit" +DEVKIT_BUNDLE="${DEVKIT_ROOT}.tar.gz" + +echo "Creating devkit in $DEVKIT_ROOT" + +MSVCR_DLL=${MSVC_DIR}/vcruntime${VS_DLL_VERSION}.dll +MSVCP_DLL=${MSVC_DIR}/msvcp${VS_DLL_VERSION}.dll + +################################################################################ +# Copy Visual Studio files + +TOOLS_VERSION="$(ls "$VS_INSTALL_DIR/VC/Tools/MSVC" | sort -r -n | head -n1)" +echo "Found Tools version: $TOOLS_VERSION" +VC_SUBDIR="VC/Tools/MSVC/$TOOLS_VERSION" +REDIST_VERSION="$(ls "$VS_INSTALL_DIR/VC/Redist/MSVC" | sort -r -n | head -n1)" +echo "Found Redist version: $REDIST_VERSION" +REDIST_SUBDIR="VC/Redist/MSVC/$REDIST_VERSION" +echo "Copying VC..." +rm -rf $DEVKIT_ROOT/VC +mkdir -p $DEVKIT_ROOT/VC/bin +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/bin/Hostx64/x64" $DEVKIT_ROOT/VC/bin/ +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/bin/Hostx86/x86" $DEVKIT_ROOT/VC/bin/ +mkdir -p $DEVKIT_ROOT/VC/lib +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/lib/x64" $DEVKIT_ROOT/VC/lib/ +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/lib/x86" $DEVKIT_ROOT/VC/lib/ +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/include" $DEVKIT_ROOT/VC/ +mkdir -p $DEVKIT_ROOT/VC/atlmfc/lib +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/lib/x64" $DEVKIT_ROOT/VC/atlmfc/lib/ +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/lib/x86" $DEVKIT_ROOT/VC/atlmfc/lib/ +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/include" $DEVKIT_ROOT/VC/atlmfc/ +mkdir -p $DEVKIT_ROOT/VC/Auxiliary +cp -r "$VS_INSTALL_DIR/VC/Auxiliary/Build" $DEVKIT_ROOT/VC/Auxiliary/ +mkdir -p $DEVKIT_ROOT/VC/redist +cp -r "$VS_INSTALL_DIR/$REDIST_SUBDIR/x64" $DEVKIT_ROOT/VC/redist/ +cp -r "$VS_INSTALL_DIR/$REDIST_SUBDIR/x86" $DEVKIT_ROOT/VC/redist/ + +# The redist runtime libs are needed to run the compiler but may not be +# installed on the machine where the devkit will be used. +cp $DEVKIT_ROOT/VC/redist/x86/$MSVCR_DLL $DEVKIT_ROOT/VC/bin/x86 +cp $DEVKIT_ROOT/VC/redist/x86/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/x86 +cp $DEVKIT_ROOT/VC/redist/x64/$MSVCR_DLL $DEVKIT_ROOT/VC/bin/x64 +cp $DEVKIT_ROOT/VC/redist/x64/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/x64 + +################################################################################ +# Copy SDK files + +SDK_INSTALL_DIR="$PROGRAMFILES_X86/Windows Kits/$SDK_VERSION" +echo "SDK_INSTALL_DIR: $SDK_INSTALL_DIR" + +SDK_FULL_VERSION="$(ls "$SDK_INSTALL_DIR/bin" | sort -r -n | head -n1)" +echo "Found SDK version: $SDK_FULL_VERSION" +UCRT_VERSION="$(ls "$SDK_INSTALL_DIR/Redist" | grep $SDK_VERSION | sort -r -n | head -n1)" +echo "Found UCRT version: $UCRT_VERSION" +echo "Copying SDK..." +rm -rf $DEVKIT_ROOT/$SDK_VERSION +mkdir -p $DEVKIT_ROOT/$SDK_VERSION/bin +cp -r "$SDK_INSTALL_DIR/bin/$SDK_FULL_VERSION/x64" $DEVKIT_ROOT/$SDK_VERSION/bin/ +cp -r "$SDK_INSTALL_DIR/bin/$SDK_FULL_VERSION/x86" $DEVKIT_ROOT/$SDK_VERSION/bin/ +mkdir -p $DEVKIT_ROOT/$SDK_VERSION/lib +cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/um/x64" $DEVKIT_ROOT/$SDK_VERSION/lib/ +cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/um/x86" $DEVKIT_ROOT/$SDK_VERSION/lib/ +cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/ucrt/x64" $DEVKIT_ROOT/$SDK_VERSION/lib/ +cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/ucrt/x86" $DEVKIT_ROOT/$SDK_VERSION/lib/ +mkdir -p $DEVKIT_ROOT/$SDK_VERSION/Redist +cp -r "$SDK_INSTALL_DIR/Redist/$UCRT_VERSION/ucrt" $DEVKIT_ROOT/$SDK_VERSION/Redist/ +mkdir -p $DEVKIT_ROOT/$SDK_VERSION/include +cp -r "$SDK_INSTALL_DIR/include/$SDK_FULL_VERSION/"* $DEVKIT_ROOT/$SDK_VERSION/include/ + +################################################################################ +# Generate devkit.info + +echo-info() { + echo "$1" >> $DEVKIT_ROOT/devkit.info +} + +echo "Generating devkit.info..." +rm -f $DEVKIT_ROOT/devkit.info +echo-info "# This file describes to configure how to interpret the contents of this devkit" +echo-info "DEVKIT_NAME=\"Microsoft Visual Studio $VS_VERSION $VS_VERSION_SP (devkit)\"" +echo-info "DEVKIT_VS_VERSION=\"$VS_VERSION\"" +echo-info "" +echo-info "DEVKIT_TOOLCHAIN_PATH_x86=\"\$DEVKIT_ROOT/VC/bin/x86:\$DEVKIT_ROOT/$SDK_VERSION/bin/x86\"" +echo-info "DEVKIT_VS_INCLUDE_x86=\"\$DEVKIT_ROOT/VC/include;\$DEVKIT_ROOT/VC/atlmfc/include;\$DEVKIT_ROOT/$SDK_VERSION/include/shared;\$DEVKIT_ROOT/$SDK_VERSION/include/ucrt;\$DEVKIT_ROOT/$SDK_VERSION/include/um;\$DEVKIT_ROOT/$SDK_VERSION/include/winrt\"" +echo-info "DEVKIT_VS_LIB_x86=\"\$DEVKIT_ROOT/VC/lib/x86;\$DEVKIT_ROOT/VC/atlmfc/lib/x86;\$DEVKIT_ROOT/$SDK_VERSION/lib/x86\"" +echo-info "DEVKIT_MSVCR_DLL_x86=\"\$DEVKIT_ROOT/VC/redist/x86/$MSVCR_DLL\"" +echo-info "DEVKIT_MSVCP_DLL_x86=\"\$DEVKIT_ROOT/VC/redist/x86/$MSVCP_DLL\"" +echo-info "DEVKIT_UCRT_DLL_DIR_x86=\"\$DEVKIT_ROOT/10/Redist/ucrt/DLLs/x86\"" +echo-info "" +echo-info "DEVKIT_TOOLCHAIN_PATH_x86_64=\"\$DEVKIT_ROOT/VC/bin/x64:\$DEVKIT_ROOT/$SDK_VERSION/bin/x64:\$DEVKIT_ROOT/$SDK_VERSION/bin/x86\"" +echo-info "DEVKIT_VS_INCLUDE_x86_64=\"\$DEVKIT_ROOT/VC/include;\$DEVKIT_ROOT/VC/atlmfc/include;\$DEVKIT_ROOT/$SDK_VERSION/include/shared;\$DEVKIT_ROOT/$SDK_VERSION/include/ucrt;\$DEVKIT_ROOT/$SDK_VERSION/include/um;\$DEVKIT_ROOT/$SDK_VERSION/include/winrt\"" +echo-info "DEVKIT_VS_LIB_x86_64=\"\$DEVKIT_ROOT/VC/lib/x64;\$DEVKIT_ROOT/VC/atlmfc/lib/x64;\$DEVKIT_ROOT/$SDK_VERSION/lib/x64\"" +echo-info "DEVKIT_MSVCR_DLL_x86_64=\"\$DEVKIT_ROOT/VC/redist/x64/$MSVCR_DLL\"" +echo-info "DEVKIT_MSVCP_DLL_x86_64=\"\$DEVKIT_ROOT/VC/redist/x64/$MSVCP_DLL\"" +echo-info "DEVKIT_UCRT_DLL_DIR_x86_64=\"\$DEVKIT_ROOT/10/Redist/ucrt/DLLs/x64\"" +echo-info "" +echo-info "DEVKIT_TOOLS_VERSION=\"$TOOLS_VERSION\"" +echo-info "DEVKIT_REDIST_VERSION=\"$REDIST_VERSION\"" +echo-info "DEVKIT_SDK_VERSION=\"$SDK_FULL_VERSION\"" +echo-info "DEVKIT_UCRT_VERSION=\"$UCRT_VERSION\"" + +################################################################################ +# Copy this script + +echo "Copying this script..." +cp $0 $DEVKIT_ROOT/ + +################################################################################ +# Create bundle + +echo "Creating bundle: $DEVKIT_BUNDLE" +(cd "$DEVKIT_ROOT" && tar zcf "$DEVKIT_BUNDLE" .)
diff --git a/make/gendata/Gendata-java.base.gmk b/make/gendata/Gendata-java.base.gmk index f3e4fde..3bead43 100644 --- a/make/gendata/Gendata-java.base.gmk +++ b/make/gendata/Gendata-java.base.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -63,6 +63,20 @@ ################################################################################ +GENDATA_CACERTS_SRC := $(TOPDIR)/make/data/cacerts/ +GENDATA_CACERTS := $(SUPPORT_OUTPUTDIR)/modules_libs/java.base/security/cacerts + +$(GENDATA_CACERTS): $(BUILD_TOOLS_JDK) $(wildcard $(GENDATA_CACERTS_SRC)/*) + $(call LogInfo, Generating cacerts) + $(call MakeTargetDir) + $(TOOL_GENERATECACERTS) $(GENDATA_CACERTS_SRC) $@ + +ifeq ($(CACERTS_FILE), ) + TARGETS += $(GENDATA_CACERTS) +endif + +################################################################################ + GENDATA_JAVA_SECURITY_SRC := $(TOPDIR)/src/java.base/share/conf/security/java.security GENDATA_JAVA_SECURITY := $(SUPPORT_OUTPUTDIR)/modules_conf/java.base/security/java.security @@ -74,9 +88,9 @@ # RESTRICTED_PKGS_SRC is optionally set in custom extension for this makefile -$(GENDATA_JAVA_SECURITY): $(BUILD_TOOLS) $(GENDATA_JAVA_SECURITY_SRC) $(RESTRICTED_PKGS_SRC) +$(GENDATA_JAVA_SECURITY): $(BUILD_TOOLS_JDK) $(GENDATA_JAVA_SECURITY_SRC) $(RESTRICTED_PKGS_SRC) $(call LogInfo, Generating java.security) - $(call MakeDir, $(@D)) + $(call MakeTargetDir) $(TOOL_MAKEJAVASECURITY) $(GENDATA_JAVA_SECURITY_SRC) $@ $(OPENJDK_TARGET_OS) \ $(OPENJDK_TARGET_CPU_ARCH) $(CRYPTO.POLICY) $(RESTRICTED_PKGS_SRC)
diff --git a/make/gendata/GendataBlacklistedCerts.gmk b/make/gendata/GendataBlacklistedCerts.gmk index 9eb183a..a35a293 100644 --- a/make/gendata/GendataBlacklistedCerts.gmk +++ b/make/gendata/GendataBlacklistedCerts.gmk
@@ -28,7 +28,7 @@ GENDATA_BLACKLISTED_CERTS_SRC += $(TOPDIR)/make/data/blacklistedcertsconverter/blacklisted.certs.pem GENDATA_BLACKLISTED_CERTS := $(SUPPORT_OUTPUTDIR)/modules_libs/$(MODULE)/security/blacklisted.certs -$(GENDATA_BLACKLISTED_CERTS): $(BUILD_TOOLS) $(GENDATA_BLACKLISTED_CERTS_SRC) +$(GENDATA_BLACKLISTED_CERTS): $(BUILD_TOOLS_JDK) $(GENDATA_BLACKLISTED_CERTS_SRC) $(call LogInfo, Generating blacklisted certs) $(call MakeDir, $(@D)) ($(CAT) $(GENDATA_BLACKLISTED_CERTS_SRC) | $(TOOL_BLACKLISTED_CERTS) > $@) || exit 1
diff --git a/make/gendata/GendataBreakIterator.gmk b/make/gendata/GendataBreakIterator.gmk index 5cd1836..55b8100 100644 --- a/make/gendata/GendataBreakIterator.gmk +++ b/make/gendata/GendataBreakIterator.gmk
@@ -84,7 +84,7 @@ $(BIFILES): $(BASE_DATA_PKG_DIR)/_the.bifiles $(BASE_DATA_PKG_DIR)/_the.bifiles: JAVA_FLAGS += $(BREAK_ITERATOR_BOOTCLASSPATH) -$(BASE_DATA_PKG_DIR)/_the.bifiles: $(BUILD_TOOLS) $(UNICODEDATA) \ +$(BASE_DATA_PKG_DIR)/_the.bifiles: $(BUILD_TOOLS_JDK) $(UNICODEDATA) \ $(BUILD_BREAKITERATOR_BASE) $(BUILD_BREAKITERATOR_LD) $(call LogInfo, Generating BreakIteratorData) $(call MakeDir, $(@D)) @@ -96,7 +96,7 @@ $(BIFILES_TH): $(LD_DATA_PKG_DIR)/_the.bifiles_th $(LD_DATA_PKG_DIR)/_the.bifiles_th: JAVA_FLAGS += $(BREAK_ITERATOR_BOOTCLASSPATH) -$(LD_DATA_PKG_DIR)/_the.bifiles_th: $(BUILD_TOOLS) $(UNICODEDATA) \ +$(LD_DATA_PKG_DIR)/_the.bifiles_th: $(BUILD_TOOLS_JDK) $(UNICODEDATA) \ $(BUILD_BREAKITERATOR_BASE) $(BUILD_BREAKITERATOR_LD) $(call LogInfo, Generating BreakIteratorData_th) $(RM) $(BIFILES_TH)
diff --git a/make/gendata/GendataPublicSuffixList.gmk b/make/gendata/GendataPublicSuffixList.gmk index a5bda54..9cf90f4 100644 --- a/make/gendata/GendataPublicSuffixList.gmk +++ b/make/gendata/GendataPublicSuffixList.gmk
@@ -28,7 +28,7 @@ GENDATA_PUBLICSUFFIXLIST_SRC += $(TOPDIR)/make/data/publicsuffixlist/public_suffix_list.dat GENDATA_PUBLICSUFFIXLIST := $(SUPPORT_OUTPUTDIR)/modules_libs/$(MODULE)/security/public_suffix_list.dat -$(GENDATA_PUBLICSUFFIXLIST): $(GENDATA_PUBLICSUFFIXLIST_SRC) $(BUILD_TOOLS) +$(GENDATA_PUBLICSUFFIXLIST): $(GENDATA_PUBLICSUFFIXLIST_SRC) $(BUILD_TOOLS_JDK) $(call LogInfo, Generating public suffix list) $(call MakeDir, $(@D)) $(RM) $@
diff --git a/make/gendata/GendataTZDB.gmk b/make/gendata/GendataTZDB.gmk index e9be176..5186e15 100644 --- a/make/gendata/GendataTZDB.gmk +++ b/make/gendata/GendataTZDB.gmk
@@ -29,7 +29,7 @@ # Time zone data file creation # TZDATA_DIR := $(TOPDIR)/make/data/tzdata -TZDATA_TZFILE := africa antarctica asia australasia europe northamerica pacificnew southamerica backward etcetera gmt jdk11_backward +TZDATA_TZFILE := africa antarctica asia australasia europe northamerica southamerica backward etcetera gmt jdk11_backward TZDATA_TZFILES := $(addprefix $(TZDATA_DIR)/,$(TZDATA_TZFILE)) GENDATA_TZDB_DAT := $(SUPPORT_OUTPUTDIR)/modules_libs/$(MODULE)/tzdb.dat
diff --git a/make/gensrc/Gensrc-jdk.internal.vm.compiler.gmk b/make/gensrc/Gensrc-jdk.internal.vm.compiler.gmk index c88862e..4f9566a 100644 --- a/make/gensrc/Gensrc-jdk.internal.vm.compiler.gmk +++ b/make/gensrc/Gensrc-jdk.internal.vm.compiler.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -65,9 +65,9 @@ PROC_SRC_DIRS := $(patsubst %, $(SRC_DIR)/%/src, $(PROC_SRC_SUBDIRS)) -PROC_SRCS := $(filter %.java, $(call CacheFind, $(PROC_SRC_DIRS))) +PROC_SRCS := $(filter %.java, $(call FindFiles, $(PROC_SRC_DIRS))) -ALL_SRC_DIRS := $(wildcard $(SRC_DIR)/*/src) +ALL_SRC_DIRS := $(SRC_DIR) $(wildcard $(SRC_DIR)/*/src) SOURCEPATH := $(call PathList, $(ALL_SRC_DIRS)) PROCESSOR_JARS := \ @@ -81,23 +81,23 @@ ADD_EXPORTS := \ --add-modules jdk.internal.vm.ci \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.aarch64=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.amd64=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.code=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.code.site=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.code.stack=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.common=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.aarch64=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.amd64=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.events=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.sparc=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspotvmconfig=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.inittimer=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.meta=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.runtime=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.services=ALL-UNNAMED \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.sparc=ALL-UNNAMED \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.aarch64=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.amd64=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.code=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.code.site=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.code.stack=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.common=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.aarch64=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.amd64=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.events=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.sparc=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspotvmconfig=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.inittimer=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.meta=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.runtime=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.services=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.sparc=jdk.internal.vm.compiler \ # $(GENSRC_DIR)/_gensrc_proc_done: $(PROC_SRCS) $(PROCESSOR_JARS) @@ -121,6 +121,7 @@ ################################################################################ $(GENSRC_DIR)/module-info.java.extra: $(GENSRC_DIR)/_gensrc_proc_done + $(ECHO) "" > $@; ($(CD) $(GENSRC_DIR)/META-INF/providers && \ p=""; \ for i in $$($(LS) | $(SORT)); do \
diff --git a/make/gensrc/Gensrc-jdk.internal.vm.compiler.management.gmk b/make/gensrc/Gensrc-jdk.internal.vm.compiler.management.gmk new file mode 100644 index 0000000..d9ea39f --- /dev/null +++ b/make/gensrc/Gensrc-jdk.internal.vm.compiler.management.gmk
@@ -0,0 +1,101 @@ +# +# Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved. +# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. +# +# This code is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 only, as +# published by the Free Software Foundation. Oracle designates this +# particular file as subject to the "Classpath" exception as provided +# by Oracle in the LICENSE file that accompanied this code. +# +# This code is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# version 2 for more details (a copy is included in the LICENSE file that +# accompanied this code). +# +# You should have received a copy of the GNU General Public License version +# 2 along with this work; if not, write to the Free Software Foundation, +# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +# +# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +# or visit www.oracle.com if you need additional information or have any +# questions. +# + +default: all + +include $(SPEC) +include MakeBase.gmk + +GENSRC_DIR := $(SUPPORT_OUTPUTDIR)/gensrc/$(MODULE) +SRC_DIR := $(TOPDIR)/src/$(MODULE)/share/classes + +################################################################################ + +PROC_SRC_SUBDIRS := \ + org.graalvm.compiler.hotspot.management \ + # + +PROC_SRC_DIRS := $(patsubst %, $(SRC_DIR)/%/src, $(PROC_SRC_SUBDIRS)) + +PROC_SRCS := $(filter %.java, $(call FindFiles, $(PROC_SRC_DIRS))) + +ALL_SRC_DIRS := $(SRC_DIR) $(wildcard $(SRC_DIR)/*/src) +SOURCEPATH := $(call PathList, $(ALL_SRC_DIRS)) + +PROCESSOR_JARS := \ + $(BUILDTOOLS_OUTPUTDIR)/jdk.vm.compiler.serviceprovider.processor.jar \ + # +PROCESSOR_PATH := $(call PathList, $(PROCESSOR_JARS)) + +$(GENSRC_DIR)/_gensrc_proc_done: $(PROC_SRCS) $(PROCESSOR_JARS) + $(call MakeDir, $(@D)) + $(eval $(call ListPathsSafely,PROC_SRCS,$(@D)/_gensrc_proc_files)) + $(JAVA) $(NEW_JAVAC) \ + -XDignore.symbol.file \ + --upgrade-module-path $(JDK_OUTPUTDIR)/modules --system none \ + -sourcepath $(SOURCEPATH) \ + -implicit:none \ + -proc:only \ + -processorpath $(PROCESSOR_PATH) \ + -d $(GENSRC_DIR) \ + -s $(GENSRC_DIR) \ + @$(@D)/_gensrc_proc_files + $(TOUCH) $@ + +TARGETS += $(GENSRC_DIR)/_gensrc_proc_done + +################################################################################ + +$(GENSRC_DIR)/module-info.java.extra: $(GENSRC_DIR)/_gensrc_proc_done + $(ECHO) "" > $@; + ($(CD) $(GENSRC_DIR)/META-INF/providers && \ + p=""; \ + impl=""; \ + for i in $$($(GREP) '^' * | $(SORT) -t ':' -k 2 | $(SED) 's/:.*//'); do \ + c=$$($(CAT) $$i | $(TR) -d '\n\r' | $(TR) '$$' '.' ); \ + if test x$$p != x$$c; then \ + if test x$$p != x; then \ + $(ECHO) " ;" >> $@; \ + fi; \ + $(ECHO) "provides $$c with" >> $@; \ + p=$$c; \ + impl=""; \ + fi; \ + if test x$$impl != x; then \ + $(ECHO) " , $$i" >> $@; \ + else \ + $(ECHO) " $$i" >> $@; \ + fi; \ + impl=$$i; \ + done); \ + $(ECHO) " ;" >> $@; + +TARGETS += $(GENSRC_DIR)/module-info.java.extra + +################################################################################ + +all: $(TARGETS) + +.PHONY: default all
diff --git a/make/gensrc/GensrcCharacterData.gmk b/make/gensrc/GensrcCharacterData.gmk index 7e88211..647f29f 100644 --- a/make/gensrc/GensrcCharacterData.gmk +++ b/make/gensrc/GensrcCharacterData.gmk
@@ -38,6 +38,7 @@ $$(call LogInfo, Generating $1.java) $$(call MakeDir, $$(@D)) $(TOOL_GENERATECHARACTER) $2 \ + $(if $(call equals, $(ALLOW_ABSOLUTE_PATHS_IN_OUTPUT), true), -d) \ -template $(CHARACTERDATA)/$1.java.template \ -spec $(UNICODEDATA)/UnicodeData.txt \ -specialcasing $(UNICODEDATA)/SpecialCasing.txt \
diff --git a/make/gensrc/GensrcCommonLangtools.gmk b/make/gensrc/GensrcCommonLangtools.gmk index 682808c..0e9a924 100644 --- a/make/gensrc/GensrcCommonLangtools.gmk +++ b/make/gensrc/GensrcCommonLangtools.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2014, 2016, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2014, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -64,7 +64,7 @@ define SetupCompileProperties # Lookup the properties that need to be compiled into resource bundles. PROPSOURCES := $2 \ - $$(shell $(FIND) $(TOPDIR)/src/$(MODULE)/share/classes -name "*.properties") + $$(call FindFiles, $(TOPDIR)/src/$(MODULE)/share/classes, *.properties) # Filter out any excluded translations PROPSOURCES := $$(call FilterExcludedTranslations, $$(PROPSOURCES), .properties)
diff --git a/make/gensrc/GensrcLocaleData.gmk b/make/gensrc/GensrcLocaleData.gmk index 3235136..a68da06 100644 --- a/make/gensrc/GensrcLocaleData.gmk +++ b/make/gensrc/GensrcLocaleData.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -28,16 +28,16 @@ # into LocaleDataMetaInfo.java # First go look for all locale files -LOCALE_FILES := $(shell $(FIND) \ +LOCALE_FILES := $(call FindFiles, \ $(TOPDIR)/src/$(MODULE)/share/classes/sun/text/resources \ - $(TOPDIR)/src/$(MODULE)/share/classes/sun/util/resources \ - -name "FormatData_*.java" -o -name "FormatData_*.properties" -o \ - -name "CollationData_*.java" -o -name "CollationData_*.properties" -o \ - -name "TimeZoneNames_*.java" -o -name "TimeZoneNames_*.properties" -o \ - -name "LocaleNames_*.java" -o -name "LocaleNames_*.properties" -o \ - -name "CurrencyNames_*.java" -o -name "CurrencyNames_*.properties" -o \ - -name "CalendarData_*.java" -o -name "CalendarData_*.properties" -o \ - -name "BreakIteratorInfo_*.java" -o -name "BreakIteratorRules_*.java") + $(TOPDIR)/src/$(MODULE)/share/classes/sun/util/resources, \ + FormatData_*.java FormatData_*.properties \ + CollationData_*.java CollationData_*.properties \ + TimeZoneNames_*.java TimeZoneNames_*.properties \ + LocaleNames_*.java LocaleNames_*.properties \ + CurrencyNames_*.java CurrencyNames_*.properties \ + CalendarData_*.java CalendarData_*.properties \ + BreakIteratorInfo_*.java BreakIteratorRules_*.java) # Then translate the locale files into for example: FormatData_sv LOCALE_RESOURCES := $(sort $(subst .properties,,$(subst .java,,$(notdir $(LOCALE_FILES)))))
diff --git a/make/gensrc/GensrcMisc.gmk b/make/gensrc/GensrcMisc.gmk index a97f5aa..b01dd17 100644 --- a/make/gensrc/GensrcMisc.gmk +++ b/make/gensrc/GensrcMisc.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -27,6 +27,12 @@ # Install the launcher name, release version string, full version # string and the runtime name into the VersionProps.java file. +ifeq ($(COMPANY_NAME), N/A) + VENDOR=Oracle Corporation +else + VENDOR=$(COMPANY_NAME) +endif + $(eval $(call SetupTextFileProcessing, BUILD_VERSION_JAVA, \ SOURCE_FILES := $(TOPDIR)/src/java.base/share/classes/java/lang/VersionProps.java.template, \ OUTPUT_FILE := $(SUPPORT_OUTPUTDIR)/gensrc/java.base/java/lang/VersionProps.java, \ @@ -40,7 +46,11 @@ @@VERSION_BUILD@@ => $(VERSION_BUILD) ; \ @@VERSION_OPT@@ => $(VERSION_OPT) ; \ @@VERSION_DATE@@ => $(VERSION_DATE) ; \ - @@VENDOR_VERSION_STRING@@ => $(VENDOR_VERSION_STRING), \ + @@VENDOR_VERSION_STRING@@ => $(VENDOR_VERSION_STRING) ; \ + @@VENDOR@@ => $(VENDOR) ; \ + @@VENDOR_URL@@ => $(VENDOR_URL) ; \ + @@VENDOR_URL_BUG@@ => $(VENDOR_URL_BUG) ; \ + @@VENDOR_URL_VM_BUG@@ => $(VENDOR_URL_VM_BUG), \ )) GENSRC_JAVA_BASE += $(BUILD_VERSION_JAVA)
diff --git a/make/gensrc/GensrcModuleInfo.gmk b/make/gensrc/GensrcModuleInfo.gmk new file mode 100644 index 0000000..49846b4 --- /dev/null +++ b/make/gensrc/GensrcModuleInfo.gmk
@@ -0,0 +1,104 @@ +# +# Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved. +# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. +# +# This code is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 only, as +# published by the Free Software Foundation. Oracle designates this +# particular file as subject to the "Classpath" exception as provided +# by Oracle in the LICENSE file that accompanied this code. +# +# This code is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# version 2 for more details (a copy is included in the LICENSE file that +# accompanied this code). +# +# You should have received a copy of the GNU General Public License version +# 2 along with this work; if not, write to the Free Software Foundation, +# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +# +# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +# or visit www.oracle.com if you need additional information or have any +# questions. +# + +################################################################################ +# This file makes modifications to module-info.java files based on the build +# configuration. +# +# Depending on build platform, imported modules and optional parts of the build +# being active, some modules need to have extra exports, provides or uses +# declarations added to them. These optional extras are defined in .extra files: +# +# src/<module>/<share,platform>/classes/module-info.java.extra +# +# The contents of the .extra files are simply extra lines that could fit into +# the module-info file. +# +# This makefile is called once for each from-module with the variable +# MODULE naming the from-module. +# +# The modified module-info.java files are put in the gensrc directory where +# they will automatically override the static versions in the src tree. +# +################################################################################ + +default: all + +include $(SPEC) +include MakeBase.gmk +include Modules.gmk + +################################################################################ +# Define this here since jdk/make/Tools.gmk cannot be included from the top +# make directory. Should probably move some tools away from the jdk repo. +TOOL_GENMODULEINFOSOURCE = $(JAVA_SMALL) \ + $(INTERIM_LANGTOOLS_ARGS) \ + -cp "$(BUILDTOOLS_OUTPUTDIR)/jdk_tools_classes" \ + build.tools.module.GenModuleInfoSource + +################################################################################ + +# Name of modification file. +MOD_FILENAME := module-info.java.extra + +# Construct all possible src directories for the module. +MODULE_CLASSES_DIRS := $(call FindModuleSrcDirs, $(MODULE)) + +# Find all the .extra files in the src dirs. +MOD_FILES := $(wildcard $(foreach f, $(MOD_FILENAME), $(addsuffix /$(f), \ + $(MODULE_CLASSES_DIRS)))) + +ifneq ($(MOD_FILES), ) + # Only make this call if modification files are found for this module + ALL_MODULES := $(call FindAllModules) + + $(SUPPORT_OUTPUTDIR)/gensrc/$(MODULE)/module-info.java: \ + $(firstword $(call FindAllModuleInfos, $(MODULE))) \ + $(BUILD_TOOLS_JDK) \ + $(MOD_FILES) \ + $(call DependOnVariable, ALL_MODULES) + $(MKDIR) -p $(@D) + $(RM) $@ $@.tmp + $(TOOL_GENMODULEINFOSOURCE) \ + $(if $(call equals, $(ALLOW_ABSOLUTE_PATHS_IN_OUTPUT), true), -d) \ + -o $@.tmp \ + --source-file $< \ + --modules $(call CommaList, $(ALL_MODULES)) \ + $(MOD_FILES) + $(MV) $@.tmp $@ + + TARGETS += $(SUPPORT_OUTPUTDIR)/gensrc/$(MODULE)/module-info.java + +else + # If no modifications are found for this module, remove any module-info.java + # created by a previous build since that is no longer valid. + ifneq ($(wildcard $(SUPPORT_OUTPUTDIR)/gensrc/$(MODULE)/module-info.java), ) + $(shell $(RM) $(SUPPORT_OUTPUTDIR)/gensrc/$(MODULE)/module-info.java) + endif +endif + +################################################################################ + +all: $(TARGETS)
diff --git a/make/gensrc/GensrcProperties.gmk b/make/gensrc/GensrcProperties.gmk index c8d17a3..33df382 100644 --- a/make/gensrc/GensrcProperties.gmk +++ b/make/gensrc/GensrcProperties.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -68,7 +68,7 @@ endif # Locate all properties files in the given source dirs. - $1_SRC_FILES := $$(filter %.properties, $$(call CacheFind, $$($1_SRC_DIRS))) + $1_SRC_FILES := $$(call FindFiles, $$($1_SRC_DIRS), *.properties) ifneq ($$($1_EXCLUDE), ) $1_SRC_FILES := $$(filter-out $$($1_EXCLUDE), $$($1_SRC_FILES))
diff --git a/make/hotspot/gensrc/GensrcAdlc.gmk b/make/hotspot/gensrc/GensrcAdlc.gmk index 92b030b..6878962 100644 --- a/make/hotspot/gensrc/GensrcAdlc.gmk +++ b/make/hotspot/gensrc/GensrcAdlc.gmk
@@ -62,6 +62,10 @@ ADLC_CFLAGS += -I$(TOPDIR)/src/hotspot/share + ifneq ($(call check-jvm-feature, shenandoahgc), true) + ADLC_CFLAGS += -DINCLUDE_SHENANDOAHGC=0 + endif + $(eval $(call SetupNativeCompilation, BUILD_ADLC, \ NAME := adlc, \ TYPE := EXECUTABLE, \ @@ -136,6 +140,12 @@ $d/os_cpu/$(HOTSPOT_TARGET_OS)_$(HOTSPOT_TARGET_CPU_ARCH)/$(HOTSPOT_TARGET_OS)_$(HOTSPOT_TARGET_CPU_ARCH).ad \ ))) + ifeq ($(call check-jvm-feature, shenandoahgc), true) + AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \ + $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/shenandoah/shenandoah_$(HOTSPOT_TARGET_CPU).ad \ + ))) + endif + SINGLE_AD_SRCFILE := $(ADLC_SUPPORT_DIR)/all-ad-src.ad INSERT_FILENAME_AWK_SCRIPT := \ @@ -191,6 +201,9 @@ $(NAWK) \ 'BEGIN { print "#line 1 \"$*\""; } \ /^#line 999999$$/ {print "#line " (NR+1) " \"$*\""; next} \ + $(if $(call equals, $(ALLOW_ABSOLUTE_PATHS_IN_OUTPUT), false), \ + /^#line .*$$/ {sub("$(WORKSPACE_ROOT)/","")} \ + ) \ {print}' \ < $(ADLC_SUPPORT_DIR)/$* > $@
diff --git a/make/hotspot/gensrc/GensrcDtrace.gmk b/make/hotspot/gensrc/GensrcDtrace.gmk index 3a013c7..9b279e8 100644 --- a/make/hotspot/gensrc/GensrcDtrace.gmk +++ b/make/hotspot/gensrc/GensrcDtrace.gmk
@@ -64,8 +64,9 @@ include lib/JvmFeatures.gmk include lib/JvmFlags.gmk - # We cannot compile until the JVMTI gensrc has finished + # We cannot compile until the JVMTI and JFR gensrc has finished JVMTI_H := $(JVM_VARIANT_OUTPUTDIR)/gensrc/jvmtifiles/jvmti.h + JFR_FILES := $(JVM_VARIANT_OUTPUTDIR)/gensrc/jfrfiles/jfrEventClasses.hpp $(eval $(call SetupNativeCompilation, BUILD_DTRACE_GEN_OFFSETS, \ NAME := dtraceGenOffsets, \ @@ -74,7 +75,7 @@ TOOLCHAIN := $(TOOLCHAIN_BUILD), \ LDFLAGS := -m64, \ CFLAGS := -m64 $(JVM_CFLAGS), \ - EXTRA_DEPS := $(JVMTI_H), \ + EXTRA_DEPS := $(JVMTI_H) $(JFR_FILES), \ OBJECT_DIR := $(JVM_VARIANT_OUTPUTDIR)/tools/dtrace-gen-offsets/objs, \ OUTPUT_DIR := $(JVM_VARIANT_OUTPUTDIR)/tools/dtrace-gen-offsets, \ ))
diff --git a/make/hotspot/lib/CompileGtest.gmk b/make/hotspot/lib/CompileGtest.gmk index e288482..c4c8429 100644 --- a/make/hotspot/lib/CompileGtest.gmk +++ b/make/hotspot/lib/CompileGtest.gmk
@@ -55,6 +55,7 @@ # Disabling undef, switch, format-nonliteral and tautological-undefined-compare # warnings for clang because of test source. +# Solaris: Disable inlining (+d) to workaround Assertion: (../lnk/vardescr.h, line 109) $(eval $(call SetupNativeCompilation, BUILD_GTEST_LIBJVM, \ NAME := jvm, \ TOOLCHAIN := TOOLCHAIN_LINK_CXX, \ @@ -71,13 +72,12 @@ -I$(GTEST_FRAMEWORK_SRC)/include \ $(addprefix -I,$(GTEST_TEST_SRC)), \ CFLAGS_windows := -EHsc, \ - CFLAGS_solaris := -DGTEST_HAS_EXCEPTIONS=0 -library=stlport4, \ + CFLAGS_solaris := -DGTEST_HAS_EXCEPTIONS=0 -library=stlport4 +d, \ CFLAGS_macosx := -DGTEST_OS_MAC=1, \ DISABLED_WARNINGS_gcc := undef, \ DISABLED_WARNINGS_clang := undef switch format-nonliteral \ tautological-undefined-compare $(BUILD_LIBJVM_DISABLED_WARNINGS_clang), \ DISABLED_WARNINGS_solstudio := identexpected, \ - DISABLED_WARNINGS_CXX_microsoft := 4996, \ LDFLAGS := $(JVM_LDFLAGS), \ LDFLAGS_solaris := -library=stlport4 $(call SET_SHARED_LIBRARY_ORIGIN), \ LIBS := $(JVM_LIBS), \
diff --git a/make/hotspot/lib/CompileJvm.gmk b/make/hotspot/lib/CompileJvm.gmk index a4b67f0..5942540 100644 --- a/make/hotspot/lib/CompileJvm.gmk +++ b/make/hotspot/lib/CompileJvm.gmk
@@ -47,6 +47,8 @@ $(EXTRA_LDFLAGS) \ # +JVM_ASFLAGS += $(EXTRA_ASFLAGS) + JVM_LIBS += \ $(JVM_LIBS_FEATURES) \ # @@ -55,7 +57,7 @@ JVM_EXCLUDE_FILES += args.cc JVM_EXCLUDES += adlc -# Needed by vm_version.cpp +# Needed by abstract_vm_version.cpp ifeq ($(OPENJDK_TARGET_CPU), x86_64) OPENJDK_TARGET_CPU_VM_VERSION := amd64 else ifeq ($(OPENJDK_TARGET_CPU), sparcv9) @@ -156,7 +158,7 @@ EXCLUDE_PATTERNS := $(JVM_EXCLUDE_PATTERNS), \ EXTRA_OBJECT_FILES := $(DTRACE_EXTRA_OBJECT_FILES), \ CFLAGS := $(JVM_CFLAGS), \ - vm_version.cpp_CXXFLAGS := $(CFLAGS_VM_VERSION), \ + abstract_vm_version.cpp_CXXFLAGS := $(CFLAGS_VM_VERSION), \ arguments.cpp_CXXFLAGS := $(CFLAGS_VM_VERSION), \ DISABLED_WARNINGS_clang := tautological-compare, \ DISABLED_WARNINGS_solstudio := $(DISABLED_WARNINGS_solstudio), \ @@ -177,22 +179,24 @@ PRECOMPILED_HEADER_EXCLUDE := $(JVM_PRECOMPILED_HEADER_EXCLUDE), \ )) -# Always recompile vm_version.cpp if libjvm needs to be relinked. This ensures +# Always recompile abstract_vm_version.cpp if libjvm needs to be relinked. This ensures # that the internal vm version is updated as it relies on __DATE__ and __TIME__ # macros. -VM_VERSION_OBJ := $(JVM_OUTPUTDIR)/objs/vm_version$(OBJ_SUFFIX) -$(VM_VERSION_OBJ): $(filter-out $(VM_VERSION_OBJ) $(JVM_MAPFILE), \ +ABSTRACT_VM_VERSION_OBJ := $(JVM_OUTPUTDIR)/objs/abstract_vm_version$(OBJ_SUFFIX) +$(ABSTRACT_VM_VERSION_OBJ): $(filter-out $(ABSTRACT_VM_VERSION_OBJ) $(JVM_MAPFILE), \ $(BUILD_LIBJVM_TARGET_DEPS)) -ifeq ($(OPENJDK_TARGET_OS), windows) - # It doesn't matter which jvm.lib file gets exported, but we need - # to pick just one. - ifeq ($(JVM_VARIANT), $(JVM_VARIANT_MAIN)) - $(eval $(call SetupCopyFiles, COPY_JVM_LIB, \ - DEST := $(LIB_OUTPUTDIR), \ - FILES :=$(BUILD_LIBJVM_IMPORT_LIBRARY), \ - )) - TARGETS += $(COPY_JVM_LIB) +ifneq ($(GENERATE_COMPILE_COMMANDS_ONLY), true) + ifeq ($(OPENJDK_TARGET_OS), windows) + # It doesn't matter which jvm.lib file gets exported, but we need + # to pick just one. + ifeq ($(JVM_VARIANT), $(JVM_VARIANT_MAIN)) + $(eval $(call SetupCopyFiles, COPY_JVM_LIB, \ + DEST := $(LIB_OUTPUTDIR), \ + FILES :=$(BUILD_LIBJVM_IMPORT_LIBRARY), \ + )) + TARGETS += $(COPY_JVM_LIB) + endif endif endif @@ -231,44 +235,46 @@ # Search the output for the operator(s) of interest, to see where they are # referenced. -ifneq ($(filter $(TOOLCHAIN_TYPE), gcc clang solstudio), ) +ifneq ($(GENERATE_COMPILE_COMMANDS_ONLY), true) + ifneq ($(filter $(TOOLCHAIN_TYPE), gcc clang solstudio), ) - DEMANGLED_REGEXP := [^:]operator (new|delete) + DEMANGLED_REGEXP := [^:]operator (new|delete) - # Running c++filt to find offending symbols in all files is too expensive, - # especially on Solaris, so use mangled names when looking for symbols. - # Save the demangling for when something is actually found. - ifeq ($(TOOLCHAIN_TYPE), solstudio) - MANGLED_SYMS := \ - __1c2n6FL_pv_ \ - __1c2N6FL_pv_ \ - __1c2k6Fpv_v_ \ - __1c2K6Fpv_v_ \ - # - UNDEF_PATTERN := UNDEF - else - MANGLED_SYMS := \ - _ZdaPv \ - _ZdlPv \ - _Znam \ - _Znwm \ - # - UNDEF_PATTERN := ' U ' + # Running c++filt to find offending symbols in all files is too expensive, + # especially on Solaris, so use mangled names when looking for symbols. + # Save the demangling for when something is actually found. + ifeq ($(TOOLCHAIN_TYPE), solstudio) + MANGLED_SYMS := \ + __1c2n6FL_pv_ \ + __1c2N6FL_pv_ \ + __1c2k6Fpv_v_ \ + __1c2K6Fpv_v_ \ + # + UNDEF_PATTERN := UNDEF + else + MANGLED_SYMS := \ + _ZdaPv \ + _ZdlPv \ + _Znam \ + _Znwm \ + # + UNDEF_PATTERN := ' U ' + endif + + define SetupOperatorNewDeleteCheck + $1.op_check: $1 + if [ -n "`$(NM) $$< | $(GREP) $(addprefix -e , $(MANGLED_SYMS)) \ + | $(GREP) $(UNDEF_PATTERN)`" ]; then \ + $(ECHO) "$$<: Error: Use of global operators new and delete is not allowed in Hotspot:"; \ + $(NM) $$< | $(CXXFILT) | $(EGREP) '$(DEMANGLED_REGEXP)' | $(GREP) $(UNDEF_PATTERN); \ + $(ECHO) "See: $(TOPDIR)/make/hotspot/lib/CompileJvm.gmk"; \ + exit 1; \ + fi + $(TOUCH) $$@ + + TARGETS += $1.op_check + endef + + $(foreach o, $(BUILD_LIBJVM_ALL_OBJS), $(eval $(call SetupOperatorNewDeleteCheck,$o))) endif - - define SetupOperatorNewDeleteCheck - $1.op_check: $1 - if [ -n "`$(NM) $$< | $(GREP) $(addprefix -e , $(MANGLED_SYMS)) \ - | $(GREP) $(UNDEF_PATTERN)`" ]; then \ - $(ECHO) "$$<: Error: Use of global operators new and delete is not allowed in Hotspot:"; \ - $(NM) $$< | $(CXXFILT) | $(EGREP) '$(DEMANGLED_REGEXP)' | $(GREP) $(UNDEF_PATTERN); \ - $(ECHO) "See: $(TOPDIR)/make/hotspot/lib/CompileJvm.gmk"; \ - exit 1; \ - fi - $(TOUCH) $$@ - - TARGETS += $1.op_check - endef - - $(foreach o, $(BUILD_LIBJVM_ALL_OBJS), $(eval $(call SetupOperatorNewDeleteCheck,$o))) endif
diff --git a/make/hotspot/lib/JvmFeatures.gmk b/make/hotspot/lib/JvmFeatures.gmk index d4f0891..7525681 100644 --- a/make/hotspot/lib/JvmFeatures.gmk +++ b/make/hotspot/lib/JvmFeatures.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2013, 2017, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -109,6 +109,7 @@ classListParser.cpp \ classLoaderExt.cpp \ filemap.cpp \ + heapShared.cpp \ metaspaceShared.cpp \ metaspaceShared_$(HOTSPOT_TARGET_CPU).cpp \ metaspaceShared_$(HOTSPOT_TARGET_CPU_ARCH).cpp \ @@ -165,6 +166,11 @@ JVM_EXCLUDE_PATTERNS += gc/z endif +ifneq ($(call check-jvm-feature, shenandoahgc), true) + JVM_CFLAGS_FEATURES += -DINCLUDE_SHENANDOAHGC=0 + JVM_EXCLUDE_PATTERNS += gc/shenandoah +endif + ifneq ($(call check-jvm-feature, jfr), true) JVM_CFLAGS_FEATURES += -DINCLUDE_JFR=0 JVM_EXCLUDE_PATTERNS += jfr
diff --git a/make/hotspot/lib/JvmOverrideFiles.gmk b/make/hotspot/lib/JvmOverrideFiles.gmk index 3e32966..17e73b2 100644 --- a/make/hotspot/lib/JvmOverrideFiles.gmk +++ b/make/hotspot/lib/JvmOverrideFiles.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2013, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -36,6 +36,10 @@ BUILD_LIBJVM_assembler_x86.cpp_CXXFLAGS := -Wno-maybe-uninitialized BUILD_LIBJVM_cardTableBarrierSetAssembler_x86.cpp_CXXFLAGS := -Wno-maybe-uninitialized BUILD_LIBJVM_interp_masm_x86.cpp_CXXFLAGS := -Wno-uninitialized + ifeq ($(DEBUG_LEVEL), release) + # Need extra inlining to collapse all marking code into the hot marking loop + BUILD_LIBJVM_shenandoahConcurrentMark.cpp_CXXFLAGS := --param inline-unit-growth=1000 + endif endif LIBJVM_FDLIBM_COPY_OPT_FLAG := $(CXX_O_FLAG_NONE) @@ -65,7 +69,7 @@ # significantly reduce the GC pause time on 32 bit Linux/Unix platforms by # compiling without the PIC flag (-fPIC on linux). # See 6454213 for more details. - ALL_SRC := $(filter %.cpp, $(call CacheFind, $(TOPDIR)/src/hotspot/share)) + ALL_SRC := $(call FindFiles, $(TOPDIR)/src/hotspot/share, *.cpp) NONPIC_FILTER := $(addsuffix %, $(addprefix $(TOPDIR)/src/hotspot/share/, \ memory oops gc)) # Due to what looks like a bug in the old build implementation of this, add a @@ -132,9 +136,6 @@ # NOTE: The old build tested clang version to make sure this workaround # for the clang bug was still needed. BUILD_LIBJVM_loopTransform.cpp_CXXFLAGS := $(CXX_O_FLAG_NONE) - ifneq ($(DEBUG_LEVEL), slowdebug) - BUILD_LIBJVM_unsafe.cpp_CXXFLAGS := -O1 - endif # The following files are compiled at various optimization # levels due to optimization issues encountered at the @@ -150,7 +151,6 @@ sharedRuntimeTrig.cpp \ sharedRuntimeTrans.cpp \ loopTransform.cpp \ - unsafe.cpp \ jvmciCompilerToVM.cpp \ # endif
diff --git a/make/hotspot/src/native/dtrace/generateJvmOffsets.cpp b/make/hotspot/src/native/dtrace/generateJvmOffsets.cpp index 259b881..cdf66f9 100644 --- a/make/hotspot/src/native/dtrace/generateJvmOffsets.cpp +++ b/make/hotspot/src/native/dtrace/generateJvmOffsets.cpp
@@ -40,6 +40,7 @@ #include <proc_service.h> #include "gc/shared/collectedHeap.hpp" +#include "memory/heap.hpp" #include "runtime/vmStructs.hpp" typedef enum GEN_variant {
diff --git a/make/hotspot/symbols/symbols-linux b/make/hotspot/symbols/symbols-linux index 0efd2db..bbb0d35 100644 --- a/make/hotspot/symbols/symbols-linux +++ b/make/hotspot/symbols/symbols-linux
@@ -22,6 +22,7 @@ # JVM_handle_linux_signal +JVM_IsUseContainerSupport numa_error numa_warn sysThreadAvailableStackWithSlack
diff --git a/make/hotspot/symbols/symbols-unix b/make/hotspot/symbols/symbols-unix index b3d09ba..b101792 100644 --- a/make/hotspot/symbols/symbols-unix +++ b/make/hotspot/symbols/symbols-unix
@@ -136,6 +136,7 @@ JVM_InitProperties JVM_InitStackTraceElement JVM_InitStackTraceElementArray +JVM_InitializeFromArchive JVM_InternString JVM_Interrupt JVM_InvokeMethod
diff --git a/make/hotspot/test/GtestImage.gmk b/make/hotspot/test/GtestImage.gmk index f24b1a7..28a70c8 100644 --- a/make/hotspot/test/GtestImage.gmk +++ b/make/hotspot/test/GtestImage.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2016, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -45,12 +45,14 @@ FLATTEN := true, \ )) \ $(eval TARGETS += $$(COPY_GTEST_MSVCR_$v)) \ - $(eval $(call SetupCopyFiles, COPY_GTEST_PDB_$v, \ - SRC := $(HOTSPOT_OUTPUTDIR)/variant-$v/libjvm/gtest, \ - DEST := $(TEST_IMAGE_DIR)/hotspot/gtest/$v, \ - FILES := jvm.pdb gtestLauncher.pdb, \ - )) \ - $(eval TARGETS += $$(COPY_GTEST_PDB_$v)) \ + $(if $(call equals, $(COPY_DEBUG_SYMBOLS), true), \ + $(eval $(call SetupCopyFiles, COPY_GTEST_PDB_$v, \ + SRC := $(HOTSPOT_OUTPUTDIR)/variant-$v/libjvm/gtest, \ + DEST := $(TEST_IMAGE_DIR)/hotspot/gtest/$v, \ + FILES := jvm.pdb gtestLauncher.pdb, \ + )) \ + $(eval TARGETS += $$(COPY_GTEST_PDB_$v)) \ + ) \ ) endif
diff --git a/make/jdk/src/classes/build/tools/blacklistedcertsconverter/BlacklistedCertsConverter.java b/make/jdk/src/classes/build/tools/blacklistedcertsconverter/BlacklistedCertsConverter.java index 54c60eb..653a1db 100644 --- a/make/jdk/src/classes/build/tools/blacklistedcertsconverter/BlacklistedCertsConverter.java +++ b/make/jdk/src/classes/build/tools/blacklistedcertsconverter/BlacklistedCertsConverter.java
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2013, 2020, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -25,14 +25,24 @@ package build.tools.blacklistedcertsconverter; +import java.io.IOException; +import java.math.BigInteger; import java.security.MessageDigest; +import java.security.PublicKey; import java.security.cert.Certificate; import java.security.cert.CertificateFactory; import java.security.cert.X509Certificate; +import java.security.interfaces.ECPublicKey; +import java.util.ArrayList; +import java.util.Arrays; import java.util.Collection; +import java.util.List; import java.util.Set; import java.util.TreeSet; +import sun.security.util.DerInputStream; +import sun.security.util.DerOutputStream; +import sun.security.util.DerValue; /** * Converts blacklisted.certs.pem from System.in to blacklisted.certs in @@ -75,8 +85,8 @@ // Output sorted so that it's easy to locate an entry. Set<String> fingerprints = new TreeSet<>(); for (Certificate cert: certs) { - fingerprints.add( - getCertificateFingerPrint(mdAlg, (X509Certificate)cert)); + fingerprints.addAll( + getCertificateFingerPrints(mdAlg, (X509Certificate)cert)); } for (String s: fingerprints) { @@ -97,17 +107,90 @@ } /** - * Gets the requested finger print of the certificate. + * Computes the possible fingerprints of the certificate. */ - private static String getCertificateFingerPrint( + private static List<String> getCertificateFingerPrints( String mdAlg, X509Certificate cert) throws Exception { - byte[] encCertInfo = cert.getEncoded(); - MessageDigest md = MessageDigest.getInstance(mdAlg); - byte[] digest = md.digest(encCertInfo); - StringBuffer buf = new StringBuffer(); - for (int i = 0; i < digest.length; i++) { - byte2hex(digest[i], buf); + List<String> fingerprints = new ArrayList<>(); + for (byte[] encoding : altEncodings(cert)) { + MessageDigest md = MessageDigest.getInstance(mdAlg); + byte[] digest = md.digest(encoding); + StringBuffer buf = new StringBuffer(); + for (int i = 0; i < digest.length; i++) { + byte2hex(digest[i], buf); + } + fingerprints.add(buf.toString()); } - return buf.toString(); + return fingerprints; + } + + private static List<byte[]> altEncodings(X509Certificate c) + throws Exception { + List<byte[]> result = new ArrayList<>(); + + DerValue d = new DerValue(c.getEncoded()); + DerValue[] seq = new DerValue[3]; + // tbsCertificate + seq[0] = d.data.getDerValue(); + // signatureAlgorithm + seq[1] = d.data.getDerValue(); + // signature + seq[2] = d.data.getDerValue(); + + List<DerValue> algIds = Arrays.asList(seq[1], altAlgId(seq[1])); + + List<DerValue> sigs; + PublicKey p = c.getPublicKey(); + if (p instanceof ECPublicKey) { + ECPublicKey ep = (ECPublicKey) p; + BigInteger mod = ep.getParams().getOrder(); + sigs = Arrays.asList(seq[2], altSig(mod, seq[2])); + } else { + sigs = Arrays.asList(seq[2]); + } + + for (DerValue algId : algIds) { + for (DerValue sig : sigs) { + DerOutputStream tmp = new DerOutputStream(); + tmp.putDerValue(seq[0]); + tmp.putDerValue(algId); + tmp.putDerValue(sig); + DerOutputStream tmp2 = new DerOutputStream(); + tmp2.write(DerValue.tag_Sequence, tmp); + result.add(tmp2.toByteArray()); + } + } + return result; + } + + private static DerValue altSig(BigInteger mod, DerValue sig) + throws IOException { + byte[] sigBits = sig.getBitString(); + DerInputStream in = + new DerInputStream(sigBits, 0, sigBits.length, false); + DerValue[] values = in.getSequence(2); + BigInteger r = values[0].getBigInteger(); + BigInteger s = values[1].getBigInteger(); + BigInteger s2 = s.negate().mod(mod); + DerOutputStream out = new DerOutputStream(); + out.putInteger(r); + out.putInteger(s2); + DerOutputStream tmp = new DerOutputStream(); + tmp.putBitString(new DerValue(DerValue.tag_Sequence, + out.toByteArray()).toByteArray()); + return new DerValue(tmp.toByteArray()); + } + + private static DerValue altAlgId(DerValue algId) throws IOException { + DerInputStream in = algId.toDerInputStream(); + DerOutputStream bytes = new DerOutputStream(); + bytes.putOID(in.getOID()); + // encode parameters as NULL if not present or omit if NULL + if (in.available() == 0) { + bytes.putNull(); + } + DerOutputStream tmp = new DerOutputStream(); + tmp.write(DerValue.tag_Sequence, bytes); + return new DerValue(tmp.toByteArray()); } }
diff --git a/make/jdk/src/classes/build/tools/charsetmapping/SBCS.java b/make/jdk/src/classes/build/tools/charsetmapping/SBCS.java index 79dc16d..296a815 100644 --- a/make/jdk/src/classes/build/tools/charsetmapping/SBCS.java +++ b/make/jdk/src/classes/build/tools/charsetmapping/SBCS.java
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2008, 2015, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -46,6 +46,7 @@ String hisName = cs.hisName; String pkgName = cs.pkgName; boolean isASCII = cs.isASCII; + boolean isLatin1Decodable = true; StringBuilder b2cSB = new StringBuilder(); StringBuilder b2cNRSB = new StringBuilder(); @@ -69,6 +70,9 @@ c2bOff += 0x100; c2bIndex[e.cp>>8] = 1; } + if (e.cp > 0xFF) { + isLatin1Decodable = false; + } } Formatter fm = new Formatter(b2cSB); @@ -178,6 +182,9 @@ if (line.indexOf("$ASCIICOMPATIBLE$") != -1) { line = line.replace("$ASCIICOMPATIBLE$", isASCII ? "true" : "false"); } + if (line.indexOf("$LATIN1DECODABLE$") != -1) { + line = line.replace("$LATIN1DECODABLE$", isLatin1Decodable ? "true" : "false"); + } if (line.indexOf("$B2CTABLE$") != -1) { line = line.replace("$B2CTABLE$", b2c); }
diff --git a/make/jdk/src/classes/build/tools/classlist/HelloClasslist.java b/make/jdk/src/classes/build/tools/classlist/HelloClasslist.java index e32b8d7..b961320 100644 --- a/make/jdk/src/classes/build/tools/classlist/HelloClasslist.java +++ b/make/jdk/src/classes/build/tools/classlist/HelloClasslist.java
@@ -32,6 +32,7 @@ package build.tools.classlist; import java.net.InetAddress; +import java.nio.file.FileSystems; import java.time.LocalDateTime; import java.time.ZoneId; import java.time.format.DateTimeFormatter; @@ -56,6 +57,8 @@ public static void main(String ... args) { + FileSystems.getDefault(); + List<String> strings = Arrays.asList("Hello", "World!", "From: ", InetAddress.getLoopbackAddress().toString());
diff --git a/make/jdk/src/classes/build/tools/cldrconverter/Bundle.java b/make/jdk/src/classes/build/tools/cldrconverter/Bundle.java index f608bc9..19712eb 100644 --- a/make/jdk/src/classes/build/tools/cldrconverter/Bundle.java +++ b/make/jdk/src/classes/build/tools/cldrconverter/Bundle.java
@@ -297,7 +297,6 @@ } // First, weed out any empty timezone or metazone names from myMap. - // Fill in any missing abbreviations if locale is "en". for (Iterator<String> it = myMap.keySet().iterator(); it.hasNext();) { String key = it.next(); if (key.startsWith(CLDRConverter.TIMEZONE_ID_PREFIX) @@ -310,10 +309,6 @@ it.remove(); continue; } - - if (id.equals("en")) { - fillInJREs(key, nameMap); - } } } for (Iterator<String> it = myMap.keySet().iterator(); it.hasNext();) { @@ -626,42 +621,6 @@ return null; } - static List<Object[]> jreTimeZoneNames = Arrays.asList(TimeZoneNames.getContents()); - private void fillInJREs(String key, Map<String, String> map) { - String tzid = null; - - if (key.startsWith(CLDRConverter.METAZONE_ID_PREFIX)) { - // Look for tzid - String meta = key.substring(CLDRConverter.METAZONE_ID_PREFIX.length()); - if (meta.equals("GMT")) { - tzid = meta; - } else { - for (String tz : CLDRConverter.handlerMetaZones.keySet()) { - if (CLDRConverter.handlerMetaZones.get(tz).equals(meta)) { - tzid = tz; - break; - } - } - } - } else { - tzid = key.substring(CLDRConverter.TIMEZONE_ID_PREFIX.length()); - } - - if (tzid != null) { - for (Object[] jreZone : jreTimeZoneNames) { - if (jreZone[0].equals(tzid)) { - for (int i = 0; i < ZONE_NAME_KEYS.length; i++) { - if (map.get(ZONE_NAME_KEYS[i]) == null) { - String[] jreNames = (String[])jreZone[1]; - map.put(ZONE_NAME_KEYS[i], jreNames[i]); - } - } - break; - } - } - } - } - private void convert(CalendarType calendarType, char cldrLetter, int count, StringBuilder sb) { switch (cldrLetter) { case 'G':
diff --git a/make/jdk/src/classes/build/tools/cldrconverter/CLDRConverter.java b/make/jdk/src/classes/build/tools/cldrconverter/CLDRConverter.java index bc40688..034b8ad 100644 --- a/make/jdk/src/classes/build/tools/cldrconverter/CLDRConverter.java +++ b/make/jdk/src/classes/build/tools/cldrconverter/CLDRConverter.java
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2012, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2020, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -25,7 +25,6 @@ package build.tools.cldrconverter; -import static build.tools.cldrconverter.Bundle.jreTimeZoneNames; import build.tools.cldrconverter.BundleGenerator.BundleType; import java.io.File; import java.io.IOException; @@ -87,7 +86,9 @@ static final String ZONE_NAME_PREFIX = "timezone.displayname."; static final String METAZONE_ID_PREFIX = "metazone.id."; static final String PARENT_LOCALE_PREFIX = "parentLocale."; + static final String META_EMPTY_ZONE_NAME = "EMPTY_ZONE"; static final String[] EMPTY_ZONE = {"", "", "", "", "", ""}; + static final String META_ETCUTC_ZONE_NAME = "ETC_UTC"; private static SupplementDataParseHandler handlerSuppl; private static LikelySubtagsParseHandler handlerLikelySubtags; @@ -106,7 +107,7 @@ private static final ResourceBundle.Control defCon = ResourceBundle.Control.getControl(ResourceBundle.Control.FORMAT_DEFAULT); - private static final String[] AVAILABLE_TZIDS = TimeZone.getAvailableIDs(); + private static Set<String> AVAILABLE_TZIDS; private static String zoneNameTempFile; private static String tzDataDir; private static final Map<String, String> canonicalTZMap = new HashMap<>(); @@ -340,17 +341,26 @@ if (sb.indexOf("root") == -1) { sb.append("root"); } - Bundle b = new Bundle(id, sb.toString(), null, null); - // Insert the bundle for root at the top so that it will get - // processed first. - if ("root".equals(id)) { - retList.add(0, b); - } else { - retList.add(b); - } + retList.add(new Bundle(id, sb.toString(), null, null)); } } } + + // Sort the bundles based on id. This will make sure all the parent bundles are + // processed first, e.g., for en_GB bundle, en_001, and "root" comes before + // en_GB. In order for "root" to come at the beginning, "root" is replaced with + // empty string on comparison. + retList.sort((o1, o2) -> { + String id1 = o1.getID(); + String id2 = o2.getID(); + if(id1.equals("root")) { + id1 = ""; + } + if(id2.equals("root")) { + id2 = ""; + } + return id1.compareTo(id2); + }); return retList; } @@ -657,68 +667,21 @@ private static Map<String, Object> extractZoneNames(Map<String, Object> map, String id) { Map<String, Object> names = new HashMap<>(); - // Copy over missing time zone ids from JRE for English locale - if (id.equals("en")) { - Map<String[], String> jreMetaMap = new HashMap<>(); - jreTimeZoneNames.stream().forEach(e -> { - String tzid = (String)e[0]; - String[] data = (String[])e[1]; - - if (map.get(TIMEZONE_ID_PREFIX + tzid) == null && - handlerMetaZones.get(tzid) == null || - handlerMetaZones.get(tzid) != null && - map.get(METAZONE_ID_PREFIX + handlerMetaZones.get(tzid)) == null) { - - // First, check the alias - String canonID = canonicalTZMap.get(tzid); - if (canonID != null && !tzid.equals(canonID)) { - Object value = map.get(TIMEZONE_ID_PREFIX + canonID); - if (value != null) { - names.put(tzid, value); - return; - } else { - String meta = handlerMetaZones.get(canonID); - if (meta != null) { - value = map.get(METAZONE_ID_PREFIX + meta); - if (value != null) { - names.put(tzid, meta); - return; - } - } - } - } - - // Check the CLDR meta key - Optional<Map.Entry<String, String>> cldrMeta = - handlerMetaZones.getData().entrySet().stream() - .filter(me -> - Arrays.deepEquals(data, - (String[])map.get(METAZONE_ID_PREFIX + me.getValue()))) - .findAny(); - cldrMeta.ifPresentOrElse(meta -> names.put(tzid, meta.getValue()), () -> { - // Check the JRE meta key, add if there is not. - Optional<Map.Entry<String[], String>> jreMeta = - jreMetaMap.entrySet().stream() - .filter(jm -> Arrays.deepEquals(data, jm.getKey())) - .findAny(); - jreMeta.ifPresentOrElse(meta -> names.put(tzid, meta.getValue()), () -> { - String metaName = "JRE_" + tzid.replaceAll("[/-]", "_"); - names.put(METAZONE_ID_PREFIX + metaName, data); - names.put(tzid, metaName); - }); - }); - } - }); - } - - Arrays.stream(AVAILABLE_TZIDS).forEach(tzid -> { + getAvailableZoneIds().stream().forEach(tzid -> { // If the tzid is deprecated, get the data for the replacement id String tzKey = Optional.ofNullable((String)handlerSupplMeta.get(tzid)) .orElse(tzid); Object data = map.get(TIMEZONE_ID_PREFIX + tzKey); if (data instanceof String[]) { - names.put(tzid, data); + // Hack for UTC. UTC is an alias to Etc/UTC in CLDR + if (tzid.equals("Etc/UTC") && !map.containsKey(TIMEZONE_ID_PREFIX + "UTC")) { + names.put(METAZONE_ID_PREFIX + META_ETCUTC_ZONE_NAME, data); + names.put(tzid, META_ETCUTC_ZONE_NAME); + names.put("UTC", META_ETCUTC_ZONE_NAME); + } else { + names.put(tzid, data); + } } else { String meta = handlerMetaZones.get(tzKey); if (meta != null) { @@ -735,24 +698,23 @@ // exemplar cities. Map<String, Object> exCities = map.entrySet().stream() - .filter(e -> e.getKey().startsWith(CLDRConverter.EXEMPLAR_CITY_PREFIX)) - .collect(Collectors - .toMap(Map.Entry::getKey, Map.Entry::getValue)); + .filter(e -> e.getKey().startsWith(CLDRConverter.EXEMPLAR_CITY_PREFIX)) + .collect(Collectors.toMap(Map.Entry::getKey, Map.Entry::getValue)); names.putAll(exCities); - if (!id.equals("en") && - !names.isEmpty()) { - // CLDR does not have UTC entry, so add it here. - names.put("UTC", EMPTY_ZONE); - - // no metazone zones - Arrays.asList(handlerMetaZones.get(MetaZonesParseHandler.NO_METAZONE_KEY) - .split("\\s")).stream() - .forEach(tz -> { - names.put(tz, EMPTY_ZONE); - }); + // If there's no UTC entry at this point, add an empty one + if (!names.isEmpty() && !names.containsKey("UTC")) { + names.putIfAbsent(METAZONE_ID_PREFIX + META_EMPTY_ZONE_NAME, EMPTY_ZONE); + names.put("UTC", META_EMPTY_ZONE_NAME); } + // Finally some compatibility stuff + ZoneId.SHORT_IDS.entrySet().stream() + .filter(e -> !names.containsKey(e.getKey()) && names.containsKey(e.getValue())) + .forEach(e -> { + names.put(e.getKey(), names.get(e.getValue())); + }); + return names; } @@ -1053,8 +1015,20 @@ StandardOpenOption.CREATE, StandardOpenOption.TRUNCATE_EXISTING); } + // This method assumes handlerMetaZones is already initialized + private static Set<String> getAvailableZoneIds() { + assert handlerMetaZones != null; + if (AVAILABLE_TZIDS == null) { + AVAILABLE_TZIDS = new HashSet<>(ZoneId.getAvailableZoneIds()); + AVAILABLE_TZIDS.addAll(handlerMetaZones.keySet()); + AVAILABLE_TZIDS.remove(MetaZonesParseHandler.NO_METAZONE_KEY); + } + + return AVAILABLE_TZIDS; + } + private static Stream<String> zidMapEntry() { - return ZoneId.getAvailableZoneIds().stream() + return getAvailableZoneIds().stream() .map(id -> { String canonId = canonicalTZMap.getOrDefault(id, id); String meta = handlerMetaZones.get(canonId);
diff --git a/make/jdk/src/classes/build/tools/generatecacerts/GenerateCacerts.java b/make/jdk/src/classes/build/tools/generatecacerts/GenerateCacerts.java new file mode 100644 index 0000000..8f260ea --- /dev/null +++ b/make/jdk/src/classes/build/tools/generatecacerts/GenerateCacerts.java
@@ -0,0 +1,148 @@ +/* + * Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. Oracle designates this + * particular file as subject to the "Classpath" exception as provided + * by Oracle in the LICENSE file that accompanied this code. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + */ + +package build.tools.generatecacerts; + +import java.io.DataOutputStream; +import java.io.FileOutputStream; +import java.io.IOException; +import java.io.InputStream; +import java.io.OutputStream; +import java.io.UnsupportedEncodingException; +import java.nio.file.Files; +import java.nio.file.Paths; +import java.security.DigestOutputStream; +import java.security.MessageDigest; +import java.security.NoSuchAlgorithmException; +import java.security.cert.CertificateException; +import java.security.cert.CertificateFactory; +import java.security.cert.X509Certificate; +import java.util.Arrays; +import java.util.List; +import java.util.stream.Collectors; + +/** + * Generate cacerts + * args[0]: Full path string to the directory that contains CA certs + * args[1]: Full path string to the generated cacerts + */ +public class GenerateCacerts { + public static void main(String[] args) throws Exception { + try (FileOutputStream fos = new FileOutputStream(args[1])) { + store(args[0], fos, "changeit".toCharArray()); + } + } + + // The following code are copied from JavaKeyStore.java. + + private static final int MAGIC = 0xfeedfeed; + private static final int VERSION_2 = 0x02; + + // This method is a simplified version of JavaKeyStore::engineStore. + // A new "dir" argument is added. All cert names in "dir" is collected into + // a sorted array. Each cert is stored with a creation date set to its + // notBefore value. Thus the output is determined as long as the certs + // are the same. + public static void store(String dir, OutputStream stream, char[] password) + throws IOException, NoSuchAlgorithmException, CertificateException + { + byte[] encoded; // the certificate encoding + CertificateFactory cf = CertificateFactory.getInstance("X509"); + + MessageDigest md = getPreKeyedHash(password); + DataOutputStream dos + = new DataOutputStream(new DigestOutputStream(stream, md)); + + dos.writeInt(MAGIC); + // always write the latest version + dos.writeInt(VERSION_2); + + // All file names in dir sorted. + // README is excluded. Name starting with "." excluded. + List<String> entries = Files.list(Paths.get(dir)) + .map(p -> p.getFileName().toString()) + .filter(s -> !s.equals("README") && !s.startsWith(".")) + .collect(Collectors.toList()); + + entries.sort(String::compareTo); + + dos.writeInt(entries.size()); + + for (String entry : entries) { + + String alias = entry + " [jdk]"; + X509Certificate cert; + try (InputStream fis = Files.newInputStream(Paths.get(dir, entry))) { + cert = (X509Certificate) cf.generateCertificate(fis); + } + + dos.writeInt(2); + + // Write the alias + dos.writeUTF(alias); + + // Write the (entry creation) date, which is notBefore of the cert + dos.writeLong(cert.getNotBefore().getTime()); + + // Write the trusted certificate + encoded = cert.getEncoded(); + dos.writeUTF(cert.getType()); + dos.writeInt(encoded.length); + dos.write(encoded); + } + + /* + * Write the keyed hash which is used to detect tampering with + * the keystore (such as deleting or modifying key or + * certificate entries). + */ + byte[] digest = md.digest(); + + dos.write(digest); + dos.flush(); + } + + private static MessageDigest getPreKeyedHash(char[] password) + throws NoSuchAlgorithmException, UnsupportedEncodingException + { + + MessageDigest md = MessageDigest.getInstance("SHA"); + byte[] passwdBytes = convertToBytes(password); + md.update(passwdBytes); + Arrays.fill(passwdBytes, (byte) 0x00); + md.update("Mighty Aphrodite".getBytes("UTF8")); + return md; + } + + private static byte[] convertToBytes(char[] password) { + int i, j; + byte[] passwdBytes = new byte[password.length * 2]; + for (i=0, j=0; i<password.length; i++) { + passwdBytes[j++] = (byte)(password[i] >> 8); + passwdBytes[j++] = (byte)password[i]; + } + return passwdBytes; + } +}
diff --git a/make/jdk/src/classes/build/tools/generatecharacter/GenerateCharacter.java b/make/jdk/src/classes/build/tools/generatecharacter/GenerateCharacter.java index 58e9dc7..f293569 100644 --- a/make/jdk/src/classes/build/tools/generatecharacter/GenerateCharacter.java +++ b/make/jdk/src/classes/build/tools/generatecharacter/GenerateCharacter.java
@@ -933,14 +933,15 @@ int n = sizes.length; StringBuffer result = new StringBuffer(); // liu : Add a comment showing the source of this table - result.append(commentStart + " The following tables and code generated using:" + - commentEnd + "\n "); - result.append(commentStart + ' ' + commandLineDescription + commentEnd + "\n "); - - if (plane == 0 && bLatin1 == false) { + if (debug) { + result.append(commentStart + " The following tables and code generated using:" + + commentEnd + "\n "); + result.append(commentStart + ' ' + commandLineDescription + commentEnd + "\n "); + } + if (plane == 0 && bLatin1 == false) { genCaseMapTableDeclaration(result); genCaseMapTable(initializers, specialCaseMaps); - } + } int totalBytes = 0; for (int k = 0; k < n - 1; k++) { genTable(result, tableNames[k], tables[k], 0, bytes[k]<<3, sizes[k], preshifted[k], @@ -1603,6 +1604,7 @@ */ static boolean verbose = false; + static boolean debug = false; static boolean nobidi = false; static boolean nomirror = false; static boolean identifiers = false; @@ -1682,6 +1684,8 @@ for (int j = 0; j < args.length; j++) { if (args[j].equals("-verbose") || args[j].equals("-v")) verbose = true; + else if (args[j].equals("-d")) + debug = true; else if (args[j].equals("-nobidi")) nobidi = true; else if (args[j].equals("-nomirror"))
diff --git a/make/jdk/src/classes/build/tools/generatelsrequivmaps/EquivMapsGenerator.java b/make/jdk/src/classes/build/tools/generatelsrequivmaps/EquivMapsGenerator.java index 86f2243..a4e673d 100644 --- a/make/jdk/src/classes/build/tools/generatelsrequivmaps/EquivMapsGenerator.java +++ b/make/jdk/src/classes/build/tools/generatelsrequivmaps/EquivMapsGenerator.java
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2012, 2017, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2020, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -33,10 +33,12 @@ import java.time.ZoneId; import java.time.ZonedDateTime; import java.util.ArrayList; +import java.util.Arrays; import java.util.List; import java.util.Locale; import java.util.Map; import java.util.TreeMap; +import java.util.stream.Collectors; /** * This tool reads the IANA Language Subtag Registry data file downloaded from @@ -75,32 +77,49 @@ String type = null; String tag = null; String preferred = null; + String prefix = null; for (String line : Files.readAllLines(Paths.get(filename), Charset.forName("UTF-8"))) { line = line.toLowerCase(Locale.ROOT); - int index = line.indexOf(' ')+1; + int index = line.indexOf(' ') + 1; if (line.startsWith("file-date:")) { LSRrevisionDate = line.substring(index); } else if (line.startsWith("type:")) { type = line.substring(index); } else if (line.startsWith("tag:") || line.startsWith("subtag:")) { tag = line.substring(index); - } else if (line.startsWith("preferred-value:") - && !type.equals("extlang")) { + } else if (line.startsWith("preferred-value:")) { preferred = line.substring(index); - processDeprecatedData(type, tag, preferred); + } else if (line.startsWith("prefix:")) { + prefix = line.substring(index); } else if (line.equals("%%")) { + processDeprecatedData(type, tag, preferred, prefix); type = null; tag = null; + preferred = null; + prefix = null; } } + + // Last entry + processDeprecatedData(type, tag, preferred, prefix); } private static void processDeprecatedData(String type, String tag, - String preferred) { + String preferred, + String prefix) { StringBuilder sb; + + if (type == null || tag == null || preferred == null) { + return; + } + + if (type.equals("extlang") && prefix != null) { + tag = prefix + "-" + tag; + } + if (type.equals("region") || type.equals("variant")) { if (!initialRegionVariantMap.containsKey(preferred)) { sb = new StringBuilder("-"); @@ -113,7 +132,7 @@ + " A region/variant subtag \"" + preferred + "\" is registered for more than one subtags."); } - } else { // language, grandfahered, and redundant + } else { // language, extlang, grandfathered, and redundant if (!initialLanguageMap.containsKey(preferred)) { sb = new StringBuilder(preferred); sb.append(','); @@ -131,7 +150,12 @@ private static void generateEquivalentMap() { String[] subtags; for (String preferred : initialLanguageMap.keySet()) { - subtags = initialLanguageMap.get(preferred).toString().split(","); + // There are cases where the same tag may appear in two entries, e.g., + // "yue" is defined both as extlang and redundant. Remove the dup. + subtags = Arrays.stream(initialLanguageMap.get(preferred).toString().split(",")) + .distinct() + .collect(Collectors.toList()) + .toArray(new String[0]); if (subtags.length == 2) { sortedLanguageMap1.put(subtags[0], subtags[1]); @@ -215,10 +239,7 @@ + " static final Map<String, String[]> multiEquivsMap;\n" + " static final Map<String, String> regionVariantEquivMap;\n\n" + " static {\n" - + " singleEquivMap = new HashMap<>();\n" - + " multiEquivsMap = new HashMap<>();\n" - + " regionVariantEquivMap = new HashMap<>();\n\n" - + " // This is an auto-generated file and should not be manually edited.\n"; + + " singleEquivMap = new HashMap<>("; private static final String footerText = " }\n\n" @@ -242,6 +263,12 @@ Paths.get(fileName))) { writer.write(getOpenJDKCopyright()); writer.write(headerText + + (int)(sortedLanguageMap1.size() / 0.75f + 1) + ");\n" + + " multiEquivsMap = new HashMap<>(" + + (int)(sortedLanguageMap2.size() / 0.75f + 1) + ");\n" + + " regionVariantEquivMap = new HashMap<>(" + + (int)(sortedRegionVariantMap.size() / 0.75f + 1) + ");\n\n" + + " // This is an auto-generated file and should not be manually edited.\n" + " // LSR Revision: " + LSRrevisionDate); writer.newLine();
diff --git a/make/jdk/src/classes/build/tools/module/GenModuleInfoSource.java b/make/jdk/src/classes/build/tools/module/GenModuleInfoSource.java index 60d0b6e..67b3c41 100644 --- a/make/jdk/src/classes/build/tools/module/GenModuleInfoSource.java +++ b/make/jdk/src/classes/build/tools/module/GenModuleInfoSource.java
@@ -57,11 +57,14 @@ */ public class GenModuleInfoSource { private final static String USAGE = - "Usage: GenModuleInfoSource -o <output file> \n" + - " --source-file <module-info-java>\n" + - " --modules <module-name>[,<module-name>...]\n" + - " <module-info.java.extra> ...\n"; + "Usage: GenModuleInfoSource \n" + + " [-d]\n" + + " -o <output file>\n" + + " --source-file <module-info-java>\n" + + " --modules <module-name>[,<module-name>...]\n" + + " <module-info.java.extra> ...\n"; + static boolean debug = false; static boolean verbose = false; public static void main(String... args) throws Exception { Path outfile = null; @@ -73,6 +76,9 @@ String option = args[i]; String arg = i+1 < args.length ? args[i+1] : null; switch (option) { + case "-d": + debug = true; + break; case "-o": outfile = Paths.get(arg); i++; @@ -146,10 +152,12 @@ for (String l : lines) { writer.println(l); if (l.trim().startsWith("module ")) { - // print URI rather than file path to avoid escape - writer.format(" // source file: %s%n", sourceFile.toUri()); - for (Path file: extraFiles) { - writer.format(" // %s%n", file.toUri()); + if (debug) { + // print URI rather than file path to avoid escape + writer.format(" // source file: %s%n", sourceFile.toUri()); + for (Path file : extraFiles) { + writer.format(" // %s%n", file.toUri()); + } } break; }
diff --git a/make/jdk/src/classes/build/tools/tzdb/TzdbZoneRulesCompiler.java b/make/jdk/src/classes/build/tools/tzdb/TzdbZoneRulesCompiler.java index 8cbdd0d..148cdbc 100644 --- a/make/jdk/src/classes/build/tools/tzdb/TzdbZoneRulesCompiler.java +++ b/make/jdk/src/classes/build/tools/tzdb/TzdbZoneRulesCompiler.java
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2012, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2019, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -263,7 +263,7 @@ for (ZoneRules rules : rulesList) { baos.reset(); DataOutputStream dataos = new DataOutputStream(baos); - rules.writeExternal(dataos); + Ser.write(rules, dataos); dataos.close(); byte[] bytes = baos.toByteArray(); out.writeShort(bytes.length);
diff --git a/make/jdk/src/classes/build/tools/tzdb/TzdbZoneRulesProvider.java b/make/jdk/src/classes/build/tools/tzdb/TzdbZoneRulesProvider.java index 488a1ad..2622a8f 100644 --- a/make/jdk/src/classes/build/tools/tzdb/TzdbZoneRulesProvider.java +++ b/make/jdk/src/classes/build/tools/tzdb/TzdbZoneRulesProvider.java
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2019, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -31,26 +31,14 @@ import java.nio.file.Files; import java.nio.file.Path; import java.nio.file.Paths; -import java.util.ArrayList; -import java.util.Collections; -import java.util.HashMap; -import java.util.HashSet; -import java.util.List; -import java.util.Map; +import java.util.*; import java.util.Map.Entry; -import java.util.NavigableMap; -import java.util.Objects; -import java.util.Set; -import java.util.TreeMap; -import java.util.TreeSet; import java.util.concurrent.ConcurrentHashMap; import java.time.*; import java.time.Year; import java.time.chrono.IsoChronology; import java.time.temporal.TemporalAdjusters; -import java.time.zone.ZoneOffsetTransition; -import java.time.zone.ZoneOffsetTransitionRule; -import java.time.zone.ZoneOffsetTransitionRule.TimeDefinition; +import build.tools.tzdb.ZoneOffsetTransitionRule.TimeDefinition; import java.time.zone.ZoneRulesException; /** @@ -274,8 +262,8 @@ /** Whether this is midnight end of day. */ boolean endOfDay; - /** The time of the cutover. */ + /** The time definition of the cutover. */ TimeDefinition timeDefinition = TimeDefinition.WALL; void adjustToForwards(int year) { @@ -345,6 +333,20 @@ // time must be midnight when end of day flag is true endOfDay = true; secsOfDay = 0; + } else if (secsOfDay < 0 || secsOfDay > 86400) { + // beyond 0:00-24:00 range. Adjust the cutover date. + int beyondDays = secsOfDay / 86400; + secsOfDay %= 86400; + if (secsOfDay < 0) { + secsOfDay = 86400 + secsOfDay; + beyondDays -= 1; + } + LocalDate date = LocalDate.of(2004, month, dayOfMonth).plusDays(beyondDays); // leap-year + month = date.getMonth(); + dayOfMonth = date.getDayOfMonth(); + if (dayOfWeek != null) { + dayOfWeek = dayOfWeek.plus(beyondDays); + } } timeDefinition = parseTimeDefinition(timeStr.charAt(timeStr.length() - 1)); } @@ -499,9 +501,11 @@ * * @param standardOffset the active standard offset, not null * @param savingsBeforeSecs the active savings before the transition in seconds + * @param negativeSavings minimum savings in the rule, usually zero, but negative if negative DST is + * in effect. * @return the transition, not null */ - ZoneOffsetTransitionRule toTransitionRule(ZoneOffset stdOffset, int savingsBefore) { + ZoneOffsetTransitionRule toTransitionRule(ZoneOffset stdOffset, int savingsBefore, int negativeSavings) { // rule shared by different zones, so don't change it Month month = this.month; int dayOfMonth = this.dayOfMonth; @@ -524,6 +528,7 @@ } endOfDay = false; } + // build rule return ZoneOffsetTransitionRule.of( //month, dayOfMonth, dayOfWeek, time, endOfDay, timeDefinition, @@ -531,7 +536,7 @@ LocalTime.ofSecondOfDay(secsOfDay), endOfDay, timeDefinition, stdOffset, ZoneOffset.ofTotalSeconds(stdOffset.getTotalSeconds() + savingsBefore), - ZoneOffset.ofTotalSeconds(stdOffset.getTotalSeconds() + savingsAmount)); + ZoneOffset.ofTotalSeconds(stdOffset.getTotalSeconds() + savingsAmount - negativeSavings)); } RuleLine parse(String[] tokens) { @@ -645,12 +650,12 @@ this.ldtSecs = ldt.toEpochSecond(ZoneOffset.UTC); } - ZoneOffsetTransition toTransition(ZoneOffset standardOffset, int savingsBeforeSecs) { + ZoneOffsetTransition toTransition(ZoneOffset standardOffset, int savingsBeforeSecs, int negativeSavings) { // copy of code in ZoneOffsetTransitionRule to avoid infinite loop ZoneOffset wallOffset = ZoneOffset.ofTotalSeconds( standardOffset.getTotalSeconds() + savingsBeforeSecs); ZoneOffset offsetAfter = ZoneOffset.ofTotalSeconds( - standardOffset.getTotalSeconds() + rule.savingsAmount); + standardOffset.getTotalSeconds() + rule.savingsAmount - negativeSavings); LocalDateTime dt = rule.timeDefinition .createDateTime(ldt, standardOffset, wallOffset); return ZoneOffsetTransition.of(dt, wallOffset, offsetAfter); @@ -668,10 +673,12 @@ * Tests if this a real transition with the active savings in seconds * * @param savingsBefore the active savings in seconds + * @param negativeSavings minimum savings in the rule, usually zero, but negative if negative DST is + * in effect. * @return true, if savings changes */ - boolean isTransition(int savingsBefore) { - return rule.savingsAmount != savingsBefore; + boolean isTransition(int savingsBefore, int negativeSavings) { + return rule.savingsAmount - negativeSavings != savingsBefore; } public int compareTo(TransRule other) { @@ -699,12 +706,22 @@ // start ldt of each zone window LocalDateTime zoneStart = LocalDateTime.MIN; - // first stanard offset + // first standard offset ZoneOffset firstStdOffset = stdOffset; // first wall offset ZoneOffset firstWallOffset = wallOffset; for (ZoneLine zone : zones) { + // Adjust stdOffset, if negative DST is observed. It should be either + // fixed amount, or expressed in the named Rules. + int negativeSavings = Math.min(zone.fixedSavingsSecs, findNegativeSavings(zoneStart, zone)); + if (negativeSavings < 0) { + zone.stdOffsetSecs += negativeSavings; + if (zone.fixedSavingsSecs < 0) { + zone.fixedSavingsSecs = 0; + } + } + // check if standard offset changed, update it if yes ZoneOffset stdOffsetPrev = stdOffset; // for effectiveSavings check if (zone.stdOffsetSecs != stdOffset.getTotalSeconds()) { @@ -793,7 +810,7 @@ // sort the merged rules Collections.sort(trules); - effectiveSavings = 0; + effectiveSavings = -negativeSavings; for (TransRule rule : trules) { if (rule.toEpochSecond(stdOffsetPrev, savings) > zoneStart.toEpochSecond(wallOffset)) { @@ -802,7 +819,7 @@ // (hence isAfter) break; } - effectiveSavings = rule.rule.savingsAmount; + effectiveSavings = rule.rule.savingsAmount - negativeSavings; } } // check if the start of the window represents a transition @@ -819,21 +836,21 @@ if (trules != null) { long zoneStartEpochSecs = zoneStart.toEpochSecond(wallOffset); for (TransRule trule : trules) { - if (trule.isTransition(savings)) { + if (trule.isTransition(savings, negativeSavings)) { long epochSecs = trule.toEpochSecond(stdOffset, savings); if (epochSecs < zoneStartEpochSecs || epochSecs >= zone.toDateTimeEpochSecond(savings)) { continue; } - transitionList.add(trule.toTransition(stdOffset, savings)); - savings = trule.rule.savingsAmount; + transitionList.add(trule.toTransition(stdOffset, savings, negativeSavings)); + savings = trule.rule.savingsAmount - negativeSavings; } } } if (lastRules != null) { for (TransRule trule : lastRules) { - lastTransitionRuleList.add(trule.rule.toTransitionRule(stdOffset, savings)); - savings = trule.rule.savingsAmount; + lastTransitionRuleList.add(trule.rule.toTransitionRule(stdOffset, savings, negativeSavings)); + savings = trule.rule.savingsAmount - negativeSavings; } } @@ -850,4 +867,38 @@ lastTransitionRuleList); } + /** + * Find the minimum negative savings in named Rules for a Zone. Savings are only + * looked at for the period of the subject Zone. + * + * @param zoneStart start LDT of the zone + * @param zl ZoneLine to look at + */ + private int findNegativeSavings(LocalDateTime zoneStart, ZoneLine zl) { + int negativeSavings = 0; + LocalDateTime zoneEnd = zl.toDateTime(); + + if (zl.savingsRule != null) { + List<RuleLine> rlines = rules.get(zl.savingsRule); + if (rlines == null) { + throw new IllegalArgumentException("<Rule> not found: " + + zl.savingsRule); + } + + negativeSavings = Math.min(0, rlines.stream() + .filter(l -> windowOverlap(l, zoneStart.getYear(), zoneEnd.getYear())) + .map(l -> l.savingsAmount) + .min(Comparator.naturalOrder()) + .orElse(0)); + } + + return negativeSavings; + } + + private boolean windowOverlap(RuleLine ruleLine, int zoneStartYear, int zoneEndYear) { + boolean overlap = zoneStartYear <= ruleLine.startYear && zoneEndYear >= ruleLine.startYear || + zoneStartYear <= ruleLine.endYear && zoneEndYear >= ruleLine.endYear; + + return overlap; + } }
diff --git a/make/jdk/src/classes/build/tools/tzdb/ZoneRules.java b/make/jdk/src/classes/build/tools/tzdb/ZoneRules.java deleted file mode 100644 index 25d7cb7..0000000 --- a/make/jdk/src/classes/build/tools/tzdb/ZoneRules.java +++ /dev/null
@@ -1,317 +0,0 @@ -/* - * Copyright (c) 2012, 2016, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. Oracle designates this - * particular file as subject to the "Classpath" exception as provided - * by Oracle in the LICENSE file that accompanied this code. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - */ - -/* - * This file is available under and governed by the GNU General Public - * License version 2 only, as published by the Free Software Foundation. - * However, the following notice accompanied the original version of this - * file: - * - * Copyright (c) 2011-2012, Stephen Colebourne & Michael Nascimento Santos - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of JSR-310 nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -package build.tools.tzdb; - -import java.io.DataOutput; -import java.io.IOException; -import java.io.ObjectOutput; -import java.time.LocalDateTime; -import java.time.LocalTime; -import java.time.ZoneOffset; -import java.time.zone.ZoneOffsetTransition; -import java.time.zone.ZoneOffsetTransitionRule; -import java.time.zone.ZoneOffsetTransitionRule.TimeDefinition; -import java.util.Arrays; -import java.util.ArrayList; -import java.util.List; - -/** - * Duplicated code of javax.time.zone.ZoneRules, ZoneOffsetTransitionRule - * and Ser to generate the serialization form output of ZoneRules for - * tzdb.jar. - * - * Implementation here is the copy/paste of ZoneRules, ZoneOffsetTransitionRule - * and Ser in javax.time.zone package. Make sure the code here is synchrionozed - * with the serialization implementation there. - * - * @since 1.8 - */ - -final class ZoneRules { - - /** - * The transitions between standard offsets (epoch seconds), sorted. - */ - private final long[] standardTransitions; - /** - * The standard offsets. - */ - private final ZoneOffset[] standardOffsets; - /** - * The transitions between instants (epoch seconds), sorted. - */ - private final long[] savingsInstantTransitions; - - /** - * The wall offsets. - */ - private final ZoneOffset[] wallOffsets; - /** - * The last rule. - */ - private final ZoneOffsetTransitionRule[] lastRules; - - /** - * Creates an instance. - * - * @param baseStandardOffset the standard offset to use before legal rules were set, not null - * @param baseWallOffset the wall offset to use before legal rules were set, not null - * @param standardOffsetTransitionList the list of changes to the standard offset, not null - * @param transitionList the list of transitions, not null - * @param lastRules the recurring last rules, size 16 or less, not null - */ - ZoneRules(ZoneOffset baseStandardOffset, - ZoneOffset baseWallOffset, - List<ZoneOffsetTransition> standardOffsetTransitionList, - List<ZoneOffsetTransition> transitionList, - List<ZoneOffsetTransitionRule> lastRules) { - - this.standardTransitions = new long[standardOffsetTransitionList.size()]; - - this.standardOffsets = new ZoneOffset[standardOffsetTransitionList.size() + 1]; - this.standardOffsets[0] = baseStandardOffset; - for (int i = 0; i < standardOffsetTransitionList.size(); i++) { - this.standardTransitions[i] = standardOffsetTransitionList.get(i).toEpochSecond(); - this.standardOffsets[i + 1] = standardOffsetTransitionList.get(i).getOffsetAfter(); - } - - // convert savings transitions to locals - List<ZoneOffset> localTransitionOffsetList = new ArrayList<>(); - localTransitionOffsetList.add(baseWallOffset); - for (ZoneOffsetTransition trans : transitionList) { - localTransitionOffsetList.add(trans.getOffsetAfter()); - } - - this.wallOffsets = localTransitionOffsetList.toArray(new ZoneOffset[localTransitionOffsetList.size()]); - - // convert savings transitions to instants - this.savingsInstantTransitions = new long[transitionList.size()]; - for (int i = 0; i < transitionList.size(); i++) { - this.savingsInstantTransitions[i] = transitionList.get(i).toEpochSecond(); - } - - // last rules - if (lastRules.size() > 16) { - throw new IllegalArgumentException("Too many transition rules"); - } - this.lastRules = lastRules.toArray(new ZoneOffsetTransitionRule[lastRules.size()]); - } - - /** Type for ZoneRules. */ - static final byte ZRULES = 1; - - /** - * Writes the state to the stream. - * - * @param out the output stream, not null - * @throws IOException if an error occurs - */ - void writeExternal(DataOutput out) throws IOException { - out.writeByte(ZRULES); - out.writeInt(standardTransitions.length); - for (long trans : standardTransitions) { - writeEpochSec(trans, out); - } - for (ZoneOffset offset : standardOffsets) { - writeOffset(offset, out); - } - out.writeInt(savingsInstantTransitions.length); - for (long trans : savingsInstantTransitions) { - writeEpochSec(trans, out); - } - for (ZoneOffset offset : wallOffsets) { - writeOffset(offset, out); - } - out.writeByte(lastRules.length); - for (ZoneOffsetTransitionRule rule : lastRules) { - writeRule(rule, out); - } - } - - /** - * Writes the state the ZoneOffset to the stream. - * - * @param offset the offset, not null - * @param out the output stream, not null - * @throws IOException if an error occurs - */ - static void writeOffset(ZoneOffset offset, DataOutput out) throws IOException { - final int offsetSecs = offset.getTotalSeconds(); - int offsetByte = offsetSecs % 900 == 0 ? offsetSecs / 900 : 127; // compress to -72 to +72 - out.writeByte(offsetByte); - if (offsetByte == 127) { - out.writeInt(offsetSecs); - } - } - - /** - * Writes the epoch seconds to the stream. - * - * @param epochSec the epoch seconds, not null - * @param out the output stream, not null - * @throws IOException if an error occurs - */ - static void writeEpochSec(long epochSec, DataOutput out) throws IOException { - if (epochSec >= -4575744000L && epochSec < 10413792000L && epochSec % 900 == 0) { // quarter hours between 1825 and 2300 - int store = (int) ((epochSec + 4575744000L) / 900); - out.writeByte((store >>> 16) & 255); - out.writeByte((store >>> 8) & 255); - out.writeByte(store & 255); - } else { - out.writeByte(255); - out.writeLong(epochSec); - } - } - - /** - * Writes the state of the transition rule to the stream. - * - * @param rule the transition rule, not null - * @param out the output stream, not null - * @throws IOException if an error occurs - */ - static void writeRule(ZoneOffsetTransitionRule rule, DataOutput out) throws IOException { - int month = rule.getMonth().getValue(); - byte dom = (byte)rule.getDayOfMonthIndicator(); - int dow = (rule.getDayOfWeek() == null ? -1 : rule.getDayOfWeek().getValue()); - LocalTime time = rule.getLocalTime(); - boolean timeEndOfDay = rule.isMidnightEndOfDay(); - TimeDefinition timeDefinition = rule.getTimeDefinition(); - ZoneOffset standardOffset = rule.getStandardOffset(); - ZoneOffset offsetBefore = rule.getOffsetBefore(); - ZoneOffset offsetAfter = rule.getOffsetAfter(); - - int timeSecs = (timeEndOfDay ? 86400 : time.toSecondOfDay()); - int stdOffset = standardOffset.getTotalSeconds(); - int beforeDiff = offsetBefore.getTotalSeconds() - stdOffset; - int afterDiff = offsetAfter.getTotalSeconds() - stdOffset; - int timeByte = (timeSecs % 3600 == 0 ? (timeEndOfDay ? 24 : time.getHour()) : 31); - int stdOffsetByte = (stdOffset % 900 == 0 ? stdOffset / 900 + 128 : 255); - int beforeByte = (beforeDiff == 0 || beforeDiff == 1800 || beforeDiff == 3600 ? beforeDiff / 1800 : 3); - int afterByte = (afterDiff == 0 || afterDiff == 1800 || afterDiff == 3600 ? afterDiff / 1800 : 3); - int dowByte = (dow == -1 ? 0 : dow); - int b = (month << 28) + // 4 bytes - ((dom + 32) << 22) + // 6 bytes - (dowByte << 19) + // 3 bytes - (timeByte << 14) + // 5 bytes - (timeDefinition.ordinal() << 12) + // 2 bytes - (stdOffsetByte << 4) + // 8 bytes - (beforeByte << 2) + // 2 bytes - afterByte; // 2 bytes - out.writeInt(b); - if (timeByte == 31) { - out.writeInt(timeSecs); - } - if (stdOffsetByte == 255) { - out.writeInt(stdOffset); - } - if (beforeByte == 3) { - out.writeInt(offsetBefore.getTotalSeconds()); - } - if (afterByte == 3) { - out.writeInt(offsetAfter.getTotalSeconds()); - } - } - - /** - * Checks if this set of rules equals another. - * <p> - * Two rule sets are equal if they will always result in the same output - * for any given input instant or local date-time. - * Rules from two different groups may return false even if they are in fact the same. - * <p> - * This definition should result in implementations comparing their entire state. - * - * @param otherRules the other rules, null returns false - * @return true if this rules is the same as that specified - */ - @Override - public boolean equals(Object otherRules) { - if (this == otherRules) { - return true; - } - if (otherRules instanceof ZoneRules) { - ZoneRules other = (ZoneRules) otherRules; - return Arrays.equals(standardTransitions, other.standardTransitions) && - Arrays.equals(standardOffsets, other.standardOffsets) && - Arrays.equals(savingsInstantTransitions, other.savingsInstantTransitions) && - Arrays.equals(wallOffsets, other.wallOffsets) && - Arrays.equals(lastRules, other.lastRules); - } - return false; - } - - /** - * Returns a suitable hash code given the definition of {@code #equals}. - * - * @return the hash code - */ - @Override - public int hashCode() { - return Arrays.hashCode(standardTransitions) ^ - Arrays.hashCode(standardOffsets) ^ - Arrays.hashCode(savingsInstantTransitions) ^ - Arrays.hashCode(wallOffsets) ^ - Arrays.hashCode(lastRules); - } - -}
diff --git a/make/langtools/src/classes/build/tools/symbolgenerator/CreateSymbols.java b/make/langtools/src/classes/build/tools/symbolgenerator/CreateSymbols.java index 03f84fa..6379ef8 100644 --- a/make/langtools/src/classes/build/tools/symbolgenerator/CreateSymbols.java +++ b/make/langtools/src/classes/build/tools/symbolgenerator/CreateSymbols.java
@@ -31,6 +31,7 @@ import build.tools.symbolgenerator.CreateSymbols .ModuleHeaderDescription .RequiresDescription; + import java.io.BufferedInputStream; import java.io.BufferedReader; import java.io.ByteArrayInputStream; @@ -41,6 +42,7 @@ import java.io.OutputStream; import java.io.StringWriter; import java.io.Writer; +import java.nio.charset.StandardCharsets; import java.nio.file.Files; import java.nio.file.FileVisitResult; import java.nio.file.FileVisitor; @@ -198,7 +200,7 @@ */ @SuppressWarnings("unchecked") public void createSymbols(String ctDescriptionFile, String ctSymLocation, CtSymKind ctSymKind) throws IOException { - LoadDescriptions data = load(Paths.get(ctDescriptionFile), null); + LoadDescriptions data = load(Paths.get(ctDescriptionFile)); splitHeaders(data.classes); @@ -237,7 +239,7 @@ public static String EXTENSION = ".sig"; - LoadDescriptions load(Path ctDescription, String deletePlatform) throws IOException { + LoadDescriptions load(Path ctDescription) throws IOException { List<PlatformInput> platforms = new ArrayList<>(); Set<String> generatePlatforms = null; @@ -247,13 +249,11 @@ case "generate": String[] platformsAttr = reader.attributes.get("platforms").split(":"); generatePlatforms = new HashSet<>(List.of(platformsAttr)); - generatePlatforms.remove(deletePlatform); reader.moveNext(); break; case "platform": PlatformInput platform = PlatformInput.load(reader); - if (!platform.version.equals(deletePlatform)) - platforms.add(platform); + platforms.add(platform); reader.moveNext(); break; default: @@ -318,18 +318,28 @@ ClassList result = new ClassList(); - for (ClassDescription desc : classes.values()) { + classes.values().forEach(result::add); + return new LoadDescriptions(result, + modules, + new ArrayList<>(platforms)); + } + + private static void removeVersion(LoadDescriptions load, String deletePlatform) { + for (Iterator<ClassDescription> it = load.classes.iterator(); it.hasNext();) { + ClassDescription desc = it.next(); Iterator<ClassHeaderDescription> chdIt = desc.header.iterator(); while (chdIt.hasNext()) { ClassHeaderDescription chd = chdIt.next(); - chd.versions = reduce(chd.versions, generatePlatforms); - if (chd.versions.isEmpty()) + chd.versions = removeVersion(chd.versions, deletePlatform); + if (chd.versions.isEmpty()) { chdIt.remove(); + } } if (desc.header.isEmpty()) { + it.remove(); continue; } @@ -338,7 +348,7 @@ while (methodIt.hasNext()) { MethodDescription method = methodIt.next(); - method.versions = reduce(method.versions, generatePlatforms); + method.versions = removeVersion(method.versions, deletePlatform); if (method.versions.isEmpty()) methodIt.remove(); } @@ -348,35 +358,29 @@ while (fieldIt.hasNext()) { FieldDescription field = fieldIt.next(); - field.versions = reduce(field.versions, generatePlatforms); + field.versions = removeVersion(field.versions, deletePlatform); if (field.versions.isEmpty()) fieldIt.remove(); } - - result.add(desc); } - Map<String, ModuleDescription> moduleList = new HashMap<>(); - - for (ModuleDescription desc : modules.values()) { + for (Iterator<ModuleDescription> it = load.modules.values().iterator(); it.hasNext();) { + ModuleDescription desc = it.next(); Iterator<ModuleHeaderDescription> mhdIt = desc.header.iterator(); while (mhdIt.hasNext()) { ModuleHeaderDescription mhd = mhdIt.next(); - mhd.versions = reduce(mhd.versions, generatePlatforms); + mhd.versions = removeVersion(mhd.versions, deletePlatform); if (mhd.versions.isEmpty()) mhdIt.remove(); } if (desc.header.isEmpty()) { + it.remove(); continue; } - - moduleList.put(desc.name, desc); } - - return new LoadDescriptions(result, moduleList, platforms); } static final class LoadDescriptions { @@ -458,6 +462,17 @@ return sb.toString(); } + private static String removeVersion(String original, String remove) { + StringBuilder sb = new StringBuilder(); + + for (char v : original.toCharArray()) { + if (v != remove.charAt(0)) { + sb.append(v); + } + } + return sb.toString(); + } + private static class PlatformInput { public final String version; public final String basePlatform; @@ -1129,24 +1144,9 @@ Map<String, ModuleDescription> modules = new HashMap<>(); for (VersionDescription desc : versions) { - List<byte[]> classFileData = new ArrayList<>(); + Iterable<byte[]> classFileData = loadClassData(desc.classes); - try (BufferedReader descIn = - Files.newBufferedReader(Paths.get(desc.classes))) { - String line; - while ((line = descIn.readLine()) != null) { - ByteArrayOutputStream data = new ByteArrayOutputStream(); - for (int i = 0; i < line.length(); i += 2) { - String hex = line.substring(i, i + 2); - data.write(Integer.parseInt(hex, 16)); - } - classFileData.add(data.toByteArray()); - } - } catch (IOException ex) { - throw new IllegalStateException(ex); - } - - loadVersionClasses(classes, modules, classFileData, excludesIncludes, desc.version); + loadVersionClasses(classes, modules, classFileData, excludesIncludes, desc.version, null); } List<PlatformInput> platforms = @@ -1156,7 +1156,7 @@ null)) .collect(Collectors.toList()); - dumpDescriptions(classes, modules, platforms, descDest.resolve("symbols"), args); + dumpDescriptions(classes, modules, platforms, Set.of(), descDest.resolve("symbols"), args); } //where: private static final String DO_NO_MODIFY = @@ -1189,11 +1189,33 @@ "# ##########################################################\n" + "#\n"; + private Iterable<byte[]> loadClassData(String path) { + List<byte[]> classFileData = new ArrayList<>(); + + try (BufferedReader descIn = + Files.newBufferedReader(Paths.get(path))) { + String line; + while ((line = descIn.readLine()) != null) { + ByteArrayOutputStream data = new ByteArrayOutputStream(); + for (int i = 0; i < line.length(); i += 2) { + String hex = line.substring(i, i + 2); + data.write(Integer.parseInt(hex, 16)); + } + classFileData.add(data.toByteArray()); + } + } catch (IOException ex) { + throw new IllegalStateException(ex); + } + + return classFileData; + } + private void loadVersionClasses(ClassList classes, Map<String, ModuleDescription> modules, Iterable<byte[]> classData, ExcludeIncludeList excludesIncludes, - String version) { + String version, + String baseline) { Map<String, ModuleDescription> currentVersionModules = new HashMap<>(); @@ -1307,12 +1329,12 @@ ClassDescription existing = classes.find(clazz.name, true); if (existing != null) { - addClassHeader(existing, header, version); + addClassHeader(existing, header, version, baseline); for (MethodDescription currentMethod : clazz.methods) { - addMethod(existing, currentMethod, version); + addMethod(existing, currentMethod, version, baseline); } for (FieldDescription currentField : clazz.fields) { - addField(existing, currentField, version); + addField(existing, currentField, version, baseline); } } else { classes.add(clazz); @@ -1349,6 +1371,7 @@ private void dumpDescriptions(ClassList classes, Map<String, ModuleDescription> modules, List<PlatformInput> versions, + Set<String> forceWriteVersions, Path ctDescriptionFile, String[] args) throws IOException { classes.sort(); @@ -1410,7 +1433,7 @@ for (PlatformInput desc : versions) { List<String> files = desc.files; - if (files == null) { + if (files == null || forceWriteVersions.contains(desc.version)) { files = new ArrayList<>(); for (Entry<String, List<ClassDescription>> e : module2Classes.entrySet()) { StringWriter data = new StringWriter(); @@ -1428,9 +1451,34 @@ String dataString = data.toString(); if (!dataString.isEmpty()) { - try (Writer out = Files.newBufferedWriter(f)) { - out.append(DO_NO_MODIFY.replace("{YEAR}", String.valueOf(year))); - out.write(dataString); + String existingYear = null; + boolean hasChange = true; + if (Files.isReadable(f)) { + String oldContent = new String(Files.readAllBytes(f), StandardCharsets.UTF_8); + int yearPos = DO_NO_MODIFY.indexOf("{YEAR}"); + String headerPattern = + Pattern.quote(DO_NO_MODIFY.substring(0, yearPos)) + + "([0-9]+)(, [0-9]+)?" + + Pattern.quote(DO_NO_MODIFY.substring(yearPos + "{YEAR}".length())); + String pattern = headerPattern + + Pattern.quote(dataString); + Matcher m = Pattern.compile(pattern, Pattern.MULTILINE).matcher(oldContent); + if (m.matches()) { + hasChange = false; + } else { + m = Pattern.compile(headerPattern).matcher(oldContent); + if (m.find()) { + existingYear = m.group(1); + } + } + } + if (hasChange) { + try (Writer out = Files.newBufferedWriter(f, StandardCharsets.UTF_8)) { + String currentYear = String.valueOf(year); + String yearSpec = (existingYear != null && !currentYear.equals(existingYear) ? existingYear + ", " : "") + currentYear; + out.append(DO_NO_MODIFY.replace("{YEAR}", yearSpec)); + out.write(dataString); + } } files.add(f.getFileName().toString()); } @@ -1472,15 +1520,17 @@ } } - public void createIncrementalBaseLine(String ctDescriptionFile, - String excludeFile, - String[] args) throws IOException { - String specVersion = System.getProperty("java.specification.version"); + private void incrementalUpdate(String ctDescriptionFile, + String excludeFile, + String platformVersion, + Iterable<byte[]> classBytes, + Function<LoadDescriptions, String> baseline, + String[] args) throws IOException { String currentVersion = - Integer.toString(Integer.parseInt(specVersion), Character.MAX_RADIX); - currentVersion = currentVersion.toUpperCase(Locale.ROOT); + Integer.toString(Integer.parseInt(platformVersion), Character.MAX_RADIX); + String version = currentVersion.toUpperCase(Locale.ROOT); Path ctDescriptionPath = Paths.get(ctDescriptionFile).toAbsolutePath(); - LoadDescriptions data = load(ctDescriptionPath, currentVersion); + LoadDescriptions data = load(ctDescriptionPath); ClassList classes = data.classes; Map<String, ModuleDescription> modules = data.modules; @@ -1488,24 +1538,70 @@ ExcludeIncludeList excludeList = ExcludeIncludeList.create(excludeFile); + loadVersionClasses(classes, modules, classBytes, excludeList, "$", version); - Iterable<byte[]> classBytes = dumpCurrentClasses(); - loadVersionClasses(classes, modules, classBytes, excludeList, currentVersion); + removeVersion(data, version); - String baseline; - - if (versions.isEmpty()) { - baseline = null; - } else { - baseline = versions.stream() - .sorted((v1, v2) -> v2.version.compareTo(v1.version)) - .findFirst() - .get() - .version; + for (ModuleDescription md : data.modules.values()) { + for (ModuleHeaderDescription header : md.header) { + header.versions = header.versions.replace("$", version); + } } - versions.add(new PlatformInput(currentVersion, baseline, null)); - dumpDescriptions(classes, modules, versions, ctDescriptionPath, args); + for (ClassDescription clazzDesc : data.classes) { + for (ClassHeaderDescription header : clazzDesc.header) { + header.versions = header.versions.replace("$", version); + } + for (MethodDescription method : clazzDesc.methods) { + method.versions = method.versions.replace("$", version); + } + for (FieldDescription field : clazzDesc.fields) { + field.versions = field.versions.replace("$", version); + } + } + + if (versions.stream().noneMatch(inp -> version.equals(inp.version))) { + versions.add(new PlatformInput(version, baseline.apply(data), null)); + } + + Set<String> writeVersions = new HashSet<>(); + + writeVersions.add(version); + + //re-write all platforms that have version as their basline: + versions.stream() + .filter(inp -> version.equals(inp.basePlatform)) + .map(inp -> inp.version) + .forEach(writeVersions::add); + dumpDescriptions(classes, modules, versions, writeVersions, ctDescriptionPath, args); + } + + public void createIncrementalBaseLineFromDataFile(String ctDescriptionFile, + String excludeFile, + String version, + String dataFile, + String baseline, + String[] args) throws IOException { + incrementalUpdate(ctDescriptionFile, excludeFile, version, loadClassData(dataFile), x -> baseline, args); + } + + public void createIncrementalBaseLine(String ctDescriptionFile, + String excludeFile, + String[] args) throws IOException { + String specVersion = System.getProperty("java.specification.version"); + Iterable<byte[]> classBytes = dumpCurrentClasses(); + Function<LoadDescriptions, String> baseline = data -> { + if (data.versions.isEmpty()) { + return null; + } else { + return data.versions.stream() + .sorted((v1, v2) -> v2.version.compareTo(v1.version)) + .findFirst() + .get() + .version; + } + }; + incrementalUpdate(ctDescriptionFile, excludeFile, specVersion, classBytes, baseline, args); } private List<byte[]> dumpCurrentClasses() throws IOException { @@ -1599,7 +1695,7 @@ classes.add(clazzDesc); } - addClassHeader(clazzDesc, headerDesc, version); + addClassHeader(clazzDesc, headerDesc, version, null); for (Method m : cf.methods) { if (!include(m.access_flags.flags)) @@ -1611,7 +1707,7 @@ for (Attribute attr : m.attributes) { readAttribute(cf, methDesc, attr); } - addMethod(clazzDesc, methDesc, version); + addMethod(clazzDesc, methDesc, version, null); } for (Field f : cf.fields) { if (!include(f.access_flags.flags)) @@ -1623,7 +1719,7 @@ for (Attribute attr : f.attributes) { readAttribute(cf, fieldDesc, attr); } - addField(clazzDesc, fieldDesc, version); + addField(clazzDesc, fieldDesc, version, null); } } @@ -1682,11 +1778,11 @@ return (accessFlags & (AccessFlags.ACC_PUBLIC | AccessFlags.ACC_PROTECTED)) != 0; } - private void addClassHeader(ClassDescription clazzDesc, ClassHeaderDescription headerDesc, String version) { + private void addClassHeader(ClassDescription clazzDesc, ClassHeaderDescription headerDesc, String version, String baseline) { //normalize: boolean existed = false; for (ClassHeaderDescription existing : clazzDesc.header) { - if (existing.equals(headerDesc)) { + if (existing.equals(headerDesc) && (!existed || (baseline != null && existing.versions.contains(baseline)))) { headerDesc = existing; existed = true; } else { @@ -1718,14 +1814,13 @@ } } - private void addMethod(ClassDescription clazzDesc, MethodDescription methDesc, String version) { + private void addMethod(ClassDescription clazzDesc, MethodDescription methDesc, String version, String baseline) { //normalize: boolean methodExisted = false; for (MethodDescription existing : clazzDesc.methods) { - if (existing.equals(methDesc)) { + if (existing.equals(methDesc) && (!methodExisted || (baseline != null && existing.versions.contains(baseline)))) { methodExisted = true; methDesc = existing; - break; } } methDesc.versions += version; @@ -1734,13 +1829,12 @@ } } - private void addField(ClassDescription clazzDesc, FieldDescription fieldDesc, String version) { + private void addField(ClassDescription clazzDesc, FieldDescription fieldDesc, String version, String baseline) { boolean fieldExisted = false; for (FieldDescription existing : clazzDesc.fields) { - if (existing.equals(fieldDesc)) { + if (existing.equals(fieldDesc) && (!fieldExisted || (baseline != null && existing.versions.contains(baseline)))) { fieldExisted = true; fieldDesc = existing; - break; } } fieldDesc.versions += version; @@ -2133,6 +2227,7 @@ } static abstract class FeatureDescription { + int flagsNormalization = ~0; int flags; boolean deprecated; String signature; @@ -2197,7 +2292,7 @@ @Override public int hashCode() { int hash = 3; - hash = 89 * hash + this.flags; + hash = 89 * hash + (this.flags & flagsNormalization); hash = 89 * hash + (this.deprecated ? 1 : 0); hash = 89 * hash + Objects.hashCode(this.signature); hash = 89 * hash + listHashCode(this.classAnnotations); @@ -2214,7 +2309,7 @@ return false; } final FeatureDescription other = (FeatureDescription) obj; - if (this.flags != other.flags) { + if ((this.flags & flagsNormalization) != (other.flags & flagsNormalization)) { return false; } if (this.deprecated != other.deprecated) { @@ -2785,6 +2880,7 @@ } static class MethodDescription extends FeatureDescription { + static int METHODS_FLAGS_NORMALIZATION = ~0; String name; String descriptor; List<String> thrownTypes; @@ -2792,6 +2888,10 @@ List<List<AnnotationDescription>> classParameterAnnotations; List<List<AnnotationDescription>> runtimeParameterAnnotations; + public MethodDescription() { + flagsNormalization = METHODS_FLAGS_NORMALIZATION; + } + @Override public int hashCode() { int hash = super.hashCode(); @@ -3516,6 +3616,24 @@ args); break; } + case "build-description-incremental-file": { + if (args.length != 6 && args.length != 7) { + help(); + return ; + } + + if (args.length == 7) { + if ("--normalize-method-flags".equals(args[6])) { + MethodDescription.METHODS_FLAGS_NORMALIZATION = ~(0x100 | 0x20); + } else { + help(); + return ; + } + } + + new CreateSymbols().createIncrementalBaseLineFromDataFile(args[1], args[2], args[3], args[4], "<none>".equals(args[5]) ? null : args[5], args); + break; + } case "build-description-incremental": { if (args.length != 3) { help();
diff --git a/make/langtools/tools/propertiesparser/gen/ClassGenerator.java b/make/langtools/tools/propertiesparser/gen/ClassGenerator.java index 999f67e..3d05cb6 100644 --- a/make/langtools/tools/propertiesparser/gen/ClassGenerator.java +++ b/make/langtools/tools/propertiesparser/gen/ClassGenerator.java
@@ -25,6 +25,8 @@ package propertiesparser.gen; +import static java.util.stream.Collectors.toList; + import propertiesparser.parser.Message; import propertiesparser.parser.MessageFile; import propertiesparser.parser.MessageInfo; @@ -44,11 +46,12 @@ import java.util.ArrayList; import java.util.Arrays; import java.util.Collections; -import java.util.TreeSet; import java.util.List; import java.util.Map; -import java.util.Set; import java.util.Properties; +import java.util.Set; +import java.util.TreeMap; +import java.util.TreeSet; import java.util.stream.Collectors; import java.util.stream.Stream; @@ -150,7 +153,11 @@ public void generateFactory(MessageFile messageFile, File outDir) { Map<FactoryKind, List<Map.Entry<String, Message>>> groupedEntries = messageFile.messages.entrySet().stream() - .collect(Collectors.groupingBy(e -> FactoryKind.parseFrom(e.getKey().split("\\.")[1]))); + .collect( + Collectors.groupingBy( + e -> FactoryKind.parseFrom(e.getKey().split("\\.")[1]), + TreeMap::new, + toList())); //generate nested classes List<String> nestedDecls = new ArrayList<>(); Set<String> importedTypes = new TreeSet<>();
diff --git a/make/launcher/Launcher-java.base.gmk b/make/launcher/Launcher-java.base.gmk index e62e96b..f6d4aa2 100644 --- a/make/launcher/Launcher-java.base.gmk +++ b/make/launcher/Launcher-java.base.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -32,36 +32,21 @@ ################################################################################ -# On windows, the debuginfo files get the same name as for java.dll. Build -# into another dir and copy selectively so debuginfo for java.dll isn't -# overwritten. $(eval $(call SetupBuildLauncher, java, \ CFLAGS := -DEXPAND_CLASSPATH_WILDCARDS -DENABLE_ARG_FILES, \ LDFLAGS_solaris := -R$(OPENWIN_HOME)/lib$(OPENJDK_TARGET_CPU_ISADIR), \ LIBS_windows := user32.lib comctl32.lib, \ EXTRA_RC_FLAGS := $(JAVA_RC_FLAGS), \ VERSION_INFO_RESOURCE := $(JAVA_VERSION_INFO_RESOURCE), \ - OUTPUT_DIR := $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/java_objs, \ OPTIMIZATION := HIGH, \ - WINDOWS_STATIC_LINK := true, \ - NO_JAVA_MS := true, \ )) -$(SUPPORT_OUTPUTDIR)/modules_cmds/java.base/java$(EXE_SUFFIX): $(BUILD_LAUNCHER_java) - $(MKDIR) -p $(@D) - $(RM) $@ - $(CP) $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/java_objs/java$(EXE_SUFFIX) $@ - -TARGETS += $(SUPPORT_OUTPUTDIR)/modules_cmds/java.base/java$(EXE_SUFFIX) - ifeq ($(OPENJDK_TARGET_OS), windows) $(eval $(call SetupBuildLauncher, javaw, \ CFLAGS := -DJAVAW -DEXPAND_CLASSPATH_WILDCARDS -DENABLE_ARG_FILES, \ LIBS_windows := user32.lib comctl32.lib, \ EXTRA_RC_FLAGS := $(JAVA_RC_FLAGS), \ VERSION_INFO_RESOURCE := $(JAVA_VERSION_INFO_RESOURCE), \ - WINDOWS_STATIC_LINK := true, \ - NO_JAVA_MS := true, \ )) endif
diff --git a/make/launcher/Launcher-jdk.aot.gmk b/make/launcher/Launcher-jdk.aot.gmk index 919ee76..10717a5 100644 --- a/make/launcher/Launcher-jdk.aot.gmk +++ b/make/launcher/Launcher-jdk.aot.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -46,7 +46,7 @@ --add-exports=jdk.internal.vm.ci/jdk.vm.ci.meta=$(call CommaList, jdk.internal.vm.compiler jdk.aot) \ --add-exports=jdk.internal.vm.ci/jdk.vm.ci.runtime=$(call CommaList, jdk.internal.vm.compiler jdk.aot) \ --add-exports=jdk.internal.vm.ci/jdk.vm.ci.sparc=$(call CommaList, jdk.internal.vm.compiler jdk.aot) \ - -XX:+UseAOT \ + -XX:+UnlockExperimentalVMOptions -XX:+UseAOT \ -XX:+CalculateClassFingerprint \ -Djvmci.UseProfilingInformation=false \ -Dgraal.UseExceptionProbability=false \
diff --git a/make/launcher/Launcher-jdk.hotspot.agent.gmk b/make/launcher/Launcher-jdk.hotspot.agent.gmk index cbf04bf..76da360 100644 --- a/make/launcher/Launcher-jdk.hotspot.agent.gmk +++ b/make/launcher/Launcher-jdk.hotspot.agent.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2016, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -27,5 +27,5 @@ $(eval $(call SetupBuildLauncher, jhsdb, \ MAIN_CLASS := sun.jvm.hotspot.SALauncher, \ - MACOSX_SIGNED := true, \ + MACOSX_PRIVILEGED := true, \ ))
diff --git a/make/launcher/Launcher-jdk.jcmd.gmk b/make/launcher/Launcher-jdk.jcmd.gmk index 66671d1..7117fa7 100644 --- a/make/launcher/Launcher-jdk.jcmd.gmk +++ b/make/launcher/Launcher-jdk.jcmd.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -30,7 +30,7 @@ JAVA_ARGS := \ -Dsun.jvm.hotspot.debugger.useProcDebugger \ -Dsun.jvm.hotspot.debugger.useWindbgDebugger, \ - MACOSX_SIGNED := true, \ + MACOSX_PRIVILEGED := true, \ )) $(eval $(call SetupBuildLauncher, jmap, \ @@ -38,7 +38,7 @@ JAVA_ARGS := \ -Dsun.jvm.hotspot.debugger.useProcDebugger \ -Dsun.jvm.hotspot.debugger.useWindbgDebugger, \ - MACOSX_SIGNED := true, \ + MACOSX_PRIVILEGED := true, \ )) $(eval $(call SetupBuildLauncher, jps, \ @@ -50,7 +50,7 @@ JAVA_ARGS := \ -Dsun.jvm.hotspot.debugger.useProcDebugger \ -Dsun.jvm.hotspot.debugger.useWindbgDebugger, \ - MACOSX_SIGNED := true, \ + MACOSX_PRIVILEGED := true, \ )) $(eval $(call SetupBuildLauncher, jstat, \
diff --git a/make/launcher/Launcher-jdk.jconsole.gmk b/make/launcher/Launcher-jdk.jconsole.gmk index 6205ae6..575b9e0 100644 --- a/make/launcher/Launcher-jdk.jconsole.gmk +++ b/make/launcher/Launcher-jdk.jconsole.gmk
@@ -28,7 +28,8 @@ $(eval $(call SetupBuildLauncher, jconsole, \ MAIN_CLASS := sun.tools.jconsole.JConsole, \ JAVA_ARGS := --add-opens java.base/java.io=jdk.jconsole \ - -Djconsole.showOutputViewer, \ + -Djconsole.showOutputViewer \ + -Djdk.attach.allowAttachSelf=true, \ CFLAGS_windows := -DJAVAW, \ LIBS_windows := user32.lib, \ ))
diff --git a/make/launcher/Launcher-jdk.jfr.gmk b/make/launcher/Launcher-jdk.jfr.gmk new file mode 100644 index 0000000..f2d504a --- /dev/null +++ b/make/launcher/Launcher-jdk.jfr.gmk
@@ -0,0 +1,31 @@ +# +# Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. +# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. +# +# This code is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 only, as +# published by the Free Software Foundation. Oracle designates this +# particular file as subject to the "Classpath" exception as provided +# by Oracle in the LICENSE file that accompanied this code. +# +# This code is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# version 2 for more details (a copy is included in the LICENSE file that +# accompanied this code). +# +# You should have received a copy of the GNU General Public License version +# 2 along with this work; if not, write to the Free Software Foundation, +# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +# +# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +# or visit www.oracle.com if you need additional information or have any +# questions. +# + +include LauncherCommon.gmk + +$(eval $(call SetupBuildLauncher, jfr, \ + MAIN_CLASS := jdk.jfr.internal.tool.Main, \ + CFLAGS := -DEXPAND_CLASSPATH_WILDCARDS, \ +))
diff --git a/make/launcher/Launcher-jdk.pack.gmk b/make/launcher/Launcher-jdk.pack.gmk index d712b91..a93fd2a 100644 --- a/make/launcher/Launcher-jdk.pack.gmk +++ b/make/launcher/Launcher-jdk.pack.gmk
@@ -86,21 +86,15 @@ CFLAGS_linux := -fPIC, \ CFLAGS_solaris := -KPIC, \ CFLAGS_macosx := -fPIC, \ - LDFLAGS := $(UNPACKEXE_ZIPOBJS) \ - $(LDFLAGS_JDKEXE) $(LDFLAGS_CXX_JDK) \ + LDFLAGS := $(LDFLAGS_JDKEXE) $(LDFLAGS_CXX_JDK) \ $(call SET_SHARED_LIBRARY_ORIGIN), \ LIBS := $(UNPACKEXE_LIBS) $(LIBCXX), \ OBJECT_DIR := $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/unpackexe, \ MANIFEST := $(TOPDIR)/src/jdk.pack/windows/native/unpack200/unpack200_proto.exe.manifest, \ MANIFEST_VERSION := $(VERSION_NUMBER_FOUR_POSITIONS), \ + EXTRA_OBJECT_FILES := $(UNPACKEXE_ZIPOBJS) \ )) -ifneq ($(USE_EXTERNAL_LIBZ), true) - - $(BUILD_UNPACKEXE): $(UNPACKEXE_ZIPOBJS) - -endif - TARGETS += $(BUILD_UNPACKEXE) ################################################################################
diff --git a/make/launcher/LauncherCommon.gmk b/make/launcher/LauncherCommon.gmk index 8736d8f..61e5c20 100644 --- a/make/launcher/LauncherCommon.gmk +++ b/make/launcher/LauncherCommon.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -24,20 +24,15 @@ # include JdkNativeCompilation.gmk +include TextFileProcessing.gmk -ifeq ($(OPENJDK_TARGET_OS), macosx) - ORIGIN_ARG := $(call SET_EXECUTABLE_ORIGIN) -else - ifeq ($(OPENJDK_TARGET_OS), windows) - endif - ORIGIN_ARG := $(call SET_EXECUTABLE_ORIGIN,/../lib/jli) +ORIGIN_ARG := $(call SET_EXECUTABLE_ORIGIN,/../lib/jli) - # Applications expect to be able to link against libjawt without invoking - # System.loadLibrary("jawt") first. This was the behaviour described in the - # devloper documentation of JAWT and what worked with OpenJDK6. - ifneq ($(findstring $(OPENJDK_TARGET_OS), linux solaris), ) - ORIGIN_ARG += $(call SET_EXECUTABLE_ORIGIN,/../lib) - endif +# Applications expect to be able to link against libjawt without invoking +# System.loadLibrary("jawt") first. This was the behaviour described in the +# devloper documentation of JAWT and what worked with OpenJDK6. +ifneq ($(findstring $(OPENJDK_TARGET_OS), linux solaris), ) + ORIGIN_ARG += $(call SET_EXECUTABLE_ORIGIN,/../lib) endif # Tell the compiler not to export any functions unless declared so in @@ -92,12 +87,10 @@ # LIBS_windows Additional LIBS_windows # LDFLAGS_solaris Additional LDFLAGS_solaris # RC_FLAGS Additional RC_FLAGS -# MACOSX_SIGNED On macosx, sign this binary -# WINDOWS_STATIC_LINK On windows, link statically with C runtime and libjli. +# MACOSX_PRIVILEGED On macosx, allow to access other processes # OPTIMIZATION Override default optimization level (LOW) # OUTPUT_DIR Override default output directory # VERSION_INFO_RESOURCE Override default Windows resource file -# NO_JAVA_MS Do not add -ms8m to JAVA_ARGS. SetupBuildLauncher = $(NamedParamsMacroTemplate) define SetupBuildLauncherBody # Setup default values (unless overridden) @@ -105,38 +98,46 @@ $1_OPTIMIZATION := LOW endif - ifneq ($$($1_NO_JAVA_MS), true) - # The norm is to append -ms8m, unless otherwise instructed. - $1_JAVA_ARGS += -ms8m - endif - ifeq ($$($1_MAIN_MODULE), ) $1_MAIN_MODULE := $(MODULE) endif - ifneq ($$($1_JAVA_ARGS), ) - ifneq ($$($1_EXTRA_JAVA_ARGS), ) - $1_EXTRA_JAVA_ARGS_STR := '{ $$(strip $$(foreach a, \ - $$(addprefix -J, $$($1_EXTRA_JAVA_ARGS)), "$$a"$(COMMA) )) }' - $1_CFLAGS += -DEXTRA_JAVA_ARGS=$$($1_EXTRA_JAVA_ARGS_STR) - endif - $1_JAVA_ARGS_STR := '{ $$(strip $$(foreach a, \ - $$(addprefix -J, $$($1_JAVA_ARGS)) -m $$($1_MAIN_MODULE)/$$($1_MAIN_CLASS), "$$a"$(COMMA) )) }' - $1_CFLAGS += -DJAVA_ARGS=$$($1_JAVA_ARGS_STR) + $1_JAVA_ARGS += -ms8m + ifneq ($$($1_MAIN_CLASS), ) + $1_LAUNCHER_CLASS := -m $$($1_MAIN_MODULE)/$$($1_MAIN_CLASS) endif + ifneq ($$($1_EXTRA_JAVA_ARGS), ) + $1_EXTRA_JAVA_ARGS_STR := '{ $$(strip $$(foreach a, \ + $$(addprefix -J, $$($1_EXTRA_JAVA_ARGS)), "$$a"$(COMMA) )) }' + $1_CFLAGS += -DEXTRA_JAVA_ARGS=$$($1_EXTRA_JAVA_ARGS_STR) + endif + $1_JAVA_ARGS_STR := '{ $$(strip $$(foreach a, \ + $$(addprefix -J, $$($1_JAVA_ARGS)) $$($1_LAUNCHER_CLASS), "$$a"$(COMMA) )) }' + $1_CFLAGS += -DJAVA_ARGS=$$($1_JAVA_ARGS_STR) + $1_LIBS := ifeq ($(OPENJDK_TARGET_OS), macosx) - ifeq ($$($1_MACOSX_SIGNED), true) - $1_PLIST_FILE := Info-privileged.plist - $1_CODESIGN := true + ifeq ($$($1_MACOSX_PRIVILEGED), true) + $1_PLIST_SRC_FILE := Info-privileged.plist else - $1_PLIST_FILE := Info-cmdline.plist + $1_PLIST_SRC_FILE := Info-cmdline.plist endif $1_CFLAGS += -DPACKAGE_PATH='"$(PACKAGE_PATH)"' - $1_LDFLAGS += -Wl,-all_load \ - -sectcreate __TEXT __info_plist $(MACOSX_PLIST_DIR)/$$($1_PLIST_FILE) + + $1_PLIST_FILE := $$(SUPPORT_OUTPUTDIR)/native/$$(MODULE)/$1/Info.plist + + $$(eval $$(call SetupTextFileProcessing, BUILD_PLIST_$1, \ + SOURCE_FILES := $$(TOPDIR)/src/java.base/macosx/native/launcher/$$($1_PLIST_SRC_FILE), \ + OUTPUT_FILE := $$($1_PLIST_FILE), \ + REPLACEMENTS := \ + @@ID@@ => $(MACOSX_BUNDLE_ID_BASE).$(VERSION_SHORT).$1 ; \ + @@VERSION@@ => $(VERSION_NUMBER) ; \ + )) + + $1_LDFLAGS += -Wl,-all_load -sectcreate __TEXT __info_plist $$($1_PLIST_FILE) + ifeq ($(STATIC_BUILD), true) $1_LDFLAGS += -exported_symbols_list \ $(SUPPORT_OUTPUTDIR)/build-static/exported.symbols @@ -149,8 +150,6 @@ -framework Foundation \ -framework SystemConfiguration \ -lstdc++ -liconv - else - $1_LIBS += $(SUPPORT_OUTPUTDIR)/native/java.base/libjli_static.a endif $1_LIBS += -framework Cocoa -framework Security \ -framework ApplicationServices @@ -165,37 +164,33 @@ $1_LIBS += -lz endif - ifeq ($$($1_WINDOWS_STATIC_LINK), true) - $1_CFLAGS += $(filter-out -MD, $(CFLAGS_JDKEXE)) - $1_WINDOWS_JLI_LIB := $(SUPPORT_OUTPUTDIR)/native/java.base/jli_static.lib - else - $1_CFLAGS += $(CFLAGS_JDKEXE) - $1_WINDOWS_JLI_LIB := $(SUPPORT_OUTPUTDIR)/native/java.base/libjli/jli.lib - endif + $1_WINDOWS_JLI_LIB := $(call FindStaticLib, java.base, jli, /libjli) $$(eval $$(call SetupJdkExecutable, BUILD_LAUNCHER_$1, \ NAME := $1, \ EXTRA_FILES := $(LAUNCHER_SRC)/main.c, \ OPTIMIZATION := $$($1_OPTIMIZATION), \ - CFLAGS := $$($1_CFLAGS) \ - $(LAUNCHER_CFLAGS) \ - $(VERSION_CFLAGS) \ - -DLAUNCHER_NAME='"$(LAUNCHER_NAME)"' \ + CFLAGS := $$(CFLAGS_JDKEXE) $$($1_CFLAGS) \ + $$(LAUNCHER_CFLAGS) \ + $$(VERSION_CFLAGS) \ + -DLAUNCHER_NAME='"$$(LAUNCHER_NAME)"' \ -DPROGNAME='"$1"' \ $$($1_CFLAGS), \ - CFLAGS_linux := -fPIC, \ - CFLAGS_solaris := -KPIC -DHAVE_GETHRTIME, \ + CFLAGS_solaris := -KPIC, \ CFLAGS_windows := $$($1_CFLAGS_windows), \ LDFLAGS := $$(LDFLAGS_JDKEXE) \ $$(ORIGIN_ARG) \ $$($1_LDFLAGS), \ LDFLAGS_linux := \ - -L$(SUPPORT_OUTPUTDIR)/modules_libs/java.base/jli, \ + -L$(call FindLibDirForModule, java.base)/jli, \ + LDFLAGS_macosx := \ + -L$(call FindLibDirForModule, java.base)/jli, \ LDFLAGS_solaris := $$($1_LDFLAGS_solaris) \ - -L$(SUPPORT_OUTPUTDIR)/modules_libs/java.base/jli, \ + -L$(call FindLibDirForModule, java.base)/jli, \ LIBS := $(JDKEXE_LIBS) $$($1_LIBS), \ LIBS_unix := $$($1_LIBS_unix), \ LIBS_linux := -lpthread -ljli $(LIBDL), \ + LIBS_macosx := -ljli, \ LIBS_solaris := -ljli -lthread $(LIBDL), \ LIBS_windows := $$($1_WINDOWS_JLI_LIB) \ $(SUPPORT_OUTPUTDIR)/native/java.base/libjava/java.lib advapi32.lib \ @@ -205,18 +200,19 @@ EXTRA_RC_FLAGS := $$($1_EXTRA_RC_FLAGS), \ MANIFEST := $(JAVA_MANIFEST), \ MANIFEST_VERSION := $(VERSION_NUMBER_FOUR_POSITIONS), \ - CODESIGN := $$($1_CODESIGN), \ )) $1 += $$(BUILD_LAUNCHER_$1) TARGETS += $$($1) - ifneq (,$(filter $(OPENJDK_TARGET_OS), macosx aix)) - $$(BUILD_LAUNCHER_$1): $(SUPPORT_OUTPUTDIR)/native/java.base/libjli_static.a + $$(BUILD_LAUNCHER_$1): $$(BUILD_PLIST_$1) + + ifeq ($(OPENJDK_TARGET_OS), aix) + $$(BUILD_LAUNCHER_$1): $(call FindStaticLib, java.base, jli_static) endif ifeq ($(OPENJDK_TARGET_OS), windows) - $$(BUILD_LAUNCHER_$1): $(SUPPORT_OUTPUTDIR)/native/java.base/libjava/java.lib \ + $$(BUILD_LAUNCHER_$1): $(call FindStaticLib, java.base, java, /libjava) \ $$($1_WINDOWS_JLI_LIB) endif endef
diff --git a/make/lib/Awt2dLibraries.gmk b/make/lib/Awt2dLibraries.gmk index aaf0244..39269d0 100644 --- a/make/lib/Awt2dLibraries.gmk +++ b/make/lib/Awt2dLibraries.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -244,7 +244,6 @@ LIBS_macosx := -lmlib_image \ -framework Cocoa \ -framework OpenGL \ - -framework JavaNativeFoundation \ -framework JavaRuntimeSupport \ -framework ApplicationServices \ -framework AudioToolbox, \ @@ -371,6 +370,13 @@ BUILD_LIBLCMS_INCLUDE_FILES := endif +ifeq ($(TOOLCHAIN_TYPE), clang) + ifeq ($(TOOLCHAIN_VERSION), 10.1) + # Work around an optimizer bug seen with Xcode 10.1, but fixed by 10.3 + BUILD_LIBLCMS_cmsopt.c_CFLAGS := -O0 + endif +endif + $(eval $(call SetupJdkLibrary, BUILD_LIBLCMS, \ NAME := lcms, \ INCLUDE_FILES := $(BUILD_LIBLCMS_INCLUDE_FILES), \ @@ -383,7 +389,7 @@ common/awt/debug \ libawt/java2d, \ HEADERS_FROM_SRC := $(LIBLCMS_HEADERS_FROM_SRC), \ - DISABLED_WARNINGS_gcc := format-nonliteral type-limits misleading-indentation, \ + DISABLED_WARNINGS_gcc := format-nonliteral type-limits misleading-indentation stringop-truncation, \ DISABLED_WARNINGS_clang := tautological-compare, \ DISABLED_WARNINGS_solstudio := E_STATEMENT_NOT_REACHED, \ DISABLED_WARNINGS_microsoft := 4819, \ @@ -503,6 +509,8 @@ LIBFREETYPE_CFLAGS := -I$(BUILD_LIBFREETYPE_HEADER_DIRS) ifeq ($(OPENJDK_TARGET_OS), windows) LIBFREETYPE_LIBS := $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/libfreetype/freetype.lib + # freetype now requires you to manually define this (see ftconfig.h) + BUILD_LIBFREETYPE_CFLAGS += -DDLL_EXPORT else LIBFREETYPE_LIBS := -lfreetype endif @@ -516,8 +524,8 @@ DISABLED_WARNINGS_solstudio := \ E_STATEMENT_NOT_REACHED \ E_END_OF_LOOP_CODE_NOT_REACHED, \ - DISABLED_WARNINGS_microsoft := 4267 4244 4312, \ - DISABLED_WARNINGS_gcc := implicit-fallthrough, \ + DISABLED_WARNINGS_microsoft := 4018 4267 4244 4312 4819, \ + DISABLED_WARNINGS_gcc := implicit-fallthrough cast-function-type bad-function-cast, \ LDFLAGS := $(LDFLAGS_JDKLIB) \ $(call SET_SHARED_LIBRARY_ORIGIN), \ )) @@ -527,37 +535,57 @@ ########################################################################### -#### Begin harfbuzz configuration -HARFBUZZ_CFLAGS := -DHAVE_OT -DHAVE_FALLBACK -DHAVE_UCDN -DHAVE_ROUND +ifeq ($(USE_EXTERNAL_HARFBUZZ), true) + LIBFONTMANAGER_EXTRA_SRC = + BUILD_LIBFONTMANAGER_FONTLIB += $(HARFBUZZ_LIBS) +else + LIBFONTMANAGER_EXTRA_SRC = libharfbuzz + HARFBUZZ_CFLAGS := -DHAVE_OT -DHAVE_FALLBACK -DHAVE_UCDN -DHAVE_ROUND -ifneq ($(OPENJDK_TARGET_OS), windows) - HARFBUZZ_CFLAGS += -DGETPAGESIZE -DHAVE_MPROTECT -DHAVE_PTHREAD \ - -DHAVE_SYSCONF -DHAVE_SYS_MMAN_H -DHAVE_UNISTD_H \ - -DHB_NO_PRAGMA_GCC_DIAGNOSTIC -endif -ifneq (, $(findstring $(OPENJDK_TARGET_OS), linux macosx)) - HARFBUZZ_CFLAGS += -DHAVE_INTEL_ATOMIC_PRIMITIVES -endif -ifeq ($(OPENJDK_TARGET_OS), solaris) - HARFBUZZ_CFLAGS += -DHAVE_SOLARIS_ATOMIC_OPS -endif -ifeq ($(OPENJDK_TARGET_OS), macosx) - HARFBUZZ_CFLAGS += -DHAVE_CORETEXT -endif -ifneq ($(OPENJDK_TARGET_OS), macosx) - LIBFONTMANAGER_EXCLUDE_FILES += harfbuzz/hb-coretext.cc -endif -# hb-ft.cc is not presently needed, and requires freetype 2.4.2 or later. -LIBFONTMANAGER_EXCLUDE_FILES += harfbuzz/hb-ft.cc + ifneq ($(OPENJDK_TARGET_OS), windows) + HARFBUZZ_CFLAGS += -DGETPAGESIZE -DHAVE_MPROTECT -DHAVE_PTHREAD \ + -DHAVE_SYSCONF -DHAVE_SYS_MMAN_H -DHAVE_UNISTD_H \ + -DHB_NO_PRAGMA_GCC_DIAGNOSTIC + endif + ifneq (, $(findstring $(OPENJDK_TARGET_OS), linux macosx)) + HARFBUZZ_CFLAGS += -DHAVE_INTEL_ATOMIC_PRIMITIVES + endif + ifeq ($(OPENJDK_TARGET_OS), solaris) + HARFBUZZ_CFLAGS += -DHAVE_SOLARIS_ATOMIC_OPS + endif + ifeq ($(OPENJDK_TARGET_OS), macosx) + HARFBUZZ_CFLAGS += -DHAVE_CORETEXT + endif + ifneq ($(OPENJDK_TARGET_OS), macosx) + LIBFONTMANAGER_EXCLUDE_FILES += libharfbuzz/hb-coretext.cc + endif + # hb-ft.cc is not presently needed, and requires freetype 2.4.2 or later. + LIBFONTMANAGER_EXCLUDE_FILES += libharfbuzz/hb-ft.cc -LIBFONTMANAGER_CFLAGS += $(HARFBUZZ_CFLAGS) + HARFBUZZ_DISABLED_WARNINGS_gcc := type-limits missing-field-initializers strict-aliasing + HARFBUZZ_DISABLED_WARNINGS_CXX_gcc := reorder delete-non-virtual-dtor strict-overflow \ + maybe-uninitialized class-memaccess + HARFBUZZ_DISABLED_WARNINGS_clang := unused-value incompatible-pointer-types \ + tautological-constant-out-of-range-compare int-to-pointer-cast \ + undef missing-field-initializers + HARFBUZZ_DISABLED_WARNINGS_microsoft := 4267 4244 4090 4146 4334 4819 4101 4068 4805 4138 + HARFBUZZ_DISABLED_WARNINGS_C_solstudio := \ + E_INTEGER_OVERFLOW_DETECTED \ + E_ARG_INCOMPATIBLE_WITH_ARG_L \ + E_ENUM_VAL_OVERFLOWS_INT_MAX + HARFBUZZ_DISABLED_WARNINGS_CXX_solstudio := \ + truncwarn wvarhidenmem wvarhidemem wbadlkginit identexpected \ + hidevf w_novirtualdescr arrowrtn2 unknownpragma -#### End harfbuzz configuration + LIBFONTMANAGER_CFLAGS += $(HARFBUZZ_CFLAGS) + +endif + LIBFONTMANAGER_EXTRA_HEADER_DIRS := \ - libfontmanager/harfbuzz \ - libfontmanager/harfbuzz/hb-ucdn \ + libharfbuzz \ + libharfbuzz/hb-ucdn \ common/awt \ common/font \ libawt/java2d \ @@ -566,9 +594,9 @@ # LIBFONTMANAGER_CFLAGS += $(LIBFREETYPE_CFLAGS) -BUILD_LIBFONTMANAGER_FONTLIB += $(LIBFREETYPE_LIBS) +BUILD_LIBFONTMANAGER_FONTLIB += $(LIBFREETYPE_LIBS) -LIBFONTMANAGER_OPTIMIZATION := HIGH +LIBFONTMANAGER_OPTIMIZATION := HIGHEST ifeq ($(OPENJDK_TARGET_OS), windows) LIBFONTMANAGER_EXCLUDE_FILES += X11FontScaler.c \ @@ -606,21 +634,14 @@ OPTIMIZATION := $(LIBFONTMANAGER_OPTIMIZATION), \ CFLAGS_windows = -DCC_NOEX, \ EXTRA_HEADER_DIRS := $(LIBFONTMANAGER_EXTRA_HEADER_DIRS), \ + EXTRA_SRC := $(LIBFONTMANAGER_EXTRA_SRC), \ WARNINGS_AS_ERRORS_xlc := false, \ - DISABLED_WARNINGS_gcc := sign-compare int-to-pointer-cast \ - type-limits missing-field-initializers implicit-fallthrough strict-aliasing, \ - DISABLED_WARNINGS_CXX_gcc := reorder delete-non-virtual-dtor strict-overflow \ - maybe-uninitialized, \ - DISABLED_WARNINGS_clang := unused-value incompatible-pointer-types \ - tautological-constant-out-of-range-compare int-to-pointer-cast, \ - DISABLED_WARNINGS_C_solstudio = \ - E_INTEGER_OVERFLOW_DETECTED \ - E_ARG_INCOMPATIBLE_WITH_ARG_L \ - E_ENUM_VAL_OVERFLOWS_INT_MAX, \ - DISABLED_WARNINGS_CXX_solstudio := \ - truncwarn wvarhidenmem wvarhidemem wbadlkginit identexpected \ - hidevf w_novirtualdescr arrowrtn2 unknownpragma, \ - DISABLED_WARNINGS_microsoft := 4267 4244 4018 4090 4996 4146 4334 4819 4101 4068 4805 4138, \ + DISABLED_WARNINGS_gcc := sign-compare unused-function int-to-pointer-cast $(HARFBUZZ_DISABLED_WARNINGS_gcc), \ + DISABLED_WARNINGS_CXX_gcc := $(HARFBUZZ_DISABLED_WARNINGS_CXX_gcc), \ + DISABLED_WARNINGS_clang := sign-compare $(HARFBUZZ_DISABLED_WARNINGS_clang), \ + DISABLED_WARNINGS_C_solstudio := $(HARFBUZZ_DISABLED_WARNINGS_C_solstudio), \ + DISABLED_WARNINGS_CXX_solstudio := $(HARFBUZZ_DISABLED_WARNINGS_CXX_solstudio), \ + DISABLED_WARNINGS_microsoft := 4018 4996 $(HARFBUZZ_DISABLED_WARNINGS_microsoft), \ LDFLAGS := $(subst -Xlinker -z -Xlinker defs,, \ $(subst -Wl$(COMMA)-z$(COMMA)defs,,$(LDFLAGS_JDKLIB))) $(LDFLAGS_CXX_JDK) \ $(call SET_SHARED_LIBRARY_ORIGIN), \ @@ -628,8 +649,7 @@ LDFLAGS_aix := -Wl$(COMMA)-berok, \ LIBS := $(BUILD_LIBFONTMANAGER_FONTLIB), \ LIBS_unix := -lawt -ljava -ljvm $(LIBM) $(LIBCXX), \ - LIBS_macosx := -lawt_lwawt -framework CoreText -framework CoreFoundation \ - -framework CoreGraphics, \ + LIBS_macosx := -lawt_lwawt -framework CoreText -framework CoreFoundation -framework CoreGraphics, \ LIBS_windows := $(WIN_JAVA_LIB) advapi32.lib user32.lib gdi32.lib \ $(WIN_AWT_LIB), \ )) @@ -734,11 +754,11 @@ ifeq ($(ENABLE_HEADLESS_ONLY), false) $(BUILD_LIBJAWT): $(BUILD_LIBAWT_XAWT) else - $(BUILD_LIBJAWT): $(INSTALL_LIBRARIES_HERE)/$(LIBRARY_PREFIX)awt_headless$(SHARED_LIBRARY_SUFFIX) + $(BUILD_LIBJAWT): $(call FindLib, $(MODULE), awt_headless) endif ifeq ($(OPENJDK_TARGET_OS), macosx) - $(BUILD_LIBJAWT): $(INSTALL_LIBRARIES_HERE)/$(LIBRARY_PREFIX)awt_lwawt$(SHARED_LIBRARY_SUFFIX) + $(BUILD_LIBJAWT): $(call FindLib, $(MODULE), awt_lwawt) endif endif # OPENJDK_TARGET_OS @@ -795,7 +815,8 @@ LIBSPLASHSCREEN_EXCLUDE_SRC_PATTERNS := unix endif - LIBSPLASHSCREEN_CFLAGS += -DSPLASHSCREEN -DPNG_NO_MMX_CODE -DPNG_ARM_NEON_OPT=0 + LIBSPLASHSCREEN_CFLAGS += -DSPLASHSCREEN -DPNG_NO_MMX_CODE \ + -DPNG_ARM_NEON_OPT=0 -DPNG_ARM_NEON_IMPLEMENTATION=0 ifeq ($(OPENJDK_TARGET_OS), macosx) LIBSPLASHSCREEN_CFLAGS += -DWITH_MACOSX @@ -821,8 +842,7 @@ $(LIBM) -lpthread -liconv -losxapp \ -framework ApplicationServices \ -framework Foundation \ - -framework Cocoa \ - -framework JavaNativeFoundation + -framework Cocoa else ifeq ($(OPENJDK_TARGET_OS), windows) LIBSPLASHSCREEN_LIBS += kernel32.lib user32.lib gdi32.lib delayimp.lib $(WIN_JAVA_LIB) jvm.lib else @@ -918,7 +938,6 @@ -framework Cocoa \ -framework Security \ -framework ExceptionHandling \ - -framework JavaNativeFoundation \ -framework JavaRuntimeSupport \ -framework OpenGL \ -framework QuartzCore -ljava, \ @@ -956,7 +975,6 @@ -framework Cocoa \ -framework Carbon \ -framework ApplicationServices \ - -framework JavaNativeFoundation \ -framework JavaRuntimeSupport \ -ljava -ljvm, \ ))
diff --git a/make/lib/CoreLibraries.gmk b/make/lib/CoreLibraries.gmk index b7c4986..226e208 100644 --- a/make/lib/CoreLibraries.gmk +++ b/make/lib/CoreLibraries.gmk
@@ -49,40 +49,20 @@ LIBFDLIBM_SRC := $(TOPDIR)/src/java.base/share/native/libfdlibm LIBFDLIBM_CFLAGS := -I$(LIBFDLIBM_SRC) $(FDLIBM_CFLAGS) -ifneq ($(OPENJDK_TARGET_OS), macosx) - $(eval $(call SetupNativeCompilation, BUILD_LIBFDLIBM, \ - NAME := fdlibm, \ - TYPE := STATIC_LIBRARY, \ - OUTPUT_DIR := $(SUPPORT_OUTPUTDIR)/native/$(MODULE), \ - SRC := $(LIBFDLIBM_SRC), \ - OPTIMIZATION := $(BUILD_LIBFDLIBM_OPTIMIZATION), \ - CFLAGS := $(CFLAGS_JDKLIB) $(LIBFDLIBM_CFLAGS), \ - CFLAGS_windows_debug := -DLOGGING, \ - CFLAGS_aix := -qfloat=nomaf, \ - DISABLED_WARNINGS_gcc := sign-compare misleading-indentation array-bounds, \ - DISABLED_WARNINGS_microsoft := 4146 4244 4018, \ - ARFLAGS := $(ARFLAGS), \ - OBJECT_DIR := $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/libfdlibm, \ - )) - -else - - # On macosx the old build does partial (incremental) linking of fdlibm instead of - # a plain static library. - $(eval $(call SetupNativeCompilation, BUILD_LIBFDLIBM_MAC, \ - NAME := fdlibm, \ - OUTPUT_DIR := $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/libfdlibm, \ - SRC := $(LIBFDLIBM_SRC), \ - CFLAGS := $(CFLAGS_JDKLIB) $(LIBFDLIBM_CFLAGS), \ - LDFLAGS := -nostdlib $(ARFLAGS), \ - OBJECT_DIR := $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/libfdlibm, \ - )) - - BUILD_LIBFDLIBM := $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/$(LIBRARY_PREFIX)fdlibm$(STATIC_LIBRARY_SUFFIX) - $(BUILD_LIBFDLIBM): $(BUILD_LIBFDLIBM_MAC) - $(call install-file) - -endif +$(eval $(call SetupNativeCompilation, BUILD_LIBFDLIBM, \ + NAME := fdlibm, \ + TYPE := STATIC_LIBRARY, \ + OUTPUT_DIR := $(SUPPORT_OUTPUTDIR)/native/$(MODULE), \ + SRC := $(LIBFDLIBM_SRC), \ + OPTIMIZATION := $(BUILD_LIBFDLIBM_OPTIMIZATION), \ + CFLAGS := $(CFLAGS_JDKLIB) $(LIBFDLIBM_CFLAGS), \ + CFLAGS_windows_debug := -DLOGGING, \ + CFLAGS_aix := -qfloat=nomaf, \ + DISABLED_WARNINGS_gcc := sign-compare misleading-indentation array-bounds, \ + DISABLED_WARNINGS_microsoft := 4146 4244 4018, \ + ARFLAGS := $(ARFLAGS), \ + OBJECT_DIR := $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/libfdlibm, \ +)) ########################################################################################## @@ -131,15 +111,15 @@ $(call SET_SHARED_LIBRARY_ORIGIN), \ LDFLAGS_macosx := -L$(SUPPORT_OUTPUTDIR)/native/$(MODULE)/, \ LDFLAGS_windows := -delayload:shell32.dll, \ + LIBS := $(BUILD_LIBFDLIBM_TARGET), \ LIBS_unix := -ljvm -lverify, \ - LIBS_linux := $(LIBDL) $(BUILD_LIBFDLIBM), \ - LIBS_solaris := -lsocket -lnsl -lscf $(LIBDL) $(BUILD_LIBFDLIBM), \ - LIBS_aix := $(LIBDL) $(BUILD_LIBFDLIBM) $(LIBM),\ - LIBS_macosx := -lfdlibm \ - -framework CoreFoundation \ + LIBS_linux := $(LIBDL), \ + LIBS_solaris := -lsocket -lnsl -lscf $(LIBDL), \ + LIBS_aix := $(LIBDL) $(LIBM),\ + LIBS_macosx := -framework CoreFoundation \ -framework Foundation \ -framework Security -framework SystemConfiguration, \ - LIBS_windows := jvm.lib $(BUILD_LIBFDLIBM) $(WIN_VERIFY_LIB) \ + LIBS_windows := jvm.lib $(WIN_VERIFY_LIB) \ shell32.lib delayimp.lib \ advapi32.lib version.lib, \ )) @@ -168,6 +148,7 @@ CFLAGS := $(CFLAGS_JDKLIB) \ $(LIBZ_CFLAGS), \ CFLAGS_unix := $(BUILD_LIBZIP_MMAP) -UDEBUG, \ + DISABLED_WARNINGS_gcc := unused-function implicit-fallthrough, \ LDFLAGS := $(LDFLAGS_JDKLIB) \ $(call SET_SHARED_LIBRARY_ORIGIN), \ LIBS_unix := -ljvm -ljava $(LIBZ_LIBS), \ @@ -227,8 +208,6 @@ endif ifeq ($(OPENJDK_TARGET_OS), windows) - # Staticically link with c runtime on windows. - LIBJLI_CFLAGS_JDKLIB := $(filter-out -MD, $(CFLAGS_JDKLIB)) LIBJLI_OUTPUT_DIR := $(INSTALL_LIBRARIES_HERE) # Supply the name of the C runtime lib. LIBJLI_CFLAGS += -DMSVCR_DLL_NAME='"$(notdir $(MSVCR_DLL))"' @@ -236,7 +215,6 @@ LIBJLI_CFLAGS += -DMSVCP_DLL_NAME='"$(notdir $(MSVCP_DLL))"' endif else - LIBJLI_CFLAGS_JDKLIB := $(CFLAGS_JDKLIB) LIBJLI_OUTPUT_DIR := $(INSTALL_LIBRARIES_HERE)/jli endif @@ -260,7 +238,8 @@ EXCLUDE_FILES := $(LIBJLI_EXCLUDE_FILES), \ EXTRA_FILES := $(LIBJLI_EXTRA_FILES), \ OPTIMIZATION := HIGH, \ - CFLAGS := $(LIBJLI_CFLAGS_JDKLIB) $(LIBJLI_CFLAGS), \ + CFLAGS := $(CFLAGS_JDKLIB) $(LIBJLI_CFLAGS), \ + DISABLED_WARNINGS_gcc := unused-function implicit-fallthrough, \ DISABLED_WARNINGS_solstudio := \ E_ASM_DISABLES_OPTIMIZATION \ E_STATEMENT_NOT_REACHED, \ @@ -280,54 +259,7 @@ LIBJLI_SRC_DIRS := $(call FindSrcDirsForComponent, java.base, libjli) -# On windows, the static library has the same suffix as the import library created by -# with the shared library, so the static library is given a different name. No harm -# in doing it for all platform to reduce complexity. -ifeq ($(OPENJDK_TARGET_OS), windows) - $(eval $(call SetupNativeCompilation, BUILD_LIBJLI_STATIC, \ - NAME := jli_static, \ - TYPE := STATIC_LIBRARY, \ - OUTPUT_DIR := $(SUPPORT_OUTPUTDIR)/native/$(MODULE), \ - SRC := $(LIBJLI_SRC_DIRS), \ - EXCLUDE_FILES := $(LIBJLI_EXCLUDE_FILES), \ - EXTRA_FILES := $(LIBJLI_EXTRA_FILES), \ - OPTIMIZATION := HIGH, \ - CFLAGS := $(STATIC_LIBRARY_FLAGS) $(LIBJLI_CFLAGS_JDKLIB) $(LIBJLI_CFLAGS) \ - $(addprefix -I, $(LIBJLI_SRC_DIRS)), \ - ARFLAGS := $(ARFLAGS), \ - OBJECT_DIR := $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/libjli_static, \ - )) - - TARGETS += $(BUILD_LIBJLI_STATIC) - -else ifeq ($(OPENJDK_TARGET_OS), macosx) - # - # On macosx they do partial (incremental) linking of libjli_static.a - # code it here...rather than add support to NativeCompilation - # as this is first time I see it - $(eval $(call SetupNativeCompilation, BUILD_LIBJLI_STATIC, \ - NAME := jli_static, \ - OUTPUT_DIR := $(SUPPORT_OUTPUTDIR)/native/$(MODULE), \ - SRC := $(LIBJLI_SRC_DIRS), \ - EXCLUDE_FILES := $(LIBJLI_EXCLUDE_FILES), \ - EXTRA_FILES := $(LIBJLI_EXTRA_FILES), \ - OPTIMIZATION := HIGH, \ - CFLAGS := $(LIBJLI_CFLAGS_JDKLIB) $(LIBJLI_CFLAGS) \ - $(addprefix -I, $(LIBJLI_SRC_DIRS)), \ - LDFLAGS := -nostdlib $(ARFLAGS), \ - OBJECT_DIR := $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/libjli_static, \ - )) - - ifeq ($(STATIC_BUILD), true) - TARGETS += $(BUILD_LIBJLI_STATIC) - else - $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/libjli_static.a: $(BUILD_LIBJLI_STATIC) - $(call install-file) - - TARGETS += $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/libjli_static.a - endif - -else ifeq ($(OPENJDK_TARGET_OS), aix) +ifeq ($(OPENJDK_TARGET_OS), aix) # AIX also requires a static libjli because the compiler doesn't support '-rpath' $(eval $(call SetupNativeCompilation, BUILD_LIBJLI_STATIC, \ NAME := jli_static, \ @@ -337,7 +269,7 @@ EXCLUDE_FILES := $(LIBJLI_EXCLUDE_FILES), \ EXTRA_FILES := $(LIBJLI_EXTRA_FILES), \ OPTIMIZATION := HIGH, \ - CFLAGS := $(STATIC_LIBRARY_FLAGS) $(LIBJLI_CFLAGS_JDKLIB) $(LIBJLI_CFLAGS) \ + CFLAGS := $(STATIC_LIBRARY_FLAGS) $(CFLAGS_JDKLIB) $(LIBJLI_CFLAGS) \ $(addprefix -I, $(LIBJLI_SRC_DIRS)), \ ARFLAGS := $(ARFLAGS), \ OBJECT_DIR := $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/libjli_static))
diff --git a/make/lib/Lib-java.base.gmk b/make/lib/Lib-java.base.gmk index 1e96356..74f8f28 100644 --- a/make/lib/Lib-java.base.gmk +++ b/make/lib/Lib-java.base.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -29,7 +29,7 @@ $(eval $(call IncludeCustomExtension, lib/Lib-java.base.gmk)) # Prepare the find cache. -$(eval $(call FillCacheFind, $(wildcard $(TOPDIR)/src/java.base/*/native))) +$(call FillFindCache, $(wildcard $(TOPDIR)/src/java.base/*/native)) ################################################################################ # Create all the core libraries @@ -55,7 +55,7 @@ LIBS_solaris := -lnsl -lsocket $(LIBDL), \ LIBS_aix := $(LIBDL),\ LIBS_windows := ws2_32.lib jvm.lib secur32.lib iphlpapi.lib winhttp.lib \ - urlmon.lib delayimp.lib $(WIN_JAVA_LIB) advapi32.lib, \ + delayimp.lib $(WIN_JAVA_LIB) advapi32.lib, \ LIBS_macosx := -framework CoreFoundation -framework CoreServices, \ )) @@ -110,12 +110,12 @@ DISABLED_WARNINGS_clang := deprecated-declarations, \ LDFLAGS := $(LDFLAGS_JDKLIB) \ -L$(SUPPORT_OUTPUTDIR)/modules_libs/java.base \ - $(call SET_SHARED_LIBRARY_ORIGIN) \ - -fobjc-link-runtime, \ + $(call SET_SHARED_LIBRARY_ORIGIN), \ LIBS := \ - -framework JavaNativeFoundation \ + -lobjc \ -framework CoreServices \ -framework Security \ + -framework Foundation \ $(JDKLIB_LIBS), \ )) @@ -158,26 +158,27 @@ ############################################################################ # Create symlinks to libjsig in each JVM variant sub dir - LIB_OUTPUTDIR := $(call FindLibDirForModule, java.base) + ifneq ($(STATIC_LIBS), true) + LIB_OUTPUTDIR := $(call FindLibDirForModule, java.base) - # $1 variant subdir - define CreateSymlinks - # Always symlink from libdir/variant/libjsig.so -> ../libjsig.so. - $(LIB_OUTPUTDIR)/$1/$(call SHARED_LIBRARY,jsig): \ - $(LIB_OUTPUTDIR)/$(call SHARED_LIBRARY,jsig) + # $1 variant subdir + define CreateSymlinks + # Always symlink from libdir/variant/libjsig.so -> ../libjsig.so. + $(LIB_OUTPUTDIR)/$1/$(call SHARED_LIBRARY,jsig): \ + $(LIB_OUTPUTDIR)/$(call SHARED_LIBRARY,jsig) $$(call MakeDir, $$(@D)) $(RM) $$@ $(LN) -s ../$$(@F) $$@ - TARGETS += $(LIB_OUTPUTDIR)/$1/$(call SHARED_LIBRARY,jsig) - endef + TARGETS += $(LIB_OUTPUTDIR)/$1/$(call SHARED_LIBRARY,jsig) + endef - # The subdir is the same as the variant for client and minimal, for all - # others it's server. - VARIANT_SUBDIRS := $(filter client minimal, $(JVM_VARIANTS)) \ - $(if $(filter-out client minimal, $(JVM_VARIANTS)), server) - $(foreach v, $(VARIANT_SUBDIRS), $(eval $(call CreateSymlinks,$v))) - + # The subdir is the same as the variant for client and minimal, for all + # others it's server. + VARIANT_SUBDIRS := $(filter client minimal, $(JVM_VARIANTS)) \ + $(if $(filter-out client minimal, $(JVM_VARIANTS)), server) + $(foreach v, $(VARIANT_SUBDIRS), $(eval $(call CreateSymlinks,$v))) + endif ############################################################################ endif
diff --git a/make/lib/Lib-java.desktop.gmk b/make/lib/Lib-java.desktop.gmk index 81f85fe..274df2b 100644 --- a/make/lib/Lib-java.desktop.gmk +++ b/make/lib/Lib-java.desktop.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -29,7 +29,7 @@ $(eval $(call IncludeCustomExtension, lib/Lib-java.desktop.gmk)) # Prepare the find cache. -$(eval $(call FillCacheFind, $(wildcard $(TOPDIR)/src/java.desktop/*/native))) +$(call FillFindCache, $(wildcard $(TOPDIR)/src/java.desktop/*/native)) ################################################################################ # Create the AWT/2D libraries @@ -96,6 +96,7 @@ LDFLAGS := $(LDFLAGS_JDKLIB) \ $(call SET_SHARED_LIBRARY_ORIGIN), \ LIBS := \ + -ljava \ -framework Accelerate \ -framework ApplicationServices \ -framework AudioToolbox \ @@ -103,13 +104,14 @@ -framework Cocoa \ -framework Security \ -framework ExceptionHandling \ - -framework JavaNativeFoundation \ -framework JavaRuntimeSupport \ -framework OpenGL \ -framework IOSurface \ -framework QuartzCore, \ )) + $(BUILD_LIBOSXAPP): $(call FindLib, java.base, java) + TARGETS += $(BUILD_LIBOSXAPP) ############################################################################## @@ -127,7 +129,6 @@ -losxapp \ -framework Cocoa \ -framework ApplicationServices \ - -framework JavaNativeFoundation \ -framework JavaRuntimeSupport \ -framework SystemConfiguration \ $(JDKLIB_LIBS), \
diff --git a/make/lib/Lib-java.instrument.gmk b/make/lib/Lib-java.instrument.gmk index 7e625e3..9acde85 100644 --- a/make/lib/Lib-java.instrument.gmk +++ b/make/lib/Lib-java.instrument.gmk
@@ -31,20 +31,15 @@ ################################################################################ ifeq ($(OPENJDK_TARGET_OS), windows) - # Statically link the C runtime so that there are not dependencies on modules - # not on the search patch when invoked from the Windows system directory - # (or elsewhere). - LIBINSTRUMENT_CFLAGS_JDKLIB := $(filter-out -MD, $(CFLAGS_JDKLIB)) # equivalent of strcasecmp is stricmp on Windows LIBINSTRUMENT_CFLAGS := -Dstrcasecmp=stricmp -else - LIBINSTRUMENT_CFLAGS_JDKLIB := $(CFLAGS_JDKLIB) + WINDOWS_JLI_LIB := $(SUPPORT_OUTPUTDIR)/native/java.base/libjli/jli.lib endif $(eval $(call SetupJdkLibrary, BUILD_LIBINSTRUMENT, \ NAME := instrument, \ OPTIMIZATION := LOW, \ - CFLAGS := $(LIBINSTRUMENT_CFLAGS_JDKLIB) $(LIBINSTRUMENT_CFLAGS), \ + CFLAGS := $(CFLAGS_JDKLIB) $(LIBINSTRUMENT_CFLAGS), \ CFLAGS_debug := -DJPLIS_LOGGING, \ CFLAGS_release := -DNO_JPLIS_LOGGING, \ EXTRA_HEADER_DIRS := java.base:libjli, \ @@ -55,22 +50,24 @@ -L$(call FindLibDirForModule, java.base)/jli, \ LDFLAGS_solaris := $(call SET_SHARED_LIBRARY_ORIGIN,/jli) \ -L$(call FindLibDirForModule, java.base)/jli, \ - LDFLAGS_macosx := -Wl$(COMMA)-all_load, \ + LDFLAGS_macosx := $(call SET_SHARED_LIBRARY_ORIGIN,/jli) \ + -L$(call FindLibDirForModule, java.base)/jli, \ LDFLAGS_aix := -L$(SUPPORT_OUTPUTDIR)/native/java.base, \ LIBS := $(JDKLIB_LIBS), \ LIBS_unix := -ljava -ljvm $(LIBZ_LIBS), \ LIBS_linux := -ljli $(LIBDL), \ LIBS_solaris := -ljli $(LIBDL), \ LIBS_aix := -liconv -ljli_static $(LIBDL), \ - LIBS_macosx := -liconv -framework Cocoa -framework Security \ - -framework ApplicationServices \ - $(call FindStaticLib, java.base, jli_static), \ + LIBS_macosx := -ljli -liconv -framework Cocoa -framework Security \ + -framework ApplicationServices, \ LIBS_windows := jvm.lib $(WIN_JAVA_LIB) advapi32.lib \ - $(call FindStaticLib, java.base, jli_static), \ + $(WINDOWS_JLI_LIB), \ )) -ifneq ($(filter $(OPENJDK_TARGET_OS), macosx windows aix), ) +ifeq ($(OPENJDK_TARGET_OS), aix) $(BUILD_LIBINSTRUMENT): $(call FindStaticLib, java.base, jli_static) +else ifeq ($(OPENJDK_TARGET_OS), windows) + $(BUILD_LIBINSTRUMENT): $(call FindLib, java.base, jli) else $(BUILD_LIBINSTRUMENT): $(call FindLib, java.base, jli, /jli) endif
diff --git a/make/lib/Lib-java.security.jgss.gmk b/make/lib/Lib-java.security.jgss.gmk index b130671..2daf048 100644 --- a/make/lib/Lib-java.security.jgss.gmk +++ b/make/lib/Lib-java.security.jgss.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -55,6 +55,17 @@ )) TARGETS += $(BUILD_LIBW2K_LSA_AUTH) + + $(eval $(call SetupJdkLibrary, BUILD_LIBSSPI_BRIDGE, \ + NAME := sspi_bridge, \ + OPTIMIZATION := LOW, \ + CFLAGS := $(CFLAGS_JDKLIB) \ + -I$(TOPDIR)/src/java.security.jgss/share/native/libj2gss, \ + LDFLAGS := $(LDFLAGS_JDKLIB) \ + $(call SET_SHARED_LIBRARY_ORIGIN) \ + )) + + TARGETS += $(BUILD_LIBSSPI_BRIDGE) endif ifeq ($(OPENJDK_TARGET_OS), macosx) @@ -67,8 +78,8 @@ DISABLED_WARNINGS_clang := deprecated-declarations, \ LDFLAGS := $(LDFLAGS_JDKLIB) \ $(call SET_SHARED_LIBRARY_ORIGIN), \ - LIBS := -framework JavaNativeFoundation -framework Cocoa \ - -framework SystemConfiguration -framework Kerberos, \ + LIBS := -framework Cocoa -framework SystemConfiguration \ + -framework Kerberos, \ )) TARGETS += $(BUILD_LIBOSXKRB5)
diff --git a/make/lib/Lib-jdk.accessibility.gmk b/make/lib/Lib-jdk.accessibility.gmk index b7f820b..cdf3a7c 100644 --- a/make/lib/Lib-jdk.accessibility.gmk +++ b/make/lib/Lib-jdk.accessibility.gmk
@@ -55,7 +55,7 @@ VERSIONINFO_RESOURCE := $(ROOT_SRCDIR)/common/AccessBridgeStatusWindow.rc, \ ) - $$(BUILD_JAVAACCESSBRIDGE$1): $(SUPPORT_OUTPUTDIR)/native/java.desktop/libjawt/jawt.lib + $$(BUILD_JAVAACCESSBRIDGE$1): $(call FindStaticLib, java.desktop, jawt, /libjawt) TARGETS += $$(BUILD_JAVAACCESSBRIDGE$1) endef
diff --git a/make/lib/Lib-jdk.hotspot.agent.gmk b/make/lib/Lib-jdk.hotspot.agent.gmk index 1cbae70..83c0b53 100644 --- a/make/lib/Lib-jdk.hotspot.agent.gmk +++ b/make/lib/Lib-jdk.hotspot.agent.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2015, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2015, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -65,9 +65,9 @@ CXXFLAGS := $(CXXFLAGS_JDKLIB) $(SA_CFLAGS) $(SA_CXXFLAGS), \ EXTRA_SRC := $(LIBSA_EXTRA_SRC), \ LDFLAGS := $(LDFLAGS_JDKLIB) $(SA_LDFLAGS), \ - LIBS_linux := -lthread_db $(LIBDL), \ + LIBS_linux := $(LIBDL), \ LIBS_solaris := -ldl -ldemangle -lthread -lproc, \ - LIBS_macosx := -framework Foundation -framework JavaNativeFoundation \ + LIBS_macosx := -framework Foundation \ -framework JavaRuntimeSupport -framework Security -framework CoreFoundation, \ LIBS_windows := dbgeng.lib, \ ))
diff --git a/make/lib/Lib-jdk.jdwp.agent.gmk b/make/lib/Lib-jdk.jdwp.agent.gmk index 0bc93e0..f00f076 100644 --- a/make/lib/Lib-jdk.jdwp.agent.gmk +++ b/make/lib/Lib-jdk.jdwp.agent.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -64,6 +64,7 @@ LIBS_solaris := $(LIBDL), \ LIBS_macosx := -liconv, \ LIBS_aix := -liconv, \ + LIBS_windows := $(WIN_JAVA_LIB), \ )) $(BUILD_LIBJDWP): $(call FindLib, java.base, java)
diff --git a/make/lib/LibCommon.gmk b/make/lib/LibCommon.gmk index 86856f3..4c3eb66 100644 --- a/make/lib/LibCommon.gmk +++ b/make/lib/LibCommon.gmk
@@ -57,24 +57,6 @@ EXPORT_ALL_SYMBOLS := -xldscope=global endif -################################################################################ -# Find a library -# Param 1 - module name -# Param 2 - library name -# Param 3 - optional subdir for library -FindLib = \ - $(call FindLibDirForModule, \ - $(strip $1))$(strip $3)/$(LIBRARY_PREFIX)$(strip $2)$(SHARED_LIBRARY_SUFFIX) - -################################################################################ -# Find a static library -# Param 1 - module name -# Param 2 - library name -# Param 3 - optional subdir for library -FindStaticLib = \ - $(addprefix $(SUPPORT_OUTPUTDIR)/native/, \ - $(strip $1)$(strip $3)/$(LIBRARY_PREFIX)$(strip $2)$(STATIC_LIBRARY_SUFFIX)) - # Put the libraries here. INSTALL_LIBRARIES_HERE := $(call FindLibDirForModule, $(MODULE))
diff --git a/make/nb_native/nbproject/configurations.xml b/make/nb_native/nbproject/configurations.xml index e1cff6d..fb07d54 100644 --- a/make/nb_native/nbproject/configurations.xml +++ b/make/nb_native/nbproject/configurations.xml
@@ -6142,6 +6142,9 @@ <df name="AddModuleUsesAndProvides"> <in>libAddModuleUsesAndProvidesTest.c</in> </df> + <df name="GetClassMethods"> + <in>libOverpassMethods.c</in> + </df> <df name="GetModulesInfo"> <in>libJvmtiGetAllModulesTest.c</in> </df> @@ -40143,6 +40146,11 @@ tool="0" flavor2="0"> </item> + <item path="../../test/hotspot/jtreg/serviceability/jvmti/GetClassMethods/libOverpassMethods.c" + ex="false" + tool="0" + flavor2="0"> + </item> <item path="../../test/hotspot/jtreg/serviceability/jvmti/GetModulesInfo/libJvmtiGetAllModulesTest.c" ex="false" tool="0"
diff --git a/make/scripts/compare.sh b/make/scripts/compare.sh index 8db1ae0..728de45 100644 --- a/make/scripts/compare.sh +++ b/make/scripts/compare.sh
@@ -1,6 +1,6 @@ #!/bin/bash # -# Copyright (c) 2012, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2012, 2020, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -657,7 +657,6 @@ # pdb files. PDB_DIRS="$(ls -d \ {$OTHER,$THIS}/support/modules_{cmds,libs}/{*,*/*} \ - {$OTHER,$THIS}/support/native/java.base/java_objs \ )" export _NT_SYMBOL_PATH="$(echo $PDB_DIRS | tr ' ' ';')" fi
diff --git a/make/test/JtregNativeHotspot.gmk b/make/test/JtregNativeHotspot.gmk index eef272c..bb6a0ec 100644 --- a/make/test/JtregNativeHotspot.gmk +++ b/make/test/JtregNativeHotspot.gmk
@@ -878,7 +878,7 @@ ifeq ($(OPENJDK_TARGET_OS), windows) BUILD_HOTSPOT_JTREG_EXECUTABLES_CFLAGS_exeFPRegs := -MT BUILD_HOTSPOT_JTREG_EXCLUDE += exesigtest.c libterminatedThread.c - + BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libatExit := jvm.lib else BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libbootclssearch_agent += -lpthread BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libsystemclssearch_agent += -lpthread @@ -1512,6 +1512,7 @@ BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libgetphase001 += -lpthread BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libgetphase002 += -lpthread BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libterminatedThread += -lpthread + BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libatExit += -ljvm endif $(eval $(call SetupTestFilesCompilation, BUILD_HOTSPOT_JTREG_LIBRARIES, \
diff --git a/make/test/JtregNativeJdk.gmk b/make/test/JtregNativeJdk.gmk index 2969173..f6cf7cf 100644 --- a/make/test/JtregNativeJdk.gmk +++ b/make/test/JtregNativeJdk.gmk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2015, 2018, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2015, 2021, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -48,12 +48,20 @@ BUILD_JDK_JTREG_IMAGE_DIR := $(TEST_IMAGE_DIR)/jdk/jtreg +BUILD_JDK_JTREG_EXECUTABLES_CFLAGS_exeJliLaunchTest := \ + -I$(TOPDIR)/src/java.base/share/native/libjli \ + -I$(TOPDIR)/src/java.base/$(OPENJDK_TARGET_OS_TYPE)/native/libjli \ + -I$(TOPDIR)/src/java.base/$(OPENJDK_TARGET_OS)/native/libjli \ + -DPACKAGE_PATH=\"$(PACKAGE_PATH)\" + # Platform specific setup ifeq ($(OPENJDK_TARGET_OS), windows) BUILD_JDK_JTREG_EXCLUDE += libDirectIO.c libInheritedChannel.c WIN_LIB_JAVA := $(SUPPORT_OUTPUTDIR)/native/java.base/libjava/java.lib BUILD_JDK_JTREG_LIBRARIES_LIBS_libstringPlatformChars := $(WIN_LIB_JAVA) + WIN_LIB_JLI := $(SUPPORT_OUTPUTDIR)/native/java.base/libjli/jli.lib + BUILD_JDK_JTREG_EXECUTABLES_LIBS_exeJliLaunchTest := $(WIN_LIB_JLI) else BUILD_JDK_JTREG_LIBRARIES_LIBS_libstringPlatformChars := -ljava BUILD_JDK_JTREG_LIBRARIES_LIBS_libDirectIO := -ljava @@ -62,14 +70,19 @@ else ifeq ($(OPENJDK_TARGET_OS), solaris) BUILD_JDK_JTREG_LIBRARIES_LIBS_libInheritedChannel := -ljava endif + UNIX_LDFLAGS_JLI := -L$(SUPPORT_OUTPUTDIR)/modules_libs/java.base/jli + BUILD_JDK_JTREG_EXECUTABLES_LDFLAGS_exeJliLaunchTest := $(UNIX_LDFLAGS_JLI) + BUILD_JDK_JTREG_EXECUTABLES_LIBS_exeJliLaunchTest := -ljli endif ifeq ($(OPENJDK_TARGET_OS), macosx) - BUILD_JDK_JTREG_LIBRARIES_CFLAGS_libTestMainKeyWindow := -ObjC - BUILD_JDK_JTREG_LIBRARIES_LIBS_libTestMainKeyWindow := -framework JavaVM \ - -framework Cocoa -framework JavaNativeFoundation + BUILD_JDK_JTREG_LIBRARIES_LIBS_libTestMainKeyWindow := \ + -framework Cocoa + BUILD_JDK_JTREG_LIBRARIES_LIBS_libTestDynamicStore := \ + -framework Cocoa -framework SystemConfiguration else - BUILD_JDK_JTREG_EXCLUDE += libTestMainKeyWindow.c + BUILD_JDK_JTREG_EXCLUDE += libTestMainKeyWindow.m + BUILD_JDK_JTREG_EXCLUDE += libTestDynamicStore.m endif $(eval $(call SetupTestFilesCompilation, BUILD_JDK_JTREG_LIBRARIES, \
diff --git a/make/vscode/CreateVSCodeProject.gmk b/make/vscode/CreateVSCodeProject.gmk new file mode 100644 index 0000000..8583225 --- /dev/null +++ b/make/vscode/CreateVSCodeProject.gmk
@@ -0,0 +1,113 @@ +# +# Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved. +# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. +# +# This code is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 only, as +# published by the Free Software Foundation. Oracle designates this +# particular file as subject to the "Classpath" exception as provided +# by Oracle in the LICENSE file that accompanied this code. +# +# This code is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# version 2 for more details (a copy is included in the LICENSE file that +# accompanied this code). +# +# You should have received a copy of the GNU General Public License version +# 2 along with this work; if not, write to the Free Software Foundation, +# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +# +# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +# or visit www.oracle.com if you need additional information or have any +# questions. +# + +# This must be the first rule +default: all + +include $(SPEC) +include MakeBase.gmk + +################################################################################ +# Return the full path to an indexer-specific file fragment. +# +# Param 1: Fragment name +################################################################################ +GetIndexerFragment = \ + $(TOPDIR)/make/vscode/indexers/$(VSCODE_INDEXER)-$(1).txt + +################################################################################ +# Show indexer-specific notes if they exist, otherwise do nothing +################################################################################ +ifneq (,$(wildcard $(call GetIndexerFragment,notes))) + ShowIndexerNotes = $(CAT) $(call GetIndexerFragment,notes) +else + ShowIndexerNotes = +endif + +################################################################################ +# Return the platform-dependent preferred debug engine name. +################################################################################ +ifeq ($(OPENJDK_TARGET_OS), windows) + DebugEngineName = cppvsdbg +else + DebugEngineName = cppdbg +endif + +################################################################################ +# Return an additional configuration fragment if the WORKSPACE_ROOT is different +# from TOPDIR. +################################################################################ +ifneq ($(WORKSPACE_ROOT),$(TOPDIR)) + GetExtraWorkspaceRoot = $(TOPDIR)/make/vscode/template-workspace-folder.txt +else + GetExtraWorkspaceRoot = /dev/null +endif + +################################################################################ +# Create a project configuration from a given template, replacing a known set +# of variables. +# +# Param 1: Template +# Param 2: Output +################################################################################ +define CreateFromTemplate + $(call LogInfo, Generating $2) + $(call MakeDir, $(dir $2)) + $(SED) -e '/{{INDEXER_EXTENSIONS}}/r $(call GetIndexerFragment,extensions)' \ + -e '/{{INDEXER_SETTINGS}}/r $(call GetIndexerFragment,settings)' \ + -e '/{{EXTRA_WORKSPACE_ROOT}}/r $(call GetExtraWorkspaceRoot)' $1 | \ + $(SED) -e 's!{{TOPDIR}}!$(call FixPath,$(TOPDIR))!g' \ + -e 's!{{TOPDIR_RELATIVE}}!$(call FixPath,$(strip \ + $(call RelativePath,$(OUTPUTDIR),$(TOPDIR))))!g' \ + -e 's!{{WORKSPACE_ROOT}}!$(call FixPath,$(WORKSPACE_ROOT))!g' \ + -e 's!{{OUTPUTDIR}}!$(call FixPath,$(OUTPUTDIR))!g' \ + -e 's!{{CONF_NAME}}!$(CONF_NAME)!g' \ + -e 's!{{COMPILER}}!$(call FixPath,$(CXX)) $(SYSROOT_CFLAGS)!g' \ + -e 's!{{MAKE}}!$(call FixPath,$(MAKE))!g' \ + -e 's!{{PATH}}!$(call FixPathList,$(PATH))!g' \ + -e 's!{{DEBUGENGINENAME}}!$(call DebugEngineName)!g' \ + -e '/{{INDEXER_EXTENSIONS}}/d' \ + -e '/{{INDEXER_SETTINGS}}/d' \ + -e '/{{EXTRA_WORKSPACE_ROOT}}/d' \ + > $2 +endef + +$(OUTPUTDIR)/jdk.code-workspace: + $(call LogWarn, Creating workspace $@) + $(call CreateFromTemplate, $(TOPDIR)/make/vscode/template-workspace.jsonc, $@) + $(call ShowIndexerNotes) + +$(OUTPUTDIR)/.vscode/tasks.json: + $(call CreateFromTemplate, $(TOPDIR)/make/vscode/template-tasks.jsonc, $@) + +$(OUTPUTDIR)/.vscode/launch.json: + $(call CreateFromTemplate, $(TOPDIR)/make/vscode/template-launch.jsonc, $@) + +TARGETS := $(OUTPUTDIR)/jdk.code-workspace $(OUTPUTDIR)/.vscode/tasks.json \ + $(OUTPUTDIR)/.vscode/launch.json + +all: $(TARGETS) + +.PHONY: all $(TARGETS)
diff --git a/make/vscode/indexers/ccls-extensions.txt b/make/vscode/indexers/ccls-extensions.txt new file mode 100644 index 0000000..4fdb292 --- /dev/null +++ b/make/vscode/indexers/ccls-extensions.txt
@@ -0,0 +1,2 @@ + "ms-vscode.cpptools", + "ccls-project.ccls"
diff --git a/make/vscode/indexers/ccls-notes.txt b/make/vscode/indexers/ccls-notes.txt new file mode 100644 index 0000000..674894f --- /dev/null +++ b/make/vscode/indexers/ccls-notes.txt
@@ -0,0 +1,3 @@ + +* The "ccls" indexer must be present in PATH, or configured with "ccls.launch.command" in user preferences. +
diff --git a/make/vscode/indexers/ccls-settings.txt b/make/vscode/indexers/ccls-settings.txt new file mode 100644 index 0000000..394a139 --- /dev/null +++ b/make/vscode/indexers/ccls-settings.txt
@@ -0,0 +1,28 @@ + // Configure cpptools IntelliSense + "C_Cpp.intelliSenseCachePath": "{{OUTPUTDIR}}/.vscode", + "C_Cpp.default.compileCommands": "{{OUTPUTDIR}}/compile_commands.json", + "C_Cpp.default.cppStandard": "c++03", + "C_Cpp.default.compilerPath": "{{COMPILER}}", + + // Configure ccls + "ccls.misc.compilationDatabaseDirectory": "{{TOPDIR_RELATIVE}}", + "ccls.cache.hierarchicalPath": true, + "ccls.cache.directory": "{{OUTPUTDIR}}/.vscode/ccls", + + // Avoid issues with precompiled headers + "ccls.clang.excludeArgs": [ + // Windows / MSVC + "-Fp{{OUTPUTDIR}}/hotspot/variant-server/libjvm/objs/BUILD_LIBJVM.pch", + "-Fp{{OUTPUTDIR}}/hotspot/variant-server/libjvm/gtest/objs/BUILD_GTEST_LIBJVM.pch", + "-Yuprecompiled.hpp", + // MacOS / clang + "{{OUTPUTDIR}}/hotspot/variant-server/libjvm/objs/precompiled/precompiled.hpp.pch", + "{{OUTPUTDIR}}/hotspot/variant-server/libjvm/gtest/objs/precompiled/precompiled.hpp.pch", + "-include-pch" + ], + + // Disable conflicting features from cpptools + "C_Cpp.autocomplete": "Disabled", + "C_Cpp.errorSquiggles": "Disabled", + "C_Cpp.formatting": "Disabled", + "C_Cpp.intelliSenseEngine": "Disabled",
diff --git a/make/vscode/indexers/clangd-extensions.txt b/make/vscode/indexers/clangd-extensions.txt new file mode 100644 index 0000000..06ca0d3 --- /dev/null +++ b/make/vscode/indexers/clangd-extensions.txt
@@ -0,0 +1,2 @@ + "ms-vscode.cpptools", + "llvm-vs-code-extensions.vscode-clangd"
diff --git a/make/vscode/indexers/clangd-notes.txt b/make/vscode/indexers/clangd-notes.txt new file mode 100644 index 0000000..46ff343 --- /dev/null +++ b/make/vscode/indexers/clangd-notes.txt
@@ -0,0 +1,4 @@ + +* The "clangd" indexer must be present in PATH, or configured with "clangd.path" in user preferences. +* If building with clang (default on OSX), precompiled headers must be disabled. +
diff --git a/make/vscode/indexers/clangd-settings.txt b/make/vscode/indexers/clangd-settings.txt new file mode 100644 index 0000000..b3227ce --- /dev/null +++ b/make/vscode/indexers/clangd-settings.txt
@@ -0,0 +1,17 @@ + // Configure cpptools IntelliSense + "C_Cpp.intelliSenseCachePath": "{{OUTPUTDIR}}/.vscode", + "C_Cpp.default.compileCommands": "{{OUTPUTDIR}}/compile_commands.json", + "C_Cpp.default.cppStandard": "c++03", + "C_Cpp.default.compilerPath": "{{COMPILER}}", + + // Configure clangd + "clangd.arguments": [ + "-background-index", + "-compile-commands-dir={{OUTPUTDIR}}" + ], + + // Disable conflicting features from cpptools + "C_Cpp.autocomplete": "Disabled", + "C_Cpp.errorSquiggles": "Disabled", + "C_Cpp.formatting": "Disabled", + "C_Cpp.intelliSenseEngine": "Disabled",
diff --git a/make/vscode/indexers/cpptools-extensions.txt b/make/vscode/indexers/cpptools-extensions.txt new file mode 100644 index 0000000..820e367 --- /dev/null +++ b/make/vscode/indexers/cpptools-extensions.txt
@@ -0,0 +1 @@ + "ms-vscode.cpptools"
diff --git a/make/vscode/indexers/cpptools-settings.txt b/make/vscode/indexers/cpptools-settings.txt new file mode 100644 index 0000000..155bf9c --- /dev/null +++ b/make/vscode/indexers/cpptools-settings.txt
@@ -0,0 +1,5 @@ + // Configure cpptools IntelliSense + "C_Cpp.intelliSenseCachePath": "{{OUTPUTDIR}}/.vscode", + "C_Cpp.default.compileCommands": "{{OUTPUTDIR}}/compile_commands.json", + "C_Cpp.default.cppStandard": "c++03", + "C_Cpp.default.compilerPath": "{{COMPILER}}",
diff --git a/make/vscode/indexers/rtags-extensions.txt b/make/vscode/indexers/rtags-extensions.txt new file mode 100644 index 0000000..c4b872d --- /dev/null +++ b/make/vscode/indexers/rtags-extensions.txt
@@ -0,0 +1,2 @@ + "ms-vscode.cpptools", + "jomiller.rtags-client"
diff --git a/make/vscode/indexers/rtags-settings.txt b/make/vscode/indexers/rtags-settings.txt new file mode 100644 index 0000000..7e32633 --- /dev/null +++ b/make/vscode/indexers/rtags-settings.txt
@@ -0,0 +1,14 @@ + // Configure cpptools IntelliSense + "C_Cpp.intelliSenseCachePath": "{{OUTPUTDIR}}/.vscode", + "C_Cpp.default.compileCommands": "{{OUTPUTDIR}}/compile_commands.json", + "C_Cpp.default.cppStandard": "c++03", + "C_Cpp.default.compilerPath": "{{COMPILER}}", + + // Configure RTags + "rtags.misc.compilationDatabaseDirectory": "{{OUTPUTDIR}}", + + // Disable conflicting features from cpptools + "C_Cpp.autocomplete": "Disabled", + "C_Cpp.errorSquiggles": "Disabled", + "C_Cpp.formatting": "Disabled", + "C_Cpp.intelliSenseEngine": "Disabled",
diff --git a/make/vscode/template-launch.jsonc b/make/vscode/template-launch.jsonc new file mode 100644 index 0000000..a7b3510 --- /dev/null +++ b/make/vscode/template-launch.jsonc
@@ -0,0 +1,55 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "gtestLauncher", + "type": "{{DEBUGENGINENAME}}", + "request": "launch", + "program": "{{OUTPUTDIR}}/hotspot/variant-server/libjvm/gtest/gtestLauncher", + "args": ["-jdk:{{OUTPUTDIR}}/jdk"], + "stopAtEntry": false, + "cwd": "{{WORKSPACE_ROOT}}", + "environment": [], + "externalConsole": false, + "preLaunchTask": "Make 'exploded-image'", + "osx": { + "MIMode": "lldb", + "internalConsoleOptions": "openOnSessionStart", + "args": ["--gtest_color=no", "-jdk:{{OUTPUTDIR}}/jdk"] + }, + "linux": { + "MIMode": "gdb", + "setupCommands": [ + { + "text": "handle SIGSEGV noprint nostop", + "description": "Disable stopping on signals handled by the JVM" + } + ] + } + }, + { + "name": "java", + "type": "{{DEBUGENGINENAME}}", + "request": "launch", + "program": "{{OUTPUTDIR}}/jdk/bin/java", + "stopAtEntry": false, + "cwd": "{{WORKSPACE_ROOT}}", + "environment": [], + "externalConsole": false, + "preLaunchTask": "Make 'exploded-image'", + "osx": { + "MIMode": "lldb", + "internalConsoleOptions": "openOnSessionStart", + }, + "linux": { + "MIMode": "gdb", + "setupCommands": [ + { + "text": "handle SIGSEGV noprint nostop", + "description": "Disable stopping on signals handled by the JVM" + } + ] + } + } + ] +} \ No newline at end of file
diff --git a/make/vscode/template-tasks.jsonc b/make/vscode/template-tasks.jsonc new file mode 100644 index 0000000..0b7badb --- /dev/null +++ b/make/vscode/template-tasks.jsonc
@@ -0,0 +1,55 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=733558 + // for the documentation about the tasks.json format + "version": "2.0.0", + "tasks": [ + { + "label": "Update compilation database (compile_commands.json)", + "type": "shell", + "options": { + "env": { + "PATH": "{{PATH}}" + }, + "cwd": "{{WORKSPACE_ROOT}}" + }, + "command": "{{MAKE}} CONF_NAME={{CONF_NAME}} compile-commands", + "problemMatcher": [] + }, + { + "label": "Make 'hotspot'", + "type": "shell", + "options": { + "env": { + "PATH": "{{PATH}}" + }, + "cwd": "{{WORKSPACE_ROOT}}" + }, + "command": "{{MAKE}} CONF_NAME={{CONF_NAME}} hotspot", + "problemMatcher": ["$gcc"] + }, + { + "label": "Make 'exploded-image'", + "type": "shell", + "options": { + "env": { + "PATH": "{{PATH}}" + }, + "cwd": "{{WORKSPACE_ROOT}}" + }, + "command": "{{MAKE}} CONF_NAME={{CONF_NAME}} exploded-image", + "problemMatcher": ["$gcc"] + }, + { + "label": "Make 'jdk'", + "type": "shell", + "options": { + "env": { + "PATH": "{{PATH}}" + }, + "cwd": "{{WORKSPACE_ROOT}}" + }, + "command": "{{MAKE}} CONF_NAME={{CONF_NAME}} jdk", + "problemMatcher": ["$gcc"] + } + ] +}
diff --git a/make/vscode/template-workspace-folder.txt b/make/vscode/template-workspace-folder.txt new file mode 100644 index 0000000..82c15fb --- /dev/null +++ b/make/vscode/template-workspace-folder.txt
@@ -0,0 +1,4 @@ + { + "name": "Additional sources", + "path": "{{WORKSPACE_ROOT}}" + },
diff --git a/make/vscode/template-workspace.jsonc b/make/vscode/template-workspace.jsonc new file mode 100644 index 0000000..30533c7 --- /dev/null +++ b/make/vscode/template-workspace.jsonc
@@ -0,0 +1,63 @@ +{ + "folders": [ + { + "name": "Source root", + "path": "{{TOPDIR}}" + }, + // {{EXTRA_WORKSPACE_ROOT}} + { + "name": "Build artifacts", + "path": "{{OUTPUTDIR}}" + } + ], + "extensions": { + "recommendations": [ + // {{INDEXER_EXTENSIONS}} + ] + }, + "settings": { + // {{INDEXER_SETTINGS}} + + // Additional conventions + "files.associations": { + "*.gmk": "makefile" + }, + + // Having these enabled slow down task execution + "typescript.tsc.autoDetect": "off", + "gulp.autoDetect": "off", + "npm.autoDetect": "off", + "grunt.autoDetect": "off", + "jake.autoDetect": "off", + + // Certain types of files are not relevant for the file browser + "files.exclude": { + "**/.git": true, + "**/.hg": true, + "**/.DS_Store": true, + }, + + // Files that may be interesting to browse manually, but avoided during searches + "search.exclude": { + "**/*.class": true, + "**/*.jsa": true, + "**/*.vardeps": true, + "**/*.o": true, + "**/*.obj": true, + "**/*.d": true, + "**/*.d.*": true, + "**/*_batch*": true, + "**/*.marker": true, + "**/compile-commands/": true, + "**/objs": true, + "**/launcher-objs": true, + "**/*.cmdline": true, + "**/*.log": true, + ".vscode": true, + ".clangd": true + }, + + // Trailing whitespace should never be used in this project + "files.trimTrailingWhitespace": true + } +} \ No newline at end of file
diff --git a/src/demo/share/jfc/SwingSet2/BezierAnimationPanel.java b/src/demo/share/jfc/SwingSet2/BezierAnimationPanel.java index 9cfd7d0..659a193 100644 --- a/src/demo/share/jfc/SwingSet2/BezierAnimationPanel.java +++ b/src/demo/share/jfc/SwingSet2/BezierAnimationPanel.java
@@ -1,6 +1,6 @@ /* * - * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2007, 2019, Oracle and/or its affiliates. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -43,6 +43,7 @@ import java.awt.font.*; import java.awt.geom.*; import java.awt.image.*; +import java.lang.reflect.InvocationTargetException; import java.awt.event.*; /** @@ -309,10 +310,19 @@ g2d.fill(gp); } if (g2d == BufferG2D) { - repaint(); + try { + SwingUtilities.invokeAndWait(new Runnable() { + + @Override + public void run() { + repaint(); + } + }); + } catch (InvocationTargetException | InterruptedException e) { + e.printStackTrace(); + } } ++frame; - Thread.yield(); } if (g2d != null) { g2d.dispose();
diff --git a/src/hotspot/cpu/aarch64/aarch64-asmtest.py b/src/hotspot/cpu/aarch64/aarch64-asmtest.py new file mode 100644 index 0000000..7b5eab0 --- /dev/null +++ b/src/hotspot/cpu/aarch64/aarch64-asmtest.py
@@ -0,0 +1,1177 @@ +import random + +AARCH64_AS = "as" +AARCH64_OBJDUMP = "objdump" +AARCH64_OBJCOPY = "objcopy" + +class Operand(object): + + def generate(self): + return self + +class Register(Operand): + + def generate(self): + self.number = random.randint(0, 30) + return self + + def astr(self, prefix): + return prefix + str(self.number) + +class FloatRegister(Register): + + def __str__(self): + return self.astr("v") + + def nextReg(self): + next = FloatRegister() + next.number = (self.number + 1) % 32 + return next + +class GeneralRegister(Register): + + def __str__(self): + return self.astr("r") + +class GeneralRegisterOrZr(Register): + + def generate(self): + self.number = random.randint(0, 31) + return self + + def astr(self, prefix = ""): + if (self.number == 31): + return prefix + "zr" + else: + return prefix + str(self.number) + + def __str__(self): + if (self.number == 31): + return self.astr() + else: + return self.astr("r") + +class GeneralRegisterOrSp(Register): + def generate(self): + self.number = random.randint(0, 31) + return self + + def astr(self, prefix = ""): + if (self.number == 31): + return "sp" + else: + return prefix + str(self.number) + + def __str__(self): + if (self.number == 31): + return self.astr() + else: + return self.astr("r") + +class FloatZero(Operand): + + def __str__(self): + return "0.0" + + def astr(self, ignored): + return "#0.0" + +class OperandFactory: + + _modes = {'x' : GeneralRegister, + 'w' : GeneralRegister, + 's' : FloatRegister, + 'd' : FloatRegister, + 'z' : FloatZero} + + @classmethod + def create(cls, mode): + return OperandFactory._modes[mode]() + +class ShiftKind: + + def generate(self): + self.kind = ["LSL", "LSR", "ASR"][random.randint(0,2)] + return self + + def cstr(self): + return self.kind + +class Instruction(object): + + def __init__(self, name): + self._name = name + self.isWord = name.endswith("w") | name.endswith("wi") + self.asmRegPrefix = ["x", "w"][self.isWord] + + def aname(self): + if (self._name.endswith("wi")): + return self._name[:len(self._name)-2] + else: + if (self._name.endswith("i") | self._name.endswith("w")): + return self._name[:len(self._name)-1] + else: + return self._name + + def emit(self) : + pass + + def compare(self) : + pass + + def generate(self) : + return self + + def cstr(self): + return '__ %s(' % self.name() + + def astr(self): + return '%s\t' % self.aname() + + def name(self): + name = self._name + if name == "and": + name = "andr" # Special case: the name "and" can't be used + # in HotSpot, even for a member. + return name + + def multipleForms(self): + return 0 + +class InstructionWithModes(Instruction): + + def __init__(self, name, mode): + Instruction.__init__(self, name) + self.mode = mode + self.isFloat = (mode == 'd') | (mode == 's') + if self.isFloat: + self.isWord = mode != 'd' + self.asmRegPrefix = ["d", "s"][self.isWord] + else: + self.isWord = mode != 'x' + self.asmRegPrefix = ["x", "w"][self.isWord] + + def name(self): + return self._name + (self.mode if self.mode != 'x' else '') + + def aname(self): + return (self._name+mode if (mode == 'b' or mode == 'h') + else self._name) + +class ThreeRegInstruction(Instruction): + + def generate(self): + self.reg = [GeneralRegister().generate(), GeneralRegister().generate(), + GeneralRegister().generate()] + return self + + + def cstr(self): + return (super(ThreeRegInstruction, self).cstr() + + ('%s, %s, %s' + % (self.reg[0], + self.reg[1], self.reg[2]))) + + def astr(self): + prefix = self.asmRegPrefix + return (super(ThreeRegInstruction, self).astr() + + ('%s, %s, %s' + % (self.reg[0].astr(prefix), + self.reg[1].astr(prefix), self.reg[2].astr(prefix)))) + +class FourRegInstruction(ThreeRegInstruction): + + def generate(self): + self.reg = ThreeRegInstruction.generate(self).reg + [GeneralRegister().generate()] + return self + + + def cstr(self): + return (super(FourRegInstruction, self).cstr() + + (', %s' % self.reg[3])) + + def astr(self): + prefix = self.asmRegPrefix + return (super(FourRegInstruction, self).astr() + + (', %s' % self.reg[3].astr(prefix))) + +class TwoRegInstruction(Instruction): + + def generate(self): + self.reg = [GeneralRegister().generate(), GeneralRegister().generate()] + return self + + def cstr(self): + return (super(TwoRegInstruction, self).cstr() + + '%s, %s' % (self.reg[0], + self.reg[1])) + + def astr(self): + prefix = self.asmRegPrefix + return (super(TwoRegInstruction, self).astr() + + ('%s, %s' + % (self.reg[0].astr(prefix), + self.reg[1].astr(prefix)))) + +class TwoRegImmedInstruction(TwoRegInstruction): + + def generate(self): + super(TwoRegImmedInstruction, self).generate() + self.immed = random.randint(0, 1<<11 -1) + return self + + def cstr(self): + return (super(TwoRegImmedInstruction, self).cstr() + + ', %su' % self.immed) + + def astr(self): + return (super(TwoRegImmedInstruction, self).astr() + + ', #%s' % self.immed) + +class OneRegOp(Instruction): + + def generate(self): + self.reg = GeneralRegister().generate() + return self + + def cstr(self): + return (super(OneRegOp, self).cstr() + + '%s);' % self.reg) + + def astr(self): + return (super(OneRegOp, self).astr() + + '%s' % self.reg.astr(self.asmRegPrefix)) + +class ArithOp(ThreeRegInstruction): + + def generate(self): + super(ArithOp, self).generate() + self.kind = ShiftKind().generate() + self.distance = random.randint(0, (1<<5)-1 if self.isWord else (1<<6)-1) + return self + + def cstr(self): + return ('%s, Assembler::%s, %s);' + % (ThreeRegInstruction.cstr(self), + self.kind.cstr(), self.distance)) + + def astr(self): + return ('%s, %s #%s' + % (ThreeRegInstruction.astr(self), + self.kind.cstr(), + self.distance)) + +class AddSubCarryOp(ThreeRegInstruction): + + def cstr(self): + return ('%s);' + % (ThreeRegInstruction.cstr(self))) + +class AddSubExtendedOp(ThreeRegInstruction): + + uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx = range(8) + optNames = ["uxtb", "uxth", "uxtw", "uxtx", "sxtb", "sxth", "sxtw", "sxtx"] + + def generate(self): + super(AddSubExtendedOp, self).generate() + self.amount = random.randint(1, 4) + self.option = random.randint(0, 7) + return self + + def cstr(self): + return (super(AddSubExtendedOp, self).cstr() + + (", ext::" + AddSubExtendedOp.optNames[self.option] + + ", " + str(self.amount) + ");")) + + def astr(self): + return (super(AddSubExtendedOp, self).astr() + + (", " + AddSubExtendedOp.optNames[self.option] + + " #" + str(self.amount))) + +class AddSubImmOp(TwoRegImmedInstruction): + + def cstr(self): + return super(AddSubImmOp, self).cstr() + ");" + +class LogicalImmOp(AddSubImmOp): + + # These tables are legal immediate logical operands + immediates32 \ + = [0x1, 0x3f, 0x1f0, 0x7e0, + 0x1c00, 0x3ff0, 0x8000, 0x1e000, + 0x3e000, 0x78000, 0xe0000, 0x100000, + 0x1fffe0, 0x3fe000, 0x780000, 0x7ffff8, + 0xff8000, 0x1800180, 0x1fffc00, 0x3c003c0, + 0x3ffff00, 0x7c00000, 0x7fffe00, 0xf000f00, + 0xfffe000, 0x18181818, 0x1ffc0000, 0x1ffffffe, + 0x3f003f00, 0x3fffe000, 0x60006000, 0x7f807f80, + 0x7ffffc00, 0x800001ff, 0x803fffff, 0x9f9f9f9f, + 0xc0000fff, 0xc0c0c0c0, 0xe0000000, 0xe003e003, + 0xe3ffffff, 0xf0000fff, 0xf0f0f0f0, 0xf80000ff, + 0xf83ff83f, 0xfc00007f, 0xfc1fffff, 0xfe0001ff, + 0xfe3fffff, 0xff003fff, 0xff800003, 0xff87ff87, + 0xffc00fff, 0xffe0000f, 0xffefffef, 0xfff1fff1, + 0xfff83fff, 0xfffc0fff, 0xfffe0fff, 0xffff3fff, + 0xffffc007, 0xffffe1ff, 0xfffff80f, 0xfffffe07, + 0xffffffbf, 0xfffffffd] + + immediates \ + = [0x1, 0x1f80, 0x3fff0, 0x3ffffc, + 0x3fe0000, 0x1ffc0000, 0xf8000000, 0x3ffffc000, + 0xffffffe00, 0x3ffffff800, 0xffffc00000, 0x3f000000000, + 0x7fffffff800, 0x1fe000001fe0, 0x3ffffff80000, 0xc00000000000, + 0x1ffc000000000, 0x3ffff0003ffff, 0x7ffffffe00000, 0xfffffffffc000, + 0x1ffffffffffc00, 0x3fffffffffff00, 0x7ffffffffffc00, 0xffffffffff8000, + 0x1ffffffff800000, 0x3fffffc03fffffc, 0x7fffc0000000000, 0xff80ff80ff80ff8, + 0x1c00000000000000, 0x1fffffffffff0000, 0x3fffff803fffff80, 0x7fc000007fc00000, + 0x8000000000000000, 0x803fffff803fffff, 0xc000007fc000007f, 0xe00000000000ffff, + 0xe3ffffffffffffff, 0xf007f007f007f007, 0xf80003ffffffffff, 0xfc000003fc000003, + 0xfe000000007fffff, 0xff00000000007fff, 0xff800000000003ff, 0xffc00000000000ff, + 0xffe00000000003ff, 0xfff0000000003fff, 0xfff80000001fffff, 0xfffc0000fffc0000, + 0xfffe003fffffffff, 0xffff3fffffffffff, 0xffffc0000007ffff, 0xffffe01fffffe01f, + 0xfffff800000007ff, 0xfffffc0fffffffff, 0xffffff00003fffff, 0xffffffc0000007ff, + 0xfffffff0000001ff, 0xfffffffc00003fff, 0xffffffff07ffffff, 0xffffffffe003ffff, + 0xfffffffffc01ffff, 0xffffffffffc00003, 0xfffffffffffc000f, 0xffffffffffffe07f] + + def generate(self): + AddSubImmOp.generate(self) + self.immed = \ + self.immediates32[random.randint(0, len(self.immediates32)-1)] \ + if self.isWord \ + else \ + self.immediates[random.randint(0, len(self.immediates)-1)] + + return self + + def astr(self): + return (super(TwoRegImmedInstruction, self).astr() + + ', #0x%x' % self.immed) + + def cstr(self): + return super(AddSubImmOp, self).cstr() + "ll);" + +class MultiOp(): + + def multipleForms(self): + return 3 + + def forms(self): + return ["__ pc()", "back", "forth"] + + def aforms(self): + return [".", "back", "forth"] + +class AbsOp(MultiOp, Instruction): + + def cstr(self): + return super(AbsOp, self).cstr() + "%s);" + + def astr(self): + return Instruction.astr(self) + "%s" + +class RegAndAbsOp(MultiOp, Instruction): + + def multipleForms(self): + if self.name() == "adrp": + # We can only test one form of adrp because anything other + # than "adrp ." requires relocs in the assembler output + return 1 + return 3 + + def generate(self): + Instruction.generate(self) + self.reg = GeneralRegister().generate() + return self + + def cstr(self): + if self.name() == "adrp": + return "__ _adrp(" + "%s, %s);" % (self.reg, "%s") + return (super(RegAndAbsOp, self).cstr() + + "%s, %s);" % (self.reg, "%s")) + + def astr(self): + return (super(RegAndAbsOp, self).astr() + + self.reg.astr(self.asmRegPrefix) + ", %s") + +class RegImmAbsOp(RegAndAbsOp): + + def cstr(self): + return (Instruction.cstr(self) + + "%s, %s, %s);" % (self.reg, self.immed, "%s")) + + def astr(self): + return (Instruction.astr(self) + + ("%s, #%s, %s" + % (self.reg.astr(self.asmRegPrefix), self.immed, "%s"))) + + def generate(self): + super(RegImmAbsOp, self).generate() + self.immed = random.randint(0, 1<<5 -1) + return self + +class MoveWideImmOp(RegImmAbsOp): + + def multipleForms(self): + return 0 + + def cstr(self): + return (Instruction.cstr(self) + + "%s, %s, %s);" % (self.reg, self.immed, self.shift)) + + def astr(self): + return (Instruction.astr(self) + + ("%s, #%s, lsl %s" + % (self.reg.astr(self.asmRegPrefix), + self.immed, self.shift))) + + def generate(self): + super(RegImmAbsOp, self).generate() + self.immed = random.randint(0, 1<<16 -1) + if self.isWord: + self.shift = random.randint(0, 1) * 16 + else: + self.shift = random.randint(0, 3) * 16 + return self + +class BitfieldOp(TwoRegInstruction): + + def cstr(self): + return (Instruction.cstr(self) + + ("%s, %s, %s, %s);" + % (self.reg[0], self.reg[1], self.immr, self.imms))) + + def astr(self): + return (TwoRegInstruction.astr(self) + + (", #%s, #%s" + % (self.immr, self.imms))) + + def generate(self): + TwoRegInstruction.generate(self) + self.immr = random.randint(0, 31) + self.imms = random.randint(0, 31) + return self + +class ExtractOp(ThreeRegInstruction): + + def generate(self): + super(ExtractOp, self).generate() + self.lsb = random.randint(0, (1<<5)-1 if self.isWord else (1<<6)-1) + return self + + def cstr(self): + return (ThreeRegInstruction.cstr(self) + + (", %s);" % self.lsb)) + + def astr(self): + return (ThreeRegInstruction.astr(self) + + (", #%s" % self.lsb)) + +class CondBranchOp(MultiOp, Instruction): + + def cstr(self): + return "__ br(Assembler::" + self.name() + ", %s);" + + def astr(self): + return "b." + self.name() + "\t%s" + +class ImmOp(Instruction): + + def cstr(self): + return "%s%s);" % (Instruction.cstr(self), self.immed) + + def astr(self): + return Instruction.astr(self) + "#" + str(self.immed) + + def generate(self): + self.immed = random.randint(0, 1<<16 -1) + return self + +class Op(Instruction): + + def cstr(self): + return Instruction.cstr(self) + ");" + +class SystemOp(Instruction): + + def __init__(self, op): + Instruction.__init__(self, op[0]) + self.barriers = op[1] + + def generate(self): + Instruction.generate(self) + self.barrier \ + = self.barriers[random.randint(0, len(self.barriers)-1)] + return self + + def cstr(self): + return Instruction.cstr(self) + "Assembler::" + self.barrier + ");" + + def astr(self): + return Instruction.astr(self) + self.barrier + +conditionCodes = ["EQ", "NE", "HS", "CS", "LO", "CC", "MI", "PL", "VS", \ + "VC", "HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV"] + +class ConditionalCompareOp(TwoRegImmedInstruction): + + def generate(self): + TwoRegImmedInstruction.generate(self) + self.cond = random.randint(0, 15) + self.immed = random.randint(0, 15) + return self + + def cstr(self): + return (super(ConditionalCompareOp, self).cstr() + ", " + + "Assembler::" + conditionCodes[self.cond] + ");") + + def astr(self): + return (super(ConditionalCompareOp, self).astr() + + ", " + conditionCodes[self.cond]) + +class ConditionalCompareImmedOp(Instruction): + + def generate(self): + self.reg = GeneralRegister().generate() + self.cond = random.randint(0, 15) + self.immed2 = random.randint(0, 15) + self.immed = random.randint(0, 31) + return self + + def cstr(self): + return (Instruction.cstr(self) + str(self.reg) + ", " + + str(self.immed) + ", " + + str(self.immed2) + ", " + + "Assembler::" + conditionCodes[self.cond] + ");") + + def astr(self): + return (Instruction.astr(self) + + self.reg.astr(self.asmRegPrefix) + + ", #" + str(self.immed) + + ", #" + str(self.immed2) + + ", " + conditionCodes[self.cond]) + +class TwoRegOp(TwoRegInstruction): + + def cstr(self): + return TwoRegInstruction.cstr(self) + ");" + +class ThreeRegOp(ThreeRegInstruction): + + def cstr(self): + return ThreeRegInstruction.cstr(self) + ");" + +class FourRegMulOp(FourRegInstruction): + + def cstr(self): + return FourRegInstruction.cstr(self) + ");" + + def astr(self): + isMaddsub = self.name().startswith("madd") | self.name().startswith("msub") + midPrefix = self.asmRegPrefix if isMaddsub else "w" + return (Instruction.astr(self) + + self.reg[0].astr(self.asmRegPrefix) + + ", " + self.reg[1].astr(midPrefix) + + ", " + self.reg[2].astr(midPrefix) + + ", " + self.reg[3].astr(self.asmRegPrefix)) + +class ConditionalSelectOp(ThreeRegInstruction): + + def generate(self): + ThreeRegInstruction.generate(self) + self.cond = random.randint(0, 15) + return self + + def cstr(self): + return (ThreeRegInstruction.cstr(self) + ", " + + "Assembler::" + conditionCodes[self.cond] + ");") + + def astr(self): + return (ThreeRegInstruction.astr(self) + + ", " + conditionCodes[self.cond]) + +class LoadStoreExclusiveOp(InstructionWithModes): + + def __init__(self, op): # op is a tuple of ["name", "mode", registers] + InstructionWithModes.__init__(self, op[0], op[1]) + self.num_registers = op[2] + + def astr(self): + result = self.aname() + '\t' + regs = list(self.regs) + index = regs.pop() # The last reg is the index register + prefix = ('x' if (self.mode == 'x') + & ((self.name().startswith("ld")) + | (self.name().startswith("stlr"))) # Ewww :-( + else 'w') + result = result + regs.pop(0).astr(prefix) + ", " + for s in regs: + result = result + s.astr(self.asmRegPrefix) + ", " + result = result + "[" + index.astr("x") + "]" + return result + + def cstr(self): + result = InstructionWithModes.cstr(self) + regs = list(self.regs) + index = regs.pop() # The last reg is the index register + for s in regs: + result = result + str(s) + ", " + result = result + str(index) + ");" + return result + + def appendUniqueReg(self): + result = 0 + while result == 0: + newReg = GeneralRegister().generate() + result = 1 + for i in self.regs: + result = result and (i.number != newReg.number) + self.regs.append(newReg) + + def generate(self): + self.regs = [] + for i in range(self.num_registers): + self.appendUniqueReg() + return self + + def name(self): + if self.mode == 'x': + return self._name + else: + return self._name + self.mode + + def aname(self): + if (self.mode == 'b') | (self.mode == 'h'): + return self._name + self.mode + else: + return self._name + +class Address(object): + + base_plus_unscaled_offset, pre, post, base_plus_reg, \ + base_plus_scaled_offset, pcrel, post_reg, base_only = range(8) + kinds = ["base_plus_unscaled_offset", "pre", "post", "base_plus_reg", + "base_plus_scaled_offset", "pcrel", "post_reg", "base_only"] + extend_kinds = ["uxtw", "lsl", "sxtw", "sxtx"] + + @classmethod + def kindToStr(cls, i): + return cls.kinds[i] + + def generate(self, kind, shift_distance): + self.kind = kind + self.base = GeneralRegister().generate() + self.index = GeneralRegister().generate() + self.offset = { + Address.base_plus_unscaled_offset: random.randint(-1<<8, 1<<8-1) | 1, + Address.pre: random.randint(-1<<8, 1<<8-1), + Address.post: random.randint(-1<<8, 1<<8-1), + Address.pcrel: random.randint(0, 2), + Address.base_plus_reg: 0, + Address.base_plus_scaled_offset: (random.randint(0, 1<<11-1) | (3 << 9))*8, + Address.post_reg: 0, + Address.base_only: 0} [kind] + self.offset >>= (3 - shift_distance) + self.extend_kind = Address.extend_kinds[random.randint(0, 3)] + self.shift_distance = random.randint(0, 1) * shift_distance + return self + + def __str__(self): + result = { + Address.base_plus_unscaled_offset: "Address(%s, %s)" \ + % (str(self.base), self.offset), + Address.pre: "Address(__ pre(%s, %s))" % (str(self.base), self.offset), + Address.post: "Address(__ post(%s, %s))" % (str(self.base), self.offset), + Address.post_reg: "Address(__ post(%s, %s))" % (str(self.base), self.index), + Address.base_only: "Address(%s)" % (str(self.base)), + Address.pcrel: "", + Address.base_plus_reg: "Address(%s, %s, Address::%s(%s))" \ + % (self.base, self.index, self.extend_kind, self.shift_distance), + Address.base_plus_scaled_offset: + "Address(%s, %s)" % (self.base, self.offset) } [self.kind] + if (self.kind == Address.pcrel): + result = ["__ pc()", "back", "forth"][self.offset] + return result + + def astr(self, prefix): + extend_prefix = prefix + if self.kind == Address.base_plus_reg: + if self.extend_kind.endswith("w"): + extend_prefix = "w" + result = { + Address.base_plus_unscaled_offset: "[%s, %s]" \ + % (self.base.astr(prefix), self.offset), + Address.pre: "[%s, %s]!" % (self.base.astr(prefix), self.offset), + Address.post: "[%s], %s" % (self.base.astr(prefix), self.offset), + Address.post_reg: "[%s], %s" % (self.base.astr(prefix), self.index.astr(prefix)), + Address.base_only: "[%s]" % (self.base.astr(prefix)), + Address.pcrel: "", + Address.base_plus_reg: "[%s, %s, %s #%s]" \ + % (self.base.astr(prefix), self.index.astr(extend_prefix), + self.extend_kind, self.shift_distance), + Address.base_plus_scaled_offset: \ + "[%s, %s]" \ + % (self.base.astr(prefix), self.offset) + } [self.kind] + if (self.kind == Address.pcrel): + result = [".", "back", "forth"][self.offset] + return result + +class LoadStoreOp(InstructionWithModes): + + def __init__(self, args): + name, self.asmname, self.kind, mode = args + InstructionWithModes.__init__(self, name, mode) + + def generate(self): + + # This is something of a kludge, but the offset needs to be + # scaled by the memory datamode somehow. + shift = 3 + if (self.mode == 'b') | (self.asmname.endswith("b")): + shift = 0 + elif (self.mode == 'h') | (self.asmname.endswith("h")): + shift = 1 + elif (self.mode == 'w') | (self.asmname.endswith("w")) \ + | (self.mode == 's') : + shift = 2 + + self.adr = Address().generate(self.kind, shift) + + isFloat = (self.mode == 'd') | (self.mode == 's') + + regMode = FloatRegister if isFloat else GeneralRegister + self.reg = regMode().generate() + return self + + def cstr(self): + if not(self._name.startswith("prfm")): + return "%s%s, %s);" % (Instruction.cstr(self), str(self.reg), str(self.adr)) + else: # No target register for a prefetch + return "%s%s);" % (Instruction.cstr(self), str(self.adr)) + + def astr(self): + if not(self._name.startswith("prfm")): + return "%s\t%s, %s" % (self.aname(), self.reg.astr(self.asmRegPrefix), + self.adr.astr("x")) + else: # No target register for a prefetch + return "%s %s" % (self.aname(), + self.adr.astr("x")) + + def aname(self): + result = self.asmname + # if self.kind == Address.base_plus_unscaled_offset: + # result = result.replace("ld", "ldu", 1) + # result = result.replace("st", "stu", 1) + return result + +class LoadStorePairOp(InstructionWithModes): + + numRegs = 2 + + def __init__(self, args): + name, self.asmname, self.kind, mode = args + InstructionWithModes.__init__(self, name, mode) + self.offset = random.randint(-1<<4, 1<<4-1) << 4 + + def generate(self): + self.reg = [OperandFactory.create(self.mode).generate() + for i in range(self.numRegs)] + self.base = OperandFactory.create('x').generate() + return self + + def astr(self): + address = ["[%s, #%s]", "[%s, #%s]!", "[%s], #%s"][self.kind] + address = address % (self.base.astr('x'), self.offset) + result = "%s\t%s, %s, %s" \ + % (self.asmname, + self.reg[0].astr(self.asmRegPrefix), + self.reg[1].astr(self.asmRegPrefix), address) + return result + + def cstr(self): + address = { + Address.base_plus_unscaled_offset: "Address(%s, %s)" \ + % (str(self.base), self.offset), + Address.pre: "Address(__ pre(%s, %s))" % (str(self.base), self.offset), + Address.post: "Address(__ post(%s, %s))" % (str(self.base), self.offset), + } [self.kind] + result = "__ %s(%s, %s, %s);" \ + % (self.name(), self.reg[0], self.reg[1], address) + return result + +class FloatInstruction(Instruction): + + def aname(self): + if (self._name.endswith("s") | self._name.endswith("d")): + return self._name[:len(self._name)-1] + else: + return self._name + + def __init__(self, args): + name, self.modes = args + Instruction.__init__(self, name) + + def generate(self): + self.reg = [OperandFactory.create(self.modes[i]).generate() + for i in range(self.numRegs)] + return self + + def cstr(self): + formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)] + [");"]) + return (formatStr + % tuple([Instruction.cstr(self)] + + [str(self.reg[i]) for i in range(self.numRegs)])) # Yowza + + def astr(self): + formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)]) + return (formatStr + % tuple([Instruction.astr(self)] + + [(self.reg[i].astr(self.modes[i])) for i in range(self.numRegs)])) + +class LdStSIMDOp(Instruction): + def __init__(self, args): + self._name, self.regnum, self.arrangement, self.addresskind = args + + def generate(self): + self.address = Address().generate(self.addresskind, 0) + self._firstSIMDreg = FloatRegister().generate() + if (self.addresskind == Address.post): + if (self._name in ["ld1r", "ld2r", "ld3r", "ld4r"]): + elem_size = {"8B" : 1, "16B" : 1, "4H" : 2, "8H" : 2, "2S" : 4, "4S" : 4, "1D" : 8, "2D" : 8} [self.arrangement] + self.address.offset = self.regnum * elem_size + else: + if (self.arrangement in ["8B", "4H", "2S", "1D"]): + self.address.offset = self.regnum * 8 + else: + self.address.offset = self.regnum * 16 + return self + + def cstr(self): + buf = super(LdStSIMDOp, self).cstr() + str(self._firstSIMDreg) + current = self._firstSIMDreg + for cnt in range(1, self.regnum): + buf = '%s, %s' % (buf, current.nextReg()) + current = current.nextReg() + return '%s, __ T%s, %s);' % (buf, self.arrangement, str(self.address)) + + def astr(self): + buf = '%s\t{%s.%s' % (self._name, self._firstSIMDreg, self.arrangement) + current = self._firstSIMDreg + for cnt in range(1, self.regnum): + buf = '%s, %s.%s' % (buf, current.nextReg(), self.arrangement) + current = current.nextReg() + return '%s}, %s' % (buf, self.address.astr("x")) + + def aname(self): + return self._name + +class LSEOp(Instruction): + def __init__(self, args): + self._name, self.asmname, self.size, self.suffix = args + + def generate(self): + self._name = "%s%s" % (self._name, self.suffix) + self.asmname = "%s%s" % (self.asmname, self.suffix) + self.srcReg = GeneralRegisterOrZr().generate() + self.tgtReg = GeneralRegisterOrZr().generate() + self.adrReg = GeneralRegisterOrSp().generate() + + return self + + def cstr(self): + sizeSpec = {"x" : "Assembler::xword", "w" : "Assembler::word"} [self.size] + return super(LSEOp, self).cstr() + "%s, %s, %s, %s);" % (sizeSpec, self.srcReg, self.tgtReg, self.adrReg) + + def astr(self): + return "%s\t%s, %s, [%s]" % (self.asmname, self.srcReg.astr(self.size), self.tgtReg.astr(self.size), self.adrReg.astr("x")) + + def aname(self): + return self.asmname + +class TwoRegFloatOp(FloatInstruction): + numRegs = 2 + +class ThreeRegFloatOp(TwoRegFloatOp): + numRegs = 3 + +class FourRegFloatOp(TwoRegFloatOp): + numRegs = 4 + +class FloatConvertOp(TwoRegFloatOp): + + def __init__(self, args): + self._cname, self._aname, modes = args + TwoRegFloatOp.__init__(self, [self._cname, modes]) + + def aname(self): + return self._aname + + def cname(self): + return self._cname + +class SpecialCases(Instruction): + def __init__(self, data): + self._name = data[0] + self._cstr = data[1] + self._astr = data[2] + + def cstr(self): + return self._cstr + + def astr(self): + return self._astr + +def generate(kind, names): + outfile.write("# " + kind.__name__ + "\n"); + print "\n// " + kind.__name__ + for name in names: + for i in range(1): + op = kind(name).generate() + if op.multipleForms(): + forms = op.forms() + aforms = op.aforms() + for i in range(op.multipleForms()): + cstr = op.cstr() % forms[i] + astr = op.astr() % aforms[i] + print " %-50s //\t%s" % (cstr, astr) + outfile.write("\t" + astr + "\n") + else: + print " %-50s //\t%s" % (op.cstr(), op.astr()) + outfile.write("\t" + op.astr() + "\n") + +outfile = open("aarch64ops.s", "w") + +print "// BEGIN Generated code -- do not edit" +print "// Generated by aarch64-asmtest.py" + +print " Label back, forth;" +print " __ bind(back);" + +outfile.write("back:\n") + +generate (ArithOp, + [ "add", "sub", "adds", "subs", + "addw", "subw", "addsw", "subsw", + "and", "orr", "eor", "ands", + "andw", "orrw", "eorw", "andsw", + "bic", "orn", "eon", "bics", + "bicw", "ornw", "eonw", "bicsw" ]) + +generate (AddSubImmOp, + [ "addw", "addsw", "subw", "subsw", + "add", "adds", "sub", "subs"]) +generate (LogicalImmOp, + [ "andw", "orrw", "eorw", "andsw", + "and", "orr", "eor", "ands"]) + +generate (AbsOp, [ "b", "bl" ]) + +generate (RegAndAbsOp, ["cbzw", "cbnzw", "cbz", "cbnz", "adr", "adrp"]) + +generate (RegImmAbsOp, ["tbz", "tbnz"]) + +generate (MoveWideImmOp, ["movnw", "movzw", "movkw", "movn", "movz", "movk"]) + +generate (BitfieldOp, ["sbfm", "bfmw", "ubfmw", "sbfm", "bfm", "ubfm"]) + +generate (ExtractOp, ["extrw", "extr"]) + +generate (CondBranchOp, ["EQ", "NE", "HS", "CS", "LO", "CC", "MI", "PL", "VS", "VC", + "HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV" ]) + +generate (ImmOp, ["svc", "hvc", "smc", "brk", "hlt", # "dpcs1", "dpcs2", "dpcs3" + ]) + +generate (Op, ["nop", "eret", "drps", "isb"]) + +barriers = ["OSHLD", "OSHST", "OSH", "NSHLD", "NSHST", "NSH", + "ISHLD", "ISHST", "ISH", "LD", "ST", "SY"] + +generate (SystemOp, [["dsb", barriers], ["dmb", barriers]]) + +generate (OneRegOp, ["br", "blr"]) + +for mode in 'xwhb': + generate (LoadStoreExclusiveOp, [["stxr", mode, 3], ["stlxr", mode, 3], + ["ldxr", mode, 2], ["ldaxr", mode, 2], + ["stlr", mode, 2], ["ldar", mode, 2]]) + +for mode in 'xw': + generate (LoadStoreExclusiveOp, [["ldxp", mode, 3], ["ldaxp", mode, 3], + ["stxp", mode, 4], ["stlxp", mode, 4]]) + +for kind in range(6): + print "\n// " + Address.kindToStr(kind), + if kind != Address.pcrel: + generate (LoadStoreOp, + [["str", "str", kind, "x"], ["str", "str", kind, "w"], + ["str", "strb", kind, "b"], ["str", "strh", kind, "h"], + ["ldr", "ldr", kind, "x"], ["ldr", "ldr", kind, "w"], + ["ldr", "ldrb", kind, "b"], ["ldr", "ldrh", kind, "h"], + ["ldrsb", "ldrsb", kind, "x"], ["ldrsh", "ldrsh", kind, "x"], + ["ldrsh", "ldrsh", kind, "w"], ["ldrsw", "ldrsw", kind, "x"], + ["ldr", "ldr", kind, "d"], ["ldr", "ldr", kind, "s"], + ["str", "str", kind, "d"], ["str", "str", kind, "s"], + ]) + else: + generate (LoadStoreOp, + [["ldr", "ldr", kind, "x"], ["ldr", "ldr", kind, "w"]]) + + +for kind in (Address.base_plus_unscaled_offset, Address.pcrel, Address.base_plus_reg, \ + Address.base_plus_scaled_offset): + generate (LoadStoreOp, + [["prfm", "prfm\tPLDL1KEEP,", kind, "x"]]) + +generate(AddSubCarryOp, ["adcw", "adcsw", "sbcw", "sbcsw", "adc", "adcs", "sbc", "sbcs"]) + +generate(AddSubExtendedOp, ["addw", "addsw", "sub", "subsw", "add", "adds", "sub", "subs"]) + +generate(ConditionalCompareOp, ["ccmnw", "ccmpw", "ccmn", "ccmp"]) +generate(ConditionalCompareImmedOp, ["ccmnw", "ccmpw", "ccmn", "ccmp"]) +generate(ConditionalSelectOp, + ["cselw", "csincw", "csinvw", "csnegw", "csel", "csinc", "csinv", "csneg"]) + +generate(TwoRegOp, + ["rbitw", "rev16w", "revw", "clzw", "clsw", "rbit", + "rev16", "rev32", "rev", "clz", "cls"]) +generate(ThreeRegOp, + ["udivw", "sdivw", "lslvw", "lsrvw", "asrvw", "rorvw", "udiv", "sdiv", + "lslv", "lsrv", "asrv", "rorv", "umulh", "smulh"]) +generate(FourRegMulOp, + ["maddw", "msubw", "madd", "msub", "smaddl", "smsubl", "umaddl", "umsubl"]) + +generate(ThreeRegFloatOp, + [["fmuls", "sss"], ["fdivs", "sss"], ["fadds", "sss"], ["fsubs", "sss"], + ["fmuls", "sss"], + ["fmuld", "ddd"], ["fdivd", "ddd"], ["faddd", "ddd"], ["fsubd", "ddd"], + ["fmuld", "ddd"]]) + +generate(FourRegFloatOp, + [["fmadds", "ssss"], ["fmsubs", "ssss"], ["fnmadds", "ssss"], ["fnmadds", "ssss"], + ["fmaddd", "dddd"], ["fmsubd", "dddd"], ["fnmaddd", "dddd"], ["fnmaddd", "dddd"],]) + +generate(TwoRegFloatOp, + [["fmovs", "ss"], ["fabss", "ss"], ["fnegs", "ss"], ["fsqrts", "ss"], + ["fcvts", "ds"], + ["fmovd", "dd"], ["fabsd", "dd"], ["fnegd", "dd"], ["fsqrtd", "dd"], + ["fcvtd", "sd"], + ]) + +generate(FloatConvertOp, [["fcvtzsw", "fcvtzs", "ws"], ["fcvtzs", "fcvtzs", "xs"], + ["fcvtzdw", "fcvtzs", "wd"], ["fcvtzd", "fcvtzs", "xd"], + ["scvtfws", "scvtf", "sw"], ["scvtfs", "scvtf", "sx"], + ["scvtfwd", "scvtf", "dw"], ["scvtfd", "scvtf", "dx"], + ["fmovs", "fmov", "ws"], ["fmovd", "fmov", "xd"], + ["fmovs", "fmov", "sw"], ["fmovd", "fmov", "dx"]]) + +generate(TwoRegFloatOp, [["fcmps", "ss"], ["fcmpd", "dd"], + ["fcmps", "sz"], ["fcmpd", "dz"]]) + +for kind in range(3): + generate(LoadStorePairOp, [["stp", "stp", kind, "w"], ["ldp", "ldp", kind, "w"], + ["ldpsw", "ldpsw", kind, "x"], + ["stp", "stp", kind, "x"], ["ldp", "ldp", kind, "x"] + ]) +generate(LoadStorePairOp, [["stnp", "stnp", 0, "w"], ["ldnp", "ldnp", 0, "w"], + ["stnp", "stnp", 0, "x"], ["ldnp", "ldnp", 0, "x"]]) + +generate(LdStSIMDOp, [["ld1", 1, "8B", Address.base_only], + ["ld1", 2, "16B", Address.post], + ["ld1", 3, "1D", Address.post_reg], + ["ld1", 4, "8H", Address.post], + ["ld1r", 1, "8B", Address.base_only], + ["ld1r", 1, "4S", Address.post], + ["ld1r", 1, "1D", Address.post_reg], + ["ld2", 2, "2D", Address.base_only], + ["ld2", 2, "4H", Address.post], + ["ld2r", 2, "16B", Address.base_only], + ["ld2r", 2, "2S", Address.post], + ["ld2r", 2, "2D", Address.post_reg], + ["ld3", 3, "4S", Address.post_reg], + ["ld3", 3, "2S", Address.base_only], + ["ld3r", 3, "8H", Address.base_only], + ["ld3r", 3, "4S", Address.post], + ["ld3r", 3, "1D", Address.post_reg], + ["ld4", 4, "8H", Address.post], + ["ld4", 4, "8B", Address.post_reg], + ["ld4r", 4, "8B", Address.base_only], + ["ld4r", 4, "4H", Address.post], + ["ld4r", 4, "2S", Address.post_reg], +]) + +generate(SpecialCases, [["ccmn", "__ ccmn(zr, zr, 3u, Assembler::LE);", "ccmn\txzr, xzr, #3, LE"], + ["ccmnw", "__ ccmnw(zr, zr, 5u, Assembler::EQ);", "ccmn\twzr, wzr, #5, EQ"], + ["ccmp", "__ ccmp(zr, 1, 4u, Assembler::NE);", "ccmp\txzr, 1, #4, NE"], + ["ccmpw", "__ ccmpw(zr, 2, 2, Assembler::GT);", "ccmp\twzr, 2, #2, GT"], + ["extr", "__ extr(zr, zr, zr, 0);", "extr\txzr, xzr, xzr, 0"], + ["stlxp", "__ stlxp(r0, zr, zr, sp);", "stlxp\tw0, xzr, xzr, [sp]"], + ["stlxpw", "__ stlxpw(r2, zr, zr, r3);", "stlxp\tw2, wzr, wzr, [x3]"], + ["stxp", "__ stxp(r4, zr, zr, r5);", "stxp\tw4, xzr, xzr, [x5]"], + ["stxpw", "__ stxpw(r6, zr, zr, sp);", "stxp\tw6, wzr, wzr, [sp]"], + ["dup", "__ dup(v0, __ T16B, zr);", "dup\tv0.16b, wzr"], + ["mov", "__ mov(v1, __ T1D, 0, zr);", "mov\tv1.d[0], xzr"], + ["mov", "__ mov(v1, __ T2S, 1, zr);", "mov\tv1.s[1], wzr"], + ["mov", "__ mov(v1, __ T4H, 2, zr);", "mov\tv1.h[2], wzr"], + ["mov", "__ mov(v1, __ T8B, 3, zr);", "mov\tv1.b[3], wzr"], + ["ld1", "__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0)));", "ld1\t{v31.2d, v0.2d}, [x1], x0"]]) + +print "\n// FloatImmediateOp" +for float in ("2.0", "2.125", "4.0", "4.25", "8.0", "8.5", "16.0", "17.0", "0.125", + "0.1328125", "0.25", "0.265625", "0.5", "0.53125", "1.0", "1.0625", + "-2.0", "-2.125", "-4.0", "-4.25", "-8.0", "-8.5", "-16.0", "-17.0", + "-0.125", "-0.1328125", "-0.25", "-0.265625", "-0.5", "-0.53125", "-1.0", "-1.0625"): + astr = "fmov d0, #" + float + cstr = "__ fmovd(v0, " + float + ");" + print " %-50s //\t%s" % (cstr, astr) + outfile.write("\t" + astr + "\n") + +# ARMv8.1A +for size in ("x", "w"): + for suffix in ("", "a", "al", "l"): + generate(LSEOp, [["swp", "swp", size, suffix], + ["ldadd", "ldadd", size, suffix], + ["ldbic", "ldclr", size, suffix], + ["ldeor", "ldeor", size, suffix], + ["ldorr", "ldset", size, suffix], + ["ldsmin", "ldsmin", size, suffix], + ["ldsmax", "ldsmax", size, suffix], + ["ldumin", "ldumin", size, suffix], + ["ldumax", "ldumax", size, suffix]]); + +print "\n __ bind(forth);" +outfile.write("forth:\n") + +outfile.close() + +import subprocess +import sys + +# compile for 8.1 because of lse atomics +subprocess.check_call([AARCH64_AS, "-march=armv8.1-a", "aarch64ops.s", "-o", "aarch64ops.o"]) + +print +print "/*", +sys.stdout.flush() +subprocess.check_call([AARCH64_OBJDUMP, "-d", "aarch64ops.o"]) +print "*/" + +subprocess.check_call([AARCH64_OBJCOPY, "-O", "binary", "-j", ".text", "aarch64ops.o", "aarch64ops.bin"]) + +infile = open("aarch64ops.bin", "r") +bytes = bytearray(infile.read()) + +print +print " static const unsigned int insns[] =" +print " {" + +i = 0 +while i < len(bytes): + print " 0x%02x%02x%02x%02x," % (bytes[i+3], bytes[i+2], bytes[i+1], bytes[i]), + i += 4 + if i%16 == 0: + print +print "\n };" +print "// END Generated code -- do not edit" + +
diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad index 98ffd67..d4ae8da 100644 --- a/src/hotspot/cpu/aarch64/aarch64.ad +++ b/src/hotspot/cpu/aarch64/aarch64.ad
@@ -201,43 +201,43 @@ reg_def V7_J ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(2) ); reg_def V7_K ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(3) ); - reg_def V8 ( SOC, SOC, Op_RegF, 8, v8->as_VMReg() ); - reg_def V8_H ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next() ); + reg_def V8 ( SOC, SOE, Op_RegF, 8, v8->as_VMReg() ); + reg_def V8_H ( SOC, SOE, Op_RegF, 8, v8->as_VMReg()->next() ); reg_def V8_J ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(2) ); reg_def V8_K ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(3) ); - reg_def V9 ( SOC, SOC, Op_RegF, 9, v9->as_VMReg() ); - reg_def V9_H ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next() ); + reg_def V9 ( SOC, SOE, Op_RegF, 9, v9->as_VMReg() ); + reg_def V9_H ( SOC, SOE, Op_RegF, 9, v9->as_VMReg()->next() ); reg_def V9_J ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(2) ); reg_def V9_K ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(3) ); - reg_def V10 ( SOC, SOC, Op_RegF, 10, v10->as_VMReg() ); - reg_def V10_H( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next() ); + reg_def V10 ( SOC, SOE, Op_RegF, 10, v10->as_VMReg() ); + reg_def V10_H( SOC, SOE, Op_RegF, 10, v10->as_VMReg()->next() ); reg_def V10_J( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(2)); reg_def V10_K( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(3)); - reg_def V11 ( SOC, SOC, Op_RegF, 11, v11->as_VMReg() ); - reg_def V11_H( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next() ); + reg_def V11 ( SOC, SOE, Op_RegF, 11, v11->as_VMReg() ); + reg_def V11_H( SOC, SOE, Op_RegF, 11, v11->as_VMReg()->next() ); reg_def V11_J( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(2)); reg_def V11_K( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(3)); - reg_def V12 ( SOC, SOC, Op_RegF, 12, v12->as_VMReg() ); - reg_def V12_H( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next() ); + reg_def V12 ( SOC, SOE, Op_RegF, 12, v12->as_VMReg() ); + reg_def V12_H( SOC, SOE, Op_RegF, 12, v12->as_VMReg()->next() ); reg_def V12_J( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(2)); reg_def V12_K( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(3)); - reg_def V13 ( SOC, SOC, Op_RegF, 13, v13->as_VMReg() ); - reg_def V13_H( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next() ); + reg_def V13 ( SOC, SOE, Op_RegF, 13, v13->as_VMReg() ); + reg_def V13_H( SOC, SOE, Op_RegF, 13, v13->as_VMReg()->next() ); reg_def V13_J( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(2)); reg_def V13_K( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(3)); - reg_def V14 ( SOC, SOC, Op_RegF, 14, v14->as_VMReg() ); - reg_def V14_H( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next() ); + reg_def V14 ( SOC, SOE, Op_RegF, 14, v14->as_VMReg() ); + reg_def V14_H( SOC, SOE, Op_RegF, 14, v14->as_VMReg()->next() ); reg_def V14_J( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(2)); reg_def V14_K( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(3)); - reg_def V15 ( SOC, SOC, Op_RegF, 15, v15->as_VMReg() ); - reg_def V15_H( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next() ); + reg_def V15 ( SOC, SOE, Op_RegF, 15, v15->as_VMReg() ); + reg_def V15_H( SOC, SOE, Op_RegF, 15, v15->as_VMReg()->next() ); reg_def V15_J( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(2)); reg_def V15_K( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(3)); @@ -996,6 +996,7 @@ source_hpp %{ #include "asm/macroAssembler.hpp" +#include "gc/shared/barrierSetAssembler.hpp" #include "gc/shared/cardTable.hpp" #include "gc/shared/cardTableBarrierSet.hpp" #include "gc/shared/collectedHeap.hpp" @@ -1036,20 +1037,7 @@ } }; - // graph traversal helpers - - MemBarNode *parent_membar(const Node *n); - MemBarNode *child_membar(const MemBarNode *n); - bool leading_membar(const MemBarNode *barrier); - - bool is_card_mark_membar(const MemBarNode *barrier); - bool is_CAS(int opcode); - - MemBarNode *leading_to_normal(MemBarNode *leading); - MemBarNode *normal_to_leading(const MemBarNode *barrier); - MemBarNode *card_mark_to_trailing(const MemBarNode *barrier); - MemBarNode *trailing_to_card_mark(const MemBarNode *trailing); - MemBarNode *trailing_to_leading(const MemBarNode *trailing); + bool is_CAS(int opcode, bool maybe_volatile); // predicates controlling emit of ldr<x>/ldar<x> and associated dmb @@ -1272,611 +1260,12 @@ // relevant dmb instructions. // - // graph traversal helpers used for volatile put/get and CAS - // optimization - - // 1) general purpose helpers - - // if node n is linked to a parent MemBarNode by an intervening - // Control and Memory ProjNode return the MemBarNode otherwise return - // NULL. - // - // n may only be a Load or a MemBar. - - MemBarNode *parent_membar(const Node *n) - { - Node *ctl = NULL; - Node *mem = NULL; - Node *membar = NULL; - - if (n->is_Load()) { - ctl = n->lookup(LoadNode::Control); - mem = n->lookup(LoadNode::Memory); - } else if (n->is_MemBar()) { - ctl = n->lookup(TypeFunc::Control); - mem = n->lookup(TypeFunc::Memory); - } else { - return NULL; - } - - if (!ctl || !mem || !ctl->is_Proj() || !mem->is_Proj()) { - return NULL; - } - - membar = ctl->lookup(0); - - if (!membar || !membar->is_MemBar()) { - return NULL; - } - - if (mem->lookup(0) != membar) { - return NULL; - } - - return membar->as_MemBar(); - } - - // if n is linked to a child MemBarNode by intervening Control and - // Memory ProjNodes return the MemBarNode otherwise return NULL. - - MemBarNode *child_membar(const MemBarNode *n) - { - ProjNode *ctl = n->proj_out_or_null(TypeFunc::Control); - ProjNode *mem = n->proj_out_or_null(TypeFunc::Memory); - - // MemBar needs to have both a Ctl and Mem projection - if (! ctl || ! mem) - return NULL; - - MemBarNode *child = NULL; - Node *x; - - for (DUIterator_Fast imax, i = ctl->fast_outs(imax); i < imax; i++) { - x = ctl->fast_out(i); - // if we see a membar we keep hold of it. we may also see a new - // arena copy of the original but it will appear later - if (x->is_MemBar()) { - child = x->as_MemBar(); - break; - } - } - - if (child == NULL) { - return NULL; - } - - for (DUIterator_Fast imax, i = mem->fast_outs(imax); i < imax; i++) { - x = mem->fast_out(i); - // if we see a membar we keep hold of it. we may also see a new - // arena copy of the original but it will appear later - if (x == child) { - return child; - } - } - return NULL; - } - - // helper predicate use to filter candidates for a leading memory - // barrier - // - // returns true if barrier is a MemBarRelease or a MemBarCPUOrder - // whose Ctl and Mem feeds come from a MemBarRelease otherwise false - - bool leading_membar(const MemBarNode *barrier) - { - int opcode = barrier->Opcode(); - // if this is a release membar we are ok - if (opcode == Op_MemBarRelease) { - return true; - } - // if its a cpuorder membar . . . - if (opcode != Op_MemBarCPUOrder) { - return false; - } - // then the parent has to be a release membar - MemBarNode *parent = parent_membar(barrier); - if (!parent) { - return false; - } - opcode = parent->Opcode(); - return opcode == Op_MemBarRelease; - } - - // 2) card mark detection helper - - // helper predicate which can be used to detect a volatile membar - // introduced as part of a conditional card mark sequence either by - // G1 or by CMS when UseCondCardMark is true. - // - // membar can be definitively determined to be part of a card mark - // sequence if and only if all the following hold - // - // i) it is a MemBarVolatile - // - // ii) either UseG1GC or (UseConcMarkSweepGC && UseCondCardMark) is - // true - // - // iii) the node's Mem projection feeds a StoreCM node. - - bool is_card_mark_membar(const MemBarNode *barrier) - { - if (!UseG1GC && !(UseConcMarkSweepGC && UseCondCardMark)) { - return false; - } - - if (barrier->Opcode() != Op_MemBarVolatile) { - return false; - } - - ProjNode *mem = barrier->proj_out(TypeFunc::Memory); - - for (DUIterator_Fast imax, i = mem->fast_outs(imax); i < imax ; i++) { - Node *y = mem->fast_out(i); - if (y->Opcode() == Op_StoreCM) { - return true; - } - } - - return false; - } - - - // 3) helper predicates to traverse volatile put or CAS graphs which - // may contain GC barrier subgraphs - - // Preamble - // -------- - // - // for volatile writes we can omit generating barriers and employ a - // releasing store when we see a node sequence sequence with a - // leading MemBarRelease and a trailing MemBarVolatile as follows - // - // MemBarRelease - // { || } -- optional - // {MemBarCPUOrder} - // || \\ - // || StoreX[mo_release] - // | \ / - // | MergeMem - // | / - // {MemBarCPUOrder} -- optional - // { || } - // MemBarVolatile - // - // where - // || and \\ represent Ctl and Mem feeds via Proj nodes - // | \ and / indicate further routing of the Ctl and Mem feeds - // - // this is the graph we see for non-object stores. however, for a - // volatile Object store (StoreN/P) we may see other nodes below the - // leading membar because of the need for a GC pre- or post-write - // barrier. - // - // with most GC configurations we with see this simple variant which - // includes a post-write barrier card mark. - // - // MemBarRelease______________________________ - // || \\ Ctl \ \\ - // || StoreN/P[mo_release] CastP2X StoreB/CM - // | \ / . . . / - // | MergeMem - // | / - // || / - // {MemBarCPUOrder} -- optional - // { || } - // MemBarVolatile - // - // i.e. the leading membar feeds Ctl to a CastP2X (which converts - // the object address to an int used to compute the card offset) and - // Ctl+Mem to a StoreB node (which does the actual card mark). - // - // n.b. a StoreCM node will only appear in this configuration when - // using CMS or G1. StoreCM differs from a normal card mark write (StoreB) - // because it implies a requirement to order visibility of the card - // mark (StoreCM) relative to the object put (StoreP/N) using a - // StoreStore memory barrier (arguably this ought to be represented - // explicitly in the ideal graph but that is not how it works). This - // ordering is required for both non-volatile and volatile - // puts. Normally that means we need to translate a StoreCM using - // the sequence - // - // dmb ishst - // strb - // - // However, when using G1 or CMS with conditional card marking (as - // we shall see) we don't need to insert the dmb when translating - // StoreCM because there is already an intervening StoreLoad barrier - // between it and the StoreP/N. - // - // It is also possible to perform the card mark conditionally on it - // currently being unmarked in which case the volatile put graph - // will look slightly different - // - // MemBarRelease____________________________________________ - // || \\ Ctl \ Ctl \ \\ Mem \ - // || StoreN/P[mo_release] CastP2X If LoadB | - // | \ / \ | - // | MergeMem . . . StoreB - // | / / - // || / - // MemBarVolatile - // - // It is worth noting at this stage that both the above - // configurations can be uniquely identified by checking that the - // memory flow includes the following subgraph: - // - // MemBarRelease - // {MemBarCPUOrder} - // | \ . . . - // | StoreX[mo_release] . . . - // | / - // MergeMem - // | - // {MemBarCPUOrder} - // MemBarVolatile - // - // This is referred to as a *normal* subgraph. It can easily be - // detected starting from any candidate MemBarRelease, - // StoreX[mo_release] or MemBarVolatile. - // - // A simple variation on this normal case occurs for an unsafe CAS - // operation. The basic graph for a non-object CAS is - // - // MemBarRelease - // || - // MemBarCPUOrder - // || \\ . . . - // || CompareAndSwapX - // || | - // || SCMemProj - // | \ / - // | MergeMem - // | / - // MemBarCPUOrder - // || - // MemBarAcquire - // - // The same basic variations on this arrangement (mutatis mutandis) - // occur when a card mark is introduced. i.e. we se the same basic - // shape but the StoreP/N is replaced with CompareAndSawpP/N and the - // tail of the graph is a pair comprising a MemBarCPUOrder + - // MemBarAcquire. - // - // So, in the case of a CAS the normal graph has the variant form - // - // MemBarRelease - // MemBarCPUOrder - // | \ . . . - // | CompareAndSwapX . . . - // | | - // | SCMemProj - // | / . . . - // MergeMem - // | - // MemBarCPUOrder - // MemBarAcquire - // - // This graph can also easily be detected starting from any - // candidate MemBarRelease, CompareAndSwapX or MemBarAcquire. - // - // the code below uses two helper predicates, leading_to_normal and - // normal_to_leading to identify these normal graphs, one validating - // the layout starting from the top membar and searching down and - // the other validating the layout starting from the lower membar - // and searching up. - // - // There are two special case GC configurations when a normal graph - // may not be generated: when using G1 (which always employs a - // conditional card mark); and when using CMS with conditional card - // marking configured. These GCs are both concurrent rather than - // stop-the world GCs. So they introduce extra Ctl+Mem flow into the - // graph between the leading and trailing membar nodes, in - // particular enforcing stronger memory serialisation beween the - // object put and the corresponding conditional card mark. CMS - // employs a post-write GC barrier while G1 employs both a pre- and - // post-write GC barrier. Of course the extra nodes may be absent -- - // they are only inserted for object puts/swaps. This significantly - // complicates the task of identifying whether a MemBarRelease, - // StoreX[mo_release] or MemBarVolatile forms part of a volatile put - // when using these GC configurations (see below). It adds similar - // complexity to the task of identifying whether a MemBarRelease, - // CompareAndSwapX or MemBarAcquire forms part of a CAS. - // - // In both cases the post-write subtree includes an auxiliary - // MemBarVolatile (StoreLoad barrier) separating the object put/swap - // and the read of the corresponding card. This poses two additional - // problems. - // - // Firstly, a card mark MemBarVolatile needs to be distinguished - // from a normal trailing MemBarVolatile. Resolving this first - // problem is straightforward: a card mark MemBarVolatile always - // projects a Mem feed to a StoreCM node and that is a unique marker - // - // MemBarVolatile (card mark) - // C | \ . . . - // | StoreCM . . . - // . . . - // - // The second problem is how the code generator is to translate the - // card mark barrier? It always needs to be translated to a "dmb - // ish" instruction whether or not it occurs as part of a volatile - // put. A StoreLoad barrier is needed after the object put to ensure - // i) visibility to GC threads of the object put and ii) visibility - // to the mutator thread of any card clearing write by a GC - // thread. Clearly a normal store (str) will not guarantee this - // ordering but neither will a releasing store (stlr). The latter - // guarantees that the object put is visible but does not guarantee - // that writes by other threads have also been observed. - // - // So, returning to the task of translating the object put and the - // leading/trailing membar nodes: what do the non-normal node graph - // look like for these 2 special cases? and how can we determine the - // status of a MemBarRelease, StoreX[mo_release] or MemBarVolatile - // in both normal and non-normal cases? - // - // A CMS GC post-barrier wraps its card write (StoreCM) inside an If - // which selects conditonal execution based on the value loaded - // (LoadB) from the card. Ctl and Mem are fed to the If via an - // intervening StoreLoad barrier (MemBarVolatile). - // - // So, with CMS we may see a node graph for a volatile object store - // which looks like this - // - // MemBarRelease - // {MemBarCPUOrder}_(leading)_________________ - // C | M \ \\ C \ - // | \ StoreN/P[mo_release] CastP2X - // | Bot \ / - // | MergeMem - // | / - // MemBarVolatile (card mark) - // C | || M | - // | LoadB | - // | | | - // | Cmp |\ - // | / | \ - // If | \ - // | \ | \ - // IfFalse IfTrue | \ - // \ / \ | \ - // \ / StoreCM | - // \ / | | - // Region . . . | - // | \ / - // | . . . \ / Bot - // | MergeMem - // | | - // {MemBarCPUOrder} - // MemBarVolatile (trailing) - // - // The first MergeMem merges the AliasIdxBot Mem slice from the - // leading membar and the oopptr Mem slice from the Store into the - // card mark membar. The trailing MergeMem merges the AliasIdxBot - // Mem slice from the card mark membar and the AliasIdxRaw slice - // from the StoreCM into the trailing membar (n.b. the latter - // proceeds via a Phi associated with the If region). - // - // The graph for a CAS varies slightly, the difference being - // that the StoreN/P node is replaced by a CompareAndSwapP/N node - // and the trailing MemBarVolatile by a MemBarCPUOrder + - // MemBarAcquire pair (also the MemBarCPUOrder nodes are not optional). - // - // MemBarRelease - // MemBarCPUOrder_(leading)_______________ - // C | M \ \\ C \ - // | \ CompareAndSwapN/P CastP2X - // | \ | - // | \ SCMemProj - // | Bot \ / - // | MergeMem - // | / - // MemBarVolatile (card mark) - // C | || M | - // | LoadB | - // | | | - // | Cmp |\ - // | / | \ - // If | \ - // | \ | \ - // IfFalse IfTrue | \ - // \ / \ | \ - // \ / StoreCM | - // \ / | | - // Region . . . | - // | \ / - // | . . . \ / Bot - // | MergeMem - // | | - // MemBarCPUOrder - // MemBarVolatile (trailing) - // - // - // G1 is quite a lot more complicated. The nodes inserted on behalf - // of G1 may comprise: a pre-write graph which adds the old value to - // the SATB queue; the releasing store itself; and, finally, a - // post-write graph which performs a card mark. - // - // The pre-write graph may be omitted, but only when the put is - // writing to a newly allocated (young gen) object and then only if - // there is a direct memory chain to the Initialize node for the - // object allocation. This will not happen for a volatile put since - // any memory chain passes through the leading membar. - // - // The pre-write graph includes a series of 3 If tests. The outermost - // If tests whether SATB is enabled (no else case). The next If tests - // whether the old value is non-NULL (no else case). The third tests - // whether the SATB queue index is > 0, if so updating the queue. The - // else case for this third If calls out to the runtime to allocate a - // new queue buffer. - // - // So with G1 the pre-write and releasing store subgraph looks like - // this (the nested Ifs are omitted). - // - // MemBarRelease - // {MemBarCPUOrder}_(leading)___________ - // C | || M \ M \ M \ M \ . . . - // | LoadB \ LoadL LoadN \ - // | / \ \ - // If |\ \ - // | \ | \ \ - // IfFalse IfTrue | \ \ - // | | | \ | - // | If | /\ | - // | | \ | - // | \ | - // | . . . \ | - // | / | / | | - // Region Phi[M] | | - // | \ | | | - // | \_____ | ___ | | - // C | C \ | C \ M | | - // | CastP2X | StoreN/P[mo_release] | - // | | | | - // C | M | M | M | - // \ | | / - // . . . - // (post write subtree elided) - // . . . - // C \ M / - // \ / - // {MemBarCPUOrder} - // MemBarVolatile (trailing) - // - // n.b. the LoadB in this subgraph is not the card read -- it's a - // read of the SATB queue active flag. - // - // The G1 post-write subtree is also optional, this time when the - // new value being written is either null or can be identified as a - // newly allocated (young gen) object with no intervening control - // flow. The latter cannot happen but the former may, in which case - // the card mark membar is omitted and the memory feeds form the - // leading membar and the SToreN/P are merged direct into the - // trailing membar as per the normal subgraph. So, the only special - // case which arises is when the post-write subgraph is generated. - // - // The kernel of the post-write G1 subgraph is the card mark itself - // which includes a card mark memory barrier (MemBarVolatile), a - // card test (LoadB), and a conditional update (If feeding a - // StoreCM). These nodes are surrounded by a series of nested Ifs - // which try to avoid doing the card mark. The top level If skips if - // the object reference does not cross regions (i.e. it tests if - // (adr ^ val) >> log2(regsize) != 0) -- intra-region references - // need not be recorded. The next If, which skips on a NULL value, - // may be absent (it is not generated if the type of value is >= - // OopPtr::NotNull). The 3rd If skips writes to young regions (by - // checking if card_val != young). n.b. although this test requires - // a pre-read of the card it can safely be done before the StoreLoad - // barrier. However that does not bypass the need to reread the card - // after the barrier. A final, 4th If tests if the card is already - // marked. - // - // (pre-write subtree elided) - // . . . . . . . . . . . . - // C | M | M | M | - // Region Phi[M] StoreN | - // | / \ | | - // / \_______ / \ | | - // C / C \ . . . \ | | - // If CastP2X . . . | | | - // / \ | | | - // / \ | | | - // IfFalse IfTrue | | | - // | | | | /| - // | If | | / | - // | / \ | | / | - // | / \ \ | / | - // | IfFalse IfTrue MergeMem | - // | . . . / \ / | - // | / \ / | - // | IfFalse IfTrue / | - // | . . . | / | - // | If / | - // | / \ / | - // | / \ / | - // | IfFalse IfTrue / | - // | . . . | / | - // | \ / | - // | \ / | - // | MemBarVolatile__(card mark) | - // | || C | M \ M \ | - // | LoadB If | | | - // | / \ | | | - // | . . . | | | - // | \ | | / - // | StoreCM | / - // | . . . | / - // | _________/ / - // | / _____________/ - // | . . . . . . | / / - // | | | / _________/ - // | | Phi[M] / / - // | | | / / - // | | | / / - // | Region . . . Phi[M] _____/ - // | / | / - // | | / - // | . . . . . . | / - // | / | / - // Region | | Phi[M] - // | | | / Bot - // \ MergeMem - // \ / - // {MemBarCPUOrder} - // MemBarVolatile - // - // As with CMS the initial MergeMem merges the AliasIdxBot Mem slice - // from the leading membar and the oopptr Mem slice from the Store - // into the card mark membar i.e. the memory flow to the card mark - // membar still looks like a normal graph. - // - // The trailing MergeMem merges an AliasIdxBot Mem slice with other - // Mem slices (from the StoreCM and other card mark queue stores). - // However in this case the AliasIdxBot Mem slice does not come - // direct from the card mark membar. It is merged through a series - // of Phi nodes. These are needed to merge the AliasIdxBot Mem flow - // from the leading membar with the Mem feed from the card mark - // membar. Each Phi corresponds to one of the Ifs which may skip - // around the card mark membar. So when the If implementing the NULL - // value check has been elided the total number of Phis is 2 - // otherwise it is 3. - // - // The CAS graph when using G1GC also includes a pre-write subgraph - // and an optional post-write subgraph. The same variations are - // introduced as for CMS with conditional card marking i.e. the - // StoreP/N is swapped for a CompareAndSwapP/N with a following - // SCMemProj, the trailing MemBarVolatile for a MemBarCPUOrder + - // MemBarAcquire pair. There may be an extra If test introduced in - // the CAS case, when the boolean result of the CAS is tested by the - // caller. In that case an extra Region and AliasIdxBot Phi may be - // introduced before the MergeMem - // - // So, the upshot is that in all cases the subgraph will include a - // *normal* memory subgraph betwen the leading membar and its child - // membar: either a normal volatile put graph including a releasing - // StoreX and terminating with a trailing volatile membar or card - // mark volatile membar; or a normal CAS graph including a - // CompareAndSwapX + SCMemProj pair and terminating with a card mark - // volatile membar or a trailing cpu order and acquire membar - // pair. If the child membar is not a (volatile) card mark membar - // then it marks the end of the volatile put or CAS subgraph. If the - // child is a card mark membar then the normal subgraph will form - // part of a larger volatile put or CAS subgraph if and only if the - // child feeds an AliasIdxBot Mem feed to a trailing barrier via a - // MergeMem. That feed is either direct (for CMS) or via 2, 3 or 4 - // Phi nodes merging the leading barrier memory flow (for G1). - // - // The predicates controlling generation of instructions for store - // and barrier nodes employ a few simple helper functions (described - // below) which identify the presence or absence of all these - // subgraph configurations and provide a means of traversing from - // one node in the subgraph to another. - - // is_CAS(int opcode) + // is_CAS(int opcode, bool maybe_volatile) // // return true if opcode is one of the possible CompareAndSwapX // values otherwise false. - bool is_CAS(int opcode) + bool is_CAS(int opcode, bool maybe_volatile) { switch(opcode) { // We handle these @@ -1884,23 +1273,32 @@ case Op_CompareAndSwapL: case Op_CompareAndSwapP: case Op_CompareAndSwapN: - // case Op_CompareAndSwapB: - // case Op_CompareAndSwapS: + case Op_CompareAndSwapB: + case Op_CompareAndSwapS: + case Op_GetAndSetI: + case Op_GetAndSetL: + case Op_GetAndSetP: + case Op_GetAndSetN: + case Op_GetAndAddI: + case Op_GetAndAddL: +#if INCLUDE_SHENANDOAHGC + case Op_ShenandoahCompareAndSwapP: + case Op_ShenandoahCompareAndSwapN: +#endif return true; - // These are TBD + case Op_CompareAndExchangeI: + case Op_CompareAndExchangeN: + case Op_CompareAndExchangeB: + case Op_CompareAndExchangeS: + case Op_CompareAndExchangeL: + case Op_CompareAndExchangeP: case Op_WeakCompareAndSwapB: case Op_WeakCompareAndSwapS: case Op_WeakCompareAndSwapI: case Op_WeakCompareAndSwapL: case Op_WeakCompareAndSwapP: case Op_WeakCompareAndSwapN: - case Op_CompareAndExchangeB: - case Op_CompareAndExchangeS: - case Op_CompareAndExchangeI: - case Op_CompareAndExchangeL: - case Op_CompareAndExchangeP: - case Op_CompareAndExchangeN: - return false; + return maybe_volatile; default: return false; } @@ -1910,674 +1308,7 @@ // traverse when searching from a card mark membar for the merge mem // feeding a trailing membar or vice versa - int max_phis() - { - if (UseG1GC) { - return 4; - } else if (UseConcMarkSweepGC && UseCondCardMark) { - return 1; - } else { - return 0; - } - } - - // leading_to_normal - // - // graph traversal helper which detects the normal case Mem feed - // from a release membar (or, optionally, its cpuorder child) to a - // dependent volatile or acquire membar i.e. it ensures that one of - // the following 3 Mem flow subgraphs is present. - // - // MemBarRelease - // {MemBarCPUOrder} {leading} - // | \ . . . - // | StoreN/P[mo_release] . . . - // | / - // MergeMem - // | - // {MemBarCPUOrder} - // MemBarVolatile {trailing or card mark} - // - // MemBarRelease - // MemBarCPUOrder {leading} - // | \ . . . - // | CompareAndSwapX . . . - // | / - // MergeMem - // | - // MemBarVolatile {card mark} - // - // MemBarRelease - // MemBarCPUOrder {leading} - // | \ . . . - // | CompareAndSwapX . . . - // | / - // MergeMem - // | - // MemBarCPUOrder - // MemBarAcquire {trailing} - // - // if the correct configuration is present returns the trailing - // or cardmark membar otherwise NULL. - // - // the input membar is expected to be either a cpuorder membar or a - // release membar. in the latter case it should not have a cpu membar - // child. - // - // the returned value may be a card mark or trailing membar - // - - MemBarNode *leading_to_normal(MemBarNode *leading) - { - assert((leading->Opcode() == Op_MemBarRelease || - leading->Opcode() == Op_MemBarCPUOrder), - "expecting a volatile or cpuroder membar!"); - - // check the mem flow - ProjNode *mem = leading->proj_out(TypeFunc::Memory); - - if (!mem) { - return NULL; - } - - Node *x = NULL; - StoreNode * st = NULL; - LoadStoreNode *cas = NULL; - MergeMemNode *mm = NULL; - - for (DUIterator_Fast imax, i = mem->fast_outs(imax); i < imax; i++) { - x = mem->fast_out(i); - if (x->is_MergeMem()) { - if (mm != NULL) { - return NULL; - } - // two merge mems is one too many - mm = x->as_MergeMem(); - } else if (x->is_Store() && x->as_Store()->is_release() && x->Opcode() != Op_StoreCM) { - // two releasing stores/CAS nodes is one too many - if (st != NULL || cas != NULL) { - return NULL; - } - st = x->as_Store(); - } else if (is_CAS(x->Opcode())) { - if (st != NULL || cas != NULL) { - return NULL; - } - cas = x->as_LoadStore(); - } - } - - // must have a store or a cas - if (!st && !cas) { - return NULL; - } - - // must have a merge - if (!mm) { - return NULL; - } - - Node *feed = NULL; - if (cas) { - // look for an SCMemProj - for (DUIterator_Fast imax, i = cas->fast_outs(imax); i < imax; i++) { - x = cas->fast_out(i); - if (x->Opcode() == Op_SCMemProj) { - feed = x; - break; - } - } - if (feed == NULL) { - return NULL; - } - } else { - feed = st; - } - // ensure the feed node feeds the existing mergemem; - for (DUIterator_Fast imax, i = feed->fast_outs(imax); i < imax; i++) { - x = feed->fast_out(i); - if (x == mm) { - break; - } - } - if (x != mm) { - return NULL; - } - - MemBarNode *mbar = NULL; - // ensure the merge feeds to the expected type of membar - for (DUIterator_Fast imax, i = mm->fast_outs(imax); i < imax; i++) { - x = mm->fast_out(i); - if (x->is_MemBar()) { - if (x->Opcode() == Op_MemBarCPUOrder) { - // with a store any cpu order membar should precede a - // trailing volatile membar. with a cas it should precede a - // trailing acquire membar. in either case try to skip to - // that next membar - MemBarNode *y = x->as_MemBar(); - y = child_membar(y); - if (y != NULL) { - // skip to this new membar to do the check - x = y; - } - - } - if (x->Opcode() == Op_MemBarVolatile) { - mbar = x->as_MemBar(); - // for a volatile store this can be either a trailing membar - // or a card mark membar. for a cas it must be a card mark - // membar - guarantee(cas == NULL || is_card_mark_membar(mbar), - "in CAS graph volatile membar must be a card mark"); - } else if (cas != NULL && x->Opcode() == Op_MemBarAcquire) { - mbar = x->as_MemBar(); - } - break; - } - } - - return mbar; - } - - // normal_to_leading - // - // graph traversal helper which detects the normal case Mem feed - // from either a card mark or a trailing membar to a preceding - // release membar (optionally its cpuorder child) i.e. it ensures - // that one of the following 3 Mem flow subgraphs is present. - // - // MemBarRelease - // {MemBarCPUOrder} {leading} - // | \ . . . - // | StoreN/P[mo_release] . . . - // | / - // MergeMem - // | - // {MemBarCPUOrder} - // MemBarVolatile {trailing or card mark} - // - // MemBarRelease - // MemBarCPUOrder {leading} - // | \ . . . - // | CompareAndSwapX . . . - // | / - // MergeMem - // | - // MemBarVolatile {card mark} - // - // MemBarRelease - // MemBarCPUOrder {leading} - // | \ . . . - // | CompareAndSwapX . . . - // | / - // MergeMem - // | - // MemBarCPUOrder - // MemBarAcquire {trailing} - // - // this predicate checks for the same flow as the previous predicate - // but starting from the bottom rather than the top. - // - // if the configuration is present returns the cpuorder member for - // preference or when absent the release membar otherwise NULL. - // - // n.b. the input membar is expected to be a MemBarVolatile but - // need not be a card mark membar. - - MemBarNode *normal_to_leading(const MemBarNode *barrier) - { - // input must be a volatile membar - assert((barrier->Opcode() == Op_MemBarVolatile || - barrier->Opcode() == Op_MemBarAcquire), - "expecting a volatile or an acquire membar"); - bool barrier_is_acquire = barrier->Opcode() == Op_MemBarAcquire; - - // if we have an intervening cpu order membar then start the - // search from it - - Node *x = parent_membar(barrier); - - if (x == NULL) { - // stick with the original barrier - x = (Node *)barrier; - } else if (x->Opcode() != Op_MemBarCPUOrder) { - // any other barrier means this is not the graph we want - return NULL; - } - - // the Mem feed to the membar should be a merge - x = x ->in(TypeFunc::Memory); - if (!x->is_MergeMem()) - return NULL; - - MergeMemNode *mm = x->as_MergeMem(); - - // the merge should get its Bottom mem feed from the leading membar - x = mm->in(Compile::AliasIdxBot); - - // ensure this is a non control projection - if (!x->is_Proj() || x->is_CFG()) { - return NULL; - } - // if it is fed by a membar that's the one we want - x = x->in(0); - - if (!x->is_MemBar()) { - return NULL; - } - - MemBarNode *leading = x->as_MemBar(); - // reject invalid candidates - if (!leading_membar(leading)) { - return NULL; - } - - // ok, we have a leading membar, now for the sanity clauses - - // the leading membar must feed Mem to a releasing store or CAS - ProjNode *mem = leading->proj_out(TypeFunc::Memory); - StoreNode *st = NULL; - LoadStoreNode *cas = NULL; - for (DUIterator_Fast imax, i = mem->fast_outs(imax); i < imax; i++) { - x = mem->fast_out(i); - if (x->is_Store() && x->as_Store()->is_release() && x->Opcode() != Op_StoreCM) { - // two stores or CASes is one too many - if (st != NULL || cas != NULL) { - return NULL; - } - st = x->as_Store(); - } else if (is_CAS(x->Opcode())) { - if (st != NULL || cas != NULL) { - return NULL; - } - cas = x->as_LoadStore(); - } - } - - // we cannot have both a store and a cas - if (st == NULL && cas == NULL) { - // we have neither -- this is not a normal graph - return NULL; - } - if (st == NULL) { - // if we started from a volatile membar and found a CAS then the - // original membar ought to be for a card mark - guarantee((barrier_is_acquire || is_card_mark_membar(barrier)), - "unexpected volatile barrier (i.e. not card mark) in CAS graph"); - // check that the CAS feeds the merge we used to get here via an - // intermediary SCMemProj - Node *scmemproj = NULL; - for (DUIterator_Fast imax, i = cas->fast_outs(imax); i < imax; i++) { - x = cas->fast_out(i); - if (x->Opcode() == Op_SCMemProj) { - scmemproj = x; - break; - } - } - if (scmemproj == NULL) { - return NULL; - } - for (DUIterator_Fast imax, i = scmemproj->fast_outs(imax); i < imax; i++) { - x = scmemproj->fast_out(i); - if (x == mm) { - return leading; - } - } - } else { - // we should not have found a store if we started from an acquire - guarantee(!barrier_is_acquire, - "unexpected trailing acquire barrier in volatile store graph"); - - // the store should feed the merge we used to get here - for (DUIterator_Fast imax, i = st->fast_outs(imax); i < imax; i++) { - if (st->fast_out(i) == mm) { - return leading; - } - } - } - - return NULL; - } - - // card_mark_to_trailing - // - // graph traversal helper which detects extra, non-normal Mem feed - // from a card mark volatile membar to a trailing membar i.e. it - // ensures that one of the following three GC post-write Mem flow - // subgraphs is present. - // - // 1) - // . . . - // | - // MemBarVolatile (card mark) - // | | - // | StoreCM - // | | - // | . . . - // Bot | / - // MergeMem - // | - // {MemBarCPUOrder} OR MemBarCPUOrder - // MemBarVolatile {trailing} MemBarAcquire {trailing} - // - // - // 2) - // MemBarRelease/CPUOrder (leading) - // | - // | - // |\ . . . - // | \ | - // | \ MemBarVolatile (card mark) - // | \ | | - // \ \ | StoreCM . . . - // \ \ | - // \ Phi - // \ / - // Phi . . . - // Bot | / - // MergeMem - // | - // {MemBarCPUOrder} OR MemBarCPUOrder - // MemBarVolatile {trailing} MemBarAcquire {trailing} - // - // 3) - // MemBarRelease/CPUOrder (leading) - // | - // |\ - // | \ - // | \ . . . - // | \ | - // |\ \ MemBarVolatile (card mark) - // | \ \ | | - // | \ \ | StoreCM . . . - // | \ \ | - // \ \ Phi - // \ \ / - // \ Phi - // \ / - // Phi . . . - // Bot | / - // MergeMem - // | - // | - // {MemBarCPUOrder} OR MemBarCPUOrder - // MemBarVolatile {trailing} MemBarAcquire {trailing} - // - // 4) - // MemBarRelease/CPUOrder (leading) - // | - // |\ - // | \ - // | \ - // | \ - // |\ \ - // | \ \ - // | \ \ . . . - // | \ \ | - // |\ \ \ MemBarVolatile (card mark) - // | \ \ \ / | - // | \ \ \ / StoreCM . . . - // | \ \ Phi - // \ \ \ / - // \ \ Phi - // \ \ / - // \ Phi - // \ / - // Phi . . . - // Bot | / - // MergeMem - // | - // | - // MemBarCPUOrder - // MemBarAcquire {trailing} - // - // configuration 1 is only valid if UseConcMarkSweepGC && - // UseCondCardMark - // - // configuration 2, is only valid if UseConcMarkSweepGC && - // UseCondCardMark or if UseG1GC - // - // configurations 3 and 4 are only valid if UseG1GC. - // - // if a valid configuration is present returns the trailing membar - // otherwise NULL. - // - // n.b. the supplied membar is expected to be a card mark - // MemBarVolatile i.e. the caller must ensure the input node has the - // correct operand and feeds Mem to a StoreCM node - - MemBarNode *card_mark_to_trailing(const MemBarNode *barrier) - { - // input must be a card mark volatile membar - assert(is_card_mark_membar(barrier), "expecting a card mark membar"); - - Node *feed = barrier->proj_out(TypeFunc::Memory); - Node *x; - MergeMemNode *mm = NULL; - - const int MAX_PHIS = max_phis(); // max phis we will search through - int phicount = 0; // current search count - - bool retry_feed = true; - while (retry_feed) { - // see if we have a direct MergeMem feed - for (DUIterator_Fast imax, i = feed->fast_outs(imax); i < imax; i++) { - x = feed->fast_out(i); - // the correct Phi will be merging a Bot memory slice - if (x->is_MergeMem()) { - mm = x->as_MergeMem(); - break; - } - } - if (mm) { - retry_feed = false; - } else if (phicount++ < MAX_PHIS) { - // the barrier may feed indirectly via one or two Phi nodes - PhiNode *phi = NULL; - for (DUIterator_Fast imax, i = feed->fast_outs(imax); i < imax; i++) { - x = feed->fast_out(i); - // the correct Phi will be merging a Bot memory slice - if (x->is_Phi() && x->adr_type() == TypePtr::BOTTOM) { - phi = x->as_Phi(); - break; - } - } - if (!phi) { - return NULL; - } - // look for another merge below this phi - feed = phi; - } else { - // couldn't find a merge - return NULL; - } - } - - // sanity check this feed turns up as the expected slice - guarantee(mm->as_MergeMem()->in(Compile::AliasIdxBot) == feed, "expecting membar to feed AliasIdxBot slice to Merge"); - - MemBarNode *trailing = NULL; - // be sure we have a trailing membar fed by the merge - for (DUIterator_Fast imax, i = mm->fast_outs(imax); i < imax; i++) { - x = mm->fast_out(i); - if (x->is_MemBar()) { - // if this is an intervening cpu order membar skip to the - // following membar - if (x->Opcode() == Op_MemBarCPUOrder) { - MemBarNode *y = x->as_MemBar(); - y = child_membar(y); - if (y != NULL) { - x = y; - } - } - if (x->Opcode() == Op_MemBarVolatile || - x->Opcode() == Op_MemBarAcquire) { - trailing = x->as_MemBar(); - } - break; - } - } - - return trailing; - } - - // trailing_to_card_mark - // - // graph traversal helper which detects extra, non-normal Mem feed - // from a trailing volatile membar to a preceding card mark volatile - // membar i.e. it identifies whether one of the three possible extra - // GC post-write Mem flow subgraphs is present - // - // this predicate checks for the same flow as the previous predicate - // but starting from the bottom rather than the top. - // - // if the configuration is present returns the card mark membar - // otherwise NULL - // - // n.b. the supplied membar is expected to be a trailing - // MemBarVolatile or MemBarAcquire i.e. the caller must ensure the - // input node has the correct opcode - - MemBarNode *trailing_to_card_mark(const MemBarNode *trailing) - { - assert(trailing->Opcode() == Op_MemBarVolatile || - trailing->Opcode() == Op_MemBarAcquire, - "expecting a volatile or acquire membar"); - assert(!is_card_mark_membar(trailing), - "not expecting a card mark membar"); - - Node *x = (Node *)trailing; - - // look for a preceding cpu order membar - MemBarNode *y = parent_membar(x->as_MemBar()); - if (y != NULL) { - // make sure it is a cpu order membar - if (y->Opcode() != Op_MemBarCPUOrder) { - // this is nto the graph we were looking for - return NULL; - } - // start the search from here - x = y; - } - - // the Mem feed to the membar should be a merge - x = x->in(TypeFunc::Memory); - if (!x->is_MergeMem()) { - return NULL; - } - - MergeMemNode *mm = x->as_MergeMem(); - - x = mm->in(Compile::AliasIdxBot); - // with G1 we may possibly see a Phi or two before we see a Memory - // Proj from the card mark membar - - const int MAX_PHIS = max_phis(); // max phis we will search through - int phicount = 0; // current search count - - bool retry_feed = !x->is_Proj(); - - while (retry_feed) { - if (x->is_Phi() && phicount++ < MAX_PHIS) { - PhiNode *phi = x->as_Phi(); - ProjNode *proj = NULL; - PhiNode *nextphi = NULL; - bool found_leading = false; - for (uint i = 1; i < phi->req(); i++) { - x = phi->in(i); - if (x->is_Phi() && x->adr_type() == TypePtr::BOTTOM) { - nextphi = x->as_Phi(); - } else if (x->is_Proj()) { - int opcode = x->in(0)->Opcode(); - if (opcode == Op_MemBarVolatile) { - proj = x->as_Proj(); - } else if (opcode == Op_MemBarRelease || - opcode == Op_MemBarCPUOrder) { - // probably a leading membar - found_leading = true; - } - } - } - // if we found a correct looking proj then retry from there - // otherwise we must see a leading and a phi or this the - // wrong config - if (proj != NULL) { - x = proj; - retry_feed = false; - } else if (found_leading && nextphi != NULL) { - // retry from this phi to check phi2 - x = nextphi; - } else { - // not what we were looking for - return NULL; - } - } else { - return NULL; - } - } - // the proj has to come from the card mark membar - x = x->in(0); - if (!x->is_MemBar()) { - return NULL; - } - - MemBarNode *card_mark_membar = x->as_MemBar(); - - if (!is_card_mark_membar(card_mark_membar)) { - return NULL; - } - - return card_mark_membar; - } - - // trailing_to_leading - // - // graph traversal helper which checks the Mem flow up the graph - // from a (non-card mark) trailing membar attempting to locate and - // return an associated leading membar. it first looks for a - // subgraph in the normal configuration (relying on helper - // normal_to_leading). failing that it then looks for one of the - // possible post-write card mark subgraphs linking the trailing node - // to a the card mark membar (relying on helper - // trailing_to_card_mark), and then checks that the card mark membar - // is fed by a leading membar (once again relying on auxiliary - // predicate normal_to_leading). - // - // if the configuration is valid returns the cpuorder member for - // preference or when absent the release membar otherwise NULL. - // - // n.b. the input membar is expected to be either a volatile or - // acquire membar but in the former case must *not* be a card mark - // membar. - - MemBarNode *trailing_to_leading(const MemBarNode *trailing) - { - assert((trailing->Opcode() == Op_MemBarAcquire || - trailing->Opcode() == Op_MemBarVolatile), - "expecting an acquire or volatile membar"); - assert((trailing->Opcode() != Op_MemBarVolatile || - !is_card_mark_membar(trailing)), - "not expecting a card mark membar"); - - MemBarNode *leading = normal_to_leading(trailing); - - if (leading) { - return leading; - } - - // there is no normal path from trailing to leading membar. see if - // we can arrive via a card mark membar - - MemBarNode *card_mark_membar = trailing_to_card_mark(trailing); - - if (!card_mark_membar) { - return NULL; - } - - return normal_to_leading(card_mark_membar); - } - - // predicates controlling emit of ldr<x>/ldar<x> and associated dmb +// predicates controlling emit of ldr<x>/ldar<x> and associated dmb bool unnecessary_acquire(const Node *barrier) { @@ -2588,40 +1319,19 @@ return false; } - // a volatile read derived from bytecode (or also from an inlined - // SHA field read via LibraryCallKit::load_field_from_object) - // manifests as a LoadX[mo_acquire] followed by an acquire membar - // with a bogus read dependency on it's preceding load. so in those - // cases we will find the load node at the PARMS offset of the - // acquire membar. n.b. there may be an intervening DecodeN node. + MemBarNode* mb = barrier->as_MemBar(); - Node *x = barrier->lookup(TypeFunc::Parms); - if (x) { - // we are starting from an acquire and it has a fake dependency - // - // need to check for - // - // LoadX[mo_acquire] - // { |1 } - // {DecodeN} - // |Parms - // MemBarAcquire* - // - // where * tags node we were passed - // and |k means input k - if (x->is_DecodeNarrowPtr()) { - x = x->in(1); - } - - return (x->is_Load() && x->as_Load()->is_acquire()); + if (mb->trailing_load()) { + return true; } - // other option for unnecessary membar is that it is a trailing node - // belonging to a CAS + if (mb->trailing_load_store()) { + Node* load_store = mb->in(MemBarNode::Precedent); + assert(load_store->is_LoadStore(), "unexpected graph shape"); + return is_CAS(load_store->Opcode(), true); + } - MemBarNode *leading = trailing_to_leading(barrier->as_MemBar()); - - return leading != NULL; + return false; } bool needs_acquiring_load(const Node *n) @@ -2634,45 +1344,7 @@ LoadNode *ld = n->as_Load(); - if (!ld->is_acquire()) { - return false; - } - - // check if this load is feeding an acquire membar - // - // LoadX[mo_acquire] - // { |1 } - // {DecodeN} - // |Parms - // MemBarAcquire* - // - // where * tags node we were passed - // and |k means input k - - Node *start = ld; - Node *mbacq = NULL; - - // if we hit a DecodeNarrowPtr we reset the start node and restart - // the search through the outputs - restart: - - for (DUIterator_Fast imax, i = start->fast_outs(imax); i < imax; i++) { - Node *x = start->fast_out(i); - if (x->is_MemBar() && x->Opcode() == Op_MemBarAcquire) { - mbacq = x; - } else if (!mbacq && - (x->is_DecodeNarrowPtr() || - (x->is_Mach() && x->Opcode() == Op_DecodeN))) { - start = x; - goto restart; - } - } - - if (mbacq) { - return true; - } - - return false; + return ld->is_acquire(); } bool unnecessary_release(const Node *n) @@ -2686,32 +1358,27 @@ return false; } - // if there is a dependent CPUOrder barrier then use that as the - // leading - MemBarNode *barrier = n->as_MemBar(); - // check for an intervening cpuorder membar - MemBarNode *b = child_membar(barrier); - if (b && b->Opcode() == Op_MemBarCPUOrder) { - // ok, so start the check from the dependent cpuorder barrier - barrier = b; - } - - // must start with a normal feed - MemBarNode *child_barrier = leading_to_normal(barrier); - - if (!child_barrier) { + if (!barrier->leading()) { return false; - } + } else { + Node* trailing = barrier->trailing_membar(); + MemBarNode* trailing_mb = trailing->as_MemBar(); + assert(trailing_mb->trailing(), "Not a trailing membar?"); + assert(trailing_mb->leading_membar() == n, "inconsistent leading/trailing membars"); - if (!is_card_mark_membar(child_barrier)) { - // this is the trailing membar and we are done - return true; + Node* mem = trailing_mb->in(MemBarNode::Precedent); + if (mem->is_Store()) { + assert(mem->as_Store()->is_release(), ""); + assert(trailing_mb->Opcode() == Op_MemBarVolatile, ""); + return true; + } else { + assert(mem->is_LoadStore(), ""); + assert(trailing_mb->Opcode() == Op_MemBarAcquire, ""); + return is_CAS(mem->Opcode(), true); + } } - - // must be sure this card mark feeds a trailing membar - MemBarNode *trailing = card_mark_to_trailing(child_barrier); - return (trailing != NULL); + return false; } bool unnecessary_volatile(const Node *n) @@ -2724,17 +1391,18 @@ MemBarNode *mbvol = n->as_MemBar(); - // first we check if this is part of a card mark. if so then we have - // to generate a StoreLoad barrier - - if (is_card_mark_membar(mbvol)) { - return false; + bool release = mbvol->trailing_store(); + assert(!release || (mbvol->in(MemBarNode::Precedent)->is_Store() && mbvol->in(MemBarNode::Precedent)->as_Store()->is_release()), ""); +#ifdef ASSERT + if (release) { + Node* leading = mbvol->leading_membar(); + assert(leading->Opcode() == Op_MemBarRelease, ""); + assert(leading->as_MemBar()->leading_store(), ""); + assert(leading->as_MemBar()->trailing_membar() == mbvol, ""); } +#endif - // ok, if it's not a card mark then we still need to check if it is - // a trailing membar of a volatile put graph. - - return (trailing_to_leading(mbvol) != NULL); + return release; } // predicates controlling emit of str<x>/stlr<x> and associated dmbs @@ -2749,53 +1417,7 @@ StoreNode *st = n->as_Store(); - // the store must be marked as releasing - if (!st->is_release()) { - return false; - } - - // the store must be fed by a membar - - Node *x = st->lookup(StoreNode::Memory); - - if (! x || !x->is_Proj()) { - return false; - } - - ProjNode *proj = x->as_Proj(); - - x = proj->lookup(0); - - if (!x || !x->is_MemBar()) { - return false; - } - - MemBarNode *barrier = x->as_MemBar(); - - // if the barrier is a release membar or a cpuorder mmebar fed by a - // release membar then we need to check whether that forms part of a - // volatile put graph. - - // reject invalid candidates - if (!leading_membar(barrier)) { - return false; - } - - // does this lead a normal subgraph? - MemBarNode *mbvol = leading_to_normal(barrier); - - if (!mbvol) { - return false; - } - - // all done unless this is a card mark - if (!is_card_mark_membar(mbvol)) { - return true; - } - - // we found a card mark -- just make sure we have a trailing barrier - - return (card_mark_to_trailing(mbvol) != NULL); + return st->trailing_membar() != NULL; } // predicate controlling translation of CAS @@ -2804,53 +1426,18 @@ bool needs_acquiring_load_exclusive(const Node *n) { - assert(is_CAS(n->Opcode()), "expecting a compare and swap"); + assert(is_CAS(n->Opcode(), true), "expecting a compare and swap"); if (UseBarriersForVolatile) { return false; } - // CAS nodes only ought to turn up in inlined unsafe CAS operations -#ifdef ASSERT - LoadStoreNode *st = n->as_LoadStore(); - - // the store must be fed by a membar - - Node *x = st->lookup(StoreNode::Memory); - - assert (x && x->is_Proj(), "CAS not fed by memory proj!"); - - ProjNode *proj = x->as_Proj(); - - x = proj->lookup(0); - - assert (x && x->is_MemBar(), "CAS not fed by membar!"); - - MemBarNode *barrier = x->as_MemBar(); - - // the barrier must be a cpuorder mmebar fed by a release membar - - guarantee(barrier->Opcode() == Op_MemBarCPUOrder, - "CAS not fed by cpuorder membar!"); - - MemBarNode *b = parent_membar(barrier); - assert ((b != NULL && b->Opcode() == Op_MemBarRelease), - "CAS not fed by cpuorder+release membar pair!"); - - // does this lead a normal subgraph? - MemBarNode *mbar = leading_to_normal(barrier); - - guarantee(mbar != NULL, "CAS not embedded in normal graph!"); - - // if this is a card mark membar check we have a trailing acquire - - if (is_card_mark_membar(mbar)) { - mbar = card_mark_to_trailing(mbar); + LoadStoreNode* ldst = n->as_LoadStore(); + if (is_CAS(n->Opcode(), false)) { + assert(ldst->trailing_membar() != NULL, "expected trailing membar"); + } else { + return ldst->trailing_membar() != NULL; } - guarantee(mbar != NULL, "card mark membar for CAS not embedded in normal graph!"); - - guarantee(mbar->Opcode() == Op_MemBarAcquire, "trailing membar should be an acquire"); -#endif // ASSERT // so we can just return true here return true; } @@ -2908,16 +1495,18 @@ int MachCallRuntimeNode::ret_addr_offset() { // for generated stubs the call will be - // far_call(addr) + // bl(addr) + // or with far branches + // bl(trampoline_stub) // for real runtime callouts it will be six instructions // see aarch64_enc_java_to_runtime // adr(rscratch2, retaddr) // lea(rscratch1, RuntimeAddress(addr) // stp(zr, rscratch2, Address(__ pre(sp, -2 * wordSize))) - // blrt rscratch1 + // blr(rscratch1) CodeBlob *cb = CodeCache::find_blob(_entry_point); if (cb) { - return MacroAssembler::far_branch_size(); + return 1 * NativeInstruction::instruction_size; } else { return 6 * NativeInstruction::instruction_size; } @@ -3026,7 +1615,7 @@ MacroAssembler _masm(&cbuf); // n.b. frame size includes space for return pc and rfp - const long framesize = C->frame_size_in_bytes(); + const int framesize = C->frame_size_in_bytes(); assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); // insert a nop at the start of the prolog so we can patch in a @@ -3039,10 +1628,6 @@ __ build_frame(framesize); - if (NotifySimulator) { - __ notify(Assembler::method_entry); - } - if (VerifyStackAtCalls) { Unimplemented(); } @@ -3103,10 +1688,6 @@ __ remove_frame(framesize); - if (NotifySimulator) { - __ notify(Assembler::method_reentry); - } - if (StackReservedPages > 0 && C->has_reserved_stack_access()) { __ reserved_stack_check(); } @@ -3152,13 +1733,14 @@ // we have 30 int registers * 2 halves // (rscratch1 and rscratch2 are omitted) + int slots_of_int_registers = RegisterImpl::max_slots_per_register * (RegisterImpl::number_of_registers - 2); - if (reg < 60) { + if (reg < slots_of_int_registers) { return rc_int; } - // we have 32 float register * 2 halves - if (reg < 60 + 128) { + // we have 32 float register * 4 halves + if (reg < slots_of_int_registers + FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers) { return rc_float; } @@ -3354,16 +1936,20 @@ int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); int reg = ra_->get_encode(this); - if (Assembler::operand_valid_for_add_sub_immediate(offset)) { - __ add(as_Register(reg), sp, offset); - } else { - ShouldNotReachHere(); - } + // This add will handle any 24-bit signed offset. 24 bits allows an + // 8 megabyte stack frame. + __ add(as_Register(reg), sp, offset); } uint BoxLockNode::size(PhaseRegAlloc *ra_) const { // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_). - return 4; + int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); + + if (Assembler::operand_valid_for_add_sub_immediate(offset)) { + return NativeInstruction::instruction_size; + } else { + return 2 * NativeInstruction::instruction_size; + } } //============================================================================= @@ -3545,7 +2131,12 @@ } const uint Matcher::vector_shift_count_ideal_reg(int size) { - return Op_VecX; + switch(size) { + case 8: return Op_VecD; + case 16: return Op_VecX; + } + ShouldNotReachHere(); + return 0; } // AES support not yet implemented @@ -3553,9 +2144,9 @@ return false; } -// x86 supports misaligned vectors store/load. +// aarch64 supports misaligned vectors store/load. const bool Matcher::misaligned_vectors_ok() { - return !AlignVector; // can be changed by flag + return true; } // false => size gets scaled to BytesPerLong, ok. @@ -3763,47 +2354,6 @@ void Compile::reshape_address(AddPNode* addp) { } -// helper for encoding java_to_runtime calls on sim -// -// this is needed to compute the extra arguments required when -// planting a call to the simulator blrt instruction. the TypeFunc -// can be queried to identify the counts for integral, and floating -// arguments and the return type - -static void getCallInfo(const TypeFunc *tf, int &gpcnt, int &fpcnt, int &rtype) -{ - int gps = 0; - int fps = 0; - const TypeTuple *domain = tf->domain(); - int max = domain->cnt(); - for (int i = TypeFunc::Parms; i < max; i++) { - const Type *t = domain->field_at(i); - switch(t->basic_type()) { - case T_FLOAT: - case T_DOUBLE: - fps++; - default: - gps++; - } - } - gpcnt = gps; - fpcnt = fps; - BasicType rt = tf->return_type(); - switch (rt) { - case T_VOID: - rtype = MacroAssembler::ret_type_void; - break; - default: - rtype = MacroAssembler::ret_type_integral; - break; - case T_FLOAT: - rtype = MacroAssembler::ret_type_float; - break; - case T_DOUBLE: - rtype = MacroAssembler::ret_type_double; - break; - } -} #define MOV_VOLATILE(REG, BASE, INDEX, SCALE, DISP, SCRATCH, INSN) \ MacroAssembler _masm(&cbuf); \ @@ -4370,6 +2920,21 @@ /*weak*/ false, noreg); %} + enc_class aarch64_enc_cmpxchgs_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{ + MacroAssembler _masm(&cbuf); + guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); + __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register, + Assembler::halfword, /*acquire*/ true, /*release*/ true, + /*weak*/ false, noreg); + %} + + enc_class aarch64_enc_cmpxchgb_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{ + MacroAssembler _masm(&cbuf); + guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); + __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register, + Assembler::byte, /*acquire*/ true, /*release*/ true, + /*weak*/ false, noreg); + %} // auxiliary used for CompareAndSwapX to set result register enc_class aarch64_enc_cset_eq(iRegINoSp res) %{ @@ -4403,7 +2968,7 @@ enc_class aarch64_enc_movw_imm(iRegI dst, immI src) %{ MacroAssembler _masm(&cbuf); - u_int32_t con = (u_int32_t)$src$$constant; + uint32_t con = (uint32_t)$src$$constant; Register dst_reg = as_Register($dst$$reg); if (con == 0) { __ movw(dst_reg, zr); @@ -4415,7 +2980,7 @@ enc_class aarch64_enc_mov_imm(iRegL dst, immL src) %{ MacroAssembler _masm(&cbuf); Register dst_reg = as_Register($dst$$reg); - u_int64_t con = (u_int64_t)$src$$constant; + uint64_t con = (uint64_t)$src$$constant; if (con == 0) { __ mov(dst_reg, zr); } else { @@ -4440,7 +3005,7 @@ if (con < (address)(uintptr_t)os::vm_page_size()) { __ mov(dst_reg, con); } else { - unsigned long offset; + uintptr_t offset; __ adrp(dst_reg, con, offset); __ add(dst_reg, dst_reg, offset); } @@ -4457,14 +3022,14 @@ enc_class aarch64_enc_mov_p1(iRegP dst, immP_1 src) %{ MacroAssembler _masm(&cbuf); Register dst_reg = as_Register($dst$$reg); - __ mov(dst_reg, (u_int64_t)1); + __ mov(dst_reg, (uint64_t)1); %} enc_class aarch64_enc_mov_poll_page(iRegP dst, immPollPage src) %{ MacroAssembler _masm(&cbuf); address page = (address)$src$$constant; Register dst_reg = as_Register($dst$$reg); - unsigned long off; + uint64_t off; __ adrp(dst_reg, Address(page, relocInfo::poll_type), off); assert(off == 0, "assumed offset == 0"); %} @@ -4591,7 +3156,7 @@ enc_class aarch64_enc_cmpw_imm(iRegI src1, immI src2) %{ MacroAssembler _masm(&cbuf); Register reg1 = as_Register($src1$$reg); - u_int32_t val = (u_int32_t)$src2$$constant; + uint32_t val = (uint32_t)$src2$$constant; __ movw(rscratch1, val); __ cmpw(reg1, rscratch1); %} @@ -4613,7 +3178,7 @@ __ adds(zr, reg, -val); } else { // aargh, Long.MIN_VALUE is a special case - __ orr(rscratch1, zr, (u_int64_t)val); + __ orr(rscratch1, zr, (uint64_t)val); __ subs(zr, reg, rscratch1); } %} @@ -4621,7 +3186,7 @@ enc_class aarch64_enc_cmp_imm(iRegL src1, immL src2) %{ MacroAssembler _masm(&cbuf); Register reg1 = as_Register($src1$$reg); - u_int64_t val = (u_int64_t)$src2$$constant; + uint64_t val = (uint64_t)$src2$$constant; __ mov(rscratch1, val); __ cmp(reg1, rscratch1); %} @@ -4696,12 +3261,19 @@ if (!_method) { // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap. call = __ trampoline_call(Address(addr, relocInfo::runtime_call_type), &cbuf); + if (call == NULL) { + ciEnv::current()->record_failure("CodeCache is full"); + return; + } } else { int method_index = resolved_method_index(cbuf); RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index) : static_call_Relocation::spec(method_index); call = __ trampoline_call(Address(addr, rspec), &cbuf); - + if (call == NULL) { + ciEnv::current()->record_failure("CodeCache is full"); + return; + } // Emit stub for static call address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); if (stub == NULL) { @@ -4709,10 +3281,6 @@ return; } } - if (call == NULL) { - ciEnv::current()->record_failure("CodeCache is full"); - return; - } %} enc_class aarch64_enc_java_dynamic_call(method meth) %{ @@ -4738,7 +3306,7 @@ // some calls to generated routines (arraycopy code) are scheduled // by C2 as runtime calls. if so we can call them using a br (they - // will be in a reachable segment) otherwise we have to use a blrt + // will be in a reachable segment) otherwise we have to use a blr // which loads the absolute address into a register. address entry = (address)$meth$$method; CodeBlob *cb = CodeCache::find_blob(entry); @@ -4749,16 +3317,12 @@ return; } } else { - int gpcnt; - int fpcnt; - int rtype; - getCallInfo(tf(), gpcnt, fpcnt, rtype); Label retaddr; __ adr(rscratch2, retaddr); __ lea(rscratch1, RuntimeAddress(entry)); // Leave a breadcrumb for JavaFrameAnchor::capture_last_Java_pc() __ stp(zr, rscratch2, Address(__ pre(sp, -2 * wordSize))); - __ blrt(rscratch1, gpcnt, fpcnt, rtype); + __ blr(rscratch1); __ bind(retaddr); __ add(sp, sp, 2 * wordSize); } @@ -4815,39 +3379,23 @@ __ biased_locking_enter(box, oop, disp_hdr, tmp, true, cont); } - // Handle existing monitor + // Check for existing monitor if ((EmitSync & 0x02) == 0) { __ tbnz(disp_hdr, exact_log2(markOopDesc::monitor_value), object_has_monitor); } - // Set displaced_header to be (markOop of object | UNLOCK_VALUE). - __ orr(disp_hdr, disp_hdr, markOopDesc::unlocked_value); - - // Load Compare Value application register. + // Set tmp to be (markOop of object | UNLOCK_VALUE). + __ orr(tmp, disp_hdr, markOopDesc::unlocked_value); // Initialize the box. (Must happen before we update the object mark!) - __ str(disp_hdr, Address(box, BasicLock::displaced_header_offset_in_bytes())); + __ str(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes())); - // Compare object markOop with mark and if equal exchange scratch1 - // with object markOop. - if (UseLSE) { - __ mov(tmp, disp_hdr); - __ casal(Assembler::xword, tmp, box, oop); - __ cmp(tmp, disp_hdr); - __ br(Assembler::EQ, cont); - } else { - Label retry_load; - if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) - __ prfm(Address(oop), PSTL1STRM); - __ bind(retry_load); - __ ldaxr(tmp, oop); - __ cmp(tmp, disp_hdr); - __ br(Assembler::NE, cas_failed); - // use stlxr to ensure update is immediately visible - __ stlxr(tmp, box, oop); - __ cbzw(tmp, cont); - __ b(retry_load); - } + // Compare object markOop with an unlocked value (tmp) and if + // equal exchange the stack address of our box with object markOop. + // On failure disp_hdr contains the possibly locked markOop. + __ cmpxchg(oop, tmp, box, Assembler::xword, /*acquire*/ true, + /*release*/ true, /*weak*/ false, disp_hdr); + __ br(Assembler::EQ, cont); assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0"); @@ -4861,41 +3409,24 @@ // markOop of object (disp_hdr) with the stack pointer. __ mov(rscratch1, sp); __ sub(disp_hdr, disp_hdr, rscratch1); - __ mov(tmp, (address) (~(os::vm_page_size()-1) | markOopDesc::lock_mask_in_place)); + __ mov(tmp, (address) (~(os::vm_page_size()-1) | (uintptr_t)markOopDesc::lock_mask_in_place)); // If condition is true we are cont and hence we can store 0 as the // displaced header in the box, which indicates that it is a recursive lock. - __ ands(tmp/*==0?*/, disp_hdr, tmp); + __ ands(tmp/*==0?*/, disp_hdr, tmp); // Sets flags for result __ str(tmp/*==0, perhaps*/, Address(box, BasicLock::displaced_header_offset_in_bytes())); - // Handle existing monitor. if ((EmitSync & 0x02) == 0) { __ b(cont); + // Handle existing monitor. __ bind(object_has_monitor); // The object's monitor m is unlocked iff m->owner == NULL, // otherwise m->owner may contain a thread or a stack address. // // Try to CAS m->owner from NULL to current thread. __ add(tmp, disp_hdr, (ObjectMonitor::owner_offset_in_bytes()-markOopDesc::monitor_value)); - __ mov(disp_hdr, zr); - - if (UseLSE) { - __ mov(rscratch1, disp_hdr); - __ casal(Assembler::xword, rscratch1, rthread, tmp); - __ cmp(rscratch1, disp_hdr); - } else { - Label retry_load, fail; - if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) - __ prfm(Address(tmp), PSTL1STRM); - __ bind(retry_load); - __ ldaxr(rscratch1, tmp); - __ cmp(disp_hdr, rscratch1); - __ br(Assembler::NE, fail); - // use stlxr to ensure update is immediately visible - __ stlxr(rscratch1, rthread, tmp); - __ cbnzw(rscratch1, retry_load); - __ bind(fail); - } + __ cmpxchg(tmp, zr, rthread, Assembler::xword, /*acquire*/ true, + /*release*/ true, /*weak*/ false, noreg); // Sets flags for result // Store a non-null value into the box to avoid looking like a re-entrant // lock. The fast-path monitor unlock code checks for @@ -4948,24 +3479,9 @@ // see the stack address of the basicLock in the markOop of the // object. - if (UseLSE) { - __ mov(tmp, box); - __ casl(Assembler::xword, tmp, disp_hdr, oop); - __ cmp(tmp, box); - __ b(cont); - } else { - Label retry_load; - if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) - __ prfm(Address(oop), PSTL1STRM); - __ bind(retry_load); - __ ldxr(tmp, oop); - __ cmp(box, tmp); - __ br(Assembler::NE, cont); - // use stlxr to ensure update is immediately visible - __ stlxr(tmp, disp_hdr, oop); - __ cbzw(tmp, cont); - __ b(retry_load); - } + __ cmpxchg(oop, box, disp_hdr, Assembler::xword, /*acquire*/ false, + /*release*/ true, /*weak*/ false, tmp); + __ b(cont); assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0"); @@ -4977,13 +3493,13 @@ __ ldr(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes())); __ eor(rscratch1, rscratch1, rthread); // Will be 0 if we are the owner. __ orr(rscratch1, rscratch1, disp_hdr); // Will be 0 if there are 0 recursions - __ cmp(rscratch1, zr); + __ cmp(rscratch1, zr); // Sets flags for result __ br(Assembler::NE, cont); __ ldr(rscratch1, Address(tmp, ObjectMonitor::EntryList_offset_in_bytes())); __ ldr(disp_hdr, Address(tmp, ObjectMonitor::cxq_offset_in_bytes())); __ orr(rscratch1, rscratch1, disp_hdr); // Will be 0 if both are 0. - __ cmp(rscratch1, zr); + __ cmp(rscratch1, zr); // Sets flags for result __ cbnz(rscratch1, cont); // need a release store here __ lea(tmp, Address(tmp, ObjectMonitor::owner_offset_in_bytes())); @@ -5391,7 +3907,8 @@ operand immL_bitmask() %{ - predicate(((n->get_long() & 0xc000000000000000l) == 0) + predicate((n->get_long() != 0) + && ((n->get_long() & 0xc000000000000000l) == 0) && is_power_of_2(n->get_long() + 1)); match(ConL); @@ -5402,7 +3919,8 @@ operand immI_bitmask() %{ - predicate(((n->get_int() & 0xc0000000) == 0) + predicate((n->get_int() != 0) + && ((n->get_int() & 0xc0000000) == 0) && is_power_of_2(n->get_int() + 1)); match(ConI); @@ -5411,6 +3929,18 @@ interface(CONST_INTER); %} +operand immL_positive_bitmaskI() +%{ + predicate((n->get_long() != 0) + && ((julong)n->get_long() < 0x80000000ULL) + && is_power_of_2(n->get_long() + 1)); + match(ConL); + + op_cost(0); + format %{ %} + interface(CONST_INTER); +%} + // Scale values for scaled offset addressing modes (up to long but not quad) operand immIScale() %{ @@ -5549,7 +4079,7 @@ // 32 bit integer valid for add sub immediate operand immIAddSub() %{ - predicate(Assembler::operand_valid_for_add_sub_immediate((long)n->get_int())); + predicate(Assembler::operand_valid_for_add_sub_immediate((int64_t)n->get_int())); match(ConI); op_cost(0); format %{ %} @@ -5560,7 +4090,7 @@ // TODO -- check this is right when e.g the mask is 0x80000000 operand immILog() %{ - predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/true, (unsigned long)n->get_int())); + predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/true, (uint64_t)n->get_int())); match(ConI); op_cost(0); @@ -5638,7 +4168,7 @@ // 64 bit integer valid for logical immediate operand immLLog() %{ - predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/false, (unsigned long)n->get_long())); + predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/false, (uint64_t)n->get_long())); match(ConL); op_cost(0); format %{ %} @@ -9637,6 +8167,44 @@ // alternative CompareAndSwapX when we are eliding barriers +instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{ + + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (CompareAndSwapB mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + + effect(KILL cr); + + format %{ + "cmpxchgb_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval" + "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)" + %} + + ins_encode(aarch64_enc_cmpxchgb_acq(mem, oldval, newval), + aarch64_enc_cset_eq(res)); + + ins_pipe(pipe_slow); +%} + +instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{ + + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (CompareAndSwapS mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + + effect(KILL cr); + + format %{ + "cmpxchgs_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval" + "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)" + %} + + ins_encode(aarch64_enc_cmpxchgs_acq(mem, oldval, newval), + aarch64_enc_cset_eq(res)); + + ins_pipe(pipe_slow); +%} + instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{ predicate(needs_acquiring_load_exclusive(n)); @@ -9735,7 +8303,7 @@ ins_cost(2 * VOLATILE_REF_COST); effect(TEMP_DEF res, KILL cr); format %{ - "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval" + "cmpxchgb $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval" %} ins_encode %{ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, @@ -9751,7 +8319,7 @@ ins_cost(2 * VOLATILE_REF_COST); effect(TEMP_DEF res, KILL cr); format %{ - "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval" + "cmpxchgs $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval" %} ins_encode %{ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, @@ -9767,7 +8335,7 @@ ins_cost(2 * VOLATILE_REF_COST); effect(TEMP_DEF res, KILL cr); format %{ - "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval" + "cmpxchgw $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval" %} ins_encode %{ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, @@ -9797,7 +8365,7 @@ ins_cost(2 * VOLATILE_REF_COST); effect(TEMP_DEF res, KILL cr); format %{ - "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval" + "cmpxchgw $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval" %} ins_encode %{ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, @@ -9822,12 +8390,112 @@ ins_pipe(pipe_slow); %} +instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (CompareAndExchangeB mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + effect(TEMP_DEF res, KILL cr); + format %{ + "cmpxchgb_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval" + %} + ins_encode %{ + __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, + Assembler::byte, /*acquire*/ true, /*release*/ true, + /*weak*/ false, $res$$Register); + __ sxtbw($res$$Register, $res$$Register); + %} + ins_pipe(pipe_slow); +%} + +instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (CompareAndExchangeS mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + effect(TEMP_DEF res, KILL cr); + format %{ + "cmpxchgs_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval" + %} + ins_encode %{ + __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, + Assembler::halfword, /*acquire*/ true, /*release*/ true, + /*weak*/ false, $res$$Register); + __ sxthw($res$$Register, $res$$Register); + %} + ins_pipe(pipe_slow); +%} + + +instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (CompareAndExchangeI mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + effect(TEMP_DEF res, KILL cr); + format %{ + "cmpxchgw_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval" + %} + ins_encode %{ + __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, + Assembler::word, /*acquire*/ true, /*release*/ true, + /*weak*/ false, $res$$Register); + %} + ins_pipe(pipe_slow); +%} + +instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (CompareAndExchangeL mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + effect(TEMP_DEF res, KILL cr); + format %{ + "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval" + %} + ins_encode %{ + __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, + Assembler::xword, /*acquire*/ true, /*release*/ true, + /*weak*/ false, $res$$Register); + %} + ins_pipe(pipe_slow); +%} + + +instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (CompareAndExchangeN mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + effect(TEMP_DEF res, KILL cr); + format %{ + "cmpxchgw_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval" + %} + ins_encode %{ + __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, + Assembler::word, /*acquire*/ true, /*release*/ true, + /*weak*/ false, $res$$Register); + %} + ins_pipe(pipe_slow); +%} + +instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (CompareAndExchangeP mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + effect(TEMP_DEF res, KILL cr); + format %{ + "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval" + %} + ins_encode %{ + __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, + Assembler::xword, /*acquire*/ true, /*release*/ true, + /*weak*/ false, $res$$Register); + %} + ins_pipe(pipe_slow); +%} + instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{ match(Set res (WeakCompareAndSwapB mem (Binary oldval newval))); ins_cost(2 * VOLATILE_REF_COST); effect(KILL cr); format %{ - "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval" + "cmpxchgb $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval" "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)" %} ins_encode %{ @@ -9844,7 +8512,7 @@ ins_cost(2 * VOLATILE_REF_COST); effect(KILL cr); format %{ - "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval" + "cmpxchgs $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval" "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)" %} ins_encode %{ @@ -9861,7 +8529,7 @@ ins_cost(2 * VOLATILE_REF_COST); effect(KILL cr); format %{ - "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval" + "cmpxchgw $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval" "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)" %} ins_encode %{ @@ -9895,7 +8563,7 @@ ins_cost(2 * VOLATILE_REF_COST); effect(KILL cr); format %{ - "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval" + "cmpxchgw $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval" "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)" %} ins_encode %{ @@ -9924,11 +8592,120 @@ ins_pipe(pipe_slow); %} +instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (WeakCompareAndSwapB mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + effect(KILL cr); + format %{ + "cmpxchgb_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval" + "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)" + %} + ins_encode %{ + __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, + Assembler::byte, /*acquire*/ true, /*release*/ true, + /*weak*/ true, noreg); + __ csetw($res$$Register, Assembler::EQ); + %} + ins_pipe(pipe_slow); +%} + +instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (WeakCompareAndSwapS mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + effect(KILL cr); + format %{ + "cmpxchgs_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval" + "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)" + %} + ins_encode %{ + __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, + Assembler::halfword, /*acquire*/ true, /*release*/ true, + /*weak*/ true, noreg); + __ csetw($res$$Register, Assembler::EQ); + %} + ins_pipe(pipe_slow); +%} + +instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (WeakCompareAndSwapI mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + effect(KILL cr); + format %{ + "cmpxchgw_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval" + "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)" + %} + ins_encode %{ + __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, + Assembler::word, /*acquire*/ true, /*release*/ true, + /*weak*/ true, noreg); + __ csetw($res$$Register, Assembler::EQ); + %} + ins_pipe(pipe_slow); +%} + +instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (WeakCompareAndSwapL mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + effect(KILL cr); + format %{ + "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval" + "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)" + %} + ins_encode %{ + __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, + Assembler::xword, /*acquire*/ true, /*release*/ true, + /*weak*/ true, noreg); + __ csetw($res$$Register, Assembler::EQ); + %} + ins_pipe(pipe_slow); +%} + +instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (WeakCompareAndSwapN mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + effect(KILL cr); + format %{ + "cmpxchgw_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval" + "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)" + %} + ins_encode %{ + __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, + Assembler::word, /*acquire*/ true, /*release*/ true, + /*weak*/ true, noreg); + __ csetw($res$$Register, Assembler::EQ); + %} + ins_pipe(pipe_slow); +%} + +instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + effect(KILL cr); + format %{ + "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval" + "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)" + %} + ins_encode %{ + __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, + Assembler::xword, /*acquire*/ true, /*release*/ true, + /*weak*/ true, noreg); + __ csetw($res$$Register, Assembler::EQ); + %} + ins_pipe(pipe_slow); +%} + // END This section of the file is automatically generated. Do not edit -------------- // --------------------------------------------------------------------- instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev) %{ match(Set prev (GetAndSetI mem newv)); + ins_cost(2 * VOLATILE_REF_COST); format %{ "atomic_xchgw $prev, $newv, [$mem]" %} ins_encode %{ __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base)); @@ -9938,6 +8715,7 @@ instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev) %{ match(Set prev (GetAndSetL mem newv)); + ins_cost(2 * VOLATILE_REF_COST); format %{ "atomic_xchg $prev, $newv, [$mem]" %} ins_encode %{ __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base)); @@ -9947,6 +8725,7 @@ instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev) %{ match(Set prev (GetAndSetN mem newv)); + ins_cost(2 * VOLATILE_REF_COST); format %{ "atomic_xchgw $prev, $newv, [$mem]" %} ins_encode %{ __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base)); @@ -9956,6 +8735,7 @@ instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev) %{ match(Set prev (GetAndSetP mem newv)); + ins_cost(2 * VOLATILE_REF_COST); format %{ "atomic_xchg $prev, $newv, [$mem]" %} ins_encode %{ __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base)); @@ -9963,10 +8743,54 @@ ins_pipe(pipe_serial); %} +instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set prev (GetAndSetI mem newv)); + ins_cost(VOLATILE_REF_COST); + format %{ "atomic_xchgw_acq $prev, $newv, [$mem]" %} + ins_encode %{ + __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base)); + %} + ins_pipe(pipe_serial); +%} + +instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set prev (GetAndSetL mem newv)); + ins_cost(VOLATILE_REF_COST); + format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %} + ins_encode %{ + __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base)); + %} + ins_pipe(pipe_serial); +%} + +instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set prev (GetAndSetN mem newv)); + ins_cost(VOLATILE_REF_COST); + format %{ "atomic_xchgw_acq $prev, $newv, [$mem]" %} + ins_encode %{ + __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base)); + %} + ins_pipe(pipe_serial); +%} + +instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set prev (GetAndSetP mem newv)); + ins_cost(VOLATILE_REF_COST); + format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %} + ins_encode %{ + __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base)); + %} + ins_pipe(pipe_serial); +%} + instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr) %{ match(Set newval (GetAndAddL mem incr)); - ins_cost(INSN_COST * 10); + ins_cost(2 * VOLATILE_REF_COST + 1); format %{ "get_and_addL $newval, [$mem], $incr" %} ins_encode %{ __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base)); @@ -9977,7 +8801,7 @@ instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr) %{ predicate(n->as_LoadStore()->result_not_used()); match(Set dummy (GetAndAddL mem incr)); - ins_cost(INSN_COST * 9); + ins_cost(2 * VOLATILE_REF_COST); format %{ "get_and_addL [$mem], $incr" %} ins_encode %{ __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base)); @@ -9987,7 +8811,7 @@ instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAddSub incr) %{ match(Set newval (GetAndAddL mem incr)); - ins_cost(INSN_COST * 10); + ins_cost(2 * VOLATILE_REF_COST + 1); format %{ "get_and_addL $newval, [$mem], $incr" %} ins_encode %{ __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base)); @@ -9998,7 +8822,7 @@ instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAddSub incr) %{ predicate(n->as_LoadStore()->result_not_used()); match(Set dummy (GetAndAddL mem incr)); - ins_cost(INSN_COST * 9); + ins_cost(2 * VOLATILE_REF_COST); format %{ "get_and_addL [$mem], $incr" %} ins_encode %{ __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base)); @@ -10008,7 +8832,7 @@ instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr) %{ match(Set newval (GetAndAddI mem incr)); - ins_cost(INSN_COST * 10); + ins_cost(2 * VOLATILE_REF_COST + 1); format %{ "get_and_addI $newval, [$mem], $incr" %} ins_encode %{ __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base)); @@ -10019,7 +8843,7 @@ instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr) %{ predicate(n->as_LoadStore()->result_not_used()); match(Set dummy (GetAndAddI mem incr)); - ins_cost(INSN_COST * 9); + ins_cost(2 * VOLATILE_REF_COST); format %{ "get_and_addI [$mem], $incr" %} ins_encode %{ __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base)); @@ -10029,7 +8853,7 @@ instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAddSub incr) %{ match(Set newval (GetAndAddI mem incr)); - ins_cost(INSN_COST * 10); + ins_cost(2 * VOLATILE_REF_COST + 1); format %{ "get_and_addI $newval, [$mem], $incr" %} ins_encode %{ __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base)); @@ -10040,7 +8864,7 @@ instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAddSub incr) %{ predicate(n->as_LoadStore()->result_not_used()); match(Set dummy (GetAndAddI mem incr)); - ins_cost(INSN_COST * 9); + ins_cost(2 * VOLATILE_REF_COST); format %{ "get_and_addI [$mem], $incr" %} ins_encode %{ __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base)); @@ -10048,6 +8872,94 @@ ins_pipe(pipe_serial); %} +instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set newval (GetAndAddL mem incr)); + ins_cost(VOLATILE_REF_COST + 1); + format %{ "get_and_addL_acq $newval, [$mem], $incr" %} + ins_encode %{ + __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base)); + %} + ins_pipe(pipe_serial); +%} + +instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{ + predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n)); + match(Set dummy (GetAndAddL mem incr)); + ins_cost(VOLATILE_REF_COST); + format %{ "get_and_addL_acq [$mem], $incr" %} + ins_encode %{ + __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base)); + %} + ins_pipe(pipe_serial); +%} + +instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAddSub incr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set newval (GetAndAddL mem incr)); + ins_cost(VOLATILE_REF_COST + 1); + format %{ "get_and_addL_acq $newval, [$mem], $incr" %} + ins_encode %{ + __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base)); + %} + ins_pipe(pipe_serial); +%} + +instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAddSub incr) %{ + predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n)); + match(Set dummy (GetAndAddL mem incr)); + ins_cost(VOLATILE_REF_COST); + format %{ "get_and_addL_acq [$mem], $incr" %} + ins_encode %{ + __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base)); + %} + ins_pipe(pipe_serial); +%} + +instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set newval (GetAndAddI mem incr)); + ins_cost(VOLATILE_REF_COST + 1); + format %{ "get_and_addI_acq $newval, [$mem], $incr" %} + ins_encode %{ + __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base)); + %} + ins_pipe(pipe_serial); +%} + +instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr) %{ + predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n)); + match(Set dummy (GetAndAddI mem incr)); + ins_cost(VOLATILE_REF_COST); + format %{ "get_and_addI_acq [$mem], $incr" %} + ins_encode %{ + __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base)); + %} + ins_pipe(pipe_serial); +%} + +instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAddSub incr) %{ + predicate(needs_acquiring_load_exclusive(n)); + match(Set newval (GetAndAddI mem incr)); + ins_cost(VOLATILE_REF_COST + 1); + format %{ "get_and_addI_acq $newval, [$mem], $incr" %} + ins_encode %{ + __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base)); + %} + ins_pipe(pipe_serial); +%} + +instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAddSub incr) %{ + predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n)); + match(Set dummy (GetAndAddI mem incr)); + ins_cost(VOLATILE_REF_COST); + format %{ "get_and_addI_acq [$mem], $incr" %} + ins_encode %{ + __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base)); + %} + ins_pipe(pipe_serial); +%} + // Manifest a CmpL result in an integer register. // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0) instruct cmpL3_reg_reg(iRegINoSp dst, iRegL src1, iRegL src2, rFlagsReg flags) @@ -10748,7 +9660,7 @@ ins_encode %{ __ sbfiz(as_Register($dst$$reg), as_Register($src$$reg), - $scale$$constant & 63, MIN(32, (-$scale$$constant) & 63)); + $scale$$constant & 63, MIN2(32, (int)((-$scale$$constant) & 63))); %} ins_pipe(ialu_reg_shift); @@ -11031,6 +9943,56 @@ ins_pipe(lmac_reg_reg); %} +// Combine Integer Signed Multiply & Add/Sub/Neg Long + +instruct smaddL(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegLNoSp src3) %{ + match(Set dst (AddL src3 (MulL (ConvI2L src1) (ConvI2L src2)))); + + ins_cost(INSN_COST * 3); + format %{ "smaddl $dst, $src1, $src2, $src3" %} + + ins_encode %{ + __ smaddl(as_Register($dst$$reg), + as_Register($src1$$reg), + as_Register($src2$$reg), + as_Register($src3$$reg)); + %} + + ins_pipe(imac_reg_reg); +%} + +instruct smsubL(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegLNoSp src3) %{ + match(Set dst (SubL src3 (MulL (ConvI2L src1) (ConvI2L src2)))); + + ins_cost(INSN_COST * 3); + format %{ "smsubl $dst, $src1, $src2, $src3" %} + + ins_encode %{ + __ smsubl(as_Register($dst$$reg), + as_Register($src1$$reg), + as_Register($src2$$reg), + as_Register($src3$$reg)); + %} + + ins_pipe(imac_reg_reg); +%} + +instruct smnegL(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2, immL0 zero) %{ + match(Set dst (MulL (SubL zero (ConvI2L src1)) (ConvI2L src2))); + match(Set dst (MulL (ConvI2L src1) (SubL zero (ConvI2L src2)))); + + ins_cost(INSN_COST * 3); + format %{ "smnegl $dst, $src1, $src2" %} + + ins_encode %{ + __ smnegl(as_Register($dst$$reg), + as_Register($src1$$reg), + as_Register($src2$$reg)); + %} + + ins_pipe(imac_reg_reg); +%} + // Integer Divide instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{ @@ -11043,30 +10005,6 @@ ins_pipe(idiv_reg_reg); %} -instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{ - match(Set dst (URShiftI (RShiftI src1 div1) div2)); - ins_cost(INSN_COST); - format %{ "lsrw $dst, $src1, $div1" %} - ins_encode %{ - __ lsrw(as_Register($dst$$reg), as_Register($src1$$reg), 31); - %} - ins_pipe(ialu_reg_shift); -%} - -instruct div2Round(iRegINoSp dst, iRegIorL2I src, immI_31 div1, immI_31 div2) %{ - match(Set dst (AddI src (URShiftI (RShiftI src div1) div2))); - ins_cost(INSN_COST); - format %{ "addw $dst, $src, LSR $div1" %} - - ins_encode %{ - __ addw(as_Register($dst$$reg), - as_Register($src$$reg), - as_Register($src$$reg), - Assembler::LSR, 31); - %} - ins_pipe(ialu_reg); -%} - // Long Divide instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{ @@ -11079,30 +10017,6 @@ ins_pipe(ldiv_reg_reg); %} -instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{ - match(Set dst (URShiftL (RShiftL src1 div1) div2)); - ins_cost(INSN_COST); - format %{ "lsr $dst, $src1, $div1" %} - ins_encode %{ - __ lsr(as_Register($dst$$reg), as_Register($src1$$reg), 63); - %} - ins_pipe(ialu_reg_shift); -%} - -instruct div2RoundL(iRegLNoSp dst, iRegL src, immI_63 div1, immI_63 div2) %{ - match(Set dst (AddL src (URShiftL (RShiftL src div1) div2))); - ins_cost(INSN_COST); - format %{ "add $dst, $src, $div1" %} - - ins_encode %{ - __ add(as_Register($dst$$reg), - as_Register($src$$reg), - as_Register($src$$reg), - Assembler::LSR, 63); - %} - ins_pipe(ialu_reg); -%} - // Integer Remainder instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{ @@ -11346,6 +10260,10 @@ // BEGIN This section of the file is automatically generated. Do not edit -------------- + + +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1, rFlagsReg cr) %{ @@ -11362,6 +10280,9 @@ ins_pipe(ialu_reg); %} + +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct regI_not_reg(iRegINoSp dst, iRegIorL2I src1, immI_M1 m1, rFlagsReg cr) %{ @@ -11379,6 +10300,8 @@ ins_pipe(ialu_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndI_reg_not_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1, rFlagsReg cr) %{ @@ -11396,6 +10319,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndL_reg_not_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immL_M1 m1, rFlagsReg cr) %{ @@ -11413,6 +10338,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrI_reg_not_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1, rFlagsReg cr) %{ @@ -11430,6 +10357,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrL_reg_not_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immL_M1 m1, rFlagsReg cr) %{ @@ -11447,6 +10376,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorI_reg_not_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1, rFlagsReg cr) %{ @@ -11464,6 +10395,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorL_reg_not_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immL_M1 m1, rFlagsReg cr) %{ @@ -11481,6 +10414,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndI_reg_URShift_not_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, immI_M1 src4, rFlagsReg cr) %{ @@ -11499,6 +10434,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndL_reg_URShift_not_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, immL_M1 src4, rFlagsReg cr) %{ @@ -11517,6 +10454,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndI_reg_RShift_not_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, immI_M1 src4, rFlagsReg cr) %{ @@ -11535,6 +10474,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndL_reg_RShift_not_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, immL_M1 src4, rFlagsReg cr) %{ @@ -11553,6 +10494,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndI_reg_LShift_not_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, immI_M1 src4, rFlagsReg cr) %{ @@ -11571,6 +10514,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndL_reg_LShift_not_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, immL_M1 src4, rFlagsReg cr) %{ @@ -11589,6 +10534,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorI_reg_URShift_not_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, immI_M1 src4, rFlagsReg cr) %{ @@ -11607,6 +10554,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorL_reg_URShift_not_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, immL_M1 src4, rFlagsReg cr) %{ @@ -11625,6 +10574,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorI_reg_RShift_not_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, immI_M1 src4, rFlagsReg cr) %{ @@ -11643,6 +10594,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorL_reg_RShift_not_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, immL_M1 src4, rFlagsReg cr) %{ @@ -11661,6 +10614,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorI_reg_LShift_not_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, immI_M1 src4, rFlagsReg cr) %{ @@ -11679,6 +10634,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorL_reg_LShift_not_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, immL_M1 src4, rFlagsReg cr) %{ @@ -11697,6 +10654,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrI_reg_URShift_not_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, immI_M1 src4, rFlagsReg cr) %{ @@ -11715,6 +10674,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrL_reg_URShift_not_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, immL_M1 src4, rFlagsReg cr) %{ @@ -11733,6 +10694,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrI_reg_RShift_not_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, immI_M1 src4, rFlagsReg cr) %{ @@ -11751,6 +10714,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrL_reg_RShift_not_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, immL_M1 src4, rFlagsReg cr) %{ @@ -11769,6 +10734,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrI_reg_LShift_not_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, immI_M1 src4, rFlagsReg cr) %{ @@ -11787,6 +10754,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrL_reg_LShift_not_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, immL_M1 src4, rFlagsReg cr) %{ @@ -11805,6 +10774,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndI_reg_URShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -11824,6 +10795,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndL_reg_URShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -11843,6 +10816,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndI_reg_RShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -11862,6 +10837,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndL_reg_RShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -11881,6 +10858,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndI_reg_LShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -11900,6 +10879,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AndL_reg_LShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -11919,6 +10900,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorI_reg_URShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -11938,6 +10921,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorL_reg_URShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -11957,6 +10942,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorI_reg_RShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -11976,6 +10963,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorL_reg_RShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -11995,6 +10984,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorI_reg_LShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -12014,6 +11005,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct XorL_reg_LShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -12033,6 +11026,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrI_reg_URShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -12052,6 +11047,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrL_reg_URShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -12071,6 +11068,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrI_reg_RShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -12090,6 +11089,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrL_reg_RShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -12109,6 +11110,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrI_reg_LShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -12128,6 +11131,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct OrL_reg_LShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -12147,6 +11152,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddI_reg_URShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -12166,6 +11173,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddL_reg_URShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -12185,6 +11194,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddI_reg_RShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -12204,6 +11215,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddL_reg_RShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -12223,6 +11236,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddI_reg_LShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -12242,6 +11257,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddL_reg_LShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -12261,6 +11278,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubI_reg_URShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -12280,6 +11299,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubL_reg_URShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -12299,6 +11320,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubI_reg_RShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -12318,6 +11341,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubL_reg_RShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -12337,6 +11362,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubI_reg_LShift_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI src3, rFlagsReg cr) %{ @@ -12356,6 +11383,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubL_reg_LShift_reg(iRegLNoSp dst, iRegL src1, iRegL src2, immI src3, rFlagsReg cr) %{ @@ -12375,21 +11404,20 @@ ins_pipe(ialu_reg_reg_shift); %} - + +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE // Shift Left followed by Shift Right. // This idiom is used by the compiler for the i2b bytecode etc. instruct sbfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count) %{ match(Set dst (RShiftL (LShiftL src lshift_count) rshift_count)); - // Make sure we are not going to exceed what sbfm can do. - predicate((unsigned int)n->in(2)->get_int() <= 63 - && (unsigned int)n->in(1)->in(2)->get_int() <= 63); - ins_cost(INSN_COST * 2); format %{ "sbfm $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %} ins_encode %{ - int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant; + int lshift = $lshift_count$$constant & 63; + int rshift = $rshift_count$$constant & 63; int s = 63 - lshift; int r = (rshift - lshift) & 63; __ sbfm(as_Register($dst$$reg), @@ -12400,19 +11428,19 @@ ins_pipe(ialu_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE + // Shift Left followed by Shift Right. // This idiom is used by the compiler for the i2b bytecode etc. instruct sbfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count) %{ match(Set dst (RShiftI (LShiftI src lshift_count) rshift_count)); - // Make sure we are not going to exceed what sbfmw can do. - predicate((unsigned int)n->in(2)->get_int() <= 31 - && (unsigned int)n->in(1)->in(2)->get_int() <= 31); - ins_cost(INSN_COST * 2); format %{ "sbfmw $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %} ins_encode %{ - int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant; + int lshift = $lshift_count$$constant & 31; + int rshift = $rshift_count$$constant & 31; int s = 31 - lshift; int r = (rshift - lshift) & 31; __ sbfmw(as_Register($dst$$reg), @@ -12423,19 +11451,19 @@ ins_pipe(ialu_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE + // Shift Left followed by Shift Right. // This idiom is used by the compiler for the i2b bytecode etc. instruct ubfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count) %{ match(Set dst (URShiftL (LShiftL src lshift_count) rshift_count)); - // Make sure we are not going to exceed what ubfm can do. - predicate((unsigned int)n->in(2)->get_int() <= 63 - && (unsigned int)n->in(1)->in(2)->get_int() <= 63); - ins_cost(INSN_COST * 2); format %{ "ubfm $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %} ins_encode %{ - int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant; + int lshift = $lshift_count$$constant & 63; + int rshift = $rshift_count$$constant & 63; int s = 63 - lshift; int r = (rshift - lshift) & 63; __ ubfm(as_Register($dst$$reg), @@ -12446,19 +11474,19 @@ ins_pipe(ialu_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE + // Shift Left followed by Shift Right. // This idiom is used by the compiler for the i2b bytecode etc. instruct ubfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count) %{ match(Set dst (URShiftI (LShiftI src lshift_count) rshift_count)); - // Make sure we are not going to exceed what ubfmw can do. - predicate((unsigned int)n->in(2)->get_int() <= 31 - && (unsigned int)n->in(1)->in(2)->get_int() <= 31); - ins_cost(INSN_COST * 2); format %{ "ubfmw $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %} ins_encode %{ - int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant; + int lshift = $lshift_count$$constant & 31; + int rshift = $rshift_count$$constant & 31; int s = 31 - lshift; int r = (rshift - lshift) & 31; __ ubfmw(as_Register($dst$$reg), @@ -12468,50 +11496,66 @@ ins_pipe(ialu_reg_shift); %} + // Bitfield extract with shift & mask +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct ubfxwI(iRegINoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask) %{ match(Set dst (AndI (URShiftI src rshift) mask)); + // Make sure we are not going to exceed what ubfxw can do. + predicate((exact_log2(n->in(2)->get_int() + 1) + (n->in(1)->in(2)->get_int() & 31)) <= (31 + 1)); ins_cost(INSN_COST); format %{ "ubfxw $dst, $src, $rshift, $mask" %} ins_encode %{ - int rshift = $rshift$$constant; - long mask = $mask$$constant; + int rshift = $rshift$$constant & 31; + intptr_t mask = $mask$$constant; int width = exact_log2(mask+1); __ ubfxw(as_Register($dst$$reg), as_Register($src$$reg), rshift, width); %} ins_pipe(ialu_reg_shift); %} + +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct ubfxL(iRegLNoSp dst, iRegL src, immI rshift, immL_bitmask mask) %{ match(Set dst (AndL (URShiftL src rshift) mask)); + // Make sure we are not going to exceed what ubfx can do. + predicate((exact_log2_long(n->in(2)->get_long() + 1) + (n->in(1)->in(2)->get_int() & 63)) <= (63 + 1)); ins_cost(INSN_COST); format %{ "ubfx $dst, $src, $rshift, $mask" %} ins_encode %{ - int rshift = $rshift$$constant; - long mask = $mask$$constant; - int width = exact_log2(mask+1); + int rshift = $rshift$$constant & 63; + intptr_t mask = $mask$$constant; + int width = exact_log2_long(mask+1); __ ubfx(as_Register($dst$$reg), as_Register($src$$reg), rshift, width); %} ins_pipe(ialu_reg_shift); %} + +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE + // We can use ubfx when extending an And with a mask when we know mask // is positive. We know that because immI_bitmask guarantees it. instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask) %{ match(Set dst (ConvI2L (AndI (URShiftI src rshift) mask))); + // Make sure we are not going to exceed what ubfxw can do. + predicate((exact_log2(n->in(1)->in(2)->get_int() + 1) + (n->in(1)->in(1)->in(2)->get_int() & 31)) <= (31 + 1)); ins_cost(INSN_COST * 2); format %{ "ubfx $dst, $src, $rshift, $mask" %} ins_encode %{ - int rshift = $rshift$$constant; - long mask = $mask$$constant; + int rshift = $rshift$$constant & 31; + intptr_t mask = $mask$$constant; int width = exact_log2(mask+1); __ ubfx(as_Register($dst$$reg), as_Register($src$$reg), rshift, width); @@ -12519,57 +11563,110 @@ ins_pipe(ialu_reg_shift); %} + +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE + // We can use ubfiz when masking by a positive number and then left shifting the result. // We know that the mask is positive because immI_bitmask guarantees it. instruct ubfizwI(iRegINoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask) %{ match(Set dst (LShiftI (AndI src mask) lshift)); - predicate((unsigned int)n->in(2)->get_int() <= 31 && - (exact_log2(n->in(1)->in(2)->get_int()+1) + (unsigned int)n->in(2)->get_int()) <= (31+1)); + predicate((exact_log2(n->in(1)->in(2)->get_int() + 1) + (n->in(2)->get_int() & 31)) <= (31 + 1)); ins_cost(INSN_COST); format %{ "ubfizw $dst, $src, $lshift, $mask" %} ins_encode %{ - int lshift = $lshift$$constant; - long mask = $mask$$constant; + int lshift = $lshift$$constant & 31; + intptr_t mask = $mask$$constant; int width = exact_log2(mask+1); __ ubfizw(as_Register($dst$$reg), as_Register($src$$reg), lshift, width); %} ins_pipe(ialu_reg_shift); %} + +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE + // We can use ubfiz when masking by a positive number and then left shifting the result. // We know that the mask is positive because immL_bitmask guarantees it. instruct ubfizL(iRegLNoSp dst, iRegL src, immI lshift, immL_bitmask mask) %{ match(Set dst (LShiftL (AndL src mask) lshift)); - predicate((unsigned int)n->in(2)->get_int() <= 63 && - (exact_log2_long(n->in(1)->in(2)->get_long()+1) + (unsigned int)n->in(2)->get_int()) <= (63+1)); + predicate((exact_log2_long(n->in(1)->in(2)->get_long() + 1) + (n->in(2)->get_int() & 63)) <= (63 + 1)); ins_cost(INSN_COST); format %{ "ubfiz $dst, $src, $lshift, $mask" %} ins_encode %{ - int lshift = $lshift$$constant; - long mask = $mask$$constant; - int width = exact_log2(mask+1); + int lshift = $lshift$$constant & 63; + intptr_t mask = $mask$$constant; + int width = exact_log2_long(mask+1); __ ubfiz(as_Register($dst$$reg), as_Register($src$$reg), lshift, width); %} ins_pipe(ialu_reg_shift); %} -// If there is a convert I to L block between and AndI and a LShiftL, we can also match ubfiz -instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask) +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE + +// We can use ubfiz when masking by a positive number and then left shifting the result. +// We know that the mask is positive because immI_bitmask guarantees it. +instruct ubfizwIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask) %{ - match(Set dst (LShiftL (ConvI2L(AndI src mask)) lshift)); - predicate((unsigned int)n->in(2)->get_int() <= 31 && - (exact_log2((unsigned int)n->in(1)->in(1)->in(2)->get_int()+1) + (unsigned int)n->in(2)->get_int()) <= 32); + match(Set dst (ConvI2L (LShiftI (AndI src mask) lshift))); + predicate((exact_log2(n->in(1)->in(1)->in(2)->get_int() + 1) + (n->in(1)->in(2)->get_int() & 31)) <= 31); + + ins_cost(INSN_COST); + format %{ "ubfizw $dst, $src, $lshift, $mask" %} + ins_encode %{ + int lshift = $lshift$$constant & 31; + intptr_t mask = $mask$$constant; + int width = exact_log2(mask+1); + __ ubfizw(as_Register($dst$$reg), + as_Register($src$$reg), lshift, width); + %} + ins_pipe(ialu_reg_shift); +%} + +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE + +// We can use ubfiz when masking by a positive number and then left shifting the result. +// We know that the mask is positive because immL_bitmask guarantees it. +instruct ubfizLConvL2I(iRegINoSp dst, iRegL src, immI lshift, immL_positive_bitmaskI mask) +%{ + match(Set dst (ConvL2I (LShiftL (AndL src mask) lshift))); + predicate((exact_log2_long(n->in(1)->in(1)->in(2)->get_long() + 1) + (n->in(1)->in(2)->get_int() & 63)) <= 31); ins_cost(INSN_COST); format %{ "ubfiz $dst, $src, $lshift, $mask" %} ins_encode %{ - int lshift = $lshift$$constant; - long mask = $mask$$constant; + int lshift = $lshift$$constant & 63; + intptr_t mask = $mask$$constant; + int width = exact_log2_long(mask+1); + __ ubfiz(as_Register($dst$$reg), + as_Register($src$$reg), lshift, width); + %} + ins_pipe(ialu_reg_shift); +%} + + +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE + +// If there is a convert I to L block between and AndI and a LShiftL, we can also match ubfiz +instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask) +%{ + match(Set dst (LShiftL (ConvI2L (AndI src mask)) lshift)); + predicate((exact_log2(n->in(1)->in(1)->in(2)->get_int() + 1) + (n->in(2)->get_int() & 63)) <= (63 + 1)); + + ins_cost(INSN_COST); + format %{ "ubfiz $dst, $src, $lshift, $mask" %} + ins_encode %{ + int lshift = $lshift$$constant & 63; + intptr_t mask = $mask$$constant; int width = exact_log2(mask+1); __ ubfiz(as_Register($dst$$reg), as_Register($src$$reg), lshift, width); @@ -12577,12 +11674,47 @@ ins_pipe(ialu_reg_shift); %} -// Rotations +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE +// If there is a convert L to I block between and AndL and a LShiftI, we can also match ubfiz +instruct ubfizLConvL2Ix(iRegINoSp dst, iRegL src, immI lshift, immL_positive_bitmaskI mask) +%{ + match(Set dst (LShiftI (ConvL2I (AndL src mask)) lshift)); + predicate((exact_log2_long(n->in(1)->in(1)->in(2)->get_long() + 1) + (n->in(2)->get_int() & 31)) <= 31); + + ins_cost(INSN_COST); + format %{ "ubfiz $dst, $src, $lshift, $mask" %} + ins_encode %{ + int lshift = $lshift$$constant & 31; + intptr_t mask = $mask$$constant; + int width = exact_log2(mask+1); + __ ubfiz(as_Register($dst$$reg), + as_Register($src$$reg), lshift, width); + %} + ins_pipe(ialu_reg_shift); +%} + +// Can skip int2long conversions after AND with small bitmask +instruct ubfizIConvI2LAndI(iRegLNoSp dst, iRegI src, immI_bitmask msk) +%{ + match(Set dst (ConvI2L (AndI src msk))); + ins_cost(INSN_COST); + format %{ "ubfiz $dst, $src, 0, exact_log2($msk + 1) " %} + ins_encode %{ + __ ubfiz(as_Register($dst$$reg), as_Register($src$$reg), 0, exact_log2($msk$$constant + 1)); + %} + ins_pipe(ialu_reg_shift); +%} + + +// Rotations +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr) %{ match(Set dst (OrL (LShiftL src1 lshift) (URShiftL src2 rshift))); - predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 63)); + predicate(0 == (((n->in(1)->in(2)->get_int() & 63) + (n->in(2)->in(2)->get_int() & 63)) & 63)); ins_cost(INSN_COST); format %{ "extr $dst, $src1, $src2, #$rshift" %} @@ -12594,10 +11726,13 @@ ins_pipe(ialu_reg_reg_extr); %} + +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct extrOrI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr) %{ match(Set dst (OrI (LShiftI src1 lshift) (URShiftI src2 rshift))); - predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 31)); + predicate(0 == (((n->in(1)->in(2)->get_int() & 31) + (n->in(2)->in(2)->get_int() & 31)) & 31)); ins_cost(INSN_COST); format %{ "extr $dst, $src1, $src2, #$rshift" %} @@ -12609,10 +11744,13 @@ ins_pipe(ialu_reg_reg_extr); %} + +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct extrAddL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr) %{ match(Set dst (AddL (LShiftL src1 lshift) (URShiftL src2 rshift))); - predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 63)); + predicate(0 == (((n->in(1)->in(2)->get_int() & 63) + (n->in(2)->in(2)->get_int() & 63)) & 63)); ins_cost(INSN_COST); format %{ "extr $dst, $src1, $src2, #$rshift" %} @@ -12624,10 +11762,13 @@ ins_pipe(ialu_reg_reg_extr); %} + +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct extrAddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr) %{ match(Set dst (AddI (LShiftI src1 lshift) (URShiftI src2 rshift))); - predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 31)); + predicate(0 == (((n->in(1)->in(2)->get_int() & 31) + (n->in(2)->in(2)->get_int() & 31)) & 31)); ins_cost(INSN_COST); format %{ "extr $dst, $src1, $src2, #$rshift" %} @@ -12640,8 +11781,10 @@ %} -// rol expander +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE +// rol expander instruct rolL_rReg(iRegLNoSp dst, iRegL src, iRegI shift, rFlagsReg cr) %{ effect(DEF dst, USE src, USE shift); @@ -12656,8 +11799,10 @@ ins_pipe(ialu_reg_reg_vshift); %} -// rol expander +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE +// rol expander instruct rolI_rReg(iRegINoSp dst, iRegI src, iRegI shift, rFlagsReg cr) %{ effect(DEF dst, USE src, USE shift); @@ -12672,6 +11817,8 @@ ins_pipe(ialu_reg_reg_vshift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct rolL_rReg_Var_C_64(iRegLNoSp dst, iRegL src, iRegI shift, immI_64 c_64, rFlagsReg cr) %{ match(Set dst (OrL (LShiftL src shift) (URShiftL src (SubI c_64 shift)))); @@ -12681,6 +11828,8 @@ %} %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct rolL_rReg_Var_C0(iRegLNoSp dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr) %{ match(Set dst (OrL (LShiftL src shift) (URShiftL src (SubI c0 shift)))); @@ -12690,6 +11839,8 @@ %} %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct rolI_rReg_Var_C_32(iRegINoSp dst, iRegI src, iRegI shift, immI_32 c_32, rFlagsReg cr) %{ match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c_32 shift)))); @@ -12699,6 +11850,8 @@ %} %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct rolI_rReg_Var_C0(iRegINoSp dst, iRegI src, iRegI shift, immI0 c0, rFlagsReg cr) %{ match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c0 shift)))); @@ -12708,8 +11861,10 @@ %} %} -// ror expander +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE +// ror expander instruct rorL_rReg(iRegLNoSp dst, iRegL src, iRegI shift, rFlagsReg cr) %{ effect(DEF dst, USE src, USE shift); @@ -12723,8 +11878,10 @@ ins_pipe(ialu_reg_reg_vshift); %} -// ror expander +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE +// ror expander instruct rorI_rReg(iRegINoSp dst, iRegI src, iRegI shift, rFlagsReg cr) %{ effect(DEF dst, USE src, USE shift); @@ -12738,6 +11895,8 @@ ins_pipe(ialu_reg_reg_vshift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct rorL_rReg_Var_C_64(iRegLNoSp dst, iRegL src, iRegI shift, immI_64 c_64, rFlagsReg cr) %{ match(Set dst (OrL (URShiftL src shift) (LShiftL src (SubI c_64 shift)))); @@ -12747,6 +11906,8 @@ %} %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct rorL_rReg_Var_C0(iRegLNoSp dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr) %{ match(Set dst (OrL (URShiftL src shift) (LShiftL src (SubI c0 shift)))); @@ -12756,6 +11917,8 @@ %} %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct rorI_rReg_Var_C_32(iRegINoSp dst, iRegI src, iRegI shift, immI_32 c_32, rFlagsReg cr) %{ match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c_32 shift)))); @@ -12765,6 +11928,8 @@ %} %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct rorI_rReg_Var_C0(iRegINoSp dst, iRegI src, iRegI shift, immI0 c0, rFlagsReg cr) %{ match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c0 shift)))); @@ -12774,8 +11939,11 @@ %} %} + // Add/subtract (extended) +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtI(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, rFlagsReg cr) %{ match(Set dst (AddL src1 (ConvI2L src2))); @@ -12787,8 +11955,10 @@ as_Register($src2$$reg), ext::sxtw); %} ins_pipe(ialu_reg_reg); -%}; +%} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtI(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, rFlagsReg cr) %{ match(Set dst (SubL src1 (ConvI2L src2))); @@ -12800,9 +11970,10 @@ as_Register($src2$$reg), ext::sxtw); %} ins_pipe(ialu_reg_reg); -%}; +%} - +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtI_sxth(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_16 lshift, immI_16 rshift, rFlagsReg cr) %{ match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift))); @@ -12816,6 +11987,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtI_sxtb(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr) %{ match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift))); @@ -12829,6 +12002,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtI_uxtb(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr) %{ match(Set dst (AddI src1 (URShiftI (LShiftI src2 lshift) rshift))); @@ -12842,6 +12017,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtL_sxth(iRegLNoSp dst, iRegL src1, iRegL src2, immI_48 lshift, immI_48 rshift, rFlagsReg cr) %{ match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift))); @@ -12855,6 +12032,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtL_sxtw(iRegLNoSp dst, iRegL src1, iRegL src2, immI_32 lshift, immI_32 rshift, rFlagsReg cr) %{ match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift))); @@ -12868,6 +12047,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtL_sxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr) %{ match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift))); @@ -12881,6 +12062,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtL_uxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr) %{ match(Set dst (AddL src1 (URShiftL (LShiftL src2 lshift) rshift))); @@ -12894,7 +12077,8 @@ ins_pipe(ialu_reg_reg); %} - +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtI_uxtb_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, rFlagsReg cr) %{ match(Set dst (AddI src1 (AndI src2 mask))); @@ -12908,6 +12092,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtI_uxth_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, rFlagsReg cr) %{ match(Set dst (AddI src1 (AndI src2 mask))); @@ -12921,6 +12107,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr) %{ match(Set dst (AddL src1 (AndL src2 mask))); @@ -12934,6 +12122,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr) %{ match(Set dst (AddL src1 (AndL src2 mask))); @@ -12947,6 +12137,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr) %{ match(Set dst (AddL src1 (AndL src2 mask))); @@ -12960,6 +12152,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtI_uxtb_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, rFlagsReg cr) %{ match(Set dst (SubI src1 (AndI src2 mask))); @@ -12973,6 +12167,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtI_uxth_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, rFlagsReg cr) %{ match(Set dst (SubI src1 (AndI src2 mask))); @@ -12986,6 +12182,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr) %{ match(Set dst (SubL src1 (AndL src2 mask))); @@ -12999,6 +12197,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr) %{ match(Set dst (SubL src1 (AndL src2 mask))); @@ -13012,6 +12212,8 @@ ins_pipe(ialu_reg_reg); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr) %{ match(Set dst (SubL src1 (AndL src2 mask))); @@ -13026,6 +12228,8 @@ %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr) %{ match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2))); @@ -13039,6 +12243,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr) %{ match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2))); @@ -13052,6 +12258,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr) %{ match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2))); @@ -13065,6 +12273,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr) %{ match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2))); @@ -13078,6 +12288,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr) %{ match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2))); @@ -13091,6 +12303,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr) %{ match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2))); @@ -13104,6 +12318,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr) %{ match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2))); @@ -13117,6 +12333,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr) %{ match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2))); @@ -13130,6 +12348,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr) %{ match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2))); @@ -13143,6 +12363,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr) %{ match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2))); @@ -13156,7 +12378,8 @@ ins_pipe(ialu_reg_reg_shift); %} - +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr) %{ match(Set dst (AddL src1 (LShiftL (ConvI2L src2) lshift))); @@ -13168,8 +12391,10 @@ as_Register($src2$$reg), ext::sxtw, ($lshift$$constant)); %} ins_pipe(ialu_reg_reg_shift); -%}; +%} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr) %{ match(Set dst (SubL src1 (LShiftL (ConvI2L src2) lshift))); @@ -13181,9 +12406,10 @@ as_Register($src2$$reg), ext::sxtw, ($lshift$$constant)); %} ins_pipe(ialu_reg_reg_shift); -%}; +%} - +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr) %{ match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift))); @@ -13197,6 +12423,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr) %{ match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift))); @@ -13210,6 +12438,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr) %{ match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift))); @@ -13223,6 +12453,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr) %{ match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift))); @@ -13236,6 +12468,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr) %{ match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift))); @@ -13249,6 +12483,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr) %{ match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift))); @@ -13262,6 +12498,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr) %{ match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift))); @@ -13275,6 +12513,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct AddExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr) %{ match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift))); @@ -13288,6 +12528,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr) %{ match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift))); @@ -13301,6 +12543,8 @@ ins_pipe(ialu_reg_reg_shift); %} +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct SubExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr) %{ match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift))); @@ -13313,8 +12557,12 @@ %} ins_pipe(ialu_reg_reg_shift); %} + + + // END This section of the file is automatically generated. Do not edit -------------- + // ============================================================================ // Floating Point Arithmetic Instructions @@ -13550,6 +12798,63 @@ %} +// Math.max(FF)F +instruct maxF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{ + match(Set dst (MaxF src1 src2)); + + format %{ "fmaxs $dst, $src1, $src2" %} + ins_encode %{ + __ fmaxs(as_FloatRegister($dst$$reg), + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg)); + %} + + ins_pipe(fp_dop_reg_reg_s); +%} + +// Math.min(FF)F +instruct minF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{ + match(Set dst (MinF src1 src2)); + + format %{ "fmins $dst, $src1, $src2" %} + ins_encode %{ + __ fmins(as_FloatRegister($dst$$reg), + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg)); + %} + + ins_pipe(fp_dop_reg_reg_s); +%} + +// Math.max(DD)D +instruct maxD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{ + match(Set dst (MaxD src1 src2)); + + format %{ "fmaxd $dst, $src1, $src2" %} + ins_encode %{ + __ fmaxd(as_FloatRegister($dst$$reg), + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg)); + %} + + ins_pipe(fp_dop_reg_reg_d); +%} + +// Math.min(DD)D +instruct minD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{ + match(Set dst (MinD src1 src2)); + + format %{ "fmind $dst, $src1, $src2" %} + ins_encode %{ + __ fmind(as_FloatRegister($dst$$reg), + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg)); + %} + + ins_pipe(fp_dop_reg_reg_d); +%} + + instruct divF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{ match(Set dst (DivF src1 src2)); @@ -13608,6 +12913,40 @@ ins_pipe(fp_uop_d); %} +instruct absI_reg(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr) +%{ + match(Set dst (AbsI src)); + + effect(KILL cr); + ins_cost(INSN_COST * 2); + format %{ "cmpw $src, zr\n\t" + "cnegw $dst, $src, Assembler::LT\t# int abs" + %} + + ins_encode %{ + __ cmpw(as_Register($src$$reg), zr); + __ cnegw(as_Register($dst$$reg), as_Register($src$$reg), Assembler::LT); + %} + ins_pipe(pipe_class_default); +%} + +instruct absL_reg(iRegLNoSp dst, iRegL src, rFlagsReg cr) +%{ + match(Set dst (AbsL src)); + + effect(KILL cr); + ins_cost(INSN_COST * 2); + format %{ "cmp $src, zr\n\t" + "cneg $dst, $src, Assembler::LT\t# long abs" + %} + + ins_encode %{ + __ cmp(as_Register($src$$reg), zr); + __ cneg(as_Register($dst$$reg), as_Register($src$$reg), Assembler::LT); + %} + ins_pipe(pipe_class_default); +%} + instruct absF_reg(vRegF dst, vRegF src) %{ match(Set dst (AbsF src)); @@ -13648,7 +12987,7 @@ %} instruct sqrtF_reg(vRegF dst, vRegF src) %{ - match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); + match(Set dst (SqrtF src)); ins_cost(INSN_COST * 50); format %{ "fsqrts $dst, $src" %} @@ -13660,6 +12999,77 @@ ins_pipe(fp_div_d); %} +instruct copySignD_reg(vRegD dst, vRegD src1, vRegD src2, vRegD zero) %{ + match(Set dst (CopySignD src1 (Binary src2 zero))); + effect(TEMP_DEF dst, USE src1, USE src2, USE zero); + format %{ "CopySignD $dst $src1 $src2" %} + ins_encode %{ + FloatRegister dst = as_FloatRegister($dst$$reg), + src1 = as_FloatRegister($src1$$reg), + src2 = as_FloatRegister($src2$$reg), + zero = as_FloatRegister($zero$$reg); + __ fnegd(dst, zero); + __ bsl(dst, __ T8B, src2, src1); + %} + ins_pipe(fp_uop_d); +%} + +instruct copySignF_reg(vRegF dst, vRegF src1, vRegF src2) %{ + match(Set dst (CopySignF src1 src2)); + effect(TEMP_DEF dst, USE src1, USE src2); + format %{ "CopySignF $dst $src1 $src2" %} + ins_encode %{ + FloatRegister dst = as_FloatRegister($dst$$reg), + src1 = as_FloatRegister($src1$$reg), + src2 = as_FloatRegister($src2$$reg); + __ movi(dst, __ T2S, 0x80, 24); + __ bsl(dst, __ T8B, src2, src1); + %} + ins_pipe(fp_uop_d); +%} + +instruct signumD_reg(vRegD dst, vRegD src, vRegD zero, vRegD one) %{ + match(Set dst (SignumD src (Binary zero one))); + effect(TEMP_DEF dst, USE src, USE zero, USE one); + format %{ "signumD $dst, $src" %} + ins_encode %{ + FloatRegister src = as_FloatRegister($src$$reg), + dst = as_FloatRegister($dst$$reg), + zero = as_FloatRegister($zero$$reg), + one = as_FloatRegister($one$$reg); + __ facgtd(dst, src, zero); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise + __ ushrd(dst, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise + // Bit selection instruction gets bit from "one" for each enabled bit in + // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or + // NaN the whole "src" will be copied because "dst" is zero. For all other + // "src" values dst is 0x7FF..F, which means only the sign bit is copied + // from "src", and all other bits are copied from 1.0. + __ bsl(dst, __ T8B, one, src); + %} + ins_pipe(fp_uop_d); +%} + +instruct signumF_reg(vRegF dst, vRegF src, vRegF zero, vRegF one) %{ + match(Set dst (SignumF src (Binary zero one))); + effect(TEMP_DEF dst, USE src, USE zero, USE one); + format %{ "signumF $dst, $src" %} + ins_encode %{ + FloatRegister src = as_FloatRegister($src$$reg), + dst = as_FloatRegister($dst$$reg), + zero = as_FloatRegister($zero$$reg), + one = as_FloatRegister($one$$reg); + __ facgts(dst, src, zero); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise + __ ushr(dst, __ T2S, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise + // Bit selection instruction gets bit from "one" for each enabled bit in + // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or + // NaN the whole "src" will be copied because "dst" is zero. For all other + // "src" values dst is 0x7FF..F, which means only the sign bit is copied + // from "src", and all other bits are copied from 1.0. + __ bsl(dst, __ T8B, one, src); + %} + ins_pipe(fp_uop_d); +%} + // ============================================================================ // Logical Instructions @@ -13692,7 +13102,7 @@ ins_encode %{ __ andw(as_Register($dst$$reg), as_Register($src1$$reg), - (unsigned long)($src2$$constant)); + (uint64_t)($src2$$constant)); %} ins_pipe(ialu_reg_imm); @@ -13724,7 +13134,7 @@ ins_encode %{ __ orrw(as_Register($dst$$reg), as_Register($src1$$reg), - (unsigned long)($src2$$constant)); + (uint64_t)($src2$$constant)); %} ins_pipe(ialu_reg_imm); @@ -13756,7 +13166,7 @@ ins_encode %{ __ eorw(as_Register($dst$$reg), as_Register($src1$$reg), - (unsigned long)($src2$$constant)); + (uint64_t)($src2$$constant)); %} ins_pipe(ialu_reg_imm); @@ -13789,7 +13199,7 @@ ins_encode %{ __ andr(as_Register($dst$$reg), as_Register($src1$$reg), - (unsigned long)($src2$$constant)); + (uint64_t)($src2$$constant)); %} ins_pipe(ialu_reg_imm); @@ -13821,7 +13231,7 @@ ins_encode %{ __ orr(as_Register($dst$$reg), as_Register($src1$$reg), - (unsigned long)($src2$$constant)); + (uint64_t)($src2$$constant)); %} ins_pipe(ialu_reg_imm); @@ -13853,7 +13263,7 @@ ins_encode %{ __ eor(as_Register($dst$$reg), as_Register($src1$$reg), - (unsigned long)($src2$$constant)); + (uint64_t)($src2$$constant)); %} ins_pipe(ialu_reg_imm); @@ -14288,13 +13698,17 @@ instruct clearArray_reg_reg(iRegL_R11 cnt, iRegP_R10 base, Universe dummy, rFlagsReg cr) %{ match(Set dummy (ClearArray cnt base)); - effect(USE_KILL cnt, USE_KILL base); + effect(USE_KILL cnt, USE_KILL base, KILL cr); ins_cost(4 * INSN_COST); format %{ "ClearArray $cnt, $base" %} ins_encode %{ - __ zero_words($base$$Register, $cnt$$Register); + address tpc = __ zero_words($base$$Register, $cnt$$Register); + if (tpc == NULL) { + ciEnv::current()->record_failure("CodeCache is full"); + return; + } %} ins_pipe(pipe_class_memory); @@ -14302,8 +13716,8 @@ instruct clearArray_imm_reg(immL cnt, iRegP_R10 base, Universe dummy, rFlagsReg cr) %{ - predicate((u_int64_t)n->in(2)->get_long() - < (u_int64_t)(BlockZeroingLowLimit >> LogBytesPerWord)); + predicate((uint64_t)n->in(2)->get_long() + < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord)); match(Set dummy (ClearArray cnt base)); effect(USE_KILL base); @@ -14311,7 +13725,7 @@ format %{ "ClearArray $cnt, $base" %} ins_encode %{ - __ zero_words($base$$Register, (u_int64_t)$cnt$$constant); + __ zero_words($base$$Register, (uint64_t)$cnt$$constant); %} ins_pipe(pipe_class_memory); @@ -14854,7 +14268,7 @@ format %{ "fcmps $src1, 0.0" %} ins_encode %{ - __ fcmps(as_FloatRegister($src1$$reg), 0.0D); + __ fcmps(as_FloatRegister($src1$$reg), 0.0); %} ins_pipe(pipe_class_compare); @@ -14883,7 +14297,7 @@ format %{ "fcmpd $src1, 0.0" %} ins_encode %{ - __ fcmpd(as_FloatRegister($src1$$reg), 0.0D); + __ fcmpd(as_FloatRegister($src1$$reg), 0.0); %} ins_pipe(pipe_class_compare); @@ -14959,7 +14373,7 @@ Label done; FloatRegister s1 = as_FloatRegister($src1$$reg); Register d = as_Register($dst$$reg); - __ fcmps(s1, 0.0D); + __ fcmps(s1, 0.0); // installs 0 if EQ else -1 __ csinvw(d, zr, zr, Assembler::EQ); // keeps -1 if less or unordered else installs 1 @@ -14986,7 +14400,7 @@ Label done; FloatRegister s1 = as_FloatRegister($src1$$reg); Register d = as_Register($dst$$reg); - __ fcmpd(s1, 0.0D); + __ fcmpd(s1, 0.0); // installs 0 if EQ else -1 __ csinvw(d, zr, zr, Assembler::EQ); // keeps -1 if less or unordered else installs 1 @@ -15037,55 +14451,63 @@ // ============================================================================ // Max and Min -instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr) +instruct cmovI_reg_reg_lt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr) %{ - match(Set dst (MinI src1 src2)); + effect( DEF dst, USE src1, USE src2, USE cr ); - effect(DEF dst, USE src1, USE src2, KILL cr); - size(8); - - ins_cost(INSN_COST * 3); - format %{ - "cmpw $src1 $src2\t signed int\n\t" - "cselw $dst, $src1, $src2 lt\t" - %} + ins_cost(INSN_COST * 2); + format %{ "cselw $dst, $src1, $src2 lt\t" %} ins_encode %{ - __ cmpw(as_Register($src1$$reg), - as_Register($src2$$reg)); __ cselw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg), Assembler::LT); %} - ins_pipe(ialu_reg_reg); + ins_pipe(icond_reg_reg); +%} + +instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2) +%{ + match(Set dst (MinI src1 src2)); + ins_cost(INSN_COST * 3); + + expand %{ + rFlagsReg cr; + compI_reg_reg(cr, src1, src2); + cmovI_reg_reg_lt(dst, src1, src2, cr); + %} + %} // FROM HERE -instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr) +instruct cmovI_reg_reg_gt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr) %{ - match(Set dst (MaxI src1 src2)); + effect( DEF dst, USE src1, USE src2, USE cr ); - effect(DEF dst, USE src1, USE src2, KILL cr); - size(8); - - ins_cost(INSN_COST * 3); - format %{ - "cmpw $src1 $src2\t signed int\n\t" - "cselw $dst, $src1, $src2 gt\t" - %} + ins_cost(INSN_COST * 2); + format %{ "cselw $dst, $src1, $src2 gt\t" %} ins_encode %{ - __ cmpw(as_Register($src1$$reg), - as_Register($src2$$reg)); __ cselw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg), Assembler::GT); %} - ins_pipe(ialu_reg_reg); + ins_pipe(icond_reg_reg); +%} + +instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2) +%{ + match(Set dst (MaxI src1 src2)); + ins_cost(INSN_COST * 3); + expand %{ + rFlagsReg cr; + compI_reg_reg(cr, src1, src2); + cmovI_reg_reg_gt(dst, src1, src2, cr); + %} %} // ============================================================================ @@ -15723,9 +15145,9 @@ format %{ "ShouldNotReachHere" %} ins_encode %{ - // +1 so NativeInstruction::is_sigill_zombie_not_entrant() doesn't - // return true - __ dpcs1(0xdead + 1); + if (is_reachable()) { + __ dpcs1(0xdead + 1); + } %} ins_pipe(pipe_class_default); @@ -16030,10 +15452,14 @@ format %{ "Array Equals $ary1,ary2 -> $result // KILL $tmp" %} ins_encode %{ - __ arrays_equals($ary1$$Register, $ary2$$Register, - $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, - $result$$Register, $tmp$$Register, 1); - %} + address tpc = __ arrays_equals($ary1$$Register, $ary2$$Register, + $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, + $result$$Register, $tmp$$Register, 1); + if (tpc == NULL) { + ciEnv::current()->record_failure("CodeCache is full"); + return; + } + %} ins_pipe(pipe_class_memory); %} @@ -16047,9 +15473,13 @@ format %{ "Array Equals $ary1,ary2 -> $result // KILL $tmp" %} ins_encode %{ - __ arrays_equals($ary1$$Register, $ary2$$Register, - $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, - $result$$Register, $tmp$$Register, 2); + address tpc = __ arrays_equals($ary1$$Register, $ary2$$Register, + $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, + $result$$Register, $tmp$$Register, 2); + if (tpc == NULL) { + ciEnv::current()->record_failure("CodeCache is full"); + return; + } %} ins_pipe(pipe_class_memory); %} @@ -16060,7 +15490,11 @@ effect(USE_KILL ary1, USE_KILL len, KILL cr); format %{ "has negatives byte[] $ary1,$len -> $result" %} ins_encode %{ - __ has_negatives($ary1$$Register, $len$$Register, $result$$Register); + address tpc = __ has_negatives($ary1$$Register, $len$$Register, $result$$Register); + if (tpc == NULL) { + ciEnv::current()->record_failure("CodeCache is full"); + return; + } %} ins_pipe( pipe_slow ); %} @@ -16093,8 +15527,13 @@ format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %} ins_encode %{ - __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register, - $tmp1$$FloatRegister, $tmp2$$FloatRegister, $tmp3$$FloatRegister, $tmp4$$Register); + address tpc = __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register, + $tmp1$$FloatRegister, $tmp2$$FloatRegister, + $tmp3$$FloatRegister, $tmp4$$Register); + if (tpc == NULL) { + ciEnv::current()->record_failure("CodeCache is full"); + return; + } %} ins_pipe(pipe_class_memory); %} @@ -16427,14 +15866,14 @@ effect(TEMP tmp, TEMP tmp2); format %{ "umov $tmp, $src2, S, 0\n\t" "umov $tmp2, $src2, S, 1\n\t" - "addw $dst, $src1, $tmp\n\t" - "addw $dst, $dst, $tmp2\t add reduction2i" + "addw $tmp, $src1, $tmp\n\t" + "addw $dst, $tmp, $tmp2\t# add reduction2I" %} ins_encode %{ __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ S, 0); __ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ S, 1); - __ addw($dst$$Register, $src1$$Register, $tmp$$Register); - __ addw($dst$$Register, $dst$$Register, $tmp2$$Register); + __ addw($tmp$$Register, $src1$$Register, $tmp$$Register); + __ addw($dst$$Register, $tmp$$Register, $tmp2$$Register); %} ins_pipe(pipe_class_default); %} @@ -16446,7 +15885,7 @@ effect(TEMP tmp, TEMP tmp2); format %{ "addv $tmp, T4S, $src2\n\t" "umov $tmp2, $tmp, S, 0\n\t" - "addw $dst, $tmp2, $src1\t add reduction4i" + "addw $dst, $tmp2, $src1\t# add reduction4I" %} ins_encode %{ __ addv(as_FloatRegister($tmp$$reg), __ T4S, @@ -16465,7 +15904,7 @@ format %{ "umov $tmp, $src2, S, 0\n\t" "mul $dst, $tmp, $src1\n\t" "umov $tmp, $src2, S, 1\n\t" - "mul $dst, $tmp, $dst\t mul reduction2i\n\t" + "mul $dst, $tmp, $dst\t# mul reduction2I" %} ins_encode %{ __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ S, 0); @@ -16486,7 +15925,7 @@ "umov $tmp2, $tmp, S, 0\n\t" "mul $dst, $tmp2, $src1\n\t" "umov $tmp2, $tmp, S, 1\n\t" - "mul $dst, $tmp2, $dst\t mul reduction4i\n\t" + "mul $dst, $tmp2, $dst\t# mul reduction4I" %} ins_encode %{ __ ins(as_FloatRegister($tmp$$reg), __ D, @@ -16508,7 +15947,7 @@ effect(TEMP tmp, TEMP dst); format %{ "fadds $dst, $src1, $src2\n\t" "ins $tmp, S, $src2, 0, 1\n\t" - "fadds $dst, $dst, $tmp\t add reduction2f" + "fadds $dst, $dst, $tmp\t# add reduction2F" %} ins_encode %{ __ fadds(as_FloatRegister($dst$$reg), @@ -16532,7 +15971,7 @@ "ins $tmp, S, $src2, 0, 2\n\t" "fadds $dst, $dst, $tmp\n\t" "ins $tmp, S, $src2, 0, 3\n\t" - "fadds $dst, $dst, $tmp\t add reduction4f" + "fadds $dst, $dst, $tmp\t# add reduction4F" %} ins_encode %{ __ fadds(as_FloatRegister($dst$$reg), @@ -16560,7 +15999,7 @@ effect(TEMP tmp, TEMP dst); format %{ "fmuls $dst, $src1, $src2\n\t" "ins $tmp, S, $src2, 0, 1\n\t" - "fmuls $dst, $dst, $tmp\t add reduction4f" + "fmuls $dst, $dst, $tmp\t# mul reduction2F" %} ins_encode %{ __ fmuls(as_FloatRegister($dst$$reg), @@ -16584,7 +16023,7 @@ "ins $tmp, S, $src2, 0, 2\n\t" "fmuls $dst, $dst, $tmp\n\t" "ins $tmp, S, $src2, 0, 3\n\t" - "fmuls $dst, $dst, $tmp\t add reduction4f" + "fmuls $dst, $dst, $tmp\t# mul reduction4F" %} ins_encode %{ __ fmuls(as_FloatRegister($dst$$reg), @@ -16612,7 +16051,7 @@ effect(TEMP tmp, TEMP dst); format %{ "faddd $dst, $src1, $src2\n\t" "ins $tmp, D, $src2, 0, 1\n\t" - "faddd $dst, $dst, $tmp\t add reduction2d" + "faddd $dst, $dst, $tmp\t# add reduction2D" %} ins_encode %{ __ faddd(as_FloatRegister($dst$$reg), @@ -16632,7 +16071,7 @@ effect(TEMP tmp, TEMP dst); format %{ "fmuld $dst, $src1, $src2\n\t" "ins $tmp, D, $src2, 0, 1\n\t" - "fmuld $dst, $dst, $tmp\t add reduction2d" + "fmuld $dst, $dst, $tmp\t# mul reduction2D" %} ins_encode %{ __ fmuld(as_FloatRegister($dst$$reg), @@ -16645,6 +16084,98 @@ ins_pipe(pipe_class_default); %} +instruct reduce_max2F(vRegF dst, vRegF src1, vecD src2, vecD tmp) %{ + predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT); + match(Set dst (MaxReductionV src1 src2)); + ins_cost(INSN_COST); + effect(TEMP_DEF dst, TEMP tmp); + format %{ "fmaxs $dst, $src1, $src2\n\t" + "ins $tmp, S, $src2, 0, 1\n\t" + "fmaxs $dst, $dst, $tmp\t# max reduction2F" %} + ins_encode %{ + __ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg)); + __ ins(as_FloatRegister($tmp$$reg), __ S, as_FloatRegister($src2$$reg), 0, 1); + __ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg)); + %} + ins_pipe(pipe_class_default); +%} + +instruct reduce_max4F(vRegF dst, vRegF src1, vecX src2) %{ + predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT); + match(Set dst (MaxReductionV src1 src2)); + ins_cost(INSN_COST); + effect(TEMP_DEF dst); + format %{ "fmaxv $dst, T4S, $src2\n\t" + "fmaxs $dst, $dst, $src1\t# max reduction4F" %} + ins_encode %{ + __ fmaxv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src2$$reg)); + __ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg)); + %} + ins_pipe(pipe_class_default); +%} + +instruct reduce_max2D(vRegD dst, vRegD src1, vecX src2, vecX tmp) %{ + predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE); + match(Set dst (MaxReductionV src1 src2)); + ins_cost(INSN_COST); + effect(TEMP_DEF dst, TEMP tmp); + format %{ "fmaxd $dst, $src1, $src2\n\t" + "ins $tmp, D, $src2, 0, 1\n\t" + "fmaxd $dst, $dst, $tmp\t# max reduction2D" %} + ins_encode %{ + __ fmaxd(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg)); + __ ins(as_FloatRegister($tmp$$reg), __ D, as_FloatRegister($src2$$reg), 0, 1); + __ fmaxd(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg)); + %} + ins_pipe(pipe_class_default); +%} + +instruct reduce_min2F(vRegF dst, vRegF src1, vecD src2, vecD tmp) %{ + predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT); + match(Set dst (MinReductionV src1 src2)); + ins_cost(INSN_COST); + effect(TEMP_DEF dst, TEMP tmp); + format %{ "fmins $dst, $src1, $src2\n\t" + "ins $tmp, S, $src2, 0, 1\n\t" + "fmins $dst, $dst, $tmp\t# min reduction2F" %} + ins_encode %{ + __ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg)); + __ ins(as_FloatRegister($tmp$$reg), __ S, as_FloatRegister($src2$$reg), 0, 1); + __ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg)); + %} + ins_pipe(pipe_class_default); +%} + +instruct reduce_min4F(vRegF dst, vRegF src1, vecX src2) %{ + predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT); + match(Set dst (MinReductionV src1 src2)); + ins_cost(INSN_COST); + effect(TEMP_DEF dst); + format %{ "fminv $dst, T4S, $src2\n\t" + "fmins $dst, $dst, $src1\t# min reduction4F" %} + ins_encode %{ + __ fminv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src2$$reg)); + __ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg)); + %} + ins_pipe(pipe_class_default); +%} + +instruct reduce_min2D(vRegD dst, vRegD src1, vecX src2, vecX tmp) %{ + predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE); + match(Set dst (MinReductionV src1 src2)); + ins_cost(INSN_COST); + effect(TEMP_DEF dst, TEMP tmp); + format %{ "fmind $dst, $src1, $src2\n\t" + "ins $tmp, D, $src2, 0, 1\n\t" + "fmind $dst, $dst, $tmp\t# min reduction2D" %} + ins_encode %{ + __ fmind(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg)); + __ ins(as_FloatRegister($tmp$$reg), __ D, as_FloatRegister($src2$$reg), 0, 1); + __ fmind(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg)); + %} + ins_pipe(pipe_class_default); +%} + // ====================VECTOR ARITHMETIC======================================= // --------------------------------- ADD -------------------------------------- @@ -16936,6 +16467,35 @@ // --------------------------------- MUL -------------------------------------- +instruct vmul8B(vecD dst, vecD src1, vecD src2) +%{ + predicate(n->as_Vector()->length() == 4 || + n->as_Vector()->length() == 8); + match(Set dst (MulVB src1 src2)); + ins_cost(INSN_COST); + format %{ "mulv $dst,$src1,$src2\t# vector (8B)" %} + ins_encode %{ + __ mulv(as_FloatRegister($dst$$reg), __ T8B, + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg)); + %} + ins_pipe(vmul64); +%} + +instruct vmul16B(vecX dst, vecX src1, vecX src2) +%{ + predicate(n->as_Vector()->length() == 16); + match(Set dst (MulVB src1 src2)); + ins_cost(INSN_COST); + format %{ "mulv $dst,$src1,$src2\t# vector (16B)" %} + ins_encode %{ + __ mulv(as_FloatRegister($dst$$reg), __ T16B, + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg)); + %} + ins_pipe(vmul128); +%} + instruct vmul4S(vecD dst, vecD src1, vecD src2) %{ predicate(n->as_Vector()->length() == 2 || @@ -17286,6 +16846,28 @@ // --------------------------------- SQRT ------------------------------------- +instruct vsqrt2F(vecD dst, vecD src) +%{ + predicate(n->as_Vector()->length() == 2); + match(Set dst (SqrtVF src)); + format %{ "fsqrt $dst, $src\t# vector (2F)" %} + ins_encode %{ + __ fsqrt(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg)); + %} + ins_pipe(vunop_fp64); +%} + +instruct vsqrt4F(vecX dst, vecX src) +%{ + predicate(n->as_Vector()->length() == 4); + match(Set dst (SqrtVF src)); + format %{ "fsqrt $dst, $src\t# vector (4F)" %} + ins_encode %{ + __ fsqrt(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg)); + %} + ins_pipe(vsqrt_fp128); +%} + instruct vsqrt2D(vecX dst, vecX src) %{ predicate(n->as_Vector()->length() == 2); @@ -17300,6 +16882,91 @@ // --------------------------------- ABS -------------------------------------- +instruct vabs8B(vecD dst, vecD src) +%{ + predicate(n->as_Vector()->length() == 4 || + n->as_Vector()->length() == 8); + match(Set dst (AbsVB src)); + ins_cost(INSN_COST); + format %{ "abs $dst, $src\t# vector (8B)" %} + ins_encode %{ + __ absr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg)); + %} + ins_pipe(vlogical64); +%} + +instruct vabs16B(vecX dst, vecX src) +%{ + predicate(n->as_Vector()->length() == 16); + match(Set dst (AbsVB src)); + ins_cost(INSN_COST); + format %{ "abs $dst, $src\t# vector (16B)" %} + ins_encode %{ + __ absr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($src$$reg)); + %} + ins_pipe(vlogical128); +%} + +instruct vabs4S(vecD dst, vecD src) +%{ + predicate(n->as_Vector()->length() == 4); + match(Set dst (AbsVS src)); + ins_cost(INSN_COST); + format %{ "abs $dst, $src\t# vector (4H)" %} + ins_encode %{ + __ absr(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg)); + %} + ins_pipe(vlogical64); +%} + +instruct vabs8S(vecX dst, vecX src) +%{ + predicate(n->as_Vector()->length() == 8); + match(Set dst (AbsVS src)); + ins_cost(INSN_COST); + format %{ "abs $dst, $src\t# vector (8H)" %} + ins_encode %{ + __ absr(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg)); + %} + ins_pipe(vlogical128); +%} + +instruct vabs2I(vecD dst, vecD src) +%{ + predicate(n->as_Vector()->length() == 2); + match(Set dst (AbsVI src)); + ins_cost(INSN_COST); + format %{ "abs $dst, $src\t# vector (2S)" %} + ins_encode %{ + __ absr(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg)); + %} + ins_pipe(vlogical64); +%} + +instruct vabs4I(vecX dst, vecX src) +%{ + predicate(n->as_Vector()->length() == 4); + match(Set dst (AbsVI src)); + ins_cost(INSN_COST); + format %{ "abs $dst, $src\t# vector (4S)" %} + ins_encode %{ + __ absr(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg)); + %} + ins_pipe(vlogical128); +%} + +instruct vabs2L(vecX dst, vecX src) +%{ + predicate(n->as_Vector()->length() == 2); + match(Set dst (AbsVL src)); + ins_cost(INSN_COST); + format %{ "abs $dst, $src\t# vector (2D)" %} + ins_encode %{ + __ absr(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg)); + %} + ins_pipe(vlogical128); +%} + instruct vabs2F(vecD dst, vecD src) %{ predicate(n->as_Vector()->length() == 2); @@ -17474,32 +17141,32 @@ %} // ------------------------------ Shift --------------------------------------- - -instruct vshiftcntL(vecX dst, iRegIorL2I cnt) %{ +instruct vshiftcnt8B(vecD dst, iRegIorL2I cnt) %{ + predicate(n->as_Vector()->length_in_bytes() == 8); match(Set dst (LShiftCntV cnt)); - format %{ "dup $dst, $cnt\t# shift count (vecX)" %} - ins_encode %{ - __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg)); - %} - ins_pipe(vdup_reg_reg128); -%} - -// Right shifts on aarch64 SIMD are implemented as left shift by -ve amount -instruct vshiftcntR(vecX dst, iRegIorL2I cnt) %{ match(Set dst (RShiftCntV cnt)); - format %{ "dup $dst, $cnt\t# shift count (vecX)\n\tneg $dst, $dst\t T16B" %} + format %{ "dup $dst, $cnt\t# shift count vector (8B)" %} + ins_encode %{ + __ dup(as_FloatRegister($dst$$reg), __ T8B, as_Register($cnt$$reg)); + %} + ins_pipe(vdup_reg_reg64); +%} + +instruct vshiftcnt16B(vecX dst, iRegIorL2I cnt) %{ + predicate(n->as_Vector()->length_in_bytes() == 16); + match(Set dst (LShiftCntV cnt)); + match(Set dst (RShiftCntV cnt)); + format %{ "dup $dst, $cnt\t# shift count vector (16B)" %} ins_encode %{ __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg)); - __ negr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg)); %} ins_pipe(vdup_reg_reg128); %} -instruct vsll8B(vecD dst, vecD src, vecX shift) %{ +instruct vsll8B(vecD dst, vecD src, vecD shift) %{ predicate(n->as_Vector()->length() == 4 || n->as_Vector()->length() == 8); match(Set dst (LShiftVB src shift)); - match(Set dst (RShiftVB src shift)); ins_cost(INSN_COST); format %{ "sshl $dst,$src,$shift\t# vector (8B)" %} ins_encode %{ @@ -17513,7 +17180,6 @@ instruct vsll16B(vecX dst, vecX src, vecX shift) %{ predicate(n->as_Vector()->length() == 16); match(Set dst (LShiftVB src shift)); - match(Set dst (RShiftVB src shift)); ins_cost(INSN_COST); format %{ "sshl $dst,$src,$shift\t# vector (16B)" %} ins_encode %{ @@ -17524,29 +17190,93 @@ ins_pipe(vshift128); %} -instruct vsrl8B(vecD dst, vecD src, vecX shift) %{ +// Right shifts with vector shift count on aarch64 SIMD are implemented +// as left shift by negative shift count. +// There are two cases for vector shift count. +// +// Case 1: The vector shift count is from replication. +// | | +// LoadVector RShiftCntV +// | / +// RShiftVI +// Note: In inner loop, multiple neg instructions are used, which can be +// moved to outer loop and merge into one neg instruction. +// +// Case 2: The vector shift count is from loading. +// This case isn't supported by middle-end now. But it's supported by +// panama/vectorIntrinsics(JEP 338: Vector API). +// | | +// LoadVector LoadVector +// | / +// RShiftVI +// + +instruct vsra8B(vecD dst, vecD src, vecD shift, vecD tmp) %{ predicate(n->as_Vector()->length() == 4 || n->as_Vector()->length() == 8); - match(Set dst (URShiftVB src shift)); + match(Set dst (RShiftVB src shift)); ins_cost(INSN_COST); - format %{ "ushl $dst,$src,$shift\t# vector (8B)" %} + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "sshl $dst,$src,$tmp\t# vector (8B)" %} ins_encode %{ - __ ushl(as_FloatRegister($dst$$reg), __ T8B, - as_FloatRegister($src$$reg), + __ negr(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($shift$$reg)); + __ sshl(as_FloatRegister($dst$$reg), __ T8B, + as_FloatRegister($src$$reg), + as_FloatRegister($tmp$$reg)); %} ins_pipe(vshift64); %} -instruct vsrl16B(vecX dst, vecX src, vecX shift) %{ +instruct vsra16B(vecX dst, vecX src, vecX shift, vecX tmp) %{ + predicate(n->as_Vector()->length() == 16); + match(Set dst (RShiftVB src shift)); + ins_cost(INSN_COST); + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "sshl $dst,$src,$tmp\t# vector (16B)" %} + ins_encode %{ + __ negr(as_FloatRegister($tmp$$reg), __ T16B, + as_FloatRegister($shift$$reg)); + __ sshl(as_FloatRegister($dst$$reg), __ T16B, + as_FloatRegister($src$$reg), + as_FloatRegister($tmp$$reg)); + %} + ins_pipe(vshift128); +%} + +instruct vsrl8B(vecD dst, vecD src, vecD shift, vecD tmp) %{ + predicate(n->as_Vector()->length() == 4 || + n->as_Vector()->length() == 8); + match(Set dst (URShiftVB src shift)); + ins_cost(INSN_COST); + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "ushl $dst,$src,$tmp\t# vector (8B)" %} + ins_encode %{ + __ negr(as_FloatRegister($tmp$$reg), __ T8B, + as_FloatRegister($shift$$reg)); + __ ushl(as_FloatRegister($dst$$reg), __ T8B, + as_FloatRegister($src$$reg), + as_FloatRegister($tmp$$reg)); + %} + ins_pipe(vshift64); +%} + +instruct vsrl16B(vecX dst, vecX src, vecX shift, vecX tmp) %{ predicate(n->as_Vector()->length() == 16); match(Set dst (URShiftVB src shift)); ins_cost(INSN_COST); - format %{ "ushl $dst,$src,$shift\t# vector (16B)" %} + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "ushl $dst,$src,$tmp\t# vector (16B)" %} ins_encode %{ + __ negr(as_FloatRegister($tmp$$reg), __ T16B, + as_FloatRegister($shift$$reg)); __ ushl(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($src$$reg), - as_FloatRegister($shift$$reg)); + as_FloatRegister($tmp$$reg)); %} ins_pipe(vshift128); %} @@ -17658,11 +17388,10 @@ ins_pipe(vshift128_imm); %} -instruct vsll4S(vecD dst, vecD src, vecX shift) %{ +instruct vsll4S(vecD dst, vecD src, vecD shift) %{ predicate(n->as_Vector()->length() == 2 || n->as_Vector()->length() == 4); match(Set dst (LShiftVS src shift)); - match(Set dst (RShiftVS src shift)); ins_cost(INSN_COST); format %{ "sshl $dst,$src,$shift\t# vector (4H)" %} ins_encode %{ @@ -17676,7 +17405,6 @@ instruct vsll8S(vecX dst, vecX src, vecX shift) %{ predicate(n->as_Vector()->length() == 8); match(Set dst (LShiftVS src shift)); - match(Set dst (RShiftVS src shift)); ins_cost(INSN_COST); format %{ "sshl $dst,$src,$shift\t# vector (8H)" %} ins_encode %{ @@ -17687,29 +17415,72 @@ ins_pipe(vshift128); %} -instruct vsrl4S(vecD dst, vecD src, vecX shift) %{ +instruct vsra4S(vecD dst, vecD src, vecD shift, vecD tmp) %{ predicate(n->as_Vector()->length() == 2 || n->as_Vector()->length() == 4); - match(Set dst (URShiftVS src shift)); + match(Set dst (RShiftVS src shift)); ins_cost(INSN_COST); - format %{ "ushl $dst,$src,$shift\t# vector (4H)" %} + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "sshl $dst,$src,$tmp\t# vector (4H)" %} ins_encode %{ - __ ushl(as_FloatRegister($dst$$reg), __ T4H, - as_FloatRegister($src$$reg), + __ negr(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($shift$$reg)); + __ sshl(as_FloatRegister($dst$$reg), __ T4H, + as_FloatRegister($src$$reg), + as_FloatRegister($tmp$$reg)); %} ins_pipe(vshift64); %} -instruct vsrl8S(vecX dst, vecX src, vecX shift) %{ +instruct vsra8S(vecX dst, vecX src, vecX shift, vecX tmp) %{ + predicate(n->as_Vector()->length() == 8); + match(Set dst (RShiftVS src shift)); + ins_cost(INSN_COST); + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "sshl $dst,$src,$tmp\t# vector (8H)" %} + ins_encode %{ + __ negr(as_FloatRegister($tmp$$reg), __ T16B, + as_FloatRegister($shift$$reg)); + __ sshl(as_FloatRegister($dst$$reg), __ T8H, + as_FloatRegister($src$$reg), + as_FloatRegister($tmp$$reg)); + %} + ins_pipe(vshift128); +%} + +instruct vsrl4S(vecD dst, vecD src, vecD shift, vecD tmp) %{ + predicate(n->as_Vector()->length() == 2 || + n->as_Vector()->length() == 4); + match(Set dst (URShiftVS src shift)); + ins_cost(INSN_COST); + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "ushl $dst,$src,$tmp\t# vector (4H)" %} + ins_encode %{ + __ negr(as_FloatRegister($tmp$$reg), __ T8B, + as_FloatRegister($shift$$reg)); + __ ushl(as_FloatRegister($dst$$reg), __ T4H, + as_FloatRegister($src$$reg), + as_FloatRegister($tmp$$reg)); + %} + ins_pipe(vshift64); +%} + +instruct vsrl8S(vecX dst, vecX src, vecX shift, vecX tmp) %{ predicate(n->as_Vector()->length() == 8); match(Set dst (URShiftVS src shift)); ins_cost(INSN_COST); - format %{ "ushl $dst,$src,$shift\t# vector (8H)" %} + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "ushl $dst,$src,$tmp\t# vector (8H)" %} ins_encode %{ + __ negr(as_FloatRegister($tmp$$reg), __ T16B, + as_FloatRegister($shift$$reg)); __ ushl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), - as_FloatRegister($shift$$reg)); + as_FloatRegister($tmp$$reg)); %} ins_pipe(vshift128); %} @@ -17821,10 +17592,9 @@ ins_pipe(vshift128_imm); %} -instruct vsll2I(vecD dst, vecD src, vecX shift) %{ +instruct vsll2I(vecD dst, vecD src, vecD shift) %{ predicate(n->as_Vector()->length() == 2); match(Set dst (LShiftVI src shift)); - match(Set dst (RShiftVI src shift)); ins_cost(INSN_COST); format %{ "sshl $dst,$src,$shift\t# vector (2S)" %} ins_encode %{ @@ -17838,7 +17608,6 @@ instruct vsll4I(vecX dst, vecX src, vecX shift) %{ predicate(n->as_Vector()->length() == 4); match(Set dst (LShiftVI src shift)); - match(Set dst (RShiftVI src shift)); ins_cost(INSN_COST); format %{ "sshl $dst,$src,$shift\t# vector (4S)" %} ins_encode %{ @@ -17849,28 +17618,70 @@ ins_pipe(vshift128); %} -instruct vsrl2I(vecD dst, vecD src, vecX shift) %{ +instruct vsra2I(vecD dst, vecD src, vecD shift, vecD tmp) %{ predicate(n->as_Vector()->length() == 2); - match(Set dst (URShiftVI src shift)); + match(Set dst (RShiftVI src shift)); ins_cost(INSN_COST); - format %{ "ushl $dst,$src,$shift\t# vector (2S)" %} + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "sshl $dst,$src,$tmp\t# vector (2S)" %} ins_encode %{ - __ ushl(as_FloatRegister($dst$$reg), __ T2S, - as_FloatRegister($src$$reg), + __ negr(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($shift$$reg)); + __ sshl(as_FloatRegister($dst$$reg), __ T2S, + as_FloatRegister($src$$reg), + as_FloatRegister($tmp$$reg)); %} ins_pipe(vshift64); %} -instruct vsrl4I(vecX dst, vecX src, vecX shift) %{ +instruct vsra4I(vecX dst, vecX src, vecX shift, vecX tmp) %{ + predicate(n->as_Vector()->length() == 4); + match(Set dst (RShiftVI src shift)); + ins_cost(INSN_COST); + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "sshl $dst,$src,$tmp\t# vector (4S)" %} + ins_encode %{ + __ negr(as_FloatRegister($tmp$$reg), __ T16B, + as_FloatRegister($shift$$reg)); + __ sshl(as_FloatRegister($dst$$reg), __ T4S, + as_FloatRegister($src$$reg), + as_FloatRegister($tmp$$reg)); + %} + ins_pipe(vshift128); +%} + +instruct vsrl2I(vecD dst, vecD src, vecD shift, vecD tmp) %{ + predicate(n->as_Vector()->length() == 2); + match(Set dst (URShiftVI src shift)); + ins_cost(INSN_COST); + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "ushl $dst,$src,$tmp\t# vector (2S)" %} + ins_encode %{ + __ negr(as_FloatRegister($tmp$$reg), __ T8B, + as_FloatRegister($shift$$reg)); + __ ushl(as_FloatRegister($dst$$reg), __ T2S, + as_FloatRegister($src$$reg), + as_FloatRegister($tmp$$reg)); + %} + ins_pipe(vshift64); +%} + +instruct vsrl4I(vecX dst, vecX src, vecX shift, vecX tmp) %{ predicate(n->as_Vector()->length() == 4); match(Set dst (URShiftVI src shift)); ins_cost(INSN_COST); - format %{ "ushl $dst,$src,$shift\t# vector (4S)" %} + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "ushl $dst,$src,$tmp\t# vector (4S)" %} ins_encode %{ + __ negr(as_FloatRegister($tmp$$reg), __ T16B, + as_FloatRegister($shift$$reg)); __ ushl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg), - as_FloatRegister($shift$$reg)); + as_FloatRegister($tmp$$reg)); %} ins_pipe(vshift128); %} @@ -17956,7 +17767,6 @@ instruct vsll2L(vecX dst, vecX src, vecX shift) %{ predicate(n->as_Vector()->length() == 2); match(Set dst (LShiftVL src shift)); - match(Set dst (RShiftVL src shift)); ins_cost(INSN_COST); format %{ "sshl $dst,$src,$shift\t# vector (2D)" %} ins_encode %{ @@ -17967,15 +17777,36 @@ ins_pipe(vshift128); %} -instruct vsrl2L(vecX dst, vecX src, vecX shift) %{ +instruct vsra2L(vecX dst, vecX src, vecX shift, vecX tmp) %{ + predicate(n->as_Vector()->length() == 2); + match(Set dst (RShiftVL src shift)); + ins_cost(INSN_COST); + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "sshl $dst,$src,$tmp\t# vector (2D)" %} + ins_encode %{ + __ negr(as_FloatRegister($tmp$$reg), __ T16B, + as_FloatRegister($shift$$reg)); + __ sshl(as_FloatRegister($dst$$reg), __ T2D, + as_FloatRegister($src$$reg), + as_FloatRegister($tmp$$reg)); + %} + ins_pipe(vshift128); +%} + +instruct vsrl2L(vecX dst, vecX src, vecX shift, vecX tmp) %{ predicate(n->as_Vector()->length() == 2); match(Set dst (URShiftVL src shift)); ins_cost(INSN_COST); - format %{ "ushl $dst,$src,$shift\t# vector (2D)" %} + effect(TEMP tmp); + format %{ "negr $tmp,$shift\t" + "ushl $dst,$src,$tmp\t# vector (2D)" %} ins_encode %{ + __ negr(as_FloatRegister($tmp$$reg), __ T16B, + as_FloatRegister($shift$$reg)); __ ushl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), - as_FloatRegister($shift$$reg)); + as_FloatRegister($tmp$$reg)); %} ins_pipe(vshift128); %} @@ -18019,6 +17850,128 @@ ins_pipe(vshift128_imm); %} +instruct vmax2F(vecD dst, vecD src1, vecD src2) +%{ + predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT); + match(Set dst (MaxV src1 src2)); + ins_cost(INSN_COST); + format %{ "fmax $dst,$src1,$src2\t# vector (2F)" %} + ins_encode %{ + __ fmax(as_FloatRegister($dst$$reg), __ T2S, + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg)); + %} + ins_pipe(vdop_fp64); +%} + +instruct vmax4F(vecX dst, vecX src1, vecX src2) +%{ + predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT); + match(Set dst (MaxV src1 src2)); + ins_cost(INSN_COST); + format %{ "fmax $dst,$src1,$src2\t# vector (4S)" %} + ins_encode %{ + __ fmax(as_FloatRegister($dst$$reg), __ T4S, + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg)); + %} + ins_pipe(vdop_fp128); +%} + +instruct vmax2D(vecX dst, vecX src1, vecX src2) +%{ + predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE); + match(Set dst (MaxV src1 src2)); + ins_cost(INSN_COST); + format %{ "fmax $dst,$src1,$src2\t# vector (2D)" %} + ins_encode %{ + __ fmax(as_FloatRegister($dst$$reg), __ T2D, + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg)); + %} + ins_pipe(vdop_fp128); +%} + +instruct vmin2F(vecD dst, vecD src1, vecD src2) +%{ + predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT); + match(Set dst (MinV src1 src2)); + ins_cost(INSN_COST); + format %{ "fmin $dst,$src1,$src2\t# vector (2F)" %} + ins_encode %{ + __ fmin(as_FloatRegister($dst$$reg), __ T2S, + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg)); + %} + ins_pipe(vdop_fp64); +%} + +instruct vmin4F(vecX dst, vecX src1, vecX src2) +%{ + predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT); + match(Set dst (MinV src1 src2)); + ins_cost(INSN_COST); + format %{ "fmin $dst,$src1,$src2\t# vector (4S)" %} + ins_encode %{ + __ fmin(as_FloatRegister($dst$$reg), __ T4S, + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg)); + %} + ins_pipe(vdop_fp128); +%} + +instruct vmin2D(vecX dst, vecX src1, vecX src2) +%{ + predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE); + match(Set dst (MinV src1 src2)); + ins_cost(INSN_COST); + format %{ "fmin $dst,$src1,$src2\t# vector (2D)" %} + ins_encode %{ + __ fmin(as_FloatRegister($dst$$reg), __ T2D, + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg)); + %} + ins_pipe(vdop_fp128); +%} + +instruct vpopcount4I(vecX dst, vecX src) %{ + predicate(UsePopCountInstruction && n->as_Vector()->length() == 4); + match(Set dst (PopCountVI src)); + format %{ + "cnt $dst, $src\t# vector (16B)\n\t" + "uaddlp $dst, $dst\t# vector (16B)\n\t" + "uaddlp $dst, $dst\t# vector (8H)" + %} + ins_encode %{ + __ cnt(as_FloatRegister($dst$$reg), __ T16B, + as_FloatRegister($src$$reg)); + __ uaddlp(as_FloatRegister($dst$$reg), __ T16B, + as_FloatRegister($dst$$reg)); + __ uaddlp(as_FloatRegister($dst$$reg), __ T8H, + as_FloatRegister($dst$$reg)); + %} + ins_pipe(pipe_class_default); +%} + +instruct vpopcount2I(vecD dst, vecD src) %{ + predicate(UsePopCountInstruction && n->as_Vector()->length() == 2); + match(Set dst (PopCountVI src)); + format %{ + "cnt $dst, $src\t# vector (8B)\n\t" + "uaddlp $dst, $dst\t# vector (8B)\n\t" + "uaddlp $dst, $dst\t# vector (4H)" + %} + ins_encode %{ + __ cnt(as_FloatRegister($dst$$reg), __ T8B, + as_FloatRegister($src$$reg)); + __ uaddlp(as_FloatRegister($dst$$reg), __ T8B, + as_FloatRegister($dst$$reg)); + __ uaddlp(as_FloatRegister($dst$$reg), __ T4H, + as_FloatRegister($dst$$reg)); + %} + ins_pipe(pipe_class_default); +%} + //----------PEEPHOLE RULES----------------------------------------------------- // These must follow all instruction definitions as they use the names // defined in the instructions definitions.
diff --git a/src/hotspot/cpu/aarch64/aarch64Test.cpp b/src/hotspot/cpu/aarch64/aarch64Test.cpp index 5d2f041..65dd987 100644 --- a/src/hotspot/cpu/aarch64/aarch64Test.cpp +++ b/src/hotspot/cpu/aarch64/aarch64Test.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, Red Hat Inc. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -32,10 +32,12 @@ extern "C" void entry(CodeBuffer*); +#ifdef ASSERT void aarch64TestHook() { BufferBlob* b = BufferBlob::create("aarch64Test", 500000); CodeBuffer code(b); - MacroAssembler _masm(&code); entry(&code); + BufferBlob::free(b); } +#endif
diff --git a/src/hotspot/cpu/aarch64/aarch64_ad.m4 b/src/hotspot/cpu/aarch64/aarch64_ad.m4 index 0dd69df..4ac6f2c 100644 --- a/src/hotspot/cpu/aarch64/aarch64_ad.m4 +++ b/src/hotspot/cpu/aarch64/aarch64_ad.m4
@@ -1,4 +1,4 @@ -dnl Copyright (c) 2014, Red Hat Inc. All rights reserved. +dnl Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. dnl DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. dnl dnl This code is free software; you can redistribute it and/or modify it @@ -23,12 +23,12 @@ dnl Process this file with m4 aarch64_ad.m4 to generate the arithmetic dnl and shift patterns patterns used in aarch64.ad. dnl -// BEGIN This section of the file is automatically generated. Do not edit -------------- dnl define(`ORL2I', `ifelse($1,I,orL2I)') dnl define(`BASE_SHIFT_INSN', -` +`// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct $2$1_reg_$4_reg(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI src3, rFlagsReg cr) %{ @@ -46,9 +46,11 @@ %} ins_pipe(ialu_reg_reg_shift); -%}')dnl +%} +')dnl define(`BASE_INVERTED_INSN', -` +`// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct $2$1_reg_not_reg(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_M1 m1, rFlagsReg cr) %{ @@ -68,9 +70,11 @@ %} ins_pipe(ialu_reg_reg); -%}')dnl +%} +')dnl define(`INVERTED_SHIFT_INSN', -` +`// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct $2$1_reg_$4_not_reg(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI src3, imm$1_M1 src4, rFlagsReg cr) %{ @@ -91,9 +95,12 @@ %} ins_pipe(ialu_reg_reg_shift); -%}')dnl +%} +')dnl define(`NOT_INSN', -`instruct reg$1_not_reg(iReg$1NoSp dst, +`// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE +instruct reg$1_not_reg(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, imm$1_M1 m1, rFlagsReg cr) %{ match(Set dst (Xor$1 src1 m1)); @@ -108,7 +115,8 @@ %} ins_pipe(ialu_reg); -%}')dnl +%} +')dnl dnl define(`BOTH_SHIFT_INSNS', `BASE_SHIFT_INSN(I, $1, ifelse($2,andr,andw,$2w), $3, $4) @@ -120,7 +128,7 @@ dnl define(`BOTH_INVERTED_SHIFT_INSNS', `INVERTED_SHIFT_INSN(I, $1, $2w, $3, $4, ~0, int) -INVERTED_SHIFT_INSN(L, $1, $2, $3, $4, ~0l, long)')dnl +INVERTED_SHIFT_INSN(L, $1, $2, $3, $4, ~0l, jlong)')dnl dnl define(`ALL_SHIFT_KINDS', `BOTH_SHIFT_INSNS($1, $2, URShift, LSR) @@ -147,21 +155,20 @@ ALL_SHIFT_KINDS(Sub, sub) dnl dnl EXTEND mode, rshift_op, src, lshift_count, rshift_count -define(`EXTEND', `($2$1 (LShift$1 $3 $4) $5)') -define(`BFM_INSN',` +define(`EXTEND', `($2$1 (LShift$1 $3 $4) $5)') dnl +define(`BFM_INSN',`// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE + // Shift Left followed by Shift Right. // This idiom is used by the compiler for the i2b bytecode etc. instruct $4$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift_count, immI rshift_count) %{ match(Set dst EXTEND($1, $3, src, lshift_count, rshift_count)); - // Make sure we are not going to exceed what $4 can do. - predicate((unsigned int)n->in(2)->get_int() <= $2 - && (unsigned int)n->in(1)->in(2)->get_int() <= $2); - ins_cost(INSN_COST * 2); format %{ "$4 $dst, $src, $rshift_count - $lshift_count, #$2 - $lshift_count" %} ins_encode %{ - int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant; + int lshift = $lshift_count$$constant & $2; + int rshift = $rshift_count$$constant & $2; int s = $2 - lshift; int r = (rshift - lshift) & $2; __ $4(as_Register($dst$$reg), @@ -170,7 +177,8 @@ %} ins_pipe(ialu_reg_shift); -%}') +%} +') BFM_INSN(L, 63, RShift, sbfm) BFM_INSN(I, 31, RShift, sbfmw) BFM_INSN(L, 63, URShift, ubfm) @@ -178,35 +186,45 @@ dnl // Bitfield extract with shift & mask define(`BFX_INSN', -`instruct $3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI rshift, imm$1_bitmask mask) +`// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE +instruct $3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI rshift, imm$1_bitmask mask) %{ match(Set dst (And$1 ($2$1 src rshift) mask)); + // Make sure we are not going to exceed what $3 can do. + predicate((exact_log2$6(n->in(2)->get_$5() + 1) + (n->in(1)->in(2)->get_int() & $4)) <= ($4 + 1)); ins_cost(INSN_COST); format %{ "$3 $dst, $src, $rshift, $mask" %} ins_encode %{ - int rshift = $rshift$$constant; - long mask = $mask$$constant; - int width = exact_log2(mask+1); + int rshift = $rshift$$constant & $4; + intptr_t mask = $mask$$constant; + int width = exact_log2$6(mask+1); __ $3(as_Register($dst$$reg), as_Register($src$$reg), rshift, width); %} ins_pipe(ialu_reg_shift); -%}') -BFX_INSN(I,URShift,ubfxw) -BFX_INSN(L,URShift,ubfx) +%} +') +BFX_INSN(I, URShift, ubfxw, 31, int) +BFX_INSN(L, URShift, ubfx, 63, long, _long) + +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE // We can use ubfx when extending an And with a mask when we know mask // is positive. We know that because immI_bitmask guarantees it. instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask) %{ match(Set dst (ConvI2L (AndI (URShiftI src rshift) mask))); + // Make sure we are not going to exceed what ubfxw can do. + predicate((exact_log2(n->in(1)->in(2)->get_int() + 1) + (n->in(1)->in(1)->in(2)->get_int() & 31)) <= (31 + 1)); ins_cost(INSN_COST * 2); format %{ "ubfx $dst, $src, $rshift, $mask" %} ins_encode %{ - int rshift = $rshift$$constant; - long mask = $mask$$constant; + int rshift = $rshift$$constant & 31; + intptr_t mask = $mask$$constant; int width = exact_log2(mask+1); __ ubfx(as_Register($dst$$reg), as_Register($src$$reg), rshift, width); @@ -214,55 +232,81 @@ ins_pipe(ialu_reg_shift); %} -define(`UBFIZ_INSN', +define(`UBFIZ_INSN', `// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE + // We can use ubfiz when masking by a positive number and then left shifting the result. // We know that the mask is positive because imm$1_bitmask guarantees it. -`instruct $2$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift, imm$1_bitmask mask) +instruct $3$1$8(iReg$2NoSp dst, iReg$1`'ORL2I($1) src, immI lshift, $7 mask) %{ - match(Set dst (LShift$1 (And$1 src mask) lshift)); - predicate((unsigned int)n->in(2)->get_int() <= $3 && - (exact_log2$5(n->in(1)->in(2)->get_$4()+1) + (unsigned int)n->in(2)->get_int()) <= ($3+1)); + ifelse($8,, + match(Set dst (LShift$1 (And$1 src mask) lshift));, + match(Set dst ($8 (LShift$1 (And$1 src mask) lshift)));) + ifelse($8,, + predicate(($6(n->in(1)->in(2)->get_$5() + 1) + (n->in(2)->get_int() & $4)) <= ($4 + 1));, + predicate(($6(n->in(1)->in(1)->in(2)->get_$5() + 1) + (n->in(1)->in(2)->get_int() & $4)) <= 31);) ins_cost(INSN_COST); - format %{ "$2 $dst, $src, $lshift, $mask" %} + format %{ "$3 $dst, $src, $lshift, $mask" %} ins_encode %{ - int lshift = $lshift$$constant; - long mask = $mask$$constant; - int width = exact_log2(mask+1); - __ $2(as_Register($dst$$reg), + int lshift = $lshift$$constant & $4; + intptr_t mask = $mask$$constant; + int width = $6(mask+1); + __ $3(as_Register($dst$$reg), as_Register($src$$reg), lshift, width); %} ins_pipe(ialu_reg_shift); -%}') -UBFIZ_INSN(I, ubfizw, 31, int) -UBFIZ_INSN(L, ubfiz, 63, long, _long) +%} +') +UBFIZ_INSN(I, I, ubfizw, 31, int, exact_log2, immI_bitmask) +UBFIZ_INSN(L, L, ubfiz, 63, long, exact_log2_long, immL_bitmask) +UBFIZ_INSN(I, L, ubfizw, 31, int, exact_log2, immI_bitmask, ConvI2L) +UBFIZ_INSN(L, I, ubfiz, 63, long, exact_log2_long, immL_positive_bitmaskI, ConvL2I) -// If there is a convert I to L block between and AndI and a LShiftL, we can also match ubfiz -instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask) +define(`BFX1_INSN', `// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE + +// If there is a convert $1 to $2 block between and And$1 and a LShift$2, we can also match ubfiz +instruct ubfiz$1Conv$3$9(iReg$2NoSp dst, iReg$1`'ORL2I($1) src, immI lshift, $8 mask) %{ - match(Set dst (LShiftL (ConvI2L(AndI src mask)) lshift)); - predicate((unsigned int)n->in(2)->get_int() <= 31 && - (exact_log2((unsigned int)n->in(1)->in(1)->in(2)->get_int()+1) + (unsigned int)n->in(2)->get_int()) <= 32); + match(Set dst (LShift$2 (Conv$3 (And$1 src mask)) lshift)); + predicate(($4(n->in(1)->in(1)->in(2)->$5() + 1) + (n->in(2)->get_int() & $6)) <= $7); ins_cost(INSN_COST); format %{ "ubfiz $dst, $src, $lshift, $mask" %} ins_encode %{ - int lshift = $lshift$$constant; - long mask = $mask$$constant; + int lshift = $lshift$$constant & $6; + intptr_t mask = $mask$$constant; int width = exact_log2(mask+1); __ ubfiz(as_Register($dst$$reg), as_Register($src$$reg), lshift, width); %} ins_pipe(ialu_reg_shift); %} +')dnl +BFX1_INSN(I, L, I2L, exact_log2, get_int, 63, (63 + 1), immI_bitmask) +BFX1_INSN(L, I, L2I, exact_log2_long, get_long, 31, 31, immL_positive_bitmaskI, x) +// Can skip int2long conversions after AND with small bitmask +instruct ubfizIConvI2LAndI(iRegLNoSp dst, iRegI src, immI_bitmask msk) +%{ + match(Set dst (ConvI2L (AndI src msk))); + ins_cost(INSN_COST); + format %{ "ubfiz $dst, $src, 0, exact_log2($msk + 1) " %} + ins_encode %{ + __ ubfiz(as_Register($dst$$reg), as_Register($src$$reg), 0, exact_log2($msk$$constant + 1)); + %} + ins_pipe(ialu_reg_shift); +%} -// Rotations -define(`EXTRACT_INSN', -`instruct extr$3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI lshift, immI rshift, rFlagsReg cr) +// Rotations dnl +define(`EXTRACT_INSN',` +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE +instruct extr$3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI lshift, immI rshift, rFlagsReg cr) %{ match(Set dst ($3$1 (LShift$1 src1 lshift) (URShift$1 src2 rshift))); - predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & $2)); + predicate(0 == (((n->in(1)->in(2)->get_int() & $2) + (n->in(2)->in(2)->get_int() & $2)) & $2)); ins_cost(INSN_COST); format %{ "extr $dst, $src1, $src2, #$rshift" %} @@ -278,9 +322,10 @@ EXTRACT_INSN(I, 31, Or, extrw) EXTRACT_INSN(L, 63, Add, extr) EXTRACT_INSN(I, 31, Add, extrw) -define(`ROL_EXPAND', ` -// $2 expander +define(`ROL_EXPAND', `// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE +// $2 expander instruct $2$1_rReg(iReg$1NoSp dst, iReg$1 src, iRegI shift, rFlagsReg cr) %{ effect(DEF dst, USE src, USE shift); @@ -293,10 +338,12 @@ rscratch1); %} ins_pipe(ialu_reg_reg_vshift); -%}')dnl -define(`ROR_EXPAND', ` -// $2 expander +%} +') +define(`ROR_EXPAND', `// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE +// $2 expander instruct $2$1_rReg(iReg$1NoSp dst, iReg$1 src, iRegI shift, rFlagsReg cr) %{ effect(DEF dst, USE src, USE shift); @@ -308,8 +355,10 @@ as_Register($shift$$reg)); %} ins_pipe(ialu_reg_reg_vshift); -%}')dnl -define(ROL_INSN, ` +%} +')dnl +define(ROL_INSN, `// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2, rFlagsReg cr) %{ match(Set dst (Or$1 (LShift$1 src shift) (URShift$1 src (SubI c$2 shift)))); @@ -317,8 +366,10 @@ expand %{ $3$1_rReg(dst, src, shift, cr); %} -%}')dnl -define(ROR_INSN, ` +%} +')dnl +define(ROR_INSN, `// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2, rFlagsReg cr) %{ match(Set dst (Or$1 (URShift$1 src shift) (LShift$1 src (SubI c$2 shift)))); @@ -326,7 +377,8 @@ expand %{ $3$1_rReg(dst, src, shift, cr); %} -%}')dnl +%} +')dnl ROL_EXPAND(L, rol, rorv) ROL_EXPAND(I, rol, rorvw) ROL_INSN(L, _64, rol) @@ -343,6 +395,8 @@ // Add/subtract (extended) dnl ADD_SUB_EXTENDED(mode, size, add node, shift node, insn, shift type, wordsize define(`ADD_SUB_CONV', ` +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct $3Ext$1(iReg$2NoSp dst, iReg$2`'ORL2I($2) src1, iReg$1`'ORL2I($1) src2, rFlagsReg cr) %{ match(Set dst ($3$2 src1 (ConvI2L src2))); @@ -355,10 +409,12 @@ %} ins_pipe(ialu_reg_reg); %}')dnl -ADD_SUB_CONV(I,L,Add,add,sxtw); -ADD_SUB_CONV(I,L,Sub,sub,sxtw); +ADD_SUB_CONV(I,L,Add,add,sxtw) +ADD_SUB_CONV(I,L,Sub,sub,sxtw) dnl define(`ADD_SUB_EXTENDED', ` +// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct $3Ext$1_$6(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI_`'eval($7-$2) lshift, immI_`'eval($7-$2) rshift, rFlagsReg cr) %{ match(Set dst ($3$1 src1 EXTEND($1, $4, src2, lshift, rshift))); @@ -370,7 +426,7 @@ as_Register($src2$$reg), ext::$6); %} ins_pipe(ialu_reg_reg); -%}') +%}')dnl ADD_SUB_EXTENDED(I,16,Add,RShift,add,sxth,32) ADD_SUB_EXTENDED(I,8,Add,RShift,add,sxtb,32) ADD_SUB_EXTENDED(I,8,Add,URShift,add,uxtb,32) @@ -380,7 +436,8 @@ ADD_SUB_EXTENDED(L,8,Add,URShift,add,uxtb,64) dnl dnl ADD_SUB_ZERO_EXTEND(mode, size, add node, insn, shift type) -define(`ADD_SUB_ZERO_EXTEND', ` +define(`ADD_SUB_ZERO_EXTEND', `// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct $3Ext$1_$5_and(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_$2 mask, rFlagsReg cr) %{ match(Set dst ($3$1 src1 (And$1 src2 mask))); @@ -392,7 +449,8 @@ as_Register($src2$$reg), ext::$5); %} ins_pipe(ialu_reg_reg); -%}') +%} +') dnl ADD_SUB_ZERO_EXTEND(I,255,Add,addw,uxtb) ADD_SUB_ZERO_EXTEND(I,65535,Add,addw,uxth) @@ -407,7 +465,8 @@ ADD_SUB_ZERO_EXTEND(L,4294967295,Sub,sub,uxtw) dnl dnl ADD_SUB_ZERO_EXTEND_SHIFT(mode, size, add node, insn, ext type) -define(`ADD_SUB_EXTENDED_SHIFT', ` +define(`ADD_SUB_EXTENDED_SHIFT', `// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct $3Ext$1_$6_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immIExt lshift2, immI_`'eval($7-$2) lshift1, immI_`'eval($7-$2) rshift1, rFlagsReg cr) %{ match(Set dst ($3$1 src1 (LShift$1 EXTEND($1, $4, src2, lshift1, rshift1) lshift2))); @@ -419,7 +478,8 @@ as_Register($src2$$reg), ext::$6, ($lshift2$$constant)); %} ins_pipe(ialu_reg_reg_shift); -%}') +%} +') dnl $1 $2 $3 $4 $5 $6 $7 ADD_SUB_EXTENDED_SHIFT(L,8,Add,RShift,add,sxtb,64) ADD_SUB_EXTENDED_SHIFT(L,16,Add,RShift,add,sxth,64) @@ -436,7 +496,8 @@ ADD_SUB_EXTENDED_SHIFT(I,16,Sub,RShift,subw,sxth,32) dnl dnl ADD_SUB_CONV_SHIFT(mode, add node, insn, ext type) -define(`ADD_SUB_CONV_SHIFT', ` +define(`ADD_SUB_CONV_SHIFT', `// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct $2ExtI_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr) %{ match(Set dst ($2$1 src1 (LShiftL (ConvI2L src2) lshift))); @@ -448,13 +509,14 @@ as_Register($src2$$reg), ext::$4, ($lshift$$constant)); %} ins_pipe(ialu_reg_reg_shift); -%}') -dnl -ADD_SUB_CONV_SHIFT(L,Add,add,sxtw); -ADD_SUB_CONV_SHIFT(L,Sub,sub,sxtw); +%} +')dnl +ADD_SUB_CONV_SHIFT(L,Add,add,sxtw) +ADD_SUB_CONV_SHIFT(L,Sub,sub,sxtw) dnl dnl ADD_SUB_ZERO_EXTEND(mode, size, add node, insn, ext type) -define(`ADD_SUB_ZERO_EXTEND_SHIFT', ` +define(`ADD_SUB_ZERO_EXTEND_SHIFT', `// This pattern is automatically generated from aarch64_ad.m4 +// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE instruct $3Ext$1_$5_and_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_$2 mask, immIExt lshift, rFlagsReg cr) %{ match(Set dst ($3$1 src1 (LShift$1 (And$1 src2 mask) lshift))); @@ -466,8 +528,8 @@ as_Register($src2$$reg), ext::$5, ($lshift$$constant)); %} ins_pipe(ialu_reg_reg_shift); -%}') -dnl +%} +')dnl dnl $1 $2 $3 $4 $5 ADD_SUB_ZERO_EXTEND_SHIFT(L,255,Add,add,uxtb) ADD_SUB_ZERO_EXTEND_SHIFT(L,65535,Add,add,uxth) @@ -483,4 +545,4 @@ ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Sub,subw,uxtb) ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Sub,subw,uxth) dnl -// END This section of the file is automatically generated. Do not edit -------------- +
diff --git a/src/hotspot/cpu/aarch64/aarch64_call.cpp b/src/hotspot/cpu/aarch64/aarch64_call.cpp deleted file mode 100644 index 844dd9e..0000000 --- a/src/hotspot/cpu/aarch64/aarch64_call.cpp +++ /dev/null
@@ -1,200 +0,0 @@ -/* - * Copyright (c) 2014, Red Hat Inc. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#ifdef BUILTIN_SIM - -#include <stdio.h> -#include <sys/types.h> -#include "asm/macroAssembler.hpp" -#include "asm/macroAssembler.inline.hpp" -#include "runtime/sharedRuntime.hpp" -#include "../../../../../../simulator/cpustate.hpp" -#include "../../../../../../simulator/simulator.hpp" - -/* - * a routine to initialise and enter ARM simulator execution when - * calling into ARM code from x86 code. - * - * we maintain a simulator per-thread and provide it with 8 Mb of - * stack space - */ -#define SIM_STACK_SIZE (1024 * 1024) // in units of u_int64_t - -extern "C" u_int64_t get_alt_stack() -{ - return AArch64Simulator::altStack(); -} - -extern "C" void setup_arm_sim(void *sp, u_int64_t calltype) -{ - // n.b. this function runs on the simulator stack so as to avoid - // simulator frames appearing in between VM x86 and ARM frames. note - // that arfgument sp points to the old (VM) stack from which the - // call into the sim was made. The stack switch and entry into this - // routine is handled by x86 prolog code planted in the head of the - // ARM code buffer which the sim is about to start executing (see - // aarch64_linkage.S). - // - // The first ARM instruction in the buffer is identified by fnptr - // stored at the top of the old stack. x86 register contents precede - // fnptr. preceding that are the fp and return address of the VM - // caller into ARM code. any extra, non-register arguments passed to - // the linkage routine precede the fp (this is as per any normal x86 - // call wirth extra args). - // - // note that the sim creates Java frames on the Java stack just - // above sp (i.e. directly above fnptr). it sets the sim FP register - // to the pushed fp for the caller effectively eliding the register - // data saved by the linkage routine. - // - // x86 register call arguments are loaded from the stack into ARM - // call registers. if extra arguments occur preceding the x86 - // caller's fp then they are copied either into extra ARM registers - // (ARM has 8 rather than 6 gp call registers) or up the stack - // beyond the saved x86 registers so that they immediately precede - // the ARM frame where the ARM calling convention expects them to - // be. - // - // n.b. the number of register/stack values passed to the ARM code - // is determined by calltype - // - // +--------+ - // | fnptr | <--- argument sp points here - // +--------+ | - // | rax | | return slot if we need to return a value - // +--------+ | - // | rdi | increasing - // +--------+ address - // | rsi | | - // +--------+ V - // | rdx | - // +--------+ - // | rcx | - // +--------+ - // | r8 | - // +--------+ - // | r9 | - // +--------+ - // | xmm0 | - // +--------+ - // | xmm1 | - // +--------+ - // | xmm2 | - // +--------+ - // | xmm3 | - // +--------+ - // | xmm4 | - // +--------+ - // | xmm5 | - // +--------+ - // | xmm6 | - // +--------+ - // | xmm7 | - // +--------+ - // | fp | - // +--------+ - // | caller | - // | ret ip | - // +--------+ - // | arg0 | <-- any extra call args start here - // +--------+ offset = 18 * wordSize - // | . . . | (i.e. 1 * calladdr + 1 * rax + 6 * gp call regs - // + 8 * fp call regs + 2 * frame words) - // - // we use a unique sim/stack per thread - const int cursor2_offset = 18; - const int fp_offset = 16; - u_int64_t *cursor = (u_int64_t *)sp; - u_int64_t *cursor2 = ((u_int64_t *)sp) + cursor2_offset; - u_int64_t *fp = ((u_int64_t *)sp) + fp_offset; - int gp_arg_count = calltype & 0xf; - int fp_arg_count = (calltype >> 4) & 0xf; - int return_type = (calltype >> 8) & 0x3; - AArch64Simulator *sim = AArch64Simulator::get_current(UseSimulatorCache, DisableBCCheck); - // save previous cpu state in case this is a recursive entry - CPUState saveState = sim->getCPUState(); - // set up initial sim pc, sp and fp registers - sim->init(*cursor++, (u_int64_t)sp, (u_int64_t)fp); - u_int64_t *return_slot = cursor++; - - // if we need to pass the sim extra args on the stack then bump - // the stack pointer now - u_int64_t *cursor3 = (u_int64_t *)sim->getCPUState().xreg(SP, 1); - if (gp_arg_count > 8) { - cursor3 -= gp_arg_count - 8; - } - if (fp_arg_count > 8) { - cursor3 -= fp_arg_count - 8; - } - sim->getCPUState().xreg(SP, 1) = (u_int64_t)(cursor3++); - - for (int i = 0; i < gp_arg_count; i++) { - if (i < 6) { - // copy saved register to sim register - GReg reg = (GReg)i; - sim->getCPUState().xreg(reg, 0) = *cursor++; - } else if (i < 8) { - // copy extra int arg to sim register - GReg reg = (GReg)i; - sim->getCPUState().xreg(reg, 0) = *cursor2++; - } else { - // copy extra fp arg to sim stack - *cursor3++ = *cursor2++; - } - } - for (int i = 0; i < fp_arg_count; i++) { - if (i < 8) { - // copy saved register to sim register - GReg reg = (GReg)i; - sim->getCPUState().xreg(reg, 0) = *cursor++; - } else { - // copy extra arg to sim stack - *cursor3++ = *cursor2++; - } - } - AArch64Simulator::status_t return_status = sim->run(); - if (return_status != AArch64Simulator::STATUS_RETURN){ - sim->simPrint0(); - fatal("invalid status returned from simulator.run()\n"); - } - switch (return_type) { - case MacroAssembler::ret_type_void: - default: - break; - case MacroAssembler::ret_type_integral: - // this overwrites the saved r0 - *return_slot = sim->getCPUState().xreg(R0, 0); - break; - case MacroAssembler::ret_type_float: - *(float *)return_slot = sim->getCPUState().sreg(V0); - break; - case MacroAssembler::ret_type_double: - *(double *)return_slot = sim->getCPUState().dreg(V0); - break; - } - // restore incoimng cpu state - sim->getCPUState() = saveState; -} - -#endif
diff --git a/src/hotspot/cpu/aarch64/aarch64_linkage.S b/src/hotspot/cpu/aarch64/aarch64_linkage.S deleted file mode 100644 index 1370c6a..0000000 --- a/src/hotspot/cpu/aarch64/aarch64_linkage.S +++ /dev/null
@@ -1,167 +0,0 @@ -# -# Copyright (c) 2012, Red Hat. All rights reserved. -# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -# -# This code is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License version 2 only, as -# published by the Free Software Foundation. -# -# This code is distributed in the hope that it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# version 2 for more details (a copy is included in the LICENSE file that -# accompanied this code). -# -# You should have received a copy of the GNU General Public License version -# 2 along with this work; if not, write to the Free Software Foundation, -# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -# -# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -# or visit www.oracle.com if you need additional information or have any -# questions. - -# Routines used to enable x86 VM C++ code to invoke JIT-compiled ARM code -# -- either Java methods or generated stub -- and to allow JIT-compiled -# ARM code to invoke x86 VM C++ code -# -# the code for aarch64_stub_prolog below can be copied into the start -# of the ARM code buffer and patched with a link to the -# C++ routine which starts execution on the simulator. the ARM -# code can be generated immediately following the copied code. - -#ifdef BUILTIN_SIM - - .data - .globl setup_arm_sim, - .type setup_arm_sim,@function - .globl get_alt_stack, - .type get_alt_stack,@function - .globl aarch64_stub_prolog - .p2align 4 -aarch64_stub_prolog: - // entry point -4: lea 1f(%rip), %r11 - mov (%r11), %r10 - mov (%r10), %r10 - jmp *%r10 - .p2align 4 -1: - .set entry_offset, . - 1b - .quad aarch64_prolog_ptr - // 64 bit int used to idenitfy called fn arg/return types - .set calltype_offset, . - 1b - .quad 0 - // arm JIT code follows the stub - .set arm_code_offset, . - 1b - .size aarch64_stub_prolog, .-aarch64_stub_prolog -aarch64_stub_prolog_end: - - .text -aarch64_prolog_ptr: - .quad aarch64_prolog - - .globl aarch64_prolog -aarch64_prolog: - .cfi_startproc - pushq %rbp - .cfi_def_cfa_offset 16 - .cfi_offset 6, -16 - movq %rsp, %rbp - .cfi_def_cfa_register 6 - // save all registers used to pass args - sub $8, %rsp - movd %xmm7, (%rsp) - sub $8, %rsp - movd %xmm6, (%rsp) - sub $8, %rsp - movd %xmm5, (%rsp) - sub $8, %rsp - movd %xmm4, (%rsp) - sub $8, %rsp - movd %xmm3, (%rsp) - sub $8, %rsp - movd %xmm2, (%rsp) - sub $8, %rsp - movd %xmm1, (%rsp) - sub $8, %rsp - movd %xmm0, (%rsp) - push %r9 - push %r8 - push %rcx - push %rdx - push %rsi - push %rdi - // save rax -- this stack slot will be rewritten with a - // return value if needed - push %rax - // temporarily save r11 while we find the other stack - push %r11 - // retrieve alt stack - call get_alt_stack@PLT - pop %r11 - // push start of arm code - lea (arm_code_offset)(%r11), %rsi - push %rsi - // load call type code in arg reg 1 - mov (calltype_offset)(%r11), %rsi - // load current stack pointer in arg reg 0 - mov %rsp, %rdi - // switch to alt stack - mov %rax, %rsp - // save previous stack pointer on new stack - push %rdi - // 16-align the new stack pointer - push %rdi - // call sim setup routine - call setup_arm_sim@PLT - // switch back to old stack - pop %rsp - // pop start of arm code - pop %rdi - // pop rax -- either restores old value or installs return value - pop %rax - // pop arg registers - pop %rdi - pop %rsi - pop %rdx - pop %rcx - pop %r8 - pop %r9 - movd (%rsp), %xmm0 - add $8, %rsp - movd (%rsp), %xmm1 - add $8, %rsp - movd (%rsp), %xmm2 - add $8, %rsp - movd (%rsp), %xmm3 - add $8, %rsp - movd (%rsp), %xmm4 - add $8, %rsp - movd (%rsp), %xmm5 - add $8, %rsp - movd (%rsp), %xmm6 - add $8, %rsp - movd (%rsp), %xmm7 - add $8, %rsp - leave - .cfi_def_cfa 7, 8 - ret - .cfi_endproc - - - .p2align 4 -get_pc: - // get return pc in rdi and then push it back - pop %rdi - push %rdi - ret - - .p2align 4 - .long - .globl aarch64_stub_prolog_size - .type aarch64_stub_prolog_size,@function -aarch64_stub_prolog_size: - leaq aarch64_stub_prolog_end - aarch64_stub_prolog, %rax - ret - -#endif
diff --git a/src/hotspot/cpu/aarch64/abstractInterpreter_aarch64.cpp b/src/hotspot/cpu/aarch64/abstractInterpreter_aarch64.cpp index e73f152..cba7381 100644 --- a/src/hotspot/cpu/aarch64/abstractInterpreter_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/abstractInterpreter_aarch64.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2014, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * @@ -135,7 +135,20 @@ // interpreter_frame_sender_sp interpreter_frame_sender_sp is // the original sp of the caller (the unextended_sp) and // sender_sp is fp+8/16 (32bit/64bit) XXX - intptr_t* locals = interpreter_frame->sender_sp() + max_locals - 1; + // + // The interpreted method entry on AArch64 aligns SP to 16 bytes + // before generating the fixed part of the activation frame. So there + // may be a gap between the locals block and the saved sender SP. For + // an interpreted caller we need to recreate this gap and exactly + // align the incoming parameters with the caller's temporary + // expression stack. For other types of caller frame it doesn't + // matter. + intptr_t* locals; + if (caller->is_interpreted_frame()) { + locals = caller->interpreter_frame_last_sp() + caller_actual_parameters - 1; + } else { + locals = interpreter_frame->sender_sp() + max_locals - 1; + } #ifdef ASSERT if (caller->is_interpreted_frame()) {
diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.cpp b/src/hotspot/cpu/aarch64/assembler_aarch64.cpp index b6c0877..50e774f 100644 --- a/src/hotspot/cpu/aarch64/assembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, Red Hat Inc. All rights reserved. + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020 Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -31,18 +31,13 @@ #include "interpreter/interpreter.hpp" #ifndef PRODUCT -const unsigned long Assembler::asm_bp = 0x00007fffee09ac88; +const uintptr_t Assembler::asm_bp = 0x00007fffee09ac88; #endif #include "compiler/disassembler.hpp" #include "memory/resourceArea.hpp" #include "runtime/interfaceSupport.inline.hpp" #include "runtime/sharedRuntime.hpp" - -// for the moment we reuse the logical/floating point immediate encode -// and decode functiosn provided by the simulator. when we move to -// real hardware we will need to pull taht code into here - #include "immediate_aarch64.hpp" extern "C" void entry(CodeBuffer *cb); @@ -78,7 +73,6 @@ } assert(ok, "Assembler smoke test failed"); } -#endif // ASSERT void entry(CodeBuffer *cb) { @@ -96,538 +90,668 @@ // Smoke test for assembler -#ifdef ASSERT // BEGIN Generated code -- do not edit // Generated by aarch64-asmtest.py Label back, forth; __ bind(back); // ArithOp - __ add(r19, r22, r7, Assembler::LSL, 28); // add x19, x22, x7, LSL #28 - __ sub(r16, r11, r10, Assembler::LSR, 13); // sub x16, x11, x10, LSR #13 - __ adds(r27, r13, r28, Assembler::ASR, 2); // adds x27, x13, x28, ASR #2 - __ subs(r20, r28, r26, Assembler::ASR, 41); // subs x20, x28, x26, ASR #41 - __ addw(r8, r19, r19, Assembler::ASR, 19); // add w8, w19, w19, ASR #19 - __ subw(r4, r9, r10, Assembler::LSL, 14); // sub w4, w9, w10, LSL #14 - __ addsw(r8, r11, r30, Assembler::LSL, 13); // adds w8, w11, w30, LSL #13 - __ subsw(r0, r25, r19, Assembler::LSL, 9); // subs w0, w25, w19, LSL #9 - __ andr(r20, r0, r21, Assembler::LSL, 19); // and x20, x0, x21, LSL #19 - __ orr(r21, r14, r20, Assembler::LSL, 17); // orr x21, x14, x20, LSL #17 - __ eor(r25, r28, r1, Assembler::LSL, 51); // eor x25, x28, x1, LSL #51 - __ ands(r10, r27, r11, Assembler::ASR, 15); // ands x10, x27, x11, ASR #15 - __ andw(r25, r5, r12, Assembler::ASR, 23); // and w25, w5, w12, ASR #23 - __ orrw(r18, r14, r10, Assembler::LSR, 4); // orr w18, w14, w10, LSR #4 - __ eorw(r4, r21, r5, Assembler::ASR, 22); // eor w4, w21, w5, ASR #22 - __ andsw(r21, r0, r5, Assembler::ASR, 29); // ands w21, w0, w5, ASR #29 - __ bic(r26, r30, r6, Assembler::ASR, 37); // bic x26, x30, x6, ASR #37 - __ orn(r3, r1, r13, Assembler::LSR, 29); // orn x3, x1, x13, LSR #29 - __ eon(r0, r28, r9, Assembler::LSL, 47); // eon x0, x28, x9, LSL #47 - __ bics(r29, r5, r28, Assembler::LSL, 46); // bics x29, x5, x28, LSL #46 - __ bicw(r9, r18, r7, Assembler::LSR, 20); // bic w9, w18, w7, LSR #20 - __ ornw(r26, r13, r25, Assembler::ASR, 24); // orn w26, w13, w25, ASR #24 - __ eonw(r25, r4, r19, Assembler::LSL, 6); // eon w25, w4, w19, LSL #6 - __ bicsw(r5, r26, r4, Assembler::LSR, 24); // bics w5, w26, w4, LSR #24 + __ add(r15, r12, r16, Assembler::LSR, 30); // add x15, x12, x16, LSR #30 + __ sub(r1, r15, r3, Assembler::LSR, 32); // sub x1, x15, x3, LSR #32 + __ adds(r13, r25, r5, Assembler::LSL, 13); // adds x13, x25, x5, LSL #13 + __ subs(r22, r28, r6, Assembler::ASR, 17); // subs x22, x28, x6, ASR #17 + __ addw(r0, r9, r22, Assembler::ASR, 6); // add w0, w9, w22, ASR #6 + __ subw(r19, r3, r25, Assembler::LSL, 21); // sub w19, w3, w25, LSL #21 + __ addsw(r4, r19, r11, Assembler::LSL, 20); // adds w4, w19, w11, LSL #20 + __ subsw(r24, r7, r19, Assembler::ASR, 0); // subs w24, w7, w19, ASR #0 + __ andr(r30, r7, r11, Assembler::LSL, 48); // and x30, x7, x11, LSL #48 + __ orr(r24, r8, r15, Assembler::LSL, 12); // orr x24, x8, x15, LSL #12 + __ eor(r17, r9, r23, Assembler::LSL, 1); // eor x17, x9, x23, LSL #1 + __ ands(r14, r11, r4, Assembler::LSR, 55); // ands x14, x11, x4, LSR #55 + __ andw(r19, r7, r12, Assembler::LSR, 17); // and w19, w7, w12, LSR #17 + __ orrw(r19, r27, r11, Assembler::ASR, 28); // orr w19, w27, w11, ASR #28 + __ eorw(r30, r3, r22, Assembler::LSR, 31); // eor w30, w3, w22, LSR #31 + __ andsw(r19, r26, r28, Assembler::ASR, 0); // ands w19, w26, w28, ASR #0 + __ bic(r29, r6, r26, Assembler::LSL, 51); // bic x29, x6, x26, LSL #51 + __ orn(r26, r27, r17, Assembler::LSL, 35); // orn x26, x27, x17, LSL #35 + __ eon(r21, r4, r14, Assembler::LSL, 5); // eon x21, x4, x14, LSL #5 + __ bics(r2, r15, r0, Assembler::ASR, 5); // bics x2, x15, x0, ASR #5 + __ bicw(r2, r7, r2, Assembler::LSL, 29); // bic w2, w7, w2, LSL #29 + __ ornw(r24, r12, r21, Assembler::LSR, 5); // orn w24, w12, w21, LSR #5 + __ eonw(r30, r15, r19, Assembler::LSL, 2); // eon w30, w15, w19, LSL #2 + __ bicsw(r30, r23, r17, Assembler::ASR, 28); // bics w30, w23, w17, ASR #28 // AddSubImmOp - __ addw(r7, r19, 340u); // add w7, w19, #340 - __ addsw(r8, r0, 401u); // adds w8, w0, #401 - __ subw(r29, r20, 163u); // sub w29, w20, #163 - __ subsw(r8, r23, 759u); // subs w8, w23, #759 - __ add(r1, r12, 523u); // add x1, x12, #523 - __ adds(r2, r11, 426u); // adds x2, x11, #426 - __ sub(r14, r29, 716u); // sub x14, x29, #716 - __ subs(r11, r5, 582u); // subs x11, x5, #582 + __ addw(r4, r20, 660u); // add w4, w20, #660 + __ addsw(r2, r10, 710u); // adds w2, w10, #710 + __ subw(r19, r26, 244u); // sub w19, w26, #244 + __ subsw(r28, r13, 73u); // subs w28, w13, #73 + __ add(r2, r30, 862u); // add x2, x30, #862 + __ adds(r27, r16, 574u); // adds x27, x16, #574 + __ sub(r22, r9, 589u); // sub x22, x9, #589 + __ subs(r4, r1, 698u); // subs x4, x1, #698 // LogicalImmOp - __ andw(r23, r22, 32768ul); // and w23, w22, #0x8000 - __ orrw(r4, r10, 4042322160ul); // orr w4, w10, #0xf0f0f0f0 - __ eorw(r0, r24, 4042322160ul); // eor w0, w24, #0xf0f0f0f0 - __ andsw(r19, r29, 2139127680ul); // ands w19, w29, #0x7f807f80 - __ andr(r5, r10, 4503599627354112ul); // and x5, x10, #0xfffffffffc000 - __ orr(r12, r30, 18445618178097414144ul); // orr x12, x30, #0xfffc0000fffc0000 - __ eor(r30, r5, 262128ul); // eor x30, x5, #0x3fff0 - __ ands(r26, r23, 4194300ul); // ands x26, x23, #0x3ffffc + __ andw(r28, r19, 4294709247ull); // and w28, w19, #0xfffc0fff + __ orrw(r27, r5, 536870910ull); // orr w27, w5, #0x1ffffffe + __ eorw(r30, r20, 4294840319ull); // eor w30, w20, #0xfffe0fff + __ andsw(r22, r26, 4294959615ull); // ands w22, w26, #0xffffe1ff + __ andr(r5, r7, 4194300ull); // and x5, x7, #0x3ffffc + __ orr(r13, r7, 18014398509481728ull); // orr x13, x7, #0x3fffffffffff00 + __ eor(r7, r9, 18442240474082197503ull); // eor x7, x9, #0xfff0000000003fff + __ ands(r3, r0, 18374686479671656447ull); // ands x3, x0, #0xff00000000007fff // AbsOp - __ b(__ pc()); // b . - __ b(back); // b back - __ b(forth); // b forth - __ bl(__ pc()); // bl . - __ bl(back); // bl back - __ bl(forth); // bl forth + __ b(__ pc()); // b . + __ b(back); // b back + __ b(forth); // b forth + __ bl(__ pc()); // bl . + __ bl(back); // bl back + __ bl(forth); // bl forth // RegAndAbsOp - __ cbzw(r12, __ pc()); // cbz w12, . - __ cbzw(r12, back); // cbz w12, back - __ cbzw(r12, forth); // cbz w12, forth - __ cbnzw(r20, __ pc()); // cbnz w20, . - __ cbnzw(r20, back); // cbnz w20, back - __ cbnzw(r20, forth); // cbnz w20, forth - __ cbz(r12, __ pc()); // cbz x12, . - __ cbz(r12, back); // cbz x12, back - __ cbz(r12, forth); // cbz x12, forth - __ cbnz(r24, __ pc()); // cbnz x24, . - __ cbnz(r24, back); // cbnz x24, back - __ cbnz(r24, forth); // cbnz x24, forth - __ adr(r6, __ pc()); // adr x6, . - __ adr(r6, back); // adr x6, back - __ adr(r6, forth); // adr x6, forth - __ _adrp(r21, __ pc()); // adrp x21, . + __ cbzw(r16, __ pc()); // cbz w16, . + __ cbzw(r16, back); // cbz w16, back + __ cbzw(r16, forth); // cbz w16, forth + __ cbnzw(r19, __ pc()); // cbnz w19, . + __ cbnzw(r19, back); // cbnz w19, back + __ cbnzw(r19, forth); // cbnz w19, forth + __ cbz(r5, __ pc()); // cbz x5, . + __ cbz(r5, back); // cbz x5, back + __ cbz(r5, forth); // cbz x5, forth + __ cbnz(r4, __ pc()); // cbnz x4, . + __ cbnz(r4, back); // cbnz x4, back + __ cbnz(r4, forth); // cbnz x4, forth + __ adr(r27, __ pc()); // adr x27, . + __ adr(r27, back); // adr x27, back + __ adr(r27, forth); // adr x27, forth + __ _adrp(r16, __ pc()); // adrp x16, . // RegImmAbsOp - __ tbz(r1, 1, __ pc()); // tbz x1, #1, . - __ tbz(r1, 1, back); // tbz x1, #1, back - __ tbz(r1, 1, forth); // tbz x1, #1, forth - __ tbnz(r8, 9, __ pc()); // tbnz x8, #9, . - __ tbnz(r8, 9, back); // tbnz x8, #9, back - __ tbnz(r8, 9, forth); // tbnz x8, #9, forth + __ tbz(r28, 8, __ pc()); // tbz x28, #8, . + __ tbz(r28, 8, back); // tbz x28, #8, back + __ tbz(r28, 8, forth); // tbz x28, #8, forth + __ tbnz(r1, 1, __ pc()); // tbnz x1, #1, . + __ tbnz(r1, 1, back); // tbnz x1, #1, back + __ tbnz(r1, 1, forth); // tbnz x1, #1, forth // MoveWideImmOp - __ movnw(r12, 23175, 0); // movn w12, #23175, lsl 0 - __ movzw(r11, 20476, 16); // movz w11, #20476, lsl 16 - __ movkw(r21, 3716, 0); // movk w21, #3716, lsl 0 - __ movn(r29, 28661, 48); // movn x29, #28661, lsl 48 - __ movz(r3, 6927, 0); // movz x3, #6927, lsl 0 - __ movk(r22, 9828, 16); // movk x22, #9828, lsl 16 + __ movnw(r20, 8639, 16); // movn w20, #8639, lsl 16 + __ movzw(r7, 25835, 0); // movz w7, #25835, lsl 0 + __ movkw(r17, 7261, 0); // movk w17, #7261, lsl 0 + __ movn(r14, 2097, 32); // movn x14, #2097, lsl 32 + __ movz(r9, 16082, 0); // movz x9, #16082, lsl 0 + __ movk(r19, 13962, 16); // movk x19, #13962, lsl 16 // BitfieldOp - __ sbfm(r12, r8, 6, 22); // sbfm x12, x8, #6, #22 - __ bfmw(r19, r25, 25, 19); // bfm w19, w25, #25, #19 - __ ubfmw(r9, r12, 29, 15); // ubfm w9, w12, #29, #15 - __ sbfm(r28, r25, 16, 16); // sbfm x28, x25, #16, #16 - __ bfm(r12, r5, 4, 25); // bfm x12, x5, #4, #25 - __ ubfm(r0, r10, 6, 8); // ubfm x0, x10, #6, #8 + __ sbfm(r9, r22, 6, 22); // sbfm x9, x22, #6, #22 + __ bfmw(r19, r0, 11, 0); // bfm w19, w0, #11, #0 + __ ubfmw(r10, r19, 11, 19); // ubfm w10, w19, #11, #19 + __ sbfm(r4, r15, 5, 17); // sbfm x4, x15, #5, #17 + __ bfm(r3, r5, 19, 28); // bfm x3, x5, #19, #28 + __ ubfm(r12, r28, 17, 2); // ubfm x12, x28, #17, #2 // ExtractOp - __ extrw(r4, r13, r26, 24); // extr w4, w13, w26, #24 - __ extr(r23, r30, r24, 31); // extr x23, x30, x24, #31 + __ extrw(r15, r0, r22, 3); // extr w15, w0, w22, #3 + __ extr(r6, r14, r14, 55); // extr x6, x14, x14, #55 // CondBranchOp - __ br(Assembler::EQ, __ pc()); // b.EQ . - __ br(Assembler::EQ, back); // b.EQ back - __ br(Assembler::EQ, forth); // b.EQ forth - __ br(Assembler::NE, __ pc()); // b.NE . - __ br(Assembler::NE, back); // b.NE back - __ br(Assembler::NE, forth); // b.NE forth - __ br(Assembler::HS, __ pc()); // b.HS . - __ br(Assembler::HS, back); // b.HS back - __ br(Assembler::HS, forth); // b.HS forth - __ br(Assembler::CS, __ pc()); // b.CS . - __ br(Assembler::CS, back); // b.CS back - __ br(Assembler::CS, forth); // b.CS forth - __ br(Assembler::LO, __ pc()); // b.LO . - __ br(Assembler::LO, back); // b.LO back - __ br(Assembler::LO, forth); // b.LO forth - __ br(Assembler::CC, __ pc()); // b.CC . - __ br(Assembler::CC, back); // b.CC back - __ br(Assembler::CC, forth); // b.CC forth - __ br(Assembler::MI, __ pc()); // b.MI . - __ br(Assembler::MI, back); // b.MI back - __ br(Assembler::MI, forth); // b.MI forth - __ br(Assembler::PL, __ pc()); // b.PL . - __ br(Assembler::PL, back); // b.PL back - __ br(Assembler::PL, forth); // b.PL forth - __ br(Assembler::VS, __ pc()); // b.VS . - __ br(Assembler::VS, back); // b.VS back - __ br(Assembler::VS, forth); // b.VS forth - __ br(Assembler::VC, __ pc()); // b.VC . - __ br(Assembler::VC, back); // b.VC back - __ br(Assembler::VC, forth); // b.VC forth - __ br(Assembler::HI, __ pc()); // b.HI . - __ br(Assembler::HI, back); // b.HI back - __ br(Assembler::HI, forth); // b.HI forth - __ br(Assembler::LS, __ pc()); // b.LS . - __ br(Assembler::LS, back); // b.LS back - __ br(Assembler::LS, forth); // b.LS forth - __ br(Assembler::GE, __ pc()); // b.GE . - __ br(Assembler::GE, back); // b.GE back - __ br(Assembler::GE, forth); // b.GE forth - __ br(Assembler::LT, __ pc()); // b.LT . - __ br(Assembler::LT, back); // b.LT back - __ br(Assembler::LT, forth); // b.LT forth - __ br(Assembler::GT, __ pc()); // b.GT . - __ br(Assembler::GT, back); // b.GT back - __ br(Assembler::GT, forth); // b.GT forth - __ br(Assembler::LE, __ pc()); // b.LE . - __ br(Assembler::LE, back); // b.LE back - __ br(Assembler::LE, forth); // b.LE forth - __ br(Assembler::AL, __ pc()); // b.AL . - __ br(Assembler::AL, back); // b.AL back - __ br(Assembler::AL, forth); // b.AL forth - __ br(Assembler::NV, __ pc()); // b.NV . - __ br(Assembler::NV, back); // b.NV back - __ br(Assembler::NV, forth); // b.NV forth + __ br(Assembler::EQ, __ pc()); // b.EQ . + __ br(Assembler::EQ, back); // b.EQ back + __ br(Assembler::EQ, forth); // b.EQ forth + __ br(Assembler::NE, __ pc()); // b.NE . + __ br(Assembler::NE, back); // b.NE back + __ br(Assembler::NE, forth); // b.NE forth + __ br(Assembler::HS, __ pc()); // b.HS . + __ br(Assembler::HS, back); // b.HS back + __ br(Assembler::HS, forth); // b.HS forth + __ br(Assembler::CS, __ pc()); // b.CS . + __ br(Assembler::CS, back); // b.CS back + __ br(Assembler::CS, forth); // b.CS forth + __ br(Assembler::LO, __ pc()); // b.LO . + __ br(Assembler::LO, back); // b.LO back + __ br(Assembler::LO, forth); // b.LO forth + __ br(Assembler::CC, __ pc()); // b.CC . + __ br(Assembler::CC, back); // b.CC back + __ br(Assembler::CC, forth); // b.CC forth + __ br(Assembler::MI, __ pc()); // b.MI . + __ br(Assembler::MI, back); // b.MI back + __ br(Assembler::MI, forth); // b.MI forth + __ br(Assembler::PL, __ pc()); // b.PL . + __ br(Assembler::PL, back); // b.PL back + __ br(Assembler::PL, forth); // b.PL forth + __ br(Assembler::VS, __ pc()); // b.VS . + __ br(Assembler::VS, back); // b.VS back + __ br(Assembler::VS, forth); // b.VS forth + __ br(Assembler::VC, __ pc()); // b.VC . + __ br(Assembler::VC, back); // b.VC back + __ br(Assembler::VC, forth); // b.VC forth + __ br(Assembler::HI, __ pc()); // b.HI . + __ br(Assembler::HI, back); // b.HI back + __ br(Assembler::HI, forth); // b.HI forth + __ br(Assembler::LS, __ pc()); // b.LS . + __ br(Assembler::LS, back); // b.LS back + __ br(Assembler::LS, forth); // b.LS forth + __ br(Assembler::GE, __ pc()); // b.GE . + __ br(Assembler::GE, back); // b.GE back + __ br(Assembler::GE, forth); // b.GE forth + __ br(Assembler::LT, __ pc()); // b.LT . + __ br(Assembler::LT, back); // b.LT back + __ br(Assembler::LT, forth); // b.LT forth + __ br(Assembler::GT, __ pc()); // b.GT . + __ br(Assembler::GT, back); // b.GT back + __ br(Assembler::GT, forth); // b.GT forth + __ br(Assembler::LE, __ pc()); // b.LE . + __ br(Assembler::LE, back); // b.LE back + __ br(Assembler::LE, forth); // b.LE forth + __ br(Assembler::AL, __ pc()); // b.AL . + __ br(Assembler::AL, back); // b.AL back + __ br(Assembler::AL, forth); // b.AL forth + __ br(Assembler::NV, __ pc()); // b.NV . + __ br(Assembler::NV, back); // b.NV back + __ br(Assembler::NV, forth); // b.NV forth // ImmOp - __ svc(12729); // svc #12729 - __ hvc(6788); // hvc #6788 - __ smc(1535); // smc #1535 - __ brk(16766); // brk #16766 - __ hlt(9753); // hlt #9753 + __ svc(22064); // svc #22064 + __ hvc(533); // hvc #533 + __ smc(9942); // smc #9942 + __ brk(4714); // brk #4714 + __ hlt(4302); // hlt #4302 // Op - __ nop(); // nop - __ eret(); // eret - __ drps(); // drps - __ isb(); // isb + __ nop(); // nop + __ eret(); // eret + __ drps(); // drps + __ isb(); // isb // SystemOp - __ dsb(Assembler::SY); // dsb SY - __ dmb(Assembler::ISHST); // dmb ISHST + __ dsb(Assembler::OSH); // dsb OSH + __ dmb(Assembler::NSHLD); // dmb NSHLD // OneRegOp - __ br(r2); // br x2 - __ blr(r5); // blr x5 + __ br(r20); // br x20 + __ blr(r2); // blr x2 // LoadStoreExclusiveOp - __ stxr(r20, r21, r2); // stxr w20, x21, [x2] - __ stlxr(r5, r29, r7); // stlxr w5, x29, [x7] - __ ldxr(r5, r16); // ldxr x5, [x16] - __ ldaxr(r27, r29); // ldaxr x27, [x29] - __ stlr(r0, r29); // stlr x0, [x29] - __ ldar(r21, r28); // ldar x21, [x28] + __ stxr(r18, r23, r0); // stxr w18, x23, [x0] + __ stlxr(r30, r5, r22); // stlxr w30, x5, [x22] + __ ldxr(r5, r8); // ldxr x5, [x8] + __ ldaxr(r20, r16); // ldaxr x20, [x16] + __ stlr(r6, r11); // stlr x6, [x11] + __ ldar(r6, r27); // ldar x6, [x27] // LoadStoreExclusiveOp - __ stxrw(r21, r24, r7); // stxr w21, w24, [x7] - __ stlxrw(r21, r26, r28); // stlxr w21, w26, [x28] - __ ldxrw(r21, r6); // ldxr w21, [x6] - __ ldaxrw(r15, r30); // ldaxr w15, [x30] - __ stlrw(r19, r3); // stlr w19, [x3] - __ ldarw(r22, r2); // ldar w22, [x2] + __ stxrw(r10, r17, r5); // stxr w10, w17, [x5] + __ stlxrw(r22, r9, r12); // stlxr w22, w9, [x12] + __ ldxrw(r27, r8); // ldxr w27, [x8] + __ ldaxrw(r23, r2); // ldaxr w23, [x2] + __ stlrw(r26, r29); // stlr w26, [x29] + __ ldarw(r13, r10); // ldar w13, [x10] // LoadStoreExclusiveOp - __ stxrh(r18, r15, r0); // stxrh w18, w15, [x0] - __ stlxrh(r11, r5, r28); // stlxrh w11, w5, [x28] - __ ldxrh(r29, r6); // ldxrh w29, [x6] - __ ldaxrh(r18, r7); // ldaxrh w18, [x7] - __ stlrh(r25, r28); // stlrh w25, [x28] - __ ldarh(r2, r19); // ldarh w2, [x19] + __ stxrh(r25, r28, r27); // stxrh w25, w28, [x27] + __ stlxrh(r29, r22, r12); // stlxrh w29, w22, [x12] + __ ldxrh(r22, r28); // ldxrh w22, [x28] + __ ldaxrh(r3, r30); // ldaxrh w3, [x30] + __ stlrh(r24, r15); // stlrh w24, [x15] + __ ldarh(r27, r26); // ldarh w27, [x26] // LoadStoreExclusiveOp - __ stxrb(r10, r30, r1); // stxrb w10, w30, [x1] - __ stlxrb(r20, r21, r22); // stlxrb w20, w21, [x22] - __ ldxrb(r25, r2); // ldxrb w25, [x2] - __ ldaxrb(r24, r5); // ldaxrb w24, [x5] - __ stlrb(r16, r3); // stlrb w16, [x3] - __ ldarb(r22, r29); // ldarb w22, [x29] + __ stxrb(r11, r10, r19); // stxrb w11, w10, [x19] + __ stlxrb(r23, r27, r22); // stlxrb w23, w27, [x22] + __ ldxrb(r24, r16); // ldxrb w24, [x16] + __ ldaxrb(r24, r1); // ldaxrb w24, [x1] + __ stlrb(r5, r29); // stlrb w5, [x29] + __ ldarb(r24, r16); // ldarb w24, [x16] // LoadStoreExclusiveOp - __ ldxp(r8, r2, r19); // ldxp x8, x2, [x19] - __ ldaxp(r7, r19, r14); // ldaxp x7, x19, [x14] - __ stxp(r8, r27, r28, r5); // stxp w8, x27, x28, [x5] - __ stlxp(r5, r8, r14, r6); // stlxp w5, x8, x14, [x6] + __ ldxp(r25, r24, r17); // ldxp x25, x24, [x17] + __ ldaxp(r22, r12, r19); // ldaxp x22, x12, [x19] + __ stxp(r0, r26, r21, r25); // stxp w0, x26, x21, [x25] + __ stlxp(r1, r6, r11, r5); // stlxp w1, x6, x11, [x5] // LoadStoreExclusiveOp - __ ldxpw(r25, r4, r22); // ldxp w25, w4, [x22] - __ ldaxpw(r13, r14, r15); // ldaxp w13, w14, [x15] - __ stxpw(r20, r26, r8, r10); // stxp w20, w26, w8, [x10] - __ stlxpw(r23, r18, r18, r18); // stlxp w23, w18, w18, [x18] + __ ldxpw(r13, r14, r4); // ldxp w13, w14, [x4] + __ ldaxpw(r17, r2, r6); // ldaxp w17, w2, [x6] + __ stxpw(r15, r3, r9, r18); // stxp w15, w3, w9, [x18] + __ stlxpw(r18, r17, r4, r9); // stlxp w18, w17, w4, [x9] // base_plus_unscaled_offset // LoadStoreOp - __ str(r30, Address(r11, 99)); // str x30, [x11, 99] - __ strw(r23, Address(r25, -77)); // str w23, [x25, -77] - __ strb(r2, Address(r14, 3)); // strb w2, [x14, 3] - __ strh(r9, Address(r10, 5)); // strh w9, [x10, 5] - __ ldr(r20, Address(r15, 57)); // ldr x20, [x15, 57] - __ ldrw(r12, Address(r16, -78)); // ldr w12, [x16, -78] - __ ldrb(r22, Address(r26, -3)); // ldrb w22, [x26, -3] - __ ldrh(r30, Address(r19, -47)); // ldrh w30, [x19, -47] - __ ldrsb(r9, Address(r10, -12)); // ldrsb x9, [x10, -12] - __ ldrsh(r28, Address(r17, 14)); // ldrsh x28, [x17, 14] - __ ldrshw(r3, Address(r5, 10)); // ldrsh w3, [x5, 10] - __ ldrsw(r17, Address(r17, -91)); // ldrsw x17, [x17, -91] - __ ldrd(v2, Address(r20, -17)); // ldr d2, [x20, -17] - __ ldrs(v22, Address(r7, -10)); // ldr s22, [x7, -10] - __ strd(v30, Address(r18, -223)); // str d30, [x18, -223] - __ strs(v13, Address(r22, 21)); // str s13, [x22, 21] + __ str(r23, Address(r21, -49)); // str x23, [x21, -49] + __ strw(r21, Address(r2, 63)); // str w21, [x2, 63] + __ strb(r27, Address(r28, 11)); // strb w27, [x28, 11] + __ strh(r29, Address(r15, -13)); // strh w29, [x15, -13] + __ ldr(r14, Address(r30, -45)); // ldr x14, [x30, -45] + __ ldrw(r29, Address(r28, 53)); // ldr w29, [x28, 53] + __ ldrb(r20, Address(r26, 7)); // ldrb w20, [x26, 7] + __ ldrh(r25, Address(r2, -50)); // ldrh w25, [x2, -50] + __ ldrsb(r3, Address(r10, -15)); // ldrsb x3, [x10, -15] + __ ldrsh(r14, Address(r15, 19)); // ldrsh x14, [x15, 19] + __ ldrshw(r29, Address(r11, -5)); // ldrsh w29, [x11, -5] + __ ldrsw(r15, Address(r5, -71)); // ldrsw x15, [x5, -71] + __ ldrd(v19, Address(r12, 3)); // ldr d19, [x12, 3] + __ ldrs(v12, Address(r27, 42)); // ldr s12, [x27, 42] + __ strd(v22, Address(r28, 125)); // str d22, [x28, 125] + __ strs(v24, Address(r15, -20)); // str s24, [x15, -20] // pre // LoadStoreOp - __ str(r9, Address(__ pre(r18, -112))); // str x9, [x18, -112]! - __ strw(r29, Address(__ pre(r23, 11))); // str w29, [x23, 11]! - __ strb(r18, Address(__ pre(r12, -1))); // strb w18, [x12, -1]! - __ strh(r16, Address(__ pre(r20, -23))); // strh w16, [x20, -23]! - __ ldr(r3, Address(__ pre(r29, 9))); // ldr x3, [x29, 9]! - __ ldrw(r25, Address(__ pre(r3, 19))); // ldr w25, [x3, 19]! - __ ldrb(r1, Address(__ pre(r29, -1))); // ldrb w1, [x29, -1]! - __ ldrh(r8, Address(__ pre(r29, -57))); // ldrh w8, [x29, -57]! - __ ldrsb(r5, Address(__ pre(r14, -13))); // ldrsb x5, [x14, -13]! - __ ldrsh(r10, Address(__ pre(r27, 1))); // ldrsh x10, [x27, 1]! - __ ldrshw(r11, Address(__ pre(r10, 25))); // ldrsh w11, [x10, 25]! - __ ldrsw(r4, Address(__ pre(r22, -92))); // ldrsw x4, [x22, -92]! - __ ldrd(v11, Address(__ pre(r23, 8))); // ldr d11, [x23, 8]! - __ ldrs(v25, Address(__ pre(r19, 54))); // ldr s25, [x19, 54]! - __ strd(v1, Address(__ pre(r7, -174))); // str d1, [x7, -174]! - __ strs(v8, Address(__ pre(r25, 54))); // str s8, [x25, 54]! + __ str(r8, Address(__ pre(r28, -24))); // str x8, [x28, -24]! + __ strw(r6, Address(__ pre(r15, 37))); // str w6, [x15, 37]! + __ strb(r7, Address(__ pre(r1, 7))); // strb w7, [x1, 7]! + __ strh(r0, Address(__ pre(r17, 30))); // strh w0, [x17, 30]! + __ ldr(r25, Address(__ pre(r29, 84))); // ldr x25, [x29, 84]! + __ ldrw(r26, Address(__ pre(r20, -52))); // ldr w26, [x20, -52]! + __ ldrb(r26, Address(__ pre(r29, -25))); // ldrb w26, [x29, -25]! + __ ldrh(r4, Address(__ pre(r25, 26))); // ldrh w4, [x25, 26]! + __ ldrsb(r28, Address(__ pre(r8, -21))); // ldrsb x28, [x8, -21]! + __ ldrsh(r17, Address(__ pre(r14, -6))); // ldrsh x17, [x14, -6]! + __ ldrshw(r28, Address(__ pre(r23, 10))); // ldrsh w28, [x23, 10]! + __ ldrsw(r30, Address(__ pre(r27, -64))); // ldrsw x30, [x27, -64]! + __ ldrd(v20, Address(__ pre(r30, -242))); // ldr d20, [x30, -242]! + __ ldrs(v17, Address(__ pre(r27, 20))); // ldr s17, [x27, 20]! + __ strd(v7, Address(__ pre(r3, 17))); // str d7, [x3, 17]! + __ strs(v13, Address(__ pre(r11, -16))); // str s13, [x11, -16]! // post // LoadStoreOp - __ str(r5, Address(__ post(r11, 37))); // str x5, [x11], 37 - __ strw(r24, Address(__ post(r15, 19))); // str w24, [x15], 19 - __ strb(r15, Address(__ post(r26, -1))); // strb w15, [x26], -1 - __ strh(r18, Address(__ post(r18, -6))); // strh w18, [x18], -6 - __ ldr(r7, Address(__ post(r2, -230))); // ldr x7, [x2], -230 - __ ldrw(r27, Address(__ post(r11, -27))); // ldr w27, [x11], -27 - __ ldrb(r18, Address(__ post(r3, -25))); // ldrb w18, [x3], -25 - __ ldrh(r10, Address(__ post(r24, -32))); // ldrh w10, [x24], -32 - __ ldrsb(r22, Address(__ post(r10, 4))); // ldrsb x22, [x10], 4 - __ ldrsh(r17, Address(__ post(r12, 25))); // ldrsh x17, [x12], 25 - __ ldrshw(r8, Address(__ post(r7, -62))); // ldrsh w8, [x7], -62 - __ ldrsw(r23, Address(__ post(r22, -51))); // ldrsw x23, [x22], -51 - __ ldrd(v24, Address(__ post(r25, 48))); // ldr d24, [x25], 48 - __ ldrs(v21, Address(__ post(r12, -10))); // ldr s21, [x12], -10 - __ strd(v18, Address(__ post(r13, -222))); // str d18, [x13], -222 - __ strs(v16, Address(__ post(r1, -41))); // str s16, [x1], -41 + __ str(r6, Address(__ post(r9, -61))); // str x6, [x9], -61 + __ strw(r16, Address(__ post(r5, -29))); // str w16, [x5], -29 + __ strb(r29, Address(__ post(r29, 15))); // strb w29, [x29], 15 + __ strh(r4, Address(__ post(r20, 18))); // strh w4, [x20], 18 + __ ldr(r19, Address(__ post(r18, 46))); // ldr x19, [x18], 46 + __ ldrw(r22, Address(__ post(r2, 23))); // ldr w22, [x2], 23 + __ ldrb(r7, Address(__ post(r3, -30))); // ldrb w7, [x3], -30 + __ ldrh(r11, Address(__ post(r12, -29))); // ldrh w11, [x12], -29 + __ ldrsb(r8, Address(__ post(r6, -29))); // ldrsb x8, [x6], -29 + __ ldrsh(r24, Address(__ post(r23, 4))); // ldrsh x24, [x23], 4 + __ ldrshw(r17, Address(__ post(r16, 0))); // ldrsh w17, [x16], 0 + __ ldrsw(r0, Address(__ post(r20, -8))); // ldrsw x0, [x20], -8 + __ ldrd(v20, Address(__ post(r2, -126))); // ldr d20, [x2], -126 + __ ldrs(v19, Address(__ post(r30, -104))); // ldr s19, [x30], -104 + __ strd(v4, Address(__ post(r17, 118))); // str d4, [x17], 118 + __ strs(v21, Address(__ post(r19, -112))); // str s21, [x19], -112 // base_plus_reg // LoadStoreOp - __ str(r2, Address(r22, r15, Address::sxtw(0))); // str x2, [x22, w15, sxtw #0] - __ strw(r2, Address(r16, r29, Address::lsl(0))); // str w2, [x16, x29, lsl #0] - __ strb(r20, Address(r18, r14, Address::uxtw(0))); // strb w20, [x18, w14, uxtw #0] - __ strh(r6, Address(r19, r20, Address::sxtx(1))); // strh w6, [x19, x20, sxtx #1] - __ ldr(r14, Address(r29, r14, Address::sxtw(0))); // ldr x14, [x29, w14, sxtw #0] - __ ldrw(r16, Address(r20, r12, Address::sxtw(2))); // ldr w16, [x20, w12, sxtw #2] - __ ldrb(r9, Address(r12, r0, Address::sxtw(0))); // ldrb w9, [x12, w0, sxtw #0] - __ ldrh(r12, Address(r17, r3, Address::lsl(1))); // ldrh w12, [x17, x3, lsl #1] - __ ldrsb(r2, Address(r17, r3, Address::sxtx(0))); // ldrsb x2, [x17, x3, sxtx #0] - __ ldrsh(r7, Address(r1, r17, Address::uxtw(1))); // ldrsh x7, [x1, w17, uxtw #1] - __ ldrshw(r25, Address(r15, r18, Address::sxtw(1))); // ldrsh w25, [x15, w18, sxtw #1] - __ ldrsw(r23, Address(r21, r12, Address::lsl(0))); // ldrsw x23, [x21, x12, lsl #0] - __ ldrd(v5, Address(r13, r8, Address::lsl(3))); // ldr d5, [x13, x8, lsl #3] - __ ldrs(v3, Address(r10, r22, Address::lsl(2))); // ldr s3, [x10, x22, lsl #2] - __ strd(v14, Address(r2, r27, Address::sxtw(0))); // str d14, [x2, w27, sxtw #0] - __ strs(v20, Address(r6, r25, Address::lsl(0))); // str s20, [x6, x25, lsl #0] + __ str(r26, Address(r2, r19, Address::lsl(3))); // str x26, [x2, x19, lsl #3] + __ strw(r9, Address(r0, r15, Address::sxtw(2))); // str w9, [x0, w15, sxtw #2] + __ strb(r26, Address(r12, r1, Address::lsl(0))); // strb w26, [x12, x1, lsl #0] + __ strh(r21, Address(r11, r10, Address::lsl(1))); // strh w21, [x11, x10, lsl #1] + __ ldr(r16, Address(r23, r16, Address::sxtx(0))); // ldr x16, [x23, x16, sxtx #0] + __ ldrw(r10, Address(r11, r17, Address::sxtw(2))); // ldr w10, [x11, w17, sxtw #2] + __ ldrb(r13, Address(r23, r11, Address::lsl(0))); // ldrb w13, [x23, x11, lsl #0] + __ ldrh(r27, Address(r4, r21, Address::lsl(0))); // ldrh w27, [x4, x21, lsl #0] + __ ldrsb(r26, Address(r8, r15, Address::sxtw(0))); // ldrsb x26, [x8, w15, sxtw #0] + __ ldrsh(r21, Address(r10, r2, Address::sxtw(0))); // ldrsh x21, [x10, w2, sxtw #0] + __ ldrshw(r8, Address(r30, r14, Address::lsl(0))); // ldrsh w8, [x30, x14, lsl #0] + __ ldrsw(r29, Address(r14, r20, Address::sxtx(2))); // ldrsw x29, [x14, x20, sxtx #2] + __ ldrd(v30, Address(r27, r22, Address::sxtx(0))); // ldr d30, [x27, x22, sxtx #0] + __ ldrs(v13, Address(r9, r22, Address::lsl(0))); // ldr s13, [x9, x22, lsl #0] + __ strd(v8, Address(r25, r17, Address::sxtw(3))); // str d8, [x25, w17, sxtw #3] + __ strs(v1, Address(r24, r5, Address::uxtw(2))); // str s1, [x24, w5, uxtw #2] // base_plus_scaled_offset // LoadStoreOp - __ str(r30, Address(r7, 16256)); // str x30, [x7, 16256] - __ strw(r15, Address(r8, 7588)); // str w15, [x8, 7588] - __ strb(r11, Address(r0, 1866)); // strb w11, [x0, 1866] - __ strh(r3, Address(r17, 3734)); // strh w3, [x17, 3734] - __ ldr(r2, Address(r7, 14224)); // ldr x2, [x7, 14224] - __ ldrw(r5, Address(r9, 7396)); // ldr w5, [x9, 7396] - __ ldrb(r28, Address(r9, 1721)); // ldrb w28, [x9, 1721] - __ ldrh(r2, Address(r20, 3656)); // ldrh w2, [x20, 3656] - __ ldrsb(r22, Address(r14, 1887)); // ldrsb x22, [x14, 1887] - __ ldrsh(r8, Address(r0, 4080)); // ldrsh x8, [x0, 4080] - __ ldrshw(r0, Address(r30, 3916)); // ldrsh w0, [x30, 3916] - __ ldrsw(r24, Address(r19, 6828)); // ldrsw x24, [x19, 6828] - __ ldrd(v24, Address(r12, 13032)); // ldr d24, [x12, 13032] - __ ldrs(v8, Address(r8, 7452)); // ldr s8, [x8, 7452] - __ strd(v10, Address(r15, 15992)); // str d10, [x15, 15992] - __ strs(v26, Address(r19, 6688)); // str s26, [x19, 6688] + __ str(r10, Address(r21, 14496)); // str x10, [x21, 14496] + __ strw(r18, Address(r29, 7228)); // str w18, [x29, 7228] + __ strb(r23, Address(r3, 2018)); // strb w23, [x3, 2018] + __ strh(r28, Address(r11, 3428)); // strh w28, [x11, 3428] + __ ldr(r24, Address(r26, 14376)); // ldr x24, [x26, 14376] + __ ldrw(r21, Address(r2, 6972)); // ldr w21, [x2, 6972] + __ ldrb(r4, Address(r5, 1848)); // ldrb w4, [x5, 1848] + __ ldrh(r14, Address(r14, 3112)); // ldrh w14, [x14, 3112] + __ ldrsb(r4, Address(r27, 1959)); // ldrsb x4, [x27, 1959] + __ ldrsh(r4, Address(r27, 3226)); // ldrsh x4, [x27, 3226] + __ ldrshw(r10, Address(r28, 3286)); // ldrsh w10, [x28, 3286] + __ ldrsw(r10, Address(r17, 7912)); // ldrsw x10, [x17, 7912] + __ ldrd(v13, Address(r28, 13400)); // ldr d13, [x28, 13400] + __ ldrs(v24, Address(r3, 7596)); // ldr s24, [x3, 7596] + __ strd(v2, Address(r12, 15360)); // str d2, [x12, 15360] + __ strs(v17, Address(r1, 6492)); // str s17, [x1, 6492] // pcrel // LoadStoreOp - __ ldr(r10, forth); // ldr x10, forth - __ ldrw(r3, __ pc()); // ldr w3, . + __ ldr(r16, __ pc()); // ldr x16, . + __ ldrw(r13, __ pc()); // ldr w13, . // LoadStoreOp - __ prfm(Address(r23, 9)); // prfm PLDL1KEEP, [x23, 9] + __ prfm(Address(r18, -127)); // prfm PLDL1KEEP, [x18, -127] // LoadStoreOp - __ prfm(back); // prfm PLDL1KEEP, back + __ prfm(back); // prfm PLDL1KEEP, back // LoadStoreOp - __ prfm(Address(r3, r8, Address::uxtw(0))); // prfm PLDL1KEEP, [x3, w8, uxtw #0] + __ prfm(Address(r20, r2, Address::lsl(3))); // prfm PLDL1KEEP, [x20, x2, lsl #3] // LoadStoreOp - __ prfm(Address(r11, 15080)); // prfm PLDL1KEEP, [x11, 15080] + __ prfm(Address(r9, 13808)); // prfm PLDL1KEEP, [x9, 13808] // AddSubCarryOp - __ adcw(r13, r9, r28); // adc w13, w9, w28 - __ adcsw(r27, r19, r28); // adcs w27, w19, w28 - __ sbcw(r19, r18, r6); // sbc w19, w18, w6 - __ sbcsw(r14, r20, r3); // sbcs w14, w20, w3 - __ adc(r16, r14, r8); // adc x16, x14, x8 - __ adcs(r0, r29, r8); // adcs x0, x29, x8 - __ sbc(r8, r24, r20); // sbc x8, x24, x20 - __ sbcs(r12, r28, r0); // sbcs x12, x28, x0 + __ adcw(r8, r23, r2); // adc w8, w23, w2 + __ adcsw(r24, r3, r19); // adcs w24, w3, w19 + __ sbcw(r22, r24, r29); // sbc w22, w24, w29 + __ sbcsw(r12, r27, r3); // sbcs w12, w27, w3 + __ adc(r11, r23, r1); // adc x11, x23, x1 + __ adcs(r29, r5, r23); // adcs x29, x5, x23 + __ sbc(r9, r25, r12); // sbc x9, x25, x12 + __ sbcs(r12, r0, r22); // sbcs x12, x0, x22 // AddSubExtendedOp - __ addw(r23, r6, r16, ext::uxtb, 4); // add w23, w6, w16, uxtb #4 - __ addsw(r25, r25, r23, ext::sxth, 2); // adds w25, w25, w23, sxth #2 - __ sub(r26, r22, r4, ext::uxtx, 1); // sub x26, x22, x4, uxtx #1 - __ subsw(r17, r29, r19, ext::sxtx, 3); // subs w17, w29, w19, sxtx #3 - __ add(r11, r30, r21, ext::uxtb, 3); // add x11, x30, x21, uxtb #3 - __ adds(r16, r19, r0, ext::sxtb, 2); // adds x16, x19, x0, sxtb #2 - __ sub(r11, r9, r25, ext::sxtx, 1); // sub x11, x9, x25, sxtx #1 - __ subs(r17, r20, r12, ext::sxtb, 4); // subs x17, x20, x12, sxtb #4 + __ addw(r26, r12, r3, ext::uxtw, 1); // add w26, w12, w3, uxtw #1 + __ addsw(r20, r16, r18, ext::sxtb, 2); // adds w20, w16, w18, sxtb #2 + __ sub(r30, r30, r7, ext::uxtw, 2); // sub x30, x30, x7, uxtw #2 + __ subsw(r11, r21, r2, ext::uxth, 3); // subs w11, w21, w2, uxth #3 + __ add(r2, r26, r1, ext::uxtw, 2); // add x2, x26, x1, uxtw #2 + __ adds(r18, r29, r20, ext::sxth, 1); // adds x18, x29, x20, sxth #1 + __ sub(r14, r16, r4, ext::uxtw, 4); // sub x14, x16, x4, uxtw #4 + __ subs(r0, r17, r23, ext::sxtb, 3); // subs x0, x17, x23, sxtb #3 // ConditionalCompareOp - __ ccmnw(r13, r11, 3u, Assembler::LE); // ccmn w13, w11, #3, LE - __ ccmpw(r13, r12, 2u, Assembler::HI); // ccmp w13, w12, #2, HI - __ ccmn(r3, r2, 12u, Assembler::NE); // ccmn x3, x2, #12, NE - __ ccmp(r7, r21, 3u, Assembler::VS); // ccmp x7, x21, #3, VS + __ ccmnw(r20, r22, 3u, Assembler::PL); // ccmn w20, w22, #3, PL + __ ccmpw(r25, r2, 1u, Assembler::EQ); // ccmp w25, w2, #1, EQ + __ ccmn(r18, r24, 7u, Assembler::GT); // ccmn x18, x24, #7, GT + __ ccmp(r8, r13, 6u, Assembler::PL); // ccmp x8, x13, #6, PL // ConditionalCompareImmedOp - __ ccmnw(r2, 14, 4, Assembler::CC); // ccmn w2, #14, #4, CC - __ ccmpw(r17, 17, 6, Assembler::PL); // ccmp w17, #17, #6, PL - __ ccmn(r10, 12, 0, Assembler::CS); // ccmn x10, #12, #0, CS - __ ccmp(r21, 18, 14, Assembler::GE); // ccmp x21, #18, #14, GE + __ ccmnw(r9, 2, 4, Assembler::VS); // ccmn w9, #2, #4, VS + __ ccmpw(r2, 27, 7, Assembler::EQ); // ccmp w2, #27, #7, EQ + __ ccmn(r16, 1, 2, Assembler::CC); // ccmn x16, #1, #2, CC + __ ccmp(r17, 31, 3, Assembler::LT); // ccmp x17, #31, #3, LT // ConditionalSelectOp - __ cselw(r21, r13, r12, Assembler::GT); // csel w21, w13, w12, GT - __ csincw(r10, r27, r15, Assembler::LS); // csinc w10, w27, w15, LS - __ csinvw(r0, r13, r9, Assembler::HI); // csinv w0, w13, w9, HI - __ csnegw(r18, r4, r26, Assembler::VS); // csneg w18, w4, w26, VS - __ csel(r12, r29, r7, Assembler::LS); // csel x12, x29, x7, LS - __ csinc(r6, r7, r20, Assembler::VC); // csinc x6, x7, x20, VC - __ csinv(r22, r21, r3, Assembler::LE); // csinv x22, x21, x3, LE - __ csneg(r19, r12, r27, Assembler::LS); // csneg x19, x12, x27, LS + __ cselw(r23, r27, r23, Assembler::LS); // csel w23, w27, w23, LS + __ csincw(r10, r0, r6, Assembler::VS); // csinc w10, w0, w6, VS + __ csinvw(r11, r0, r9, Assembler::CC); // csinv w11, w0, w9, CC + __ csnegw(r17, r27, r18, Assembler::LO); // csneg w17, w27, w18, LO + __ csel(r12, r16, r11, Assembler::VC); // csel x12, x16, x11, VC + __ csinc(r6, r28, r6, Assembler::HI); // csinc x6, x28, x6, HI + __ csinv(r13, r27, r26, Assembler::VC); // csinv x13, x27, x26, VC + __ csneg(r29, r22, r18, Assembler::PL); // csneg x29, x22, x18, PL // TwoRegOp - __ rbitw(r0, r16); // rbit w0, w16 - __ rev16w(r17, r23); // rev16 w17, w23 - __ revw(r17, r14); // rev w17, w14 - __ clzw(r24, r30); // clz w24, w30 - __ clsw(r24, r22); // cls w24, w22 - __ rbit(r3, r17); // rbit x3, x17 - __ rev16(r12, r13); // rev16 x12, x13 - __ rev32(r9, r22); // rev32 x9, x22 - __ rev(r0, r0); // rev x0, x0 - __ clz(r5, r16); // clz x5, x16 - __ cls(r25, r22); // cls x25, x22 + __ rbitw(r12, r19); // rbit w12, w19 + __ rev16w(r23, r18); // rev16 w23, w18 + __ revw(r9, r28); // rev w9, w28 + __ clzw(r2, r19); // clz w2, w19 + __ clsw(r25, r29); // cls w25, w29 + __ rbit(r4, r23); // rbit x4, x23 + __ rev16(r29, r18); // rev16 x29, x18 + __ rev32(r7, r8); // rev32 x7, x8 + __ rev(r13, r17); // rev x13, x17 + __ clz(r17, r0); // clz x17, x0 + __ cls(r18, r26); // cls x18, x26 // ThreeRegOp - __ udivw(r29, r4, r0); // udiv w29, w4, w0 - __ sdivw(r0, r29, r29); // sdiv w0, w29, w29 - __ lslvw(r5, r17, r21); // lslv w5, w17, w21 - __ lsrvw(r9, r9, r18); // lsrv w9, w9, w18 - __ asrvw(r1, r27, r8); // asrv w1, w27, w8 - __ rorvw(r18, r20, r13); // rorv w18, w20, w13 - __ udiv(r8, r25, r12); // udiv x8, x25, x12 - __ sdiv(r7, r5, r28); // sdiv x7, x5, x28 - __ lslv(r5, r17, r27); // lslv x5, x17, x27 - __ lsrv(r23, r26, r20); // lsrv x23, x26, x20 - __ asrv(r28, r8, r28); // asrv x28, x8, x28 - __ rorv(r3, r29, r4); // rorv x3, x29, x4 + __ udivw(r11, r12, r16); // udiv w11, w12, w16 + __ sdivw(r4, r9, r7); // sdiv w4, w9, w7 + __ lslvw(r12, r7, r16); // lslv w12, w7, w16 + __ lsrvw(r19, r16, r23); // lsrv w19, w16, w23 + __ asrvw(r7, r4, r6); // asrv w7, w4, w6 + __ rorvw(r21, r20, r23); // rorv w21, w20, w23 + __ udiv(r16, r12, r28); // udiv x16, x12, x28 + __ sdiv(r4, r12, r13); // sdiv x4, x12, x13 + __ lslv(r9, r13, r7); // lslv x9, x13, x7 + __ lsrv(r28, r27, r15); // lsrv x28, x27, x15 + __ asrv(r20, r30, r14); // asrv x20, x30, x14 + __ rorv(r14, r18, r30); // rorv x14, x18, x30 + __ umulh(r3, r11, r7); // umulh x3, x11, x7 + __ smulh(r23, r20, r24); // smulh x23, x20, x24 // FourRegMulOp - __ maddw(r17, r14, r26, r21); // madd w17, w14, w26, w21 - __ msubw(r1, r30, r11, r11); // msub w1, w30, w11, w11 - __ madd(r1, r17, r6, r28); // madd x1, x17, x6, x28 - __ msub(r30, r6, r30, r8); // msub x30, x6, x30, x8 - __ smaddl(r21, r6, r14, r8); // smaddl x21, w6, w14, x8 - __ smsubl(r10, r10, r24, r19); // smsubl x10, w10, w24, x19 - __ umaddl(r20, r18, r14, r24); // umaddl x20, w18, w14, x24 - __ umsubl(r18, r2, r5, r5); // umsubl x18, w2, w5, x5 + __ maddw(r2, r5, r21, r9); // madd w2, w5, w21, w9 + __ msubw(r24, r24, r4, r8); // msub w24, w24, w4, w8 + __ madd(r11, r12, r15, r19); // madd x11, x12, x15, x19 + __ msub(r29, r25, r12, r25); // msub x29, x25, x12, x25 + __ smaddl(r17, r11, r12, r22); // smaddl x17, w11, w12, x22 + __ smsubl(r28, r3, r20, r18); // smsubl x28, w3, w20, x18 + __ umaddl(r7, r4, r28, r26); // umaddl x7, w4, w28, x26 + __ umsubl(r22, r10, r17, r5); // umsubl x22, w10, w17, x5 // ThreeRegFloatOp - __ fmuls(v8, v18, v13); // fmul s8, s18, s13 - __ fdivs(v2, v14, v28); // fdiv s2, s14, s28 - __ fadds(v15, v12, v28); // fadd s15, s12, s28 - __ fsubs(v0, v12, v1); // fsub s0, s12, s1 - __ fmuls(v15, v29, v4); // fmul s15, s29, s4 - __ fmuld(v12, v1, v23); // fmul d12, d1, d23 - __ fdivd(v27, v8, v18); // fdiv d27, d8, d18 - __ faddd(v23, v20, v11); // fadd d23, d20, d11 - __ fsubd(v8, v12, v18); // fsub d8, d12, d18 - __ fmuld(v26, v24, v23); // fmul d26, d24, d23 + __ fmuls(v17, v3, v17); // fmul s17, s3, s17 + __ fdivs(v11, v17, v6); // fdiv s11, s17, s6 + __ fadds(v29, v7, v9); // fadd s29, s7, s9 + __ fsubs(v7, v12, v19); // fsub s7, s12, s19 + __ fmuls(v0, v23, v3); // fmul s0, s23, s3 + __ fmuld(v26, v3, v21); // fmul d26, d3, d21 + __ fdivd(v0, v19, v5); // fdiv d0, d19, d5 + __ faddd(v0, v26, v9); // fadd d0, d26, d9 + __ fsubd(v25, v21, v21); // fsub d25, d21, d21 + __ fmuld(v16, v13, v19); // fmul d16, d13, d19 // FourRegFloatOp - __ fmadds(v21, v23, v13, v25); // fmadd s21, s23, s13, s25 - __ fmsubs(v22, v10, v1, v14); // fmsub s22, s10, s1, s14 - __ fnmadds(v14, v20, v2, v30); // fnmadd s14, s20, s2, s30 - __ fnmadds(v7, v29, v22, v22); // fnmadd s7, s29, s22, s22 - __ fmaddd(v13, v5, v15, v5); // fmadd d13, d5, d15, d5 - __ fmsubd(v14, v12, v5, v10); // fmsub d14, d12, d5, d10 - __ fnmaddd(v10, v19, v0, v1); // fnmadd d10, d19, d0, d1 - __ fnmaddd(v20, v2, v2, v0); // fnmadd d20, d2, d2, d0 + __ fmadds(v29, v18, v0, v16); // fmadd s29, s18, s0, s16 + __ fmsubs(v23, v13, v29, v5); // fmsub s23, s13, s29, s5 + __ fnmadds(v9, v7, v10, v14); // fnmadd s9, s7, s10, s14 + __ fnmadds(v25, v28, v15, v23); // fnmadd s25, s28, s15, s23 + __ fmaddd(v6, v13, v21, v17); // fmadd d6, d13, d21, d17 + __ fmsubd(v3, v21, v2, v7); // fmsub d3, d21, d2, d7 + __ fnmaddd(v10, v25, v5, v17); // fnmadd d10, d25, d5, d17 + __ fnmaddd(v14, v14, v20, v18); // fnmadd d14, d14, d20, d18 // TwoRegFloatOp - __ fmovs(v25, v9); // fmov s25, s9 - __ fabss(v20, v4); // fabs s20, s4 - __ fnegs(v3, v27); // fneg s3, s27 - __ fsqrts(v1, v2); // fsqrt s1, s2 - __ fcvts(v30, v0); // fcvt d30, s0 - __ fmovd(v12, v4); // fmov d12, d4 - __ fabsd(v1, v27); // fabs d1, d27 - __ fnegd(v8, v22); // fneg d8, d22 - __ fsqrtd(v11, v11); // fsqrt d11, d11 - __ fcvtd(v22, v28); // fcvt s22, d28 + __ fmovs(v15, v2); // fmov s15, s2 + __ fabss(v18, v7); // fabs s18, s7 + __ fnegs(v3, v6); // fneg s3, s6 + __ fsqrts(v12, v1); // fsqrt s12, s1 + __ fcvts(v9, v0); // fcvt d9, s0 + __ fmovd(v4, v5); // fmov d4, d5 + __ fabsd(v3, v15); // fabs d3, d15 + __ fnegd(v17, v25); // fneg d17, d25 + __ fsqrtd(v12, v24); // fsqrt d12, d24 + __ fcvtd(v21, v5); // fcvt s21, d5 // FloatConvertOp - __ fcvtzsw(r28, v22); // fcvtzs w28, s22 - __ fcvtzs(r20, v27); // fcvtzs x20, s27 - __ fcvtzdw(r14, v0); // fcvtzs w14, d0 - __ fcvtzd(r26, v11); // fcvtzs x26, d11 - __ scvtfws(v28, r22); // scvtf s28, w22 - __ scvtfs(v16, r10); // scvtf s16, x10 - __ scvtfwd(v8, r21); // scvtf d8, w21 - __ scvtfd(v21, r28); // scvtf d21, x28 - __ fmovs(r24, v24); // fmov w24, s24 - __ fmovd(r8, v19); // fmov x8, d19 - __ fmovs(v8, r12); // fmov s8, w12 - __ fmovd(v6, r7); // fmov d6, x7 + __ fcvtzsw(r4, v21); // fcvtzs w4, s21 + __ fcvtzs(r27, v3); // fcvtzs x27, s3 + __ fcvtzdw(r29, v8); // fcvtzs w29, d8 + __ fcvtzd(r9, v21); // fcvtzs x9, d21 + __ scvtfws(v20, r29); // scvtf s20, w29 + __ scvtfs(v7, r8); // scvtf s7, x8 + __ scvtfwd(v12, r21); // scvtf d12, w21 + __ scvtfd(v16, r21); // scvtf d16, x21 + __ fmovs(r18, v5); // fmov w18, s5 + __ fmovd(r25, v8); // fmov x25, d8 + __ fmovs(v18, r26); // fmov s18, w26 + __ fmovd(v0, r11); // fmov d0, x11 // TwoRegFloatOp - __ fcmps(v30, v16); // fcmp s30, s16 - __ fcmpd(v25, v11); // fcmp d25, d11 - __ fcmps(v11, 0.0); // fcmp s11, #0.0 - __ fcmpd(v11, 0.0); // fcmp d11, #0.0 + __ fcmps(v16, v6); // fcmp s16, s6 + __ fcmpd(v16, v29); // fcmp d16, d29 + __ fcmps(v30, 0.0); // fcmp s30, #0.0 + __ fcmpd(v9, 0.0); // fcmp d9, #0.0 // LoadStorePairOp - __ stpw(r29, r12, Address(r17, 128)); // stp w29, w12, [x17, #128] - __ ldpw(r22, r18, Address(r14, -96)); // ldp w22, w18, [x14, #-96] - __ ldpsw(r11, r16, Address(r1, 64)); // ldpsw x11, x16, [x1, #64] - __ stp(r0, r11, Address(r26, 112)); // stp x0, x11, [x26, #112] - __ ldp(r7, r1, Address(r26, 16)); // ldp x7, x1, [x26, #16] + __ stpw(r27, r4, Address(r12, -16)); // stp w27, w4, [x12, #-16] + __ ldpw(r3, r9, Address(r10, 80)); // ldp w3, w9, [x10, #80] + __ ldpsw(r16, r3, Address(r3, 64)); // ldpsw x16, x3, [x3, #64] + __ stp(r10, r28, Address(r19, -192)); // stp x10, x28, [x19, #-192] + __ ldp(r19, r18, Address(r7, -192)); // ldp x19, x18, [x7, #-192] // LoadStorePairOp - __ stpw(r10, r7, Address(__ pre(r24, 0))); // stp w10, w7, [x24, #0]! - __ ldpw(r7, r28, Address(__ pre(r24, -256))); // ldp w7, w28, [x24, #-256]! - __ ldpsw(r25, r28, Address(__ pre(r21, -240))); // ldpsw x25, x28, [x21, #-240]! - __ stp(r20, r18, Address(__ pre(r14, -16))); // stp x20, x18, [x14, #-16]! - __ ldp(r8, r10, Address(__ pre(r13, 80))); // ldp x8, x10, [x13, #80]! + __ stpw(r10, r16, Address(__ pre(r30, 16))); // stp w10, w16, [x30, #16]! + __ ldpw(r2, r4, Address(__ pre(r18, -240))); // ldp w2, w4, [x18, #-240]! + __ ldpsw(r24, r19, Address(__ pre(r13, 48))); // ldpsw x24, x19, [x13, #48]! + __ stp(r17, r0, Address(__ pre(r24, 0))); // stp x17, x0, [x24, #0]! + __ ldp(r14, r26, Address(__ pre(r3, -192))); // ldp x14, x26, [x3, #-192]! // LoadStorePairOp - __ stpw(r26, r24, Address(__ post(r2, -128))); // stp w26, w24, [x2], #-128 - __ ldpw(r2, r25, Address(__ post(r21, -192))); // ldp w2, w25, [x21], #-192 - __ ldpsw(r17, r2, Address(__ post(r21, -144))); // ldpsw x17, x2, [x21], #-144 - __ stp(r12, r10, Address(__ post(r11, 96))); // stp x12, x10, [x11], #96 - __ ldp(r24, r6, Address(__ post(r17, -32))); // ldp x24, x6, [x17], #-32 + __ stpw(r22, r1, Address(__ post(r0, 80))); // stp w22, w1, [x0], #80 + __ ldpw(r18, r10, Address(__ post(r0, -16))); // ldp w18, w10, [x0], #-16 + __ ldpsw(r24, r24, Address(__ post(r22, -16))); // ldpsw x24, x24, [x22], #-16 + __ stp(r12, r12, Address(__ post(r4, 80))); // stp x12, x12, [x4], #80 + __ ldp(r4, r9, Address(__ post(r19, -240))); // ldp x4, x9, [x19], #-240 // LoadStorePairOp - __ stnpw(r3, r30, Address(r14, -224)); // stnp w3, w30, [x14, #-224] - __ ldnpw(r15, r20, Address(r26, -144)); // ldnp w15, w20, [x26, #-144] - __ stnp(r22, r25, Address(r12, -128)); // stnp x22, x25, [x12, #-128] - __ ldnp(r27, r22, Address(r17, -176)); // ldnp x27, x22, [x17, #-176] + __ stnpw(r18, r26, Address(r6, -224)); // stnp w18, w26, [x6, #-224] + __ ldnpw(r21, r20, Address(r1, 112)); // ldnp w21, w20, [x1, #112] + __ stnp(r25, r29, Address(r20, -224)); // stnp x25, x29, [x20, #-224] + __ ldnp(r1, r5, Address(r23, 112)); // ldnp x1, x5, [x23, #112] + +// LdStSIMDOp + __ ld1(v4, __ T8B, Address(r20)); // ld1 {v4.8B}, [x20] + __ ld1(v24, v25, __ T16B, Address(__ post(r10, 32))); // ld1 {v24.16B, v25.16B}, [x10], 32 + __ ld1(v24, v25, v26, __ T1D, Address(__ post(r6, r15))); // ld1 {v24.1D, v25.1D, v26.1D}, [x6], x15 + __ ld1(v3, v4, v5, v6, __ T8H, Address(__ post(r4, 64))); // ld1 {v3.8H, v4.8H, v5.8H, v6.8H}, [x4], 64 + __ ld1r(v2, __ T8B, Address(r6)); // ld1r {v2.8B}, [x6] + __ ld1r(v13, __ T4S, Address(__ post(r14, 4))); // ld1r {v13.4S}, [x14], 4 + __ ld1r(v15, __ T1D, Address(__ post(r21, r24))); // ld1r {v15.1D}, [x21], x24 + __ ld2(v9, v10, __ T2D, Address(r21)); // ld2 {v9.2D, v10.2D}, [x21] + __ ld2(v29, v30, __ T4H, Address(__ post(r21, 16))); // ld2 {v29.4H, v30.4H}, [x21], 16 + __ ld2r(v8, v9, __ T16B, Address(r14)); // ld2r {v8.16B, v9.16B}, [x14] + __ ld2r(v7, v8, __ T2S, Address(__ post(r20, 8))); // ld2r {v7.2S, v8.2S}, [x20], 8 + __ ld2r(v28, v29, __ T2D, Address(__ post(r3, r3))); // ld2r {v28.2D, v29.2D}, [x3], x3 + __ ld3(v27, v28, v29, __ T4S, Address(__ post(r11, r29))); // ld3 {v27.4S, v28.4S, v29.4S}, [x11], x29 + __ ld3(v16, v17, v18, __ T2S, Address(r10)); // ld3 {v16.2S, v17.2S, v18.2S}, [x10] + __ ld3r(v21, v22, v23, __ T8H, Address(r12)); // ld3r {v21.8H, v22.8H, v23.8H}, [x12] + __ ld3r(v4, v5, v6, __ T4S, Address(__ post(r29, 12))); // ld3r {v4.4S, v5.4S, v6.4S}, [x29], 12 + __ ld3r(v24, v25, v26, __ T1D, Address(__ post(r9, r19))); // ld3r {v24.1D, v25.1D, v26.1D}, [x9], x19 + __ ld4(v10, v11, v12, v13, __ T8H, Address(__ post(r3, 64))); // ld4 {v10.8H, v11.8H, v12.8H, v13.8H}, [x3], 64 + __ ld4(v27, v28, v29, v30, __ T8B, Address(__ post(r28, r9))); // ld4 {v27.8B, v28.8B, v29.8B, v30.8B}, [x28], x9 + __ ld4r(v21, v22, v23, v24, __ T8B, Address(r30)); // ld4r {v21.8B, v22.8B, v23.8B, v24.8B}, [x30] + __ ld4r(v23, v24, v25, v26, __ T4H, Address(__ post(r14, 8))); // ld4r {v23.4H, v24.4H, v25.4H, v26.4H}, [x14], 8 + __ ld4r(v4, v5, v6, v7, __ T2S, Address(__ post(r13, r20))); // ld4r {v4.2S, v5.2S, v6.2S, v7.2S}, [x13], x20 + +// SpecialCases + __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE + __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ + __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE + __ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT + __ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0 + __ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp] + __ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3] + __ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5] + __ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp] + __ dup(v0, __ T16B, zr); // dup v0.16b, wzr + __ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr + __ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr + __ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr + __ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr + __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0 // FloatImmediateOp - __ fmovd(v0, 2.0); // fmov d0, #2.0 - __ fmovd(v0, 2.125); // fmov d0, #2.125 - __ fmovd(v0, 4.0); // fmov d0, #4.0 - __ fmovd(v0, 4.25); // fmov d0, #4.25 - __ fmovd(v0, 8.0); // fmov d0, #8.0 - __ fmovd(v0, 8.5); // fmov d0, #8.5 - __ fmovd(v0, 16.0); // fmov d0, #16.0 - __ fmovd(v0, 17.0); // fmov d0, #17.0 - __ fmovd(v0, 0.125); // fmov d0, #0.125 - __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125 - __ fmovd(v0, 0.25); // fmov d0, #0.25 - __ fmovd(v0, 0.265625); // fmov d0, #0.265625 - __ fmovd(v0, 0.5); // fmov d0, #0.5 - __ fmovd(v0, 0.53125); // fmov d0, #0.53125 - __ fmovd(v0, 1.0); // fmov d0, #1.0 - __ fmovd(v0, 1.0625); // fmov d0, #1.0625 - __ fmovd(v0, -2.0); // fmov d0, #-2.0 - __ fmovd(v0, -2.125); // fmov d0, #-2.125 - __ fmovd(v0, -4.0); // fmov d0, #-4.0 - __ fmovd(v0, -4.25); // fmov d0, #-4.25 - __ fmovd(v0, -8.0); // fmov d0, #-8.0 - __ fmovd(v0, -8.5); // fmov d0, #-8.5 - __ fmovd(v0, -16.0); // fmov d0, #-16.0 - __ fmovd(v0, -17.0); // fmov d0, #-17.0 - __ fmovd(v0, -0.125); // fmov d0, #-0.125 - __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125 - __ fmovd(v0, -0.25); // fmov d0, #-0.25 - __ fmovd(v0, -0.265625); // fmov d0, #-0.265625 - __ fmovd(v0, -0.5); // fmov d0, #-0.5 - __ fmovd(v0, -0.53125); // fmov d0, #-0.53125 - __ fmovd(v0, -1.0); // fmov d0, #-1.0 - __ fmovd(v0, -1.0625); // fmov d0, #-1.0625 + __ fmovd(v0, 2.0); // fmov d0, #2.0 + __ fmovd(v0, 2.125); // fmov d0, #2.125 + __ fmovd(v0, 4.0); // fmov d0, #4.0 + __ fmovd(v0, 4.25); // fmov d0, #4.25 + __ fmovd(v0, 8.0); // fmov d0, #8.0 + __ fmovd(v0, 8.5); // fmov d0, #8.5 + __ fmovd(v0, 16.0); // fmov d0, #16.0 + __ fmovd(v0, 17.0); // fmov d0, #17.0 + __ fmovd(v0, 0.125); // fmov d0, #0.125 + __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125 + __ fmovd(v0, 0.25); // fmov d0, #0.25 + __ fmovd(v0, 0.265625); // fmov d0, #0.265625 + __ fmovd(v0, 0.5); // fmov d0, #0.5 + __ fmovd(v0, 0.53125); // fmov d0, #0.53125 + __ fmovd(v0, 1.0); // fmov d0, #1.0 + __ fmovd(v0, 1.0625); // fmov d0, #1.0625 + __ fmovd(v0, -2.0); // fmov d0, #-2.0 + __ fmovd(v0, -2.125); // fmov d0, #-2.125 + __ fmovd(v0, -4.0); // fmov d0, #-4.0 + __ fmovd(v0, -4.25); // fmov d0, #-4.25 + __ fmovd(v0, -8.0); // fmov d0, #-8.0 + __ fmovd(v0, -8.5); // fmov d0, #-8.5 + __ fmovd(v0, -16.0); // fmov d0, #-16.0 + __ fmovd(v0, -17.0); // fmov d0, #-17.0 + __ fmovd(v0, -0.125); // fmov d0, #-0.125 + __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125 + __ fmovd(v0, -0.25); // fmov d0, #-0.25 + __ fmovd(v0, -0.265625); // fmov d0, #-0.265625 + __ fmovd(v0, -0.5); // fmov d0, #-0.5 + __ fmovd(v0, -0.53125); // fmov d0, #-0.53125 + __ fmovd(v0, -1.0); // fmov d0, #-1.0 + __ fmovd(v0, -1.0625); // fmov d0, #-1.0625 + +// LSEOp + __ swp(Assembler::xword, r21, r5, r24); // swp x21, x5, [x24] + __ ldadd(Assembler::xword, r13, r13, r15); // ldadd x13, x13, [x15] + __ ldbic(Assembler::xword, r22, r19, r26); // ldclr x22, x19, [x26] + __ ldeor(Assembler::xword, r25, r10, r26); // ldeor x25, x10, [x26] + __ ldorr(Assembler::xword, r5, r27, r15); // ldset x5, x27, [x15] + __ ldsmin(Assembler::xword, r19, r5, r11); // ldsmin x19, x5, [x11] + __ ldsmax(Assembler::xword, r26, r0, r4); // ldsmax x26, x0, [x4] + __ ldumin(Assembler::xword, r22, r23, r30); // ldumin x22, x23, [x30] + __ ldumax(Assembler::xword, r18, r28, r8); // ldumax x18, x28, [x8] + +// LSEOp + __ swpa(Assembler::xword, r13, r29, r27); // swpa x13, x29, [x27] + __ ldadda(Assembler::xword, r11, r5, r13); // ldadda x11, x5, [x13] + __ ldbica(Assembler::xword, r1, r24, r21); // ldclra x1, x24, [x21] + __ ldeora(Assembler::xword, r27, r17, r24); // ldeora x27, x17, [x24] + __ ldorra(Assembler::xword, r18, r30, r5); // ldseta x18, x30, [x5] + __ ldsmina(Assembler::xword, r7, r22, r25); // ldsmina x7, x22, [x25] + __ ldsmaxa(Assembler::xword, r4, r26, r19); // ldsmaxa x4, x26, [x19] + __ ldumina(Assembler::xword, r6, r30, r3); // ldumina x6, x30, [x3] + __ ldumaxa(Assembler::xword, r24, r23, r5); // ldumaxa x24, x23, [x5] + +// LSEOp + __ swpal(Assembler::xword, r24, r18, r28); // swpal x24, x18, [x28] + __ ldaddal(Assembler::xword, r19, zr, r7); // ldaddal x19, xzr, [x7] + __ ldbical(Assembler::xword, r13, r6, r28); // ldclral x13, x6, [x28] + __ ldeoral(Assembler::xword, r8, r15, r21); // ldeoral x8, x15, [x21] + __ ldorral(Assembler::xword, r2, r13, r1); // ldsetal x2, x13, [x1] + __ ldsminal(Assembler::xword, r17, r29, r25); // ldsminal x17, x29, [x25] + __ ldsmaxal(Assembler::xword, r25, r18, r14); // ldsmaxal x25, x18, [x14] + __ lduminal(Assembler::xword, zr, r6, r27); // lduminal xzr, x6, [x27] + __ ldumaxal(Assembler::xword, r16, r5, r15); // ldumaxal x16, x5, [x15] + +// LSEOp + __ swpl(Assembler::xword, r11, r18, r3); // swpl x11, x18, [x3] + __ ldaddl(Assembler::xword, r26, r20, r2); // ldaddl x26, x20, [x2] + __ ldbicl(Assembler::xword, r11, r4, r11); // ldclrl x11, x4, [x11] + __ ldeorl(Assembler::xword, r30, r19, r23); // ldeorl x30, x19, [x23] + __ ldorrl(Assembler::xword, r3, r15, r14); // ldsetl x3, x15, [x14] + __ ldsminl(Assembler::xword, r30, r22, r20); // ldsminl x30, x22, [x20] + __ ldsmaxl(Assembler::xword, r7, r5, r24); // ldsmaxl x7, x5, [x24] + __ lduminl(Assembler::xword, r23, r16, r15); // lduminl x23, x16, [x15] + __ ldumaxl(Assembler::xword, r11, r19, r0); // ldumaxl x11, x19, [x0] + +// LSEOp + __ swp(Assembler::word, r28, r28, r1); // swp w28, w28, [x1] + __ ldadd(Assembler::word, r11, r21, r12); // ldadd w11, w21, [x12] + __ ldbic(Assembler::word, r29, r0, r18); // ldclr w29, w0, [x18] + __ ldeor(Assembler::word, r5, r0, r25); // ldeor w5, w0, [x25] + __ ldorr(Assembler::word, r14, r0, r26); // ldset w14, w0, [x26] + __ ldsmin(Assembler::word, r28, r18, r29); // ldsmin w28, w18, [x29] + __ ldsmax(Assembler::word, r15, r1, r29); // ldsmax w15, w1, [x29] + __ ldumin(Assembler::word, r8, r26, r28); // ldumin w8, w26, [x28] + __ ldumax(Assembler::word, r17, r14, r4); // ldumax w17, w14, [x4] + +// LSEOp + __ swpa(Assembler::word, r24, r25, r1); // swpa w24, w25, [x1] + __ ldadda(Assembler::word, r10, r17, r17); // ldadda w10, w17, [x17] + __ ldbica(Assembler::word, r29, r20, r21); // ldclra w29, w20, [x21] + __ ldeora(Assembler::word, r29, r9, r12); // ldeora w29, w9, [x12] + __ ldorra(Assembler::word, r11, r6, r5); // ldseta w11, w6, [x5] + __ ldsmina(Assembler::word, r21, r7, r21); // ldsmina w21, w7, [x21] + __ ldsmaxa(Assembler::word, r10, r23, r12); // ldsmaxa w10, w23, [x12] + __ ldumina(Assembler::word, r21, r5, r10); // ldumina w21, w5, [x10] + __ ldumaxa(Assembler::word, r30, r20, r18); // ldumaxa w30, w20, [x18] + +// LSEOp + __ swpal(Assembler::word, r13, r23, r5); // swpal w13, w23, [x5] + __ ldaddal(Assembler::word, r15, r24, r5); // ldaddal w15, w24, [x5] + __ ldbical(Assembler::word, r9, r10, r25); // ldclral w9, w10, [x25] + __ ldeoral(Assembler::word, r20, r17, r17); // ldeoral w20, w17, [x17] + __ ldorral(Assembler::word, r12, r18, r30); // ldsetal w12, w18, [x30] + __ ldsminal(Assembler::word, r3, r3, r25); // ldsminal w3, w3, [x25] + __ ldsmaxal(Assembler::word, r26, r25, r10); // ldsmaxal w26, w25, [x10] + __ lduminal(Assembler::word, r2, r11, sp); // lduminal w2, w11, [sp] + __ ldumaxal(Assembler::word, r7, r2, r5); // ldumaxal w7, w2, [x5] + +// LSEOp + __ swpl(Assembler::word, r0, r7, r20); // swpl w0, w7, [x20] + __ ldaddl(Assembler::word, r5, zr, r2); // ldaddl w5, wzr, [x2] + __ ldbicl(Assembler::word, r27, r25, r27); // ldclrl w27, w25, [x27] + __ ldeorl(Assembler::word, r30, r24, r26); // ldeorl w30, w24, [x26] + __ ldorrl(Assembler::word, r15, r2, r22); // ldsetl w15, w2, [x22] + __ ldsminl(Assembler::word, r0, r3, sp); // ldsminl w0, w3, [sp] + __ ldsmaxl(Assembler::word, r15, r20, r10); // ldsmaxl w15, w20, [x10] + __ lduminl(Assembler::word, r22, r21, r14); // lduminl w22, w21, [x14] + __ ldumaxl(Assembler::word, r6, r30, r2); // ldumaxl w6, w30, [x2] __ bind(forth); @@ -638,542 +762,681 @@ Disassembly of section .text: 0000000000000000 <back>: - 0: 8b0772d3 add x19, x22, x7, lsl #28 - 4: cb4a3570 sub x16, x11, x10, lsr #13 - 8: ab9c09bb adds x27, x13, x28, asr #2 - c: eb9aa794 subs x20, x28, x26, asr #41 - 10: 0b934e68 add w8, w19, w19, asr #19 - 14: 4b0a3924 sub w4, w9, w10, lsl #14 - 18: 2b1e3568 adds w8, w11, w30, lsl #13 - 1c: 6b132720 subs w0, w25, w19, lsl #9 - 20: 8a154c14 and x20, x0, x21, lsl #19 - 24: aa1445d5 orr x21, x14, x20, lsl #17 - 28: ca01cf99 eor x25, x28, x1, lsl #51 - 2c: ea8b3f6a ands x10, x27, x11, asr #15 - 30: 0a8c5cb9 and w25, w5, w12, asr #23 - 34: 2a4a11d2 orr w18, w14, w10, lsr #4 - 38: 4a855aa4 eor w4, w21, w5, asr #22 - 3c: 6a857415 ands w21, w0, w5, asr #29 - 40: 8aa697da bic x26, x30, x6, asr #37 - 44: aa6d7423 orn x3, x1, x13, lsr #29 - 48: ca29bf80 eon x0, x28, x9, lsl #47 - 4c: ea3cb8bd bics x29, x5, x28, lsl #46 - 50: 0a675249 bic w9, w18, w7, lsr #20 - 54: 2ab961ba orn w26, w13, w25, asr #24 - 58: 4a331899 eon w25, w4, w19, lsl #6 - 5c: 6a646345 bics w5, w26, w4, lsr #24 - 60: 11055267 add w7, w19, #0x154 - 64: 31064408 adds w8, w0, #0x191 - 68: 51028e9d sub w29, w20, #0xa3 - 6c: 710bdee8 subs w8, w23, #0x2f7 - 70: 91082d81 add x1, x12, #0x20b - 74: b106a962 adds x2, x11, #0x1aa - 78: d10b33ae sub x14, x29, #0x2cc - 7c: f10918ab subs x11, x5, #0x246 - 80: 121102d7 and w23, w22, #0x8000 - 84: 3204cd44 orr w4, w10, #0xf0f0f0f0 - 88: 5204cf00 eor w0, w24, #0xf0f0f0f0 - 8c: 72099fb3 ands w19, w29, #0x7f807f80 - 90: 92729545 and x5, x10, #0xfffffffffc000 - 94: b20e37cc orr x12, x30, #0xfffc0000fffc0000 - 98: d27c34be eor x30, x5, #0x3fff0 - 9c: f27e4efa ands x26, x23, #0x3ffffc - a0: 14000000 b a0 <back+0xa0> - a4: 17ffffd7 b 0 <back> - a8: 1400017f b 6a4 <forth> - ac: 94000000 bl ac <back+0xac> - b0: 97ffffd4 bl 0 <back> - b4: 9400017c bl 6a4 <forth> - b8: 3400000c cbz w12, b8 <back+0xb8> - bc: 34fffa2c cbz w12, 0 <back> - c0: 34002f2c cbz w12, 6a4 <forth> - c4: 35000014 cbnz w20, c4 <back+0xc4> - c8: 35fff9d4 cbnz w20, 0 <back> - cc: 35002ed4 cbnz w20, 6a4 <forth> - d0: b400000c cbz x12, d0 <back+0xd0> - d4: b4fff96c cbz x12, 0 <back> - d8: b4002e6c cbz x12, 6a4 <forth> - dc: b5000018 cbnz x24, dc <back+0xdc> - e0: b5fff918 cbnz x24, 0 <back> - e4: b5002e18 cbnz x24, 6a4 <forth> - e8: 10000006 adr x6, e8 <back+0xe8> - ec: 10fff8a6 adr x6, 0 <back> - f0: 10002da6 adr x6, 6a4 <forth> - f4: 90000015 adrp x21, 0 <back> - f8: 36080001 tbz w1, #1, f8 <back+0xf8> - fc: 360ff821 tbz w1, #1, 0 <back> - 100: 36082d21 tbz w1, #1, 6a4 <forth> - 104: 37480008 tbnz w8, #9, 104 <back+0x104> - 108: 374ff7c8 tbnz w8, #9, 0 <back> - 10c: 37482cc8 tbnz w8, #9, 6a4 <forth> - 110: 128b50ec movn w12, #0x5a87 - 114: 52a9ff8b movz w11, #0x4ffc, lsl #16 - 118: 7281d095 movk w21, #0xe84 - 11c: 92edfebd movn x29, #0x6ff5, lsl #48 - 120: d28361e3 movz x3, #0x1b0f - 124: f2a4cc96 movk x22, #0x2664, lsl #16 - 128: 9346590c sbfx x12, x8, #6, #17 - 12c: 33194f33 bfi w19, w25, #7, #20 - 130: 531d3d89 ubfiz w9, w12, #3, #16 - 134: 9350433c sbfx x28, x25, #16, #1 - 138: b34464ac bfxil x12, x5, #4, #22 - 13c: d3462140 ubfx x0, x10, #6, #3 - 140: 139a61a4 extr w4, w13, w26, #24 - 144: 93d87fd7 extr x23, x30, x24, #31 - 148: 54000000 b.eq 148 <back+0x148> - 14c: 54fff5a0 b.eq 0 <back> - 150: 54002aa0 b.eq 6a4 <forth> - 154: 54000001 b.ne 154 <back+0x154> - 158: 54fff541 b.ne 0 <back> - 15c: 54002a41 b.ne 6a4 <forth> - 160: 54000002 b.cs 160 <back+0x160> - 164: 54fff4e2 b.cs 0 <back> - 168: 540029e2 b.cs 6a4 <forth> - 16c: 54000002 b.cs 16c <back+0x16c> - 170: 54fff482 b.cs 0 <back> - 174: 54002982 b.cs 6a4 <forth> - 178: 54000003 b.cc 178 <back+0x178> - 17c: 54fff423 b.cc 0 <back> - 180: 54002923 b.cc 6a4 <forth> - 184: 54000003 b.cc 184 <back+0x184> - 188: 54fff3c3 b.cc 0 <back> - 18c: 540028c3 b.cc 6a4 <forth> - 190: 54000004 b.mi 190 <back+0x190> - 194: 54fff364 b.mi 0 <back> - 198: 54002864 b.mi 6a4 <forth> - 19c: 54000005 b.pl 19c <back+0x19c> - 1a0: 54fff305 b.pl 0 <back> - 1a4: 54002805 b.pl 6a4 <forth> - 1a8: 54000006 b.vs 1a8 <back+0x1a8> - 1ac: 54fff2a6 b.vs 0 <back> - 1b0: 540027a6 b.vs 6a4 <forth> - 1b4: 54000007 b.vc 1b4 <back+0x1b4> - 1b8: 54fff247 b.vc 0 <back> - 1bc: 54002747 b.vc 6a4 <forth> - 1c0: 54000008 b.hi 1c0 <back+0x1c0> - 1c4: 54fff1e8 b.hi 0 <back> - 1c8: 540026e8 b.hi 6a4 <forth> - 1cc: 54000009 b.ls 1cc <back+0x1cc> - 1d0: 54fff189 b.ls 0 <back> - 1d4: 54002689 b.ls 6a4 <forth> - 1d8: 5400000a b.ge 1d8 <back+0x1d8> - 1dc: 54fff12a b.ge 0 <back> - 1e0: 5400262a b.ge 6a4 <forth> - 1e4: 5400000b b.lt 1e4 <back+0x1e4> - 1e8: 54fff0cb b.lt 0 <back> - 1ec: 540025cb b.lt 6a4 <forth> - 1f0: 5400000c b.gt 1f0 <back+0x1f0> - 1f4: 54fff06c b.gt 0 <back> - 1f8: 5400256c b.gt 6a4 <forth> - 1fc: 5400000d b.le 1fc <back+0x1fc> - 200: 54fff00d b.le 0 <back> - 204: 5400250d b.le 6a4 <forth> - 208: 5400000e b.al 208 <back+0x208> - 20c: 54ffefae b.al 0 <back> - 210: 540024ae b.al 6a4 <forth> - 214: 5400000f b.nv 214 <back+0x214> - 218: 54ffef4f b.nv 0 <back> - 21c: 5400244f b.nv 6a4 <forth> - 220: d4063721 svc #0x31b9 - 224: d4035082 hvc #0x1a84 - 228: d400bfe3 smc #0x5ff - 22c: d4282fc0 brk #0x417e - 230: d444c320 hlt #0x2619 - 234: d503201f nop - 238: d69f03e0 eret - 23c: d6bf03e0 drps - 240: d5033fdf isb - 244: d5033f9f dsb sy - 248: d5033abf dmb ishst - 24c: d61f0040 br x2 - 250: d63f00a0 blr x5 - 254: c8147c55 stxr w20, x21, [x2] - 258: c805fcfd stlxr w5, x29, [x7] - 25c: c85f7e05 ldxr x5, [x16] - 260: c85fffbb ldaxr x27, [x29] - 264: c89fffa0 stlr x0, [x29] - 268: c8dfff95 ldar x21, [x28] - 26c: 88157cf8 stxr w21, w24, [x7] - 270: 8815ff9a stlxr w21, w26, [x28] - 274: 885f7cd5 ldxr w21, [x6] - 278: 885fffcf ldaxr w15, [x30] - 27c: 889ffc73 stlr w19, [x3] - 280: 88dffc56 ldar w22, [x2] - 284: 48127c0f stxrh w18, w15, [x0] - 288: 480bff85 stlxrh w11, w5, [x28] - 28c: 485f7cdd ldxrh w29, [x6] - 290: 485ffcf2 ldaxrh w18, [x7] - 294: 489fff99 stlrh w25, [x28] - 298: 48dffe62 ldarh w2, [x19] - 29c: 080a7c3e stxrb w10, w30, [x1] - 2a0: 0814fed5 stlxrb w20, w21, [x22] - 2a4: 085f7c59 ldxrb w25, [x2] - 2a8: 085ffcb8 ldaxrb w24, [x5] - 2ac: 089ffc70 stlrb w16, [x3] - 2b0: 08dfffb6 ldarb w22, [x29] - 2b4: c87f0a68 ldxp x8, x2, [x19] - 2b8: c87fcdc7 ldaxp x7, x19, [x14] - 2bc: c82870bb stxp w8, x27, x28, [x5] - 2c0: c825b8c8 stlxp w5, x8, x14, [x6] - 2c4: 887f12d9 ldxp w25, w4, [x22] - 2c8: 887fb9ed ldaxp w13, w14, [x15] - 2cc: 8834215a stxp w20, w26, w8, [x10] - 2d0: 8837ca52 stlxp w23, w18, w18, [x18] - 2d4: f806317e str x30, [x11,#99] - 2d8: b81b3337 str w23, [x25,#-77] - 2dc: 39000dc2 strb w2, [x14,#3] - 2e0: 78005149 strh w9, [x10,#5] - 2e4: f84391f4 ldr x20, [x15,#57] - 2e8: b85b220c ldr w12, [x16,#-78] - 2ec: 385fd356 ldrb w22, [x26,#-3] - 2f0: 785d127e ldrh w30, [x19,#-47] - 2f4: 389f4149 ldrsb x9, [x10,#-12] - 2f8: 79801e3c ldrsh x28, [x17,#14] - 2fc: 79c014a3 ldrsh w3, [x5,#10] - 300: b89a5231 ldrsw x17, [x17,#-91] - 304: fc5ef282 ldr d2, [x20,#-17] - 308: bc5f60f6 ldr s22, [x7,#-10] - 30c: fc12125e str d30, [x18,#-223] - 310: bc0152cd str s13, [x22,#21] - 314: f8190e49 str x9, [x18,#-112]! - 318: b800befd str w29, [x23,#11]! - 31c: 381ffd92 strb w18, [x12,#-1]! - 320: 781e9e90 strh w16, [x20,#-23]! - 324: f8409fa3 ldr x3, [x29,#9]! - 328: b8413c79 ldr w25, [x3,#19]! - 32c: 385fffa1 ldrb w1, [x29,#-1]! - 330: 785c7fa8 ldrh w8, [x29,#-57]! - 334: 389f3dc5 ldrsb x5, [x14,#-13]! - 338: 78801f6a ldrsh x10, [x27,#1]! - 33c: 78c19d4b ldrsh w11, [x10,#25]! - 340: b89a4ec4 ldrsw x4, [x22,#-92]! - 344: fc408eeb ldr d11, [x23,#8]! - 348: bc436e79 ldr s25, [x19,#54]! - 34c: fc152ce1 str d1, [x7,#-174]! - 350: bc036f28 str s8, [x25,#54]! - 354: f8025565 str x5, [x11],#37 - 358: b80135f8 str w24, [x15],#19 - 35c: 381ff74f strb w15, [x26],#-1 - 360: 781fa652 strh w18, [x18],#-6 - 364: f851a447 ldr x7, [x2],#-230 - 368: b85e557b ldr w27, [x11],#-27 - 36c: 385e7472 ldrb w18, [x3],#-25 - 370: 785e070a ldrh w10, [x24],#-32 - 374: 38804556 ldrsb x22, [x10],#4 - 378: 78819591 ldrsh x17, [x12],#25 - 37c: 78dc24e8 ldrsh w8, [x7],#-62 - 380: b89cd6d7 ldrsw x23, [x22],#-51 - 384: fc430738 ldr d24, [x25],#48 - 388: bc5f6595 ldr s21, [x12],#-10 - 38c: fc1225b2 str d18, [x13],#-222 - 390: bc1d7430 str s16, [x1],#-41 - 394: f82fcac2 str x2, [x22,w15,sxtw] - 398: b83d6a02 str w2, [x16,x29] - 39c: 382e5a54 strb w20, [x18,w14,uxtw #0] - 3a0: 7834fa66 strh w6, [x19,x20,sxtx #1] - 3a4: f86ecbae ldr x14, [x29,w14,sxtw] - 3a8: b86cda90 ldr w16, [x20,w12,sxtw #2] - 3ac: 3860d989 ldrb w9, [x12,w0,sxtw #0] - 3b0: 78637a2c ldrh w12, [x17,x3,lsl #1] - 3b4: 38a3fa22 ldrsb x2, [x17,x3,sxtx #0] - 3b8: 78b15827 ldrsh x7, [x1,w17,uxtw #1] - 3bc: 78f2d9f9 ldrsh w25, [x15,w18,sxtw #1] - 3c0: b8ac6ab7 ldrsw x23, [x21,x12] - 3c4: fc6879a5 ldr d5, [x13,x8,lsl #3] - 3c8: bc767943 ldr s3, [x10,x22,lsl #2] - 3cc: fc3bc84e str d14, [x2,w27,sxtw] - 3d0: bc3968d4 str s20, [x6,x25] - 3d4: f91fc0fe str x30, [x7,#16256] - 3d8: b91da50f str w15, [x8,#7588] - 3dc: 391d280b strb w11, [x0,#1866] - 3e0: 791d2e23 strh w3, [x17,#3734] - 3e4: f95bc8e2 ldr x2, [x7,#14224] - 3e8: b95ce525 ldr w5, [x9,#7396] - 3ec: 395ae53c ldrb w28, [x9,#1721] - 3f0: 795c9282 ldrh w2, [x20,#3656] - 3f4: 399d7dd6 ldrsb x22, [x14,#1887] - 3f8: 799fe008 ldrsh x8, [x0,#4080] - 3fc: 79de9bc0 ldrsh w0, [x30,#3916] - 400: b99aae78 ldrsw x24, [x19,#6828] - 404: fd597598 ldr d24, [x12,#13032] - 408: bd5d1d08 ldr s8, [x8,#7452] - 40c: fd1f3dea str d10, [x15,#15992] - 410: bd1a227a str s26, [x19,#6688] - 414: 5800148a ldr x10, 6a4 <forth> - 418: 18000003 ldr w3, 418 <back+0x418> - 41c: f88092e0 prfm pldl1keep, [x23,#9] - 420: d8ffdf00 prfm pldl1keep, 0 <back> - 424: f8a84860 prfm pldl1keep, [x3,w8,uxtw] - 428: f99d7560 prfm pldl1keep, [x11,#15080] - 42c: 1a1c012d adc w13, w9, w28 - 430: 3a1c027b adcs w27, w19, w28 - 434: 5a060253 sbc w19, w18, w6 - 438: 7a03028e sbcs w14, w20, w3 - 43c: 9a0801d0 adc x16, x14, x8 - 440: ba0803a0 adcs x0, x29, x8 - 444: da140308 sbc x8, x24, x20 - 448: fa00038c sbcs x12, x28, x0 - 44c: 0b3010d7 add w23, w6, w16, uxtb #4 - 450: 2b37ab39 adds w25, w25, w23, sxth #2 - 454: cb2466da sub x26, x22, x4, uxtx #1 - 458: 6b33efb1 subs w17, w29, w19, sxtx #3 - 45c: 8b350fcb add x11, x30, w21, uxtb #3 - 460: ab208a70 adds x16, x19, w0, sxtb #2 - 464: cb39e52b sub x11, x9, x25, sxtx #1 - 468: eb2c9291 subs x17, x20, w12, sxtb #4 - 46c: 3a4bd1a3 ccmn w13, w11, #0x3, le - 470: 7a4c81a2 ccmp w13, w12, #0x2, hi - 474: ba42106c ccmn x3, x2, #0xc, ne - 478: fa5560e3 ccmp x7, x21, #0x3, vs - 47c: 3a4e3844 ccmn w2, #0xe, #0x4, cc - 480: 7a515a26 ccmp w17, #0x11, #0x6, pl - 484: ba4c2940 ccmn x10, #0xc, #0x0, cs - 488: fa52aaae ccmp x21, #0x12, #0xe, ge - 48c: 1a8cc1b5 csel w21, w13, w12, gt - 490: 1a8f976a csinc w10, w27, w15, ls - 494: 5a8981a0 csinv w0, w13, w9, hi - 498: 5a9a6492 csneg w18, w4, w26, vs - 49c: 9a8793ac csel x12, x29, x7, ls - 4a0: 9a9474e6 csinc x6, x7, x20, vc - 4a4: da83d2b6 csinv x22, x21, x3, le - 4a8: da9b9593 csneg x19, x12, x27, ls - 4ac: 5ac00200 rbit w0, w16 - 4b0: 5ac006f1 rev16 w17, w23 - 4b4: 5ac009d1 rev w17, w14 - 4b8: 5ac013d8 clz w24, w30 - 4bc: 5ac016d8 cls w24, w22 - 4c0: dac00223 rbit x3, x17 - 4c4: dac005ac rev16 x12, x13 - 4c8: dac00ac9 rev32 x9, x22 - 4cc: dac00c00 rev x0, x0 - 4d0: dac01205 clz x5, x16 - 4d4: dac016d9 cls x25, x22 - 4d8: 1ac0089d udiv w29, w4, w0 - 4dc: 1add0fa0 sdiv w0, w29, w29 - 4e0: 1ad52225 lsl w5, w17, w21 - 4e4: 1ad22529 lsr w9, w9, w18 - 4e8: 1ac82b61 asr w1, w27, w8 - 4ec: 1acd2e92 ror w18, w20, w13 - 4f0: 9acc0b28 udiv x8, x25, x12 - 4f4: 9adc0ca7 sdiv x7, x5, x28 - 4f8: 9adb2225 lsl x5, x17, x27 - 4fc: 9ad42757 lsr x23, x26, x20 - 500: 9adc291c asr x28, x8, x28 - 504: 9ac42fa3 ror x3, x29, x4 - 508: 1b1a55d1 madd w17, w14, w26, w21 - 50c: 1b0bafc1 msub w1, w30, w11, w11 - 510: 9b067221 madd x1, x17, x6, x28 - 514: 9b1ea0de msub x30, x6, x30, x8 - 518: 9b2e20d5 smaddl x21, w6, w14, x8 - 51c: 9b38cd4a smsubl x10, w10, w24, x19 - 520: 9bae6254 umaddl x20, w18, w14, x24 - 524: 9ba59452 umsubl x18, w2, w5, x5 - 528: 1e2d0a48 fmul s8, s18, s13 - 52c: 1e3c19c2 fdiv s2, s14, s28 - 530: 1e3c298f fadd s15, s12, s28 - 534: 1e213980 fsub s0, s12, s1 - 538: 1e240baf fmul s15, s29, s4 - 53c: 1e77082c fmul d12, d1, d23 - 540: 1e72191b fdiv d27, d8, d18 - 544: 1e6b2a97 fadd d23, d20, d11 - 548: 1e723988 fsub d8, d12, d18 - 54c: 1e770b1a fmul d26, d24, d23 - 550: 1f0d66f5 fmadd s21, s23, s13, s25 - 554: 1f01b956 fmsub s22, s10, s1, s14 - 558: 1f227a8e fnmadd s14, s20, s2, s30 - 55c: 1f365ba7 fnmadd s7, s29, s22, s22 - 560: 1f4f14ad fmadd d13, d5, d15, d5 - 564: 1f45a98e fmsub d14, d12, d5, d10 - 568: 1f60066a fnmadd d10, d19, d0, d1 - 56c: 1f620054 fnmadd d20, d2, d2, d0 - 570: 1e204139 fmov s25, s9 - 574: 1e20c094 fabs s20, s4 - 578: 1e214363 fneg s3, s27 - 57c: 1e21c041 fsqrt s1, s2 - 580: 1e22c01e fcvt d30, s0 - 584: 1e60408c fmov d12, d4 - 588: 1e60c361 fabs d1, d27 - 58c: 1e6142c8 fneg d8, d22 - 590: 1e61c16b fsqrt d11, d11 - 594: 1e624396 fcvt s22, d28 - 598: 1e3802dc fcvtzs w28, s22 - 59c: 9e380374 fcvtzs x20, s27 - 5a0: 1e78000e fcvtzs w14, d0 - 5a4: 9e78017a fcvtzs x26, d11 - 5a8: 1e2202dc scvtf s28, w22 - 5ac: 9e220150 scvtf s16, x10 - 5b0: 1e6202a8 scvtf d8, w21 - 5b4: 9e620395 scvtf d21, x28 - 5b8: 1e260318 fmov w24, s24 - 5bc: 9e660268 fmov x8, d19 - 5c0: 1e270188 fmov s8, w12 - 5c4: 9e6700e6 fmov d6, x7 - 5c8: 1e3023c0 fcmp s30, s16 - 5cc: 1e6b2320 fcmp d25, d11 - 5d0: 1e202168 fcmp s11, #0.0 - 5d4: 1e602168 fcmp d11, #0.0 - 5d8: 2910323d stp w29, w12, [x17,#128] - 5dc: 297449d6 ldp w22, w18, [x14,#-96] - 5e0: 6948402b ldpsw x11, x16, [x1,#64] - 5e4: a9072f40 stp x0, x11, [x26,#112] - 5e8: a9410747 ldp x7, x1, [x26,#16] - 5ec: 29801f0a stp w10, w7, [x24,#0]! - 5f0: 29e07307 ldp w7, w28, [x24,#-256]! - 5f4: 69e272b9 ldpsw x25, x28, [x21,#-240]! - 5f8: a9bf49d4 stp x20, x18, [x14,#-16]! - 5fc: a9c529a8 ldp x8, x10, [x13,#80]! - 600: 28b0605a stp w26, w24, [x2],#-128 - 604: 28e866a2 ldp w2, w25, [x21],#-192 - 608: 68ee0ab1 ldpsw x17, x2, [x21],#-144 - 60c: a886296c stp x12, x10, [x11],#96 - 610: a8fe1a38 ldp x24, x6, [x17],#-32 - 614: 282479c3 stnp w3, w30, [x14,#-224] - 618: 286e534f ldnp w15, w20, [x26,#-144] - 61c: a8386596 stnp x22, x25, [x12,#-128] - 620: a8755a3b ldnp x27, x22, [x17,#-176] - 624: 1e601000 fmov d0, #2.000000000000000000e+00 - 628: 1e603000 fmov d0, #2.125000000000000000e+00 - 62c: 1e621000 fmov d0, #4.000000000000000000e+00 - 630: 1e623000 fmov d0, #4.250000000000000000e+00 - 634: 1e641000 fmov d0, #8.000000000000000000e+00 - 638: 1e643000 fmov d0, #8.500000000000000000e+00 - 63c: 1e661000 fmov d0, #1.600000000000000000e+01 - 640: 1e663000 fmov d0, #1.700000000000000000e+01 - 644: 1e681000 fmov d0, #1.250000000000000000e-01 - 648: 1e683000 fmov d0, #1.328125000000000000e-01 - 64c: 1e6a1000 fmov d0, #2.500000000000000000e-01 - 650: 1e6a3000 fmov d0, #2.656250000000000000e-01 - 654: 1e6c1000 fmov d0, #5.000000000000000000e-01 - 658: 1e6c3000 fmov d0, #5.312500000000000000e-01 - 65c: 1e6e1000 fmov d0, #1.000000000000000000e+00 - 660: 1e6e3000 fmov d0, #1.062500000000000000e+00 - 664: 1e701000 fmov d0, #-2.000000000000000000e+00 - 668: 1e703000 fmov d0, #-2.125000000000000000e+00 - 66c: 1e721000 fmov d0, #-4.000000000000000000e+00 - 670: 1e723000 fmov d0, #-4.250000000000000000e+00 - 674: 1e741000 fmov d0, #-8.000000000000000000e+00 - 678: 1e743000 fmov d0, #-8.500000000000000000e+00 - 67c: 1e761000 fmov d0, #-1.600000000000000000e+01 - 680: 1e763000 fmov d0, #-1.700000000000000000e+01 - 684: 1e781000 fmov d0, #-1.250000000000000000e-01 - 688: 1e783000 fmov d0, #-1.328125000000000000e-01 - 68c: 1e7a1000 fmov d0, #-2.500000000000000000e-01 - 690: 1e7a3000 fmov d0, #-2.656250000000000000e-01 - 694: 1e7c1000 fmov d0, #-5.000000000000000000e-01 - 698: 1e7c3000 fmov d0, #-5.312500000000000000e-01 - 69c: 1e7e1000 fmov d0, #-1.000000000000000000e+00 - 6a0: 1e7e3000 fmov d0, #-1.062500000000000000e+00 + 0: 8b50798f add x15, x12, x16, lsr #30 + 4: cb4381e1 sub x1, x15, x3, lsr #32 + 8: ab05372d adds x13, x25, x5, lsl #13 + c: eb864796 subs x22, x28, x6, asr #17 + 10: 0b961920 add w0, w9, w22, asr #6 + 14: 4b195473 sub w19, w3, w25, lsl #21 + 18: 2b0b5264 adds w4, w19, w11, lsl #20 + 1c: 6b9300f8 subs w24, w7, w19, asr #0 + 20: 8a0bc0fe and x30, x7, x11, lsl #48 + 24: aa0f3118 orr x24, x8, x15, lsl #12 + 28: ca170531 eor x17, x9, x23, lsl #1 + 2c: ea44dd6e ands x14, x11, x4, lsr #55 + 30: 0a4c44f3 and w19, w7, w12, lsr #17 + 34: 2a8b7373 orr w19, w27, w11, asr #28 + 38: 4a567c7e eor w30, w3, w22, lsr #31 + 3c: 6a9c0353 ands w19, w26, w28, asr #0 + 40: 8a3accdd bic x29, x6, x26, lsl #51 + 44: aa318f7a orn x26, x27, x17, lsl #35 + 48: ca2e1495 eon x21, x4, x14, lsl #5 + 4c: eaa015e2 bics x2, x15, x0, asr #5 + 50: 0a2274e2 bic w2, w7, w2, lsl #29 + 54: 2a751598 orn w24, w12, w21, lsr #5 + 58: 4a3309fe eon w30, w15, w19, lsl #2 + 5c: 6ab172fe bics w30, w23, w17, asr #28 + 60: 110a5284 add w4, w20, #0x294 + 64: 310b1942 adds w2, w10, #0x2c6 + 68: 5103d353 sub w19, w26, #0xf4 + 6c: 710125bc subs w28, w13, #0x49 + 70: 910d7bc2 add x2, x30, #0x35e + 74: b108fa1b adds x27, x16, #0x23e + 78: d1093536 sub x22, x9, #0x24d + 7c: f10ae824 subs x4, x1, #0x2ba + 80: 120e667c and w28, w19, #0xfffc0fff + 84: 321f6cbb orr w27, w5, #0x1ffffffe + 88: 520f6a9e eor w30, w20, #0xfffe0fff + 8c: 72136f56 ands w22, w26, #0xffffe1ff + 90: 927e4ce5 and x5, x7, #0x3ffffc + 94: b278b4ed orr x13, x7, #0x3fffffffffff00 + 98: d24c6527 eor x7, x9, #0xfff0000000003fff + 9c: f2485803 ands x3, x0, #0xff00000000007fff + a0: 14000000 b a0 <back+0xa0> + a4: 17ffffd7 b 0 <back> + a8: 140001ee b 860 <forth> + ac: 94000000 bl ac <back+0xac> + b0: 97ffffd4 bl 0 <back> + b4: 940001eb bl 860 <forth> + b8: 34000010 cbz w16, b8 <back+0xb8> + bc: 34fffa30 cbz w16, 0 <back> + c0: 34003d10 cbz w16, 860 <forth> + c4: 35000013 cbnz w19, c4 <back+0xc4> + c8: 35fff9d3 cbnz w19, 0 <back> + cc: 35003cb3 cbnz w19, 860 <forth> + d0: b4000005 cbz x5, d0 <back+0xd0> + d4: b4fff965 cbz x5, 0 <back> + d8: b4003c45 cbz x5, 860 <forth> + dc: b5000004 cbnz x4, dc <back+0xdc> + e0: b5fff904 cbnz x4, 0 <back> + e4: b5003be4 cbnz x4, 860 <forth> + e8: 1000001b adr x27, e8 <back+0xe8> + ec: 10fff8bb adr x27, 0 <back> + f0: 10003b9b adr x27, 860 <forth> + f4: 90000010 adrp x16, 0 <back> + f8: 3640001c tbz w28, #8, f8 <back+0xf8> + fc: 3647f83c tbz w28, #8, 0 <back> + 100: 36403b1c tbz w28, #8, 860 <forth> + 104: 37080001 tbnz w1, #1, 104 <back+0x104> + 108: 370ff7c1 tbnz w1, #1, 0 <back> + 10c: 37083aa1 tbnz w1, #1, 860 <forth> + 110: 12a437f4 mov w20, #0xde40ffff // #-566165505 + 114: 528c9d67 mov w7, #0x64eb // #25835 + 118: 72838bb1 movk w17, #0x1c5d + 11c: 92c1062e mov x14, #0xfffff7ceffffffff // #-9006546419713 + 120: d287da49 mov x9, #0x3ed2 // #16082 + 124: f2a6d153 movk x19, #0x368a, lsl #16 + 128: 93465ac9 sbfx x9, x22, #6, #17 + 12c: 330b0013 bfi w19, w0, #21, #1 + 130: 530b4e6a ubfx w10, w19, #11, #9 + 134: 934545e4 sbfx x4, x15, #5, #13 + 138: b35370a3 bfxil x3, x5, #19, #10 + 13c: d3510b8c ubfiz x12, x28, #47, #3 + 140: 13960c0f extr w15, w0, w22, #3 + 144: 93ceddc6 ror x6, x14, #55 + 148: 54000000 b.eq 148 <back+0x148> // b.none + 14c: 54fff5a0 b.eq 0 <back> // b.none + 150: 54003880 b.eq 860 <forth> // b.none + 154: 54000001 b.ne 154 <back+0x154> // b.any + 158: 54fff541 b.ne 0 <back> // b.any + 15c: 54003821 b.ne 860 <forth> // b.any + 160: 54000002 b.cs 160 <back+0x160> // b.hs, b.nlast + 164: 54fff4e2 b.cs 0 <back> // b.hs, b.nlast + 168: 540037c2 b.cs 860 <forth> // b.hs, b.nlast + 16c: 54000002 b.cs 16c <back+0x16c> // b.hs, b.nlast + 170: 54fff482 b.cs 0 <back> // b.hs, b.nlast + 174: 54003762 b.cs 860 <forth> // b.hs, b.nlast + 178: 54000003 b.cc 178 <back+0x178> // b.lo, b.ul, b.last + 17c: 54fff423 b.cc 0 <back> // b.lo, b.ul, b.last + 180: 54003703 b.cc 860 <forth> // b.lo, b.ul, b.last + 184: 54000003 b.cc 184 <back+0x184> // b.lo, b.ul, b.last + 188: 54fff3c3 b.cc 0 <back> // b.lo, b.ul, b.last + 18c: 540036a3 b.cc 860 <forth> // b.lo, b.ul, b.last + 190: 54000004 b.mi 190 <back+0x190> // b.first + 194: 54fff364 b.mi 0 <back> // b.first + 198: 54003644 b.mi 860 <forth> // b.first + 19c: 54000005 b.pl 19c <back+0x19c> // b.nfrst + 1a0: 54fff305 b.pl 0 <back> // b.nfrst + 1a4: 540035e5 b.pl 860 <forth> // b.nfrst + 1a8: 54000006 b.vs 1a8 <back+0x1a8> + 1ac: 54fff2a6 b.vs 0 <back> + 1b0: 54003586 b.vs 860 <forth> + 1b4: 54000007 b.vc 1b4 <back+0x1b4> + 1b8: 54fff247 b.vc 0 <back> + 1bc: 54003527 b.vc 860 <forth> + 1c0: 54000008 b.hi 1c0 <back+0x1c0> // b.pmore + 1c4: 54fff1e8 b.hi 0 <back> // b.pmore + 1c8: 540034c8 b.hi 860 <forth> // b.pmore + 1cc: 54000009 b.ls 1cc <back+0x1cc> // b.plast + 1d0: 54fff189 b.ls 0 <back> // b.plast + 1d4: 54003469 b.ls 860 <forth> // b.plast + 1d8: 5400000a b.ge 1d8 <back+0x1d8> // b.tcont + 1dc: 54fff12a b.ge 0 <back> // b.tcont + 1e0: 5400340a b.ge 860 <forth> // b.tcont + 1e4: 5400000b b.lt 1e4 <back+0x1e4> // b.tstop + 1e8: 54fff0cb b.lt 0 <back> // b.tstop + 1ec: 540033ab b.lt 860 <forth> // b.tstop + 1f0: 5400000c b.gt 1f0 <back+0x1f0> + 1f4: 54fff06c b.gt 0 <back> + 1f8: 5400334c b.gt 860 <forth> + 1fc: 5400000d b.le 1fc <back+0x1fc> + 200: 54fff00d b.le 0 <back> + 204: 540032ed b.le 860 <forth> + 208: 5400000e b.al 208 <back+0x208> + 20c: 54ffefae b.al 0 <back> + 210: 5400328e b.al 860 <forth> + 214: 5400000f b.nv 214 <back+0x214> + 218: 54ffef4f b.nv 0 <back> + 21c: 5400322f b.nv 860 <forth> + 220: d40ac601 svc #0x5630 + 224: d40042a2 hvc #0x215 + 228: d404dac3 smc #0x26d6 + 22c: d4224d40 brk #0x126a + 230: d44219c0 hlt #0x10ce + 234: d503201f nop + 238: d69f03e0 eret + 23c: d6bf03e0 drps + 240: d5033fdf isb + 244: d503339f dsb osh + 248: d50335bf dmb nshld + 24c: d61f0280 br x20 + 250: d63f0040 blr x2 + 254: c8127c17 stxr w18, x23, [x0] + 258: c81efec5 stlxr w30, x5, [x22] + 25c: c85f7d05 ldxr x5, [x8] + 260: c85ffe14 ldaxr x20, [x16] + 264: c89ffd66 stlr x6, [x11] + 268: c8dfff66 ldar x6, [x27] + 26c: 880a7cb1 stxr w10, w17, [x5] + 270: 8816fd89 stlxr w22, w9, [x12] + 274: 885f7d1b ldxr w27, [x8] + 278: 885ffc57 ldaxr w23, [x2] + 27c: 889fffba stlr w26, [x29] + 280: 88dffd4d ldar w13, [x10] + 284: 48197f7c stxrh w25, w28, [x27] + 288: 481dfd96 stlxrh w29, w22, [x12] + 28c: 485f7f96 ldxrh w22, [x28] + 290: 485fffc3 ldaxrh w3, [x30] + 294: 489ffdf8 stlrh w24, [x15] + 298: 48dfff5b ldarh w27, [x26] + 29c: 080b7e6a stxrb w11, w10, [x19] + 2a0: 0817fedb stlxrb w23, w27, [x22] + 2a4: 085f7e18 ldxrb w24, [x16] + 2a8: 085ffc38 ldaxrb w24, [x1] + 2ac: 089fffa5 stlrb w5, [x29] + 2b0: 08dffe18 ldarb w24, [x16] + 2b4: c87f6239 ldxp x25, x24, [x17] + 2b8: c87fb276 ldaxp x22, x12, [x19] + 2bc: c820573a stxp w0, x26, x21, [x25] + 2c0: c821aca6 stlxp w1, x6, x11, [x5] + 2c4: 887f388d ldxp w13, w14, [x4] + 2c8: 887f88d1 ldaxp w17, w2, [x6] + 2cc: 882f2643 stxp w15, w3, w9, [x18] + 2d0: 88329131 stlxp w18, w17, w4, [x9] + 2d4: f81cf2b7 stur x23, [x21, #-49] + 2d8: b803f055 stur w21, [x2, #63] + 2dc: 39002f9b strb w27, [x28, #11] + 2e0: 781f31fd sturh w29, [x15, #-13] + 2e4: f85d33ce ldur x14, [x30, #-45] + 2e8: b843539d ldur w29, [x28, #53] + 2ec: 39401f54 ldrb w20, [x26, #7] + 2f0: 785ce059 ldurh w25, [x2, #-50] + 2f4: 389f1143 ldursb x3, [x10, #-15] + 2f8: 788131ee ldursh x14, [x15, #19] + 2fc: 78dfb17d ldursh w29, [x11, #-5] + 300: b89b90af ldursw x15, [x5, #-71] + 304: fc403193 ldur d19, [x12, #3] + 308: bc42a36c ldur s12, [x27, #42] + 30c: fc07d396 stur d22, [x28, #125] + 310: bc1ec1f8 stur s24, [x15, #-20] + 314: f81e8f88 str x8, [x28, #-24]! + 318: b8025de6 str w6, [x15, #37]! + 31c: 38007c27 strb w7, [x1, #7]! + 320: 7801ee20 strh w0, [x17, #30]! + 324: f8454fb9 ldr x25, [x29, #84]! + 328: b85cce9a ldr w26, [x20, #-52]! + 32c: 385e7fba ldrb w26, [x29, #-25]! + 330: 7841af24 ldrh w4, [x25, #26]! + 334: 389ebd1c ldrsb x28, [x8, #-21]! + 338: 789fadd1 ldrsh x17, [x14, #-6]! + 33c: 78c0aefc ldrsh w28, [x23, #10]! + 340: b89c0f7e ldrsw x30, [x27, #-64]! + 344: fc50efd4 ldr d20, [x30, #-242]! + 348: bc414f71 ldr s17, [x27, #20]! + 34c: fc011c67 str d7, [x3, #17]! + 350: bc1f0d6d str s13, [x11, #-16]! + 354: f81c3526 str x6, [x9], #-61 + 358: b81e34b0 str w16, [x5], #-29 + 35c: 3800f7bd strb w29, [x29], #15 + 360: 78012684 strh w4, [x20], #18 + 364: f842e653 ldr x19, [x18], #46 + 368: b8417456 ldr w22, [x2], #23 + 36c: 385e2467 ldrb w7, [x3], #-30 + 370: 785e358b ldrh w11, [x12], #-29 + 374: 389e34c8 ldrsb x8, [x6], #-29 + 378: 788046f8 ldrsh x24, [x23], #4 + 37c: 78c00611 ldrsh w17, [x16], #0 + 380: b89f8680 ldrsw x0, [x20], #-8 + 384: fc582454 ldr d20, [x2], #-126 + 388: bc5987d3 ldr s19, [x30], #-104 + 38c: fc076624 str d4, [x17], #118 + 390: bc190675 str s21, [x19], #-112 + 394: f833785a str x26, [x2, x19, lsl #3] + 398: b82fd809 str w9, [x0, w15, sxtw #2] + 39c: 3821799a strb w26, [x12, x1, lsl #0] + 3a0: 782a7975 strh w21, [x11, x10, lsl #1] + 3a4: f870eaf0 ldr x16, [x23, x16, sxtx] + 3a8: b871d96a ldr w10, [x11, w17, sxtw #2] + 3ac: 386b7aed ldrb w13, [x23, x11, lsl #0] + 3b0: 7875689b ldrh w27, [x4, x21] + 3b4: 38afd91a ldrsb x26, [x8, w15, sxtw #0] + 3b8: 78a2c955 ldrsh x21, [x10, w2, sxtw] + 3bc: 78ee6bc8 ldrsh w8, [x30, x14] + 3c0: b8b4f9dd ldrsw x29, [x14, x20, sxtx #2] + 3c4: fc76eb7e ldr d30, [x27, x22, sxtx] + 3c8: bc76692d ldr s13, [x9, x22] + 3cc: fc31db28 str d8, [x25, w17, sxtw #3] + 3d0: bc255b01 str s1, [x24, w5, uxtw #2] + 3d4: f91c52aa str x10, [x21, #14496] + 3d8: b91c3fb2 str w18, [x29, #7228] + 3dc: 391f8877 strb w23, [x3, #2018] + 3e0: 791ac97c strh w28, [x11, #3428] + 3e4: f95c1758 ldr x24, [x26, #14376] + 3e8: b95b3c55 ldr w21, [x2, #6972] + 3ec: 395ce0a4 ldrb w4, [x5, #1848] + 3f0: 795851ce ldrh w14, [x14, #3112] + 3f4: 399e9f64 ldrsb x4, [x27, #1959] + 3f8: 79993764 ldrsh x4, [x27, #3226] + 3fc: 79d9af8a ldrsh w10, [x28, #3286] + 400: b99eea2a ldrsw x10, [x17, #7912] + 404: fd5a2f8d ldr d13, [x28, #13400] + 408: bd5dac78 ldr s24, [x3, #7596] + 40c: fd1e0182 str d2, [x12, #15360] + 410: bd195c31 str s17, [x1, #6492] + 414: 58000010 ldr x16, 414 <back+0x414> + 418: 1800000d ldr w13, 418 <back+0x418> + 41c: f8981240 prfum pldl1keep, [x18, #-127] + 420: d8ffdf00 prfm pldl1keep, 0 <back> + 424: f8a27a80 prfm pldl1keep, [x20, x2, lsl #3] + 428: f99af920 prfm pldl1keep, [x9, #13808] + 42c: 1a0202e8 adc w8, w23, w2 + 430: 3a130078 adcs w24, w3, w19 + 434: 5a1d0316 sbc w22, w24, w29 + 438: 7a03036c sbcs w12, w27, w3 + 43c: 9a0102eb adc x11, x23, x1 + 440: ba1700bd adcs x29, x5, x23 + 444: da0c0329 sbc x9, x25, x12 + 448: fa16000c sbcs x12, x0, x22 + 44c: 0b23459a add w26, w12, w3, uxtw #1 + 450: 2b328a14 adds w20, w16, w18, sxtb #2 + 454: cb274bde sub x30, x30, w7, uxtw #2 + 458: 6b222eab subs w11, w21, w2, uxth #3 + 45c: 8b214b42 add x2, x26, w1, uxtw #2 + 460: ab34a7b2 adds x18, x29, w20, sxth #1 + 464: cb24520e sub x14, x16, w4, uxtw #4 + 468: eb378e20 subs x0, x17, w23, sxtb #3 + 46c: 3a565283 ccmn w20, w22, #0x3, pl // pl = nfrst + 470: 7a420321 ccmp w25, w2, #0x1, eq // eq = none + 474: ba58c247 ccmn x18, x24, #0x7, gt + 478: fa4d5106 ccmp x8, x13, #0x6, pl // pl = nfrst + 47c: 3a426924 ccmn w9, #0x2, #0x4, vs + 480: 7a5b0847 ccmp w2, #0x1b, #0x7, eq // eq = none + 484: ba413a02 ccmn x16, #0x1, #0x2, cc // cc = lo, ul, last + 488: fa5fba23 ccmp x17, #0x1f, #0x3, lt // lt = tstop + 48c: 1a979377 csel w23, w27, w23, ls // ls = plast + 490: 1a86640a csinc w10, w0, w6, vs + 494: 5a89300b csinv w11, w0, w9, cc // cc = lo, ul, last + 498: 5a923771 csneg w17, w27, w18, cc // cc = lo, ul, last + 49c: 9a8b720c csel x12, x16, x11, vc + 4a0: 9a868786 csinc x6, x28, x6, hi // hi = pmore + 4a4: da9a736d csinv x13, x27, x26, vc + 4a8: da9256dd csneg x29, x22, x18, pl // pl = nfrst + 4ac: 5ac0026c rbit w12, w19 + 4b0: 5ac00657 rev16 w23, w18 + 4b4: 5ac00b89 rev w9, w28 + 4b8: 5ac01262 clz w2, w19 + 4bc: 5ac017b9 cls w25, w29 + 4c0: dac002e4 rbit x4, x23 + 4c4: dac0065d rev16 x29, x18 + 4c8: dac00907 rev32 x7, x8 + 4cc: dac00e2d rev x13, x17 + 4d0: dac01011 clz x17, x0 + 4d4: dac01752 cls x18, x26 + 4d8: 1ad0098b udiv w11, w12, w16 + 4dc: 1ac70d24 sdiv w4, w9, w7 + 4e0: 1ad020ec lsl w12, w7, w16 + 4e4: 1ad72613 lsr w19, w16, w23 + 4e8: 1ac62887 asr w7, w4, w6 + 4ec: 1ad72e95 ror w21, w20, w23 + 4f0: 9adc0990 udiv x16, x12, x28 + 4f4: 9acd0d84 sdiv x4, x12, x13 + 4f8: 9ac721a9 lsl x9, x13, x7 + 4fc: 9acf277c lsr x28, x27, x15 + 500: 9ace2bd4 asr x20, x30, x14 + 504: 9ade2e4e ror x14, x18, x30 + 508: 9bc77d63 umulh x3, x11, x7 + 50c: 9b587e97 smulh x23, x20, x24 + 510: 1b1524a2 madd w2, w5, w21, w9 + 514: 1b04a318 msub w24, w24, w4, w8 + 518: 9b0f4d8b madd x11, x12, x15, x19 + 51c: 9b0ce73d msub x29, x25, x12, x25 + 520: 9b2c5971 smaddl x17, w11, w12, x22 + 524: 9b34c87c smsubl x28, w3, w20, x18 + 528: 9bbc6887 umaddl x7, w4, w28, x26 + 52c: 9bb19556 umsubl x22, w10, w17, x5 + 530: 1e310871 fmul s17, s3, s17 + 534: 1e261a2b fdiv s11, s17, s6 + 538: 1e2928fd fadd s29, s7, s9 + 53c: 1e333987 fsub s7, s12, s19 + 540: 1e230ae0 fmul s0, s23, s3 + 544: 1e75087a fmul d26, d3, d21 + 548: 1e651a60 fdiv d0, d19, d5 + 54c: 1e692b40 fadd d0, d26, d9 + 550: 1e753ab9 fsub d25, d21, d21 + 554: 1e7309b0 fmul d16, d13, d19 + 558: 1f00425d fmadd s29, s18, s0, s16 + 55c: 1f1d95b7 fmsub s23, s13, s29, s5 + 560: 1f2a38e9 fnmadd s9, s7, s10, s14 + 564: 1f2f5f99 fnmadd s25, s28, s15, s23 + 568: 1f5545a6 fmadd d6, d13, d21, d17 + 56c: 1f429ea3 fmsub d3, d21, d2, d7 + 570: 1f65472a fnmadd d10, d25, d5, d17 + 574: 1f7449ce fnmadd d14, d14, d20, d18 + 578: 1e20404f fmov s15, s2 + 57c: 1e20c0f2 fabs s18, s7 + 580: 1e2140c3 fneg s3, s6 + 584: 1e21c02c fsqrt s12, s1 + 588: 1e22c009 fcvt d9, s0 + 58c: 1e6040a4 fmov d4, d5 + 590: 1e60c1e3 fabs d3, d15 + 594: 1e614331 fneg d17, d25 + 598: 1e61c30c fsqrt d12, d24 + 59c: 1e6240b5 fcvt s21, d5 + 5a0: 1e3802a4 fcvtzs w4, s21 + 5a4: 9e38007b fcvtzs x27, s3 + 5a8: 1e78011d fcvtzs w29, d8 + 5ac: 9e7802a9 fcvtzs x9, d21 + 5b0: 1e2203b4 scvtf s20, w29 + 5b4: 9e220107 scvtf s7, x8 + 5b8: 1e6202ac scvtf d12, w21 + 5bc: 9e6202b0 scvtf d16, x21 + 5c0: 1e2600b2 fmov w18, s5 + 5c4: 9e660119 fmov x25, d8 + 5c8: 1e270352 fmov s18, w26 + 5cc: 9e670160 fmov d0, x11 + 5d0: 1e262200 fcmp s16, s6 + 5d4: 1e7d2200 fcmp d16, d29 + 5d8: 1e2023c8 fcmp s30, #0.0 + 5dc: 1e602128 fcmp d9, #0.0 + 5e0: 293e119b stp w27, w4, [x12, #-16] + 5e4: 294a2543 ldp w3, w9, [x10, #80] + 5e8: 69480c70 ldpsw x16, x3, [x3, #64] + 5ec: a934726a stp x10, x28, [x19, #-192] + 5f0: a97448f3 ldp x19, x18, [x7, #-192] + 5f4: 298243ca stp w10, w16, [x30, #16]! + 5f8: 29e21242 ldp w2, w4, [x18, #-240]! + 5fc: 69c64db8 ldpsw x24, x19, [x13, #48]! + 600: a9800311 stp x17, x0, [x24, #0]! + 604: a9f4686e ldp x14, x26, [x3, #-192]! + 608: 288a0416 stp w22, w1, [x0], #80 + 60c: 28fe2812 ldp w18, w10, [x0], #-16 + 610: 68fe62d8 .inst 0x68fe62d8 ; undefined + 614: a885308c stp x12, x12, [x4], #80 + 618: a8f12664 ldp x4, x9, [x19], #-240 + 61c: 282468d2 stnp w18, w26, [x6, #-224] + 620: 284e5035 ldnp w21, w20, [x1, #112] + 624: a8327699 stnp x25, x29, [x20, #-224] + 628: a84716e1 ldnp x1, x5, [x23, #112] + 62c: 0c407284 ld1 {v4.8b}, [x20] + 630: 4cdfa158 ld1 {v24.16b, v25.16b}, [x10], #32 + 634: 0ccf6cd8 ld1 {v24.1d-v26.1d}, [x6], x15 + 638: 4cdf2483 ld1 {v3.8h-v6.8h}, [x4], #64 + 63c: 0d40c0c2 ld1r {v2.8b}, [x6] + 640: 4ddfc9cd ld1r {v13.4s}, [x14], #4 + 644: 0dd8ceaf ld1r {v15.1d}, [x21], x24 + 648: 4c408ea9 ld2 {v9.2d, v10.2d}, [x21] + 64c: 0cdf86bd ld2 {v29.4h, v30.4h}, [x21], #16 + 650: 4d60c1c8 ld2r {v8.16b, v9.16b}, [x14] + 654: 0dffca87 ld2r {v7.2s, v8.2s}, [x20], #8 + 658: 4de3cc7c ld2r {v28.2d, v29.2d}, [x3], x3 + 65c: 4cdd497b ld3 {v27.4s-v29.4s}, [x11], x29 + 660: 0c404950 ld3 {v16.2s-v18.2s}, [x10] + 664: 4d40e595 ld3r {v21.8h-v23.8h}, [x12] + 668: 4ddfeba4 ld3r {v4.4s-v6.4s}, [x29], #12 + 66c: 0dd3ed38 ld3r {v24.1d-v26.1d}, [x9], x19 + 670: 4cdf046a ld4 {v10.8h-v13.8h}, [x3], #64 + 674: 0cc9039b ld4 {v27.8b-v30.8b}, [x28], x9 + 678: 0d60e3d5 ld4r {v21.8b-v24.8b}, [x30] + 67c: 0dffe5d7 ld4r {v23.4h-v26.4h}, [x14], #8 + 680: 0df4e9a4 ld4r {v4.2s-v7.2s}, [x13], x20 + 684: ba5fd3e3 ccmn xzr, xzr, #0x3, le + 688: 3a5f03e5 ccmn wzr, wzr, #0x5, eq // eq = none + 68c: fa411be4 ccmp xzr, #0x1, #0x4, ne // ne = any + 690: 7a42cbe2 ccmp wzr, #0x2, #0x2, gt + 694: 93df03ff ror xzr, xzr, #0 + 698: c820ffff stlxp w0, xzr, xzr, [sp] + 69c: 8822fc7f stlxp w2, wzr, wzr, [x3] + 6a0: c8247cbf stxp w4, xzr, xzr, [x5] + 6a4: 88267fff stxp w6, wzr, wzr, [sp] + 6a8: 4e010fe0 dup v0.16b, wzr + 6ac: 4e081fe1 mov v1.d[0], xzr + 6b0: 4e0c1fe1 mov v1.s[1], wzr + 6b4: 4e0a1fe1 mov v1.h[2], wzr + 6b8: 4e071fe1 mov v1.b[3], wzr + 6bc: 4cc0ac3f ld1 {v31.2d, v0.2d}, [x1], x0 + 6c0: 1e601000 fmov d0, #2.000000000000000000e+00 + 6c4: 1e603000 fmov d0, #2.125000000000000000e+00 + 6c8: 1e621000 fmov d0, #4.000000000000000000e+00 + 6cc: 1e623000 fmov d0, #4.250000000000000000e+00 + 6d0: 1e641000 fmov d0, #8.000000000000000000e+00 + 6d4: 1e643000 fmov d0, #8.500000000000000000e+00 + 6d8: 1e661000 fmov d0, #1.600000000000000000e+01 + 6dc: 1e663000 fmov d0, #1.700000000000000000e+01 + 6e0: 1e681000 fmov d0, #1.250000000000000000e-01 + 6e4: 1e683000 fmov d0, #1.328125000000000000e-01 + 6e8: 1e6a1000 fmov d0, #2.500000000000000000e-01 + 6ec: 1e6a3000 fmov d0, #2.656250000000000000e-01 + 6f0: 1e6c1000 fmov d0, #5.000000000000000000e-01 + 6f4: 1e6c3000 fmov d0, #5.312500000000000000e-01 + 6f8: 1e6e1000 fmov d0, #1.000000000000000000e+00 + 6fc: 1e6e3000 fmov d0, #1.062500000000000000e+00 + 700: 1e701000 fmov d0, #-2.000000000000000000e+00 + 704: 1e703000 fmov d0, #-2.125000000000000000e+00 + 708: 1e721000 fmov d0, #-4.000000000000000000e+00 + 70c: 1e723000 fmov d0, #-4.250000000000000000e+00 + 710: 1e741000 fmov d0, #-8.000000000000000000e+00 + 714: 1e743000 fmov d0, #-8.500000000000000000e+00 + 718: 1e761000 fmov d0, #-1.600000000000000000e+01 + 71c: 1e763000 fmov d0, #-1.700000000000000000e+01 + 720: 1e781000 fmov d0, #-1.250000000000000000e-01 + 724: 1e783000 fmov d0, #-1.328125000000000000e-01 + 728: 1e7a1000 fmov d0, #-2.500000000000000000e-01 + 72c: 1e7a3000 fmov d0, #-2.656250000000000000e-01 + 730: 1e7c1000 fmov d0, #-5.000000000000000000e-01 + 734: 1e7c3000 fmov d0, #-5.312500000000000000e-01 + 738: 1e7e1000 fmov d0, #-1.000000000000000000e+00 + 73c: 1e7e3000 fmov d0, #-1.062500000000000000e+00 + 740: f8358305 swp x21, x5, [x24] + 744: f82d01ed ldadd x13, x13, [x15] + 748: f8361353 ldclr x22, x19, [x26] + 74c: f839234a ldeor x25, x10, [x26] + 750: f82531fb ldset x5, x27, [x15] + 754: f8335165 ldsmin x19, x5, [x11] + 758: f83a4080 ldsmax x26, x0, [x4] + 75c: f83673d7 ldumin x22, x23, [x30] + 760: f832611c ldumax x18, x28, [x8] + 764: f8ad837d swpa x13, x29, [x27] + 768: f8ab01a5 ldadda x11, x5, [x13] + 76c: f8a112b8 ldclra x1, x24, [x21] + 770: f8bb2311 ldeora x27, x17, [x24] + 774: f8b230be ldseta x18, x30, [x5] + 778: f8a75336 ldsmina x7, x22, [x25] + 77c: f8a4427a ldsmaxa x4, x26, [x19] + 780: f8a6707e ldumina x6, x30, [x3] + 784: f8b860b7 ldumaxa x24, x23, [x5] + 788: f8f88392 swpal x24, x18, [x28] + 78c: f8f300ff ldaddal x19, xzr, [x7] + 790: f8ed1386 ldclral x13, x6, [x28] + 794: f8e822af ldeoral x8, x15, [x21] + 798: f8e2302d ldsetal x2, x13, [x1] + 79c: f8f1533d ldsminal x17, x29, [x25] + 7a0: f8f941d2 ldsmaxal x25, x18, [x14] + 7a4: f8ff7366 lduminal xzr, x6, [x27] + 7a8: f8f061e5 ldumaxal x16, x5, [x15] + 7ac: f86b8072 swpl x11, x18, [x3] + 7b0: f87a0054 ldaddl x26, x20, [x2] + 7b4: f86b1164 ldclrl x11, x4, [x11] + 7b8: f87e22f3 ldeorl x30, x19, [x23] + 7bc: f86331cf ldsetl x3, x15, [x14] + 7c0: f87e5296 ldsminl x30, x22, [x20] + 7c4: f8674305 ldsmaxl x7, x5, [x24] + 7c8: f87771f0 lduminl x23, x16, [x15] + 7cc: f86b6013 ldumaxl x11, x19, [x0] + 7d0: b83c803c swp w28, w28, [x1] + 7d4: b82b0195 ldadd w11, w21, [x12] + 7d8: b83d1240 ldclr w29, w0, [x18] + 7dc: b8252320 ldeor w5, w0, [x25] + 7e0: b82e3340 ldset w14, w0, [x26] + 7e4: b83c53b2 ldsmin w28, w18, [x29] + 7e8: b82f43a1 ldsmax w15, w1, [x29] + 7ec: b828739a ldumin w8, w26, [x28] + 7f0: b831608e ldumax w17, w14, [x4] + 7f4: b8b88039 swpa w24, w25, [x1] + 7f8: b8aa0231 ldadda w10, w17, [x17] + 7fc: b8bd12b4 ldclra w29, w20, [x21] + 800: b8bd2189 ldeora w29, w9, [x12] + 804: b8ab30a6 ldseta w11, w6, [x5] + 808: b8b552a7 ldsmina w21, w7, [x21] + 80c: b8aa4197 ldsmaxa w10, w23, [x12] + 810: b8b57145 ldumina w21, w5, [x10] + 814: b8be6254 ldumaxa w30, w20, [x18] + 818: b8ed80b7 swpal w13, w23, [x5] + 81c: b8ef00b8 ldaddal w15, w24, [x5] + 820: b8e9132a ldclral w9, w10, [x25] + 824: b8f42231 ldeoral w20, w17, [x17] + 828: b8ec33d2 ldsetal w12, w18, [x30] + 82c: b8e35323 ldsminal w3, w3, [x25] + 830: b8fa4159 ldsmaxal w26, w25, [x10] + 834: b8e273eb lduminal w2, w11, [sp] + 838: b8e760a2 ldumaxal w7, w2, [x5] + 83c: b8608287 swpl w0, w7, [x20] + 840: b865005f staddl w5, [x2] + 844: b87b1379 ldclrl w27, w25, [x27] + 848: b87e2358 ldeorl w30, w24, [x26] + 84c: b86f32c2 ldsetl w15, w2, [x22] + 850: b86053e3 ldsminl w0, w3, [sp] + 854: b86f4154 ldsmaxl w15, w20, [x10] + 858: b87671d5 lduminl w22, w21, [x14] + 85c: b866605e ldumaxl w6, w30, [x2] */ static const unsigned int insns[] = { - 0x8b0772d3, 0xcb4a3570, 0xab9c09bb, 0xeb9aa794, - 0x0b934e68, 0x4b0a3924, 0x2b1e3568, 0x6b132720, - 0x8a154c14, 0xaa1445d5, 0xca01cf99, 0xea8b3f6a, - 0x0a8c5cb9, 0x2a4a11d2, 0x4a855aa4, 0x6a857415, - 0x8aa697da, 0xaa6d7423, 0xca29bf80, 0xea3cb8bd, - 0x0a675249, 0x2ab961ba, 0x4a331899, 0x6a646345, - 0x11055267, 0x31064408, 0x51028e9d, 0x710bdee8, - 0x91082d81, 0xb106a962, 0xd10b33ae, 0xf10918ab, - 0x121102d7, 0x3204cd44, 0x5204cf00, 0x72099fb3, - 0x92729545, 0xb20e37cc, 0xd27c34be, 0xf27e4efa, - 0x14000000, 0x17ffffd7, 0x1400017f, 0x94000000, - 0x97ffffd4, 0x9400017c, 0x3400000c, 0x34fffa2c, - 0x34002f2c, 0x35000014, 0x35fff9d4, 0x35002ed4, - 0xb400000c, 0xb4fff96c, 0xb4002e6c, 0xb5000018, - 0xb5fff918, 0xb5002e18, 0x10000006, 0x10fff8a6, - 0x10002da6, 0x90000015, 0x36080001, 0x360ff821, - 0x36082d21, 0x37480008, 0x374ff7c8, 0x37482cc8, - 0x128b50ec, 0x52a9ff8b, 0x7281d095, 0x92edfebd, - 0xd28361e3, 0xf2a4cc96, 0x9346590c, 0x33194f33, - 0x531d3d89, 0x9350433c, 0xb34464ac, 0xd3462140, - 0x139a61a4, 0x93d87fd7, 0x54000000, 0x54fff5a0, - 0x54002aa0, 0x54000001, 0x54fff541, 0x54002a41, - 0x54000002, 0x54fff4e2, 0x540029e2, 0x54000002, - 0x54fff482, 0x54002982, 0x54000003, 0x54fff423, - 0x54002923, 0x54000003, 0x54fff3c3, 0x540028c3, - 0x54000004, 0x54fff364, 0x54002864, 0x54000005, - 0x54fff305, 0x54002805, 0x54000006, 0x54fff2a6, - 0x540027a6, 0x54000007, 0x54fff247, 0x54002747, - 0x54000008, 0x54fff1e8, 0x540026e8, 0x54000009, - 0x54fff189, 0x54002689, 0x5400000a, 0x54fff12a, - 0x5400262a, 0x5400000b, 0x54fff0cb, 0x540025cb, - 0x5400000c, 0x54fff06c, 0x5400256c, 0x5400000d, - 0x54fff00d, 0x5400250d, 0x5400000e, 0x54ffefae, - 0x540024ae, 0x5400000f, 0x54ffef4f, 0x5400244f, - 0xd4063721, 0xd4035082, 0xd400bfe3, 0xd4282fc0, - 0xd444c320, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, - 0xd5033fdf, 0xd5033f9f, 0xd5033abf, 0xd61f0040, - 0xd63f00a0, 0xc8147c55, 0xc805fcfd, 0xc85f7e05, - 0xc85fffbb, 0xc89fffa0, 0xc8dfff95, 0x88157cf8, - 0x8815ff9a, 0x885f7cd5, 0x885fffcf, 0x889ffc73, - 0x88dffc56, 0x48127c0f, 0x480bff85, 0x485f7cdd, - 0x485ffcf2, 0x489fff99, 0x48dffe62, 0x080a7c3e, - 0x0814fed5, 0x085f7c59, 0x085ffcb8, 0x089ffc70, - 0x08dfffb6, 0xc87f0a68, 0xc87fcdc7, 0xc82870bb, - 0xc825b8c8, 0x887f12d9, 0x887fb9ed, 0x8834215a, - 0x8837ca52, 0xf806317e, 0xb81b3337, 0x39000dc2, - 0x78005149, 0xf84391f4, 0xb85b220c, 0x385fd356, - 0x785d127e, 0x389f4149, 0x79801e3c, 0x79c014a3, - 0xb89a5231, 0xfc5ef282, 0xbc5f60f6, 0xfc12125e, - 0xbc0152cd, 0xf8190e49, 0xb800befd, 0x381ffd92, - 0x781e9e90, 0xf8409fa3, 0xb8413c79, 0x385fffa1, - 0x785c7fa8, 0x389f3dc5, 0x78801f6a, 0x78c19d4b, - 0xb89a4ec4, 0xfc408eeb, 0xbc436e79, 0xfc152ce1, - 0xbc036f28, 0xf8025565, 0xb80135f8, 0x381ff74f, - 0x781fa652, 0xf851a447, 0xb85e557b, 0x385e7472, - 0x785e070a, 0x38804556, 0x78819591, 0x78dc24e8, - 0xb89cd6d7, 0xfc430738, 0xbc5f6595, 0xfc1225b2, - 0xbc1d7430, 0xf82fcac2, 0xb83d6a02, 0x382e5a54, - 0x7834fa66, 0xf86ecbae, 0xb86cda90, 0x3860d989, - 0x78637a2c, 0x38a3fa22, 0x78b15827, 0x78f2d9f9, - 0xb8ac6ab7, 0xfc6879a5, 0xbc767943, 0xfc3bc84e, - 0xbc3968d4, 0xf91fc0fe, 0xb91da50f, 0x391d280b, - 0x791d2e23, 0xf95bc8e2, 0xb95ce525, 0x395ae53c, - 0x795c9282, 0x399d7dd6, 0x799fe008, 0x79de9bc0, - 0xb99aae78, 0xfd597598, 0xbd5d1d08, 0xfd1f3dea, - 0xbd1a227a, 0x5800148a, 0x18000003, 0xf88092e0, - 0xd8ffdf00, 0xf8a84860, 0xf99d7560, 0x1a1c012d, - 0x3a1c027b, 0x5a060253, 0x7a03028e, 0x9a0801d0, - 0xba0803a0, 0xda140308, 0xfa00038c, 0x0b3010d7, - 0x2b37ab39, 0xcb2466da, 0x6b33efb1, 0x8b350fcb, - 0xab208a70, 0xcb39e52b, 0xeb2c9291, 0x3a4bd1a3, - 0x7a4c81a2, 0xba42106c, 0xfa5560e3, 0x3a4e3844, - 0x7a515a26, 0xba4c2940, 0xfa52aaae, 0x1a8cc1b5, - 0x1a8f976a, 0x5a8981a0, 0x5a9a6492, 0x9a8793ac, - 0x9a9474e6, 0xda83d2b6, 0xda9b9593, 0x5ac00200, - 0x5ac006f1, 0x5ac009d1, 0x5ac013d8, 0x5ac016d8, - 0xdac00223, 0xdac005ac, 0xdac00ac9, 0xdac00c00, - 0xdac01205, 0xdac016d9, 0x1ac0089d, 0x1add0fa0, - 0x1ad52225, 0x1ad22529, 0x1ac82b61, 0x1acd2e92, - 0x9acc0b28, 0x9adc0ca7, 0x9adb2225, 0x9ad42757, - 0x9adc291c, 0x9ac42fa3, 0x1b1a55d1, 0x1b0bafc1, - 0x9b067221, 0x9b1ea0de, 0x9b2e20d5, 0x9b38cd4a, - 0x9bae6254, 0x9ba59452, 0x1e2d0a48, 0x1e3c19c2, - 0x1e3c298f, 0x1e213980, 0x1e240baf, 0x1e77082c, - 0x1e72191b, 0x1e6b2a97, 0x1e723988, 0x1e770b1a, - 0x1f0d66f5, 0x1f01b956, 0x1f227a8e, 0x1f365ba7, - 0x1f4f14ad, 0x1f45a98e, 0x1f60066a, 0x1f620054, - 0x1e204139, 0x1e20c094, 0x1e214363, 0x1e21c041, - 0x1e22c01e, 0x1e60408c, 0x1e60c361, 0x1e6142c8, - 0x1e61c16b, 0x1e624396, 0x1e3802dc, 0x9e380374, - 0x1e78000e, 0x9e78017a, 0x1e2202dc, 0x9e220150, - 0x1e6202a8, 0x9e620395, 0x1e260318, 0x9e660268, - 0x1e270188, 0x9e6700e6, 0x1e3023c0, 0x1e6b2320, - 0x1e202168, 0x1e602168, 0x2910323d, 0x297449d6, - 0x6948402b, 0xa9072f40, 0xa9410747, 0x29801f0a, - 0x29e07307, 0x69e272b9, 0xa9bf49d4, 0xa9c529a8, - 0x28b0605a, 0x28e866a2, 0x68ee0ab1, 0xa886296c, - 0xa8fe1a38, 0x282479c3, 0x286e534f, 0xa8386596, - 0xa8755a3b, 0x1e601000, 0x1e603000, 0x1e621000, - 0x1e623000, 0x1e641000, 0x1e643000, 0x1e661000, - 0x1e663000, 0x1e681000, 0x1e683000, 0x1e6a1000, - 0x1e6a3000, 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, - 0x1e6e3000, 0x1e701000, 0x1e703000, 0x1e721000, - 0x1e723000, 0x1e741000, 0x1e743000, 0x1e761000, - 0x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000, - 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, - 0x1e7e3000, + 0x8b50798f, 0xcb4381e1, 0xab05372d, 0xeb864796, + 0x0b961920, 0x4b195473, 0x2b0b5264, 0x6b9300f8, + 0x8a0bc0fe, 0xaa0f3118, 0xca170531, 0xea44dd6e, + 0x0a4c44f3, 0x2a8b7373, 0x4a567c7e, 0x6a9c0353, + 0x8a3accdd, 0xaa318f7a, 0xca2e1495, 0xeaa015e2, + 0x0a2274e2, 0x2a751598, 0x4a3309fe, 0x6ab172fe, + 0x110a5284, 0x310b1942, 0x5103d353, 0x710125bc, + 0x910d7bc2, 0xb108fa1b, 0xd1093536, 0xf10ae824, + 0x120e667c, 0x321f6cbb, 0x520f6a9e, 0x72136f56, + 0x927e4ce5, 0xb278b4ed, 0xd24c6527, 0xf2485803, + 0x14000000, 0x17ffffd7, 0x140001ee, 0x94000000, + 0x97ffffd4, 0x940001eb, 0x34000010, 0x34fffa30, + 0x34003d10, 0x35000013, 0x35fff9d3, 0x35003cb3, + 0xb4000005, 0xb4fff965, 0xb4003c45, 0xb5000004, + 0xb5fff904, 0xb5003be4, 0x1000001b, 0x10fff8bb, + 0x10003b9b, 0x90000010, 0x3640001c, 0x3647f83c, + 0x36403b1c, 0x37080001, 0x370ff7c1, 0x37083aa1, + 0x12a437f4, 0x528c9d67, 0x72838bb1, 0x92c1062e, + 0xd287da49, 0xf2a6d153, 0x93465ac9, 0x330b0013, + 0x530b4e6a, 0x934545e4, 0xb35370a3, 0xd3510b8c, + 0x13960c0f, 0x93ceddc6, 0x54000000, 0x54fff5a0, + 0x54003880, 0x54000001, 0x54fff541, 0x54003821, + 0x54000002, 0x54fff4e2, 0x540037c2, 0x54000002, + 0x54fff482, 0x54003762, 0x54000003, 0x54fff423, + 0x54003703, 0x54000003, 0x54fff3c3, 0x540036a3, + 0x54000004, 0x54fff364, 0x54003644, 0x54000005, + 0x54fff305, 0x540035e5, 0x54000006, 0x54fff2a6, + 0x54003586, 0x54000007, 0x54fff247, 0x54003527, + 0x54000008, 0x54fff1e8, 0x540034c8, 0x54000009, + 0x54fff189, 0x54003469, 0x5400000a, 0x54fff12a, + 0x5400340a, 0x5400000b, 0x54fff0cb, 0x540033ab, + 0x5400000c, 0x54fff06c, 0x5400334c, 0x5400000d, + 0x54fff00d, 0x540032ed, 0x5400000e, 0x54ffefae, + 0x5400328e, 0x5400000f, 0x54ffef4f, 0x5400322f, + 0xd40ac601, 0xd40042a2, 0xd404dac3, 0xd4224d40, + 0xd44219c0, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, + 0xd5033fdf, 0xd503339f, 0xd50335bf, 0xd61f0280, + 0xd63f0040, 0xc8127c17, 0xc81efec5, 0xc85f7d05, + 0xc85ffe14, 0xc89ffd66, 0xc8dfff66, 0x880a7cb1, + 0x8816fd89, 0x885f7d1b, 0x885ffc57, 0x889fffba, + 0x88dffd4d, 0x48197f7c, 0x481dfd96, 0x485f7f96, + 0x485fffc3, 0x489ffdf8, 0x48dfff5b, 0x080b7e6a, + 0x0817fedb, 0x085f7e18, 0x085ffc38, 0x089fffa5, + 0x08dffe18, 0xc87f6239, 0xc87fb276, 0xc820573a, + 0xc821aca6, 0x887f388d, 0x887f88d1, 0x882f2643, + 0x88329131, 0xf81cf2b7, 0xb803f055, 0x39002f9b, + 0x781f31fd, 0xf85d33ce, 0xb843539d, 0x39401f54, + 0x785ce059, 0x389f1143, 0x788131ee, 0x78dfb17d, + 0xb89b90af, 0xfc403193, 0xbc42a36c, 0xfc07d396, + 0xbc1ec1f8, 0xf81e8f88, 0xb8025de6, 0x38007c27, + 0x7801ee20, 0xf8454fb9, 0xb85cce9a, 0x385e7fba, + 0x7841af24, 0x389ebd1c, 0x789fadd1, 0x78c0aefc, + 0xb89c0f7e, 0xfc50efd4, 0xbc414f71, 0xfc011c67, + 0xbc1f0d6d, 0xf81c3526, 0xb81e34b0, 0x3800f7bd, + 0x78012684, 0xf842e653, 0xb8417456, 0x385e2467, + 0x785e358b, 0x389e34c8, 0x788046f8, 0x78c00611, + 0xb89f8680, 0xfc582454, 0xbc5987d3, 0xfc076624, + 0xbc190675, 0xf833785a, 0xb82fd809, 0x3821799a, + 0x782a7975, 0xf870eaf0, 0xb871d96a, 0x386b7aed, + 0x7875689b, 0x38afd91a, 0x78a2c955, 0x78ee6bc8, + 0xb8b4f9dd, 0xfc76eb7e, 0xbc76692d, 0xfc31db28, + 0xbc255b01, 0xf91c52aa, 0xb91c3fb2, 0x391f8877, + 0x791ac97c, 0xf95c1758, 0xb95b3c55, 0x395ce0a4, + 0x795851ce, 0x399e9f64, 0x79993764, 0x79d9af8a, + 0xb99eea2a, 0xfd5a2f8d, 0xbd5dac78, 0xfd1e0182, + 0xbd195c31, 0x58000010, 0x1800000d, 0xf8981240, + 0xd8ffdf00, 0xf8a27a80, 0xf99af920, 0x1a0202e8, + 0x3a130078, 0x5a1d0316, 0x7a03036c, 0x9a0102eb, + 0xba1700bd, 0xda0c0329, 0xfa16000c, 0x0b23459a, + 0x2b328a14, 0xcb274bde, 0x6b222eab, 0x8b214b42, + 0xab34a7b2, 0xcb24520e, 0xeb378e20, 0x3a565283, + 0x7a420321, 0xba58c247, 0xfa4d5106, 0x3a426924, + 0x7a5b0847, 0xba413a02, 0xfa5fba23, 0x1a979377, + 0x1a86640a, 0x5a89300b, 0x5a923771, 0x9a8b720c, + 0x9a868786, 0xda9a736d, 0xda9256dd, 0x5ac0026c, + 0x5ac00657, 0x5ac00b89, 0x5ac01262, 0x5ac017b9, + 0xdac002e4, 0xdac0065d, 0xdac00907, 0xdac00e2d, + 0xdac01011, 0xdac01752, 0x1ad0098b, 0x1ac70d24, + 0x1ad020ec, 0x1ad72613, 0x1ac62887, 0x1ad72e95, + 0x9adc0990, 0x9acd0d84, 0x9ac721a9, 0x9acf277c, + 0x9ace2bd4, 0x9ade2e4e, 0x9bc77d63, 0x9b587e97, + 0x1b1524a2, 0x1b04a318, 0x9b0f4d8b, 0x9b0ce73d, + 0x9b2c5971, 0x9b34c87c, 0x9bbc6887, 0x9bb19556, + 0x1e310871, 0x1e261a2b, 0x1e2928fd, 0x1e333987, + 0x1e230ae0, 0x1e75087a, 0x1e651a60, 0x1e692b40, + 0x1e753ab9, 0x1e7309b0, 0x1f00425d, 0x1f1d95b7, + 0x1f2a38e9, 0x1f2f5f99, 0x1f5545a6, 0x1f429ea3, + 0x1f65472a, 0x1f7449ce, 0x1e20404f, 0x1e20c0f2, + 0x1e2140c3, 0x1e21c02c, 0x1e22c009, 0x1e6040a4, + 0x1e60c1e3, 0x1e614331, 0x1e61c30c, 0x1e6240b5, + 0x1e3802a4, 0x9e38007b, 0x1e78011d, 0x9e7802a9, + 0x1e2203b4, 0x9e220107, 0x1e6202ac, 0x9e6202b0, + 0x1e2600b2, 0x9e660119, 0x1e270352, 0x9e670160, + 0x1e262200, 0x1e7d2200, 0x1e2023c8, 0x1e602128, + 0x293e119b, 0x294a2543, 0x69480c70, 0xa934726a, + 0xa97448f3, 0x298243ca, 0x29e21242, 0x69c64db8, + 0xa9800311, 0xa9f4686e, 0x288a0416, 0x28fe2812, + 0x68fe62d8, 0xa885308c, 0xa8f12664, 0x282468d2, + 0x284e5035, 0xa8327699, 0xa84716e1, 0x0c407284, + 0x4cdfa158, 0x0ccf6cd8, 0x4cdf2483, 0x0d40c0c2, + 0x4ddfc9cd, 0x0dd8ceaf, 0x4c408ea9, 0x0cdf86bd, + 0x4d60c1c8, 0x0dffca87, 0x4de3cc7c, 0x4cdd497b, + 0x0c404950, 0x4d40e595, 0x4ddfeba4, 0x0dd3ed38, + 0x4cdf046a, 0x0cc9039b, 0x0d60e3d5, 0x0dffe5d7, + 0x0df4e9a4, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, + 0x7a42cbe2, 0x93df03ff, 0xc820ffff, 0x8822fc7f, + 0xc8247cbf, 0x88267fff, 0x4e010fe0, 0x4e081fe1, + 0x4e0c1fe1, 0x4e0a1fe1, 0x4e071fe1, 0x4cc0ac3f, + 0x1e601000, 0x1e603000, 0x1e621000, 0x1e623000, + 0x1e641000, 0x1e643000, 0x1e661000, 0x1e663000, + 0x1e681000, 0x1e683000, 0x1e6a1000, 0x1e6a3000, + 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, 0x1e6e3000, + 0x1e701000, 0x1e703000, 0x1e721000, 0x1e723000, + 0x1e741000, 0x1e743000, 0x1e761000, 0x1e763000, + 0x1e781000, 0x1e783000, 0x1e7a1000, 0x1e7a3000, + 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, 0x1e7e3000, + 0xf8358305, 0xf82d01ed, 0xf8361353, 0xf839234a, + 0xf82531fb, 0xf8335165, 0xf83a4080, 0xf83673d7, + 0xf832611c, 0xf8ad837d, 0xf8ab01a5, 0xf8a112b8, + 0xf8bb2311, 0xf8b230be, 0xf8a75336, 0xf8a4427a, + 0xf8a6707e, 0xf8b860b7, 0xf8f88392, 0xf8f300ff, + 0xf8ed1386, 0xf8e822af, 0xf8e2302d, 0xf8f1533d, + 0xf8f941d2, 0xf8ff7366, 0xf8f061e5, 0xf86b8072, + 0xf87a0054, 0xf86b1164, 0xf87e22f3, 0xf86331cf, + 0xf87e5296, 0xf8674305, 0xf87771f0, 0xf86b6013, + 0xb83c803c, 0xb82b0195, 0xb83d1240, 0xb8252320, + 0xb82e3340, 0xb83c53b2, 0xb82f43a1, 0xb828739a, + 0xb831608e, 0xb8b88039, 0xb8aa0231, 0xb8bd12b4, + 0xb8bd2189, 0xb8ab30a6, 0xb8b552a7, 0xb8aa4197, + 0xb8b57145, 0xb8be6254, 0xb8ed80b7, 0xb8ef00b8, + 0xb8e9132a, 0xb8f42231, 0xb8ec33d2, 0xb8e35323, + 0xb8fa4159, 0xb8e273eb, 0xb8e760a2, 0xb8608287, + 0xb865005f, 0xb87b1379, 0xb87e2358, 0xb86f32c2, + 0xb86053e3, 0xb86f4154, 0xb87671d5, 0xb866605e, + }; // END Generated code -- do not edit @@ -1194,9 +1457,8 @@ asm_check((unsigned int *)PC, vector_insns, sizeof vector_insns / sizeof vector_insns[0]); } - -#endif // ASSERT } +#endif // ASSERT #undef __ @@ -1231,7 +1493,7 @@ Disassembler::decode((address)start, (address)start + len); } - JNIEXPORT void das1(unsigned long insn) { + JNIEXPORT void das1(uintptr_t insn) { das(insn, 1); } } @@ -1255,7 +1517,7 @@ break; } case base_plus_offset_reg: { - __ add(r, _base, _index, _ext.op(), MAX(_ext.shift(), 0)); + __ add(r, _base, _index, _ext.op(), MAX2(_ext.shift(), 0)); break; } case literal: { @@ -1270,7 +1532,7 @@ } } -void Assembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) { +void Assembler::adrp(Register reg1, const Address &dest, uintptr_t &byte_offset) { ShouldNotReachHere(); } @@ -1279,7 +1541,7 @@ #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use) void Assembler::adr(Register Rd, address adr) { - long offset = adr - pc(); + intptr_t offset = adr - pc(); int offset_lo = offset & 3; offset >>= 2; starti; @@ -1290,7 +1552,7 @@ void Assembler::_adrp(Register Rd, address adr) { uint64_t pc_page = (uint64_t)pc() >> 12; uint64_t adr_page = (uint64_t)adr >> 12; - long offset = adr_page - pc_page; + intptr_t offset = adr_page - pc_page; int offset_lo = offset & 3; offset >>= 2; starti; @@ -1439,9 +1701,8 @@ srf(Rn, 5); } -bool Assembler::operand_valid_for_add_sub_immediate(long imm) { - bool shift = false; - unsigned long uimm = uabs(imm); +bool Assembler::operand_valid_for_add_sub_immediate(int64_t imm) { + uint64_t uimm = (uint64_t)uabs(imm); if (uimm < (1 << 12)) return true; if (uimm < (1 << 24) @@ -1485,21 +1746,6 @@ void Assembler::bang_stack_with_offset(int offset) { Unimplemented(); } -// these are the functions provided by the simulator which are used to -// encode and decode logical immediates and floating point immediates -// -// u_int64_t logical_immediate_for_encoding(u_int32_t encoding); -// -// u_int32_t encoding_for_logical_immediate(u_int64_t immediate); -// -// u_int64_t fp_immediate_for_encoding(u_int32_t imm8, int is_dp); -// -// u_int32_t encoding_for_fp_immediate(float immediate); -// -// we currently import these from the simulator librray but the -// definitions will need to be moved to here when we switch to real -// hardware. - // and now the routines called by the assembler which encapsulate the // above encode and decode functions
diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp index 56c3381..8a2dd3f 100644 --- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp
@@ -188,7 +188,7 @@ static inline uint32_t extract(uint32_t val, int msb, int lsb) { int nbits = msb - lsb + 1; assert_cond(msb >= lsb); - uint32_t mask = (1U << nbits) - 1; + uint32_t mask = checked_cast<uint32_t>(right_n_bits(nbits)); uint32_t result = val >> lsb; result &= mask; return result; @@ -199,11 +199,11 @@ return extend(uval, msb - lsb); } - static void patch(address a, int msb, int lsb, unsigned long val) { + static void patch(address a, int msb, int lsb, uint64_t val) { int nbits = msb - lsb + 1; guarantee(val < (1U << nbits), "Field too big for insn"); assert_cond(msb >= lsb); - unsigned mask = (1U << nbits) - 1; + unsigned mask = checked_cast<unsigned>(right_n_bits(nbits)); val <<= lsb; mask <<= lsb; unsigned target = *(unsigned *)a; @@ -212,12 +212,12 @@ *(unsigned *)a = target; } - static void spatch(address a, int msb, int lsb, long val) { + static void spatch(address a, int msb, int lsb, int64_t val) { int nbits = msb - lsb + 1; - long chk = val >> (nbits - 1); + int64_t chk = val >> (nbits - 1); guarantee (chk == -1 || chk == 0, "Field too big for insn"); unsigned uval = val; - unsigned mask = (1U << nbits) - 1; + unsigned mask = checked_cast<unsigned>(right_n_bits(nbits)); uval &= mask; uval <<= lsb; mask <<= lsb; @@ -229,9 +229,9 @@ void f(unsigned val, int msb, int lsb) { int nbits = msb - lsb + 1; - guarantee(val < (1U << nbits), "Field too big for insn"); + guarantee(val < (1ULL << nbits), "Field too big for insn"); assert_cond(msb >= lsb); - unsigned mask = (1U << nbits) - 1; + unsigned mask = checked_cast<unsigned>(right_n_bits(nbits)); val <<= lsb; mask <<= lsb; insn |= val; @@ -245,12 +245,12 @@ f(val, bit, bit); } - void sf(long val, int msb, int lsb) { + void sf(int64_t val, int msb, int lsb) { int nbits = msb - lsb + 1; - long chk = val >> (nbits - 1); + int64_t chk = val >> (nbits - 1); guarantee (chk == -1 || chk == 0, "Field too big for insn"); unsigned uval = val; - unsigned mask = (1U << nbits) - 1; + unsigned mask = checked_cast<unsigned>(right_n_bits(nbits)); uval &= mask; f(uval, lsb + nbits - 1, lsb); } @@ -275,8 +275,8 @@ unsigned get(int msb = 31, int lsb = 0) { int nbits = msb - lsb + 1; - unsigned mask = ((1U << nbits) - 1) << lsb; - assert_cond(bits & mask == mask); + unsigned mask = checked_cast<unsigned>(right_n_bits(nbits)) << lsb; + assert_cond((bits & mask) == mask); return (insn & mask) >> lsb; } @@ -295,7 +295,7 @@ int _offset; Register _r; public: - PrePost(Register reg, int o) : _r(reg), _offset(o) { } + PrePost(Register reg, int o) : _offset(o), _r(reg) { } int offset() { return _offset; } Register reg() { return _r; } }; @@ -306,10 +306,12 @@ }; class Post : public PrePost { Register _idx; + bool _is_postreg; public: - Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; } - Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; } + Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; _is_postreg = false; } + Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; _is_postreg = true; } Register idx_reg() { return _idx; } + bool is_postreg() {return _is_postreg; } }; namespace ext @@ -330,7 +332,7 @@ ext::operation _op; public: extend() { } - extend(int s, int o, ext::operation op) : _shift(s), _option(o), _op(op) { } + extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { } int option() const{ return _option; } int shift() const { return _shift; } ext::operation op() const { return _op; } @@ -355,7 +357,7 @@ private: Register _base; Register _index; - long _offset; + int64_t _offset; enum mode _mode; extend _ext; @@ -375,26 +377,25 @@ Address() : _mode(no_mode) { } Address(Register r) - : _mode(base_plus_offset), _base(r), _offset(0), _index(noreg), _target(0) { } + : _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { } Address(Register r, int o) - : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } - Address(Register r, long o) - : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } - Address(Register r, unsigned long o) - : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } + : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { } + Address(Register r, int64_t o) + : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { } + Address(Register r, uint64_t o) + : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { } #ifdef ASSERT Address(Register r, ByteSize disp) - : _mode(base_plus_offset), _base(r), _offset(in_bytes(disp)), - _index(noreg), _target(0) { } + : _base(r), _index(noreg), _offset(in_bytes(disp)), _mode(base_plus_offset), _target(0) { } #endif Address(Register r, Register r1, extend ext = lsl()) - : _mode(base_plus_offset_reg), _base(r), _index(r1), - _ext(ext), _offset(0), _target(0) { } + : _base(r), _index(r1), _offset(0), _mode(base_plus_offset_reg), + _ext(ext), _target(0) { } Address(Pre p) - : _mode(pre), _base(p.reg()), _offset(p.offset()) { } + : _base(p.reg()), _offset(p.offset()), _mode(pre) { } Address(Post p) - : _mode(p.idx_reg() == NULL ? post : post_reg), _base(p.reg()), - _offset(p.offset()), _target(0), _index(p.idx_reg()) { } + : _base(p.reg()), _index(p.idx_reg()), _offset(p.offset()), + _mode(p.is_postreg() ? post_reg : post), _target(0) { } Address(address target, RelocationHolder const& rspec) : _mode(literal), _rspec(rspec), @@ -403,7 +404,7 @@ Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type); Address(Register base, RegisterOrConstant index, extend ext = lsl()) : _base (base), - _ext(ext), _offset(0), _target(0) { + _offset(0), _ext(ext), _target(0) { if (index.is_register()) { _mode = base_plus_offset_reg; _index = index.as_register(); @@ -421,7 +422,7 @@ "wrong mode"); return _base; } - long offset() const { + int64_t offset() const { return _offset; } Register index() const { @@ -475,8 +476,7 @@ if (size == 0) // It's a byte i->f(_ext.shift() >= 0, 12); else { - if (_ext.shift() > 0) - assert(_ext.shift() == (int)size, "bad shift"); + assert(_ext.shift() <= 0 || _ext.shift() == (int)size, "bad shift"); i->f(_ext.shift() > 0, 12); } i->f(0b10, 11, 10); @@ -553,14 +553,7 @@ void lea(MacroAssembler *, Register) const; - static bool offset_ok_for_immed(long offset, int shift = 0) { - unsigned mask = (1 << shift) - 1; - if (offset < 0 || offset & mask) { - return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset - } else { - return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset - } - } + static bool offset_ok_for_immed(int64_t offset, uint shift = 0); }; // Convience classes @@ -603,7 +596,9 @@ InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {} }; -const int FPUStateSizeInWords = 32 * 2; +const int FPUStateSizeInWords = FloatRegisterImpl::number_of_registers * + FloatRegisterImpl::save_slots_per_register; + typedef enum { PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM, PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM, @@ -613,10 +608,10 @@ class Assembler : public AbstractAssembler { #ifndef PRODUCT - static const unsigned long asm_bp; + static const uintptr_t asm_bp; void emit_long(jint x) { - if ((unsigned long)pc() == asm_bp) + if ((uintptr_t)pc() == asm_bp) asm volatile ("nop"); AbstractAssembler::emit_int32(x); } @@ -659,7 +654,7 @@ void f(unsigned val, int msb) { current->f(val, msb, msb); } - void sf(long val, int msb, int lsb) { + void sf(int64_t val, int msb, int lsb) { current->sf(val, msb, lsb); } void rf(Register reg, int lsb) { @@ -709,7 +704,7 @@ wrap_label(Rd, L, &Assembler::_adrp); } - void adrp(Register Rd, const Address &dest, unsigned long &offset); + void adrp(Register Rd, const Address &dest, uint64_t &offset); #undef INSN @@ -800,32 +795,34 @@ #undef INSN // Bitfield -#define INSN(NAME, opcode) \ +#define INSN(NAME, opcode, size) \ void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \ starti; \ + guarantee(size == 1 || (immr < 32 && imms < 32), "incorrect immr/imms");\ f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \ zrf(Rn, 5), rf(Rd, 0); \ } - INSN(sbfmw, 0b0001001100); - INSN(bfmw, 0b0011001100); - INSN(ubfmw, 0b0101001100); - INSN(sbfm, 0b1001001101); - INSN(bfm, 0b1011001101); - INSN(ubfm, 0b1101001101); + INSN(sbfmw, 0b0001001100, 0); + INSN(bfmw, 0b0011001100, 0); + INSN(ubfmw, 0b0101001100, 0); + INSN(sbfm, 0b1001001101, 1); + INSN(bfm, 0b1011001101, 1); + INSN(ubfm, 0b1101001101, 1); #undef INSN // Extract -#define INSN(NAME, opcode) \ +#define INSN(NAME, opcode, size) \ void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \ starti; \ + guarantee(size == 1 || imms < 32, "incorrect imms"); \ f(opcode, 31, 21), f(imms, 15, 10); \ - rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \ + zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \ } - INSN(extrw, 0b00010011100); - INSN(extr, 0b10010011110); + INSN(extrw, 0b00010011100, 0); + INSN(extr, 0b10010011110, 1); #undef INSN @@ -833,7 +830,7 @@ // architecture. In debug mode we shrink it in order to test // trampolines, but not so small that branches in the interpreter // are out of range. - static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M); + static const uint64_t branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M); static bool reachable_from_branch_at(address branch, address target) { return uabs(target - branch) < branch_range; @@ -843,7 +840,7 @@ #define INSN(NAME, opcode) \ void NAME(address dest) { \ starti; \ - long offset = (dest - pc()) >> 2; \ + int64_t offset = (dest - pc()) >> 2; \ DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \ f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \ } \ @@ -860,7 +857,7 @@ // Compare & branch (immediate) #define INSN(NAME, opcode) \ void NAME(Register Rt, address dest) { \ - long offset = (dest - pc()) >> 2; \ + int64_t offset = (dest - pc()) >> 2; \ starti; \ f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \ } \ @@ -878,7 +875,7 @@ // Test & branch (immediate) #define INSN(NAME, opcode) \ void NAME(Register Rt, int bitpos, address dest) { \ - long offset = (dest - pc()) >> 2; \ + int64_t offset = (dest - pc()) >> 2; \ int b5 = bitpos >> 5; \ bitpos &= 0x1f; \ starti; \ @@ -899,7 +896,7 @@ {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV}; void br(Condition cond, address dest) { - long offset = (dest - pc()) >> 2; + int64_t offset = (dest - pc()) >> 2; starti; f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0); } @@ -1119,7 +1116,7 @@ Register Rn, enum operand_size sz, int op, bool ordered) { starti; f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21); - rf(Rs, 16), f(ordered, 15), rf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0); + rf(Rs, 16), f(ordered, 15), zrf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0); } void load_exclusive(Register dst, Register addr, @@ -1212,8 +1209,8 @@ /* The size bit is in bit 30, not 31 */ sz = (operand_size)(sz == word ? 0b00:0b01); } - f(sz, 31, 30), f(0b001000, 29, 24), f(1, 23), f(a, 22), f(1, 21); - rf(Rs, 16), f(r, 15), f(0b11111, 14, 10), rf(Rn, 5), rf(Rt, 0); + f(sz, 31, 30), f(0b001000, 29, 24), f(not_pair ? 1 : 0, 23), f(a, 22), f(1, 21); + zrf(Rs, 16), f(r, 15), f(0b11111, 14, 10), srf(Rn, 5), zrf(Rt, 0); } // CAS @@ -1248,7 +1245,7 @@ enum operand_size sz, int op1, int op2, bool a, bool r) { starti; f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21); - rf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), rf(Rn, 5), zrf(Rt, 0); + zrf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), srf(Rn, 5), zrf(Rt, 0); } #define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2) \ @@ -1278,7 +1275,7 @@ // Load register (literal) #define INSN(NAME, opc, V) \ void NAME(Register Rt, address dest) { \ - long offset = (dest - pc()) >> 2; \ + int64_t offset = (dest - pc()) >> 2; \ starti; \ f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ sf(offset, 23, 5); \ @@ -1303,7 +1300,7 @@ #define INSN(NAME, opc, V) \ void NAME(FloatRegister Rt, address dest) { \ - long offset = (dest - pc()) >> 2; \ + int64_t offset = (dest - pc()) >> 2; \ starti; \ f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ sf(offset, 23, 5); \ @@ -1318,7 +1315,7 @@ #define INSN(NAME, opc, V) \ void NAME(address dest, prfop op = PLDL1KEEP) { \ - long offset = (dest - pc()) >> 2; \ + int64_t offset = (dest - pc()) >> 2; \ starti; \ f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ sf(offset, 23, 5); \ @@ -1394,7 +1391,7 @@ assert(size == 0b10 || size == 0b11, "bad operand size in ldr"); assert(op == 0b01, "literal form can only be used with loads"); f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24); - long offset = (adr.target() - pc()) >> 2; + int64_t offset = (adr.target() - pc()) >> 2; sf(offset, 23, 5); code_section()->relocate(pc(), adr.rspec()); return; @@ -1470,6 +1467,7 @@ void NAME(Register Rd, Register Rn, Register Rm, \ enum shift_kind kind = LSL, unsigned shift = 0) { \ starti; \ + guarantee(size == 1 || shift < 32, "incorrect shift"); \ f(N, 21); \ zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \ op_shifted_reg(0b01010, kind, shift, size, op); \ @@ -1532,6 +1530,7 @@ starti; \ f(0, 21); \ assert_cond(kind != ROR); \ + guarantee(size == 1 || shift < 32, "incorrect shift");\ zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \ op_shifted_reg(0b01011, kind, shift, size, op); \ } @@ -1560,7 +1559,7 @@ void add_sub_extended_reg(unsigned op, unsigned decode, Register Rd, Register Rn, Register Rm, unsigned opt, ext::operation option, unsigned imm) { - guarantee(imm <= 4, "shift amount must be < 4"); + guarantee(imm <= 4, "shift amount must be <= 4"); f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21); f(option, 15, 13), f(imm, 12, 10); } @@ -1645,7 +1644,7 @@ f(o2, 10); f(o3, 4); f(nzcv, 3, 0); - f(imm5, 20, 16), rf(Rn, 5); + f(imm5, 20, 16), zrf(Rn, 5); } #define INSN(NAME, op) \ @@ -1846,12 +1845,16 @@ INSN(fdivs, 0b000, 0b00, 0b0001); INSN(fadds, 0b000, 0b00, 0b0010); INSN(fsubs, 0b000, 0b00, 0b0011); + INSN(fmaxs, 0b000, 0b00, 0b0100); + INSN(fmins, 0b000, 0b00, 0b0101); INSN(fnmuls, 0b000, 0b00, 0b1000); INSN(fmuld, 0b000, 0b01, 0b0000); INSN(fdivd, 0b000, 0b01, 0b0001); INSN(faddd, 0b000, 0b01, 0b0010); INSN(fsubd, 0b000, 0b01, 0b0011); + INSN(fmaxd, 0b000, 0b01, 0b0100); + INSN(fmind, 0b000, 0b01, 0b0101); INSN(fnmuld, 0b000, 0b01, 0b1000); #undef INSN @@ -1994,6 +1997,21 @@ #undef INSN #undef INSN1 +// Floating-point compare. 3-registers versions (scalar). +#define INSN(NAME, sz, e) \ + void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \ + starti; \ + f(0b01111110, 31, 24), f(e, 23), f(sz, 22), f(1, 21), rf(Vm, 16); \ + f(0b111011, 15, 10), rf(Vn, 5), rf(Vd, 0); \ + } \ + + INSN(facged, 1, 0); // facge-double + INSN(facges, 0, 0); // facge-single + INSN(facgtd, 1, 1); // facgt-double + INSN(facgts, 0, 1); // facgt-single + +#undef INSN + // Floating-point Move (immediate) private: unsigned pack(double value); @@ -2110,7 +2128,12 @@ } void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int imm, int op1, int op2, int regs) { - guarantee(T <= T1Q && imm == SIMD_Size_in_bytes[T] * regs, "bad offset"); + + bool replicate = op2 >> 2 == 3; + // post-index value (imm) is formed differently for replicate/non-replicate ld* instructions + int expectedImmediate = replicate ? regs * (1 << (T >> 1)) : SIMD_Size_in_bytes[T] * regs; + guarantee(T < T1Q , "incorrect arrangement"); + guarantee(imm == expectedImmediate, "bad offset"); starti; f(0,31), f((int)T & 1, 30); f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12); @@ -2217,39 +2240,62 @@ #undef INSN -#define INSN(NAME, opc, opc2) \ +#define INSN(NAME, opc, opc2, acceptT2D) \ void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ + guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \ + if (!acceptT2D) guarantee(T != T2D, "incorrect arrangement"); \ starti; \ f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \ f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \ rf(Vn, 5), rf(Vd, 0); \ } - INSN(addv, 0, 0b100001); - INSN(subv, 1, 0b100001); - INSN(mulv, 0, 0b100111); - INSN(mlav, 0, 0b100101); - INSN(mlsv, 1, 0b100101); - INSN(sshl, 0, 0b010001); - INSN(ushl, 1, 0b010001); + INSN(addv, 0, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D + INSN(subv, 1, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D + INSN(mulv, 0, 0b100111, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S + INSN(mlav, 0, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S + INSN(mlsv, 1, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S + INSN(sshl, 0, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D + INSN(ushl, 1, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D + INSN(umullv, 1, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S + INSN(umlalv, 1, 0b100000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S #undef INSN -#define INSN(NAME, opc, opc2) \ +#define INSN(NAME, opc, opc2, accepted) \ void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ + guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \ + if (accepted < 3) guarantee(T != T2D, "incorrect arrangement"); \ + if (accepted < 2) guarantee(T != T2S, "incorrect arrangement"); \ + if (accepted < 1) guarantee(T == T8B || T == T16B, "incorrect arrangement"); \ starti; \ f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \ f((int)T >> 1, 23, 22), f(opc2, 21, 10); \ rf(Vn, 5), rf(Vd, 0); \ } - INSN(absr, 0, 0b100000101110); - INSN(negr, 1, 0b100000101110); - INSN(notr, 1, 0b100000010110); - INSN(addv, 0, 0b110001101110); - INSN(cls, 0, 0b100000010010); - INSN(clz, 1, 0b100000010010); - INSN(cnt, 0, 0b100000010110); + INSN(absr, 0, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D + INSN(negr, 1, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D + INSN(notr, 1, 0b100000010110, 0); // accepted arrangements: T8B, T16B + INSN(addv, 0, 0b110001101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S + INSN(cls, 0, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S + INSN(clz, 1, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S + INSN(cnt, 0, 0b100000010110, 0); // accepted arrangements: T8B, T16B + INSN(uaddlp, 1, 0b100000001010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S + INSN(uaddlv, 1, 0b110000001110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S + +#undef INSN + +#define INSN(NAME, opc) \ + void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ + starti; \ + assert(T == T4S, "arrangement must be T4S"); \ + f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24), f(opc, 23), \ + f(T == T4S ? 0 : 1, 22), f(0b110000111110, 21, 10); rf(Vn, 5), rf(Vd, 0); \ + } + + INSN(fmaxv, 0); + INSN(fminv, 1); #undef INSN @@ -2260,7 +2306,7 @@ starti; \ assert(lsl == 0 || \ ((T == T4H || T == T8H) && lsl == 8) || \ - ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \ + ((T == T2S || T == T4S) && ((lsl >> 3) < 4) && ((lsl & 7) == 0)), "invalid shift");\ cmode |= lsl >> 2; \ if (T == T4H || T == T8H) cmode |= 0b1000; \ if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \ @@ -2294,6 +2340,8 @@ INSN(fsub, 0, 1, 0b110101); INSN(fmla, 0, 0, 0b110011); INSN(fmls, 0, 1, 0b110011); + INSN(fmax, 0, 0, 0b111101); + INSN(fmin, 0, 1, 0b111101); #undef INSN @@ -2353,7 +2401,7 @@ // FMLA/FMLS - Vector - Scalar INSN(fmlavs, 0, 0b0001); - INSN(fmlsvs, 0, 0b0001); + INSN(fmlsvs, 0, 0b0101); // FMULX - Vector - Scalar INSN(fmulxvs, 1, 0b1001); @@ -2419,7 +2467,22 @@ #undef INSN - void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { +#define INSN(NAME, opc, opc2, isSHR) \ + void NAME(FloatRegister Vd, FloatRegister Vn, int shift){ \ + starti; \ + int encodedShift = isSHR ? 128 - shift : 64 + shift; \ + f(0b01, 31, 30), f(opc, 29), f(0b111110, 28, 23), \ + f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \ + } + + INSN(shld, 0, 0b010101, /* isSHR = */ false); + INSN(sshrd, 0, 0b000001, /* isSHR = */ true); + INSN(ushrd, 1, 0b000001, /* isSHR = */ true); + +#undef INSN + +private: + void _ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { starti; /* The encodings for the immh:immb fields (bits 22:16) are * 0001 xxx 8H, 8B/16b shift = xxx @@ -2432,8 +2495,16 @@ f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16); f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0); } + +public: + void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { + assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement"); + _ushll(Vd, Ta, Vn, Tb, shift); + } + void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { - ushll(Vd, Ta, Vn, Tb, shift); + assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement"); + _ushll(Vd, Ta, Vn, Tb, shift); } // Move from general purpose register @@ -2441,19 +2512,21 @@ void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) { starti; f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); - f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0); + f(0b000111, 15, 10), zrf(Xn, 5), rf(Vd, 0); } // Move to general purpose register // mov Rd, Vn.T[index] void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) { + guarantee(T >= T2S && T < T1Q, "only D and S arrangements are supported"); starti; f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21); f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0); } - void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { +private: + void _pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { starti; assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) || (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier"); @@ -2461,9 +2534,16 @@ f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22); f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0); } + +public: + void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { + assert(Tb == T1D || Tb == T8B, "pmull assumes T1D or T8B as the second size specifier"); + _pmull(Vd, Ta, Vn, Vm, Tb); + } + void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier"); - pmull(Vd, Ta, Vn, Vm, Tb); + _pmull(Vd, Ta, Vn, Vm, Tb); } void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) { @@ -2480,7 +2560,7 @@ starti; assert(T != T1D, "reserved encoding"); f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21); - f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0); + f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), zrf(Xs, 5), rf(Vd, 0); } void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0) @@ -2495,6 +2575,7 @@ // AdvSIMD ZIP/UZP/TRN #define INSN(NAME, opcode) \ void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ + guarantee(T != T1D && T != T1Q, "invalid arrangement"); \ starti; \ f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15); \ f(opcode, 14, 12), f(0b10, 11, 10); \ @@ -2580,7 +2661,7 @@ // RBIT only allows T8B and T16B but encodes them oddly. Argh... void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { assert((ASSERTION), MSG); - _rbit(Vd, SIMD_Arrangement(T & 1 | 0b010), Vn); + _rbit(Vd, SIMD_Arrangement((T & 1) | 0b010), Vn); } #undef ASSERTION @@ -2598,137 +2679,6 @@ f(0, 10), rf(Vn, 5), rf(Vd, 0); } -/* Simulator extensions to the ISA - - haltsim - - takes no arguments, causes the sim to enter a debug break and then - return from the simulator run() call with STATUS_HALT? The linking - code will call fatal() when it sees STATUS_HALT. - - blrt Xn, Wm - blrt Xn, #gpargs, #fpargs, #type - Xn holds the 64 bit x86 branch_address - call format is encoded either as immediate data in the call - or in register Wm. In the latter case - Wm[13..6] = #gpargs, - Wm[5..2] = #fpargs, - Wm[1,0] = #type - - calls the x86 code address 'branch_address' supplied in Xn passing - arguments taken from the general and floating point registers according - to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0 - or v0 according to the the return type #type' where - - address branch_address; - uimm4 gpargs; - uimm4 fpargs; - enum ReturnType type; - - enum ReturnType - { - void_ret = 0, - int_ret = 1, - long_ret = 1, - obj_ret = 1, // i.e. same as long - float_ret = 2, - double_ret = 3 - } - - notify - - notifies the simulator of a transfer of control. instr[14:0] - identifies the type of change of control. - - 0 ==> initial entry to a method. - - 1 ==> return into a method from a submethod call. - - 2 ==> exit out of Java method code. - - 3 ==> start execution for a new bytecode. - - in cases 1 and 2 the simulator is expected to use a JVM callback to - identify the name of the specific method being executed. in case 4 - the simulator is expected to use a JVM callback to identify the - bytecode index. - - Instruction encodings - --------------------- - - These are encoded in the space with instr[28:25] = 00 which is - unallocated. Encodings are - - 10987654321098765432109876543210 - PSEUDO_HALT = 0x11100000000000000000000000000000 - PSEUDO_BLRT = 0x11000000000000000_______________ - PSEUDO_BLRTR = 0x1100000000000000100000__________ - PSEUDO_NOTIFY = 0x10100000000000000_______________ - - instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY - - for BLRT - instr[14,11] = #gpargs, instr[10,7] = #fpargs - instr[6,5] = #type, instr[4,0] = Rn - for BLRTR - instr[9,5] = Rm, instr[4,0] = Rn - for NOTIFY - instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart -*/ - - enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start }; - - virtual void notify(int type) { - if (UseBuiltinSim) { - starti; - // 109 - f(0b101, 31, 29); - // 87654321098765 - f(0b00000000000000, 28, 15); - f(type, 14, 0); - } - } - - void blrt(Register Rn, int gpargs, int fpargs, int type) { - if (UseBuiltinSim) { - starti; - f(0b110, 31 ,29); - f(0b00, 28, 25); - // 4321098765 - f(0b0000000000, 24, 15); - f(gpargs, 14, 11); - f(fpargs, 10, 7); - f(type, 6, 5); - rf(Rn, 0); - } else { - blr(Rn); - } - } - - void blrt(Register Rn, Register Rm) { - if (UseBuiltinSim) { - starti; - f(0b110, 31 ,29); - f(0b00, 28, 25); - // 4321098765 - f(0b0000000001, 24, 15); - // 43210 - f(0b00000, 14, 10); - rf(Rm, 5); - rf(Rn, 0); - } else { - blr(Rn); - } - } - - void haltsim() { - starti; - f(0b111, 31 ,29); - f(0b00, 28, 27); - // 654321098765432109876543210 - f(0b000000000000000000000000000, 26, 0); - } - Assembler(CodeBuffer* code) : AbstractAssembler(code) { } @@ -2743,7 +2693,7 @@ virtual void bang_stack_with_offset(int offset); static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm); - static bool operand_valid_for_add_sub_immediate(long imm); + static bool operand_valid_for_add_sub_immediate(int64_t imm); static bool operand_valid_for_float_immediate(double imm); void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.inline.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.inline.hpp index 86eb8c2..ab99fc0 100644 --- a/src/hotspot/cpu/aarch64/assembler_aarch64.inline.hpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.inline.hpp
@@ -30,4 +30,16 @@ #include "asm/codeBuffer.hpp" #include "code/codeCache.hpp" + +inline bool Address::offset_ok_for_immed(int64_t offset, uint shift) { + uint mask = (1 << shift) - 1; + if (offset < 0 || (offset & mask) != 0) { + // Unscaled signed offset, encoded in a signed imm9 field. + return Assembler::is_simm9(offset); + } else { + // Scaled unsigned offset, encoded in an unsigned imm12:_ field. + return Assembler::is_uimm12(offset >> shift); + } +} + #endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_INLINE_HPP
diff --git a/src/hotspot/cpu/aarch64/atomic_aarch64.hpp b/src/hotspot/cpu/aarch64/atomic_aarch64.hpp new file mode 100644 index 0000000..ac12ba9 --- /dev/null +++ b/src/hotspot/cpu/aarch64/atomic_aarch64.hpp
@@ -0,0 +1,49 @@ +/* Copyright (c) 2021, Red Hat Inc. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef CPU_AARCH64_ATOMIC_AARCH64_HPP +#define CPU_AARCH64_ATOMIC_AARCH64_HPP + +// Atomic stub implementation. +// Default implementations are in atomic_linux_aarch64.S +// +// All stubs pass arguments the same way +// x0: src/dest address +// x1: arg1 +// x2: arg2 (optional) +// x3, x8, x9: scratch +typedef uint64_t (*aarch64_atomic_stub_t)(volatile void *ptr, uint64_t arg1, uint64_t arg2); + +// Pointers to stubs +extern aarch64_atomic_stub_t aarch64_atomic_fetch_add_4_impl; +extern aarch64_atomic_stub_t aarch64_atomic_fetch_add_8_impl; +extern aarch64_atomic_stub_t aarch64_atomic_xchg_4_impl; +extern aarch64_atomic_stub_t aarch64_atomic_xchg_8_impl; +extern aarch64_atomic_stub_t aarch64_atomic_cmpxchg_1_impl; +extern aarch64_atomic_stub_t aarch64_atomic_cmpxchg_4_impl; +extern aarch64_atomic_stub_t aarch64_atomic_cmpxchg_8_impl; +extern aarch64_atomic_stub_t aarch64_atomic_cmpxchg_1_relaxed_impl; +extern aarch64_atomic_stub_t aarch64_atomic_cmpxchg_4_relaxed_impl; +extern aarch64_atomic_stub_t aarch64_atomic_cmpxchg_8_relaxed_impl; + +#endif // CPU_AARCH64_ATOMIC_AARCH64_HPP
diff --git a/src/hotspot/cpu/aarch64/c1_CodeStubs_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_CodeStubs_aarch64.cpp index fca142f..09f5ded 100644 --- a/src/hotspot/cpu/aarch64/c1_CodeStubs_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/c1_CodeStubs_aarch64.cpp
@@ -50,13 +50,13 @@ } RangeCheckStub::RangeCheckStub(CodeEmitInfo* info, LIR_Opr index, LIR_Opr array) - : _throw_index_out_of_bounds_exception(false), _index(index), _array(array) { + : _index(index), _array(array), _throw_index_out_of_bounds_exception(false) { assert(info != NULL, "must have info"); _info = new CodeEmitInfo(info); } RangeCheckStub::RangeCheckStub(CodeEmitInfo* info, LIR_Opr index) - : _throw_index_out_of_bounds_exception(true), _index(index), _array(NULL) { + : _index(index), _array(NULL), _throw_index_out_of_bounds_exception(true) { assert(info != NULL, "must have info"); _info = new CodeEmitInfo(info); }
diff --git a/src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp index abb57ff..8bf36e7 100644 --- a/src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp
@@ -49,6 +49,8 @@ opr = as_oop_opr(reg); } else if (type == T_METADATA) { opr = as_metadata_opr(reg); + } else if (type == T_ADDRESS) { + opr = as_address_opr(reg); } else { opr = as_opr(reg); }
diff --git a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp index c4a8288..0120ebd 100644 --- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, Red Hat Inc. All rights reserved. + * Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -34,6 +34,7 @@ #include "c1/c1_ValueStack.hpp" #include "ci/ciArrayKlass.hpp" #include "ci/ciInstance.hpp" +#include "code/compiledIC.hpp" #include "gc/shared/barrierSet.hpp" #include "gc/shared/cardTableBarrierSet.hpp" #include "gc/shared/collectedHeap.hpp" @@ -41,6 +42,7 @@ #include "oops/objArrayKlass.hpp" #include "runtime/frame.inline.hpp" #include "runtime/sharedRuntime.hpp" +#include "utilities/macros.hpp" #include "vmreg_aarch64.inline.hpp" @@ -224,6 +226,19 @@ // FIXME: This needs to be much more clever. See x86. } +// Ensure a valid Address (base + offset) to a stack-slot. If stack access is +// not encodable as a base + (immediate) offset, generate an explicit address +// calculation to hold the address in a temporary register. +Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) { + precond(size == 4 || size == 8); + Address addr = frame_map()->address_for_slot(index, adjust); + precond(addr.getMode() == Address::base_plus_offset); + precond(addr.base() == sp); + precond(addr.offset() > 0); + uint mask = size - 1; + assert((addr.offset() & mask) == 0, "scaled offsets only"); + return __ legitimize_address(addr, size, tmp); +} void LIR_Assembler::osr_entry() { offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); @@ -434,12 +449,9 @@ } if (compilation()->env()->dtrace_method_probes()) { - __ call_Unimplemented(); -#if 0 - __ movptr(Address(rsp, 0), rax); - __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding()); - __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); -#endif + __ mov(c_rarg0, rthread); + __ mov_metadata(c_rarg1, method()->constant_encoding()); + __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1); } if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { @@ -743,32 +755,38 @@ } void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { + precond(src->is_register() && dest->is_stack()); + + uint const c_sz32 = sizeof(uint32_t); + uint const c_sz64 = sizeof(uint64_t); + if (src->is_single_cpu()) { + int index = dest->single_stack_ix(); if (type == T_ARRAY || type == T_OBJECT) { - __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix())); + __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1)); __ verify_oop(src->as_register()); - } else if (type == T_METADATA || type == T_DOUBLE) { - __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix())); + } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) { + __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1)); } else { - __ strw(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix())); + __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1)); } } else if (src->is_double_cpu()) { - Address dest_addr_LO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); + int index = dest->double_stack_ix(); + Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes); __ str(src->as_register_lo(), dest_addr_LO); } else if (src->is_single_fpu()) { - Address dest_addr = frame_map()->address_for_slot(dest->single_stack_ix()); - __ strs(src->as_float_reg(), dest_addr); + int index = dest->single_stack_ix(); + __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1)); } else if (src->is_double_fpu()) { - Address dest_addr = frame_map()->address_for_slot(dest->double_stack_ix()); - __ strd(src->as_double_reg(), dest_addr); + int index = dest->double_stack_ix(); + __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1)); } else { ShouldNotReachHere(); } - } @@ -853,30 +871,34 @@ void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { - assert(src->is_stack(), "should not call otherwise"); - assert(dest->is_register(), "should not call otherwise"); + precond(src->is_stack() && dest->is_register()); + + uint const c_sz32 = sizeof(uint32_t); + uint const c_sz64 = sizeof(uint64_t); if (dest->is_single_cpu()) { + int index = src->single_stack_ix(); if (type == T_ARRAY || type == T_OBJECT) { - __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); + __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1)); __ verify_oop(dest->as_register()); - } else if (type == T_METADATA) { - __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); + } else if (type == T_METADATA || type == T_ADDRESS) { + __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1)); } else { - __ ldrw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); + __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1)); } } else if (dest->is_double_cpu()) { - Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); + int index = src->double_stack_ix(); + Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes); __ ldr(dest->as_register_lo(), src_addr_LO); } else if (dest->is_single_fpu()) { - Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); - __ ldrs(dest->as_float_reg(), src_addr); + int index = src->single_stack_ix(); + __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1)); } else if (dest->is_double_fpu()) { - Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); - __ ldrd(dest->as_double_reg(), src_addr); + int index = src->double_stack_ix(); + __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1)); } else { ShouldNotReachHere(); @@ -1025,37 +1047,17 @@ return exact_log2(elem_size); } -void LIR_Assembler::arithmetic_idiv(LIR_Op3* op, bool is_irem) { - Register Rdividend = op->in_opr1()->as_register(); - Register Rdivisor = op->in_opr2()->as_register(); - Register Rscratch = op->in_opr3()->as_register(); - Register Rresult = op->result_opr()->as_register(); - int divisor = -1; - - /* - TODO: For some reason, using the Rscratch that gets passed in is - not possible because the register allocator does not see the tmp reg - as used, and assignes it the same register as Rdividend. We use rscratch1 - instead. - - assert(Rdividend != Rscratch, ""); - assert(Rdivisor != Rscratch, ""); - */ - - if (Rdivisor == noreg && is_power_of_2(divisor)) { - // convert division by a power of two into some shifts and logical operations - } - - __ corrected_idivl(Rresult, Rdividend, Rdivisor, is_irem, rscratch1); -} void LIR_Assembler::emit_op3(LIR_Op3* op) { switch (op->code()) { case lir_idiv: - arithmetic_idiv(op, false); - break; case lir_irem: - arithmetic_idiv(op, true); + arithmetic_idiv(op->code(), + op->in_opr1(), + op->in_opr2(), + op->in_opr3(), + op->result_opr(), + op->info()); break; case lir_fmad: __ fmaddd(op->result_opr()->as_double_reg(), @@ -1090,8 +1092,8 @@ // Assembler::EQ does not permit unordered branches, so we add // another branch here. Likewise, Assembler::NE does not permit // ordered branches. - if (is_unordered && op->cond() == lir_cond_equal - || !is_unordered && op->cond() == lir_cond_notEqual) + if ((is_unordered && op->cond() == lir_cond_equal) + || (!is_unordered && op->cond() == lir_cond_notEqual)) __ br(Assembler::VS, *(op->ublock()->label())); switch(op->cond()) { case lir_cond_equal: acond = Assembler::EQ; break; @@ -1376,7 +1378,7 @@ __ load_klass(klass_RInfo, obj); if (k->is_loaded()) { // See if we get an immediate positive hit - __ ldr(rscratch1, Address(klass_RInfo, long(k->super_check_offset()))); + __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset()))); __ cmp(k_RInfo, rscratch1); if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { __ br(Assembler::NE, *failure_target); @@ -1753,16 +1755,43 @@ } } else if (right->is_constant()) { - jlong c = right->as_constant_ptr()->as_jlong_bits(); + jlong c = right->as_constant_ptr()->as_jlong(); Register dreg = as_reg(dest); - assert(code == lir_add || code == lir_sub, "mismatched arithmetic op"); - if (c == 0 && dreg == lreg_lo) { - COMMENT("effective nop elided"); - return; - } switch (code) { - case lir_add: __ add(dreg, lreg_lo, c); break; - case lir_sub: __ sub(dreg, lreg_lo, c); break; + case lir_add: + case lir_sub: + if (c == 0 && dreg == lreg_lo) { + COMMENT("effective nop elided"); + return; + } + code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c); + break; + case lir_div: + assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant"); + if (c == 1) { + // move lreg_lo to dreg if divisor is 1 + __ mov(dreg, lreg_lo); + } else { + unsigned int shift = exact_log2_long(c); + // use rscratch1 as intermediate result register + __ asr(rscratch1, lreg_lo, 63); + __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift); + __ asr(dreg, rscratch1, shift); + } + break; + case lir_rem: + assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant"); + if (c == 1) { + // move 0 to dreg if divisor is 1 + __ mov(dreg, zr); + } else { + // use rscratch1 as intermediate result register + __ negs(rscratch1, lreg_lo); + __ andr(dreg, lreg_lo, c - 1); + __ andr(rscratch1, rscratch1, c - 1); + __ csneg(dreg, dreg, rscratch1, Assembler::MI); + } + break; default: ShouldNotReachHere(); } @@ -1774,18 +1803,22 @@ switch (code) { case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; + case lir_mul_strictfp: // fall through case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; + case lir_div_strictfp: // fall through case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; default: ShouldNotReachHere(); } } else if (left->is_double_fpu()) { if (right->is_double_fpu()) { - // cpu register - cpu register + // fpu register - fpu register switch (code) { case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; + case lir_mul_strictfp: // fall through case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; + case lir_div_strictfp: // fall through case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; default: ShouldNotReachHere(); @@ -1863,7 +1896,51 @@ -void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { Unimplemented(); } +void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) { + + // opcode check + assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem"); + bool is_irem = (code == lir_irem); + + // operand check + assert(left->is_single_cpu(), "left must be register"); + assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); + assert(result->is_single_cpu(), "result must be register"); + Register lreg = left->as_register(); + Register dreg = result->as_register(); + + // power-of-2 constant check and codegen + if (right->is_constant()) { + int c = right->as_constant_ptr()->as_jint(); + assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant"); + if (is_irem) { + if (c == 1) { + // move 0 to dreg if divisor is 1 + __ movw(dreg, zr); + } else { + // use rscratch1 as intermediate result register + __ negsw(rscratch1, lreg); + __ andw(dreg, lreg, c - 1); + __ andw(rscratch1, rscratch1, c - 1); + __ csnegw(dreg, dreg, rscratch1, Assembler::MI); + } + } else { + if (c == 1) { + // move lreg to dreg if divisor is 1 + __ movw(dreg, lreg); + } else { + unsigned int shift = exact_log2(c); + // use rscratch1 as intermediate result register + __ asrw(rscratch1, lreg, 31); + __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift); + __ asrw(dreg, rscratch1, shift); + } + } + } else { + Register rreg = right->as_register(); + __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1); + } +} void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { @@ -1907,6 +1984,9 @@ case T_ADDRESS: imm = opr2->as_constant_ptr()->as_jint(); break; + case T_METADATA: + imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata()); + break; case T_OBJECT: case T_ARRAY: jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1); @@ -1962,7 +2042,7 @@ } else if (code == lir_cmp_l2i) { Label done; __ cmp(left->as_register_lo(), right->as_register_lo()); - __ mov(dst->as_register(), (u_int64_t)-1L); + __ mov(dst->as_register(), (uint64_t)-1L); __ br(Assembler::LT, done); __ csinc(dst->as_register(), zr, zr, Assembler::EQ); __ bind(done); @@ -2012,11 +2092,10 @@ int start = __ offset(); __ relocate(static_stub_Relocation::spec(call_pc)); - __ mov_metadata(rmethod, (Metadata*)NULL); - __ movptr(rscratch1, 0); - __ br(rscratch1); + __ emit_static_call_stub(); - assert(__ offset() - start <= call_stub_size(), "stub too big"); + assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size() + <= call_stub_size(), "stub too big"); __ end_a_stub(); } @@ -2032,6 +2111,13 @@ // get current pc information // pc is only needed if the method has an exception handler, the unwind code does not need it. + if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) { + // As no instructions have been generated yet for this LIR node it's + // possible that an oop map already exists for the current offset. + // In that case insert an dummy NOP here to ensure all oop map PCs + // are unique. See JDK-8237483. + __ nop(); + } int pc_for_athrow_offset = __ offset(); InternalAddress pc_for_athrow(__ pc()); __ adr(exceptionPC->as_register(), pc_for_athrow); @@ -2228,7 +2314,6 @@ assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); int elem_size = type2aelembytes(basic_type); - int shift_amount; int scale = exact_log2(elem_size); Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); @@ -2618,7 +2703,7 @@ Register res = op->result_opr()->as_register(); assert_different_registers(val, crc, res); - unsigned long offset; + uint64_t offset; __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset); if (offset) __ add(res, res, offset); @@ -2765,7 +2850,7 @@ } #endif // first time here. Set profile type. - __ ldr(tmp, mdo_addr); + __ str(tmp, mdo_addr); } else { assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); @@ -2811,6 +2896,12 @@ void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { +#if INCLUDE_SHENANDOAHGC + if (UseShenandoahGC && patch_code != lir_patch_none) { + deoptimize_trap(info); + return; + } +#endif assert(patch_code == lir_patch_none, "Patch code not supported"); __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr())); } @@ -2824,40 +2915,7 @@ __ far_call(RuntimeAddress(dest)); } else { __ mov(rscratch1, RuntimeAddress(dest)); - int len = args->length(); - int type = 0; - if (! result->is_illegal()) { - switch (result->type()) { - case T_VOID: - type = 0; - break; - case T_INT: - case T_LONG: - case T_OBJECT: - type = 1; - break; - case T_FLOAT: - type = 2; - break; - case T_DOUBLE: - type = 3; - break; - default: - ShouldNotReachHere(); - break; - } - } - int num_gpargs = 0; - int num_fpargs = 0; - for (int i = 0; i < args->length(); i++) { - LIR_Opr arg = args->at(i); - if (arg->type() == T_FLOAT || arg->type() == T_DOUBLE) { - num_fpargs++; - } else { - num_gpargs++; - } - } - __ blrt(rscratch1, num_gpargs, num_fpargs, type); + __ blr(rscratch1); } if (info != NULL) {
diff --git a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.hpp index 95b89dd..b3597ce 100644 --- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.hpp
@@ -45,10 +45,12 @@ bool is_literal_address(LIR_Address* addr); - // When we need to use something other than rscratch1 use this - // method. + // When we need to use something other than rscratch1 use this method. Address as_Address(LIR_Address* addr, Register tmp); + // Ensure we have a valid Address (base+offset) to a stack-slot. + Address stack_slot_address(int index, uint shift, Register tmp, int adjust = 0); + // Record the type of the receiver in ReceiverTypeData void type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data, @@ -69,14 +71,14 @@ void deoptimize_trap(CodeEmitInfo *info); enum { - _call_stub_size = 12 * NativeInstruction::instruction_size, + // call stub: CompiledStaticCall::to_interp_stub_size() + + // CompiledStaticCall::to_trampoline_stub_size() + _call_stub_size = 13 * NativeInstruction::instruction_size, _call_aot_stub_size = 0, _exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(175), _deopt_handler_size = 7 * NativeInstruction::instruction_size }; - void arithmetic_idiv(LIR_Op3* op, bool is_irem); - public: void store_parameter(Register r, int offset_from_esp_in_words);
diff --git a/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp index e9e6af9..a469763 100644 --- a/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2014, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * @@ -173,10 +173,10 @@ if (large_disp != 0) { LIR_Opr tmp = new_pointer_register(); if (Assembler::operand_valid_for_add_sub_immediate(large_disp)) { - __ add(tmp, tmp, LIR_OprFact::intptrConst(large_disp)); + __ add(index, LIR_OprFact::intptrConst(large_disp), tmp); index = tmp; } else { - __ move(tmp, LIR_OprFact::intptrConst(large_disp)); + __ move(LIR_OprFact::intptrConst(large_disp), tmp); __ add(tmp, index, tmp); index = tmp; } @@ -190,7 +190,7 @@ } // at this point we either have base + index or base + displacement - if (large_disp == 0) { + if (large_disp == 0 && index->is_register()) { return new LIR_Address(base, index, type); } else { assert(Address::offset_ok_for_immed(large_disp, 0), "must be"); @@ -290,7 +290,7 @@ } -bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) { +bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { if (is_power_of_2(c - 1)) { __ shift_left(left, exact_log2(c - 1), tmp); @@ -426,7 +426,7 @@ tmp = new_register(T_DOUBLE); } - arithmetic_op_fpu(x->op(), reg, left.result(), right.result(), NULL); + arithmetic_op_fpu(x->op(), reg, left.result(), right.result(), x->is_strictfp()); set_result(x, round_item(reg)); } @@ -440,17 +440,26 @@ if (x->op() == Bytecodes::_ldiv || x->op() == Bytecodes::_lrem) { - // the check for division by zero destroys the right operand - right.set_destroys_register(); - - // check for division by zero (destroys registers of right operand!) - CodeEmitInfo* info = state_for(x); - left.load_item(); - right.load_item(); - - __ cmp(lir_cond_equal, right.result(), LIR_OprFact::longConst(0)); - __ branch(lir_cond_equal, T_LONG, new DivByZeroStub(info)); + bool need_zero_check = true; + if (right.is_constant()) { + jlong c = right.get_jlong_constant(); + // no need to do div-by-zero check if the divisor is a non-zero constant + if (c != 0) need_zero_check = false; + // do not load right if the divisor is a power-of-2 constant + if (c > 0 && is_power_of_2_long(c)) { + right.dont_load_item(); + } else { + right.load_item(); + } + } else { + right.load_item(); + } + if (need_zero_check) { + CodeEmitInfo* info = state_for(x); + __ cmp(lir_cond_equal, right.result(), LIR_OprFact::longConst(0)); + __ branch(lir_cond_equal, T_LONG, new DivByZeroStub(info)); + } rlock_result(x); switch (x->op()) { @@ -506,19 +515,32 @@ // do not need to load right, as we can handle stack and constants if (x->op() == Bytecodes::_idiv || x->op() == Bytecodes::_irem) { - right_arg->load_item(); rlock_result(x); + bool need_zero_check = true; + if (right.is_constant()) { + jint c = right.get_jint_constant(); + // no need to do div-by-zero check if the divisor is a non-zero constant + if (c != 0) need_zero_check = false; + // do not load right if the divisor is a power-of-2 constant + if (c > 0 && is_power_of_2(c)) { + right_arg->dont_load_item(); + } else { + right_arg->load_item(); + } + } else { + right_arg->load_item(); + } + if (need_zero_check) { + CodeEmitInfo* info = state_for(x); + __ cmp(lir_cond_equal, right_arg->result(), LIR_OprFact::longConst(0)); + __ branch(lir_cond_equal, T_INT, new DivByZeroStub(info)); + } - CodeEmitInfo* info = state_for(x); - LIR_Opr tmp = new_register(T_INT); - __ cmp(lir_cond_equal, right_arg->result(), LIR_OprFact::longConst(0)); - __ branch(lir_cond_equal, T_INT, new DivByZeroStub(info)); - info = state_for(x); - + LIR_Opr ill = LIR_OprFact::illegalOpr; if (x->op() == Bytecodes::_irem) { - __ irem(left_arg->result(), right_arg->result(), x->operand(), tmp, NULL); + __ irem(left_arg->result(), right_arg->result(), x->operand(), ill, NULL); } else if (x->op() == Bytecodes::_idiv) { - __ idiv(left_arg->result(), right_arg->result(), x->operand(), tmp, NULL); + __ idiv(left_arg->result(), right_arg->result(), x->operand(), ill, NULL); } } else if (x->op() == Bytecodes::_iadd || x->op() == Bytecodes::_isub) {
diff --git a/src/hotspot/cpu/aarch64/c1_MacroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_MacroAssembler_aarch64.cpp index ccc7050..218113b 100644 --- a/src/hotspot/cpu/aarch64/c1_MacroAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/c1_MacroAssembler_aarch64.cpp
@@ -341,16 +341,10 @@ // Note that we do this before doing an enter(). generate_stack_overflow_check(bang_size_in_bytes); MacroAssembler::build_frame(framesize + 2 * wordSize); - if (NotifySimulator) { - notify(Assembler::method_entry); - } } void C1_MacroAssembler::remove_frame(int framesize) { MacroAssembler::remove_frame(framesize + 2 * wordSize); - if (NotifySimulator) { - notify(Assembler::method_reentry); - } }
diff --git a/src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp index 3fd2bd9..77658aa 100644 --- a/src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 1999, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2014, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * @@ -62,7 +62,7 @@ // do the call lea(rscratch1, RuntimeAddress(entry)); - blrt(rscratch1, args_size + 1, 8, 1); + blr(rscratch1); bind(retaddr); int call_offset = offset(); // verify callee-saved register @@ -141,9 +141,9 @@ int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) { // if there is any conflict use the stack if (arg1 == c_rarg2 || arg1 == c_rarg3 || - arg2 == c_rarg1 || arg1 == c_rarg3 || - arg3 == c_rarg1 || arg1 == c_rarg2) { - stp(arg3, arg2, Address(pre(sp, 2 * wordSize))); + arg2 == c_rarg1 || arg2 == c_rarg3 || + arg3 == c_rarg1 || arg3 == c_rarg2) { + stp(arg3, arg2, Address(pre(sp, -2 * wordSize))); stp(arg1, zr, Address(pre(sp, -2 * wordSize))); ldp(c_rarg1, zr, Address(post(sp, 2 * wordSize))); ldp(c_rarg3, c_rarg2, Address(post(sp, 2 * wordSize))); @@ -537,7 +537,7 @@ __ set_last_Java_frame(sp, rfp, retaddr, rscratch1); // do the call __ lea(rscratch1, RuntimeAddress(target)); - __ blrt(rscratch1, 1, 0, 1); + __ blr(rscratch1); __ bind(retaddr); OopMapSet* oop_maps = new OopMapSet(); oop_maps->add_gc_map(__ offset(), oop_map); @@ -839,6 +839,7 @@ __ sub(arr_size, arr_size, t1); // body length __ add(t1, t1, obj); // body start __ initialize_body(t1, arr_size, 0, t2); + __ membar(Assembler::StoreStore); __ verify_oop(obj); __ ret(lr); @@ -1122,6 +1123,16 @@ } break; + case dtrace_object_alloc_id: + { // c_rarg0: object + StubFrame f(sasm, "dtrace_object_alloc", dont_gc_arguments); + save_live_registers(sasm); + + __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc), c_rarg0); + + restore_live_registers(sasm); + } + break; default: { StubFrame f(sasm, "unimplemented entry", dont_gc_arguments);
diff --git a/src/hotspot/cpu/aarch64/c1_globals_aarch64.hpp b/src/hotspot/cpu/aarch64/c1_globals_aarch64.hpp index 3177a89..44608fe 100644 --- a/src/hotspot/cpu/aarch64/c1_globals_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/c1_globals_aarch64.hpp
@@ -41,13 +41,7 @@ define_pd_global(bool, ProfileTraps, false); define_pd_global(bool, UseOnStackReplacement, true ); define_pd_global(bool, TieredCompilation, false); -#ifdef BUILTIN_SIM -// We compile very aggressively with the builtin simulator because -// doing so greatly reduces run times and tests more code. -define_pd_global(intx, CompileThreshold, 150 ); -#else define_pd_global(intx, CompileThreshold, 1500 ); -#endif define_pd_global(intx, OnStackReplacePercentage, 933 ); define_pd_global(intx, FreqInlineSize, 325 );
diff --git a/src/hotspot/cpu/aarch64/c2_globals_aarch64.hpp b/src/hotspot/cpu/aarch64/c2_globals_aarch64.hpp index bb242a7..f78faba 100644 --- a/src/hotspot/cpu/aarch64/c2_globals_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/c2_globals_aarch64.hpp
@@ -46,7 +46,7 @@ define_pd_global(intx, OnStackReplacePercentage, 140); define_pd_global(intx, ConditionalMoveLimit, 3); -define_pd_global(intx, FLOATPRESSURE, 64); +define_pd_global(intx, FLOATPRESSURE, 32); define_pd_global(intx, FreqInlineSize, 325); define_pd_global(intx, MinJumpTableSize, 10); define_pd_global(intx, INTPRESSURE, 24); @@ -76,7 +76,7 @@ define_pd_global(intx, NonProfiledCodeHeapSize, 21*M); define_pd_global(intx, ProfiledCodeHeapSize, 22*M); define_pd_global(intx, NonNMethodCodeHeapSize, 5*M ); -define_pd_global(uintx, CodeCacheMinBlockLength, 4); +define_pd_global(uintx, CodeCacheMinBlockLength, 6); define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K); // Heap related flags
diff --git a/src/hotspot/cpu/aarch64/compiledIC_aarch64.cpp b/src/hotspot/cpu/aarch64/compiledIC_aarch64.cpp index cc4d7d4..0bcb7fc 100644 --- a/src/hotspot/cpu/aarch64/compiledIC_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/compiledIC_aarch64.cpp
@@ -36,6 +36,9 @@ #define __ _masm. address CompiledStaticCall::emit_to_interp_stub(CodeBuffer &cbuf, address mark) { + precond(cbuf.stubs()->start() != badAddress); + precond(cbuf.stubs()->end() != badAddress); + // Stub is fixed up when the corresponding call is converted from // calling compiled code to calling interpreted code. // mov rmethod, 0 @@ -61,14 +64,14 @@ // Don't create a Metadata reloc if we're generating immutable PIC. if (cbuf.immutable_PIC()) { __ movptr(rmethod, 0); - } else { - __ mov_metadata(rmethod, (Metadata*)NULL); - } -#else - __ mov_metadata(rmethod, (Metadata*)NULL); + __ movptr(rscratch1, 0); + __ br(rscratch1); + + } else #endif - __ movptr(rscratch1, 0); - __ br(rscratch1); + { + __ emit_static_call_stub(); + } assert((__ offset() - offset) <= (int)to_interp_stub_size(), "stub too big"); __ end_a_stub(); @@ -77,7 +80,8 @@ #undef __ int CompiledStaticCall::to_interp_stub_size() { - return 7 * NativeInstruction::instruction_size; + // isb; movk; movz; movz; movk; movz; movz; br + return 8 * NativeInstruction::instruction_size; } int CompiledStaticCall::to_trampoline_stub_size() { @@ -159,7 +163,8 @@ } // Creation also verifies the object. - NativeMovConstReg* method_holder = nativeMovConstReg_at(stub); + NativeMovConstReg* method_holder + = nativeMovConstReg_at(stub + NativeInstruction::instruction_size); #ifndef PRODUCT NativeGeneralJump* jump = nativeGeneralJump_at(method_holder->next_instruction_address()); @@ -184,7 +189,8 @@ address stub = static_stub->addr(); assert(stub != NULL, "stub not found"); // Creation also verifies the object. - NativeMovConstReg* method_holder = nativeMovConstReg_at(stub); + NativeMovConstReg* method_holder + = nativeMovConstReg_at(stub + NativeInstruction::instruction_size); method_holder->set_data(0); } @@ -203,8 +209,9 @@ address stub = find_stub(false /* is_aot */); assert(stub != NULL, "no stub found for static call"); // Creation also verifies the object. - NativeMovConstReg* method_holder = nativeMovConstReg_at(stub); - NativeJump* jump = nativeJump_at(method_holder->next_instruction_address()); + NativeMovConstReg* method_holder + = nativeMovConstReg_at(stub + NativeInstruction::instruction_size); + NativeJump* jump = nativeJump_at(method_holder->next_instruction_address()); // Verify state. assert(is_clean() || is_call_to_compiled() || is_call_to_interpreted(), "sanity check");
diff --git a/src/hotspot/cpu/aarch64/cpustate_aarch64.hpp b/src/hotspot/cpu/aarch64/cpustate_aarch64.hpp deleted file mode 100644 index ce996e3..0000000 --- a/src/hotspot/cpu/aarch64/cpustate_aarch64.hpp +++ /dev/null
@@ -1,595 +0,0 @@ -/* - * Copyright (c) 2014, Red Hat Inc. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#ifndef _CPU_STATE_H -#define _CPU_STATE_H - -#include <sys/types.h> - -/* - * symbolic names used to identify general registers which also match - * the registers indices in machine code - * - * We have 32 general registers which can be read/written as 32 bit or - * 64 bit sources/sinks and are appropriately referred to as Wn or Xn - * in the assembly code. Some instructions mix these access modes - * (e.g. ADD X0, X1, W2) so the implementation of the instruction - * needs to *know* which type of read or write access is required. - */ -enum GReg { - R0, - R1, - R2, - R3, - R4, - R5, - R6, - R7, - R8, - R9, - R10, - R11, - R12, - R13, - R14, - R15, - R16, - R17, - R18, - R19, - R20, - R21, - R22, - R23, - R24, - R25, - R26, - R27, - R28, - R29, - R30, - R31, - // and now the aliases - RSCRATCH1=R8, - RSCRATCH2=R9, - RMETHOD=R12, - RESP=R20, - RDISPATCH=R21, - RBCP=R22, - RLOCALS=R24, - RMONITORS=R25, - RCPOOL=R26, - RHEAPBASE=R27, - RTHREAD=R28, - FP = R29, - LR = R30, - SP = R31, - ZR = R31 -}; - -/* - * symbolic names used to refer to floating point registers which also - * match the registers indices in machine code - * - * We have 32 FP registers which can be read/written as 8, 16, 32, 64 - * and 128 bit sources/sinks and are appropriately referred to as Bn, - * Hn, Sn, Dn and Qn in the assembly code. Some instructions mix these - * access modes (e.g. FCVT S0, D0) so the implementation of the - * instruction needs to *know* which type of read or write access is - * required. - */ - -enum VReg { - V0, - V1, - V2, - V3, - V4, - V5, - V6, - V7, - V8, - V9, - V10, - V11, - V12, - V13, - V14, - V15, - V16, - V17, - V18, - V19, - V20, - V21, - V22, - V23, - V24, - V25, - V26, - V27, - V28, - V29, - V30, - V31, -}; - -/** - * all the different integer bit patterns for the components of a - * general register are overlaid here using a union so as to allow all - * reading and writing of the desired bits. - * - * n.b. the ARM spec says that when you write a 32 bit register you - * are supposed to write the low 32 bits and zero the high 32 - * bits. But we don't actually have to care about this because Java - * will only ever consume the 32 bits value as a 64 bit quantity after - * an explicit extend. - */ -union GRegisterValue -{ - int8_t s8; - int16_t s16; - int32_t s32; - int64_t s64; - u_int8_t u8; - u_int16_t u16; - u_int32_t u32; - u_int64_t u64; -}; - -class GRegister -{ -public: - GRegisterValue value; -}; - -/* - * float registers provide for storage of a single, double or quad - * word format float in the same register. single floats are not - * paired within each double register as per 32 bit arm. instead each - * 128 bit register Vn embeds the bits for Sn, and Dn in the lower - * quarter and half, respectively, of the bits for Qn. - * - * The upper bits can also be accessed as single or double floats by - * the float vector operations using indexing e.g. V1.D[1], V1.S[3] - * etc and, for SIMD operations using a horrible index range notation. - * - * The spec also talks about accessing float registers as half words - * and bytes with Hn and Bn providing access to the low 16 and 8 bits - * of Vn but it is not really clear what these bits represent. We can - * probably ignore this for Java anyway. However, we do need to access - * the raw bits at 32 and 64 bit resolution to load to/from integer - * registers. - */ - -union FRegisterValue -{ - float s; - double d; - long double q; - // eventually we will need to be able to access the data as a vector - // the integral array elements allow us to access the bits in s, d, - // q, vs and vd at an appropriate level of granularity - u_int8_t vb[16]; - u_int16_t vh[8]; - u_int32_t vw[4]; - u_int64_t vx[2]; - float vs[4]; - double vd[2]; -}; - -class FRegister -{ -public: - FRegisterValue value; -}; - -/* - * CPSR register -- this does not exist as a directly accessible - * register but we need to store the flags so we can implement - * flag-seting and flag testing operations - * - * we can possibly use injected x86 asm to report the outcome of flag - * setting operations. if so we will need to grab the flags - * immediately after the operation in order to ensure we don't lose - * them because of the actions of the simulator. so we still need - * somewhere to store the condition codes. - */ - -class CPSRRegister -{ -public: - u_int32_t value; - -/* - * condition register bit select values - * - * the order of bits here is important because some of - * the flag setting conditional instructions employ a - * bit field to populate the flags when a false condition - * bypasses execution of the operation and we want to - * be able to assign the flags register using the - * supplied value. - */ - - enum CPSRIdx { - V_IDX, - C_IDX, - Z_IDX, - N_IDX - }; - - enum CPSRMask { - V = 1 << V_IDX, - C = 1 << C_IDX, - Z = 1 << Z_IDX, - N = 1 << N_IDX - }; - - static const int CPSR_ALL_FLAGS = (V | C | Z | N); -}; - -// auxiliary function to assemble the relevant bits from -// the x86 EFLAGS register into an ARM CPSR value - -#define X86_V_IDX 11 -#define X86_C_IDX 0 -#define X86_Z_IDX 6 -#define X86_N_IDX 7 - -#define X86_V (1 << X86_V_IDX) -#define X86_C (1 << X86_C_IDX) -#define X86_Z (1 << X86_Z_IDX) -#define X86_N (1 << X86_N_IDX) - -inline u_int32_t convertX86Flags(u_int32_t x86flags) -{ - u_int32_t flags; - // set N flag - flags = ((x86flags & X86_N) >> X86_N_IDX); - // shift then or in Z flag - flags <<= 1; - flags |= ((x86flags & X86_Z) >> X86_Z_IDX); - // shift then or in C flag - flags <<= 1; - flags |= ((x86flags & X86_C) >> X86_C_IDX); - // shift then or in V flag - flags <<= 1; - flags |= ((x86flags & X86_V) >> X86_V_IDX); - - return flags; -} - -inline u_int32_t convertX86FlagsFP(u_int32_t x86flags) -{ - // x86 flags set by fcomi(x,y) are ZF:PF:CF - // (yes, that's PF for parity, WTF?) - // where - // 0) 0:0:0 means x > y - // 1) 0:0:1 means x < y - // 2) 1:0:0 means x = y - // 3) 1:1:1 means x and y are unordered - // note that we don't have to check PF so - // we really have a simple 2-bit case switch - // the corresponding ARM64 flags settings - // in hi->lo bit order are - // 0) --C- - // 1) N--- - // 2) -ZC- - // 3) --CV - - static u_int32_t armFlags[] = { - 0b0010, - 0b1000, - 0b0110, - 0b0011 - }; - // pick out the ZF and CF bits - u_int32_t zc = ((x86flags & X86_Z) >> X86_Z_IDX); - zc <<= 1; - zc |= ((x86flags & X86_C) >> X86_C_IDX); - - return armFlags[zc]; -} - -/* - * FPSR register -- floating point status register - - * this register includes IDC, IXC, UFC, OFC, DZC, IOC and QC bits, - * and the floating point N, Z, C, V bits but the latter are unused in - * aarch64 mode. the sim ignores QC for now. - * - * bit positions are as per the ARMv7 FPSCR register - * - * IDC : 7 ==> Input Denormal (cumulative exception bit) - * IXC : 4 ==> Inexact - * UFC : 3 ==> Underflow - * OFC : 2 ==> Overflow - * DZC : 1 ==> Division by Zero - * IOC : 0 ==> Invalid Operation - */ - -class FPSRRegister -{ -public: - u_int32_t value; - // indices for bits in the FPSR register value - enum FPSRIdx { - IO_IDX = 0, - DZ_IDX = 1, - OF_IDX = 2, - UF_IDX = 3, - IX_IDX = 4, - ID_IDX = 7 - }; - // corresponding bits as numeric values - enum FPSRMask { - IO = (1 << IO_IDX), - DZ = (1 << DZ_IDX), - OF = (1 << OF_IDX), - UF = (1 << UF_IDX), - IX = (1 << IX_IDX), - ID = (1 << ID_IDX) - }; - static const int FPSR_ALL_FPSRS = (IO | DZ | OF | UF | IX | ID); -}; - -// debugger support - -enum PrintFormat -{ - FMT_DECIMAL, - FMT_HEX, - FMT_SINGLE, - FMT_DOUBLE, - FMT_QUAD, - FMT_MULTI -}; - -/* - * model of the registers and other state associated with the cpu - */ -class CPUState -{ - friend class AArch64Simulator; -private: - // this is the PC of the instruction being executed - u_int64_t pc; - // this is the PC of the instruction to be executed next - // it is defaulted to pc + 4 at instruction decode but - // execute may reset it - - u_int64_t nextpc; - GRegister gr[33]; // extra register at index 32 is used - // to hold zero value - FRegister fr[32]; - CPSRRegister cpsr; - FPSRRegister fpsr; - -public: - - CPUState() { - gr[20].value.u64 = 0; // establish initial condition for - // checkAssertions() - trace_counter = 0; - } - - // General Register access macros - - // only xreg or xregs can be used as an lvalue in order to update a - // register. this ensures that the top part of a register is always - // assigned when it is written by the sim. - - inline u_int64_t &xreg(GReg reg, int r31_is_sp) { - if (reg == R31 && !r31_is_sp) { - return gr[32].value.u64; - } else { - return gr[reg].value.u64; - } - } - - inline int64_t &xregs(GReg reg, int r31_is_sp) { - if (reg == R31 && !r31_is_sp) { - return gr[32].value.s64; - } else { - return gr[reg].value.s64; - } - } - - inline u_int32_t wreg(GReg reg, int r31_is_sp) { - if (reg == R31 && !r31_is_sp) { - return gr[32].value.u32; - } else { - return gr[reg].value.u32; - } - } - - inline int32_t wregs(GReg reg, int r31_is_sp) { - if (reg == R31 && !r31_is_sp) { - return gr[32].value.s32; - } else { - return gr[reg].value.s32; - } - } - - inline u_int32_t hreg(GReg reg, int r31_is_sp) { - if (reg == R31 && !r31_is_sp) { - return gr[32].value.u16; - } else { - return gr[reg].value.u16; - } - } - - inline int32_t hregs(GReg reg, int r31_is_sp) { - if (reg == R31 && !r31_is_sp) { - return gr[32].value.s16; - } else { - return gr[reg].value.s16; - } - } - - inline u_int32_t breg(GReg reg, int r31_is_sp) { - if (reg == R31 && !r31_is_sp) { - return gr[32].value.u8; - } else { - return gr[reg].value.u8; - } - } - - inline int32_t bregs(GReg reg, int r31_is_sp) { - if (reg == R31 && !r31_is_sp) { - return gr[32].value.s8; - } else { - return gr[reg].value.s8; - } - } - - // FP Register access macros - - // all non-vector accessors return a reference so we can both read - // and assign - - inline float &sreg(VReg reg) { - return fr[reg].value.s; - } - - inline double &dreg(VReg reg) { - return fr[reg].value.d; - } - - inline long double &qreg(VReg reg) { - return fr[reg].value.q; - } - - // all vector register accessors return a pointer - - inline float *vsreg(VReg reg) { - return &fr[reg].value.vs[0]; - } - - inline double *vdreg(VReg reg) { - return &fr[reg].value.vd[0]; - } - - inline u_int8_t *vbreg(VReg reg) { - return &fr[reg].value.vb[0]; - } - - inline u_int16_t *vhreg(VReg reg) { - return &fr[reg].value.vh[0]; - } - - inline u_int32_t *vwreg(VReg reg) { - return &fr[reg].value.vw[0]; - } - - inline u_int64_t *vxreg(VReg reg) { - return &fr[reg].value.vx[0]; - } - - union GRegisterValue prev_sp, prev_fp; - - static const int trace_size = 256; - u_int64_t trace_buffer[trace_size]; - int trace_counter; - - bool checkAssertions() - { - // Make sure that SP is 16-aligned - // Also make sure that ESP is above SP. - // We don't care about checking ESP if it is null, i.e. it hasn't - // been used yet. - if (gr[31].value.u64 & 0x0f) { - asm volatile("nop"); - return false; - } - return true; - } - - // pc register accessors - - // this instruction can be used to fetch the current PC - u_int64_t getPC(); - // instead of setting the current PC directly you can - // first set the next PC (either absolute or PC-relative) - // and later copy the next PC into the current PC - // this supports a default increment by 4 at instruction - // fetch with an optional reset by control instructions - u_int64_t getNextPC(); - void setNextPC(u_int64_t next); - void offsetNextPC(int64_t offset); - // install nextpc as current pc - void updatePC(); - - // this instruction can be used to save the next PC to LR - // just before installing a branch PC - inline void saveLR() { gr[LR].value.u64 = nextpc; } - - // cpsr register accessors - u_int32_t getCPSRRegister(); - void setCPSRRegister(u_int32_t flags); - // read a specific subset of the flags as a bit pattern - // mask should be composed using elements of enum FlagMask - u_int32_t getCPSRBits(u_int32_t mask); - // assign a specific subset of the flags as a bit pattern - // mask and value should be composed using elements of enum FlagMask - void setCPSRBits(u_int32_t mask, u_int32_t value); - // test the value of a single flag returned as 1 or 0 - u_int32_t testCPSR(CPSRRegister::CPSRIdx idx); - // set a single flag - void setCPSR(CPSRRegister::CPSRIdx idx); - // clear a single flag - void clearCPSR(CPSRRegister::CPSRIdx idx); - // utility method to set ARM CSPR flags from an x86 bit mask generated by integer arithmetic - void setCPSRRegisterFromX86(u_int64_t x86Flags); - // utility method to set ARM CSPR flags from an x86 bit mask generated by floating compare - void setCPSRRegisterFromX86FP(u_int64_t x86Flags); - - // fpsr register accessors - u_int32_t getFPSRRegister(); - void setFPSRRegister(u_int32_t flags); - // read a specific subset of the fprs bits as a bit pattern - // mask should be composed using elements of enum FPSRRegister::FlagMask - u_int32_t getFPSRBits(u_int32_t mask); - // assign a specific subset of the flags as a bit pattern - // mask and value should be composed using elements of enum FPSRRegister::FlagMask - void setFPSRBits(u_int32_t mask, u_int32_t value); - // test the value of a single flag returned as 1 or 0 - u_int32_t testFPSR(FPSRRegister::FPSRIdx idx); - // set a single flag - void setFPSR(FPSRRegister::FPSRIdx idx); - // clear a single flag - void clearFPSR(FPSRRegister::FPSRIdx idx); - - // debugger support - void printPC(int pending, const char *trailing = "\n"); - void printInstr(u_int32_t instr, void (*dasm)(u_int64_t), const char *trailing = "\n"); - void printGReg(GReg reg, PrintFormat format = FMT_HEX, const char *trailing = "\n"); - void printVReg(VReg reg, PrintFormat format = FMT_HEX, const char *trailing = "\n"); - void printCPSR(const char *trailing = "\n"); - void printFPSR(const char *trailing = "\n"); - void dumpState(); -}; - -#endif // ifndef _CPU_STATE_H
diff --git a/src/hotspot/cpu/aarch64/decode_aarch64.hpp b/src/hotspot/cpu/aarch64/decode_aarch64.hpp deleted file mode 100644 index e93924d..0000000 --- a/src/hotspot/cpu/aarch64/decode_aarch64.hpp +++ /dev/null
@@ -1,412 +0,0 @@ -/* - * Copyright (c) 2014, Red Hat Inc. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#ifndef _DECODE_H -#define _DECODE_H - -#include <sys/types.h> -#include "cpustate_aarch64.hpp" - -// bitfield immediate expansion helper - -extern int expandLogicalImmediate(u_int32_t immN, u_int32_t immr, - u_int32_t imms, u_int64_t &bimm); - - -/* - * codes used in conditional instructions - * - * these are passed to conditional operations to identify which - * condition to test for - */ -enum CondCode { - EQ = 0b0000, // meaning Z == 1 - NE = 0b0001, // meaning Z == 0 - HS = 0b0010, // meaning C == 1 - CS = HS, - LO = 0b0011, // meaning C == 0 - CC = LO, - MI = 0b0100, // meaning N == 1 - PL = 0b0101, // meaning N == 0 - VS = 0b0110, // meaning V == 1 - VC = 0b0111, // meaning V == 0 - HI = 0b1000, // meaning C == 1 && Z == 0 - LS = 0b1001, // meaning !(C == 1 && Z == 0) - GE = 0b1010, // meaning N == V - LT = 0b1011, // meaning N != V - GT = 0b1100, // meaning Z == 0 && N == V - LE = 0b1101, // meaning !(Z == 0 && N == V) - AL = 0b1110, // meaning ANY - NV = 0b1111 // ditto -}; - -/* - * certain addressing modes for load require pre or post writeback of - * the computed address to a base register - */ -enum WriteBack { - Post = 0, - Pre = 1 -}; - -/* - * certain addressing modes for load require an offset to - * be optionally scaled so the decode needs to pass that - * through to the execute routine - */ -enum Scaling { - Unscaled = 0, - Scaled = 1 -}; - -/* - * when we do have to scale we do so by shifting using - * log(bytes in data element - 1) as the shift count. - * so we don't have to scale offsets when loading - * bytes. - */ -enum ScaleShift { - ScaleShift16 = 1, - ScaleShift32 = 2, - ScaleShift64 = 3, - ScaleShift128 = 4 -}; - -/* - * one of the addressing modes for load requires a 32-bit register - * value to be either zero- or sign-extended for these instructions - * UXTW or SXTW should be passed - * - * arithmetic register data processing operations can optionally - * extend a portion of the second register value for these - * instructions the value supplied must identify the portion of the - * register which is to be zero- or sign-exended - */ -enum Extension { - UXTB = 0, - UXTH = 1, - UXTW = 2, - UXTX = 3, - SXTB = 4, - SXTH = 5, - SXTW = 6, - SXTX = 7 -}; - -/* - * arithmetic and logical register data processing operations - * optionally perform a shift on the second register value - */ -enum Shift { - LSL = 0, - LSR = 1, - ASR = 2, - ROR = 3 -}; - -/* - * bit twiddling helpers for instruction decode - */ - -// 32 bit mask with bits [hi,...,lo] set - -static inline u_int32_t mask32(int hi = 31, int lo = 0) -{ - int nbits = (hi + 1) - lo; - return ((1 << nbits) - 1) << lo; -} - -static inline u_int64_t mask64(int hi = 63, int lo = 0) -{ - int nbits = (hi + 1) - lo; - return ((1L << nbits) - 1) << lo; -} - -// pick bits [hi,...,lo] from val -static inline u_int32_t pick32(u_int32_t val, int hi = 31, int lo = 0) -{ - return (val & mask32(hi, lo)); -} - -// pick bits [hi,...,lo] from val -static inline u_int64_t pick64(u_int64_t val, int hi = 31, int lo = 0) -{ - return (val & mask64(hi, lo)); -} - -// pick bits [hi,...,lo] from val and shift to [(hi-(newlo - lo)),newlo] -static inline u_int32_t pickshift32(u_int32_t val, int hi = 31, - int lo = 0, int newlo = 0) -{ - u_int32_t bits = pick32(val, hi, lo); - if (lo < newlo) { - return (bits << (newlo - lo)); - } else { - return (bits >> (lo - newlo)); - } -} -// mask [hi,lo] and shift down to start at bit 0 -static inline u_int32_t pickbits32(u_int32_t val, int hi = 31, int lo = 0) -{ - return (pick32(val, hi, lo) >> lo); -} - -// mask [hi,lo] and shift down to start at bit 0 -static inline u_int64_t pickbits64(u_int64_t val, int hi = 63, int lo = 0) -{ - return (pick64(val, hi, lo) >> lo); -} - -/* - * decode registers, immediates and constants of various types - */ - -static inline GReg greg(u_int32_t val, int lo) -{ - return (GReg)pickbits32(val, lo + 4, lo); -} - -static inline VReg vreg(u_int32_t val, int lo) -{ - return (VReg)pickbits32(val, lo + 4, lo); -} - -static inline u_int32_t uimm(u_int32_t val, int hi, int lo) -{ - return pickbits32(val, hi, lo); -} - -static inline int32_t simm(u_int32_t val, int hi = 31, int lo = 0) { - union { - u_int32_t u; - int32_t n; - }; - - u = val << (31 - hi); - n = n >> (31 - hi + lo); - return n; -} - -static inline int64_t simm(u_int64_t val, int hi = 63, int lo = 0) { - union { - u_int64_t u; - int64_t n; - }; - - u = val << (63 - hi); - n = n >> (63 - hi + lo); - return n; -} - -static inline Shift shift(u_int32_t val, int lo) -{ - return (Shift)pickbits32(val, lo+1, lo); -} - -static inline Extension extension(u_int32_t val, int lo) -{ - return (Extension)pickbits32(val, lo+2, lo); -} - -static inline Scaling scaling(u_int32_t val, int lo) -{ - return (Scaling)pickbits32(val, lo, lo); -} - -static inline WriteBack writeback(u_int32_t val, int lo) -{ - return (WriteBack)pickbits32(val, lo, lo); -} - -static inline CondCode condcode(u_int32_t val, int lo) -{ - return (CondCode)pickbits32(val, lo+3, lo); -} - -/* - * operation decode - */ -// bits [28,25] are the primary dispatch vector - -static inline u_int32_t dispatchGroup(u_int32_t val) -{ - return pickshift32(val, 28, 25, 0); -} - -/* - * the 16 possible values for bits [28,25] identified by tags which - * map them to the 5 main instruction groups LDST, DPREG, ADVSIMD, - * BREXSYS and DPIMM. - * - * An extra group PSEUDO is included in one of the unallocated ranges - * for simulator-specific pseudo-instructions. - */ -enum DispatchGroup { - GROUP_PSEUDO_0000, - GROUP_UNALLOC_0001, - GROUP_UNALLOC_0010, - GROUP_UNALLOC_0011, - GROUP_LDST_0100, - GROUP_DPREG_0101, - GROUP_LDST_0110, - GROUP_ADVSIMD_0111, - GROUP_DPIMM_1000, - GROUP_DPIMM_1001, - GROUP_BREXSYS_1010, - GROUP_BREXSYS_1011, - GROUP_LDST_1100, - GROUP_DPREG_1101, - GROUP_LDST_1110, - GROUP_ADVSIMD_1111 -}; - -// bits [31, 29] of a Pseudo are the secondary dispatch vector - -static inline u_int32_t dispatchPseudo(u_int32_t val) -{ - return pickshift32(val, 31, 29, 0); -} - -/* - * the 8 possible values for bits [31,29] in a Pseudo Instruction. - * Bits [28,25] are always 0000. - */ - -enum DispatchPseudo { - PSEUDO_UNALLOC_000, // unallocated - PSEUDO_UNALLOC_001, // ditto - PSEUDO_UNALLOC_010, // ditto - PSEUDO_UNALLOC_011, // ditto - PSEUDO_UNALLOC_100, // ditto - PSEUDO_UNALLOC_101, // ditto - PSEUDO_CALLOUT_110, // CALLOUT -- bits [24,0] identify call/ret sig - PSEUDO_HALT_111 // HALT -- bits [24, 0] identify halt code -}; - -// bits [25, 23] of a DPImm are the secondary dispatch vector - -static inline u_int32_t dispatchDPImm(u_int32_t instr) -{ - return pickshift32(instr, 25, 23, 0); -} - -/* - * the 8 possible values for bits [25,23] in a Data Processing Immediate - * Instruction. Bits [28,25] are always 100_. - */ - -enum DispatchDPImm { - DPIMM_PCADR_000, // PC-rel-addressing - DPIMM_PCADR_001, // ditto - DPIMM_ADDSUB_010, // Add/Subtract (immediate) - DPIMM_ADDSUB_011, // ditto - DPIMM_LOG_100, // Logical (immediate) - DPIMM_MOV_101, // Move Wide (immediate) - DPIMM_BITF_110, // Bitfield - DPIMM_EXTR_111 // Extract -}; - -// bits [29,28:26] of a LS are the secondary dispatch vector - -static inline u_int32_t dispatchLS(u_int32_t instr) -{ - return (pickshift32(instr, 29, 28, 1) | - pickshift32(instr, 26, 26, 0)); -} - -/* - * the 8 possible values for bits [29,28:26] in a Load/Store - * Instruction. Bits [28,25] are always _1_0 - */ - -enum DispatchLS { - LS_EXCL_000, // Load/store exclusive (includes some unallocated) - LS_ADVSIMD_001, // AdvSIMD load/store (various -- includes some unallocated) - LS_LIT_010, // Load register literal (includes some unallocated) - LS_LIT_011, // ditto - LS_PAIR_100, // Load/store register pair (various) - LS_PAIR_101, // ditto - LS_OTHER_110, // other load/store formats - LS_OTHER_111 // ditto -}; - -// bits [28:24:21] of a DPReg are the secondary dispatch vector - -static inline u_int32_t dispatchDPReg(u_int32_t instr) -{ - return (pickshift32(instr, 28, 28, 2) | - pickshift32(instr, 24, 24, 1) | - pickshift32(instr, 21, 21, 0)); -} - -/* - * the 8 possible values for bits [28:24:21] in a Data Processing - * Register Instruction. Bits [28,25] are always _101 - */ - -enum DispatchDPReg { - DPREG_LOG_000, // Logical (shifted register) - DPREG_LOG_001, // ditto - DPREG_ADDSHF_010, // Add/subtract (shifted register) - DPREG_ADDEXT_011, // Add/subtract (extended register) - DPREG_ADDCOND_100, // Add/subtract (with carry) AND - // Cond compare/select AND - // Data Processing (1/2 source) - DPREG_UNALLOC_101, // Unallocated - DPREG_3SRC_110, // Data Processing (3 source) - DPREG_3SRC_111 // Data Processing (3 source) -}; - -// bits [31,29] of a BrExSys are the secondary dispatch vector - -static inline u_int32_t dispatchBrExSys(u_int32_t instr) -{ - return pickbits32(instr, 31, 29); -} - -/* - * the 8 possible values for bits [31,29] in a Branch/Exception/System - * Instruction. Bits [28,25] are always 101_ - */ - -enum DispatchBr { - BR_IMM_000, // Unconditional branch (immediate) - BR_IMMCMP_001, // Compare & branch (immediate) AND - // Test & branch (immediate) - BR_IMMCOND_010, // Conditional branch (immediate) AND Unallocated - BR_UNALLOC_011, // Unallocated - BR_IMM_100, // Unconditional branch (immediate) - BR_IMMCMP_101, // Compare & branch (immediate) AND - // Test & branch (immediate) - BR_REG_110, // Unconditional branch (register) AND System AND - // Excn gen AND Unallocated - BR_UNALLOC_111 // Unallocated -}; - -/* - * TODO still need to provide secondary decode and dispatch for - * AdvSIMD Insructions with instr[28,25] = 0111 or 1111 - */ - -#endif // ifndef DECODE_H
diff --git a/src/hotspot/cpu/aarch64/frame_aarch64.cpp b/src/hotspot/cpu/aarch64/frame_aarch64.cpp index 443459c..ffe14bb 100644 --- a/src/hotspot/cpu/aarch64/frame_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/frame_aarch64.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, Red Hat Inc. All rights reserved. + * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -284,6 +284,9 @@ tty->print_cr("patch_pc at address " INTPTR_FORMAT " [" INTPTR_FORMAT " -> " INTPTR_FORMAT "]", p2i(pc_addr), p2i(*pc_addr), p2i(pc)); } + + // Only generated code frames should be patched, therefore the return address will not be signed. + assert(pauth_ptr_is_raw(*pc_addr), "cannot be signed"); // Either the return address is the original one or we are going to // patch in the same address that's already there. assert(_pc == *pc_addr || pc == *pc_addr, "must be"); @@ -448,7 +451,9 @@ } #endif // COMPILER2_OR_JVMCI - return frame(sender_sp, unextended_sp, link(), sender_pc()); + // Use the raw version of pc - the interpreter should not have signed it. + + return frame(sender_sp, unextended_sp, link(), sender_pc_maybe_signed()); } @@ -511,6 +516,7 @@ // Must be native-compiled frame, i.e. the marshaling code for native // methods that exists in the core system. + return frame(sender_sp(), link(), sender_pc()); } @@ -539,7 +545,7 @@ Method* m = *interpreter_frame_method_addr(); // validate the method we'd find in this potential sender - if (!m->is_valid_method()) return false; + if (!Method::is_valid_method(m)) return false; // stack frames shouldn't be much larger than max_stack elements // this test requires the use of unextended_sp which is the sp as seen by @@ -559,7 +565,7 @@ // validate constantPoolCache* ConstantPoolCache* cp = *interpreter_frame_cache_addr(); - if (cp == NULL || !cp->is_metaspace_object()) return false; + if (MetaspaceObj::is_valid(cp) == false) return false; // validate locals @@ -672,15 +678,15 @@ #define DESCRIBE_FP_OFFSET(name) \ { \ - unsigned long *p = (unsigned long *)fp; \ - printf("0x%016lx 0x%016lx %s\n", (unsigned long)(p + frame::name##_offset), \ + uintptr_t *p = (uintptr_t *)fp; \ + printf("0x%016lx 0x%016lx %s\n", (uintptr_t)(p + frame::name##_offset), \ p[frame::name##_offset], #name); \ } -static __thread unsigned long nextfp; -static __thread unsigned long nextpc; -static __thread unsigned long nextsp; -static __thread RegisterMap *reg_map; +static THREAD_LOCAL_DECL uintptr_t nextfp; +static THREAD_LOCAL_DECL uintptr_t nextpc; +static THREAD_LOCAL_DECL uintptr_t nextsp; +static THREAD_LOCAL_DECL RegisterMap *reg_map; static void printbc(Method *m, intptr_t bcx) { const char *name; @@ -698,7 +704,7 @@ printf("%s : %s ==> %s\n", m->name_and_sig_as_C_string(), buf, name); } -void internal_pf(unsigned long sp, unsigned long fp, unsigned long pc, unsigned long bcx) { +void internal_pf(uintptr_t sp, uintptr_t fp, uintptr_t pc, uintptr_t bcx) { if (! fp) return; @@ -712,7 +718,7 @@ DESCRIBE_FP_OFFSET(interpreter_frame_locals); DESCRIBE_FP_OFFSET(interpreter_frame_bcp); DESCRIBE_FP_OFFSET(interpreter_frame_initial_sp); - unsigned long *p = (unsigned long *)fp; + uintptr_t *p = (uintptr_t *)fp; // We want to see all frames, native and Java. For compiled and // interpreted frames we have special information that allows us to @@ -722,16 +728,16 @@ if (this_frame.is_compiled_frame() || this_frame.is_interpreted_frame()) { frame sender = this_frame.sender(reg_map); - nextfp = (unsigned long)sender.fp(); - nextpc = (unsigned long)sender.pc(); - nextsp = (unsigned long)sender.unextended_sp(); + nextfp = (uintptr_t)sender.fp(); + nextpc = (uintptr_t)sender.pc(); + nextsp = (uintptr_t)sender.unextended_sp(); } else { nextfp = p[frame::link_offset]; nextpc = p[frame::return_addr_offset]; - nextsp = (unsigned long)&p[frame::sender_sp_offset]; + nextsp = (uintptr_t)&p[frame::sender_sp_offset]; } - if (bcx == -1ul) + if (bcx == -1ULL) bcx = p[frame::interpreter_frame_bcp_offset]; if (Interpreter::contains((address)pc)) { @@ -765,13 +771,15 @@ internal_pf (nextsp, nextfp, nextpc, -1); } -extern "C" void pf(unsigned long sp, unsigned long fp, unsigned long pc, - unsigned long bcx, unsigned long thread) { - RegisterMap map((JavaThread*)thread, false); +extern "C" void pf(uintptr_t sp, uintptr_t fp, uintptr_t pc, + uintptr_t bcx, uintptr_t thread) { if (!reg_map) { - reg_map = (RegisterMap*)os::malloc(sizeof map, mtNone); + reg_map = NEW_C_HEAP_OBJ(RegisterMap, mtNone); + ::new (reg_map) RegisterMap((JavaThread*)thread, false); + } else { + *reg_map = RegisterMap((JavaThread*)thread, false); } - memcpy(reg_map, &map, sizeof map); + { CodeBlob *cb = CodeCache::find_blob((address)pc); if (cb && cb->frame_size()) @@ -783,9 +791,9 @@ // support for printing out where we are in a Java method // needs to be passed current fp and bcp register values // prints method name, bc index and bytecode name -extern "C" void pm(unsigned long fp, unsigned long bcx) { +extern "C" void pm(uintptr_t fp, uintptr_t bcx) { DESCRIBE_FP_OFFSET(interpreter_frame_method); - unsigned long *p = (unsigned long *)fp; + uintptr_t *p = (uintptr_t *)fp; Method* m = (Method*)p[frame::interpreter_frame_method_offset]; printbc(m, bcx); }
diff --git a/src/hotspot/cpu/aarch64/frame_aarch64.hpp b/src/hotspot/cpu/aarch64/frame_aarch64.hpp index d8c94e2..007397b 100644 --- a/src/hotspot/cpu/aarch64/frame_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/frame_aarch64.hpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2014, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * @@ -61,6 +61,7 @@ // [last sp ] // [oop temp ] (only for native calls) +// [padding ] (to preserve machine SP alignment) // [locals and parameters ] // <- sender sp // ------------------------------ Asm interpreter ---------------------------------------- @@ -148,6 +149,7 @@ intptr_t* fp() const { return _fp; } inline address* sender_pc_addr() const; + inline address sender_pc_maybe_signed() const; // expression stack tos if we are nested in a java call intptr_t* interpreter_frame_last_sp() const;
diff --git a/src/hotspot/cpu/aarch64/frame_aarch64.inline.hpp b/src/hotspot/cpu/aarch64/frame_aarch64.inline.hpp index 243cba9..968840b 100644 --- a/src/hotspot/cpu/aarch64/frame_aarch64.inline.hpp +++ b/src/hotspot/cpu/aarch64/frame_aarch64.inline.hpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2014, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * @@ -28,6 +28,7 @@ #include "code/codeCache.hpp" #include "code/vmreg.inline.hpp" +#include "pauth_aarch64.hpp" // Inline functions for AArch64 frames: @@ -45,6 +46,7 @@ static int spin; inline void frame::init(intptr_t* sp, intptr_t* fp, address pc) { + assert(pauth_ptr_is_raw(pc), "cannot be signed"); intptr_t a = intptr_t(sp); intptr_t b = intptr_t(fp); _sp = sp; @@ -69,6 +71,7 @@ } inline frame::frame(intptr_t* sp, intptr_t* unextended_sp, intptr_t* fp, address pc) { + assert(pauth_ptr_is_raw(pc), "cannot be signed"); intptr_t a = intptr_t(sp); intptr_t b = intptr_t(fp); _sp = sp; @@ -155,8 +158,9 @@ // Return address: -inline address* frame::sender_pc_addr() const { return (address*) addr_at( return_addr_offset); } -inline address frame::sender_pc() const { return *sender_pc_addr(); } +inline address* frame::sender_pc_addr() const { return (address*) addr_at( return_addr_offset); } +inline address frame::sender_pc_maybe_signed() const { return *sender_pc_addr(); } +inline address frame::sender_pc() const { return pauth_strip_pointer(sender_pc_maybe_signed()); } inline intptr_t* frame::sender_sp() const { return addr_at( sender_sp_offset); }
diff --git a/src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.cpp index c9e8135..d75485f 100644 --- a/src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2018, 2020, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -47,6 +47,18 @@ Register addr, Register count, RegSet saved_regs) { bool dest_uninitialized = (decorators & IS_DEST_UNINITIALIZED) != 0; if (!dest_uninitialized) { + Label done; + Address in_progress(rthread, in_bytes(G1ThreadLocalData::satb_mark_queue_active_offset())); + + // Is marking active? + if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { + __ ldrw(rscratch1, in_progress); + } else { + assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); + __ ldrb(rscratch1, in_progress); + } + __ cbzw(rscratch1, done); + __ push(saved_regs, sp); if (count == c_rarg0) { if (addr == c_rarg1) { @@ -68,19 +80,18 @@ __ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_array_pre_oop_entry), 2); } __ pop(saved_regs, sp); + + __ bind(done); } } void G1BarrierSetAssembler::gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, - Register start, Register end, Register scratch, RegSet saved_regs) { + Register start, Register count, Register scratch, RegSet saved_regs) { __ push(saved_regs, sp); - // must compute element count unless barrier set interface is changed (other platforms supply count) - assert_different_registers(start, end, scratch); - __ lea(scratch, Address(end, BytesPerHeapOop)); - __ sub(scratch, scratch, start); // subtract start to get #bytes - __ lsr(scratch, scratch, LogBytesPerHeapOop); // convert to element count + assert_different_registers(start, count, scratch); + assert_different_registers(c_rarg0, count); __ mov(c_rarg0, start); - __ mov(c_rarg1, scratch); + __ mov(c_rarg1, count); __ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_array_post_entry), 2); __ pop(saved_regs, sp); } @@ -210,7 +221,6 @@ // storing region crossing non-NULL, is card already dirty? - ExternalAddress cardtable((address) ct->byte_map_base()); assert(sizeof(*ct->byte_map_base()) == sizeof(jbyte), "adjust this code"); const Register card_addr = tmp;
diff --git a/src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.hpp index 965fd06..e38746f 100644 --- a/src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.hpp
@@ -39,7 +39,7 @@ void gen_write_ref_array_pre_barrier(MacroAssembler* masm, DecoratorSet decorators, Register addr, Register count, RegSet saved_regs); void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, - Register start, Register end, Register tmp, RegSet saved_regs); + Register start, Register count, Register tmp, RegSet saved_regs); void g1_write_barrier_pre(MacroAssembler* masm, Register obj,
diff --git a/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp index b16bd17..4da49d3 100644 --- a/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp
@@ -172,7 +172,7 @@ Label retry; __ bind(retry); { - unsigned long offset; + uint64_t offset; __ adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset); __ ldr(heap_end, Address(rscratch1, offset)); } @@ -181,7 +181,7 @@ // Get the current top of the heap { - unsigned long offset; + uint64_t offset; __ adrp(rscratch1, heap_top, offset); // Use add() here after ARDP, rather than lea(). // lea() does not generate anything if its offset is zero.
diff --git a/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.hpp index 6bd6c6b..68e2875 100644 --- a/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.hpp
@@ -37,7 +37,7 @@ public: virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, - Register addr, Register count, RegSet saved_regs) {} + Register src, Register dst, Register count, RegSet saved_regs) {} virtual void arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, Register start, Register end, Register tmp, RegSet saved_regs) {} virtual void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
diff --git a/src/hotspot/cpu/aarch64/gc/shared/cardTableBarrierSetAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/gc/shared/cardTableBarrierSetAssembler_aarch64.cpp index ad8c8c9..2d3ebb7 100644 --- a/src/hotspot/cpu/aarch64/gc/shared/cardTableBarrierSetAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/gc/shared/cardTableBarrierSetAssembler_aarch64.cpp
@@ -64,19 +64,22 @@ } void CardTableBarrierSetAssembler::gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, - Register start, Register end, Register scratch, RegSet saved_regs) { + Register start, Register count, Register scratch, RegSet saved_regs) { BarrierSet* bs = BarrierSet::barrier_set(); CardTableBarrierSet* ctbs = barrier_set_cast<CardTableBarrierSet>(bs); CardTable* ct = ctbs->card_table(); - assert(sizeof(*ct->byte_map_base()) == sizeof(jbyte), "adjust this code"); - Label L_loop; + Label L_loop, L_done; + const Register end = count; + __ cbz(count, L_done); // zero count - nothing to do + + __ lea(end, Address(start, count, Address::lsl(LogBytesPerHeapOop))); // end = start + count << LogBytesPerHeapOop + __ sub(end, end, BytesPerHeapOop); // last element address to make inclusive __ lsr(start, start, CardTable::card_shift); __ lsr(end, end, CardTable::card_shift); - __ sub(end, end, start); // number of bytes to copy + __ sub(count, end, start); // number of bytes to copy - const Register count = end; // 'end' register contains bytes count now __ load_byte_map_base(scratch); __ add(start, start, scratch); if (ct->scanned_concurrently()) { @@ -86,6 +89,7 @@ __ strb(zr, Address(start, count)); __ subs(count, count, 1); __ br(Assembler::GE, L_loop); + __ bind(L_done); } void CardTableBarrierSetAssembler::oop_store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
diff --git a/src/hotspot/cpu/aarch64/gc/shared/cardTableBarrierSetAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/gc/shared/cardTableBarrierSetAssembler_aarch64.hpp index d613c6d..1be48f4 100644 --- a/src/hotspot/cpu/aarch64/gc/shared/cardTableBarrierSetAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/gc/shared/cardTableBarrierSetAssembler_aarch64.hpp
@@ -33,7 +33,7 @@ void store_check(MacroAssembler* masm, Register obj, Address dst); virtual void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, - Register start, Register end, Register tmp, RegSet saved_regs); + Register start, Register count, Register tmp, RegSet saved_regs); virtual void oop_store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, Address dst, Register val, Register tmp1, Register tmp2);
diff --git a/src/hotspot/cpu/aarch64/gc/shared/modRefBarrierSetAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/gc/shared/modRefBarrierSetAssembler_aarch64.cpp index 7693e0b..badd46d 100644 --- a/src/hotspot/cpu/aarch64/gc/shared/modRefBarrierSetAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/gc/shared/modRefBarrierSetAssembler_aarch64.cpp
@@ -29,18 +29,18 @@ #define __ masm-> void ModRefBarrierSetAssembler::arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, - Register addr, Register count, RegSet saved_regs) { + Register src, Register dst, Register count, RegSet saved_regs) { if (is_oop) { - gen_write_ref_array_pre_barrier(masm, decorators, addr, count, saved_regs); + gen_write_ref_array_pre_barrier(masm, decorators, dst, count, saved_regs); } } void ModRefBarrierSetAssembler::arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, - Register start, Register end, Register tmp, + Register start, Register count, Register tmp, RegSet saved_regs) { if (is_oop) { - gen_write_ref_array_post_barrier(masm, decorators, start, end, tmp, saved_regs); + gen_write_ref_array_post_barrier(masm, decorators, start, count, tmp, saved_regs); } }
diff --git a/src/hotspot/cpu/aarch64/gc/shared/modRefBarrierSetAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/gc/shared/modRefBarrierSetAssembler_aarch64.hpp index f0de095..00e36b9 100644 --- a/src/hotspot/cpu/aarch64/gc/shared/modRefBarrierSetAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/gc/shared/modRefBarrierSetAssembler_aarch64.hpp
@@ -37,16 +37,16 @@ virtual void gen_write_ref_array_pre_barrier(MacroAssembler* masm, DecoratorSet decorators, Register addr, Register count, RegSet saved_regs) {} virtual void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, - Register start, Register end, Register tmp, RegSet saved_regs) {} + Register start, Register count, Register tmp, RegSet saved_regs) {} virtual void oop_store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, Address dst, Register val, Register tmp1, Register tmp2) = 0; public: virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, - Register addr, Register count, RegSet saved_regs); + Register src, Register dst, Register count, RegSet saved_regs); virtual void arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, - Register start, Register end, Register tmp, RegSet saved_regs); + Register start, Register count, Register tmp, RegSet saved_regs); virtual void store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, Address dst, Register val, Register tmp1, Register tmp2); };
diff --git a/src/hotspot/cpu/aarch64/gc/shenandoah/c1/shenandoahBarrierSetC1_aarch64.cpp b/src/hotspot/cpu/aarch64/gc/shenandoah/c1/shenandoahBarrierSetC1_aarch64.cpp new file mode 100644 index 0000000..03bada8 --- /dev/null +++ b/src/hotspot/cpu/aarch64/gc/shenandoah/c1/shenandoahBarrierSetC1_aarch64.cpp
@@ -0,0 +1,123 @@ +/* + * Copyright (c) 2018, 2020, Red Hat, Inc. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#include "precompiled.hpp" +#include "c1/c1_LIRAssembler.hpp" +#include "c1/c1_MacroAssembler.hpp" +#include "gc/shenandoah/shenandoahBarrierSet.hpp" +#include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" +#include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp" + +#define __ masm->masm()-> + +void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) { + Register addr = _addr->as_register_lo(); + Register newval = _new_value->as_register(); + Register cmpval = _cmp_value->as_register(); + Register tmp1 = _tmp1->as_register(); + Register tmp2 = _tmp2->as_register(); + Register result = result_opr()->as_register(); + + ShenandoahBarrierSet::assembler()->iu_barrier(masm->masm(), newval, rscratch2); + + if (UseCompressedOops) { + __ encode_heap_oop(tmp1, cmpval); + cmpval = tmp1; + __ encode_heap_oop(tmp2, newval); + newval = tmp2; + } + + ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmpval, newval, /*acquire*/ true, /*release*/ true, /*is_cae*/ false, result); + + if (UseBarriersForVolatile) { + // The membar here is necessary to prevent reordering between the + // release store in the CAS above and a subsequent volatile load. + // However for !UseBarriersForVolatile, C1 inserts a full barrier before + // volatile loads which means we don't need an additional barrier + // here (see LIRGenerator::volatile_field_load()). + __ membar(__ AnyAny); + } +} + +#undef __ + +#ifdef ASSERT +#define __ gen->lir(__FILE__, __LINE__)-> +#else +#define __ gen->lir()-> +#endif + +LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) { + BasicType bt = access.type(); + if (access.is_oop()) { + LIRGenerator *gen = access.gen(); + if (ShenandoahSATBBarrier) { + pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(), + LIR_OprFact::illegalOpr /* pre_val */); + } + if (ShenandoahCASBarrier) { + cmp_value.load_item(); + new_value.load_item(); + + LIR_Opr t1 = gen->new_register(T_OBJECT); + LIR_Opr t2 = gen->new_register(T_OBJECT); + LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base(); + LIR_Opr result = gen->new_register(T_INT); + + __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result)); + return result; + } + } + return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value); +} + +LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) { + LIRGenerator* gen = access.gen(); + BasicType type = access.type(); + + LIR_Opr result = gen->new_register(type); + value.load_item(); + LIR_Opr value_opr = value.result(); + + if (access.is_oop()) { + value_opr = iu_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators()); + } + + assert(type == T_INT || type == T_OBJECT || type == T_ARRAY LP64_ONLY( || type == T_LONG ), "unexpected type"); + LIR_Opr tmp = gen->new_register(T_INT); + __ xchg(access.resolved_addr(), value_opr, result, tmp); + + if (access.is_oop()) { + result = load_reference_barrier(access.gen(), result, LIR_OprFact::addressConst(0)); + LIR_Opr tmp = gen->new_register(type); + __ move(result, tmp); + result = tmp; + if (ShenandoahSATBBarrier) { + pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr, + result /* pre_val */); + } + } + + return result; +}
diff --git a/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.cpp new file mode 100644 index 0000000..abc689f --- /dev/null +++ b/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.cpp
@@ -0,0 +1,769 @@ +/* + * Copyright (c) 2018, 2020, Red Hat, Inc. All rights reserved. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#include "precompiled.hpp" +#include "gc/shenandoah/shenandoahBarrierSet.hpp" +#include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" +#include "gc/shenandoah/shenandoahForwarding.hpp" +#include "gc/shenandoah/shenandoahHeap.hpp" +#include "gc/shenandoah/shenandoahHeapRegion.hpp" +#include "gc/shenandoah/shenandoahRuntime.hpp" +#include "gc/shenandoah/shenandoahThreadLocalData.hpp" +#include "gc/shenandoah/heuristics/shenandoahHeuristics.hpp" +#include "interpreter/interpreter.hpp" +#include "interpreter/interp_masm.hpp" +#include "runtime/sharedRuntime.hpp" +#include "runtime/thread.hpp" +#ifdef COMPILER1 +#include "c1/c1_LIRAssembler.hpp" +#include "c1/c1_MacroAssembler.hpp" +#include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp" +#endif + +#define __ masm-> + +address ShenandoahBarrierSetAssembler::_shenandoah_lrb = NULL; + +void ShenandoahBarrierSetAssembler::arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, + Register src, Register dst, Register count, RegSet saved_regs) { + if (is_oop) { + bool dest_uninitialized = (decorators & IS_DEST_UNINITIALIZED) != 0; + if ((ShenandoahSATBBarrier && !dest_uninitialized) || ShenandoahIUBarrier || ShenandoahLoadRefBarrier) { + + Label done; + + // Avoid calling runtime if count == 0 + __ cbz(count, done); + + // Is GC active? + Address gc_state(rthread, in_bytes(ShenandoahThreadLocalData::gc_state_offset())); + __ ldrb(rscratch1, gc_state); + if (ShenandoahSATBBarrier && dest_uninitialized) { + __ tbz(rscratch1, ShenandoahHeap::HAS_FORWARDED_BITPOS, done); + } else { + __ mov(rscratch2, ShenandoahHeap::HAS_FORWARDED | ShenandoahHeap::MARKING); + __ tst(rscratch1, rscratch2); + __ br(Assembler::EQ, done); + } + + __ push(saved_regs, sp); + if (UseCompressedOops) { + __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::arraycopy_barrier_narrow_oop_entry), src, dst, count); + } else { + __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::arraycopy_barrier_oop_entry), src, dst, count); + } + __ pop(saved_regs, sp); + __ bind(done); + } + } +} + +void ShenandoahBarrierSetAssembler::shenandoah_write_barrier_pre(MacroAssembler* masm, + Register obj, + Register pre_val, + Register thread, + Register tmp, + bool tosca_live, + bool expand_call) { + if (ShenandoahSATBBarrier) { + satb_write_barrier_pre(masm, obj, pre_val, thread, tmp, tosca_live, expand_call); + } +} + +void ShenandoahBarrierSetAssembler::satb_write_barrier_pre(MacroAssembler* masm, + Register obj, + Register pre_val, + Register thread, + Register tmp, + bool tosca_live, + bool expand_call) { + // If expand_call is true then we expand the call_VM_leaf macro + // directly to skip generating the check by + // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. + + assert(thread == rthread, "must be"); + + Label done; + Label runtime; + + assert_different_registers(obj, pre_val, tmp, rscratch1); + assert(pre_val != noreg && tmp != noreg, "expecting a register"); + + Address in_progress(thread, in_bytes(ShenandoahThreadLocalData::satb_mark_queue_active_offset())); + Address index(thread, in_bytes(ShenandoahThreadLocalData::satb_mark_queue_index_offset())); + Address buffer(thread, in_bytes(ShenandoahThreadLocalData::satb_mark_queue_buffer_offset())); + + // Is marking active? + if (in_bytes(ShenandoahSATBMarkQueue::byte_width_of_active()) == 4) { + __ ldrw(tmp, in_progress); + } else { + assert(in_bytes(ShenandoahSATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); + __ ldrb(tmp, in_progress); + } + __ cbzw(tmp, done); + + // Do we need to load the previous value? + if (obj != noreg) { + __ load_heap_oop(pre_val, Address(obj, 0), noreg, noreg, AS_RAW); + } + + // Is the previous value null? + __ cbz(pre_val, done); + + // Can we store original value in the thread's buffer? + // Is index == 0? + // (The index field is typed as size_t.) + + __ ldr(tmp, index); // tmp := *index_adr + __ cbz(tmp, runtime); // tmp == 0? + // If yes, goto runtime + + __ sub(tmp, tmp, wordSize); // tmp := tmp - wordSize + __ str(tmp, index); // *index_adr := tmp + __ ldr(rscratch1, buffer); + __ add(tmp, tmp, rscratch1); // tmp := tmp + *buffer_adr + + // Record the previous value + __ str(pre_val, Address(tmp, 0)); + __ b(done); + + __ bind(runtime); + // save the live input values + RegSet saved = RegSet::of(pre_val); + if (tosca_live) saved += RegSet::of(r0); + if (obj != noreg) saved += RegSet::of(obj); + + __ push(saved, sp); + + // Calling the runtime using the regular call_VM_leaf mechanism generates + // code (generated by InterpreterMacroAssember::call_VM_leaf_base) + // that checks that the *(rfp+frame::interpreter_frame_last_sp) == NULL. + // + // If we care generating the pre-barrier without a frame (e.g. in the + // intrinsified Reference.get() routine) then ebp might be pointing to + // the caller frame and so this check will most likely fail at runtime. + // + // Expanding the call directly bypasses the generation of the check. + // So when we do not have have a full interpreter frame on the stack + // expand_call should be passed true. + + if (expand_call) { + assert(pre_val != c_rarg1, "smashed arg"); + __ super_call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::write_ref_field_pre_entry), pre_val, thread); + } else { + __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::write_ref_field_pre_entry), pre_val, thread); + } + + __ pop(saved, sp); + + __ bind(done); +} + +void ShenandoahBarrierSetAssembler::resolve_forward_pointer(MacroAssembler* masm, Register dst, Register tmp) { + assert(ShenandoahLoadRefBarrier || ShenandoahCASBarrier, "Should be enabled"); + Label is_null; + __ cbz(dst, is_null); + resolve_forward_pointer_not_null(masm, dst, tmp); + __ bind(is_null); +} + +// IMPORTANT: This must preserve all registers, even rscratch1 and rscratch2, except those explicitely +// passed in. +void ShenandoahBarrierSetAssembler::resolve_forward_pointer_not_null(MacroAssembler* masm, Register dst, Register tmp) { + assert(ShenandoahLoadRefBarrier || ShenandoahCASBarrier, "Should be enabled"); + // The below loads the mark word, checks if the lowest two bits are + // set, and if so, clear the lowest two bits and copy the result + // to dst. Otherwise it leaves dst alone. + // Implementing this is surprisingly awkward. I do it here by: + // - Inverting the mark word + // - Test lowest two bits == 0 + // - If so, set the lowest two bits + // - Invert the result back, and copy to dst + + bool borrow_reg = (tmp == noreg); + if (borrow_reg) { + // No free registers available. Make one useful. + tmp = rscratch1; + if (tmp == dst) { + tmp = rscratch2; + } + __ push(RegSet::of(tmp), sp); + } + + assert_different_registers(tmp, dst); + + Label done; + __ ldr(tmp, Address(dst, oopDesc::mark_offset_in_bytes())); + __ eon(tmp, tmp, zr); + __ ands(zr, tmp, markOopDesc::lock_mask_in_place); + __ br(Assembler::NE, done); + __ orr(tmp, tmp, markOopDesc::marked_value); + __ eon(dst, tmp, zr); + __ bind(done); + + if (borrow_reg) { + __ pop(RegSet::of(tmp), sp); + } +} + +void ShenandoahBarrierSetAssembler::load_reference_barrier_not_null(MacroAssembler* masm, Register dst, Address load_addr) { + assert(ShenandoahLoadRefBarrier, "Should be enabled"); + assert(dst != rscratch2, "need rscratch2"); + assert_different_registers(load_addr.base(), load_addr.index(), rscratch1, rscratch2); + + Label done; + __ enter(); + Address gc_state(rthread, in_bytes(ShenandoahThreadLocalData::gc_state_offset())); + __ ldrb(rscratch2, gc_state); + + // Check for heap stability + __ tbz(rscratch2, ShenandoahHeap::HAS_FORWARDED_BITPOS, done); + + // use r1 for load address + Register result_dst = dst; + if (dst == r1) { + __ mov(rscratch1, dst); + dst = rscratch1; + } + + // Save r0 and r1, unless it is an output register + RegSet to_save = RegSet::of(r0, r1) - result_dst; + __ push(to_save, sp); + __ lea(r1, load_addr); + __ mov(r0, dst); + + __ far_call(RuntimeAddress(CAST_FROM_FN_PTR(address, ShenandoahBarrierSetAssembler::shenandoah_lrb()))); + + __ mov(result_dst, r0); + __ pop(to_save, sp); + + __ bind(done); + __ leave(); +} + +void ShenandoahBarrierSetAssembler::iu_barrier(MacroAssembler* masm, Register dst, Register tmp) { + if (ShenandoahIUBarrier) { + __ push_call_clobbered_registers(); + satb_write_barrier_pre(masm, noreg, dst, rthread, tmp, true, false); + __ pop_call_clobbered_registers(); + } +} + +void ShenandoahBarrierSetAssembler::load_reference_barrier(MacroAssembler* masm, Register dst, Address load_addr) { + if (ShenandoahLoadRefBarrier) { + Label is_null; + __ cbz(dst, is_null); + load_reference_barrier_not_null(masm, dst, load_addr); + __ bind(is_null); + } +} + +// +// Arguments: +// +// Inputs: +// src: oop location to load from, might be clobbered +// +// Output: +// dst: oop loaded from src location +// +// Kill: +// rscratch1 (scratch reg) +// +// Alias: +// dst: rscratch1 (might use rscratch1 as temporary output register to avoid clobbering src) +// +void ShenandoahBarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Register dst, Address src, Register tmp1, Register tmp_thread) { + // 1: non-reference load, no additional barrier is needed + if (!is_reference_type(type)) { + BarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp_thread); + return; + } + + // 2: load a reference from src location and apply LRB if needed + if (ShenandoahBarrierSet::need_load_reference_barrier(decorators, type)) { + Register result_dst = dst; + + // Preserve src location for LRB + if (dst == src.base() || dst == src.index()) { + dst = rscratch1; + } + assert_different_registers(dst, src.base(), src.index()); + + BarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp_thread); + + load_reference_barrier(masm, dst, src); + + if (dst != result_dst) { + __ mov(result_dst, dst); + dst = result_dst; + } + } else { + BarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp_thread); + } + + // 3: apply keep-alive barrier if needed + if (ShenandoahBarrierSet::need_keep_alive_barrier(decorators, type)) { + __ enter(); + __ push_call_clobbered_registers(); + satb_write_barrier_pre(masm /* masm */, + noreg /* obj */, + dst /* pre_val */, + rthread /* thread */, + tmp1 /* tmp */, + true /* tosca_live */, + true /* expand_call */); + __ pop_call_clobbered_registers(); + __ leave(); + } +} + +void ShenandoahBarrierSetAssembler::store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Address dst, Register val, Register tmp1, Register tmp2) { + bool on_oop = type == T_OBJECT || type == T_ARRAY; + if (!on_oop) { + BarrierSetAssembler::store_at(masm, decorators, type, dst, val, tmp1, tmp2); + return; + } + + // flatten object address if needed + if (dst.index() == noreg && dst.offset() == 0) { + if (dst.base() != r3) { + __ mov(r3, dst.base()); + } + } else { + __ lea(r3, dst); + } + + shenandoah_write_barrier_pre(masm, + r3 /* obj */, + tmp2 /* pre_val */, + rthread /* thread */, + tmp1 /* tmp */, + val != noreg /* tosca_live */, + false /* expand_call */); + + if (val == noreg) { + BarrierSetAssembler::store_at(masm, decorators, type, Address(r3, 0), noreg, noreg, noreg); + } else { + iu_barrier(masm, val, tmp1); + // G1 barrier needs uncompressed oop for region cross check. + Register new_val = val; + if (UseCompressedOops) { + new_val = rscratch2; + __ mov(new_val, val); + } + BarrierSetAssembler::store_at(masm, decorators, type, Address(r3, 0), val, noreg, noreg); + } + +} + +void ShenandoahBarrierSetAssembler::try_resolve_jobject_in_native(MacroAssembler* masm, Register jni_env, + Register obj, Register tmp, Label& slowpath) { + Label done; + // Resolve jobject + BarrierSetAssembler::try_resolve_jobject_in_native(masm, jni_env, obj, tmp, slowpath); + + // Check for null. + __ cbz(obj, done); + + assert(obj != rscratch2, "need rscratch2"); + Address gc_state(jni_env, ShenandoahThreadLocalData::gc_state_offset() - JavaThread::jni_environment_offset()); + __ lea(rscratch2, gc_state); + __ ldrb(rscratch2, Address(rscratch2)); + + // Check for heap in evacuation phase + __ tbnz(rscratch2, ShenandoahHeap::EVACUATION_BITPOS, slowpath); + + __ bind(done); +} + +// Special Shenandoah CAS implementation that handles false negatives due +// to concurrent evacuation. The service is more complex than a +// traditional CAS operation because the CAS operation is intended to +// succeed if the reference at addr exactly matches expected or if the +// reference at addr holds a pointer to a from-space object that has +// been relocated to the location named by expected. There are two +// races that must be addressed: +// a) A parallel thread may mutate the contents of addr so that it points +// to a different object. In this case, the CAS operation should fail. +// b) A parallel thread may heal the contents of addr, replacing a +// from-space pointer held in addr with the to-space pointer +// representing the new location of the object. +// Upon entry to cmpxchg_oop, it is assured that new_val equals NULL +// or it refers to an object that is not being evacuated out of +// from-space, or it refers to the to-space version of an object that +// is being evacuated out of from-space. +// +// By default the value held in the result register following execution +// of the generated code sequence is 0 to indicate failure of CAS, +// non-zero to indicate success. If is_cae, the result is the value most +// recently fetched from addr rather than a boolean success indicator. +// +// Clobbers rscratch1, rscratch2 +void ShenandoahBarrierSetAssembler::cmpxchg_oop(MacroAssembler* masm, + Register addr, + Register expected, + Register new_val, + bool acquire, bool release, + bool is_cae, + Register result) { + Register tmp1 = rscratch1; + Register tmp2 = rscratch2; + bool is_narrow = UseCompressedOops; + Assembler::operand_size size = is_narrow ? Assembler::word : Assembler::xword; + + assert_different_registers(addr, expected, tmp1, tmp2); + assert_different_registers(addr, new_val, tmp1, tmp2); + + Label step4, done; + + // There are two ways to reach this label. Initial entry into the + // cmpxchg_oop code expansion starts at step1 (which is equivalent + // to label step4). Additionally, in the rare case that four steps + // are required to perform the requested operation, the fourth step + // is the same as the first. On a second pass through step 1, + // control may flow through step 2 on its way to failure. It will + // not flow from step 2 to step 3 since we are assured that the + // memory at addr no longer holds a from-space pointer. + // + // The comments that immediately follow the step4 label apply only + // to the case in which control reaches this label by branch from + // step 3. + + __ bind (step4); + + // Step 4. CAS has failed because the value most recently fetched + // from addr is no longer the from-space pointer held in tmp2. If a + // different thread replaced the in-memory value with its equivalent + // to-space pointer, then CAS may still be able to succeed. The + // value held in the expected register has not changed. + // + // It is extremely rare we reach this point. For this reason, the + // implementation opts for smaller rather than potentially faster + // code. Ultimately, smaller code for this rare case most likely + // delivers higher overall throughput by enabling improved icache + // performance. + + // Step 1. Fast-path. + // + // Try to CAS with given arguments. If successful, then we are done. + // + // No label required for step 1. + + __ cmpxchg(addr, expected, new_val, size, acquire, release, false, tmp2); + // EQ flag set iff success. tmp2 holds value fetched. + + // If expected equals null but tmp2 does not equal null, the + // following branches to done to report failure of CAS. If both + // expected and tmp2 equal null, the following branches to done to + // report success of CAS. There's no need for a special test of + // expected equal to null. + + __ br(Assembler::EQ, done); + // if CAS failed, fall through to step 2 + + // Step 2. CAS has failed because the value held at addr does not + // match expected. This may be a false negative because the value fetched + // from addr (now held in tmp2) may be a from-space pointer to the + // original copy of same object referenced by to-space pointer expected. + // + // To resolve this, it suffices to find the forward pointer associated + // with fetched value. If this matches expected, retry CAS with new + // parameters. If this mismatches, then we have a legitimate + // failure, and we're done. + // + // No need for step2 label. + + // overwrite tmp1 with from-space pointer fetched from memory + __ mov(tmp1, tmp2); + + if (is_narrow) { + // Decode tmp1 in order to resolve its forward pointer + __ decode_heap_oop(tmp1, tmp1); + } + resolve_forward_pointer(masm, tmp1); + // Encode tmp1 to compare against expected. + __ encode_heap_oop(tmp1, tmp1); + + // Does forwarded value of fetched from-space pointer match original + // value of expected? If tmp1 holds null, this comparison will fail + // because we know from step1 that expected is not null. There is + // no need for a separate test for tmp1 (the value originally held + // in memory) equal to null. + __ cmp(tmp1, expected); + + // If not, then the failure was legitimate and we're done. + // Branching to done with NE condition denotes failure. + __ br(Assembler::NE, done); + + // Fall through to step 3. No need for step3 label. + + // Step 3. We've confirmed that the value originally held in memory + // (now held in tmp2) pointed to from-space version of original + // expected value. Try the CAS again with the from-space expected + // value. If it now succeeds, we're good. + // + // Note: tmp2 holds encoded from-space pointer that matches to-space + // object residing at expected. tmp2 is the new "expected". + + // Note that macro implementation of __cmpxchg cannot use same register + // tmp2 for result and expected since it overwrites result before it + // compares result with expected. + __ cmpxchg(addr, tmp2, new_val, size, acquire, release, false, noreg); + // EQ flag set iff success. tmp2 holds value fetched, tmp1 (rscratch1) clobbered. + + // If fetched value did not equal the new expected, this could + // still be a false negative because some other thread may have + // newly overwritten the memory value with its to-space equivalent. + __ br(Assembler::NE, step4); + + if (is_cae) { + // We're falling through to done to indicate success. Success + // with is_cae is denoted by returning the value of expected as + // result. + __ mov(tmp2, expected); + } + + __ bind(done); + // At entry to done, the Z (EQ) flag is on iff if the CAS + // operation was successful. Additionally, if is_cae, tmp2 holds + // the value most recently fetched from addr. In this case, success + // is denoted by tmp2 matching expected. + + if (is_cae) { + __ mov(result, tmp2); + } else { + __ cset(result, Assembler::EQ); + } +} + +#undef __ + +#ifdef COMPILER1 + +#define __ ce->masm()-> + +void ShenandoahBarrierSetAssembler::gen_pre_barrier_stub(LIR_Assembler* ce, ShenandoahPreBarrierStub* stub) { + ShenandoahBarrierSetC1* bs = (ShenandoahBarrierSetC1*)BarrierSet::barrier_set()->barrier_set_c1(); + // At this point we know that marking is in progress. + // If do_load() is true then we have to emit the + // load of the previous value; otherwise it has already + // been loaded into _pre_val. + + __ bind(*stub->entry()); + + assert(stub->pre_val()->is_register(), "Precondition."); + + Register pre_val_reg = stub->pre_val()->as_register(); + + if (stub->do_load()) { + ce->mem2reg(stub->addr(), stub->pre_val(), T_OBJECT, stub->patch_code(), stub->info(), false /*wide*/, false /*unaligned*/); + } + __ cbz(pre_val_reg, *stub->continuation()); + ce->store_parameter(stub->pre_val()->as_register(), 0); + __ far_call(RuntimeAddress(bs->pre_barrier_c1_runtime_code_blob()->code_begin())); + __ b(*stub->continuation()); +} + +void ShenandoahBarrierSetAssembler::gen_load_reference_barrier_stub(LIR_Assembler* ce, ShenandoahLoadReferenceBarrierStub* stub) { + ShenandoahBarrierSetC1* bs = (ShenandoahBarrierSetC1*)BarrierSet::barrier_set()->barrier_set_c1(); + __ bind(*stub->entry()); + + Register obj = stub->obj()->as_register(); + Register res = stub->result()->as_register(); + Register addr = stub->addr()->as_pointer_register(); + Register tmp1 = stub->tmp1()->as_register(); + Register tmp2 = stub->tmp2()->as_register(); + + assert(res == r0, "result must arrive in r0"); + + if (res != obj) { + __ mov(res, obj); + } + + // Check for null. + __ cbz(res, *stub->continuation()); + + // Check for object in cset. + __ mov(tmp2, ShenandoahHeap::in_cset_fast_test_addr()); + __ lsr(tmp1, res, ShenandoahHeapRegion::region_size_bytes_shift_jint()); + __ ldrb(tmp2, Address(tmp2, tmp1)); + __ cbz(tmp2, *stub->continuation()); + + // Check if object is already forwarded. + Label slow_path; + __ ldr(tmp1, Address(res, oopDesc::mark_offset_in_bytes())); + __ eon(tmp1, tmp1, zr); + __ ands(zr, tmp1, markOopDesc::lock_mask_in_place); + __ br(Assembler::NE, slow_path); + + // Decode forwarded object. + __ orr(tmp1, tmp1, markOopDesc::marked_value); + __ eon(res, tmp1, zr); + __ b(*stub->continuation()); + + __ bind(slow_path); + ce->store_parameter(res, 0); + ce->store_parameter(addr, 1); + __ far_call(RuntimeAddress(bs->load_reference_barrier_rt_code_blob()->code_begin())); + + __ b(*stub->continuation()); +} + +#undef __ + +#define __ sasm-> + +void ShenandoahBarrierSetAssembler::generate_c1_pre_barrier_runtime_stub(StubAssembler* sasm) { + __ prologue("shenandoah_pre_barrier", false); + + // arg0 : previous value of memory + + BarrierSet* bs = BarrierSet::barrier_set(); + + const Register pre_val = r0; + const Register thread = rthread; + const Register tmp = rscratch1; + + Address queue_index(thread, in_bytes(ShenandoahThreadLocalData::satb_mark_queue_index_offset())); + Address buffer(thread, in_bytes(ShenandoahThreadLocalData::satb_mark_queue_buffer_offset())); + + Label done; + Label runtime; + + // Is marking still active? + Address gc_state(thread, in_bytes(ShenandoahThreadLocalData::gc_state_offset())); + __ ldrb(tmp, gc_state); + __ tbz(tmp, ShenandoahHeap::MARKING_BITPOS, done); + + // Can we store original value in the thread's buffer? + __ ldr(tmp, queue_index); + __ cbz(tmp, runtime); + + __ sub(tmp, tmp, wordSize); + __ str(tmp, queue_index); + __ ldr(rscratch2, buffer); + __ add(tmp, tmp, rscratch2); + __ load_parameter(0, rscratch2); + __ str(rscratch2, Address(tmp, 0)); + __ b(done); + + __ bind(runtime); + __ push_call_clobbered_registers(); + __ load_parameter(0, pre_val); + __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::write_ref_field_pre_entry), pre_val, thread); + __ pop_call_clobbered_registers(); + __ bind(done); + + __ epilogue(); +} + +void ShenandoahBarrierSetAssembler::generate_c1_load_reference_barrier_runtime_stub(StubAssembler* sasm) { + __ prologue("shenandoah_load_reference_barrier", false); + // arg0 : object to be resolved + + __ push_call_clobbered_registers(); + __ load_parameter(0, r0); + __ load_parameter(1, r1); + if (UseCompressedOops) { + __ mov(lr, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_narrow)); + } else { + __ mov(lr, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier)); + } + __ blr(lr); + __ mov(rscratch1, r0); + __ pop_call_clobbered_registers(); + __ mov(r0, rscratch1); + + __ epilogue(); +} + +#undef __ + +#endif // COMPILER1 + +address ShenandoahBarrierSetAssembler::shenandoah_lrb() { + assert(_shenandoah_lrb != NULL, "need load reference barrier stub"); + return _shenandoah_lrb; +} + +#define __ cgen->assembler()-> + +// Shenandoah load reference barrier. +// +// Input: +// r0: OOP to evacuate. Not null. +// r1: load address +// +// Output: +// r0: Pointer to evacuated OOP. +// +// Trash rscratch1, rscratch2. Preserve everything else. +address ShenandoahBarrierSetAssembler::generate_shenandoah_lrb(StubCodeGenerator* cgen) { + + __ align(6); + StubCodeMark mark(cgen, "StubRoutines", "shenandoah_lrb"); + address start = __ pc(); + + Label slow_path; + __ mov(rscratch2, ShenandoahHeap::in_cset_fast_test_addr()); + __ lsr(rscratch1, r0, ShenandoahHeapRegion::region_size_bytes_shift_jint()); + __ ldrb(rscratch2, Address(rscratch2, rscratch1)); + __ tbnz(rscratch2, 0, slow_path); + __ ret(lr); + + __ bind(slow_path); + __ enter(); // required for proper stackwalking of RuntimeStub frame + + __ push_call_clobbered_registers(); + + if (UseCompressedOops) { + __ mov(lr, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_narrow)); + } else { + __ mov(lr, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier)); + } + __ blr(lr); + __ mov(rscratch1, r0); + __ pop_call_clobbered_registers(); + __ mov(r0, rscratch1); + + __ leave(); // required for proper stackwalking of RuntimeStub frame + __ ret(lr); + + return start; +} + +#undef __ + +void ShenandoahBarrierSetAssembler::barrier_stubs_init() { + if (ShenandoahLoadRefBarrier) { + int stub_code_size = 2048; + ResourceMark rm; + BufferBlob* bb = BufferBlob::create("shenandoah_barrier_stubs", stub_code_size); + CodeBuffer buf(bb); + StubCodeGenerator cgen(&buf); + _shenandoah_lrb = generate_shenandoah_lrb(&cgen); + } +}
diff --git a/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.hpp new file mode 100644 index 0000000..45a3fe8 --- /dev/null +++ b/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.hpp
@@ -0,0 +1,90 @@ +/* + * Copyright (c) 2018, Red Hat, Inc. All rights reserved. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef CPU_AARCH64_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_AARCH64_HPP +#define CPU_AARCH64_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_AARCH64_HPP + +#include "asm/macroAssembler.hpp" +#include "gc/shared/barrierSetAssembler.hpp" +#ifdef COMPILER1 +class LIR_Assembler; +class ShenandoahPreBarrierStub; +class ShenandoahLoadReferenceBarrierStub; +class StubAssembler; +#endif +class StubCodeGenerator; + +class ShenandoahBarrierSetAssembler: public BarrierSetAssembler { +private: + + static address _shenandoah_lrb; + + void satb_write_barrier_pre(MacroAssembler* masm, + Register obj, + Register pre_val, + Register thread, + Register tmp, + bool tosca_live, + bool expand_call); + void shenandoah_write_barrier_pre(MacroAssembler* masm, + Register obj, + Register pre_val, + Register thread, + Register tmp, + bool tosca_live, + bool expand_call); + + void resolve_forward_pointer(MacroAssembler* masm, Register dst, Register tmp = noreg); + void resolve_forward_pointer_not_null(MacroAssembler* masm, Register dst, Register tmp = noreg); + void load_reference_barrier(MacroAssembler* masm, Register dst, Address load_addr); + void load_reference_barrier_not_null(MacroAssembler* masm, Register dst, Address load_addr); + + address generate_shenandoah_lrb(StubCodeGenerator* cgen); + +public: + static address shenandoah_lrb(); + + void iu_barrier(MacroAssembler* masm, Register dst, Register tmp); + +#ifdef COMPILER1 + void gen_pre_barrier_stub(LIR_Assembler* ce, ShenandoahPreBarrierStub* stub); + void gen_load_reference_barrier_stub(LIR_Assembler* ce, ShenandoahLoadReferenceBarrierStub* stub); + void generate_c1_pre_barrier_runtime_stub(StubAssembler* sasm); + void generate_c1_load_reference_barrier_runtime_stub(StubAssembler* sasm); +#endif + + virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, + Register src, Register dst, Register count, RegSet saved_regs); + virtual void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Register dst, Address src, Register tmp1, Register tmp_thread); + virtual void store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Address dst, Register val, Register tmp1, Register tmp2); + virtual void try_resolve_jobject_in_native(MacroAssembler* masm, Register jni_env, + Register obj, Register tmp, Label& slowpath); + virtual void cmpxchg_oop(MacroAssembler* masm, Register addr, Register expected, Register new_val, + bool acquire, bool release, bool is_cae, Register result); + + virtual void barrier_stubs_init(); +}; + +#endif // CPU_AARCH64_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_AARCH64_HPP
diff --git a/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoah_aarch64.ad b/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoah_aarch64.ad new file mode 100644 index 0000000..d12bb55 --- /dev/null +++ b/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoah_aarch64.ad
@@ -0,0 +1,189 @@ +// +// Copyright (c) 2018, Red Hat, Inc. All rights reserved. +// +// This code is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License version 2 only, as +// published by the Free Software Foundation. +// +// This code is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// version 2 for more details (a copy is included in the LICENSE file that +// accompanied this code). +// +// You should have received a copy of the GNU General Public License version +// 2 along with this work; if not, write to the Free Software Foundation, +// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +// +// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +// or visit www.oracle.com if you need additional information or have any +// questions. +// +// + +source_hpp %{ +#include "gc/shenandoah/shenandoahBarrierSet.hpp" +#include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" +%} + +encode %{ + enc_class aarch64_enc_cmpxchg_oop_shenandoah(memory mem, iRegP oldval, iRegP newval, iRegPNoSp tmp, iRegINoSp res) %{ + MacroAssembler _masm(&cbuf); + guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); + Register tmp = $tmp$$Register; + __ mov(tmp, $oldval$$Register); // Must not clobber oldval. + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register, + /*acquire*/ false, /*release*/ true, /*is_cae*/ false, $res$$Register); + %} + + enc_class aarch64_enc_cmpxchg_acq_oop_shenandoah(memory mem, iRegP oldval, iRegP newval, iRegPNoSp tmp, iRegINoSp res) %{ + MacroAssembler _masm(&cbuf); + guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); + Register tmp = $tmp$$Register; + __ mov(tmp, $oldval$$Register); // Must not clobber oldval. + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register, + /*acquire*/ true, /*release*/ true, /*is_cae*/ false, $res$$Register); + %} +%} + +instruct compareAndSwapP_shenandoah(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, iRegPNoSp tmp, rFlagsReg cr) %{ + + match(Set res (ShenandoahCompareAndSwapP mem (Binary oldval newval))); + ins_cost(2 * VOLATILE_REF_COST); + + effect(TEMP tmp, KILL cr); + + format %{ + "cmpxchg_shenandoah_oop $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval with temp $tmp" + %} + + ins_encode(aarch64_enc_cmpxchg_oop_shenandoah(mem, oldval, newval, tmp, res)); + + ins_pipe(pipe_slow); +%} + +instruct compareAndSwapN_shenandoah(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval, iRegNNoSp tmp, rFlagsReg cr) %{ + + match(Set res (ShenandoahCompareAndSwapN mem (Binary oldval newval))); + ins_cost(2 * VOLATILE_REF_COST); + + effect(TEMP tmp, KILL cr); + + format %{ + "cmpxchgw_shenandoah_narrow_oop $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval with temp $tmp" + %} + + ins_encode %{ + Register tmp = $tmp$$Register; + __ mov(tmp, $oldval$$Register); // Must not clobber oldval. + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register, /*acquire*/ false, /*release*/ true, /*is_cae*/ false, $res$$Register); + %} + + ins_pipe(pipe_slow); +%} + +instruct compareAndSwapPAcq_shenandoah(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, iRegPNoSp tmp, rFlagsReg cr) %{ + + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (ShenandoahCompareAndSwapP mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + + effect(TEMP tmp, KILL cr); + + format %{ + "cmpxchg_acq_shenandoah_oop $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval with temp $tmp" + %} + + ins_encode(aarch64_enc_cmpxchg_acq_oop_shenandoah(mem, oldval, newval, tmp, res)); + + ins_pipe(pipe_slow); +%} + +instruct compareAndSwapNAcq_shenandoah(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval, iRegNNoSp tmp, rFlagsReg cr) %{ + + predicate(needs_acquiring_load_exclusive(n)); + match(Set res (ShenandoahCompareAndSwapN mem (Binary oldval newval))); + ins_cost(VOLATILE_REF_COST); + + effect(TEMP tmp, KILL cr); + + format %{ + "cmpxchgw_acq_shenandoah_narrow_oop $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval with temp $tmp" + %} + + ins_encode %{ + Register tmp = $tmp$$Register; + __ mov(tmp, $oldval$$Register); // Must not clobber oldval. + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register, /*acquire*/ true, /*release*/ true, /*is_cae*/ false, $res$$Register); + %} + + ins_pipe(pipe_slow); +%} + +instruct compareAndExchangeN_shenandoah(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval, iRegNNoSp tmp, rFlagsReg cr) %{ + match(Set res (ShenandoahCompareAndExchangeN mem (Binary oldval newval))); + ins_cost(3 * VOLATILE_REF_COST); + effect(TEMP_DEF res, TEMP tmp, KILL cr); + format %{ + "cmpxchg_oop_shenandoah $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval" + %} + ins_encode %{ + Register tmp = $tmp$$Register; + __ mov(tmp, $oldval$$Register); // Must not clobber oldval. + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register, + /*acquire*/ false, /*release*/ true, /*is_cae*/ true, $res$$Register); + %} + ins_pipe(pipe_slow); +%} + +instruct compareAndExchangeP_shenandoah(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, iRegPNoSp tmp, rFlagsReg cr) %{ + match(Set res (ShenandoahCompareAndExchangeP mem (Binary oldval newval))); + ins_cost(3 * VOLATILE_REF_COST); + effect(TEMP_DEF res, TEMP tmp, KILL cr); + format %{ + "cmpxchg_oop_shenandoah $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval with temp $tmp" + %} + ins_encode %{ + Register tmp = $tmp$$Register; + __ mov(tmp, $oldval$$Register); // Must not clobber oldval. + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register, + /*acquire*/ false, /*release*/ true, /*is_cae*/ true, $res$$Register); + %} + ins_pipe(pipe_slow); +%} + +instruct weakCompareAndSwapN_shenandoah(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval, iRegNNoSp tmp, rFlagsReg cr) %{ + match(Set res (ShenandoahWeakCompareAndSwapN mem (Binary oldval newval))); + ins_cost(3 * VOLATILE_REF_COST); + effect(TEMP tmp, KILL cr); + format %{ + "cmpxchg_oop_shenandoah $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval" + %} + ins_encode %{ + Register tmp = $tmp$$Register; + __ mov(tmp, $oldval$$Register); // Must not clobber oldval. + // Weak is not currently supported by ShenandoahBarrierSet::cmpxchg_oop + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register, + /*acquire*/ false, /*release*/ true, /*is_cae*/ false, $res$$Register); + %} + ins_pipe(pipe_slow); +%} + +instruct weakCompareAndSwapP_shenandoah(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, iRegPNoSp tmp, rFlagsReg cr) %{ + match(Set res (ShenandoahWeakCompareAndSwapP mem (Binary oldval newval))); + ins_cost(3 * VOLATILE_REF_COST); + effect(TEMP tmp, KILL cr); + format %{ + "cmpxchg_oop_shenandoah $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval" + %} + ins_encode %{ + Register tmp = $tmp$$Register; + __ mov(tmp, $oldval$$Register); // Must not clobber oldval. + // Weak is not currently supported by ShenandoahBarrierSet::cmpxchg_oop + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register, + /*acquire*/ false, /*release*/ true, /*is_cae*/ false, $res$$Register); + %} + ins_pipe(pipe_slow); +%} + +
diff --git a/src/hotspot/cpu/aarch64/globals_aarch64.hpp b/src/hotspot/cpu/aarch64/globals_aarch64.hpp index a8b1efb..071845e 100644 --- a/src/hotspot/cpu/aarch64/globals_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/globals_aarch64.hpp
@@ -32,7 +32,6 @@ // Sets the default values for platform dependent flags used by the runtime system. // (see globals.hpp) -define_pd_global(bool, ShareVtableStubs, true); define_pd_global(bool, NeedsDeoptSuspend, false); // only register window machines need this define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks @@ -85,48 +84,6 @@ define_pd_global(intx, InlineSmallCode, 1000); #endif -#ifdef BUILTIN_SIM -#define UseBuiltinSim true -#define ARCH_FLAGS(develop, \ - product, \ - diagnostic, \ - experimental, \ - notproduct, \ - range, \ - constraint, \ - writeable) \ - \ - product(bool, NotifySimulator, UseBuiltinSim, \ - "tell the AArch64 sim where we are in method code") \ - \ - product(bool, UseSimulatorCache, false, \ - "tell sim to cache memory updates until exclusive op occurs") \ - \ - product(bool, DisableBCCheck, true, \ - "tell sim not to invoke bccheck callback") \ - \ - product(bool, NearCpool, true, \ - "constant pool is close to instructions") \ - \ - product(bool, UseBarriersForVolatile, false, \ - "Use memory barriers to implement volatile accesses") \ - \ - product(bool, UseCRC32, false, \ - "Use CRC32 instructions for CRC32 computation") \ - \ - product(bool, UseLSE, false, \ - "Use LSE instructions") \ - -// Don't attempt to use Neon on builtin sim until builtin sim supports it -#define UseCRC32 false -#define UseSIMDForMemoryOps false -#define AvoidUnalignedAcesses false - -#else -#define UseBuiltinSim false -#define NotifySimulator false -#define UseSimulatorCache false -#define DisableBCCheck true #define ARCH_FLAGS(develop, \ product, \ diagnostic, \ @@ -165,7 +122,5 @@ "Use prfm hint with specified distance in compiled code." \ "Value -1 means off.") \ range(-1, 4096) -#endif - #endif // CPU_AARCH64_VM_GLOBALS_AARCH64_HPP
diff --git a/src/hotspot/cpu/aarch64/icache_aarch64.cpp b/src/hotspot/cpu/aarch64/icache_aarch64.cpp index 9cad1ea..86b3dc3 100644 --- a/src/hotspot/cpu/aarch64/icache_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/icache_aarch64.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, Red Hat Inc. All rights reserved. + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020 Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -24,7 +24,6 @@ */ #include "precompiled.hpp" -#include "asm/macroAssembler.hpp" #include "runtime/icache.hpp" extern void aarch64TestHook(); @@ -36,5 +35,7 @@ } void ICache::initialize() { +#ifdef ASSERT aarch64TestHook(); +#endif }
diff --git a/src/hotspot/cpu/aarch64/immediate_aarch64.cpp b/src/hotspot/cpu/aarch64/immediate_aarch64.cpp index 7410c07..7a67d95 100644 --- a/src/hotspot/cpu/aarch64/immediate_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/immediate_aarch64.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, Red Hat Inc. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -23,7 +23,7 @@ */ #include <stdlib.h> -#include "decode_aarch64.hpp" +#include <stdint.h> #include "immediate_aarch64.hpp" // there are at most 2^13 possible logical immediate encodings @@ -35,14 +35,14 @@ // for forward lookup we just use a direct array lookup // and assume that the cient has supplied a valid encoding // table[encoding] = immediate -static u_int64_t LITable[LI_TABLE_SIZE]; +static uint64_t LITable[LI_TABLE_SIZE]; // for reverse lookup we need a sparse map so we store a table of // immediate and encoding pairs sorted by immediate value struct li_pair { - u_int64_t immediate; - u_int32_t encoding; + uint64_t immediate; + uint32_t encoding; }; static struct li_pair InverseLITable[LI_TABLE_SIZE]; @@ -64,26 +64,71 @@ // helper functions used by expandLogicalImmediate // for i = 1, ... N result<i-1> = 1 other bits are zero -static inline u_int64_t ones(int N) +static inline uint64_t ones(int N) { - return (N == 64 ? (u_int64_t)-1UL : ((1UL << N) - 1)); + return (N == 64 ? -1ULL : (1ULL << N) - 1); +} + +/* + * bit twiddling helpers for instruction decode + */ + +// 32 bit mask with bits [hi,...,lo] set +static inline uint32_t mask32(int hi = 31, int lo = 0) +{ + int nbits = (hi + 1) - lo; + return ((1 << nbits) - 1) << lo; +} + +static inline uint64_t mask64(int hi = 63, int lo = 0) +{ + int nbits = (hi + 1) - lo; + return ((1L << nbits) - 1) << lo; +} + +// pick bits [hi,...,lo] from val +static inline uint32_t pick32(uint32_t val, int hi = 31, int lo = 0) +{ + return (val & mask32(hi, lo)); +} + +// pick bits [hi,...,lo] from val +static inline uint64_t pick64(uint64_t val, int hi = 31, int lo = 0) +{ + return (val & mask64(hi, lo)); +} + +// mask [hi,lo] and shift down to start at bit 0 +static inline uint32_t pickbits32(uint32_t val, int hi = 31, int lo = 0) +{ + return (pick32(val, hi, lo) >> lo); +} + +// mask [hi,lo] and shift down to start at bit 0 +static inline uint64_t pickbits64(uint64_t val, int hi = 63, int lo = 0) +{ + return (pick64(val, hi, lo) >> lo); } // result<0> to val<N> -static inline u_int64_t pickbit(u_int64_t val, int N) +static inline uint64_t pickbit(uint64_t val, int N) { return pickbits64(val, N, N); } +static inline uint32_t uimm(uint32_t val, int hi, int lo) +{ + return pickbits32(val, hi, lo); +} // SPEC bits(M*N) Replicate(bits(M) x, integer N); // this is just an educated guess -u_int64_t replicate(u_int64_t bits, int nbits, int count) +uint64_t replicate(uint64_t bits, int nbits, int count) { - u_int64_t result = 0; + uint64_t result = 0; // nbits may be 64 in which case we want mask to be -1 - u_int64_t mask = ones(nbits); + uint64_t mask = ones(nbits); for (int i = 0; i < count ; i++) { result <<= nbits; result |= (bits & mask); @@ -96,24 +141,24 @@ // encoding must be treated as an UNALLOC instruction // construct a 32 bit immediate value for a logical immediate operation -int expandLogicalImmediate(u_int32_t immN, u_int32_t immr, - u_int32_t imms, u_int64_t &bimm) +int expandLogicalImmediate(uint32_t immN, uint32_t immr, + uint32_t imms, uint64_t &bimm) { - int len; // ought to be <= 6 - u_int32_t levels; // 6 bits - u_int32_t tmask_and; // 6 bits - u_int32_t wmask_and; // 6 bits - u_int32_t tmask_or; // 6 bits - u_int32_t wmask_or; // 6 bits - u_int64_t imm64; // 64 bits - u_int64_t tmask, wmask; // 64 bits - u_int32_t S, R, diff; // 6 bits? + int len; // ought to be <= 6 + uint32_t levels; // 6 bits + uint32_t tmask_and; // 6 bits + uint32_t wmask_and; // 6 bits + uint32_t tmask_or; // 6 bits + uint32_t wmask_or; // 6 bits + uint64_t imm64; // 64 bits + uint64_t tmask, wmask; // 64 bits + uint32_t S, R, diff; // 6 bits? if (immN == 1) { len = 6; // looks like 7 given the spec above but this cannot be! } else { len = 0; - u_int32_t val = (~imms & 0x3f); + uint32_t val = (~imms & 0x3f); for (int i = 5; i > 0; i--) { if (val & (1 << i)) { len = i; @@ -126,7 +171,7 @@ // for valid inputs leading 1s in immr must be less than leading // zeros in imms int len2 = 0; // ought to be < len - u_int32_t val2 = (~immr & 0x3f); + uint32_t val2 = (~immr & 0x3f); for (int i = 5; i > 0; i--) { if (!(val2 & (1 << i))) { len2 = i; @@ -155,12 +200,12 @@ for (int i = 0; i < 6; i++) { int nbits = 1 << i; - u_int64_t and_bit = pickbit(tmask_and, i); - u_int64_t or_bit = pickbit(tmask_or, i); - u_int64_t and_bits_sub = replicate(and_bit, 1, nbits); - u_int64_t or_bits_sub = replicate(or_bit, 1, nbits); - u_int64_t and_bits_top = (and_bits_sub << nbits) | ones(nbits); - u_int64_t or_bits_top = (0 << nbits) | or_bits_sub; + uint64_t and_bit = pickbit(tmask_and, i); + uint64_t or_bit = pickbit(tmask_or, i); + uint64_t and_bits_sub = replicate(and_bit, 1, nbits); + uint64_t or_bits_sub = replicate(or_bit, 1, nbits); + uint64_t and_bits_top = (and_bits_sub << nbits) | ones(nbits); + uint64_t or_bits_top = (0 << nbits) | or_bits_sub; tmask = ((tmask & (replicate(and_bits_top, 2 * nbits, 32 / nbits))) @@ -174,12 +219,12 @@ for (int i = 0; i < 6; i++) { int nbits = 1 << i; - u_int64_t and_bit = pickbit(wmask_and, i); - u_int64_t or_bit = pickbit(wmask_or, i); - u_int64_t and_bits_sub = replicate(and_bit, 1, nbits); - u_int64_t or_bits_sub = replicate(or_bit, 1, nbits); - u_int64_t and_bits_top = (ones(nbits) << nbits) | and_bits_sub; - u_int64_t or_bits_top = (or_bits_sub << nbits) | 0; + uint64_t and_bit = pickbit(wmask_and, i); + uint64_t or_bit = pickbit(wmask_or, i); + uint64_t and_bits_sub = replicate(and_bit, 1, nbits); + uint64_t or_bits_sub = replicate(or_bit, 1, nbits); + uint64_t and_bits_top = (ones(nbits) << nbits) | and_bits_sub; + uint64_t or_bits_top = (or_bits_sub << nbits) | 0; wmask = ((wmask & (replicate(and_bits_top, 2 * nbits, 32 / nbits))) @@ -204,9 +249,9 @@ { li_table_entry_count = 0; for (unsigned index = 0; index < LI_TABLE_SIZE; index++) { - u_int32_t N = uimm(index, 12, 12); - u_int32_t immr = uimm(index, 11, 6); - u_int32_t imms = uimm(index, 5, 0); + uint32_t N = uimm(index, 12, 12); + uint32_t immr = uimm(index, 11, 6); + uint32_t imms = uimm(index, 5, 0); if (expandLogicalImmediate(N, immr, imms, LITable[index])) { InverseLITable[li_table_entry_count].immediate = LITable[index]; InverseLITable[li_table_entry_count].encoding = index; @@ -220,12 +265,12 @@ // public APIs provided for logical immediate lookup and reverse lookup -u_int64_t logical_immediate_for_encoding(u_int32_t encoding) +uint64_t logical_immediate_for_encoding(uint32_t encoding) { return LITable[encoding]; } -u_int32_t encoding_for_logical_immediate(u_int64_t immediate) +uint32_t encoding_for_logical_immediate(uint64_t immediate) { struct li_pair pair; struct li_pair *result; @@ -249,15 +294,15 @@ // fpimm[3:0] = fraction (assuming leading 1) // i.e. F = s * 1.f * 2^(e - b) -u_int64_t fp_immediate_for_encoding(u_int32_t imm8, int is_dp) +uint64_t fp_immediate_for_encoding(uint32_t imm8, int is_dp) { union { float fpval; double dpval; - u_int64_t val; + uint64_t val; }; - u_int32_t s, e, f; + uint32_t s, e, f; s = (imm8 >> 7 ) & 0x1; e = (imm8 >> 4) & 0x7; f = imm8 & 0xf; @@ -285,7 +330,7 @@ return val; } -u_int32_t encoding_for_fp_immediate(float immediate) +uint32_t encoding_for_fp_immediate(float immediate) { // given a float which is of the form // @@ -297,10 +342,10 @@ union { float fpval; - u_int32_t val; + uint32_t val; }; fpval = immediate; - u_int32_t s, r, f, res; + uint32_t s, r, f, res; // sign bit is 31 s = (val >> 31) & 0x1; // exponent is bits 30-23 but we only want the bottom 3 bits
diff --git a/src/hotspot/cpu/aarch64/immediate_aarch64.hpp b/src/hotspot/cpu/aarch64/immediate_aarch64.hpp index 6610772..0cbdb56 100644 --- a/src/hotspot/cpu/aarch64/immediate_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/immediate_aarch64.hpp
@@ -46,9 +46,9 @@ * encoding then a map lookup will return 0xffffffff. */ -u_int64_t logical_immediate_for_encoding(u_int32_t encoding); -u_int32_t encoding_for_logical_immediate(u_int64_t immediate); -u_int64_t fp_immediate_for_encoding(u_int32_t imm8, int is_dp); -u_int32_t encoding_for_fp_immediate(float immediate); +uint64_t logical_immediate_for_encoding(uint32_t encoding); +uint32_t encoding_for_logical_immediate(uint64_t immediate); +uint64_t fp_immediate_for_encoding(uint32_t imm8, int is_dp); +uint32_t encoding_for_fp_immediate(float immediate); #endif // _IMMEDIATE_H
diff --git a/src/hotspot/cpu/aarch64/interp_masm_aarch64.cpp b/src/hotspot/cpu/aarch64/interp_masm_aarch64.cpp index 0930fc6..3c34f36 100644 --- a/src/hotspot/cpu/aarch64/interp_masm_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/interp_masm_aarch64.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, Red Hat Inc. All rights reserved. + * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -168,7 +168,7 @@ } void InterpreterMacroAssembler::get_dispatch() { - unsigned long offset; + uint64_t offset; adrp(rdispatch, ExternalAddress((address)Interpreter::dispatch_table()), offset); lea(rdispatch, Address(rdispatch, offset)); } @@ -654,14 +654,16 @@ // remove activation // get sender esp - ldr(esp, + ldr(rscratch2, Address(rfp, frame::interpreter_frame_sender_sp_offset * wordSize)); if (StackReservedPages > 0) { // testing if reserved zone needs to be re-enabled Label no_reserved_zone_enabling; + // look for an overflow into the stack reserved zone, i.e. + // interpreter_frame_sender_sp <= JavaThread::reserved_stack_activation ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset())); - cmp(esp, rscratch1); + cmp(rscratch2, rscratch1); br(Assembler::LS, no_reserved_zone_enabling); call_VM_leaf( @@ -672,6 +674,9 @@ bind(no_reserved_zone_enabling); } + + // restore sender esp + mov(esp, rscratch2); // remove frame anchor leave(); // If we're returning to interpreted code we will shortly be @@ -754,7 +759,7 @@ // copy mov(rscratch1, sp); sub(swap_reg, swap_reg, rscratch1); - ands(swap_reg, swap_reg, (unsigned long)(7 - os::vm_page_size())); + ands(swap_reg, swap_reg, (uint64_t)(7 - os::vm_page_size())); // Save the test result, for recursive case, the result is zero str(swap_reg, Address(lock_reg, mark_offset));
diff --git a/src/hotspot/cpu/aarch64/interp_masm_aarch64.hpp b/src/hotspot/cpu/aarch64/interp_masm_aarch64.hpp index 1143f6b..2b59b19 100644 --- a/src/hotspot/cpu/aarch64/interp_masm_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/interp_masm_aarch64.hpp
@@ -38,8 +38,6 @@ protected: protected: - using MacroAssembler::call_VM_leaf_base; - // Interpreter specific version of call_VM_base using MacroAssembler::call_VM_leaf_base;
diff --git a/src/hotspot/cpu/aarch64/interpreterRT_aarch64.cpp b/src/hotspot/cpu/aarch64/interpreterRT_aarch64.cpp index 86a7478..4496d39 100644 --- a/src/hotspot/cpu/aarch64/interpreterRT_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/interpreterRT_aarch64.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, Red Hat Inc. All rights reserved. + * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -260,29 +260,6 @@ // generate code to handle arguments iterate(fingerprint); - // set the call format - // n.b. allow extra 1 for the JNI_Env in c_rarg0 - unsigned int call_format = ((_num_int_args + 1) << 6) | (_num_fp_args << 2); - - switch (method()->result_type()) { - case T_VOID: - call_format |= MacroAssembler::ret_type_void; - break; - case T_FLOAT: - call_format |= MacroAssembler::ret_type_float; - break; - case T_DOUBLE: - call_format |= MacroAssembler::ret_type_double; - break; - default: - call_format |= MacroAssembler::ret_type_integral; - break; - } - - // // store the call format in the method - // __ movw(r0, call_format); - // __ str(r0, Address(rmethod, Method::call_format_offset())); - // return result handler __ lea(r0, ExternalAddress(Interpreter::result_handler(method()->result_type()))); __ ret(lr); @@ -370,7 +347,7 @@ if (_num_fp_args < Argument::n_float_register_parameters_c) { *_fp_args++ = from_obj; - *_fp_identifiers |= (1 << _num_fp_args); // mark as double + *_fp_identifiers |= (1ull << _num_fp_args); // mark as double _num_fp_args++; } else { *_to++ = from_obj; @@ -393,28 +370,6 @@ _num_fp_args = 0; } - // n.b. allow extra 1 for the JNI_Env in c_rarg0 - unsigned int get_call_format() - { - unsigned int call_format = ((_num_int_args + 1) << 6) | (_num_fp_args << 2); - - switch (method()->result_type()) { - case T_VOID: - call_format |= MacroAssembler::ret_type_void; - break; - case T_FLOAT: - call_format |= MacroAssembler::ret_type_float; - break; - case T_DOUBLE: - call_format |= MacroAssembler::ret_type_double; - break; - default: - call_format |= MacroAssembler::ret_type_integral; - break; - } - - return call_format; - } }; @@ -428,10 +383,7 @@ // handle arguments SlowSignatureHandler ssh(m, (address)from, to); - ssh.iterate(UCONST64(-1)); - - // // set the call format - // method->set_call_format(ssh.get_call_format()); + ssh.iterate((uint64_t)CONST64(-1)); // return result handler return Interpreter::result_handler(m->result_type());
diff --git a/src/hotspot/cpu/aarch64/interpreterRT_aarch64.hpp b/src/hotspot/cpu/aarch64/interpreterRT_aarch64.hpp index 70dd029..a403bf4 100644 --- a/src/hotspot/cpu/aarch64/interpreterRT_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/interpreterRT_aarch64.hpp
@@ -34,7 +34,6 @@ class SignatureHandlerGenerator: public NativeSignatureIterator { private: MacroAssembler* _masm; - unsigned int _call_format; unsigned int _num_fp_args; unsigned int _num_int_args; int _stack_offset;
diff --git a/src/hotspot/cpu/aarch64/jniFastGetField_aarch64.cpp b/src/hotspot/cpu/aarch64/jniFastGetField_aarch64.cpp index f7fbe63..655baf9 100644 --- a/src/hotspot/cpu/aarch64/jniFastGetField_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/jniFastGetField_aarch64.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2004, 2017, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, Red Hat Inc. All rights reserved. + * Copyright (c) 2004, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -73,7 +73,7 @@ Label slow; - unsigned long offset; + uint64_t offset; __ adrp(rcounter_addr, SafepointSynchronize::safepoint_counter_addr(), offset); Address safepoint_counter_addr(rcounter_addr, offset);
diff --git a/src/hotspot/cpu/aarch64/jvmciCodeInstaller_aarch64.cpp b/src/hotspot/cpu/aarch64/jvmciCodeInstaller_aarch64.cpp index f9b3ff7..e477ca5 100644 --- a/src/hotspot/cpu/aarch64/jvmciCodeInstaller_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/jvmciCodeInstaller_aarch64.cpp
@@ -21,6 +21,7 @@ * questions. */ +#include "asm/macroAssembler.hpp" #include "jvmci/jvmciCodeInstaller.hpp" #include "jvmci/jvmciRuntime.hpp" #include "jvmci/jvmciCompilerToVM.hpp"
diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp index 1895fde..578e0d1 100644 --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -40,16 +40,21 @@ #include "oops/accessDecorators.hpp" #include "oops/compressedOops.inline.hpp" #include "oops/klass.inline.hpp" -#include "oops/oop.hpp" -#include "opto/compile.hpp" -#include "opto/intrinsicnode.hpp" -#include "opto/node.hpp" #include "runtime/biasedLocking.hpp" #include "runtime/icache.hpp" #include "runtime/interfaceSupport.inline.hpp" #include "runtime/jniHandles.inline.hpp" #include "runtime/sharedRuntime.hpp" #include "runtime/thread.hpp" +#ifdef COMPILER1 +#include "c1/c1_LIRAssembler.hpp" +#endif +#ifdef COMPILER2 +#include "oops/oop.hpp" +#include "opto/compile.hpp" +#include "opto/intrinsicnode.hpp" +#include "opto/node.hpp" +#endif #ifdef PRODUCT #define BLOCK_COMMENT(str) /* nothing */ @@ -65,8 +70,8 @@ // Return the total length (in bytes) of the instructions. int MacroAssembler::pd_patch_instruction_size(address branch, address target) { int instructions = 1; - assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant"); - long offset = (target - branch) >> 2; + assert((uint64_t)target < (1ull << 48), "48-bit overflow in address constant"); + intptr_t offset = (target - branch) >> 2; unsigned insn = *(unsigned*)branch; if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) { // Load register (literal) @@ -88,7 +93,7 @@ offset = target-branch; int shift = Instruction_aarch64::extract(insn, 31, 31); if (shift) { - u_int64_t dest = (u_int64_t)target; + uint64_t dest = (uint64_t)target; uint64_t pc_page = (uint64_t)branch >> 12; uint64_t adr_page = (uint64_t)target >> 12; unsigned offset_lo = dest & 0xfff; @@ -129,9 +134,9 @@ Instruction_aarch64::extract(insn2, 4, 0)) { // movk #imm16<<32 Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32); - long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L); - long pc_page = (long)branch >> 12; - long adr_page = (long)dest >> 12; + uintptr_t dest = ((uintptr_t)target & 0xffffffffULL) | ((uintptr_t)branch & 0xffff00000000ULL); + uintptr_t pc_page = (uintptr_t)branch >> 12; + uintptr_t adr_page = (uintptr_t)dest >> 12; offset = adr_page - pc_page; instructions = 2; } @@ -141,7 +146,7 @@ Instruction_aarch64::spatch(branch, 23, 5, offset); Instruction_aarch64::patch(branch, 30, 29, offset_lo); } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) { - u_int64_t dest = (u_int64_t)target; + uint64_t dest = (uint64_t)target; // Move wide constant assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch"); assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch"); @@ -200,7 +205,7 @@ } address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) { - long offset = 0; + intptr_t offset = 0; if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) { // Load register (literal) offset = Instruction_aarch64::sextract(insn, 23, 5); @@ -267,13 +272,13 @@ ShouldNotReachHere(); } } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) { - u_int32_t *insns = (u_int32_t *)insn_addr; + uint32_t *insns = (uint32_t *)insn_addr; // Move wide constant: movz, movk, movk. See movptr(). assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch"); assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch"); - return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5)) - + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16) - + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32)); + return address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5)) + + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16) + + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32)); } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { return 0; @@ -372,15 +377,9 @@ Register last_java_fp, address last_java_pc, Register scratch) { - if (last_java_pc != NULL) { - adr(scratch, last_java_pc); - } else { - // FIXME: This is almost never correct. We should delete all - // cases of set_last_Java_frame with last_java_pc=NULL and use the - // correct return address instead. - adr(scratch, pc()); - } + assert(last_java_pc != NULL, "must provide a valid PC"); + adr(scratch, last_java_pc); str(scratch, Address(rthread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset())); @@ -397,7 +396,7 @@ } else { InstructionMark im(this); L.add_patch_at(code(), locator()); - set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch); + set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch); } } @@ -406,7 +405,7 @@ assert(CodeCache::find_blob(entry.target()) != NULL, "destination of far call not found in code cache"); if (far_branches()) { - unsigned long offset; + uintptr_t offset; // We can use ADRP here because we know that the total size of // the code cache cannot exceed 2Gb. adrp(tmp, entry, offset); @@ -424,7 +423,7 @@ assert(CodeCache::find_blob(entry.target()) != NULL, "destination of far call not found in code cache"); if (far_branches()) { - unsigned long offset; + uintptr_t offset; // We can use ADRP here because we know that the total size of // the code cache cannot exceed 2Gb. adrp(tmp, entry, offset); @@ -701,6 +700,11 @@ // do the call, remove parameters MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l); + // lr could be poisoned with PAC signature during throw_pending_exception + // if it was tail-call optimized by compiler, since lr is not callee-saved + // reload it with proper value + adr(lr, l); + // reset last Java frame // Only interpreter should have to clear fp reset_last_Java_frame(true); @@ -741,15 +745,19 @@ // We need a trampoline if branches are far. if (far_branches()) { + bool in_scratch_emit_size = false; +#ifdef COMPILER2 // We don't want to emit a trampoline if C2 is generating dummy // code during its branch shortening phase. CompileTask* task = ciEnv::current()->task(); - bool in_scratch_emit_size = + in_scratch_emit_size = (task != NULL && is_c2_compile(task->comp_level()) && Compile::current()->in_scratch_emit_size()); +#endif if (!in_scratch_emit_size) { address stub = emit_trampoline_stub(offset(), entry.target()); if (stub == NULL) { + postcond(pc() == badAddress); return NULL; // CodeCache is full } } @@ -763,6 +771,7 @@ bl(pc()); } // just need to return a non-null address + postcond(pc() != badAddress); return pc(); } @@ -780,7 +789,9 @@ address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset, address dest) { - address stub = start_a_stub(Compile::MAX_stubs_size/2); + // Max stub size: alignment nop, TrampolineStub. + address stub = start_a_stub(NativeInstruction::instruction_size + + NativeCallTrampolineStub::instruction_size); if (stub == NULL) { return NULL; // CodeBuffer::expand failed } @@ -812,6 +823,18 @@ return stub_start_addr; } +void MacroAssembler::emit_static_call_stub() { + // CompiledDirectStaticCall::set_to_interpreted knows the + // exact layout of this stub. + + isb(); + mov_metadata(rmethod, (Metadata*)NULL); + + // Jump to the entry point of the i2c stub. + movptr(rscratch1, 0); + br(rscratch1); +} + void MacroAssembler::c2bool(Register x) { // implements x == 0 ? 0 : 1 // note: must only look at least-significant byte of x @@ -824,7 +847,7 @@ address MacroAssembler::ic_call(address entry, jint method_index) { RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); // address const_ptr = long_constant((jlong)Universe::non_oop_word()); - // unsigned long offset; + // uintptr_t offset; // ldr_constant(rscratch2, const_ptr); movptr(rscratch2, (uintptr_t)Universe::non_oop_word()); return trampoline_call(Address(entry, rh)); @@ -959,17 +982,6 @@ return RegisterOrConstant(tmp); } - -void MacroAssembler:: notify(int type) { - if (type == bytecode_start) { - // set_last_Java_frame(esp, rfp, (address)NULL); - Assembler:: notify(type); - // reset_last_Java_frame(true); - } - else - Assembler:: notify(type); -} - // Look up the method for a megamorphic invokeinterface call. // The target method is determined by <intf_klass, itable_index>. // The receiver klass is in recv_klass. @@ -1019,27 +1031,22 @@ // } Label search, found_method; - for (int peel = 1; peel >= 0; peel--) { - ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); - cmp(intf_klass, method_result); - - if (peel) { - br(Assembler::EQ, found_method); - } else { - br(Assembler::NE, search); - // (invert the test to fall through to found_method...) - } - - if (!peel) break; - - bind(search); - - // Check that the previous entry is non-null. A null entry means that - // the receiver class doesn't implement the interface, and wasn't the - // same as when the caller was compiled. - cbz(method_result, L_no_such_interface); + ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); + cmp(intf_klass, method_result); + br(Assembler::EQ, found_method); + bind(search); + // Check that the previous entry is non-null. A null entry means that + // the receiver class doesn't implement the interface, and wasn't the + // same as when the caller was compiled. + cbz(method_result, L_no_such_interface); + if (itableOffsetEntry::interface_offset_in_bytes() != 0) { add(scan_temp, scan_temp, scan_step); + ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); + } else { + ldr(method_result, Address(pre(scan_temp, scan_step))); } + cmp(intf_klass, method_result); + br(Assembler::NE, search); bind(found_method); @@ -1312,7 +1319,7 @@ stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); mov(r0, reg); - mov(rscratch1, (address)b); + movptr(rscratch1, (uintptr_t)(address)b); // call indirectly to solve generation ordering problem lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); @@ -1348,7 +1355,7 @@ } else { ldr(r0, addr); } - mov(rscratch1, (address)b); + movptr(rscratch1, (uintptr_t)(address)b); // call indirectly to solve generation ordering problem lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); @@ -1383,22 +1390,12 @@ void MacroAssembler::call_VM_leaf_base(address entry_point, int number_of_arguments, Label *retaddr) { - call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr); -} - -void MacroAssembler::call_VM_leaf_base1(address entry_point, - int number_of_gp_arguments, - int number_of_fp_arguments, - ret_type type, - Label *retaddr) { Label E, L; stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize))); - // We add 1 to number_of_arguments because the thread in arg0 is - // not counted mov(rscratch1, entry_point); - blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type); + blr(rscratch1); if (retaddr) bind(*retaddr); @@ -1483,7 +1480,7 @@ void MacroAssembler::mov(Register r, Address dest) { code_section()->relocate(pc(), dest.rspec()); - u_int64_t imm64 = (u_int64_t)dest.target(); + uint64_t imm64 = (uint64_t)dest.target(); movptr(r, imm64); } @@ -1499,7 +1496,7 @@ block_comment(buffer); } #endif - assert(imm64 < (1ul << 48), "48-bit overflow in address constant"); + assert(imm64 < (1ull << 48), "48-bit overflow in address constant"); movz(r, imm64 & 0xffff); imm64 >>= 16; movk(r, imm64 & 0xffff, 16); @@ -1516,20 +1513,20 @@ // imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh // imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh // T1D/T2D: invalid -void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) { +void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint32_t imm32) { assert(T != T1D && T != T2D, "invalid arrangement"); if (T == T8B || T == T16B) { assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)"); movi(Vd, T, imm32 & 0xff, 0); return; } - u_int32_t nimm32 = ~imm32; + uint32_t nimm32 = ~imm32; if (T == T4H || T == T8H) { assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)"); imm32 &= 0xffff; nimm32 &= 0xffff; } - u_int32_t x = imm32; + uint32_t x = imm32; int movi_cnt = 0; int movn_cnt = 0; while (x) { if (x & 0xff) movi_cnt++; x >>= 8; } @@ -1553,7 +1550,7 @@ } } -void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64) +void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64) { #ifndef PRODUCT { @@ -1567,7 +1564,7 @@ } else { // we can use a combination of MOVZ or MOVN with // MOVK to build up the constant - u_int64_t imm_h[4]; + uint64_t imm_h[4]; int zero_count = 0; int neg_count = 0; int i; @@ -1588,7 +1585,7 @@ } else if (zero_count == 3) { for (i = 0; i < 4; i++) { if (imm_h[i] != 0L) { - movz(dst, (u_int32_t)imm_h[i], (i << 4)); + movz(dst, (uint32_t)imm_h[i], (i << 4)); break; } } @@ -1596,7 +1593,7 @@ // one MOVN will do for (int i = 0; i < 4; i++) { if (imm_h[i] != 0xffffL) { - movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); + movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4)); break; } } @@ -1604,69 +1601,69 @@ // one MOVZ and one MOVK will do for (i = 0; i < 3; i++) { if (imm_h[i] != 0L) { - movz(dst, (u_int32_t)imm_h[i], (i << 4)); + movz(dst, (uint32_t)imm_h[i], (i << 4)); i++; break; } } for (;i < 4; i++) { if (imm_h[i] != 0L) { - movk(dst, (u_int32_t)imm_h[i], (i << 4)); + movk(dst, (uint32_t)imm_h[i], (i << 4)); } } } else if (neg_count == 2) { // one MOVN and one MOVK will do for (i = 0; i < 4; i++) { if (imm_h[i] != 0xffffL) { - movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); + movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4)); i++; break; } } for (;i < 4; i++) { if (imm_h[i] != 0xffffL) { - movk(dst, (u_int32_t)imm_h[i], (i << 4)); + movk(dst, (uint32_t)imm_h[i], (i << 4)); } } } else if (zero_count == 1) { // one MOVZ and two MOVKs will do for (i = 0; i < 4; i++) { if (imm_h[i] != 0L) { - movz(dst, (u_int32_t)imm_h[i], (i << 4)); + movz(dst, (uint32_t)imm_h[i], (i << 4)); i++; break; } } for (;i < 4; i++) { if (imm_h[i] != 0x0L) { - movk(dst, (u_int32_t)imm_h[i], (i << 4)); + movk(dst, (uint32_t)imm_h[i], (i << 4)); } } } else if (neg_count == 1) { // one MOVN and two MOVKs will do for (i = 0; i < 4; i++) { if (imm_h[i] != 0xffffL) { - movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); + movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4)); i++; break; } } for (;i < 4; i++) { if (imm_h[i] != 0xffffL) { - movk(dst, (u_int32_t)imm_h[i], (i << 4)); + movk(dst, (uint32_t)imm_h[i], (i << 4)); } } } else { // use a MOVZ and 3 MOVKs (makes it easier to debug) - movz(dst, (u_int32_t)imm_h[0], 0); + movz(dst, (uint32_t)imm_h[0], 0); for (i = 1; i < 4; i++) { - movk(dst, (u_int32_t)imm_h[i], (i << 4)); + movk(dst, (uint32_t)imm_h[i], (i << 4)); } } } } -void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32) +void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32) { #ifndef PRODUCT { @@ -1680,7 +1677,7 @@ } else { // we can use MOVZ, MOVN or two calls to MOVK to build up the // constant - u_int32_t imm_h[2]; + uint32_t imm_h[2]; imm_h[0] = imm32 & 0xffff; imm_h[1] = ((imm32 >> 16) & 0xffff); if (imm_h[0] == 0) { @@ -1703,7 +1700,7 @@ // not actually be used: you must use the Address that is returned. // It is up to you to ensure that the shift provided matches the size // of your data. -Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) { +Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) { if (Address::offset_ok_for_immed(byte_offset, shift)) // It fits; no need for any heroics return Address(base, byte_offset); @@ -1718,9 +1715,9 @@ // See if we can do this with two 12-bit offsets { - unsigned long word_offset = byte_offset >> shift; - unsigned long masked_offset = word_offset & 0xfff000; - if (Address::offset_ok_for_immed(word_offset - masked_offset) + uint64_t word_offset = byte_offset >> shift; + uint64_t masked_offset = word_offset & 0xfff000; + if (Address::offset_ok_for_immed(word_offset - masked_offset, 0) && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) { add(Rd, base, masked_offset << shift); word_offset -= masked_offset; @@ -1960,7 +1957,7 @@ if (value < (1 << 12)) { sub(reg, reg, value); return; } /* else */ { assert(reg != rscratch2, "invalid dst for register decrement"); - mov(rscratch2, (unsigned long)value); + mov(rscratch2, (uint64_t)value); sub(reg, reg, rscratch2); } } @@ -2152,12 +2149,11 @@ void MacroAssembler::stop(const char* msg) { address ip = pc(); pusha(); - mov(c_rarg0, (address)msg); - mov(c_rarg1, (address)ip); + movptr(c_rarg0, (uintptr_t)(address)msg); + movptr(c_rarg1, (uintptr_t)(address)ip); mov(c_rarg2, sp); mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64)); - // call(c_rarg3); - blrt(c_rarg3, 3, 0, 1); + blr(c_rarg3); hlt(0); } @@ -2165,7 +2161,7 @@ pusha(); mov(c_rarg0, (address)msg); mov(lr, CAST_FROM_FN_PTR(address, warning)); - blrt(lr, 1, 0, MacroAssembler::ret_type_void); + blr(lr); popa(); } @@ -2474,6 +2470,8 @@ ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword) ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word) +ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword) +ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word) ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword) ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word) @@ -2546,50 +2544,6 @@ } } -#ifdef BUILTIN_SIM -// routine to generate an x86 prolog for a stub function which -// bootstraps into the generated ARM code which directly follows the -// stub -// -// the argument encodes the number of general and fp registers -// passed by the caller and the callng convention (currently just -// the number of general registers and assumes C argument passing) - -extern "C" { -int aarch64_stub_prolog_size(); -void aarch64_stub_prolog(); -void aarch64_prolog(); -} - -void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, - address *prolog_ptr) -{ - int calltype = (((ret_type & 0x3) << 8) | - ((fp_arg_count & 0xf) << 4) | - (gp_arg_count & 0xf)); - - // the addresses for the x86 to ARM entry code we need to use - address start = pc(); - // printf("start = %lx\n", start); - int byteCount = aarch64_stub_prolog_size(); - // printf("byteCount = %x\n", byteCount); - int instructionCount = (byteCount + 3)/ 4; - // printf("instructionCount = %x\n", instructionCount); - for (int i = 0; i < instructionCount; i++) { - nop(); - } - - memcpy(start, (void*)aarch64_stub_prolog, byteCount); - - // write the address of the setup routine and the call format at the - // end of into the copied code - u_int64_t *patch_end = (u_int64_t *)(start + byteCount); - if (prolog_ptr) - patch_end[-2] = (u_int64_t)prolog_ptr; - patch_end[-1] = calltype; -} -#endif - void MacroAssembler::push_call_clobbered_registers() { int step = 4 * wordSize; push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); @@ -2668,7 +2622,7 @@ if ((offset & (size-1)) && offset >= (1<<8)) { add(tmp, base, offset & ((1<<12)-1)); base = tmp; - offset &= -1<<12; + offset &= -1u<<12; } if (offset >= (1<<12) * size) { @@ -2684,19 +2638,19 @@ // Returns true if it is, else false. bool MacroAssembler::merge_alignment_check(Register base, size_t size, - long cur_offset, - long prev_offset) const { + int64_t cur_offset, + int64_t prev_offset) const { if (AvoidUnalignedAccesses) { if (base == sp) { // Checks whether low offset if aligned to pair of registers. - long pair_mask = size * 2 - 1; - long offset = prev_offset > cur_offset ? cur_offset : prev_offset; + int64_t pair_mask = size * 2 - 1; + int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset; return (offset & pair_mask) == 0; } else { // If base is not sp, we can't guarantee the access is aligned. return false; } } else { - long mask = size - 1; + int64_t mask = size - 1; // Load/store pair instruction only supports element size aligned offset. return (cur_offset & mask) == 0 && (prev_offset & mask) == 0; } @@ -2729,8 +2683,8 @@ return false; } - long max_offset = 63 * prev_size_in_bytes; - long min_offset = -64 * prev_size_in_bytes; + int64_t max_offset = 63 * prev_size_in_bytes; + int64_t min_offset = -64 * prev_size_in_bytes; assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged."); @@ -2739,8 +2693,8 @@ return false; } - long cur_offset = adr.offset(); - long prev_offset = prev_ldst->offset(); + int64_t cur_offset = adr.offset(); + int64_t prev_offset = prev_ldst->offset(); size_t diff = abs(cur_offset - prev_offset); if (diff != prev_size_in_bytes) { return false; @@ -2757,7 +2711,7 @@ return false; } - long low_offset = prev_offset > cur_offset ? cur_offset : prev_offset; + int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset; // Offset range must be in ldp/stp instruction's range. if (low_offset > max_offset || low_offset < min_offset) { return false; @@ -2782,7 +2736,7 @@ address prev = pc() - NativeInstruction::instruction_size; NativeLdSt* prev_ldst = NativeLdSt_at(prev); - long offset; + int64_t offset; if (adr.offset() < prev_ldst->offset()) { offset = adr.offset(); @@ -3328,7 +3282,7 @@ Register table0, Register table1, Register table2, Register table3, Register tmp, Register tmp2, Register tmp3) { Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit; - unsigned long offset; + uint64_t offset; if (UseCRC32) { kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3); @@ -3630,7 +3584,7 @@ SkipIfEqual::SkipIfEqual( MacroAssembler* masm, const bool* flag_addr, bool value) { _masm = masm; - unsigned long offset; + uint64_t offset; _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset); _masm->ldrb(rscratch1, Address(rscratch1, offset)); _masm->cbzw(rscratch1, _label); @@ -3659,7 +3613,7 @@ } void MacroAssembler::cmpptr(Register src1, Address src2) { - unsigned long offset; + uint64_t offset; adrp(rscratch1, src2, offset); ldr(rscratch1, Address(rscratch1, offset)); cmp(src1, rscratch1); @@ -4267,13 +4221,12 @@ return inst_mark(); } -void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) { - relocInfo::relocType rtype = dest.rspec().reloc()->type(); - unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12; - unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12; - unsigned long dest_page = (unsigned long)dest.target() >> 12; - long offset_low = dest_page - low_page; - long offset_high = dest_page - high_page; +void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) { + uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12; + uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12; + uint64_t dest_page = (uint64_t)dest.target() >> 12; + int64_t offset_low = dest_page - low_page; + int64_t offset_high = dest_page - high_page; assert(is_valid_AArch64_address(dest.target()), "bad address"); assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address"); @@ -4285,32 +4238,23 @@ if (offset_high >= -(1<<20) && offset_low < (1<<20)) { _adrp(reg1, dest.target()); } else { - unsigned long target = (unsigned long)dest.target(); - unsigned long adrp_target - = (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL); + uint64_t target = (uint64_t)dest.target(); + uint64_t adrp_target + = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL); _adrp(reg1, (address)adrp_target); movk(reg1, target >> 32, 32); } - byte_offset = (unsigned long)dest.target() & 0xfff; + byte_offset = (uint64_t)dest.target() & 0xfff; } void MacroAssembler::load_byte_map_base(Register reg) { jbyte *byte_map_base = ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base(); - if (is_valid_AArch64_address((address)byte_map_base)) { - // Strictly speaking the byte_map_base isn't an address at all, - // and it might even be negative. - unsigned long offset; - adrp(reg, ExternalAddress((address)byte_map_base), offset); - // We expect offset to be zero with most collectors. - if (offset != 0) { - add(reg, reg, offset); - } - } else { - mov(reg, (uint64_t)byte_map_base); - } + // Strictly speaking the byte_map_base isn't an address at all, and it might + // even be negative. It is thus materialised as a constant. + mov(reg, (uint64_t)byte_map_base); } void MacroAssembler::build_frame(int framesize) { @@ -4347,6 +4291,7 @@ } } +#ifdef COMPILER2 typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr); // Search for str1 in str2 and return index or -1 @@ -4793,6 +4738,8 @@ Register ch1 = rscratch1; Register result_tmp = rscratch2; + cbz(cnt1, NOMATCH); + cmp(cnt1, 4); br(LT, DO1_SHORT); @@ -4907,8 +4854,6 @@ sub(cnt2, zr, cnt2, LSL, str2_chr_shift); } else if (isLU) { ldrs(vtmp, Address(str1)); - cmp(str1, str2); - br(Assembler::EQ, DONE); ldr(tmp2, Address(str2)); cmp(cnt2, STUB_THRESHOLD); br(GE, STUB); @@ -4923,8 +4868,6 @@ fmovd(tmp1, vtmp); } else { // UL case ldr(tmp1, Address(str1)); - cmp(str1, str2); - br(Assembler::EQ, DONE); ldrs(vtmp, Address(str2)); cmp(cnt2, STUB_THRESHOLD); br(GE, STUB); @@ -5074,9 +5017,10 @@ BLOCK_COMMENT("} string_compare"); } +#endif // COMPILER2 // This method checks if provided byte array contains byte with highest bit set. -void MacroAssembler::has_negatives(Register ary1, Register len, Register result) { +address MacroAssembler::has_negatives(Register ary1, Register len, Register result) { // Simple and most common case of aligned small array which is not at the // end of memory page is placed here. All other cases are in stub. Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE; @@ -5113,27 +5057,38 @@ b(SET_RESULT); BIND(STUB); - RuntimeAddress has_neg = RuntimeAddress(StubRoutines::aarch64::has_negatives()); + RuntimeAddress has_neg = RuntimeAddress(StubRoutines::aarch64::has_negatives()); assert(has_neg.target() != NULL, "has_negatives stub has not been generated"); - trampoline_call(has_neg); + address tpc1 = trampoline_call(has_neg); + if (tpc1 == NULL) { + DEBUG_ONLY(reset_labels3(STUB_LONG, SET_RESULT, DONE)); + postcond(pc() == badAddress); + return NULL; + } b(DONE); BIND(STUB_LONG); - RuntimeAddress has_neg_long = RuntimeAddress( - StubRoutines::aarch64::has_negatives_long()); + RuntimeAddress has_neg_long = RuntimeAddress(StubRoutines::aarch64::has_negatives_long()); assert(has_neg_long.target() != NULL, "has_negatives stub has not been generated"); - trampoline_call(has_neg_long); + address tpc2 = trampoline_call(has_neg_long); + if (tpc2 == NULL) { + DEBUG_ONLY(reset_labels2(SET_RESULT, DONE)); + postcond(pc() == badAddress); + return NULL; + } b(DONE); BIND(SET_RESULT); cset(result, NE); // set true or false BIND(DONE); + postcond(pc() != badAddress); + return pc(); } -void MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3, - Register tmp4, Register tmp5, Register result, - Register cnt1, int elem_size) { +address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3, + Register tmp4, Register tmp5, Register result, + Register cnt1, int elem_size) { Label DONE, SAME; Register tmp1 = rscratch1; Register tmp2 = rscratch2; @@ -5237,7 +5192,7 @@ } } } else { - Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB, EARLY_OUT, + Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB, CSET_EQ, LAST_CHECK; mov(result, false); cbz(a1, DONE); @@ -5296,10 +5251,14 @@ cbnz(tmp5, DONE); RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals()); assert(stub.target() != NULL, "array_equals_long stub has not been generated"); - trampoline_call(stub); + address tpc = trampoline_call(stub); + if (tpc == NULL) { + DEBUG_ONLY(reset_labels5(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE)); + postcond(pc() == badAddress); + return NULL; + } b(DONE); - bind(EARLY_OUT); // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2) // so, if a2 == null => return false(0), else return true, so we can return a2 mov(result, a2); @@ -5326,6 +5285,8 @@ bind(DONE); BLOCK_COMMENT("} array_equals"); + postcond(pc() != badAddress); + return pc(); } // Compare Strings @@ -5433,7 +5394,7 @@ // cnt: Count in HeapWords. // // ptr, cnt, rscratch1, and rscratch2 are clobbered. -void MacroAssembler::zero_words(Register ptr, Register cnt) +address MacroAssembler::zero_words(Register ptr, Register cnt) { assert(is_power_of_2(zero_words_block_size), "adjust this"); assert(ptr == r10 && cnt == r11, "mismatch in register usage"); @@ -5443,10 +5404,15 @@ Label around, done, done16; br(LO, around); { - RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks()); + RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks()); assert(zero_blocks.target() != NULL, "zero_blocks stub has not been generated"); if (StubRoutines::aarch64::complete()) { - trampoline_call(zero_blocks); + address tpc = trampoline_call(zero_blocks); + if (tpc == NULL) { + DEBUG_ONLY(reset_labels1(around)); + postcond(pc() == badAddress); + return NULL; + } } else { bl(zero_blocks); } @@ -5467,26 +5433,29 @@ bind(l); } BLOCK_COMMENT("} zero_words"); + postcond(pc() != badAddress); + return pc(); } // base: Address of a buffer to be zeroed, 8 bytes aligned. // cnt: Immediate count in HeapWords. #define SmallArraySize (18 * BytesPerLong) -void MacroAssembler::zero_words(Register base, u_int64_t cnt) +void MacroAssembler::zero_words(Register base, uint64_t cnt) { BLOCK_COMMENT("zero_words {"); int i = cnt & 1; // store any odd word to start if (i) str(zr, Address(base)); if (cnt <= SmallArraySize / BytesPerLong) { - for (; i < (int)cnt; i += 2) + for (; i < (int)cnt; i += 2) { stp(zr, zr, Address(base, i * wordSize)); + } } else { const int unroll = 4; // Number of stp(zr, zr) instructions we'll unroll int remainder = cnt % (2 * unroll); - for (; i < remainder; i += 2) + for (; i < remainder; i += 2) { stp(zr, zr, Address(base, i * wordSize)); - + } Label loop; Register cnt_reg = rscratch1; Register loop_base = rscratch2; @@ -5496,8 +5465,9 @@ add(loop_base, base, (remainder - 2) * wordSize); bind(loop); sub(cnt_reg, cnt_reg, 2 * unroll); - for (i = 1; i < unroll; i++) + for (i = 1; i < unroll; i++) { stp(zr, zr, Address(loop_base, 2 * i * wordSize)); + } stp(zr, zr, Address(pre(loop_base, 2 * unroll * wordSize))); cbnz(cnt_reg, loop); } @@ -5619,7 +5589,6 @@ mov(result, len); // Save initial len -#ifndef BUILTIN_SIM cmp(len, 8); // handle shortest strings first br(LT, LOOP_1); cmp(len, 32); @@ -5695,7 +5664,7 @@ br(GE, NEXT_8); BIND(LOOP_1); -#endif + cbz(len, DONE); BIND(NEXT_1); ldrh(tmp1, Address(post(src, 2))); @@ -5714,9 +5683,9 @@ // Inflate byte[] array to char[]. -void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, - FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3, - Register tmp4) { +address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, + FloatRegister vtmp1, FloatRegister vtmp2, + FloatRegister vtmp3, Register tmp4) { Label big, done, after_init, to_stub; assert_different_registers(src, dst, len, tmp4, rscratch1); @@ -5753,9 +5722,14 @@ if (SoftwarePrefetchHintDistance >= 0) { bind(to_stub); - RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate()); + RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate()); assert(stub.target() != NULL, "large_byte_array_inflate stub has not been generated"); - trampoline_call(stub); + address tpc = trampoline_call(stub); + if (tpc == NULL) { + DEBUG_ONLY(reset_labels2(big, done)); + postcond(pc() == badAddress); + return NULL; + } b(after_init); } @@ -5809,6 +5783,8 @@ strq(vtmp3, Address(dst, -16)); bind(done); + postcond(pc() != badAddress); + return pc(); } // Compress char[] array to byte[]. @@ -5827,14 +5803,18 @@ // by the call to JavaThread::aarch64_get_thread_helper() or, indeed, // the call setup code. // -// aarch64_get_thread_helper() clobbers only r0, r1, and flags. +// On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags. +// On other systems, the helper is a usual C function. // void MacroAssembler::get_thread(Register dst) { - RegSet saved_regs = RegSet::range(r0, r1) + lr - dst; + RegSet saved_regs = + LINUX_ONLY(RegSet::range(r0, r1) + lr - dst) + NOT_LINUX (RegSet::range(r0, r17) + lr - dst); + push(saved_regs, sp); mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)); - blrt(lr, 1, 0, 1); + blr(lr); if (dst != c_rarg0) { mov(dst, c_rarg0); }
diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp index 918cda7..9a18e79 100644 --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp
@@ -26,7 +26,7 @@ #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP -#include "asm/assembler.hpp" +#include "asm/assembler.inline.hpp" // MacroAssembler extends Assembler by frequently used macros. // @@ -132,6 +132,20 @@ a.lea(this, r); } + /* Sometimes we get misaligned loads and stores, usually from Unsafe + accesses, and these can exceed the offset range. */ + Address legitimize_address(const Address &a, int size, Register scratch) { + if (a.getMode() == Address::base_plus_offset) { + if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) { + block_comment("legitimize_address {"); + lea(scratch, a); + block_comment("} legitimize_address"); + return Address(scratch); + } + } + return a; + } + void addmw(Address a, Register incr, Register scratch) { ldrw(scratch, a); addw(scratch, scratch, incr); @@ -169,13 +183,10 @@ virtual void _call_Unimplemented(address call_site) { mov(rscratch2, call_site); - haltsim(); } #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__) - virtual void notify(int type); - // aliases defined in AARCH64 spec template<class T> @@ -437,8 +448,8 @@ // first two private routines for loading 32 bit or 64 bit constants private: - void mov_immediate64(Register dst, u_int64_t imm64); - void mov_immediate32(Register dst, u_int32_t imm32); + void mov_immediate64(Register dst, uint64_t imm64); + void mov_immediate32(Register dst, uint32_t imm32); int push(unsigned int bitset, Register stack); int pop(unsigned int bitset, Register stack); @@ -461,27 +472,27 @@ inline void mov(Register dst, address addr) { - mov_immediate64(dst, (u_int64_t)addr); + mov_immediate64(dst, (uint64_t)addr); } - inline void mov(Register dst, u_int64_t imm64) + inline void mov(Register dst, uint64_t imm64) { mov_immediate64(dst, imm64); } - inline void movw(Register dst, u_int32_t imm32) + inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); } - inline void mov(Register dst, long l) + inline void mov(Register dst, int64_t l) { - mov(dst, (u_int64_t)l); + mov(dst, (uint64_t)l); } inline void mov(Register dst, int i) { - mov(dst, (long)i); + mov(dst, (int64_t)i); } void mov(Register dst, RegisterOrConstant src) { @@ -493,7 +504,7 @@ void movptr(Register r, uintptr_t imm64); - void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32); + void mov(FloatRegister Vd, SIMD_Arrangement T, uint32_t imm32); void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { orr(Vd, T, Vn, Vn); @@ -605,6 +616,7 @@ static int patch_narrow_klass(address insn_addr, narrowKlass n); address emit_trampoline_stub(int insts_call_instruction_offset, address target); + void emit_static_call_stub(); // The following 4 methods return the offset of the appropriate move instruction @@ -997,6 +1009,8 @@ void atomic_xchg(Register prev, Register newv, Register addr); void atomic_xchgw(Register prev, Register newv, Register addr); + void atomic_xchgl(Register prev, Register newv, Register addr); + void atomic_xchglw(Register prev, Register newv, Register addr); void atomic_xchgal(Register prev, Register newv, Register addr); void atomic_xchgalw(Register prev, Register newv, Register addr); @@ -1018,6 +1032,16 @@ private: void compare_eq(Register rn, Register rm, enum operand_size size); +#ifdef ASSERT + // Macro short-hand support to clean-up after a failed call to trampoline + // call generation (see trampoline_call() below), when a set of Labels must + // be reset (before returning). +#define reset_labels1(L1) L1.reset() +#define reset_labels2(L1, L2) L1.reset(); L2.reset() +#define reset_labels3(L1, L2, L3) L1.reset(); reset_labels2(L2, L3) +#define reset_labels5(L1, L2, L3, L4, L5) reset_labels2(L1, L2); reset_labels3(L3, L4, L5) +#endif + public: // Calls @@ -1136,7 +1160,7 @@ void sub(Register Rd, Register Rn, RegisterOrConstant decrement); void subw(Register Rd, Register Rn, RegisterOrConstant decrement); - void adrp(Register reg1, const Address &dest, unsigned long &byte_offset); + void adrp(Register reg1, const Address &dest, uint64_t &byte_offset); void tableswitch(Register index, jint lowbound, jint highbound, Label &jumptable, Label &jumptable_end, int stride = 1) { @@ -1153,7 +1177,7 @@ // actually be used: you must use the Address that is returned. It // is up to you to ensure that the shift provided matches the size // of your data. - Address form_address(Register Rd, Register base, long byte_offset, int shift); + Address form_address(Register Rd, Register base, int64_t byte_offset, int shift); // Return true iff an address is within the 48-bit AArch64 address // space. @@ -1173,34 +1197,12 @@ // public: - // enum used for aarch64--x86 linkage to define return type of x86 function - enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double}; - -#ifdef BUILTIN_SIM - void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL); -#else - void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { } -#endif - - // special version of call_VM_leaf_base needed for aarch64 simulator - // where we need to specify both the gp and fp arg counts and the - // return type so that the linkage routine from aarch64 to x86 and - // back knows which aarch64 registers to copy to x86 registers and - // which x86 result register to copy back to an aarch64 register - - void call_VM_leaf_base1( - address entry_point, // the entry point - int number_of_gp_arguments, // the number of gp reg arguments to pass - int number_of_fp_arguments, // the number of fp reg arguments to pass - ret_type type, // the return type for the call - Label* retaddr = NULL - ); void ldr_constant(Register dest, const Address &const_addr) { if (NearCpool) { ldr(dest, const_addr); } else { - unsigned long offset; + uint64_t offset; adrp(dest, InternalAddress(const_addr.target()), offset); ldr(dest, Address(dest, offset)); } @@ -1221,24 +1223,24 @@ Register tmp1, Register tmp2, FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3, int ae); - void has_negatives(Register ary1, Register len, Register result); + address has_negatives(Register ary1, Register len, Register result); - void arrays_equals(Register a1, Register a2, Register result, Register cnt1, - Register tmp1, Register tmp2, Register tmp3, int elem_size); + address arrays_equals(Register a1, Register a2, Register result, Register cnt1, + Register tmp1, Register tmp2, Register tmp3, int elem_size); void string_equals(Register a1, Register a2, Register result, Register cnt1, int elem_size); void fill_words(Register base, Register cnt, Register value); - void zero_words(Register base, u_int64_t cnt); - void zero_words(Register ptr, Register cnt); + void zero_words(Register base, uint64_t cnt); + address zero_words(Register ptr, Register cnt); void zero_dcache_blocks(Register base, Register cnt); static const int zero_words_block_size; - void byte_array_inflate(Register src, Register dst, Register len, - FloatRegister vtmp1, FloatRegister vtmp2, - FloatRegister vtmp3, Register tmp4); + address byte_array_inflate(Register src, Register dst, Register len, + FloatRegister vtmp1, FloatRegister vtmp2, + FloatRegister vtmp3, Register tmp4); void char_array_compress(Register src, Register dst, Register len, FloatRegister tmp1Reg, FloatRegister tmp2Reg, @@ -1312,7 +1314,7 @@ // Uses rscratch2 if the address is not directly reachable Address spill_address(int size, int offset, Register tmp=rscratch2); - bool merge_alignment_check(Register base, size_t size, long cur_offset, long prev_offset) const; + bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const; // Check whether two loads/stores can be merged into ldp/stp. bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64_log.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64_log.cpp index d4f2431..46b9567 100644 --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64_log.cpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64_log.cpp
@@ -65,7 +65,7 @@ // Table with p(r) polynomial coefficients // and table representation of logarithm values (hi and low parts) -__attribute__ ((aligned(64))) juint _L_tbl[] = +ATTRIBUTE_ALIGNED(64) juint _L_tbl[] = { // coefficients of p(r) polynomial: // _coeff[] @@ -260,9 +260,9 @@ Register tmp4, Register tmp5) { Label DONE, CHECK_CORNER_CASES, SMALL_VALUE, MAIN, CHECKED_CORNER_CASES, RETURN_MINF_OR_NAN; - const long INF_OR_NAN_PREFIX = 0x7FF0; - const long MINF_OR_MNAN_PREFIX = 0xFFF0; - const long ONE_PREFIX = 0x3FF0; + const int64_t INF_OR_NAN_PREFIX = 0x7FF0; + const int64_t MINF_OR_MNAN_PREFIX = 0xFFF0; + const int64_t ONE_PREFIX = 0x3FF0; movz(tmp2, ONE_PREFIX, 48); movz(tmp4, 0x0010, 48); fmovd(rscratch1, v0); // rscratch1 = AS_LONG_BITS(X) @@ -286,7 +286,7 @@ frecpe(vtmp5, vtmp5, S); // vtmp5 ~= 1/vtmp5 lsr(tmp2, rscratch1, 48); movz(tmp4, 0x77f0, 48); - fmovd(vtmp4, 1.0d); + fmovd(vtmp4, 1.0); movz(tmp1, INF_OR_NAN_PREFIX, 48); bfm(tmp4, rscratch1, 0, 51); // tmp4 = 0x77F0 << 48 | mantissa(X) // vtmp1 = AS_DOUBLE_BITS(0x77F0 << 48 | mantissa(X)) == mx @@ -358,7 +358,7 @@ br(GE, DONE); cmp(rscratch1, tmp2); br(NE, CHECKED_CORNER_CASES); - fmovd(v0, 0.0d); + fmovd(v0, 0.0); } bind(DONE); ret(lr);
diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp index dfff03c..d84915e 100644 --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp
@@ -201,9 +201,9 @@ // NOTE: fpu registers are actively reused. See comments in code about their usage void MacroAssembler::generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2) { - const long PIO2_1t = 0x3DD0B4611A626331UL; - const long PIO2_2 = 0x3DD0B4611A600000UL; - const long PIO2_2t = 0x3BA3198A2E037073UL; + const int64_t PIO2_1t = 0x3DD0B4611A626331ULL; + const int64_t PIO2_2 = 0x3DD0B4611A600000ULL; + const int64_t PIO2_2t = 0x3BA3198A2E037073ULL; Label X_IS_NEGATIVE, X_IS_MEDIUM_OR_LARGE, X_IS_POSITIVE_LONG_PI, LARGE_ELSE, REDUCTION_DONE, X_IS_MEDIUM_BRANCH_DONE, X_IS_LARGE, NX_SET, X_IS_NEGATIVE_LONG_PI; @@ -360,7 +360,7 @@ lsr(rscratch1, ix, 20); // ix >> 20 movz(tmp5, 0x4170, 48); subw(rscratch1, rscratch1, 1046); // e0 - fmovd(v10, tmp5); // init two24A value + fmovd(v24, tmp5); // init two24A value subw(jv, ix, rscratch1, LSL, 20); // ix - (e0<<20) lsl(jv, jv, 32); subw(rscratch2, rscratch1, 3); @@ -374,18 +374,18 @@ sdivw(jv, rscratch2, i); // jv = (e0 - 3)/24 fsubd(v26, v26, v6); sub(sp, sp, 560); - fmuld(v26, v26, v10); + fmuld(v26, v26, v24); frintzd(v7, v26); // v7 = (double)((int)v26) movw(jx, 2); // calculate jx as nx - 1, which is initially 2. Not a part of unrolled loop fsubd(v26, v26, v7); } block_comment("nx calculation with unrolled while(tx[nx-1]==zeroA) nx--;"); { - fcmpd(v26, 0.0d); // if NE then jx == 2. else it's 1 or 0 + fcmpd(v26, 0.0); // if NE then jx == 2. else it's 1 or 0 add(iqBase, sp, 480); // base of iq[] - fmuld(v3, v26, v10); + fmuld(v3, v26, v24); br(NE, NX_SET); - fcmpd(v7, 0.0d); // v7 == 0 => jx = 0. Else jx = 1 + fcmpd(v7, 0.0); // v7 == 0 => jx = 0. Else jx = 1 csetw(jx, NE); } bind(NX_SET); @@ -696,7 +696,7 @@ cmpw(jv, zr); addw(tmp4, jx, 4); // tmp4 = m = jx + jk = jx + 4. jx is in {0,1,2} so m is in [4,5,6] cselw(jv, jv, zr, GE); - fmovd(v26, 0.0d); + fmovd(v26, 0.0); addw(tmp5, jv, 1); // jv+1 subsw(j, jv, jx); add(qBase, sp, 320); // base of q[] @@ -819,8 +819,8 @@ movw(jz, 4); fmovd(v17, i); // v17 = twon24 fmovd(v30, tmp5); // 2^q0 - fmovd(v21, 0.125d); - fmovd(v20, 8.0d); + fmovd(v21, 0.125); + fmovd(v20, 8.0); fmovd(v22, tmp4); // 2^-q0 block_comment("recompute loop"); { @@ -839,7 +839,7 @@ ldrd(v27, post(tmp2, -8)); fmuld(v29, v17, v18); // twon24*z frintzd(v29, v29); // (double)(int) - fmsubd(v28, v10, v29, v18); // v28 = z-two24A*fw + fmsubd(v28, v24, v29, v18); // v28 = z-two24A*fw fcvtzdw(tmp1, v28); // (int)(z-two24A*fw) strw(tmp1, Address(iqBase, i, Address::lsl(2))); faddd(v18, v27, v29); @@ -877,7 +877,7 @@ lsr(ih, tmp2, 23); // ih = iq[z-1] >> 23 b(Q0_ZERO_CMP_DONE); bind(Q0_ZERO_CMP_LT); - fmovd(v4, 0.5d); + fmovd(v4, 0.5); fcmpd(v18, v4); cselw(ih, zr, ih, LT); // if (z<0.5) ih = 0 } @@ -924,7 +924,7 @@ br(NE, IH_HANDLED); block_comment("if(ih==2) {"); { - fmovd(v25, 1.0d); + fmovd(v25, 1.0); fsubd(v18, v25, v18); // z = one - z; cbzw(rscratch2, IH_HANDLED); fsubd(v18, v18, v30); // z -= scalbnA(one,q0); @@ -932,7 +932,7 @@ } bind(IH_HANDLED); // check if recomputation is needed - fcmpd(v18, 0.0d); + fcmpd(v18, 0.0); br(NE, RECOMP_CHECK_DONE_NOT_ZERO); block_comment("if(z==zeroB) {"); { @@ -994,17 +994,17 @@ } bind(RECOMP_CHECK_DONE); // chop off zero terms - fcmpd(v18, 0.0d); + fcmpd(v18, 0.0); br(EQ, Z_IS_ZERO); block_comment("else block of if(z==0.0) {"); { bind(RECOMP_CHECK_DONE_NOT_ZERO); fmuld(v18, v18, v22); - fcmpd(v18, v10); // v10 is stil two24A + fcmpd(v18, v24); // v24 is stil two24A br(LT, Z_IS_LESS_THAN_TWO24B); fmuld(v1, v18, v17); // twon24*z frintzd(v1, v1); // v1 = (double)(int)(v1) - fmaddd(v2, v10, v1, v18); + fmaddd(v2, v24, v1, v18); fcvtzdw(tmp3, v1); // (int)fw fcvtzdw(tmp2, v2); // double to int strw(tmp2, Address(iqBase, jz, Address::lsl(2))); @@ -1053,7 +1053,7 @@ movw(tmp2, zr); // tmp2 will keep jz - i == 0 at start bind(COMP_FOR); // for(fw=0.0,k=0;k<=jp&&k<=jz-i;k++) fw += PIo2[k]*q[i+k]; - fmovd(v30, 0.0d); + fmovd(v30, 0.0); add(tmp5, qBase, i, LSL, 3); // address of q[i+k] for k==0 movw(tmp3, 4); movw(tmp4, zr); // used as k @@ -1081,7 +1081,7 @@ // remember prec == 2 block_comment("for (i=jz;i>=0;i--) fw += fq[i];"); { - fmovd(v4, 0.0d); + fmovd(v4, 0.0); mov(i, jz); bind(FW_FOR1); ldrd(v1, Address(rscratch2, i, Address::lsl(3))); @@ -1319,7 +1319,7 @@ ld1(C1, C2, C3, C4, T1D, Address(rscratch2)); // load C1..C3\4 block_comment("calculate r = z*(C1+z*(C2+z*(C3+z*(C4+z*(C5+z*C6)))))"); { fmaddd(r, z, C6, C5); - fmovd(half, 0.5d); + fmovd(half, 0.5); fmaddd(r, z, r, C4); fmuld(y, x, y); fmaddd(r, z, r, C3); @@ -1329,7 +1329,7 @@ fmaddd(r, z, r, C1); // r = C1+z(C2+z(C4+z(C5+z*C6))) } // need to multiply r by z to have "final" r value - fmovd(one, 1.0d); + fmovd(one, 1.0); cmp(ix, rscratch1); br(GT, IX_IS_LARGE); block_comment("if(ix < 0x3FD33333) return one - (0.5*z - (z*r - x*y))"); { @@ -1352,7 +1352,7 @@ b(QX_SET); bind(SET_QX_CONST); block_comment("if(ix > 0x3fe90000) qx = 0.28125;"); { - fmovd(qx, 0.28125d); + fmovd(qx, 0.28125); } bind(QX_SET); fnmsub(C6, x, r, y); // z*r - xy @@ -1443,7 +1443,7 @@ block_comment("kernel_sin/kernel_cos: if(ix<0x3e400000) {<fast return>}"); { bind(TINY_X); if (isCos) { - fmovd(v0, 1.0d); + fmovd(v0, 1.0); } ret(lr); }
diff --git a/src/hotspot/cpu/aarch64/nativeInst_aarch64.cpp b/src/hotspot/cpu/aarch64/nativeInst_aarch64.cpp index 4e99dda..05d769b 100644 --- a/src/hotspot/cpu/aarch64/nativeInst_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/nativeInst_aarch64.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, 2018, Red Hat Inc. All rights reserved. + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -230,7 +230,11 @@ //------------------------------------------------------------------- void NativeMovConstReg::verify() { - // make sure code pattern is actually mov reg64, imm64 instructions + if (! (nativeInstruction_at(instruction_address())->is_movz() || + is_adrp_at(instruction_address()) || + is_ldr_literal_at(instruction_address())) ) { + fatal("should be MOVZ or ADRP or LDR (literal)"); + } } @@ -281,8 +285,6 @@ //------------------------------------------------------------------- -address NativeMovRegMem::instruction_address() const { return addr_at(instruction_offset); } - int NativeMovRegMem::offset() const { address pc = instruction_address(); unsigned insn = *(unsigned*)pc; @@ -299,7 +301,7 @@ unsigned insn = *(unsigned*)pc; if (maybe_cpool_ref(pc)) { address addr = MacroAssembler::target_addr_for_insn(pc); - *(long*)addr = x; + *(int64_t*)addr = x; } else { MacroAssembler::pd_patch_instruction(pc, (address)intptr_t(x)); ICache::invalidate_range(instruction_address(), instruction_size);
diff --git a/src/hotspot/cpu/aarch64/nativeInst_aarch64.hpp b/src/hotspot/cpu/aarch64/nativeInst_aarch64.hpp index 5cda3e0..a1166c6 100644 --- a/src/hotspot/cpu/aarch64/nativeInst_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/nativeInst_aarch64.hpp
@@ -379,11 +379,11 @@ public: // helper - int instruction_start() const; + int instruction_start() const { return instruction_offset; } - address instruction_address() const; + address instruction_address() const { return addr_at(instruction_offset); } - address next_instruction_address() const; + int num_bytes_to_end_of_patch() const { return instruction_offset + instruction_size; } int offset() const;
diff --git a/src/hotspot/cpu/aarch64/pauth_aarch64.hpp b/src/hotspot/cpu/aarch64/pauth_aarch64.hpp new file mode 100644 index 0000000..6109964 --- /dev/null +++ b/src/hotspot/cpu/aarch64/pauth_aarch64.hpp
@@ -0,0 +1,35 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef CPU_AARCH64_PAUTH_AARCH64_INLINE_HPP +#define CPU_AARCH64_PAUTH_AARCH64_INLINE_HPP + +#include OS_CPU_HEADER_INLINE(pauth) + +inline bool pauth_ptr_is_raw(address ptr) { + // Confirm none of the high bits are set in the pointer. + return ptr == pauth_strip_pointer(ptr); +} + +#endif // CPU_AARCH64_PAUTH_AARCH64_INLINE_HPP
diff --git a/src/hotspot/cpu/aarch64/register_aarch64.cpp b/src/hotspot/cpu/aarch64/register_aarch64.cpp index 30924e8..36cbe3f 100644 --- a/src/hotspot/cpu/aarch64/register_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/register_aarch64.cpp
@@ -26,10 +26,12 @@ #include "precompiled.hpp" #include "register_aarch64.hpp" -const int ConcreteRegisterImpl::max_gpr = RegisterImpl::number_of_registers << 1; +const int ConcreteRegisterImpl::max_gpr = RegisterImpl::number_of_registers * + RegisterImpl::max_slots_per_register; const int ConcreteRegisterImpl::max_fpr - = ConcreteRegisterImpl::max_gpr + (FloatRegisterImpl::number_of_registers << 1); + = ConcreteRegisterImpl::max_gpr + + FloatRegisterImpl::number_of_registers * FloatRegisterImpl::max_slots_per_register; const char* RegisterImpl::name() const { const char* names[number_of_registers] = {
diff --git a/src/hotspot/cpu/aarch64/register_aarch64.hpp b/src/hotspot/cpu/aarch64/register_aarch64.hpp index 8cda52a..458a797 100644 --- a/src/hotspot/cpu/aarch64/register_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/register_aarch64.hpp
@@ -1,6 +1,6 @@ /* * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, Red Hat Inc. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -44,7 +44,8 @@ enum { number_of_registers = 32, number_of_byte_registers = 32, - number_of_registers_for_jvmci = 34 // Including SP and ZR. + number_of_registers_for_jvmci = 34, // Including SP and ZR. + max_slots_per_register = 2 }; // derived registers, offsets, and addresses @@ -64,7 +65,7 @@ // Return the bit which represents this register. This is intended // to be ORed into a bitmask: for usage see class RegSet below. - unsigned long bit(bool should_set = true) const { return should_set ? 1 << encoding() : 0; } + uint64_t bit(bool should_set = true) const { return should_set ? 1 << encoding() : 0; } }; // The integer registers of the aarch64 architecture @@ -127,7 +128,10 @@ class FloatRegisterImpl: public AbstractRegisterImpl { public: enum { - number_of_registers = 32 + number_of_registers = 32, + max_slots_per_register = 4, + save_slots_per_register = 2, + extra_save_slots_per_register = max_slots_per_register - save_slots_per_register }; // construction @@ -136,7 +140,7 @@ VMReg as_VMReg(); // derived registers, offsets, and addresses - FloatRegister successor() const { return as_FloatRegister(encoding() + 1); } + FloatRegister successor() const { return as_FloatRegister((encoding() + 1) % 32); } // accessors int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } @@ -193,8 +197,8 @@ // There is no requirement that any ordering here matches any ordering c2 gives // it's optoregs. - number_of_registers = (2 * RegisterImpl::number_of_registers + - 4 * FloatRegisterImpl::number_of_registers + + number_of_registers = (RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers + + FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers + 1) // flags };
diff --git a/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp b/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp index 3db6b91..325c15c 100644 --- a/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, 2018, Red Hat Inc. All rights reserved. + * Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -50,10 +50,6 @@ #include "jvmci/jvmciJavaClasses.hpp" #endif -#ifdef BUILTIN_SIM -#include "../../../../../../simulator/simulator.hpp" -#endif - #define __ masm-> const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size; @@ -102,15 +98,15 @@ // Capture info about frame layout enum layout { fpu_state_off = 0, - fpu_state_end = fpu_state_off+FPUStateSizeInWords-1, + fpu_state_end = fpu_state_off + FPUStateSizeInWords - 1, // The frame sender code expects that rfp will be in // the "natural" place and will override any oopMap // setting for it. We must therefore force the layout // so that it agrees with the frame sender code. - r0_off = fpu_state_off+FPUStateSizeInWords, - rfp_off = r0_off + 30 * 2, - return_off = rfp_off + 2, // slot for return address - reg_save_size = return_off + 2}; + r0_off = fpu_state_off + FPUStateSizeInWords, + rfp_off = r0_off + (RegisterImpl::number_of_registers - 2) * RegisterImpl::max_slots_per_register, + return_off = rfp_off + RegisterImpl::max_slots_per_register, // slot for return address + reg_save_size = return_off + RegisterImpl::max_slots_per_register}; }; @@ -118,19 +114,20 @@ #if COMPILER2_OR_JVMCI if (save_vectors) { // Save upper half of vector registers - int vect_words = 32 * 8 / wordSize; + int vect_words = FloatRegisterImpl::number_of_registers * FloatRegisterImpl::extra_save_slots_per_register / + VMRegImpl::slots_per_word; additional_frame_words += vect_words; } #else assert(!save_vectors, "vectors are generated only by C2 and JVMCI"); #endif - int frame_size_in_bytes = align_up(additional_frame_words*wordSize + - reg_save_size*BytesPerInt, 16); + int frame_size_in_bytes = align_up(additional_frame_words * wordSize + + reg_save_size * BytesPerInt, 16); // OopMap frame size is in compiler stack slots (jint's) not bytes or words int frame_size_in_slots = frame_size_in_bytes / BytesPerInt; // The caller will allocate additional_frame_words - int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt; + int additional_frame_slots = additional_frame_words * wordSize / BytesPerInt; // CodeBlob frame size is in words. int frame_size_in_words = frame_size_in_bytes / wordSize; *total_frame_words = frame_size_in_words; @@ -150,10 +147,10 @@ for (int i = 0; i < RegisterImpl::number_of_registers; i++) { Register r = as_Register(i); if (r < rheapbase && r != rscratch1 && r != rscratch2) { - int sp_offset = 2 * (i + 32); // SP offsets are in 4-byte words, - // register slots are 8 bytes - // wide, 32 floating-point - // registers + // SP offsets are in 4-byte words. + // Register slots are 8 bytes wide, 32 floating-point registers. + int sp_offset = RegisterImpl::max_slots_per_register * i + + FloatRegisterImpl::save_slots_per_register * FloatRegisterImpl::number_of_registers; oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset + additional_frame_slots), r->as_VMReg()); } @@ -161,7 +158,8 @@ for (int i = 0; i < FloatRegisterImpl::number_of_registers; i++) { FloatRegister r = as_FloatRegister(i); - int sp_offset = save_vectors ? (4 * i) : (2 * i); + int sp_offset = save_vectors ? (FloatRegisterImpl::max_slots_per_register * i) : + (FloatRegisterImpl::save_slots_per_register * i); oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset), r->as_VMReg()); } @@ -342,7 +340,7 @@ __ mov(c_rarg0, rmethod); __ mov(c_rarg1, lr); __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite))); - __ blrt(rscratch1, 2, 0, 0); + __ blr(rscratch1); __ maybe_isb(); __ pop_CPU_state(); @@ -400,7 +398,7 @@ // 3 8 T_BOOL // - 0 return address // - // However to make thing extra confusing. Because we can fit a long/double in + // However to make thing extra confusing. Because we can fit a Java long/double in // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter // leaves one slot empty and only stores to a single slot. In this case the // slot that is occupied is the T_VOID slot. See I said it was confusing. @@ -433,7 +431,7 @@ __ str(rscratch1, Address(sp, next_off)); #ifdef ASSERT // Overwrite the unused slot with known junk - __ mov(rscratch1, 0xdeadffffdeadaaaaul); + __ mov(rscratch1, (uint64_t)0xdeadffffdeadaaaaull); __ str(rscratch1, Address(sp, st_off)); #endif /* ASSERT */ } else { @@ -450,10 +448,9 @@ // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG // T_DOUBLE and T_LONG use two slots in the interpreter if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { - // long/double in gpr + // jlong/double in gpr #ifdef ASSERT - // Overwrite the unused slot with known junk - __ mov(rscratch1, 0xdeadffffdeadaaabul); + __ mov(rscratch1, (uint64_t)0xdeadffffdeadaaabull); __ str(rscratch1, Address(sp, st_off)); #endif /* ASSERT */ __ str(r, Address(sp, next_off)); @@ -469,7 +466,7 @@ } else { #ifdef ASSERT // Overwrite the unused slot with known junk - __ mov(rscratch1, 0xdeadffffdeadaaacul); + __ mov(rscratch1, (uint64_t)0xdeadffffdeadaaacull); __ str(rscratch1, Address(sp, st_off)); #endif /* ASSERT */ __ strd(r_1->as_FloatRegister(), Address(sp, next_off)); @@ -662,71 +659,6 @@ __ br(rscratch1); } -#ifdef BUILTIN_SIM -static void generate_i2c_adapter_name(char *result, int total_args_passed, const BasicType *sig_bt) -{ - strcpy(result, "i2c("); - int idx = 4; - for (int i = 0; i < total_args_passed; i++) { - switch(sig_bt[i]) { - case T_BOOLEAN: - result[idx++] = 'Z'; - break; - case T_CHAR: - result[idx++] = 'C'; - break; - case T_FLOAT: - result[idx++] = 'F'; - break; - case T_DOUBLE: - assert((i < (total_args_passed - 1)) && (sig_bt[i+1] == T_VOID), - "double must be followed by void"); - i++; - result[idx++] = 'D'; - break; - case T_BYTE: - result[idx++] = 'B'; - break; - case T_SHORT: - result[idx++] = 'S'; - break; - case T_INT: - result[idx++] = 'I'; - break; - case T_LONG: - assert((i < (total_args_passed - 1)) && (sig_bt[i+1] == T_VOID), - "long must be followed by void"); - i++; - result[idx++] = 'L'; - break; - case T_OBJECT: - result[idx++] = 'O'; - break; - case T_ARRAY: - result[idx++] = '['; - break; - case T_ADDRESS: - result[idx++] = 'P'; - break; - case T_NARROWOOP: - result[idx++] = 'N'; - break; - case T_METADATA: - result[idx++] = 'M'; - break; - case T_NARROWKLASS: - result[idx++] = 'K'; - break; - default: - result[idx++] = '?'; - break; - } - } - result[idx++] = ')'; - result[idx] = '\0'; -} -#endif - // --------------------------------------------------------------- AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, int total_args_passed, @@ -735,20 +667,7 @@ const VMRegPair *regs, AdapterFingerPrint* fingerprint) { address i2c_entry = __ pc(); -#ifdef BUILTIN_SIM - char *name = NULL; - AArch64Simulator *sim = NULL; - size_t len = 65536; - if (NotifySimulator) { - name = NEW_C_HEAP_ARRAY(char, len, mtInternal); - } - if (name) { - generate_i2c_adapter_name(name, total_args_passed, sig_bt); - sim = AArch64Simulator::get_current(UseSimulatorCache, DisableBCCheck); - sim->notifyCompile(name, i2c_entry); - } -#endif gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs); address c2i_unverified_entry = __ pc(); @@ -790,15 +709,6 @@ address c2i_entry = __ pc(); -#ifdef BUILTIN_SIM - if (name) { - name[0] = 'c'; - name[2] = 'i'; - sim->notifyCompile(name, c2i_entry); - FREE_C_HEAP_ARRAY(char, name, mtInternal); - } -#endif - gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup); __ flush(); @@ -1151,12 +1061,12 @@ public: MoveOperation(int src_index, VMRegPair src, int dst_index, VMRegPair dst): _src(src) - , _src_index(src_index) , _dst(dst) + , _src_index(src_index) , _dst_index(dst_index) + , _processed(false) , _next(NULL) - , _prev(NULL) - , _processed(false) { Unimplemented(); } + , _prev(NULL) { Unimplemented(); } VMRegPair src() const { Unimplemented(); return _src; } int src_id() const { Unimplemented(); return 0; } @@ -1192,16 +1102,13 @@ }; -static void rt_call(MacroAssembler* masm, address dest, int gpargs, int fpargs, int type) { +static void rt_call(MacroAssembler* masm, address dest) { CodeBlob *cb = CodeCache::find_blob(dest); if (cb) { __ far_call(RuntimeAddress(dest)); } else { - assert((unsigned)gpargs < 256, "eek!"); - assert((unsigned)fpargs < 32, "eek!"); __ lea(rscratch1, RuntimeAddress(dest)); - if (UseBuiltinSim) __ mov(rscratch2, (gpargs << 6) | (fpargs << 2) | type); - __ blrt(rscratch1, rscratch2); + __ blr(rscratch1); __ maybe_isb(); } } @@ -1321,25 +1228,8 @@ int compile_id, BasicType* in_sig_bt, VMRegPair* in_regs, - BasicType ret_type) { -#ifdef BUILTIN_SIM - if (NotifySimulator) { - // Names are up to 65536 chars long. UTF8-coded strings are up to - // 3 bytes per character. We concatenate three such strings. - // Yes, I know this is ridiculous, but it's debug code and glibc - // allocates large arrays very efficiently. - size_t len = (65536 * 3) * 3; - char *name = new char[len]; - - strncpy(name, method()->method_holder()->name()->as_utf8(), len); - strncat(name, ".", len); - strncat(name, method()->name()->as_utf8(), len); - strncat(name, method()->signature()->as_utf8(), len); - AArch64Simulator::get_current(UseSimulatorCache, DisableBCCheck)->notifyCompile(name, __ pc()); - delete[] name; - } -#endif - + BasicType ret_type, + address critical_entry) { if (method->is_method_handle_intrinsic()) { vmIntrinsics::ID iid = method->intrinsic_id(); intptr_t start = (intptr_t)__ pc(); @@ -1365,7 +1255,7 @@ (OopMapSet*)NULL); } bool is_critical_native = true; - address native_func = method->critical_native_function(); + address native_func = critical_entry; if (native_func == NULL) { native_func = method->native_function(); is_critical_native = false; @@ -1596,11 +1486,6 @@ // Frame is now completed as far as size and linkage. int frame_complete = ((intptr_t)__ pc()) - start; - // record entry into native wrapper code - if (NotifySimulator) { - __ notify(Assembler::method_entry); - } - // We use r20 as the oop handle for the receiver/klass // It is callee save so it survives the call to native @@ -1781,18 +1666,15 @@ } // Change state to native (we save the return address in the thread, since it might not - // be pushed on the stack when we do a a stack traversal). It is enough that the pc() - // points into the right code segment. It does not have to be the correct return pc. + // be pushed on the stack when we do a stack traversal). // We use the same pc/oopMap repeatedly when we call out - intptr_t the_pc = (intptr_t) __ pc(); - oop_maps->add_gc_map(the_pc - start, map); - - __ set_last_Java_frame(sp, noreg, (address)the_pc, rscratch1); + Label native_return; + __ set_last_Java_frame(sp, noreg, native_return, rscratch1); Label dtrace_method_entry, dtrace_method_entry_done; { - unsigned long offset; + uint64_t offset; __ adrp(rscratch1, ExternalAddress((address)&DTraceMethodProbes), offset); __ ldrb(rscratch1, Address(rscratch1, offset)); __ cbnzw(rscratch1, dtrace_method_entry); @@ -1891,33 +1773,12 @@ __ lea(rscratch2, Address(rthread, JavaThread::thread_state_offset())); __ stlrw(rscratch1, rscratch2); - { - int return_type = 0; - switch (ret_type) { - case T_VOID: break; - return_type = 0; break; - case T_CHAR: - case T_BYTE: - case T_SHORT: - case T_INT: - case T_BOOLEAN: - case T_LONG: - return_type = 1; break; - case T_ARRAY: - case T_OBJECT: - return_type = 1; break; - case T_FLOAT: - return_type = 2; break; - case T_DOUBLE: - return_type = 3; break; - default: - ShouldNotReachHere(); - } - rt_call(masm, native_func, - int_args + 2, // AArch64 passes up to 8 args in int registers - float_args, // and up to 8 float args - return_type); - } + rt_call(masm, native_func); + + __ bind(native_return); + + intptr_t return_pc = (intptr_t) __ pc(); + oop_maps->add_gc_map(return_pc - start, map); // Unpack native results. switch (ret_type) { @@ -2038,7 +1899,7 @@ Label dtrace_method_exit, dtrace_method_exit_done; { - unsigned long offset; + uint64_t offset; __ adrp(rscratch1, ExternalAddress((address)&DTraceMethodProbes), offset); __ ldrb(rscratch1, Address(rscratch1, offset)); __ cbnzw(rscratch1, dtrace_method_exit); @@ -2071,11 +1932,6 @@ __ cbnz(rscratch1, exception_pending); } - // record exit from native wrapper code - if (NotifySimulator) { - __ notify(Assembler::method_reentry); - } - // We're done __ ret(lr); @@ -2140,7 +1996,7 @@ __ ldr(r19, Address(rthread, in_bytes(Thread::pending_exception_offset()))); __ str(zr, Address(rthread, in_bytes(Thread::pending_exception_offset()))); - rt_call(masm, CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), 3, 0, 1); + rt_call(masm, CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)); #ifdef ASSERT { @@ -2167,7 +2023,7 @@ __ bind(reguard); save_native_result(masm, ret_type, stack_slots); - rt_call(masm, CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages), 0, 0, 0); + rt_call(masm, CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)); restore_native_result(masm, ret_type, stack_slots); // and continue __ b(reguard_done); @@ -2190,7 +2046,7 @@ } else { __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition))); } - __ blrt(rscratch1, 1, 0, 1); + __ blr(rscratch1); __ maybe_isb(); // Restore any method result value restore_native_result(masm, ret_type, stack_slots); @@ -2287,14 +2143,6 @@ OopMap* map = NULL; OopMapSet *oop_maps = new OopMapSet(); -#ifdef BUILTIN_SIM - AArch64Simulator *simulator; - if (NotifySimulator) { - simulator = AArch64Simulator::get_current(UseSimulatorCache, DisableBCCheck); - simulator->notifyCompile(const_cast<char*>("SharedRuntime::deopt_blob"), __ pc()); - } -#endif - // ------------- // This code enters when returning to a de-optimized nmethod. A return // address has been pushed on the the stack, and return values are in @@ -2383,7 +2231,7 @@ __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap))); - __ blrt(rscratch1, 2, 0, MacroAssembler::ret_type_integral); + __ blr(rscratch1); __ bind(retaddr); oop_maps->add_gc_map( __ pc()-start, map->deep_copy()); @@ -2475,7 +2323,7 @@ __ mov(c_rarg0, rthread); __ mov(c_rarg1, rcpool); __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info))); - __ blrt(rscratch1, 1, 0, 1); + __ blr(rscratch1); __ bind(retaddr); // Need to have an oopmap that tells fetch_unroll_info where to @@ -2615,7 +2463,7 @@ __ mov(c_rarg0, rthread); __ movw(c_rarg1, rcpool); // second arg: exec_mode __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); - __ blrt(rscratch1, 2, 0, 0); + __ blr(rscratch1); // Set an oopmap for the call site // Use the same PC we used for the last java frame @@ -2648,12 +2496,6 @@ _deopt_blob->set_implicit_exception_uncommon_trap_offset(implicit_exception_uncommon_trap_offset); } #endif -#ifdef BUILTIN_SIM - if (NotifySimulator) { - unsigned char *base = _deopt_blob->code_begin(); - simulator->notifyRelocate(start, base - start); - } -#endif } uint SharedRuntime::out_preserve_stack_slots() { @@ -2669,14 +2511,6 @@ CodeBuffer buffer("uncommon_trap_blob", 2048, 1024); MacroAssembler* masm = new MacroAssembler(&buffer); -#ifdef BUILTIN_SIM - AArch64Simulator *simulator; - if (NotifySimulator) { - simulator = AArch64Simulator::get_current(UseSimulatorCache, DisableBCCheck); - simulator->notifyCompile(const_cast<char*>("SharedRuntime:uncommon_trap_blob"), __ pc()); - } -#endif - assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned"); address start = __ pc(); @@ -2715,7 +2549,7 @@ __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap))); - __ blrt(rscratch1, 2, 0, MacroAssembler::ret_type_integral); + __ blr(rscratch1); __ bind(retaddr); // Set an oopmap for the call site @@ -2838,7 +2672,7 @@ __ mov(c_rarg0, rthread); __ movw(c_rarg1, (unsigned)Deoptimization::Unpack_uncommon_trap); __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); - __ blrt(rscratch1, 2, 0, MacroAssembler::ret_type_integral); + __ blr(rscratch1); // Set an oopmap for the call site // Use the same PC we used for the last java frame @@ -2858,13 +2692,6 @@ _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1); - -#ifdef BUILTIN_SIM - if (NotifySimulator) { - unsigned char *base = _deopt_blob->code_begin(); - simulator->notifyRelocate(start, base - start); - } -#endif } #endif // COMPILER2_OR_JVMCI @@ -2914,7 +2741,7 @@ // Do the call __ mov(c_rarg0, rthread); __ lea(rscratch1, RuntimeAddress(call_ptr)); - __ blrt(rscratch1, 1, 0, 1); + __ blr(rscratch1); __ bind(retaddr); // Set an oopmap for the call site. This oopmap will map all @@ -3019,7 +2846,7 @@ __ mov(c_rarg0, rthread); __ lea(rscratch1, RuntimeAddress(destination)); - __ blrt(rscratch1, 1, 0, 1); + __ blr(rscratch1); __ bind(retaddr); } @@ -3151,7 +2978,7 @@ __ set_last_Java_frame(sp, noreg, the_pc, rscratch1); __ mov(c_rarg0, rthread); __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C))); - __ blrt(rscratch1, 1, 0, MacroAssembler::ret_type_integral); + __ blr(rscratch1); __ maybe_isb(); // Set an oopmap for the call site. This oopmap will only be used if we
diff --git a/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp index 9824625..f4a68a3 100644 --- a/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. + * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -26,6 +26,7 @@ #include "precompiled.hpp" #include "asm/macroAssembler.hpp" #include "asm/macroAssembler.inline.hpp" +#include "atomic_aarch64.hpp" #include "gc/shared/barrierSet.hpp" #include "gc/shared/barrierSetAssembler.hpp" #include "interpreter/interpreter.hpp" @@ -35,6 +36,7 @@ #include "oops/objArrayKlass.hpp" #include "oops/oop.inline.hpp" #include "prims/methodHandles.hpp" +#include "runtime/atomic.hpp" #include "runtime/frame.inline.hpp" #include "runtime/handles.inline.hpp" #include "runtime/sharedRuntime.hpp" @@ -46,10 +48,6 @@ #include "opto/runtime.hpp" #endif -#ifdef BUILTIN_SIM -#include "../../../../../../simulator/simulator.hpp" -#endif - // Declaration and definition of StubGenerator (no .hpp file). // For a more detailed description of the stub routine structure // see the comment in stubRoutines.hpp @@ -217,16 +215,8 @@ // stub code - // we need a C prolog to bootstrap the x86 caller into the sim - __ c_stub_prolog(8, 0, MacroAssembler::ret_type_void); - address aarch64_entry = __ pc(); -#ifdef BUILTIN_SIM - // Save sender's SP for stack traces. - __ mov(rscratch1, sp); - __ str(rscratch1, Address(__ pre(sp, -2 * wordSize))); -#endif // set up frame and move sp to end of save area __ enter(); __ sub(sp, rfp, -sp_after_call_off * wordSize); @@ -297,8 +287,6 @@ __ mov(r13, sp); __ blr(c_rarg4); - // tell the simulator we have returned to the stub - // we do this here because the notify will already have been done // if we get to the next instruction via an exception // @@ -308,9 +296,6 @@ // pc against the address saved below. so we may need to allow for // this extra instruction in the check. - if (NotifySimulator) { - __ notify(Assembler::method_reentry); - } // save current address for use by exception handling code return_address = __ pc(); @@ -373,12 +358,6 @@ __ ldp(c_rarg4, c_rarg5, entry_point); __ ldp(c_rarg6, c_rarg7, parameter_size); -#ifndef PRODUCT - // tell the simulator we are about to end Java execution - if (NotifySimulator) { - __ notify(Assembler::method_exit); - } -#endif // leave frame and return to caller __ leave(); __ ret(lr); @@ -412,13 +391,6 @@ // // r0: exception oop - // NOTE: this is used as a target from the signal handler so it - // needs an x86 prolog which returns into the current simulator - // executing the generated catch_exception code. so the prolog - // needs to install rax in a sim register and adjust the sim's - // restart pc to enter the generated code at the start position - // then return from native to simulated execution. - address generate_catch_exception() { StubCodeMark mark(this, "StubRoutines", "catch_exception"); address start = __ pc(); @@ -613,7 +585,7 @@ #endif BLOCK_COMMENT("call MacroAssembler::debug"); __ mov(rscratch1, CAST_FROM_FN_PTR(address, MacroAssembler::debug64)); - __ blrt(rscratch1, 3, 0, 1); + __ blr(rscratch1); return start; } @@ -711,7 +683,6 @@ int unit = wordSize * direction; int bias = (UseSIMDForMemoryOps ? 4:2) * wordSize; - int offset; const Register t0 = r3, t1 = r4, t2 = r5, t3 = r6, t4 = r7, t5 = r10, t6 = r11, t7 = r12; const Register stride = r13; @@ -725,8 +696,11 @@ stub_name = "forward_copy_longs"; else stub_name = "backward_copy_longs"; - StubCodeMark mark(this, "StubRoutines", stub_name); + __ align(CodeEntryAlignment); + + StubCodeMark mark(this, "StubRoutines", stub_name); + __ bind(start); Label unaligned_copy_long; @@ -1091,10 +1065,10 @@ Register count, Register tmp, int step) { copy_direction direction = step < 0 ? copy_backwards : copy_forwards; bool is_backwards = step < 0; - int granularity = uabs(step); + unsigned int granularity = uabs(step); const Register t0 = r3, t1 = r4; - // <= 96 bytes do inline. Direction doesn't matter because we always + // <= 80 (or 96 for SIMD) bytes do inline. Direction doesn't matter because we always // load all the data before writing anything Label copy4, copy8, copy16, copy32, copy80, copy128, copy_big, finish; const Register t2 = r5, t3 = r6, t4 = r7, t5 = r8; @@ -1149,9 +1123,32 @@ // (96 bytes if SIMD because we do 32 byes per instruction) __ bind(copy80); if (UseSIMDForMemoryOps) { - __ ld4(v0, v1, v2, v3, __ T16B, Address(s, 0)); + __ ldpq(v0, v1, Address(s, 0)); + __ ldpq(v2, v3, Address(s, 32)); + // Unaligned pointers can be an issue for copying. + // The issue has more chances to happen when granularity of data is + // less than 4(sizeof(jint)). Pointers for arrays of jint are at least + // 4 byte aligned. Pointers for arrays of jlong are 8 byte aligned. + // The most performance drop has been seen for the range 65-80 bytes. + // For such cases using the pair of ldp/stp instead of the third pair of + // ldpq/stpq fixes the performance issue. + if (granularity < sizeof (jint)) { + Label copy96; + __ cmp(count, u1(80/granularity)); + __ br(Assembler::HI, copy96); + __ ldp(t0, t1, Address(send, -16)); + + __ stpq(v0, v1, Address(d, 0)); + __ stpq(v2, v3, Address(d, 32)); + __ stp(t0, t1, Address(dend, -16)); + __ b(finish); + + __ bind(copy96); + } __ ldpq(v4, v5, Address(send, -32)); - __ st4(v0, v1, v2, v3, __ T16B, Address(d, 0)); + + __ stpq(v0, v1, Address(d, 0)); + __ stpq(v2, v3, Address(d, 32)); __ stpq(v4, v5, Address(dend, -32)); } else { __ ldp(t0, t1, Address(s, 0)); @@ -1309,10 +1306,10 @@ __ ldr(temp, Address(a, rscratch2, Address::lsl(exact_log2(size)))); __ verify_oop(temp); } else { - __ ldrw(r16, Address(a, rscratch2, Address::lsl(exact_log2(size)))); + __ ldrw(temp, Address(a, rscratch2, Address::lsl(exact_log2(size)))); __ decode_heap_oop(temp); // calls verify_oop } - __ add(rscratch2, rscratch2, size); + __ add(rscratch2, rscratch2, 1); __ b(loop); __ bind(end); } @@ -1330,7 +1327,7 @@ // // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let // the hardware handle it. The two dwords within qwords that span - // cache line boundaries will still be loaded and stored atomicly. + // cache line boundaries will still be loaded and stored atomically. // // Side Effects: // disjoint_int_copy_entry is set to the no-overlap entry point @@ -1360,7 +1357,7 @@ } BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); - bs->arraycopy_prologue(_masm, decorators, is_oop, d, count, saved_reg); + bs->arraycopy_prologue(_masm, decorators, is_oop, s, d, count, saved_reg); if (is_oop) { // save regs before copy_memory @@ -1372,8 +1369,6 @@ __ pop(RegSet::of(d, count), sp); if (VerifyOops) verify_oop_array(size, d, count, r16); - __ sub(count, count, 1); // make an inclusive end pointer - __ lea(count, Address(d, count, Address::lsl(exact_log2(size)))); } bs->arraycopy_epilogue(_masm, decorators, is_oop, d, count, rscratch1, RegSet()); @@ -1381,12 +1376,6 @@ __ leave(); __ mov(r0, zr); // return 0 __ ret(lr); -#ifdef BUILTIN_SIM - { - AArch64Simulator *sim = AArch64Simulator::get_current(UseSimulatorCache, DisableBCCheck); - sim->notifyCompile(const_cast<char*>(name), start); - } -#endif return start; } @@ -1403,7 +1392,7 @@ // // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let // the hardware handle it. The two dwords within qwords that span - // cache line boundaries will still be loaded and stored atomicly. + // cache line boundaries will still be loaded and stored atomically. // address generate_conjoint_copy(size_t size, bool aligned, bool is_oop, address nooverlap_target, address *entry, const char *name, @@ -1434,7 +1423,7 @@ } BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); - bs->arraycopy_prologue(_masm, decorators, is_oop, d, count, saved_regs); + bs->arraycopy_prologue(_masm, decorators, is_oop, s, d, count, saved_regs); if (is_oop) { // save regs before copy_memory @@ -1445,19 +1434,11 @@ __ pop(RegSet::of(d, count), sp); if (VerifyOops) verify_oop_array(size, d, count, r16); - __ sub(count, count, 1); // make an inclusive end pointer - __ lea(count, Address(d, count, Address::lsl(exact_log2(size)))); } bs->arraycopy_epilogue(_masm, decorators, is_oop, d, count, rscratch1, RegSet()); __ leave(); __ mov(r0, zr); // return 0 __ ret(lr); -#ifdef BUILTIN_SIM - { - AArch64Simulator *sim = AArch64Simulator::get_current(UseSimulatorCache, DisableBCCheck); - sim->notifyCompile(const_cast<char*>(name), start); - } -#endif return start; } @@ -1571,7 +1552,7 @@ // // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let // the hardware handle it. The two dwords within qwords that span - // cache line boundaries will still be loaded and stored atomicly. + // cache line boundaries will still be loaded and stored atomically. // // Side Effects: // disjoint_int_copy_entry is set to the no-overlap entry point @@ -1595,7 +1576,7 @@ // // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let // the hardware handle it. The two dwords within qwords that span - // cache line boundaries will still be loaded and stored atomicly. + // cache line boundaries will still be loaded and stored atomically. // address generate_conjoint_int_copy(bool aligned, address nooverlap_target, address *entry, const char *name, @@ -1789,14 +1770,14 @@ } #endif //ASSERT - DecoratorSet decorators = IN_HEAP | IS_ARRAY | ARRAYCOPY_CHECKCAST; + DecoratorSet decorators = IN_HEAP | IS_ARRAY | ARRAYCOPY_CHECKCAST | ARRAYCOPY_DISJOINT; bool is_oop = true; if (dest_uninitialized) { decorators |= IS_DEST_UNINITIALIZED; } BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); - bs->arraycopy_prologue(_masm, decorators, is_oop, to, count, wb_pre_saved_regs); + bs->arraycopy_prologue(_masm, decorators, is_oop, from, to, count, wb_pre_saved_regs); // save the original count __ mov(count_save, count); @@ -1839,8 +1820,7 @@ __ br(Assembler::EQ, L_done_pop); __ BIND(L_do_card_marks); - __ add(to, to, -heapOopSize); // make an inclusive end pointer - bs->arraycopy_epilogue(_masm, decorators, is_oop, start_to, to, rscratch1, wb_post_saved_regs); + bs->arraycopy_epilogue(_masm, decorators, is_oop, start_to, count_save, rscratch1, wb_post_saved_regs); __ bind(L_done_pop); __ pop(RegSet::of(r18, r19, r20, r21), sp); @@ -1976,13 +1956,13 @@ const Register dst_pos = c_rarg3; // destination position const Register length = c_rarg4; - StubCodeMark mark(this, "StubRoutines", name); + __ align(CodeEntryAlignment); + StubCodeMark mark(this, "StubRoutines", name); // Registers used as temps const Register dst_klass = c_rarg5; - __ align(CodeEntryAlignment); address start = __ pc(); __ enter(); // required for proper stackwalking of RuntimeStub frame @@ -3105,7 +3085,6 @@ return start; } -#ifndef BUILTIN_SIM // Safefetch stubs. void generate_safefetch(const char* name, int size, address* entry, address* fault_pc, address* continuation_pc) { @@ -3145,7 +3124,6 @@ __ mov(r0, c_rarg1); __ ret(lr); } -#endif /** * Arguments: @@ -3253,20 +3231,27 @@ Register buff = c_rarg1; Register len = c_rarg2; Register nmax = r4; - Register base = r5; + Register base = r5; Register count = r6; Register temp0 = rscratch1; Register temp1 = rscratch2; - Register temp2 = r7; + FloatRegister vbytes = v0; + FloatRegister vs1acc = v1; + FloatRegister vs2acc = v2; + FloatRegister vtable = v3; // Max number of bytes we can process before having to take the mod // 0x15B0 is 5552 in decimal, the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 - unsigned long BASE = 0xfff1; - unsigned long NMAX = 0x15B0; + uint64_t BASE = 0xfff1; + uint64_t NMAX = 0x15B0; __ mov(base, BASE); __ mov(nmax, NMAX); + // Load accumulation coefficients for the upper 16 bits + __ lea(temp0, ExternalAddress((address) StubRoutines::aarch64::_adler_table)); + __ ld1(vtable, __ T16B, Address(temp0)); + // s1 is initialized to the lower 16 bits of adler // s2 is initialized to the upper 16 bits of adler __ ubfx(s2, adler, 16, 16); // s2 = ((adler >> 16) & 0xffff) @@ -3307,53 +3292,8 @@ __ bind(L_nmax_loop); - __ ldp(temp0, temp1, Address(__ post(buff, 16))); - - __ add(s1, s1, temp0, ext::uxtb); - __ ubfx(temp2, temp0, 8, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp0, 16, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp0, 24, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp0, 32, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp0, 40, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp0, 48, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ add(s2, s2, s1); - __ add(s1, s1, temp0, Assembler::LSR, 56); - __ add(s2, s2, s1); - - __ add(s1, s1, temp1, ext::uxtb); - __ ubfx(temp2, temp1, 8, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp1, 16, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp1, 24, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp1, 32, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp1, 40, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp1, 48, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ add(s2, s2, s1); - __ add(s1, s1, temp1, Assembler::LSR, 56); - __ add(s2, s2, s1); + generate_updateBytesAdler32_accum(s1, s2, buff, temp0, temp1, + vbytes, vs1acc, vs2acc, vtable); __ subs(count, count, 16); __ br(Assembler::HS, L_nmax_loop); @@ -3396,53 +3336,8 @@ __ bind(L_by16_loop); - __ ldp(temp0, temp1, Address(__ post(buff, 16))); - - __ add(s1, s1, temp0, ext::uxtb); - __ ubfx(temp2, temp0, 8, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp0, 16, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp0, 24, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp0, 32, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp0, 40, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp0, 48, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ add(s2, s2, s1); - __ add(s1, s1, temp0, Assembler::LSR, 56); - __ add(s2, s2, s1); - - __ add(s1, s1, temp1, ext::uxtb); - __ ubfx(temp2, temp1, 8, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp1, 16, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp1, 24, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp1, 32, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp1, 40, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ ubfx(temp2, temp1, 48, 8); - __ add(s2, s2, s1); - __ add(s1, s1, temp2); - __ add(s2, s2, s1); - __ add(s1, s1, temp1, Assembler::LSR, 56); - __ add(s2, s2, s1); + generate_updateBytesAdler32_accum(s1, s2, buff, temp0, temp1, + vbytes, vs1acc, vs2acc, vtable); __ subs(len, len, 16); __ br(Assembler::HS, L_by16_loop); @@ -3496,6 +3391,43 @@ return start; } + void generate_updateBytesAdler32_accum(Register s1, Register s2, Register buff, + Register temp0, Register temp1, FloatRegister vbytes, + FloatRegister vs1acc, FloatRegister vs2acc, FloatRegister vtable) { + // Below is a vectorized implementation of updating s1 and s2 for 16 bytes. + // We use b1, b2, ..., b16 to denote the 16 bytes loaded in each iteration. + // In non-vectorized code, we update s1 and s2 as: + // s1 <- s1 + b1 + // s2 <- s2 + s1 + // s1 <- s1 + b2 + // s2 <- s2 + b1 + // ... + // s1 <- s1 + b16 + // s2 <- s2 + s1 + // Putting above assignments together, we have: + // s1_new = s1 + b1 + b2 + ... + b16 + // s2_new = s2 + (s1 + b1) + (s1 + b1 + b2) + ... + (s1 + b1 + b2 + ... + b16) + // = s2 + s1 * 16 + (b1 * 16 + b2 * 15 + ... + b16 * 1) + // = s2 + s1 * 16 + (b1, b2, ... b16) dot (16, 15, ... 1) + __ ld1(vbytes, __ T16B, Address(__ post(buff, 16))); + + // s2 = s2 + s1 * 16 + __ add(s2, s2, s1, Assembler::LSL, 4); + + // vs1acc = b1 + b2 + b3 + ... + b16 + // vs2acc = (b1 * 16) + (b2 * 15) + (b3 * 14) + ... + (b16 * 1) + __ umullv(vs2acc, __ T8B, vtable, vbytes); + __ umlalv(vs2acc, __ T16B, vtable, vbytes); + __ uaddlv(vs1acc, __ T16B, vbytes); + __ uaddlv(vs2acc, __ T8H, vs2acc); + + // s1 = s1 + vs1acc, s2 = s2 + vs2acc + __ fmovd(temp0, vs1acc); + __ fmovd(temp1, vs2acc); + __ add(s1, s1, temp0); + __ add(s2, s2, temp1); + } + /** * Arguments: * @@ -3657,7 +3589,6 @@ } address generate_has_negatives(address &has_negatives_long) { - StubCodeMark mark(this, "StubRoutines", "has_negatives"); const int large_loop_size = 64; const uint64_t UPPER_BIT_MASK=0x8080808080808080; int dcache_line = VM_Version::dcache_line_size(); @@ -3665,6 +3596,9 @@ Register ary1 = r1, len = r2, result = r0; __ align(CodeEntryAlignment); + + StubCodeMark mark(this, "StubRoutines", "has_negatives"); + address entry = __ pc(); __ enter(); @@ -3904,7 +3838,6 @@ // cnt1 = r10 - amount of elements left to check, reduced by wordSize // r3-r5 are reserved temporary registers address generate_large_array_equals() { - StubCodeMark mark(this, "StubRoutines", "large_array_equals"); Register a1 = r1, a2 = r2, result = r0, cnt1 = r10, tmp1 = rscratch1, tmp2 = rscratch2, tmp3 = r3, tmp4 = r4, tmp5 = r5, tmp6 = r11, tmp7 = r12, tmp8 = r13; @@ -3919,6 +3852,9 @@ tmp5, tmp6, tmp7, tmp8); __ align(CodeEntryAlignment); + + StubCodeMark mark(this, "StubRoutines", "large_array_equals"); + address entry = __ pc(); __ enter(); __ sub(cnt1, cnt1, wordSize); // first 8 bytes were loaded outside of stub @@ -4077,14 +4013,14 @@ : "compare_long_string_different_encoding UL"); address entry = __ pc(); Label SMALL_LOOP, TAIL, TAIL_LOAD_16, LOAD_LAST, DIFF1, DIFF2, - DONE, CALCULATE_DIFFERENCE, LARGE_LOOP_PREFETCH, SMALL_LOOP_ENTER, + DONE, CALCULATE_DIFFERENCE, LARGE_LOOP_PREFETCH, NO_PREFETCH, LARGE_LOOP_PREFETCH_REPEAT1, LARGE_LOOP_PREFETCH_REPEAT2; Register result = r0, str1 = r1, cnt1 = r2, str2 = r3, cnt2 = r4, tmp1 = r10, tmp2 = r11, tmp3 = r12, tmp4 = r14; FloatRegister vtmpZ = v0, vtmp = v1, vtmp3 = v2; RegSet spilled_regs = RegSet::of(tmp3, tmp4); - int prefetchLoopExitCondition = MAX(32, SoftwarePrefetchHintDistance/2); + int prefetchLoopExitCondition = MAX2(64, SoftwarePrefetchHintDistance/2); __ eor(vtmpZ, __ T16B, vtmpZ, vtmpZ); // cnt2 == amount of characters left to compare @@ -4111,7 +4047,7 @@ if (SoftwarePrefetchHintDistance >= 0) { __ cmp(cnt2, prefetchLoopExitCondition); - __ br(__ LT, SMALL_LOOP); + __ br(__ LT, NO_PREFETCH); __ bind(LARGE_LOOP_PREFETCH); __ prfm(Address(tmp2, SoftwarePrefetchHintDistance)); __ mov(tmp4, 2); @@ -4131,51 +4067,20 @@ __ br(__ GE, LARGE_LOOP_PREFETCH); } __ cbz(cnt2, LOAD_LAST); // no characters left except last load + __ bind(NO_PREFETCH); __ subs(cnt2, cnt2, 16); __ br(__ LT, TAIL); - __ b(SMALL_LOOP_ENTER); __ bind(SMALL_LOOP); // smaller loop __ subs(cnt2, cnt2, 16); - __ bind(SMALL_LOOP_ENTER); compare_string_16_x_LU(tmpL, tmpU, DIFF1, DIFF2); __ br(__ GE, SMALL_LOOP); - __ cbz(cnt2, LOAD_LAST); - __ bind(TAIL); // 1..15 characters left - __ cmp(cnt2, -8); - __ br(__ GT, TAIL_LOAD_16); - __ ldrd(vtmp, Address(tmp2)); - __ zip1(vtmp3, __ T8B, vtmp, vtmpZ); - - __ ldr(tmpU, Address(__ post(cnt1, 8))); - __ fmovd(tmpL, vtmp3); - __ eor(rscratch2, tmp3, tmpL); - __ cbnz(rscratch2, DIFF2); - __ umov(tmpL, vtmp3, __ D, 1); - __ eor(rscratch2, tmpU, tmpL); - __ cbnz(rscratch2, DIFF1); - __ b(LOAD_LAST); - __ bind(TAIL_LOAD_16); - __ ldrq(vtmp, Address(tmp2)); - __ ldr(tmpU, Address(__ post(cnt1, 8))); - __ zip1(vtmp3, __ T16B, vtmp, vtmpZ); - __ zip2(vtmp, __ T16B, vtmp, vtmpZ); - __ fmovd(tmpL, vtmp3); - __ eor(rscratch2, tmp3, tmpL); - __ cbnz(rscratch2, DIFF2); - - __ ldr(tmp3, Address(__ post(cnt1, 8))); - __ umov(tmpL, vtmp3, __ D, 1); - __ eor(rscratch2, tmpU, tmpL); - __ cbnz(rscratch2, DIFF1); - - __ ldr(tmpU, Address(__ post(cnt1, 8))); - __ fmovd(tmpL, vtmp); - __ eor(rscratch2, tmp3, tmpL); - __ cbnz(rscratch2, DIFF2); - - __ umov(tmpL, vtmp, __ D, 1); - __ eor(rscratch2, tmpU, tmpL); - __ cbnz(rscratch2, DIFF1); + __ cmn(cnt2, (u1)16); + __ br(__ EQ, LOAD_LAST); + __ bind(TAIL); // 1..15 characters left until last load (last 4 characters) + __ add(cnt1, cnt1, cnt2, __ LSL, 1); // Address of 8 bytes before last 4 characters in UTF-16 string + __ add(tmp2, tmp2, cnt2); // Address of 16 bytes before last 4 characters in Latin1 string + __ ldr(tmp3, Address(cnt1, -8)); + compare_string_16_x_LU(tmpL, tmpU, DIFF1, DIFF2); // last 16 characters before last load __ b(LOAD_LAST); __ bind(DIFF2); __ mov(tmpU, tmp3); @@ -4183,10 +4088,12 @@ __ pop(spilled_regs, sp); __ b(CALCULATE_DIFFERENCE); __ bind(LOAD_LAST); + // Last 4 UTF-16 characters are already pre-loaded into tmp3 by compare_string_16_x_LU. + // No need to load it again + __ mov(tmpU, tmp3); __ pop(spilled_regs, sp); __ ldrs(vtmp, Address(strL)); - __ ldr(tmpU, Address(strU)); __ zip1(vtmp, __ T8B, vtmp, vtmpZ); __ fmovd(tmpL, vtmp); @@ -4229,7 +4136,7 @@ DIFF_LAST_POSITION, DIFF_LAST_POSITION2; // exit from large loop when less than 64 bytes left to read or we're about // to prefetch memory behind array border - int largeLoopExitCondition = MAX(64, SoftwarePrefetchHintDistance)/(isLL ? 1 : 2); + int largeLoopExitCondition = MAX2(64, SoftwarePrefetchHintDistance)/(isLL ? 1 : 2); // cnt1/cnt2 contains amount of characters to compare. cnt1 can be re-used // update cnt2 counter with already loaded 8 bytes __ sub(cnt2, cnt2, wordSize/(isLL ? 1 : 2)); @@ -4248,10 +4155,10 @@ compare_string_16_bytes_same(DIFF, DIFF2); __ br(__ GT, LARGE_LOOP_PREFETCH); __ cbz(cnt2, LAST_CHECK_AND_LENGTH_DIFF); // no more chars left? - // less than 16 bytes left? - __ subs(cnt2, cnt2, isLL ? 16 : 8); - __ br(__ LT, TAIL); } + // less than 16 bytes left? + __ subs(cnt2, cnt2, isLL ? 16 : 8); + __ br(__ LT, TAIL); __ bind(SMALL_LOOP); compare_string_16_bytes_same(DIFF, DIFF2); __ subs(cnt2, cnt2, isLL ? 16 : 8); @@ -4380,6 +4287,7 @@ __ ldr(ch1, Address(str1)); // Read whole register from str2. It is safe, because length >=8 here __ ldr(ch2, Address(str2)); + __ sub(cnt2, cnt2, cnt1); __ andr(first, ch1, str1_isL ? 0xFF : 0xFFFF); if (str1_isL != str2_isL) { __ eor(v0, __ T16B, v0, v0); @@ -4653,7 +4561,7 @@ address entry = __ pc(); Label LOOP, LOOP_START, LOOP_PRFM, LOOP_PRFM_START, DONE; Register src = r0, dst = r1, len = r2, octetCounter = r3; - const int large_loop_threshold = MAX(64, SoftwarePrefetchHintDistance)/8 + 4; + const int large_loop_threshold = MAX2(64, SoftwarePrefetchHintDistance)/8 + 4; // do one more 8-byte read to have address 16-byte aligned in most cases // also use single store instruction @@ -4777,6 +4685,315 @@ return start; } +#ifdef LINUX + + // ARMv8.1 LSE versions of the atomic stubs used by Atomic::PlatformXX. + // + // If LSE is in use, generate LSE versions of all the stubs. The + // non-LSE versions are in atomic_aarch64.S. + + // class AtomicStubMark records the entry point of a stub and the + // stub pointer which will point to it. The stub pointer is set to + // the entry point when ~AtomicStubMark() is called, which must be + // after ICache::invalidate_range. This ensures safe publication of + // the generated code. + class AtomicStubMark { + address _entry_point; + aarch64_atomic_stub_t *_stub; + MacroAssembler *_masm; + public: + AtomicStubMark(MacroAssembler *masm, aarch64_atomic_stub_t *stub) { + _masm = masm; + __ align(32); + _entry_point = __ pc(); + _stub = stub; + } + ~AtomicStubMark() { + *_stub = (aarch64_atomic_stub_t)_entry_point; + } + }; + + // NB: For memory_order_conservative we need a trailing membar after + // LSE atomic operations but not a leading membar. + // + // We don't need a leading membar because a clause in the Arm ARM + // says: + // + // Barrier-ordered-before + // + // Barrier instructions order prior Memory effects before subsequent + // Memory effects generated by the same Observer. A read or a write + // RW1 is Barrier-ordered-before a read or a write RW 2 from the same + // Observer if and only if RW1 appears in program order before RW 2 + // and [ ... ] at least one of RW 1 and RW 2 is generated by an atomic + // instruction with both Acquire and Release semantics. + // + // All the atomic instructions {ldaddal, swapal, casal} have Acquire + // and Release semantics, therefore we don't need a leading + // barrier. However, there is no corresponding Barrier-ordered-after + // relationship, therefore we need a trailing membar to prevent a + // later store or load from being reordered with the store in an + // atomic instruction. + // + // This was checked by using the herd7 consistency model simulator + // (http://diy.inria.fr/) with this test case: + // + // AArch64 LseCas + // { 0:X1=x; 0:X2=y; 1:X1=x; 1:X2=y; } + // P0 | P1; + // LDR W4, [X2] | MOV W3, #0; + // DMB LD | MOV W4, #1; + // LDR W3, [X1] | CASAL W3, W4, [X1]; + // | DMB ISH; + // | STR W4, [X2]; + // exists + // (0:X3=0 /\ 0:X4=1) + // + // If X3 == 0 && X4 == 1, the store to y in P1 has been reordered + // with the store to x in P1. Without the DMB in P1 this may happen. + // + // At the time of writing we don't know of any AArch64 hardware that + // reorders stores in this way, but the Reference Manual permits it. + + void gen_cas_entry(Assembler::operand_size size, + atomic_memory_order order) { + Register prev = r3, ptr = c_rarg0, compare_val = c_rarg1, + exchange_val = c_rarg2; + bool acquire, release; + switch (order) { + case memory_order_relaxed: + acquire = false; + release = false; + break; + default: + acquire = true; + release = true; + break; + } + __ mov(prev, compare_val); + __ lse_cas(prev, exchange_val, ptr, size, acquire, release, /*not_pair*/true); + if (order == memory_order_conservative) { + __ membar(Assembler::StoreStore|Assembler::StoreLoad); + } + if (size == Assembler::xword) { + __ mov(r0, prev); + } else { + __ movw(r0, prev); + } + __ ret(lr); + } + + void gen_ldaddal_entry(Assembler::operand_size size) { + Register prev = r2, addr = c_rarg0, incr = c_rarg1; + __ ldaddal(size, incr, prev, addr); + __ membar(Assembler::StoreStore|Assembler::StoreLoad); + if (size == Assembler::xword) { + __ mov(r0, prev); + } else { + __ movw(r0, prev); + } + __ ret(lr); + } + + void gen_swpal_entry(Assembler::operand_size size) { + Register prev = r2, addr = c_rarg0, incr = c_rarg1; + __ swpal(size, incr, prev, addr); + __ membar(Assembler::StoreStore|Assembler::StoreLoad); + if (size == Assembler::xword) { + __ mov(r0, prev); + } else { + __ movw(r0, prev); + } + __ ret(lr); + } + + void generate_atomic_entry_points() { + if (! UseLSE) { + return; + } + + __ align(CodeEntryAlignment); + StubCodeMark mark(this, "StubRoutines", "atomic entry points"); + address first_entry = __ pc(); + + // All memory_order_conservative + AtomicStubMark mark_fetch_add_4(_masm, &aarch64_atomic_fetch_add_4_impl); + gen_ldaddal_entry(Assembler::word); + AtomicStubMark mark_fetch_add_8(_masm, &aarch64_atomic_fetch_add_8_impl); + gen_ldaddal_entry(Assembler::xword); + + AtomicStubMark mark_xchg_4(_masm, &aarch64_atomic_xchg_4_impl); + gen_swpal_entry(Assembler::word); + AtomicStubMark mark_xchg_8_impl(_masm, &aarch64_atomic_xchg_8_impl); + gen_swpal_entry(Assembler::xword); + + // CAS, memory_order_conservative + AtomicStubMark mark_cmpxchg_1(_masm, &aarch64_atomic_cmpxchg_1_impl); + gen_cas_entry(MacroAssembler::byte, memory_order_conservative); + AtomicStubMark mark_cmpxchg_4(_masm, &aarch64_atomic_cmpxchg_4_impl); + gen_cas_entry(MacroAssembler::word, memory_order_conservative); + AtomicStubMark mark_cmpxchg_8(_masm, &aarch64_atomic_cmpxchg_8_impl); + gen_cas_entry(MacroAssembler::xword, memory_order_conservative); + + // CAS, memory_order_relaxed + AtomicStubMark mark_cmpxchg_1_relaxed + (_masm, &aarch64_atomic_cmpxchg_1_relaxed_impl); + gen_cas_entry(MacroAssembler::byte, memory_order_relaxed); + AtomicStubMark mark_cmpxchg_4_relaxed + (_masm, &aarch64_atomic_cmpxchg_4_relaxed_impl); + gen_cas_entry(MacroAssembler::word, memory_order_relaxed); + AtomicStubMark mark_cmpxchg_8_relaxed + (_masm, &aarch64_atomic_cmpxchg_8_relaxed_impl); + gen_cas_entry(MacroAssembler::xword, memory_order_relaxed); + + ICache::invalidate_range(first_entry, __ pc() - first_entry); + } +#endif // LINUX + + void generate_base64_encode_simdround(Register src, Register dst, + FloatRegister codec, u8 size) { + + FloatRegister in0 = v4, in1 = v5, in2 = v6; + FloatRegister out0 = v16, out1 = v17, out2 = v18, out3 = v19; + FloatRegister ind0 = v20, ind1 = v21, ind2 = v22, ind3 = v23; + + Assembler::SIMD_Arrangement arrangement = size == 16 ? __ T16B : __ T8B; + + __ ld3(in0, in1, in2, arrangement, __ post(src, 3 * size)); + + __ ushr(ind0, arrangement, in0, 2); + + __ ushr(ind1, arrangement, in1, 2); + __ shl(in0, arrangement, in0, 6); + __ orr(ind1, arrangement, ind1, in0); + __ ushr(ind1, arrangement, ind1, 2); + + __ ushr(ind2, arrangement, in2, 4); + __ shl(in1, arrangement, in1, 4); + __ orr(ind2, arrangement, in1, ind2); + __ ushr(ind2, arrangement, ind2, 2); + + __ shl(ind3, arrangement, in2, 2); + __ ushr(ind3, arrangement, ind3, 2); + + __ tbl(out0, arrangement, codec, 4, ind0); + __ tbl(out1, arrangement, codec, 4, ind1); + __ tbl(out2, arrangement, codec, 4, ind2); + __ tbl(out3, arrangement, codec, 4, ind3); + + __ st4(out0, out1, out2, out3, arrangement, __ post(dst, 4 * size)); + } + + /** + * Arguments: + * + * Input: + * c_rarg0 - src_start + * c_rarg1 - src_offset + * c_rarg2 - src_length + * c_rarg3 - dest_start + * c_rarg4 - dest_offset + * c_rarg5 - isURL + * + */ + address generate_base64_encodeBlock() { + + static const char toBase64[64] = { + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', + 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', + 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', + 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', + '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '+', '/' + }; + + static const char toBase64URL[64] = { + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', + 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', + 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', + 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', + '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '-', '_' + }; + + __ align(CodeEntryAlignment); + StubCodeMark mark(this, "StubRoutines", "encodeBlock"); + address start = __ pc(); + + Register src = c_rarg0; // source array + Register soff = c_rarg1; // source start offset + Register send = c_rarg2; // source end offset + Register dst = c_rarg3; // dest array + Register doff = c_rarg4; // position for writing to dest array + Register isURL = c_rarg5; // Base64 or URL chracter set + + // c_rarg6 and c_rarg7 are free to use as temps + Register codec = c_rarg6; + Register length = c_rarg7; + + Label ProcessData, Process48B, Process24B, Process3B, SIMDExit, Exit; + + __ add(src, src, soff); + __ add(dst, dst, doff); + __ sub(length, send, soff); + + // load the codec base address + __ lea(codec, ExternalAddress((address) toBase64)); + __ cbz(isURL, ProcessData); + __ lea(codec, ExternalAddress((address) toBase64URL)); + + __ BIND(ProcessData); + + // too short to formup a SIMD loop, roll back + __ cmp(length, (u1)24); + __ br(Assembler::LT, Process3B); + + __ ld1(v0, v1, v2, v3, __ T16B, Address(codec)); + + __ BIND(Process48B); + __ cmp(length, (u1)48); + __ br(Assembler::LT, Process24B); + generate_base64_encode_simdround(src, dst, v0, 16); + __ sub(length, length, 48); + __ b(Process48B); + + __ BIND(Process24B); + __ cmp(length, (u1)24); + __ br(Assembler::LT, SIMDExit); + generate_base64_encode_simdround(src, dst, v0, 8); + __ sub(length, length, 24); + + __ BIND(SIMDExit); + __ cbz(length, Exit); + + __ BIND(Process3B); + // 3 src bytes, 24 bits + __ ldrb(r10, __ post(src, 1)); + __ ldrb(r11, __ post(src, 1)); + __ ldrb(r12, __ post(src, 1)); + __ orrw(r11, r11, r10, Assembler::LSL, 8); + __ orrw(r12, r12, r11, Assembler::LSL, 8); + // codec index + __ ubfmw(r15, r12, 18, 23); + __ ubfmw(r14, r12, 12, 17); + __ ubfmw(r13, r12, 6, 11); + __ andw(r12, r12, 63); + // get the code based on the codec + __ ldrb(r15, Address(codec, r15, Address::uxtw(0))); + __ ldrb(r14, Address(codec, r14, Address::uxtw(0))); + __ ldrb(r13, Address(codec, r13, Address::uxtw(0))); + __ ldrb(r12, Address(codec, r12, Address::uxtw(0))); + __ strb(r15, __ post(dst, 1)); + __ strb(r14, __ post(dst, 1)); + __ strb(r13, __ post(dst, 1)); + __ strb(r12, __ post(dst, 1)); + __ sub(length, length, 3); + __ cbnz(length, Process3B); + + __ BIND(Exit); + __ ret(lr); + + return start; + } + // Continuation point for throwing of implicit exceptions that are // not handled in the current activation. Fabricates an exception // oop and initiates normal exception dispatching in this @@ -4838,7 +5055,7 @@ // Set up last_Java_sp and last_Java_fp address the_pc = __ pc(); - __ set_last_Java_frame(sp, rfp, (address)NULL, rscratch1); + __ set_last_Java_frame(sp, rfp, the_pc, rscratch1); // Call runtime if (arg1 != noreg) { @@ -4851,7 +5068,7 @@ __ mov(c_rarg0, rthread); BLOCK_COMMENT("call runtime_entry"); __ mov(rscratch1, runtime_entry); - __ blrt(rscratch1, 3 /* number_of_arguments */, 0, 1); + __ blr(rscratch1); // Generate oop map OopMap* map = new OopMap(framesize, 0); @@ -5389,12 +5606,12 @@ // In C, approximately: // void - // montgomery_multiply(unsigned long Pa_base[], unsigned long Pb_base[], - // unsigned long Pn_base[], unsigned long Pm_base[], - // unsigned long inv, int len) { - // unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator - // unsigned long *Pa, *Pb, *Pn, *Pm; - // unsigned long Ra, Rb, Rn, Rm; + // montgomery_multiply(julong Pa_base[], julong Pb_base[], + // julong Pn_base[], julong Pm_base[], + // julong inv, int len) { + // julong t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator + // julong *Pa, *Pb, *Pn, *Pm; + // julong Ra, Rb, Rn, Rm; // int i; @@ -5602,11 +5819,12 @@ // In C, approximately: // void - // montgomery_square(unsigned long Pa_base[], unsigned long Pn_base[], - // unsigned long Pm_base[], unsigned long inv, int len) { - // unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator - // unsigned long *Pa, *Pb, *Pn, *Pm; - // unsigned long Ra, Rb, Rn, Rm; + // montgomery_multiply(julong Pa_base[], julong Pb_base[], + // julong Pn_base[], julong Pm_base[], + // julong inv, int len) { + // julong t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator + // julong *Pa, *Pb, *Pn, *Pm; + // julong Ra, Rb, Rn, Rm; // int i; @@ -5799,6 +6017,7 @@ // byte_array_inflate stub for large arrays. StubRoutines::aarch64::_large_byte_array_inflate = generate_large_byte_array_inflate(); +#ifdef COMPILER2 if (UseMultiplyToLenIntrinsic) { StubRoutines::_multiplyToLen = generate_multiplyToLen(); } @@ -5824,13 +6043,17 @@ // because it's faster for the sizes of modulus we care about. StubRoutines::_montgomerySquare = g.generate_multiply(); } +#endif // COMPILER2 -#ifndef BUILTIN_SIM // generate GHASH intrinsics code if (UseGHASHIntrinsics) { StubRoutines::_ghash_processBlocks = generate_ghash_processBlocks(); } + if (UseBASE64Intrinsics) { + StubRoutines::_base64_encodeBlock = generate_base64_encodeBlock(); + } + if (UseAESIntrinsics) { StubRoutines::_aescrypt_encryptBlock = generate_aescrypt_encryptBlock(); StubRoutines::_aescrypt_decryptBlock = generate_aescrypt_decryptBlock(); @@ -5859,8 +6082,13 @@ generate_safefetch("SafeFetchN", sizeof(intptr_t), &StubRoutines::_safefetchN_entry, &StubRoutines::_safefetchN_fault_pc, &StubRoutines::_safefetchN_continuation_pc); -#endif - StubRoutines::aarch64::set_completed(); +#ifdef LINUX + + generate_atomic_entry_points(); + +#endif // LINUX + + StubRoutines::aarch64::set_completed(); } public: @@ -5876,3 +6104,30 @@ void StubGenerator_generate(CodeBuffer* code, bool all) { StubGenerator g(code, all); } + + +#ifdef LINUX + +// Define pointers to atomic stubs and initialize them to point to the +// code in atomic_aarch64.S. + +#define DEFAULT_ATOMIC_OP(OPNAME, SIZE, RELAXED) \ + extern "C" uint64_t aarch64_atomic_ ## OPNAME ## _ ## SIZE ## RELAXED ## _default_impl \ + (volatile void *ptr, uint64_t arg1, uint64_t arg2); \ + aarch64_atomic_stub_t aarch64_atomic_ ## OPNAME ## _ ## SIZE ## RELAXED ## _impl \ + = aarch64_atomic_ ## OPNAME ## _ ## SIZE ## RELAXED ## _default_impl; + +DEFAULT_ATOMIC_OP(fetch_add, 4, ) +DEFAULT_ATOMIC_OP(fetch_add, 8, ) +DEFAULT_ATOMIC_OP(xchg, 4, ) +DEFAULT_ATOMIC_OP(xchg, 8, ) +DEFAULT_ATOMIC_OP(cmpxchg, 1, ) +DEFAULT_ATOMIC_OP(cmpxchg, 4, ) +DEFAULT_ATOMIC_OP(cmpxchg, 8, ) +DEFAULT_ATOMIC_OP(cmpxchg, 1, _relaxed) +DEFAULT_ATOMIC_OP(cmpxchg, 4, _relaxed) +DEFAULT_ATOMIC_OP(cmpxchg, 8, _relaxed) + +#undef DEFAULT_ATOMIC_OP + +#endif // LINUX
diff --git a/src/hotspot/cpu/aarch64/stubRoutines_aarch64.cpp b/src/hotspot/cpu/aarch64/stubRoutines_aarch64.cpp index 98a3fd6..ff73c65 100644 --- a/src/hotspot/cpu/aarch64/stubRoutines_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/stubRoutines_aarch64.cpp
@@ -61,7 +61,7 @@ /** * crc_table[] from jdk/src/share/native/java/util/zip/zlib-1.2.5/crc32.h */ -juint StubRoutines::aarch64::_crc_table[] ATTRIBUTE_ALIGNED(4096) = +ATTRIBUTE_ALIGNED(4096) juint StubRoutines::aarch64::_crc_table[] = { // Table 0 0x00000000UL, 0x77073096UL, 0xee0e612cUL, 0x990951baUL, 0x076dc419UL, @@ -287,7 +287,12 @@ 0xD502ED78UL, 0xAE7D62EDUL, // byte swap of word swap }; -juint StubRoutines::aarch64::_npio2_hw[] __attribute__ ((aligned(64))) = { +// Accumulation coefficients for adler32 upper 16 bits +ATTRIBUTE_ALIGNED(64) jubyte StubRoutines::aarch64::_adler_table[] = { + 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1 +}; + +ATTRIBUTE_ALIGNED(64) juint StubRoutines::aarch64::_npio2_hw[] = { // first, various coefficient values: 0.5, invpio2, pio2_1, pio2_1t, pio2_2, // pio2_2t, pio2_3, pio2_3t // This is a small optimization wich keeping double[8] values in int[] table @@ -319,7 +324,7 @@ // Coefficients for sin(x) polynomial approximation: S1..S6. // See kernel_sin comments in macroAssembler_aarch64_trig.cpp for details -jdouble StubRoutines::aarch64::_dsin_coef[] __attribute__ ((aligned(64))) = { +ATTRIBUTE_ALIGNED(64) jdouble StubRoutines::aarch64::_dsin_coef[] = { -1.66666666666666324348e-01, // 0xBFC5555555555549 8.33333333332248946124e-03, // 0x3F8111111110F8A6 -1.98412698298579493134e-04, // 0xBF2A01A019C161D5 @@ -330,7 +335,7 @@ // Coefficients for cos(x) polynomial approximation: C1..C6. // See kernel_cos comments in macroAssembler_aarch64_trig.cpp for details -jdouble StubRoutines::aarch64::_dcos_coef[] __attribute__ ((aligned(64))) = { +ATTRIBUTE_ALIGNED(64) jdouble StubRoutines::aarch64::_dcos_coef[] = { 4.16666666666666019037e-02, // c0x3FA555555555554C -1.38888888888741095749e-03, // 0xBF56C16C16C15177 2.48015872894767294178e-05, // 0x3EFA01A019CB1590 @@ -345,7 +350,7 @@ // Converted to double to avoid unnecessary conversion in code // NOTE: table looks like original int table: {0xA2F983, 0x6E4E44,...} with // only (double) conversion added -jdouble StubRoutines::aarch64::_two_over_pi[] __attribute__ ((aligned(64))) = { +ATTRIBUTE_ALIGNED(64) jdouble StubRoutines::aarch64::_two_over_pi[] = { (double)0xA2F983, (double)0x6E4E44, (double)0x1529FC, (double)0x2757D1, (double)0xF534DD, (double)0xC0DB62, (double)0x95993C, (double)0x439041, (double)0xFE5163, (double)0xABDEBB, (double)0xC561B7, (double)0x246E3A, (double)0x424DD2, (double)0xE00649, (double)0x2EEA09, (double)0xD1921C, (double)0xFE1DEB, (double)0x1CB129, @@ -360,7 +365,7 @@ }; // Pi over 2 value -jdouble StubRoutines::aarch64::_pio2[] __attribute__ ((aligned(64))) = { +ATTRIBUTE_ALIGNED(64) jdouble StubRoutines::aarch64::_pio2[] = { 1.57079625129699707031e+00, // 0x3FF921FB40000000 7.54978941586159635335e-08, // 0x3E74442D00000000 5.39030252995776476554e-15, // 0x3CF8469880000000
diff --git a/src/hotspot/cpu/aarch64/stubRoutines_aarch64.hpp b/src/hotspot/cpu/aarch64/stubRoutines_aarch64.hpp index 4315b51..4e5930b 100644 --- a/src/hotspot/cpu/aarch64/stubRoutines_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/stubRoutines_aarch64.hpp
@@ -30,13 +30,8 @@ // definition. See stubRoutines.hpp for a description on how to // extend it. -// n.b. if we are notifying entry/exit to the simulator then the call -// stub does a notify at normal return placing -// call_stub_return_address one instruction beyond the notify. the -// latter address is sued by the stack unwind code when doign an -// exception return. static bool returns_to_call_stub(address return_pc) { - return return_pc == _call_stub_return_address + (NotifySimulator ? -4 : 0); + return return_pc == _call_stub_return_address; } enum platform_dependent_constants { @@ -186,6 +181,7 @@ private: static juint _crc_table[]; + static jubyte _adler_table[]; // begin trigonometric tables block. See comments in .cpp file static juint _npio2_hw[]; static jdouble _two_over_pi[];
diff --git a/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp index e19fb92..6b12b9c 100644 --- a/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, 2018, Red Hat Inc. All rights reserved. + * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -49,16 +49,13 @@ #include "runtime/timer.hpp" #include "runtime/vframeArray.hpp" #include "utilities/debug.hpp" +#include "utilities/macros.hpp" #include <sys/types.h> #ifndef PRODUCT #include "oops/method.hpp" #endif // !PRODUCT -#ifdef BUILTIN_SIM -#include "../../../../../../simulator/simulator.hpp" -#endif - // Size of interpreter code. Increase if too small. Interpreter will // fail with a guarantee ("not enough space for interpreter generation"); // if too small. @@ -300,9 +297,8 @@ ShouldNotReachHere(); fn = NULL; // unreachable } - const int gpargs = 0, rtype = 3; __ mov(rscratch1, fn); - __ blrt(rscratch1, gpargs, fpargs, rtype); + __ blr(rscratch1); } // Abstract method entry @@ -449,7 +445,6 @@ Register obj = r0; Register mdp = r1; Register tmp = r2; - __ ldr(mdp, Address(rmethod, Method::method_data_offset())); __ profile_return_type(mdp, obj, tmp); } @@ -469,13 +464,6 @@ __ sub(rscratch1, rscratch2, rscratch1, ext::uxtw, 3); __ andr(sp, rscratch1, -16); -#ifndef PRODUCT - // tell the simulator that the method has been reentered - if (NotifySimulator) { - __ notify(Assembler::method_reentry); - } -#endif - __ check_and_handle_popframe(rthread); __ check_and_handle_earlyret(rthread); @@ -514,7 +502,7 @@ // only occur on method entry so emit it only for vtos with step 0. if ((EnableJVMCI || UseAOT) && state == vtos && step == 0) { Label L; - __ ldr(rscratch1, Address(rthread, Thread::pending_exception_offset())); + __ ldrb(rscratch1, Address(rthread, JavaThread::pending_monitorenter_offset())); __ cbz(rscratch1, L); // Clear flag. __ strb(zr, Address(rthread, JavaThread::pending_monitorenter_offset())); @@ -525,7 +513,7 @@ #ifdef ASSERT if (EnableJVMCI) { Label L; - __ ldr(rscratch1, Address(rthread, Thread::pending_exception_offset())); + __ ldrb(rscratch1, Address(rthread, JavaThread::pending_monitorenter_offset())); __ cbz(rscratch1, L); __ stop("unexpected pending monitor in deopt entry"); __ bind(L); @@ -885,8 +873,16 @@ } // Get mirror and store it in the frame as GC root for this Method* - __ load_mirror(rscratch1, rmethod); - __ stp(rscratch1, zr, Address(sp, 4 * wordSize)); +#if INCLUDE_SHENANDOAHGC + if (UseShenandoahGC) { + __ load_mirror(r10, rmethod); + __ stp(r10, zr, Address(sp, 4 * wordSize)); + } else +#endif + { + __ load_mirror(rscratch1, rmethod); + __ stp(rscratch1, zr, Address(sp, 4 * wordSize)); + } __ ldr(rcpool, Address(rmethod, Method::const_offset())); __ ldr(rcpool, Address(rcpool, ConstMethod::constants_offset())); @@ -1007,7 +1003,7 @@ __ ldrw(val, Address(esp, 0)); // byte value __ ldrw(crc, Address(esp, wordSize)); // Initial CRC - unsigned long offset; + uint64_t offset; __ adrp(tbl, ExternalAddress(StubRoutines::crc_table_addr()), offset); __ add(tbl, tbl, offset); @@ -1180,12 +1176,6 @@ // initialize fixed part of activation frame generate_fixed_frame(true); -#ifndef PRODUCT - // tell the simulator that a method has been entered - if (NotifySimulator) { - __ notify(Assembler::method_entry); - } -#endif // make sure method is native & not abstract #ifdef ASSERT @@ -1346,9 +1336,11 @@ // pass JNIEnv __ add(c_rarg0, rthread, in_bytes(JavaThread::jni_environment_offset())); - // It is enough that the pc() points into the right code - // segment. It does not have to be the correct return pc. - __ set_last_Java_frame(esp, rfp, (address)NULL, rscratch1); + // Set the last Java PC in the frame anchor to be the return address from + // the call to the native method: this will allow the debugger to + // generate an accurate stack trace. + Label native_return; + __ set_last_Java_frame(esp, rfp, native_return, rscratch1); // change thread state #ifdef ASSERT @@ -1368,7 +1360,8 @@ __ stlrw(rscratch1, rscratch2); // Call the native method. - __ blrt(r10, rscratch1); + __ blr(r10); + __ bind(native_return); __ maybe_isb(); __ get_method(rmethod); // result potentially in r0 or v0 @@ -1417,7 +1410,7 @@ // __ mov(c_rarg0, rthread); __ mov(rscratch2, CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans)); - __ blrt(rscratch2, 1, 0, 0); + __ blr(rscratch2); __ maybe_isb(); __ get_method(rmethod); __ reinit_heapbase(); @@ -1468,7 +1461,7 @@ __ pusha(); // XXX only save smashed registers __ mov(c_rarg0, rthread); __ mov(rscratch2, CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)); - __ blrt(rscratch2, 0, 0, 0); + __ blr(rscratch2); __ popa(); // XXX only restore smashed registers __ bind(no_reguard); } @@ -1600,35 +1593,36 @@ __ add(rlocals, esp, r2, ext::uxtx, 3); __ sub(rlocals, rlocals, wordSize); - // Make room for locals - __ sub(rscratch1, esp, r3, ext::uxtx, 3); - __ andr(sp, rscratch1, -16); + __ mov(rscratch1, esp); // r3 - # of additional locals // allocate space for locals // explicitly initialize locals + // Initializing memory allocated for locals in the same direction as + // the stack grows to ensure page initialization order according + // to windows-aarch64 stack page growth requirement (see + // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions?view=msvc-160#stack) { Label exit, loop; __ ands(zr, r3, r3); __ br(Assembler::LE, exit); // do nothing if r3 <= 0 __ bind(loop); - __ str(zr, Address(__ post(rscratch1, wordSize))); + __ str(zr, Address(__ pre(rscratch1, -wordSize))); __ sub(r3, r3, 1); // until everything initialized __ cbnz(r3, loop); __ bind(exit); } + // Padding between locals and fixed part of activation frame to ensure + // SP is always 16-byte aligned. + __ andr(sp, rscratch1, -16); + // And the base dispatch table __ get_dispatch(); // initialize fixed part of activation frame generate_fixed_frame(false); -#ifndef PRODUCT - // tell the simulator that a method has been entered - if (NotifySimulator) { - __ notify(Assembler::method_entry); - } -#endif + // make sure method is not native & not abstract #ifdef ASSERT __ ldrw(r0, access_flags); @@ -1659,13 +1653,8 @@ __ mov(rscratch2, true); __ strb(rscratch2, do_not_unlock_if_synchronized); - Label no_mdp; Register mdp = r3; - __ ldr(mdp, Address(rmethod, Method::method_data_offset())); - __ cbz(mdp, no_mdp); - __ add(mdp, mdp, in_bytes(MethodData::data_offset())); __ profile_parameters_type(mdp, r1, r2); - __ bind(no_mdp); // increment invocation count & check for overflow Label invocation_counter_overflow; @@ -1764,13 +1753,6 @@ __ reinit_heapbase(); // restore rheapbase as heapbase. __ get_dispatch(); -#ifndef PRODUCT - // tell the simulator that the caller method has been reentered - if (NotifySimulator) { - __ get_method(rmethod); - __ notify(Assembler::method_reentry); - } -#endif // Entry point for exceptions thrown within interpreter code Interpreter::_throw_exception_entry = __ pc(); // If we came here via a NullPointerException on the receiver of a @@ -2088,121 +2070,4 @@ __ pop(rscratch1); } -#ifdef BUILTIN_SIM - -#include <sys/mman.h> -#include <unistd.h> - -extern "C" { - static int PAGESIZE = getpagesize(); - int is_mapped_address(u_int64_t address) - { - address = (address & ~((u_int64_t)PAGESIZE - 1)); - if (msync((void *)address, PAGESIZE, MS_ASYNC) == 0) { - return true; - } - if (errno != ENOMEM) { - return true; - } - return false; - } - - void bccheck1(u_int64_t pc, u_int64_t fp, char *method, int *bcidx, int *framesize, char *decode) - { - if (method != 0) { - method[0] = '\0'; - } - if (bcidx != 0) { - *bcidx = -2; - } - if (decode != 0) { - decode[0] = 0; - } - - if (framesize != 0) { - *framesize = -1; - } - - if (Interpreter::contains((address)pc)) { - AArch64Simulator *sim = AArch64Simulator::get_current(UseSimulatorCache, DisableBCCheck); - Method* meth; - address bcp; - if (fp) { -#define FRAME_SLOT_METHOD 3 -#define FRAME_SLOT_BCP 7 - meth = (Method*)sim->getMemory()->loadU64(fp - (FRAME_SLOT_METHOD << 3)); - bcp = (address)sim->getMemory()->loadU64(fp - (FRAME_SLOT_BCP << 3)); -#undef FRAME_SLOT_METHOD -#undef FRAME_SLOT_BCP - } else { - meth = (Method*)sim->getCPUState().xreg(RMETHOD, 0); - bcp = (address)sim->getCPUState().xreg(RBCP, 0); - } - if (meth->is_native()) { - return; - } - if(method && meth->is_method()) { - ResourceMark rm; - method[0] = 'I'; - method[1] = ' '; - meth->name_and_sig_as_C_string(method + 2, 398); - } - if (bcidx) { - if (meth->contains(bcp)) { - *bcidx = meth->bci_from(bcp); - } else { - *bcidx = -2; - } - } - if (decode) { - if (!BytecodeTracer::closure()) { - BytecodeTracer::set_closure(BytecodeTracer::std_closure()); - } - stringStream str(decode, 400); - BytecodeTracer::trace(meth, bcp, &str); - } - } else { - if (method) { - CodeBlob *cb = CodeCache::find_blob((address)pc); - if (cb != NULL) { - if (cb->is_nmethod()) { - ResourceMark rm; - nmethod* nm = (nmethod*)cb; - method[0] = 'C'; - method[1] = ' '; - nm->method()->name_and_sig_as_C_string(method + 2, 398); - } else if (cb->is_adapter_blob()) { - strcpy(method, "B adapter blob"); - } else if (cb->is_runtime_stub()) { - strcpy(method, "B runtime stub"); - } else if (cb->is_exception_stub()) { - strcpy(method, "B exception stub"); - } else if (cb->is_deoptimization_stub()) { - strcpy(method, "B deoptimization stub"); - } else if (cb->is_safepoint_stub()) { - strcpy(method, "B safepoint stub"); - } else if (cb->is_uncommon_trap_stub()) { - strcpy(method, "B uncommon trap stub"); - } else if (cb->contains((address)StubRoutines::call_stub())) { - strcpy(method, "B call stub"); - } else { - strcpy(method, "B unknown blob : "); - strcat(method, cb->name()); - } - if (framesize != NULL) { - *framesize = cb->frame_size(); - } - } - } - } - } - - - JNIEXPORT void bccheck(u_int64_t pc, u_int64_t fp, char *method, int *bcidx, int *framesize, char *decode) - { - bccheck1(pc, fp, method, bcidx, framesize, decode); - } -} - -#endif // BUILTIN_SIM #endif // !PRODUCT
diff --git a/src/hotspot/cpu/aarch64/templateTable_aarch64.cpp b/src/hotspot/cpu/aarch64/templateTable_aarch64.cpp index c9a3d92..dfd2040 100644 --- a/src/hotspot/cpu/aarch64/templateTable_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/templateTable_aarch64.cpp
@@ -1478,8 +1478,7 @@ case rem: __ fmovs(v1, v0); __ pop_f(v0); - __ call_VM_leaf_base1(CAST_FROM_FN_PTR(address, SharedRuntime::frem), - 0, 2, MacroAssembler::ret_type_float); + __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::frem)); break; default: ShouldNotReachHere(); @@ -1511,8 +1510,7 @@ case rem: __ fmovd(v1, v0); __ pop_d(v0); - __ call_VM_leaf_base1(CAST_FROM_FN_PTR(address, SharedRuntime::drem), - 0, 2, MacroAssembler::ret_type_double); + __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::drem)); break; default: ShouldNotReachHere(); @@ -1653,8 +1651,7 @@ __ fcvtzsw(r0, v0); __ get_fpsr(r1); __ cbzw(r1, L_Okay); - __ call_VM_leaf_base1(CAST_FROM_FN_PTR(address, SharedRuntime::f2i), - 0, 1, MacroAssembler::ret_type_integral); + __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2i)); __ bind(L_Okay); } break; @@ -1665,8 +1662,7 @@ __ fcvtzs(r0, v0); __ get_fpsr(r1); __ cbzw(r1, L_Okay); - __ call_VM_leaf_base1(CAST_FROM_FN_PTR(address, SharedRuntime::f2l), - 0, 1, MacroAssembler::ret_type_integral); + __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2l)); __ bind(L_Okay); } break; @@ -1680,8 +1676,7 @@ __ fcvtzdw(r0, v0); __ get_fpsr(r1); __ cbzw(r1, L_Okay); - __ call_VM_leaf_base1(CAST_FROM_FN_PTR(address, SharedRuntime::d2i), - 0, 1, MacroAssembler::ret_type_integral); + __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2i)); __ bind(L_Okay); } break; @@ -1692,8 +1687,7 @@ __ fcvtzd(r0, v0); __ get_fpsr(r1); __ cbzw(r1, L_Okay); - __ call_VM_leaf_base1(CAST_FROM_FN_PTR(address, SharedRuntime::d2l), - 0, 1, MacroAssembler::ret_type_integral); + __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2l)); __ bind(L_Okay); } break; @@ -1711,7 +1705,7 @@ Label done; __ pop_l(r1); __ cmp(r1, r0); - __ mov(r0, (u_int64_t)-1L); + __ mov(r0, (uint64_t)-1L); __ br(Assembler::LT, done); // __ mov(r0, 1UL); // __ csel(r0, r0, zr, Assembler::NE); @@ -1735,7 +1729,7 @@ if (unordered_result < 0) { // we want -1 for unordered or less than, 0 for equal and 1 for // greater than. - __ mov(r0, (u_int64_t)-1L); + __ mov(r0, (uint64_t)-1L); // for FP LT tests less than or unordered __ br(Assembler::LT, done); // install 0 for EQ otherwise 1 @@ -1916,7 +1910,7 @@ __ dispatch_only(vtos, /*generate_poll*/true); if (UseLoopCounter) { - if (ProfileInterpreter) { + if (ProfileInterpreter && !TieredCompilation) { // Out-of-line code to allocate method data oop. __ bind(profile_method); __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::profile_method)); @@ -2719,7 +2713,7 @@ { Label notVolatile; __ tbz(r5, ConstantPoolCacheEntry::is_volatile_shift, notVolatile); - __ membar(MacroAssembler::StoreStore); + __ membar(MacroAssembler::StoreStore | MacroAssembler::LoadStore); __ bind(notVolatile); } @@ -2884,7 +2878,7 @@ { Label notVolatile; __ tbz(r5, ConstantPoolCacheEntry::is_volatile_shift, notVolatile); - __ membar(MacroAssembler::StoreLoad); + __ membar(MacroAssembler::StoreLoad | MacroAssembler::StoreStore); __ bind(notVolatile); } } @@ -2969,6 +2963,9 @@ // access constant pool cache __ get_cache_and_index_at_bcp(r2, r1, 1); + // Must prevent reordering of the following cp cache loads with bytecode load + __ membar(MacroAssembler::LoadLoad); + // test for volatile with r3 __ ldrw(r3, Address(r2, in_bytes(base + ConstantPoolCacheEntry::flags_offset()))); @@ -2979,7 +2976,7 @@ { Label notVolatile; __ tbz(r3, ConstantPoolCacheEntry::is_volatile_shift, notVolatile); - __ membar(MacroAssembler::StoreStore); + __ membar(MacroAssembler::StoreStore | MacroAssembler::LoadStore); __ bind(notVolatile); } @@ -3027,7 +3024,7 @@ { Label notVolatile; __ tbz(r3, ConstantPoolCacheEntry::is_volatile_shift, notVolatile); - __ membar(MacroAssembler::StoreLoad); + __ membar(MacroAssembler::StoreLoad | MacroAssembler::StoreStore); __ bind(notVolatile); } } @@ -3061,6 +3058,10 @@ // access constant pool cache __ get_cache_and_index_at_bcp(r2, r1, 1); + + // Must prevent reordering of the following cp cache loads with bytecode load + __ membar(MacroAssembler::LoadLoad); + __ ldr(r1, Address(r2, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::f2_offset()))); __ ldrw(r3, Address(r2, in_bytes(ConstantPoolCache::base_offset() +
diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index c5d7a61..32dd246 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2015, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * @@ -29,17 +29,13 @@ #include "memory/resourceArea.hpp" #include "runtime/java.hpp" #include "runtime/stubCodeGenerator.hpp" +#include "runtime/vm_version.hpp" #include "utilities/macros.hpp" -#include "vm_version_aarch64.hpp" #include OS_HEADER_INLINE(os) -#ifndef BUILTIN_SIM #include <sys/auxv.h> #include <asm/hwcap.h> -#else -#define getauxval(hwcap) 0 -#endif #ifndef HWCAP_AES #define HWCAP_AES (1<<3) @@ -92,10 +88,6 @@ # define __ _masm-> address start = __ pc(); -#ifdef BUILTIN_SIM - __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void); -#endif - // void getPsrInfo(VM_Version::PsrInfo* psr_info); address entry = __ pc(); @@ -167,7 +159,11 @@ SoftwarePrefetchHintDistance &= ~7; } - unsigned long auxv = getauxval(AT_HWCAP); + if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (dcache_line > ContendedPaddingWidth)) { + ContendedPaddingWidth = dcache_line; + } + + uint64_t auxv = getauxval(AT_HWCAP); char buf[512]; @@ -177,7 +173,7 @@ if (FILE *f = fopen("/proc/cpuinfo", "r")) { char buf[128], *p; while (fgets(buf, sizeof (buf), f) != NULL) { - if (p = strchr(buf, ':')) { + if ((p = strchr(buf, ':')) != NULL) { long v = strtol(p+1, NULL, 0); if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) { _cpu = v; @@ -220,9 +216,11 @@ if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) { FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true); } +#ifdef COMPILER2 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) { FLAG_SET_DEFAULT(UseFPUForSpilling, true); } +#endif } // Cortex A53 @@ -244,6 +242,19 @@ } } + // Neoverse N1 + if (_cpu == CPU_ARM && (_model == 0xd0c || _model2 == 0xd0c)) { + if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) { + FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true); + } + } + + if (_cpu == CPU_ARM) { + if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) { + FLAG_SET_DEFAULT(UseSignumIntrinsic, true); + } + } + if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH; // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07) // we assume the worst and assume we could be on a big little system and have @@ -299,11 +310,11 @@ } } else { if (UseAES) { - warning("UseAES specified, but not supported on this CPU"); + warning("AES instructions are not available on this CPU"); FLAG_SET_DEFAULT(UseAES, false); } if (UseAESIntrinsics) { - warning("UseAESIntrinsics specified, but not supported on this CPU"); + warning("AES intrinsics are not available on this CPU"); FLAG_SET_DEFAULT(UseAESIntrinsics, false); } } @@ -375,6 +386,10 @@ FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); } + if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) { + UseBASE64Intrinsics = true; + } + if (is_zva_enabled()) { if (FLAG_IS_DEFAULT(UseBlockZeroing)) { FLAG_SET_DEFAULT(UseBlockZeroing, true); @@ -392,6 +407,15 @@ FLAG_SET_DEFAULT(UseUnalignedAccesses, true); } + if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) { + UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0; + } + + if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { + UsePopCountInstruction = true; + } + +#ifdef COMPILER2 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { UseMultiplyToLenIntrinsic = true; } @@ -404,14 +428,6 @@ UseMulAddIntrinsic = true; } - if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) { - UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0; - } - - if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { - UsePopCountInstruction = true; - } - if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { UseMontgomeryMultiplyIntrinsic = true; } @@ -419,7 +435,6 @@ UseMontgomerySquareIntrinsic = true; } -#ifdef COMPILER2 if (FLAG_IS_DEFAULT(OptoScheduling)) { OptoScheduling = true; }
diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp index 0a17f3e..dcb6342 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp
@@ -26,8 +26,8 @@ #ifndef CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP #define CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP +#include "runtime/abstract_vm_version.hpp" #include "runtime/globals_extension.hpp" -#include "runtime/vm_version.hpp" #include "utilities/sizes.hpp" class VM_Version : public Abstract_VM_Version {
diff --git a/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.cpp index 6444a9b..ebabc37 100644 --- a/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.cpp
@@ -50,7 +50,7 @@ _no_of_threads = _no_of_cores; _no_of_sockets = _no_of_cores; snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "AArch64"); - snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "%s", _features_string); + snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "AArch64 %s", _features_string); _initialized = true; }
diff --git a/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.hpp index 1bca629..1e556c9 100644 --- a/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.hpp
@@ -25,8 +25,8 @@ #ifndef CPU_AARCH64_VM_VM_VERSION_EXT_AARCH64_HPP #define CPU_AARCH64_VM_VM_VERSION_EXT_AARCH64_HPP +#include "runtime/vm_version.hpp" #include "utilities/macros.hpp" -#include "vm_version_aarch64.hpp" class VM_Version_Ext : public VM_Version { private:
diff --git a/src/hotspot/cpu/aarch64/vmreg_aarch64.cpp b/src/hotspot/cpu/aarch64/vmreg_aarch64.cpp index 9fd20be..35d0adf 100644 --- a/src/hotspot/cpu/aarch64/vmreg_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vmreg_aarch64.cpp
@@ -33,15 +33,17 @@ Register reg = ::as_Register(0); int i; for (i = 0; i < ConcreteRegisterImpl::max_gpr ; ) { - regName[i++] = reg->name(); - regName[i++] = reg->name(); + for (int j = 0 ; j < RegisterImpl::max_slots_per_register ; j++) { + regName[i++] = reg->name(); + } reg = reg->successor(); } FloatRegister freg = ::as_FloatRegister(0); for ( ; i < ConcreteRegisterImpl::max_fpr ; ) { - regName[i++] = freg->name(); - regName[i++] = freg->name(); + for (int j = 0 ; j < FloatRegisterImpl::max_slots_per_register ; j++) { + regName[i++] = freg->name(); + } freg = freg->successor(); }
diff --git a/src/hotspot/cpu/aarch64/vmreg_aarch64.hpp b/src/hotspot/cpu/aarch64/vmreg_aarch64.hpp index 0b1d000..c249c26 100644 --- a/src/hotspot/cpu/aarch64/vmreg_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vmreg_aarch64.hpp
@@ -38,13 +38,14 @@ assert( is_Register(), "must be"); // Yuk - return ::as_Register(value() >> 1); + return ::as_Register(value() / RegisterImpl::max_slots_per_register); } inline FloatRegister as_FloatRegister() { assert( is_FloatRegister() && is_even(value()), "must be" ); // Yuk - return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1); + return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) / + FloatRegisterImpl::max_slots_per_register); } inline bool is_concrete() {
diff --git a/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp b/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp index 145f979..c5d4383 100644 --- a/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp +++ b/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp
@@ -28,11 +28,12 @@ inline VMReg RegisterImpl::as_VMReg() { if( this==noreg ) return VMRegImpl::Bad(); - return VMRegImpl::as_VMReg(encoding() << 1 ); + return VMRegImpl::as_VMReg(encoding() * RegisterImpl::max_slots_per_register); } inline VMReg FloatRegisterImpl::as_VMReg() { - return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr); + return VMRegImpl::as_VMReg((encoding() * FloatRegisterImpl::max_slots_per_register) + + ConcreteRegisterImpl::max_gpr); } #endif // CPU_AARCH64_VM_VMREG_AARCH64_INLINE_HPP
diff --git a/src/hotspot/cpu/aarch64/vtableStubs_aarch64.cpp b/src/hotspot/cpu/aarch64/vtableStubs_aarch64.cpp index 9cb3ffa..4a2285b 100644 --- a/src/hotspot/cpu/aarch64/vtableStubs_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vtableStubs_aarch64.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2014, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * @@ -70,7 +70,7 @@ #if (!defined(PRODUCT) && defined(COMPILER2)) if (CountCompiledCalls) { __ lea(r16, ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr())); - __ incrementw(Address(r16)); + __ increment(Address(r16)); } #endif @@ -145,6 +145,7 @@ if (s == NULL) { return NULL; } + // Count unused bytes in instruction sequences of variable size. // We add them to the computed buffer size in order to avoid // overflow in subsequently generated stubs. @@ -159,7 +160,7 @@ #if (!defined(PRODUCT) && defined(COMPILER2)) if (CountCompiledCalls) { __ lea(r10, ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr())); - __ incrementw(Address(r10)); + __ increment(Address(r10)); } #endif @@ -170,11 +171,13 @@ // rscratch2: CompiledICHolder // j_rarg0: Receiver - // Most registers are in use; we'll use r16, rmethod, r10, r11 + // This stub is called from compiled code which has no callee-saved registers, + // so all registers except arguments are free at this point. const Register recv_klass_reg = r10; const Register holder_klass_reg = r16; // declaring interface klass (DECC) const Register resolved_klass_reg = rmethod; // resolved interface klass (REFC) const Register temp_reg = r11; + const Register temp_reg2 = r15; const Register icholder_reg = rscratch2; Label L_no_such_interface; @@ -189,11 +192,10 @@ __ load_klass(recv_klass_reg, j_rarg0); // Receiver subtype check against REFC. - // Destroys recv_klass_reg value. __ lookup_interface_method(// inputs: rec. class, interface recv_klass_reg, resolved_klass_reg, noreg, // outputs: scan temp. reg1, scan temp. reg2 - recv_klass_reg, temp_reg, + temp_reg2, temp_reg, L_no_such_interface, /*return_method=*/false); @@ -201,7 +203,6 @@ start_pc = __ pc(); // Get selected method from declaring class and itable index - __ load_klass(recv_klass_reg, j_rarg0); // restore recv_klass_reg __ lookup_interface_method(// inputs: rec. class, interface, itable index recv_klass_reg, holder_klass_reg, itable_index, // outputs: method, scan temp. reg @@ -211,7 +212,7 @@ const ptrdiff_t lookupSize = __ pc() - start_pc; // Reduce "estimate" such that "padding" does not drop below 8. - const ptrdiff_t estimate = 152; + const ptrdiff_t estimate = 124; const ptrdiff_t codesize = typecheckSize + lookupSize; slop_delta = (int)(estimate - codesize); slop_bytes += slop_delta;
diff --git a/src/hotspot/cpu/arm/arm.ad b/src/hotspot/cpu/arm/arm.ad index 7cc789f..fe89bb2 100644 --- a/src/hotspot/cpu/arm/arm.ad +++ b/src/hotspot/cpu/arm/arm.ad
@@ -212,7 +212,7 @@ // flds, fldd: 8-bit offset multiplied by 4: +/- 1024 // ldr, ldrb : 12-bit offset: +/- 4096 if (!Assembler::is_simm10(offset)) { - offset = Assembler::min_simm10(); + offset = Assembler::min_simm10; } return offset; #endif @@ -11966,15 +11966,16 @@ match(Halt); ins_cost(CALL_COST); - size(4); // Use the following format syntax format %{ "ShouldNotReachHere" %} ins_encode %{ + if (is_reachable()) { #ifdef AARCH64 - __ dpcs1(0xdead); + __ dpcs1(0xdead); #else - __ udf(0xdead); + __ udf(0xdead); #endif + } %} ins_pipe(tail_call); %} @@ -12015,9 +12016,10 @@ #ifdef AARCH64 effect(TEMP scratch, TEMP scratch2, TEMP scratch3); #else + predicate(!(UseBiasedLocking && !UseOptoBiasInlining)); effect(TEMP scratch, TEMP scratch2); #endif - ins_cost(100); + ins_cost(DEFAULT_COST*3); #ifdef AARCH64 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $scratch3" %} @@ -12047,6 +12049,21 @@ ins_pipe(long_memory_op); %} #else +instruct cmpFastLock_noBiasInline(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, + iRegP scratch, iRegP scratch3) %{ + match(Set pcc (FastLock object box)); + predicate(UseBiasedLocking && !UseOptoBiasInlining); + + effect(TEMP scratch, TEMP scratch2, TEMP scratch3); + ins_cost(DEFAULT_COST*5); + + format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $scratch3" %} + ins_encode %{ + __ fast_lock($object$$Register, $box$$Register, $scratch$$Register, $scratch2$$Register, $scratch3$$Register); + %} + ins_pipe(long_memory_op); +%} + instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, iRegP scratch ) %{ match(Set pcc (FastUnlock object box)); effect(TEMP scratch, TEMP scratch2);
diff --git a/src/hotspot/cpu/arm/assembler_arm_32.hpp b/src/hotspot/cpu/arm/assembler_arm_32.hpp index 53d6d17..afac7b4 100644 --- a/src/hotspot/cpu/arm/assembler_arm_32.hpp +++ b/src/hotspot/cpu/arm/assembler_arm_32.hpp
@@ -953,8 +953,8 @@ F(fldmia, 1, 1) F(fldmfd, 1, 1) F(fldmdb, 1, 2) F(fldmea, 1, 2) - F(fstmia, 0, 1) F(fstmfd, 0, 1) - F(fstmdb, 0, 2) F(fstmea, 0, 2) + F(fstmia, 0, 1) F(fstmea, 0, 1) + F(fstmdb, 0, 2) F(fstmfd, 0, 2) #undef F // fconst{s,d} encoding: @@ -1083,6 +1083,7 @@ break; default: ShouldNotReachHere(); + return; } emit_int32(0xf << 28 | 0x1 << 25 | 0x1 << 23 | 0x1 << 4 | (imm8 >> 7) << 24 | ((imm8 & 0x70) >> 4) << 16 | (imm8 & 0xf) | @@ -1113,6 +1114,7 @@ break; default: ShouldNotReachHere(); + return; } emit_int32(cond << 28 | 0x1D /* 0b11101 */ << 23 | 0xB /* 0b1011 */ << 8 | 0x1 << 4 | quad << 21 | b << 22 | e << 5 | Rs->encoding() << 12 | @@ -1143,6 +1145,7 @@ break; default: ShouldNotReachHere(); + return; } emit_int32(0xF /* 0b1111 */ << 28 | 0x3B /* 0b00111011 */ << 20 | 0x6 /* 0b110 */ << 9 | quad << 6 | imm4 << 16 |
diff --git a/src/hotspot/cpu/arm/c1_CodeStubs_arm.cpp b/src/hotspot/cpu/arm/c1_CodeStubs_arm.cpp index 4a2a093..b284035 100644 --- a/src/hotspot/cpu/arm/c1_CodeStubs_arm.cpp +++ b/src/hotspot/cpu/arm/c1_CodeStubs_arm.cpp
@@ -52,13 +52,13 @@ RangeCheckStub::RangeCheckStub(CodeEmitInfo* info, LIR_Opr index, LIR_Opr array) - : _throw_index_out_of_bounds_exception(false), _index(index), _array(array) { + : _index(index), _array(array), _throw_index_out_of_bounds_exception(false) { assert(info != NULL, "must have info"); _info = new CodeEmitInfo(info); } RangeCheckStub::RangeCheckStub(CodeEmitInfo* info, LIR_Opr index) - : _throw_index_out_of_bounds_exception(true), _index(index), _array(NULL) { + : _index(index), _array(NULL), _throw_index_out_of_bounds_exception(true) { assert(info != NULL, "must have info"); _info = new CodeEmitInfo(info); }
diff --git a/src/hotspot/cpu/arm/c1_FrameMap_arm.cpp b/src/hotspot/cpu/arm/c1_FrameMap_arm.cpp index 55b5fcc..11d0e07 100644 --- a/src/hotspot/cpu/arm/c1_FrameMap_arm.cpp +++ b/src/hotspot/cpu/arm/c1_FrameMap_arm.cpp
@@ -88,10 +88,12 @@ #else opr = as_long_opr(reg, r_2->as_Register()); #endif - } else if (type == T_OBJECT || type == T_ARRAY) { + } else if (is_reference_type(type)) { opr = as_oop_opr(reg); } else if (type == T_METADATA) { opr = as_metadata_opr(reg); + } else if (type == T_ADDRESS) { + opr = as_address_opr(reg); } else { // PreferInterpreterNativeStubs should ensure we never need to // handle a long opr passed as R3+stack_slot
diff --git a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp index f5b8dcb..6180516 100644 --- a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp +++ b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp
@@ -716,6 +716,7 @@ base_reg = Rtemp; __ str(from_lo, Address(Rtemp)); if (patch != NULL) { + __ nop(); // see comment before patching_epilog for 2nd str patching_epilog(patch, lir_patch_low, base_reg, info); patch = new PatchingStub(_masm, PatchingStub::access_field_id); patch_code = lir_patch_high; @@ -724,6 +725,7 @@ } else if (base_reg == from_lo) { __ str(from_hi, as_Address_hi(to_addr)); if (patch != NULL) { + __ nop(); // see comment before patching_epilog for 2nd str patching_epilog(patch, lir_patch_high, base_reg, info); patch = new PatchingStub(_masm, PatchingStub::access_field_id); patch_code = lir_patch_low; @@ -732,6 +734,7 @@ } else { __ str(from_lo, as_Address_lo(to_addr)); if (patch != NULL) { + __ nop(); // see comment before patching_epilog for 2nd str patching_epilog(patch, lir_patch_low, base_reg, info); patch = new PatchingStub(_masm, PatchingStub::access_field_id); patch_code = lir_patch_high; @@ -776,7 +779,7 @@ } if (patch != NULL) { - // Offset embeedded into LDR/STR instruction may appear not enough + // Offset embedded into LDR/STR instruction may appear not enough // to address a field. So, provide a space for one more instruction // that will deal with larger offsets. __ nop(); @@ -958,6 +961,7 @@ base_reg = Rtemp; __ ldr(to_lo, Address(Rtemp)); if (patch != NULL) { + __ nop(); // see comment before patching_epilog for 2nd ldr patching_epilog(patch, lir_patch_low, base_reg, info); patch = new PatchingStub(_masm, PatchingStub::access_field_id); patch_code = lir_patch_high; @@ -966,6 +970,7 @@ } else if (base_reg == to_lo) { __ ldr(to_hi, as_Address_hi(addr)); if (patch != NULL) { + __ nop(); // see comment before patching_epilog for 2nd ldr patching_epilog(patch, lir_patch_high, base_reg, info); patch = new PatchingStub(_masm, PatchingStub::access_field_id); patch_code = lir_patch_low; @@ -974,6 +979,7 @@ } else { __ ldr(to_lo, as_Address_lo(addr)); if (patch != NULL) { + __ nop(); // see comment before patching_epilog for 2nd ldr patching_epilog(patch, lir_patch_low, base_reg, info); patch = new PatchingStub(_masm, PatchingStub::access_field_id); patch_code = lir_patch_high; @@ -1014,7 +1020,7 @@ } if (patch != NULL) { - // Offset embeedded into LDR/STR instruction may appear not enough + // Offset embedded into LDR/STR instruction may appear not enough // to address a field. So, provide a space for one more instruction // that will deal with larger offsets. __ nop(); @@ -2355,6 +2361,11 @@ assert(opr2->as_constant_ptr()->as_jobject() == NULL, "cannot handle otherwise"); __ cmp(opr1->as_register(), 0); break; + case T_METADATA: + assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "Only equality tests"); + assert(opr2->as_constant_ptr()->as_metadata() == NULL, "cannot handle otherwise"); + __ cmp(opr1->as_register(), 0); + break; default: ShouldNotReachHere(); } @@ -3086,7 +3097,7 @@ Label ok; if (op->condition() != lir_cond_always) { - AsmCondition acond; + AsmCondition acond = al; switch (op->condition()) { case lir_cond_equal: acond = eq; break; case lir_cond_notEqual: acond = ne; break;
diff --git a/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp b/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp index 342c1c3..b05fc87 100644 --- a/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp +++ b/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp
@@ -436,7 +436,7 @@ } -bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) { +bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { assert(left != result, "should be different registers"); if (is_power_of_2(c + 1)) { #ifdef AARCH64 @@ -733,6 +733,7 @@ default: ShouldNotReachHere(); + return; } #else switch (x->op()) { @@ -757,6 +758,7 @@ break; default: ShouldNotReachHere(); + return; } LIR_Opr result = call_runtime(x->y(), x->x(), entry, x->type(), NULL); set_result(x, result); @@ -824,7 +826,7 @@ if (x->op() == Bytecodes::_irem) { out_reg = FrameMap::R0_opr; __ irem(left_arg->result(), right_arg->result(), out_reg, tmp, info); - } else if (x->op() == Bytecodes::_idiv) { + } else { // (x->op() == Bytecodes::_idiv) out_reg = FrameMap::R1_opr; __ idiv(left_arg->result(), right_arg->result(), out_reg, tmp, info); }
diff --git a/src/hotspot/cpu/arm/c1_MacroAssembler_arm.cpp b/src/hotspot/cpu/arm/c1_MacroAssembler_arm.cpp index bc60571..facfbdd 100644 --- a/src/hotspot/cpu/arm/c1_MacroAssembler_arm.cpp +++ b/src/hotspot/cpu/arm/c1_MacroAssembler_arm.cpp
@@ -323,8 +323,9 @@ // -2- test (hdr - SP) if the low two bits are 0 sub(tmp2, hdr, SP, eq); movs(tmp2, AsmOperand(tmp2, lsr, exact_log2(os::vm_page_size())), eq); - // If 'eq' then OK for recursive fast locking: store 0 into a lock record. - str(tmp2, Address(disp_hdr, mark_offset), eq); + // If still 'eq' then recursive locking OK + // set to zero if recursive lock, set to non zero otherwise (see discussion in JDK-8267042) + str(tmp2, Address(disp_hdr, mark_offset)); b(fast_lock_done, eq); // else need slow case b(slow_case);
diff --git a/src/hotspot/cpu/arm/c1_Runtime1_arm.cpp b/src/hotspot/cpu/arm/c1_Runtime1_arm.cpp index 5828647..b44ab31 100644 --- a/src/hotspot/cpu/arm/c1_Runtime1_arm.cpp +++ b/src/hotspot/cpu/arm/c1_Runtime1_arm.cpp
@@ -270,7 +270,7 @@ __ push(RegisterSet(FP) | RegisterSet(LR)); __ push(RegisterSet(R0, R6) | RegisterSet(R8, R10) | R12 | altFP_7_11); if (save_fpu_registers) { - __ fstmdbd(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback); + __ fpush(FloatRegisterSet(D0, fpu_save_size / 2)); } else { __ sub(SP, SP, fpu_save_size * wordSize); } @@ -316,7 +316,7 @@ } #else if (restore_fpu_registers) { - __ fldmiad(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback); + __ fpop(FloatRegisterSet(D0, fpu_save_size / 2)); if (!restore_R0) { __ add(SP, SP, (R1_offset - fpu_save_size) * wordSize); }
diff --git a/src/hotspot/cpu/arm/c2_globals_arm.hpp b/src/hotspot/cpu/arm/c2_globals_arm.hpp index 2c09196..9e19c53 100644 --- a/src/hotspot/cpu/arm/c2_globals_arm.hpp +++ b/src/hotspot/cpu/arm/c2_globals_arm.hpp
@@ -109,7 +109,7 @@ // Ergonomics related flags define_pd_global(uint64_t, MaxRAM, 4ULL*G); #endif -define_pd_global(uintx, CodeCacheMinBlockLength, 4); +define_pd_global(uintx, CodeCacheMinBlockLength, 6); define_pd_global(size_t, CodeCacheMinimumUseSpace, 400*K); define_pd_global(bool, TrapBasedRangeChecks, false); // Not needed
diff --git a/src/hotspot/cpu/arm/frame_arm.cpp b/src/hotspot/cpu/arm/frame_arm.cpp index ae40ec8..7b3515e 100644 --- a/src/hotspot/cpu/arm/frame_arm.cpp +++ b/src/hotspot/cpu/arm/frame_arm.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -500,7 +500,7 @@ Method* m = *interpreter_frame_method_addr(); // validate the method we'd find in this potential sender - if (!m->is_valid_method()) return false; + if (!Method::is_valid_method(m)) return false; // stack frames shouldn't be much larger than max_stack elements @@ -517,7 +517,7 @@ // validate ConstantPoolCache* ConstantPoolCache* cp = *interpreter_frame_cache_addr(); - if (cp == NULL || !cp->is_metaspace_object()) return false; + if (MetaspaceObj::is_valid(cp) == false) return false; // validate locals
diff --git a/src/hotspot/cpu/arm/globalDefinitions_arm.hpp b/src/hotspot/cpu/arm/globalDefinitions_arm.hpp index 0ede3bf..29a856d 100644 --- a/src/hotspot/cpu/arm/globalDefinitions_arm.hpp +++ b/src/hotspot/cpu/arm/globalDefinitions_arm.hpp
@@ -69,11 +69,4 @@ #endif #define C1_LIRGENERATOR_MD_HPP "c1_LIRGenerator_arm.hpp" -#ifdef TARGET_COMPILER_gcc -#ifdef ARM32 -#undef BREAKPOINT -#define BREAKPOINT __asm__ volatile ("bkpt") -#endif -#endif - #endif // CPU_ARM_VM_GLOBALDEFINITIONS_ARM_HPP
diff --git a/src/hotspot/cpu/arm/globals_arm.hpp b/src/hotspot/cpu/arm/globals_arm.hpp index eadb841..fd044da 100644 --- a/src/hotspot/cpu/arm/globals_arm.hpp +++ b/src/hotspot/cpu/arm/globals_arm.hpp
@@ -30,8 +30,6 @@ // (see globals.hpp) // -define_pd_global(bool, ShareVtableStubs, true); - define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks define_pd_global(bool, UncommonNullCast, true); // Uncommon-trap NULLs past to check cast define_pd_global(bool, TrapBasedNullChecks, false); // Not needed
diff --git a/src/hotspot/cpu/arm/interpreterRT_arm.cpp b/src/hotspot/cpu/arm/interpreterRT_arm.cpp index 47c0227..a3eb57e 100644 --- a/src/hotspot/cpu/arm/interpreterRT_arm.cpp +++ b/src/hotspot/cpu/arm/interpreterRT_arm.cpp
@@ -86,11 +86,12 @@ // For ARM, the fast signature handler only needs to know whether // the return value must be unboxed. T_OBJECT and T_ARRAY need not // be distinguished from each other and all other return values - // behave like integers with respect to the handler. + // behave like integers with respect to the handler except T_BOOLEAN + // which must be mapped to the range 0..1. bool unbox = (ret_type == T_OBJECT) || (ret_type == T_ARRAY); if (unbox) { ret_type = T_OBJECT; - } else { + } else if (ret_type != T_BOOLEAN) { ret_type = T_INT; } result |= ((uint64_t) ret_type) << shift; @@ -281,14 +282,7 @@ address result_handler = Interpreter::result_handler(result_type); -#ifdef AARCH64 - __ mov_slow(R0, (address)result_handler); -#else - // Check that result handlers are not real handler on ARM (0 or -1). - // This ensures the signature handlers do not need symbolic information. - assert((result_handler == NULL)||(result_handler==(address)0xffffffff),""); __ mov_slow(R0, (intptr_t)result_handler); -#endif __ ret(); }
diff --git a/src/hotspot/cpu/arm/macroAssembler_arm.cpp b/src/hotspot/cpu/arm/macroAssembler_arm.cpp index a673251..9e22fd1 100644 --- a/src/hotspot/cpu/arm/macroAssembler_arm.cpp +++ b/src/hotspot/cpu/arm/macroAssembler_arm.cpp
@@ -1229,6 +1229,15 @@ bind(done); } +void MacroAssembler::c2bool(Register x) { + tst(x, 0xff); // Only look at the lowest byte +#ifdef AARCH64 + cset(x, ne); +#else + mov(x, 1, ne); +#endif +} + void MacroAssembler::null_check(Register reg, Register tmp, int offset) { if (needs_explicit_null_check(offset)) { #ifdef AARCH64 @@ -2987,7 +2996,7 @@ #endif // AARCH64 #ifdef COMPILER2 -void MacroAssembler::fast_lock(Register Roop, Register Rbox, Register Rscratch, Register Rscratch2 AARCH64_ONLY_ARG(Register Rscratch3)) +void MacroAssembler::fast_lock(Register Roop, Register Rbox, Register Rscratch, Register Rscratch2, Register scratch3) { assert(VM_Version::supports_ldrex(), "unsupported, yet?"); @@ -3001,15 +3010,13 @@ Label fast_lock, done; if (UseBiasedLocking && !UseOptoBiasInlining) { - Label failed; -#ifdef AARCH64 - biased_locking_enter(Roop, Rmark, Rscratch, false, Rscratch3, done, failed); -#else - biased_locking_enter(Roop, Rmark, Rscratch, false, noreg, done, failed); -#endif - bind(failed); + assert(scratch3 != noreg, "need extra temporary for -XX:-UseOptoBiasInlining"); + biased_locking_enter(Roop, Rmark, Rscratch, false, scratch3, done, done); + // Fall through if lock not biased otherwise branch to done } + // Invariant: Rmark loaded below does not contain biased lock pattern + ldr(Rmark, Address(Roop, oopDesc::mark_offset_in_bytes())); tst(Rmark, markOopDesc::unlocked_value); b(fast_lock, ne); @@ -3048,6 +3055,9 @@ bind(done); + // At this point flags are set as follows: + // EQ -> Success + // NE -> Failure, branch to slow path } void MacroAssembler::fast_unlock(Register Roop, Register Rbox, Register Rscratch, Register Rscratch2 AARCH64_ONLY_ARG(Register Rscratch3))
diff --git a/src/hotspot/cpu/arm/macroAssembler_arm.hpp b/src/hotspot/cpu/arm/macroAssembler_arm.hpp index 43977e8..9337f95 100644 --- a/src/hotspot/cpu/arm/macroAssembler_arm.hpp +++ b/src/hotspot/cpu/arm/macroAssembler_arm.hpp
@@ -376,10 +376,10 @@ // lock_reg and obj_reg must be loaded up with the appropriate values. // swap_reg must be supplied. // tmp_reg must be supplied. - // Optional slow case is for implementations (interpreter and C1) which branch to - // slow case directly. If slow_case is NULL, then leaves condition - // codes set (for C2's Fast_Lock node) and jumps to done label. - // Falls through for the fast locking attempt. + // Done label is branched to with condition code EQ set if the lock is + // biased and we acquired it. Slow case label is branched to with + // condition code NE set if the lock is biased but we failed to acquire + // it. Otherwise fall through. // Returns offset of first potentially-faulting instruction for null // check info (currently consumed only by C1). If // swap_reg_contains_mark is true then returns -1 as it is assumed @@ -443,6 +443,26 @@ } #endif // !AARCH64 + void fpush(FloatRegisterSet reg_set) { + fstmdbd(SP, reg_set, writeback); + } + + void fpop(FloatRegisterSet reg_set) { + fldmiad(SP, reg_set, writeback); + } + + void fpush_hardfp(FloatRegisterSet reg_set) { +#ifndef __SOFTFP__ + fpush(reg_set); +#endif + } + + void fpop_hardfp(FloatRegisterSet reg_set) { +#ifndef __SOFTFP__ + fpop(reg_set); +#endif + } + // Order access primitives enum Membar_mask_bits { StoreStore = 1 << 3, @@ -1034,6 +1054,8 @@ #endif } + // C 'boolean' to Java boolean: x == 0 ? 0 : 1 + void c2bool(Register x); // klass oop manipulations if compressed @@ -1326,12 +1348,11 @@ void restore_default_fp_mode(); #ifdef COMPILER2 -#ifdef AARCH64 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file. - void fast_lock(Register obj, Register box, Register scratch, Register scratch2, Register scratch3); + void fast_lock(Register obj, Register box, Register scratch, Register scratch2, Register scratch3 = noreg); +#ifdef AARCH64 void fast_unlock(Register obj, Register box, Register scratch, Register scratch2, Register scratch3); #else - void fast_lock(Register obj, Register box, Register scratch, Register scratch2); void fast_unlock(Register obj, Register box, Register scratch, Register scratch2); #endif #endif
diff --git a/src/hotspot/cpu/arm/nativeInst_arm_32.hpp b/src/hotspot/cpu/arm/nativeInst_arm_32.hpp index a174116..8842f90 100644 --- a/src/hotspot/cpu/arm/nativeInst_arm_32.hpp +++ b/src/hotspot/cpu/arm/nativeInst_arm_32.hpp
@@ -348,6 +348,11 @@ // (field access patching is handled differently in that case) class NativeMovRegMem: public NativeInstruction { public: + enum arm_specific_constants { + instruction_size = 8 + }; + + int num_bytes_to_end_of_patch() const { return instruction_size; } int offset() const; void set_offset(int x);
diff --git a/src/hotspot/cpu/arm/register_arm.hpp b/src/hotspot/cpu/arm/register_arm.hpp index 87ea7f5..bdaa138 100644 --- a/src/hotspot/cpu/arm/register_arm.hpp +++ b/src/hotspot/cpu/arm/register_arm.hpp
@@ -26,7 +26,7 @@ #define CPU_ARM_VM_REGISTER_ARM_HPP #include "asm/register.hpp" -#include "vm_version_arm.hpp" +#include "runtime/vm_version.hpp" class VMRegImpl; typedef VMRegImpl* VMReg;
diff --git a/src/hotspot/cpu/arm/sharedRuntime_arm.cpp b/src/hotspot/cpu/arm/sharedRuntime_arm.cpp index 7922682..25366a8 100644 --- a/src/hotspot/cpu/arm/sharedRuntime_arm.cpp +++ b/src/hotspot/cpu/arm/sharedRuntime_arm.cpp
@@ -217,14 +217,14 @@ __ push(SAVED_BASE_REGS); if (HaveVFP) { if (VM_Version::has_vfp3_32()) { - __ fstmdbd(SP, FloatRegisterSet(D16, 16), writeback); + __ fpush(FloatRegisterSet(D16, 16)); } else { if (FloatRegisterImpl::number_of_registers > 32) { assert(FloatRegisterImpl::number_of_registers == 64, "nb fp registers should be 64"); __ sub(SP, SP, 32 * wordSize); } } - __ fstmdbd(SP, FloatRegisterSet(D0, 16), writeback); + __ fpush(FloatRegisterSet(D0, 16)); } else { __ sub(SP, SP, fpu_save_size * wordSize); } @@ -285,9 +285,9 @@ } #else if (HaveVFP) { - __ fldmiad(SP, FloatRegisterSet(D0, 16), writeback); + __ fpop(FloatRegisterSet(D0, 16)); if (VM_Version::has_vfp3_32()) { - __ fldmiad(SP, FloatRegisterSet(D16, 16), writeback); + __ fpop(FloatRegisterSet(D16, 16)); } else { if (FloatRegisterImpl::number_of_registers > 32) { assert(FloatRegisterImpl::number_of_registers == 64, "nb fp registers should be 64"); @@ -382,26 +382,21 @@ // R1-R3 arguments need to be saved, but we push 4 registers for 8-byte alignment __ push(RegisterSet(R0, R3)); -#ifdef __ABI_HARD__ // preserve arguments // Likely not needed as the locking code won't probably modify volatile FP registers, // but there is no way to guarantee that if (fp_regs_in_arguments) { // convert fp_regs_in_arguments to a number of double registers int double_regs_num = (fp_regs_in_arguments + 1) >> 1; - __ fstmdbd(SP, FloatRegisterSet(D0, double_regs_num), writeback); + __ fpush_hardfp(FloatRegisterSet(D0, double_regs_num)); } -#endif // __ ABI_HARD__ } static void pop_param_registers(MacroAssembler* masm, int fp_regs_in_arguments) { -#ifdef __ABI_HARD__ if (fp_regs_in_arguments) { int double_regs_num = (fp_regs_in_arguments + 1) >> 1; - __ fldmiad(SP, FloatRegisterSet(D0, double_regs_num), writeback); + __ fpop_hardfp(FloatRegisterSet(D0, double_regs_num)); } -#endif // __ABI_HARD__ - __ pop(RegisterSet(R0, R3)); } @@ -701,6 +696,7 @@ // Pushing an even number of registers for stack alignment. // Selecting R9, which had to be saved anyway for some platforms. __ push(RegisterSet(R0, R3) | R9 | LR); + __ fpush_hardfp(FloatRegisterSet(D0, 8)); #endif // AARCH64 __ mov(R0, Rmethod); @@ -711,6 +707,7 @@ __ raw_pop(LR, ZR); pop_param_registers(masm, FPR_PARAMS); #else + __ fpop_hardfp(FloatRegisterSet(D0, 8)); __ pop(RegisterSet(R0, R3) | R9 | LR); #endif // AARCH64 @@ -1111,7 +1108,8 @@ int compile_id, BasicType* in_sig_bt, VMRegPair* in_regs, - BasicType ret_type) { + BasicType ret_type, + address critical_entry) { if (method->is_method_handle_intrinsic()) { vmIntrinsics::ID iid = method->intrinsic_id(); intptr_t start = (intptr_t)__ pc(); @@ -1624,8 +1622,9 @@ // -2- test (hdr - SP) if the low two bits are 0 __ sub(Rtemp, mark, SP, eq); __ movs(Rtemp, AsmOperand(Rtemp, lsr, exact_log2(os::vm_page_size())), eq); - // If still 'eq' then recursive locking OK: set displaced header to 0 - __ str(Rtemp, Address(disp_hdr, BasicLock::displaced_header_offset_in_bytes()), eq); + // If still 'eq' then recursive locking OK + // set to zero if recursive lock, set to non zero otherwise (see discussion in JDK-8267042) + __ str(Rtemp, Address(disp_hdr, BasicLock::displaced_header_offset_in_bytes())); __ b(lock_done, eq); __ b(slow_lock); @@ -1659,6 +1658,11 @@ __ restore_default_fp_mode(); } + // Ensure a Boolean result is mapped to 0..1 + if (ret_type == T_BOOLEAN) { + __ c2bool(R0); + } + // Do a safepoint check while thread is in transition state InlinedAddress safepoint_state(SafepointSynchronize::address_of_state()); Label call_safepoint_runtime, return_to_java; @@ -2115,9 +2119,9 @@ __ mov(R0, Rthread); __ mov(R1, Rkind); - pc_offset = __ set_last_Java_frame(SP, FP, false, Rtemp); + pc_offset = __ set_last_Java_frame(SP, FP, true, Rtemp); assert(((__ pc()) - start) == __ offset(), "warning: start differs from code_begin"); - __ call(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)); + __ call_VM_leaf(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)); if (pc_offset == -1) { pc_offset = __ offset(); } @@ -2332,8 +2336,8 @@ // Call unpack_frames with proper arguments __ mov(R0, Rthread); __ mov(R1, Deoptimization::Unpack_uncommon_trap); - __ set_last_Java_frame(SP, FP, false, Rtemp); - __ call(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)); + __ set_last_Java_frame(SP, FP, true, Rtemp); + __ call_VM_leaf(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)); // oop_maps->add_gc_map(__ pc() - start, new OopMap(frame_size_in_words, 0)); __ reset_last_Java_frame(Rtemp);
diff --git a/src/hotspot/cpu/arm/stubGenerator_arm.cpp b/src/hotspot/cpu/arm/stubGenerator_arm.cpp index bcd6699..67d9fbc 100644 --- a/src/hotspot/cpu/arm/stubGenerator_arm.cpp +++ b/src/hotspot/cpu/arm/stubGenerator_arm.cpp
@@ -289,9 +289,7 @@ __ mov(Rtemp, SP); __ push(RegisterSet(FP) | RegisterSet(LR)); -#ifndef __SOFTFP__ - __ fstmdbd(SP, FloatRegisterSet(D8, 8), writeback); -#endif + __ fpush_hardfp(FloatRegisterSet(D8, 8)); __ stmdb(SP, RegisterSet(R0, R2) | RegisterSet(R4, R6) | RegisterSet(R8, R10) | altFP_7_11, writeback); __ mov(Rmethod, R3); __ ldmia(Rtemp, RegisterSet(R1, R3) | Rthread); // stacked arguments @@ -353,9 +351,7 @@ #endif __ pop(RegisterSet(R4, R6) | RegisterSet(R8, R10) | altFP_7_11); -#ifndef __SOFTFP__ - __ fldmiad(SP, FloatRegisterSet(D8, 8), writeback); -#endif + __ fpop_hardfp(FloatRegisterSet(D8, 8)); __ pop(RegisterSet(FP) | RegisterSet(PC)); #endif // AARCH64
diff --git a/src/hotspot/cpu/arm/stubRoutinesCrypto_arm.cpp b/src/hotspot/cpu/arm/stubRoutinesCrypto_arm.cpp index c82fa6c..b4e58e8 100644 --- a/src/hotspot/cpu/arm/stubRoutinesCrypto_arm.cpp +++ b/src/hotspot/cpu/arm/stubRoutinesCrypto_arm.cpp
@@ -129,7 +129,7 @@ // Register tbox = R3; // transposition box reference __ push (RegisterSet(R4, R12) | LR); - __ fstmdbd(SP, FloatRegisterSet(D0, 4), writeback); + __ fpush(FloatRegisterSet(D0, 4)); __ sub(SP, SP, 32); // preserve TBox references @@ -308,7 +308,7 @@ __ str(R0, Address(R9)); __ add(SP, SP, 32); - __ fldmiad(SP, FloatRegisterSet(D0, 4), writeback);; + __ fpop(FloatRegisterSet(D0, 4)); __ pop(RegisterSet(R4, R12) | PC); return start; @@ -326,7 +326,7 @@ // Register tbox = R3; // transposition box reference __ push (RegisterSet(R4, R12) | LR); - __ fstmdbd(SP, FloatRegisterSet(D0, 4), writeback); + __ fpush(FloatRegisterSet(D0, 4)); __ sub(SP, SP, 32); // retrieve key length @@ -521,7 +521,7 @@ __ str(R0, Address(R9)); __ add(SP, SP, 32); - __ fldmiad(SP, FloatRegisterSet(D0, 4), writeback);; + __ fpop(FloatRegisterSet(D0, 4)); __ pop(RegisterSet(R4, R12) | PC); return start; @@ -680,7 +680,7 @@ Label decrypt_8_blocks; int quad = 1; // Process 8 blocks in parallel - __ fstmdbd(SP, FloatRegisterSet(D8, 8), writeback); + __ fpush(FloatRegisterSet(D8, 8)); __ sub(SP, SP, 40); // record output buffer end address (used as a block counter) @@ -1020,7 +1020,7 @@ __ b(decrypt_8_blocks, ne); __ add(SP, SP, 40); - __ fldmiad(SP, FloatRegisterSet(D8, 8), writeback);; + __ fpop(FloatRegisterSet(D8, 8)); } __ bind(cbc_done);
diff --git a/src/hotspot/cpu/arm/templateInterpreterGenerator_arm.cpp b/src/hotspot/cpu/arm/templateInterpreterGenerator_arm.cpp index 8dcfe28..c96f4ea 100644 --- a/src/hotspot/cpu/arm/templateInterpreterGenerator_arm.cpp +++ b/src/hotspot/cpu/arm/templateInterpreterGenerator_arm.cpp
@@ -351,16 +351,12 @@ } address TemplateInterpreterGenerator::generate_result_handler_for(BasicType type) { -#ifdef AARCH64 address entry = __ pc(); switch (type) { - case T_BOOLEAN: - __ tst(R0, 0xff); - __ cset(R0, ne); - break; - case T_CHAR : __ zero_extend(R0, R0, 16); break; - case T_BYTE : __ sign_extend(R0, R0, 8); break; - case T_SHORT : __ sign_extend(R0, R0, 16); break; + case T_BOOLEAN: __ c2bool(R0); break; + case T_CHAR : AARCH64_ONLY(__ zero_extend(R0, R0, 16);) break; + case T_BYTE : AARCH64_ONLY(__ sign_extend(R0, R0, 8);) break; + case T_SHORT : AARCH64_ONLY(__ sign_extend(R0, R0, 16);) break; case T_INT : // fall through case T_LONG : // fall through case T_VOID : // fall through @@ -372,19 +368,10 @@ // and verify it __ verify_oop(R0); break; - default : ShouldNotReachHere(); + default : __ should_not_reach_here(); break; } __ ret(); return entry; -#else - // Result handlers are not used on 32-bit ARM - // since the returned value is already in appropriate format. - __ should_not_reach_here(); // to avoid empty code block - - // The result handler non-zero indicates an object is returned and this is - // used in the native entry code. - return type == T_OBJECT ? (address)(-1) : NULL; -#endif // AARCH64 } address TemplateInterpreterGenerator::generate_safept_entry_for(TosState state, address runtime_entry) { @@ -1216,14 +1203,9 @@ // Unbox oop result, e.g. JNIHandles::resolve result if it's an oop. { Label Lnot_oop; -#ifdef AARCH64 __ mov_slow(Rtemp, AbstractInterpreter::result_handler(T_OBJECT)); __ cmp(Rresult_handler, Rtemp); __ b(Lnot_oop, ne); -#else // !AARCH64 - // For ARM32, Rresult_handler is -1 for oop result, 0 otherwise. - __ cbz(Rresult_handler, Lnot_oop); -#endif // !AARCH64 Register value = AARCH64_ONLY(Rsaved_result) NOT_AARCH64(Rsaved_result_lo); __ resolve_jobject(value, // value Rtemp, // tmp1 @@ -1296,25 +1278,14 @@ __ blr(Rresult_handler); #else - __ cmp(Rresult_handler, 0); - __ ldr(R0, Address(FP, frame::interpreter_frame_oop_temp_offset * wordSize), ne); - __ mov(R0, Rsaved_result_lo, eq); + __ mov(R0, Rsaved_result_lo); __ mov(R1, Rsaved_result_hi); #ifdef __ABI_HARD__ // reload native FP result __ fcpyd(D0, D8); #endif // __ABI_HARD__ - -#ifdef ASSERT - if (VerifyOops) { - Label L; - __ cmp(Rresult_handler, 0); - __ b(L, eq); - __ verify_oop(R0); - __ bind(L); - } -#endif // ASSERT + __ blx(Rresult_handler); #endif // AARCH64 // Restore FP/LR, sender_sp and return
diff --git a/src/hotspot/cpu/arm/templateTable_arm.cpp b/src/hotspot/cpu/arm/templateTable_arm.cpp index 13726c3..3adf9fb 100644 --- a/src/hotspot/cpu/arm/templateTable_arm.cpp +++ b/src/hotspot/cpu/arm/templateTable_arm.cpp
@@ -527,19 +527,20 @@ __ add(Rbase, Rcpool, AsmOperand(Rindex, lsl, LogBytesPerWord)); - Label Condy, exit; -#ifdef __ABI_HARD__ - Label Long; // get type from tags __ add(Rtemp, Rtags, tags_offset); __ ldrb(Rtemp, Address(Rtemp, Rindex)); + + Label Condy, exit; +#ifdef __ABI_HARD__ + Label NotDouble; __ cmp(Rtemp, JVM_CONSTANT_Double); - __ b(Long, ne); + __ b(NotDouble, ne); __ ldr_double(D0_tos, Address(Rbase, base_offset)); __ push(dtos); __ b(exit); - __ bind(Long); + __ bind(NotDouble); #endif __ cmp(Rtemp, JVM_CONSTANT_Long); @@ -2373,7 +2374,7 @@ const Address mask(Rcounters, in_bytes(MethodCounters::backedge_mask_offset())); __ increment_mask_and_jump(Address(Rcounters, be_offset), increment, mask, Rcnt, R4_tmp, eq, &backedge_counter_overflow); - } else { + } else { // not TieredCompilation // Increment backedge counter in MethodCounters* __ get_method_counters(Rmethod, Rcounters, dispatch, true /*saveRegs*/, Rdisp, R3_bytecode, @@ -2446,7 +2447,7 @@ __ dispatch_only(vtos); if (UseLoopCounter) { - if (ProfileInterpreter) { + if (ProfileInterpreter && !TieredCompilation) { // Out-of-line code to allocate method data oop. __ bind(profile_method);
diff --git a/src/hotspot/cpu/arm/vm_version_arm.hpp b/src/hotspot/cpu/arm/vm_version_arm.hpp index e2770f0..3659682 100644 --- a/src/hotspot/cpu/arm/vm_version_arm.hpp +++ b/src/hotspot/cpu/arm/vm_version_arm.hpp
@@ -25,8 +25,8 @@ #ifndef CPU_ARM_VM_VM_VERSION_ARM_HPP #define CPU_ARM_VM_VM_VERSION_ARM_HPP +#include "runtime/abstract_vm_version.hpp" #include "runtime/globals_extension.hpp" -#include "runtime/vm_version.hpp" class VM_Version: public Abstract_VM_Version { friend class JVMCIVMStructs;
diff --git a/src/hotspot/cpu/arm/vm_version_arm_32.cpp b/src/hotspot/cpu/arm/vm_version_arm_32.cpp index df0fb2e..4e58162 100644 --- a/src/hotspot/cpu/arm/vm_version_arm_32.cpp +++ b/src/hotspot/cpu/arm/vm_version_arm_32.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -29,7 +29,7 @@ #include "runtime/java.hpp" #include "runtime/os.inline.hpp" #include "runtime/stubCodeGenerator.hpp" -#include "vm_version_arm.hpp" +#include "runtime/vm_version.hpp" int VM_Version::_stored_pc_adjustment = 4; int VM_Version::_arm_arch = 5; @@ -260,6 +260,8 @@ if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { FLAG_SET_DEFAULT(UsePopCountInstruction, true); } + } else { + FLAG_SET_DEFAULT(UsePopCountInstruction, false); } if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { @@ -294,6 +296,9 @@ Tier3MinInvocationThreshold = 500; } + UNSUPPORTED_OPTION(TypeProfileLevel); + UNSUPPORTED_OPTION(CriticalJNINatives); + FLAG_SET_DEFAULT(TypeProfileLevel, 0); // unsupported // This machine does not allow unaligned memory accesses
diff --git a/src/hotspot/cpu/arm/vm_version_ext_arm.hpp b/src/hotspot/cpu/arm/vm_version_ext_arm.hpp index 4502a1a..2819076 100644 --- a/src/hotspot/cpu/arm/vm_version_ext_arm.hpp +++ b/src/hotspot/cpu/arm/vm_version_ext_arm.hpp
@@ -25,8 +25,8 @@ #ifndef CPU_ARM_VM_VM_VERSION_EXT_ARM_HPP #define CPU_ARM_VM_VM_VERSION_EXT_ARM_HPP +#include "runtime/vm_version.hpp" #include "utilities/macros.hpp" -#include "vm_version_arm.hpp" class VM_Version_Ext : public VM_Version { private:
diff --git a/src/hotspot/cpu/ppc/assembler_ppc.hpp b/src/hotspot/cpu/ppc/assembler_ppc.hpp index 4e0b75f..8839392 100644 --- a/src/hotspot/cpu/ppc/assembler_ppc.hpp +++ b/src/hotspot/cpu/ppc/assembler_ppc.hpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2002, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2018 SAP SE. All rights reserved. + * Copyright (c) 2002, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2020 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -436,6 +436,10 @@ NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM + // Byte reverse opcodes (introduced with Power10) + BRH_OPCODE = (31u << OPCODE_SHIFT | 219u << 1), // X-FORM + BRW_OPCODE = (31u << OPCODE_SHIFT | 155u << 1), // X-FORM + BRD_OPCODE = (31u << OPCODE_SHIFT | 187u << 1), // X-FORM // opcodes only used for floating arithmetic FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1), @@ -1532,6 +1536,11 @@ // testbit with condition register inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6); + // Byte reverse instructions (introduced with Power10) + inline void brh( Register a, Register s); + inline void brw( Register a, Register s); + inline void brd( Register a, Register s); + // rotate instructions inline void rotldi( Register a, Register s, int n); inline void rotrdi( Register a, Register s, int n);
diff --git a/src/hotspot/cpu/ppc/assembler_ppc.inline.hpp b/src/hotspot/cpu/ppc/assembler_ppc.inline.hpp index d790899..b7575a9 100644 --- a/src/hotspot/cpu/ppc/assembler_ppc.inline.hpp +++ b/src/hotspot/cpu/ppc/assembler_ppc.inline.hpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2002, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2018 SAP SE. All rights reserved. + * Copyright (c) 2002, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2020 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -287,6 +287,11 @@ } } +// Byte reverse instructions (introduced with Power10) +inline void Assembler::brh(Register a, Register s) { emit_int32(BRH_OPCODE | rta(a) | rs(s)); } +inline void Assembler::brw(Register a, Register s) { emit_int32(BRW_OPCODE | rta(a) | rs(s)); } +inline void Assembler::brd(Register a, Register s) { emit_int32(BRD_OPCODE | rta(a) | rs(s)); } + // rotate instructions inline void Assembler::rotldi( Register a, Register s, int n) { Assembler::rldicl(a, s, n, 0); } inline void Assembler::rotrdi( Register a, Register s, int n) { Assembler::rldicl(a, s, 64-n, 0); }
diff --git a/src/hotspot/cpu/ppc/c1_FrameMap_ppc.cpp b/src/hotspot/cpu/ppc/c1_FrameMap_ppc.cpp index 5a50b96..6ea3092 100644 --- a/src/hotspot/cpu/ppc/c1_FrameMap_ppc.cpp +++ b/src/hotspot/cpu/ppc/c1_FrameMap_ppc.cpp
@@ -54,6 +54,10 @@ opr = as_long_opr(reg); } else if (type == T_OBJECT || type == T_ARRAY) { opr = as_oop_opr(reg); + } else if (type == T_METADATA) { + opr = as_metadata_opr(reg); + } else if (type == T_ADDRESS) { + opr = as_address_opr(reg); } else { opr = as_opr(reg); }
diff --git a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp index e83f027..847f7d6 100644 --- a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp +++ b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
@@ -1450,6 +1450,19 @@ } break; + case T_METADATA: + // We only need, for now, comparison with NULL for metadata. + { + assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); + Metadata* p = opr2->as_constant_ptr()->as_metadata(); + if (p == NULL) { + __ cmpdi(BOOL_RESULT, opr1->as_register(), 0); + } else { + ShouldNotReachHere(); + } + } + break; + default: ShouldNotReachHere(); break;
diff --git a/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp index cd2d427..d34ea45 100644 --- a/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp +++ b/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp
@@ -289,7 +289,7 @@ } -bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) { +bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { assert(left != result, "should be different registers"); if (is_power_of_2(c + 1)) { __ shift_left(left, log2_int(c + 1), result);
diff --git a/src/hotspot/cpu/ppc/c1_globals_ppc.hpp b/src/hotspot/cpu/ppc/c1_globals_ppc.hpp index 66f6f91..963b92c 100644 --- a/src/hotspot/cpu/ppc/c1_globals_ppc.hpp +++ b/src/hotspot/cpu/ppc/c1_globals_ppc.hpp
@@ -1,6 +1,6 @@ /* * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2018 SAP SE. All rights reserved. + * Copyright (c) 2012, 2019 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -48,8 +48,12 @@ define_pd_global(intx, FreqInlineSize, 325 ); define_pd_global(bool, ResizeTLAB, true); define_pd_global(uintx, ReservedCodeCacheSize, 32*M); +define_pd_global(uintx, NonProfiledCodeHeapSize, 13*M ); +define_pd_global(uintx, ProfiledCodeHeapSize, 14*M ); +define_pd_global(uintx, NonNMethodCodeHeapSize, 5*M ); define_pd_global(uintx, CodeCacheExpansionSize, 32*K); define_pd_global(uintx, CodeCacheMinBlockLength, 1); +define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K); define_pd_global(size_t, MetaspaceSize, 12*M); define_pd_global(bool, NeverActAsServerClassMachine, true); define_pd_global(size_t, NewSizeThreadIncrease, 16*K);
diff --git a/src/hotspot/cpu/ppc/c2_globals_ppc.hpp b/src/hotspot/cpu/ppc/c2_globals_ppc.hpp index a947e45..dc7b413 100644 --- a/src/hotspot/cpu/ppc/c2_globals_ppc.hpp +++ b/src/hotspot/cpu/ppc/c2_globals_ppc.hpp
@@ -1,6 +1,6 @@ /* * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2018 SAP SE. All rights reserved. + * Copyright (c) 2012, 2019 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -82,15 +82,15 @@ define_pd_global(bool, IdealizeClearArrayNode, true); define_pd_global(uintx, InitialCodeCacheSize, 2048*K); // Integral multiple of CodeCacheExpansionSize -define_pd_global(uintx, ReservedCodeCacheSize, 256*M); -define_pd_global(uintx, NonProfiledCodeHeapSize, 125*M); -define_pd_global(uintx, ProfiledCodeHeapSize, 126*M); +define_pd_global(uintx, ReservedCodeCacheSize, 48*M); +define_pd_global(uintx, NonProfiledCodeHeapSize, 21*M); +define_pd_global(uintx, ProfiledCodeHeapSize, 22*M); define_pd_global(uintx, NonNMethodCodeHeapSize, 5*M ); define_pd_global(uintx, CodeCacheExpansionSize, 64*K); // Ergonomics related flags define_pd_global(uint64_t, MaxRAM, 128ULL*G); -define_pd_global(uintx, CodeCacheMinBlockLength, 4); +define_pd_global(uintx, CodeCacheMinBlockLength, 6); define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K); define_pd_global(bool, TrapBasedRangeChecks, true);
diff --git a/src/hotspot/cpu/ppc/frame_ppc.hpp b/src/hotspot/cpu/ppc/frame_ppc.hpp index 6a0c4bf..5011127 100644 --- a/src/hotspot/cpu/ppc/frame_ppc.hpp +++ b/src/hotspot/cpu/ppc/frame_ppc.hpp
@@ -250,9 +250,6 @@ (offset_of(frame::top_ijava_frame_abi, _component)) struct ijava_state { -#ifdef ASSERT - uint64_t ijava_reserved; // Used for assertion. -#endif uint64_t method; uint64_t mirror; uint64_t locals; @@ -409,12 +406,6 @@ // The size of a cInterpreter object. static inline int interpreter_frame_cinterpreterstate_size_in_bytes(); - private: - - ConstantPoolCache** interpreter_frame_cpoolcache_addr() const; - - public: - // Additional interface for entry frames: inline entry_frame_locals* get_entry_frame_locals() const { return (entry_frame_locals*) (((address) fp()) - entry_frame_locals_size);
diff --git a/src/hotspot/cpu/ppc/frame_ppc.inline.hpp b/src/hotspot/cpu/ppc/frame_ppc.inline.hpp index a1a6600..a994998 100644 --- a/src/hotspot/cpu/ppc/frame_ppc.inline.hpp +++ b/src/hotspot/cpu/ppc/frame_ppc.inline.hpp
@@ -130,19 +130,22 @@ inline intptr_t** frame::interpreter_frame_locals_addr() const { return (intptr_t**) &(get_ijava_state()->locals); } + inline intptr_t* frame::interpreter_frame_bcp_addr() const { return (intptr_t*) &(get_ijava_state()->bcp); } + inline intptr_t* frame::interpreter_frame_mdp_addr() const { return (intptr_t*) &(get_ijava_state()->mdx); } + // Pointer beyond the "oldest/deepest" BasicObjectLock on stack. inline BasicObjectLock* frame::interpreter_frame_monitor_end() const { - return (BasicObjectLock *) get_ijava_state()->monitors; + return (BasicObjectLock*) get_ijava_state()->monitors; } inline BasicObjectLock* frame::interpreter_frame_monitor_begin() const { - return (BasicObjectLock *) get_ijava_state(); + return (BasicObjectLock*) get_ijava_state(); } // Return register stack slot addr at which currently interpreted method is found. @@ -154,23 +157,21 @@ return (oop*) &(get_ijava_state()->mirror); } -inline ConstantPoolCache** frame::interpreter_frame_cpoolcache_addr() const { - return (ConstantPoolCache**) &(get_ijava_state()->cpoolCache); -} inline ConstantPoolCache** frame::interpreter_frame_cache_addr() const { return (ConstantPoolCache**) &(get_ijava_state()->cpoolCache); } inline oop* frame::interpreter_frame_temp_oop_addr() const { - return (oop *) &(get_ijava_state()->oop_tmp); + return (oop*) &(get_ijava_state()->oop_tmp); } + inline intptr_t* frame::interpreter_frame_esp() const { return (intptr_t*) get_ijava_state()->esp; } // Convenient setters inline void frame::interpreter_frame_set_monitor_end(BasicObjectLock* end) { get_ijava_state()->monitors = (intptr_t) end;} -inline void frame::interpreter_frame_set_cpcache(ConstantPoolCache* cp) { *frame::interpreter_frame_cpoolcache_addr() = cp; } +inline void frame::interpreter_frame_set_cpcache(ConstantPoolCache* cp) { *interpreter_frame_cache_addr() = cp; } inline void frame::interpreter_frame_set_esp(intptr_t* esp) { get_ijava_state()->esp = (intptr_t) esp; } inline void frame::interpreter_frame_set_top_frame_sp(intptr_t* top_frame_sp) { get_ijava_state()->top_frame_sp = (intptr_t) top_frame_sp; } inline void frame::interpreter_frame_set_sender_sp(intptr_t* sender_sp) { get_ijava_state()->sender_sp = (intptr_t) sender_sp; }
diff --git a/src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp b/src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp index 404ea99..43b6403 100644 --- a/src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp +++ b/src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp
@@ -50,6 +50,8 @@ #if defined(COMPILER2) && (defined(AIX) || defined(LINUX)) // Include Transactional Memory lock eliding optimization #define INCLUDE_RTM_OPT 1 +#else +#define INCLUDE_RTM_OPT 0 #endif #define SUPPORT_RESERVED_STACK_AREA
diff --git a/src/hotspot/cpu/ppc/globals_ppc.hpp b/src/hotspot/cpu/ppc/globals_ppc.hpp index ad21779..3327f9b 100644 --- a/src/hotspot/cpu/ppc/globals_ppc.hpp +++ b/src/hotspot/cpu/ppc/globals_ppc.hpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2002, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2018 SAP SE. All rights reserved. + * Copyright (c) 2002, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2020 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -32,7 +32,6 @@ // Sets the default values for platform dependent flags used by the runtime system. // (see globals.hpp) -define_pd_global(bool, ShareVtableStubs, true); define_pd_global(bool, NeedsDeoptSuspend, false); // Only register window machines need this. @@ -96,8 +95,9 @@ writeable) \ \ product(uintx, PowerArchitecturePPC64, 0, \ - "CPU Version: x for PowerX. Currently recognizes Power5 to " \ - "Power8. Default is 0. Newer CPUs will be recognized as Power8.") \ + "Specify the PowerPC family version in use. If not provided, " \ + "HotSpot will determine it automatically. Host family version " \ + "is the maximum value allowed (instructions are not emulated).") \ \ product(bool, SuperwordUseVSX, false, \ "Use Power8 VSX instructions for superword optimization.") \ @@ -124,6 +124,8 @@ "Use load instructions for stack banging.") \ \ /* special instructions */ \ + product(bool, UseByteReverseInstructions, false, \ + "Use byte reverse instructions.") \ \ product(bool, UseCountLeadingZerosInstructionsPPC64, true, \ "Use count leading zeros instructions.") \
diff --git a/src/hotspot/cpu/ppc/interp_masm_ppc_64.cpp b/src/hotspot/cpu/ppc/interp_masm_ppc_64.cpp index a8d719a..e800e7d 100644 --- a/src/hotspot/cpu/ppc/interp_masm_ppc_64.cpp +++ b/src/hotspot/cpu/ppc/interp_masm_ppc_64.cpp
@@ -756,16 +756,6 @@ ld(Rscratch1, 0, R1_SP); // *SP ld(Rsender_sp, _ijava_state_neg(sender_sp), Rscratch1); // top_frame_sp ld(Rscratch2, 0, Rscratch1); // **SP -#ifdef ASSERT - { - Label Lok; - ld(R0, _ijava_state_neg(ijava_reserved), Rscratch1); - cmpdi(CCR0, R0, 0x5afe); - beq(CCR0, Lok); - stop("frame corrupted (remove activation)", 0x5afe); - bind(Lok); - } -#endif if (return_pc!=noreg) { ld(return_pc, _abi(lr), Rscratch1); // LR } @@ -2251,14 +2241,6 @@ stop("frame too small (restore istate)", 0x5432); bind(Lok); } - { - Label Lok; - ld(R0, _ijava_state_neg(ijava_reserved), scratch); - cmpdi(CCR0, R0, 0x5afe); - beq(CCR0, Lok); - stop("frame corrupted (restore istate)", 0x5afe); - bind(Lok); - } #endif } @@ -2271,7 +2253,7 @@ cmpdi(CCR0, Rcounters, 0); bne(CCR0, has_counters); call_VM(noreg, CAST_FROM_FN_PTR(address, - InterpreterRuntime::build_method_counters), method, false); + InterpreterRuntime::build_method_counters), method); ld(Rcounters, in_bytes(Method::method_counters_offset()), method); cmpdi(CCR0, Rcounters, 0); beq(CCR0, skip); // No MethodCounters, OutOfMemory.
diff --git a/src/hotspot/cpu/ppc/macroAssembler_ppc.cpp b/src/hotspot/cpu/ppc/macroAssembler_ppc.cpp index 2a32d28..be0125d 100644 --- a/src/hotspot/cpu/ppc/macroAssembler_ppc.cpp +++ b/src/hotspot/cpu/ppc/macroAssembler_ppc.cpp
@@ -2302,7 +2302,7 @@ ) { // make sure arguments make sense assert_different_registers(obj, var_size_in_bytes, t1); - assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size"); + assert(0 <= con_size_in_bytes && is_simm16(con_size_in_bytes), "illegal object size"); assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); const Register new_top = t1; @@ -3221,10 +3221,25 @@ } int MacroAssembler::instr_size_for_decode_klass_not_null() { - if (!UseCompressedClassPointers) return 0; - int num_instrs = 1; // shift or move - if (Universe::narrow_klass_base() != 0) num_instrs = 7; // shift + load const + add - return num_instrs * BytesPerInstWord; + static int computed_size = -1; + + // Not yet computed? + if (computed_size == -1) { + + if (!UseCompressedClassPointers) { + computed_size = 0; + } else { + // Determine by scratch emit. + ResourceMark rm; + int code_size = 8 * BytesPerInstWord; + CodeBuffer cb("decode_klass_not_null scratch buffer", code_size, 0); + MacroAssembler* a = new MacroAssembler(&cb); + a->decode_klass_not_null(R11_scratch1); + computed_size = a->offset(); + } + } + + return computed_size; } void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
diff --git a/src/hotspot/cpu/ppc/nativeInst_ppc.cpp b/src/hotspot/cpu/ppc/nativeInst_ppc.cpp index 196d42e..7aa9bcf 100644 --- a/src/hotspot/cpu/ppc/nativeInst_ppc.cpp +++ b/src/hotspot/cpu/ppc/nativeInst_ppc.cpp
@@ -176,6 +176,7 @@ address NativeMovConstReg::next_instruction_address() const { #ifdef ASSERT CodeBlob* nm = CodeCache::find_blob(instruction_address()); + assert(nm != NULL, "Could not find code blob"); assert(!MacroAssembler::is_set_narrow_oop(addr_at(0), nm->content_begin()), "Should not patch narrow oop here"); #endif @@ -194,6 +195,7 @@ } CodeBlob* cb = CodeCache::find_blob_unsafe(addr); + assert(cb != NULL, "Could not find code blob"); if (MacroAssembler::is_set_narrow_oop(addr, cb->content_begin())) { narrowOop no = (narrowOop)MacroAssembler::get_narrow_oop(addr, cb->content_begin()); return cast_from_oop<intptr_t>(CompressedOops::decode(no)); @@ -292,6 +294,7 @@ void NativeMovConstReg::set_narrow_oop(narrowOop data, CodeBlob *code /* = NULL */) { address inst2_addr = addr_at(0); CodeBlob* cb = (code) ? code : CodeCache::find_blob(instruction_address()); + assert(cb != NULL, "Could not find code blob"); if (MacroAssembler::get_narrow_oop(inst2_addr, cb->content_begin()) == (long)data) return; const address inst1_addr = @@ -402,6 +405,7 @@ address NativeCallTrampolineStub::destination(nmethod *nm) const { CodeBlob* cb = nm ? nm : CodeCache::find_blob_unsafe(addr_at(0)); + assert(cb != NULL, "Could not find code blob"); address ctable = cb->content_begin(); return *(address*)(ctable + destination_toc_offset()); @@ -413,6 +417,7 @@ void NativeCallTrampolineStub::set_destination(address new_destination) { CodeBlob* cb = CodeCache::find_blob(addr_at(0)); + assert(cb != NULL, "Could not find code blob"); address ctable = cb->content_begin(); *(address*)(ctable + destination_toc_offset()) = new_destination;
diff --git a/src/hotspot/cpu/ppc/nativeInst_ppc.hpp b/src/hotspot/cpu/ppc/nativeInst_ppc.hpp index 2399ec6..630c858 100644 --- a/src/hotspot/cpu/ppc/nativeInst_ppc.hpp +++ b/src/hotspot/cpu/ppc/nativeInst_ppc.hpp
@@ -468,6 +468,8 @@ address instruction_address() const { return addr_at(0); } + int num_bytes_to_end_of_patch() const { return instruction_size; } + intptr_t offset() const { #ifdef VM_LITTLE_ENDIAN short *hi_ptr = (short*)(addr_at(0));
diff --git a/src/hotspot/cpu/ppc/ppc.ad b/src/hotspot/cpu/ppc/ppc.ad index 6cc8875..fb58373 100644 --- a/src/hotspot/cpu/ppc/ppc.ad +++ b/src/hotspot/cpu/ppc/ppc.ad
@@ -1,6 +1,6 @@ // -// Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. -// Copyright (c) 2012, 2018 SAP SE. All rights reserved. +// Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved. +// Copyright (c) 2012, 2020 SAP SE. All rights reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This code is free software; you can redistribute it and/or modify it @@ -980,6 +980,8 @@ source %{ +#include "oops/klass.inline.hpp" + // Should the Matcher clone shifts on addressing modes, expecting them // to be subsumed into complex addressing expressions or compute them // into registers? @@ -1084,8 +1086,7 @@ int MachCallDynamicJavaNode::ret_addr_offset() { // Offset is 4 with postalloc expanded calls (bl is one instruction). We use // postalloc expanded calls if we use inline caches and do not update method data. - if (UseInlineCaches) - return 4; + if (UseInlineCaches) return 4; int vtable_index = this->_vtable_index; if (vtable_index < 0) { @@ -1093,8 +1094,7 @@ assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); return 12; } else { - assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); - return 24; + return 24 + MacroAssembler::instr_size_for_decode_klass_not_null(); } } @@ -2310,9 +2310,10 @@ return max_vector_size(bt); // Same as max. } -// PPC doesn't support misaligned vectors store/load. +// PPC implementation uses VSX load/store instructions (if +// SuperwordUseVSX) which support 4 byte but not arbitrary alignment const bool Matcher::misaligned_vectors_ok() { - return !AlignVector; // can be changed by flag + return false; } // PPC AES support not yet implemented @@ -3820,11 +3821,11 @@ int start_offset = __ offset(); Register Rtoc = (ra_) ? $constanttablebase : R2_TOC; -#if 0 + int vtable_index = this->_vtable_index; - if (_vtable_index < 0) { + if (vtable_index < 0) { // Must be invalid_vtable_index, not nonvirtual_vtable_index. - assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value"); + assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); Register ic_reg = as_Register(Matcher::inline_cache_reg_encode()); // Virtual call relocation will point to ic load. @@ -3841,7 +3842,7 @@ __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none); assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, - "Fix constant in ret_addr_offset()"); + "Fix constant in ret_addr_offset(), expected %d", __ offset() - start_offset); } else { assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); // Go thru the vtable. Get receiver klass. Receiver already @@ -3850,7 +3851,7 @@ __ load_klass(R11_scratch1, R3); - int entry_offset = in_bytes(Klass::vtable_start_offset()) + _vtable_index * vtableEntry::size_in_bytes(); + int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes(); int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); __ li(R19_method, v_off); __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/); @@ -3861,14 +3862,9 @@ // Call target. Either compiled code or C2I adapter. __ mtctr(R11_scratch1); __ bctrl(); - if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) { - tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset); - } assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, - "Fix constant in ret_addr_offset()"); + "Fix constant in ret_addr_offset(), expected %d", __ offset() - start_offset); } -#endif - Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!). %} // a runtime call @@ -4602,6 +4598,16 @@ interface(CONST_INTER); %} +// Double Immediate: +0.0d. +operand immD_0() %{ + predicate(jlong_cast(n->getd()) == 0); + match(ConD); + + op_cost(0); + format %{ %} + interface(CONST_INTER); +%} + // Integer Register Operands // Integer Destination Register // See definition of reg_class bits32_reg_rw. @@ -13627,6 +13633,7 @@ // Just slightly faster than java implementation. instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{ match(Set dst (ReverseBytesI src)); + predicate(!UseByteReverseInstructions); ins_cost(7*DEFAULT_COST); expand %{ @@ -13649,8 +13656,23 @@ %} %} +instruct bytes_reverse_int(iRegIdst dst, iRegIsrc src) %{ + match(Set dst (ReverseBytesI src)); + predicate(UseByteReverseInstructions); + ins_cost(DEFAULT_COST); + size(4); + + format %{ "BRW $dst, $src" %} + + ins_encode %{ + __ brw($dst$$Register, $src$$Register); + %} + ins_pipe(pipe_class_default); +%} + instruct bytes_reverse_long_Ex(iRegLdst dst, iRegLsrc src) %{ match(Set dst (ReverseBytesL src)); + predicate(!UseByteReverseInstructions); ins_cost(15*DEFAULT_COST); expand %{ @@ -13688,8 +13710,23 @@ %} %} +instruct bytes_reverse_long(iRegLdst dst, iRegLsrc src) %{ + match(Set dst (ReverseBytesL src)); + predicate(UseByteReverseInstructions); + ins_cost(DEFAULT_COST); + size(4); + + format %{ "BRD $dst, $src" %} + + ins_encode %{ + __ brd($dst$$Register, $src$$Register); + %} + ins_pipe(pipe_class_default); +%} + instruct bytes_reverse_ushort_Ex(iRegIdst dst, iRegIsrc src) %{ match(Set dst (ReverseBytesUS src)); + predicate(!UseByteReverseInstructions); ins_cost(2*DEFAULT_COST); expand %{ @@ -13701,8 +13738,23 @@ %} %} +instruct bytes_reverse_ushort(iRegIdst dst, iRegIsrc src) %{ + match(Set dst (ReverseBytesUS src)); + predicate(UseByteReverseInstructions); + ins_cost(DEFAULT_COST); + size(4); + + format %{ "BRH $dst, $src" %} + + ins_encode %{ + __ brh($dst$$Register, $src$$Register); + %} + ins_pipe(pipe_class_default); +%} + instruct bytes_reverse_short_Ex(iRegIdst dst, iRegIsrc src) %{ match(Set dst (ReverseBytesS src)); + predicate(!UseByteReverseInstructions); ins_cost(3*DEFAULT_COST); expand %{ @@ -13716,9 +13768,26 @@ %} %} +instruct bytes_reverse_short(iRegIdst dst, iRegIsrc src) %{ + match(Set dst (ReverseBytesS src)); + predicate(UseByteReverseInstructions); + ins_cost(DEFAULT_COST); + size(8); + + format %{ "BRH $dst, $src\n\t" + "EXTSH $dst, $dst" %} + + ins_encode %{ + __ brh($dst$$Register, $src$$Register); + __ extsh($dst$$Register, $dst$$Register); + %} + ins_pipe(pipe_class_default); +%} + // Load Integer reversed byte order instruct loadI_reversed(iRegIdst dst, indirect mem) %{ match(Set dst (ReverseBytesI (LoadI mem))); + predicate(n->in(1)->as_Load()->is_unordered() || followed_by_acquire(n->in(1))); ins_cost(MEMORY_REF_COST); size(4); @@ -13728,10 +13797,23 @@ ins_pipe(pipe_class_default); %} +instruct loadI_reversed_acquire(iRegIdst dst, indirect mem) %{ + match(Set dst (ReverseBytesI (LoadI mem))); + ins_cost(2 * MEMORY_REF_COST); + + size(12); + ins_encode %{ + __ lwbrx($dst$$Register, $mem$$Register); + __ twi_0($dst$$Register); + __ isync(); + %} + ins_pipe(pipe_class_default); +%} + // Load Long - aligned and reversed instruct loadL_reversed(iRegLdst dst, indirect mem) %{ match(Set dst (ReverseBytesL (LoadL mem))); - predicate(VM_Version::has_ldbrx()); + predicate(VM_Version::has_ldbrx() && (n->in(1)->as_Load()->is_unordered() || followed_by_acquire(n->in(1)))); ins_cost(MEMORY_REF_COST); size(4); @@ -13741,9 +13823,24 @@ ins_pipe(pipe_class_default); %} +instruct loadL_reversed_acquire(iRegLdst dst, indirect mem) %{ + match(Set dst (ReverseBytesL (LoadL mem))); + predicate(VM_Version::has_ldbrx()); + ins_cost(2 * MEMORY_REF_COST); + + size(12); + ins_encode %{ + __ ldbrx($dst$$Register, $mem$$Register); + __ twi_0($dst$$Register); + __ isync(); + %} + ins_pipe(pipe_class_default); +%} + // Load unsigned short / char reversed byte order instruct loadUS_reversed(iRegIdst dst, indirect mem) %{ match(Set dst (ReverseBytesUS (LoadUS mem))); + predicate(n->in(1)->as_Load()->is_unordered() || followed_by_acquire(n->in(1))); ins_cost(MEMORY_REF_COST); size(4); @@ -13753,9 +13850,23 @@ ins_pipe(pipe_class_default); %} +instruct loadUS_reversed_acquire(iRegIdst dst, indirect mem) %{ + match(Set dst (ReverseBytesUS (LoadUS mem))); + ins_cost(2 * MEMORY_REF_COST); + + size(12); + ins_encode %{ + __ lhbrx($dst$$Register, $mem$$Register); + __ twi_0($dst$$Register); + __ isync(); + %} + ins_pipe(pipe_class_default); +%} + // Load short reversed byte order instruct loadS_reversed(iRegIdst dst, indirect mem) %{ match(Set dst (ReverseBytesS (LoadS mem))); + predicate(n->in(1)->as_Load()->is_unordered() || followed_by_acquire(n->in(1))); ins_cost(MEMORY_REF_COST + DEFAULT_COST); size(8); @@ -13766,6 +13877,20 @@ ins_pipe(pipe_class_default); %} +instruct loadS_reversed_acquire(iRegIdst dst, indirect mem) %{ + match(Set dst (ReverseBytesS (LoadS mem))); + ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST); + + size(16); + ins_encode %{ + __ lhbrx($dst$$Register, $mem$$Register); + __ twi_0($dst$$Register); + __ extsh($dst$$Register, $dst$$Register); + __ isync(); + %} + ins_pipe(pipe_class_default); +%} + // Store Integer reversed byte order instruct storeI_reversed(iRegIsrc src, indirect mem) %{ match(Set mem (StoreI mem (ReverseBytesI src))); @@ -13967,7 +14092,7 @@ instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{ match(Set dst (ReplicateS zero)); predicate(n->as_Vector()->length() == 4); - format %{ "LI $dst, #0 \t// replicate4C" %} + format %{ "LI $dst, #0 \t// replicate4S" %} size(4); ins_encode %{ // TODO: PPC port $archOpcode(ppc64Opcode_addi); @@ -13979,7 +14104,7 @@ instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{ match(Set dst (ReplicateS src)); predicate(n->as_Vector()->length() == 4); - format %{ "LI $dst, -1 \t// replicate4C" %} + format %{ "LI $dst, -1 \t// replicate4S" %} size(4); ins_encode %{ // TODO: PPC port $archOpcode(ppc64Opcode_addi); @@ -14020,7 +14145,7 @@ match(Set dst (ReplicateS src)); predicate(n->as_Vector()->length() == 8); - format %{ "XXLEQV $dst, $src \t// replicate16B" %} + format %{ "XXLEQV $dst, $src \t// replicate8S" %} size(4); ins_encode %{ __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister); @@ -14041,7 +14166,7 @@ instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{ match(Set dst (ReplicateI zero)); predicate(n->as_Vector()->length() == 2); - format %{ "LI $dst, #0 \t// replicate4C" %} + format %{ "LI $dst, #0 \t// replicate2I" %} size(4); ins_encode %{ // TODO: PPC port $archOpcode(ppc64Opcode_addi); @@ -14053,7 +14178,7 @@ instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{ match(Set dst (ReplicateI src)); predicate(n->as_Vector()->length() == 2); - format %{ "LI $dst, -1 \t// replicate4C" %} + format %{ "LI $dst, -1 \t// replicate2I" %} size(4); ins_encode %{ // TODO: PPC port $archOpcode(ppc64Opcode_addi); @@ -14256,7 +14381,7 @@ %} %} -instruct repl2D_immI0(vecX dst, immI_0 zero) %{ +instruct repl2D_immD0(vecX dst, immD_0 zero) %{ match(Set dst (ReplicateD zero)); predicate(n->as_Vector()->length() == 2); @@ -14268,18 +14393,6 @@ ins_pipe(pipe_class_default); %} -instruct repl2D_immIminus1(vecX dst, immI_minus1 src) %{ - match(Set dst (ReplicateD src)); - predicate(n->as_Vector()->length() == 2); - - format %{ "XXLEQV $dst, $src \t// replicate16B" %} - size(4); - ins_encode %{ - __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister); - %} - ins_pipe(pipe_class_default); -%} - instruct mtvsrd(vecX dst, iRegLsrc src) %{ predicate(false); effect(DEF dst, USE src); @@ -14341,7 +14454,7 @@ match(Set dst (ReplicateL src)); predicate(n->as_Vector()->length() == 2); - format %{ "XXLEQV $dst, $src \t// replicate16B" %} + format %{ "XXLEQV $dst, $src \t// replicate2L" %} size(4); ins_encode %{ __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister); @@ -14606,10 +14719,11 @@ ins_cost(CALL_COST); format %{ "ShouldNotReachHere" %} - size(4); ins_encode %{ - // TODO: PPC port $archOpcode(ppc64Opcode_tdi); - __ trap_should_not_reach_here(); + if (is_reachable()) { + // TODO: PPC port $archOpcode(ppc64Opcode_tdi); + __ trap_should_not_reach_here(); + } %} ins_pipe(pipe_class_default); %}
diff --git a/src/hotspot/cpu/ppc/sharedRuntime_ppc.cpp b/src/hotspot/cpu/ppc/sharedRuntime_ppc.cpp index 3fdeb23..a139708 100644 --- a/src/hotspot/cpu/ppc/sharedRuntime_ppc.cpp +++ b/src/hotspot/cpu/ppc/sharedRuntime_ppc.cpp
@@ -570,7 +570,6 @@ __ bctr(); } -#ifdef COMPILER2 static int reg2slot(VMReg r) { return r->reg2stack() + SharedRuntime::out_preserve_stack_slots(); } @@ -578,7 +577,6 @@ static int reg2offset(VMReg r) { return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; } -#endif // --------------------------------------------------------------------------- // Read the array of BasicTypes from a signature, and compute where the @@ -1279,7 +1277,6 @@ return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); } -#ifdef COMPILER2 // An oop arg. Must pass a handle not the oop itself. static void object_move(MacroAssembler* masm, int frame_size_in_slots, @@ -1788,8 +1785,6 @@ receiver_reg, member_reg, /*for_compiler_entry:*/ true); } -#endif // COMPILER2 - // --------------------------------------------------------------------------- // Generate a native wrapper for a given method. The method takes arguments // in the Java compiled code convention, marshals them to the native @@ -1824,8 +1819,8 @@ int compile_id, BasicType *in_sig_bt, VMRegPair *in_regs, - BasicType ret_type) { -#ifdef COMPILER2 + BasicType ret_type, + address critical_entry) { if (method->is_method_handle_intrinsic()) { vmIntrinsics::ID iid = method->intrinsic_id(); intptr_t start = (intptr_t)__ pc(); @@ -1849,7 +1844,7 @@ } bool is_critical_native = true; - address native_func = method->critical_native_function(); + address native_func = critical_entry; if (native_func == NULL) { native_func = method->native_function(); is_critical_native = false; @@ -2083,7 +2078,7 @@ // Check ic: object class == cached class? if (!method_is_static) { - Register ic = as_Register(Matcher::inline_cache_reg_encode()); + Register ic = R19_inline_cache_reg; Register receiver_klass = r_temp_1; __ cmpdi(CCR0, R3_ARG1, 0); @@ -2608,12 +2603,10 @@ // Handler for pending exceptions (out-of-line). // -------------------------------------------------------------------------- - // Since this is a native call, we know the proper exception handler // is the empty function. We just pop this frame and then jump to // forward_exception_entry. if (!is_critical_native) { - __ align(InteriorEntryAlignment); __ bind(handle_pending_exception); __ pop_frame(); @@ -2626,7 +2619,6 @@ // -------------------------------------------------------------------------- if (!method_is_static) { - __ align(InteriorEntryAlignment); __ bind(ic_miss); __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), @@ -2653,10 +2645,6 @@ } return nm; -#else - ShouldNotReachHere(); - return NULL; -#endif // COMPILER2 } // This function returns the adjust size (in number of words) to a c2i adapter @@ -2690,10 +2678,6 @@ __ ld(frame_size_reg, 0, frame_sizes_reg); __ std(pc_reg, _abi(lr), R1_SP); __ push_frame(frame_size_reg, R0/*tmp*/); -#ifdef ASSERT - __ load_const_optimized(pc_reg, 0x5afe); - __ std(pc_reg, _ijava_state_neg(ijava_reserved), R1_SP); -#endif __ std(R1_SP, _ijava_state_neg(sender_sp), R1_SP); __ addi(number_of_frames_reg, number_of_frames_reg, -1); __ addi(frame_sizes_reg, frame_sizes_reg, wordSize); @@ -2766,10 +2750,6 @@ __ std(R12_scratch2, _abi(lr), R1_SP); // Initialize initial_caller_sp. -#ifdef ASSERT - __ load_const_optimized(pc_reg, 0x5afe); - __ std(pc_reg, _ijava_state_neg(ijava_reserved), R1_SP); -#endif __ std(frame_size_reg, _ijava_state_neg(sender_sp), R1_SP); #ifdef ASSERT @@ -2841,7 +2821,7 @@ // We can't grab a free register here, because all registers may // contain live values, so let the RegisterSaver do the adjustment // of the return pc. - const int return_pc_adjustment_no_exception = -HandlerImpl::size_deopt_handler(); + const int return_pc_adjustment_no_exception = -MacroAssembler::bl64_patchable_size; // Push the "unpack frame" // Save everything in sight.
diff --git a/src/hotspot/cpu/ppc/stubGenerator_ppc.cpp b/src/hotspot/cpu/ppc/stubGenerator_ppc.cpp index 36e6076..df6271b 100644 --- a/src/hotspot/cpu/ppc/stubGenerator_ppc.cpp +++ b/src/hotspot/cpu/ppc/stubGenerator_ppc.cpp
@@ -2554,7 +2554,7 @@ address start = __ function_entry(); - Label L_doLast; + Label L_doLast, L_error; Register from = R3_ARG1; // source array address Register to = R4_ARG2; // destination array address @@ -2584,7 +2584,7 @@ __ li (fifteen, 15); - // load unaligned from[0-15] to vsRet + // load unaligned from[0-15] to vRet __ lvx (vRet, from); __ lvx (vTmp1, fifteen, from); __ lvsl (fromPerm, from); @@ -2699,6 +2699,11 @@ __ cmpwi (CCR0, keylen, 52); __ beq (CCR0, L_doLast); +#ifdef ASSERT + __ cmpwi (CCR0, keylen, 60); + __ bne (CCR0, L_error); +#endif + // 12th - 13th rounds __ vcipher (vRet, vRet, vKey1); __ vcipher (vRet, vRet, vKey2); @@ -2719,29 +2724,30 @@ __ vcipher (vRet, vRet, vKey1); __ vcipherlast (vRet, vRet, vKey2); +#ifdef VM_LITTLE_ENDIAN + // toPerm = 0x0F0E0D0C0B0A09080706050403020100 + __ lvsl (toPerm, keypos); // keypos is a multiple of 16 + __ vxor (toPerm, toPerm, fSplt); + + // Swap Bytes + __ vperm (vRet, vRet, vRet, toPerm); +#endif + // store result (unaligned) -#ifdef VM_LITTLE_ENDIAN - __ lvsl (toPerm, to); -#else - __ lvsr (toPerm, to); -#endif - __ vspltisb (vTmp3, -1); - __ vspltisb (vTmp4, 0); - __ lvx (vTmp1, to); - __ lvx (vTmp2, fifteen, to); -#ifdef VM_LITTLE_ENDIAN - __ vperm (vTmp3, vTmp3, vTmp4, toPerm); // generate select mask - __ vxor (toPerm, toPerm, fSplt); // swap bytes -#else - __ vperm (vTmp3, vTmp4, vTmp3, toPerm); // generate select mask -#endif - __ vperm (vTmp4, vRet, vRet, toPerm); // rotate data - __ vsel (vTmp2, vTmp4, vTmp2, vTmp3); - __ vsel (vTmp1, vTmp1, vTmp4, vTmp3); - __ stvx (vTmp2, fifteen, to); // store this one first (may alias) - __ stvx (vTmp1, to); + // Note: We can't use a read-modify-write sequence which touches additional Bytes. + Register lo = temp, hi = fifteen; // Reuse + __ vsldoi (vTmp1, vRet, vRet, 8); + __ mfvrd (hi, vRet); + __ mfvrd (lo, vTmp1); + __ std (hi, 0 LITTLE_ENDIAN_ONLY(+ 8), to); + __ std (lo, 0 BIG_ENDIAN_ONLY(+ 8), to); __ blr(); + +#ifdef ASSERT + __ bind(L_error); + __ stop("aescrypt_encryptBlock: invalid key length"); +#endif return start; } @@ -2755,10 +2761,7 @@ address start = __ function_entry(); - Label L_doLast; - Label L_do44; - Label L_do52; - Label L_do60; + Label L_doLast, L_do44, L_do52, L_error; Register from = R3_ARG1; // source array address Register to = R4_ARG2; // destination array address @@ -2789,7 +2792,7 @@ __ li (fifteen, 15); - // load unaligned from[0-15] to vsRet + // load unaligned from[0-15] to vRet __ lvx (vRet, from); __ lvx (vTmp1, fifteen, from); __ lvsl (fromPerm, from); @@ -2818,6 +2821,11 @@ __ cmpwi (CCR0, keylen, 52); __ beq (CCR0, L_do52); +#ifdef ASSERT + __ cmpwi (CCR0, keylen, 60); + __ bne (CCR0, L_error); +#endif + // load the 15th round key to vKey1 __ li (keypos, 240); __ lvx (vKey1, keypos, key); @@ -2854,6 +2862,7 @@ __ b (L_doLast); + __ align(32); __ bind (L_do52); // load the 13th round key to vKey1 @@ -2880,6 +2889,7 @@ __ b (L_doLast); + __ align(32); __ bind (L_do44); // load the 11th round key to vKey1 @@ -2957,29 +2967,30 @@ __ vncipher (vRet, vRet, vKey4); __ vncipherlast (vRet, vRet, vKey5); +#ifdef VM_LITTLE_ENDIAN + // toPerm = 0x0F0E0D0C0B0A09080706050403020100 + __ lvsl (toPerm, keypos); // keypos is a multiple of 16 + __ vxor (toPerm, toPerm, fSplt); + + // Swap Bytes + __ vperm (vRet, vRet, vRet, toPerm); +#endif + // store result (unaligned) -#ifdef VM_LITTLE_ENDIAN - __ lvsl (toPerm, to); -#else - __ lvsr (toPerm, to); -#endif - __ vspltisb (vTmp3, -1); - __ vspltisb (vTmp4, 0); - __ lvx (vTmp1, to); - __ lvx (vTmp2, fifteen, to); -#ifdef VM_LITTLE_ENDIAN - __ vperm (vTmp3, vTmp3, vTmp4, toPerm); // generate select mask - __ vxor (toPerm, toPerm, fSplt); // swap bytes -#else - __ vperm (vTmp3, vTmp4, vTmp3, toPerm); // generate select mask -#endif - __ vperm (vTmp4, vRet, vRet, toPerm); // rotate data - __ vsel (vTmp2, vTmp4, vTmp2, vTmp3); - __ vsel (vTmp1, vTmp1, vTmp4, vTmp3); - __ stvx (vTmp2, fifteen, to); // store this one first (may alias) - __ stvx (vTmp1, to); + // Note: We can't use a read-modify-write sequence which touches additional Bytes. + Register lo = temp, hi = fifteen; // Reuse + __ vsldoi (vTmp1, vRet, vRet, 8); + __ mfvrd (hi, vRet); + __ mfvrd (lo, vTmp1); + __ std (hi, 0 LITTLE_ENDIAN_ONLY(+ 8), to); + __ std (lo, 0 BIG_ENDIAN_ONLY(+ 8), to); __ blr(); + +#ifdef ASSERT + __ bind(L_error); + __ stop("aescrypt_decryptBlock: invalid key length"); +#endif return start; } @@ -3060,6 +3071,7 @@ STUB_ENTRY(checkcast_arraycopy)); // fill routines +#ifdef COMPILER2 if (OptimizeFill) { StubRoutines::_jbyte_fill = generate_fill(T_BYTE, false, "jbyte_fill"); StubRoutines::_jshort_fill = generate_fill(T_SHORT, false, "jshort_fill"); @@ -3068,6 +3080,7 @@ StubRoutines::_arrayof_jshort_fill = generate_fill(T_SHORT, true, "arrayof_jshort_fill"); StubRoutines::_arrayof_jint_fill = generate_fill(T_INT, true, "arrayof_jint_fill"); } +#endif } // Safefetch stubs. @@ -3536,8 +3549,6 @@ if (UseMultiplyToLenIntrinsic) { StubRoutines::_multiplyToLen = generate_multiplyToLen(); } -#endif - if (UseSquareToLenIntrinsic) { StubRoutines::_squareToLen = generate_squareToLen(); } @@ -3552,6 +3563,7 @@ StubRoutines::_montgomerySquare = CAST_FROM_FN_PTR(address, SharedRuntime::montgomery_square); } +#endif if (UseAESIntrinsics) { StubRoutines::_aescrypt_encryptBlock = generate_aescrypt_encryptBlock();
diff --git a/src/hotspot/cpu/ppc/templateInterpreterGenerator_ppc.cpp b/src/hotspot/cpu/ppc/templateInterpreterGenerator_ppc.cpp index 133ca71..b25d61c 100644 --- a/src/hotspot/cpu/ppc/templateInterpreterGenerator_ppc.cpp +++ b/src/hotspot/cpu/ppc/templateInterpreterGenerator_ppc.cpp
@@ -592,10 +592,10 @@ __ load_const_optimized(R4_ARG2, (address) name, R11_scratch1); if (pass_oop) { __ mr(R5_ARG3, Rexception); - __ call_VM(Rexception, CAST_FROM_FN_PTR(address, InterpreterRuntime::create_klass_exception), false); + __ call_VM(Rexception, CAST_FROM_FN_PTR(address, InterpreterRuntime::create_klass_exception)); } else { __ load_const_optimized(R5_ARG3, (address) message, R11_scratch1); - __ call_VM(Rexception, CAST_FROM_FN_PTR(address, InterpreterRuntime::create_exception), false); + __ call_VM(Rexception, CAST_FROM_FN_PTR(address, InterpreterRuntime::create_exception)); } // Throw exception. @@ -1050,17 +1050,14 @@ // Get mirror and store it in the frame as GC root for this Method*. __ load_mirror_from_const_method(R12_scratch2, Rconst_method); - __ addi(R26_monitor, R1_SP, - frame::ijava_state_size); - __ addi(R15_esp, R26_monitor, - Interpreter::stackElementSize); + __ addi(R26_monitor, R1_SP, -frame::ijava_state_size); + __ addi(R15_esp, R26_monitor, -Interpreter::stackElementSize); // Store values. - // R15_esp, R14_bcp, R26_monitor, R28_mdx are saved at java calls - // in InterpreterMacroAssembler::call_from_interpreter. __ std(R19_method, _ijava_state_neg(method), R1_SP); __ std(R12_scratch2, _ijava_state_neg(mirror), R1_SP); - __ std(R21_sender_SP, _ijava_state_neg(sender_sp), R1_SP); - __ std(R27_constPoolCache, _ijava_state_neg(cpoolCache), R1_SP); __ std(R18_locals, _ijava_state_neg(locals), R1_SP); + __ std(R27_constPoolCache, _ijava_state_neg(cpoolCache), R1_SP); // Note: esp, bcp, monitor, mdx live in registers. Hence, the correct version can only // be found in the frame after save_interpreter_state is done. This is always true @@ -1068,31 +1065,20 @@ // because e.g. frame::interpreter_frame_bcp() will not access the correct value // (Enhanced Stack Trace). // The signal handler does not save the interpreter state into the frame. + + // We have to initialize some of these frame slots for native calls (accessed by GC). + // Also initialize them for non-native calls for better tool support (even though + // you may not get the most recent version as described above). __ li(R0, 0); -#ifdef ASSERT - // Fill remaining slots with constants. - __ load_const_optimized(R11_scratch1, 0x5afe); - __ load_const_optimized(R12_scratch2, 0xdead); -#endif - // We have to initialize some frame slots for native calls (accessed by GC). - if (native_call) { - __ std(R26_monitor, _ijava_state_neg(monitors), R1_SP); - __ std(R14_bcp, _ijava_state_neg(bcp), R1_SP); - if (ProfileInterpreter) { __ std(R28_mdx, _ijava_state_neg(mdx), R1_SP); } - } -#ifdef ASSERT - else { - __ std(R12_scratch2, _ijava_state_neg(monitors), R1_SP); - __ std(R12_scratch2, _ijava_state_neg(bcp), R1_SP); - __ std(R12_scratch2, _ijava_state_neg(mdx), R1_SP); - } - __ std(R11_scratch1, _ijava_state_neg(ijava_reserved), R1_SP); - __ std(R12_scratch2, _ijava_state_neg(esp), R1_SP); - __ std(R12_scratch2, _ijava_state_neg(lresult), R1_SP); - __ std(R12_scratch2, _ijava_state_neg(fresult), R1_SP); -#endif + __ std(R26_monitor, _ijava_state_neg(monitors), R1_SP); + __ std(R14_bcp, _ijava_state_neg(bcp), R1_SP); + if (ProfileInterpreter) { __ std(R28_mdx, _ijava_state_neg(mdx), R1_SP); } + __ std(R15_esp, _ijava_state_neg(esp), R1_SP); + __ std(R0, _ijava_state_neg(oop_tmp), R1_SP); // only used for native_call + + // Store sender's SP and this frame's top SP. __ subf(R12_scratch2, top_frame_size, R1_SP); - __ std(R0, _ijava_state_neg(oop_tmp), R1_SP); + __ std(R21_sender_SP, _ijava_state_neg(sender_sp), R1_SP); __ std(R12_scratch2, _ijava_state_neg(top_frame_sp), R1_SP); // Push top frame. @@ -2128,7 +2114,7 @@ // The member name argument must be restored if _invokestatic is re-executed after a PopFrame call. // Detect such a case in the InterpreterRuntime function and return the member name argument, or NULL. __ ld(R4_ARG2, 0, R18_locals); - __ MacroAssembler::call_VM(R4_ARG2, CAST_FROM_FN_PTR(address, InterpreterRuntime::member_name_arg_or_null), R4_ARG2, R19_method, R14_bcp, false); + __ call_VM(R4_ARG2, CAST_FROM_FN_PTR(address, InterpreterRuntime::member_name_arg_or_null), R4_ARG2, R19_method, R14_bcp); __ restore_interpreter_state(R11_scratch1, /*bcp_and_mdx_only*/ true); __ cmpdi(CCR0, R4_ARG2, 0); __ beq(CCR0, L_done);
diff --git a/src/hotspot/cpu/ppc/vm_version_ext_ppc.hpp b/src/hotspot/cpu/ppc/vm_version_ext_ppc.hpp index 5da8569..cb5218e 100644 --- a/src/hotspot/cpu/ppc/vm_version_ext_ppc.hpp +++ b/src/hotspot/cpu/ppc/vm_version_ext_ppc.hpp
@@ -25,8 +25,8 @@ #ifndef CPU_PPC_VM_VM_VERSION_EXT_PPC_HPP #define CPU_PPC_VM_VM_VERSION_EXT_PPC_HPP +#include "runtime/vm_version.hpp" #include "utilities/macros.hpp" -#include "vm_version_ppc.hpp" #define CPU_INFO "cpu_info" #define CPU_TYPE "fpu_type"
diff --git a/src/hotspot/cpu/ppc/vm_version_ppc.cpp b/src/hotspot/cpu/ppc/vm_version_ppc.cpp index e5a6238..1792e64 100644 --- a/src/hotspot/cpu/ppc/vm_version_ppc.cpp +++ b/src/hotspot/cpu/ppc/vm_version_ppc.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2018, SAP SE. All rights reserved. + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2020 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -32,12 +32,15 @@ #include "runtime/java.hpp" #include "runtime/os.hpp" #include "runtime/stubCodeGenerator.hpp" +#include "runtime/vm_version.hpp" #include "utilities/align.hpp" #include "utilities/defaultStream.hpp" #include "utilities/globalDefinitions.hpp" -#include "vm_version_ppc.hpp" #include <sys/sysinfo.h> +#if defined(_AIX) +#include <libperfstat.h> +#endif #if defined(LINUX) && defined(VM_LITTLE_ENDIAN) #include <sys/auxv.h> @@ -63,7 +66,9 @@ // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features. if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) { - if (VM_Version::has_darn()) { + if (VM_Version::has_brw()) { + FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 10); + } else if (VM_Version::has_darn()) { FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 9); } else if (VM_Version::has_lqarx()) { FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8); @@ -80,12 +85,13 @@ bool PowerArchitecturePPC64_ok = false; switch (PowerArchitecturePPC64) { - case 9: if (!VM_Version::has_darn() ) break; - case 8: if (!VM_Version::has_lqarx() ) break; - case 7: if (!VM_Version::has_popcntw()) break; - case 6: if (!VM_Version::has_cmpb() ) break; - case 5: if (!VM_Version::has_popcntb()) break; - case 0: PowerArchitecturePPC64_ok = true; break; + case 10: if (!VM_Version::has_brw() ) break; + case 9: if (!VM_Version::has_darn() ) break; + case 8: if (!VM_Version::has_lqarx() ) break; + case 7: if (!VM_Version::has_popcntw()) break; + case 6: if (!VM_Version::has_cmpb() ) break; + case 5: if (!VM_Version::has_popcntb()) break; + case 0: PowerArchitecturePPC64_ok = true; break; default: break; } guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to " @@ -147,12 +153,23 @@ FLAG_SET_DEFAULT(UseCharacterCompareIntrinsics, false); } } + + if (PowerArchitecturePPC64 >= 10) { + if (FLAG_IS_DEFAULT(UseByteReverseInstructions)) { + FLAG_SET_ERGO(bool, UseByteReverseInstructions, true); + } + } else { + if (UseByteReverseInstructions) { + warning("UseByteReverseInstructions specified, but needs at least Power10."); + FLAG_SET_DEFAULT(UseByteReverseInstructions, false); + } + } #endif // Create and print feature-string. char buf[(num_features+1) * 16]; // Max 16 chars per feature. jio_snprintf(buf, sizeof(buf), - "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", + "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", (has_fsqrt() ? " fsqrt" : ""), (has_isel() ? " isel" : ""), (has_lxarxeh() ? " lxarxeh" : ""), @@ -170,7 +187,8 @@ (has_stdbrx() ? " stdbrx" : ""), (has_vshasig() ? " sha" : ""), (has_tm() ? " rtm" : ""), - (has_darn() ? " darn" : "") + (has_darn() ? " darn" : ""), + (has_brw() ? " brw" : "") // Make sure number of %s matches num_features! ); _features_string = os::strdup(buf); @@ -215,6 +233,10 @@ assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); + if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (cache_line_size > ContendedPaddingWidth)) { + ContendedPaddingWidth = cache_line_size; + } + // If running on Power8 or newer hardware, the implementation uses the available vector instructions. // In all other cases, the implementation uses only generally available instructions. if (!UseCRC32Intrinsics) { @@ -309,6 +331,7 @@ FLAG_SET_DEFAULT(UseSHA, false); } +#ifdef COMPILER2 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { UseSquareToLenIntrinsic = true; } @@ -324,6 +347,7 @@ if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { UseMontgomerySquareIntrinsic = true; } +#endif if (UseVectorizedMismatchIntrinsic) { warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); @@ -370,15 +394,135 @@ if (UseRTMDeopt) { FLAG_SET_DEFAULT(UseRTMDeopt, false); } +#ifdef COMPILER2 if (PrintPreciseRTMLockingStatistics) { FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); } +#endif } // This machine allows unaligned memory accesses if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { FLAG_SET_DEFAULT(UseUnalignedAccesses, true); } + + check_virtualizations(); +} + +void VM_Version::check_virtualizations() { +#if defined(_AIX) + int rc = 0; + perfstat_partition_total_t pinfo; + rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1); + if (rc == 1) { + Abstract_VM_Version::_detected_virtualization = PowerVM; + } +#else + const char* info_file = "/proc/ppc64/lparcfg"; + // system_type=...qemu indicates PowerKVM + // e.g. system_type=IBM pSeries (emulated by qemu) + char line[500]; + FILE* fp = fopen(info_file, "r"); + if (fp == NULL) { + return; + } + const char* system_type="system_type="; // in case this line contains qemu, it is KVM + const char* num_lpars="NumLpars="; // in case of non-KVM : if this line is found it is PowerVM + bool num_lpars_found = false; + + while (fgets(line, sizeof(line), fp) != NULL) { + if (strncmp(line, system_type, strlen(system_type)) == 0) { + if (strstr(line, "qemu") != 0) { + Abstract_VM_Version::_detected_virtualization = PowerKVM; + fclose(fp); + return; + } + } + if (strncmp(line, num_lpars, strlen(num_lpars)) == 0) { + num_lpars_found = true; + } + } + if (num_lpars_found) { + Abstract_VM_Version::_detected_virtualization = PowerVM; + } else { + Abstract_VM_Version::_detected_virtualization = PowerFullPartitionMode; + } + fclose(fp); +#endif +} + +void VM_Version::print_platform_virtualization_info(outputStream* st) { +#if defined(_AIX) + // more info about perfstat API see + // https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/com.ibm.aix.prftools/idprftools_perfstat_glob_partition.htm + int rc = 0; + perfstat_partition_total_t pinfo; + memset(&pinfo, 0, sizeof(perfstat_partition_total_t)); + rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1); + if (rc != 1) { + return; + } else { + st->print_cr("Virtualization type : PowerVM"); + } + // CPU information + perfstat_cpu_total_t cpuinfo; + memset(&cpuinfo, 0, sizeof(perfstat_cpu_total_t)); + rc = perfstat_cpu_total(NULL, &cpuinfo, sizeof(perfstat_cpu_total_t), 1); + if (rc != 1) { + return; + } + + st->print_cr("Processor description : %s", cpuinfo.description); + st->print_cr("Processor speed : %llu Hz", cpuinfo.processorHZ); + + st->print_cr("LPAR partition name : %s", pinfo.name); + st->print_cr("LPAR partition number : %u", pinfo.lpar_id); + st->print_cr("LPAR partition type : %s", pinfo.type.b.shared_enabled ? "shared" : "dedicated"); + st->print_cr("LPAR mode : %s", pinfo.type.b.donate_enabled ? "donating" : pinfo.type.b.capped ? "capped" : "uncapped"); + st->print_cr("LPAR partition group ID : %u", pinfo.group_id); + st->print_cr("LPAR shared pool ID : %u", pinfo.pool_id); + + st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_capable ? "capable" : "not capable"); + st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_enabled ? "on" : "off"); + st->print_cr("AME (active memory expansion) : %s", pinfo.type.b.ame_enabled ? "on" : "off"); + + if (pinfo.type.b.ame_enabled) { + st->print_cr("AME true memory in bytes : %llu", pinfo.true_memory); + st->print_cr("AME expanded memory in bytes : %llu", pinfo.expanded_memory); + } + + st->print_cr("SMT : %s", pinfo.type.b.smt_capable ? "capable" : "not capable"); + st->print_cr("SMT : %s", pinfo.type.b.smt_enabled ? "on" : "off"); + int ocpus = pinfo.online_cpus > 0 ? pinfo.online_cpus : 1; + st->print_cr("LPAR threads : %d", cpuinfo.ncpus/ocpus); + st->print_cr("LPAR online virtual cpus : %d", pinfo.online_cpus); + st->print_cr("LPAR logical cpus : %d", cpuinfo.ncpus); + st->print_cr("LPAR maximum virtual cpus : %u", pinfo.max_cpus); + st->print_cr("LPAR minimum virtual cpus : %u", pinfo.min_cpus); + st->print_cr("LPAR entitled capacity : %4.2f", (double) (pinfo.entitled_proc_capacity/100.0)); + st->print_cr("LPAR online memory : %llu MB", pinfo.online_memory); + st->print_cr("LPAR maximum memory : %llu MB", pinfo.max_memory); + st->print_cr("LPAR minimum memory : %llu MB", pinfo.min_memory); +#else + const char* info_file = "/proc/ppc64/lparcfg"; + const char* kw[] = { "system_type=", // qemu indicates PowerKVM + "partition_entitled_capacity=", // entitled processor capacity percentage + "partition_max_entitled_capacity=", + "capacity_weight=", // partition CPU weight + "partition_active_processors=", + "partition_potential_processors=", + "entitled_proc_capacity_available=", + "capped=", // 0 - uncapped, 1 - vcpus capped at entitled processor capacity percentage + "shared_processor_mode=", // (non)dedicated partition + "system_potential_processors=", + "pool=", // CPU-pool number + "pool_capacity=", + "NumLpars=", // on non-KVM machines, NumLpars is not found for full partition mode machines + NULL }; + if (!print_matching_lines_from_file(info_file, st, kw)) { + st->print_cr(" <%s Not Available>", info_file); + } +#endif } bool VM_Version::use_biased_locking() { @@ -404,6 +548,13 @@ void VM_Version::print_features() { tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size()); + + if (Verbose) { + if (ContendedPaddingWidth > 0) { + tty->cr(); + tty->print_cr("ContendedPaddingWidth " INTX_FORMAT, ContendedPaddingWidth); + } + } } #ifdef COMPILER2 @@ -686,6 +837,7 @@ a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig // rtm is determined by OS a->darn(R7); // code[17] -> darn + a->brw(R5, R6); // code[18] -> brw a->blr(); // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it. @@ -739,6 +891,7 @@ if (code[feature_cntr++]) features |= vshasig_m; // feature rtm_m is determined by OS if (code[feature_cntr++]) features |= darn_m; + if (code[feature_cntr++]) features |= brw_m; // Print the detection code. if (PrintAssembly) {
diff --git a/src/hotspot/cpu/ppc/vm_version_ppc.hpp b/src/hotspot/cpu/ppc/vm_version_ppc.hpp index 22ce370..d6a9478 100644 --- a/src/hotspot/cpu/ppc/vm_version_ppc.hpp +++ b/src/hotspot/cpu/ppc/vm_version_ppc.hpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2018 SAP SE. All rights reserved. + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2020 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -26,8 +26,8 @@ #ifndef CPU_PPC_VM_VM_VERSION_PPC_HPP #define CPU_PPC_VM_VM_VERSION_PPC_HPP +#include "runtime/abstract_vm_version.hpp" #include "runtime/globals_extension.hpp" -#include "runtime/vm_version.hpp" class VM_Version: public Abstract_VM_Version { protected: @@ -51,6 +51,7 @@ vshasig, rtm, darn, + brw, num_features // last entry to count features }; enum Feature_Flag_Set { @@ -74,6 +75,7 @@ vshasig_m = (1 << vshasig), rtm_m = (1 << rtm ), darn_m = (1 << darn ), + brw_m = (1 << brw ), all_features_m = (unsigned long)-1 }; @@ -87,6 +89,10 @@ public: // Initialization static void initialize(); + static void check_virtualizations(); + + // Override Abstract_VM_Version implementation + static void print_platform_virtualization_info(outputStream*); // Override Abstract_VM_Version implementation static bool use_biased_locking(); @@ -112,6 +118,7 @@ static bool has_vshasig() { return (_features & vshasig_m) != 0; } static bool has_tm() { return (_features & rtm_m) != 0; } static bool has_darn() { return (_features & darn_m) != 0; } + static bool has_brw() { return (_features & brw_m) != 0; } static bool has_mtfprd() { return has_vpmsumb(); } // alias for P8
diff --git a/src/hotspot/cpu/ppc/vtableStubs_ppc_64.cpp b/src/hotspot/cpu/ppc/vtableStubs_ppc_64.cpp index 3af43aa..8f242ec 100644 --- a/src/hotspot/cpu/ppc/vtableStubs_ppc_64.cpp +++ b/src/hotspot/cpu/ppc/vtableStubs_ppc_64.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2018 SAP SE. All rights reserved. + * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2021 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -72,9 +72,9 @@ slop_delta = load_const_maxLen - (__ pc() - start_pc); slop_bytes += slop_delta; assert(slop_delta >= 0, "negative slop(%d) encountered, adjust code size estimate!", slop_delta); - __ lwz(R12_scratch2, offs, R11_scratch1); + __ ld(R12_scratch2, offs, R11_scratch1); __ addi(R12_scratch2, R12_scratch2, 1); - __ stw(R12_scratch2, offs, R11_scratch1); + __ std(R12_scratch2, offs, R11_scratch1); } #endif @@ -140,6 +140,7 @@ if (s == NULL) { return NULL; } + // Count unused bytes in instruction sequences of variable size. // We add them to the computed buffer size in order to avoid // overflow in subsequently generated stubs. @@ -159,9 +160,9 @@ slop_delta = load_const_maxLen - (__ pc() - start_pc); slop_bytes += slop_delta; assert(slop_delta >= 0, "negative slop(%d) encountered, adjust code size estimate!", slop_delta); - __ lwz(R12_scratch2, offs, R11_scratch1); + __ ld(R12_scratch2, offs, R11_scratch1); __ addi(R12_scratch2, R12_scratch2, 1); - __ stw(R12_scratch2, offs, R11_scratch1); + __ std(R12_scratch2, offs, R11_scratch1); } #endif
diff --git a/src/hotspot/cpu/s390/assembler_s390.hpp b/src/hotspot/cpu/s390/assembler_s390.hpp index 8c2ba15..a162d18 100644 --- a/src/hotspot/cpu/s390/assembler_s390.hpp +++ b/src/hotspot/cpu/s390/assembler_s390.hpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2016, 2017 SAP SE. All rights reserved. + * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2016, 2021 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -1344,6 +1344,10 @@ #define CKSM_ZOPC (unsigned int)(0xb2 << 24 | 0x41 << 16) // checksum. This is NOT CRC32 #define KM_ZOPC (unsigned int)(0xb9 << 24 | 0x2e << 16) // cipher #define KMC_ZOPC (unsigned int)(0xb9 << 24 | 0x2f << 16) // cipher +#define KMA_ZOPC (unsigned int)(0xb9 << 24 | 0x29 << 16) // cipher +#define KMF_ZOPC (unsigned int)(0xb9 << 24 | 0x2a << 16) // cipher +#define KMCTR_ZOPC (unsigned int)(0xb9 << 24 | 0x2d << 16) // cipher +#define KMO_ZOPC (unsigned int)(0xb9 << 24 | 0x2b << 16) // cipher #define KIMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3e << 16) // SHA (msg digest) #define KLMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3f << 16) // SHA (msg digest) #define KMAC_ZOPC (unsigned int)(0xb9 << 24 | 0x1e << 16) // Message Authentication Code @@ -2389,12 +2393,16 @@ // Complex CISC instructions // ========================== - inline void z_cksm(Register r1, Register r2); // checksum. This is NOT CRC32 - inline void z_km( Register r1, Register r2); // cipher message - inline void z_kmc( Register r1, Register r2); // cipher message with chaining - inline void z_kimd(Register r1, Register r2); // msg digest (SHA) - inline void z_klmd(Register r1, Register r2); // msg digest (SHA) - inline void z_kmac(Register r1, Register r2); // msg authentication code + inline void z_cksm( Register r1, Register r2); // checksum. This is NOT CRC32 + inline void z_km( Register r1, Register r2); // cipher message + inline void z_kmc( Register r1, Register r2); // cipher message with chaining + inline void z_kma( Register r1, Register r3, Register r2); // cipher message with authentication + inline void z_kmf( Register r1, Register r2); // cipher message with cipher feedback + inline void z_kmctr(Register r1, Register r3, Register r2); // cipher message with counter + inline void z_kmo( Register r1, Register r2); // cipher message with output feedback + inline void z_kimd( Register r1, Register r2); // msg digest (SHA) + inline void z_klmd( Register r1, Register r2); // msg digest (SHA) + inline void z_kmac( Register r1, Register r2); // msg authentication code inline void z_ex(Register r1, int64_t d2, Register x2, Register b2);// execute inline void z_exrl(Register r1, int64_t i2); // execute relative long -- z10 @@ -3030,8 +3038,8 @@ inline void z_bvat(Label& L); // all true inline void z_bvnt(Label& L); // not all true (mixed or all false) inline void z_bvmix(Label& L); // mixed true and false - inline void z_bvaf(Label& L); // not all false (mixed or all true) - inline void z_bvnf(Label& L); // all false + inline void z_bvnf(Label& L); // not all false (mixed or all true) + inline void z_bvaf(Label& L); // all false inline void z_brno( Label& L);
diff --git a/src/hotspot/cpu/s390/assembler_s390.inline.hpp b/src/hotspot/cpu/s390/assembler_s390.inline.hpp index b96bd17f..ea096fb 100644 --- a/src/hotspot/cpu/s390/assembler_s390.inline.hpp +++ b/src/hotspot/cpu/s390/assembler_s390.inline.hpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2016, 2017 SAP SE. All rights reserved. + * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2016, 2021 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -90,15 +90,19 @@ inline void Assembler::z_llgfrl(Register r1, int64_t i2){ emit_48( LLGFRL_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); } inline void Assembler::z_sthrl(Register r1, int64_t i2) { emit_48( STHRL_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); } -inline void Assembler::z_strl(Register r1, int64_t i2) { emit_48( STRL_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); } +inline void Assembler::z_strl( Register r1, int64_t i2) { emit_48( STRL_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); } inline void Assembler::z_stgrl(Register r1, int64_t i2) { emit_48( STGRL_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); } -inline void Assembler::z_cksm(Register r1, Register r2) { emit_32( CKSM_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } -inline void Assembler::z_km( Register r1, Register r2) { emit_32( KM_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } -inline void Assembler::z_kmc( Register r1, Register r2) { emit_32( KMC_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } -inline void Assembler::z_kimd(Register r1, Register r2) { emit_32( KIMD_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } -inline void Assembler::z_klmd(Register r1, Register r2) { emit_32( KLMD_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } -inline void Assembler::z_kmac(Register r1, Register r2) { emit_32( KMAC_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } +inline void Assembler::z_cksm( Register r1, Register r2) { emit_32( CKSM_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } +inline void Assembler::z_km( Register r1, Register r2) { emit_32( KM_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } +inline void Assembler::z_kmc( Register r1, Register r2) { emit_32( KMC_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } +inline void Assembler::z_kma( Register r1, Register r3, Register r2) { emit_32( KMA_ZOPC | regt(r3, 16, 32) | regt(r1, 24, 32) | regt(r2, 28, 32)); } +inline void Assembler::z_kmf( Register r1, Register r2) { emit_32( KMF_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } +inline void Assembler::z_kmctr(Register r1, Register r3, Register r2) { emit_32( KMCTR_ZOPC | regt(r3, 16, 32) | regt(r1, 24, 32) | regt(r2, 28, 32)); } +inline void Assembler::z_kmo( Register r1, Register r2) { emit_32( KMO_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } +inline void Assembler::z_kimd( Register r1, Register r2) { emit_32( KIMD_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } +inline void Assembler::z_klmd( Register r1, Register r2) { emit_32( KLMD_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } +inline void Assembler::z_kmac( Register r1, Register r2) { emit_32( KMAC_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); } inline void Assembler::z_exrl(Register r1, int64_t i2) { emit_48( EXRL_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); } // z10 inline void Assembler::z_exrl(Register r1, address a2) { emit_48( EXRL_ZOPC | regt(r1, 8, 48) | simm32(RelAddr::pcrel_off32(a2, pc()), 16, 48)); } // z10 @@ -1383,6 +1387,7 @@ // The length as returned from instr_len() can only be 2, 4, or 6 bytes. // Having a default clause makes the compiler happy. ShouldNotReachHere(); + *instr = 0L; // This assignment is there to make gcc8 happy. break; } return len;
diff --git a/src/hotspot/cpu/s390/c1_FrameMap_s390.cpp b/src/hotspot/cpu/s390/c1_FrameMap_s390.cpp index f19b2d5..e0f44d0 100644 --- a/src/hotspot/cpu/s390/c1_FrameMap_s390.cpp +++ b/src/hotspot/cpu/s390/c1_FrameMap_s390.cpp
@@ -50,6 +50,8 @@ opr = as_oop_opr(reg); } else if (type == T_METADATA) { opr = as_metadata_opr(reg); + } else if (type == T_ADDRESS) { + opr = as_address_opr(reg); } else { opr = as_opr(reg); }
diff --git a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp index c7dbf91..897be22 100644 --- a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp +++ b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2016, 2017, SAP SE. All rights reserved. + * Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2016, 2019, SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -993,7 +993,7 @@ if (type == T_ARRAY || type == T_OBJECT) { __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true); __ verify_oop(dest->as_register()); - } else if (type == T_METADATA) { + } else if (type == T_METADATA || type == T_ADDRESS) { __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true); } else { __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), false); @@ -1021,7 +1021,7 @@ if (type == T_OBJECT || type == T_ARRAY) { __ verify_oop(src->as_register()); __ reg2mem_opt(src->as_register(), dst, true); - } else if (type == T_METADATA) { + } else if (type == T_METADATA || type == T_ADDRESS) { __ reg2mem_opt(src->as_register(), dst, true); } else { __ reg2mem_opt(src->as_register(), dst, false); @@ -1308,6 +1308,15 @@ } else { __ z_cfi(reg1, c->as_jint()); } + } else if (c->type() == T_METADATA) { + // We only need, for now, comparison with NULL for metadata. + assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); + Metadata* m = c->as_metadata(); + if (m == NULL) { + __ z_cghi(reg1, 0); + } else { + ShouldNotReachHere(); + } } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { // In 64bit oops are single register. jobject o = c->as_jobject(); @@ -1969,7 +1978,6 @@ return; } - Label done; // Save outgoing arguments in callee saved registers (C convention) in case // a call to System.arraycopy is needed. Register callee_saved_src = Z_R10; @@ -2141,7 +2149,7 @@ store_parameter(src_klass, 0); // sub store_parameter(dst_klass, 1); // super emit_call_c(Runtime1::entry_for (Runtime1::slow_subtype_check_id)); - CHECK_BAILOUT(); + CHECK_BAILOUT2(cont, slow); // Sets condition code 0 for match (2 otherwise). __ branch_optimized(Assembler::bcondEqual, cont); @@ -2200,7 +2208,7 @@ __ z_lg(Z_ARG5, Address(Z_ARG5, ObjArrayKlass::element_klass_offset())); __ z_lg(Z_ARG4, Address(Z_ARG5, Klass::super_check_offset_offset())); emit_call_c(copyfunc_addr); - CHECK_BAILOUT(); + CHECK_BAILOUT2(cont, slow); #ifndef PRODUCT if (PrintC1Statistics) { @@ -2555,7 +2563,7 @@ store_parameter(klass_RInfo, 0); // sub store_parameter(k_RInfo, 1); // super emit_call_c(a); // Sets condition code 0 for match (2 otherwise). - CHECK_BAILOUT(); + CHECK_BAILOUT2(profile_cast_failure, profile_cast_success); __ branch_optimized(Assembler::bcondNotEqual, *failure_target); // Fall through to success case. } @@ -2638,7 +2646,7 @@ store_parameter(klass_RInfo, 0); // sub store_parameter(k_RInfo, 1); // super emit_call_c(a); // Sets condition code 0 for match (2 otherwise). - CHECK_BAILOUT(); + CHECK_BAILOUT3(profile_cast_success, profile_cast_failure, done); __ branch_optimized(Assembler::bcondNotEqual, *failure_target); // Fall through to success case.
diff --git a/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp b/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp index 267ab51..ae297ac 100644 --- a/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp +++ b/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp
@@ -223,7 +223,7 @@ __ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info); } -bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) { +bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { if (tmp->is_valid()) { if (is_power_of_2(c + 1)) { __ move(left, tmp);
diff --git a/src/hotspot/cpu/s390/compiledIC_s390.cpp b/src/hotspot/cpu/s390/compiledIC_s390.cpp index 32b8b5c..51e13b1 100644 --- a/src/hotspot/cpu/s390/compiledIC_s390.cpp +++ b/src/hotspot/cpu/s390/compiledIC_s390.cpp
@@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2016 SAP SE. All rights reserved. + * Copyright (c) 2016, 2019, SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -75,6 +75,7 @@ return stub; #else ShouldNotReachHere(); + return NULL; #endif } @@ -119,7 +120,7 @@ #endif // Update stub. - method_holder->set_data((intptr_t)callee()); + method_holder->set_data((intptr_t)callee(), relocInfo::metadata_type); jump->set_jump_destination(entry); // Update jump to call. @@ -134,7 +135,7 @@ // Creation also verifies the object. NativeMovConstReg* method_holder = nativeMovConstReg_at(stub + NativeCall::get_IC_pos_in_java_to_interp_stub()); NativeJump* jump = nativeJump_at(method_holder->next_instruction_address()); - method_holder->set_data(0); + method_holder->set_data(0, relocInfo::metadata_type); jump->set_jump_destination((address)-1); }
diff --git a/src/hotspot/cpu/s390/copy_s390.hpp b/src/hotspot/cpu/s390/copy_s390.hpp index c7eb27d..357285f 100644 --- a/src/hotspot/cpu/s390/copy_s390.hpp +++ b/src/hotspot/cpu/s390/copy_s390.hpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2016 SAP SE. All rights reserved. + * Copyright (c) 2016, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2016, 2020 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -1095,12 +1095,6 @@ pd_zero_to_bytes(tohw, count*HeapWordSize); } -// Delegate to pd_zero_to_bytes. It also works HeapWord-atomic. -static void pd_zero_to_words_large(HeapWord* tohw, size_t count) { - // JVM2008: generally frequent, some tests show very frequent calls. - pd_zero_to_bytes(tohw, count*HeapWordSize); -} - static void pd_zero_to_bytes(void* to, size_t count) { // JVM2008: some calls (generally), some tests frequent #ifdef USE_INLINE_ASM
diff --git a/src/hotspot/cpu/s390/globals_s390.hpp b/src/hotspot/cpu/s390/globals_s390.hpp index 2354e5a..96f2da0 100644 --- a/src/hotspot/cpu/s390/globals_s390.hpp +++ b/src/hotspot/cpu/s390/globals_s390.hpp
@@ -33,8 +33,6 @@ // (see globals.hpp) // Sorted according to sparc. -// z/Architecture remembers branch targets, so don't share vtables. -define_pd_global(bool, ShareVtableStubs, true); define_pd_global(bool, NeedsDeoptSuspend, false); // Only register window machines need this. define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks. @@ -55,7 +53,7 @@ #define DEFAULT_STACK_RED_PAGES (1) // Java_java_net_SocketOutputStream_socketWrite0() uses a 64k buffer on the // stack. To pass stack overflow tests we need 20 shadow pages. -#define DEFAULT_STACK_SHADOW_PAGES (20 DEBUG_ONLY(+2)) +#define DEFAULT_STACK_SHADOW_PAGES (20 DEBUG_ONLY(+4)) #define DEFAULT_STACK_RESERVED_PAGES (1) #define MIN_STACK_YELLOW_PAGES DEFAULT_STACK_YELLOW_PAGES
diff --git a/src/hotspot/cpu/s390/interp_masm_s390.cpp b/src/hotspot/cpu/s390/interp_masm_s390.cpp index 957fd0d..5143dc4 100644 --- a/src/hotspot/cpu/s390/interp_masm_s390.cpp +++ b/src/hotspot/cpu/s390/interp_masm_s390.cpp
@@ -954,8 +954,7 @@ void InterpreterMacroAssembler::lock_object(Register monitor, Register object) { if (UseHeavyMonitors) { - call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorenter), - monitor, /*check_for_exceptions=*/false); + call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorenter), monitor); return; } @@ -1040,9 +1039,7 @@ // None of the above fast optimizations worked so we have to get into the // slow case of monitor enter. bind(slow_case); - - call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorenter), - monitor, /*check_for_exceptions=*/false); + call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorenter), monitor); // } @@ -1059,8 +1056,7 @@ void InterpreterMacroAssembler::unlock_object(Register monitor, Register object) { if (UseHeavyMonitors) { - call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorexit), - monitor, /*check_for_exceptions=*/ true); + call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorexit), monitor); return; } @@ -1134,8 +1130,7 @@ // The lock has been converted into a heavy lock and hence // we need to get into the slow case. z_stg(object, obj_entry); // Restore object entry, has been cleared above. - call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorexit), - monitor, /*check_for_exceptions=*/false); + call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorexit), monitor); // } @@ -1901,7 +1896,7 @@ load_and_test_long(Rcounters, Address(Rmethod, Method::method_counters_offset())); z_brnz(has_counters); - call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::build_method_counters), Rmethod, false); + call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::build_method_counters), Rmethod); z_ltgr(Rcounters, Z_RET); // Runtime call returns MethodCounters object. z_brz(skip); // No MethodCounters, out of memory. @@ -2082,7 +2077,7 @@ Label jvmti_post_done; MacroAssembler::load_and_test_int(Z_R0, Address(Z_thread, JavaThread::interp_only_mode_offset())); z_bre(jvmti_post_done); - call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::post_method_entry), /*check_exceptions=*/false); + call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::post_method_entry)); bind(jvmti_post_done); } } @@ -2116,7 +2111,7 @@ MacroAssembler::load_and_test_int(Z_R0, Address(Z_thread, JavaThread::interp_only_mode_offset())); z_bre(jvmti_post_done); if (!native_method) push(state); // see frame::interpreter_frame_result() - call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::post_method_exit), /*check_exceptions=*/false); + call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::post_method_exit)); if (!native_method) pop(state); bind(jvmti_post_done); }
diff --git a/src/hotspot/cpu/s390/macroAssembler_s390.cpp b/src/hotspot/cpu/s390/macroAssembler_s390.cpp index 001ebe5..58ed963 100644 --- a/src/hotspot/cpu/s390/macroAssembler_s390.cpp +++ b/src/hotspot/cpu/s390/macroAssembler_s390.cpp
@@ -37,9 +37,11 @@ #include "oops/accessDecorators.hpp" #include "oops/compressedOops.inline.hpp" #include "oops/klass.inline.hpp" +#ifdef COMPILER2 #include "opto/compile.hpp" #include "opto/intrinsicnode.hpp" #include "opto/matcher.hpp" +#endif #include "prims/methodHandles.hpp" #include "registerSaver_s390.hpp" #include "runtime/biasedLocking.hpp" @@ -2952,7 +2954,7 @@ } void MacroAssembler::nmethod_UEP(Label& ic_miss) { - Register ic_reg = as_Register(Matcher::inline_cache_reg_encode()); + Register ic_reg = Z_inline_cache; int klass_offset = oopDesc::klass_offset_in_bytes(); if (!ImplicitNullChecks || MacroAssembler::needs_explicit_null_check(klass_offset)) { if (VM_Version::has_CompareBranch()) { @@ -4598,6 +4600,7 @@ return block_end - block_start; } +#ifdef COMPILER2 //------------------------------------------------------ // Special String Intrinsics. Implementation //------------------------------------------------------ @@ -5845,7 +5848,7 @@ return offset() - block_start; } - +#endif //------------------------------------------------- // Constants (scalar and oop) in constant pool @@ -5899,7 +5902,7 @@ if (tocOffset == -1) return false; address tocPos = tocOffset + code()->consts()->start(); assert((address)code()->consts()->start() != NULL, "Please add CP address"); - + relocate(a.rspec()); load_long_pcrelative(dst, tocPos); return true; } @@ -6158,96 +6161,6 @@ Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry); } - -void MacroAssembler::generate_type_profiling(const Register Rdata, - const Register Rreceiver_klass, - const Register Rwanted_receiver_klass, - const Register Rmatching_row, - bool is_virtual_call) { - const int row_size = in_bytes(ReceiverTypeData::receiver_offset(1)) - - in_bytes(ReceiverTypeData::receiver_offset(0)); - const int num_rows = ReceiverTypeData::row_limit(); - NearLabel found_free_row; - NearLabel do_increment; - NearLabel found_no_slot; - - BLOCK_COMMENT("type profiling {"); - - // search for: - // a) The type given in Rwanted_receiver_klass. - // b) The *first* empty row. - - // First search for a) only, just running over b) with no regard. - // This is possible because - // wanted_receiver_class == receiver_class && wanted_receiver_class == 0 - // is never true (receiver_class can't be zero). - for (int row_num = 0; row_num < num_rows; row_num++) { - // Row_offset should be a well-behaved positive number. The generated code relies - // on that wrt constant code size. Add2reg can handle all row_offset values, but - // will have to vary generated code size. - int row_offset = in_bytes(ReceiverTypeData::receiver_offset(row_num)); - assert(Displacement::is_shortDisp(row_offset), "Limitation of generated code"); - - // Is Rwanted_receiver_klass in this row? - if (VM_Version::has_CompareBranch()) { - z_lg(Rwanted_receiver_klass, row_offset, Z_R0, Rdata); - // Rmatching_row = Rdata + row_offset; - add2reg(Rmatching_row, row_offset, Rdata); - // if (*row_recv == (intptr_t) receiver_klass) goto fill_existing_slot; - compare64_and_branch(Rwanted_receiver_klass, Rreceiver_klass, Assembler::bcondEqual, do_increment); - } else { - add2reg(Rmatching_row, row_offset, Rdata); - z_cg(Rreceiver_klass, row_offset, Z_R0, Rdata); - z_bre(do_increment); - } - } - - // Now that we did not find a match, let's search for b). - - // We could save the first calculation of Rmatching_row if we woud search for a) in reverse order. - // We would then end up here with Rmatching_row containing the value for row_num == 0. - // We would not see much benefit, if any at all, because the CPU can schedule - // two instructions together with a branch anyway. - for (int row_num = 0; row_num < num_rows; row_num++) { - int row_offset = in_bytes(ReceiverTypeData::receiver_offset(row_num)); - - // Has this row a zero receiver_klass, i.e. is it empty? - if (VM_Version::has_CompareBranch()) { - z_lg(Rwanted_receiver_klass, row_offset, Z_R0, Rdata); - // Rmatching_row = Rdata + row_offset - add2reg(Rmatching_row, row_offset, Rdata); - // if (*row_recv == (intptr_t) 0) goto found_free_row - compare64_and_branch(Rwanted_receiver_klass, (intptr_t)0, Assembler::bcondEqual, found_free_row); - } else { - add2reg(Rmatching_row, row_offset, Rdata); - load_and_test_long(Rwanted_receiver_klass, Address(Rdata, row_offset)); - z_bre(found_free_row); // zero -> Found a free row. - } - } - - // No match, no empty row found. - // Increment total counter to indicate polymorphic case. - if (is_virtual_call) { - add2mem_64(Address(Rdata, CounterData::count_offset()), 1, Rmatching_row); - } - z_bru(found_no_slot); - - // Here we found an empty row, but we have not found Rwanted_receiver_klass. - // Rmatching_row holds the address to the first empty row. - bind(found_free_row); - // Store receiver_klass into empty slot. - z_stg(Rreceiver_klass, 0, Z_R0, Rmatching_row); - - // Increment the counter of Rmatching_row. - bind(do_increment); - ByteSize counter_offset = ReceiverTypeData::receiver_count_offset(0) - ReceiverTypeData::receiver_offset(0); - add2mem_64(Address(Rmatching_row, counter_offset), 1, Rdata); - - bind(found_no_slot); - - BLOCK_COMMENT("} type profiling"); -} - //--------------------------------------- // Helpers for Intrinsic Emitters //---------------------------------------
diff --git a/src/hotspot/cpu/s390/macroAssembler_s390.hpp b/src/hotspot/cpu/s390/macroAssembler_s390.hpp index daf71f7..8782177 100644 --- a/src/hotspot/cpu/s390/macroAssembler_s390.hpp +++ b/src/hotspot/cpu/s390/macroAssembler_s390.hpp
@@ -851,6 +851,7 @@ // Kills: tmp, Z_R0, Z_R1. // Early clobber: result. // Boolean precise controls accuracy of result value. +#ifdef COMPILER2 unsigned int string_compress(Register result, Register src, Register dst, Register cnt, Register tmp, bool precise); @@ -886,6 +887,7 @@ unsigned int string_indexof_char(Register result, Register haystack, Register haycnt, Register needle, jchar needleChar, Register odd_reg, Register even_reg, bool is_byte); +#endif // Emit an oop const to the constant pool and set a relocation info // with address current_pc. Return the TOC offset of the constant. @@ -919,13 +921,6 @@ // Offset is +/- 2**32 -> use long. static long get_load_const_from_toc_offset(address a); - - void generate_type_profiling(const Register Rdata, - const Register Rreceiver_klass, - const Register Rwanted_receiver_klass, - const Register Rmatching_row, - bool is_virtual_call); - // Bit operations for single register operands. inline void lshift(Register r, int places, bool doubl = true); // << inline void rshift(Register r, int places, bool doubl = true); // >>
diff --git a/src/hotspot/cpu/s390/nativeInst_s390.cpp b/src/hotspot/cpu/s390/nativeInst_s390.cpp index 6d3eccd..62697e0 100644 --- a/src/hotspot/cpu/s390/nativeInst_s390.cpp +++ b/src/hotspot/cpu/s390/nativeInst_s390.cpp
@@ -475,12 +475,42 @@ // Divided up in set_data_plain() which patches the instruction in the // code stream and set_data() which additionally patches the oop pool // if necessary. -void NativeMovConstReg::set_data(intptr_t src) { +void NativeMovConstReg::set_data(intptr_t data, relocInfo::relocType expected_type) { // Also store the value into an oop_Relocation cell, if any. CodeBlob *cb = CodeCache::find_blob(instruction_address()); - address next_address = set_data_plain(src, cb); + address next_address = set_data_plain(data, cb); - relocInfo::update_oop_pool(instruction_address(), next_address, (address)src, cb); + // 'RelocIterator' requires an nmethod + nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL; + if (nm != NULL) { + RelocIterator iter(nm, instruction_address(), next_address); + oop* oop_addr = NULL; + Metadata** metadata_addr = NULL; + while (iter.next()) { + if (iter.type() == relocInfo::oop_type) { + oop_Relocation *r = iter.oop_reloc(); + if (oop_addr == NULL) { + oop_addr = r->oop_addr(); + *oop_addr = cast_to_oop(data); + } else { + assert(oop_addr == r->oop_addr(), "must be only one set-oop here"); + } + } + if (iter.type() == relocInfo::metadata_type) { + metadata_Relocation *r = iter.metadata_reloc(); + if (metadata_addr == NULL) { + metadata_addr = r->metadata_addr(); + *metadata_addr = (Metadata*)data; + } else { + assert(metadata_addr == r->metadata_addr(), "must be only one set-metadata here"); + } + } + } + assert(expected_type == relocInfo::none || + (expected_type == relocInfo::metadata_type && metadata_addr != NULL) || + (expected_type == relocInfo::oop_type && oop_addr != NULL), + "%s relocation not found", expected_type == relocInfo::oop_type ? "oop" : "metadata"); + } } void NativeMovConstReg::set_narrow_oop(intptr_t data) { @@ -510,7 +540,7 @@ ICache::invalidate_range(start, range); } -void NativeMovConstReg::set_pcrel_addr(intptr_t newTarget, CompiledMethod *passed_nm /* = NULL */, bool copy_back_to_oop_pool) { +void NativeMovConstReg::set_pcrel_addr(intptr_t newTarget, CompiledMethod *passed_nm /* = NULL */) { address next_address; address loc = addr_at(0); @@ -533,20 +563,9 @@ assert(false, "Not a NativeMovConstReg site for set_pcrel_addr"); next_address = next_instruction_address(); // Failure should be handled in next_instruction_address(). } - - if (copy_back_to_oop_pool) { - if (relocInfo::update_oop_pool(instruction_address(), next_address, (address)newTarget, NULL)) { - ((NativeMovConstReg*)instruction_address())->dump(64, "NativeMovConstReg::set_pcrel_addr(): found oop reloc for pcrel_addr"); -#ifdef LUCY_DBG - VM_Version::z_SIGSEGV(); -#else - assert(false, "Ooooops: found oop reloc for pcrel_addr"); -#endif - } - } } -void NativeMovConstReg::set_pcrel_data(intptr_t newData, CompiledMethod *passed_nm /* = NULL */, bool copy_back_to_oop_pool) { +void NativeMovConstReg::set_pcrel_data(intptr_t newData, CompiledMethod *passed_nm /* = NULL */) { address next_address; address loc = addr_at(0); @@ -573,17 +592,6 @@ assert(false, "Not a NativeMovConstReg site for set_pcrel_data"); next_address = next_instruction_address(); // Failure should be handled in next_instruction_address(). } - - if (copy_back_to_oop_pool) { - if (relocInfo::update_oop_pool(instruction_address(), next_address, (address)newData, NULL)) { - ((NativeMovConstReg*)instruction_address())->dump(64, "NativeMovConstReg::set_pcrel_data(): found oop reloc for pcrel_data"); -#ifdef LUCY_DBG - VM_Version::z_SIGSEGV(); -#else - assert(false, "Ooooops: found oop reloc for pcrel_data"); -#endif - } - } } #ifdef COMPILER1 @@ -593,7 +601,6 @@ void NativeMovRegMem::verify() { address l1 = addr_at(0); - address l2 = addr_at(MacroAssembler::load_const_size()); if (!MacroAssembler::is_load_const(l1)) { tty->cr(); @@ -602,32 +609,6 @@ ((NativeMovRegMem*)l1)->dump(64, "NativeMovConstReg::verify()"); fatal("this is not a `NativeMovRegMem' site"); } - - unsigned long inst1; - Assembler::get_instruction(l2, &inst1); - - if (!Assembler::is_z_lb(inst1) && - !Assembler::is_z_llgh(inst1) && - !Assembler::is_z_lh(inst1) && - !Assembler::is_z_l(inst1) && - !Assembler::is_z_llgf(inst1) && - !Assembler::is_z_lg(inst1) && - !Assembler::is_z_le(inst1) && - !Assembler::is_z_ld(inst1) && - !Assembler::is_z_stc(inst1) && - !Assembler::is_z_sth(inst1) && - !Assembler::is_z_st(inst1) && - !UseCompressedOops && - !Assembler::is_z_stg(inst1) && - !Assembler::is_z_ste(inst1) && - !Assembler::is_z_std(inst1)) { - tty->cr(); - tty->print_cr("NativeMovRegMem::verify(): verifying addr " PTR_FORMAT - ": wrong or missing load or store at " PTR_FORMAT, p2i(l1), p2i(l2)); - tty->cr(); - ((NativeMovRegMem*)l1)->dump(64, "NativeMovConstReg::verify()"); - fatal("this is not a `NativeMovRegMem' site"); - } } #endif // COMPILER1
diff --git a/src/hotspot/cpu/s390/nativeInst_s390.hpp b/src/hotspot/cpu/s390/nativeInst_s390.hpp index 5a7a8a2..6763192 100644 --- a/src/hotspot/cpu/s390/nativeInst_s390.hpp +++ b/src/hotspot/cpu/s390/nativeInst_s390.hpp
@@ -496,13 +496,13 @@ // Patch data in code stream. address set_data_plain(intptr_t x, CodeBlob *code); // Patch data in code stream and oop pool if necessary. - void set_data(intptr_t x); + void set_data(intptr_t x, relocInfo::relocType expected_type = relocInfo::none); // Patch narrow oop constant in code stream. void set_narrow_oop(intptr_t data); void set_narrow_klass(intptr_t data); - void set_pcrel_addr(intptr_t addr, CompiledMethod *nm = NULL, bool copy_back_to_oop_pool=false); - void set_pcrel_data(intptr_t data, CompiledMethod *nm = NULL, bool copy_back_to_oop_pool=false); + void set_pcrel_addr(intptr_t addr, CompiledMethod *nm = NULL); + void set_pcrel_data(intptr_t data, CompiledMethod *nm = NULL); void verify(); @@ -534,13 +534,19 @@ // The instruction sequence looks like this: // iihf %r1,$bits1 ; load offset for mem access // iilf %r1,$bits2 -// [compress oop] ; optional, load only +// [compress oop] ; optional, store only // load/store %r2,0(%r1,%r2) ; memory access class NativeMovRegMem; inline NativeMovRegMem* nativeMovRegMem_at (address address); class NativeMovRegMem: public NativeInstruction { public: + enum z_specific_constants { + instruction_size = 12 // load_const used with access_field_id + }; + + int num_bytes_to_end_of_patch() const { return instruction_size; } + intptr_t offset() const { return nativeMovConstReg_at(addr_at(0))->data(); }
diff --git a/src/hotspot/cpu/s390/register_s390.hpp b/src/hotspot/cpu/s390/register_s390.hpp index f8f218e..b5f5d11 100644 --- a/src/hotspot/cpu/s390/register_s390.hpp +++ b/src/hotspot/cpu/s390/register_s390.hpp
@@ -1,6 +1,6 @@ /* * Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2016, 2017 SAP SE. All rights reserved. + * Copyright (c) 2016, 2019 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -27,7 +27,7 @@ #define CPU_S390_VM_REGISTER_S390_HPP #include "asm/register.hpp" -#include "vm_version_s390.hpp" +#include "runtime/vm_version.hpp" class Address; class VMRegImpl;
diff --git a/src/hotspot/cpu/s390/relocInfo_s390.cpp b/src/hotspot/cpu/s390/relocInfo_s390.cpp index fd1437c..9fcefd7 100644 --- a/src/hotspot/cpu/s390/relocInfo_s390.cpp +++ b/src/hotspot/cpu/s390/relocInfo_s390.cpp
@@ -164,49 +164,6 @@ } -// store the new target address into an oop_Relocation cell, if any -// return indication if update happened. -bool relocInfo::update_oop_pool(address begin, address end, address newTarget, CodeBlob* cb) { - - // Try to find the CodeBlob, if not given by caller - if (cb == NULL) cb = CodeCache::find_blob(begin); -#ifdef ASSERT - else - assert(cb == CodeCache::find_blob(begin), "consistency"); -#endif - - // 'RelocIterator' requires an nmethod - nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL; - if (nm != NULL) { - RelocIterator iter(nm, begin, end); - oop* oop_addr = NULL; - Metadata** metadata_addr = NULL; - while (iter.next()) { - if (iter.type() == relocInfo::oop_type) { - oop_Relocation *r = iter.oop_reloc(); - if (oop_addr == NULL) { - oop_addr = r->oop_addr(); - *oop_addr = (oop)newTarget; - } else { - assert(oop_addr == r->oop_addr(), "must be only one set-oop here"); - } - } - if (iter.type() == relocInfo::metadata_type) { - metadata_Relocation *r = iter.metadata_reloc(); - if (metadata_addr == NULL) { - metadata_addr = r->metadata_addr(); - *metadata_addr = (Metadata*)newTarget; - } else { - assert(metadata_addr == r->metadata_addr(), "must be only one set-metadata here"); - } - } - } - return oop_addr || metadata_addr; - } - return false; -} - - address* Relocation::pd_address_in_code() { ShouldNotReachHere(); return 0;
diff --git a/src/hotspot/cpu/s390/relocInfo_s390.hpp b/src/hotspot/cpu/s390/relocInfo_s390.hpp index ba9d40b..529f2b6 100644 --- a/src/hotspot/cpu/s390/relocInfo_s390.hpp +++ b/src/hotspot/cpu/s390/relocInfo_s390.hpp
@@ -114,8 +114,4 @@ // listed in the oop section. static bool mustIterateImmediateOopsInCode() { return false; } - // Store the new target address into an oop_Relocation cell, if any. - // Return indication if update happened. - static bool update_oop_pool(address begin, address end, address newTarget, CodeBlob* cb); - #endif // CPU_S390_VM_RELOCINFO_S390_HPP
diff --git a/src/hotspot/cpu/s390/s390.ad b/src/hotspot/cpu/s390/s390.ad index e20bcd8..e335f47 100644 --- a/src/hotspot/cpu/s390/s390.ad +++ b/src/hotspot/cpu/s390/s390.ad
@@ -9823,9 +9823,12 @@ instruct ShouldNotReachHere() %{ match(Halt); ins_cost(CALL_COST); - size(2); format %{ "ILLTRAP; ShouldNotReachHere" %} - ins_encode %{ __ z_illtrap(); %} + ins_encode %{ + if (is_reachable()) { + __ z_illtrap(); + } + %} ins_pipe(pipe_class_dummy); %}
diff --git a/src/hotspot/cpu/s390/sharedRuntime_s390.cpp b/src/hotspot/cpu/s390/sharedRuntime_s390.cpp index aad5907..6d24fff 100644 --- a/src/hotspot/cpu/s390/sharedRuntime_s390.cpp +++ b/src/hotspot/cpu/s390/sharedRuntime_s390.cpp
@@ -32,6 +32,7 @@ #include "interpreter/interpreter.hpp" #include "interpreter/interp_masm.hpp" #include "memory/resourceArea.hpp" +#include "nativeInst_s390.hpp" #include "oops/compiledICHolder.hpp" #include "registerSaver_s390.hpp" #include "runtime/safepointMechanism.hpp" @@ -1512,8 +1513,8 @@ int compile_id, BasicType *in_sig_bt, VMRegPair *in_regs, - BasicType ret_type) { -#ifdef COMPILER2 + BasicType ret_type, + address critical_entry) { int total_in_args = method->size_of_parameters(); if (method->is_method_handle_intrinsic()) { vmIntrinsics::ID iid = method->intrinsic_id(); @@ -1548,7 +1549,7 @@ /////////////////////////////////////////////////////////////////////// bool is_critical_native = true; - address native_func = method->critical_native_function(); + address native_func = critical_entry; if (native_func == NULL) { native_func = method->native_function(); is_critical_native = false; @@ -2389,10 +2390,6 @@ } return nm; -#else - ShouldNotReachHere(); - return NULL; -#endif // COMPILER2 } static address gen_c2i_adapter(MacroAssembler *masm, @@ -2846,7 +2843,7 @@ // to Deoptimization::fetch_unroll_info below. // The (int) cast is necessary, because -((unsigned int)14) // is an unsigned int. - __ add2reg(Z_R14, -(int)HandlerImpl::size_deopt_handler()); + __ add2reg(Z_R14, -(int)NativeCall::max_instruction_size()); const Register exec_mode_reg = Z_tmp_1;
diff --git a/src/hotspot/cpu/s390/templateTable_s390.cpp b/src/hotspot/cpu/s390/templateTable_s390.cpp index 4306247..5f6c7f2 100644 --- a/src/hotspot/cpu/s390/templateTable_s390.cpp +++ b/src/hotspot/cpu/s390/templateTable_s390.cpp
@@ -2010,7 +2010,7 @@ // Out-of-line code runtime calls. if (UseLoopCounter) { - if (ProfileInterpreter) { + if (ProfileInterpreter && !TieredCompilation) { // Out-of-line code to allocate method data oop. __ bind(profile_method); @@ -3815,9 +3815,8 @@ // Get instance_size in InstanceKlass (scaled to a count of bytes). Register Rsize = offset; - const int mask = 1 << Klass::_lh_instance_slow_path_bit; __ z_llgf(Rsize, Address(iklass, Klass::layout_helper_offset())); - __ z_tmll(Rsize, mask); + __ z_tmll(Rsize, Klass::_lh_instance_slow_path_bit); __ z_btrue(slow_case); // Allocate the instance
diff --git a/src/hotspot/cpu/s390/vm_version_ext_s390.cpp b/src/hotspot/cpu/s390/vm_version_ext_s390.cpp index dd4a721..2be9d1c 100644 --- a/src/hotspot/cpu/s390/vm_version_ext_s390.cpp +++ b/src/hotspot/cpu/s390/vm_version_ext_s390.cpp
@@ -46,7 +46,7 @@ _no_of_threads = _no_of_cores; _no_of_sockets = _no_of_cores; snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE, "s390 %s", VM_Version::get_model_string()); - snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "zArch %s", features_string()); + snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "s390 %s", features_string()); _initialized = true; }
diff --git a/src/hotspot/cpu/s390/vm_version_ext_s390.hpp b/src/hotspot/cpu/s390/vm_version_ext_s390.hpp index dc18303..30d6452 100644 --- a/src/hotspot/cpu/s390/vm_version_ext_s390.hpp +++ b/src/hotspot/cpu/s390/vm_version_ext_s390.hpp
@@ -25,8 +25,8 @@ #ifndef CPU_S390_VM_VM_VERSION_EXT_S390_HPP #define CPU_S390_VM_VM_VERSION_EXT_S390_HPP +#include "runtime/vm_version.hpp" #include "utilities/macros.hpp" -#include "vm_version_s390.hpp" #define CPU_INFO "cpu_info" #define CPU_TYPE "fpu_type"
diff --git a/src/hotspot/cpu/s390/vm_version_s390.cpp b/src/hotspot/cpu/s390/vm_version_s390.cpp index 5fd2392..80a2a32 100644 --- a/src/hotspot/cpu/s390/vm_version_s390.cpp +++ b/src/hotspot/cpu/s390/vm_version_s390.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2016, 2019 SAP SE. All rights reserved. + * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2016, 2021 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -31,37 +31,74 @@ #include "memory/resourceArea.hpp" #include "runtime/java.hpp" #include "runtime/stubCodeGenerator.hpp" -#include "vm_version_s390.hpp" +#include "runtime/vm_version.hpp" # include <sys/sysinfo.h> bool VM_Version::_is_determine_features_test_running = false; const char* VM_Version::_model_string; -unsigned long VM_Version::_features[_features_buffer_len] = {0, 0, 0, 0}; -unsigned long VM_Version::_cipher_features[_features_buffer_len] = {0, 0, 0, 0}; -unsigned long VM_Version::_msgdigest_features[_features_buffer_len] = {0, 0, 0, 0}; -unsigned int VM_Version::_nfeatures = 0; -unsigned int VM_Version::_ncipher_features = 0; -unsigned int VM_Version::_nmsgdigest_features = 0; -unsigned int VM_Version::_Dcache_lineSize = 256; -unsigned int VM_Version::_Icache_lineSize = 256; +unsigned long VM_Version::_features[_features_buffer_len] = {0, 0, 0, 0}; +unsigned long VM_Version::_cipher_features_KM[_features_buffer_len] = {0, 0, 0, 0}; +unsigned long VM_Version::_cipher_features_KMA[_features_buffer_len] = {0, 0, 0, 0}; +unsigned long VM_Version::_cipher_features_KMF[_features_buffer_len] = {0, 0, 0, 0}; +unsigned long VM_Version::_cipher_features_KMCTR[_features_buffer_len] = {0, 0, 0, 0}; +unsigned long VM_Version::_cipher_features_KMO[_features_buffer_len] = {0, 0, 0, 0}; +unsigned long VM_Version::_msgdigest_features[_features_buffer_len] = {0, 0, 0, 0}; +unsigned int VM_Version::_nfeatures = 0; +unsigned int VM_Version::_ncipher_features_KM = 0; +unsigned int VM_Version::_ncipher_features_KMA = 0; +unsigned int VM_Version::_ncipher_features_KMF = 0; +unsigned int VM_Version::_ncipher_features_KMCTR = 0; +unsigned int VM_Version::_ncipher_features_KMO = 0; +unsigned int VM_Version::_nmsgdigest_features = 0; +unsigned int VM_Version::_Dcache_lineSize = DEFAULT_CACHE_LINE_SIZE; +unsigned int VM_Version::_Icache_lineSize = DEFAULT_CACHE_LINE_SIZE; -static const char* z_gen[] = {" ", "G1", "G2", "G3", "G4", "G5", "G6", "G7" }; -static const char* z_machine[] = {" ", "2064", "2084", "2094", "2097", "2817", " ", "2964" }; -static const char* z_name[] = {" ", "z900", "z990", "z9 EC", "z10 EC", "z196 EC", "ec12", "z13" }; +// The following list contains the (approximate) announcement/availability +// dates of the many System z generations in existence as of now. +// Information compiled from https://www.ibm.com/support/techdocs/atsmastr.nsf/WebIndex/TD105503 +// z900: 2000-10 +// z990: 2003-06 +// z9: 2005-09 +// z10: 2007-04 +// z10: 2008-02 +// z196: 2010-08 +// ec12: 2012-09 +// z13: 2015-03 +// z14: 2017-09 +// z15: 2019-09 + +static const char* z_gen[] = {" ", "G1", "G2", "G3", "G4", "G5", "G6", "G7", "G8", "G9" }; +static const char* z_machine[] = {" ", "2064", "2084", "2094", "2097", "2817", "2827", "2964", "3906", "8561" }; +static const char* z_name[] = {" ", "z900", "z990", "z9 EC", "z10 EC", "z196 EC", "ec12", "z13", "z14", "z15" }; +static const char* z_WDFM[] = {" ", "2006-06-30", "2008-06-30", "2010-06-30", "2012-06-30", "2014-06-30", "2016-12-31", "2019-06-30", "2021-06-30", "tbd" }; +static const char* z_EOS[] = {" ", "2014-12-31", "2014-12-31", "2017-10-31", "2019-12-31", "2021-12-31", "tbd", "tbd", "tbd", "tbd" }; +static const char* z_features[] = {" ", + "system-z, g1-z900, ldisp", + "system-z, g2-z990, ldisp_fast", + "system-z, g3-z9, ldisp_fast, extimm", + "system-z, g4-z10, ldisp_fast, extimm, pcrel_load/store, cmpb", + "system-z, g5-z196, ldisp_fast, extimm, pcrel_load/store, cmpb, cond_load/store, interlocked_update", + "system-z, g6-ec12, ldisp_fast, extimm, pcrel_load/store, cmpb, cond_load/store, interlocked_update, txm", + "system-z, g7-z13, ldisp_fast, extimm, pcrel_load/store, cmpb, cond_load/store, interlocked_update, txm, vectorinstr", + "system-z, g8-z14, ldisp_fast, extimm, pcrel_load/store, cmpb, cond_load/store, interlocked_update, txm, vectorinstr, instrext2, venh1)", + "system-z, g9-z15, ldisp_fast, extimm, pcrel_load/store, cmpb, cond_load/store, interlocked_update, txm, vectorinstr, instrext2, venh1, instrext3, VEnh2 )" + }; void VM_Version::initialize() { determine_features(); // Get processor capabilities. set_features_string(); // Set a descriptive feature indication. - if (Verbose) { - print_features(); + if (Verbose || PrintAssembly || PrintStubCode) { + print_features_internal("CPU Version as detected internally:", PrintAssembly || PrintStubCode); } intx cache_line_size = Dcache_lineSize(0); +#ifdef COMPILER2 MaxVectorSize = 8; +#endif if (has_PrefetchRaw()) { if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { // not preset @@ -217,6 +254,7 @@ FLAG_SET_DEFAULT(UseSHA, false); } +#ifdef COMPILER2 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, true); } @@ -226,6 +264,7 @@ if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, true); } +#endif if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { FLAG_SET_DEFAULT(UsePopCountInstruction, true); } @@ -248,76 +287,104 @@ } -void VM_Version::set_features_string() { - - unsigned int ambiguity = 0; - _model_string = z_name[0]; +int VM_Version::get_model_index() { + // returns the index used to access the various model-dependent strings. + // > 0 valid (known) model detected. + // = 0 model not recognized, maybe not yet supported. + // < 0 model detection is ambiguous. The absolute value of the returned value + // is the index of the oldest detected model. + int ambiguity = 0; + int model_ix = 0; + if (is_z15()) { + model_ix = 9; + ambiguity++; + } + if (is_z14()) { + model_ix = 8; + ambiguity++; + } if (is_z13()) { - _features_string = "System z G7-z13 (LDISP_fast, ExtImm, PCrel Load/Store, CmpB, Cond Load/Store, Interlocked Update, TxM, VectorInstr)"; - _model_string = z_name[7]; + model_ix = 7; ambiguity++; } if (is_ec12()) { - _features_string = "System z G6-EC12 (LDISP_fast, ExtImm, PCrel Load/Store, CmpB, Cond Load/Store, Interlocked Update, TxM)"; - _model_string = z_name[6]; + model_ix = 6; ambiguity++; } if (is_z196()) { - _features_string = "System z G5-z196 (LDISP_fast, ExtImm, PCrel Load/Store, CmpB, Cond Load/Store, Interlocked Update)"; - _model_string = z_name[5]; + model_ix = 5; ambiguity++; } if (is_z10()) { - _features_string = "System z G4-z10 (LDISP_fast, ExtImm, PCrel Load/Store, CmpB)"; - _model_string = z_name[4]; + model_ix = 4; ambiguity++; } if (is_z9()) { - _features_string = "System z G3-z9 (LDISP_fast, ExtImm), out-of-support as of 2016-04-01"; - _model_string = z_name[3]; + model_ix = 3; ambiguity++; } if (is_z990()) { - _features_string = "System z G2-z990 (LDISP_fast), out-of-support as of 2014-07-01"; - _model_string = z_name[2]; + model_ix = 2; ambiguity++; } if (is_z900()) { - _features_string = "System z G1-z900 (LDISP), out-of-support as of 2014-07-01"; - _model_string = z_name[1]; + model_ix = 1; ambiguity++; } - if (ambiguity == 0) { - _features_string = "z/Architecture (unknown generation)"; - } else if (ambiguity > 1) { - tty->print_cr("*** WARNING *** Ambiguous z/Architecture detection, ambiguity = %d", ambiguity); - tty->print_cr(" oldest detected generation is %s", _features_string); - _features_string = "z/Architecture (ambiguous detection)"; + if (ambiguity > 1) { + model_ix = -model_ix; } + return model_ix; +} + + +void VM_Version::set_features_string() { + // A note on the _features_string format: + // There are jtreg tests checking the _features_string for various properties. + // For some strange reason, these tests require the string to contain + // only _lowercase_ characters. Keep that in mind when being surprised + // about the unusual notation of features - and when adding new ones. + // Features may have one comma at the end. + // Furthermore, use one, and only one, separator space between features. + // Multiple spaces are considered separate tokens, messing up everything. + + int model_ix = get_model_index(); + char buf[512]; + if (model_ix == 0) { + _model_string = "unknown model"; + strcpy(buf, "z/Architecture (unknown generation)"); + } else if (model_ix > 0) { + _model_string = z_name[model_ix]; + jio_snprintf(buf, sizeof(buf), "%s, out-of-support_as_of_", z_features[model_ix], z_EOS[model_ix]); + } else if (model_ix < 0) { + tty->print_cr("*** WARNING *** Ambiguous z/Architecture detection!"); + tty->print_cr(" oldest detected generation is %s", z_features[-model_ix]); + _model_string = "unknown model"; + strcpy(buf, "z/Architecture (ambiguous detection)"); + } + _features_string = os::strdup(buf); if (has_Crypto_AES()) { - char buf[256]; - assert(strlen(_features_string) + 4 + 3*4 + 1 < sizeof(buf), "increase buffer size"); - jio_snprintf(buf, sizeof(buf), "%s aes%s%s%s", // String 'aes' must be surrounded by spaces so that jtreg tests recognize it. + assert(strlen(_features_string) + 3*8 < sizeof(buf), "increase buffer size"); + jio_snprintf(buf, sizeof(buf), "%s%s%s%s", _features_string, - has_Crypto_AES128() ? " 128" : "", - has_Crypto_AES192() ? " 192" : "", - has_Crypto_AES256() ? " 256" : ""); + has_Crypto_AES128() ? ", aes128" : "", + has_Crypto_AES192() ? ", aes192" : "", + has_Crypto_AES256() ? ", aes256" : ""); + os::free((void *)_features_string); _features_string = os::strdup(buf); } if (has_Crypto_SHA()) { - char buf[256]; - assert(strlen(_features_string) + 4 + 2 + 2*4 + 6 + 1 < sizeof(buf), "increase buffer size"); - // String 'sha1' etc must be surrounded by spaces so that jtreg tests recognize it. - jio_snprintf(buf, sizeof(buf), "%s %s%s%s%s", + assert(strlen(_features_string) + 6 + 2*8 + 7 < sizeof(buf), "increase buffer size"); + jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s", _features_string, - has_Crypto_SHA1() ? " sha1" : "", - has_Crypto_SHA256() ? " sha256" : "", - has_Crypto_SHA512() ? " sha512" : "", - has_Crypto_GHASH() ? " ghash" : ""); - if (has_Crypto_AES()) { os::free((void *)_features_string); } + has_Crypto_SHA1() ? ", sha1" : "", + has_Crypto_SHA256() ? ", sha256" : "", + has_Crypto_SHA512() ? ", sha512" : "", + has_Crypto_GHASH() ? ", ghash" : ""); + os::free((void *)_features_string); _features_string = os::strdup(buf); } } @@ -348,11 +415,7 @@ } void VM_Version::print_features_internal(const char* text, bool print_anyway) { - tty->print_cr("%s %s", text, features_string()); - tty->print("%s", text); - for (unsigned int i = 0; i < _nfeatures; i++) { - tty->print(" 0x%16.16lx", _features[i]); - } + tty->print_cr("%s %s", text, features_string()); tty->cr(); if (Verbose || print_anyway) { @@ -382,7 +445,7 @@ if (has_Prefetch() ) tty->print_cr(" available: %s", "Prefetch"); if (has_MoveImmToMem() ) tty->print_cr(" available: %s", "Direct Moves Immediate to Memory"); if (has_MemWithImmALUOps() ) tty->print_cr(" available: %s", "Direct ALU Ops Memory .op. Immediate"); - if (has_ExtractCPUAttributes() ) tty->print_cr(" available: %s", "Extract CPU Atributes"); + if (has_ExtractCPUAttributes() ) tty->print_cr(" available: %s", "Extract CPU Attributes"); if (has_ExecuteExtensions() ) tty->print_cr("available: %s", "ExecuteExtensions"); if (has_FPSupportEnhancements() ) tty->print_cr("available: %s", "FPSupportEnhancements"); if (has_DecimalFloatingPoint() ) tty->print_cr("available: %s", "DecimalFloatingPoint"); @@ -398,7 +461,7 @@ if (has_CryptoExt3() ) tty->print_cr("available: %s", "Crypto Extensions 3"); if (has_CryptoExt4() ) tty->print_cr("available: %s", "Crypto Extensions 4"); // EC12 - if (has_MiscInstrExt() ) tty->print_cr("available: %s", "Miscelaneous Instruction Extensions"); + if (has_MiscInstrExt() ) tty->print_cr("available: %s", "Miscellaneous Instruction Extensions"); if (has_ExecutionHint() ) tty->print_cr(" available: %s", "Execution Hints (branch prediction)"); if (has_ProcessorAssist() ) tty->print_cr(" available: %s", "Processor Assists"); if (has_LoadAndTrap() ) tty->print_cr(" available: %s", "Load and Trap"); @@ -410,23 +473,27 @@ if (has_CryptoExt5() ) tty->print_cr("available: %s", "Crypto Extensions 5"); if (has_DFPPackedConversion() ) tty->print_cr("available: %s", "DFP Packed Conversions"); if (has_VectorFacility() ) tty->print_cr("available: %s", "Vector Facility"); - // test switches - if (has_TestFeature1Impl() ) tty->print_cr("available: %s", "TestFeature1Impl"); - if (has_TestFeature2Impl() ) tty->print_cr("available: %s", "TestFeature2Impl"); - if (has_TestFeature4Impl() ) tty->print_cr("available: %s", "TestFeature4Impl"); - if (has_TestFeature8Impl() ) tty->print_cr("available: %s", "TestFeature8Impl"); + // z14 + if (has_MiscInstrExt2() ) tty->print_cr("available: %s", "Miscellaneous Instruction Extensions 2"); + if (has_VectorEnhancements1() ) tty->print_cr("available: %s", "Vector Facility Enhancements 3"); + if (has_CryptoExt8() ) tty->print_cr("available: %s", "Crypto Extensions 8"); + // z15 + if (has_MiscInstrExt3() ) tty->print_cr("available: %s", "Miscellaneous Instruction Extensions 3"); + if (has_VectorEnhancements2() ) tty->print_cr("available: %s", "Vector Facility Enhancements 3"); + if (has_CryptoExt9() ) tty->print_cr("available: %s", "Crypto Extensions 9"); if (has_Crypto()) { tty->cr(); tty->print_cr("detailed availability of %s capabilities:", "CryptoFacility"); - if (test_feature_bit(&_cipher_features[0], -1, 2*Cipher::_featureBits)) { + if (test_feature_bit(&_cipher_features_KM[0], -1, 2*Cipher::_featureBits)) { tty->cr(); tty->print_cr(" available: %s", "Message Cipher Functions"); } - if (test_feature_bit(&_cipher_features[0], -1, (int)Cipher::_featureBits)) { + + if (test_feature_bit(&_cipher_features_KM[0], -1, (int)Cipher::_featureBits)) { tty->print_cr(" available Crypto Features of KM (Cipher Message):"); for (unsigned int i = 0; i < Cipher::_featureBits; i++) { - if (test_feature_bit(&_cipher_features[0], i, (int)Cipher::_featureBits)) { + if (test_feature_bit(&_cipher_features_KM[0], i, (int)Cipher::_featureBits)) { switch (i) { case Cipher::_Query: tty->print_cr(" available: KM Query"); break; case Cipher::_DEA: tty->print_cr(" available: KM DEA"); break; @@ -450,10 +517,11 @@ } } } - if (test_feature_bit(&_cipher_features[2], -1, (int)Cipher::_featureBits)) { + + if (test_feature_bit(&_cipher_features_KM[2], -1, (int)Cipher::_featureBits)) { tty->print_cr(" available Crypto Features of KMC (Cipher Message with Chaining):"); for (unsigned int i = 0; i < Cipher::_featureBits; i++) { - if (test_feature_bit(&_cipher_features[2], i, (int)Cipher::_featureBits)) { + if (test_feature_bit(&_cipher_features_KM[2], i, (int)Cipher::_featureBits)) { switch (i) { case Cipher::_Query: tty->print_cr(" available: KMC Query"); break; case Cipher::_DEA: tty->print_cr(" available: KMC DEA"); break; @@ -474,35 +542,145 @@ } } } + } + if (has_CryptoExt4()) { + if (test_feature_bit(&_cipher_features_KMF[0], -1, (int)Cipher::_featureBits)) { + tty->print_cr(" available Crypto Features of KMF (Cipher Message with Cipher Feedback):"); + for (unsigned int i = 0; i < Cipher::_featureBits; i++) { + if (test_feature_bit(&_cipher_features_KMF[0], i, (int)Cipher::_featureBits)) { + switch (i) { + case Cipher::_Query: tty->print_cr(" available: KMF Query"); break; + case Cipher::_DEA: tty->print_cr(" available: KMF DEA"); break; + case Cipher::_TDEA128: tty->print_cr(" available: KMF TDEA-128"); break; + case Cipher::_TDEA192: tty->print_cr(" available: KMF TDEA-192"); break; + case Cipher::_EncryptedDEA: tty->print_cr(" available: KMF Encrypted DEA"); break; + case Cipher::_EncryptedDEA128: tty->print_cr(" available: KMF Encrypted DEA-128"); break; + case Cipher::_EncryptedDEA192: tty->print_cr(" available: KMF Encrypted DEA-192"); break; + case Cipher::_AES128: tty->print_cr(" available: KMF AES-128"); break; + case Cipher::_AES192: tty->print_cr(" available: KMF AES-192"); break; + case Cipher::_AES256: tty->print_cr(" available: KMF AES-256"); break; + case Cipher::_EnccryptedAES128: tty->print_cr(" available: KMF Encrypted-AES-128"); break; + case Cipher::_EnccryptedAES192: tty->print_cr(" available: KMF Encrypted-AES-192"); break; + case Cipher::_EnccryptedAES256: tty->print_cr(" available: KMF Encrypted-AES-256"); break; + default: tty->print_cr(" available: unknown KMF code %d", i); break; + } + } + } + } + + if (test_feature_bit(&_cipher_features_KMCTR[0], -1, (int)Cipher::_featureBits)) { + tty->print_cr(" available Crypto Features of KMCTR (Cipher Message with Counter):"); + for (unsigned int i = 0; i < Cipher::_featureBits; i++) { + if (test_feature_bit(&_cipher_features_KMCTR[0], i, (int)Cipher::_featureBits)) { + switch (i) { + case Cipher::_Query: tty->print_cr(" available: KMCTR Query"); break; + case Cipher::_DEA: tty->print_cr(" available: KMCTR DEA"); break; + case Cipher::_TDEA128: tty->print_cr(" available: KMCTR TDEA-128"); break; + case Cipher::_TDEA192: tty->print_cr(" available: KMCTR TDEA-192"); break; + case Cipher::_EncryptedDEA: tty->print_cr(" available: KMCTR Encrypted DEA"); break; + case Cipher::_EncryptedDEA128: tty->print_cr(" available: KMCTR Encrypted DEA-128"); break; + case Cipher::_EncryptedDEA192: tty->print_cr(" available: KMCTR Encrypted DEA-192"); break; + case Cipher::_AES128: tty->print_cr(" available: KMCTR AES-128"); break; + case Cipher::_AES192: tty->print_cr(" available: KMCTR AES-192"); break; + case Cipher::_AES256: tty->print_cr(" available: KMCTR AES-256"); break; + case Cipher::_EnccryptedAES128: tty->print_cr(" available: KMCTR Encrypted-AES-128"); break; + case Cipher::_EnccryptedAES192: tty->print_cr(" available: KMCTR Encrypted-AES-192"); break; + case Cipher::_EnccryptedAES256: tty->print_cr(" available: KMCTR Encrypted-AES-256"); break; + default: tty->print_cr(" available: unknown KMCTR code %d", i); break; + } + } + } + } + + if (test_feature_bit(&_cipher_features_KMO[0], -1, (int)Cipher::_featureBits)) { + tty->print_cr(" available Crypto Features of KMO (Cipher Message with Output Feedback):"); + for (unsigned int i = 0; i < Cipher::_featureBits; i++) { + if (test_feature_bit(&_cipher_features_KMO[0], i, (int)Cipher::_featureBits)) { + switch (i) { + case Cipher::_Query: tty->print_cr(" available: KMO Query"); break; + case Cipher::_DEA: tty->print_cr(" available: KMO DEA"); break; + case Cipher::_TDEA128: tty->print_cr(" available: KMO TDEA-128"); break; + case Cipher::_TDEA192: tty->print_cr(" available: KMO TDEA-192"); break; + case Cipher::_EncryptedDEA: tty->print_cr(" available: KMO Encrypted DEA"); break; + case Cipher::_EncryptedDEA128: tty->print_cr(" available: KMO Encrypted DEA-128"); break; + case Cipher::_EncryptedDEA192: tty->print_cr(" available: KMO Encrypted DEA-192"); break; + case Cipher::_AES128: tty->print_cr(" available: KMO AES-128"); break; + case Cipher::_AES192: tty->print_cr(" available: KMO AES-192"); break; + case Cipher::_AES256: tty->print_cr(" available: KMO AES-256"); break; + case Cipher::_EnccryptedAES128: tty->print_cr(" available: KMO Encrypted-AES-128"); break; + case Cipher::_EnccryptedAES192: tty->print_cr(" available: KMO Encrypted-AES-192"); break; + case Cipher::_EnccryptedAES256: tty->print_cr(" available: KMO Encrypted-AES-256"); break; + default: tty->print_cr(" available: unknown KMO code %d", i); break; + } + } + } + } + } + + if (has_CryptoExt8()) { + if (test_feature_bit(&_cipher_features_KMA[0], -1, (int)Cipher::_featureBits)) { + tty->print_cr(" available Crypto Features of KMA (Cipher Message with Authentication):"); + for (unsigned int i = 0; i < Cipher::_featureBits; i++) { + if (test_feature_bit(&_cipher_features_KMA[0], i, (int)Cipher::_featureBits)) { + switch (i) { + case Cipher::_Query: tty->print_cr(" available: KMA Query"); break; + case Cipher::_AES128: tty->print_cr(" available: KMA-GCM AES-128"); break; + case Cipher::_AES192: tty->print_cr(" available: KMA-GCM AES-192"); break; + case Cipher::_AES256: tty->print_cr(" available: KMA-GCM AES-256"); break; + case Cipher::_EnccryptedAES128: tty->print_cr(" available: KMA-GCM Encrypted-AES-128"); break; + case Cipher::_EnccryptedAES192: tty->print_cr(" available: KMA-GCM Encrypted-AES-192"); break; + case Cipher::_EnccryptedAES256: tty->print_cr(" available: KMA-GCM Encrypted-AES-256"); break; + default: tty->print_cr(" available: unknown KMA code %d", i); break; + } + } + } + } + } + + if (has_Crypto()) { if (test_feature_bit(&_msgdigest_features[0], -1, 2*MsgDigest::_featureBits)) { tty->cr(); tty->print_cr(" available: %s", "Message Digest Functions for SHA"); } + if (test_feature_bit(&_msgdigest_features[0], -1, (int)MsgDigest::_featureBits)) { tty->print_cr(" available Features of KIMD (Msg Digest):"); for (unsigned int i = 0; i < MsgDigest::_featureBits; i++) { - if (test_feature_bit(&_msgdigest_features[0], i, (int)MsgDigest::_featureBits)) { + if (test_feature_bit(&_msgdigest_features[0], i, (int)MsgDigest::_featureBits)) { switch (i) { - case MsgDigest::_Query: tty->print_cr(" available: KIMD Query"); break; - case MsgDigest::_SHA1: tty->print_cr(" available: KIMD SHA-1"); break; - case MsgDigest::_SHA256: tty->print_cr(" available: KIMD SHA-256"); break; - case MsgDigest::_SHA512: tty->print_cr(" available: KIMD SHA-512"); break; - case MsgDigest::_GHASH: tty->print_cr(" available: KIMD GHASH"); break; + case MsgDigest::_Query: tty->print_cr(" available: KIMD Query"); break; + case MsgDigest::_SHA1: tty->print_cr(" available: KIMD SHA-1"); break; + case MsgDigest::_SHA256: tty->print_cr(" available: KIMD SHA-256"); break; + case MsgDigest::_SHA512: tty->print_cr(" available: KIMD SHA-512"); break; + case MsgDigest::_SHA3_224: tty->print_cr(" available: KIMD SHA3-224"); break; + case MsgDigest::_SHA3_256: tty->print_cr(" available: KIMD SHA3-256"); break; + case MsgDigest::_SHA3_384: tty->print_cr(" available: KIMD SHA3-384"); break; + case MsgDigest::_SHA3_512: tty->print_cr(" available: KIMD SHA3-512"); break; + case MsgDigest::_SHAKE_128: tty->print_cr(" available: KIMD SHAKE-128"); break; + case MsgDigest::_SHAKE_256: tty->print_cr(" available: KIMD SHAKE-256"); break; + case MsgDigest::_GHASH: tty->print_cr(" available: KIMD GHASH"); break; default: tty->print_cr(" available: unknown code %d", i); break; } } } } + if (test_feature_bit(&_msgdigest_features[2], -1, (int)MsgDigest::_featureBits)) { tty->print_cr(" available Features of KLMD (Msg Digest):"); for (unsigned int i = 0; i < MsgDigest::_featureBits; i++) { if (test_feature_bit(&_msgdigest_features[2], i, (int)MsgDigest::_featureBits)) { switch (i) { - case MsgDigest::_Query: tty->print_cr(" available: KLMD Query"); break; - case MsgDigest::_SHA1: tty->print_cr(" available: KLMD SHA-1"); break; - case MsgDigest::_SHA256: tty->print_cr(" available: KLMD SHA-256"); break; - case MsgDigest::_SHA512: tty->print_cr(" available: KLMD SHA-512"); break; + case MsgDigest::_Query: tty->print_cr(" available: KLMD Query"); break; + case MsgDigest::_SHA1: tty->print_cr(" available: KLMD SHA-1"); break; + case MsgDigest::_SHA256: tty->print_cr(" available: KLMD SHA-256"); break; + case MsgDigest::_SHA512: tty->print_cr(" available: KLMD SHA-512"); break; + case MsgDigest::_SHA3_224: tty->print_cr(" available: KLMD SHA3-224"); break; + case MsgDigest::_SHA3_256: tty->print_cr(" available: KLMD SHA3-256"); break; + case MsgDigest::_SHA3_384: tty->print_cr(" available: KLMD SHA3-384"); break; + case MsgDigest::_SHA3_512: tty->print_cr(" available: KLMD SHA3-512"); break; + case MsgDigest::_SHAKE_128: tty->print_cr(" available: KLMD SHAKE-128"); break; + case MsgDigest::_SHAKE_256: tty->print_cr(" available: KLMD SHAKE-256"); break; default: tty->print_cr(" available: unknown code %d", i); break; } } @@ -516,6 +694,19 @@ } } +void VM_Version::print_platform_virtualization_info(outputStream* st) { + // /proc/sysinfo contains interesting information about + // - LPAR + // - whole "Box" (CPUs ) + // - z/VM / KVM (VM<nn>); this is not available in an LPAR-only setup + const char* kw[] = { "LPAR", "CPUs", "VM", NULL }; + const char* info_file = "/proc/sysinfo"; + + if (!print_matching_lines_from_file(info_file, st, kw)) { + st->print_cr(" <%s Not Available>", info_file); + } +} + void VM_Version::print_features() { print_features_internal("Version:"); } @@ -609,6 +800,26 @@ set_has_VectorFacility(); } +void VM_Version::set_features_z14(bool reset) { + reset_features(reset); + + set_features_z13(false); + set_has_MiscInstrExt2(); + set_has_VectorEnhancements1(); + has_VectorPackedDecimal(); + set_has_CryptoExt8(); +} + +void VM_Version::set_features_z15(bool reset) { + reset_features(reset); + + set_features_z14(false); + set_has_MiscInstrExt3(); + set_has_VectorEnhancements2(); + has_VectorPackedDecimalEnh(); + set_has_CryptoExt9(); +} + void VM_Version::set_features_from(const char* march) { bool err = false; bool prt = false; @@ -638,33 +849,10 @@ set_features_ec12(); } else if (!strcmp(march, "z13")) { set_features_z13(); - } else if (!strcmp(buf, "ztest")) { - assert(!has_TestFeaturesImpl(), "possible facility list flag conflict"); - if (strlen(march) > hdr_len) { - int itest = 0; - if ((strlen(march)-hdr_len) >= buf_len) err = true; - if (!err) { - memcpy(buf, &march[hdr_len], strlen(march)-hdr_len); - buf[strlen(march)-hdr_len] = '\00'; - for (size_t i = 0; !err && (i < strlen(buf)); i++) { - itest = itest*10 + buf[i]-'0'; - err = err || ((buf[i]-'0') < 0) || ((buf[i]-'0') > 9) || (itest > 15); - } - } - if (!err) { - prt = true; - if (itest & 0x01) { set_has_TestFeature1Impl(); } - if (itest & 0x02) { set_has_TestFeature2Impl(); } - if (itest & 0x04) { set_has_TestFeature4Impl(); } - if (itest & 0x08) { set_has_TestFeature8Impl(); } - } - } else { - prt = true; - set_has_TestFeature1Impl(); - set_has_TestFeature2Impl(); - set_has_TestFeature4Impl(); - set_has_TestFeature8Impl(); - } + } else if (!strcmp(march, "z14")) { + set_features_z14(); + } else if (!strcmp(march, "z15")) { + set_features_z15(); } else { err = true; } @@ -680,6 +868,29 @@ } +// getFeatures call interface +// Z_ARG1 (R2) - feature bit buffer address. +// Must be DW aligned. +// Z_ARG2 (R3) - > 0 feature bit buffer length (#DWs). +// Implies request to store cpu feature list via STFLE. +// = 0 invalid +// < 0 function code (which feature information to retrieve) +// Implies that a buffer of at least two DWs is passed in. +// =-1 - retrieve cache topology +// =-2 - basic cipher instruction capabilities +// =-3 - msg digest (secure hash) instruction capabilities +// =-4 - vector instruction OS support availability +// =-17 - cipher (KMF) support +// =-18 - cipher (KMCTR) support +// =-19 - cipher (KMO) support +// =-20 - cipher (KMA) support +// Z_ARG3 (R4) - feature code for ECAG instruction +// +// Z_RET (R2) - return value +// > 0: success: number of retrieved feature bit string words. +// < 0: failure: required number of feature bit string words (buffer too small). +// == 0: failure: operation aborted. +// static long (*getFeatures)(unsigned long*, int, int) = NULL; void VM_Version::set_getFeatures(address entryPoint) { @@ -702,6 +913,14 @@ return (attributeIndication<<4) | (levelIndication<<1) | typeIndication; } +void VM_Version::clear_buffer(unsigned long* buffer, unsigned int len) { + memset(buffer, 0, sizeof(buffer[0])*len); +} + +void VM_Version::copy_buffer(unsigned long* to, unsigned long* from, unsigned int len) { + memcpy(to, from, sizeof(to[0])*len); +} + void VM_Version::determine_features() { const int cbuf_size = _code_buffer_len; @@ -719,27 +938,38 @@ // Try STFLE. Possible INVOP will cause defaults to be used. Label getFEATURES; Label getCPUFEATURES; // fcode = -1 (cache) - Label getCIPHERFEATURES; // fcode = -2 (cipher) + Label getCIPHERFEATURES_KM; // fcode = -2 (cipher) + Label getCIPHERFEATURES_KMA; // fcode = -20 (cipher) + Label getCIPHERFEATURES_KMF; // fcode = -17 (cipher) + Label getCIPHERFEATURES_KMCTR; // fcode = -18 (cipher) + Label getCIPHERFEATURES_KMO; // fcode = -19 (cipher) Label getMSGDIGESTFEATURES; // fcode = -3 (SHA) Label getVECTORFEATURES; // fcode = -4 (OS support for vector instructions) Label errRTN; - a->z_ltgfr(Z_R0, Z_ARG2); // Buf len to r0 and test. - a->z_brl(getFEATURES); // negative -> Get machine features not covered by facility list. + a->z_ltgfr(Z_R0, Z_ARG2); // buf_len/fcode to r0 and test. + a->z_brl(getFEATURES); // negative -> Get machine features or instruction-specific features a->z_lghi(Z_R1,0); a->z_brz(errRTN); // zero -> Function code currently not used, indicate "aborted". - a->z_aghi(Z_R0, -1); + //---< store feature list >--- + // We have three possible outcomes here: + // success: cc = 0 and first DW of feature bit array != 0 + // Z_R0 contains index of last stored DW (used_len - 1) + // incomplete: cc = 3 and first DW of feature bit array != 0 + // Z_R0 contains index of last DW that would have been stored (required_len - 1) + a->z_aghi(Z_R0, -1); // STFLE needs last index, not length, of feature bit array. a->z_stfle(0, Z_ARG1); - a->z_lg(Z_R1, 0, Z_ARG1); // Get first DW of facility list. - a->z_lgr(Z_RET, Z_R0); // Calculate rtn value for success. - a->z_la(Z_RET, 1, Z_RET); + a->z_lg(Z_R1, Address(Z_ARG1, (intptr_t)0)); // Get first DW of facility list. + a->z_lgr(Z_RET, Z_R0); // Calculate used/required len + a->z_la(Z_RET, 1, Z_RET); // don't destroy cc from stfle! a->z_brnz(errRTN); // Instr failed if non-zero CC. - a->z_ltgr(Z_R1, Z_R1); // Instr failed if first DW == 0. + a->z_ltgr(Z_R1, Z_R1); // Check if first DW of facility list was filled. a->z_bcr(Assembler::bcondNotZero, Z_R14); // Successful return. + //---< error exit >--- a->bind(errRTN); - a->z_lngr(Z_RET, Z_RET); - a->z_ltgr(Z_R1, Z_R1); + a->z_lngr(Z_RET, Z_RET); // negative return value to indicate "buffer too small" + a->z_ltgr(Z_R1, Z_R1); // Check if first DW of facility list was filled. a->z_bcr(Assembler::bcondNotZero, Z_R14); // Return "buffer too small". a->z_xgr(Z_RET, Z_RET); a->z_br(Z_R14); // Return "operation aborted". @@ -748,12 +978,21 @@ a->z_cghi(Z_R0, -1); // -1: Extract CPU attributes, currently: cache layout only. a->z_bre(getCPUFEATURES); a->z_cghi(Z_R0, -2); // -2: Extract detailed crypto capabilities (cipher instructions). - a->z_bre(getCIPHERFEATURES); + a->z_bre(getCIPHERFEATURES_KM); a->z_cghi(Z_R0, -3); // -3: Extract detailed crypto capabilities (msg digest instructions). a->z_bre(getMSGDIGESTFEATURES); a->z_cghi(Z_R0, -4); // -4: Verify vector instruction availability (OS support). a->z_bre(getVECTORFEATURES); + a->z_cghi(Z_R0, -17); // -17: Extract detailed crypto capabilities (cipher instructions). + a->z_bre(getCIPHERFEATURES_KMF); + a->z_cghi(Z_R0, -18); // -18: Extract detailed crypto capabilities (cipher instructions). + a->z_bre(getCIPHERFEATURES_KMCTR); + a->z_cghi(Z_R0, -19); // -19: Extract detailed crypto capabilities (cipher instructions). + a->z_bre(getCIPHERFEATURES_KMO); + a->z_cghi(Z_R0, -20); // -20: Extract detailed crypto capabilities (cipher instructions). + a->z_bre(getCIPHERFEATURES_KMA); + a->z_xgr(Z_RET, Z_RET); // Not a valid function code. a->z_br(Z_R14); // Return "operation aborted". @@ -761,20 +1000,52 @@ a->bind(getMSGDIGESTFEATURES); a->z_lghi(Z_R0,(int)MsgDigest::_Query); // query function code a->z_lgr(Z_R1,Z_R2); // param block addr, 2*16 bytes min size - a->z_kimd(Z_R2,Z_R2); // Get available KIMD functions (bit pattern in param blk). + a->z_kimd(Z_R2,Z_R2); // Get available KIMD functions (bit pattern in param blk). Must use even regs. a->z_la(Z_R1,16,Z_R1); // next param block addr - a->z_klmd(Z_R2,Z_R2); // Get available KLMD functions (bit pattern in param blk). - a->z_lghi(Z_RET,4); + a->z_klmd(Z_R2,Z_R4); // Get available KLMD functions (bit pattern in param blk). Must use distinct even regs. + a->z_lghi(Z_RET,4); // #used words in output buffer a->z_br(Z_R14); // Try KM/KMC query function to get details about crypto instructions. - a->bind(getCIPHERFEATURES); + a->bind(getCIPHERFEATURES_KM); a->z_lghi(Z_R0,(int)Cipher::_Query); // query function code a->z_lgr(Z_R1,Z_R2); // param block addr, 2*16 bytes min size (KIMD/KLMD output) - a->z_km(Z_R2,Z_R2); // get available KM functions + a->z_km(Z_R2,Z_R2); // get available KM functions. Must use even regs. a->z_la(Z_R1,16,Z_R1); // next param block addr a->z_kmc(Z_R2,Z_R2); // get available KMC functions - a->z_lghi(Z_RET,4); + a->z_lghi(Z_RET,4); // #used words in output buffer + a->z_br(Z_R14); + + // Try KMA query function to get details about crypto instructions. + a->bind(getCIPHERFEATURES_KMA); + a->z_lghi(Z_R0,(int)Cipher::_Query); // query function code + a->z_lgr(Z_R1,Z_R2); // param block addr, 2*16 bytes min size (KIMD/KLMD output) + a->z_kma(Z_R2,Z_R4,Z_R6); // get available KMA functions. Must use distinct even regs. + a->z_lghi(Z_RET,2); // #used words in output buffer + a->z_br(Z_R14); + + // Try KMF query function to get details about crypto instructions. + a->bind(getCIPHERFEATURES_KMF); + a->z_lghi(Z_R0,(int)Cipher::_Query); // query function code + a->z_lgr(Z_R1,Z_R2); // param block addr, 2*16 bytes min size (KIMD/KLMD output) + a->z_kmf(Z_R2,Z_R2); // get available KMA functions. Must use even regs. + a->z_lghi(Z_RET,2); // #used words in output buffer + a->z_br(Z_R14); + + // Try KMCTR query function to get details about crypto instructions. + a->bind(getCIPHERFEATURES_KMCTR); + a->z_lghi(Z_R0,(int)Cipher::_Query); // query function code + a->z_lgr(Z_R1,Z_R2); // param block addr, 2*16 bytes min size (KIMD/KLMD output) + a->z_kmctr(Z_R2,Z_R2,Z_R2); // get available KMCTR functions. Must use even regs. + a->z_lghi(Z_RET,2); // #used words in output buffer + a->z_br(Z_R14); + + // Try KMO query function to get details about crypto instructions. + a->bind(getCIPHERFEATURES_KMO); + a->z_lghi(Z_R0,(int)Cipher::_Query); // query function code + a->z_lgr(Z_R1,Z_R2); // param block addr, 2*16 bytes min size (KIMD/KLMD output) + a->z_kmo(Z_R2,Z_R2); // get available KMO functions. Must use even regs. + a->z_lghi(Z_RET,2); // #used words in output buffer a->z_br(Z_R14); // Use EXTRACT CPU ATTRIBUTE instruction to get information about cache layout. @@ -803,14 +1074,9 @@ Disassembler::decode((u_char*)code, (u_char*)code_end, tty); } - // Prepare for detection code execution and clear work buffer. - _nfeatures = 0; - _ncipher_features = 0; + // prepare work buffer unsigned long buffer[buf_len]; - - for (int i = 0; i < buf_len; i++) { - buffer[i] = 0L; - } + clear_buffer(buffer, buf_len); // execute code // Illegal instructions will be replaced by 0 in signal handler. @@ -818,40 +1084,37 @@ long used_len = call_getFeatures(buffer, buf_len, 0); bool ok; - if (used_len == 1) { + if ((used_len > 0) && (used_len <= buf_len)) { ok = true; - } else if (used_len > 1) { - unsigned int used_lenU = (unsigned int)used_len; - ok = true; - for (unsigned int i = 1; i < used_lenU; i++) { - ok = ok && (buffer[i] == 0L); - } - if (printVerbose && !ok) { - bool compact = false; - tty->print_cr("Note: feature list has %d (i.e. more than one) array elements.", used_lenU); + if (printVerbose) { + bool compact = Verbose; + tty->print_cr("Note: feature list uses %ld array elements.", used_len); if (compact) { tty->print("non-zero feature list elements:"); - for (unsigned int i = 0; i < used_lenU; i++) { - tty->print(" [%d]: 0x%16.16lx", i, buffer[i]); + for (unsigned int k = 0; k < used_len; k++) { + if (buffer[k] != 0) { + tty->print(" [%d]: 0x%16.16lx", k, buffer[k]); + } } tty->cr(); } else { - for (unsigned int i = 0; i < used_lenU; i++) { - tty->print_cr("non-zero feature list[%d]: 0x%16.16lx", i, buffer[i]); + for (unsigned int k = 0; k < used_len; k++) { + tty->print_cr("non-zero feature list[%d]: 0x%16.16lx", k, buffer[k]); } } if (compact) { tty->print_cr("Active features (compact view):"); - for (unsigned int k = 0; k < used_lenU; k++) { + for (unsigned int k = 0; k < used_len; k++) { tty->print_cr(" buffer[%d]:", k); for (unsigned int j = k*sizeof(long); j < (k+1)*sizeof(long); j++) { bool line = false; for (unsigned int i = j*8; i < (j+1)*8; i++) { - bool bit = test_feature_bit(buffer, i, used_lenU*sizeof(long)*8); + bool bit = test_feature_bit(buffer, i, used_len*sizeof(long)*8); if (bit) { if (!line) { tty->print(" byte[%d]:", j); + tty->fill_to(13); line = true; } tty->print(" [%3.3d]", i); @@ -864,12 +1127,13 @@ } } else { tty->print_cr("Active features (full view):"); - for (unsigned int k = 0; k < used_lenU; k++) { + for (unsigned int k = 0; k < used_len; k++) { tty->print_cr(" buffer[%d]:", k); for (unsigned int j = k*sizeof(long); j < (k+1)*sizeof(long); j++) { tty->print(" byte[%d]:", j); + tty->fill_to(13); for (unsigned int i = j*8; i < (j+1)*8; i++) { - bool bit = test_feature_bit(buffer, i, used_lenU*sizeof(long)*8); + bool bit = test_feature_bit(buffer, i, used_len*sizeof(long)*8); if (bit) { tty->print(" [%3.3d]", i); } else { @@ -881,69 +1145,32 @@ } } } - ok = true; } else { // No features retrieved if we reach here. Buffer too short or instr not available. + ok = false; if (used_len < 0) { - ok = false; if (printVerbose) { tty->print_cr("feature list buffer[%d] too short, required: buffer[%ld]", buf_len, -used_len); } } else { if (printVerbose) { - tty->print_cr("feature list could not be retrieved. Running on z900 or z990? Trying to find out..."); + tty->print_cr("feature list could not be retrieved. Bad function code? Running on z900 or z990?"); } - used_len = call_getFeatures(buffer, 0, 0); // Must provide at least two DW buffer elements!!!! - - ok = used_len > 0; - if (ok) { - if (buffer[1]*10 < buffer[0]) { - set_features_z900(); - } else { - set_features_z990(); - } - - if (printVerbose) { - tty->print_cr("Note: high-speed long displacement test used %ld iterations.", used_len); - tty->print_cr(" Positive displacement loads took %8.8lu microseconds.", buffer[1]); - tty->print_cr(" Negative displacement loads took %8.8lu microseconds.", buffer[0]); - if (has_long_displacement_fast()) { - tty->print_cr(" assuming high-speed long displacement IS available."); - } else { - tty->print_cr(" assuming high-speed long displacement is NOT available."); - } - } - } else { - if (printVerbose) { - tty->print_cr("Note: high-speed long displacement test was not successful."); - tty->print_cr(" assuming long displacement is NOT available."); - } - } - return; // Do not copy buffer to _features, no test for cipher features. } } if (ok) { - // Fill features buffer. - // Clear work buffer. - for (int i = 0; i < buf_len; i++) { - _features[i] = buffer[i]; - _cipher_features[i] = 0; - _msgdigest_features[i] = 0; - buffer[i] = 0L; - } + // Copy detected features to features buffer. + copy_buffer(_features, buffer, buf_len); _nfeatures = used_len; } else { - for (int i = 0; i < buf_len; i++) { - _features[i] = 0; - _cipher_features[i] = 0; - _msgdigest_features[i] = 0; - buffer[i] = 0L; - } + // Something went wrong with feature detection. Disable everything. + clear_buffer(_features, buf_len); _nfeatures = 0; } if (has_VectorFacility()) { // Verify that feature can actually be used. OS support required. + // We will get a signal if not. Signal handler will disable vector facility call_getFeatures(buffer, -4, 0); if (printVerbose) { ttyLocker ttyl; @@ -955,23 +1182,69 @@ } } - // Extract Crypto Facility details. + // Clear all Cipher feature buffers and the work buffer. + clear_buffer(_cipher_features_KM, buf_len); + clear_buffer(_cipher_features_KMA, buf_len); + clear_buffer(_cipher_features_KMF, buf_len); + clear_buffer(_cipher_features_KMCTR, buf_len); + clear_buffer(_cipher_features_KMO, buf_len); + clear_buffer(_msgdigest_features, buf_len); + _ncipher_features_KM = 0; + _ncipher_features_KMA = 0; + _ncipher_features_KMF = 0; + _ncipher_features_KMCTR = 0; + _ncipher_features_KMO = 0; + _nmsgdigest_features = 0; + + //--------------------------------------- + //-- Extract Crypto Facility details -- + //--------------------------------------- + if (has_Crypto()) { - // Get cipher features. + // Get features of KM/KMC cipher instructions + clear_buffer(buffer, buf_len); used_len = call_getFeatures(buffer, -2, 0); - for (int i = 0; i < buf_len; i++) { - _cipher_features[i] = buffer[i]; - } - _ncipher_features = used_len; + copy_buffer(_cipher_features_KM, buffer, buf_len); + _ncipher_features_KM = used_len; // Get msg digest features. + clear_buffer(buffer, buf_len); used_len = call_getFeatures(buffer, -3, 0); - for (int i = 0; i < buf_len; i++) { - _msgdigest_features[i] = buffer[i]; - } + copy_buffer(_msgdigest_features, buffer, buf_len); _nmsgdigest_features = used_len; } + if (has_CryptoExt4()) { + // Get features of KMF cipher instruction + clear_buffer(buffer, buf_len); + used_len = call_getFeatures(buffer, -17, 0); + copy_buffer(_cipher_features_KMF, buffer, buf_len); + _ncipher_features_KMF = used_len; + + // Get features of KMCTR cipher instruction + clear_buffer(buffer, buf_len); + used_len = call_getFeatures(buffer, -18, 0); + copy_buffer(_cipher_features_KMCTR, buffer, buf_len); + _ncipher_features_KMCTR = used_len; + + // Get features of KMO cipher instruction + clear_buffer(buffer, buf_len); + used_len = call_getFeatures(buffer, -19, 0); + copy_buffer(_cipher_features_KMO, buffer, buf_len); + _ncipher_features_KMO = used_len; + } + + if (has_CryptoExt8()) { + // Get features of KMA cipher instruction + clear_buffer(buffer, buf_len); + used_len = call_getFeatures(buffer, -20, 0); + copy_buffer(_cipher_features_KMA, buffer, buf_len); + _ncipher_features_KMA = used_len; + } + if (printVerbose) { + tty->print_cr(" Crypto capabilities retrieved."); + } + static int levelProperties[_max_cache_levels]; // All property indications per level. static int levelScope[_max_cache_levels]; // private/shared static const char* levelScopeText[4] = {"No cache ", @@ -1205,4 +1478,3 @@ ); return ZeroBuffer; } -
diff --git a/src/hotspot/cpu/s390/vm_version_s390.hpp b/src/hotspot/cpu/s390/vm_version_s390.hpp index 210ed17..d516937 100644 --- a/src/hotspot/cpu/s390/vm_version_s390.hpp +++ b/src/hotspot/cpu/s390/vm_version_s390.hpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2016, 2018 SAP SE. All rights reserved. + * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2016, 2021 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -27,27 +27,19 @@ #define CPU_S390_VM_VM_VERSION_S390_HPP +#include "runtime/abstract_vm_version.hpp" #include "runtime/globals_extension.hpp" -#include "runtime/vm_version.hpp" class VM_Version: public Abstract_VM_Version { protected: -// The following list contains the (approximate) announcement/availability -// dates of the many System z generations in existence as of now which -// implement the z/Architecture. -// z900: 2000-10 -// z990: 2003-06 -// z9: 2005-09 -// z10: 2007-04 -// z10: 2008-02 -// z196: 2010-08 -// ec12: 2012-09 -// z13: 2015-03 -// // z/Architecture is the name of the 64-bit extension of the 31-bit s390 // architecture. // +// For information concerning the life span of the individual +// z/Architecture models, please check out the comments/tables +// in vm_version_s390.cpp + // ---------------------------------------------- // --- FeatureBitString Bits 0.. 63 (DW[0]) --- // ---------------------------------------------- @@ -55,7 +47,7 @@ // 04826048260482604 #define StoreFacilityListExtendedMask 0x0100000000000000UL // z9 #define ETF2Mask 0x0000800000000000UL // z900 -#define CryptoFacilityMask 0x0000400000000000UL // z990 +#define CryptoFacilityMask 0x0000400000000000UL // z990 (aka message-security assist) #define LongDispFacilityMask 0x0000200000000000UL // z900 with microcode update #define LongDispFacilityHighPerfMask 0x0000300000000000UL // z990 #define HFPMultiplyAndAddMask 0x0000080000000000UL // z990 @@ -94,11 +86,8 @@ #define LoadStoreConditional2Mask 0x0000000000000400UL // z13 #define CryptoExtension5Mask 0x0000000000000040UL // z13 // z13 end -// Feature-DW[0] starts to fill up. Use of these masks is risky. -#define TestFeature1ImplMask 0x0000000000000001UL -#define TestFeature2ImplMask 0x0000000000000002UL -#define TestFeature4ImplMask 0x0000000000000004UL -#define TestFeature8ImplMask 0x0000000000000008UL +#define MiscInstrExt2Mask 0x0000000000000020UL // z14 +#define MiscInstrExt3Mask 0x0000000000000004UL // z15 // ---------------------------------------------- // --- FeatureBitString Bits 64..127 (DW[1]) --- // ---------------------------------------------- @@ -107,7 +96,7 @@ // 48260482604826048 #define TransactionalExecutionMask 0x0040000000000000UL // ec12 #define CryptoExtension3Mask 0x0008000000000000UL // z196 -#define CryptoExtension4Mask 0x0004000000000000UL // z196 +#define CryptoExtension4Mask 0x0004000000000000UL // z196 (aka message-security assist extension 4, for KMF, KMCTR, KMO) #define DFPPackedConversionMask 0x0000800000000000UL // z13 // ---------------------------------------------- // --- FeatureBitString Bits 128..192 (DW[2]) --- @@ -116,6 +105,15 @@ // 23344455666778889 // 82604826048260482 #define VectorFacilityMask 0x4000000000000000UL // z13, not avail in VM guest mode! +#define ExecutionProtectionMask 0x2000000000000000UL // z14 +#define GuardedStorageMask 0x0400000000000000UL // z14 +#define VectorEnhancements1Mask 0x0100000000000000UL // z14 +#define VectorPackedDecimalMask 0x0200000000000000UL // z14 +#define CryptoExtension8Mask 0x0000200000000000UL // z14 (aka message-security assist extension 8, for KMA) +#define VectorEnhancements2Mask 0x0000080000000000UL // z15 +#define VectorPackedDecimalEnhMask 0x0000008000000000UL // z15 +#define CryptoExtension9Mask 0x0000001000000000UL // z15 (aka message-security assist extension 9) +#define DeflateMask 0x0000010000000000UL // z15 enum { _max_cache_levels = 8, // As limited by ECAG instruction. @@ -123,10 +121,18 @@ _code_buffer_len = 2*256 // For feature detection code. }; static unsigned long _features[_features_buffer_len]; - static unsigned long _cipher_features[_features_buffer_len]; + static unsigned long _cipher_features_KM[_features_buffer_len]; + static unsigned long _cipher_features_KMA[_features_buffer_len]; + static unsigned long _cipher_features_KMF[_features_buffer_len]; + static unsigned long _cipher_features_KMCTR[_features_buffer_len]; + static unsigned long _cipher_features_KMO[_features_buffer_len]; static unsigned long _msgdigest_features[_features_buffer_len]; static unsigned int _nfeatures; - static unsigned int _ncipher_features; + static unsigned int _ncipher_features_KM; + static unsigned int _ncipher_features_KMA; + static unsigned int _ncipher_features_KMF; + static unsigned int _ncipher_features_KMCTR; + static unsigned int _ncipher_features_KMO; static unsigned int _nmsgdigest_features; static unsigned int _Dcache_lineSize; static unsigned int _Icache_lineSize; @@ -134,16 +140,19 @@ static const char* _model_string; static bool test_feature_bit(unsigned long* featureBuffer, int featureNum, unsigned int bufLen); + static int get_model_index(); static void set_features_string(); static void print_features_internal(const char* text, bool print_anyway=false); static void determine_features(); static long call_getFeatures(unsigned long* buffer, int buflen, int functionCode); static void set_getFeatures(address entryPoint); + static void clear_buffer(unsigned long* buffer, unsigned int len); + static void copy_buffer(unsigned long* to, unsigned long* from, unsigned int len); static int calculate_ECAG_functionCode(unsigned int attributeIndication, unsigned int levelIndication, unsigned int typeIndication); - // Setting features via march=z900|z990|z9|z10|z196|ec12|z13|ztest commandline option. + // Setting features via march=z900|z990|z9|z10|z196|ec12|z13|z14|z15 commandline option. static void reset_features(bool reset); static void set_features_z900(bool reset = true); static void set_features_z990(bool reset = true); @@ -152,8 +161,17 @@ static void set_features_z196(bool reset = true); static void set_features_ec12(bool reset = true); static void set_features_z13(bool reset = true); + static void set_features_z14(bool reset = true); + static void set_features_z15(bool reset = true); static void set_features_from(const char* march); + // Get information about cache line sizes. + // As of now and the foreseeable future, line size of all levels will be the same and 256. + static unsigned int Dcache_lineSize(unsigned int level = 0) { return _Dcache_lineSize; } + static unsigned int Icache_lineSize(unsigned int level = 0) { return _Icache_lineSize; } + + public: + // Get the CPU type from feature bit settings. static bool is_z900() { return has_long_displacement() && !has_long_displacement_fast(); } static bool is_z990() { return has_long_displacement_fast() && !has_extended_immediate(); } @@ -161,14 +179,9 @@ static bool is_z10() { return has_GnrlInstrExtensions() && !has_DistinctOpnds(); } static bool is_z196() { return has_DistinctOpnds() && !has_MiscInstrExt(); } static bool is_ec12() { return has_MiscInstrExt() && !has_CryptoExt5(); } - static bool is_z13() { return has_CryptoExt5();} - - // Get information about cache line sizes. - // As of now and the foreseeable future, line size of all levels will be the same and 256. - static unsigned int Dcache_lineSize(unsigned int level = 0) { return _Dcache_lineSize; } - static unsigned int Icache_lineSize(unsigned int level = 0) { return _Icache_lineSize; } - - public: + static bool is_z13() { return has_CryptoExt5() && !has_MiscInstrExt2();} + static bool is_z14() { return has_MiscInstrExt2() && !has_MiscInstrExt3();} + static bool is_z15() { return has_MiscInstrExt3();} // Need to use nested class with unscoped enum. // C++11 declaration "enum class Cipher { ... } is not supported. @@ -265,32 +278,56 @@ class MsgDigest { public: enum { - _Query = 0, - _SHA1 = 1, - _SHA256 = 2, - _SHA512 = 3, - _GHASH = 65, - _featureBits = 128, + _Query = 0, + _SHA1 = 1, + _SHA256 = 2, + _SHA512 = 3, + _SHA3_224 = 32, + _SHA3_256 = 33, + _SHA3_384 = 34, + _SHA3_512 = 35, + _SHAKE_128 = 36, + _SHAKE_256 = 37, + _GHASH = 65, + _featureBits = 128, // Parameter block sizes (in bytes) for KIMD. - _Query_parmBlk_I = 16, - _SHA1_parmBlk_I = 20, - _SHA256_parmBlk_I = 32, - _SHA512_parmBlk_I = 64, - _GHASH_parmBlk_I = 32, + _Query_parmBlk_I = 16, + _SHA1_parmBlk_I = 20, + _SHA256_parmBlk_I = 32, + _SHA512_parmBlk_I = 64, + _SHA3_224_parmBlk_I = 200, + _SHA3_256_parmBlk_I = 200, + _SHA3_384_parmBlk_I = 200, + _SHA3_512_parmBlk_I = 200, + _SHAKE_128_parmBlk_I = 200, + _SHAKE_256_parmBlk_I = 200, + _GHASH_parmBlk_I = 32, // Parameter block sizes (in bytes) for KLMD. - _Query_parmBlk_L = 16, - _SHA1_parmBlk_L = 28, - _SHA256_parmBlk_L = 40, - _SHA512_parmBlk_L = 80, + _Query_parmBlk_L = 16, + _SHA1_parmBlk_L = 28, + _SHA256_parmBlk_L = 40, + _SHA512_parmBlk_L = 80, + _SHA3_224_parmBlk_L = 200, + _SHA3_256_parmBlk_L = 200, + _SHA3_384_parmBlk_L = 200, + _SHA3_512_parmBlk_L = 200, + _SHAKE_128_parmBlk_L = 200, + _SHAKE_256_parmBlk_L = 200, // Data block sizes (in bytes). - _Query_dataBlk = 0, - _SHA1_dataBlk = 64, - _SHA256_dataBlk = 64, - _SHA512_dataBlk = 128, - _GHASH_dataBlk = 16 + _Query_dataBlk = 0, + _SHA1_dataBlk = 64, + _SHA256_dataBlk = 64, + _SHA512_dataBlk = 128, + _SHA3_224_dataBlk = 144, + _SHA3_256_dataBlk = 136, + _SHA3_384_dataBlk = 104, + _SHA3_512_dataBlk = 72, + _SHAKE_128_dataBlk = 168, + _SHAKE_256_dataBlk = 136, + _GHASH_dataBlk = 16 }; }; class MsgAuthent { @@ -346,6 +383,9 @@ static void print_features(); static bool is_determine_features_test_running() { return _is_determine_features_test_running; } + // Override Abstract_VM_Version implementation + static void print_platform_virtualization_info(outputStream*); + // CPU feature query functions static const char* get_model_string() { return _model_string; } static bool has_StoreFacilityListExtended() { return (_features[0] & StoreFacilityListExtendedMask) == StoreFacilityListExtendedMask; } @@ -391,11 +431,11 @@ static bool has_HighWordInstr() { return (_features[0] & HighWordMask) == HighWordMask; } static bool has_FastSync() { return (_features[0] & FastBCRSerializationMask) == FastBCRSerializationMask; } static bool has_DistinctOpnds() { return (_features[0] & DistinctOpndsMask) == DistinctOpndsMask; } - static bool has_CryptoExt3() { return (_features[1] & CryptoExtension3Mask) == CryptoExtension3Mask; } - static bool has_CryptoExt4() { return (_features[1] & CryptoExtension4Mask) == CryptoExtension4Mask; } static bool has_DFPZonedConversion() { return (_features[0] & DFPZonedConversionMask) == DFPZonedConversionMask; } static bool has_DFPPackedConversion() { return (_features[1] & DFPPackedConversionMask) == DFPPackedConversionMask; } static bool has_MiscInstrExt() { return (_features[0] & MiscInstrExtMask) == MiscInstrExtMask; } + static bool has_MiscInstrExt2() { return (_features[0] & MiscInstrExt2Mask) == MiscInstrExt2Mask; } + static bool has_MiscInstrExt3() { return (_features[0] & MiscInstrExt3Mask) == MiscInstrExt3Mask; } static bool has_ExecutionHint() { return (_features[0] & ExecutionHintMask) == ExecutionHintMask; } static bool has_LoadAndTrap() { return (_features[0] & LoadAndTrapMask) == LoadAndTrapMask; } static bool has_ProcessorAssist() { return (_features[0] & ProcessorAssistMask) == ProcessorAssistMask; } @@ -403,21 +443,22 @@ static bool has_LoadAndALUAtomicV2() { return (_features[0] & InterlockedAccess2Mask) == InterlockedAccess2Mask; } static bool has_TxMem() { return ((_features[1] & TransactionalExecutionMask) == TransactionalExecutionMask) && ((_features[0] & ConstrainedTxExecutionMask) == ConstrainedTxExecutionMask); } + static bool has_CryptoExt3() { return (_features[1] & CryptoExtension3Mask) == CryptoExtension3Mask; } + static bool has_CryptoExt4() { return (_features[1] & CryptoExtension4Mask) == CryptoExtension4Mask; } static bool has_CryptoExt5() { return (_features[0] & CryptoExtension5Mask) == CryptoExtension5Mask; } + static bool has_CryptoExt8() { return (_features[2] & CryptoExtension8Mask) == CryptoExtension8Mask; } + static bool has_CryptoExt9() { return (_features[2] & CryptoExtension9Mask) == CryptoExtension9Mask; } static bool has_LoadStoreConditional2() { return (_features[0] & LoadStoreConditional2Mask) == LoadStoreConditional2Mask; } static bool has_VectorFacility() { return (_features[2] & VectorFacilityMask) == VectorFacilityMask; } - - static bool has_TestFeatureImpl() { return (_features[0] & TestFeature1ImplMask) == TestFeature1ImplMask; } - static bool has_TestFeature1Impl() { return (_features[0] & TestFeature1ImplMask) == TestFeature1ImplMask; } - static bool has_TestFeature2Impl() { return (_features[0] & TestFeature2ImplMask) == TestFeature2ImplMask; } - static bool has_TestFeature4Impl() { return (_features[0] & TestFeature4ImplMask) == TestFeature4ImplMask; } - static bool has_TestFeature8Impl() { return (_features[0] & TestFeature8ImplMask) == TestFeature8ImplMask; } - static bool has_TestFeaturesImpl() { return has_TestFeature1Impl() || has_TestFeature2Impl() || has_TestFeature4Impl() || has_TestFeature8Impl(); } + static bool has_VectorEnhancements1() { return (_features[2] & VectorEnhancements1Mask) == VectorEnhancements1Mask; } + static bool has_VectorEnhancements2() { return (_features[2] & VectorEnhancements2Mask) == VectorEnhancements2Mask; } + static bool has_VectorPackedDecimal() { return (_features[2] & VectorPackedDecimalMask) == VectorPackedDecimalMask; } + static bool has_VectorPackedDecimalEnh() { return (_features[2] & VectorPackedDecimalEnhMask) == VectorPackedDecimalEnhMask; } // Crypto features query functions. - static bool has_Crypto_AES128() { return has_Crypto() && test_feature_bit(&_cipher_features[0], Cipher::_AES128, Cipher::_featureBits); } - static bool has_Crypto_AES192() { return has_Crypto() && test_feature_bit(&_cipher_features[0], Cipher::_AES192, Cipher::_featureBits); } - static bool has_Crypto_AES256() { return has_Crypto() && test_feature_bit(&_cipher_features[0], Cipher::_AES256, Cipher::_featureBits); } + static bool has_Crypto_AES128() { return has_Crypto() && test_feature_bit(&_cipher_features_KM[0], Cipher::_AES128, Cipher::_featureBits); } + static bool has_Crypto_AES192() { return has_Crypto() && test_feature_bit(&_cipher_features_KM[0], Cipher::_AES192, Cipher::_featureBits); } + static bool has_Crypto_AES256() { return has_Crypto() && test_feature_bit(&_cipher_features_KM[0], Cipher::_AES256, Cipher::_featureBits); } static bool has_Crypto_AES() { return has_Crypto_AES128() || has_Crypto_AES192() || has_Crypto_AES256(); } static bool has_Crypto_SHA1() { return has_Crypto() && test_feature_bit(&_msgdigest_features[0], MsgDigest::_SHA1, MsgDigest::_featureBits); } @@ -427,10 +468,6 @@ static bool has_Crypto_SHA() { return has_Crypto_SHA1() || has_Crypto_SHA256() || has_Crypto_SHA512() || has_Crypto_GHASH(); } // CPU feature setters (to force model-specific behaviour). Test/debugging only. - static void set_has_TestFeature1Impl() { _features[0] |= TestFeature1ImplMask; } - static void set_has_TestFeature2Impl() { _features[0] |= TestFeature2ImplMask; } - static void set_has_TestFeature4Impl() { _features[0] |= TestFeature4ImplMask; } - static void set_has_TestFeature8Impl() { _features[0] |= TestFeature8ImplMask; } static void set_has_DecimalFloatingPoint() { _features[0] |= DecimalFloatingPointMask; } static void set_has_FPSupportEnhancements() { _features[0] |= FPSupportEnhancementsMask; } static void set_has_ExecuteExtensions() { _features[0] |= ExecuteExtensionsMask; } @@ -465,15 +502,23 @@ static void set_has_DistinctOpnds() { _features[0] |= DistinctOpndsMask; } static void set_has_FPExtensions() { _features[0] |= FPExtensionsMask; } static void set_has_MiscInstrExt() { _features[0] |= MiscInstrExtMask; } + static void set_has_MiscInstrExt2() { _features[0] |= MiscInstrExt2Mask; } + static void set_has_MiscInstrExt3() { _features[0] |= MiscInstrExt3Mask; } static void set_has_ProcessorAssist() { _features[0] |= ProcessorAssistMask; } static void set_has_InterlockedAccessV2() { _features[0] |= InterlockedAccess2Mask; } static void set_has_LoadAndALUAtomicV2() { _features[0] |= InterlockedAccess2Mask; } static void set_has_TxMem() { _features[0] |= ConstrainedTxExecutionMask; _features[1] |= TransactionalExecutionMask; } + static void set_has_LoadStoreConditional2() { _features[0] |= LoadStoreConditional2Mask; } static void set_has_CryptoExt3() { _features[1] |= CryptoExtension3Mask; } static void set_has_CryptoExt4() { _features[1] |= CryptoExtension4Mask; } - static void set_has_LoadStoreConditional2() { _features[0] |= LoadStoreConditional2Mask; } static void set_has_CryptoExt5() { _features[0] |= CryptoExtension5Mask; } + static void set_has_CryptoExt8() { _features[2] |= CryptoExtension8Mask; } + static void set_has_CryptoExt9() { _features[2] |= CryptoExtension9Mask; } static void set_has_VectorFacility() { _features[2] |= VectorFacilityMask; } + static void set_has_VectorEnhancements1() { _features[2] |= VectorEnhancements1Mask; } + static void set_has_VectorEnhancements2() { _features[2] |= VectorEnhancements2Mask; } + static void set_has_VectorPackedDecimal() { _features[2] |= VectorPackedDecimalMask; } + static void set_has_VectorPackedDecimalEnh() { _features[2] |= VectorPackedDecimalEnhMask; } static void reset_has_VectorFacility() { _features[2] &= ~VectorFacilityMask; }
diff --git a/src/hotspot/cpu/s390/vtableStubs_s390.cpp b/src/hotspot/cpu/s390/vtableStubs_s390.cpp index 63d9061..aa723de 100644 --- a/src/hotspot/cpu/s390/vtableStubs_s390.cpp +++ b/src/hotspot/cpu/s390/vtableStubs_s390.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2016, 2018 SAP SE. All rights reserved. + * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2016, 2021 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -74,7 +74,7 @@ // Abuse Z_method as scratch register for generic emitter. // It is loaded further down anyway before it is first used. // No dynamic code size variance here, increment is 1, always. - __ add2mem_32(Address(Z_R1_scratch), 1, Z_method); + __ add2mem_64(Address(Z_R1_scratch), 1, Z_method); } #endif @@ -157,6 +157,7 @@ if (s == NULL) { return NULL; } + // Count unused bytes in instruction sequences of variable size. // We add them to the computed buffer size in order to avoid // overflow in subsequently generated stubs. @@ -178,7 +179,7 @@ // Abuse Z_method as scratch register for generic emitter. // It is loaded further down anyway before it is first used. // No dynamic code size variance here, increment is 1, always. - __ add2mem_32(Address(Z_R1_scratch), 1, Z_method); + __ add2mem_64(Address(Z_R1_scratch), 1, Z_method); } #endif
diff --git a/src/hotspot/cpu/sparc/assembler_sparc.hpp b/src/hotspot/cpu/sparc/assembler_sparc.hpp index 01f0121..e341478 100644 --- a/src/hotspot/cpu/sparc/assembler_sparc.hpp +++ b/src/hotspot/cpu/sparc/assembler_sparc.hpp
@@ -358,6 +358,13 @@ return is_in_wdisp_range(a, b, 30); } + static bool is_simm5(intptr_t x) { return is_simm(x, 5); } + static bool is_simm11(intptr_t x) { return is_simm(x, 11); } + static bool is_simm12(intptr_t x) { return is_simm(x, 12); } + static bool is_simm13(intptr_t x) { return is_simm(x, 13); } + + static int min_simm13() { return -4096; } + enum ASIs { // page 72, v9 ASI_PRIMARY = 0x80, ASI_PRIMARY_NOFAULT = 0x82,
diff --git a/src/hotspot/cpu/sparc/c1_FrameMap_sparc.cpp b/src/hotspot/cpu/sparc/c1_FrameMap_sparc.cpp index 87a95e5..269b0a9 100644 --- a/src/hotspot/cpu/sparc/c1_FrameMap_sparc.cpp +++ b/src/hotspot/cpu/sparc/c1_FrameMap_sparc.cpp
@@ -55,6 +55,8 @@ opr = as_oop_opr(reg); } else if (type == T_METADATA) { opr = as_metadata_opr(reg); + } else if (type == T_ADDRESS) { + opr = as_address_opr(reg); } else { opr = as_opr(reg); }
diff --git a/src/hotspot/cpu/sparc/c1_LIRAssembler_sparc.cpp b/src/hotspot/cpu/sparc/c1_LIRAssembler_sparc.cpp index fb4c8bd..e503159 100644 --- a/src/hotspot/cpu/sparc/c1_LIRAssembler_sparc.cpp +++ b/src/hotspot/cpu/sparc/c1_LIRAssembler_sparc.cpp
@@ -1507,6 +1507,18 @@ } break; + case T_METADATA: + // We only need, for now, comparison with NULL for metadata. + { assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); + Metadata* m = opr2->as_constant_ptr()->as_metadata(); + if (m == NULL) { + __ cmp(opr1->as_register(), 0); + } else { + ShouldNotReachHere(); + } + } + break; + default: ShouldNotReachHere(); break;
diff --git a/src/hotspot/cpu/sparc/c2_globals_sparc.hpp b/src/hotspot/cpu/sparc/c2_globals_sparc.hpp index d4279ea..988684d 100644 --- a/src/hotspot/cpu/sparc/c2_globals_sparc.hpp +++ b/src/hotspot/cpu/sparc/c2_globals_sparc.hpp
@@ -80,7 +80,7 @@ // Ergonomics related flags define_pd_global(uint64_t,MaxRAM, 128ULL*G); -define_pd_global(uintx, CodeCacheMinBlockLength, 4); +define_pd_global(uintx, CodeCacheMinBlockLength, 6); define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K); define_pd_global(bool, TrapBasedRangeChecks, false); // Not needed on sparc.
diff --git a/src/hotspot/cpu/sparc/frame_sparc.cpp b/src/hotspot/cpu/sparc/frame_sparc.cpp index 3985a87..6f5ab67 100644 --- a/src/hotspot/cpu/sparc/frame_sparc.cpp +++ b/src/hotspot/cpu/sparc/frame_sparc.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -648,7 +648,7 @@ Method* m = *interpreter_frame_method_addr(); // validate the method we'd find in this potential sender - if (!m->is_valid_method()) return false; + if (!Method::is_valid_method(m)) return false; // stack frames shouldn't be much larger than max_stack elements @@ -665,7 +665,7 @@ // validate ConstantPoolCache* ConstantPoolCache* cp = *interpreter_frame_cache_addr(); - if (cp == NULL || !cp->is_metaspace_object()) return false; + if (MetaspaceObj::is_valid(cp) == false) return false; // validate locals
diff --git a/src/hotspot/cpu/sparc/globals_sparc.hpp b/src/hotspot/cpu/sparc/globals_sparc.hpp index 38d2834..f0631f9 100644 --- a/src/hotspot/cpu/sparc/globals_sparc.hpp +++ b/src/hotspot/cpu/sparc/globals_sparc.hpp
@@ -37,7 +37,6 @@ // the load of the dispatch address and hence the jmp would still go to the location // according to the prior table. So, we let the thread continue and let it block by itself. define_pd_global(bool, DontYieldALot, true); // yield no more than 100 times per second -define_pd_global(bool, ShareVtableStubs, false); // improves performance markedly for mtrt and compress define_pd_global(bool, NeedsDeoptSuspend, true); // register window machines need this define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks
diff --git a/src/hotspot/cpu/sparc/nativeInst_sparc.cpp b/src/hotspot/cpu/sparc/nativeInst_sparc.cpp index 950619d..133cfeb 100644 --- a/src/hotspot/cpu/sparc/nativeInst_sparc.cpp +++ b/src/hotspot/cpu/sparc/nativeInst_sparc.cpp
@@ -572,15 +572,6 @@ //------------------------------------------------------------------- -void NativeMovRegMem::copy_instruction_to(address new_instruction_address) { - Untested("copy_instruction_to"); - int instruction_size = next_instruction_address() - instruction_address(); - for (int i = 0; i < instruction_size; i += BytesPerInstWord) { - *(int*)(new_instruction_address + i) = *(int*)(address(this) + i); - } -} - - void NativeMovRegMem::verify() { NativeInstruction::verify(); // make sure code pattern is actually a "ld" or "st" of some sort.
diff --git a/src/hotspot/cpu/sparc/nativeInst_sparc.hpp b/src/hotspot/cpu/sparc/nativeInst_sparc.hpp index 82225da..401377c 100644 --- a/src/hotspot/cpu/sparc/nativeInst_sparc.hpp +++ b/src/hotspot/cpu/sparc/nativeInst_sparc.hpp
@@ -574,7 +574,8 @@ // sethi and the add. The nop is required to be in the delay slot of the call instruction // which overwrites the sethi during patching. class NativeMovConstRegPatching; -inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address);class NativeMovConstRegPatching: public NativeInstruction { +inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address); +class NativeMovConstRegPatching: public NativeInstruction { public: enum Sparc_specific_constants { sethi_offset = 0, @@ -662,10 +663,13 @@ return (is_op(i0, Assembler::ldst_op)); } - address instruction_address() const { return addr_at(0); } - address next_instruction_address() const { - return addr_at(is_immediate() ? 4 : (7 * BytesPerInstWord)); + address instruction_address() const { return addr_at(0); } + + int num_bytes_to_end_of_patch() const { + return is_immediate()? BytesPerInstWord : + NativeMovConstReg::instruction_size; } + intptr_t offset() const { return is_immediate()? inv_simm(long_at(0), offset_width) : nativeMovConstReg_at(addr_at(0))->data(); @@ -682,8 +686,6 @@ set_offset (offset() + radd_offset); } - void copy_instruction_to(address new_instruction_address); - void verify(); void print ();
diff --git a/src/hotspot/cpu/sparc/sharedRuntime_sparc.cpp b/src/hotspot/cpu/sparc/sharedRuntime_sparc.cpp index 920565f..aa95c38 100644 --- a/src/hotspot/cpu/sparc/sharedRuntime_sparc.cpp +++ b/src/hotspot/cpu/sparc/sharedRuntime_sparc.cpp
@@ -1751,7 +1751,8 @@ int compile_id, BasicType* in_sig_bt, VMRegPair* in_regs, - BasicType ret_type) { + BasicType ret_type, + address critical_entry) { if (method->is_method_handle_intrinsic()) { vmIntrinsics::ID iid = method->intrinsic_id(); intptr_t start = (intptr_t)__ pc(); @@ -1774,7 +1775,7 @@ (OopMapSet*)NULL); } bool is_critical_native = true; - address native_func = method->critical_native_function(); + address native_func = critical_entry; if (native_func == NULL) { native_func = method->native_function(); is_critical_native = false;
diff --git a/src/hotspot/cpu/sparc/vm_version_ext_sparc.hpp b/src/hotspot/cpu/sparc/vm_version_ext_sparc.hpp index 767cc24..e924f5b 100644 --- a/src/hotspot/cpu/sparc/vm_version_ext_sparc.hpp +++ b/src/hotspot/cpu/sparc/vm_version_ext_sparc.hpp
@@ -25,8 +25,8 @@ #ifndef CPU_SPARC_VM_VM_VERSION_EXT_SPARC_HPP #define CPU_SPARC_VM_VM_VERSION_EXT_SPARC_HPP +#include "runtime/vm_version.hpp" #include "utilities/macros.hpp" -#include "vm_version_sparc.hpp" #if defined(SOLARIS) #include <kstat.h>
diff --git a/src/hotspot/cpu/sparc/vm_version_sparc.cpp b/src/hotspot/cpu/sparc/vm_version_sparc.cpp index 584b1b1..c9c9b05 100644 --- a/src/hotspot/cpu/sparc/vm_version_sparc.cpp +++ b/src/hotspot/cpu/sparc/vm_version_sparc.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -31,7 +31,7 @@ #include "runtime/java.hpp" #include "runtime/os.hpp" #include "runtime/stubCodeGenerator.hpp" -#include "vm_version_sparc.hpp" +#include "runtime/vm_version.hpp" #include <sys/mman.h> @@ -160,7 +160,8 @@ // Use compare and branch instructions if available. if (has_cbcond()) { - if (FLAG_IS_DEFAULT(UseCBCond)) { + // cbcond suspected to cause issues on Athena CPUs + if (FLAG_IS_DEFAULT(UseCBCond) && !is_athena()) { FLAG_SET_DEFAULT(UseCBCond, true); } } else if (UseCBCond) { @@ -218,7 +219,7 @@ char buf[512]; jio_snprintf(buf, sizeof(buf), - "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s" + "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s", (has_v9() ? "v9" : ""), @@ -228,6 +229,7 @@ (has_blk_init() ? ", blk_init" : ""), (has_fmaf() ? ", fmaf" : ""), (has_hpc() ? ", hpc" : ""), + (has_athena() ? ", athena" : ""), (has_ima() ? ", ima" : ""), (has_aes() ? ", aes" : ""), (has_des() ? ", des" : ""),
diff --git a/src/hotspot/cpu/sparc/vm_version_sparc.hpp b/src/hotspot/cpu/sparc/vm_version_sparc.hpp index 04ff200..6fffc0b 100644 --- a/src/hotspot/cpu/sparc/vm_version_sparc.hpp +++ b/src/hotspot/cpu/sparc/vm_version_sparc.hpp
@@ -25,8 +25,8 @@ #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP +#include "runtime/abstract_vm_version.hpp" #include "runtime/globals_extension.hpp" -#include "runtime/vm_version.hpp" class VM_Version: public Abstract_VM_Version { friend class VMStructs; @@ -42,6 +42,7 @@ ISA_FMAF, ISA_VIS3, ISA_HPC, + ISA_FJATHHPC, ISA_IMA, ISA_AES, ISA_DES, @@ -104,6 +105,7 @@ ISA_fmaf_msk = UINT64_C(1) << ISA_FMAF, ISA_vis3_msk = UINT64_C(1) << ISA_VIS3, ISA_hpc_msk = UINT64_C(1) << ISA_HPC, + ISA_fjathhpc_msk = UINT64_C(1) << ISA_FJATHHPC, ISA_ima_msk = UINT64_C(1) << ISA_IMA, ISA_aes_msk = UINT64_C(1) << ISA_AES, ISA_des_msk = UINT64_C(1) << ISA_DES, @@ -253,6 +255,7 @@ static bool has_fmaf() { return (_features & ISA_fmaf_msk) != 0; } static bool has_vis3() { return (_features & ISA_vis3_msk) != 0; } static bool has_hpc() { return (_features & ISA_hpc_msk) != 0; } + static bool has_athena() { return (_features & ISA_fjathhpc_msk) != 0; } static bool has_ima() { return (_features & ISA_ima_msk) != 0; } static bool has_aes() { return (_features & ISA_aes_msk) != 0; } static bool has_des() { return (_features & ISA_des_msk) != 0; } @@ -306,6 +309,10 @@ return (_features & niagara2_msk) == niagara2_msk; } + static bool is_athena() { + return has_athena() || has_athena_plus() || has_athena_plus2(); + } + // Default prefetch block size on SPARC. static uint prefetch_data_size() { return L2_data_cache_line_size(); }
diff --git a/src/hotspot/cpu/x86/assembler_x86.cpp b/src/hotspot/cpu/x86/assembler_x86.cpp index c3b2a20..373675c 100644 --- a/src/hotspot/cpu/x86/assembler_x86.cpp +++ b/src/hotspot/cpu/x86/assembler_x86.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -1379,6 +1379,15 @@ emit_int8(0xC0 | encode); } +void Assembler::vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { + assert(VM_Version::supports_vaes(), "requires vaes support/enabling"); + InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); + attributes.set_is_evex_instruction(); + int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); + emit_int8((unsigned char)0xDC); + emit_int8((unsigned char)(0xC0 | encode)); +} + void Assembler::aesenclast(XMMRegister dst, Address src) { assert(VM_Version::supports_aes(), ""); InstructionMark im(this); @@ -1396,6 +1405,15 @@ emit_int8((unsigned char)(0xC0 | encode)); } +void Assembler::vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { + assert(VM_Version::supports_vaes(), "requires vaes support/enabling"); + InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); + attributes.set_is_evex_instruction(); + int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); + emit_int8((unsigned char)0xDD); + emit_int8((unsigned char)(0xC0 | encode)); +} + void Assembler::andl(Address dst, int32_t imm32) { InstructionMark im(this); prefix(dst); @@ -1895,6 +1913,69 @@ emit_int8((unsigned char)(0xC0 | encode)); } +void Assembler::pabsb(XMMRegister dst, XMMRegister src) { + assert(VM_Version::supports_ssse3(), ""); + InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); + int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); + emit_int8(0x1C); + emit_int8((unsigned char)(0xC0 | encode)); +} + +void Assembler::pabsw(XMMRegister dst, XMMRegister src) { + assert(VM_Version::supports_ssse3(), ""); + InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); + int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); + emit_int8(0x1D); + emit_int8((unsigned char)(0xC0 | encode)); +} + +void Assembler::pabsd(XMMRegister dst, XMMRegister src) { + assert(VM_Version::supports_ssse3(), ""); + InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); + int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); + emit_int8(0x1E); + emit_int8((unsigned char)(0xC0 | encode)); +} + +void Assembler::vpabsb(XMMRegister dst, XMMRegister src, int vector_len) { + assert(vector_len == AVX_128bit? VM_Version::supports_avx() : + vector_len == AVX_256bit? VM_Version::supports_avx2() : + vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, ""); + InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); + int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); + emit_int8((unsigned char)0x1C); + emit_int8((unsigned char)(0xC0 | encode)); +} + +void Assembler::vpabsw(XMMRegister dst, XMMRegister src, int vector_len) { + assert(vector_len == AVX_128bit? VM_Version::supports_avx() : + vector_len == AVX_256bit? VM_Version::supports_avx2() : + vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, ""); + InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); + int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); + emit_int8((unsigned char)0x1D); + emit_int8((unsigned char)(0xC0 | encode)); +} + +void Assembler::vpabsd(XMMRegister dst, XMMRegister src, int vector_len) { + assert(vector_len == AVX_128bit? VM_Version::supports_avx() : + vector_len == AVX_256bit? VM_Version::supports_avx2() : + vector_len == AVX_512bit? VM_Version::supports_evex() : 0, ""); + InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); + int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); + emit_int8((unsigned char)0x1E); + emit_int8((unsigned char)(0xC0 | encode)); +} + +void Assembler::evpabsq(XMMRegister dst, XMMRegister src, int vector_len) { + assert(UseAVX > 2, ""); + InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); + attributes.set_is_evex_instruction(); + int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); + emit_int8((unsigned char)0x1F); + emit_int8((unsigned char)(0xC0 | encode)); +} + void Assembler::decl(Address dst) { // Don't use it directly. Use MacroAssembler::decrement() instead. InstructionMark im(this); @@ -2320,7 +2401,7 @@ InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); - emit_int8((unsigned char)0x90); + emit_int8((unsigned char)0x91); emit_operand((Register)src, dst); } @@ -3417,10 +3498,19 @@ InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); emit_int8(0x00); - emit_int8(0xC0 | encode); + emit_int8((unsigned char)(0xC0 | encode)); emit_int8(imm8); } +void Assembler::vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { + assert(UseAVX > 2, "requires AVX512F"); + InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); + attributes.set_is_evex_instruction(); + int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); + emit_int8((unsigned char)0x36); + emit_int8((unsigned char)(0xC0 | encode)); +} + void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) { assert(VM_Version::supports_avx2(), ""); InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); @@ -3885,6 +3975,14 @@ emit_int8((unsigned char)(0xC0 | encode)); } +void Assembler::pmovsxbw(XMMRegister dst, XMMRegister src) { + assert(VM_Version::supports_sse4_1(), ""); + InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); + int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); + emit_int8(0x20); + emit_int8((unsigned char)(0xC0 | encode)); +} + void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { assert(VM_Version::supports_avx(), ""); InstructionMark im(this); @@ -3906,6 +4004,15 @@ emit_int8((unsigned char) (0xC0 | encode)); } +void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) { + assert(vector_len == AVX_128bit? VM_Version::supports_avx() : + vector_len == AVX_256bit? VM_Version::supports_avx2() : + vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, ""); + InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); + int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); + emit_int8(0x20); + emit_int8((unsigned char)(0xC0 | encode)); +} void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) { assert(VM_Version::supports_avx512vlbw(), ""); @@ -4083,7 +4190,7 @@ void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { assert(vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : - 0, ""); + vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, ""); InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); emit_int8(0x00); @@ -4179,6 +4286,17 @@ emit_int8(shift); } +void Assembler::vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { + assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : + vector_len == AVX_256bit ? VM_Version::supports_avx2() : + vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, ""); + InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); + int encode = vex_prefix_and_encode(xmm3->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); + emit_int8(0x73); + emit_int8((unsigned char)(0xC0 | encode)); + emit_int8(shift & 0xFF); +} + void Assembler::pslldq(XMMRegister dst, int shift) { // Shift left 128 bit value in dst XMMRegister by shift number of bytes. NOT_LP64(assert(VM_Version::supports_sse2(), "")); @@ -4190,6 +4308,17 @@ emit_int8(shift); } +void Assembler::vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { + assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : + vector_len == AVX_256bit ? VM_Version::supports_avx2() : + vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, ""); + InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); + int encode = vex_prefix_and_encode(xmm7->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); + emit_int8(0x73); + emit_int8((unsigned char)(0xC0 | encode)); + emit_int8(shift & 0xFF); +} + void Assembler::ptest(XMMRegister dst, Address src) { assert(VM_Version::supports_sse4_1(), ""); assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); @@ -4201,7 +4330,7 @@ } void Assembler::ptest(XMMRegister dst, XMMRegister src) { - assert(VM_Version::supports_sse4_1(), ""); + assert(VM_Version::supports_sse4_1() || VM_Version::supports_avx(), ""); InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); emit_int8(0x17); @@ -4575,6 +4704,25 @@ emit_int8((unsigned char)0xA5); } +void Assembler::roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { + assert(VM_Version::supports_sse4_1(), ""); + InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); + int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); + emit_int8(0x0B); + emit_int8((unsigned char)(0xC0 | encode)); + emit_int8((unsigned char)rmode); +} + +void Assembler::roundsd(XMMRegister dst, Address src, int32_t rmode) { + assert(VM_Version::supports_sse4_1(), ""); + InstructionMark im(this); + InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); + simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); + emit_int8(0x0B); + emit_operand(dst, src); + emit_int8((unsigned char)rmode); +} + void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { NOT_LP64(assert(VM_Version::supports_sse2(), "")); InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); @@ -5372,6 +5520,49 @@ emit_operand(dst, src); } +void Assembler::vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) { + assert(VM_Version::supports_avx(), ""); + InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); + int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); + emit_int8(0x09); + emit_int8((unsigned char)(0xC0 | encode)); + emit_int8((unsigned char)(rmode)); +} + +void Assembler::vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len) { + assert(VM_Version::supports_avx(), ""); + InstructionMark im(this); + InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); + vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); + emit_int8(0x09); + emit_operand(dst, src); + emit_int8((unsigned char)(rmode)); +} + +void Assembler::vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) { + assert(VM_Version::supports_evex(), "requires EVEX support"); + InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); + attributes.set_is_evex_instruction(); + int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); + emit_int8((unsigned char)0x09); + emit_int8((unsigned char)(0xC0 | encode)); + emit_int8((unsigned char)(rmode)); +} + +void Assembler::vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len) { + assert(VM_Version::supports_evex(), "requires EVEX support"); + assert(dst != xnoreg, "sanity"); + InstructionMark im(this); + InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); + attributes.set_is_evex_instruction(); + attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); + vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); + emit_int8((unsigned char)0x09); + emit_operand(dst, src); + emit_int8((unsigned char)(rmode)); +} + + void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) { assert(VM_Version::supports_avx(), ""); InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); @@ -6228,6 +6419,26 @@ emit_int8((unsigned char)(0xC0 | encode)); } +void Assembler::evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { + assert(UseAVX > 2, "requires AVX512"); + assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl"); + InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); + attributes.set_is_evex_instruction(); + int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); + emit_int8((unsigned char)0x72); + emit_int8((unsigned char)(0xC0 | encode)); + emit_int8(shift & 0xFF); +} + +void Assembler::evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { + assert(UseAVX > 2, "requires AVX512"); + assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl"); + InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); + attributes.set_is_evex_instruction(); + int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); + emit_int8((unsigned char)0xE2); + emit_int8((unsigned char)(0xC0 | encode)); +} // logical operations packed integers void Assembler::pand(XMMRegister dst, XMMRegister src) { @@ -6366,6 +6577,17 @@ } +void Assembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) { + assert(VM_Version::supports_evex(), "requires EVEX support"); + assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support"); + InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); + attributes.set_is_evex_instruction(); + int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); + emit_int8(0x25); + emit_int8((unsigned char)(0xC0 | encode)); + emit_int8(imm8); +} + // vinserti forms void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { @@ -6836,6 +7058,21 @@ emit_int8(0x59); emit_operand(dst, src); } + +void Assembler::evbroadcasti32x4(XMMRegister dst, Address src, int vector_len) { + assert(vector_len != Assembler::AVX_128bit, ""); + assert(VM_Version::supports_avx512dq(), ""); + assert(dst != xnoreg, "sanity"); + InstructionMark im(this); + InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); + attributes.set_rex_vex_w_reverted(); + attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit); + // swap src<->dst for encoding + vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); + emit_int8(0x5A); + emit_operand(dst, src); +} + void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) { assert(vector_len != Assembler::AVX_128bit, ""); assert(VM_Version::supports_avx512dq(), ""); @@ -6948,7 +7185,6 @@ emit_int8(0x7C); emit_int8((unsigned char)(0xC0 | encode)); } - void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) { assert(VM_Version::supports_evex(), ""); assert(dst != xnoreg, "sanity"); @@ -6963,7 +7199,6 @@ emit_int8((unsigned char)0x90); emit_operand(dst, src); } - // Carry-Less Multiplication Quadword void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) { assert(VM_Version::supports_clmul(), ""); @@ -6985,7 +7220,7 @@ } void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) { - assert(VM_Version::supports_vpclmulqdq(), "Requires vector carryless multiplication support"); + assert(VM_Version::supports_avx512_vpclmulqdq(), "Requires vector carryless multiplication support"); InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); attributes.set_is_evex_instruction(); int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); @@ -7716,9 +7951,43 @@ } } +void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) { + assert(VM_Version::supports_avx(), ""); + InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); + int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); + emit_int8(0x5F); + emit_int8((unsigned char)(0xC0 | encode)); +} + +void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { + assert(VM_Version::supports_avx(), ""); + InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); + attributes.set_rex_vex_w_reverted(); + int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); + emit_int8(0x5F); + emit_int8((unsigned char)(0xC0 | encode)); +} + +void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) { + assert(VM_Version::supports_avx(), ""); + InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); + int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); + emit_int8(0x5D); + emit_int8((unsigned char)(0xC0 | encode)); +} + +void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { + assert(VM_Version::supports_avx(), ""); + InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); + attributes.set_rex_vex_w_reverted(); + int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); + emit_int8(0x5D); + emit_int8((unsigned char)(0xC0 | encode)); +} + void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) { assert(VM_Version::supports_avx(), ""); - assert(!VM_Version::supports_evex(), ""); + assert(vector_len <= AVX_256bit, ""); InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); emit_int8((unsigned char)0xC2); @@ -7726,9 +7995,20 @@ emit_int8((unsigned char)(0xF & cop)); } +void Assembler::blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) { + assert(VM_Version::supports_avx(), ""); + assert(vector_len <= AVX_256bit, ""); + InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); + int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); + int src2_enc = src2->encoding(); + emit_int8((unsigned char)0x4C); + emit_int8((unsigned char)(0xC0 | encode)); + emit_int8((unsigned char)(0xF0 & src2_enc<<4)); +} + void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) { assert(VM_Version::supports_avx(), ""); - assert(!VM_Version::supports_evex(), ""); + assert(vector_len <= AVX_256bit, ""); InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); emit_int8((unsigned char)0x4B); @@ -7739,7 +8019,7 @@ void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) { assert(VM_Version::supports_avx(), ""); - assert(!VM_Version::supports_evex(), ""); + assert(vector_len <= AVX_256bit, ""); InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); emit_int8((unsigned char)0xC2); @@ -7749,7 +8029,7 @@ void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) { assert(VM_Version::supports_avx(), ""); - assert(!VM_Version::supports_evex(), ""); + assert(vector_len <= AVX_256bit, ""); InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); emit_int8((unsigned char)0x4A); @@ -8441,7 +8721,7 @@ void Assembler::cmpq(Address dst, Register src) { InstructionMark im(this); prefixq(dst, src); - emit_int8(0x3B); + emit_int8(0x39); emit_operand(src, dst); }
diff --git a/src/hotspot/cpu/x86/assembler_x86.hpp b/src/hotspot/cpu/x86/assembler_x86.hpp index 45fa423..704cf22 100644 --- a/src/hotspot/cpu/x86/assembler_x86.hpp +++ b/src/hotspot/cpu/x86/assembler_x86.hpp
@@ -26,7 +26,7 @@ #define CPU_X86_VM_ASSEMBLER_X86_HPP #include "asm/register.hpp" -#include "vm_version_x86.hpp" +#include "runtime/vm_version.hpp" class BiasedLockingCounters; @@ -957,6 +957,9 @@ void aesenc(XMMRegister dst, XMMRegister src); void aesenclast(XMMRegister dst, Address src); void aesenclast(XMMRegister dst, XMMRegister src); + // Vector AES instructions + void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); + void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); @@ -1102,6 +1105,15 @@ void cvttpd2dq(XMMRegister dst, XMMRegister src); + //Abs of packed Integer values + void pabsb(XMMRegister dst, XMMRegister src); + void pabsw(XMMRegister dst, XMMRegister src); + void pabsd(XMMRegister dst, XMMRegister src); + void vpabsb(XMMRegister dst, XMMRegister src, int vector_len); + void vpabsw(XMMRegister dst, XMMRegister src, int vector_len); + void vpabsd(XMMRegister dst, XMMRegister src, int vector_len); + void evpabsq(XMMRegister dst, XMMRegister src, int vector_len); + // Divide Scalar Double-Precision Floating-Point Values void divsd(XMMRegister dst, Address src); void divsd(XMMRegister dst, XMMRegister src); @@ -1583,6 +1595,7 @@ // Pemutation of 64bit words void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len); void vpermq(XMMRegister dst, XMMRegister src, int imm8); + void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); void vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8); void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8); void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); @@ -1662,6 +1675,10 @@ void evpmovdb(Address dst, XMMRegister src, int vector_len); + // Sign extend moves + void pmovsxbw(XMMRegister dst, XMMRegister src); + void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len); + #ifndef _LP64 // no 32bit push/pop on amd64 void popl(Address dst); #endif @@ -1813,6 +1830,9 @@ void sqrtsd(XMMRegister dst, Address src); void sqrtsd(XMMRegister dst, XMMRegister src); + void roundsd(XMMRegister dst, Address src, int32_t rmode); + void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode); + // Compute Square Root of Scalar Single-Precision Floating-Point Value void sqrtss(XMMRegister dst, Address src); void sqrtss(XMMRegister dst, XMMRegister src); @@ -1922,6 +1942,11 @@ void vsubss(XMMRegister dst, XMMRegister nds, Address src); void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); + void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src); + void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src); + void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src); + void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src); + void shlxl(Register dst, Register src1, Register src2); void shlxq(Register dst, Register src1, Register src2); @@ -1972,6 +1997,12 @@ void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len); void vsqrtps(XMMRegister dst, Address src, int vector_len); + // Round Packed Double precision value. + void vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len); + void vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len); + void vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len); + void vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len); + // Bitwise Logical AND of Packed Floating-Point Values void andpd(XMMRegister dst, XMMRegister src); void andps(XMMRegister dst, XMMRegister src); @@ -2049,6 +2080,7 @@ void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); + void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len); // Logical shift right packed integers void psrlw(XMMRegister dst, int shift); @@ -2063,6 +2095,7 @@ void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); + void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len); void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); @@ -2075,6 +2108,8 @@ void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len); void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); + void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len); + void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); // And packed integers void pand(XMMRegister dst, XMMRegister src); @@ -2099,6 +2134,8 @@ void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len); + // Ternary logic instruction. + void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len); // vinserti forms void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); @@ -2143,6 +2180,7 @@ void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len); void vpbroadcastq(XMMRegister dst, Address src, int vector_len); + void evbroadcasti32x4(XMMRegister dst, Address src, int vector_len); void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len); void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len); @@ -2172,6 +2210,7 @@ void vzeroupper(); // AVX support for vectorized conditional move (float/double). The following two instructions used only coupled. + void blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len); void cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len); void blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len); void cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
diff --git a/src/hotspot/cpu/x86/c1_FrameMap_x86.cpp b/src/hotspot/cpu/x86/c1_FrameMap_x86.cpp index 13eefe5..01e67a8 100644 --- a/src/hotspot/cpu/x86/c1_FrameMap_x86.cpp +++ b/src/hotspot/cpu/x86/c1_FrameMap_x86.cpp
@@ -54,6 +54,8 @@ opr = as_oop_opr(reg); } else if (type == T_METADATA) { opr = as_metadata_opr(reg); + } else if (type == T_ADDRESS) { + opr = as_address_opr(reg); } else { opr = as_opr(reg); }
diff --git a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp index 449cee1..cee3140 100644 --- a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp +++ b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp
@@ -919,7 +919,7 @@ if (type == T_OBJECT || type == T_ARRAY) { __ verify_oop(src->as_register()); __ movptr (dst, src->as_register()); - } else if (type == T_METADATA) { + } else if (type == T_METADATA || type == T_ADDRESS) { __ movptr (dst, src->as_register()); } else { __ movl (dst, src->as_register()); @@ -1100,7 +1100,7 @@ if (type == T_ARRAY || type == T_OBJECT) { __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); __ verify_oop(dest->as_register()); - } else if (type == T_METADATA) { + } else if (type == T_METADATA || type == T_ADDRESS) { __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); } else { __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); @@ -2637,6 +2637,15 @@ LIR_Const* c = opr2->as_constant_ptr(); if (c->type() == T_INT) { __ cmpl(reg1, c->as_jint()); + } else if (c->type() == T_METADATA) { + // All we need for now is a comparison with NULL for equality. + assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); + Metadata* m = c->as_metadata(); + if (m == NULL) { + __ cmpptr(reg1, (int32_t)0); + } else { + ShouldNotReachHere(); + } } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { // In 64bit oops are single register jobject o = c->as_jobject();
diff --git a/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp b/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp index 7441dad..231e5a1 100644 --- a/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp +++ b/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp
@@ -36,6 +36,7 @@ #include "gc/shared/c1/barrierSetC1.hpp" #include "runtime/sharedRuntime.hpp" #include "runtime/stubRoutines.hpp" +#include "utilities/macros.hpp" #include "vmreg_x86.inline.hpp" #ifdef ASSERT @@ -674,6 +675,11 @@ if (type == T_OBJECT || type == T_ARRAY) { cmp_value.load_item_force(FrameMap::rax_oop_opr); new_value.load_item(); +#if INCLUDE_SHENANDOAHGC + if (UseShenandoahGC) { + __ cas_obj(addr->as_address_ptr()->base(), cmp_value.result(), new_value.result(), new_register(T_OBJECT), new_register(T_OBJECT)); + } else +#endif __ cas_obj(addr->as_address_ptr()->base(), cmp_value.result(), new_value.result(), ill, ill); } else if (type == T_INT) { cmp_value.load_item_force(FrameMap::rax_opr); @@ -699,6 +705,12 @@ // Because we want a 2-arg form of xchg and xadd __ move(value.result(), result); assert(type == T_INT || is_oop LP64_ONLY( || type == T_LONG ), "unexpected type"); +#if INCLUDE_SHENANDOAHGC + if (UseShenandoahGC) { + LIR_Opr tmp = is_oop ? new_register(type) : LIR_OprFact::illegalOpr; + __ xchg(addr, result, result, tmp); + } else +#endif __ xchg(addr, result, result, LIR_OprFact::illegalOpr); return result; }
diff --git a/src/hotspot/cpu/x86/c1_LinearScan_x86.cpp b/src/hotspot/cpu/x86/c1_LinearScan_x86.cpp index 54a0c56..6789cc6 100644 --- a/src/hotspot/cpu/x86/c1_LinearScan_x86.cpp +++ b/src/hotspot/cpu/x86/c1_LinearScan_x86.cpp
@@ -545,21 +545,6 @@ break; } - case lir_neg: { - if (in->is_fpu_register() && !in->is_xmm_register()) { - assert(res->is_fpu_register() && !res->is_xmm_register(), "must be"); - assert(in->is_last_use(), "old value gets destroyed"); - - insert_free_if_dead(res, in); - insert_exchange(in); - new_in = to_fpu_stack_top(in); - - do_rename(in, res); - new_res = to_fpu_stack_top(res); - } - break; - } - case lir_convert: { Bytecodes::Code bc = op1->as_OpConvert()->bytecode(); switch (bc) { @@ -767,7 +752,8 @@ } case lir_abs: - case lir_sqrt: { + case lir_sqrt: + case lir_neg: { // Right argument appears to be unused assert(right->is_illegal(), "must be"); assert(left->is_fpu_register(), "must be");
diff --git a/src/hotspot/cpu/x86/c1_Runtime1_x86.cpp b/src/hotspot/cpu/x86/c1_Runtime1_x86.cpp index f9d9151..9364928 100644 --- a/src/hotspot/cpu/x86/c1_Runtime1_x86.cpp +++ b/src/hotspot/cpu/x86/c1_Runtime1_x86.cpp
@@ -171,8 +171,8 @@ #ifdef _LP64 // if there is any conflict use the stack if (arg1 == c_rarg2 || arg1 == c_rarg3 || - arg2 == c_rarg1 || arg1 == c_rarg3 || - arg3 == c_rarg1 || arg1 == c_rarg2) { + arg2 == c_rarg1 || arg2 == c_rarg3 || + arg3 == c_rarg1 || arg3 == c_rarg2) { push(arg3); push(arg2); push(arg1);
diff --git a/src/hotspot/cpu/x86/c2_globals_x86.hpp b/src/hotspot/cpu/x86/c2_globals_x86.hpp index b7e7597..73db10f 100644 --- a/src/hotspot/cpu/x86/c2_globals_x86.hpp +++ b/src/hotspot/cpu/x86/c2_globals_x86.hpp
@@ -88,7 +88,7 @@ define_pd_global(uintx, NonProfiledCodeHeapSize, 21*M); define_pd_global(uintx, ProfiledCodeHeapSize, 22*M); define_pd_global(uintx, NonNMethodCodeHeapSize, 5*M ); -define_pd_global(uintx, CodeCacheMinBlockLength, 4); +define_pd_global(uintx, CodeCacheMinBlockLength, 6); define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K); define_pd_global(bool, TrapBasedRangeChecks, false); // Not needed on x86.
diff --git a/src/hotspot/cpu/x86/frame_x86.cpp b/src/hotspot/cpu/x86/frame_x86.cpp index 26e2437..34a1a73 100644 --- a/src/hotspot/cpu/x86/frame_x86.cpp +++ b/src/hotspot/cpu/x86/frame_x86.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -526,7 +526,7 @@ Method* m = *interpreter_frame_method_addr(); // validate the method we'd find in this potential sender - if (!m->is_valid_method()) return false; + if (!Method::is_valid_method(m)) return false; // stack frames shouldn't be much larger than max_stack elements // this test requires the use the unextended_sp which is the sp as seen by @@ -546,7 +546,7 @@ // validate ConstantPoolCache* ConstantPoolCache* cp = *interpreter_frame_cache_addr(); - if (cp == NULL || !cp->is_metaspace_object()) return false; + if (MetaspaceObj::is_valid(cp) == false) return false; // validate locals
diff --git a/src/hotspot/cpu/x86/gc/shared/modRefBarrierSetAssembler_x86.cpp b/src/hotspot/cpu/x86/gc/shared/modRefBarrierSetAssembler_x86.cpp index 19b7eec..888ca13 100644 --- a/src/hotspot/cpu/x86/gc/shared/modRefBarrierSetAssembler_x86.cpp +++ b/src/hotspot/cpu/x86/gc/shared/modRefBarrierSetAssembler_x86.cpp
@@ -36,12 +36,14 @@ if (type == T_OBJECT || type == T_ARRAY) { #ifdef _LP64 - if (!checkcast && !obj_int) { - // Save count for barrier - __ movptr(r11, count); - } else if (disjoint && obj_int) { - // Save dst in r11 in the disjoint case - __ movq(r11, dst); + if (!checkcast) { + if (!obj_int) { + // Save count for barrier + __ movptr(r11, count); + } else if (disjoint) { + // Save dst in r11 in the disjoint case + __ movq(r11, dst); + } } #else if (disjoint) { @@ -61,13 +63,15 @@ if (type == T_OBJECT || type == T_ARRAY) { #ifdef _LP64 - if (!checkcast && !obj_int) { - // Save count for barrier - count = r11; - } else if (disjoint && obj_int) { - // Use the saved dst in the disjoint case - dst = r11; - } else if (checkcast) { + if (!checkcast) { + if (!obj_int) { + // Save count for barrier + count = r11; + } else if (disjoint) { + // Use the saved dst in the disjoint case + dst = r11; + } + } else { tmp = rscratch1; } #else
diff --git a/src/hotspot/cpu/x86/gc/shenandoah/c1/shenandoahBarrierSetC1_x86.cpp b/src/hotspot/cpu/x86/gc/shenandoah/c1/shenandoahBarrierSetC1_x86.cpp new file mode 100644 index 0000000..26ce2b7 --- /dev/null +++ b/src/hotspot/cpu/x86/gc/shenandoah/c1/shenandoahBarrierSetC1_x86.cpp
@@ -0,0 +1,124 @@ +/* + * Copyright (c) 2018, Red Hat, Inc. All rights reserved. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#include "precompiled.hpp" +#include "c1/c1_LIRAssembler.hpp" +#include "c1/c1_MacroAssembler.hpp" +#include "gc/shenandoah/shenandoahBarrierSet.hpp" +#include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" +#include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp" + +#define __ masm->masm()-> + +void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) { + NOT_LP64(assert(_addr->is_single_cpu(), "must be single");) + Register addr = _addr->is_single_cpu() ? _addr->as_register() : _addr->as_register_lo(); + Register newval = _new_value->as_register(); + Register cmpval = _cmp_value->as_register(); + Register tmp1 = _tmp1->as_register(); + Register tmp2 = _tmp2->as_register(); + Register result = result_opr()->as_register(); + assert(cmpval == rax, "wrong register"); + assert(newval != NULL, "new val must be register"); + assert(cmpval != newval, "cmp and new values must be in different registers"); + assert(cmpval != addr, "cmp and addr must be in different registers"); + assert(newval != addr, "new value and addr must be in different registers"); + + // Apply IU barrier to newval. + ShenandoahBarrierSet::assembler()->iu_barrier(masm->masm(), newval, tmp1); + +#ifdef _LP64 + if (UseCompressedOops) { + __ encode_heap_oop(cmpval); + __ mov(rscratch1, newval); + __ encode_heap_oop(rscratch1); + newval = rscratch1; + } +#endif + + ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), result, Address(addr, 0), cmpval, newval, false, tmp1, tmp2); +} + +#undef __ + +#ifdef ASSERT +#define __ gen->lir(__FILE__, __LINE__)-> +#else +#define __ gen->lir()-> +#endif + +LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) { + + if (access.is_oop()) { + LIRGenerator* gen = access.gen(); + if (ShenandoahSATBBarrier) { + pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(), + LIR_OprFact::illegalOpr /* pre_val */); + } + if (ShenandoahCASBarrier) { + cmp_value.load_item_force(FrameMap::rax_oop_opr); + new_value.load_item(); + + LIR_Opr t1 = gen->new_register(T_OBJECT); + LIR_Opr t2 = gen->new_register(T_OBJECT); + LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base(); + LIR_Opr result = gen->new_register(T_INT); + + __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result)); + return result; + } + } + return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value); +} + +LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) { + LIRGenerator* gen = access.gen(); + BasicType type = access.type(); + + LIR_Opr result = gen->new_register(type); + value.load_item(); + LIR_Opr value_opr = value.result(); + + if (access.is_oop()) { + value_opr = iu_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators()); + } + + // Because we want a 2-arg form of xchg and xadd + __ move(value_opr, result); + + assert(type == T_INT || type == T_OBJECT || type == T_ARRAY LP64_ONLY( || type == T_LONG ), "unexpected type"); + __ xchg(access.resolved_addr(), result, result, LIR_OprFact::illegalOpr); + + if (access.is_oop()) { + result = load_reference_barrier(access.gen(), result, LIR_OprFact::addressConst(0)); + LIR_Opr tmp = gen->new_register(type); + __ move(result, tmp); + result = tmp; + if (ShenandoahSATBBarrier) { + pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr, + result /* pre_val */); + } + } + + return result; +}
diff --git a/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp b/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp new file mode 100644 index 0000000..cffa789 --- /dev/null +++ b/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp
@@ -0,0 +1,1273 @@ +/* + * Copyright (c) 2018, 2019, Red Hat, Inc. All rights reserved. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#include "precompiled.hpp" +#include "gc/shenandoah/shenandoahBarrierSet.hpp" +#include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" +#include "gc/shenandoah/shenandoahForwarding.hpp" +#include "gc/shenandoah/shenandoahHeap.hpp" +#include "gc/shenandoah/shenandoahHeapRegion.hpp" +#include "gc/shenandoah/shenandoahRuntime.hpp" +#include "gc/shenandoah/shenandoahThreadLocalData.hpp" +#include "gc/shenandoah/heuristics/shenandoahHeuristics.hpp" +#include "interpreter/interpreter.hpp" +#include "interpreter/interp_masm.hpp" +#include "runtime/sharedRuntime.hpp" +#include "runtime/thread.hpp" +#include "utilities/macros.hpp" +#include "vmreg_x86.inline.hpp" +#ifdef COMPILER1 +#include "c1/c1_LIRAssembler.hpp" +#include "c1/c1_MacroAssembler.hpp" +#include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp" +#endif + +#define __ masm-> + +address ShenandoahBarrierSetAssembler::_shenandoah_lrb = NULL; + +static void save_machine_state(MacroAssembler* masm, bool handle_gpr, bool handle_fp) { + if (handle_gpr) { + __ push_IU_state(); + } + + if (handle_fp) { + // Some paths can be reached from the c2i adapter with live fp arguments in registers. + LP64_ONLY(assert(Argument::n_float_register_parameters_j == 8, "8 fp registers to save at java call")); + + if (UseSSE >= 2) { + const int xmm_size = wordSize * LP64_ONLY(2) NOT_LP64(4); + __ subptr(rsp, xmm_size * 8); + __ movdbl(Address(rsp, xmm_size * 0), xmm0); + __ movdbl(Address(rsp, xmm_size * 1), xmm1); + __ movdbl(Address(rsp, xmm_size * 2), xmm2); + __ movdbl(Address(rsp, xmm_size * 3), xmm3); + __ movdbl(Address(rsp, xmm_size * 4), xmm4); + __ movdbl(Address(rsp, xmm_size * 5), xmm5); + __ movdbl(Address(rsp, xmm_size * 6), xmm6); + __ movdbl(Address(rsp, xmm_size * 7), xmm7); + } else if (UseSSE >= 1) { + const int xmm_size = wordSize * LP64_ONLY(1) NOT_LP64(2); + __ subptr(rsp, xmm_size * 8); + __ movflt(Address(rsp, xmm_size * 0), xmm0); + __ movflt(Address(rsp, xmm_size * 1), xmm1); + __ movflt(Address(rsp, xmm_size * 2), xmm2); + __ movflt(Address(rsp, xmm_size * 3), xmm3); + __ movflt(Address(rsp, xmm_size * 4), xmm4); + __ movflt(Address(rsp, xmm_size * 5), xmm5); + __ movflt(Address(rsp, xmm_size * 6), xmm6); + __ movflt(Address(rsp, xmm_size * 7), xmm7); + } else { + __ push_FPU_state(); + } + } +} + +static void restore_machine_state(MacroAssembler* masm, bool handle_gpr, bool handle_fp) { + if (handle_fp) { + if (UseSSE >= 2) { + const int xmm_size = wordSize * LP64_ONLY(2) NOT_LP64(4); + __ movdbl(xmm0, Address(rsp, xmm_size * 0)); + __ movdbl(xmm1, Address(rsp, xmm_size * 1)); + __ movdbl(xmm2, Address(rsp, xmm_size * 2)); + __ movdbl(xmm3, Address(rsp, xmm_size * 3)); + __ movdbl(xmm4, Address(rsp, xmm_size * 4)); + __ movdbl(xmm5, Address(rsp, xmm_size * 5)); + __ movdbl(xmm6, Address(rsp, xmm_size * 6)); + __ movdbl(xmm7, Address(rsp, xmm_size * 7)); + __ addptr(rsp, xmm_size * 8); + } else if (UseSSE >= 1) { + const int xmm_size = wordSize * LP64_ONLY(1) NOT_LP64(2); + __ movflt(xmm0, Address(rsp, xmm_size * 0)); + __ movflt(xmm1, Address(rsp, xmm_size * 1)); + __ movflt(xmm2, Address(rsp, xmm_size * 2)); + __ movflt(xmm3, Address(rsp, xmm_size * 3)); + __ movflt(xmm4, Address(rsp, xmm_size * 4)); + __ movflt(xmm5, Address(rsp, xmm_size * 5)); + __ movflt(xmm6, Address(rsp, xmm_size * 6)); + __ movflt(xmm7, Address(rsp, xmm_size * 7)); + __ addptr(rsp, xmm_size * 8); + } else { + __ pop_FPU_state(); + } + } + + if (handle_gpr) { + __ pop_IU_state(); + } +} + +void ShenandoahBarrierSetAssembler::arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Register src, Register dst, Register count) { + + bool dest_uninitialized = (decorators & IS_DEST_UNINITIALIZED) != 0; + + if (type == T_OBJECT || type == T_ARRAY) { + + if ((ShenandoahSATBBarrier && !dest_uninitialized) || ShenandoahIUBarrier || ShenandoahLoadRefBarrier) { +#ifdef _LP64 + Register thread = r15_thread; +#else + Register thread = rax; + if (thread == src || thread == dst || thread == count) { + thread = rbx; + } + if (thread == src || thread == dst || thread == count) { + thread = rcx; + } + if (thread == src || thread == dst || thread == count) { + thread = rdx; + } + __ push(thread); + __ get_thread(thread); +#endif + assert_different_registers(src, dst, count, thread); + + Label done; + // Short-circuit if count == 0. + __ testptr(count, count); + __ jcc(Assembler::zero, done); + + // Avoid runtime call when not active. + Address gc_state(thread, in_bytes(ShenandoahThreadLocalData::gc_state_offset())); + int flags; + if (ShenandoahSATBBarrier && dest_uninitialized) { + flags = ShenandoahHeap::HAS_FORWARDED; + } else { + flags = ShenandoahHeap::HAS_FORWARDED | ShenandoahHeap::MARKING; + } + __ testb(gc_state, flags); + __ jcc(Assembler::zero, done); + + save_machine_state(masm, /* handle_gpr = */ true, /* handle_fp = */ false); + +#ifdef _LP64 + assert(src == rdi, "expected"); + assert(dst == rsi, "expected"); + assert(count == rdx, "expected"); + if (UseCompressedOops) { + __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::arraycopy_barrier_narrow_oop_entry), + src, dst, count); + } else +#endif + { + __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::arraycopy_barrier_oop_entry), + src, dst, count); + } + + restore_machine_state(masm, /* handle_gpr = */ true, /* handle_fp = */ false); + + __ bind(done); + NOT_LP64(__ pop(thread);) + } + } + +} + +void ShenandoahBarrierSetAssembler::shenandoah_write_barrier_pre(MacroAssembler* masm, + Register obj, + Register pre_val, + Register thread, + Register tmp, + bool tosca_live, + bool expand_call) { + + if (ShenandoahSATBBarrier) { + satb_write_barrier_pre(masm, obj, pre_val, thread, tmp, tosca_live, expand_call); + } +} + +void ShenandoahBarrierSetAssembler::satb_write_barrier_pre(MacroAssembler* masm, + Register obj, + Register pre_val, + Register thread, + Register tmp, + bool tosca_live, + bool expand_call) { + // If expand_call is true then we expand the call_VM_leaf macro + // directly to skip generating the check by + // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. + +#ifdef _LP64 + assert(thread == r15_thread, "must be"); +#endif // _LP64 + + Label done; + Label runtime; + + assert(pre_val != noreg, "check this code"); + + if (obj != noreg) { + assert_different_registers(obj, pre_val, tmp); + assert(pre_val != rax, "check this code"); + } + + Address in_progress(thread, in_bytes(ShenandoahThreadLocalData::satb_mark_queue_active_offset())); + Address index(thread, in_bytes(ShenandoahThreadLocalData::satb_mark_queue_index_offset())); + Address buffer(thread, in_bytes(ShenandoahThreadLocalData::satb_mark_queue_buffer_offset())); + + Address gc_state(thread, in_bytes(ShenandoahThreadLocalData::gc_state_offset())); + __ testb(gc_state, ShenandoahHeap::MARKING); + __ jcc(Assembler::zero, done); + + // Do we need to load the previous value? + if (obj != noreg) { + __ load_heap_oop(pre_val, Address(obj, 0), noreg, noreg, AS_RAW); + } + + // Is the previous value null? + __ cmpptr(pre_val, (int32_t) NULL_WORD); + __ jcc(Assembler::equal, done); + + // Can we store original value in the thread's buffer? + // Is index == 0? + // (The index field is typed as size_t.) + + __ movptr(tmp, index); // tmp := *index_adr + __ cmpptr(tmp, 0); // tmp == 0? + __ jcc(Assembler::equal, runtime); // If yes, goto runtime + + __ subptr(tmp, wordSize); // tmp := tmp - wordSize + __ movptr(index, tmp); // *index_adr := tmp + __ addptr(tmp, buffer); // tmp := tmp + *buffer_adr + + // Record the previous value + __ movptr(Address(tmp, 0), pre_val); + __ jmp(done); + + __ bind(runtime); + // save the live input values + if(tosca_live) __ push(rax); + + if (obj != noreg && obj != rax) + __ push(obj); + + if (pre_val != rax) + __ push(pre_val); + + // Calling the runtime using the regular call_VM_leaf mechanism generates + // code (generated by InterpreterMacroAssember::call_VM_leaf_base) + // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. + // + // If we care generating the pre-barrier without a frame (e.g. in the + // intrinsified Reference.get() routine) then ebp might be pointing to + // the caller frame and so this check will most likely fail at runtime. + // + // Expanding the call directly bypasses the generation of the check. + // So when we do not have have a full interpreter frame on the stack + // expand_call should be passed true. + + NOT_LP64( __ push(thread); ) + +#ifdef _LP64 + // We move pre_val into c_rarg0 early, in order to avoid smashing it, should + // pre_val be c_rarg1 (where the call prologue would copy thread argument). + // Note: this should not accidentally smash thread, because thread is always r15. + assert(thread != c_rarg0, "smashed arg"); + if (c_rarg0 != pre_val) { + __ mov(c_rarg0, pre_val); + } +#endif + + if (expand_call) { + LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) +#ifdef _LP64 + if (c_rarg1 != thread) { + __ mov(c_rarg1, thread); + } + // Already moved pre_val into c_rarg0 above +#else + __ push(thread); + __ push(pre_val); +#endif + __ MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, ShenandoahRuntime::write_ref_field_pre_entry), 2); + } else { + __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::write_ref_field_pre_entry), LP64_ONLY(c_rarg0) NOT_LP64(pre_val), thread); + } + + NOT_LP64( __ pop(thread); ) + + // save the live input values + if (pre_val != rax) + __ pop(pre_val); + + if (obj != noreg && obj != rax) + __ pop(obj); + + if(tosca_live) __ pop(rax); + + __ bind(done); +} + +void ShenandoahBarrierSetAssembler::load_reference_barrier_not_null(MacroAssembler* masm, Register dst, Address src) { + assert(ShenandoahLoadRefBarrier, "Should be enabled"); + + Label done; + +#ifdef _LP64 + Register thread = r15_thread; +#else + Register thread = rcx; + if (thread == dst) { + thread = rbx; + } + __ push(thread); + __ get_thread(thread); +#endif + + Address gc_state(thread, in_bytes(ShenandoahThreadLocalData::gc_state_offset())); + __ testb(gc_state, ShenandoahHeap::HAS_FORWARDED); + __ jcc(Assembler::zero, done); + + save_machine_state(masm, /* handle_gpr = */ false, /* handle_fp = */ true); + + // Use rsi for src address + const Register src_addr = rsi; + // Setup address parameter first, if it does not clobber oop in dst + bool need_addr_setup = (src_addr != dst); + + if (need_addr_setup) { + __ push(src_addr); + __ lea(src_addr, src); + + if (dst != rax) { + // Move obj into rax and save rax + __ push(rax); + __ movptr(rax, dst); + } + } else { + // dst == rsi + __ push(rax); + __ movptr(rax, dst); + + // we can clobber it, since it is outgoing register + __ lea(src_addr, src); + } + + __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, ShenandoahBarrierSetAssembler::shenandoah_lrb()))); + + if (need_addr_setup) { + if (dst != rax) { + __ movptr(dst, rax); + __ pop(rax); + } + __ pop(src_addr); + } else { + __ movptr(dst, rax); + __ pop(rax); + } + + restore_machine_state(masm, /* handle_gpr = */ false, /* handle_fp = */ true); + + __ bind(done); + +#ifndef _LP64 + __ pop(thread); +#endif +} + +void ShenandoahBarrierSetAssembler::iu_barrier(MacroAssembler* masm, Register dst, Register tmp) { + if (ShenandoahIUBarrier) { + iu_barrier_impl(masm, dst, tmp); + } +} + +void ShenandoahBarrierSetAssembler::iu_barrier_impl(MacroAssembler* masm, Register dst, Register tmp) { + assert(ShenandoahIUBarrier, "should be enabled"); + + if (dst == noreg) return; + + if (ShenandoahIUBarrier) { + save_machine_state(masm, /* handle_gpr = */ true, /* handle_fp = */ true); + +#ifdef _LP64 + Register thread = r15_thread; +#else + Register thread = rcx; + if (thread == dst || thread == tmp) { + thread = rdi; + } + if (thread == dst || thread == tmp) { + thread = rbx; + } + __ get_thread(thread); +#endif + assert_different_registers(dst, tmp, thread); + + satb_write_barrier_pre(masm, noreg, dst, thread, tmp, true, false); + + restore_machine_state(masm, /* handle_gpr = */ true, /* handle_fp = */ true); + } +} + +void ShenandoahBarrierSetAssembler::load_reference_barrier(MacroAssembler* masm, Register dst, Address src) { + if (ShenandoahLoadRefBarrier) { + Label done; + __ testptr(dst, dst); + __ jcc(Assembler::zero, done); + load_reference_barrier_not_null(masm, dst, src); + __ bind(done); + } +} + +// +// Arguments: +// +// Inputs: +// src: oop location, might be clobbered +// tmp1: scratch register, might not be valid. +// +// Output: +// dst: oop loaded from src location +// +// Kill: +// tmp1 (if it is valid) +// +void ShenandoahBarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Register dst, Address src, Register tmp1, Register tmp_thread) { + // 1: non-reference load, no additional barrier is needed + if (!is_reference_type(type)) { + BarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp_thread); + return; + } + + assert((decorators & ON_UNKNOWN_OOP_REF) == 0, "Not expected"); + + // 2: load a reference from src location and apply LRB if needed + if (ShenandoahBarrierSet::need_load_reference_barrier(decorators, type)) { + Register result_dst = dst; + bool use_tmp1_for_dst = false; + + // Preserve src location for LRB + if (dst == src.base() || dst == src.index()) { + // Use tmp1 for dst if possible, as it is not used in BarrierAssembler::load_at() + if (tmp1->is_valid() && tmp1 != src.base() && tmp1 != src.index()) { + dst = tmp1; + use_tmp1_for_dst = true; + } else { + dst = rdi; + __ push(dst); + } + assert_different_registers(dst, src.base(), src.index()); + } + + BarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp_thread); + + load_reference_barrier(masm, dst, src); + + // Move loaded oop to final destination + if (dst != result_dst) { + __ movptr(result_dst, dst); + + if (!use_tmp1_for_dst) { + __ pop(dst); + } + + dst = result_dst; + } + } else { + BarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp_thread); + } + + // 3: apply keep-alive barrier if needed + if (ShenandoahBarrierSet::need_keep_alive_barrier(decorators, type)) { + save_machine_state(masm, /* handle_gpr = */ true, /* handle_fp = */ true); + + Register thread = NOT_LP64(tmp_thread) LP64_ONLY(r15_thread); + assert_different_registers(dst, tmp1, tmp_thread); + if (!thread->is_valid()) { + thread = rdx; + } + NOT_LP64(__ get_thread(thread)); + // Generate the SATB pre-barrier code to log the value of + // the referent field in an SATB buffer. + shenandoah_write_barrier_pre(masm /* masm */, + noreg /* obj */, + dst /* pre_val */, + thread /* thread */, + tmp1 /* tmp */, + true /* tosca_live */, + true /* expand_call */); + + restore_machine_state(masm, /* handle_gpr = */ true, /* handle_fp = */ true); + } +} + +void ShenandoahBarrierSetAssembler::store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Address dst, Register val, Register tmp1, Register tmp2) { + + bool on_oop = type == T_OBJECT || type == T_ARRAY; + bool in_heap = (decorators & IN_HEAP) != 0; + bool as_normal = (decorators & AS_NORMAL) != 0; + if (on_oop && in_heap) { + bool needs_pre_barrier = as_normal; + + Register tmp3 = LP64_ONLY(r8) NOT_LP64(rsi); + Register rthread = LP64_ONLY(r15_thread) NOT_LP64(rcx); + // flatten object address if needed + // We do it regardless of precise because we need the registers + if (dst.index() == noreg && dst.disp() == 0) { + if (dst.base() != tmp1) { + __ movptr(tmp1, dst.base()); + } + } else { + __ lea(tmp1, dst); + } + + assert_different_registers(val, tmp1, tmp2, tmp3, rthread); + +#ifndef _LP64 + __ get_thread(rthread); + InterpreterMacroAssembler *imasm = static_cast<InterpreterMacroAssembler*>(masm); + imasm->save_bcp(); +#endif + + if (needs_pre_barrier) { + shenandoah_write_barrier_pre(masm /*masm*/, + tmp1 /* obj */, + tmp2 /* pre_val */, + rthread /* thread */, + tmp3 /* tmp */, + val != noreg /* tosca_live */, + false /* expand_call */); + } + if (val == noreg) { + BarrierSetAssembler::store_at(masm, decorators, type, Address(tmp1, 0), val, noreg, noreg); + } else { + iu_barrier(masm, val, tmp3); + BarrierSetAssembler::store_at(masm, decorators, type, Address(tmp1, 0), val, noreg, noreg); + } + NOT_LP64(imasm->restore_bcp()); + } else { + BarrierSetAssembler::store_at(masm, decorators, type, dst, val, tmp1, tmp2); + } +} + +void ShenandoahBarrierSetAssembler::try_resolve_jobject_in_native(MacroAssembler* masm, Register jni_env, + Register obj, Register tmp, Label& slowpath) { + Label done; + // Resolve jobject + BarrierSetAssembler::try_resolve_jobject_in_native(masm, jni_env, obj, tmp, slowpath); + + // Check for null. + __ testptr(obj, obj); + __ jcc(Assembler::zero, done); + + Address gc_state(jni_env, ShenandoahThreadLocalData::gc_state_offset() - JavaThread::jni_environment_offset()); + __ testb(gc_state, ShenandoahHeap::EVACUATION); + __ jccb(Assembler::notZero, slowpath); + __ bind(done); +} + +// Special Shenandoah CAS implementation that handles false negatives +// due to concurrent evacuation. +void ShenandoahBarrierSetAssembler::cmpxchg_oop(MacroAssembler* masm, + Register res, Address addr, Register oldval, Register newval, + bool exchange, Register tmp1, Register tmp2) { + assert(ShenandoahCASBarrier, "Should only be used when CAS barrier is enabled"); + assert(oldval == rax, "must be in rax for implicit use in cmpxchg"); + assert_different_registers(oldval, tmp1, tmp2); + assert_different_registers(newval, tmp1, tmp2); + + Label L_success, L_failure; + + // Remember oldval for retry logic below +#ifdef _LP64 + if (UseCompressedOops) { + __ movl(tmp1, oldval); + } else +#endif + { + __ movptr(tmp1, oldval); + } + + // Step 1. Fast-path. + // + // Try to CAS with given arguments. If successful, then we are done. + + if (os::is_MP()) __ lock(); +#ifdef _LP64 + if (UseCompressedOops) { + __ cmpxchgl(newval, addr); + } else +#endif + { + __ cmpxchgptr(newval, addr); + } + __ jcc(Assembler::equal, L_success); + + // Step 2. CAS had failed. This may be a false negative. + // + // The trouble comes when we compare the to-space pointer with the from-space + // pointer to the same object. To resolve this, it will suffice to resolve + // the value from memory -- this will give both to-space pointers. + // If they mismatch, then it was a legitimate failure. + // + // Before reaching to resolve sequence, see if we can avoid the whole shebang + // with filters. + + // Filter: when offending in-memory value is NULL, the failure is definitely legitimate + __ testptr(oldval, oldval); + __ jcc(Assembler::zero, L_failure); + + // Filter: when heap is stable, the failure is definitely legitimate +#ifdef _LP64 + const Register thread = r15_thread; +#else + const Register thread = tmp2; + __ get_thread(thread); +#endif + Address gc_state(thread, in_bytes(ShenandoahThreadLocalData::gc_state_offset())); + __ testb(gc_state, ShenandoahHeap::HAS_FORWARDED); + __ jcc(Assembler::zero, L_failure); + +#ifdef _LP64 + if (UseCompressedOops) { + __ movl(tmp2, oldval); + __ decode_heap_oop(tmp2); + } else +#endif + { + __ movptr(tmp2, oldval); + } + + // Decode offending in-memory value. + // Test if-forwarded + __ testb(Address(tmp2, oopDesc::mark_offset_in_bytes()), markOopDesc::marked_value); + __ jcc(Assembler::noParity, L_failure); // When odd number of bits, then not forwarded + __ jcc(Assembler::zero, L_failure); // When it is 00, then also not forwarded + + // Load and mask forwarding pointer + __ movptr(tmp2, Address(tmp2, oopDesc::mark_offset_in_bytes())); + __ shrptr(tmp2, 2); + __ shlptr(tmp2, 2); + +#ifdef _LP64 + if (UseCompressedOops) { + __ decode_heap_oop(tmp1); // decode for comparison + } +#endif + + // Now we have the forwarded offender in tmp2. + // Compare and if they don't match, we have legitimate failure + __ cmpptr(tmp1, tmp2); + __ jcc(Assembler::notEqual, L_failure); + + // Step 3. Need to fix the memory ptr before continuing. + // + // At this point, we have from-space oldval in the register, and its to-space + // address is in tmp2. Let's try to update it into memory. We don't care if it + // succeeds or not. If it does, then the retrying CAS would see it and succeed. + // If this fixup fails, this means somebody else beat us to it, and necessarily + // with to-space ptr store. We still have to do the retry, because the GC might + // have updated the reference for us. + +#ifdef _LP64 + if (UseCompressedOops) { + __ encode_heap_oop(tmp2); // previously decoded at step 2. + } +#endif + + if (os::is_MP()) __ lock(); +#ifdef _LP64 + if (UseCompressedOops) { + __ cmpxchgl(tmp2, addr); + } else +#endif + { + __ cmpxchgptr(tmp2, addr); + } + + // Step 4. Try to CAS again. + // + // This is guaranteed not to have false negatives, because oldval is definitely + // to-space, and memory pointer is to-space as well. Nothing is able to store + // from-space ptr into memory anymore. Make sure oldval is restored, after being + // garbled during retries. + // +#ifdef _LP64 + if (UseCompressedOops) { + __ movl(oldval, tmp2); + } else +#endif + { + __ movptr(oldval, tmp2); + } + + if (os::is_MP()) __ lock(); +#ifdef _LP64 + if (UseCompressedOops) { + __ cmpxchgl(newval, addr); + } else +#endif + { + __ cmpxchgptr(newval, addr); + } + if (!exchange) { + __ jccb(Assembler::equal, L_success); // fastpath, peeking into Step 5, no need to jump + } + + // Step 5. If we need a boolean result out of CAS, set the flag appropriately. + // and promote the result. Note that we handle the flag from both the 1st and 2nd CAS. + // Otherwise, failure witness for CAE is in oldval on all paths, and we can return. + + if (exchange) { + __ bind(L_failure); + __ bind(L_success); + } else { + assert(res != NULL, "need result register"); + + Label exit; + __ bind(L_failure); + __ xorptr(res, res); + __ jmpb(exit); + + __ bind(L_success); + __ movptr(res, 1); + __ bind(exit); + } +} + +#ifdef _LP64 +// Copied from sharedRuntime_x86_64.cpp +static int reg2offset_in(VMReg r) { + // Account for saved rbp and return address + // This should really be in_preserve_stack_slots + return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size; +} + +// Copied from sharedRuntime_x86_64.cpp +static int reg2offset_out(VMReg r) { + return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; +} + +// Copied from sharedRuntime_x86_64.cpp +static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { + if (src.first()->is_stack()) { + if (dst.first()->is_stack()) { + // stack to stack + __ movq(rax, Address(rbp, reg2offset_in(src.first()))); + __ movq(Address(rsp, reg2offset_out(dst.first())), rax); + } else { + // stack to reg + __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); + } + } else if (dst.first()->is_stack()) { + // reg to stack + __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); + } else { + if (dst.first() != src.first()) { + __ movq(dst.first()->as_Register(), src.first()->as_Register()); + } + } +} + +// Pin incoming array argument of java critical method +void ShenandoahBarrierSetAssembler::pin_critical_native_array(MacroAssembler* masm, + VMRegPair reg, + int& pinned_slot) { + __ block_comment("pin_critical_native_array {"); + Register tmp_reg = rax; + + Label is_null; + VMRegPair tmp; + VMRegPair in_reg = reg; + bool on_stack = false; + + tmp.set_ptr(tmp_reg->as_VMReg()); + if (reg.first()->is_stack()) { + // Load the arg up from the stack + move_ptr(masm, reg, tmp); + reg = tmp; + on_stack = true; + } else { + __ movptr(rax, reg.first()->as_Register()); + } + __ testptr(reg.first()->as_Register(), reg.first()->as_Register()); + __ jccb(Assembler::equal, is_null); + + __ push(c_rarg0); + __ push(c_rarg1); + __ push(c_rarg2); + __ push(c_rarg3); +#ifdef _WIN64 + // caller-saved registers on Windows + __ push(r10); + __ push(r11); +#else + __ push(c_rarg4); + __ push(c_rarg5); +#endif + + if (reg.first()->as_Register() != c_rarg1) { + __ movptr(c_rarg1, reg.first()->as_Register()); + } + __ movptr(c_rarg0, r15_thread); + __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::pin_object))); + +#ifdef _WIN64 + __ pop(r11); + __ pop(r10); +#else + __ pop(c_rarg5); + __ pop(c_rarg4); +#endif + __ pop(c_rarg3); + __ pop(c_rarg2); + __ pop(c_rarg1); + __ pop(c_rarg0); + + if (on_stack) { + __ movptr(Address(rbp, reg2offset_in(in_reg.first())), rax); + __ bind(is_null); + } else { + __ movptr(reg.first()->as_Register(), rax); + + // save on stack for unpinning later + __ bind(is_null); + assert(reg.first()->is_Register(), "Must be a register"); + int offset = pinned_slot * VMRegImpl::stack_slot_size; + pinned_slot += VMRegImpl::slots_per_word; + __ movq(Address(rsp, offset), rax); + } + __ block_comment("} pin_critical_native_array"); +} + +// Unpin array argument of java critical method +void ShenandoahBarrierSetAssembler::unpin_critical_native_array(MacroAssembler* masm, + VMRegPair reg, + int& pinned_slot) { + __ block_comment("unpin_critical_native_array {"); + Label is_null; + + if (reg.first()->is_stack()) { + __ movptr(c_rarg1, Address(rbp, reg2offset_in(reg.first()))); + } else { + int offset = pinned_slot * VMRegImpl::stack_slot_size; + pinned_slot += VMRegImpl::slots_per_word; + __ movq(c_rarg1, Address(rsp, offset)); + } + __ testptr(c_rarg1, c_rarg1); + __ jccb(Assembler::equal, is_null); + + __ movptr(c_rarg0, r15_thread); + __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::unpin_object))); + + __ bind(is_null); + __ block_comment("} unpin_critical_native_array"); +} +#else +// Copied from sharedRuntime_x86_32.cpp +static int reg2offset_in(VMReg r) { + // Account for saved rbp, and return address + // This should really be in_preserve_stack_slots + return (r->reg2stack() + 2) * VMRegImpl::stack_slot_size; +} + +// Copied from sharedRuntime_x86_32.cpp +static int reg2offset_out(VMReg r) { + return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; +} + +// Copied from sharedRuntime_x86_32.cpp +static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { + if (src.first()->is_stack()) { + if (dst.first()->is_stack()) { + // stack to stack + // __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); + // __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); + __ movl2ptr(rax, Address(rbp, reg2offset_in(src.first()))); + __ movptr(Address(rsp, reg2offset_out(dst.first())), rax); + } else { + // stack to reg + __ movl2ptr(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); + } + } else if (dst.first()->is_stack()) { + // reg to stack + // no need to sign extend on 64bit + __ movptr(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); + } else { + if (dst.first() != src.first()) { + __ mov(dst.first()->as_Register(), src.first()->as_Register()); + } + } +} + +// Registers need to be saved for runtime call +static Register caller_saved_registers[] = { + rcx, rdx, rsi, rdi +}; + +// Save caller saved registers except r1 and r2 +static void save_registers_except(MacroAssembler* masm, Register r1, Register r2) { + int reg_len = (int)(sizeof(caller_saved_registers) / sizeof(Register)); + for (int index = 0; index < reg_len; index ++) { + Register this_reg = caller_saved_registers[index]; + if (this_reg != r1 && this_reg != r2) { + __ push(this_reg); + } + } +} + +// Restore caller saved registers except r1 and r2 +static void restore_registers_except(MacroAssembler* masm, Register r1, Register r2) { + int reg_len = (int)(sizeof(caller_saved_registers) / sizeof(Register)); + for (int index = reg_len - 1; index >= 0; index --) { + Register this_reg = caller_saved_registers[index]; + if (this_reg != r1 && this_reg != r2) { + __ pop(this_reg); + } + } +} + +// Pin object, return pinned object or null in rax +void ShenandoahBarrierSetAssembler::gen_pin_object(MacroAssembler* masm, + Register thread, VMRegPair reg) { + __ block_comment("gen_pin_object {"); + + Label is_null; + Register tmp_reg = rax; + VMRegPair tmp(tmp_reg->as_VMReg()); + if (reg.first()->is_stack()) { + // Load the arg up from the stack + simple_move32(masm, reg, tmp); + reg = tmp; + } else { + __ movl(tmp_reg, reg.first()->as_Register()); + } + __ testptr(reg.first()->as_Register(), reg.first()->as_Register()); + __ jccb(Assembler::equal, is_null); + + // Save registers that may be used by runtime call + Register arg = reg.first()->is_Register() ? reg.first()->as_Register() : noreg; + save_registers_except(masm, arg, thread); + + __ call_VM_leaf( + CAST_FROM_FN_PTR(address, SharedRuntime::pin_object), + thread, reg.first()->as_Register()); + + // Restore saved registers + restore_registers_except(masm, arg, thread); + + __ bind(is_null); + __ block_comment("} gen_pin_object"); +} + +// Unpin object +void ShenandoahBarrierSetAssembler::gen_unpin_object(MacroAssembler* masm, + Register thread, VMRegPair reg) { + __ block_comment("gen_unpin_object {"); + Label is_null; + + // temp register + __ push(rax); + Register tmp_reg = rax; + VMRegPair tmp(tmp_reg->as_VMReg()); + + simple_move32(masm, reg, tmp); + + __ testptr(rax, rax); + __ jccb(Assembler::equal, is_null); + + // Save registers that may be used by runtime call + Register arg = reg.first()->is_Register() ? reg.first()->as_Register() : noreg; + save_registers_except(masm, arg, thread); + + __ call_VM_leaf( + CAST_FROM_FN_PTR(address, SharedRuntime::unpin_object), + thread, rax); + + // Restore saved registers + restore_registers_except(masm, arg, thread); + __ bind(is_null); + __ pop(rax); + __ block_comment("} gen_unpin_object"); +} +#endif + +#undef __ + +#ifdef COMPILER1 + +#define __ ce->masm()-> + +void ShenandoahBarrierSetAssembler::gen_pre_barrier_stub(LIR_Assembler* ce, ShenandoahPreBarrierStub* stub) { + ShenandoahBarrierSetC1* bs = (ShenandoahBarrierSetC1*)BarrierSet::barrier_set()->barrier_set_c1(); + // At this point we know that marking is in progress. + // If do_load() is true then we have to emit the + // load of the previous value; otherwise it has already + // been loaded into _pre_val. + + __ bind(*stub->entry()); + assert(stub->pre_val()->is_register(), "Precondition."); + + Register pre_val_reg = stub->pre_val()->as_register(); + + if (stub->do_load()) { + ce->mem2reg(stub->addr(), stub->pre_val(), T_OBJECT, stub->patch_code(), stub->info(), false /*wide*/, false /*unaligned*/); + } + + __ cmpptr(pre_val_reg, (int32_t)NULL_WORD); + __ jcc(Assembler::equal, *stub->continuation()); + ce->store_parameter(stub->pre_val()->as_register(), 0); + __ call(RuntimeAddress(bs->pre_barrier_c1_runtime_code_blob()->code_begin())); + __ jmp(*stub->continuation()); + +} + +void ShenandoahBarrierSetAssembler::gen_load_reference_barrier_stub(LIR_Assembler* ce, ShenandoahLoadReferenceBarrierStub* stub) { + ShenandoahBarrierSetC1* bs = (ShenandoahBarrierSetC1*)BarrierSet::barrier_set()->barrier_set_c1(); + __ bind(*stub->entry()); + + Register obj = stub->obj()->as_register(); + Register res = stub->result()->as_register(); + Register addr = stub->addr()->as_pointer_register(); + Register tmp1 = stub->tmp1()->as_register(); + Register tmp2 = stub->tmp2()->as_register(); + assert_different_registers(obj, res, addr, tmp1, tmp2); + + Label slow_path; + + assert(res == rax, "result must arrive in rax"); + + if (res != obj) { + __ mov(res, obj); + } + + // Check for null. + __ testptr(res, res); + __ jcc(Assembler::zero, *stub->continuation()); + + // Check for object being in the collection set. + __ mov(tmp1, res); + __ shrptr(tmp1, ShenandoahHeapRegion::region_size_bytes_shift_jint()); + __ movptr(tmp2, (intptr_t) ShenandoahHeap::in_cset_fast_test_addr()); +#ifdef _LP64 + __ movbool(tmp2, Address(tmp2, tmp1, Address::times_1)); + __ testbool(tmp2); +#else + // On x86_32, C1 register allocator can give us the register without 8-bit support. + // Do the full-register access and test to avoid compilation failures. + __ movptr(tmp2, Address(tmp2, tmp1, Address::times_1)); + __ testptr(tmp2, 0xFF); +#endif + __ jcc(Assembler::zero, *stub->continuation()); + + __ bind(slow_path); + ce->store_parameter(res, 0); + ce->store_parameter(addr, 1); + __ call(RuntimeAddress(bs->load_reference_barrier_rt_code_blob()->code_begin())); + + __ jmp(*stub->continuation()); +} + +#undef __ + +#define __ sasm-> + +void ShenandoahBarrierSetAssembler::generate_c1_pre_barrier_runtime_stub(StubAssembler* sasm) { + __ prologue("shenandoah_pre_barrier", false); + // arg0 : previous value of memory + + __ push(rax); + __ push(rdx); + + const Register pre_val = rax; + const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread); + const Register tmp = rdx; + + NOT_LP64(__ get_thread(thread);) + + Address queue_index(thread, in_bytes(ShenandoahThreadLocalData::satb_mark_queue_index_offset())); + Address buffer(thread, in_bytes(ShenandoahThreadLocalData::satb_mark_queue_buffer_offset())); + + Label done; + Label runtime; + + // Is SATB still active? + Address gc_state(thread, in_bytes(ShenandoahThreadLocalData::gc_state_offset())); + __ testb(gc_state, ShenandoahHeap::MARKING); + __ jcc(Assembler::zero, done); + + // Can we store original value in the thread's buffer? + + __ movptr(tmp, queue_index); + __ testptr(tmp, tmp); + __ jcc(Assembler::zero, runtime); + __ subptr(tmp, wordSize); + __ movptr(queue_index, tmp); + __ addptr(tmp, buffer); + + // prev_val (rax) + __ load_parameter(0, pre_val); + __ movptr(Address(tmp, 0), pre_val); + __ jmp(done); + + __ bind(runtime); + + __ save_live_registers_no_oop_map(true); + + // load the pre-value + __ load_parameter(0, rcx); + __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::write_ref_field_pre_entry), rcx, thread); + + __ restore_live_registers(true); + + __ bind(done); + + __ pop(rdx); + __ pop(rax); + + __ epilogue(); +} + +void ShenandoahBarrierSetAssembler::generate_c1_load_reference_barrier_runtime_stub(StubAssembler* sasm) { + __ prologue("shenandoah_load_reference_barrier", false); + // arg0 : object to be resolved + + __ save_live_registers_no_oop_map(true); + +#ifdef _LP64 + __ load_parameter(0, c_rarg0); + __ load_parameter(1, c_rarg1); + if (UseCompressedOops) { + __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_narrow), c_rarg0, c_rarg1); + } else { + __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier), c_rarg0, c_rarg1); + } +#else + __ load_parameter(0, rax); + __ load_parameter(1, rbx); + __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier), rax, rbx); +#endif + + __ restore_live_registers_except_rax(true); + + __ epilogue(); +} + +#undef __ + +#endif // COMPILER1 + +address ShenandoahBarrierSetAssembler::shenandoah_lrb() { + assert(_shenandoah_lrb != NULL, "need load reference barrier stub"); + return _shenandoah_lrb; +} + +#define __ cgen->assembler()-> + +/* + * Incoming parameters: + * rax: oop + * rsi: load address + */ +address ShenandoahBarrierSetAssembler::generate_shenandoah_lrb(StubCodeGenerator* cgen) { + __ align(CodeEntryAlignment); + StubCodeMark mark(cgen, "StubRoutines", "shenandoah_lrb"); + address start = __ pc(); + + Label slow_path; + + // We use RDI, which also serves as argument register for slow call. + // RAX always holds the src object ptr, except after the slow call, + // then it holds the result. R8/RBX is used as temporary register. + + Register tmp1 = rdi; + Register tmp2 = LP64_ONLY(r8) NOT_LP64(rbx); + + __ push(tmp1); + __ push(tmp2); + + // Check for object being in the collection set. + __ mov(tmp1, rax); + __ shrptr(tmp1, ShenandoahHeapRegion::region_size_bytes_shift_jint()); + __ movptr(tmp2, (intptr_t) ShenandoahHeap::in_cset_fast_test_addr()); + __ movbool(tmp2, Address(tmp2, tmp1, Address::times_1)); + __ testbool(tmp2); + __ jccb(Assembler::notZero, slow_path); + + __ pop(tmp2); + __ pop(tmp1); + __ ret(0); + + __ bind(slow_path); + + __ push(rcx); + __ push(rdx); + __ push(rdi); +#ifdef _LP64 + __ push(r8); + __ push(r9); + __ push(r10); + __ push(r11); + __ push(r12); + __ push(r13); + __ push(r14); + __ push(r15); +#endif + __ push(rbp); + __ movptr(rbp, rsp); + __ andptr(rsp, -StackAlignmentInBytes); + __ push_FPU_state(); + if (UseCompressedOops) { + __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_narrow), rax, rsi); + } else { + __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier), rax, rsi); + } + __ pop_FPU_state(); + __ movptr(rsp, rbp); + __ pop(rbp); +#ifdef _LP64 + __ pop(r15); + __ pop(r14); + __ pop(r13); + __ pop(r12); + __ pop(r11); + __ pop(r10); + __ pop(r9); + __ pop(r8); +#endif + __ pop(rdi); + __ pop(rdx); + __ pop(rcx); + + __ pop(tmp2); + __ pop(tmp1); + __ ret(0); + + return start; +} + +#undef __ + +void ShenandoahBarrierSetAssembler::barrier_stubs_init() { + if (ShenandoahLoadRefBarrier) { + int stub_code_size = 4096; + ResourceMark rm; + BufferBlob* bb = BufferBlob::create("shenandoah_barrier_stubs", stub_code_size); + CodeBuffer buf(bb); + StubCodeGenerator cgen(&buf); + _shenandoah_lrb = generate_shenandoah_lrb(&cgen); + } +}
diff --git a/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.hpp b/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.hpp new file mode 100644 index 0000000..b332a6b --- /dev/null +++ b/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.hpp
@@ -0,0 +1,106 @@ +/* + * Copyright (c) 2018, Red Hat, Inc. All rights reserved. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef CPU_X86_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_X86_HPP +#define CPU_X86_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_X86_HPP + +#include "asm/macroAssembler.hpp" +#include "gc/shared/barrierSetAssembler.hpp" +#ifdef COMPILER1 +class LIR_Assembler; +class ShenandoahPreBarrierStub; +class ShenandoahLoadReferenceBarrierStub; +class StubAssembler; +#endif +class StubCodeGenerator; + +class ShenandoahBarrierSetAssembler: public BarrierSetAssembler { +private: + + static address _shenandoah_lrb; + + void satb_write_barrier_pre(MacroAssembler* masm, + Register obj, + Register pre_val, + Register thread, + Register tmp, + bool tosca_live, + bool expand_call); + + void shenandoah_write_barrier_pre(MacroAssembler* masm, + Register obj, + Register pre_val, + Register thread, + Register tmp, + bool tosca_live, + bool expand_call); + + void load_reference_barrier_not_null(MacroAssembler* masm, Register dst, Address src); + + void iu_barrier_impl(MacroAssembler* masm, Register dst, Register tmp); + + address generate_shenandoah_lrb(StubCodeGenerator* cgen); + +public: + static address shenandoah_lrb(); + + void iu_barrier(MacroAssembler* masm, Register dst, Register tmp); +#ifdef COMPILER1 + void gen_pre_barrier_stub(LIR_Assembler* ce, ShenandoahPreBarrierStub* stub); + void gen_load_reference_barrier_stub(LIR_Assembler* ce, ShenandoahLoadReferenceBarrierStub* stub); + void generate_c1_pre_barrier_runtime_stub(StubAssembler* sasm); + void generate_c1_load_reference_barrier_runtime_stub(StubAssembler* sasm); +#endif + + void load_reference_barrier(MacroAssembler* masm, Register dst, Address src); + + virtual void cmpxchg_oop(MacroAssembler* masm, + Register res, Address addr, Register oldval, Register newval, + bool exchange, Register tmp1, Register tmp2); + virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Register src, Register dst, Register count); + virtual void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Register dst, Address src, Register tmp1, Register tmp_thread); + virtual void store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Address dst, Register val, Register tmp1, Register tmp2); + virtual void try_resolve_jobject_in_native(MacroAssembler* masm, Register jni_env, + Register obj, Register tmp, Label& slowpath); + + virtual void barrier_stubs_init(); + +#ifdef _LP64 + void pin_critical_native_array(MacroAssembler* masm, + VMRegPair reg, + int& pinned_slot); + void unpin_critical_native_array(MacroAssembler* masm, + VMRegPair reg, + int& pinned_slot); +#else + void gen_pin_object(MacroAssembler* masm, + Register thread, VMRegPair reg); + void gen_unpin_object(MacroAssembler* masm, + Register thread, VMRegPair reg); +#endif +}; + +#endif // CPU_X86_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_X86_HPP
diff --git a/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_32.ad b/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_32.ad new file mode 100644 index 0000000..d248ca0 --- /dev/null +++ b/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_32.ad
@@ -0,0 +1,70 @@ +// +// Copyright (c) 2018, Red Hat, Inc. All rights reserved. +// +// This code is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License version 2 only, as +// published by the Free Software Foundation. +// +// This code is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// version 2 for more details (a copy is included in the LICENSE file that +// accompanied this code). +// +// You should have received a copy of the GNU General Public License version +// 2 along with this work; if not, write to the Free Software Foundation, +// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +// +// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +// or visit www.oracle.com if you need additional information or have any +// questions. +// +// + +source_hpp %{ +#include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" +#include "gc/shenandoah/c2/shenandoahSupport.hpp" +%} + +instruct compareAndSwapP_shenandoah(rRegI res, + memory mem_ptr, + eRegP tmp1, eRegP tmp2, + eAXRegP oldval, eRegP newval, + eFlagsReg cr) +%{ + match(Set res (ShenandoahCompareAndSwapP mem_ptr (Binary oldval newval))); + match(Set res (ShenandoahWeakCompareAndSwapP mem_ptr (Binary oldval newval))); + effect(TEMP tmp1, TEMP tmp2, KILL cr, KILL oldval); + + format %{ "shenandoah_cas_oop $mem_ptr,$newval" %} + + ins_encode %{ + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, + $res$$Register, $mem_ptr$$Address, $oldval$$Register, $newval$$Register, + false, // swap + $tmp1$$Register, $tmp2$$Register + ); + %} + ins_pipe( pipe_cmpxchg ); +%} + +instruct compareAndExchangeP_shenandoah(memory mem_ptr, + eAXRegP oldval, eRegP newval, + eRegP tmp1, eRegP tmp2, + eFlagsReg cr) +%{ + match(Set oldval (ShenandoahCompareAndExchangeP mem_ptr (Binary oldval newval))); + effect(KILL cr, TEMP tmp1, TEMP tmp2); + ins_cost(1000); + + format %{ "shenandoah_cas_oop $mem_ptr,$newval" %} + + ins_encode %{ + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, + NULL, $mem_ptr$$Address, $oldval$$Register, $newval$$Register, + true, // exchange + $tmp1$$Register, $tmp2$$Register + ); + %} + ins_pipe( pipe_cmpxchg ); +%}
diff --git a/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad b/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad new file mode 100644 index 0000000..90481bc --- /dev/null +++ b/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad
@@ -0,0 +1,112 @@ +// +// Copyright (c) 2018, Red Hat, Inc. All rights reserved. +// +// This code is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License version 2 only, as +// published by the Free Software Foundation. +// +// This code is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// version 2 for more details (a copy is included in the LICENSE file that +// accompanied this code). +// +// You should have received a copy of the GNU General Public License version +// 2 along with this work; if not, write to the Free Software Foundation, +// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +// +// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +// or visit www.oracle.com if you need additional information or have any +// questions. +// +// + +source_hpp %{ +#include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" +#include "gc/shenandoah/c2/shenandoahSupport.hpp" +%} + +instruct compareAndSwapP_shenandoah(rRegI res, + memory mem_ptr, + rRegP tmp1, rRegP tmp2, + rax_RegP oldval, rRegP newval, + rFlagsReg cr) +%{ + predicate(VM_Version::supports_cx8()); + match(Set res (ShenandoahCompareAndSwapP mem_ptr (Binary oldval newval))); + match(Set res (ShenandoahWeakCompareAndSwapP mem_ptr (Binary oldval newval))); + effect(TEMP tmp1, TEMP tmp2, KILL cr, KILL oldval); + + format %{ "shenandoah_cas_oop $mem_ptr,$newval" %} + + ins_encode %{ + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, + $res$$Register, $mem_ptr$$Address, $oldval$$Register, $newval$$Register, + false, // swap + $tmp1$$Register, $tmp2$$Register + ); + %} + ins_pipe( pipe_cmpxchg ); +%} + +instruct compareAndSwapN_shenandoah(rRegI res, + memory mem_ptr, + rRegP tmp1, rRegP tmp2, + rax_RegN oldval, rRegN newval, + rFlagsReg cr) %{ + match(Set res (ShenandoahCompareAndSwapN mem_ptr (Binary oldval newval))); + match(Set res (ShenandoahWeakCompareAndSwapN mem_ptr (Binary oldval newval))); + effect(TEMP tmp1, TEMP tmp2, KILL cr, KILL oldval); + + format %{ "shenandoah_cas_oop $mem_ptr,$newval" %} + + ins_encode %{ + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, + $res$$Register, $mem_ptr$$Address, $oldval$$Register, $newval$$Register, + false, // swap + $tmp1$$Register, $tmp2$$Register + ); + %} + ins_pipe( pipe_cmpxchg ); +%} + +instruct compareAndExchangeN_shenandoah(memory mem_ptr, + rax_RegN oldval, rRegN newval, + rRegP tmp1, rRegP tmp2, + rFlagsReg cr) %{ + match(Set oldval (ShenandoahCompareAndExchangeN mem_ptr (Binary oldval newval))); + effect(TEMP tmp1, TEMP tmp2, KILL cr); + + format %{ "shenandoah_cas_oop $mem_ptr,$newval" %} + + ins_encode %{ + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, + NULL, $mem_ptr$$Address, $oldval$$Register, $newval$$Register, + true, // exchange + $tmp1$$Register, $tmp2$$Register + ); + %} + ins_pipe( pipe_cmpxchg ); +%} + +instruct compareAndExchangeP_shenandoah(memory mem_ptr, + rax_RegP oldval, rRegP newval, + rRegP tmp1, rRegP tmp2, + rFlagsReg cr) +%{ + predicate(VM_Version::supports_cx8()); + match(Set oldval (ShenandoahCompareAndExchangeP mem_ptr (Binary oldval newval))); + effect(KILL cr, TEMP tmp1, TEMP tmp2); + ins_cost(1000); + + format %{ "shenandoah_cas_oop $mem_ptr,$newval" %} + + ins_encode %{ + ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, + NULL, $mem_ptr$$Address, $oldval$$Register, $newval$$Register, + true, // exchange + $tmp1$$Register, $tmp2$$Register + ); + %} + ins_pipe( pipe_cmpxchg ); +%}
diff --git a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp index e8b4b74..d2290a6 100644 --- a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp +++ b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2018, 2019, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -278,7 +278,7 @@ ref_addr = stub->ref_addr()->as_pointer_register(); } else { // Load address into tmp register - ce->leal(stub->ref_addr(), stub->tmp(), stub->patch_code(), stub->patch_info()); + ce->leal(stub->ref_addr(), stub->tmp()); ref_addr = stub->tmp()->as_pointer_register(); }
diff --git a/src/hotspot/cpu/x86/globals_x86.hpp b/src/hotspot/cpu/x86/globals_x86.hpp index 423e1b1..bfa7e24 100644 --- a/src/hotspot/cpu/x86/globals_x86.hpp +++ b/src/hotspot/cpu/x86/globals_x86.hpp
@@ -31,7 +31,6 @@ // Sets the default values for platform dependent flags used by the runtime system. // (see globals.hpp) -define_pd_global(bool, ShareVtableStubs, true); define_pd_global(bool, NeedsDeoptSuspend, false); // only register window machines need this define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks @@ -216,5 +215,15 @@ "Use BMI2 instructions") \ \ diagnostic(bool, UseLibmIntrinsic, true, \ - "Use Libm Intrinsics") + "Use Libm Intrinsics") \ + \ + /* Minimum array size in bytes to use AVX512 intrinsics */ \ + /* for copy, inflate and fill which don't bail out early based on any */ \ + /* condition. When this value is set to zero compare operations like */ \ + /* compare, vectorizedMismatch, compress can also use AVX512 intrinsics.*/\ + diagnostic(int, AVX3Threshold, 4096, \ + "Minimum array size in bytes to use AVX512 intrinsics" \ + "for copy, inflate and fill. When this value is set as zero" \ + "compare operations can also use AVX512 intrinsics.") \ + range(0, max_jint) #endif // CPU_X86_VM_GLOBALS_X86_HPP
diff --git a/src/hotspot/cpu/x86/macroAssembler_x86.cpp b/src/hotspot/cpu/x86/macroAssembler_x86.cpp index 537bfcf..d3d62ea 100644 --- a/src/hotspot/cpu/x86/macroAssembler_x86.cpp +++ b/src/hotspot/cpu/x86/macroAssembler_x86.cpp
@@ -828,11 +828,13 @@ } void MacroAssembler::stop(const char* msg) { - address rip = pc(); - pusha(); // get regs on stack + if (ShowMessageBoxOnError) { + address rip = pc(); + pusha(); // get regs on stack + lea(c_rarg1, InternalAddress(rip)); + movq(c_rarg2, rsp); // pass pointer to regs array + } lea(c_rarg0, ExternalAddress((address) msg)); - lea(c_rarg1, InternalAddress(rip)); - movq(c_rarg2, rsp); // pass pointer to regs array andq(rsp, -16); // align stack as required by ABI call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); hlt(); @@ -1003,25 +1005,25 @@ } } -void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { +void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) { // Used in sign-masking with aligned address. assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); if (reachable(src)) { Assembler::andpd(dst, as_Address(src)); } else { - lea(rscratch1, src); - Assembler::andpd(dst, Address(rscratch1, 0)); + lea(scratch_reg, src); + Assembler::andpd(dst, Address(scratch_reg, 0)); } } -void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { +void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) { // Used in sign-masking with aligned address. assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); if (reachable(src)) { Assembler::andps(dst, as_Address(src)); } else { - lea(rscratch1, src); - Assembler::andps(dst, Address(rscratch1, 0)); + lea(scratch_reg, src); + Assembler::andps(dst, Address(scratch_reg, 0)); } } @@ -1183,7 +1185,7 @@ // the prototype header is no longer biased and we have to revoke // the bias on this object. testptr(header_reg, markOopDesc::biased_lock_mask_in_place); - jccb(Assembler::notZero, try_revoke_bias); + jcc(Assembler::notZero, try_revoke_bias); // Biasing is still enabled for this data type. See whether the // epoch of the current bias is still valid, meaning that the epoch @@ -3545,13 +3547,13 @@ Assembler::vmovdqu(dst, src); } -void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) { +void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) { if (reachable(src)) { vmovdqu(dst, as_Address(src)); } else { - lea(rscratch1, src); - vmovdqu(dst, Address(rscratch1, 0)); + lea(scratch_reg, src); + vmovdqu(dst, Address(scratch_reg, 0)); } } @@ -3892,6 +3894,15 @@ } } +void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) { + if (reachable(src)) { + Assembler::roundsd(dst, as_Address(src), rmode); + } else { + lea(scratch_reg, src); + Assembler::roundsd(dst, Address(scratch_reg, 0), rmode); + } +} + void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { if (reachable(src)) { Assembler::subss(dst, as_Address(src)); @@ -3919,14 +3930,14 @@ } } -void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { +void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) { // Used in sign-bit flipping with aligned address. assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); if (reachable(src)) { Assembler::xorpd(dst, as_Address(src)); } else { - lea(rscratch1, src); - Assembler::xorpd(dst, Address(rscratch1, 0)); + lea(scratch_reg, src); + Assembler::xorpd(dst, Address(scratch_reg, 0)); } } @@ -3947,14 +3958,14 @@ } } -void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { +void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) { // Used in sign-bit flipping with aligned address. assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); if (reachable(src)) { Assembler::xorps(dst, as_Address(src)); } else { - lea(rscratch1, src); - Assembler::xorps(dst, Address(rscratch1, 0)); + lea(scratch_reg, src); + Assembler::xorps(dst, Address(scratch_reg, 0)); } } @@ -3990,6 +4001,16 @@ } } +void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { + assert(UseAVX > 0, "requires some form of AVX"); + if (reachable(src)) { + Assembler::vpaddd(dst, nds, as_Address(src), vector_len); + } else { + lea(rscratch, src); + Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len); + } +} + void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15"); vandps(dst, nds, negate_field, vector_len); @@ -4020,12 +4041,12 @@ Assembler::vpaddw(dst, nds, src, vector_len); } -void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { +void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { if (reachable(src)) { Assembler::vpand(dst, nds, as_Address(src), vector_len); } else { - lea(rscratch1, src); - Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len); + lea(scratch_reg, src); + Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len); } } @@ -4094,6 +4115,22 @@ Assembler::vpsraw(dst, nds, shift, vector_len); } +void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { + assert(UseAVX > 2,""); + if (!VM_Version::supports_avx512vl() && vector_len < 2) { + vector_len = 2; + } + Assembler::evpsraq(dst, nds, shift, vector_len); +} + +void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { + assert(UseAVX > 2,""); + if (!VM_Version::supports_avx512vl() && vector_len < 2) { + vector_len = 2; + } + Assembler::evpsraq(dst, nds, shift, vector_len); +} + void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); Assembler::vpsrlw(dst, nds, shift, vector_len); @@ -4134,21 +4171,21 @@ Assembler::pshuflw(dst, src, mode); } -void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { +void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { if (reachable(src)) { vandpd(dst, nds, as_Address(src), vector_len); } else { - lea(rscratch1, src); - vandpd(dst, nds, Address(rscratch1, 0), vector_len); + lea(scratch_reg, src); + vandpd(dst, nds, Address(scratch_reg, 0), vector_len); } } -void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { +void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { if (reachable(src)) { vandps(dst, nds, as_Address(src), vector_len); } else { - lea(rscratch1, src); - vandps(dst, nds, Address(rscratch1, 0), vector_len); + lea(scratch_reg, src); + vandps(dst, nds, Address(scratch_reg, 0), vector_len); } } @@ -4216,24 +4253,162 @@ vxorpd(dst, nds, src, Assembler::AVX_128bit); } -void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { +void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { if (reachable(src)) { vxorpd(dst, nds, as_Address(src), vector_len); } else { - lea(rscratch1, src); - vxorpd(dst, nds, Address(rscratch1, 0), vector_len); + lea(scratch_reg, src); + vxorpd(dst, nds, Address(scratch_reg, 0), vector_len); } } -void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { +void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { if (reachable(src)) { vxorps(dst, nds, as_Address(src), vector_len); } else { - lea(rscratch1, src); - vxorps(dst, nds, Address(rscratch1, 0), vector_len); + lea(scratch_reg, src); + vxorps(dst, nds, Address(scratch_reg, 0), vector_len); } } +void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { + if (UseAVX > 1 || (vector_len < 1)) { + if (reachable(src)) { + Assembler::vpxor(dst, nds, as_Address(src), vector_len); + } else { + lea(scratch_reg, src); + Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len); + } + } + else { + MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg); + } +} + +//------------------------------------------------------------------------------------------- +#ifdef COMPILER2 +// Generic instructions support for use in .ad files C2 code generation + +void MacroAssembler::vabsnegd(int opcode, XMMRegister dst, Register scr) { + if (opcode == Op_AbsVD) { + andpd(dst, ExternalAddress(StubRoutines::x86::vector_double_sign_mask()), scr); + } else { + assert((opcode == Op_NegVD),"opcode should be Op_NegD"); + xorpd(dst, ExternalAddress(StubRoutines::x86::vector_double_sign_flip()), scr); + } +} + +void MacroAssembler::vabsnegd(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr) { + if (opcode == Op_AbsVD) { + vandpd(dst, src, ExternalAddress(StubRoutines::x86::vector_double_sign_mask()), vector_len, scr); + } else { + assert((opcode == Op_NegVD),"opcode should be Op_NegD"); + vxorpd(dst, src, ExternalAddress(StubRoutines::x86::vector_double_sign_flip()), vector_len, scr); + } +} + +void MacroAssembler::vabsnegf(int opcode, XMMRegister dst, Register scr) { + if (opcode == Op_AbsVF) { + andps(dst, ExternalAddress(StubRoutines::x86::vector_float_sign_mask()), scr); + } else { + assert((opcode == Op_NegVF),"opcode should be Op_NegF"); + xorps(dst, ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), scr); + } +} + +void MacroAssembler::vabsnegf(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr) { + if (opcode == Op_AbsVF) { + vandps(dst, src, ExternalAddress(StubRoutines::x86::vector_float_sign_mask()), vector_len, scr); + } else { + assert((opcode == Op_NegVF),"opcode should be Op_NegF"); + vxorps(dst, src, ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), vector_len, scr); + } +} + +void MacroAssembler::vextendbw(bool sign, XMMRegister dst, XMMRegister src) { + if (sign) { + pmovsxbw(dst, src); + } else { + pmovzxbw(dst, src); + } +} + +void MacroAssembler::vextendbw(bool sign, XMMRegister dst, XMMRegister src, int vector_len) { + if (sign) { + vpmovsxbw(dst, src, vector_len); + } else { + vpmovzxbw(dst, src, vector_len); + } +} + +void MacroAssembler::vshiftd(int opcode, XMMRegister dst, XMMRegister src) { + if (opcode == Op_RShiftVI) { + psrad(dst, src); + } else if (opcode == Op_LShiftVI) { + pslld(dst, src); + } else { + assert((opcode == Op_URShiftVI),"opcode should be Op_URShiftVI"); + psrld(dst, src); + } +} + +void MacroAssembler::vshiftd(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { + if (opcode == Op_RShiftVI) { + vpsrad(dst, nds, src, vector_len); + } else if (opcode == Op_LShiftVI) { + vpslld(dst, nds, src, vector_len); + } else { + assert((opcode == Op_URShiftVI),"opcode should be Op_URShiftVI"); + vpsrld(dst, nds, src, vector_len); + } +} + +void MacroAssembler::vshiftw(int opcode, XMMRegister dst, XMMRegister src) { + if ((opcode == Op_RShiftVS) || (opcode == Op_RShiftVB)) { + psraw(dst, src); + } else if ((opcode == Op_LShiftVS) || (opcode == Op_LShiftVB)) { + psllw(dst, src); + } else { + assert(((opcode == Op_URShiftVS) || (opcode == Op_URShiftVB)),"opcode should be one of Op_URShiftVS or Op_URShiftVB"); + psrlw(dst, src); + } +} + +void MacroAssembler::vshiftw(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { + if ((opcode == Op_RShiftVS) || (opcode == Op_RShiftVB)) { + vpsraw(dst, nds, src, vector_len); + } else if ((opcode == Op_LShiftVS) || (opcode == Op_LShiftVB)) { + vpsllw(dst, nds, src, vector_len); + } else { + assert(((opcode == Op_URShiftVS) || (opcode == Op_URShiftVB)),"opcode should be one of Op_URShiftVS or Op_URShiftVB"); + vpsrlw(dst, nds, src, vector_len); + } +} + +void MacroAssembler::vshiftq(int opcode, XMMRegister dst, XMMRegister src) { + if (opcode == Op_RShiftVL) { + psrlq(dst, src); // using srl to implement sra on pre-avs512 systems + } else if (opcode == Op_LShiftVL) { + psllq(dst, src); + } else { + assert((opcode == Op_URShiftVL),"opcode should be Op_URShiftVL"); + psrlq(dst, src); + } +} + +void MacroAssembler::vshiftq(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { + if (opcode == Op_RShiftVL) { + evpsraq(dst, nds, src, vector_len); + } else if (opcode == Op_LShiftVL) { + vpsllq(dst, nds, src, vector_len); + } else { + assert((opcode == Op_URShiftVL),"opcode should be Op_URShiftVL"); + vpsrlq(dst, nds, src, vector_len); + } +} +#endif +//------------------------------------------------------------------------------------------- + void MacroAssembler::clear_jweak_tag(Register possibly_jweak) { const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask); STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code @@ -6353,7 +6528,7 @@ movptr(result, str1); if (UseAVX >= 2) { cmpl(cnt1, stride); - jcc(Assembler::less, SCAN_TO_CHAR_LOOP); + jcc(Assembler::less, SCAN_TO_CHAR); cmpl(cnt1, 2*stride); jcc(Assembler::less, SCAN_TO_8_CHAR_INIT); movdl(vec1, ch); @@ -6380,10 +6555,8 @@ } bind(SCAN_TO_8_CHAR); cmpl(cnt1, stride); - if (UseAVX >= 2) { - jcc(Assembler::less, SCAN_TO_CHAR); - } else { - jcc(Assembler::less, SCAN_TO_CHAR_LOOP); + jcc(Assembler::less, SCAN_TO_CHAR); + if (UseAVX < 2) { movdl(vec1, ch); pshuflw(vec1, vec1, 0x00); pshufd(vec1, vec1, 0); @@ -6424,7 +6597,7 @@ pmovmskb(tmp, vec3); } bsfl(ch, tmp); - addl(result, ch); + addptr(result, ch); bind(FOUND_SEQ_CHAR); subptr(result, str1); @@ -6596,7 +6769,7 @@ bind(COMPARE_WIDE_VECTORS_LOOP); #ifdef _LP64 - if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop + if ((AVX3Threshold == 0) && VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop cmpl(cnt2, stride2x2); jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2); testl(cnt2, stride2x2-1); // cnt2 holds the vector count @@ -6856,7 +7029,7 @@ testl(len, len); jcc(Assembler::zero, FALSE_LABEL); - if ((UseAVX > 2) && // AVX512 + if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512 VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2()) { @@ -6929,7 +7102,7 @@ } else { movl(result, len); // copy - if (UseAVX == 2 && UseSSE >= 2) { + if (UseAVX >= 2 && UseSSE >= 2) { // With AVX2, use 32-byte vector compare Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; @@ -7102,14 +7275,12 @@ lea(ary2, Address(ary2, limit, Address::times_1)); negptr(limit); - bind(COMPARE_WIDE_VECTORS); - #ifdef _LP64 - if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop + if ((AVX3Threshold == 0) && VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3; cmpl(limit, -64); - jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2); + jcc(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2); bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop @@ -7142,7 +7313,7 @@ }//if (VM_Version::supports_avx512vlbw()) #endif //_LP64 - + bind(COMPARE_WIDE_VECTORS); vmovdqu(vec1, Address(ary1, limit, Address::times_1)); vmovdqu(vec2, Address(ary2, limit, Address::times_1)); vpxor(vec1, vec2); @@ -7366,32 +7537,33 @@ assert( UseSSE >= 2, "supported cpu only" ); Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; movdl(xtmp, value); - if (UseAVX > 2 && UseUnalignedLoadStores) { + if (UseAVX >= 2 && UseUnalignedLoadStores) { + Label L_check_fill_32_bytes; + if (UseAVX > 2) { + // Fill 64-byte chunks + Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2; + + // If number of bytes to fill < AVX3Threshold, perform fill using AVX2 + cmpl(count, AVX3Threshold); + jccb(Assembler::below, L_check_fill_64_bytes_avx2); + + vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); + + subl(count, 16 << shift); + jccb(Assembler::less, L_check_fill_32_bytes); + align(16); + + BIND(L_fill_64_bytes_loop_avx3); + evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); + addptr(to, 64); + subl(count, 16 << shift); + jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3); + jmpb(L_check_fill_32_bytes); + + BIND(L_check_fill_64_bytes_avx2); + } // Fill 64-byte chunks - Label L_fill_64_bytes_loop, L_check_fill_32_bytes; - vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); - - subl(count, 16 << shift); - jcc(Assembler::less, L_check_fill_32_bytes); - align(16); - - BIND(L_fill_64_bytes_loop); - evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); - addptr(to, 64); - subl(count, 16 << shift); - jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); - - BIND(L_check_fill_32_bytes); - addl(count, 8 << shift); - jccb(Assembler::less, L_check_fill_8_bytes); - vmovdqu(Address(to, 0), xtmp); - addptr(to, 32); - subl(count, 8 << shift); - - BIND(L_check_fill_8_bytes); - } else if (UseAVX == 2 && UseUnalignedLoadStores) { - // Fill 64-byte chunks - Label L_fill_64_bytes_loop, L_check_fill_32_bytes; + Label L_fill_64_bytes_loop; vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit); subl(count, 16 << shift); @@ -8105,10 +8277,11 @@ shlq(length); xorq(result, result); - if ((UseAVX > 2) && + if ((AVX3Threshold == 0) && (UseAVX > 2) && VM_Version::supports_avx512vlbw()) { cmpq(length, 64); jcc(Assembler::less, VECTOR32_TAIL); + movq(tmp1, length); andq(tmp1, 0x3F); // tail count andq(length, ~(0x3F)); //vector count @@ -8823,16 +8996,6 @@ } /** -* Fold four 128-bit data chunks -*/ -void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { - evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64] - evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0] - evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */); - evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */); -} - -/** * Fold 128-bit data chunk */ void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { @@ -8932,34 +9095,6 @@ shrl(len, 4); jcc(Assembler::zero, L_tail_restore); - // Fold total 512 bits of polynomial on each iteration - if (VM_Version::supports_vpclmulqdq()) { - Label Parallel_loop, L_No_Parallel; - - cmpl(len, 8); - jccb(Assembler::less, L_No_Parallel); - - movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); - evmovdquq(xmm1, Address(buf, 0), Assembler::AVX_512bit); - movdl(xmm5, crc); - evpxorq(xmm1, xmm1, xmm5, Assembler::AVX_512bit); - addptr(buf, 64); - subl(len, 7); - evshufi64x2(xmm0, xmm0, xmm0, 0x00, Assembler::AVX_512bit); //propagate the mask from 128 bits to 512 bits - - BIND(Parallel_loop); - fold_128bit_crc32_avx512(xmm1, xmm0, xmm5, buf, 0); - addptr(buf, 64); - subl(len, 4); - jcc(Assembler::greater, Parallel_loop); - - vextracti64x2(xmm2, xmm1, 0x01); - vextracti64x2(xmm3, xmm1, 0x02); - vextracti64x2(xmm4, xmm1, 0x03); - jmp(L_fold_512b); - - BIND(L_No_Parallel); - } // Fold crc into first bytes of vector movdqa(xmm1, Address(buf, 0)); movdl(rax, xmm1); @@ -9063,6 +9198,372 @@ } #ifdef _LP64 +// Helper function for AVX 512 CRC32 +// Fold 512-bit data chunks +void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, + Register pos, int offset) { + evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit); + evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64] + evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0] + evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */); + evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */); +} + +// Helper function for AVX 512 CRC32 +// Compute CRC32 for < 256B buffers +void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos, + Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop, + Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) { + + Label L_less_than_32, L_exact_16_left, L_less_than_16_left; + Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left; + Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2; + + // check if there is enough buffer to be able to fold 16B at a time + cmpl(len, 32); + jcc(Assembler::less, L_less_than_32); + + // if there is, load the constants + movdqu(xmm10, Address(key, 1 * 16)); //rk1 and rk2 in xmm10 + movdl(xmm0, crc); // get the initial crc value + movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext + pxor(xmm7, xmm0); + + // update the buffer pointer + addl(pos, 16); + //update the counter.subtract 32 instead of 16 to save one instruction from the loop + subl(len, 32); + jmp(L_16B_reduction_loop); + + bind(L_less_than_32); + //mov initial crc to the return value. this is necessary for zero - length buffers. + movl(rax, crc); + testl(len, len); + jcc(Assembler::equal, L_cleanup); + + movdl(xmm0, crc); //get the initial crc value + + cmpl(len, 16); + jcc(Assembler::equal, L_exact_16_left); + jcc(Assembler::less, L_less_than_16_left); + + movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext + pxor(xmm7, xmm0); //xor the initial crc value + addl(pos, 16); + subl(len, 16); + movdqu(xmm10, Address(key, 1 * 16)); // rk1 and rk2 in xmm10 + jmp(L_get_last_two_xmms); + + bind(L_less_than_16_left); + //use stack space to load data less than 16 bytes, zero - out the 16B in memory first. + pxor(xmm1, xmm1); + movptr(tmp1, rsp); + movdqu(Address(tmp1, 0 * 16), xmm1); + + cmpl(len, 4); + jcc(Assembler::less, L_only_less_than_4); + + //backup the counter value + movl(tmp2, len); + cmpl(len, 8); + jcc(Assembler::less, L_less_than_8_left); + + //load 8 Bytes + movq(rax, Address(buf, pos, Address::times_1, 0 * 16)); + movq(Address(tmp1, 0 * 16), rax); + addptr(tmp1, 8); + subl(len, 8); + addl(pos, 8); + + bind(L_less_than_8_left); + cmpl(len, 4); + jcc(Assembler::less, L_less_than_4_left); + + //load 4 Bytes + movl(rax, Address(buf, pos, Address::times_1, 0)); + movl(Address(tmp1, 0 * 16), rax); + addptr(tmp1, 4); + subl(len, 4); + addl(pos, 4); + + bind(L_less_than_4_left); + cmpl(len, 2); + jcc(Assembler::less, L_less_than_2_left); + + // load 2 Bytes + movw(rax, Address(buf, pos, Address::times_1, 0)); + movl(Address(tmp1, 0 * 16), rax); + addptr(tmp1, 2); + subl(len, 2); + addl(pos, 2); + + bind(L_less_than_2_left); + cmpl(len, 1); + jcc(Assembler::less, L_zero_left); + + // load 1 Byte + movb(rax, Address(buf, pos, Address::times_1, 0)); + movb(Address(tmp1, 0 * 16), rax); + + bind(L_zero_left); + movdqu(xmm7, Address(rsp, 0)); + pxor(xmm7, xmm0); //xor the initial crc value + + lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr())); + movdqu(xmm0, Address(rax, tmp2)); + pshufb(xmm7, xmm0); + jmp(L_128_done); + + bind(L_exact_16_left); + movdqu(xmm7, Address(buf, pos, Address::times_1, 0)); + pxor(xmm7, xmm0); //xor the initial crc value + jmp(L_128_done); + + bind(L_only_less_than_4); + cmpl(len, 3); + jcc(Assembler::less, L_only_less_than_3); + + // load 3 Bytes + movb(rax, Address(buf, pos, Address::times_1, 0)); + movb(Address(tmp1, 0), rax); + + movb(rax, Address(buf, pos, Address::times_1, 1)); + movb(Address(tmp1, 1), rax); + + movb(rax, Address(buf, pos, Address::times_1, 2)); + movb(Address(tmp1, 2), rax); + + movdqu(xmm7, Address(rsp, 0)); + pxor(xmm7, xmm0); //xor the initial crc value + + pslldq(xmm7, 0x5); + jmp(L_barrett); + bind(L_only_less_than_3); + cmpl(len, 2); + jcc(Assembler::less, L_only_less_than_2); + + // load 2 Bytes + movb(rax, Address(buf, pos, Address::times_1, 0)); + movb(Address(tmp1, 0), rax); + + movb(rax, Address(buf, pos, Address::times_1, 1)); + movb(Address(tmp1, 1), rax); + + movdqu(xmm7, Address(rsp, 0)); + pxor(xmm7, xmm0); //xor the initial crc value + + pslldq(xmm7, 0x6); + jmp(L_barrett); + + bind(L_only_less_than_2); + //load 1 Byte + movb(rax, Address(buf, pos, Address::times_1, 0)); + movb(Address(tmp1, 0), rax); + + movdqu(xmm7, Address(rsp, 0)); + pxor(xmm7, xmm0); //xor the initial crc value + + pslldq(xmm7, 0x7); +} + +/** +* Compute CRC32 using AVX512 instructions +* param crc register containing existing CRC (32-bit) +* param buf register pointing to input byte buffer (byte*) +* param len register containing number of bytes +* param tmp1 scratch register +* param tmp2 scratch register +* return rax result register +*/ +void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register key, Register tmp1, Register tmp2) { + assert_different_registers(crc, buf, len, key, tmp1, tmp2, rax); + + Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; + Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; + Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop; + Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop; + Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup; + + const Register pos = r12; + push(r12); + subptr(rsp, 16 * 2 + 8); + + // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge + // context for the registers used, where all instructions below are using 128-bit mode + // On EVEX without VL and BW, these instructions will all be AVX. + lea(key, ExternalAddress(StubRoutines::x86::crc_table_avx512_addr())); + notl(crc); + movl(pos, 0); + + // check if smaller than 256B + cmpl(len, 256); + jcc(Assembler::less, L_less_than_256); + + // load the initial crc value + movdl(xmm10, crc); + + // receive the initial 64B data, xor the initial crc value + evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit); + evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit); + evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit); + evbroadcasti32x4(xmm10, Address(key, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4 + + subl(len, 256); + cmpl(len, 256); + jcc(Assembler::less, L_fold_128_B_loop); + + evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit); + evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit); + evbroadcasti32x4(xmm16, Address(key, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2 + subl(len, 256); + + bind(L_fold_256_B_loop); + addl(pos, 256); + fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64); + fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64); + fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64); + fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64); + + subl(len, 256); + jcc(Assembler::greaterEqual, L_fold_256_B_loop); + + // Fold 256 into 128 + addl(pos, 256); + evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit); + evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit); + vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC + + evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit); + evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit); + vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC + + evmovdquq(xmm0, xmm7, Assembler::AVX_512bit); + evmovdquq(xmm4, xmm8, Assembler::AVX_512bit); + + addl(len, 128); + jmp(L_fold_128_B_register); + + // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop + // loop will fold 128B at a time until we have 128 + y Bytes of buffer + + // fold 128B at a time.This section of the code folds 8 xmm registers in parallel + bind(L_fold_128_B_loop); + addl(pos, 128); + fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64); + fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64); + + subl(len, 128); + jcc(Assembler::greaterEqual, L_fold_128_B_loop); + + addl(pos, 128); + + // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128 + // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7 + bind(L_fold_128_B_register); + evmovdquq(xmm16, Address(key, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16 + evmovdquq(xmm11, Address(key, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0 + evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit); + evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit); + // save last that has no multiplicand + vextracti64x2(xmm7, xmm4, 3); + + evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit); + evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit); + // Needed later in reduction loop + movdqu(xmm10, Address(key, 1 * 16)); + vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC + vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC + + // Swap 1,0,3,2 - 01 00 11 10 + evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit); + evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit); + vextracti128(xmm5, xmm8, 1); + evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit); + + // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop + // instead of a cmp instruction, we use the negative flag with the jl instruction + addl(len, 128 - 16); + jcc(Assembler::less, L_final_reduction_for_128); + + bind(L_16B_reduction_loop); + vpclmulqdq(xmm8, xmm7, xmm10, 0x1); + vpclmulqdq(xmm7, xmm7, xmm10, 0x10); + vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit); + movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16)); + vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit); + addl(pos, 16); + subl(len, 16); + jcc(Assembler::greaterEqual, L_16B_reduction_loop); + + bind(L_final_reduction_for_128); + addl(len, 16); + jcc(Assembler::equal, L_128_done); + + bind(L_get_last_two_xmms); + movdqu(xmm2, xmm7); + addl(pos, len); + movdqu(xmm1, Address(buf, pos, Address::times_1, -16)); + subl(pos, len); + + // get rid of the extra data that was loaded before + // load the shift constant + lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr())); + movdqu(xmm0, Address(rax, len)); + addl(rax, len); + + vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit); + //Change mask to 512 + vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2); + vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit); + + blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit); + vpclmulqdq(xmm8, xmm7, xmm10, 0x1); + vpclmulqdq(xmm7, xmm7, xmm10, 0x10); + vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit); + vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit); + + bind(L_128_done); + // compute crc of a 128-bit value + movdqu(xmm10, Address(key, 3 * 16)); + movdqu(xmm0, xmm7); + + // 64b fold + vpclmulqdq(xmm7, xmm7, xmm10, 0x0); + vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit); + vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit); + + // 32b fold + movdqu(xmm0, xmm7); + vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit); + vpclmulqdq(xmm7, xmm7, xmm10, 0x10); + vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit); + jmp(L_barrett); + + bind(L_less_than_256); + kernel_crc32_avx512_256B(crc, buf, len, key, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup); + + //barrett reduction + bind(L_barrett); + vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2); + movdqu(xmm1, xmm7); + movdqu(xmm2, xmm7); + movdqu(xmm10, Address(key, 4 * 16)); + + pclmulqdq(xmm7, xmm10, 0x0); + pxor(xmm7, xmm2); + vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2); + movdqu(xmm2, xmm7); + pclmulqdq(xmm7, xmm10, 0x10); + pxor(xmm7, xmm2); + pxor(xmm7, xmm1); + pextrd(crc, xmm7, 2); + + bind(L_cleanup); + notl(crc); // ~c + addptr(rsp, 16 * 2 + 8); + pop(r12); +} + // S. Gueron / Information Processing Letters 112 (2012) 184 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. @@ -9564,7 +10065,7 @@ // save length for return push(len); - if ((UseAVX > 2) && // AVX512 + if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512 VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2()) { @@ -9756,7 +10257,7 @@ // } void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, XMMRegister tmp1, Register tmp2) { - Label copy_chars_loop, done, below_threshold; + Label copy_chars_loop, done, below_threshold, avx3_threshold; // rsi: src // rdi: dst // rdx: len @@ -9766,7 +10267,7 @@ // rdi holds start addr of destination char[] // rdx holds length assert_different_registers(src, dst, len, tmp2); - + movl(tmp2, len); if ((UseAVX > 2) && // AVX512 VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2()) { @@ -9778,9 +10279,11 @@ testl(len, -16); jcc(Assembler::zero, below_threshold); + testl(len, -1 * AVX3Threshold); + jcc(Assembler::zero, avx3_threshold); + // In order to use only one arithmetic operation for the main loop we use // this pre-calculation - movl(tmp2, len); andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop andl(len, -32); // vector count jccb(Assembler::zero, copy_tail); @@ -9811,12 +10314,11 @@ evmovdquw(Address(dst, 0), k2, tmp1, Assembler::AVX_512bit); jmp(done); + bind(avx3_threshold); } if (UseSSE42Intrinsics) { Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail; - movl(tmp2, len); - if (UseAVX > 1) { andl(tmp2, (16 - 1)); andl(len, -16); @@ -9841,13 +10343,7 @@ bind(below_threshold); bind(copy_new_tail); - if ((UseAVX > 2) && - VM_Version::supports_avx512vlbw() && - VM_Version::supports_bmi2()) { - movl(tmp2, len); - } else { - movl(len, tmp2); - } + movl(len, tmp2); andl(tmp2, 0x00000007); andl(len, 0xFFFFFFF8); jccb(Assembler::zero, copy_tail);
diff --git a/src/hotspot/cpu/x86/macroAssembler_x86.hpp b/src/hotspot/cpu/x86/macroAssembler_x86.hpp index ee24562..9834959 100644 --- a/src/hotspot/cpu/x86/macroAssembler_x86.hpp +++ b/src/hotspot/cpu/x86/macroAssembler_x86.hpp
@@ -164,6 +164,7 @@ // Support optimal SSE move instructions. void movflt(XMMRegister dst, XMMRegister src) { + if (dst-> encoding() == src->encoding()) return; if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } else { movss (dst, src); return; } } @@ -172,6 +173,7 @@ void movflt(Address dst, XMMRegister src) { movss(dst, src); } void movdbl(XMMRegister dst, XMMRegister src) { + if (dst-> encoding() == src->encoding()) return; if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } else { movsd (dst, src); return; } } @@ -873,12 +875,12 @@ // Floating void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } - void andpd(XMMRegister dst, AddressLiteral src); + void andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1); void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); } void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); } void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); } - void andps(XMMRegister dst, AddressLiteral src); + void andps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1); void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); } void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } @@ -941,12 +943,17 @@ int iter); void addm(int disp, Register r1, Register r2); - + void gfmul(XMMRegister tmp0, XMMRegister t); + void schoolbookAAD(int i, Register subkeyH, XMMRegister data, XMMRegister tmp0, + XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3); + void generateHtbl_one_block(Register htbl); + void generateHtbl_eight_blocks(Register htbl); public: void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0, XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4, Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block, XMMRegister shuf_mask); + void avx_ghash(Register state, Register htbl, Register data, Register blocks); #endif #ifdef _LP64 @@ -964,6 +971,19 @@ XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4, Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block, XMMRegister shuf_mask); +private: + void roundEnc(XMMRegister key, int rnum); + void lastroundEnc(XMMRegister key, int rnum); + void roundDec(XMMRegister key, int rnum); + void lastroundDec(XMMRegister key, int rnum); + void ev_load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask); + +public: + void aesecb_encrypt(Register source_addr, Register dest_addr, Register key, Register len); + void aesecb_decrypt(Register source_addr, Register dest_addr, Register key, Register len); + void aesctr_encrypt(Register src_addr, Register dest_addr, Register key, Register counter, + Register len_reg, Register used, Register used_addr, Register saved_encCounter_start); + #endif void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0, @@ -1057,8 +1077,8 @@ // these are private because users should be doing movflt/movdbl - void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } + void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } void movss(XMMRegister dst, AddressLiteral src); @@ -1096,7 +1116,7 @@ void vmovdqu(Address dst, XMMRegister src); void vmovdqu(XMMRegister dst, Address src); void vmovdqu(XMMRegister dst, XMMRegister src); - void vmovdqu(XMMRegister dst, AddressLiteral src); + void vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1); void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); } void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); } void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); } @@ -1151,6 +1171,10 @@ void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } void sqrtsd(XMMRegister dst, AddressLiteral src); + void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); } + void roundsd(XMMRegister dst, Address src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); } + void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg); + void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } void sqrtss(XMMRegister dst, AddressLiteral src); @@ -1174,12 +1198,12 @@ // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values void xorpd(XMMRegister dst, XMMRegister src); void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } - void xorpd(XMMRegister dst, AddressLiteral src); + void xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1); // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values void xorps(XMMRegister dst, XMMRegister src); void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } - void xorps(XMMRegister dst, AddressLiteral src); + void xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1); // Shuffle Bytes void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); } @@ -1204,9 +1228,13 @@ void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); + void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); } + void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); } + void vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch); + void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); } void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); } - void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); + void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1); void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len); void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); } @@ -1232,6 +1260,9 @@ void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len); void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len); + void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len); + void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len); + void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len); void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len); @@ -1251,11 +1282,11 @@ void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); } void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); } - void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); + void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1); void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); } void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); } - void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); + void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1); void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); } void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); } @@ -1288,11 +1319,11 @@ void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); } void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); } - void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); + void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1); void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); } void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); } - void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); + void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1); void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2 @@ -1306,14 +1337,15 @@ else Assembler::vxorpd(dst, nds, src, vector_len); } + void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1); // Simple version for AVX2 256bit vectors void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); } void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); } void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { - if (UseAVX > 2) { - Assembler::vinserti32x4(dst, dst, src, imm8); + if (UseAVX > 2 && VM_Version::supports_avx512novl()) { + Assembler::vinserti32x4(dst, nds, src, imm8); } else if (UseAVX > 1) { // vinserti128 is available only in AVX2 Assembler::vinserti128(dst, nds, src, imm8); @@ -1323,8 +1355,8 @@ } void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { - if (UseAVX > 2) { - Assembler::vinserti32x4(dst, dst, src, imm8); + if (UseAVX > 2 && VM_Version::supports_avx512novl()) { + Assembler::vinserti32x4(dst, nds, src, imm8); } else if (UseAVX > 1) { // vinserti128 is available only in AVX2 Assembler::vinserti128(dst, nds, src, imm8); @@ -1334,7 +1366,7 @@ } void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) { - if (UseAVX > 2) { + if (UseAVX > 2 && VM_Version::supports_avx512novl()) { Assembler::vextracti32x4(dst, src, imm8); } else if (UseAVX > 1) { // vextracti128 is available only in AVX2 @@ -1345,7 +1377,7 @@ } void vextracti128(Address dst, XMMRegister src, uint8_t imm8) { - if (UseAVX > 2) { + if (UseAVX > 2 && VM_Version::supports_avx512novl()) { Assembler::vextracti32x4(dst, src, imm8); } else if (UseAVX > 1) { // vextracti128 is available only in AVX2 @@ -1370,7 +1402,7 @@ } void vinsertf128_high(XMMRegister dst, XMMRegister src) { - if (UseAVX > 2) { + if (UseAVX > 2 && VM_Version::supports_avx512novl()) { Assembler::vinsertf32x4(dst, dst, src, 1); } else { Assembler::vinsertf128(dst, dst, src, 1); @@ -1378,7 +1410,7 @@ } void vinsertf128_high(XMMRegister dst, Address src) { - if (UseAVX > 2) { + if (UseAVX > 2 && VM_Version::supports_avx512novl()) { Assembler::vinsertf32x4(dst, dst, src, 1); } else { Assembler::vinsertf128(dst, dst, src, 1); @@ -1386,7 +1418,7 @@ } void vextractf128_high(XMMRegister dst, XMMRegister src) { - if (UseAVX > 2) { + if (UseAVX > 2 && VM_Version::supports_avx512novl()) { Assembler::vextractf32x4(dst, src, 1); } else { Assembler::vextractf128(dst, src, 1); @@ -1394,7 +1426,7 @@ } void vextractf128_high(Address dst, XMMRegister src) { - if (UseAVX > 2) { + if (UseAVX > 2 && VM_Version::supports_avx512novl()) { Assembler::vextractf32x4(dst, src, 1); } else { Assembler::vextractf128(dst, src, 1); @@ -1436,7 +1468,7 @@ } void vinsertf128_low(XMMRegister dst, XMMRegister src) { - if (UseAVX > 2) { + if (UseAVX > 2 && VM_Version::supports_avx512novl()) { Assembler::vinsertf32x4(dst, dst, src, 0); } else { Assembler::vinsertf128(dst, dst, src, 0); @@ -1444,7 +1476,7 @@ } void vinsertf128_low(XMMRegister dst, Address src) { - if (UseAVX > 2) { + if (UseAVX > 2 && VM_Version::supports_avx512novl()) { Assembler::vinsertf32x4(dst, dst, src, 0); } else { Assembler::vinsertf128(dst, dst, src, 0); @@ -1452,7 +1484,7 @@ } void vextractf128_low(XMMRegister dst, XMMRegister src) { - if (UseAVX > 2) { + if (UseAVX > 2 && VM_Version::supports_avx512novl()) { Assembler::vextractf32x4(dst, src, 0); } else { Assembler::vextractf128(dst, src, 0); @@ -1460,7 +1492,7 @@ } void vextractf128_low(Address dst, XMMRegister src) { - if (UseAVX > 2) { + if (UseAVX > 2 && VM_Version::supports_avx512novl()) { Assembler::vextractf32x4(dst, src, 0); } else { Assembler::vextractf128(dst, src, 0); @@ -1496,6 +1528,15 @@ // 0x11 - multiply upper 64 bits [64:127] Assembler::vpclmulqdq(dst, nds, src, 0x11); } + void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) { + // 0x10 - multiply nds[0:63] and src[64:127] + Assembler::vpclmulqdq(dst, nds, src, 0x10); + } + void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) { + //0x01 - multiply nds[64:127] and src[0:63] + Assembler::vpclmulqdq(dst, nds, src, 0x01); + } + void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { // 0x00 - multiply lower 64 bits [0:63] Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len); @@ -1583,6 +1624,22 @@ void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } +#ifdef COMPILER2 + // Generic instructions support for use in .ad files C2 code generation + void vabsnegd(int opcode, XMMRegister dst, Register scr); + void vabsnegd(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr); + void vabsnegf(int opcode, XMMRegister dst, Register scr); + void vabsnegf(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr); + void vextendbw(bool sign, XMMRegister dst, XMMRegister src, int vector_len); + void vextendbw(bool sign, XMMRegister dst, XMMRegister src); + void vshiftd(int opcode, XMMRegister dst, XMMRegister src); + void vshiftd(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); + void vshiftw(int opcode, XMMRegister dst, XMMRegister src); + void vshiftw(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); + void vshiftq(int opcode, XMMRegister dst, XMMRegister src); + void vshiftq(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); +#endif + // C2 compiled method's prolog code. void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b); @@ -1693,6 +1750,15 @@ // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic. void update_byte_crc32(Register crc, Register val, Register table); void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp); + + +#ifdef _LP64 + void kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2); + void kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos, + Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop, + Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup); +#endif // _LP64 + // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic // Note on a naming convention: // Prefix w = register only used on a Westmere+ architecture @@ -1729,10 +1795,13 @@ // Fold 128-bit data chunk void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset); void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf); +#ifdef _LP64 + // Fold 512-bit data chunk + void fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, Register pos, int offset); +#endif // _LP64 // Fold 8-bit data void fold_8bit_crc32(Register crc, Register table, Register tmp); void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp); - void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset); // Compress char[] array to byte[]. void char_array_compress(Register src, Register dst, Register len,
diff --git a/src/hotspot/cpu/x86/macroAssembler_x86_aes.cpp b/src/hotspot/cpu/x86/macroAssembler_x86_aes.cpp new file mode 100644 index 0000000..778dd1a --- /dev/null +++ b/src/hotspot/cpu/x86/macroAssembler_x86_aes.cpp
@@ -0,0 +1,1270 @@ +/* +* Copyright (c) 2019, Intel Corporation. +* +* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. +* +* This code is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License version 2 only, as +* published by the Free Software Foundation. +* +* This code is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +* version 2 for more details (a copy is included in the LICENSE file that +* accompanied this code). +* +* You should have received a copy of the GNU General Public License version +* 2 along with this work; if not, write to the Free Software Foundation, +* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +* +* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA +* or visit www.oracle.com if you need additional information or have any +* questions. +* +*/ + +#include "precompiled.hpp" +#include "asm/assembler.hpp" +#include "asm/assembler.inline.hpp" +#include "runtime/stubRoutines.hpp" +#include "macroAssembler_x86.hpp" + +#ifdef _LP64 + +void MacroAssembler::roundEnc(XMMRegister key, int rnum) { + for (int xmm_reg_no = 0; xmm_reg_no <=rnum; xmm_reg_no++) { + vaesenc(as_XMMRegister(xmm_reg_no), as_XMMRegister(xmm_reg_no), key, Assembler::AVX_512bit); + } +} + +void MacroAssembler::lastroundEnc(XMMRegister key, int rnum) { + for (int xmm_reg_no = 0; xmm_reg_no <=rnum; xmm_reg_no++) { + vaesenclast(as_XMMRegister(xmm_reg_no), as_XMMRegister(xmm_reg_no), key, Assembler::AVX_512bit); + } +} + +void MacroAssembler::roundDec(XMMRegister key, int rnum) { + for (int xmm_reg_no = 0; xmm_reg_no <=rnum; xmm_reg_no++) { + vaesdec(as_XMMRegister(xmm_reg_no), as_XMMRegister(xmm_reg_no), key, Assembler::AVX_512bit); + } +} + +void MacroAssembler::lastroundDec(XMMRegister key, int rnum) { + for (int xmm_reg_no = 0; xmm_reg_no <=rnum; xmm_reg_no++) { + vaesdeclast(as_XMMRegister(xmm_reg_no), as_XMMRegister(xmm_reg_no), key, Assembler::AVX_512bit); + } +} + +// Load key and shuffle operation +void MacroAssembler::ev_load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask=NULL) { + movdqu(xmmdst, Address(key, offset)); + if (xmm_shuf_mask != NULL) { + pshufb(xmmdst, xmm_shuf_mask); + } else { + pshufb(xmmdst, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr())); + } + evshufi64x2(xmmdst, xmmdst, xmmdst, 0x0, Assembler::AVX_512bit); +} + +// AES-ECB Encrypt Operation +void MacroAssembler::aesecb_encrypt(Register src_addr, Register dest_addr, Register key, Register len) { + + const Register pos = rax; + const Register rounds = r12; + + Label NO_PARTS, LOOP, Loop_start, LOOP2, AES192, END_LOOP, AES256, REMAINDER, LAST2, END, KEY_192, KEY_256, EXIT; + push(r13); + push(r12); + + // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge + // context for the registers used, where all instructions below are using 128-bit mode + // On EVEX without VL and BW, these instructions will all be AVX. + if (VM_Version::supports_avx512vlbw()) { + movl(rax, 0xffff); + kmovql(k1, rax); + } + push(len); // Save + push(rbx); + + vzeroupper(); + + xorptr(pos, pos); + + // Calculate number of rounds based on key length(128, 192, 256):44 for 10-rounds, 52 for 12-rounds, 60 for 14-rounds + movl(rounds, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT))); + + // Load Key shuf mask + const XMMRegister xmm_key_shuf_mask = xmm31; // used temporarily to swap key bytes up front + movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr())); + + // Load and shuffle key based on number of rounds + ev_load_key(xmm8, key, 0 * 16, xmm_key_shuf_mask); + ev_load_key(xmm9, key, 1 * 16, xmm_key_shuf_mask); + ev_load_key(xmm10, key, 2 * 16, xmm_key_shuf_mask); + ev_load_key(xmm23, key, 3 * 16, xmm_key_shuf_mask); + ev_load_key(xmm12, key, 4 * 16, xmm_key_shuf_mask); + ev_load_key(xmm13, key, 5 * 16, xmm_key_shuf_mask); + ev_load_key(xmm14, key, 6 * 16, xmm_key_shuf_mask); + ev_load_key(xmm15, key, 7 * 16, xmm_key_shuf_mask); + ev_load_key(xmm16, key, 8 * 16, xmm_key_shuf_mask); + ev_load_key(xmm17, key, 9 * 16, xmm_key_shuf_mask); + ev_load_key(xmm24, key, 10 * 16, xmm_key_shuf_mask); + cmpl(rounds, 52); + jcc(Assembler::greaterEqual, KEY_192); + jmp(Loop_start); + + bind(KEY_192); + ev_load_key(xmm19, key, 11 * 16, xmm_key_shuf_mask); + ev_load_key(xmm20, key, 12 * 16, xmm_key_shuf_mask); + cmpl(rounds, 60); + jcc(Assembler::equal, KEY_256); + jmp(Loop_start); + + bind(KEY_256); + ev_load_key(xmm21, key, 13 * 16, xmm_key_shuf_mask); + ev_load_key(xmm22, key, 14 * 16, xmm_key_shuf_mask); + + bind(Loop_start); + movq(rbx, len); + // Divide length by 16 to convert it to number of blocks + shrq(len, 4); + shlq(rbx, 60); + jcc(Assembler::equal, NO_PARTS); + addq(len, 1); + // Check if number of blocks is greater than or equal to 32 + // If true, 512 bytes are processed at a time (code marked by label LOOP) + // If not, 16 bytes are processed (code marked by REMAINDER label) + bind(NO_PARTS); + movq(rbx, len); + shrq(len, 5); + jcc(Assembler::equal, REMAINDER); + movl(r13, len); + // Compute number of blocks that will be processed 512 bytes at a time + // Subtract this from the total number of blocks which will then be processed by REMAINDER loop + shlq(r13, 5); + subq(rbx, r13); + //Begin processing 512 bytes + bind(LOOP); + // Move 64 bytes of PT data into a zmm register, as a result 512 bytes of PT loaded in zmm0-7 + evmovdquq(xmm0, Address(src_addr, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit); + evmovdquq(xmm1, Address(src_addr, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit); + evmovdquq(xmm2, Address(src_addr, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit); + evmovdquq(xmm3, Address(src_addr, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit); + evmovdquq(xmm4, Address(src_addr, pos, Address::times_1, 4 * 64), Assembler::AVX_512bit); + evmovdquq(xmm5, Address(src_addr, pos, Address::times_1, 5 * 64), Assembler::AVX_512bit); + evmovdquq(xmm6, Address(src_addr, pos, Address::times_1, 6 * 64), Assembler::AVX_512bit); + evmovdquq(xmm7, Address(src_addr, pos, Address::times_1, 7 * 64), Assembler::AVX_512bit); + // Xor with the first round key + evpxorq(xmm0, xmm0, xmm8, Assembler::AVX_512bit); + evpxorq(xmm1, xmm1, xmm8, Assembler::AVX_512bit); + evpxorq(xmm2, xmm2, xmm8, Assembler::AVX_512bit); + evpxorq(xmm3, xmm3, xmm8, Assembler::AVX_512bit); + evpxorq(xmm4, xmm4, xmm8, Assembler::AVX_512bit); + evpxorq(xmm5, xmm5, xmm8, Assembler::AVX_512bit); + evpxorq(xmm6, xmm6, xmm8, Assembler::AVX_512bit); + evpxorq(xmm7, xmm7, xmm8, Assembler::AVX_512bit); + // 9 Aes encode round operations + roundEnc(xmm9, 7); + roundEnc(xmm10, 7); + roundEnc(xmm23, 7); + roundEnc(xmm12, 7); + roundEnc(xmm13, 7); + roundEnc(xmm14, 7); + roundEnc(xmm15, 7); + roundEnc(xmm16, 7); + roundEnc(xmm17, 7); + cmpl(rounds, 52); + jcc(Assembler::aboveEqual, AES192); + // Aesenclast round operation for keysize = 128 + lastroundEnc(xmm24, 7); + jmp(END_LOOP); + //Additional 2 rounds of Aesenc operation for keysize = 192 + bind(AES192); + roundEnc(xmm24, 7); + roundEnc(xmm19, 7); + cmpl(rounds, 60); + jcc(Assembler::aboveEqual, AES256); + // Aesenclast round for keysize = 192 + lastroundEnc(xmm20, 7); + jmp(END_LOOP); + // 2 rounds of Aesenc operation and Aesenclast for keysize = 256 + bind(AES256); + roundEnc(xmm20, 7); + roundEnc(xmm21, 7); + lastroundEnc(xmm22, 7); + + bind(END_LOOP); + // Move 512 bytes of CT to destination + evmovdquq(Address(dest_addr, pos, Address::times_1, 0 * 64), xmm0, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 1 * 64), xmm1, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 2 * 64), xmm2, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 3 * 64), xmm3, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 4 * 64), xmm4, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 5 * 64), xmm5, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 6 * 64), xmm6, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 7 * 64), xmm7, Assembler::AVX_512bit); + + addq(pos, 512); + decq(len); + jcc(Assembler::notEqual, LOOP); + + bind(REMAINDER); + vzeroupper(); + cmpq(rbx, 0); + jcc(Assembler::equal, END); + // Process 16 bytes at a time + bind(LOOP2); + movdqu(xmm1, Address(src_addr, pos, Address::times_1, 0)); + vpxor(xmm1, xmm1, xmm8, Assembler::AVX_128bit); + // xmm2 contains shuffled key for Aesenclast operation. + vmovdqu(xmm2, xmm24); + + vaesenc(xmm1, xmm1, xmm9, Assembler::AVX_128bit); + vaesenc(xmm1, xmm1, xmm10, Assembler::AVX_128bit); + vaesenc(xmm1, xmm1, xmm23, Assembler::AVX_128bit); + vaesenc(xmm1, xmm1, xmm12, Assembler::AVX_128bit); + vaesenc(xmm1, xmm1, xmm13, Assembler::AVX_128bit); + vaesenc(xmm1, xmm1, xmm14, Assembler::AVX_128bit); + vaesenc(xmm1, xmm1, xmm15, Assembler::AVX_128bit); + vaesenc(xmm1, xmm1, xmm16, Assembler::AVX_128bit); + vaesenc(xmm1, xmm1, xmm17, Assembler::AVX_128bit); + + cmpl(rounds, 52); + jcc(Assembler::below, LAST2); + vmovdqu(xmm2, xmm20); + vaesenc(xmm1, xmm1, xmm24, Assembler::AVX_128bit); + vaesenc(xmm1, xmm1, xmm19, Assembler::AVX_128bit); + cmpl(rounds, 60); + jcc(Assembler::below, LAST2); + vmovdqu(xmm2, xmm22); + vaesenc(xmm1, xmm1, xmm20, Assembler::AVX_128bit); + vaesenc(xmm1, xmm1, xmm21, Assembler::AVX_128bit); + + bind(LAST2); + // Aesenclast round + vaesenclast(xmm1, xmm1, xmm2, Assembler::AVX_128bit); + // Write 16 bytes of CT to destination + movdqu(Address(dest_addr, pos, Address::times_1, 0), xmm1); + addq(pos, 16); + decq(rbx); + jcc(Assembler::notEqual, LOOP2); + + bind(END); + // Zero out the round keys + evpxorq(xmm8, xmm8, xmm8, Assembler::AVX_512bit); + evpxorq(xmm9, xmm9, xmm9, Assembler::AVX_512bit); + evpxorq(xmm10, xmm10, xmm10, Assembler::AVX_512bit); + evpxorq(xmm23, xmm23, xmm23, Assembler::AVX_512bit); + evpxorq(xmm12, xmm12, xmm12, Assembler::AVX_512bit); + evpxorq(xmm13, xmm13, xmm13, Assembler::AVX_512bit); + evpxorq(xmm14, xmm14, xmm14, Assembler::AVX_512bit); + evpxorq(xmm15, xmm15, xmm15, Assembler::AVX_512bit); + evpxorq(xmm16, xmm16, xmm16, Assembler::AVX_512bit); + evpxorq(xmm17, xmm17, xmm17, Assembler::AVX_512bit); + evpxorq(xmm24, xmm24, xmm24, Assembler::AVX_512bit); + cmpl(rounds, 44); + jcc(Assembler::belowEqual, EXIT); + evpxorq(xmm19, xmm19, xmm19, Assembler::AVX_512bit); + evpxorq(xmm20, xmm20, xmm20, Assembler::AVX_512bit); + cmpl(rounds, 52); + jcc(Assembler::belowEqual, EXIT); + evpxorq(xmm21, xmm21, xmm21, Assembler::AVX_512bit); + evpxorq(xmm22, xmm22, xmm22, Assembler::AVX_512bit); + bind(EXIT); + pop(rbx); + pop(rax); // return length + pop(r12); + pop(r13); +} + +// AES-ECB Decrypt Operation +void MacroAssembler::aesecb_decrypt(Register src_addr, Register dest_addr, Register key, Register len) { + + Label NO_PARTS, LOOP, Loop_start, LOOP2, AES192, END_LOOP, AES256, REMAINDER, LAST2, END, KEY_192, KEY_256, EXIT; + const Register pos = rax; + const Register rounds = r12; + push(r13); + push(r12); + + // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge + // context for the registers used, where all instructions below are using 128-bit mode + // On EVEX without VL and BW, these instructions will all be AVX. + if (VM_Version::supports_avx512vlbw()) { + movl(rax, 0xffff); + kmovql(k1, rax); + } + + push(len); // Save + push(rbx); + + vzeroupper(); + + xorptr(pos, pos); + // Calculate number of rounds i.e. based on key length(128, 192, 256):44 for 10-rounds, 52 for 12-rounds, 60 for 14-rounds + movl(rounds, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT))); + + // Load Key shuf mask + const XMMRegister xmm_key_shuf_mask = xmm31; // used temporarily to swap key bytes up front + movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr())); + + // Load and shuffle round keys. The java expanded key ordering is rotated one position in decryption. + // So the first round key is loaded from 1*16 here and last round key is loaded from 0*16 + ev_load_key(xmm9, key, 1 * 16, xmm_key_shuf_mask); + ev_load_key(xmm10, key, 2 * 16, xmm_key_shuf_mask); + ev_load_key(xmm11, key, 3 * 16, xmm_key_shuf_mask); + ev_load_key(xmm12, key, 4 * 16, xmm_key_shuf_mask); + ev_load_key(xmm13, key, 5 * 16, xmm_key_shuf_mask); + ev_load_key(xmm14, key, 6 * 16, xmm_key_shuf_mask); + ev_load_key(xmm15, key, 7 * 16, xmm_key_shuf_mask); + ev_load_key(xmm16, key, 8 * 16, xmm_key_shuf_mask); + ev_load_key(xmm17, key, 9 * 16, xmm_key_shuf_mask); + ev_load_key(xmm18, key, 10 * 16, xmm_key_shuf_mask); + ev_load_key(xmm27, key, 0 * 16, xmm_key_shuf_mask); + cmpl(rounds, 52); + jcc(Assembler::greaterEqual, KEY_192); + jmp(Loop_start); + + bind(KEY_192); + ev_load_key(xmm19, key, 11 * 16, xmm_key_shuf_mask); + ev_load_key(xmm20, key, 12 * 16, xmm_key_shuf_mask); + cmpl(rounds, 60); + jcc(Assembler::equal, KEY_256); + jmp(Loop_start); + + bind(KEY_256); + ev_load_key(xmm21, key, 13 * 16, xmm_key_shuf_mask); + ev_load_key(xmm22, key, 14 * 16, xmm_key_shuf_mask); + bind(Loop_start); + movq(rbx, len); + // Convert input length to number of blocks + shrq(len, 4); + shlq(rbx, 60); + jcc(Assembler::equal, NO_PARTS); + addq(len, 1); + // Check if number of blocks is greater than/ equal to 32 + // If true, blocks then 512 bytes are processed at a time (code marked by label LOOP) + // If not, 16 bytes are processed (code marked by label REMAINDER) + bind(NO_PARTS); + movq(rbx, len); + shrq(len, 5); + jcc(Assembler::equal, REMAINDER); + movl(r13, len); + // Compute number of blocks that will be processed as 512 bytes at a time + // Subtract this from the total number of blocks, which will then be processed by REMAINDER loop. + shlq(r13, 5); + subq(rbx, r13); + + bind(LOOP); + // Move 64 bytes of CT data into a zmm register, as a result 512 bytes of CT loaded in zmm0-7 + evmovdquq(xmm0, Address(src_addr, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit); + evmovdquq(xmm1, Address(src_addr, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit); + evmovdquq(xmm2, Address(src_addr, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit); + evmovdquq(xmm3, Address(src_addr, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit); + evmovdquq(xmm4, Address(src_addr, pos, Address::times_1, 4 * 64), Assembler::AVX_512bit); + evmovdquq(xmm5, Address(src_addr, pos, Address::times_1, 5 * 64), Assembler::AVX_512bit); + evmovdquq(xmm6, Address(src_addr, pos, Address::times_1, 6 * 64), Assembler::AVX_512bit); + evmovdquq(xmm7, Address(src_addr, pos, Address::times_1, 7 * 64), Assembler::AVX_512bit); + // Xor with the first round key + evpxorq(xmm0, xmm0, xmm9, Assembler::AVX_512bit); + evpxorq(xmm1, xmm1, xmm9, Assembler::AVX_512bit); + evpxorq(xmm2, xmm2, xmm9, Assembler::AVX_512bit); + evpxorq(xmm3, xmm3, xmm9, Assembler::AVX_512bit); + evpxorq(xmm4, xmm4, xmm9, Assembler::AVX_512bit); + evpxorq(xmm5, xmm5, xmm9, Assembler::AVX_512bit); + evpxorq(xmm6, xmm6, xmm9, Assembler::AVX_512bit); + evpxorq(xmm7, xmm7, xmm9, Assembler::AVX_512bit); + // 9 rounds of Aesdec + roundDec(xmm10, 7); + roundDec(xmm11, 7); + roundDec(xmm12, 7); + roundDec(xmm13, 7); + roundDec(xmm14, 7); + roundDec(xmm15, 7); + roundDec(xmm16, 7); + roundDec(xmm17, 7); + roundDec(xmm18, 7); + cmpl(rounds, 52); + jcc(Assembler::aboveEqual, AES192); + // Aesdeclast round for keysize = 128 + lastroundDec(xmm27, 7); + jmp(END_LOOP); + + bind(AES192); + // 2 Additional rounds for keysize = 192 + roundDec(xmm19, 7); + roundDec(xmm20, 7); + cmpl(rounds, 60); + jcc(Assembler::aboveEqual, AES256); + // Aesdeclast round for keysize = 192 + lastroundDec(xmm27, 7); + jmp(END_LOOP); + bind(AES256); + // 2 Additional rounds and Aesdeclast for keysize = 256 + roundDec(xmm21, 7); + roundDec(xmm22, 7); + lastroundDec(xmm27, 7); + + bind(END_LOOP); + // Write 512 bytes of PT to the destination + evmovdquq(Address(dest_addr, pos, Address::times_1, 0 * 64), xmm0, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 1 * 64), xmm1, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 2 * 64), xmm2, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 3 * 64), xmm3, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 4 * 64), xmm4, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 5 * 64), xmm5, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 6 * 64), xmm6, Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 7 * 64), xmm7, Assembler::AVX_512bit); + + addq(pos, 512); + decq(len); + jcc(Assembler::notEqual, LOOP); + + bind(REMAINDER); + vzeroupper(); + cmpq(rbx, 0); + jcc(Assembler::equal, END); + // Process 16 bytes at a time + bind(LOOP2); + movdqu(xmm1, Address(src_addr, pos, Address::times_1, 0)); + vpxor(xmm1, xmm1, xmm9, Assembler::AVX_128bit); + // xmm2 contains shuffled key for Aesdeclast operation. + vmovdqu(xmm2, xmm27); + + vaesdec(xmm1, xmm1, xmm10, Assembler::AVX_128bit); + vaesdec(xmm1, xmm1, xmm11, Assembler::AVX_128bit); + vaesdec(xmm1, xmm1, xmm12, Assembler::AVX_128bit); + vaesdec(xmm1, xmm1, xmm13, Assembler::AVX_128bit); + vaesdec(xmm1, xmm1, xmm14, Assembler::AVX_128bit); + vaesdec(xmm1, xmm1, xmm15, Assembler::AVX_128bit); + vaesdec(xmm1, xmm1, xmm16, Assembler::AVX_128bit); + vaesdec(xmm1, xmm1, xmm17, Assembler::AVX_128bit); + vaesdec(xmm1, xmm1, xmm18, Assembler::AVX_128bit); + + cmpl(rounds, 52); + jcc(Assembler::below, LAST2); + vaesdec(xmm1, xmm1, xmm19, Assembler::AVX_128bit); + vaesdec(xmm1, xmm1, xmm20, Assembler::AVX_128bit); + cmpl(rounds, 60); + jcc(Assembler::below, LAST2); + vaesdec(xmm1, xmm1, xmm21, Assembler::AVX_128bit); + vaesdec(xmm1, xmm1, xmm22, Assembler::AVX_128bit); + + bind(LAST2); + // Aesdeclast round + vaesdeclast(xmm1, xmm1, xmm2, Assembler::AVX_128bit); + // Write 16 bytes of PT to destination + movdqu(Address(dest_addr, pos, Address::times_1, 0), xmm1); + addq(pos, 16); + decq(rbx); + jcc(Assembler::notEqual, LOOP2); + + bind(END); + // Zero out the round keys + evpxorq(xmm8, xmm8, xmm8, Assembler::AVX_512bit); + evpxorq(xmm9, xmm9, xmm9, Assembler::AVX_512bit); + evpxorq(xmm10, xmm10, xmm10, Assembler::AVX_512bit); + evpxorq(xmm11, xmm11, xmm11, Assembler::AVX_512bit); + evpxorq(xmm12, xmm12, xmm12, Assembler::AVX_512bit); + evpxorq(xmm13, xmm13, xmm13, Assembler::AVX_512bit); + evpxorq(xmm14, xmm14, xmm14, Assembler::AVX_512bit); + evpxorq(xmm15, xmm15, xmm15, Assembler::AVX_512bit); + evpxorq(xmm16, xmm16, xmm16, Assembler::AVX_512bit); + evpxorq(xmm17, xmm17, xmm17, Assembler::AVX_512bit); + evpxorq(xmm18, xmm18, xmm18, Assembler::AVX_512bit); + evpxorq(xmm27, xmm27, xmm27, Assembler::AVX_512bit); + cmpl(rounds, 44); + jcc(Assembler::belowEqual, EXIT); + evpxorq(xmm19, xmm19, xmm19, Assembler::AVX_512bit); + evpxorq(xmm20, xmm20, xmm20, Assembler::AVX_512bit); + cmpl(rounds, 52); + jcc(Assembler::belowEqual, EXIT); + evpxorq(xmm21, xmm21, xmm21, Assembler::AVX_512bit); + evpxorq(xmm22, xmm22, xmm22, Assembler::AVX_512bit); + bind(EXIT); + pop(rbx); + pop(rax); // return length + pop(r12); + pop(r13); +} + +// Multiply 128 x 128 bits, using 4 pclmulqdq operations +void MacroAssembler::schoolbookAAD(int i, Register htbl, XMMRegister data, + XMMRegister tmp0, XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3) { + movdqu(xmm15, Address(htbl, i * 16)); + vpclmulhqlqdq(tmp3, data, xmm15); // 0x01 + vpxor(tmp2, tmp2, tmp3, Assembler::AVX_128bit); + vpclmulldq(tmp3, data, xmm15); // 0x00 + vpxor(tmp0, tmp0, tmp3, Assembler::AVX_128bit); + vpclmulhdq(tmp3, data, xmm15); // 0x11 + vpxor(tmp1, tmp1, tmp3, Assembler::AVX_128bit); + vpclmullqhqdq(tmp3, data, xmm15); // 0x10 + vpxor(tmp2, tmp2, tmp3, Assembler::AVX_128bit); +} + +// Multiply two 128 bit numbers resulting in a 256 bit value +// Result of the multiplication followed by reduction stored in state +void MacroAssembler::gfmul(XMMRegister tmp0, XMMRegister state) { + const XMMRegister tmp1 = xmm4; + const XMMRegister tmp2 = xmm5; + const XMMRegister tmp3 = xmm6; + const XMMRegister tmp4 = xmm7; + + vpclmulldq(tmp1, state, tmp0); //0x00 (a0 * b0) + vpclmulhdq(tmp4, state, tmp0);//0x11 (a1 * b1) + vpclmullqhqdq(tmp2, state, tmp0);//0x10 (a1 * b0) + vpclmulhqlqdq(tmp3, state, tmp0); //0x01 (a0 * b1) + + vpxor(tmp2, tmp2, tmp3, Assembler::AVX_128bit); // (a0 * b1) + (a1 * b0) + + vpslldq(tmp3, tmp2, 8, Assembler::AVX_128bit); + vpsrldq(tmp2, tmp2, 8, Assembler::AVX_128bit); + vpxor(tmp1, tmp1, tmp3, Assembler::AVX_128bit); // tmp1 and tmp4 hold the result + vpxor(tmp4, tmp4, tmp2, Assembler::AVX_128bit); // of carryless multiplication + // Follows the reduction technique mentioned in + // Shift-XOR reduction described in Gueron-Kounavis May 2010 + // First phase of reduction + // + vpslld(xmm8, tmp1, 31, Assembler::AVX_128bit); // packed right shift shifting << 31 + vpslld(xmm9, tmp1, 30, Assembler::AVX_128bit); // packed right shift shifting << 30 + vpslld(xmm10, tmp1, 25, Assembler::AVX_128bit);// packed right shift shifting << 25 + // xor the shifted versions + vpxor(xmm8, xmm8, xmm9, Assembler::AVX_128bit); + vpxor(xmm8, xmm8, xmm10, Assembler::AVX_128bit); + vpslldq(xmm9, xmm8, 12, Assembler::AVX_128bit); + vpsrldq(xmm8, xmm8, 4, Assembler::AVX_128bit); + vpxor(tmp1, tmp1, xmm9, Assembler::AVX_128bit);// first phase of the reduction complete + // + // Second phase of the reduction + // + vpsrld(xmm9, tmp1, 1, Assembler::AVX_128bit);// packed left shifting >> 1 + vpsrld(xmm10, tmp1, 2, Assembler::AVX_128bit);// packed left shifting >> 2 + vpsrld(xmm11, tmp1, 7, Assembler::AVX_128bit);// packed left shifting >> 7 + vpxor(xmm9, xmm9, xmm10, Assembler::AVX_128bit);// xor the shifted versions + vpxor(xmm9, xmm9, xmm11, Assembler::AVX_128bit); + vpxor(xmm9, xmm9, xmm8, Assembler::AVX_128bit); + vpxor(tmp1, tmp1, xmm9, Assembler::AVX_128bit); + vpxor(state, tmp4, tmp1, Assembler::AVX_128bit);// the result is in state + ret(0); +} + +// This method takes the subkey after expansion as input and generates 1 * 16 power of subkey H. +// The power of H is used in reduction process for one block ghash +void MacroAssembler::generateHtbl_one_block(Register htbl) { + const XMMRegister t = xmm13; + + // load the original subkey hash + movdqu(t, Address(htbl, 0)); + // shuffle using long swap mask + movdqu(xmm10, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr())); + vpshufb(t, t, xmm10, Assembler::AVX_128bit); + + // Compute H' = GFMUL(H, 2) + vpsrld(xmm3, t, 7, Assembler::AVX_128bit); + movdqu(xmm4, ExternalAddress(StubRoutines::x86::ghash_shufflemask_addr())); + vpshufb(xmm3, xmm3, xmm4, Assembler::AVX_128bit); + movl(rax, 0xff00); + movdl(xmm4, rax); + vpshufb(xmm4, xmm4, xmm3, Assembler::AVX_128bit); + movdqu(xmm5, ExternalAddress(StubRoutines::x86::ghash_polynomial_addr())); + vpand(xmm5, xmm5, xmm4, Assembler::AVX_128bit); + vpsrld(xmm3, t, 31, Assembler::AVX_128bit); + vpslld(xmm4, t, 1, Assembler::AVX_128bit); + vpslldq(xmm3, xmm3, 4, Assembler::AVX_128bit); + vpxor(t, xmm4, xmm3, Assembler::AVX_128bit);// t holds p(x) <<1 or H * 2 + + //Adding p(x)<<1 to xmm5 which holds the reduction polynomial + vpxor(t, t, xmm5, Assembler::AVX_128bit); + movdqu(Address(htbl, 1 * 16), t); // H * 2 + + ret(0); +} + +// This method takes the subkey after expansion as input and generates the remaining powers of subkey H. +// The power of H is used in reduction process for eight block ghash +void MacroAssembler::generateHtbl_eight_blocks(Register htbl) { + const XMMRegister t = xmm13; + const XMMRegister tmp0 = xmm1; + Label GFMUL; + + movdqu(t, Address(htbl, 1 * 16)); + movdqu(tmp0, t); + + // tmp0 and t hold H. Now we compute powers of H by using GFMUL(H, H) + call(GFMUL, relocInfo::none); + movdqu(Address(htbl, 2 * 16), t); //H ^ 2 * 2 + call(GFMUL, relocInfo::none); + movdqu(Address(htbl, 3 * 16), t); //H ^ 3 * 2 + call(GFMUL, relocInfo::none); + movdqu(Address(htbl, 4 * 16), t); //H ^ 4 * 2 + call(GFMUL, relocInfo::none); + movdqu(Address(htbl, 5 * 16), t); //H ^ 5 * 2 + call(GFMUL, relocInfo::none); + movdqu(Address(htbl, 6 * 16), t); //H ^ 6 * 2 + call(GFMUL, relocInfo::none); + movdqu(Address(htbl, 7 * 16), t); //H ^ 7 * 2 + call(GFMUL, relocInfo::none); + movdqu(Address(htbl, 8 * 16), t); //H ^ 8 * 2 + ret(0); + + bind(GFMUL); + gfmul(tmp0, t); +} + +// Multiblock and single block GHASH computation using Shift XOR reduction technique +void MacroAssembler::avx_ghash(Register input_state, Register htbl, + Register input_data, Register blocks) { + + // temporary variables to hold input data and input state + const XMMRegister data = xmm1; + const XMMRegister state = xmm0; + // temporary variables to hold intermediate results + const XMMRegister tmp0 = xmm3; + const XMMRegister tmp1 = xmm4; + const XMMRegister tmp2 = xmm5; + const XMMRegister tmp3 = xmm6; + // temporary variables to hold byte and long swap masks + const XMMRegister bswap_mask = xmm2; + const XMMRegister lswap_mask = xmm14; + + Label GENERATE_HTBL_1_BLK, GENERATE_HTBL_8_BLKS, BEGIN_PROCESS, GFMUL, BLOCK8_REDUCTION, + ONE_BLK_INIT, PROCESS_1_BLOCK, PROCESS_8_BLOCKS, SAVE_STATE, EXIT_GHASH; + + testptr(blocks, blocks); + jcc(Assembler::zero, EXIT_GHASH); + + // Check if Hashtable (1*16) has been already generated + // For anything less than 8 blocks, we generate only the first power of H. + movdqu(tmp2, Address(htbl, 1 * 16)); + ptest(tmp2, tmp2); + jcc(Assembler::notZero, BEGIN_PROCESS); + call(GENERATE_HTBL_1_BLK, relocInfo::none); + + // Shuffle the input state + bind(BEGIN_PROCESS); + movdqu(lswap_mask, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr())); + movdqu(state, Address(input_state, 0)); + vpshufb(state, state, lswap_mask, Assembler::AVX_128bit); + + cmpl(blocks, 8); + jcc(Assembler::below, ONE_BLK_INIT); + // If we have 8 blocks or more data, then generate remaining powers of H + movdqu(tmp2, Address(htbl, 8 * 16)); + ptest(tmp2, tmp2); + jcc(Assembler::notZero, PROCESS_8_BLOCKS); + call(GENERATE_HTBL_8_BLKS, relocInfo::none); + + //Do 8 multiplies followed by a reduction processing 8 blocks of data at a time + //Each block = 16 bytes. + bind(PROCESS_8_BLOCKS); + subl(blocks, 8); + movdqu(bswap_mask, ExternalAddress(StubRoutines::x86::ghash_byte_swap_mask_addr())); + movdqu(data, Address(input_data, 16 * 7)); + vpshufb(data, data, bswap_mask, Assembler::AVX_128bit); + //Loading 1*16 as calculated powers of H required starts at that location. + movdqu(xmm15, Address(htbl, 1 * 16)); + //Perform carryless multiplication of (H*2, data block #7) + vpclmulhqlqdq(tmp2, data, xmm15);//a0 * b1 + vpclmulldq(tmp0, data, xmm15);//a0 * b0 + vpclmulhdq(tmp1, data, xmm15);//a1 * b1 + vpclmullqhqdq(tmp3, data, xmm15);//a1* b0 + vpxor(tmp2, tmp2, tmp3, Assembler::AVX_128bit);// (a0 * b1) + (a1 * b0) + + movdqu(data, Address(input_data, 16 * 6)); + vpshufb(data, data, bswap_mask, Assembler::AVX_128bit); + // Perform carryless multiplication of (H^2 * 2, data block #6) + schoolbookAAD(2, htbl, data, tmp0, tmp1, tmp2, tmp3); + + movdqu(data, Address(input_data, 16 * 5)); + vpshufb(data, data, bswap_mask, Assembler::AVX_128bit); + // Perform carryless multiplication of (H^3 * 2, data block #5) + schoolbookAAD(3, htbl, data, tmp0, tmp1, tmp2, tmp3); + movdqu(data, Address(input_data, 16 * 4)); + vpshufb(data, data, bswap_mask, Assembler::AVX_128bit); + // Perform carryless multiplication of (H^4 * 2, data block #4) + schoolbookAAD(4, htbl, data, tmp0, tmp1, tmp2, tmp3); + movdqu(data, Address(input_data, 16 * 3)); + vpshufb(data, data, bswap_mask, Assembler::AVX_128bit); + // Perform carryless multiplication of (H^5 * 2, data block #3) + schoolbookAAD(5, htbl, data, tmp0, tmp1, tmp2, tmp3); + movdqu(data, Address(input_data, 16 * 2)); + vpshufb(data, data, bswap_mask, Assembler::AVX_128bit); + // Perform carryless multiplication of (H^6 * 2, data block #2) + schoolbookAAD(6, htbl, data, tmp0, tmp1, tmp2, tmp3); + movdqu(data, Address(input_data, 16 * 1)); + vpshufb(data, data, bswap_mask, Assembler::AVX_128bit); + // Perform carryless multiplication of (H^7 * 2, data block #1) + schoolbookAAD(7, htbl, data, tmp0, tmp1, tmp2, tmp3); + movdqu(data, Address(input_data, 16 * 0)); + // xor data block#0 with input state before perfoming carry-less multiplication + vpshufb(data, data, bswap_mask, Assembler::AVX_128bit); + vpxor(data, data, state, Assembler::AVX_128bit); + // Perform carryless multiplication of (H^8 * 2, data block #0) + schoolbookAAD(8, htbl, data, tmp0, tmp1, tmp2, tmp3); + vpslldq(tmp3, tmp2, 8, Assembler::AVX_128bit); + vpsrldq(tmp2, tmp2, 8, Assembler::AVX_128bit); + vpxor(tmp0, tmp0, tmp3, Assembler::AVX_128bit);// tmp0, tmp1 contains aggregated results of + vpxor(tmp1, tmp1, tmp2, Assembler::AVX_128bit);// the multiplication operation + + // we have the 2 128-bit partially accumulated multiplication results in tmp0:tmp1 + // with higher 128-bit in tmp1 and lower 128-bit in corresponding tmp0 + // Follows the reduction technique mentioned in + // Shift-XOR reduction described in Gueron-Kounavis May 2010 + bind(BLOCK8_REDUCTION); + // First Phase of the reduction + vpslld(xmm8, tmp0, 31, Assembler::AVX_128bit); // packed right shifting << 31 + vpslld(xmm9, tmp0, 30, Assembler::AVX_128bit); // packed right shifting << 30 + vpslld(xmm10, tmp0, 25, Assembler::AVX_128bit); // packed right shifting << 25 + // xor the shifted versions + vpxor(xmm8, xmm8, xmm10, Assembler::AVX_128bit); + vpxor(xmm8, xmm8, xmm9, Assembler::AVX_128bit); + + vpslldq(xmm9, xmm8, 12, Assembler::AVX_128bit); + vpsrldq(xmm8, xmm8, 4, Assembler::AVX_128bit); + + vpxor(tmp0, tmp0, xmm9, Assembler::AVX_128bit); // first phase of reduction is complete + // second phase of the reduction + vpsrld(xmm9, tmp0, 1, Assembler::AVX_128bit); // packed left shifting >> 1 + vpsrld(xmm10, tmp0, 2, Assembler::AVX_128bit); // packed left shifting >> 2 + vpsrld(tmp2, tmp0, 7, Assembler::AVX_128bit); // packed left shifting >> 7 + // xor the shifted versions + vpxor(xmm9, xmm9, xmm10, Assembler::AVX_128bit); + vpxor(xmm9, xmm9, tmp2, Assembler::AVX_128bit); + vpxor(xmm9, xmm9, xmm8, Assembler::AVX_128bit); + vpxor(tmp0, xmm9, tmp0, Assembler::AVX_128bit); + // Final result is in state + vpxor(state, tmp0, tmp1, Assembler::AVX_128bit); + + lea(input_data, Address(input_data, 16 * 8)); + cmpl(blocks, 8); + jcc(Assembler::below, ONE_BLK_INIT); + jmp(PROCESS_8_BLOCKS); + + // Since this is one block operation we will only use H * 2 i.e. the first power of H + bind(ONE_BLK_INIT); + movdqu(tmp0, Address(htbl, 1 * 16)); + movdqu(bswap_mask, ExternalAddress(StubRoutines::x86::ghash_byte_swap_mask_addr())); + + //Do one (128 bit x 128 bit) carry-less multiplication at a time followed by a reduction. + bind(PROCESS_1_BLOCK); + cmpl(blocks, 0); + jcc(Assembler::equal, SAVE_STATE); + subl(blocks, 1); + movdqu(data, Address(input_data, 0)); + vpshufb(data, data, bswap_mask, Assembler::AVX_128bit); + vpxor(state, state, data, Assembler::AVX_128bit); + // gfmul(H*2, state) + call(GFMUL, relocInfo::none); + addptr(input_data, 16); + jmp(PROCESS_1_BLOCK); + + bind(SAVE_STATE); + vpshufb(state, state, lswap_mask, Assembler::AVX_128bit); + movdqu(Address(input_state, 0), state); + jmp(EXIT_GHASH); + + bind(GFMUL); + gfmul(tmp0, state); + + bind(GENERATE_HTBL_1_BLK); + generateHtbl_one_block(htbl); + + bind(GENERATE_HTBL_8_BLKS); + generateHtbl_eight_blocks(htbl); + + bind(EXIT_GHASH); + // zero out xmm registers used for Htbl storage + vpxor(xmm0, xmm0, xmm0, Assembler::AVX_128bit); + vpxor(xmm1, xmm1, xmm1, Assembler::AVX_128bit); + vpxor(xmm3, xmm3, xmm3, Assembler::AVX_128bit); + vpxor(xmm15, xmm15, xmm15, Assembler::AVX_128bit); +} + +// AES Counter Mode using VAES instructions +void MacroAssembler::aesctr_encrypt(Register src_addr, Register dest_addr, Register key, Register counter, + Register len_reg, Register used, Register used_addr, Register saved_encCounter_start) { + + const Register rounds = 0; + const Register pos = r12; + + Label PRELOOP_START, EXIT_PRELOOP, REMAINDER, REMAINDER_16, LOOP, END, EXIT, END_LOOP, + AES192, AES256, AES192_REMAINDER16, REMAINDER16_END_LOOP, AES256_REMAINDER16, + REMAINDER_8, REMAINDER_4, AES192_REMAINDER8, REMAINDER_LOOP, AES256_REMINDER, + AES192_REMAINDER, END_REMAINDER_LOOP, AES256_REMAINDER8, REMAINDER8_END_LOOP, + AES192_REMAINDER4, AES256_REMAINDER4, AES256_REMAINDER, END_REMAINDER4, EXTRACT_TAILBYTES, + EXTRACT_TAIL_4BYTES, EXTRACT_TAIL_2BYTES, EXTRACT_TAIL_1BYTE, STORE_CTR; + + cmpl(len_reg, 0); + jcc(Assembler::belowEqual, EXIT); + + movl(pos, 0); + // if the number of used encrypted counter bytes < 16, + // XOR PT with saved encrypted counter to obtain CT + bind(PRELOOP_START); + cmpl(used, 16); + jcc(Assembler::aboveEqual, EXIT_PRELOOP); + movb(rbx, Address(saved_encCounter_start, used)); + xorb(rbx, Address(src_addr, pos)); + movb(Address(dest_addr, pos), rbx); + addptr(pos, 1); + addptr(used, 1); + decrement(len_reg); + jmp(PRELOOP_START); + + bind(EXIT_PRELOOP); + movl(Address(used_addr, 0), used); + + // Calculate number of rounds i.e. 10, 12, 14, based on key length(128, 192, 256). + movl(rounds, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT))); + + vpxor(xmm0, xmm0, xmm0, Assembler::AVX_128bit); + // Move initial counter value in xmm0 + movdqu(xmm0, Address(counter, 0)); + // broadcast counter value to zmm8 + evshufi64x2(xmm8, xmm0, xmm0, 0, Assembler::AVX_512bit); + + // load lbswap mask + evmovdquq(xmm16, ExternalAddress(StubRoutines::x86::counter_mask_addr()), Assembler::AVX_512bit, r15); + + //shuffle counter using lbswap_mask + vpshufb(xmm8, xmm8, xmm16, Assembler::AVX_512bit); + + // pre-increment and propagate counter values to zmm9-zmm15 registers. + // Linc0 increments the zmm8 by 1 (initial value being 0), Linc4 increments the counters zmm9-zmm15 by 4 + // The counter is incremented after each block i.e. 16 bytes is processed; + // each zmm register has 4 counter values as its MSB + // the counters are incremented in parallel + vpaddd(xmm8, xmm8, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 64), Assembler::AVX_512bit, r15);//linc0 + vpaddd(xmm9, xmm8, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//linc4(rip) + vpaddd(xmm10, xmm9, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip) + vpaddd(xmm11, xmm10, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip) + vpaddd(xmm12, xmm11, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip) + vpaddd(xmm13, xmm12, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip) + vpaddd(xmm14, xmm13, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip) + vpaddd(xmm15, xmm14, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip) + + // load linc32 mask in zmm register.linc32 increments counter by 32 + evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 256), Assembler::AVX_512bit, r15);//Linc32 + + // xmm31 contains the key shuffle mask. + movdqu(xmm31, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr())); + // Load key function loads 128 bit key and shuffles it. Then we broadcast the shuffled key to convert it into a 512 bit value. + // For broadcasting the values to ZMM, vshufi64 is used instead of evbroadcasti64x2 as the source in this case is ZMM register + // that holds shuffled key value. + ev_load_key(xmm20, key, 0, xmm31); + ev_load_key(xmm21, key, 1 * 16, xmm31); + ev_load_key(xmm22, key, 2 * 16, xmm31); + ev_load_key(xmm23, key, 3 * 16, xmm31); + ev_load_key(xmm24, key, 4 * 16, xmm31); + ev_load_key(xmm25, key, 5 * 16, xmm31); + ev_load_key(xmm26, key, 6 * 16, xmm31); + ev_load_key(xmm27, key, 7 * 16, xmm31); + ev_load_key(xmm28, key, 8 * 16, xmm31); + ev_load_key(xmm29, key, 9 * 16, xmm31); + ev_load_key(xmm30, key, 10 * 16, xmm31); + + // Process 32 blocks or 512 bytes of data + bind(LOOP); + cmpl(len_reg, 512); + jcc(Assembler::less, REMAINDER); + subq(len_reg, 512); + //Shuffle counter and Exor it with roundkey1. Result is stored in zmm0-7 + vpshufb(xmm0, xmm8, xmm16, Assembler::AVX_512bit); + evpxorq(xmm0, xmm0, xmm20, Assembler::AVX_512bit); + vpshufb(xmm1, xmm9, xmm16, Assembler::AVX_512bit); + evpxorq(xmm1, xmm1, xmm20, Assembler::AVX_512bit); + vpshufb(xmm2, xmm10, xmm16, Assembler::AVX_512bit); + evpxorq(xmm2, xmm2, xmm20, Assembler::AVX_512bit); + vpshufb(xmm3, xmm11, xmm16, Assembler::AVX_512bit); + evpxorq(xmm3, xmm3, xmm20, Assembler::AVX_512bit); + vpshufb(xmm4, xmm12, xmm16, Assembler::AVX_512bit); + evpxorq(xmm4, xmm4, xmm20, Assembler::AVX_512bit); + vpshufb(xmm5, xmm13, xmm16, Assembler::AVX_512bit); + evpxorq(xmm5, xmm5, xmm20, Assembler::AVX_512bit); + vpshufb(xmm6, xmm14, xmm16, Assembler::AVX_512bit); + evpxorq(xmm6, xmm6, xmm20, Assembler::AVX_512bit); + vpshufb(xmm7, xmm15, xmm16, Assembler::AVX_512bit); + evpxorq(xmm7, xmm7, xmm20, Assembler::AVX_512bit); + // Perform AES encode operations and put results in zmm0-zmm7. + // This is followed by incrementing counter values in zmm8-zmm15. + // Since we will be processing 32 blocks at a time, the counter is incremented by 32. + roundEnc(xmm21, 7); + vpaddq(xmm8, xmm8, xmm19, Assembler::AVX_512bit); + roundEnc(xmm22, 7); + vpaddq(xmm9, xmm9, xmm19, Assembler::AVX_512bit); + roundEnc(xmm23, 7); + vpaddq(xmm10, xmm10, xmm19, Assembler::AVX_512bit); + roundEnc(xmm24, 7); + vpaddq(xmm11, xmm11, xmm19, Assembler::AVX_512bit); + roundEnc(xmm25, 7); + vpaddq(xmm12, xmm12, xmm19, Assembler::AVX_512bit); + roundEnc(xmm26, 7); + vpaddq(xmm13, xmm13, xmm19, Assembler::AVX_512bit); + roundEnc(xmm27, 7); + vpaddq(xmm14, xmm14, xmm19, Assembler::AVX_512bit); + roundEnc(xmm28, 7); + vpaddq(xmm15, xmm15, xmm19, Assembler::AVX_512bit); + roundEnc(xmm29, 7); + + cmpl(rounds, 52); + jcc(Assembler::aboveEqual, AES192); + lastroundEnc(xmm30, 7); + jmp(END_LOOP); + + bind(AES192); + roundEnc(xmm30, 7); + ev_load_key(xmm18, key, 11 * 16, xmm31); + roundEnc(xmm18, 7); + cmpl(rounds, 60); + jcc(Assembler::aboveEqual, AES256); + ev_load_key(xmm18, key, 12 * 16, xmm31); + lastroundEnc(xmm18, 7); + jmp(END_LOOP); + + bind(AES256); + ev_load_key(xmm18, key, 12 * 16, xmm31); + roundEnc(xmm18, 7); + ev_load_key(xmm18, key, 13 * 16, xmm31); + roundEnc(xmm18, 7); + ev_load_key(xmm18, key, 14 * 16, xmm31); + lastroundEnc(xmm18, 7); + + // After AES encode rounds, the encrypted block cipher lies in zmm0-zmm7 + // xor encrypted block cipher and input plaintext and store resultant ciphertext + bind(END_LOOP); + evpxorq(xmm0, xmm0, Address(src_addr, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 0), xmm0, Assembler::AVX_512bit); + evpxorq(xmm1, xmm1, Address(src_addr, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 64), xmm1, Assembler::AVX_512bit); + evpxorq(xmm2, xmm2, Address(src_addr, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 2 * 64), xmm2, Assembler::AVX_512bit); + evpxorq(xmm3, xmm3, Address(src_addr, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 3 * 64), xmm3, Assembler::AVX_512bit); + evpxorq(xmm4, xmm4, Address(src_addr, pos, Address::times_1, 4 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 4 * 64), xmm4, Assembler::AVX_512bit); + evpxorq(xmm5, xmm5, Address(src_addr, pos, Address::times_1, 5 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 5 * 64), xmm5, Assembler::AVX_512bit); + evpxorq(xmm6, xmm6, Address(src_addr, pos, Address::times_1, 6 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 6 * 64), xmm6, Assembler::AVX_512bit); + evpxorq(xmm7, xmm7, Address(src_addr, pos, Address::times_1, 7 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 7 * 64), xmm7, Assembler::AVX_512bit); + addq(pos, 512); + jmp(LOOP); + + // Encode 256, 128, 64 or 16 bytes at a time if length is less than 512 bytes + bind(REMAINDER); + cmpl(len_reg, 0); + jcc(Assembler::equal, END); + cmpl(len_reg, 256); + jcc(Assembler::aboveEqual, REMAINDER_16); + cmpl(len_reg, 128); + jcc(Assembler::aboveEqual, REMAINDER_8); + cmpl(len_reg, 64); + jcc(Assembler::aboveEqual, REMAINDER_4); + // At this point, we will process 16 bytes of data at a time. + // So load xmm19 with counter increment value as 1 + evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 80), Assembler::AVX_128bit, r15); + jmp(REMAINDER_LOOP); + + // Each ZMM register can be used to encode 64 bytes of data, so we have 4 ZMM registers to encode 256 bytes of data + bind(REMAINDER_16); + subq(len_reg, 256); + // As we process 16 blocks at a time, load mask for incrementing the counter value by 16 + evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 320), Assembler::AVX_512bit, r15);//Linc16(rip) + // shuffle counter and XOR counter with roundkey1 + vpshufb(xmm0, xmm8, xmm16, Assembler::AVX_512bit); + evpxorq(xmm0, xmm0, xmm20, Assembler::AVX_512bit); + vpshufb(xmm1, xmm9, xmm16, Assembler::AVX_512bit); + evpxorq(xmm1, xmm1, xmm20, Assembler::AVX_512bit); + vpshufb(xmm2, xmm10, xmm16, Assembler::AVX_512bit); + evpxorq(xmm2, xmm2, xmm20, Assembler::AVX_512bit); + vpshufb(xmm3, xmm11, xmm16, Assembler::AVX_512bit); + evpxorq(xmm3, xmm3, xmm20, Assembler::AVX_512bit); + // Increment counter values by 16 + vpaddq(xmm8, xmm8, xmm19, Assembler::AVX_512bit); + vpaddq(xmm9, xmm9, xmm19, Assembler::AVX_512bit); + // AES encode rounds + roundEnc(xmm21, 3); + roundEnc(xmm22, 3); + roundEnc(xmm23, 3); + roundEnc(xmm24, 3); + roundEnc(xmm25, 3); + roundEnc(xmm26, 3); + roundEnc(xmm27, 3); + roundEnc(xmm28, 3); + roundEnc(xmm29, 3); + + cmpl(rounds, 52); + jcc(Assembler::aboveEqual, AES192_REMAINDER16); + lastroundEnc(xmm30, 3); + jmp(REMAINDER16_END_LOOP); + + bind(AES192_REMAINDER16); + roundEnc(xmm30, 3); + ev_load_key(xmm18, key, 11 * 16, xmm31); + roundEnc(xmm18, 3); + ev_load_key(xmm5, key, 12 * 16, xmm31); + + cmpl(rounds, 60); + jcc(Assembler::aboveEqual, AES256_REMAINDER16); + lastroundEnc(xmm5, 3); + jmp(REMAINDER16_END_LOOP); + bind(AES256_REMAINDER16); + roundEnc(xmm5, 3); + ev_load_key(xmm6, key, 13 * 16, xmm31); + roundEnc(xmm6, 3); + ev_load_key(xmm7, key, 14 * 16, xmm31); + lastroundEnc(xmm7, 3); + + // After AES encode rounds, the encrypted block cipher lies in zmm0-zmm3 + // xor 256 bytes of PT with the encrypted counters to produce CT. + bind(REMAINDER16_END_LOOP); + evpxorq(xmm0, xmm0, Address(src_addr, pos, Address::times_1, 0), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 0), xmm0, Assembler::AVX_512bit); + evpxorq(xmm1, xmm1, Address(src_addr, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 1 * 64), xmm1, Assembler::AVX_512bit); + evpxorq(xmm2, xmm2, Address(src_addr, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 2 * 64), xmm2, Assembler::AVX_512bit); + evpxorq(xmm3, xmm3, Address(src_addr, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 3 * 64), xmm3, Assembler::AVX_512bit); + addq(pos, 256); + + cmpl(len_reg, 128); + jcc(Assembler::aboveEqual, REMAINDER_8); + + cmpl(len_reg, 64); + jcc(Assembler::aboveEqual, REMAINDER_4); + //load mask for incrementing the counter value by 1 + evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 80), Assembler::AVX_128bit, r15);//Linc0 + 16(rip) + jmp(REMAINDER_LOOP); + + // Each ZMM register can be used to encode 64 bytes of data, so we have 2 ZMM registers to encode 128 bytes of data + bind(REMAINDER_8); + subq(len_reg, 128); + // As we process 8 blocks at a time, load mask for incrementing the counter value by 8 + evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 192), Assembler::AVX_512bit, r15);//Linc8(rip) + // shuffle counters and xor with roundkey1 + vpshufb(xmm0, xmm8, xmm16, Assembler::AVX_512bit); + evpxorq(xmm0, xmm0, xmm20, Assembler::AVX_512bit); + vpshufb(xmm1, xmm9, xmm16, Assembler::AVX_512bit); + evpxorq(xmm1, xmm1, xmm20, Assembler::AVX_512bit); + // increment counter by 8 + vpaddq(xmm8, xmm8, xmm19, Assembler::AVX_512bit); + // AES encode + roundEnc(xmm21, 1); + roundEnc(xmm22, 1); + roundEnc(xmm23, 1); + roundEnc(xmm24, 1); + roundEnc(xmm25, 1); + roundEnc(xmm26, 1); + roundEnc(xmm27, 1); + roundEnc(xmm28, 1); + roundEnc(xmm29, 1); + + cmpl(rounds, 52); + jcc(Assembler::aboveEqual, AES192_REMAINDER8); + lastroundEnc(xmm30, 1); + jmp(REMAINDER8_END_LOOP); + + bind(AES192_REMAINDER8); + roundEnc(xmm30, 1); + ev_load_key(xmm18, key, 11 * 16, xmm31); + roundEnc(xmm18, 1); + ev_load_key(xmm5, key, 12 * 16, xmm31); + cmpl(rounds, 60); + jcc(Assembler::aboveEqual, AES256_REMAINDER8); + lastroundEnc(xmm5, 1); + jmp(REMAINDER8_END_LOOP); + + bind(AES256_REMAINDER8); + roundEnc(xmm5, 1); + ev_load_key(xmm6, key, 13 * 16, xmm31); + roundEnc(xmm6, 1); + ev_load_key(xmm7, key, 14 * 16, xmm31); + lastroundEnc(xmm7, 1); + + bind(REMAINDER8_END_LOOP); + // After AES encode rounds, the encrypted block cipher lies in zmm0-zmm1 + // XOR PT with the encrypted counter and store as CT + evpxorq(xmm0, xmm0, Address(src_addr, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 0 * 64), xmm0, Assembler::AVX_512bit); + evpxorq(xmm1, xmm1, Address(src_addr, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 1 * 64), xmm1, Assembler::AVX_512bit); + addq(pos, 128); + + cmpl(len_reg, 64); + jcc(Assembler::aboveEqual, REMAINDER_4); + // load mask for incrementing the counter value by 1 + evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 80), Assembler::AVX_128bit, r15);//Linc0 + 16(rip) + jmp(REMAINDER_LOOP); + + // Each ZMM register can be used to encode 64 bytes of data, so we have 1 ZMM register used in this block of code + bind(REMAINDER_4); + subq(len_reg, 64); + // As we process 4 blocks at a time, load mask for incrementing the counter value by 4 + evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip) + // XOR counter with first roundkey + vpshufb(xmm0, xmm8, xmm16, Assembler::AVX_512bit); + evpxorq(xmm0, xmm0, xmm20, Assembler::AVX_512bit); + // Increment counter + vpaddq(xmm8, xmm8, xmm19, Assembler::AVX_512bit); + vaesenc(xmm0, xmm0, xmm21, Assembler::AVX_512bit); + vaesenc(xmm0, xmm0, xmm22, Assembler::AVX_512bit); + vaesenc(xmm0, xmm0, xmm23, Assembler::AVX_512bit); + vaesenc(xmm0, xmm0, xmm24, Assembler::AVX_512bit); + vaesenc(xmm0, xmm0, xmm25, Assembler::AVX_512bit); + vaesenc(xmm0, xmm0, xmm26, Assembler::AVX_512bit); + vaesenc(xmm0, xmm0, xmm27, Assembler::AVX_512bit); + vaesenc(xmm0, xmm0, xmm28, Assembler::AVX_512bit); + vaesenc(xmm0, xmm0, xmm29, Assembler::AVX_512bit); + cmpl(rounds, 52); + jcc(Assembler::aboveEqual, AES192_REMAINDER4); + vaesenclast(xmm0, xmm0, xmm30, Assembler::AVX_512bit); + jmp(END_REMAINDER4); + + bind(AES192_REMAINDER4); + vaesenc(xmm0, xmm0, xmm30, Assembler::AVX_512bit); + ev_load_key(xmm18, key, 11 * 16, xmm31); + vaesenc(xmm0, xmm0, xmm18, Assembler::AVX_512bit); + ev_load_key(xmm5, key, 12 * 16, xmm31); + + cmpl(rounds, 60); + jcc(Assembler::aboveEqual, AES256_REMAINDER4); + vaesenclast(xmm0, xmm0, xmm5, Assembler::AVX_512bit); + jmp(END_REMAINDER4); + + bind(AES256_REMAINDER4); + vaesenc(xmm0, xmm0, xmm5, Assembler::AVX_512bit); + ev_load_key(xmm6, key, 13 * 16, xmm31); + vaesenc(xmm0, xmm0, xmm6, Assembler::AVX_512bit); + ev_load_key(xmm7, key, 14 * 16, xmm31); + vaesenclast(xmm0, xmm0, xmm7, Assembler::AVX_512bit); + // After AES encode rounds, the encrypted block cipher lies in zmm0. + // XOR encrypted block cipher with PT and store 64 bytes of ciphertext + bind(END_REMAINDER4); + evpxorq(xmm0, xmm0, Address(src_addr, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 0), xmm0, Assembler::AVX_512bit); + addq(pos, 64); + // load mask for incrementing the counter value by 1 + evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 80), Assembler::AVX_128bit, r15);//Linc0 + 16(rip) + + // For a single block, the AES rounds start here. + bind(REMAINDER_LOOP); + cmpl(len_reg, 0); + jcc(Assembler::belowEqual, END); + // XOR counter with first roundkey + vpshufb(xmm0, xmm8, xmm16, Assembler::AVX_128bit); + evpxorq(xmm0, xmm0, xmm20, Assembler::AVX_128bit); + vaesenc(xmm0, xmm0, xmm21, Assembler::AVX_128bit); + // Increment counter by 1 + vpaddq(xmm8, xmm8, xmm19, Assembler::AVX_128bit); + vaesenc(xmm0, xmm0, xmm22, Assembler::AVX_128bit); + vaesenc(xmm0, xmm0, xmm23, Assembler::AVX_128bit); + vaesenc(xmm0, xmm0, xmm24, Assembler::AVX_128bit); + vaesenc(xmm0, xmm0, xmm25, Assembler::AVX_128bit); + vaesenc(xmm0, xmm0, xmm26, Assembler::AVX_128bit); + vaesenc(xmm0, xmm0, xmm27, Assembler::AVX_128bit); + vaesenc(xmm0, xmm0, xmm28, Assembler::AVX_128bit); + vaesenc(xmm0, xmm0, xmm29, Assembler::AVX_128bit); + + cmpl(rounds, 52); + jcc(Assembler::aboveEqual, AES192_REMAINDER); + vaesenclast(xmm0, xmm0, xmm30, Assembler::AVX_128bit); + jmp(END_REMAINDER_LOOP); + + bind(AES192_REMAINDER); + vaesenc(xmm0, xmm0, xmm30, Assembler::AVX_128bit); + ev_load_key(xmm18, key, 11 * 16, xmm31); + vaesenc(xmm0, xmm0, xmm18, Assembler::AVX_128bit); + ev_load_key(xmm5, key, 12 * 16, xmm31); + cmpl(rounds, 60); + jcc(Assembler::aboveEqual, AES256_REMAINDER); + vaesenclast(xmm0, xmm0, xmm5, Assembler::AVX_128bit); + jmp(END_REMAINDER_LOOP); + + bind(AES256_REMAINDER); + vaesenc(xmm0, xmm0, xmm5, Assembler::AVX_128bit); + ev_load_key(xmm6, key, 13 * 16, xmm31); + vaesenc(xmm0, xmm0, xmm6, Assembler::AVX_128bit); + ev_load_key(xmm7, key, 14 * 16, xmm31); + vaesenclast(xmm0, xmm0, xmm7, Assembler::AVX_128bit); + + bind(END_REMAINDER_LOOP); + // If the length register is less than the blockSize i.e. 16 + // then we store only those bytes of the CT to the destination + // corresponding to the length register value + // extracting the exact number of bytes is handled by EXTRACT_TAILBYTES + cmpl(len_reg, 16); + jcc(Assembler::less, EXTRACT_TAILBYTES); + subl(len_reg, 16); + // After AES encode rounds, the encrypted block cipher lies in xmm0. + // If the length register is equal to 16 bytes, store CT in dest after XOR operation. + evpxorq(xmm0, xmm0, Address(src_addr, pos, Address::times_1, 0), Assembler::AVX_128bit); + evmovdquq(Address(dest_addr, pos, Address::times_1, 0), xmm0, Assembler::AVX_128bit); + addl(pos, 16); + + jmp(REMAINDER_LOOP); + + bind(EXTRACT_TAILBYTES); + // Save encrypted counter value in xmm0 for next invocation, before XOR operation + movdqu(Address(saved_encCounter_start, 0), xmm0); + // XOR encryted block cipher in xmm0 with PT to produce CT + evpxorq(xmm0, xmm0, Address(src_addr, pos, Address::times_1, 0), Assembler::AVX_128bit); + // extract upto 15 bytes of CT from xmm0 as specified by length register + testptr(len_reg, 8); + jcc(Assembler::zero, EXTRACT_TAIL_4BYTES); + pextrq(Address(dest_addr, pos), xmm0, 0); + psrldq(xmm0, 8); + addl(pos, 8); + bind(EXTRACT_TAIL_4BYTES); + testptr(len_reg, 4); + jcc(Assembler::zero, EXTRACT_TAIL_2BYTES); + pextrd(Address(dest_addr, pos), xmm0, 0); + psrldq(xmm0, 4); + addq(pos, 4); + bind(EXTRACT_TAIL_2BYTES); + testptr(len_reg, 2); + jcc(Assembler::zero, EXTRACT_TAIL_1BYTE); + pextrw(Address(dest_addr, pos), xmm0, 0); + psrldq(xmm0, 2); + addl(pos, 2); + bind(EXTRACT_TAIL_1BYTE); + testptr(len_reg, 1); + jcc(Assembler::zero, END); + pextrb(Address(dest_addr, pos), xmm0, 0); + addl(pos, 1); + + bind(END); + // If there are no tail bytes, store counter value and exit + cmpl(len_reg, 0); + jcc(Assembler::equal, STORE_CTR); + movl(Address(used_addr, 0), len_reg); + + bind(STORE_CTR); + //shuffle updated counter and store it + vpshufb(xmm8, xmm8, xmm16, Assembler::AVX_128bit); + movdqu(Address(counter, 0), xmm8); + // Zero out counter and key registers + evpxorq(xmm8, xmm8, xmm8, Assembler::AVX_512bit); + evpxorq(xmm20, xmm20, xmm20, Assembler::AVX_512bit); + evpxorq(xmm21, xmm21, xmm21, Assembler::AVX_512bit); + evpxorq(xmm22, xmm22, xmm22, Assembler::AVX_512bit); + evpxorq(xmm23, xmm23, xmm23, Assembler::AVX_512bit); + evpxorq(xmm24, xmm24, xmm24, Assembler::AVX_512bit); + evpxorq(xmm25, xmm25, xmm25, Assembler::AVX_512bit); + evpxorq(xmm26, xmm26, xmm26, Assembler::AVX_512bit); + evpxorq(xmm27, xmm27, xmm27, Assembler::AVX_512bit); + evpxorq(xmm28, xmm28, xmm28, Assembler::AVX_512bit); + evpxorq(xmm29, xmm29, xmm29, Assembler::AVX_512bit); + evpxorq(xmm30, xmm30, xmm30, Assembler::AVX_512bit); + cmpl(rounds, 44); + jcc(Assembler::belowEqual, EXIT); + evpxorq(xmm18, xmm18, xmm18, Assembler::AVX_512bit); + evpxorq(xmm5, xmm5, xmm5, Assembler::AVX_512bit); + cmpl(rounds, 52); + jcc(Assembler::belowEqual, EXIT); + evpxorq(xmm6, xmm6, xmm6, Assembler::AVX_512bit); + evpxorq(xmm7, xmm7, xmm7, Assembler::AVX_512bit); + bind(EXIT); +} + +#endif // _LP64
diff --git a/src/hotspot/cpu/x86/macroAssembler_x86_exp.cpp b/src/hotspot/cpu/x86/macroAssembler_x86_exp.cpp index 4863b3e..2c0610a 100644 --- a/src/hotspot/cpu/x86/macroAssembler_x86_exp.cpp +++ b/src/hotspot/cpu/x86/macroAssembler_x86_exp.cpp
@@ -493,7 +493,7 @@ subl(rsp, 120); movl(Address(rsp, 64), tmp); lea(tmp, ExternalAddress(static_const_table)); - movdqu(xmm0, Address(rsp, 128)); + movsd(xmm0, Address(rsp, 128)); unpcklpd(xmm0, xmm0); movdqu(xmm1, Address(tmp, 64)); // 0x652b82feUL, 0x40571547UL, 0x652b82feUL, 0x40571547UL movdqu(xmm6, Address(tmp, 48)); // 0x00000000UL, 0x43380000UL, 0x00000000UL, 0x43380000UL @@ -585,18 +585,18 @@ pextrw(ecx, xmm0, 3); andl(ecx, 32752); cmpl(ecx, 32752); - jcc(Assembler::greaterEqual, L_2TAG_PACKET_3_0_2); + jcc(Assembler::aboveEqual, L_2TAG_PACKET_3_0_2); cmpl(ecx, 0); jcc(Assembler::equal, L_2TAG_PACKET_4_0_2); jmp(L_2TAG_PACKET_2_0_2); cmpl(ecx, INT_MIN); - jcc(Assembler::less, L_2TAG_PACKET_3_0_2); + jcc(Assembler::below, L_2TAG_PACKET_3_0_2); cmpl(ecx, -1064950997); - jcc(Assembler::less, L_2TAG_PACKET_2_0_2); - jcc(Assembler::greater, L_2TAG_PACKET_4_0_2); + jcc(Assembler::below, L_2TAG_PACKET_2_0_2); + jcc(Assembler::above, L_2TAG_PACKET_4_0_2); movl(edx, Address(rsp, 128)); cmpl(edx, -17155601); - jcc(Assembler::less, L_2TAG_PACKET_2_0_2); + jcc(Assembler::below, L_2TAG_PACKET_2_0_2); jmp(L_2TAG_PACKET_4_0_2); bind(L_2TAG_PACKET_3_0_2); @@ -614,10 +614,10 @@ bind(L_2TAG_PACKET_7_0_2); cmpl(eax, 2146435072); - jcc(Assembler::greaterEqual, L_2TAG_PACKET_8_0_2); + jcc(Assembler::aboveEqual, L_2TAG_PACKET_8_0_2); movl(eax, Address(rsp, 132)); cmpl(eax, INT_MIN); - jcc(Assembler::greaterEqual, L_2TAG_PACKET_9_0_2); + jcc(Assembler::aboveEqual, L_2TAG_PACKET_9_0_2); movsd(xmm0, Address(tmp, 1208)); // 0xffffffffUL, 0x7fefffffUL mulsd(xmm0, xmm0); movl(edx, 14);
diff --git a/src/hotspot/cpu/x86/nativeInst_x86.cpp b/src/hotspot/cpu/x86/nativeInst_x86.cpp index 0d14c3b..989d870 100644 --- a/src/hotspot/cpu/x86/nativeInst_x86.cpp +++ b/src/hotspot/cpu/x86/nativeInst_x86.cpp
@@ -409,60 +409,7 @@ return off; } -address NativeMovRegMem::instruction_address() const { - return addr_at(instruction_start()); -} - -address NativeMovRegMem::next_instruction_address() const { - address ret = instruction_address() + instruction_size; - u_char instr_0 = *(u_char*) instruction_address(); - switch (instr_0) { - case instruction_operandsize_prefix: - - fatal("should have skipped instruction_operandsize_prefix"); - break; - - case instruction_extended_prefix: - fatal("should have skipped instruction_extended_prefix"); - break; - - case instruction_code_mem2reg_movslq: // 0x63 - case instruction_code_mem2reg_movzxb: // 0xB6 - case instruction_code_mem2reg_movsxb: // 0xBE - case instruction_code_mem2reg_movzxw: // 0xB7 - case instruction_code_mem2reg_movsxw: // 0xBF - case instruction_code_reg2mem: // 0x89 (q/l) - case instruction_code_mem2reg: // 0x8B (q/l) - case instruction_code_reg2memb: // 0x88 - case instruction_code_mem2regb: // 0x8a - - case instruction_code_lea: // 0x8d - - case instruction_code_float_s: // 0xd9 fld_s a - case instruction_code_float_d: // 0xdd fld_d a - - case instruction_code_xmm_load: // 0x10 - case instruction_code_xmm_store: // 0x11 - case instruction_code_xmm_lpd: // 0x12 - { - // If there is an SIB then instruction is longer than expected - u_char mod_rm = *(u_char*)(instruction_address() + 1); - if ((mod_rm & 7) == 0x4) { - ret++; - } - } - case instruction_code_xor: - fatal("should have skipped xor lead in"); - break; - - default: - fatal("not a NativeMovRegMem"); - } - return ret; - -} - -int NativeMovRegMem::offset() const{ +int NativeMovRegMem::patch_offset() const { int off = data_offset + instruction_start(); u_char mod_rm = *(u_char*)(instruction_address() + 1); // nnnn(r12|rsp) isn't coded as simple mod/rm since that is @@ -471,19 +418,7 @@ if ((mod_rm & 7) == 0x4) { off++; } - return int_at(off); -} - -void NativeMovRegMem::set_offset(int x) { - int off = data_offset + instruction_start(); - u_char mod_rm = *(u_char*)(instruction_address() + 1); - // nnnn(r12|rsp) isn't coded as simple mod/rm since that is - // the encoding to use an SIB byte. Which will have the nnnn - // field off by one byte - if ((mod_rm & 7) == 0x4) { - off++; - } - set_int_at(off, x); + return off; } void NativeMovRegMem::verify() {
diff --git a/src/hotspot/cpu/x86/nativeInst_x86.hpp b/src/hotspot/cpu/x86/nativeInst_x86.hpp index 80052fe..69ce9a9 100644 --- a/src/hotspot/cpu/x86/nativeInst_x86.hpp +++ b/src/hotspot/cpu/x86/nativeInst_x86.hpp
@@ -360,7 +360,6 @@ instruction_VEX_prefix_3bytes = Assembler::VEX_3bytes, instruction_EVEX_prefix_4bytes = Assembler::EVEX_4bytes, - instruction_size = 4, instruction_offset = 0, data_offset = 2, next_instruction_offset = 4 @@ -369,15 +368,26 @@ // helper int instruction_start() const; - address instruction_address() const; + address instruction_address() const { + return addr_at(instruction_start()); + } - address next_instruction_address() const; + int num_bytes_to_end_of_patch() const { + return patch_offset() + sizeof(jint); + } - int offset() const; + int offset() const { + return int_at(patch_offset()); + } - void set_offset(int x); + void set_offset(int x) { + set_int_at(patch_offset(), x); + } - void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); } + void add_offset_in_bytes(int add_offset) { + int patch_off = patch_offset(); + set_int_at(patch_off, int_at(patch_off) + add_offset); + } void verify(); void print (); @@ -386,6 +396,7 @@ static void test() {} private: + int patch_offset() const; inline friend NativeMovRegMem* nativeMovRegMem_at (address address); };
diff --git a/src/hotspot/cpu/x86/sharedRuntime_x86_32.cpp b/src/hotspot/cpu/x86/sharedRuntime_x86_32.cpp index 65c1839..20b2ff1 100644 --- a/src/hotspot/cpu/x86/sharedRuntime_x86_32.cpp +++ b/src/hotspot/cpu/x86/sharedRuntime_x86_32.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -37,7 +37,9 @@ #include "runtime/safepointMechanism.hpp" #include "runtime/sharedRuntime.hpp" #include "runtime/vframeArray.hpp" +#include "runtime/vm_version.hpp" #include "utilities/align.hpp" +#include "utilities/macros.hpp" #include "vmreg_x86.inline.hpp" #ifdef COMPILER1 #include "c1/c1_Runtime1.hpp" @@ -45,7 +47,10 @@ #ifdef COMPILER2 #include "opto/runtime.hpp" #endif -#include "vm_version_x86.hpp" +#if INCLUDE_SHENANDOAHGC +#include "gc/shenandoah/shenandoahBarrierSet.hpp" +#include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" +#endif #define __ masm-> @@ -310,18 +315,19 @@ } if (restore_vectors) { + off = additional_frame_bytes - ymm_bytes; + // Restore upper half of YMM registers. + for (int n = 0; n < num_xmm_regs; n++) { + __ vinsertf128_high(as_XMMRegister(n), Address(rsp, n*16+off)); + } + if (UseAVX > 2) { // Restore upper half of ZMM registers. for (int n = 0; n < num_xmm_regs; n++) { __ vinsertf64x4_high(as_XMMRegister(n), Address(rsp, n*32)); } - __ addptr(rsp, zmm_bytes); } - // Restore upper half of YMM registers. - for (int n = 0; n < num_xmm_regs; n++) { - __ vinsertf128_high(as_XMMRegister(n), Address(rsp, n*16)); - } - __ addptr(rsp, ymm_bytes); + __ addptr(rsp, additional_frame_bytes); } __ pop_FPU_state(); @@ -1524,7 +1530,8 @@ int compile_id, BasicType* in_sig_bt, VMRegPair* in_regs, - BasicType ret_type) { + BasicType ret_type, + address critical_entry) { if (method->is_method_handle_intrinsic()) { vmIntrinsics::ID iid = method->intrinsic_id(); intptr_t start = (intptr_t)__ pc(); @@ -1547,7 +1554,7 @@ (OopMapSet*)NULL); } bool is_critical_native = true; - address native_func = method->critical_native_function(); + address native_func = critical_entry; if (native_func == NULL) { native_func = method->native_function(); is_critical_native = false; @@ -1837,7 +1844,7 @@ __ get_thread(thread); - if (is_critical_native) { + if (is_critical_native SHENANDOAHGC_ONLY(&& !UseShenandoahGC)) { check_needs_gc_for_critical_native(masm, thread, stack_slots, total_c_args, total_in_args, oop_handle_offset, oop_maps, in_regs, in_sig_bt); } @@ -1875,6 +1882,12 @@ // OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); +#if INCLUDE_SHENANDOAHGC + // Inbound arguments that need to be pinned for critical natives + GrowableArray<int> pinned_args(total_in_args); + // Current stack slot for storing register based array argument + int pinned_slot = oop_handle_offset; +#endif // Mark location of rbp, // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, rbp->as_VMReg()); @@ -1886,7 +1899,31 @@ switch (in_sig_bt[i]) { case T_ARRAY: if (is_critical_native) { +#if INCLUDE_SHENANDOAHGC + VMRegPair in_arg = in_regs[i]; + if (UseShenandoahGC) { + // gen_pin_object handles save and restore + // of any clobbered registers + ShenandoahBarrierSet::assembler()->gen_pin_object(masm, thread, in_arg); + pinned_args.append(i); + + // rax has pinned array + VMRegPair result_reg(rax->as_VMReg()); + if (!in_arg.first()->is_stack()) { + assert(pinned_slot <= stack_slots, "overflow"); + simple_move32(masm, result_reg, VMRegImpl::stack2reg(pinned_slot)); + pinned_slot += VMRegImpl::slots_per_word; + } else { + // Write back pinned value, it will be used to unpin this argument + __ movptr(Address(rbp, reg2offset_in(in_arg.first())), result_reg.first()->as_Register()); + } + // We have the array in register, use it + in_arg = result_reg; + } + unpack_array_argument(masm, in_arg, in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]); +#else unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]); +#endif c_arg++; break; } @@ -2082,6 +2119,29 @@ default : ShouldNotReachHere(); } +#if INCLUDE_SHENANDOAHGC + if (UseShenandoahGC) { + // unpin pinned arguments + pinned_slot = oop_handle_offset; + if (pinned_args.length() > 0) { + // save return value that may be overwritten otherwise. + save_native_result(masm, ret_type, stack_slots); + for (int index = 0; index < pinned_args.length(); index ++) { + int i = pinned_args.at(index); + assert(pinned_slot <= stack_slots, "overflow"); + if (!in_regs[i].first()->is_stack()) { + int offset = pinned_slot * VMRegImpl::stack_slot_size; + __ movl(in_regs[i].first()->as_Register(), Address(rsp, offset)); + pinned_slot += VMRegImpl::slots_per_word; + } + // gen_pin_object handles save and restore + // of any other clobbered registers + ShenandoahBarrierSet::assembler()->gen_unpin_object(masm, thread, in_regs[i]); + } + restore_native_result(masm, ret_type, stack_slots); + } + } +#endif // Switch thread to "native transition" state before reading the synchronization state. // This additional state is necessary because reading and testing the synchronization // state is not atomic w.r.t. GC, as this scenario demonstrates:
diff --git a/src/hotspot/cpu/x86/sharedRuntime_x86_64.cpp b/src/hotspot/cpu/x86/sharedRuntime_x86_64.cpp index 1869b43..b08b486 100644 --- a/src/hotspot/cpu/x86/sharedRuntime_x86_64.cpp +++ b/src/hotspot/cpu/x86/sharedRuntime_x86_64.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -40,9 +40,10 @@ #include "runtime/safepointMechanism.hpp" #include "runtime/sharedRuntime.hpp" #include "runtime/vframeArray.hpp" +#include "runtime/vm_version.hpp" #include "utilities/align.hpp" #include "utilities/formatBuffer.hpp" -#include "vm_version_x86.hpp" +#include "utilities/macros.hpp" #include "vmreg_x86.inline.hpp" #ifdef COMPILER1 #include "c1/c1_Runtime1.hpp" @@ -53,6 +54,10 @@ #if INCLUDE_JVMCI #include "jvmci/jvmciJavaClasses.hpp" #endif +#if INCLUDE_SHENANDOAHGC +#include "gc/shenandoah/shenandoahBarrierSet.hpp" +#include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" +#endif #define __ masm-> @@ -83,9 +88,10 @@ #define XSAVE_AREA_YMM_BEGIN 576 #define XSAVE_AREA_ZMM_BEGIN 1152 #define XSAVE_AREA_UPPERBANK 1664 -#define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off -#define DEF_YMM_OFFS(regnum) ymm ## regnum ## _off = ymm_off + (regnum)*16/BytesPerInt, ymm ## regnum ## H_off -#define DEF_ZMM_OFFS(regnum) zmm ## regnum ## _off = zmm_off + (regnum-16)*64/BytesPerInt, zmm ## regnum ## H_off +#define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off +#define DEF_YMM_OFFS(regnum) ymm ## regnum ## _off = ymm_off + (regnum)*16/BytesPerInt, ymm ## regnum ## H_off +#define DEF_ZMM_OFFS(regnum) zmm ## regnum ## _off = zmm_off + (regnum)*32/BytesPerInt, zmm ## regnum ## H_off +#define DEF_ZMM_UPPER_OFFS(regnum) zmm ## regnum ## _off = zmm_upper_off + (regnum-16)*64/BytesPerInt, zmm ## regnum ## H_off enum layout { fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area xmm_off = fpu_state_off + XSAVE_AREA_BEGIN/BytesPerInt, // offset in fxsave save area @@ -96,10 +102,12 @@ DEF_YMM_OFFS(0), DEF_YMM_OFFS(1), // 2..15 are implied in range usage - zmm_high = xmm_off + (XSAVE_AREA_ZMM_BEGIN - XSAVE_AREA_BEGIN)/BytesPerInt, - zmm_off = xmm_off + (XSAVE_AREA_UPPERBANK - XSAVE_AREA_BEGIN)/BytesPerInt, - DEF_ZMM_OFFS(16), - DEF_ZMM_OFFS(17), + zmm_off = xmm_off + (XSAVE_AREA_ZMM_BEGIN - XSAVE_AREA_BEGIN)/BytesPerInt, + DEF_ZMM_OFFS(0), + DEF_ZMM_OFFS(1), + zmm_upper_off = xmm_off + (XSAVE_AREA_UPPERBANK - XSAVE_AREA_BEGIN)/BytesPerInt, + DEF_ZMM_UPPER_OFFS(16), + DEF_ZMM_UPPER_OFFS(17), // 18..31 are implied in range usage fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt), fpu_stateH_end, @@ -131,7 +139,7 @@ }; public: - static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors = false); + static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors); static void restore_live_registers(MacroAssembler* masm, bool restore_vectors = false); // Offsets into the register save area @@ -156,12 +164,12 @@ num_xmm_regs = num_xmm_regs/2; } #if COMPILER2_OR_JVMCI - if (save_vectors) { - assert(UseAVX > 0, "Vectors larger than 16 byte long are supported only with AVX"); - assert(MaxVectorSize <= 64, "Only up to 64 byte long vectors are supported"); + if (save_vectors && UseAVX == 0) { + save_vectors = false; // vectors larger than 16 byte long are supported only with AVX } + assert(!save_vectors || MaxVectorSize <= 64, "Only up to 64 byte long vectors are supported"); #else - assert(!save_vectors, "vectors are generated only by C2 and JVMCI"); + save_vectors = false; // vectors are generated only by C2 and JVMCI #endif // Always make the frame size 16-byte aligned, both vector and non vector stacks are always allocated @@ -253,7 +261,7 @@ map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg()); off += delta; } - if(UseAVX > 2) { + if (UseAVX > 2) { // Obtain xmm16..xmm31 from the XSAVE area on EVEX enabled targets off = zmm16_off; delta = zmm17_off - off; @@ -266,13 +274,24 @@ #if COMPILER2_OR_JVMCI if (save_vectors) { + // Save upper half of YMM registers(0..15) off = ymm0_off; - int delta = ymm1_off - off; + delta = ymm1_off - ymm0_off; for (int n = 0; n < 16; n++) { XMMRegister ymm_name = as_XMMRegister(n); map->set_callee_saved(STACK_OFFSET(off), ymm_name->as_VMReg()->next(4)); off += delta; } + if (VM_Version::supports_evex()) { + // Save upper half of ZMM registers(0..15) + off = zmm0_off; + delta = zmm1_off - zmm0_off; + for (int n = 0; n < 16; n++) { + XMMRegister zmm_name = as_XMMRegister(n); + map->set_callee_saved(STACK_OFFSET(off), zmm_name->as_VMReg()->next(8)); + off += delta; + } + } } #endif // COMPILER2_OR_JVMCI @@ -1836,7 +1855,8 @@ int compile_id, BasicType* in_sig_bt, VMRegPair* in_regs, - BasicType ret_type) { + BasicType ret_type, + address critical_entry) { if (method->is_method_handle_intrinsic()) { vmIntrinsics::ID iid = method->intrinsic_id(); intptr_t start = (intptr_t)__ pc(); @@ -1859,7 +1879,7 @@ (OopMapSet*)NULL); } bool is_critical_native = true; - address native_func = method->critical_native_function(); + address native_func = critical_entry; if (native_func == NULL) { native_func = method->native_function(); is_critical_native = false; @@ -2129,7 +2149,7 @@ const Register oop_handle_reg = r14; - if (is_critical_native) { + if (is_critical_native SHENANDOAHGC_ONLY(&& !UseShenandoahGC)) { check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args, oop_handle_offset, oop_maps, in_regs, in_sig_bt); } @@ -2186,6 +2206,12 @@ // the incoming and outgoing registers are offset upwards and for // critical natives they are offset down. GrowableArray<int> arg_order(2 * total_in_args); +#if INCLUDE_SHENANDOAHGC + // Inbound arguments that need to be pinned for critical natives + GrowableArray<int> pinned_args(total_in_args); + // Current stack slot for storing register based array argument + int pinned_slot = oop_handle_offset; +#endif VMRegPair tmp_vmreg; tmp_vmreg.set2(rbx->as_VMReg()); @@ -2233,6 +2259,14 @@ switch (in_sig_bt[i]) { case T_ARRAY: if (is_critical_native) { +#if INCLUDE_SHENANDOAHGC + // pin before unpack + if (UseShenandoahGC) { + assert(pinned_slot <= stack_slots, "overflow"); + ShenandoahBarrierSet::assembler()->pin_critical_native_array(masm, in_regs[i], pinned_slot); + pinned_args.append(i); + } +#endif unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]); c_arg++; #ifdef ASSERT @@ -2449,6 +2483,22 @@ default : ShouldNotReachHere(); } +#if INCLUDE_SHENANDOAHGC + if (UseShenandoahGC) { + // unpin pinned arguments + pinned_slot = oop_handle_offset; + if (pinned_args.length() > 0) { + // save return value that may be overwritten otherwise. + save_native_result(masm, ret_type, stack_slots); + for (int index = 0; index < pinned_args.length(); index ++) { + int i = pinned_args.at(index); + assert(pinned_slot <= stack_slots, "overflow"); + ShenandoahBarrierSet::assembler()->unpin_critical_native_array(masm, in_regs[i], pinned_slot); + } + restore_native_result(masm, ret_type, stack_slots); + } + } +#endif // Switch thread to "native transition" state before reading the synchronization state. // This additional state is necessary because reading and testing the synchronization // state is not atomic w.r.t. GC, as this scenario demonstrates: @@ -2763,12 +2813,15 @@ ResourceMark rm; // Setup code generation tools int pad = 0; + if (UseAVX > 2) { + pad += 1024; + } #if INCLUDE_JVMCI if (EnableJVMCI || UseAOT) { pad += 512; // Increase the buffer size when compiling for JVMCI } #endif - CodeBuffer buffer("deopt_blob", 2048+pad, 1024); + CodeBuffer buffer("deopt_blob", 2560+pad, 1024); MacroAssembler* masm = new MacroAssembler(&buffer); int frame_size_in_words; OopMap* map = NULL; @@ -2810,7 +2863,7 @@ // Prolog for non exception case! // Save everything in sight. - map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); + map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, /*save_vectors*/ true); // Normal deoptimization. Save exec mode for unpack_frames. __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved @@ -2828,7 +2881,7 @@ // return address is the pc describes what bci to do re-execute at // No need to update map as each call to save_live_registers will produce identical oopmap - (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); + (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, /*save_vectors*/ true); __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved __ jmp(cont); @@ -2847,7 +2900,7 @@ uncommon_trap_offset = __ pc() - start; // Save everything in sight. - RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); + RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, /*save_vectors*/ true); // fetch_unroll_info needs to call last_java_frame() __ set_last_Java_frame(noreg, noreg, NULL); @@ -2894,7 +2947,7 @@ __ push(0); // Save everything in sight. - map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); + map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, /*save_vectors*/ true); // Now it is safe to overwrite any register @@ -3491,7 +3544,8 @@ int start = __ offset(); - map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); + // No need to save vector registers since they are caller-saved anyway. + map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, /*save_vectors*/ false); int frame_complete = __ offset(); @@ -3557,14 +3611,11 @@ #ifndef _WINDOWS -#define ASM_SUBTRACT - -#ifdef ASM_SUBTRACT // Subtract 0:b from carry:a. Return carry. -static unsigned long -sub(unsigned long a[], unsigned long b[], unsigned long carry, long len) { - long i = 0, cnt = len; - unsigned long tmp; +static julong +sub(julong a[], julong b[], julong carry, long len) { + long long i = 0, cnt = len; + julong tmp; asm volatile("clc; " "0: ; " "mov (%[b], %[i], 8), %[tmp]; " @@ -3577,24 +3628,6 @@ : "memory"); return tmp; } -#else // ASM_SUBTRACT -typedef int __attribute__((mode(TI))) int128; - -// Subtract 0:b from carry:a. Return carry. -static unsigned long -sub(unsigned long a[], unsigned long b[], unsigned long carry, int len) { - int128 tmp = 0; - int i; - for (i = 0; i < len; i++) { - tmp += a[i]; - tmp -= b[i]; - a[i] = tmp; - tmp >>= 64; - assert(-1 <= tmp && tmp <= 0, "invariant"); - } - return tmp + carry; -} -#endif // ! ASM_SUBTRACT // Multiply (unsigned) Long A by Long B, accumulating the double- // length result into the accumulator formed of T0, T1, and T2. @@ -3617,17 +3650,59 @@ : "r"(A), "a"(B) : "cc"); \ } while(0) +#else //_WINDOWS + +static julong +sub(julong a[], julong b[], julong carry, long len) { + long i; + julong tmp; + unsigned char c = 1; + for (i = 0; i < len; i++) { + c = _addcarry_u64(c, a[i], ~b[i], &tmp); + a[i] = tmp; + } + c = _addcarry_u64(c, carry, ~0, &tmp); + return tmp; +} + +// Multiply (unsigned) Long A by Long B, accumulating the double- +// length result into the accumulator formed of T0, T1, and T2. +#define MACC(A, B, T0, T1, T2) \ +do { \ + julong hi, lo; \ + lo = _umul128(A, B, &hi); \ + unsigned char c = _addcarry_u64(0, lo, T0, &T0); \ + c = _addcarry_u64(c, hi, T1, &T1); \ + _addcarry_u64(c, T2, 0, &T2); \ + } while(0) + +// As above, but add twice the double-length result into the +// accumulator. +#define MACC2(A, B, T0, T1, T2) \ +do { \ + julong hi, lo; \ + lo = _umul128(A, B, &hi); \ + unsigned char c = _addcarry_u64(0, lo, T0, &T0); \ + c = _addcarry_u64(c, hi, T1, &T1); \ + _addcarry_u64(c, T2, 0, &T2); \ + c = _addcarry_u64(0, lo, T0, &T0); \ + c = _addcarry_u64(c, hi, T1, &T1); \ + _addcarry_u64(c, T2, 0, &T2); \ + } while(0) + +#endif //_WINDOWS + // Fast Montgomery multiplication. The derivation of the algorithm is // in A Cryptographic Library for the Motorola DSP56000, // Dusse and Kaliski, Proc. EUROCRYPT 90, pp. 230-237. -static void __attribute__((noinline)) -montgomery_multiply(unsigned long a[], unsigned long b[], unsigned long n[], - unsigned long m[], unsigned long inv, int len) { - unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator +static void NOINLINE +montgomery_multiply(julong a[], julong b[], julong n[], + julong m[], julong inv, int len) { + julong t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator int i; - assert(inv * n[0] == -1UL, "broken inverse in Montgomery multiply"); + assert(inv * n[0] == ULLONG_MAX, "broken inverse in Montgomery multiply"); for (i = 0; i < len; i++) { int j; @@ -3663,13 +3738,13 @@ // multiplication. However, its loop control is more complex and it // may actually run slower on some machines. -static void __attribute__((noinline)) -montgomery_square(unsigned long a[], unsigned long n[], - unsigned long m[], unsigned long inv, int len) { - unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator +static void NOINLINE +montgomery_square(julong a[], julong n[], + julong m[], julong inv, int len) { + julong t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator int i; - assert(inv * n[0] == -1UL, "broken inverse in Montgomery multiply"); + assert(inv * n[0] == ULLONG_MAX, "broken inverse in Montgomery square"); for (i = 0; i < len; i++) { int j; @@ -3715,13 +3790,13 @@ } // Swap words in a longword. -static unsigned long swap(unsigned long x) { +static julong swap(julong x) { return (x << 32) | (x >> 32); } // Copy len longwords from s to d, word-swapping as we go. The // destination array is reversed. -static void reverse_words(unsigned long *s, unsigned long *d, int len) { +static void reverse_words(julong *s, julong *d, int len) { d += len; while(len-- > 0) { d--; @@ -3743,24 +3818,24 @@ // Make very sure we don't use so much space that the stack might // overflow. 512 jints corresponds to an 16384-bit integer and // will use here a total of 8k bytes of stack space. - int total_allocation = longwords * sizeof (unsigned long) * 4; + int total_allocation = longwords * sizeof (julong) * 4; guarantee(total_allocation <= 8192, "must be"); - unsigned long *scratch = (unsigned long *)alloca(total_allocation); + julong *scratch = (julong *)alloca(total_allocation); // Local scratch arrays - unsigned long + julong *a = scratch + 0 * longwords, *b = scratch + 1 * longwords, *n = scratch + 2 * longwords, *m = scratch + 3 * longwords; - reverse_words((unsigned long *)a_ints, a, longwords); - reverse_words((unsigned long *)b_ints, b, longwords); - reverse_words((unsigned long *)n_ints, n, longwords); + reverse_words((julong *)a_ints, a, longwords); + reverse_words((julong *)b_ints, b, longwords); + reverse_words((julong *)n_ints, n, longwords); - ::montgomery_multiply(a, b, n, m, (unsigned long)inv, longwords); + ::montgomery_multiply(a, b, n, m, (julong)inv, longwords); - reverse_words(m, (unsigned long *)m_ints, longwords); + reverse_words(m, (julong *)m_ints, longwords); } void SharedRuntime::montgomery_square(jint *a_ints, jint *n_ints, @@ -3772,30 +3847,28 @@ // Make very sure we don't use so much space that the stack might // overflow. 512 jints corresponds to an 16384-bit integer and // will use here a total of 6k bytes of stack space. - int total_allocation = longwords * sizeof (unsigned long) * 3; + int total_allocation = longwords * sizeof (julong) * 3; guarantee(total_allocation <= 8192, "must be"); - unsigned long *scratch = (unsigned long *)alloca(total_allocation); + julong *scratch = (julong *)alloca(total_allocation); // Local scratch arrays - unsigned long + julong *a = scratch + 0 * longwords, *n = scratch + 1 * longwords, *m = scratch + 2 * longwords; - reverse_words((unsigned long *)a_ints, a, longwords); - reverse_words((unsigned long *)n_ints, n, longwords); + reverse_words((julong *)a_ints, a, longwords); + reverse_words((julong *)n_ints, n, longwords); if (len >= MONTGOMERY_SQUARING_THRESHOLD) { - ::montgomery_square(a, n, m, (unsigned long)inv, longwords); + ::montgomery_square(a, n, m, (julong)inv, longwords); } else { - ::montgomery_multiply(a, a, n, m, (unsigned long)inv, longwords); + ::montgomery_multiply(a, a, n, m, (julong)inv, longwords); } - reverse_words(m, (unsigned long *)m_ints, longwords); + reverse_words(m, (julong *)m_ints, longwords); } -#endif // WINDOWS - #ifdef COMPILER2 // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame //
diff --git a/src/hotspot/cpu/x86/stubGenerator_x86_32.cpp b/src/hotspot/cpu/x86/stubGenerator_x86_32.cpp index 1ef2683..e821dae 100644 --- a/src/hotspot/cpu/x86/stubGenerator_x86_32.cpp +++ b/src/hotspot/cpu/x86/stubGenerator_x86_32.cpp
@@ -602,7 +602,59 @@ return start; } + //--------------------------------------------------------------------------------------------------- + address generate_vector_mask(const char *stub_name, int32_t mask) { + __ align(CodeEntryAlignment); + StubCodeMark mark(this, "StubRoutines", stub_name); + address start = __ pc(); + + for (int i = 0; i < 16; i++) { + __ emit_data(mask, relocInfo::none, 0); + } + + return start; + } + + address generate_vector_mask_long_double(const char *stub_name, int32_t maskhi, int32_t masklo) { + __ align(CodeEntryAlignment); + StubCodeMark mark(this, "StubRoutines", stub_name); + address start = __ pc(); + + for (int i = 0; i < 8; i++) { + __ emit_data(masklo, relocInfo::none, 0); + __ emit_data(maskhi, relocInfo::none, 0); + } + + return start; + } + + //---------------------------------------------------------------------------------------------------- + + address generate_vector_byte_perm_mask(const char *stub_name) { + __ align(CodeEntryAlignment); + StubCodeMark mark(this, "StubRoutines", stub_name); + address start = __ pc(); + + __ emit_data(0x00000001, relocInfo::none, 0); + __ emit_data(0x00000000, relocInfo::none, 0); + __ emit_data(0x00000003, relocInfo::none, 0); + __ emit_data(0x00000000, relocInfo::none, 0); + __ emit_data(0x00000005, relocInfo::none, 0); + __ emit_data(0x00000000, relocInfo::none, 0); + __ emit_data(0x00000007, relocInfo::none, 0); + __ emit_data(0x00000000, relocInfo::none, 0); + __ emit_data(0x00000000, relocInfo::none, 0); + __ emit_data(0x00000000, relocInfo::none, 0); + __ emit_data(0x00000002, relocInfo::none, 0); + __ emit_data(0x00000000, relocInfo::none, 0); + __ emit_data(0x00000004, relocInfo::none, 0); + __ emit_data(0x00000000, relocInfo::none, 0); + __ emit_data(0x00000006, relocInfo::none, 0); + __ emit_data(0x00000000, relocInfo::none, 0); + + return start; + } //---------------------------------------------------------------------------------------------------- // Non-destructive plausibility checks for oops @@ -3825,6 +3877,14 @@ //------------------------------------------------------------------------------------------------------------------------ // entry points that are platform specific + StubRoutines::x86::_vector_float_sign_mask = generate_vector_mask("vector_float_sign_mask", 0x7FFFFFFF); + StubRoutines::x86::_vector_float_sign_flip = generate_vector_mask("vector_float_sign_flip", 0x80000000); + StubRoutines::x86::_vector_double_sign_mask = generate_vector_mask_long_double("vector_double_sign_mask", 0x7FFFFFFF, 0xFFFFFFFF); + StubRoutines::x86::_vector_double_sign_flip = generate_vector_mask_long_double("vector_double_sign_flip", 0x80000000, 0x00000000); + StubRoutines::x86::_vector_short_to_byte_mask = generate_vector_mask("vector_short_to_byte_mask", 0x00ff00ff); + StubRoutines::x86::_vector_byte_perm_mask = generate_vector_byte_perm_mask("vector_byte_perm_mask"); + StubRoutines::x86::_vector_long_sign_mask = generate_vector_mask_long_double("vector_long_sign_mask", 0x80000000, 0x00000000); + // support for verify_oop (must happen after universe_init) StubRoutines::_verify_oop_subroutine_entry = generate_verify_oop();
diff --git a/src/hotspot/cpu/x86/stubGenerator_x86_64.cpp b/src/hotspot/cpu/x86/stubGenerator_x86_64.cpp index 07a5cde..87cd499 100644 --- a/src/hotspot/cpu/x86/stubGenerator_x86_64.cpp +++ b/src/hotspot/cpu/x86/stubGenerator_x86_64.cpp
@@ -978,6 +978,40 @@ return start; } + address generate_vector_mask(const char *stub_name, int64_t mask) { + __ align(CodeEntryAlignment); + StubCodeMark mark(this, "StubRoutines", stub_name); + address start = __ pc(); + + __ emit_data64(mask, relocInfo::none); + __ emit_data64(mask, relocInfo::none); + __ emit_data64(mask, relocInfo::none); + __ emit_data64(mask, relocInfo::none); + __ emit_data64(mask, relocInfo::none); + __ emit_data64(mask, relocInfo::none); + __ emit_data64(mask, relocInfo::none); + __ emit_data64(mask, relocInfo::none); + + return start; + } + + address generate_vector_byte_perm_mask(const char *stub_name) { + __ align(CodeEntryAlignment); + StubCodeMark mark(this, "StubRoutines", stub_name); + address start = __ pc(); + + __ emit_data64(0x0000000000000001, relocInfo::none); + __ emit_data64(0x0000000000000003, relocInfo::none); + __ emit_data64(0x0000000000000005, relocInfo::none); + __ emit_data64(0x0000000000000007, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000002, relocInfo::none); + __ emit_data64(0x0000000000000004, relocInfo::none); + __ emit_data64(0x0000000000000006, relocInfo::none); + + return start; + } + // Non-destructive plausibility checks for oops // // Arguments: @@ -1219,30 +1253,58 @@ if (UseUnalignedLoadStores) { Label L_end; // Copy 64-bytes per iteration - __ BIND(L_loop); if (UseAVX > 2) { + Label L_loop_avx512, L_loop_avx2, L_32_byte_head, L_above_threshold, L_below_threshold; + + __ BIND(L_copy_bytes); + __ cmpptr(qword_count, (-1 * AVX3Threshold / 8)); + __ jccb(Assembler::less, L_above_threshold); + __ jmpb(L_below_threshold); + + __ bind(L_loop_avx512); __ evmovdqul(xmm0, Address(end_from, qword_count, Address::times_8, -56), Assembler::AVX_512bit); __ evmovdqul(Address(end_to, qword_count, Address::times_8, -56), xmm0, Assembler::AVX_512bit); - } else if (UseAVX == 2) { + __ bind(L_above_threshold); + __ addptr(qword_count, 8); + __ jcc(Assembler::lessEqual, L_loop_avx512); + __ jmpb(L_32_byte_head); + + __ bind(L_loop_avx2); __ vmovdqu(xmm0, Address(end_from, qword_count, Address::times_8, -56)); __ vmovdqu(Address(end_to, qword_count, Address::times_8, -56), xmm0); __ vmovdqu(xmm1, Address(end_from, qword_count, Address::times_8, -24)); __ vmovdqu(Address(end_to, qword_count, Address::times_8, -24), xmm1); + __ bind(L_below_threshold); + __ addptr(qword_count, 8); + __ jcc(Assembler::lessEqual, L_loop_avx2); + + __ bind(L_32_byte_head); + __ subptr(qword_count, 4); // sub(8) and add(4) + __ jccb(Assembler::greater, L_end); } else { - __ movdqu(xmm0, Address(end_from, qword_count, Address::times_8, -56)); - __ movdqu(Address(end_to, qword_count, Address::times_8, -56), xmm0); - __ movdqu(xmm1, Address(end_from, qword_count, Address::times_8, -40)); - __ movdqu(Address(end_to, qword_count, Address::times_8, -40), xmm1); - __ movdqu(xmm2, Address(end_from, qword_count, Address::times_8, -24)); - __ movdqu(Address(end_to, qword_count, Address::times_8, -24), xmm2); - __ movdqu(xmm3, Address(end_from, qword_count, Address::times_8, - 8)); - __ movdqu(Address(end_to, qword_count, Address::times_8, - 8), xmm3); + __ BIND(L_loop); + if (UseAVX == 2) { + __ vmovdqu(xmm0, Address(end_from, qword_count, Address::times_8, -56)); + __ vmovdqu(Address(end_to, qword_count, Address::times_8, -56), xmm0); + __ vmovdqu(xmm1, Address(end_from, qword_count, Address::times_8, -24)); + __ vmovdqu(Address(end_to, qword_count, Address::times_8, -24), xmm1); + } else { + __ movdqu(xmm0, Address(end_from, qword_count, Address::times_8, -56)); + __ movdqu(Address(end_to, qword_count, Address::times_8, -56), xmm0); + __ movdqu(xmm1, Address(end_from, qword_count, Address::times_8, -40)); + __ movdqu(Address(end_to, qword_count, Address::times_8, -40), xmm1); + __ movdqu(xmm2, Address(end_from, qword_count, Address::times_8, -24)); + __ movdqu(Address(end_to, qword_count, Address::times_8, -24), xmm2); + __ movdqu(xmm3, Address(end_from, qword_count, Address::times_8, - 8)); + __ movdqu(Address(end_to, qword_count, Address::times_8, - 8), xmm3); + } + + __ BIND(L_copy_bytes); + __ addptr(qword_count, 8); + __ jcc(Assembler::lessEqual, L_loop); + __ subptr(qword_count, 4); // sub(8) and add(4) + __ jccb(Assembler::greater, L_end); } - __ BIND(L_copy_bytes); - __ addptr(qword_count, 8); - __ jcc(Assembler::lessEqual, L_loop); - __ subptr(qword_count, 4); // sub(8) and add(4) - __ jccb(Assembler::greater, L_end); // Copy trailing 32 bytes if (UseAVX >= 2) { __ vmovdqu(xmm0, Address(end_from, qword_count, Address::times_8, -24)); @@ -1299,31 +1361,59 @@ if (UseUnalignedLoadStores) { Label L_end; // Copy 64-bytes per iteration - __ BIND(L_loop); if (UseAVX > 2) { + Label L_loop_avx512, L_loop_avx2, L_32_byte_head, L_above_threshold, L_below_threshold; + + __ BIND(L_copy_bytes); + __ cmpptr(qword_count, (AVX3Threshold / 8)); + __ jccb(Assembler::greater, L_above_threshold); + __ jmpb(L_below_threshold); + + __ BIND(L_loop_avx512); __ evmovdqul(xmm0, Address(from, qword_count, Address::times_8, 0), Assembler::AVX_512bit); __ evmovdqul(Address(dest, qword_count, Address::times_8, 0), xmm0, Assembler::AVX_512bit); - } else if (UseAVX == 2) { + __ bind(L_above_threshold); + __ subptr(qword_count, 8); + __ jcc(Assembler::greaterEqual, L_loop_avx512); + __ jmpb(L_32_byte_head); + + __ bind(L_loop_avx2); __ vmovdqu(xmm0, Address(from, qword_count, Address::times_8, 32)); __ vmovdqu(Address(dest, qword_count, Address::times_8, 32), xmm0); - __ vmovdqu(xmm1, Address(from, qword_count, Address::times_8, 0)); - __ vmovdqu(Address(dest, qword_count, Address::times_8, 0), xmm1); - } else { - __ movdqu(xmm0, Address(from, qword_count, Address::times_8, 48)); - __ movdqu(Address(dest, qword_count, Address::times_8, 48), xmm0); - __ movdqu(xmm1, Address(from, qword_count, Address::times_8, 32)); - __ movdqu(Address(dest, qword_count, Address::times_8, 32), xmm1); - __ movdqu(xmm2, Address(from, qword_count, Address::times_8, 16)); - __ movdqu(Address(dest, qword_count, Address::times_8, 16), xmm2); - __ movdqu(xmm3, Address(from, qword_count, Address::times_8, 0)); - __ movdqu(Address(dest, qword_count, Address::times_8, 0), xmm3); - } - __ BIND(L_copy_bytes); - __ subptr(qword_count, 8); - __ jcc(Assembler::greaterEqual, L_loop); + __ vmovdqu(xmm1, Address(from, qword_count, Address::times_8, 0)); + __ vmovdqu(Address(dest, qword_count, Address::times_8, 0), xmm1); + __ bind(L_below_threshold); + __ subptr(qword_count, 8); + __ jcc(Assembler::greaterEqual, L_loop_avx2); - __ addptr(qword_count, 4); // add(8) and sub(4) - __ jccb(Assembler::less, L_end); + __ bind(L_32_byte_head); + __ addptr(qword_count, 4); // add(8) and sub(4) + __ jccb(Assembler::less, L_end); + } else { + __ BIND(L_loop); + if (UseAVX == 2) { + __ vmovdqu(xmm0, Address(from, qword_count, Address::times_8, 32)); + __ vmovdqu(Address(dest, qword_count, Address::times_8, 32), xmm0); + __ vmovdqu(xmm1, Address(from, qword_count, Address::times_8, 0)); + __ vmovdqu(Address(dest, qword_count, Address::times_8, 0), xmm1); + } else { + __ movdqu(xmm0, Address(from, qword_count, Address::times_8, 48)); + __ movdqu(Address(dest, qword_count, Address::times_8, 48), xmm0); + __ movdqu(xmm1, Address(from, qword_count, Address::times_8, 32)); + __ movdqu(Address(dest, qword_count, Address::times_8, 32), xmm1); + __ movdqu(xmm2, Address(from, qword_count, Address::times_8, 16)); + __ movdqu(Address(dest, qword_count, Address::times_8, 16), xmm2); + __ movdqu(xmm3, Address(from, qword_count, Address::times_8, 0)); + __ movdqu(Address(dest, qword_count, Address::times_8, 0), xmm3); + } + + __ BIND(L_copy_bytes); + __ subptr(qword_count, 8); + __ jcc(Assembler::greaterEqual, L_loop); + + __ addptr(qword_count, 4); // add(8) and sub(4) + __ jccb(Assembler::less, L_end); + } // Copy trailing 32 bytes if (UseAVX >= 2) { __ vmovdqu(xmm0, Address(from, qword_count, Address::times_8, 0)); @@ -2112,7 +2202,7 @@ // r9 and r10 may be used to save non-volatile registers // 'from', 'to' and 'qword_count' are now valid - DecoratorSet decorators = IN_HEAP | IS_ARRAY | ARRAYCOPY_DISJOINT; + DecoratorSet decorators = IN_HEAP | IS_ARRAY; if (dest_uninitialized) { decorators |= IS_DEST_UNINITIALIZED; } @@ -2295,7 +2385,7 @@ Address from_element_addr(end_from, count, TIMES_OOP, 0); Address to_element_addr(end_to, count, TIMES_OOP, 0); - DecoratorSet decorators = IN_HEAP | IS_ARRAY | ARRAYCOPY_CHECKCAST; + DecoratorSet decorators = IN_HEAP | IS_ARRAY | ARRAYCOPY_CHECKCAST | ARRAYCOPY_DISJOINT; if (dest_uninitialized) { decorators |= IS_DEST_UNINITIALIZED; } @@ -3550,6 +3640,36 @@ return start; } + address generate_electronicCodeBook_encryptAESCrypt() { + __ align(CodeEntryAlignment); + StubCodeMark mark(this, "StubRoutines", "electronicCodeBook_encryptAESCrypt"); + address start = __ pc(); + const Register from = c_rarg0; // source array address + const Register to = c_rarg1; // destination array address + const Register key = c_rarg2; // key array address + const Register len = c_rarg3; // src len (must be multiple of blocksize 16) + __ enter(); // required for proper stackwalking of RuntimeStub frame + __ aesecb_encrypt(from, to, key, len); + __ leave(); // required for proper stackwalking of RuntimeStub frame + __ ret(0); + return start; + } + + address generate_electronicCodeBook_decryptAESCrypt() { + __ align(CodeEntryAlignment); + StubCodeMark mark(this, "StubRoutines", "electronicCodeBook_decryptAESCrypt"); + address start = __ pc(); + const Register from = c_rarg0; // source array address + const Register to = c_rarg1; // destination array address + const Register key = c_rarg2; // key array address + const Register len = c_rarg3; // src len (must be multiple of blocksize 16) + __ enter(); // required for proper stackwalking of RuntimeStub frame + __ aesecb_decrypt(from, to, key, len); + __ leave(); // required for proper stackwalking of RuntimeStub frame + __ ret(0); + return start; + } + address generate_upper_word_mask() { __ align(64); StubCodeMark mark(this, "StubRoutines", "upper_word_mask"); @@ -3725,6 +3845,123 @@ return start; } + // This mask is used for incrementing counter value(linc0, linc4, etc.) + address counter_mask_addr() { + __ align(64); + StubCodeMark mark(this, "StubRoutines", "counter_mask_addr"); + address start = __ pc(); + __ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none);//lbswapmask + __ emit_data64(0x0001020304050607, relocInfo::none); + __ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none); + __ emit_data64(0x0001020304050607, relocInfo::none); + __ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none); + __ emit_data64(0x0001020304050607, relocInfo::none); + __ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none); + __ emit_data64(0x0001020304050607, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none);//linc0 = counter_mask_addr+64 + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000001, relocInfo::none);//counter_mask_addr() + 80 + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000002, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000003, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000004, relocInfo::none);//linc4 = counter_mask_addr() + 128 + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000004, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000004, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000004, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000008, relocInfo::none);//linc8 = counter_mask_addr() + 192 + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000008, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000008, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000008, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000020, relocInfo::none);//linc32 = counter_mask_addr() + 256 + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000020, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000020, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000020, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000010, relocInfo::none);//linc16 = counter_mask_addr() + 320 + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000010, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000010, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + __ emit_data64(0x0000000000000010, relocInfo::none); + __ emit_data64(0x0000000000000000, relocInfo::none); + return start; + } + + // Vector AES Counter implementation + address generate_counterMode_VectorAESCrypt() { + __ align(CodeEntryAlignment); + StubCodeMark mark(this, "StubRoutines", "counterMode_AESCrypt"); + address start = __ pc(); + const Register from = c_rarg0; // source array address + const Register to = c_rarg1; // destination array address + const Register key = c_rarg2; // key array address r8 + const Register counter = c_rarg3; // counter byte array initialized from counter array address + // and updated with the incremented counter in the end +#ifndef _WIN64 + const Register len_reg = c_rarg4; + const Register saved_encCounter_start = c_rarg5; + const Register used_addr = r10; + const Address used_mem(rbp, 2 * wordSize); + const Register used = r11; +#else + const Address len_mem(rbp, 6 * wordSize); // length is on stack on Win64 + const Address saved_encCounter_mem(rbp, 7 * wordSize); // saved encrypted counter is on stack on Win64 + const Address used_mem(rbp, 8 * wordSize); // used length is on stack on Win64 + const Register len_reg = r10; // pick the first volatile windows register + const Register saved_encCounter_start = r11; + const Register used_addr = r13; + const Register used = r14; +#endif + __ enter(); + // Save state before entering routine + __ push(r12); + __ push(r13); + __ push(r14); + __ push(r15); +#ifdef _WIN64 + // on win64, fill len_reg from stack position + __ movl(len_reg, len_mem); + __ movptr(saved_encCounter_start, saved_encCounter_mem); + __ movptr(used_addr, used_mem); + __ movl(used, Address(used_addr, 0)); +#else + __ push(len_reg); // Save + __ movptr(used_addr, used_mem); + __ movl(used, Address(used_addr, 0)); +#endif + __ push(rbx); + __ aesctr_encrypt(from, to, key, counter, len_reg, used, used_addr, saved_encCounter_start); + // Restore state before leaving routine + __ pop(rbx); +#ifdef _WIN64 + __ movl(rax, len_mem); // return length +#else + __ pop(rax); // return length +#endif + __ pop(r15); + __ pop(r14); + __ pop(r13); + __ pop(r12); + + __ leave(); // required for proper stackwalking of RuntimeStub frame + __ ret(0); + return start; + } + // This is a version of CTR/AES crypt which does 6 blocks in a loop at a time // to hide instruction latency // @@ -4339,6 +4576,45 @@ return start; } +// Polynomial x^128+x^127+x^126+x^121+1 +address ghash_polynomial_addr() { + __ align(CodeEntryAlignment); + StubCodeMark mark(this, "StubRoutines", "_ghash_poly_addr"); + address start = __ pc(); + __ emit_data64(0x0000000000000001, relocInfo::none); + __ emit_data64(0xc200000000000000, relocInfo::none); + return start; +} + +address ghash_shufflemask_addr() { + __ align(CodeEntryAlignment); + StubCodeMark mark(this, "StubRoutines", "_ghash_shuffmask_addr"); + address start = __ pc(); + __ emit_data64(0x0f0f0f0f0f0f0f0f, relocInfo::none); + __ emit_data64(0x0f0f0f0f0f0f0f0f, relocInfo::none); + return start; +} + +// Ghash single and multi block operations using AVX instructions +address generate_avx_ghash_processBlocks() { + __ align(CodeEntryAlignment); + + StubCodeMark mark(this, "StubRoutines", "ghash_processBlocks"); + address start = __ pc(); + + // arguments + const Register state = c_rarg0; + const Register htbl = c_rarg1; + const Register data = c_rarg2; + const Register blocks = c_rarg3; + __ enter(); + // Save state before entering routine + __ avx_ghash(state, htbl, data, blocks); + __ leave(); // required for proper stackwalking of RuntimeStub frame + __ ret(0); + return start; +} + // byte swap x86 long address generate_ghash_long_swap_mask() { __ align(CodeEntryAlignment); @@ -4909,13 +5185,20 @@ const Register buf = c_rarg1; // source java byte array address const Register len = c_rarg2; // length const Register table = c_rarg3; // crc_table address (reuse register) - const Register tmp = r11; - assert_different_registers(crc, buf, len, table, tmp, rax); + const Register tmp1 = r11; + const Register tmp2 = r10; + assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax); BLOCK_COMMENT("Entry:"); __ enter(); // required for proper stackwalking of RuntimeStub frame - __ kernel_crc32(crc, buf, len, table, tmp); + if (VM_Version::supports_sse4_1() && VM_Version::supports_avx512_vpclmulqdq() && + VM_Version::supports_avx512bw() && + VM_Version::supports_avx512vl()) { + __ kernel_crc32_avx512(crc, buf, len, table, tmp1, tmp2); + } else { + __ kernel_crc32(crc, buf, len, table, tmp1); + } __ movl(rax, crc); __ vzeroupper(); @@ -5708,6 +5991,13 @@ StubRoutines::x86::_float_sign_flip = generate_fp_mask("float_sign_flip", 0x8000000080000000); StubRoutines::x86::_double_sign_mask = generate_fp_mask("double_sign_mask", 0x7FFFFFFFFFFFFFFF); StubRoutines::x86::_double_sign_flip = generate_fp_mask("double_sign_flip", 0x8000000000000000); + StubRoutines::x86::_vector_float_sign_mask = generate_vector_mask("vector_float_sign_mask", 0x7FFFFFFF7FFFFFFF); + StubRoutines::x86::_vector_float_sign_flip = generate_vector_mask("vector_float_sign_flip", 0x8000000080000000); + StubRoutines::x86::_vector_double_sign_mask = generate_vector_mask("vector_double_sign_mask", 0x7FFFFFFFFFFFFFFF); + StubRoutines::x86::_vector_double_sign_flip = generate_vector_mask("vector_double_sign_flip", 0x8000000000000000); + StubRoutines::x86::_vector_short_to_byte_mask = generate_vector_mask("vector_short_to_byte_mask", 0x00ff00ff00ff00ff); + StubRoutines::x86::_vector_byte_perm_mask = generate_vector_byte_perm_mask("vector_byte_perm_mask"); + StubRoutines::x86::_vector_long_sign_mask = generate_vector_mask("vector_long_sign_mask", 0x8000000000000000); // support for verify_oop (must happen after universe_init) StubRoutines::_verify_oop_subroutine_entry = generate_verify_oop(); @@ -5723,13 +6013,20 @@ StubRoutines::_cipherBlockChaining_encryptAESCrypt = generate_cipherBlockChaining_encryptAESCrypt(); if (VM_Version::supports_vaes() && VM_Version::supports_avx512vl() && VM_Version::supports_avx512dq() ) { StubRoutines::_cipherBlockChaining_decryptAESCrypt = generate_cipherBlockChaining_decryptVectorAESCrypt(); + StubRoutines::_electronicCodeBook_encryptAESCrypt = generate_electronicCodeBook_encryptAESCrypt(); + StubRoutines::_electronicCodeBook_decryptAESCrypt = generate_electronicCodeBook_decryptAESCrypt(); } else { StubRoutines::_cipherBlockChaining_decryptAESCrypt = generate_cipherBlockChaining_decryptAESCrypt_Parallel(); } } - if (UseAESCTRIntrinsics){ - StubRoutines::x86::_counter_shuffle_mask_addr = generate_counter_shuffle_mask(); - StubRoutines::_counterMode_AESCrypt = generate_counterMode_AESCrypt_Parallel(); + if (UseAESCTRIntrinsics) { + if (VM_Version::supports_vaes() && VM_Version::supports_avx512bw() && VM_Version::supports_avx512vl()) { + StubRoutines::x86::_counter_mask_addr = counter_mask_addr(); + StubRoutines::_counterMode_AESCrypt = generate_counterMode_VectorAESCrypt(); + } else { + StubRoutines::x86::_counter_shuffle_mask_addr = generate_counter_shuffle_mask(); + StubRoutines::_counterMode_AESCrypt = generate_counterMode_AESCrypt_Parallel(); + } } if (UseSHA1Intrinsics) { @@ -5760,9 +6057,15 @@ // Generate GHASH intrinsics code if (UseGHASHIntrinsics) { - StubRoutines::x86::_ghash_long_swap_mask_addr = generate_ghash_long_swap_mask(); - StubRoutines::x86::_ghash_byte_swap_mask_addr = generate_ghash_byte_swap_mask(); - StubRoutines::_ghash_processBlocks = generate_ghash_processBlocks(); + StubRoutines::x86::_ghash_long_swap_mask_addr = generate_ghash_long_swap_mask(); + StubRoutines::x86::_ghash_byte_swap_mask_addr = generate_ghash_byte_swap_mask(); + if (VM_Version::supports_avx()) { + StubRoutines::x86::_ghash_shuffmask_addr = ghash_shufflemask_addr(); + StubRoutines::x86::_ghash_poly_addr = ghash_polynomial_addr(); + StubRoutines::_ghash_processBlocks = generate_avx_ghash_processBlocks(); + } else { + StubRoutines::_ghash_processBlocks = generate_ghash_processBlocks(); + } } if (UseBASE64Intrinsics) { @@ -5793,7 +6096,6 @@ if (UseMulAddIntrinsic) { StubRoutines::_mulAdd = generate_mulAdd(); } -#ifndef _WINDOWS if (UseMontgomeryMultiplyIntrinsic) { StubRoutines::_montgomeryMultiply = CAST_FROM_FN_PTR(address, SharedRuntime::montgomery_multiply); @@ -5802,7 +6104,6 @@ StubRoutines::_montgomerySquare = CAST_FROM_FN_PTR(address, SharedRuntime::montgomery_square); } -#endif // WINDOWS #endif // COMPILER2 if (UseVectorizedMismatchIntrinsic) {
diff --git a/src/hotspot/cpu/x86/stubRoutines_x86.cpp b/src/hotspot/cpu/x86/stubRoutines_x86.cpp index 9e375a8..5d93d11 100644 --- a/src/hotspot/cpu/x86/stubRoutines_x86.cpp +++ b/src/hotspot/cpu/x86/stubRoutines_x86.cpp
@@ -38,9 +38,18 @@ address StubRoutines::x86::_counter_shuffle_mask_addr = NULL; address StubRoutines::x86::_ghash_long_swap_mask_addr = NULL; address StubRoutines::x86::_ghash_byte_swap_mask_addr = NULL; +address StubRoutines::x86::_ghash_poly_addr = NULL; +address StubRoutines::x86::_ghash_shuffmask_addr = NULL; address StubRoutines::x86::_upper_word_mask_addr = NULL; address StubRoutines::x86::_shuffle_byte_flip_mask_addr = NULL; address StubRoutines::x86::_k256_adr = NULL; +address StubRoutines::x86::_vector_short_to_byte_mask = NULL; +address StubRoutines::x86::_vector_float_sign_mask = NULL; +address StubRoutines::x86::_vector_float_sign_flip = NULL; +address StubRoutines::x86::_vector_double_sign_mask = NULL; +address StubRoutines::x86::_vector_double_sign_flip = NULL; +address StubRoutines::x86::_vector_byte_perm_mask = NULL; +address StubRoutines::x86::_vector_long_sign_mask = NULL; #ifdef _LP64 address StubRoutines::x86::_k256_W_adr = NULL; address StubRoutines::x86::_k512_W_addr = NULL; @@ -53,7 +62,7 @@ address StubRoutines::x86::_left_shift_mask = NULL; address StubRoutines::x86::_and_mask = NULL; address StubRoutines::x86::_url_charset = NULL; - +address StubRoutines::x86::_counter_mask_addr = NULL; #endif address StubRoutines::x86::_pshuffle_byte_flip_mask_addr = NULL; @@ -175,6 +184,38 @@ 0x2d02ef8dUL }; +#ifdef _LP64 +juint StubRoutines::x86::_crc_table_avx512[] = +{ + 0xe95c1271UL, 0x00000000UL, 0xce3371cbUL, 0x00000000UL, + 0xccaa009eUL, 0x00000000UL, 0x751997d0UL, 0x00000001UL, + 0x4a7fe880UL, 0x00000001UL, 0xe88ef372UL, 0x00000001UL, + 0xccaa009eUL, 0x00000000UL, 0x63cd6124UL, 0x00000001UL, + 0xf7011640UL, 0x00000001UL, 0xdb710640UL, 0x00000001UL, + 0xd7cfc6acUL, 0x00000001UL, 0xea89367eUL, 0x00000001UL, + 0x8cb44e58UL, 0x00000001UL, 0xdf068dc2UL, 0x00000000UL, + 0xae0b5394UL, 0x00000000UL, 0xc7569e54UL, 0x00000001UL, + 0xc6e41596UL, 0x00000001UL, 0x54442bd4UL, 0x00000001UL, + 0x74359406UL, 0x00000001UL, 0x3db1ecdcUL, 0x00000000UL, + 0x5a546366UL, 0x00000001UL, 0xf1da05aaUL, 0x00000000UL, + 0xccaa009eUL, 0x00000000UL, 0x751997d0UL, 0x00000001UL, + 0x00000000UL, 0x00000000UL, 0x00000000UL, 0x00000000UL +}; + +juint StubRoutines::x86::_crc_by128_masks_avx512[] = +{ + 0xffffffffUL, 0xffffffffUL, 0x00000000UL, 0x00000000UL, + 0x00000000UL, 0xffffffffUL, 0xffffffffUL, 0xffffffffUL, + 0x80808080UL, 0x80808080UL, 0x80808080UL, 0x80808080UL +}; + +juint StubRoutines::x86::_shuf_table_crc32_avx512[] = +{ + 0x83828100UL, 0x87868584UL, 0x8b8a8988UL, 0x8f8e8d8cUL, + 0x03020100UL, 0x07060504UL, 0x0b0a0908UL, 0x000e0d0cUL +}; +#endif // _LP64 + #define D 32 #define P 0x82F63B78 // Reflection of Castagnoli (0x11EDC6F41)
diff --git a/src/hotspot/cpu/x86/stubRoutines_x86.hpp b/src/hotspot/cpu/x86/stubRoutines_x86.hpp index 1fa697a..e54fe25 100644 --- a/src/hotspot/cpu/x86/stubRoutines_x86.hpp +++ b/src/hotspot/cpu/x86/stubRoutines_x86.hpp
@@ -33,7 +33,7 @@ enum platform_dependent_constants { code_size1 = 20000 LP64_ONLY(+10000), // simply increase if too small (assembler will crash if too small) - code_size2 = 33800 LP64_ONLY(+10000) // simply increase if too small (assembler will crash if too small) + code_size2 = 35300 LP64_ONLY(+11000) // simply increase if too small (assembler will crash if too small) }; class x86 { @@ -96,6 +96,7 @@ static address double_sign_flip() { return _double_sign_flip; } + #else // !LP64 private: @@ -117,11 +118,18 @@ // masks and table for CRC32 static uint64_t _crc_by128_masks[]; static juint _crc_table[]; +#ifdef _LP64 + static juint _crc_by128_masks_avx512[]; + static juint _crc_table_avx512[]; + static juint _shuf_table_crc32_avx512[]; +#endif // _LP64 // table for CRC32C static juint* _crc32c_table; // swap mask for ghash static address _ghash_long_swap_mask_addr; static address _ghash_byte_swap_mask_addr; + static address _ghash_poly_addr; + static address _ghash_shuffmask_addr; // upper word mask for sha1 static address _upper_word_mask_addr; @@ -131,6 +139,13 @@ //k256 table for sha256 static juint _k256[]; static address _k256_adr; + static address _vector_short_to_byte_mask; + static address _vector_float_sign_mask; + static address _vector_float_sign_flip; + static address _vector_double_sign_mask; + static address _vector_double_sign_flip; + static address _vector_byte_perm_mask; + static address _vector_long_sign_mask; #ifdef _LP64 static juint _k256_W[]; static address _k256_W_adr; @@ -138,6 +153,7 @@ static address _k512_W_addr; // byte flip mask for sha512 static address _pshuffle_byte_flip_mask_addr_sha512; + static address _counter_mask_addr; // Masks for base64 static address _base64_charset; static address _bswap_mask; @@ -197,11 +213,45 @@ static address key_shuffle_mask_addr() { return _key_shuffle_mask_addr; } static address counter_shuffle_mask_addr() { return _counter_shuffle_mask_addr; } static address crc_by128_masks_addr() { return (address)_crc_by128_masks; } +#ifdef _LP64 + static address crc_by128_masks_avx512_addr() { return (address)_crc_by128_masks_avx512; } + static address shuf_table_crc32_avx512_addr() { return (address)_shuf_table_crc32_avx512; } + static address crc_table_avx512_addr() { return (address)_crc_table_avx512; } +#endif // _LP64 static address ghash_long_swap_mask_addr() { return _ghash_long_swap_mask_addr; } static address ghash_byte_swap_mask_addr() { return _ghash_byte_swap_mask_addr; } + static address ghash_shufflemask_addr() { return _ghash_shuffmask_addr; } + static address ghash_polynomial_addr() { return _ghash_poly_addr; } static address upper_word_mask_addr() { return _upper_word_mask_addr; } static address shuffle_byte_flip_mask_addr() { return _shuffle_byte_flip_mask_addr; } static address k256_addr() { return _k256_adr; } + + static address vector_short_to_byte_mask() { + return _vector_short_to_byte_mask; + } + static address vector_float_sign_mask() { + return _vector_float_sign_mask; + } + + static address vector_float_sign_flip() { + return _vector_float_sign_flip; + } + + static address vector_double_sign_mask() { + return _vector_double_sign_mask; + } + + static address vector_double_sign_flip() { + return _vector_double_sign_flip; + } + + static address vector_byte_perm_mask() { + return _vector_byte_perm_mask; + } + + static address vector_long_sign_mask() { + return _vector_long_sign_mask; + } #ifdef _LP64 static address k256_W_addr() { return _k256_W_adr; } static address k512_W_addr() { return _k512_W_addr; } @@ -213,6 +263,7 @@ static address base64_right_shift_mask_addr() { return _right_shift_mask; } static address base64_left_shift_mask_addr() { return _left_shift_mask; } static address base64_and_mask_addr() { return _and_mask; } + static address counter_mask_addr() { return _counter_mask_addr; } #endif static address pshuffle_byte_flip_mask_addr() { return _pshuffle_byte_flip_mask_addr; } static void generate_CRC32C_table(bool is_pclmulqdq_supported);
diff --git a/src/hotspot/cpu/x86/templateTable_x86.cpp b/src/hotspot/cpu/x86/templateTable_x86.cpp index 932fae8..311a54f 100644 --- a/src/hotspot/cpu/x86/templateTable_x86.cpp +++ b/src/hotspot/cpu/x86/templateTable_x86.cpp
@@ -2297,7 +2297,7 @@ __ dispatch_only(vtos, true); if (UseLoopCounter) { - if (ProfileInterpreter) { + if (ProfileInterpreter && !TieredCompilation) { // Out-of-line code to allocate method data oop. __ bind(profile_method); __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::profile_method));
diff --git a/src/hotspot/cpu/x86/vm_version_ext_x86.cpp b/src/hotspot/cpu/x86/vm_version_ext_x86.cpp index 3cc775d..968428d 100644 --- a/src/hotspot/cpu/x86/vm_version_ext_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_ext_x86.cpp
@@ -43,10 +43,10 @@ CPU_FAMILY_PENTIUM_4 = 0xF } FamilyFlag; - typedef enum { - RDTSCP_FLAG = 0x08000000, // bit 27 - INTEL64_FLAG = 0x20000000 // bit 29 - } _featureExtendedEdxFlag; +typedef enum { + RDTSCP_FLAG = 0x08000000, // bit 27 + INTEL64_FLAG = 0x20000000 // bit 29 +} _featureExtendedEdxFlag; #define CPUID_STANDARD_FN 0x0 #define CPUID_STANDARD_FN_1 0x1 @@ -399,13 +399,17 @@ const char* VM_Version_Ext::cpu_family_description(void) { int cpu_family_id = extended_cpu_family(); if (is_amd()) { - return _family_id_amd[cpu_family_id]; + if (cpu_family_id < ExtendedFamilyIdLength_AMD) { + return _family_id_amd[cpu_family_id]; + } } if (is_intel()) { if (cpu_family_id == CPU_FAMILY_PENTIUMPRO) { return cpu_model_description(); } - return _family_id_intel[cpu_family_id]; + if (cpu_family_id < ExtendedFamilyIdLength_INTEL) { + return _family_id_intel[cpu_family_id]; + } } return "Unknown x86"; } @@ -694,7 +698,7 @@ return _max_qualified_cpu_frequency; } -const char* const VM_Version_Ext::_family_id_intel[] = { +const char* const VM_Version_Ext::_family_id_intel[ExtendedFamilyIdLength_INTEL] = { "8086/8088", "", "286", @@ -713,7 +717,7 @@ "Pentium 4" }; -const char* const VM_Version_Ext::_family_id_amd[] = { +const char* const VM_Version_Ext::_family_id_amd[ExtendedFamilyIdLength_AMD] = { "", "", "", @@ -731,6 +735,13 @@ "", "Opteron/Athlon64", "Opteron QC/Phenom" // Barcelona et.al. + "", + "", + "", + "", + "", + "", + "Zen" }; // Partially from Intel 64 and IA-32 Architecture Software Developer's Manual, // September 2013, Vol 3C Table 35-1
diff --git a/src/hotspot/cpu/x86/vm_version_ext_x86.hpp b/src/hotspot/cpu/x86/vm_version_ext_x86.hpp index 78fb001..28d3169 100644 --- a/src/hotspot/cpu/x86/vm_version_ext_x86.hpp +++ b/src/hotspot/cpu/x86/vm_version_ext_x86.hpp
@@ -25,18 +25,24 @@ #ifndef CPU_X86_VM_VM_VERSION_EXT_X86_HPP #define CPU_X86_VM_VM_VERSION_EXT_X86_HPP +#include "runtime/vm_version.hpp" #include "utilities/macros.hpp" -#include "vm_version_x86.hpp" class VM_Version_Ext : public VM_Version { + + enum { + ExtendedFamilyIdLength_INTEL = 16, + ExtendedFamilyIdLength_AMD = 24 + }; + private: static const size_t VENDOR_LENGTH; static const size_t CPU_EBS_MAX_LENGTH; static const size_t CPU_TYPE_DESC_BUF_SIZE; static const size_t CPU_DETAILED_DESC_BUF_SIZE; - static const char* const _family_id_intel[]; - static const char* const _family_id_amd[]; + static const char* const _family_id_intel[ExtendedFamilyIdLength_INTEL]; + static const char* const _family_id_amd[ExtendedFamilyIdLength_AMD]; static const char* const _brand_id[]; static const char* const _model_id_pentium_pro[];
diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index b074fd8..6284bb3 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -32,7 +32,8 @@ #include "runtime/java.hpp" #include "runtime/os.hpp" #include "runtime/stubCodeGenerator.hpp" -#include "vm_version_x86.hpp" +#include "runtime/vm_version.hpp" +#include "utilities/virtualizationSupport.hpp" int VM_Version::_cpu; @@ -46,12 +47,14 @@ address VM_Version::_cpuinfo_cont_addr = 0; static BufferBlob* stub_blob; -static const int stub_size = 1100; +static const int stub_size = 2000; extern "C" { typedef void (*get_cpu_info_stub_t)(void*); + typedef void (*detect_virt_stub_t)(uint32_t, uint32_t*); } static get_cpu_info_stub_t get_cpu_info_stub = NULL; +static detect_virt_stub_t detect_virt_stub = NULL; class VM_Version_StubGenerator: public StubCodeGenerator { @@ -365,22 +368,29 @@ // intx saved_useavx = UseAVX; intx saved_usesse = UseSSE; - // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f - __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); - __ movl(rax, 0x10000); - __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm - __ cmpl(rax, 0x10000); - __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported - // check _cpuid_info.xem_xcr0_eax.bits.opmask - // check _cpuid_info.xem_xcr0_eax.bits.zmm512 - // check _cpuid_info.xem_xcr0_eax.bits.zmm32 - __ movl(rax, 0xE0); - __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm - __ cmpl(rax, 0xE0); - __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported // If UseAVX is unitialized or is set by the user to include EVEX if (use_evex) { + // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f + __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); + __ movl(rax, 0x10000); + __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm + __ cmpl(rax, 0x10000); + __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported + // check _cpuid_info.xem_xcr0_eax.bits.opmask + // check _cpuid_info.xem_xcr0_eax.bits.zmm512 + // check _cpuid_info.xem_xcr0_eax.bits.zmm32 + __ movl(rax, 0xE0); + __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm + __ cmpl(rax, 0xE0); + __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported + + if (FLAG_IS_DEFAULT(UseAVX)) { + __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); + __ movl(rax, Address(rsi, 0)); + __ cmpl(rax, 0x50654); // If it is Skylake + __ jcc(Assembler::equal, legacy_setup); + } // EVEX setup: run in lowest evex mode VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts UseAVX = 3; @@ -449,22 +459,28 @@ VM_Version::set_cpuinfo_cont_addr(__ pc()); // Returns here after signal. Save xmm0 to check it later. - // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f - __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); - __ movl(rax, 0x10000); - __ andl(rax, Address(rsi, 4)); - __ cmpl(rax, 0x10000); - __ jcc(Assembler::notEqual, legacy_save_restore); - // check _cpuid_info.xem_xcr0_eax.bits.opmask - // check _cpuid_info.xem_xcr0_eax.bits.zmm512 - // check _cpuid_info.xem_xcr0_eax.bits.zmm32 - __ movl(rax, 0xE0); - __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm - __ cmpl(rax, 0xE0); - __ jcc(Assembler::notEqual, legacy_save_restore); - // If UseAVX is unitialized or is set by the user to include EVEX if (use_evex) { + // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f + __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); + __ movl(rax, 0x10000); + __ andl(rax, Address(rsi, 4)); + __ cmpl(rax, 0x10000); + __ jcc(Assembler::notEqual, legacy_save_restore); + // check _cpuid_info.xem_xcr0_eax.bits.opmask + // check _cpuid_info.xem_xcr0_eax.bits.zmm512 + // check _cpuid_info.xem_xcr0_eax.bits.zmm32 + __ movl(rax, 0xE0); + __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm + __ cmpl(rax, 0xE0); + __ jcc(Assembler::notEqual, legacy_save_restore); + + if (FLAG_IS_DEFAULT(UseAVX)) { + __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); + __ movl(rax, Address(rsi, 0)); + __ cmpl(rax, 0x50654); // If it is Skylake + __ jcc(Assembler::equal, legacy_save_restore); + } // EVEX check: run in lowest evex mode VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts UseAVX = 3; @@ -548,6 +564,43 @@ __ vzeroupper(); # undef __ } + address generate_detect_virt() { + StubCodeMark mark(this, "VM_Version", "detect_virt_stub"); +# define __ _masm-> + + address start = __ pc(); + + // Evacuate callee-saved registers + __ push(rbp); + __ push(rbx); + __ push(rsi); // for Windows + +#ifdef _LP64 + __ mov(rax, c_rarg0); // CPUID leaf + __ mov(rsi, c_rarg1); // register array address (eax, ebx, ecx, edx) +#else + __ movptr(rax, Address(rsp, 16)); // CPUID leaf + __ movptr(rsi, Address(rsp, 20)); // register array address +#endif + + __ cpuid(); + + // Store result to register array + __ movl(Address(rsi, 0), rax); + __ movl(Address(rsi, 4), rbx); + __ movl(Address(rsi, 8), rcx); + __ movl(Address(rsi, 12), rdx); + + // Epilogue + __ pop(rsi); + __ pop(rbx); + __ pop(rbp); + __ ret(0); + +# undef __ + + return start; + }; }; void VM_Version::get_processor_features() { @@ -647,8 +700,14 @@ } } if (FLAG_IS_DEFAULT(UseAVX)) { - FLAG_SET_DEFAULT(UseAVX, use_avx_limit); - } else if (UseAVX > use_avx_limit) { + // Don't use AVX-512 on older Skylakes unless explicitly requested. + if (use_avx_limit > 2 && is_intel_skylake() && _stepping < 5) { + FLAG_SET_DEFAULT(UseAVX, 2); + } else { + FLAG_SET_DEFAULT(UseAVX, use_avx_limit); + } + } + if (UseAVX > use_avx_limit) { warning("UseAVX=%d is not supported on this CPU, setting it to UseAVX=%d", (int) UseAVX, use_avx_limit); FLAG_SET_DEFAULT(UseAVX, use_avx_limit); } else if (UseAVX < 0) { @@ -663,7 +722,7 @@ _features &= ~CPU_AVX512BW; _features &= ~CPU_AVX512VL; _features &= ~CPU_AVX512_VPOPCNTDQ; - _features &= ~CPU_VPCLMULQDQ; + _features &= ~CPU_AVX512_VPCLMULQDQ; _features &= ~CPU_VAES; } @@ -686,10 +745,12 @@ } } - char buf[256]; - jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", + char buf[512]; + jio_snprintf(buf, sizeof(buf), + "(%u cores per cpu, %u threads per core) family %d model %d stepping %d microcode 0x%x" + "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", cores_per_cpu(), threads_per_core(), - cpu_family(), _model, _stepping, + cpu_family(), _model, _stepping, os::cpu_microcode_revision(), (supports_cmov() ? ", cmov" : ""), (supports_cmpxchg8() ? ", cx8" : ""), (supports_fxsr() ? ", fxsr" : ""), @@ -901,6 +962,13 @@ FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); } + if (!FLAG_IS_DEFAULT(AVX3Threshold)) { + if (!is_power_of_2(AVX3Threshold)) { + warning("AVX3Threshold must be a power of 2"); + FLAG_SET_DEFAULT(AVX3Threshold, 4096); + } + } + #ifdef _LP64 // These are only supported on 64-bit if (UseSHA && supports_avx2() && supports_bmi2()) { @@ -1569,6 +1637,22 @@ #endif // !PRODUCT } +void VM_Version::print_platform_virtualization_info(outputStream* st) { + VirtualizationType vrt = VM_Version::get_detected_virtualization(); + if (vrt == XenHVM) { + st->print_cr("Xen hardware-assisted virtualization detected"); + } else if (vrt == KVM) { + st->print_cr("KVM virtualization detected"); + } else if (vrt == VMWare) { + st->print_cr("VMWare virtualization detected"); + VirtualizationSupport::print_virtualization_info(st); + } else if (vrt == HyperV) { + st->print_cr("Hyper-V virtualization detected"); + } else if (vrt == HyperVRole) { + st->print_cr("Hyper-V role detected"); + } +} + bool VM_Version::use_biased_locking() { #if INCLUDE_RTM_OPT // RTM locking is most useful when there is high lock contention and @@ -1590,18 +1674,74 @@ return UseBiasedLocking; } +// On Xen, the cpuid instruction returns +// eax / registers[0]: Version of Xen +// ebx / registers[1]: chars 'XenV' +// ecx / registers[2]: chars 'MMXe' +// edx / registers[3]: chars 'nVMM' +// +// On KVM / VMWare / MS Hyper-V, the cpuid instruction returns +// ebx / registers[1]: chars 'KVMK' / 'VMwa' / 'Micr' +// ecx / registers[2]: chars 'VMKV' / 'reVM' / 'osof' +// edx / registers[3]: chars 'M' / 'ware' / 't Hv' +// +// more information : +// https://kb.vmware.com/s/article/1009458 +// +void VM_Version::check_virtualizations() { + uint32_t registers[4] = {0}; + char signature[13] = {0}; + + // Xen cpuid leaves can be found 0x100 aligned boundary starting + // from 0x40000000 until 0x40010000. + // https://lists.linuxfoundation.org/pipermail/virtualization/2012-May/019974.html + for (int leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) { + detect_virt_stub(leaf, registers); + memcpy(signature, ®isters[1], 12); + + if (strncmp("VMwareVMware", signature, 12) == 0) { + Abstract_VM_Version::_detected_virtualization = VMWare; + // check for extended metrics from guestlib + VirtualizationSupport::initialize(); + } else if (strncmp("Microsoft Hv", signature, 12) == 0) { + Abstract_VM_Version::_detected_virtualization = HyperV; +#ifdef _WINDOWS + // CPUID leaf 0x40000007 is available to the root partition only. + // See Hypervisor Top Level Functional Specification section 2.4.8 for more details. + // https://github.com/MicrosoftDocs/Virtualization-Documentation/raw/master/tlfs/Hypervisor%20Top%20Level%20Functional%20Specification%20v6.0b.pdf + detect_virt_stub(0x40000007, registers); + if ((registers[0] != 0x0) || + (registers[1] != 0x0) || + (registers[2] != 0x0) || + (registers[3] != 0x0)) { + Abstract_VM_Version::_detected_virtualization = HyperVRole; + } +#endif + } else if (strncmp("KVMKVMKVM", signature, 9) == 0) { + Abstract_VM_Version::_detected_virtualization = KVM; + } else if (strncmp("XenVMMXenVMM", signature, 12) == 0) { + Abstract_VM_Version::_detected_virtualization = XenHVM; + } + } +} + void VM_Version::initialize() { ResourceMark rm; // Making this stub must be FIRST use of assembler - stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size); + stub_blob = BufferBlob::create("VM_Version stub", stub_size); if (stub_blob == NULL) { - vm_exit_during_initialization("Unable to allocate get_cpu_info_stub"); + vm_exit_during_initialization("Unable to allocate stub for VM_Version"); } CodeBuffer c(stub_blob); VM_Version_StubGenerator g(&c); get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t, g.generate_get_cpu_info()); + detect_virt_stub = CAST_TO_FN_PTR(detect_virt_stub_t, + g.generate_detect_virt()); get_processor_features(); + if (VM_Version::supports_hv()) { // Supports hypervisor + check_virtualizations(); + } }
diff --git a/src/hotspot/cpu/x86/vm_version_x86.hpp b/src/hotspot/cpu/x86/vm_version_x86.hpp index e3b986a..d310ff0 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.hpp +++ b/src/hotspot/cpu/x86/vm_version_x86.hpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -25,8 +25,8 @@ #ifndef CPU_X86_VM_VM_VERSION_X86_HPP #define CPU_X86_VM_VM_VERSION_X86_HPP +#include "runtime/abstract_vm_version.hpp" #include "runtime/globals_extension.hpp" -#include "runtime/vm_version.hpp" class VM_Version : public Abstract_VM_Version { friend class VMStructs; @@ -88,7 +88,8 @@ : 1, osxsave : 1, avx : 1, - : 3; + : 2, + hv : 1; } bits; }; @@ -241,7 +242,7 @@ : 1, gfni : 1, vaes : 1, - vpclmulqdq : 1, + avx512_vpclmulqdq : 1, avx512_vnni : 1, avx512_bitalg : 1, : 1, @@ -334,8 +335,9 @@ #define CPU_FMA ((uint64_t)UCONST64(0x800000000)) // FMA instructions #define CPU_VZEROUPPER ((uint64_t)UCONST64(0x1000000000)) // Vzeroupper instruction #define CPU_AVX512_VPOPCNTDQ ((uint64_t)UCONST64(0x2000000000)) // Vector popcount -#define CPU_VPCLMULQDQ ((uint64_t)UCONST64(0x4000000000)) //Vector carryless multiplication +#define CPU_AVX512_VPCLMULQDQ ((uint64_t)UCONST64(0x4000000000)) //Vector carryless multiplication #define CPU_VAES ((uint64_t)UCONST64(0x8000000000)) // Vector AES instructions +#define CPU_HV_PRESENT ((uint64_t)UCONST64(0x400000000000)) // for hypervisor detection enum Extended_Family { // AMD @@ -357,7 +359,7 @@ CPU_MODEL_HASWELL_E3 = 0x3c, CPU_MODEL_HASWELL_E7 = 0x3f, CPU_MODEL_BROADWELL = 0x3d, - CPU_MODEL_SKYLAKE = CPU_MODEL_HASWELL_E3 + CPU_MODEL_SKYLAKE = 0x55 }; // cpuid information block. All info derived from executing cpuid with @@ -544,12 +546,14 @@ result |= CPU_AVX512VL; if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpopcntdq != 0) result |= CPU_AVX512_VPOPCNTDQ; - if (_cpuid_info.sef_cpuid7_ecx.bits.vpclmulqdq != 0) - result |= CPU_VPCLMULQDQ; + if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpclmulqdq != 0) + result |= CPU_AVX512_VPCLMULQDQ; if (_cpuid_info.sef_cpuid7_ecx.bits.vaes != 0) result |= CPU_VAES; } } + if (_cpuid_info.std_cpuid1_ecx.bits.hv != 0) + result |= CPU_HV_PRESENT; if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) result |= CPU_BMI1; if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) @@ -685,6 +689,9 @@ static void initialize(); // Override Abstract_VM_Version implementation + static void print_platform_virtualization_info(outputStream*); + + // Override Abstract_VM_Version implementation static bool use_biased_locking(); // Asserts @@ -828,13 +835,17 @@ static bool supports_fma() { return (_features & CPU_FMA) != 0 && supports_avx(); } static bool supports_vzeroupper() { return (_features & CPU_VZEROUPPER) != 0; } static bool supports_vpopcntdq() { return (_features & CPU_AVX512_VPOPCNTDQ) != 0; } - static bool supports_vpclmulqdq() { return (_features & CPU_VPCLMULQDQ) != 0; } + static bool supports_avx512_vpclmulqdq() { return (_features & CPU_AVX512_VPCLMULQDQ) != 0; } static bool supports_vaes() { return (_features & CPU_VAES) != 0; } + static bool supports_hv() { return (_features & CPU_HV_PRESENT) != 0; } // Intel features static bool is_intel_family_core() { return is_intel() && extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } + static bool is_intel_skylake() { return is_intel_family_core() && + extended_cpu_model() == CPU_MODEL_SKYLAKE; } + static bool is_intel_tsc_synched_at_init() { if (is_intel_family_core()) { uint32_t ext_model = extended_cpu_model(); @@ -928,6 +939,15 @@ // that can be used for efficient implementation of // the intrinsic for java.lang.Thread.onSpinWait() static bool supports_on_spin_wait() { return supports_sse2(); } + +#ifdef __APPLE__ + // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64) + static bool is_cpu_emulated(); +#endif + + // support functions for virtualization detection + private: + static void check_virtualizations(); }; #endif // CPU_X86_VM_VM_VERSION_X86_HPP
diff --git a/src/hotspot/cpu/x86/vtableStubs_x86_32.cpp b/src/hotspot/cpu/x86/vtableStubs_x86_32.cpp index 3906a12..24e080d 100644 --- a/src/hotspot/cpu/x86/vtableStubs_x86_32.cpp +++ b/src/hotspot/cpu/x86/vtableStubs_x86_32.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -97,7 +97,7 @@ start_pc = __ pc(); // check offset vs vtable length __ cmpl(Address(rax, Klass::vtable_length_offset()), vtable_index*vtableEntry::size()); - slop_delta = 6 - (__ pc() - start_pc); // cmpl varies in length, depending on data + slop_delta = 10 - (__ pc() - start_pc); // cmpl varies in length, depending on data slop_bytes += slop_delta; assert(slop_delta >= 0, "negative slop(%d) encountered, adjust code size estimate!", slop_delta); @@ -106,7 +106,7 @@ // VTABLE TODO: find upper bound for call_VM length. start_pc = __ pc(); __ call_VM(noreg, CAST_FROM_FN_PTR(address, bad_compiled_vtable_index), rcx, rbx); - slop_delta = 480 - (__ pc() - start_pc); + slop_delta = 500 - (__ pc() - start_pc); slop_bytes += slop_delta; assert(slop_delta >= 0, "negative slop(%d) encountered, adjust code size estimate!", slop_delta); __ bind(L);
diff --git a/src/hotspot/cpu/x86/vtableStubs_x86_64.cpp b/src/hotspot/cpu/x86/vtableStubs_x86_64.cpp index 6c518f5..85a9fd5 100644 --- a/src/hotspot/cpu/x86/vtableStubs_x86_64.cpp +++ b/src/hotspot/cpu/x86/vtableStubs_x86_64.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -69,7 +69,7 @@ #if (!defined(PRODUCT) && defined(COMPILER2)) if (CountCompiledCalls) { - __ incrementl(ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr())); + __ incrementq(ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr())); } #endif @@ -97,7 +97,7 @@ // VTABLE TODO: find upper bound for call_VM length. start_pc = __ pc(); __ call_VM(noreg, CAST_FROM_FN_PTR(address, bad_compiled_vtable_index), j_rarg0, rbx); - slop_delta = 480 - (__ pc() - start_pc); + slop_delta = 550 - (__ pc() - start_pc); slop_bytes += slop_delta; assert(slop_delta >= 0, "negative slop(%d) encountered, adjust code size estimate!", slop_delta); __ bind(L); @@ -147,6 +147,7 @@ if (s == NULL) { return NULL; } + // Count unused bytes in instruction sequences of variable size. // We add them to the computed buffer size in order to avoid // overflow in subsequently generated stubs. @@ -162,7 +163,7 @@ #if (!defined(PRODUCT) && defined(COMPILER2)) if (CountCompiledCalls) { - __ incrementl(ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr())); + __ incrementq(ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr())); } #endif // PRODUCT
diff --git a/src/hotspot/cpu/x86/x86.ad b/src/hotspot/cpu/x86/x86.ad index f27bc90..5c595bd 100644 --- a/src/hotspot/cpu/x86/x86.ad +++ b/src/hotspot/cpu/x86/x86.ad
@@ -1,5 +1,5 @@ // -// Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +// Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This code is free software; you can redistribute it and/or modify it @@ -1372,14 +1372,20 @@ static address double_signmask() { return (address)double_signmask_pool; } static address double_signflip() { return (address)double_signflip_pool; } #endif + static address vector_short_to_byte_mask() { return StubRoutines::x86::vector_short_to_byte_mask(); } + static address vector_byte_perm_mask() { return StubRoutines::x86::vector_byte_perm_mask(); } + static address vector_long_sign_mask() { return StubRoutines::x86::vector_long_sign_mask(); } - +//============================================================================= const bool Matcher::match_rule_supported(int opcode) { if (!has_match_rule(opcode)) return false; bool ret_value = true; switch (opcode) { + case Op_AbsVL: + if (UseAVX < 3) + ret_value = false; case Op_PopCountI: case Op_PopCountL: if (!UsePopCountInstruction) @@ -1402,8 +1408,11 @@ if (UseAVX < 3) // only EVEX : vector connectivity becomes an issue here ret_value = false; break; + case Op_AbsVB: + case Op_AbsVS: + case Op_AbsVI: case Op_AddReductionVI: - if (UseSSE < 3) // requires at least SSE3 + if (UseSSE < 3 || !VM_Version::supports_ssse3()) // requires at least SSSE3 ret_value = false; break; case Op_MulReductionVI: @@ -1446,6 +1455,32 @@ if (VM_Version::supports_on_spin_wait() == false) ret_value = false; break; + case Op_RShiftVL: + case Op_AbsVD: + case Op_NegVD: + if (UseSSE < 2) + ret_value = false; + break; + case Op_MulVB: + case Op_LShiftVB: + case Op_RShiftVB: + case Op_URShiftVB: + if (UseSSE < 4) + ret_value = false; + break; +#ifdef _LP64 + case Op_MaxD: + case Op_MaxF: + case Op_MinD: + case Op_MinF: + if (UseAVX < 1) // enabled for AVX only + ret_value = false; + break; +#endif + case Op_RoundDoubleMode: + if (UseSSE < 4) + ret_value = false; + break; } return ret_value; // Per default match rules are supported. @@ -1457,28 +1492,50 @@ bool ret_value = match_rule_supported(opcode); if (ret_value) { switch (opcode) { + case Op_AbsVB: case Op_AddVB: case Op_SubVB: if ((vlen == 64) && (VM_Version::supports_avx512bw() == false)) ret_value = false; break; - case Op_URShiftVS: - case Op_RShiftVS: - case Op_LShiftVS: - case Op_MulVS: + case Op_AbsVS: case Op_AddVS: case Op_SubVS: + case Op_MulVS: + case Op_LShiftVS: + case Op_RShiftVS: + case Op_URShiftVS: if ((vlen == 32) && (VM_Version::supports_avx512bw() == false)) ret_value = false; break; + case Op_MulVB: + case Op_LShiftVB: + case Op_RShiftVB: + case Op_URShiftVB: + if ((vlen == 32 && UseAVX < 2) || + ((vlen == 64) && (VM_Version::supports_avx512bw() == false))) + ret_value = false; + break; + case Op_NegVF: + if ((vlen == 16) && (VM_Version::supports_avx512dq() == false)) + ret_value = false; + break; case Op_CMoveVF: if (vlen != 8) ret_value = false; break; + case Op_NegVD: + if ((vlen == 8) && (VM_Version::supports_avx512dq() == false)) + ret_value = false; + break; case Op_CMoveVD: if (vlen != 4) ret_value = false; break; + case Op_RoundDoubleModeV: + if (VM_Version::supports_avx() == false) + ret_value = false; + break; } } @@ -1581,7 +1638,7 @@ // x86 supports misaligned vectors store/load. const bool Matcher::misaligned_vectors_ok() { - return !AlignVector; // can be changed by flag + return true; } // x86 AES instructions are compatible with SunJCE expanded @@ -1634,6 +1691,7 @@ // Cheap to find it by looking for screwy base. if (adr->is_AddP() && !adr->in(AddPNode::Base)->is_top() && + LP64_ONLY( off->get_long() == (int) (off->get_long()) && ) // immL32 // Are there other uses besides address expressions? !is_visited(adr)) { address_visited.set(adr->_idx); // Flag as address_visited @@ -1680,26 +1738,24 @@ case Op_VecS: // copy whole register case Op_VecD: case Op_VecX: -#ifndef LP64 +#ifndef _LP64 __ movdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo])); #else if ((UseAVX < 3) || VM_Version::supports_avx512vl()) { __ movdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo])); } else { - __ vpxor(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[dst_lo]), 2); - __ vinserti32x4(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]), 0x0); + __ vextractf32x4(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]), 0x0); } #endif break; case Op_VecY: -#ifndef LP64 +#ifndef _LP64 __ vmovdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo])); #else if ((UseAVX < 3) || VM_Version::supports_avx512vl()) { __ vmovdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo])); } else { - __ vpxor(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[dst_lo]), 2); - __ vinserti64x4(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]), 0x0); + __ vextractf64x4(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]), 0x0); } #endif break; @@ -1753,26 +1809,26 @@ __ movq(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); break; case Op_VecX: -#ifndef LP64 +#ifndef _LP64 __ movdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); #else if ((UseAVX < 3) || VM_Version::supports_avx512vl()) { __ movdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); } else { - __ vpxor(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), 2); - __ vinserti32x4(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset),0x0); + __ vpxor(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), 2); + __ vinsertf32x4(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset),0x0); } #endif break; case Op_VecY: -#ifndef LP64 +#ifndef _LP64 __ vmovdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); #else if ((UseAVX < 3) || VM_Version::supports_avx512vl()) { __ vmovdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); } else { - __ vpxor(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), 2); - __ vinserti64x4(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset),0x0); + __ vpxor(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), 2); + __ vinsertf64x4(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset),0x0); } #endif break; @@ -1791,26 +1847,26 @@ __ movq(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); break; case Op_VecX: -#ifndef LP64 +#ifndef _LP64 __ movdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); #else if ((UseAVX < 3) || VM_Version::supports_avx512vl()) { __ movdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); } else { - __ vextracti32x4(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), 0x0); + __ vextractf32x4(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]), 0x0); } #endif break; case Op_VecY: -#ifndef LP64 +#ifndef _LP64 __ vmovdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); #else if ((UseAVX < 3) || VM_Version::supports_avx512vl()) { __ vmovdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); } else { - __ vextracti64x4(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), 0x0); + __ vextractf64x4(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]), 0x0); } #endif break; @@ -2003,7 +2059,7 @@ %} operand legVecZ() %{ - constraint(ALLOC_IN_RC(vectorz_reg_vl)); + constraint(ALLOC_IN_RC(vectorz_reg_legacy)); match(VecZ); format %{ %} @@ -2039,9 +2095,11 @@ instruct ShouldNotReachHere() %{ match(Halt); - format %{ "ud2\t# ShouldNotReachHere" %} + format %{ "stop\t# ShouldNotReachHere" %} ins_encode %{ - __ ud2(); + if (is_reachable()) { + __ stop(_halt_reason); + } %} ins_pipe(pipe_slow); %} @@ -2798,6 +2856,110 @@ ins_pipe(pipe_slow); %} + +#ifdef _LP64 +instruct roundD_reg(legRegD dst, legRegD src, immU8 rmode) %{ + predicate(UseSSE>=4); + match(Set dst (RoundDoubleMode src rmode)); + format %{ "roundsd $dst, $src" %} + ins_cost(150); + ins_encode %{ + __ roundsd($dst$$XMMRegister, $src$$XMMRegister, $rmode$$constant); + %} + ins_pipe(pipe_slow); +%} + +instruct roundD_mem(legRegD dst, memory src, immU8 rmode) %{ + predicate(UseSSE>=4); + match(Set dst (RoundDoubleMode (LoadD src) rmode)); + format %{ "roundsd $dst, $src" %} + ins_cost(150); + ins_encode %{ + __ roundsd($dst$$XMMRegister, $src$$Address, $rmode$$constant); + %} + ins_pipe(pipe_slow); +%} + +instruct roundD_imm(legRegD dst, immD con, immU8 rmode, rRegI scratch_reg) %{ + predicate(UseSSE>=4); + match(Set dst (RoundDoubleMode con rmode)); + effect(TEMP scratch_reg); + format %{ "roundsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} + ins_cost(150); + ins_encode %{ + __ roundsd($dst$$XMMRegister, $constantaddress($con), $rmode$$constant, $scratch_reg$$Register); + %} + ins_pipe(pipe_slow); +%} + +instruct vround2D_reg(legVecX dst, legVecX src, immU8 rmode) %{ + predicate(UseAVX > 0 && n->as_Vector()->length() == 2); + match(Set dst (RoundDoubleModeV src rmode)); + format %{ "vroundpd $dst, $src, $rmode\t! round packed2D" %} + ins_encode %{ + int vector_len = 0; + __ vroundpd($dst$$XMMRegister, $src$$XMMRegister, $rmode$$constant, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct vround2D_mem(legVecX dst, memory mem, immU8 rmode) %{ + predicate(UseAVX > 0 && n->as_Vector()->length() == 2); + match(Set dst (RoundDoubleModeV (LoadVector mem) rmode)); + format %{ "vroundpd $dst, $mem, $rmode\t! round packed2D" %} + ins_encode %{ + int vector_len = 0; + __ vroundpd($dst$$XMMRegister, $mem$$Address, $rmode$$constant, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct vround4D_reg(legVecY dst, legVecY src, legVecY rmode) %{ + predicate(UseAVX > 0 && n->as_Vector()->length() == 4); + match(Set dst (RoundDoubleModeV src rmode)); + format %{ "vroundpd $dst, $src, $rmode\t! round packed4D" %} + ins_encode %{ + int vector_len = 1; + __ vroundpd($dst$$XMMRegister, $src$$XMMRegister, $rmode$$constant, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct vround4D_mem(legVecY dst, memory mem, immU8 rmode) %{ + predicate(UseAVX > 0 && n->as_Vector()->length() == 4); + match(Set dst (RoundDoubleModeV (LoadVector mem) rmode)); + format %{ "vroundpd $dst, $mem, $rmode\t! round packed4D" %} + ins_encode %{ + int vector_len = 1; + __ vroundpd($dst$$XMMRegister, $mem$$Address, $rmode$$constant, vector_len); + %} + ins_pipe( pipe_slow ); +%} + + +instruct vround8D_reg(vecZ dst, vecZ src, immU8 rmode) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 8); + match(Set dst (RoundDoubleModeV src rmode)); + format %{ "vrndscalepd $dst, $src, $rmode\t! round packed8D" %} + ins_encode %{ + int vector_len = 2; + __ vrndscalepd($dst$$XMMRegister, $src$$XMMRegister, $rmode$$constant, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct vround8D_mem(vecZ dst, memory mem, immU8 rmode) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 8); + match(Set dst (RoundDoubleModeV (LoadVector mem) rmode)); + format %{ "vrndscalepd $dst, $mem, $rmode\t! round packed8D" %} + ins_encode %{ + int vector_len = 2; + __ vrndscalepd($dst$$XMMRegister, $mem$$Address, $rmode$$constant, vector_len); + %} + ins_pipe( pipe_slow ); +%} +#endif // _LP64 + instruct onspinwait() %{ match(OnSpinWait); ins_cost(200); @@ -3108,30 +3270,6 @@ // ====================LEGACY REPLICATE======================================= -instruct Repl4B_mem(vecS dst, memory mem) %{ - predicate(n->as_Vector()->length() == 4 && UseAVX > 0 && !VM_Version::supports_avx512vlbw()); - match(Set dst (ReplicateB (LoadB mem))); - format %{ "punpcklbw $dst,$mem\n\t" - "pshuflw $dst,$dst,0x00\t! replicate4B" %} - ins_encode %{ - __ punpcklbw($dst$$XMMRegister, $mem$$Address); - __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); - %} - ins_pipe( pipe_slow ); -%} - -instruct Repl8B_mem(vecD dst, memory mem) %{ - predicate(n->as_Vector()->length() == 8 && UseAVX > 0 && !VM_Version::supports_avx512vlbw()); - match(Set dst (ReplicateB (LoadB mem))); - format %{ "punpcklbw $dst,$mem\n\t" - "pshuflw $dst,$dst,0x00\t! replicate8B" %} - ins_encode %{ - __ punpcklbw($dst$$XMMRegister, $mem$$Address); - __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); - %} - ins_pipe( pipe_slow ); -%} - instruct Repl16B(vecX dst, rRegI src) %{ predicate(n->as_Vector()->length() == 16 && !VM_Version::supports_avx512vlbw()); match(Set dst (ReplicateB src)); @@ -3148,20 +3286,6 @@ ins_pipe( pipe_slow ); %} -instruct Repl16B_mem(vecX dst, memory mem) %{ - predicate(n->as_Vector()->length() == 16 && UseAVX > 0 && !VM_Version::supports_avx512vlbw()); - match(Set dst (ReplicateB (LoadB mem))); - format %{ "punpcklbw $dst,$mem\n\t" - "pshuflw $dst,$dst,0x00\n\t" - "punpcklqdq $dst,$dst\t! replicate16B" %} - ins_encode %{ - __ punpcklbw($dst$$XMMRegister, $mem$$Address); - __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); - __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - instruct Repl32B(vecY dst, rRegI src) %{ predicate(n->as_Vector()->length() == 32 && !VM_Version::supports_avx512vlbw()); match(Set dst (ReplicateB src)); @@ -3180,22 +3304,6 @@ ins_pipe( pipe_slow ); %} -instruct Repl32B_mem(vecY dst, memory mem) %{ - predicate(n->as_Vector()->length() == 32 && !VM_Version::supports_avx512vlbw()); - match(Set dst (ReplicateB (LoadB mem))); - format %{ "punpcklbw $dst,$mem\n\t" - "pshuflw $dst,$dst,0x00\n\t" - "punpcklqdq $dst,$dst\n\t" - "vinserti128_high $dst,$dst\t! replicate32B" %} - ins_encode %{ - __ punpcklbw($dst$$XMMRegister, $mem$$Address); - __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); - __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); - __ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - instruct Repl64B(legVecZ dst, rRegI src) %{ predicate(n->as_Vector()->length() == 64 && !VM_Version::supports_avx512vlbw()); match(Set dst (ReplicateB src)); @@ -3216,24 +3324,6 @@ ins_pipe( pipe_slow ); %} -instruct Repl64B_mem(legVecZ dst, memory mem) %{ - predicate(n->as_Vector()->length() == 64 && !VM_Version::supports_avx512vlbw()); - match(Set dst (ReplicateB (LoadB mem))); - format %{ "punpcklbw $dst,$mem\n\t" - "pshuflw $dst,$dst,0x00\n\t" - "punpcklqdq $dst,$dst\n\t" - "vinserti128_high $dst,$dst\t" - "vinserti64x4 $dst,$dst,$dst,0x1\t! replicate64B" %} - ins_encode %{ - __ punpcklbw($dst$$XMMRegister, $mem$$Address); - __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); - __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); - __ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister); - __ vinserti64x4($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, 0x1); - %} - ins_pipe( pipe_slow ); -%} - instruct Repl16B_imm(vecX dst, immI con) %{ predicate(n->as_Vector()->length() == 16 && !VM_Version::supports_avx512vlbw()); match(Set dst (ReplicateB con)); @@ -3769,7 +3859,7 @@ %} instruct Repl2F_zero(vecD dst, immF0 zero) %{ - predicate(n->as_Vector()->length() == 2 && UseAVX < 3); + predicate(n->as_Vector()->length() == 2); match(Set dst (ReplicateF zero)); format %{ "xorps $dst,$dst\t! replicate2F zero" %} ins_encode %{ @@ -3779,7 +3869,7 @@ %} instruct Repl4F_zero(vecX dst, immF0 zero) %{ - predicate(n->as_Vector()->length() == 4 && UseAVX < 3); + predicate(n->as_Vector()->length() == 4); match(Set dst (ReplicateF zero)); format %{ "xorps $dst,$dst\t! replicate4F zero" %} ins_encode %{ @@ -3789,7 +3879,7 @@ %} instruct Repl8F_zero(vecY dst, immF0 zero) %{ - predicate(n->as_Vector()->length() == 8 && UseAVX < 3); + predicate(n->as_Vector()->length() == 8 && UseAVX > 0); match(Set dst (ReplicateF zero)); format %{ "vxorps $dst,$dst,$dst\t! replicate8F zero" %} ins_encode %{ @@ -3863,7 +3953,7 @@ // Replicate double (8 byte) scalar zero to be vector instruct Repl2D_zero(vecX dst, immD0 zero) %{ - predicate(n->as_Vector()->length() == 2 && UseAVX < 3); + predicate(n->as_Vector()->length() == 2); match(Set dst (ReplicateD zero)); format %{ "xorpd $dst,$dst\t! replicate2D zero" %} ins_encode %{ @@ -3873,7 +3963,7 @@ %} instruct Repl4D_zero(vecY dst, immD0 zero) %{ - predicate(n->as_Vector()->length() == 4 && UseAVX < 3); + predicate(n->as_Vector()->length() == 4 && UseAVX > 0); match(Set dst (ReplicateD zero)); format %{ "vxorpd $dst,$dst,$dst,vect256\t! replicate4D zero" %} ins_encode %{ @@ -4798,42 +4888,6 @@ ins_pipe( pipe_slow ); %} -instruct Repl2F_zero_evex(vecD dst, immF0 zero) %{ - predicate(n->as_Vector()->length() == 2 && UseAVX > 2); - match(Set dst (ReplicateF zero)); - format %{ "vpxor $dst k0,$dst,$dst\t! replicate2F zero" %} - ins_encode %{ - // Use vpxor in place of vxorps since EVEX has a constriant on dq for vxorps: this is a 512-bit operation - int vector_len = 2; - __ vpxor($dst$$XMMRegister,$dst$$XMMRegister, $dst$$XMMRegister, vector_len); - %} - ins_pipe( fpu_reg_reg ); -%} - -instruct Repl4F_zero_evex(vecX dst, immF0 zero) %{ - predicate(n->as_Vector()->length() == 4 && UseAVX > 2); - match(Set dst (ReplicateF zero)); - format %{ "vpxor $dst k0,$dst,$dst\t! replicate4F zero" %} - ins_encode %{ - // Use vpxor in place of vxorps since EVEX has a constriant on dq for vxorps: this is a 512-bit operation - int vector_len = 2; - __ vpxor($dst$$XMMRegister,$dst$$XMMRegister, $dst$$XMMRegister, vector_len); - %} - ins_pipe( fpu_reg_reg ); -%} - -instruct Repl8F_zero_evex(vecY dst, immF0 zero) %{ - predicate(n->as_Vector()->length() == 8 && UseAVX > 2); - match(Set dst (ReplicateF zero)); - format %{ "vpxor $dst k0,$dst,$dst\t! replicate8F zero" %} - ins_encode %{ - // Use vpxor in place of vxorps since EVEX has a constriant on dq for vxorps: this is a 512-bit operation - int vector_len = 2; - __ vpxor($dst$$XMMRegister,$dst$$XMMRegister, $dst$$XMMRegister, vector_len); - %} - ins_pipe( fpu_reg_reg ); -%} - instruct Repl16F_zero_evex(vecZ dst, immF0 zero) %{ predicate(n->as_Vector()->length() == 16 && UseAVX > 2); match(Set dst (ReplicateF zero)); @@ -4890,30 +4944,6 @@ ins_pipe( pipe_slow ); %} -instruct Repl2D_zero_evex(vecX dst, immD0 zero) %{ - predicate(n->as_Vector()->length() == 2 && UseAVX > 2); - match(Set dst (ReplicateD zero)); - format %{ "vpxor $dst k0,$dst,$dst\t! replicate2D zero" %} - ins_encode %{ - // Use vpxor in place of vxorpd since EVEX has a constriant on dq for vxorpd: this is a 512-bit operation - int vector_len = 2; - __ vpxor($dst$$XMMRegister,$dst$$XMMRegister, $dst$$XMMRegister, vector_len); - %} - ins_pipe( fpu_reg_reg ); -%} - -instruct Repl4D_zero_evex(vecY dst, immD0 zero) %{ - predicate(n->as_Vector()->length() == 4 && UseAVX > 2); - match(Set dst (ReplicateD zero)); - format %{ "vpxor $dst k0,$dst,$dst\t! replicate4D zero" %} - ins_encode %{ - // Use vpxor in place of vxorpd since EVEX has a constriant on dq for vxorpd: this is a 512-bit operation - int vector_len = 2; - __ vpxor($dst$$XMMRegister,$dst$$XMMRegister, $dst$$XMMRegister, vector_len); - %} - ins_pipe( fpu_reg_reg ); -%} - instruct Repl8D_zero_evex(vecZ dst, immD0 zero) %{ predicate(n->as_Vector()->length() == 8 && UseAVX > 2); match(Set dst (ReplicateD zero)); @@ -7294,6 +7324,186 @@ // --------------------------------- MUL -------------------------------------- +// Byte vector mul +instruct mul4B_reg(vecS dst, vecS src1, vecS src2, vecS tmp, rRegI scratch) %{ + predicate(UseSSE > 3 && n->as_Vector()->length() == 4); + match(Set dst (MulVB src1 src2)); + effect(TEMP dst, TEMP tmp, TEMP scratch); + format %{"pmovsxbw $tmp,$src1\n\t" + "pmovsxbw $dst,$src2\n\t" + "pmullw $tmp,$dst\n\t" + "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" + "pand $dst,$tmp\n\t" + "packuswb $dst,$dst\t! mul packed4B" %} + ins_encode %{ + __ pmovsxbw($tmp$$XMMRegister, $src1$$XMMRegister); + __ pmovsxbw($dst$$XMMRegister, $src2$$XMMRegister); + __ pmullw($tmp$$XMMRegister, $dst$$XMMRegister); + __ movdqu($dst$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), $scratch$$Register); + __ pand($dst$$XMMRegister, $tmp$$XMMRegister); + __ packuswb($dst$$XMMRegister, $dst$$XMMRegister); + %} + ins_pipe( pipe_slow ); +%} + +instruct mul8B_reg(vecD dst, vecD src1, vecD src2, vecD tmp, rRegI scratch) %{ + predicate(UseSSE > 3 && n->as_Vector()->length() == 8); + match(Set dst (MulVB src1 src2)); + effect(TEMP dst, TEMP tmp, TEMP scratch); + format %{"pmovsxbw $tmp,$src1\n\t" + "pmovsxbw $dst,$src2\n\t" + "pmullw $tmp,$dst\n\t" + "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" + "pand $dst,$tmp\n\t" + "packuswb $dst,$dst\t! mul packed8B" %} + ins_encode %{ + __ pmovsxbw($tmp$$XMMRegister, $src1$$XMMRegister); + __ pmovsxbw($dst$$XMMRegister, $src2$$XMMRegister); + __ pmullw($tmp$$XMMRegister, $dst$$XMMRegister); + __ movdqu($dst$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), $scratch$$Register); + __ pand($dst$$XMMRegister, $tmp$$XMMRegister); + __ packuswb($dst$$XMMRegister, $dst$$XMMRegister); + %} + ins_pipe( pipe_slow ); +%} + +instruct mul16B_reg(vecX dst, vecX src1, vecX src2, vecX tmp1, vecX tmp2, rRegI scratch) %{ + predicate(UseSSE > 3 && n->as_Vector()->length() == 16); + match(Set dst (MulVB src1 src2)); + effect(TEMP dst, TEMP tmp1, TEMP tmp2, TEMP scratch); + format %{"pmovsxbw $tmp1,$src1\n\t" + "pmovsxbw $tmp2,$src2\n\t" + "pmullw $tmp1,$tmp2\n\t" + "pshufd $tmp2,$src1,0xEE\n\t" + "pshufd $dst,$src2,0xEE\n\t" + "pmovsxbw $tmp2,$tmp2\n\t" + "pmovsxbw $dst,$dst\n\t" + "pmullw $tmp2,$dst\n\t" + "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" + "pand $tmp2,$dst\n\t" + "pand $dst,$tmp1\n\t" + "packuswb $dst,$tmp2\t! mul packed16B" %} + ins_encode %{ + __ pmovsxbw($tmp1$$XMMRegister, $src1$$XMMRegister); + __ pmovsxbw($tmp2$$XMMRegister, $src2$$XMMRegister); + __ pmullw($tmp1$$XMMRegister, $tmp2$$XMMRegister); + __ pshufd($tmp2$$XMMRegister, $src1$$XMMRegister, 0xEE); + __ pshufd($dst$$XMMRegister, $src2$$XMMRegister, 0xEE); + __ pmovsxbw($tmp2$$XMMRegister, $tmp2$$XMMRegister); + __ pmovsxbw($dst$$XMMRegister, $dst$$XMMRegister); + __ pmullw($tmp2$$XMMRegister, $dst$$XMMRegister); + __ movdqu($dst$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), $scratch$$Register); + __ pand($tmp2$$XMMRegister, $dst$$XMMRegister); + __ pand($dst$$XMMRegister, $tmp1$$XMMRegister); + __ packuswb($dst$$XMMRegister, $tmp2$$XMMRegister); + %} + ins_pipe( pipe_slow ); +%} + +instruct vmul16B_reg_avx(vecX dst, vecX src1, vecX src2, vecX tmp, rRegI scratch) %{ + predicate(UseAVX > 1 && n->as_Vector()->length() == 16); + match(Set dst (MulVB src1 src2)); + effect(TEMP dst, TEMP tmp, TEMP scratch); + format %{"vpmovsxbw $tmp,$src1\n\t" + "vpmovsxbw $dst,$src2\n\t" + "vpmullw $tmp,$tmp,$dst\n\t" + "vmovdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" + "vpand $dst,$dst,$tmp\n\t" + "vextracti128_high $tmp,$dst\n\t" + "vpackuswb $dst,$dst,$dst\n\t! mul packed16B" %} + ins_encode %{ + int vector_len = 1; + __ vpmovsxbw($tmp$$XMMRegister, $src1$$XMMRegister, vector_len); + __ vpmovsxbw($dst$$XMMRegister, $src2$$XMMRegister, vector_len); + __ vpmullw($tmp$$XMMRegister, $tmp$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vmovdqu($dst$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), $scratch$$Register); + __ vpand($dst$$XMMRegister, $dst$$XMMRegister, $tmp$$XMMRegister, vector_len); + __ vextracti128_high($tmp$$XMMRegister, $dst$$XMMRegister); + __ vpackuswb($dst$$XMMRegister, $dst$$XMMRegister, $tmp$$XMMRegister, 0); + %} + ins_pipe( pipe_slow ); +%} + +instruct vmul32B_reg_avx(vecY dst, vecY src1, vecY src2, vecY tmp1, vecY tmp2, rRegI scratch) %{ + predicate(UseAVX > 1 && n->as_Vector()->length() == 32); + match(Set dst (MulVB src1 src2)); + effect(TEMP dst, TEMP tmp1, TEMP tmp2, TEMP scratch); + format %{"vextracti128_high $tmp1,$src1\n\t" + "vextracti128_high $dst,$src2\n\t" + "vpmovsxbw $tmp1,$tmp1\n\t" + "vpmovsxbw $dst,$dst\n\t" + "vpmullw $tmp1,$tmp1,$dst\n\t" + "vpmovsxbw $tmp2,$src1\n\t" + "vpmovsxbw $dst,$src2\n\t" + "vpmullw $tmp2,$tmp2,$dst\n\t" + "vmovdqu $dst, [0x00ff00ff0x00ff00ff]\n\t" + "vpbroadcastd $dst, $dst\n\t" + "vpand $tmp1,$tmp1,$dst\n\t" + "vpand $dst,$dst,$tmp2\n\t" + "vpackuswb $dst,$dst,$tmp1\n\t" + "vpermq $dst, $dst, 0xD8\t! mul packed32B" %} + ins_encode %{ + int vector_len = 1; + __ vextracti128_high($tmp1$$XMMRegister, $src1$$XMMRegister); + __ vextracti128_high($dst$$XMMRegister, $src2$$XMMRegister); + __ vpmovsxbw($tmp1$$XMMRegister, $tmp1$$XMMRegister, vector_len); + __ vpmovsxbw($dst$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vpmullw($tmp1$$XMMRegister, $tmp1$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vpmovsxbw($tmp2$$XMMRegister, $src1$$XMMRegister, vector_len); + __ vpmovsxbw($dst$$XMMRegister, $src2$$XMMRegister, vector_len); + __ vpmullw($tmp2$$XMMRegister, $tmp2$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vmovdqu($dst$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), $scratch$$Register); + __ vpbroadcastd($dst$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vpand($tmp1$$XMMRegister, $tmp1$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vpand($dst$$XMMRegister, $dst$$XMMRegister, $tmp2$$XMMRegister, vector_len); + __ vpackuswb($dst$$XMMRegister, $dst$$XMMRegister, $tmp1$$XMMRegister, vector_len); + __ vpermq($dst$$XMMRegister, $dst$$XMMRegister, 0xD8, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct vmul64B_reg_avx(vecZ dst, vecZ src1, vecZ src2, vecZ tmp1, vecZ tmp2, rRegI scratch) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 64); + match(Set dst (MulVB src1 src2)); + effect(TEMP dst, TEMP tmp1, TEMP tmp2, TEMP scratch); + format %{"vextracti64x4_high $tmp1,$src1\n\t" + "vextracti64x4_high $dst,$src2\n\t" + "vpmovsxbw $tmp1,$tmp1\n\t" + "vpmovsxbw $dst,$dst\n\t" + "vpmullw $tmp1,$tmp1,$dst\n\t" + "vpmovsxbw $tmp2,$src1\n\t" + "vpmovsxbw $dst,$src2\n\t" + "vpmullw $tmp2,$tmp2,$dst\n\t" + "vmovdqu $dst, [0x00ff00ff0x00ff00ff]\n\t" + "vpbroadcastd $dst, $dst\n\t" + "vpand $tmp1,$tmp1,$dst\n\t" + "vpand $tmp2,$tmp2,$dst\n\t" + "vpackuswb $dst,$tmp1,$tmp2\n\t" + "evmovdquq $tmp2,[0x0604020007050301]\n\t" + "vpermq $dst,$tmp2,$dst,0x01\t! mul packed64B" %} + + ins_encode %{ + int vector_len = 2; + __ vextracti64x4_high($tmp1$$XMMRegister, $src1$$XMMRegister); + __ vextracti64x4_high($dst$$XMMRegister, $src2$$XMMRegister); + __ vpmovsxbw($tmp1$$XMMRegister, $tmp1$$XMMRegister, vector_len); + __ vpmovsxbw($dst$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vpmullw($tmp1$$XMMRegister, $tmp1$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vpmovsxbw($tmp2$$XMMRegister, $src1$$XMMRegister, vector_len); + __ vpmovsxbw($dst$$XMMRegister, $src2$$XMMRegister, vector_len); + __ vpmullw($tmp2$$XMMRegister, $tmp2$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vmovdqu($dst$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), $scratch$$Register); + __ vpbroadcastd($dst$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vpand($tmp1$$XMMRegister, $tmp1$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vpand($tmp2$$XMMRegister, $tmp2$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vpackuswb($dst$$XMMRegister, $tmp1$$XMMRegister, $tmp2$$XMMRegister, vector_len); + __ evmovdquq($tmp2$$XMMRegister, ExternalAddress(vector_byte_perm_mask()), vector_len, $scratch$$Register); + __ vpermq($dst$$XMMRegister, $tmp2$$XMMRegister, $dst$$XMMRegister, vector_len); + + %} + ins_pipe( pipe_slow ); +%} + // Shorts/Chars vector mul instruct vmul2S(vecS dst, vecS src) %{ predicate(UseAVX == 0 && n->as_Vector()->length() == 2); @@ -8016,20 +8226,6 @@ ins_pipe( pipe_slow ); %} -// ------------------------------ Shift --------------------------------------- - -// Left and right shift count vectors are the same on x86 -// (only lowest bits of xmm reg are used for count). -instruct vshiftcnt(vecS dst, rRegI cnt) %{ - match(Set dst (LShiftCntV cnt)); - match(Set dst (RShiftCntV cnt)); - format %{ "movd $dst,$cnt\t! load shift count" %} - ins_encode %{ - __ movdl($dst$$XMMRegister, $cnt$$Register); - %} - ins_pipe( pipe_slow ); -%} - // --------------------------------- Sqrt -------------------------------------- // Floating point vector sqrt @@ -8187,1093 +8383,491 @@ ins_pipe( pipe_slow ); %} -// ------------------------------ LeftShift ----------------------------------- +// ------------------------------ Shift --------------------------------------- -// Shorts/Chars vector left shift -instruct vsll2S(vecS dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (LShiftVS dst shift)); - format %{ "psllw $dst,$shift\t! left shift packed2S" %} +// Left and right shift count vectors are the same on x86 +// (only lowest bits of xmm reg are used for count). +instruct vshiftcnt(vecS dst, rRegI cnt) %{ + match(Set dst (LShiftCntV cnt)); + match(Set dst (RShiftCntV cnt)); + format %{ "movdl $dst,$cnt\t! load shift count" %} ins_encode %{ - __ psllw($dst$$XMMRegister, $shift$$XMMRegister); + __ movdl($dst$$XMMRegister, $cnt$$Register); %} ins_pipe( pipe_slow ); %} -instruct vsll2S_imm(vecS dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (LShiftVS dst shift)); - format %{ "psllw $dst,$shift\t! left shift packed2S" %} +instruct vshiftcntimm(vecS dst, immI8 cnt, rRegI tmp) %{ + match(Set dst cnt); + effect(TEMP tmp); + format %{ "movl $tmp,$cnt\t" + "movdl $dst,$tmp\t! load shift count" %} ins_encode %{ - __ psllw($dst$$XMMRegister, (int)$shift$$constant); + __ movl($tmp$$Register, $cnt$$constant); + __ movdl($dst$$XMMRegister, $tmp$$Register); %} ins_pipe( pipe_slow ); %} -instruct vsll2S_reg(vecS dst, vecS src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); - match(Set dst (LShiftVS src shift)); - format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %} +// Byte vector shift +instruct vshift4B(vecS dst, vecS src, vecS shift, vecS tmp, rRegI scratch) %{ + predicate(UseSSE > 3 && n->as_Vector()->length() == 4); + match(Set dst (LShiftVB src shift)); + match(Set dst (RShiftVB src shift)); + match(Set dst (URShiftVB src shift)); + effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch); + format %{"vextendbw $tmp,$src\n\t" + "vshiftw $tmp,$shift\n\t" + "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" + "pand $dst,$tmp\n\t" + "packuswb $dst,$dst\n\t ! packed4B shift" %} ins_encode %{ - int vector_len = 0; - __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + int opcode = this->as_Mach()->ideal_Opcode(); + + __ vextendbw(opcode, $tmp$$XMMRegister, $src$$XMMRegister); + __ vshiftw(opcode, $tmp$$XMMRegister, $shift$$XMMRegister); + __ movdqu($dst$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), $scratch$$Register); + __ pand($dst$$XMMRegister, $tmp$$XMMRegister); + __ packuswb($dst$$XMMRegister, $dst$$XMMRegister); %} ins_pipe( pipe_slow ); %} -instruct vsll2S_reg_imm(vecS dst, vecS src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); - match(Set dst (LShiftVS src shift)); - format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %} +instruct vshift8B(vecD dst, vecD src, vecS shift, vecD tmp, rRegI scratch) %{ + predicate(UseSSE > 3 && n->as_Vector()->length() == 8); + match(Set dst (LShiftVB src shift)); + match(Set dst (RShiftVB src shift)); + match(Set dst (URShiftVB src shift)); + effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch); + format %{"vextendbw $tmp,$src\n\t" + "vshiftw $tmp,$shift\n\t" + "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" + "pand $dst,$tmp\n\t" + "packuswb $dst,$dst\n\t ! packed8B shift" %} ins_encode %{ - int vector_len = 0; - __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); + int opcode = this->as_Mach()->ideal_Opcode(); + + __ vextendbw(opcode, $tmp$$XMMRegister, $src$$XMMRegister); + __ vshiftw(opcode, $tmp$$XMMRegister, $shift$$XMMRegister); + __ movdqu($dst$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), $scratch$$Register); + __ pand($dst$$XMMRegister, $tmp$$XMMRegister); + __ packuswb($dst$$XMMRegister, $dst$$XMMRegister); %} ins_pipe( pipe_slow ); %} -instruct vsll4S(vecD dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 4); - match(Set dst (LShiftVS dst shift)); - format %{ "psllw $dst,$shift\t! left shift packed4S" %} +instruct vshift16B(vecX dst, vecX src, vecS shift, vecX tmp1, vecX tmp2, rRegI scratch) %{ + predicate(UseSSE > 3 && UseAVX <= 1 && n->as_Vector()->length() == 16); + match(Set dst (LShiftVB src shift)); + match(Set dst (RShiftVB src shift)); + match(Set dst (URShiftVB src shift)); + effect(TEMP dst, USE src, USE shift, TEMP tmp1, TEMP tmp2, TEMP scratch); + format %{"vextendbw $tmp1,$src\n\t" + "vshiftw $tmp1,$shift\n\t" + "pshufd $tmp2,$src\n\t" + "vextendbw $tmp2,$tmp2\n\t" + "vshiftw $tmp2,$shift\n\t" + "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" + "pand $tmp2,$dst\n\t" + "pand $dst,$tmp1\n\t" + "packuswb $dst,$tmp2\n\t! packed16B shift" %} ins_encode %{ - __ psllw($dst$$XMMRegister, $shift$$XMMRegister); + int opcode = this->as_Mach()->ideal_Opcode(); + + __ vextendbw(opcode, $tmp1$$XMMRegister, $src$$XMMRegister); + __ vshiftw(opcode, $tmp1$$XMMRegister, $shift$$XMMRegister); + __ pshufd($tmp2$$XMMRegister, $src$$XMMRegister, 0xE); + __ vextendbw(opcode, $tmp2$$XMMRegister, $tmp2$$XMMRegister); + __ vshiftw(opcode, $tmp2$$XMMRegister, $shift$$XMMRegister); + __ movdqu($dst$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), $scratch$$Register); + __ pand($tmp2$$XMMRegister, $dst$$XMMRegister); + __ pand($dst$$XMMRegister, $tmp1$$XMMRegister); + __ packuswb($dst$$XMMRegister, $tmp2$$XMMRegister); %} ins_pipe( pipe_slow ); %} -instruct vsll4S_imm(vecD dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 4); - match(Set dst (LShiftVS dst shift)); - format %{ "psllw $dst,$shift\t! left shift packed4S" %} - ins_encode %{ - __ psllw($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll4S_reg(vecD dst, vecD src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 4); - match(Set dst (LShiftVS src shift)); - format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %} - ins_encode %{ - int vector_len = 0; - __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll4S_reg_imm(vecD dst, vecD src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 4); - match(Set dst (LShiftVS src shift)); - format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %} - ins_encode %{ - int vector_len = 0; - __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll8S(vecX dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 8); - match(Set dst (LShiftVS dst shift)); - format %{ "psllw $dst,$shift\t! left shift packed8S" %} - ins_encode %{ - __ psllw($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll8S_imm(vecX dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 8); - match(Set dst (LShiftVS dst shift)); - format %{ "psllw $dst,$shift\t! left shift packed8S" %} - ins_encode %{ - __ psllw($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll8S_reg(vecX dst, vecX src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 8); - match(Set dst (LShiftVS src shift)); - format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %} - ins_encode %{ - int vector_len = 0; - __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll8S_reg_imm(vecX dst, vecX src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 8); - match(Set dst (LShiftVS src shift)); - format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %} - ins_encode %{ - int vector_len = 0; - __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll16S_reg(vecY dst, vecY src, vecS shift) %{ +instruct vshift16B_avx(vecX dst, vecX src, vecS shift, vecX tmp, rRegI scratch) %{ predicate(UseAVX > 1 && n->as_Vector()->length() == 16); - match(Set dst (LShiftVS src shift)); - format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %} + match(Set dst (LShiftVB src shift)); + match(Set dst (RShiftVB src shift)); + match(Set dst (URShiftVB src shift)); + effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch); + format %{"vextendbw $tmp,$src\n\t" + "vshiftw $tmp,$tmp,$shift\n\t" + "vpand $tmp,$tmp,[0x00ff00ff0x00ff00ff]\n\t" + "vextracti128_high $dst,$tmp\n\t" + "vpackuswb $dst,$tmp,$dst\n\t! packed16B shift" %} ins_encode %{ + int opcode = this->as_Mach()->ideal_Opcode(); + int vector_len = 1; - __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + __ vextendbw(opcode, $tmp$$XMMRegister, $src$$XMMRegister, vector_len); + __ vshiftw(opcode, $tmp$$XMMRegister, $tmp$$XMMRegister, $shift$$XMMRegister, vector_len); + __ vpand($tmp$$XMMRegister, $tmp$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), vector_len, $scratch$$Register); + __ vextracti128_high($dst$$XMMRegister, $tmp$$XMMRegister); + __ vpackuswb($dst$$XMMRegister, $tmp$$XMMRegister, $dst$$XMMRegister, 0); %} ins_pipe( pipe_slow ); %} -instruct vsll16S_reg_imm(vecY dst, vecY src, immI8 shift) %{ - predicate(UseAVX > 1 && n->as_Vector()->length() == 16); - match(Set dst (LShiftVS src shift)); - format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %} +instruct vshift32B_avx(vecY dst, vecY src, vecS shift, vecY tmp, rRegI scratch) %{ + predicate(UseAVX > 1 && n->as_Vector()->length() == 32); + match(Set dst (LShiftVB src shift)); + match(Set dst (RShiftVB src shift)); + match(Set dst (URShiftVB src shift)); + effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch); + format %{"vextracti128_high $tmp,$src\n\t" + "vextendbw $tmp,$tmp\n\t" + "vextendbw $dst,$src\n\t" + "vshiftw $tmp,$tmp,$shift\n\t" + "vshiftw $dst,$dst,$shift\n\t" + "vpand $tmp,$tmp,[0x00ff00ff0x00ff00ff]\n\t" + "vpand $dst,$dst,[0x00ff00ff0x00ff00ff]\n\t" + "vpackuswb $dst,$dst,$tmp\n\t" + "vpermq $dst,$dst,0xD8\n\t! packed32B shift" %} ins_encode %{ + int opcode = this->as_Mach()->ideal_Opcode(); + int vector_len = 1; - __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); + __ vextracti128_high($tmp$$XMMRegister, $src$$XMMRegister); + __ vextendbw(opcode, $tmp$$XMMRegister, $tmp$$XMMRegister, vector_len); + __ vextendbw(opcode, $dst$$XMMRegister, $src$$XMMRegister, vector_len); + __ vshiftw(opcode, $tmp$$XMMRegister, $tmp$$XMMRegister, $shift$$XMMRegister, vector_len); + __ vshiftw(opcode, $dst$$XMMRegister, $dst$$XMMRegister, $shift$$XMMRegister, vector_len); + __ vpand($tmp$$XMMRegister, $tmp$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), vector_len, $scratch$$Register); + __ vpand($dst$$XMMRegister, $dst$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), vector_len, $scratch$$Register); + __ vpackuswb($dst$$XMMRegister, $dst$$XMMRegister, $tmp$$XMMRegister, vector_len); + __ vpermq($dst$$XMMRegister, $dst$$XMMRegister, 0xD8, vector_len); %} ins_pipe( pipe_slow ); %} -instruct vsll32S_reg(vecZ dst, vecZ src, vecS shift) %{ - predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 32); - match(Set dst (LShiftVS src shift)); - format %{ "vpsllw $dst,$src,$shift\t! left shift packed32S" %} +instruct vshift64B_avx(vecZ dst, vecZ src, vecS shift, vecZ tmp1, vecZ tmp2, rRegI scratch) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 64); + match(Set dst (LShiftVB src shift)); + match(Set dst (RShiftVB src shift)); + match(Set dst (URShiftVB src shift)); + effect(TEMP dst, USE src, USE shift, TEMP tmp1, TEMP tmp2, TEMP scratch); + format %{"vextracti64x4 $tmp1,$src\n\t" + "vextendbw $tmp1,$tmp1\n\t" + "vextendbw $tmp2,$src\n\t" + "vshiftw $tmp1,$tmp1,$shift\n\t" + "vshiftw $tmp2,$tmp2,$shift\n\t" + "vmovdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" + "vpbroadcastd $dst,$dst\n\t" + "vpand $tmp1,$tmp1,$dst\n\t" + "vpand $tmp2,$tmp2,$dst\n\t" + "vpackuswb $dst,$tmp1,$tmp2\n\t" + "evmovdquq $tmp2, [0x0604020007050301]\n\t" + "vpermq $dst,$tmp2,$dst\n\t! packed64B shift" %} ins_encode %{ + int opcode = this->as_Mach()->ideal_Opcode(); + int vector_len = 2; - __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + __ vextracti64x4($tmp1$$XMMRegister, $src$$XMMRegister, 1); + __ vextendbw(opcode, $tmp1$$XMMRegister, $tmp1$$XMMRegister, vector_len); + __ vextendbw(opcode, $tmp2$$XMMRegister, $src$$XMMRegister, vector_len); + __ vshiftw(opcode, $tmp1$$XMMRegister, $tmp1$$XMMRegister, $shift$$XMMRegister, vector_len); + __ vshiftw(opcode, $tmp2$$XMMRegister, $tmp2$$XMMRegister, $shift$$XMMRegister, vector_len); + __ vmovdqu($dst$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), $scratch$$Register); + __ vpbroadcastd($dst$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vpand($tmp1$$XMMRegister, $tmp1$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vpand($tmp2$$XMMRegister, $tmp2$$XMMRegister, $dst$$XMMRegister, vector_len); + __ vpackuswb($dst$$XMMRegister, $tmp1$$XMMRegister, $tmp2$$XMMRegister, vector_len); + __ evmovdquq($tmp2$$XMMRegister, ExternalAddress(vector_byte_perm_mask()), vector_len, $scratch$$Register); + __ vpermq($dst$$XMMRegister, $tmp2$$XMMRegister, $dst$$XMMRegister, vector_len); %} ins_pipe( pipe_slow ); %} -instruct vsll32S_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ - predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 32); - match(Set dst (LShiftVS src shift)); - format %{ "vpsllw $dst,$src,$shift\t! left shift packed32S" %} - ins_encode %{ - int vector_len = 2; - __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -// Integers vector left shift -instruct vsll2I(vecD dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (LShiftVI dst shift)); - format %{ "pslld $dst,$shift\t! left shift packed2I" %} - ins_encode %{ - __ pslld($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll2I_imm(vecD dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (LShiftVI dst shift)); - format %{ "pslld $dst,$shift\t! left shift packed2I" %} - ins_encode %{ - __ pslld($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll2I_reg(vecD dst, vecD src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); - match(Set dst (LShiftVI src shift)); - format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %} - ins_encode %{ - int vector_len = 0; - __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll2I_reg_imm(vecD dst, vecD src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); - match(Set dst (LShiftVI src shift)); - format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %} - ins_encode %{ - int vector_len = 0; - __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll4I(vecX dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 4); - match(Set dst (LShiftVI dst shift)); - format %{ "pslld $dst,$shift\t! left shift packed4I" %} - ins_encode %{ - __ pslld($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll4I_imm(vecX dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 4); - match(Set dst (LShiftVI dst shift)); - format %{ "pslld $dst,$shift\t! left shift packed4I" %} - ins_encode %{ - __ pslld($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll4I_reg(vecX dst, vecX src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 4); - match(Set dst (LShiftVI src shift)); - format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %} - ins_encode %{ - int vector_len = 0; - __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll4I_reg_imm(vecX dst, vecX src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 4); - match(Set dst (LShiftVI src shift)); - format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %} - ins_encode %{ - int vector_len = 0; - __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll8I_reg(vecY dst, vecY src, vecS shift) %{ - predicate(UseAVX > 1 && n->as_Vector()->length() == 8); - match(Set dst (LShiftVI src shift)); - format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %} - ins_encode %{ - int vector_len = 1; - __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll8I_reg_imm(vecY dst, vecY src, immI8 shift) %{ - predicate(UseAVX > 1 && n->as_Vector()->length() == 8); - match(Set dst (LShiftVI src shift)); - format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %} - ins_encode %{ - int vector_len = 1; - __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll16I_reg(vecZ dst, vecZ src, vecS shift) %{ - predicate(UseAVX > 2 && n->as_Vector()->length() == 16); - match(Set dst (LShiftVI src shift)); - format %{ "vpslld $dst,$src,$shift\t! left shift packed16I" %} - ins_encode %{ - int vector_len = 2; - __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll16I_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ - predicate(UseAVX > 2 && n->as_Vector()->length() == 16); - match(Set dst (LShiftVI src shift)); - format %{ "vpslld $dst,$src,$shift\t! left shift packed16I" %} - ins_encode %{ - int vector_len = 2; - __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -// Longs vector left shift -instruct vsll2L(vecX dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (LShiftVL dst shift)); - format %{ "psllq $dst,$shift\t! left shift packed2L" %} - ins_encode %{ - __ psllq($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll2L_imm(vecX dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (LShiftVL dst shift)); - format %{ "psllq $dst,$shift\t! left shift packed2L" %} - ins_encode %{ - __ psllq($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll2L_reg(vecX dst, vecX src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); - match(Set dst (LShiftVL src shift)); - format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %} - ins_encode %{ - int vector_len = 0; - __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll2L_reg_imm(vecX dst, vecX src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); - match(Set dst (LShiftVL src shift)); - format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %} - ins_encode %{ - int vector_len = 0; - __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll4L_reg(vecY dst, vecY src, vecS shift) %{ - predicate(UseAVX > 1 && n->as_Vector()->length() == 4); - match(Set dst (LShiftVL src shift)); - format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %} - ins_encode %{ - int vector_len = 1; - __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll4L_reg_imm(vecY dst, vecY src, immI8 shift) %{ - predicate(UseAVX > 1 && n->as_Vector()->length() == 4); - match(Set dst (LShiftVL src shift)); - format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %} - ins_encode %{ - int vector_len = 1; - __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll8L_reg(vecZ dst, vecZ src, vecS shift) %{ - predicate(UseAVX > 2 && n->as_Vector()->length() == 8); - match(Set dst (LShiftVL src shift)); - format %{ "vpsllq $dst,$src,$shift\t! left shift packed8L" %} - ins_encode %{ - int vector_len = 2; - __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsll8L_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ - predicate(UseAVX > 2 && n->as_Vector()->length() == 8); - match(Set dst (LShiftVL src shift)); - format %{ "vpsllq $dst,$src,$shift\t! left shift packed8L" %} - ins_encode %{ - int vector_len = 2; - __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -// ----------------------- LogicalRightShift ----------------------------------- - // Shorts vector logical right shift produces incorrect Java result // for negative data because java code convert short value into int with // sign extension before a shift. But char vectors are fine since chars are // unsigned values. - -instruct vsrl2S(vecS dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (URShiftVS dst shift)); - format %{ "psrlw $dst,$shift\t! logical right shift packed2S" %} - ins_encode %{ - __ psrlw($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl2S_imm(vecS dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (URShiftVS dst shift)); - format %{ "psrlw $dst,$shift\t! logical right shift packed2S" %} - ins_encode %{ - __ psrlw($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl2S_reg(vecS dst, vecS src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); +// Shorts/Chars vector left shift +instruct vshist2S(vecS dst, vecS src, vecS shift) %{ + predicate(n->as_Vector()->length() == 2); + match(Set dst (LShiftVS src shift)); + match(Set dst (RShiftVS src shift)); match(Set dst (URShiftVS src shift)); - format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed2S" %} + effect(TEMP dst, USE src, USE shift); + format %{ "vshiftw $dst,$src,$shift\t! shift packed2S" %} ins_encode %{ - int vector_len = 0; - __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + int opcode = this->as_Mach()->ideal_Opcode(); + if (UseAVX == 0) { + if ($dst$$XMMRegister != $src$$XMMRegister) + __ movflt($dst$$XMMRegister, $src$$XMMRegister); + __ vshiftw(opcode, $dst$$XMMRegister, $shift$$XMMRegister); + } else { + int vector_len = 0; + __ vshiftw(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + } %} ins_pipe( pipe_slow ); %} -instruct vsrl2S_reg_imm(vecS dst, vecS src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); +instruct vshift4S(vecD dst, vecD src, vecS shift) %{ + predicate(n->as_Vector()->length() == 4); + match(Set dst (LShiftVS src shift)); + match(Set dst (RShiftVS src shift)); match(Set dst (URShiftVS src shift)); - format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed2S" %} + effect(TEMP dst, USE src, USE shift); + format %{ "vshiftw $dst,$src,$shift\t! shift packed4S" %} ins_encode %{ - int vector_len = 0; - __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); + int opcode = this->as_Mach()->ideal_Opcode(); + if (UseAVX == 0) { + if ($dst$$XMMRegister != $src$$XMMRegister) + __ movdbl($dst$$XMMRegister, $src$$XMMRegister); + __ vshiftw(opcode, $dst$$XMMRegister, $shift$$XMMRegister); + + } else { + int vector_len = 0; + __ vshiftw(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + } %} ins_pipe( pipe_slow ); %} -instruct vsrl4S(vecD dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 4); - match(Set dst (URShiftVS dst shift)); - format %{ "psrlw $dst,$shift\t! logical right shift packed4S" %} - ins_encode %{ - __ psrlw($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl4S_imm(vecD dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 4); - match(Set dst (URShiftVS dst shift)); - format %{ "psrlw $dst,$shift\t! logical right shift packed4S" %} - ins_encode %{ - __ psrlw($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl4S_reg(vecD dst, vecD src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 4); +instruct vshift8S(vecX dst, vecX src, vecS shift) %{ + predicate(n->as_Vector()->length() == 8); + match(Set dst (LShiftVS src shift)); + match(Set dst (RShiftVS src shift)); match(Set dst (URShiftVS src shift)); - format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed4S" %} + effect(TEMP dst, USE src, USE shift); + format %{ "vshiftw $dst,$src,$shift\t! shift packed8S" %} ins_encode %{ - int vector_len = 0; - __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + int opcode = this->as_Mach()->ideal_Opcode(); + if (UseAVX == 0) { + if ($dst$$XMMRegister != $src$$XMMRegister) + __ movdqu($dst$$XMMRegister, $src$$XMMRegister); + __ vshiftw(opcode, $dst$$XMMRegister, $shift$$XMMRegister); + } else { + int vector_len = 0; + __ vshiftw(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + } %} ins_pipe( pipe_slow ); %} -instruct vsrl4S_reg_imm(vecD dst, vecD src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 4); - match(Set dst (URShiftVS src shift)); - format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed4S" %} - ins_encode %{ - int vector_len = 0; - __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl8S(vecX dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 8); - match(Set dst (URShiftVS dst shift)); - format %{ "psrlw $dst,$shift\t! logical right shift packed8S" %} - ins_encode %{ - __ psrlw($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl8S_imm(vecX dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 8); - match(Set dst (URShiftVS dst shift)); - format %{ "psrlw $dst,$shift\t! logical right shift packed8S" %} - ins_encode %{ - __ psrlw($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl8S_reg(vecX dst, vecX src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 8); - match(Set dst (URShiftVS src shift)); - format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed8S" %} - ins_encode %{ - int vector_len = 0; - __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl8S_reg_imm(vecX dst, vecX src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 8); - match(Set dst (URShiftVS src shift)); - format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed8S" %} - ins_encode %{ - int vector_len = 0; - __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl16S_reg(vecY dst, vecY src, vecS shift) %{ +instruct vshift16S(vecY dst, vecY src, vecS shift) %{ predicate(UseAVX > 1 && n->as_Vector()->length() == 16); + match(Set dst (LShiftVS src shift)); + match(Set dst (RShiftVS src shift)); match(Set dst (URShiftVS src shift)); - format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed16S" %} + effect(DEF dst, USE src, USE shift); + format %{ "vshiftw $dst,$src,$shift\t! shift packed16S" %} ins_encode %{ int vector_len = 1; - __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + int opcode = this->as_Mach()->ideal_Opcode(); + __ vshiftw(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); %} ins_pipe( pipe_slow ); %} -instruct vsrl16S_reg_imm(vecY dst, vecY src, immI8 shift) %{ - predicate(UseAVX > 1 && n->as_Vector()->length() == 16); - match(Set dst (URShiftVS src shift)); - format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed16S" %} - ins_encode %{ - int vector_len = 1; - __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl32S_reg(vecZ dst, vecZ src, vecS shift) %{ +instruct vshift32S(vecZ dst, vecZ src, vecS shift) %{ predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 32); + match(Set dst (LShiftVS src shift)); + match(Set dst (RShiftVS src shift)); match(Set dst (URShiftVS src shift)); - format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed32S" %} + effect(DEF dst, USE src, USE shift); + format %{ "vshiftw $dst,$src,$shift\t! shift packed32S" %} ins_encode %{ int vector_len = 2; - __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + int opcode = this->as_Mach()->ideal_Opcode(); + __ vshiftw(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); %} ins_pipe( pipe_slow ); %} -instruct vsrl32S_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ - predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 32); - match(Set dst (URShiftVS src shift)); - format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed32S" %} - ins_encode %{ - int vector_len = 2; - __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -// Integers vector logical right shift -instruct vsrl2I(vecD dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (URShiftVI dst shift)); - format %{ "psrld $dst,$shift\t! logical right shift packed2I" %} - ins_encode %{ - __ psrld($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl2I_imm(vecD dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (URShiftVI dst shift)); - format %{ "psrld $dst,$shift\t! logical right shift packed2I" %} - ins_encode %{ - __ psrld($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl2I_reg(vecD dst, vecD src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); +// Integers vector left shift +instruct vshift2I(vecD dst, vecD src, vecS shift) %{ + predicate(n->as_Vector()->length() == 2); + match(Set dst (LShiftVI src shift)); + match(Set dst (RShiftVI src shift)); match(Set dst (URShiftVI src shift)); - format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %} + effect(TEMP dst, USE src, USE shift); + format %{ "vshiftd $dst,$src,$shift\t! shift packed2I" %} ins_encode %{ - int vector_len = 0; - __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + int opcode = this->as_Mach()->ideal_Opcode(); + if (UseAVX == 0) { + if ($dst$$XMMRegister != $src$$XMMRegister) + __ movdbl($dst$$XMMRegister, $src$$XMMRegister); + __ vshiftd(opcode, $dst$$XMMRegister, $shift$$XMMRegister); + } else { + int vector_len = 0; + __ vshiftd(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + } %} ins_pipe( pipe_slow ); %} -instruct vsrl2I_reg_imm(vecD dst, vecD src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); +instruct vshift4I(vecX dst, vecX src, vecS shift) %{ + predicate(n->as_Vector()->length() == 4); + match(Set dst (LShiftVI src shift)); + match(Set dst (RShiftVI src shift)); match(Set dst (URShiftVI src shift)); - format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %} + effect(TEMP dst, USE src, USE shift); + format %{ "vshiftd $dst,$src,$shift\t! shift packed4I" %} ins_encode %{ - int vector_len = 0; - __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); + int opcode = this->as_Mach()->ideal_Opcode(); + if (UseAVX == 0) { + if ($dst$$XMMRegister != $src$$XMMRegister) + __ movdqu($dst$$XMMRegister, $src$$XMMRegister); + __ vshiftd(opcode, $dst$$XMMRegister, $shift$$XMMRegister); + } else { + int vector_len = 0; + __ vshiftd(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + } %} ins_pipe( pipe_slow ); %} -instruct vsrl4I(vecX dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 4); - match(Set dst (URShiftVI dst shift)); - format %{ "psrld $dst,$shift\t! logical right shift packed4I" %} - ins_encode %{ - __ psrld($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl4I_imm(vecX dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 4); - match(Set dst (URShiftVI dst shift)); - format %{ "psrld $dst,$shift\t! logical right shift packed4I" %} - ins_encode %{ - __ psrld($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl4I_reg(vecX dst, vecX src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 4); - match(Set dst (URShiftVI src shift)); - format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %} - ins_encode %{ - int vector_len = 0; - __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl4I_reg_imm(vecX dst, vecX src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 4); - match(Set dst (URShiftVI src shift)); - format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %} - ins_encode %{ - int vector_len = 0; - __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl8I_reg(vecY dst, vecY src, vecS shift) %{ +instruct vshift8I(vecY dst, vecY src, vecS shift) %{ predicate(UseAVX > 1 && n->as_Vector()->length() == 8); + match(Set dst (LShiftVI src shift)); + match(Set dst (RShiftVI src shift)); match(Set dst (URShiftVI src shift)); - format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %} + effect(DEF dst, USE src, USE shift); + format %{ "vshiftd $dst,$src,$shift\t! shift packed8I" %} ins_encode %{ int vector_len = 1; - __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + int opcode = this->as_Mach()->ideal_Opcode(); + __ vshiftd(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); %} ins_pipe( pipe_slow ); %} -instruct vsrl8I_reg_imm(vecY dst, vecY src, immI8 shift) %{ - predicate(UseAVX > 1 && n->as_Vector()->length() == 8); +instruct vshift16I(vecZ dst, vecZ src, vecS shift) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 16); + match(Set dst (LShiftVI src shift)); + match(Set dst (RShiftVI src shift)); match(Set dst (URShiftVI src shift)); - format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %} + effect(DEF dst, USE src, USE shift); + format %{ "vshiftd $dst,$src,$shift\t! shift packed16I" %} + ins_encode %{ + int vector_len = 2; + int opcode = this->as_Mach()->ideal_Opcode(); + __ vshiftd(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +// Longs vector shift +instruct vshift2L(vecX dst, vecX src, vecS shift) %{ + predicate(n->as_Vector()->length() == 2); + match(Set dst (LShiftVL src shift)); + match(Set dst (URShiftVL src shift)); + effect(TEMP dst, USE src, USE shift); + format %{ "vshiftq $dst,$src,$shift\t! shift packed2L" %} + ins_encode %{ + int opcode = this->as_Mach()->ideal_Opcode(); + if (UseAVX == 0) { + if ($dst$$XMMRegister != $src$$XMMRegister) + __ movdqu($dst$$XMMRegister, $src$$XMMRegister); + __ vshiftq(opcode, $dst$$XMMRegister, $shift$$XMMRegister); + } else { + int vector_len = 0; + __ vshiftq(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + } + %} + ins_pipe( pipe_slow ); +%} + +instruct vshift4L(vecY dst, vecY src, vecS shift) %{ + predicate(UseAVX > 1 && n->as_Vector()->length() == 4); + match(Set dst (LShiftVL src shift)); + match(Set dst (URShiftVL src shift)); + effect(DEF dst, USE src, USE shift); + format %{ "vshiftq $dst,$src,$shift\t! left shift packed4L" %} ins_encode %{ int vector_len = 1; - __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); + int opcode = this->as_Mach()->ideal_Opcode(); + __ vshiftq(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); %} ins_pipe( pipe_slow ); %} -instruct vsrl16I_reg(vecZ dst, vecZ src, vecS shift) %{ - predicate(UseAVX > 2 && n->as_Vector()->length() == 16); - match(Set dst (URShiftVI src shift)); - format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed16I" %} +instruct vshift8L(vecZ dst, vecZ src, vecS shift) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 8); + match(Set dst (LShiftVL src shift)); + match(Set dst (RShiftVL src shift)); + match(Set dst (URShiftVL src shift)); + effect(DEF dst, USE src, USE shift); + format %{ "vshiftq $dst,$src,$shift\t! shift packed8L" %} ins_encode %{ int vector_len = 2; - __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + int opcode = this->as_Mach()->ideal_Opcode(); + __ vshiftq(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); %} ins_pipe( pipe_slow ); %} -instruct vsrl16I_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ - predicate(UseAVX > 2 && n->as_Vector()->length() == 16); - match(Set dst (URShiftVI src shift)); - format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed16I" %} +// -------------------ArithmeticRightShift ----------------------------------- +// Long vector arithmetic right shift +instruct vsra2L_reg(vecX dst, vecX src, vecS shift, vecX tmp, rRegI scratch) %{ + predicate(UseSSE >= 2 && n->as_Vector()->length() == 2); + match(Set dst (RShiftVL src shift)); + effect(TEMP dst, TEMP tmp, TEMP scratch); + format %{ "movdqu $dst,$src\n\t" + "psrlq $dst,$shift\n\t" + "movdqu $tmp,[0x8000000000000000]\n\t" + "psrlq $tmp,$shift\n\t" + "pxor $dst,$tmp\n\t" + "psubq $dst,$tmp\t! arithmetic right shift packed2L" %} ins_encode %{ - int vector_len = 2; - __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -// Longs vector logical right shift -instruct vsrl2L(vecX dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (URShiftVL dst shift)); - format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %} - ins_encode %{ + __ movdqu($dst$$XMMRegister, $src$$XMMRegister); __ psrlq($dst$$XMMRegister, $shift$$XMMRegister); + __ movdqu($tmp$$XMMRegister, ExternalAddress(vector_long_sign_mask()), $scratch$$Register); + __ psrlq($tmp$$XMMRegister, $shift$$XMMRegister); + __ pxor($dst$$XMMRegister, $tmp$$XMMRegister); + __ psubq($dst$$XMMRegister, $tmp$$XMMRegister); %} ins_pipe( pipe_slow ); %} -instruct vsrl2L_imm(vecX dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (URShiftVL dst shift)); - format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %} - ins_encode %{ - __ psrlq($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl2L_reg(vecX dst, vecX src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); - match(Set dst (URShiftVL src shift)); - format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %} +instruct vsra2L_reg_evex(vecX dst, vecX src, vecS shift) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 2); + match(Set dst (RShiftVL src shift)); + format %{ "evpsraq $dst,$src,$shift\t! arithmetic right shift packed2L" %} ins_encode %{ int vector_len = 0; - __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + __ evpsraq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); %} ins_pipe( pipe_slow ); %} -instruct vsrl2L_reg_imm(vecX dst, vecX src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); - match(Set dst (URShiftVL src shift)); - format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %} - ins_encode %{ - int vector_len = 0; - __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl4L_reg(vecY dst, vecY src, vecS shift) %{ +instruct vsra4L_reg(vecY dst, vecY src, vecS shift, vecY tmp, rRegI scratch) %{ predicate(UseAVX > 1 && n->as_Vector()->length() == 4); - match(Set dst (URShiftVL src shift)); - format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %} + match(Set dst (RShiftVL src shift)); + effect(TEMP dst, TEMP tmp, TEMP scratch); + format %{ "vpsrlq $dst,$src,$shift\n\t" + "vmovdqu $tmp,[0x8000000000000000]\n\t" + "vpsrlq $tmp,$tmp,$shift\n\t" + "vpxor $dst,$dst,$tmp\n\t" + "vpsubq $dst,$dst,$tmp\t! arithmetic right shift packed4L" %} ins_encode %{ int vector_len = 1; __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); + __ vmovdqu($tmp$$XMMRegister, ExternalAddress(vector_long_sign_mask()), $scratch$$Register); + __ vpsrlq($tmp$$XMMRegister, $tmp$$XMMRegister, $shift$$XMMRegister, vector_len); + __ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $tmp$$XMMRegister, vector_len); + __ vpsubq($dst$$XMMRegister, $dst$$XMMRegister, $tmp$$XMMRegister, vector_len); %} ins_pipe( pipe_slow ); %} -instruct vsrl4L_reg_imm(vecY dst, vecY src, immI8 shift) %{ - predicate(UseAVX > 1 && n->as_Vector()->length() == 4); - match(Set dst (URShiftVL src shift)); - format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %} +instruct vsra4L_reg_evex(vecY dst, vecY src, vecS shift) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 4); + match(Set dst (RShiftVL src shift)); + format %{ "evpsraq $dst,$src,$shift\t! arithmetic right shift packed4L" %} ins_encode %{ int vector_len = 1; - __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); + __ evpsraq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); %} ins_pipe( pipe_slow ); %} -instruct vsrl8L_reg(vecZ dst, vecZ src, vecS shift) %{ - predicate(UseAVX > 2 && n->as_Vector()->length() == 8); - match(Set dst (URShiftVL src shift)); - format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed8L" %} - ins_encode %{ - int vector_len = 2; - __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsrl8L_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ - predicate(UseAVX > 2 && n->as_Vector()->length() == 8); - match(Set dst (URShiftVL src shift)); - format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed8L" %} - ins_encode %{ - int vector_len = 2; - __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -// ------------------- ArithmeticRightShift ----------------------------------- - -// Shorts/Chars vector arithmetic right shift -instruct vsra2S(vecS dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (RShiftVS dst shift)); - format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %} - ins_encode %{ - __ psraw($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra2S_imm(vecS dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (RShiftVS dst shift)); - format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %} - ins_encode %{ - __ psraw($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra2S_reg(vecS dst, vecS src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); - match(Set dst (RShiftVS src shift)); - format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %} - ins_encode %{ - int vector_len = 0; - __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra2S_reg_imm(vecS dst, vecS src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); - match(Set dst (RShiftVS src shift)); - format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %} - ins_encode %{ - int vector_len = 0; - __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra4S(vecD dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 4); - match(Set dst (RShiftVS dst shift)); - format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %} - ins_encode %{ - __ psraw($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra4S_imm(vecD dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 4); - match(Set dst (RShiftVS dst shift)); - format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %} - ins_encode %{ - __ psraw($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra4S_reg(vecD dst, vecD src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 4); - match(Set dst (RShiftVS src shift)); - format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %} - ins_encode %{ - int vector_len = 0; - __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra4S_reg_imm(vecD dst, vecD src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 4); - match(Set dst (RShiftVS src shift)); - format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %} - ins_encode %{ - int vector_len = 0; - __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra8S(vecX dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 8); - match(Set dst (RShiftVS dst shift)); - format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %} - ins_encode %{ - __ psraw($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra8S_imm(vecX dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 8); - match(Set dst (RShiftVS dst shift)); - format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %} - ins_encode %{ - __ psraw($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra8S_reg(vecX dst, vecX src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 8); - match(Set dst (RShiftVS src shift)); - format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %} - ins_encode %{ - int vector_len = 0; - __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra8S_reg_imm(vecX dst, vecX src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 8); - match(Set dst (RShiftVS src shift)); - format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %} - ins_encode %{ - int vector_len = 0; - __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra16S_reg(vecY dst, vecY src, vecS shift) %{ - predicate(UseAVX > 1 && n->as_Vector()->length() == 16); - match(Set dst (RShiftVS src shift)); - format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %} - ins_encode %{ - int vector_len = 1; - __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra16S_reg_imm(vecY dst, vecY src, immI8 shift) %{ - predicate(UseAVX > 1 && n->as_Vector()->length() == 16); - match(Set dst (RShiftVS src shift)); - format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %} - ins_encode %{ - int vector_len = 1; - __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra32S_reg(vecZ dst, vecZ src, vecS shift) %{ - predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 32); - match(Set dst (RShiftVS src shift)); - format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed32S" %} - ins_encode %{ - int vector_len = 2; - __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra32S_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ - predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 32); - match(Set dst (RShiftVS src shift)); - format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed32S" %} - ins_encode %{ - int vector_len = 2; - __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -// Integers vector arithmetic right shift -instruct vsra2I(vecD dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (RShiftVI dst shift)); - format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %} - ins_encode %{ - __ psrad($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra2I_imm(vecD dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 2); - match(Set dst (RShiftVI dst shift)); - format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %} - ins_encode %{ - __ psrad($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra2I_reg(vecD dst, vecD src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); - match(Set dst (RShiftVI src shift)); - format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %} - ins_encode %{ - int vector_len = 0; - __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra2I_reg_imm(vecD dst, vecD src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 2); - match(Set dst (RShiftVI src shift)); - format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %} - ins_encode %{ - int vector_len = 0; - __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra4I(vecX dst, vecS shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 4); - match(Set dst (RShiftVI dst shift)); - format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %} - ins_encode %{ - __ psrad($dst$$XMMRegister, $shift$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra4I_imm(vecX dst, immI8 shift) %{ - predicate(UseAVX == 0 && n->as_Vector()->length() == 4); - match(Set dst (RShiftVI dst shift)); - format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %} - ins_encode %{ - __ psrad($dst$$XMMRegister, (int)$shift$$constant); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra4I_reg(vecX dst, vecX src, vecS shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 4); - match(Set dst (RShiftVI src shift)); - format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %} - ins_encode %{ - int vector_len = 0; - __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra4I_reg_imm(vecX dst, vecX src, immI8 shift) %{ - predicate(UseAVX > 0 && n->as_Vector()->length() == 4); - match(Set dst (RShiftVI src shift)); - format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %} - ins_encode %{ - int vector_len = 0; - __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra8I_reg(vecY dst, vecY src, vecS shift) %{ - predicate(UseAVX > 1 && n->as_Vector()->length() == 8); - match(Set dst (RShiftVI src shift)); - format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %} - ins_encode %{ - int vector_len = 1; - __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra8I_reg_imm(vecY dst, vecY src, immI8 shift) %{ - predicate(UseAVX > 1 && n->as_Vector()->length() == 8); - match(Set dst (RShiftVI src shift)); - format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %} - ins_encode %{ - int vector_len = 1; - __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra16I_reg(vecZ dst, vecZ src, vecS shift) %{ - predicate(UseAVX > 2 && n->as_Vector()->length() == 16); - match(Set dst (RShiftVI src shift)); - format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed16I" %} - ins_encode %{ - int vector_len = 2; - __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -instruct vsra16I_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ - predicate(UseAVX > 2 && n->as_Vector()->length() == 16); - match(Set dst (RShiftVI src shift)); - format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed16I" %} - ins_encode %{ - int vector_len = 2; - __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); - %} - ins_pipe( pipe_slow ); -%} - -// There are no longs vector arithmetic right shift instructions. - - // --------------------------------- AND -------------------------------------- instruct vand4B(vecS dst, vecS src) %{ @@ -9700,6 +9294,291 @@ ins_pipe( pipe_slow ); %} +// --------------------------------- ABS -------------------------------------- +// a = |a| +instruct vabs4B_reg(vecS dst, vecS src) %{ + predicate(UseSSE > 2 && n->as_Vector()->length() == 4); + match(Set dst (AbsVB src)); + format %{ "pabsb $dst,$src\t# $dst = |$src| abs packed4B" %} + ins_encode %{ + __ pabsb($dst$$XMMRegister, $src$$XMMRegister); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs8B_reg(vecD dst, vecD src) %{ + predicate(UseSSE > 2 && n->as_Vector()->length() == 8); + match(Set dst (AbsVB src)); + format %{ "pabsb $dst,$src\t# $dst = |$src| abs packed8B" %} + ins_encode %{ + __ pabsb($dst$$XMMRegister, $src$$XMMRegister); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs16B_reg(vecX dst, vecX src) %{ + predicate(UseSSE > 2 && n->as_Vector()->length() == 16); + match(Set dst (AbsVB src)); + format %{ "pabsb $dst,$src\t# $dst = |$src| abs packed16B" %} + ins_encode %{ + __ pabsb($dst$$XMMRegister, $src$$XMMRegister); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs32B_reg(vecY dst, vecY src) %{ + predicate(UseAVX > 1 && n->as_Vector()->length() == 32); + match(Set dst (AbsVB src)); + format %{ "vpabsb $dst,$src\t# $dst = |$src| abs packed32B" %} + ins_encode %{ + int vector_len = 1; + __ vpabsb($dst$$XMMRegister, $src$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs64B_reg(vecZ dst, vecZ src) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 64); + match(Set dst (AbsVB src)); + format %{ "vpabsb $dst,$src\t# $dst = |$src| abs packed64B" %} + ins_encode %{ + int vector_len = 2; + __ vpabsb($dst$$XMMRegister, $src$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs2S_reg(vecD dst, vecD src) %{ + predicate(UseSSE > 2 && n->as_Vector()->length() == 2); + match(Set dst (AbsVS src)); + format %{ "pabsw $dst,$src\t# $dst = |$src| abs packed2S" %} + ins_encode %{ + __ pabsw($dst$$XMMRegister, $src$$XMMRegister); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs4S_reg(vecD dst, vecD src) %{ + predicate(UseSSE > 2 && n->as_Vector()->length() == 4); + match(Set dst (AbsVS src)); + format %{ "pabsw $dst,$src\t# $dst = |$src| abs packed4S" %} + ins_encode %{ + __ pabsw($dst$$XMMRegister, $src$$XMMRegister); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs8S_reg(vecX dst, vecX src) %{ + predicate(UseSSE > 2 && n->as_Vector()->length() == 8); + match(Set dst (AbsVS src)); + format %{ "pabsw $dst,$src\t# $dst = |$src| abs packed8S" %} + ins_encode %{ + __ pabsw($dst$$XMMRegister, $src$$XMMRegister); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs16S_reg(vecY dst, vecY src) %{ + predicate(UseAVX > 1 && n->as_Vector()->length() == 16); + match(Set dst (AbsVS src)); + format %{ "vpabsw $dst,$src\t# $dst = |$src| abs packed16S" %} + ins_encode %{ + int vector_len = 1; + __ vpabsw($dst$$XMMRegister, $src$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs32S_reg(vecZ dst, vecZ src) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 32); + match(Set dst (AbsVS src)); + format %{ "vpabsw $dst,$src\t# $dst = |$src| abs packed32S" %} + ins_encode %{ + int vector_len = 2; + __ vpabsw($dst$$XMMRegister, $src$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs2I_reg(vecD dst, vecD src) %{ + predicate(UseSSE > 2 && n->as_Vector()->length() == 2); + match(Set dst (AbsVI src)); + format %{ "pabsd $dst,$src\t# $dst = |$src| abs packed2I" %} + ins_encode %{ + __ pabsd($dst$$XMMRegister, $src$$XMMRegister); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs4I_reg(vecX dst, vecX src) %{ + predicate(UseSSE > 2 && n->as_Vector()->length() == 4); + match(Set dst (AbsVI src)); + format %{ "pabsd $dst,$src\t# $dst = |$src| abs packed4I" %} + ins_encode %{ + __ pabsd($dst$$XMMRegister, $src$$XMMRegister); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs8I_reg(vecY dst, vecY src) %{ + predicate(UseAVX > 0 && n->as_Vector()->length() == 8); + match(Set dst (AbsVI src)); + format %{ "vpabsd $dst,$src\t# $dst = |$src| abs packed8I" %} + ins_encode %{ + int vector_len = 1; + __ vpabsd($dst$$XMMRegister, $src$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs16I_reg(vecZ dst, vecZ src) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 16); + match(Set dst (AbsVI src)); + format %{ "vpabsd $dst,$src\t# $dst = |$src| abs packed16I" %} + ins_encode %{ + int vector_len = 2; + __ vpabsd($dst$$XMMRegister, $src$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs2L_reg(vecX dst, vecX src) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 2); + match(Set dst (AbsVL src)); + format %{ "evpabsq $dst,$src\t# $dst = |$src| abs packed2L" %} + ins_encode %{ + int vector_len = 0; + __ evpabsq($dst$$XMMRegister, $src$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs4L_reg(vecY dst, vecY src) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 4); + match(Set dst (AbsVL src)); + format %{ "evpabsq $dst,$src\t# $dst = |$src| abs packed4L" %} + ins_encode %{ + int vector_len = 1; + __ evpabsq($dst$$XMMRegister, $src$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabs8L_reg(vecZ dst, vecZ src) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 8); + match(Set dst (AbsVL src)); + format %{ "evpabsq $dst,$src\t# $dst = |$src| abs packed8L" %} + ins_encode %{ + int vector_len = 2; + __ evpabsq($dst$$XMMRegister, $src$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +// --------------------------------- ABSNEG -------------------------------------- + +instruct vabsneg2D(vecX dst, vecX src, rRegI scratch) %{ + predicate(UseSSE >= 2 && n->as_Vector()->length() == 2); + match(Set dst (AbsVD src)); + match(Set dst (NegVD src)); + effect(TEMP scratch); + format %{ "vabsnegd $dst,$src,[mask]\t# absneg packed2D" %} + ins_encode %{ + int opcode = this->as_Mach()->ideal_Opcode(); + if ($dst$$XMMRegister != $src$$XMMRegister) + __ movdqu($dst$$XMMRegister, $src$$XMMRegister); + __ vabsnegd(opcode, $dst$$XMMRegister, $scratch$$Register); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabsneg4D(vecY dst, vecY src, rRegI scratch) %{ + predicate(UseAVX > 0 && n->as_Vector()->length() == 4); + match(Set dst (AbsVD src)); + match(Set dst (NegVD src)); + effect(TEMP scratch); + format %{ "vabsnegd $dst,$src,[mask]\t# absneg packed4D" %} + ins_encode %{ + int opcode = this->as_Mach()->ideal_Opcode(); + int vector_len = 1; + __ vabsnegd(opcode, $dst$$XMMRegister, $src$$XMMRegister, vector_len, $scratch$$Register); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabsneg8D(vecZ dst, vecZ src, rRegI scratch) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 8); + match(Set dst (AbsVD src)); + match(Set dst (NegVD src)); + effect(TEMP scratch); + format %{ "vabsnegd $dst,$src,[mask]\t# absneg packed8D" %} + ins_encode %{ + int opcode = this->as_Mach()->ideal_Opcode(); + int vector_len = 2; + __ vabsnegd(opcode, $dst$$XMMRegister, $src$$XMMRegister, vector_len, $scratch$$Register); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabsneg2F(vecD dst, vecD src, rRegI scratch) %{ + predicate(UseSSE > 0 && n->as_Vector()->length() == 2); + match(Set dst (AbsVF src)); + match(Set dst (NegVF src)); + effect(TEMP scratch); + format %{ "vabsnegf $dst,$src,[mask]\t# absneg packed2F" %} + ins_encode %{ + int opcode = this->as_Mach()->ideal_Opcode(); + if ($dst$$XMMRegister != $src$$XMMRegister) + __ movdqu($dst$$XMMRegister, $src$$XMMRegister); + __ vabsnegf(opcode, $dst$$XMMRegister, $scratch$$Register); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabsneg4F(vecX dst, rRegI scratch) %{ + predicate(UseSSE > 0 && n->as_Vector()->length() == 4); + match(Set dst (AbsVF dst)); + match(Set dst (NegVF dst)); + effect(TEMP scratch); + format %{ "vabsnegf $dst,[mask]\t# absneg packed4F" %} + ins_cost(150); + ins_encode %{ + int opcode = this->as_Mach()->ideal_Opcode(); + __ vabsnegf(opcode, $dst$$XMMRegister, $scratch$$Register); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabsneg8F(vecY dst, vecY src, rRegI scratch) %{ + predicate(UseAVX > 0 && n->as_Vector()->length() == 8); + match(Set dst (AbsVF src)); + match(Set dst (NegVF src)); + effect(TEMP scratch); + format %{ "vabsnegf $dst,$src,[mask]\t# absneg packed8F" %} + ins_cost(150); + ins_encode %{ + int opcode = this->as_Mach()->ideal_Opcode(); + int vector_len = 1; + __ vabsnegf(opcode, $dst$$XMMRegister, $src$$XMMRegister, vector_len, $scratch$$Register); + %} + ins_pipe( pipe_slow ); +%} + +instruct vabsneg16F(vecZ dst, vecZ src, rRegI scratch) %{ + predicate(UseAVX > 2 && n->as_Vector()->length() == 16); + match(Set dst (AbsVF src)); + match(Set dst (NegVF src)); + effect(TEMP scratch); + format %{ "vabsnegf $dst,$src,[mask]\t# absneg packed16F" %} + ins_cost(150); + ins_encode %{ + int opcode = this->as_Mach()->ideal_Opcode(); + int vector_len = 2; + __ vabsnegf(opcode, $dst$$XMMRegister, $src$$XMMRegister, vector_len, $scratch$$Register); + %} + ins_pipe( pipe_slow ); +%} + // --------------------------------- FMA -------------------------------------- // a * b + c
diff --git a/src/hotspot/cpu/x86/x86_32.ad b/src/hotspot/cpu/x86/x86_32.ad index c948b8c..c41b323 100644 --- a/src/hotspot/cpu/x86/x86_32.ad +++ b/src/hotspot/cpu/x86/x86_32.ad
@@ -311,7 +311,7 @@ int MachCallRuntimeNode::ret_addr_offset() { assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); - return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size(); + return 5 + pre_call_resets_size() + (_leaf_no_fp ? 0 : sizeof_FFree_Float_Stack_All); } // Indicate if the safepoint node needs the polling page as an input. @@ -7324,7 +7324,6 @@ ins_pipe( empty ); %} - // Load-locked - same as a regular pointer load when used with compare-swap instruct loadPLocked(eRegP dst, memory mem) %{ match(Set dst (LoadPLocked mem)); @@ -8949,6 +8948,28 @@ ins_pipe(ialu_reg_reg_alu0); %} +// Integer Absolute Instructions +instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, eFlagsReg cr) +%{ + match(Set dst (AbsI src)); + effect(TEMP dst, TEMP tmp, KILL cr); + format %{ "movl $tmp, $src\n\t" + "sarl $tmp, 31\n\t" + "movl $dst, $src\n\t" + "xorl $dst, $tmp\n\t" + "subl $dst, $tmp\n" + %} + ins_encode %{ + __ movl($tmp$$Register, $src$$Register); + __ sarl($tmp$$Register, 31); + __ movl($dst$$Register, $src$$Register); + __ xorl($dst$$Register, $tmp$$Register); + __ subl($dst$$Register, $tmp$$Register); + %} + + ins_pipe(ialu_reg_reg); +%} + //----------Long Instructions------------------------------------------------ // Add Long Register with Register instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
diff --git a/src/hotspot/cpu/x86/x86_64.ad b/src/hotspot/cpu/x86/x86_64.ad index 1e58087..62d167b 100644 --- a/src/hotspot/cpu/x86/x86_64.ad +++ b/src/hotspot/cpu/x86/x86_64.ad
@@ -826,6 +826,87 @@ __ bind(done); } +// Math.min() # Math.max() +// -------------------------- +// ucomis[s/d] # +// ja -> b # a +// jp -> NaN # NaN +// jb -> a # b +// je # +// |-jz -> a | b # a & b +// | -> a # +void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst, + XMMRegister a, XMMRegister b, + XMMRegister xmmt, Register rt, + bool min, bool single) { + + Label nan, zero, below, above, done; + + if (single) + __ ucomiss(a, b); + else + __ ucomisd(a, b); + + if (dst->encoding() != (min ? b : a)->encoding()) + __ jccb(Assembler::above, above); // CF=0 & ZF=0 + else + __ jccb(Assembler::above, done); + + __ jccb(Assembler::parity, nan); // PF=1 + __ jccb(Assembler::below, below); // CF=1 + + // equal + __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit); + if (single) { + __ ucomiss(a, xmmt); + __ jccb(Assembler::equal, zero); + + __ movflt(dst, a); + __ jmp(done); + } + else { + __ ucomisd(a, xmmt); + __ jccb(Assembler::equal, zero); + + __ movdbl(dst, a); + __ jmp(done); + } + + __ bind(zero); + if (min) + __ vpor(dst, a, b, Assembler::AVX_128bit); + else + __ vpand(dst, a, b, Assembler::AVX_128bit); + + __ jmp(done); + + __ bind(above); + if (single) + __ movflt(dst, min ? b : a); + else + __ movdbl(dst, min ? b : a); + + __ jmp(done); + + __ bind(nan); + if (single) { + __ movl(rt, 0x7fc00000); // Float.NaN + __ movdl(dst, rt); + } + else { + __ mov64(rt, 0x7ff8000000000000L); // Double.NaN + __ movdq(dst, rt); + } + __ jmp(done); + + __ bind(below); + if (single) + __ movflt(dst, min ? a : b); + else + __ movdbl(dst, min ? a : b); + + __ bind(done); +} //============================================================================= const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; @@ -3679,6 +3760,15 @@ %} // Float register operands +operand legRegF() %{ + constraint(ALLOC_IN_RC(float_reg_legacy)); + match(RegF); + + format %{ %} + interface(REG_INTER); +%} + +// Float register operands operand vlRegF() %{ constraint(ALLOC_IN_RC(float_reg_vl)); match(RegF); @@ -3697,6 +3787,15 @@ %} // Double register operands +operand legRegD() %{ + constraint(ALLOC_IN_RC(double_reg_legacy)); + match(RegD); + + format %{ %} + interface(REG_INTER); +%} + +// Double register operands operand vlRegD() %{ constraint(ALLOC_IN_RC(double_reg_vl)); match(RegD); @@ -5371,6 +5470,16 @@ %} // Load Float +instruct MoveF2LEG(legRegF dst, regF src) %{ + match(Set dst src); + format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %} + ins_encode %{ + __ movflt($dst$$XMMRegister, $src$$XMMRegister); + %} + ins_pipe( fpu_reg_reg ); +%} + +// Load Float instruct MoveVL2F(regF dst, vlRegF src) %{ match(Set dst src); format %{ "movss $dst,$src\t! load float (4 bytes)" %} @@ -5380,6 +5489,16 @@ ins_pipe( fpu_reg_reg ); %} +// Load Float +instruct MoveLEG2F(regF dst, legRegF src) %{ + match(Set dst src); + format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %} + ins_encode %{ + __ movflt($dst$$XMMRegister, $src$$XMMRegister); + %} + ins_pipe( fpu_reg_reg ); +%} + // Load Double instruct loadD_partial(regD dst, memory mem) %{ @@ -5418,6 +5537,16 @@ %} // Load Double +instruct MoveD2LEG(legRegD dst, regD src) %{ + match(Set dst src); + format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %} + ins_encode %{ + __ movdbl($dst$$XMMRegister, $src$$XMMRegister); + %} + ins_pipe( fpu_reg_reg ); +%} + +// Load Double instruct MoveVL2D(regD dst, vlRegD src) %{ match(Set dst src); format %{ "movsd $dst,$src\t! load double (8 bytes)" %} @@ -5427,6 +5556,167 @@ ins_pipe( fpu_reg_reg ); %} +// Load Double +instruct MoveLEG2D(regD dst, legRegD src) %{ + match(Set dst src); + format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %} + ins_encode %{ + __ movdbl($dst$$XMMRegister, $src$$XMMRegister); + %} + ins_pipe( fpu_reg_reg ); +%} + +// Following pseudo code describes the algorithm for max[FD]: +// Min algorithm is on similar lines +// btmp = (b < +0.0) ? a : b +// atmp = (b < +0.0) ? b : a +// Tmp = Max_Float(atmp , btmp) +// Res = (atmp == NaN) ? atmp : Tmp + +// max = java.lang.Math.max(float a, float b) +instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{ + predicate(UseAVX > 0 && !n->is_reduction()); + match(Set dst (MaxF a b)); + effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp); + format %{ + "blendvps $btmp,$b,$a,$b \n\t" + "blendvps $atmp,$a,$b,$b \n\t" + "vmaxss $tmp,$atmp,$btmp \n\t" + "cmpps.unordered $btmp,$atmp,$atmp \n\t" + "blendvps $dst,$tmp,$atmp,$btmp \n\t" + %} + ins_encode %{ + int vector_len = Assembler::AVX_128bit; + __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len); + __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len); + __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister); + __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len); + __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{ + predicate(UseAVX > 0 && n->is_reduction()); + match(Set dst (MaxF a b)); + effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); + + format %{ "$dst = max($a, $b)\t# intrinsic (float)" %} + ins_encode %{ + emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register, + false /*min*/, true /*single*/); + %} + ins_pipe( pipe_slow ); +%} + +// max = java.lang.Math.max(double a, double b) +instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{ + predicate(UseAVX > 0 && !n->is_reduction()); + match(Set dst (MaxD a b)); + effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp); + format %{ + "blendvpd $btmp,$b,$a,$b \n\t" + "blendvpd $atmp,$a,$b,$b \n\t" + "vmaxsd $tmp,$atmp,$btmp \n\t" + "cmppd.unordered $btmp,$atmp,$atmp \n\t" + "blendvpd $dst,$tmp,$atmp,$btmp \n\t" + %} + ins_encode %{ + int vector_len = Assembler::AVX_128bit; + __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len); + __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len); + __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister); + __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len); + __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{ + predicate(UseAVX > 0 && n->is_reduction()); + match(Set dst (MaxD a b)); + effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); + + format %{ "$dst = max($a, $b)\t# intrinsic (double)" %} + ins_encode %{ + emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register, + false /*min*/, false /*single*/); + %} + ins_pipe( pipe_slow ); +%} + +// min = java.lang.Math.min(float a, float b) +instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{ + predicate(UseAVX > 0 && !n->is_reduction()); + match(Set dst (MinF a b)); + effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp); + format %{ + "blendvps $atmp,$a,$b,$a \n\t" + "blendvps $btmp,$b,$a,$a \n\t" + "vminss $tmp,$atmp,$btmp \n\t" + "cmpps.unordered $btmp,$atmp,$atmp \n\t" + "blendvps $dst,$tmp,$atmp,$btmp \n\t" + %} + ins_encode %{ + int vector_len = Assembler::AVX_128bit; + __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len); + __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len); + __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister); + __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len); + __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{ + predicate(UseAVX > 0 && n->is_reduction()); + match(Set dst (MinF a b)); + effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); + + format %{ "$dst = min($a, $b)\t# intrinsic (float)" %} + ins_encode %{ + emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register, + true /*min*/, true /*single*/); + %} + ins_pipe( pipe_slow ); +%} + +// min = java.lang.Math.min(double a, double b) +instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{ + predicate(UseAVX > 0 && !n->is_reduction()); + match(Set dst (MinD a b)); + effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp); + format %{ + "blendvpd $atmp,$a,$b,$a \n\t" + "blendvpd $btmp,$b,$a,$a \n\t" + "vminsd $tmp,$atmp,$btmp \n\t" + "cmppd.unordered $btmp,$atmp,$atmp \n\t" + "blendvpd $dst,$tmp,$atmp,$btmp \n\t" + %} + ins_encode %{ + int vector_len = Assembler::AVX_128bit; + __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len); + __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len); + __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister); + __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len); + __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); + %} + ins_pipe( pipe_slow ); +%} + +instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{ + predicate(UseAVX > 0 && n->is_reduction()); + match(Set dst (MinD a b)); + effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); + + format %{ "$dst = min($a, $b)\t# intrinsic (double)" %} + ins_encode %{ + emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register, + true /*min*/, false /*single*/); + %} + ins_pipe( pipe_slow ); +%} + // Load Effective Address instruct leaP8(rRegP dst, indOffset8 mem) %{ @@ -7963,6 +8253,52 @@ ins_pipe( pipe_cmpxchg ); %} +//----------Abs Instructions------------------------------------------- + +// Integer Absolute Instructions +instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, rFlagsReg cr) +%{ + match(Set dst (AbsI src)); + effect(TEMP dst, TEMP tmp, KILL cr); + format %{ "movl $tmp, $src\n\t" + "sarl $tmp, 31\n\t" + "movl $dst, $src\n\t" + "xorl $dst, $tmp\n\t" + "subl $dst, $tmp\n" + %} + ins_encode %{ + __ movl($tmp$$Register, $src$$Register); + __ sarl($tmp$$Register, 31); + __ movl($dst$$Register, $src$$Register); + __ xorl($dst$$Register, $tmp$$Register); + __ subl($dst$$Register, $tmp$$Register); + %} + + ins_pipe(ialu_reg_reg); +%} + +// Long Absolute Instructions +instruct absL_rReg(rRegL dst, rRegL src, rRegL tmp, rFlagsReg cr) +%{ + match(Set dst (AbsL src)); + effect(TEMP dst, TEMP tmp, KILL cr); + format %{ "movq $tmp, $src\n\t" + "sarq $tmp, 63\n\t" + "movq $dst, $src\n\t" + "xorq $dst, $tmp\n\t" + "subq $dst, $tmp\n" + %} + ins_encode %{ + __ movq($tmp$$Register, $src$$Register); + __ sarq($tmp$$Register, 63); + __ movq($dst$$Register, $src$$Register); + __ xorq($dst$$Register, $tmp$$Register); + __ subq($dst$$Register, $tmp$$Register); + %} + + ins_pipe(ialu_reg_reg); +%} + //----------Subtraction Instructions------------------------------------------- // Integer Subtraction Instructions
diff --git a/src/hotspot/cpu/zero/cppInterpreter_zero.cpp b/src/hotspot/cpu/zero/cppInterpreter_zero.cpp index 0d2ef9f..9331d02 100644 --- a/src/hotspot/cpu/zero/cppInterpreter_zero.cpp +++ b/src/hotspot/cpu/zero/cppInterpreter_zero.cpp
@@ -100,7 +100,9 @@ case T_DOUBLE: case T_VOID: return result; - default : ShouldNotReachHere(); + default: + ShouldNotReachHere(); + return result; // silence compiler warnings } } @@ -558,6 +560,9 @@ break; } if (entry->is_volatile()) { + if (support_IRIW_for_not_multiple_copy_atomic_cpu) { + OrderAccess::fence(); + } switch (entry->flag_state()) { case ctos: SET_LOCALS_INT(object->char_field_acquire(entry->f2_as_index()), 0);
diff --git a/src/hotspot/cpu/zero/globals_zero.hpp b/src/hotspot/cpu/zero/globals_zero.hpp index d594543..49b39ff 100644 --- a/src/hotspot/cpu/zero/globals_zero.hpp +++ b/src/hotspot/cpu/zero/globals_zero.hpp
@@ -32,7 +32,6 @@ // Set the default values for platform dependent flags used by the // runtime system. See globals.hpp for details of what they do. -define_pd_global(bool, ShareVtableStubs, true); define_pd_global(bool, NeedsDeoptSuspend, false); define_pd_global(bool, ImplicitNullChecks, true);
diff --git a/src/hotspot/cpu/zero/register_zero.hpp b/src/hotspot/cpu/zero/register_zero.hpp index 1ce7141..64e9336 100644 --- a/src/hotspot/cpu/zero/register_zero.hpp +++ b/src/hotspot/cpu/zero/register_zero.hpp
@@ -27,7 +27,7 @@ #define CPU_ZERO_VM_REGISTER_ZERO_HPP #include "asm/register.hpp" -#include "vm_version_zero.hpp" +#include "runtime/vm_version.hpp" class VMRegImpl; typedef VMRegImpl* VMReg;
diff --git a/src/hotspot/cpu/zero/sharedRuntime_zero.cpp b/src/hotspot/cpu/zero/sharedRuntime_zero.cpp index eab37fc..12b66b7 100644 --- a/src/hotspot/cpu/zero/sharedRuntime_zero.cpp +++ b/src/hotspot/cpu/zero/sharedRuntime_zero.cpp
@@ -75,7 +75,8 @@ int compile_id, BasicType *sig_bt, VMRegPair *regs, - BasicType ret_type) { + BasicType ret_type, + address critical_entry) { ShouldNotCallThis(); return NULL; }
diff --git a/src/hotspot/cpu/zero/stack_zero.cpp b/src/hotspot/cpu/zero/stack_zero.cpp index 075fb5d..1f4b057 100644 --- a/src/hotspot/cpu/zero/stack_zero.cpp +++ b/src/hotspot/cpu/zero/stack_zero.cpp
@@ -26,7 +26,7 @@ #include "precompiled.hpp" #include "interpreter/bytecodeInterpreter.hpp" #include "interpreter/interpreterRuntime.hpp" -#include "runtime/thread.hpp" +#include "runtime/thread.inline.hpp" #include "stack_zero.hpp" #include "stack_zero.inline.hpp" #include "runtime/frame.inline.hpp"
diff --git a/src/hotspot/cpu/zero/vm_version_ext_zero.hpp b/src/hotspot/cpu/zero/vm_version_ext_zero.hpp index f44c602..a1efc7b 100644 --- a/src/hotspot/cpu/zero/vm_version_ext_zero.hpp +++ b/src/hotspot/cpu/zero/vm_version_ext_zero.hpp
@@ -25,8 +25,8 @@ #ifndef CPU_ZERO_VM_VM_VERSION_EXT_ZERO_HPP #define CPU_ZERO_VM_VM_VERSION_EXT_ZERO_HPP +#include "runtime/vm_version.hpp" #include "utilities/macros.hpp" -#include "vm_version_zero.hpp" class VM_Version_Ext : public VM_Version { private:
diff --git a/src/hotspot/cpu/zero/vm_version_zero.cpp b/src/hotspot/cpu/zero/vm_version_zero.cpp index eb74a00..6f8519a 100644 --- a/src/hotspot/cpu/zero/vm_version_zero.cpp +++ b/src/hotspot/cpu/zero/vm_version_zero.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. * Copyright 2009 Red Hat, Inc. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * @@ -28,7 +28,7 @@ #include "memory/resourceArea.hpp" #include "runtime/java.hpp" #include "runtime/stubCodeGenerator.hpp" -#include "vm_version_zero.hpp" +#include "runtime/vm_version.hpp" void VM_Version::initialize() {
diff --git a/src/hotspot/cpu/zero/vm_version_zero.hpp b/src/hotspot/cpu/zero/vm_version_zero.hpp index 51b9c5b..9fd2beb 100644 --- a/src/hotspot/cpu/zero/vm_version_zero.hpp +++ b/src/hotspot/cpu/zero/vm_version_zero.hpp
@@ -26,8 +26,8 @@ #ifndef CPU_ZERO_VM_VM_VERSION_ZERO_HPP #define CPU_ZERO_VM_VM_VERSION_ZERO_HPP +#include "runtime/abstract_vm_version.hpp" #include "runtime/globals_extension.hpp" -#include "runtime/vm_version.hpp" class VM_Version : public Abstract_VM_Version { public:
diff --git a/src/hotspot/os/aix/attachListener_aix.cpp b/src/hotspot/os/aix/attachListener_aix.cpp index 18c7f57..ab81bec 100644 --- a/src/hotspot/os/aix/attachListener_aix.cpp +++ b/src/hotspot/os/aix/attachListener_aix.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2005, 2020, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2012, 2018 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * @@ -66,22 +66,12 @@ static char _path[UNIX_PATH_MAX]; static bool _has_path; // Shutdown marker to prevent accept blocking during clean-up. - static bool _shutdown; + static volatile bool _shutdown; // the file descriptor for the listening socket - static int _listener; + static volatile int _listener; - static void set_path(char* path) { - if (path == NULL) { - _has_path = false; - } else { - strncpy(_path, path, UNIX_PATH_MAX); - _path[UNIX_PATH_MAX-1] = '\0'; - _has_path = true; - } - } - - static void set_listener(int s) { _listener = s; } + static bool _atexit_registered; // reads a request from the given connected socket static AixAttachOperation* read_request(int s); @@ -94,6 +84,19 @@ ATTACH_ERROR_BADVERSION = 101 // error codes }; + static void set_path(char* path) { + if (path == NULL) { + _path[0] = '\0'; + _has_path = false; + } else { + strncpy(_path, path, UNIX_PATH_MAX); + _path[UNIX_PATH_MAX-1] = '\0'; + _has_path = true; + } + } + + static void set_listener(int s) { _listener = s; } + // initialize the listener, returns 0 if okay static int init(); @@ -129,9 +132,10 @@ // statics char AixAttachListener::_path[UNIX_PATH_MAX]; bool AixAttachListener::_has_path; -int AixAttachListener::_listener = -1; +volatile int AixAttachListener::_listener = -1; +bool AixAttachListener::_atexit_registered = false; // Shutdown marker to prevent accept blocking during clean-up -bool AixAttachListener::_shutdown = false; +volatile bool AixAttachListener::_shutdown = false; // Supporting class to help split a buffer into individual components class ArgumentIterator : public StackObj { @@ -177,17 +181,14 @@ // should be sufficient for cleanup. extern "C" { static void listener_cleanup() { - static int cleanup_done; - if (!cleanup_done) { - cleanup_done = 1; - AixAttachListener::set_shutdown(true); - int s = AixAttachListener::listener(); - if (s != -1) { - ::shutdown(s, 2); - } - if (AixAttachListener::has_path()) { - ::unlink(AixAttachListener::path()); - } + AixAttachListener::set_shutdown(true); + int s = AixAttachListener::listener(); + if (s != -1) { + ::shutdown(s, 2); + } + if (AixAttachListener::has_path()) { + ::unlink(AixAttachListener::path()); + AixAttachListener::set_path(NULL); } } } @@ -200,7 +201,10 @@ int listener; // listener socket (file descriptor) // register function to cleanup - ::atexit(listener_cleanup); + if (!_atexit_registered) { + _atexit_registered = true; + ::atexit(listener_cleanup); + } int n = snprintf(path, UNIX_PATH_MAX, "%s/.java_pid%d", os::get_temp_directory(), os::current_process_id()); @@ -371,10 +375,14 @@ // We must prevent accept blocking on the socket if it has been shut down. // Therefore we allow interrupts and check whether we have been shut down already. if (AixAttachListener::is_shutdown()) { + ::close(listener()); + set_listener(-1); return NULL; } - s=::accept(listener(), &addr, &len); + s = ::accept(listener(), &addr, &len); if (s == -1) { + ::close(listener()); + set_listener(-1); return NULL; // log a warning? } @@ -515,6 +523,30 @@ return ret_code; } +bool AttachListener::check_socket_file() { + int ret; + struct stat64 st; + ret = stat64(AixAttachListener::path(), &st); + if (ret == -1) { // need to restart attach listener. + log_debug(attach)("Socket file %s does not exist - Restart Attach Listener", + AixAttachListener::path()); + + listener_cleanup(); + + // wait to terminate current attach listener instance... + { + // avoid deadlock if AttachListener thread is blocked at safepoint + ThreadBlockInVM tbivm(JavaThread::current()); + while (AttachListener::transit_state(AL_INITIALIZING, + AL_NOT_INITIALIZED) != AL_NOT_INITIALIZED) { + os::naked_yield(); + } + } + return is_init_trigger(); + } + return false; +} + // Attach Listener is started lazily except in the case when // +ReduseSignalUsage is used bool AttachListener::init_at_startup() {
diff --git a/src/hotspot/os/aix/libodm_aix.cpp b/src/hotspot/os/aix/libodm_aix.cpp index af998b8..1306ddb 100644 --- a/src/hotspot/os/aix/libodm_aix.cpp +++ b/src/hotspot/os/aix/libodm_aix.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2015, 2015 SAP SE. All rights reserved. + * Copyright (c) 2015, 2019, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2019 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -59,7 +59,7 @@ void odmWrapper::clean_data() { if (_data) { free(_data); _data = NULL; } } -int odmWrapper::class_offset(char *field, bool is_aix_5) +int odmWrapper::class_offset(const char *field, bool is_aix_5) { assert(has_class(), "initialization"); for (int i = 0; i < odm_class()->nelem; i++) {
diff --git a/src/hotspot/os/aix/libodm_aix.hpp b/src/hotspot/os/aix/libodm_aix.hpp index 920b58f..d9dbad6 100644 --- a/src/hotspot/os/aix/libodm_aix.hpp +++ b/src/hotspot/os/aix/libodm_aix.hpp
@@ -1,6 +1,6 @@ /* * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2015, 2015 SAP SE. All rights reserved. + * Copyright (c) 2015, 2019 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -68,13 +68,15 @@ public: // Make sure everything gets initialized and cleaned up properly. - explicit odmWrapper(char* odm_class_name, char* odm_path = NULL) : _odm_class((CLASS_SYMBOL)-1), + explicit odmWrapper(const char* odm_class_name, const char* odm_path = NULL) : _odm_class((CLASS_SYMBOL)-1), _data(NULL), _initialized(false) { if (!odm_loaded()) { return; } _initialized = ((*_odm_initialize)() != -1); if (_initialized) { - if (odm_path) { (*_odm_set_path)(odm_path); } - _odm_class = (*_odm_mount_class)(odm_class_name); + // should we free what odm_set_path returns, man page suggests it + // see https://www.ibm.com/support/knowledgecenter/en/ssw_aix_71/o_bostechref/odm_set_path.html + if (odm_path) { (*_odm_set_path)((char*)odm_path); } + _odm_class = (*_odm_mount_class)((char*)odm_class_name); } } ~odmWrapper() { @@ -83,12 +85,12 @@ CLASS_SYMBOL odm_class() { return _odm_class; } bool has_class() { return odm_class() != (CLASS_SYMBOL)-1; } - int class_offset(char *field, bool is_aix_5); + int class_offset(const char *field, bool is_aix_5); char* data() { return _data; } - char* retrieve_obj(char* name = NULL) { + char* retrieve_obj(const char* name = NULL) { clean_data(); - char *cnp = (char*)(void*)(*_odm_get_obj)(odm_class(), name, NULL, (name == NULL) ? ODM_NEXT : ODM_FIRST); + char *cnp = (char*)(void*)(*_odm_get_obj)(odm_class(), (char*) name, NULL, (name == NULL) ? ODM_NEXT : ODM_FIRST); if (cnp != (char*)-1) { _data = cnp; } return data(); }
diff --git a/src/hotspot/os/aix/loadlib_aix.cpp b/src/hotspot/os/aix/loadlib_aix.cpp index d6e5821..9ac761f 100644 --- a/src/hotspot/os/aix/loadlib_aix.cpp +++ b/src/hotspot/os/aix/loadlib_aix.cpp
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2015 SAP SE. All rights reserved. + * Copyright (c) 2017, 2019, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2019 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -207,7 +207,7 @@ } } - trcVerbose("loadquery buffer size is %llu.", buflen); + trcVerbose("loadquery buffer size is " SIZE_FORMAT ".", buflen); // Iterate over the loadquery result. For details see sys/ldr.h on AIX. ldi = (struct ld_info*) buffer; @@ -264,7 +264,7 @@ e->info.is_in_vm = true; } - trcVerbose("entry: %p %llu, %p %llu, %s %s %s, %d", + trcVerbose("entry: %p " SIZE_FORMAT ", %p " SIZE_FORMAT ", %s %s %s, %d", e->info.text, e->info.text_len, e->info.data, e->info.data_len, e->info.path, e->info.shortname,
diff --git a/src/hotspot/os/aix/os_aix.cpp b/src/hotspot/os/aix/os_aix.cpp index e0c8b7f..44a05ae 100644 --- a/src/hotspot/os/aix/os_aix.cpp +++ b/src/hotspot/os/aix/os_aix.cpp
@@ -1,6 +1,6 @@ /* * Copyright (c) 1999, 2018, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2018 SAP SE. All rights reserved. + * Copyright (c) 2012, 2019 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -37,6 +37,7 @@ #include "compiler/compileBroker.hpp" #include "interpreter/interpreter.hpp" #include "logging/log.hpp" +#include "logging/logStream.hpp" #include "libo4.hpp" #include "libperfstat_aix.hpp" #include "libodm_aix.hpp" @@ -131,18 +132,6 @@ #define ERROR_MP_VMGETINFO_CLAIMS_NO_SUPPORT_FOR_64K 103 // excerpts from systemcfg.h that might be missing on older os levels -#ifndef PV_5_Compat - #define PV_5_Compat 0x0F8000 /* Power PC 5 */ -#endif -#ifndef PV_6 - #define PV_6 0x100000 /* Power PC 6 */ -#endif -#ifndef PV_6_1 - #define PV_6_1 0x100001 /* Power PC 6 DD1.x */ -#endif -#ifndef PV_6_Compat - #define PV_6_Compat 0x108000 /* Power PC 6 */ -#endif #ifndef PV_7 #define PV_7 0x200000 /* Power PC 7 */ #endif @@ -155,6 +144,13 @@ #ifndef PV_8_Compat #define PV_8_Compat 0x308000 /* Power PC 8 */ #endif +#ifndef PV_9 + #define PV_9 0x400000 /* Power PC 9 */ +#endif +#ifndef PV_9_Compat + #define PV_9_Compat 0x408000 /* Power PC 9 */ +#endif + static address resolve_function_descriptor_to_code_pointer(address p); @@ -486,8 +482,7 @@ if (::shmctl(shmid, SHM_PAGESIZE, &shm_buf) != 0) { const int en = errno; ::shmctl(shmid, IPC_RMID, NULL); // As early as possible! - trcVerbose("shmctl(SHM_PAGESIZE) failed with errno=%n", - errno); + trcVerbose("shmctl(SHM_PAGESIZE) failed with errno=%d", errno); } else { // Attach and double check pageisze. void* p = ::shmat(shmid, NULL, 0); @@ -495,7 +490,7 @@ guarantee0(p != (void*) -1); // Should always work. const size_t real_pagesize = os::Aix::query_pagesize(p); if (real_pagesize != pagesize) { - trcVerbose("real page size (0x%llX) differs.", real_pagesize); + trcVerbose("real page size (" SIZE_FORMAT_HEX ") differs.", real_pagesize); } else { can_use = true; } @@ -917,6 +912,11 @@ char buf[64]; log_warning(os, thread)("Failed to start thread - pthread_create failed (%d=%s) for attributes: %s.", ret, os::errno_name(ret), os::Posix::describe_pthread_attr(buf, sizeof(buf), &attr)); + // Log some OS information which might explain why creating the thread failed. + log_info(os, thread)("Number of threads approx. running in the VM: %d", Threads::number_of_threads()); + LogStream st(Log(os, thread)::info()); + os::Posix::print_rlimit_info(&st); + os::print_memory_info(&st); } pthread_attr_destroy(&attr); @@ -1016,17 +1016,15 @@ // Time since start-up in seconds to a fine granularity. // Used by VMSelfDestructTimer and the MemProfiler. double os::elapsedTime() { - return (double)(os::elapsed_counter()) * 0.000001; + return ((double)os::elapsed_counter()) / os::elapsed_frequency(); // nanosecond resolution } jlong os::elapsed_counter() { - timeval time; - int status = gettimeofday(&time, NULL); - return jlong(time.tv_sec) * 1000 * 1000 + jlong(time.tv_usec) - initial_time_count; + return javaTimeNanos() - initial_time_count; } jlong os::elapsed_frequency() { - return (1000 * 1000); + return NANOSECS_PER_SEC; // nanosecond resolution } bool os::supports_vtime() { return true; } @@ -1194,8 +1192,15 @@ } // Die immediately, no exit hook, no abort hook, no cleanup. +// Dump a core file, if possible, for debugging. void os::die() { - ::abort(); + if (TestUnresponsiveErrorHandler && !CreateCoredumpOnCrash) { + // For TimeoutInErrorHandlingTest.java, we just kill the VM + // and don't take the time to generate a core file. + os::signal_raise(SIGKILL); + } else { + ::abort(); + } } // This method is a copy of JDK's sysGetLastErrorString @@ -1311,6 +1316,8 @@ // for the same architecture as Hotspot is running on. void *os::dll_load(const char *filename, char *ebuf, int ebuflen) { + log_info(os)("attempting shared library load of %s", filename); + if (ebuf && ebuflen > 0) { ebuf[0] = '\0'; ebuf[ebuflen - 1] = '\0'; @@ -1324,16 +1331,23 @@ // RTLD_LAZY is currently not implemented. The dl is loaded immediately with all its dependants. void * result= ::dlopen(filename, RTLD_LAZY); if (result != NULL) { + Events::log(NULL, "Loaded shared library %s", filename); // Reload dll cache. Don't do this in signal handling. LoadedLibraries::reload(); + log_info(os)("shared library load of %s was successful", filename); return result; } else { // error analysis when dlopen fails - const char* const error_report = ::dlerror(); - if (error_report && ebuf && ebuflen > 0) { + const char* error_report = ::dlerror(); + if (error_report == NULL) { + error_report = "dlerror returned no error description"; + } + if (ebuf != NULL && ebuflen > 0) { snprintf(ebuf, ebuflen - 1, "%s, LIBPATH=%s, LD_LIBRARY_PATH=%s : %s", filename, ::getenv("LIBPATH"), ::getenv("LD_LIBRARY_PATH"), error_report); } + Events::log(NULL, "Loading shared library %s failed, %s", filename, error_report); + log_info(os)("shared library load of %s failed, %s", filename, error_report); } return NULL; } @@ -1377,28 +1391,21 @@ void os::print_os_info(outputStream* st) { st->print("OS:"); - st->print("uname:"); - struct utsname name; - uname(&name); - st->print(name.sysname); st->print(" "); - st->print(name.nodename); st->print(" "); - st->print(name.release); st->print(" "); - st->print(name.version); st->print(" "); - st->print(name.machine); - st->cr(); + os::Posix::print_uname_info(st); uint32_t ver = os::Aix::os_version(); st->print_cr("AIX kernel version %u.%u.%u.%u", (ver >> 24) & 0xFF, (ver >> 16) & 0xFF, (ver >> 8) & 0xFF, ver & 0xFF); + os::Posix::print_uptime_info(st); + os::Posix::print_rlimit_info(st); - // load average - st->print("load average:"); - double loadavg[3] = {-1.L, -1.L, -1.L}; - os::loadavg(loadavg, 3); - st->print("%0.02f %0.02f %0.02f", loadavg[0], loadavg[1], loadavg[2]); - st->cr(); + os::Posix::print_load_average(st); + + // _SC_THREAD_THREADS_MAX is the maximum number of threads within a process. + long tmax = sysconf(_SC_THREAD_THREADS_MAX); + st->print_cr("maximum #threads within a process:%ld", tmax); // print wpar info libperfstat::wparinfo_t wi; @@ -1409,13 +1416,7 @@ st->print_cr("type: %s", (wi.app_wpar ? "application" : "system")); } - // print partition info - libperfstat::partitioninfo_t pi; - if (libperfstat::get_partitioninfo(&pi)) { - st->print_cr("partition info"); - st->print_cr(" name: %s", pi.name); - } - + VM_Version::print_platform_virtualization_info(st); } void os::print_memory_info(outputStream* st) { @@ -1498,6 +1499,9 @@ void os::get_summary_cpu_info(char* buf, size_t buflen) { // read _system_configuration.version switch (_system_configuration.version) { + case PV_9: + strncpy(buf, "Power PC 9", buflen); + break; case PV_8: strncpy(buf, "Power PC 8", buflen); break; @@ -1531,6 +1535,9 @@ case PV_8_Compat: strncpy(buf, "PV_8_Compat", buflen); break; + case PV_9_Compat: + strncpy(buf, "PV_9_Compat", buflen); + break; default: strncpy(buf, "unknown", buflen); } @@ -1883,12 +1890,12 @@ if (!contains_range(p, s)) { trcVerbose("[" PTR_FORMAT " - " PTR_FORMAT "] is not a sub " "range of [" PTR_FORMAT " - " PTR_FORMAT "].", - p, p + s, addr, addr + size); + p2i(p), p2i(p + s), p2i(addr), p2i(addr + size)); guarantee0(false); } if (!is_aligned_to(p, pagesize) || !is_aligned_to(p + s, pagesize)) { trcVerbose("range [" PTR_FORMAT " - " PTR_FORMAT "] is not" - " aligned to pagesize (%lu)", p, p + s, (unsigned long) pagesize); + " aligned to pagesize (%lu)", p2i(p), p2i(p + s), (unsigned long) pagesize); guarantee0(false); } } @@ -1959,7 +1966,7 @@ trcVerbose("reserve_shmated_memory " UINTX_FORMAT " bytes, wishaddress " PTR_FORMAT ", alignment_hint " UINTX_FORMAT "...", - bytes, requested_addr, alignment_hint); + bytes, p2i(requested_addr), alignment_hint); // Either give me wish address or wish alignment but not both. assert0(!(requested_addr != NULL && alignment_hint != 0)); @@ -1968,7 +1975,7 @@ // BRK because that may cause malloc OOM. if (requested_addr != NULL && is_close_to_brk((address)requested_addr)) { trcVerbose("Wish address " PTR_FORMAT " is too close to the BRK segment. " - "Will attach anywhere.", requested_addr); + "Will attach anywhere.", p2i(requested_addr)); // Act like the OS refused to attach there. requested_addr = NULL; } @@ -2020,7 +2027,7 @@ // Handle shmat error. If we failed to attach, just return. if (addr == (char*)-1) { - trcVerbose("Failed to attach segment at " PTR_FORMAT " (%d).", requested_addr, errno_shmat); + trcVerbose("Failed to attach segment at " PTR_FORMAT " (%d).", p2i(requested_addr), errno_shmat); return NULL; } @@ -2028,15 +2035,15 @@ // work (see above), the system may have given us something other then 4K (LDR_CNTRL). const size_t real_pagesize = os::Aix::query_pagesize(addr); if (real_pagesize != shmbuf.shm_pagesize) { - trcVerbose("pagesize is, surprisingly, %h.", real_pagesize); + trcVerbose("pagesize is, surprisingly, " SIZE_FORMAT, real_pagesize); } if (addr) { trcVerbose("shm-allocated " PTR_FORMAT " .. " PTR_FORMAT " (" UINTX_FORMAT " bytes, " UINTX_FORMAT " %s pages)", - addr, addr + size - 1, size, size/real_pagesize, describe_pagesize(real_pagesize)); + p2i(addr), p2i(addr + size - 1), size, size/real_pagesize, describe_pagesize(real_pagesize)); } else { if (requested_addr != NULL) { - trcVerbose("failed to shm-allocate " UINTX_FORMAT " bytes at with address " PTR_FORMAT ".", size, requested_addr); + trcVerbose("failed to shm-allocate " UINTX_FORMAT " bytes at with address " PTR_FORMAT ".", size, p2i(requested_addr)); } else { trcVerbose("failed to shm-allocate " UINTX_FORMAT " bytes at any address.", size); } @@ -2052,7 +2059,7 @@ static bool release_shmated_memory(char* addr, size_t size) { trcVerbose("release_shmated_memory [" PTR_FORMAT " - " PTR_FORMAT "].", - addr, addr + size - 1); + p2i(addr), p2i(addr + size - 1)); bool rc = false; @@ -2068,12 +2075,12 @@ static bool uncommit_shmated_memory(char* addr, size_t size) { trcVerbose("uncommit_shmated_memory [" PTR_FORMAT " - " PTR_FORMAT "].", - addr, addr + size - 1); + p2i(addr), p2i(addr + size - 1)); const bool rc = my_disclaim64(addr, size); if (!rc) { - trcVerbose("my_disclaim64(" PTR_FORMAT ", " UINTX_FORMAT ") failed.\n", addr, size); + trcVerbose("my_disclaim64(" PTR_FORMAT ", " UINTX_FORMAT ") failed.\n", p2i(addr), size); return false; } return true; @@ -2090,11 +2097,11 @@ static char* reserve_mmaped_memory(size_t bytes, char* requested_addr, size_t alignment_hint) { trcVerbose("reserve_mmaped_memory " UINTX_FORMAT " bytes, wishaddress " PTR_FORMAT ", " "alignment_hint " UINTX_FORMAT "...", - bytes, requested_addr, alignment_hint); + bytes, p2i(requested_addr), alignment_hint); // If a wish address is given, but not aligned to 4K page boundary, mmap will fail. if (requested_addr && !is_aligned_to(requested_addr, os::vm_page_size()) != 0) { - trcVerbose("Wish address " PTR_FORMAT " not aligned to page boundary.", requested_addr); + trcVerbose("Wish address " PTR_FORMAT " not aligned to page boundary.", p2i(requested_addr)); return NULL; } @@ -2102,7 +2109,7 @@ // BRK because that may cause malloc OOM. if (requested_addr != NULL && is_close_to_brk((address)requested_addr)) { trcVerbose("Wish address " PTR_FORMAT " is too close to the BRK segment. " - "Will attach anywhere.", requested_addr); + "Will attach anywhere.", p2i(requested_addr)); // Act like the OS refused to attach there. requested_addr = NULL; } @@ -2149,7 +2156,7 @@ PROT_READ|PROT_WRITE|PROT_EXEC, flags, -1, 0); if (addr == MAP_FAILED) { - trcVerbose("mmap(" PTR_FORMAT ", " UINTX_FORMAT ", ..) failed (%d)", requested_addr, size, errno); + trcVerbose("mmap(" PTR_FORMAT ", " UINTX_FORMAT ", ..) failed (%d)", p2i(requested_addr), size, errno); return NULL; } @@ -2168,10 +2175,10 @@ if (addr) { trcVerbose("mmap-allocated " PTR_FORMAT " .. " PTR_FORMAT " (" UINTX_FORMAT " bytes)", - addr, addr + bytes, bytes); + p2i(addr), p2i(addr + bytes), bytes); } else { if (requested_addr != NULL) { - trcVerbose("failed to mmap-allocate " UINTX_FORMAT " bytes at wish address " PTR_FORMAT ".", bytes, requested_addr); + trcVerbose("failed to mmap-allocate " UINTX_FORMAT " bytes at wish address " PTR_FORMAT ".", bytes, p2i(requested_addr)); } else { trcVerbose("failed to mmap-allocate " UINTX_FORMAT " bytes at any address.", bytes); } @@ -2191,7 +2198,7 @@ assert0(is_aligned_to(size, os::vm_page_size())); trcVerbose("release_mmaped_memory [" PTR_FORMAT " - " PTR_FORMAT "].", - addr, addr + size - 1); + p2i(addr), p2i(addr + size - 1)); bool rc = false; if (::munmap(addr, size) != 0) { @@ -2211,7 +2218,7 @@ assert0(is_aligned_to(size, os::vm_page_size())); trcVerbose("uncommit_mmaped_memory [" PTR_FORMAT " - " PTR_FORMAT "].", - addr, addr + size - 1); + p2i(addr), p2i(addr + size - 1)); bool rc = false; // Uncommit mmap memory with msync MS_INVALIDATE. @@ -2242,7 +2249,7 @@ static void warn_fail_commit_memory(char* addr, size_t size, bool exec, int err) { warning("INFO: os::commit_memory(" PTR_FORMAT ", " SIZE_FORMAT - ", %d) failed; error='%s' (errno=%d)", addr, size, exec, + ", %d) failed; error='%s' (errno=%d)", p2i(addr), size, exec, os::errno_name(err), err); } #endif @@ -2270,7 +2277,7 @@ guarantee0(vmi); vmi->assert_is_valid_subrange(addr, size); - trcVerbose("commit_memory [" PTR_FORMAT " - " PTR_FORMAT "].", addr, addr + size - 1); + trcVerbose("commit_memory [" PTR_FORMAT " - " PTR_FORMAT "].", p2i(addr), p2i(addr + size - 1)); if (UseExplicitCommit) { // AIX commits memory on touch. So, touch all pages to be committed. @@ -2449,6 +2456,7 @@ // // See http://publib.boulder.ibm.com/infocenter/pseries/v5r3/index.jsp?topic=/com.ibm.aix.basetechref/doc/basetrf1/mprotect.htm + Events::log(NULL, "Protecting memory [" INTPTR_FORMAT "," INTPTR_FORMAT "] with protection modes %x", p2i(addr), p2i(addr+size), prot); bool rc = ::mprotect(addr, size, prot) == 0 ? true : false; if (!rc) { @@ -2489,6 +2497,7 @@ // A valid strategy is just to try again. This usually works. :-/ ::usleep(1000); + Events::log(NULL, "Protecting memory [" INTPTR_FORMAT "," INTPTR_FORMAT "] with protection modes %x", p2i(addr), p2i(addr+size), prot); if (::mprotect(addr, size, prot) == 0) { const bool read_protected_2 = (SafeFetch32((int*)addr, 0x12345678) == 0x12345678 && @@ -2612,23 +2621,6 @@ return ::pread(fd, buf, nBytes, offset); } -void os::naked_short_sleep(jlong ms) { - struct timespec req; - - assert(ms < 1000, "Un-interruptable sleep, short time use only"); - req.tv_sec = 0; - if (ms > 0) { - req.tv_nsec = (ms % 1000) * 1000000; - } - else { - req.tv_nsec = 1; - } - - nanosleep(&req, NULL); - - return; -} - // Sleep forever; naked call to OS-specific sleep; use with CAUTION void os::infinite_sleep() { while (true) { // sleep forever ... @@ -2797,7 +2789,7 @@ os::SuspendResume::State state = osthread->sr.suspended(); if (state == os::SuspendResume::SR_SUSPENDED) { sigset_t suspend_set; // signals for sigsuspend() - + sigemptyset(&suspend_set); // get current set of blocked signals and unblock resume signal pthread_sigmask(SIG_BLOCK, NULL, &suspend_set); sigdelset(&suspend_set, SR_signum); @@ -3035,8 +3027,6 @@ bool os::Aix::signal_handlers_are_installed = false; // For signal-chaining -struct sigaction sigact[NSIG]; -sigset_t sigs; bool os::Aix::libjsig_is_loaded = false; typedef struct sigaction *(*get_signal_t)(int); get_signal_t os::Aix::get_signal_action = NULL; @@ -3050,7 +3040,7 @@ } if (actp == NULL) { // Retrieve the preinstalled signal handler from jvm - actp = get_preinstalled_handler(sig); + actp = os::Posix::get_preinstalled_handler(sig); } return actp; @@ -3085,6 +3075,7 @@ // try to honor the signal mask sigset_t oset; + sigemptyset(&oset); pthread_sigmask(SIG_SETMASK, &(actp->sa_mask), &oset); // call into the chained handler @@ -3095,7 +3086,7 @@ } // restore the signal mask - pthread_sigmask(SIG_SETMASK, &oset, 0); + pthread_sigmask(SIG_SETMASK, &oset, NULL); } // Tell jvm's signal handler the signal is taken care of. return true; @@ -3113,19 +3104,6 @@ return chained; } -struct sigaction* os::Aix::get_preinstalled_handler(int sig) { - if (sigismember(&sigs, sig)) { - return &sigact[sig]; - } - return NULL; -} - -void os::Aix::save_preinstalled_handler(int sig, struct sigaction& oldAct) { - assert(sig > 0 && sig < NSIG, "vm signal out of expected range"); - sigact[sig] = oldAct; - sigaddset(&sigs, sig); -} - // for diagnostic int sigflags[NSIG]; @@ -3157,7 +3135,7 @@ return; } else if (UseSignalChaining) { // save the old handler in jvm - save_preinstalled_handler(sig, oldAct); + os::Posix::save_preinstalled_handler(sig, oldAct); // libjsig also interposes the sigaction() call below and saves the // old sigaction on it own. } else { @@ -3213,7 +3191,6 @@ (*begin_signal_setting)(); } - ::sigemptyset(&sigs); set_signal_handler(SIGSEGV, true); set_signal_handler(SIGPIPE, true); set_signal_handler(SIGBUS, true); @@ -3542,7 +3519,7 @@ // _main_thread points to the thread that created/loaded the JVM. Aix::_main_thread = pthread_self(); - initial_time_count = os::elapsed_counter(); + initial_time_count = javaTimeNanos(); os::Posix::init(); } @@ -3812,9 +3789,7 @@ // create binary file, rewriting existing file if required int os::create_binary_file(const char* path, bool rewrite_existing) { int oflags = O_WRONLY | O_CREAT; - if (!rewrite_existing) { - oflags |= O_EXCL; - } + oflags |= rewrite_existing ? O_TRUNC : O_EXCL; return ::open64(path, oflags, S_IREAD | S_IWRITE); } @@ -4062,7 +4037,7 @@ void os::pause() { char filename[MAX_PATH]; if (PauseAtStartupFile && PauseAtStartupFile[0]) { - jio_snprintf(filename, MAX_PATH, PauseAtStartupFile); + jio_snprintf(filename, MAX_PATH, "%s", PauseAtStartupFile); } else { jio_snprintf(filename, MAX_PATH, "./vm.paused.%d", current_process_id()); } @@ -4268,7 +4243,7 @@ // Unlike system(), this function can be called from signal handler. It // doesn't block SIGINT et al. int os::fork_and_exec(char* cmd, bool use_vfork_if_available) { - char * argv[4] = {"sh", "-c", cmd, NULL}; + char* argv[4] = { (char*)"sh", (char*)"-c", cmd, NULL}; pid_t pid = fork();
diff --git a/src/hotspot/os/aix/os_aix.hpp b/src/hotspot/os/aix/os_aix.hpp index 515edfd..f00036f 100644 --- a/src/hotspot/os/aix/os_aix.hpp +++ b/src/hotspot/os/aix/os_aix.hpp
@@ -37,8 +37,6 @@ static bool libjsig_is_loaded; // libjsig that interposes sigaction(), // __sigaction(), signal() is loaded static struct sigaction *(*get_signal_action)(int); - static struct sigaction *get_preinstalled_handler(int); - static void save_preinstalled_handler(int, struct sigaction&); static void check_signal_handler(int sig);
diff --git a/src/hotspot/os/aix/os_perf_aix.cpp b/src/hotspot/os/aix/os_perf_aix.cpp index f754e4a..bdd5c2b 100644 --- a/src/hotspot/os/aix/os_perf_aix.cpp +++ b/src/hotspot/os/aix/os_perf_aix.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2012, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2019, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -28,6 +28,7 @@ #include "os_aix.inline.hpp" #include "runtime/os.hpp" #include "runtime/os_perf.hpp" +#include "utilities/globalDefinitions.hpp" #include CPU_HEADER(vm_version_ext) @@ -720,11 +721,7 @@ char* SystemProcessInterface::SystemProcesses::ProcessIterator::allocate_string(const char* str) const { if (str != NULL) { - size_t len = strlen(str); - char* tmp = NEW_C_HEAP_ARRAY(char, len+1, mtInternal); - strncpy(tmp, str, len); - tmp[len] = '\0'; - return tmp; + return os::strdup_check_oom(str, mtInternal); } return NULL; } @@ -897,8 +894,7 @@ friend class NetworkPerformanceInterface; private: NetworkPerformance(); - NetworkPerformance(const NetworkPerformance& rhs); // no impl - NetworkPerformance& operator=(const NetworkPerformance& rhs); // no impl + NONCOPYABLE(NetworkPerformance); bool initialize(); ~NetworkPerformance(); int network_utilization(NetworkInterface** network_interfaces) const;
diff --git a/src/hotspot/os/aix/perfMemory_aix.cpp b/src/hotspot/os/aix/perfMemory_aix.cpp index 7c18274..a5a2135 100644 --- a/src/hotspot/os/aix/perfMemory_aix.cpp +++ b/src/hotspot/os/aix/perfMemory_aix.cpp
@@ -538,7 +538,7 @@ char* pwbuf = NEW_C_HEAP_ARRAY(char, bufsize, mtInternal); - struct passwd* p; + struct passwd* p = NULL; int result = getpwuid_r(uid, &pwent, pwbuf, (size_t)bufsize, &p); if (result != 0 || p == NULL || p->pw_name == NULL || *(p->pw_name) == '\0') { @@ -1111,7 +1111,7 @@ if ((statbuf.st_size == 0) || ((size_t)statbuf.st_size % os::vm_page_size() != 0)) { - THROW_MSG_0(vmSymbols::java_lang_Exception(), + THROW_MSG_0(vmSymbols::java_io_IOException(), "Invalid PerfMemory size"); }
diff --git a/src/hotspot/os/aix/safepointMechanism_aix.cpp b/src/hotspot/os/aix/safepointMechanism_aix.cpp index a6b33c0..7fd5ba2 100644 --- a/src/hotspot/os/aix/safepointMechanism_aix.cpp +++ b/src/hotspot/os/aix/safepointMechanism_aix.cpp
@@ -27,6 +27,7 @@ #include "runtime/globals.hpp" #include "runtime/os.hpp" #include "runtime/safepointMechanism.hpp" +#include "services/memTracker.hpp" #include <sys/mman.h> void SafepointMechanism::pd_initialize() { @@ -95,6 +96,9 @@ log_info(os)("SafePoint Polling address: " INTPTR_FORMAT, p2i(map_address)); os::set_polling_page((address)(map_address)); + // Register polling page with NMT. + MemTracker::record_virtual_memory_reserve_and_commit(map_address, map_size, CALLER_PC, mtSafepoint); + // Use same page for ThreadLocalHandshakes without SIGTRAP if (ThreadLocalHandshakes) { set_uses_thread_local_poll();
diff --git a/src/hotspot/os/bsd/attachListener_bsd.cpp b/src/hotspot/os/bsd/attachListener_bsd.cpp index 503a4d7..c951aee 100644 --- a/src/hotspot/os/bsd/attachListener_bsd.cpp +++ b/src/hotspot/os/bsd/attachListener_bsd.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2005, 2020, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -66,19 +66,9 @@ static bool _has_path; // the file descriptor for the listening socket - static int _listener; + static volatile int _listener; - static void set_path(char* path) { - if (path == NULL) { - _has_path = false; - } else { - strncpy(_path, path, UNIX_PATH_MAX); - _path[UNIX_PATH_MAX-1] = '\0'; - _has_path = true; - } - } - - static void set_listener(int s) { _listener = s; } + static bool _atexit_registered; // reads a request from the given connected socket static BsdAttachOperation* read_request(int s); @@ -91,6 +81,19 @@ ATTACH_ERROR_BADVERSION = 101 // error codes }; + static void set_path(char* path) { + if (path == NULL) { + _path[0] = '\0'; + _has_path = false; + } else { + strncpy(_path, path, UNIX_PATH_MAX); + _path[UNIX_PATH_MAX-1] = '\0'; + _has_path = true; + } + } + + static void set_listener(int s) { _listener = s; } + // initialize the listener, returns 0 if okay static int init(); @@ -123,7 +126,8 @@ // statics char BsdAttachListener::_path[UNIX_PATH_MAX]; bool BsdAttachListener::_has_path; -int BsdAttachListener::_listener = -1; +volatile int BsdAttachListener::_listener = -1; +bool BsdAttachListener::_atexit_registered = false; // Supporting class to help split a buffer into individual components class ArgumentIterator : public StackObj { @@ -158,16 +162,15 @@ // bound too. extern "C" { static void listener_cleanup() { - static int cleanup_done; - if (!cleanup_done) { - cleanup_done = 1; - int s = BsdAttachListener::listener(); - if (s != -1) { - ::close(s); - } - if (BsdAttachListener::has_path()) { - ::unlink(BsdAttachListener::path()); - } + int s = BsdAttachListener::listener(); + if (s != -1) { + BsdAttachListener::set_listener(-1); + ::shutdown(s, SHUT_RDWR); + ::close(s); + } + if (BsdAttachListener::has_path()) { + ::unlink(BsdAttachListener::path()); + BsdAttachListener::set_path(NULL); } } } @@ -180,7 +183,10 @@ int listener; // listener socket (file descriptor) // register function to cleanup - ::atexit(listener_cleanup); + if (!_atexit_registered) { + _atexit_registered = true; + ::atexit(listener_cleanup); + } int n = snprintf(path, UNIX_PATH_MAX, "%s/.java_pid%d", os::get_temp_directory(), os::current_process_id()); @@ -485,6 +491,30 @@ return ret_code; } +bool AttachListener::check_socket_file() { + int ret; + struct stat st; + ret = stat(BsdAttachListener::path(), &st); + if (ret == -1) { // need to restart attach listener. + log_debug(attach)("Socket file %s does not exist - Restart Attach Listener", + BsdAttachListener::path()); + + listener_cleanup(); + + // wait to terminate current attach listener instance... + { + // avoid deadlock if AttachListener thread is blocked at safepoint + ThreadBlockInVM tbivm(JavaThread::current()); + while (AttachListener::transit_state(AL_INITIALIZING, + AL_NOT_INITIALIZED) != AL_NOT_INITIALIZED) { + os::naked_yield(); + } + } + return is_init_trigger(); + } + return false; +} + // Attach Listener is started lazily except in the case when // +ReduseSignalUsage is used bool AttachListener::init_at_startup() {
diff --git a/src/hotspot/os/bsd/os_bsd.cpp b/src/hotspot/os/bsd/os_bsd.cpp index 6b3b3c8..15b820f 100644 --- a/src/hotspot/os/bsd/os_bsd.cpp +++ b/src/hotspot/os/bsd/os_bsd.cpp
@@ -33,6 +33,7 @@ #include "compiler/disassembler.hpp" #include "interpreter/interpreter.hpp" #include "logging/log.hpp" +#include "logging/logStream.hpp" #include "memory/allocation.inline.hpp" #include "memory/filemap.hpp" #include "oops/oop.inline.hpp" @@ -183,6 +184,22 @@ return available; } +// for more info see : +// https://man.openbsd.org/sysctl.2 +void os::Bsd::print_uptime_info(outputStream* st) { + struct timeval boottime; + size_t len = sizeof(boottime); + int mib[2]; + mib[0] = CTL_KERN; + mib[1] = KERN_BOOTTIME; + + if (sysctl(mib, 2, &boottime, &len, NULL, 0) >= 0) { + time_t bootsec = boottime.tv_sec; + time_t currsec = time(NULL); + os::print_dhm(st, "OS uptime:", (long) difftime(currsec, bootsec)); + } +} + julong os::physical_memory() { return Bsd::physical_memory(); } @@ -750,6 +767,11 @@ } else { log_warning(os, thread)("Failed to start thread - pthread_create failed (%s) for attributes: %s.", os::errno_name(ret), os::Posix::describe_pthread_attr(buf, sizeof(buf), &attr)); + // Log some OS information which might explain why creating the thread failed. + log_info(os, thread)("Number of threads approx. running in the VM: %d", Threads::number_of_threads()); + LogStream st(Log(os, thread)::info()); + os::Posix::print_rlimit_info(&st); + os::print_memory_info(&st); } pthread_attr_destroy(&attr); @@ -1074,9 +1096,16 @@ } // Die immediately, no exit hook, no abort hook, no cleanup. +// Dump a core file, if possible, for debugging. void os::die() { - // _exit() on BsdThreads only kills current thread - ::abort(); + if (TestUnresponsiveErrorHandler && !CreateCoredumpOnCrash) { + // For TimeoutInErrorHandlingTest.java, we just kill the VM + // and don't take the time to generate a core file. + os::signal_raise(SIGKILL); + } else { + // _exit() on BsdThreads only kills current thread + ::abort(); + } } // This method is a copy of JDK's sysGetLastErrorString @@ -1273,15 +1302,27 @@ #ifdef STATIC_BUILD return os::get_default_process_handle(); #else + log_info(os)("attempting shared library load of %s", filename); + void * result= ::dlopen(filename, RTLD_LAZY); if (result != NULL) { + Events::log(NULL, "Loaded shared library %s", filename); // Successful loading + log_info(os)("shared library load of %s was successful", filename); return result; } - // Read system error message into ebuf - ::strncpy(ebuf, ::dlerror(), ebuflen-1); - ebuf[ebuflen-1]='\0'; + const char* error_report = ::dlerror(); + if (error_report == NULL) { + error_report = "dlerror returned no error description"; + } + if (ebuf != NULL && ebuflen > 0) { + // Read system error message into ebuf + ::strncpy(ebuf, error_report, ebuflen-1); + ebuf[ebuflen-1]='\0'; + } + Events::log(NULL, "Loading shared library %s failed, %s", filename, error_report); + log_info(os)("shared library load of %s failed, %s", filename, error_report); return NULL; #endif // STATIC_BUILD @@ -1291,18 +1332,29 @@ #ifdef STATIC_BUILD return os::get_default_process_handle(); #else + log_info(os)("attempting shared library load of %s", filename); void * result= ::dlopen(filename, RTLD_LAZY); if (result != NULL) { + Events::log(NULL, "Loaded shared library %s", filename); // Successful loading + log_info(os)("shared library load of %s was successful", filename); return result; } Elf32_Ehdr elf_head; - // Read system error message into ebuf - // It may or may not be overwritten below - ::strncpy(ebuf, ::dlerror(), ebuflen-1); - ebuf[ebuflen-1]='\0'; + const char* const error_report = ::dlerror(); + if (error_report == NULL) { + error_report = "dlerror returned no error description"; + } + if (ebuf != NULL && ebuflen > 0) { + // Read system error message into ebuf + ::strncpy(ebuf, error_report, ebuflen-1); + ebuf[ebuflen-1]='\0'; + } + Events::log(NULL, "Loading shared library %s failed, %s", filename, error_report); + log_info(os)("shared library load of %s failed, %s", filename, error_report); + int diag_msg_max_length=ebuflen-strlen(ebuf); char* diag_msg_buf=ebuf+strlen(ebuf); @@ -1578,9 +1630,13 @@ os::Posix::print_uname_info(st); + os::Bsd::print_uptime_info(st); + os::Posix::print_rlimit_info(st); os::Posix::print_load_average(st); + + VM_Version::print_platform_virtualization_info(st); } void os::pd_print_cpu_info(outputStream* st, char* buf, size_t buflen) { @@ -1615,6 +1671,8 @@ } void os::print_memory_info(outputStream* st) { + xsw_usage swap_usage; + size_t size = sizeof(swap_usage); st->print("Memory:"); st->print(" %dk page", os::vm_page_size()>>10); @@ -1623,6 +1681,16 @@ os::physical_memory() >> 10); st->print("(" UINT64_FORMAT "k free)", os::available_memory() >> 10); + + if((sysctlbyname("vm.swapusage", &swap_usage, &size, NULL, 0) == 0) || (errno == ENOMEM)) { + if (size >= offset_of(xsw_usage, xsu_used)) { + st->print(", swap " UINT64_FORMAT "k", + ((julong) swap_usage.xsu_total) >> 10); + st->print("(" UINT64_FORMAT "k free)", + ((julong) swap_usage.xsu_avail) >> 10); + } + } + st->cr(); } @@ -1661,6 +1729,7 @@ } char dli_fname[MAXPATHLEN]; + dli_fname[0] = '\0'; bool ret = dll_address_to_library_name( CAST_FROM_FN_PTR(address, os::jvm_path), dli_fname, sizeof(dli_fname), NULL); @@ -1938,6 +2007,7 @@ int prot = exec ? PROT_READ|PROT_WRITE|PROT_EXEC : PROT_READ|PROT_WRITE; #ifdef __OpenBSD__ // XXX: Work-around mmap/MAP_FIXED bug temporarily on OpenBSD + Events::log(NULL, "Protecting memory [" INTPTR_FORMAT "," INTPTR_FORMAT "] with protection modes %x", p2i(addr), p2i(addr+size), prot); if (::mprotect(addr, size, prot) == 0) { return true; } @@ -2022,6 +2092,7 @@ bool os::pd_uncommit_memory(char* addr, size_t size) { #ifdef __OpenBSD__ // XXX: Work-around mmap/MAP_FIXED bug temporarily on OpenBSD + Events::log(NULL, "Protecting memory [" INTPTR_FORMAT "," INTPTR_FORMAT "] with PROT_NONE", p2i(addr), p2i(addr+size)); return ::mprotect(addr, size, PROT_NONE) == 0; #else uintptr_t res = (uintptr_t) ::mmap(addr, size, PROT_NONE, @@ -2090,6 +2161,7 @@ assert(addr == bottom, "sanity check"); size = align_up(pointer_delta(addr, bottom, 1) + size, os::Bsd::page_size()); + Events::log(NULL, "Protecting memory [" INTPTR_FORMAT "," INTPTR_FORMAT "] with protection modes %x", p2i(bottom), p2i(bottom+size), prot); return ::mprotect(bottom, size, prot) == 0; } @@ -2317,22 +2389,6 @@ RESTARTABLE_RETURN_INT(::pread(fd, buf, nBytes, offset)); } -void os::naked_short_sleep(jlong ms) { - struct timespec req; - - assert(ms < 1000, "Un-interruptable sleep, short time use only"); - req.tv_sec = 0; - if (ms > 0) { - req.tv_nsec = (ms % 1000) * 1000000; - } else { - req.tv_nsec = 1; - } - - nanosleep(&req, NULL); - - return; -} - // Sleep forever; naked call to OS-specific sleep; use with CAUTION void os::infinite_sleep() { while (true) { // sleep forever ... @@ -2413,7 +2469,7 @@ static int prio_init() { if (ThreadPriorityPolicy == 1) { if (geteuid() != 0) { - if (!FLAG_IS_DEFAULT(ThreadPriorityPolicy)) { + if (!FLAG_IS_DEFAULT(ThreadPriorityPolicy) && !FLAG_IS_JIMAGE_RESOURCE(ThreadPriorityPolicy)) { warning("-XX:ThreadPriorityPolicy=1 may require system level permission, " \ "e.g., being the root user. If the necessary permission is not " \ "possessed, changes to priority will be silently ignored."); @@ -2777,11 +2833,6 @@ bool os::Bsd::signal_handlers_are_installed = false; // For signal-chaining -struct sigaction sigact[NSIG]; -uint32_t sigs = 0; -#if (32 < NSIG-1) -#error "Not all signals can be encoded in sigs. Adapt its type!" -#endif bool os::Bsd::libjsig_is_loaded = false; typedef struct sigaction *(*get_signal_t)(int); get_signal_t os::Bsd::get_signal_action = NULL; @@ -2795,7 +2846,7 @@ } if (actp == NULL) { // Retrieve the preinstalled signal handler from jvm - actp = get_preinstalled_handler(sig); + actp = os::Posix::get_preinstalled_handler(sig); } return actp; @@ -2858,19 +2909,6 @@ return chained; } -struct sigaction* os::Bsd::get_preinstalled_handler(int sig) { - if ((((uint32_t)1 << (sig-1)) & sigs) != 0) { - return &sigact[sig]; - } - return NULL; -} - -void os::Bsd::save_preinstalled_handler(int sig, struct sigaction& oldAct) { - assert(sig > 0 && sig < NSIG, "vm signal out of expected range"); - sigact[sig] = oldAct; - sigs |= (uint32_t)1 << (sig-1); -} - // for diagnostic int sigflags[NSIG]; @@ -2902,7 +2940,7 @@ return; } else if (UseSignalChaining) { // save the old handler in jvm - save_preinstalled_handler(sig, oldAct); + os::Posix::save_preinstalled_handler(sig, oldAct); // libjsig also interposes the sigaction() call below and saves the // old sigaction on it own. } else { @@ -3259,16 +3297,6 @@ Bsd::clock_init(); initial_time_count = javaTimeNanos(); -#ifdef __APPLE__ - // XXXDARWIN - // Work around the unaligned VM callbacks in hotspot's - // sharedRuntime. The callbacks don't use SSE2 instructions, and work on - // Linux, Solaris, and FreeBSD. On Mac OS X, dyld (rightly so) enforces - // alignment when doing symbol lookup. To work around this, we force early - // binding of all symbols now, thus binding when alignment is known-good. - _dyld_bind_fully_image_containing_address((const void *) &os::init); -#endif - os::Posix::init(); } @@ -3600,9 +3628,7 @@ // create binary file, rewriting existing file if required int os::create_binary_file(const char* path, bool rewrite_existing) { int oflags = O_WRONLY | O_CREAT; - if (!rewrite_existing) { - oflags |= O_EXCL; - } + oflags |= rewrite_existing ? O_TRUNC : O_EXCL; return ::open(path, oflags, S_IREAD | S_IWRITE); } @@ -3786,7 +3812,7 @@ void os::pause() { char filename[MAX_PATH]; if (PauseAtStartupFile && PauseAtStartupFile[0]) { - jio_snprintf(filename, MAX_PATH, PauseAtStartupFile); + jio_snprintf(filename, MAX_PATH, "%s", PauseAtStartupFile); } else { jio_snprintf(filename, MAX_PATH, "./vm.paused.%d", current_process_id()); } @@ -3878,11 +3904,30 @@ } } -// Get the default path to the core file +// Get the kern.corefile setting, or otherwise the default path to the core file // Returns the length of the string int os::get_core_path(char* buffer, size_t bufferSize) { - int n = jio_snprintf(buffer, bufferSize, "/cores/core.%d", current_process_id()); + int n = 0; +#ifdef __APPLE__ + char coreinfo[MAX_PATH]; + size_t sz = sizeof(coreinfo); + int ret = sysctlbyname("kern.corefile", coreinfo, &sz, NULL, 0); + if (ret == 0) { + char *pid_pos = strstr(coreinfo, "%P"); + // skip over the "%P" to preserve any optional custom user pattern + const char* tail = (pid_pos != NULL) ? (pid_pos + 2) : ""; + if (pid_pos != NULL) { + *pid_pos = '\0'; + n = jio_snprintf(buffer, bufferSize, "%s%d%s", coreinfo, os::current_process_id(), tail); + } else { + n = jio_snprintf(buffer, bufferSize, "%s", coreinfo); + } + } else +#endif + { + n = jio_snprintf(buffer, bufferSize, "/cores/core.%d", os::current_process_id()); + } // Truncate if theoretical string was longer than bufferSize n = MIN2(n, (int)bufferSize);
diff --git a/src/hotspot/os/bsd/os_bsd.hpp b/src/hotspot/os/bsd/os_bsd.hpp index b04da8c..fa6f409 100644 --- a/src/hotspot/os/bsd/os_bsd.hpp +++ b/src/hotspot/os/bsd/os_bsd.hpp
@@ -37,8 +37,6 @@ static bool libjsig_is_loaded; // libjsig that interposes sigaction(), // __sigaction(), signal() is loaded static struct sigaction *(*get_signal_action)(int); - static struct sigaction *get_preinstalled_handler(int); - static void save_preinstalled_handler(int, struct sigaction&); static void check_signal_handler(int sig); @@ -157,6 +155,8 @@ } } static int get_node_by_cpu(int cpu_id); + + static void print_uptime_info(outputStream* st); }; #endif // OS_BSD_VM_OS_BSD_HPP
diff --git a/src/hotspot/os/bsd/os_perf_bsd.cpp b/src/hotspot/os/bsd/os_perf_bsd.cpp index 62c6531..104dcec 100644 --- a/src/hotspot/os/bsd/os_perf_bsd.cpp +++ b/src/hotspot/os/bsd/os_perf_bsd.cpp
@@ -26,7 +26,8 @@ #include "memory/resourceArea.hpp" #include "runtime/os.hpp" #include "runtime/os_perf.hpp" -#include "vm_version_ext_x86.hpp" +#include "utilities/globalDefinitions.hpp" +#include CPU_HEADER(vm_version_ext) #ifdef __APPLE__ #import <libproc.h> @@ -72,8 +73,8 @@ int cpu_load_total_process(double* cpu_load); int cpu_loads_process(double* pjvmUserLoad, double* pjvmKernelLoad, double* psystemTotalLoad); - CPUPerformance(const CPUPerformance& rhs); // no impl - CPUPerformance& operator=(const CPUPerformance& rhs); // no impl + NONCOPYABLE(CPUPerformance); + public: CPUPerformance(); bool initialize(); @@ -264,8 +265,7 @@ private: SystemProcesses(); bool initialize(); - SystemProcesses(const SystemProcesses& rhs); // no impl - SystemProcesses& operator=(const SystemProcesses& rhs); // no impl + NONCOPYABLE(SystemProcesses); ~SystemProcesses(); //information about system processes @@ -412,8 +412,7 @@ friend class NetworkPerformanceInterface; private: NetworkPerformance(); - NetworkPerformance(const NetworkPerformance& rhs); // no impl - NetworkPerformance& operator=(const NetworkPerformance& rhs); // no impl + NONCOPYABLE(NetworkPerformance); bool initialize(); ~NetworkPerformance(); int network_utilization(NetworkInterface** network_interfaces) const;
diff --git a/src/hotspot/os/bsd/perfMemory_bsd.cpp b/src/hotspot/os/bsd/perfMemory_bsd.cpp index 4f5c417..0a52bc4 100644 --- a/src/hotspot/os/bsd/perfMemory_bsd.cpp +++ b/src/hotspot/os/bsd/perfMemory_bsd.cpp
@@ -454,7 +454,7 @@ char* pwbuf = NEW_C_HEAP_ARRAY(char, bufsize, mtInternal); // POSIX interface to getpwuid_r is used on LINUX - struct passwd* p; + struct passwd* p = NULL; int result = getpwuid_r(uid, &pwent, pwbuf, (size_t)bufsize, &p); if (result != 0 || p == NULL || p->pw_name == NULL || *(p->pw_name) == '\0') { @@ -1028,7 +1028,7 @@ if ((statbuf.st_size == 0) || ((size_t)statbuf.st_size % os::vm_page_size() != 0)) { - THROW_MSG_0(vmSymbols::java_lang_Exception(), + THROW_MSG_0(vmSymbols::java_io_IOException(), "Invalid PerfMemory size"); }
diff --git a/src/hotspot/os/bsd/semaphore_bsd.hpp b/src/hotspot/os/bsd/semaphore_bsd.hpp index 901d81e..ab321a5 100644 --- a/src/hotspot/os/bsd/semaphore_bsd.hpp +++ b/src/hotspot/os/bsd/semaphore_bsd.hpp
@@ -25,6 +25,8 @@ #ifndef OS_BSD_VM_SEMAPHORE_BSD_HPP #define OS_BSD_VM_SEMAPHORE_BSD_HPP +#include "utilities/globalDefinitions.hpp" + #ifndef __APPLE__ // Use POSIX semaphores. # include "semaphore_posix.hpp" @@ -37,9 +39,7 @@ class OSXSemaphore : public CHeapObj<mtInternal>{ semaphore_t _semaphore; - // Prevent copying and assignment. - OSXSemaphore(const OSXSemaphore&); - OSXSemaphore& operator=(const OSXSemaphore&); + NONCOPYABLE(OSXSemaphore); public: OSXSemaphore(uint value = 0);
diff --git a/src/hotspot/os/linux/attachListener_linux.cpp b/src/hotspot/os/linux/attachListener_linux.cpp index d79bd1b..aa114d9 100644 --- a/src/hotspot/os/linux/attachListener_linux.cpp +++ b/src/hotspot/os/linux/attachListener_linux.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2005, 2020, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -67,19 +67,9 @@ static bool _has_path; // the file descriptor for the listening socket - static int _listener; + static volatile int _listener; - static void set_path(char* path) { - if (path == NULL) { - _has_path = false; - } else { - strncpy(_path, path, UNIX_PATH_MAX); - _path[UNIX_PATH_MAX-1] = '\0'; - _has_path = true; - } - } - - static void set_listener(int s) { _listener = s; } + static bool _atexit_registered; // reads a request from the given connected socket static LinuxAttachOperation* read_request(int s); @@ -92,6 +82,19 @@ ATTACH_ERROR_BADVERSION = 101 // error codes }; + static void set_path(char* path) { + if (path == NULL) { + _path[0] = '\0'; + _has_path = false; + } else { + strncpy(_path, path, UNIX_PATH_MAX); + _path[UNIX_PATH_MAX-1] = '\0'; + _has_path = true; + } + } + + static void set_listener(int s) { _listener = s; } + // initialize the listener, returns 0 if okay static int init(); @@ -124,7 +127,8 @@ // statics char LinuxAttachListener::_path[UNIX_PATH_MAX]; bool LinuxAttachListener::_has_path; -int LinuxAttachListener::_listener = -1; +volatile int LinuxAttachListener::_listener = -1; +bool LinuxAttachListener::_atexit_registered = false; // Supporting class to help split a buffer into individual components class ArgumentIterator : public StackObj { @@ -159,16 +163,15 @@ // bound too. extern "C" { static void listener_cleanup() { - static int cleanup_done; - if (!cleanup_done) { - cleanup_done = 1; - int s = LinuxAttachListener::listener(); - if (s != -1) { - ::close(s); - } - if (LinuxAttachListener::has_path()) { - ::unlink(LinuxAttachListener::path()); - } + int s = LinuxAttachListener::listener(); + if (s != -1) { + LinuxAttachListener::set_listener(-1); + ::shutdown(s, SHUT_RDWR); + ::close(s); + } + if (LinuxAttachListener::has_path()) { + ::unlink(LinuxAttachListener::path()); + LinuxAttachListener::set_path(NULL); } } } @@ -181,7 +184,10 @@ int listener; // listener socket (file descriptor) // register function to cleanup - ::atexit(listener_cleanup); + if (!_atexit_registered) { + _atexit_registered = true; + ::atexit(listener_cleanup); + } int n = snprintf(path, UNIX_PATH_MAX, "%s/.java_pid%d", os::get_temp_directory(), os::current_process_id()); @@ -485,6 +491,30 @@ return ret_code; } +bool AttachListener::check_socket_file() { + int ret; + struct stat64 st; + ret = stat64(LinuxAttachListener::path(), &st); + if (ret == -1) { // need to restart attach listener. + log_debug(attach)("Socket file %s does not exist - Restart Attach Listener", + LinuxAttachListener::path()); + + listener_cleanup(); + + // wait to terminate current attach listener instance... + { + // avoid deadlock if AttachListener thread is blocked at safepoint + ThreadBlockInVM tbivm(JavaThread::current()); + while (AttachListener::transit_state(AL_INITIALIZING, + AL_NOT_INITIALIZED) != AL_NOT_INITIALIZED) { + os::naked_yield(); + } + } + return is_init_trigger(); + } + return false; +} + // Attach Listener is started lazily except in the case when // +ReduseSignalUsage is used bool AttachListener::init_at_startup() {
diff --git a/src/hotspot/os/linux/osContainer_linux.cpp b/src/hotspot/os/linux/osContainer_linux.cpp index 0b35bb3..045eea5 100644 --- a/src/hotspot/os/linux/osContainer_linux.cpp +++ b/src/hotspot/os/linux/osContainer_linux.cpp
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2017, 2019, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -35,12 +35,16 @@ bool OSContainer::_is_initialized = false; bool OSContainer::_is_containerized = false; +int OSContainer::_active_processor_count = 1; julong _unlimited_memory; class CgroupSubsystem: CHeapObj<mtInternal> { friend class OSContainer; + private: + volatile jlong _next_check_counter; + /* mountinfo contents */ char *_root; char *_mount_point; @@ -53,6 +57,7 @@ _root = os::strdup(root); _mount_point = os::strdup(mountpoint); _path = NULL; + _next_check_counter = min_jlong; } /* @@ -81,14 +86,14 @@ buf[MAXPATHLEN-1] = '\0'; _path = os::strdup(buf); } else { - char *p = strstr(_root, cgroup_path); + char *p = strstr(cgroup_path, _root); if (p != NULL && p == _root) { if (strlen(cgroup_path) > strlen(_root)) { int buflen; strncpy(buf, _mount_point, MAXPATHLEN); buf[MAXPATHLEN-1] = '\0'; buflen = strlen(buf); - if ((buflen + strlen(cgroup_path)) > (MAXPATHLEN-1)) { + if ((buflen + strlen(cgroup_path) - strlen(_root)) > (MAXPATHLEN-1)) { return; } strncat(buf, cgroup_path + strlen(_root), MAXPATHLEN-buflen); @@ -102,9 +107,50 @@ } char *subsystem_path() { return _path; } + + bool cache_has_expired() { + return os::elapsed_counter() > _next_check_counter; + } + + void set_cache_expiry_time(jlong timeout) { + _next_check_counter = os::elapsed_counter() + timeout; + } }; -CgroupSubsystem* memory = NULL; +class CgroupMemorySubsystem: CgroupSubsystem { + friend class OSContainer; + + private: + /* Some container runtimes set limits via cgroup + * hierarchy. If set to true consider also memory.stat + * file if everything else seems unlimited */ + bool _uses_mem_hierarchy; + volatile jlong _memory_limit_in_bytes; + + public: + CgroupMemorySubsystem(char *root, char *mountpoint) : CgroupSubsystem::CgroupSubsystem(root, mountpoint) { + _uses_mem_hierarchy = false; + _memory_limit_in_bytes = -1; + + } + + bool is_hierarchical() { return _uses_mem_hierarchy; } + void set_hierarchical(bool value) { _uses_mem_hierarchy = value; } + + jlong memory_limit_in_bytes() { return _memory_limit_in_bytes; } + void set_memory_limit_in_bytes(jlong value) { + _memory_limit_in_bytes = value; + // max memory limit is unlikely to change, but we want to remain + // responsive to configuration changes. A very short grace time + // between re-read avoids excessive overhead during startup without + // significantly reducing the VMs ability to promptly react to reduced + // memory availability + set_cache_expiry_time(OSCONTAINER_CACHE_TIMEOUT); + } + +}; + +CgroupMemorySubsystem* memory = NULL; CgroupSubsystem* cpuset = NULL; CgroupSubsystem* cpu = NULL; CgroupSubsystem* cpuacct = NULL; @@ -113,21 +159,24 @@ PRAGMA_DIAG_PUSH PRAGMA_FORMAT_NONLITERAL_IGNORED -template <typename T> int subsystem_file_contents(CgroupSubsystem* c, +template <typename T> int subsystem_file_line_contents(CgroupSubsystem* c, const char *filename, + const char *matchline, const char *scan_fmt, T returnval) { FILE *fp = NULL; char *p; char file[MAXPATHLEN+1]; char buf[MAXPATHLEN+1]; + char discard[MAXPATHLEN+1]; + bool found_match = false; if (c == NULL) { - log_debug(os, container)("subsystem_file_contents: CgroupSubsytem* is NULL"); + log_debug(os, container)("subsystem_file_line_contents: CgroupSubsytem* is NULL"); return OSCONTAINER_ERROR; } if (c->subsystem_path() == NULL) { - log_debug(os, container)("subsystem_file_contents: subsystem path is NULL"); + log_debug(os, container)("subsystem_file_line_contents: subsystem path is NULL"); return OSCONTAINER_ERROR; } @@ -142,16 +191,32 @@ log_trace(os, container)("Path to %s is %s", filename, file); fp = fopen(file, "r"); if (fp != NULL) { - p = fgets(buf, MAXPATHLEN, fp); - if (p != NULL) { - int matched = sscanf(p, scan_fmt, returnval); - if (matched == 1) { + int err = 0; + while ((p = fgets(buf, MAXPATHLEN, fp)) != NULL) { + found_match = false; + if (matchline == NULL) { + // single-line file case + int matched = sscanf(p, scan_fmt, returnval); + found_match = (matched == 1); + } else { + // multi-line file case + if (strstr(p, matchline) != NULL) { + // discard matchline string prefix + int matched = sscanf(p, scan_fmt, discard, returnval); + found_match = (matched == 2); + } else { + continue; // substring not found + } + } + if (found_match) { fclose(fp); return 0; } else { + err = 1; log_debug(os, container)("Type %s not found in file %s", scan_fmt, file); } - } else { + } + if (err == 0) { log_debug(os, container)("Empty file %s", file); } } else { @@ -168,10 +233,11 @@ return_type variable; \ { \ int err; \ - err = subsystem_file_contents(subsystem, \ - filename, \ - scan_fmt, \ - &variable); \ + err = subsystem_file_line_contents(subsystem, \ + filename, \ + NULL, \ + scan_fmt, \ + &variable); \ if (err != 0) \ return (return_type) OSCONTAINER_ERROR; \ \ @@ -183,32 +249,44 @@ char variable[bufsize]; \ { \ int err; \ - err = subsystem_file_contents(subsystem, \ - filename, \ - scan_fmt, \ - variable); \ + err = subsystem_file_line_contents(subsystem, \ + filename, \ + NULL, \ + scan_fmt, \ + variable); \ if (err != 0) \ return (return_type) NULL; \ \ log_trace(os, container)(logstring, variable); \ } +#define GET_CONTAINER_INFO_LINE(return_type, subsystem, filename, \ + matchline, logstring, scan_fmt, variable) \ + return_type variable; \ +{ \ + int err; \ + err = subsystem_file_line_contents(subsystem, \ + filename, \ + matchline, \ + scan_fmt, \ + &variable); \ + if (err != 0) \ + return (return_type) OSCONTAINER_ERROR; \ + \ + log_trace(os, container)(logstring, variable); \ +} + /* init * * Initialize the container support and determine if * we are running under cgroup control. */ void OSContainer::init() { - int mountid; - int parentid; - int major; - int minor; FILE *mntinfo = NULL; FILE *cgroup = NULL; char buf[MAXPATHLEN+1]; char tmproot[MAXPATHLEN+1]; char tmpmount[MAXPATHLEN+1]; - char tmpbase[MAXPATHLEN+1]; char *p; jlong mem_limit; @@ -242,85 +320,24 @@ return; } - while ( (p = fgets(buf, MAXPATHLEN, mntinfo)) != NULL) { - // Look for the filesystem type and see if it's cgroup - char fstype[MAXPATHLEN+1]; - fstype[0] = '\0'; - char *s = strstr(p, " - "); - if (s != NULL && - sscanf(s, " - %s", fstype) == 1 && - strcmp(fstype, "cgroup") == 0) { + while ((p = fgets(buf, MAXPATHLEN, mntinfo)) != NULL) { + char tmpcgroups[MAXPATHLEN+1]; + char *cptr = tmpcgroups; + char *token; - if (strstr(p, "memory") != NULL) { - int matched = sscanf(p, "%d %d %d:%d %s %s", - &mountid, - &parentid, - &major, - &minor, - tmproot, - tmpmount); - if (matched == 6) { - memory = new CgroupSubsystem(tmproot, tmpmount); - } - else - log_debug(os, container)("Incompatible str containing cgroup and memory: %s", p); - } else if (strstr(p, "cpuset") != NULL) { - int matched = sscanf(p, "%d %d %d:%d %s %s", - &mountid, - &parentid, - &major, - &minor, - tmproot, - tmpmount); - if (matched == 6) { - cpuset = new CgroupSubsystem(tmproot, tmpmount); - } - else { - log_debug(os, container)("Incompatible str containing cgroup and cpuset: %s", p); - } - } else if (strstr(p, "cpu,cpuacct") != NULL || strstr(p, "cpuacct,cpu") != NULL) { - int matched = sscanf(p, "%d %d %d:%d %s %s", - &mountid, - &parentid, - &major, - &minor, - tmproot, - tmpmount); - if (matched == 6) { - cpu = new CgroupSubsystem(tmproot, tmpmount); - cpuacct = new CgroupSubsystem(tmproot, tmpmount); - } - else { - log_debug(os, container)("Incompatible str containing cgroup and cpu,cpuacct: %s", p); - } - } else if (strstr(p, "cpuacct") != NULL) { - int matched = sscanf(p, "%d %d %d:%d %s %s", - &mountid, - &parentid, - &major, - &minor, - tmproot, - tmpmount); - if (matched == 6) { - cpuacct = new CgroupSubsystem(tmproot, tmpmount); - } - else { - log_debug(os, container)("Incompatible str containing cgroup and cpuacct: %s", p); - } - } else if (strstr(p, "cpu") != NULL) { - int matched = sscanf(p, "%d %d %d:%d %s %s", - &mountid, - &parentid, - &major, - &minor, - tmproot, - tmpmount); - if (matched == 6) { - cpu = new CgroupSubsystem(tmproot, tmpmount); - } - else { - log_debug(os, container)("Incompatible str containing cgroup and cpu: %s", p); - } + // mountinfo format is documented at https://www.kernel.org/doc/Documentation/filesystems/proc.txt + if (sscanf(p, "%*d %*d %*d:%*d %s %s %*[^-]- cgroup %*s %s", tmproot, tmpmount, tmpcgroups) != 3) { + continue; + } + while ((token = strsep(&cptr, ",")) != NULL) { + if (strcmp(token, "memory") == 0) { + memory = new CgroupMemorySubsystem(tmproot, tmpmount); + } else if (strcmp(token, "cpuset") == 0) { + cpuset = new CgroupSubsystem(tmproot, tmpmount); + } else if (strcmp(token, "cpu") == 0) { + cpu = new CgroupSubsystem(tmproot, tmpmount); + } else if (strcmp(token, "cpuacct") == 0) { + cpuacct= new CgroupSubsystem(tmproot, tmpmount); } } } @@ -374,30 +391,34 @@ return; } - while ( (p = fgets(buf, MAXPATHLEN, cgroup)) != NULL) { - int cgno; - int matched; - char *controller; + while ((p = fgets(buf, MAXPATHLEN, cgroup)) != NULL) { + char *controllers; + char *token; char *base; /* Skip cgroup number */ strsep(&p, ":"); - /* Get controller and base */ - controller = strsep(&p, ":"); + /* Get controllers and base */ + controllers = strsep(&p, ":"); base = strsep(&p, "\n"); - if (controller != NULL) { - if (strstr(controller, "memory") != NULL) { + if (controllers == NULL) { + continue; + } + + while ((token = strsep(&controllers, ",")) != NULL) { + if (strcmp(token, "memory") == 0) { memory->set_subsystem_path(base); - } else if (strstr(controller, "cpuset") != NULL) { + jlong hierarchy = uses_mem_hierarchy(); + if (hierarchy > 0) { + memory->set_hierarchical(true); + } + } else if (strcmp(token, "cpuset") == 0) { cpuset->set_subsystem_path(base); - } else if (strstr(controller, "cpu,cpuacct") != NULL || strstr(controller, "cpuacct,cpu") != NULL) { + } else if (strcmp(token, "cpu") == 0) { cpu->set_subsystem_path(base); + } else if (strcmp(token, "cpuacct") == 0) { cpuacct->set_subsystem_path(base); - } else if (strstr(controller, "cpuacct") != NULL) { - cpuacct->set_subsystem_path(base); - } else if (strstr(controller, "cpu") != NULL) { - cpu->set_subsystem_path(base); } } } @@ -408,6 +429,7 @@ // command line arguments have been processed. if ((mem_limit = memory_limit_in_bytes()) > 0) { os::Linux::set_physical_memory(mem_limit); + log_info(os, container)("Memory Limit is: " JLONG_FORMAT, mem_limit); } _is_containerized = true; @@ -422,6 +444,21 @@ } } +/* uses_mem_hierarchy + * + * Return whether or not hierarchical cgroup accounting is being + * done. + * + * return: + * A number > 0 if true, or + * OSCONTAINER_ERROR for not supported + */ +jlong OSContainer::uses_mem_hierarchy() { + GET_CONTAINER_INFO(jlong, memory, "/memory.use_hierarchy", + "Use Hierarchy is: " JLONG_FORMAT, JLONG_FORMAT, use_hierarchy); + return use_hierarchy; +} + /* memory_limit_in_bytes * @@ -433,11 +470,32 @@ * OSCONTAINER_ERROR for not supported */ jlong OSContainer::memory_limit_in_bytes() { + if (!memory->cache_has_expired()) { + return memory->memory_limit_in_bytes(); + } + jlong memory_limit = read_memory_limit_in_bytes(); + // Update CgroupMemorySubsystem to avoid re-reading container settings too often + memory->set_memory_limit_in_bytes(memory_limit); + return memory_limit; +} + +jlong OSContainer::read_memory_limit_in_bytes() { GET_CONTAINER_INFO(julong, memory, "/memory.limit_in_bytes", "Memory Limit is: " JULONG_FORMAT, JULONG_FORMAT, memlimit); if (memlimit >= _unlimited_memory) { - log_trace(os, container)("Memory Limit is: Unlimited"); + log_trace(os, container)("Non-Hierarchical Memory Limit is: Unlimited"); + if (memory->is_hierarchical()) { + const char* matchline = "hierarchical_memory_limit"; + const char* format = "%s " JULONG_FORMAT; + GET_CONTAINER_INFO_LINE(julong, memory, "/memory.stat", matchline, + "Hierarchical Memory Limit is: " JULONG_FORMAT, format, hier_memlimit) + if (hier_memlimit >= _unlimited_memory) { + log_trace(os, container)("Hierarchical Memory Limit is: Unlimited"); + } else { + return (jlong)hier_memlimit; + } + } return (jlong)-1; } else { @@ -449,7 +507,18 @@ GET_CONTAINER_INFO(julong, memory, "/memory.memsw.limit_in_bytes", "Memory and Swap Limit is: " JULONG_FORMAT, JULONG_FORMAT, memswlimit); if (memswlimit >= _unlimited_memory) { - log_trace(os, container)("Memory and Swap Limit is: Unlimited"); + log_trace(os, container)("Non-Hierarchical Memory and Swap Limit is: Unlimited"); + if (memory->is_hierarchical()) { + const char* matchline = "hierarchical_memsw_limit"; + const char* format = "%s " JULONG_FORMAT; + GET_CONTAINER_INFO_LINE(julong, memory, "/memory.stat", matchline, + "Hierarchical Memory and Swap Limit is : " JULONG_FORMAT, format, hier_memlimit) + if (hier_memlimit >= _unlimited_memory) { + log_trace(os, container)("Hierarchical Memory and Swap Limit is: Unlimited"); + } else { + return (jlong)hier_memlimit; + } + } return (jlong)-1; } else { return (jlong)memswlimit; @@ -537,6 +606,14 @@ int cpu_count, limit_count; int result; + // We use a cache with a timeout to avoid performing expensive + // computations in the event this function is called frequently. + // [See 8227006]. + if (!cpu->cache_has_expired()) { + log_trace(os, container)("OSContainer::active_processor_count (cached): %d", OSContainer::_active_processor_count); + return OSContainer::_active_processor_count; + } + cpu_count = limit_count = os::Linux::active_processor_count(); int quota = cpu_quota(); int period = cpu_period(); @@ -569,6 +646,11 @@ result = MIN2(cpu_count, limit_count); log_trace(os, container)("OSContainer::active_processor_count: %d", result); + + // Update the value and reset the cache timeout + OSContainer::_active_processor_count = result; + cpu->set_cache_expiry_time(OSCONTAINER_CACHE_TIMEOUT); + return result; }
diff --git a/src/hotspot/os/linux/osContainer_linux.hpp b/src/hotspot/os/linux/osContainer_linux.hpp index 0a81364..5adad29 100644 --- a/src/hotspot/os/linux/osContainer_linux.hpp +++ b/src/hotspot/os/linux/osContainer_linux.hpp
@@ -31,17 +31,24 @@ #define OSCONTAINER_ERROR (-2) +// 20ms timeout between re-reads of memory limit and _active_processor_count. +#define OSCONTAINER_CACHE_TIMEOUT (NANOSECS_PER_SEC/50) + class OSContainer: AllStatic { private: static bool _is_initialized; static bool _is_containerized; + static int _active_processor_count; + + static jlong read_memory_limit_in_bytes(); public: static void init(); static inline bool is_containerized(); static const char * container_type(); + static jlong uses_mem_hierarchy(); static jlong memory_limit_in_bytes(); static jlong memory_and_swap_limit_in_bytes(); static jlong memory_soft_limit_in_bytes();
diff --git a/src/hotspot/os/linux/os_linux.cpp b/src/hotspot/os/linux/os_linux.cpp index 4a7986e..f31a474 100644 --- a/src/hotspot/os/linux/os_linux.cpp +++ b/src/hotspot/os/linux/os_linux.cpp
@@ -33,6 +33,7 @@ #include "compiler/disassembler.hpp" #include "interpreter/interpreter.hpp" #include "logging/log.hpp" +#include "logging/logStream.hpp" #include "memory/allocation.inline.hpp" #include "memory/filemap.hpp" #include "oops/oop.inline.hpp" @@ -61,6 +62,7 @@ #include "runtime/threadCritical.hpp" #include "runtime/threadSMR.hpp" #include "runtime/timer.hpp" +#include "runtime/vm_version.hpp" #include "semaphore_posix.hpp" #include "services/attachListener.hpp" #include "services/memTracker.hpp" @@ -106,6 +108,9 @@ # include <stdint.h> # include <inttypes.h> # include <sys/ioctl.h> +#ifdef __GLIBC__ +# include <malloc.h> +#endif #ifndef _GNU_SOURCE #define _GNU_SOURCE @@ -409,7 +414,14 @@ #if defined(AMD64) || (defined(_LP64) && defined(SPARC)) || defined(PPC64) || defined(S390) #define DEFAULT_LIBPATH "/usr/lib64:/lib64:/lib:/usr/lib" #else +#if defined(AARCH64) + // Use 32-bit locations first for AARCH64 (a 64-bit architecture), since some systems + // might not adhere to the FHS and it would be a change in behaviour if we used + // DEFAULT_LIBPATH of other 64-bit architectures which prefer the 64-bit paths. + #define DEFAULT_LIBPATH "/lib:/usr/lib:/usr/lib64:/lib64" +#else #define DEFAULT_LIBPATH "/lib:/usr/lib" +#endif // AARCH64 #endif // Base path of extensions installed on the system. @@ -848,6 +860,13 @@ } else { log_warning(os, thread)("Failed to start thread - pthread_create failed (%s) for attributes: %s.", os::errno_name(ret), os::Posix::describe_pthread_attr(buf, sizeof(buf), &attr)); + // Log some OS information which might explain why creating the thread failed. + log_info(os, thread)("Number of threads approx. running in the VM: %d", Threads::number_of_threads()); + LogStream st(Log(os, thread)::info()); + os::Posix::print_rlimit_info(&st); + os::print_memory_info(&st); + os::Linux::print_proc_sys_info(&st); + os::Linux::print_container_info(&st); } pthread_attr_destroy(&attr); @@ -1497,8 +1516,15 @@ } // Die immediately, no exit hook, no abort hook, no cleanup. +// Dump a core file, if possible, for debugging. void os::die() { - ::abort(); + if (TestUnresponsiveErrorHandler && !CreateCoredumpOnCrash) { + // For TimeoutInErrorHandlingTest.java, we just kill the VM + // and don't take the time to generate a core file. + os::signal_raise(SIGKILL); + } else { + ::abort(); + } } @@ -1707,6 +1733,8 @@ void * result = NULL; bool load_attempted = false; + log_info(os)("attempting shared library load of %s", filename); + // Check whether the library to load might change execution rights // of the stack. If they are changed, the protection of the stack // guard pages will be lost. We need a safepoint to fix this. @@ -1927,8 +1955,19 @@ int ebuflen) { void * result = ::dlopen(filename, RTLD_LAZY); if (result == NULL) { - ::strncpy(ebuf, ::dlerror(), ebuflen - 1); - ebuf[ebuflen-1] = '\0'; + const char* error_report = ::dlerror(); + if (error_report == NULL) { + error_report = "dlerror returned no error description"; + } + if (ebuf != NULL && ebuflen > 0) { + ::strncpy(ebuf, error_report, ebuflen-1); + ebuf[ebuflen-1]='\0'; + } + Events::log(NULL, "Loading shared library %s failed, %s", filename, error_report); + log_info(os)("shared library load of %s failed, %s", filename, error_report); + } else { + Events::log(NULL, "Loaded shared library %s", filename); + log_info(os)("shared library load of %s was successful", filename); } return result; } @@ -1993,34 +2032,12 @@ return true; } -#if defined(S390) || defined(PPC64) -// keywords_to_match - NULL terminated array of keywords -static bool print_matching_lines_from_file(const char* filename, outputStream* st, const char* keywords_to_match[]) { - char* line = NULL; - size_t length = 0; - FILE* fp = fopen(filename, "r"); - if (fp == NULL) { - return false; +static void _print_ascii_file_h(const char* header, const char* filename, outputStream* st) { + st->print_cr("%s:", header); + if (!_print_ascii_file(filename, st)) { + st->print_cr("<Not Available>"); } - - st->print_cr("Virtualization information:"); - while (getline(&line, &length, fp) != -1) { - int i = 0; - while (keywords_to_match[i] != NULL) { - if (strncmp(line, keywords_to_match[i], strlen(keywords_to_match[i])) == 0) { - st->print("%s", line); - break; - } - i++; - } - } - - free(line); - fclose(fp); - - return true; } -#endif void os::print_dll_info(outputStream *st) { st->print_cr("Dynamic libraries:"); @@ -2045,17 +2062,18 @@ // Read line by line from 'file' while (fgets(line, sizeof(line), procmapsFile) != NULL) { - u8 base, top, offset, inode; - char permissions[5]; - char device[6]; - char name[PATH_MAX + 1]; + u8 base, top, inode; + char name[sizeof(line)]; - // Parse fields from line - sscanf(line, UINT64_FORMAT_X "-" UINT64_FORMAT_X " %4s " UINT64_FORMAT_X " %7s " INT64_FORMAT " %s", - &base, &top, permissions, &offset, device, &inode, name); + // Parse fields from line, discard perms, offset and device + int matches = sscanf(line, UINT64_FORMAT_X "-" UINT64_FORMAT_X " %*s %*s %*s " INT64_FORMAT " %s", + &base, &top, &inode, name); + // the last entry 'name' is empty for some entries, so we might have 3 matches instead of 4 for some lines + if (matches < 3) continue; + if (matches == 3) name[0] = '\0'; - // Filter by device id '00:00' so that we only get file system mapped files. - if (strcmp(device, "00:00") != 0) { + // Filter by inode 0 so that we only get file system mapped files. + if (inode != 0) { // Call callback with the fields of interest if(callback(name, (address)base, (address)top, param)) { @@ -2086,6 +2104,8 @@ os::Posix::print_uname_info(st); + os::Linux::print_uptime_info(st); + // Print warning if unsafe chroot environment detected if (unsafe_chroot_detected) { st->print("WARNING!! "); @@ -2098,7 +2118,10 @@ os::Posix::print_load_average(st); - os::Linux::print_full_memory_info(st); + os::Linux::print_system_memory_info(st); + st->cr(); + + os::Linux::print_process_memory_info(st); os::Linux::print_proc_sys_info(st); @@ -2106,7 +2129,7 @@ os::Linux::print_container_info(st); - os::Linux::print_virtualization_info(st); + VM_Version::print_platform_virtualization_info(st); os::Linux::print_steal_info(st); } @@ -2244,26 +2267,87 @@ void os::Linux::print_proc_sys_info(outputStream* st) { st->cr(); - st->print_cr("/proc/sys/kernel/threads-max (system-wide limit on the number of threads):"); - _print_ascii_file("/proc/sys/kernel/threads-max", st); - st->cr(); - st->cr(); - - st->print_cr("/proc/sys/vm/max_map_count (maximum number of memory map areas a process may have):"); - _print_ascii_file("/proc/sys/vm/max_map_count", st); - st->cr(); - st->cr(); - - st->print_cr("/proc/sys/kernel/pid_max (system-wide limit on number of process identifiers):"); - _print_ascii_file("/proc/sys/kernel/pid_max", st); - st->cr(); - st->cr(); + _print_ascii_file_h("/proc/sys/kernel/threads-max (system-wide limit on the number of threads)", + "/proc/sys/kernel/threads-max", st); + _print_ascii_file_h("/proc/sys/vm/max_map_count (maximum number of memory map areas a process may have)", + "/proc/sys/vm/max_map_count", st); + _print_ascii_file_h("/proc/sys/kernel/pid_max (system-wide limit on number of process identifiers)", + "/proc/sys/kernel/pid_max", st); } -void os::Linux::print_full_memory_info(outputStream* st) { - st->print("\n/proc/meminfo:\n"); - _print_ascii_file("/proc/meminfo", st); +void os::Linux::print_system_memory_info(outputStream* st) { + _print_ascii_file_h("\n/proc/meminfo", "/proc/meminfo", st); st->cr(); + + // some information regarding THPs; for details see + // https://www.kernel.org/doc/Documentation/vm/transhuge.txt + _print_ascii_file_h("/sys/kernel/mm/transparent_hugepage/enabled", + "/sys/kernel/mm/transparent_hugepage/enabled", st); + _print_ascii_file_h("/sys/kernel/mm/transparent_hugepage/defrag (defrag/compaction efforts parameter)", + "/sys/kernel/mm/transparent_hugepage/defrag", st); +} + +void os::Linux::print_process_memory_info(outputStream* st) { + + st->print_cr("Process Memory:"); + + // Print virtual and resident set size; peak values; swap; and for + // rss its components if the kernel is recent enough. + ssize_t vmsize = -1, vmpeak = -1, vmswap = -1, + vmrss = -1, vmhwm = -1, rssanon = -1, rssfile = -1, rssshmem = -1; + const int num_values = 8; + int num_found = 0; + FILE* f = ::fopen("/proc/self/status", "r"); + char buf[256]; + if (f != NULL) { + while (::fgets(buf, sizeof(buf), f) != NULL && num_found < num_values) { + if ( (vmsize == -1 && sscanf(buf, "VmSize: " SSIZE_FORMAT " kB", &vmsize) == 1) || + (vmpeak == -1 && sscanf(buf, "VmPeak: " SSIZE_FORMAT " kB", &vmpeak) == 1) || + (vmswap == -1 && sscanf(buf, "VmSwap: " SSIZE_FORMAT " kB", &vmswap) == 1) || + (vmhwm == -1 && sscanf(buf, "VmHWM: " SSIZE_FORMAT " kB", &vmhwm) == 1) || + (vmrss == -1 && sscanf(buf, "VmRSS: " SSIZE_FORMAT " kB", &vmrss) == 1) || + (rssanon == -1 && sscanf(buf, "RssAnon: " SSIZE_FORMAT " kB", &rssanon) == 1) || + (rssfile == -1 && sscanf(buf, "RssFile: " SSIZE_FORMAT " kB", &rssfile) == 1) || + (rssshmem == -1 && sscanf(buf, "RssShmem: " SSIZE_FORMAT " kB", &rssshmem) == 1) + ) + { + num_found ++; + } + } + fclose(f); + + st->print_cr("Virtual Size: " SSIZE_FORMAT "K (peak: " SSIZE_FORMAT "K)", vmsize, vmpeak); + st->print("Resident Set Size: " SSIZE_FORMAT "K (peak: " SSIZE_FORMAT "K)", vmrss, vmhwm); + if (rssanon != -1) { // requires kernel >= 4.5 + st->print(" (anon: " SSIZE_FORMAT "K, file: " SSIZE_FORMAT "K, shmem: " SSIZE_FORMAT "K)", + rssanon, rssfile, rssshmem); + } + st->cr(); + if (vmswap != -1) { // requires kernel >= 2.6.34 + st->print_cr("Swapped out: " SSIZE_FORMAT "K", vmswap); + } + } else { + st->print_cr("Could not open /proc/self/status to get process memory related information"); + } + + // Print glibc outstanding allocations. + // (note: there is no implementation of mallinfo for muslc) +#ifdef __GLIBC__ + struct mallinfo mi = ::mallinfo(); + + // mallinfo is an old API. Member names mean next to nothing and, beyond that, are int. + // So values may have wrapped around. Still useful enough to see how much glibc thinks + // we allocated. + const size_t total_allocated = (size_t)(unsigned)mi.uordblks; + st->print("C-Heap outstanding allocations: " SIZE_FORMAT "K", total_allocated / K); + // Since mallinfo members are int, glibc values may have wrapped. Warn about this. + if ((vmrss * K) > UINT_MAX && (vmrss * K) > (total_allocated + UINT_MAX)) { + st->print(" (may have wrapped)"); + } + st->cr(); + +#endif // __GLIBC__ + } void os::Linux::print_ld_preload_file(outputStream* st) { @@ -2271,6 +2355,15 @@ st->cr(); } +void os::Linux::print_uptime_info(outputStream* st) { + struct sysinfo sinfo; + int ret = sysinfo(&sinfo); + if (ret == 0) { + os::print_dhm(st, "OS uptime:", (long) sinfo.uptime); + } +} + + void os::Linux::print_container_info(outputStream* st) { if (!OSContainer::is_containerized()) { return; @@ -2322,40 +2415,6 @@ st->cr(); } -void os::Linux::print_virtualization_info(outputStream* st) { -#if defined(S390) - // /proc/sysinfo contains interesting information about - // - LPAR - // - whole "Box" (CPUs ) - // - z/VM / KVM (VM<nn>); this is not available in an LPAR-only setup - const char* kw[] = { "LPAR", "CPUs", "VM", NULL }; - const char* info_file = "/proc/sysinfo"; - - if (!print_matching_lines_from_file(info_file, st, kw)) { - st->print_cr(" <%s Not Available>", info_file); - } -#elif defined(PPC64) - const char* info_file = "/proc/ppc64/lparcfg"; - const char* kw[] = { "system_type=", // qemu indicates PowerKVM - "partition_entitled_capacity=", // entitled processor capacity percentage - "partition_max_entitled_capacity=", - "capacity_weight=", // partition CPU weight - "partition_active_processors=", - "partition_potential_processors=", - "entitled_proc_capacity_available=", - "capped=", // 0 - uncapped, 1 - vcpus capped at entitled processor capacity percentage - "shared_processor_mode=", // (non)dedicated partition - "system_potential_processors=", - "pool=", // CPU-pool number - "pool_capacity=", - "NumLpars=", // on non-KVM machines, NumLpars is not found for full partition mode machines - NULL }; - if (!print_matching_lines_from_file(info_file, st, kw)) { - st->print_cr(" <%s Not Available>", info_file); - } -#endif -} - void os::Linux::print_steal_info(outputStream* st) { if (has_initial_tick_info) { CPUPerfTicks pticks; @@ -2432,14 +2491,60 @@ return false; } +// additional information about CPU e.g. available frequency ranges +static void print_sys_devices_cpu_info(outputStream* st, char* buf, size_t buflen) { + _print_ascii_file_h("Online cpus", "/sys/devices/system/cpu/online", st); + _print_ascii_file_h("Offline cpus", "/sys/devices/system/cpu/offline", st); + + if (ExtensiveErrorReports) { + // cache related info (cpu 0, should be similar for other CPUs) + for (unsigned int i=0; i < 10; i++) { // handle max. 10 cache entries + char hbuf_level[60]; + char hbuf_type[60]; + char hbuf_size[60]; + char hbuf_coherency_line_size[80]; + snprintf(hbuf_level, 60, "/sys/devices/system/cpu/cpu0/cache/index%u/level", i); + snprintf(hbuf_type, 60, "/sys/devices/system/cpu/cpu0/cache/index%u/type", i); + snprintf(hbuf_size, 60, "/sys/devices/system/cpu/cpu0/cache/index%u/size", i); + snprintf(hbuf_coherency_line_size, 80, "/sys/devices/system/cpu/cpu0/cache/index%u/coherency_line_size", i); + if (file_exists(hbuf_level)) { + _print_ascii_file_h("cache level", hbuf_level, st); + _print_ascii_file_h("cache type", hbuf_type, st); + _print_ascii_file_h("cache size", hbuf_size, st); + _print_ascii_file_h("cache coherency line size", hbuf_coherency_line_size, st); + } + } + } + + // we miss the cpufreq entries on Power and s390x +#if defined(IA32) || defined(AMD64) + _print_ascii_file_h("BIOS frequency limitation", "/sys/devices/system/cpu/cpu0/cpufreq/bios_limit", st); + _print_ascii_file_h("Frequency switch latency (ns)", "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_transition_latency", st); + _print_ascii_file_h("Available cpu frequencies", "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", st); + // min and max should be in the Available range but still print them (not all info might be available for all kernels) + if (ExtensiveErrorReports) { + _print_ascii_file_h("Maximum cpu frequency", "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq", st); + _print_ascii_file_h("Minimum cpu frequency", "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_min_freq", st); + _print_ascii_file_h("Current cpu frequency", "/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq", st); + } + // governors are power schemes, see https://wiki.archlinux.org/index.php/CPU_frequency_scaling + if (ExtensiveErrorReports) { + _print_ascii_file_h("Available governors", "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", st); + } + _print_ascii_file_h("Current governor", "/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor", st); + // Core performance boost, see https://www.kernel.org/doc/Documentation/cpu-freq/boost.txt + // Raise operating frequency of some cores in a multi-core package if certain conditions apply, e.g. + // whole chip is not fully utilized + _print_ascii_file_h("Core performance/turbo boost", "/sys/devices/system/cpu/cpufreq/boost", st); +#endif +} + void os::pd_print_cpu_info(outputStream* st, char* buf, size_t buflen) { // Only print the model name if the platform provides this as a summary if (!print_model_name_and_flags(st, buf, buflen)) { - st->print("\n/proc/cpuinfo:\n"); - if (!_print_ascii_file("/proc/cpuinfo", st)) { - st->print_cr(" <Not Available>"); - } + _print_ascii_file_h("\n/proc/cpuinfo", "/proc/cpuinfo", st); } + print_sys_devices_cpu_info(st, buf, buflen); } #if defined(AMD64) || defined(IA32) || defined(X32) @@ -2550,6 +2655,7 @@ } char dli_fname[MAXPATHLEN]; + dli_fname[0] = '\0'; bool ret = dll_address_to_library_name( CAST_FROM_FN_PTR(address, os::jvm_path), dli_fname, sizeof(dli_fname), NULL); @@ -3537,6 +3643,7 @@ assert(addr == bottom, "sanity check"); size = align_up(pointer_delta(addr, bottom, 1) + size, os::Linux::page_size()); + Events::log(NULL, "Protecting memory [" INTPTR_FORMAT "," INTPTR_FORMAT "] with protection modes %x", p2i(bottom), p2i(bottom+size), prot); return ::mprotect(bottom, size, prot) == 0; } @@ -4256,33 +4363,6 @@ return ::pread(fd, buf, nBytes, offset); } -// Short sleep, direct OS call. -// -// Note: certain versions of Linux CFS scheduler (since 2.6.23) do not guarantee -// sched_yield(2) will actually give up the CPU: -// -// * Alone on this pariticular CPU, keeps running. -// * Before the introduction of "skip_buddy" with "compat_yield" disabled -// (pre 2.6.39). -// -// So calling this with 0 is an alternative. -// -void os::naked_short_sleep(jlong ms) { - struct timespec req; - - assert(ms < 1000, "Un-interruptable sleep, short time use only"); - req.tv_sec = 0; - if (ms > 0) { - req.tv_nsec = (ms % 1000) * 1000000; - } else { - req.tv_nsec = 1; - } - - nanosleep(&req, NULL); - - return; -} - // Sleep forever; naked call to OS-specific sleep; use with CAUTION void os::infinite_sleep() { while (true) { // sleep forever ... @@ -4295,6 +4375,16 @@ return DontYieldALot; } +// Linux CFS scheduler (since 2.6.23) does not guarantee sched_yield(2) will +// actually give up the CPU. Since skip buddy (v2.6.28): +// +// * Sets the yielding task as skip buddy for current CPU's run queue. +// * Picks next from run queue,