Merge "simpleperf : enhanced profiling capabilities of Instruction Decode Queue, IPC and updated DSB event types for Intel x86 Core processors" into main am: 3c6b43b1b5 Original change: https://android-review.googlesource.com/c/platform/system/extras/+/3516774 Change-Id: I94f0d73794a803f3341161aa10529ee0ed0505b9 Signed-off-by: Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com>
diff --git a/simpleperf/event_table.json b/simpleperf/event_table.json index 9caabab..739fdd8 100644 --- a/simpleperf/event_table.json +++ b/simpleperf/event_table.json
@@ -1068,7 +1068,7 @@ ["0x0160", "BACLEARS.ANY", "Count the number of BACLEARS occur when Branch Target Buffer prediction or lackthereof", "atom=0x01e6"], ["0x00c4", "BR_INST_RETIRED.ALL_BRANCHES", "Count all branch instructions retired", "atom=0x00c4"], ["0x11c4", "BR_INST_RETIRED.COND", "Count conditional branch instructions retired", "atom=0x7ec4"], - ["0x10c4", "BR_INST_RETIRED.COND_NTAKEN", "Count not taken branch instructions retired", "atom=0x0000"], + ["0x10c4", "BR_INST_RETIRED.COND_NTAKEN", "Count not taken branch instructions retired","atom=0x0000"], ["0x01c4", "BR_INST_RETIRED.COND_TAKEN", "Counts taken conditional branch instructions retired", "atom=0xfeC4"], ["0x40c4", "BR_INST_RETIRED.FAR_BRANCH", "Counts the number of far branch instructions retired", "atom=0xbfc4"], ["0x80c4", "BR_INST_RETIRED.INDIRECT", "Count near indirect branch instructions retired excluding returns", "atom=0xebc4"], @@ -1081,18 +1081,24 @@ ["0x80c5", "BR_MISP_RETIRED.INDIRECT", "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", "atom=0xebc5"], ["0x02c5", "BR_MISP_RETIRED.INDIRECT_CALL", "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", "atom=0xfbc5"], ["0x08c5", "BR_MISP_RETIRED.RET", "Counts the number of mispredicted near RET branch instructions retired.", "atom=0xf7c5"], - ["0x0261", "DSB2MITE_SWITCHES.PENALTY_CYCLES", "event counts fetch penalty cycles when a transition occurs from DSB to MITE", "atom=0x0000"], - ["0x03C6", "FRONTEND_RETIRED.ANY_DSB_MISS", "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", "atom=0x0000"], - ["0x03C6" , "FRONTEND_RETIRED.DSB_MISS", "event count number of retired Instructions that experienced a critical DSB", "atom=0x0000"], - ["0x0879", "IDQ.DSB_CYCLES_ANY", "Counts the number of cycles uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", "atom=0x0000"], - ["0x0879", "IDQ.DSB_UOPS_OK", "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", "atom=0x0000"], - ["0x0879", "IDQ.DSB_UOPS", "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", "atom=0x0000"], - ["0x0479", "IDQ.MITE_CYCLES_ANY", "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE", "atom=0x0000"], - ["0x0479", "IDQ.MITE_CYCLES_OK", "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE path", "atom=0x0000"], - ["0x0479", "IDQ.MITE_UOPS", "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path", "atom=0x0000"], - ["0x2079", "IDQ.MS_CYCLES_ANY", "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy", "atom=0x0000"], - ["0x2079", "IDQ.MS_SWITCHES", "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", "atom=0x0000"], - ["0x2079", "IDQ.MS_UOPS", "Count the number of uops initiated by by MITE or DSB and delivered to Instruction Decode Queue (IDQ) while the Micrococde sequencer (MS) is busy", "atom=0x0000"] + ["0x0261", "DSB2MITE_SWITCHES.PENALTY_CYCLES", "event counts fetch penalty cycles when a transition occurs from DSB to MITE","atom=0x0000"], + ["0x03C6", "FRONTEND_RETIRED.ANY_DSB_MISS", "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss","atom=0x0000"], + ["0x03C6" , "FRONTEND_RETIRED.DSB_MISS", "event count number of retired Instructions that experienced a critical DSB","atom=0x0000"], + ["0x0879", "IDQ.DSB_CYCLES_ANY", "Counts the number of cycles uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path","atom=0x0000"], + ["0x0879", "IDQ.DSB_CYCLES_OK", "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path","atom=0x0000"], + ["0x0879", "IDQ.DSB_UOPS", "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path","atom=0x0000"], + ["0x0479", "IDQ.MITE_CYCLES_ANY", "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE","atom=0x0000"], + ["0x0479", "IDQ.MITE_CYCLES_OK", "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE path","atom=0x0000"], + ["0x0479", "IDQ.MITE_UOPS", "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path","atom=0x0000"], + ["0x2079", "IDQ.MS_CYCLES_ANY", "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy","atom=0x0000"], + ["0x2079", "IDQ.MS_SWITCHES", "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer","atom=0x0000"], + ["0x2079", "IDQ.MS_UOPS", "Count the number of uops initiated by by MITE or DSB and delivered to Instruction Decode Queue (IDQ) while the Micrococde sequencer (MS) is busy","atom=0x0000"], + ["0x019C", "IDQ_UOPS_NOT_DELIVERED.CORE", "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.","atom=0x0000"], + ["0x069C", "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.","atom=0x0000"], + ["0x069C", "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.","atom=0x0000"], + ["0x069C", "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.","atom=0x0000"], + ["0x0100", "INST_RETIRED.ANY", "Number of instructions retired. Fixed Counter - architectural event","atom=0x0100"], + ["0x0200", "CPU_CLK_UNHALTED.THREAD", "Counts the number of unhalted core clock cycles. (Fixed event)","atom=0x0200"] ] }, "x86-amd": {