| static const IntrinToName MapData[] = { |
| { ARM::BI__builtin_arm_mve_asrl, 0, -1}, |
| { ARM::BI__builtin_arm_mve_lsll, 5, -1}, |
| { ARM::BI__builtin_arm_mve_sqrshr, 10, -1}, |
| { ARM::BI__builtin_arm_mve_sqrshrl, 17, -1}, |
| { ARM::BI__builtin_arm_mve_sqrshrl_sat48, 25, -1}, |
| { ARM::BI__builtin_arm_mve_sqshl, 39, -1}, |
| { ARM::BI__builtin_arm_mve_sqshll, 45, -1}, |
| { ARM::BI__builtin_arm_mve_srshr, 52, -1}, |
| { ARM::BI__builtin_arm_mve_srshrl, 58, -1}, |
| { ARM::BI__builtin_arm_mve_uqrshl, 65, -1}, |
| { ARM::BI__builtin_arm_mve_uqrshll, 72, -1}, |
| { ARM::BI__builtin_arm_mve_uqrshll_sat48, 80, -1}, |
| { ARM::BI__builtin_arm_mve_uqshl, 94, -1}, |
| { ARM::BI__builtin_arm_mve_uqshll, 100, -1}, |
| { ARM::BI__builtin_arm_mve_urshr, 107, -1}, |
| { ARM::BI__builtin_arm_mve_urshrl, 113, -1}, |
| { ARM::BI__builtin_arm_mve_vabavq_p_s16, 129, 120}, |
| { ARM::BI__builtin_arm_mve_vabavq_p_s32, 142, 120}, |
| { ARM::BI__builtin_arm_mve_vabavq_p_s8, 155, 120}, |
| { ARM::BI__builtin_arm_mve_vabavq_p_u16, 167, 120}, |
| { ARM::BI__builtin_arm_mve_vabavq_p_u32, 180, 120}, |
| { ARM::BI__builtin_arm_mve_vabavq_p_u8, 193, 120}, |
| { ARM::BI__builtin_arm_mve_vabavq_s16, 212, 205}, |
| { ARM::BI__builtin_arm_mve_vabavq_s32, 223, 205}, |
| { ARM::BI__builtin_arm_mve_vabavq_s8, 234, 205}, |
| { ARM::BI__builtin_arm_mve_vabavq_u16, 244, 205}, |
| { ARM::BI__builtin_arm_mve_vabavq_u32, 255, 205}, |
| { ARM::BI__builtin_arm_mve_vabavq_u8, 266, 205}, |
| { ARM::BI__builtin_arm_mve_vabdq_f16, 282, 276}, |
| { ARM::BI__builtin_arm_mve_vabdq_f32, 292, 276}, |
| { ARM::BI__builtin_arm_mve_vabdq_m_f16, 310, 302}, |
| { ARM::BI__builtin_arm_mve_vabdq_m_f32, 322, 302}, |
| { ARM::BI__builtin_arm_mve_vabdq_m_s16, 334, 302}, |
| { ARM::BI__builtin_arm_mve_vabdq_m_s32, 346, 302}, |
| { ARM::BI__builtin_arm_mve_vabdq_m_s8, 358, 302}, |
| { ARM::BI__builtin_arm_mve_vabdq_m_u16, 369, 302}, |
| { ARM::BI__builtin_arm_mve_vabdq_m_u32, 381, 302}, |
| { ARM::BI__builtin_arm_mve_vabdq_m_u8, 393, 302}, |
| { ARM::BI__builtin_arm_mve_vabdq_s16, 404, 276}, |
| { ARM::BI__builtin_arm_mve_vabdq_s32, 414, 276}, |
| { ARM::BI__builtin_arm_mve_vabdq_s8, 424, 276}, |
| { ARM::BI__builtin_arm_mve_vabdq_u16, 433, 276}, |
| { ARM::BI__builtin_arm_mve_vabdq_u32, 443, 276}, |
| { ARM::BI__builtin_arm_mve_vabdq_u8, 453, 276}, |
| { ARM::BI__builtin_arm_mve_vabdq_x_f16, 470, 462}, |
| { ARM::BI__builtin_arm_mve_vabdq_x_f32, 482, 462}, |
| { ARM::BI__builtin_arm_mve_vabdq_x_s16, 494, 462}, |
| { ARM::BI__builtin_arm_mve_vabdq_x_s32, 506, 462}, |
| { ARM::BI__builtin_arm_mve_vabdq_x_s8, 518, 462}, |
| { ARM::BI__builtin_arm_mve_vabdq_x_u16, 529, 462}, |
| { ARM::BI__builtin_arm_mve_vabdq_x_u32, 541, 462}, |
| { ARM::BI__builtin_arm_mve_vabdq_x_u8, 553, 462}, |
| { ARM::BI__builtin_arm_mve_vabsq_f16, 570, 564}, |
| { ARM::BI__builtin_arm_mve_vabsq_f32, 580, 564}, |
| { ARM::BI__builtin_arm_mve_vabsq_m_f16, 598, 590}, |
| { ARM::BI__builtin_arm_mve_vabsq_m_f32, 610, 590}, |
| { ARM::BI__builtin_arm_mve_vabsq_m_s16, 622, 590}, |
| { ARM::BI__builtin_arm_mve_vabsq_m_s32, 634, 590}, |
| { ARM::BI__builtin_arm_mve_vabsq_m_s8, 646, 590}, |
| { ARM::BI__builtin_arm_mve_vabsq_s16, 657, 564}, |
| { ARM::BI__builtin_arm_mve_vabsq_s32, 667, 564}, |
| { ARM::BI__builtin_arm_mve_vabsq_s8, 677, 564}, |
| { ARM::BI__builtin_arm_mve_vabsq_x_f16, 694, 686}, |
| { ARM::BI__builtin_arm_mve_vabsq_x_f32, 706, 686}, |
| { ARM::BI__builtin_arm_mve_vabsq_x_s16, 718, 686}, |
| { ARM::BI__builtin_arm_mve_vabsq_x_s32, 730, 686}, |
| { ARM::BI__builtin_arm_mve_vabsq_x_s8, 742, 686}, |
| { ARM::BI__builtin_arm_mve_vadciq_m_s32, 762, 753}, |
| { ARM::BI__builtin_arm_mve_vadciq_m_u32, 775, 753}, |
| { ARM::BI__builtin_arm_mve_vadciq_s32, 795, 788}, |
| { ARM::BI__builtin_arm_mve_vadciq_u32, 806, 788}, |
| { ARM::BI__builtin_arm_mve_vadcq_m_s32, 825, 817}, |
| { ARM::BI__builtin_arm_mve_vadcq_m_u32, 837, 817}, |
| { ARM::BI__builtin_arm_mve_vadcq_s32, 855, 849}, |
| { ARM::BI__builtin_arm_mve_vadcq_u32, 865, 849}, |
| { ARM::BI__builtin_arm_mve_vaddlvaq_p_s32, 886, 875}, |
| { ARM::BI__builtin_arm_mve_vaddlvaq_p_u32, 901, 875}, |
| { ARM::BI__builtin_arm_mve_vaddlvaq_s32, 925, 916}, |
| { ARM::BI__builtin_arm_mve_vaddlvaq_u32, 938, 916}, |
| { ARM::BI__builtin_arm_mve_vaddlvq_p_s32, 961, 951}, |
| { ARM::BI__builtin_arm_mve_vaddlvq_p_u32, 975, 951}, |
| { ARM::BI__builtin_arm_mve_vaddlvq_s32, 997, 989}, |
| { ARM::BI__builtin_arm_mve_vaddlvq_u32, 1009, 989}, |
| { ARM::BI__builtin_arm_mve_vaddq_f16, 1027, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_f32, 1037, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_f16, 1055, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_f32, 1067, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_n_f16, 1079, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_n_f32, 1093, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_n_s16, 1107, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_n_s32, 1121, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_n_s8, 1135, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_n_u16, 1148, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_n_u32, 1162, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_n_u8, 1176, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_s16, 1189, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_s32, 1201, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_s8, 1213, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_u16, 1224, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_u32, 1236, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_m_u8, 1248, 1047}, |
| { ARM::BI__builtin_arm_mve_vaddq_n_f16, 1259, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_n_f32, 1271, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_n_s16, 1283, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_n_s32, 1295, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_n_s8, 1307, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_n_u16, 1318, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_n_u32, 1330, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_n_u8, 1342, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_s16, 1353, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_s32, 1363, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_s8, 1373, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_u16, 1382, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_u32, 1392, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_u8, 1402, 1021}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_f16, 1419, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_f32, 1431, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_n_f16, 1443, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_n_f32, 1457, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_n_s16, 1471, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_n_s32, 1485, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_n_s8, 1499, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_n_u16, 1512, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_n_u32, 1526, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_n_u8, 1540, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_s16, 1553, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_s32, 1565, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_s8, 1577, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_u16, 1588, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_u32, 1600, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddq_x_u8, 1612, 1411}, |
| { ARM::BI__builtin_arm_mve_vaddvaq_p_s16, 1633, 1623}, |
| { ARM::BI__builtin_arm_mve_vaddvaq_p_s32, 1647, 1623}, |
| { ARM::BI__builtin_arm_mve_vaddvaq_p_s8, 1661, 1623}, |
| { ARM::BI__builtin_arm_mve_vaddvaq_p_u16, 1674, 1623}, |
| { ARM::BI__builtin_arm_mve_vaddvaq_p_u32, 1688, 1623}, |
| { ARM::BI__builtin_arm_mve_vaddvaq_p_u8, 1702, 1623}, |
| { ARM::BI__builtin_arm_mve_vaddvaq_s16, 1723, 1715}, |
| { ARM::BI__builtin_arm_mve_vaddvaq_s32, 1735, 1715}, |
| { ARM::BI__builtin_arm_mve_vaddvaq_s8, 1747, 1715}, |
| { ARM::BI__builtin_arm_mve_vaddvaq_u16, 1758, 1715}, |
| { ARM::BI__builtin_arm_mve_vaddvaq_u32, 1770, 1715}, |
| { ARM::BI__builtin_arm_mve_vaddvaq_u8, 1782, 1715}, |
| { ARM::BI__builtin_arm_mve_vaddvq_p_s16, 1802, 1793}, |
| { ARM::BI__builtin_arm_mve_vaddvq_p_s32, 1815, 1793}, |
| { ARM::BI__builtin_arm_mve_vaddvq_p_s8, 1828, 1793}, |
| { ARM::BI__builtin_arm_mve_vaddvq_p_u16, 1840, 1793}, |
| { ARM::BI__builtin_arm_mve_vaddvq_p_u32, 1853, 1793}, |
| { ARM::BI__builtin_arm_mve_vaddvq_p_u8, 1866, 1793}, |
| { ARM::BI__builtin_arm_mve_vaddvq_s16, 1885, 1878}, |
| { ARM::BI__builtin_arm_mve_vaddvq_s32, 1896, 1878}, |
| { ARM::BI__builtin_arm_mve_vaddvq_s8, 1907, 1878}, |
| { ARM::BI__builtin_arm_mve_vaddvq_u16, 1917, 1878}, |
| { ARM::BI__builtin_arm_mve_vaddvq_u32, 1928, 1878}, |
| { ARM::BI__builtin_arm_mve_vaddvq_u8, 1939, 1878}, |
| { ARM::BI__builtin_arm_mve_vandq_f16, 1955, 1949}, |
| { ARM::BI__builtin_arm_mve_vandq_f32, 1965, 1949}, |
| { ARM::BI__builtin_arm_mve_vandq_m_f16, 1983, 1975}, |
| { ARM::BI__builtin_arm_mve_vandq_m_f32, 1995, 1975}, |
| { ARM::BI__builtin_arm_mve_vandq_m_s16, 2007, 1975}, |
| { ARM::BI__builtin_arm_mve_vandq_m_s32, 2019, 1975}, |
| { ARM::BI__builtin_arm_mve_vandq_m_s8, 2031, 1975}, |
| { ARM::BI__builtin_arm_mve_vandq_m_u16, 2042, 1975}, |
| { ARM::BI__builtin_arm_mve_vandq_m_u32, 2054, 1975}, |
| { ARM::BI__builtin_arm_mve_vandq_m_u8, 2066, 1975}, |
| { ARM::BI__builtin_arm_mve_vandq_s16, 2077, 1949}, |
| { ARM::BI__builtin_arm_mve_vandq_s32, 2087, 1949}, |
| { ARM::BI__builtin_arm_mve_vandq_s8, 2097, 1949}, |
| { ARM::BI__builtin_arm_mve_vandq_u16, 2106, 1949}, |
| { ARM::BI__builtin_arm_mve_vandq_u32, 2116, 1949}, |
| { ARM::BI__builtin_arm_mve_vandq_u8, 2126, 1949}, |
| { ARM::BI__builtin_arm_mve_vandq_x_f16, 2143, 2135}, |
| { ARM::BI__builtin_arm_mve_vandq_x_f32, 2155, 2135}, |
| { ARM::BI__builtin_arm_mve_vandq_x_s16, 2167, 2135}, |
| { ARM::BI__builtin_arm_mve_vandq_x_s32, 2179, 2135}, |
| { ARM::BI__builtin_arm_mve_vandq_x_s8, 2191, 2135}, |
| { ARM::BI__builtin_arm_mve_vandq_x_u16, 2202, 2135}, |
| { ARM::BI__builtin_arm_mve_vandq_x_u32, 2214, 2135}, |
| { ARM::BI__builtin_arm_mve_vandq_x_u8, 2226, 2135}, |
| { ARM::BI__builtin_arm_mve_vbicq_f16, 2243, 2237}, |
| { ARM::BI__builtin_arm_mve_vbicq_f32, 2253, 2237}, |
| { ARM::BI__builtin_arm_mve_vbicq_m_f16, 2271, 2263}, |
| { ARM::BI__builtin_arm_mve_vbicq_m_f32, 2283, 2263}, |
| { ARM::BI__builtin_arm_mve_vbicq_m_n_s16, 2305, 2295}, |
| { ARM::BI__builtin_arm_mve_vbicq_m_n_s32, 2319, 2295}, |
| { ARM::BI__builtin_arm_mve_vbicq_m_n_u16, 2333, 2295}, |
| { ARM::BI__builtin_arm_mve_vbicq_m_n_u32, 2347, 2295}, |
| { ARM::BI__builtin_arm_mve_vbicq_m_s16, 2361, 2263}, |
| { ARM::BI__builtin_arm_mve_vbicq_m_s32, 2373, 2263}, |
| { ARM::BI__builtin_arm_mve_vbicq_m_s8, 2385, 2263}, |
| { ARM::BI__builtin_arm_mve_vbicq_m_u16, 2396, 2263}, |
| { ARM::BI__builtin_arm_mve_vbicq_m_u32, 2408, 2263}, |
| { ARM::BI__builtin_arm_mve_vbicq_m_u8, 2420, 2263}, |
| { ARM::BI__builtin_arm_mve_vbicq_n_s16, 2431, 2237}, |
| { ARM::BI__builtin_arm_mve_vbicq_n_s32, 2443, 2237}, |
| { ARM::BI__builtin_arm_mve_vbicq_n_u16, 2455, 2237}, |
| { ARM::BI__builtin_arm_mve_vbicq_n_u32, 2467, 2237}, |
| { ARM::BI__builtin_arm_mve_vbicq_s16, 2479, 2237}, |
| { ARM::BI__builtin_arm_mve_vbicq_s32, 2489, 2237}, |
| { ARM::BI__builtin_arm_mve_vbicq_s8, 2499, 2237}, |
| { ARM::BI__builtin_arm_mve_vbicq_u16, 2508, 2237}, |
| { ARM::BI__builtin_arm_mve_vbicq_u32, 2518, 2237}, |
| { ARM::BI__builtin_arm_mve_vbicq_u8, 2528, 2237}, |
| { ARM::BI__builtin_arm_mve_vbicq_x_f16, 2545, 2537}, |
| { ARM::BI__builtin_arm_mve_vbicq_x_f32, 2557, 2537}, |
| { ARM::BI__builtin_arm_mve_vbicq_x_s16, 2569, 2537}, |
| { ARM::BI__builtin_arm_mve_vbicq_x_s32, 2581, 2537}, |
| { ARM::BI__builtin_arm_mve_vbicq_x_s8, 2593, 2537}, |
| { ARM::BI__builtin_arm_mve_vbicq_x_u16, 2604, 2537}, |
| { ARM::BI__builtin_arm_mve_vbicq_x_u32, 2616, 2537}, |
| { ARM::BI__builtin_arm_mve_vbicq_x_u8, 2628, 2537}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_m_n_f16, 2648, 2639}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_m_n_f32, 2663, 2639}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_m_n_s16, 2678, 2639}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_m_n_s32, 2693, 2639}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_m_n_s8, 2708, 2639}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_m_n_u16, 2722, 2639}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_m_n_u32, 2737, 2639}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_m_n_u8, 2752, 2639}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_n_f16, 2773, 2766}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_n_f32, 2786, 2766}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_n_s16, 2799, 2766}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_n_s32, 2812, 2766}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_n_s8, 2825, 2766}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_n_u16, 2837, 2766}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_n_u32, 2850, 2766}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_n_u8, 2863, 2766}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_x_n_f16, 2884, 2875}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_x_n_f32, 2899, 2875}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_x_n_s16, 2914, 2875}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_x_n_s32, 2929, 2875}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_x_n_s8, 2944, 2875}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_x_n_u16, 2958, 2875}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_x_n_u32, 2973, 2875}, |
| { ARM::BI__builtin_arm_mve_vbrsrq_x_n_u8, 2988, 2875}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_f16, 3016, 3002}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_f32, 3034, 3002}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_f16, 3068, 3052}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_f32, 3088, 3052}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_s16, 3108, 3052}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_s32, 3128, 3052}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_s8, 3148, 3052}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_u16, 3167, 3052}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_u32, 3187, 3052}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_u8, 3207, 3052}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_s16, 3226, 3002}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_s32, 3244, 3002}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_s8, 3262, 3002}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_u16, 3279, 3002}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_u32, 3297, 3002}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_u8, 3315, 3002}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_f16, 3348, 3332}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_f32, 3368, 3332}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_s16, 3388, 3332}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_s32, 3408, 3332}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_s8, 3428, 3332}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_u16, 3447, 3332}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_u32, 3467, 3332}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_u8, 3487, 3332}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_f16, 3519, 3506}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_f32, 3536, 3506}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_f16, 3568, 3553}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_f32, 3587, 3553}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_s16, 3606, 3553}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_s32, 3625, 3553}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_s8, 3644, 3553}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_u16, 3662, 3553}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_u32, 3681, 3553}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_u8, 3700, 3553}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_s16, 3718, 3506}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_s32, 3735, 3506}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_s8, 3752, 3506}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_u16, 3768, 3506}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_u32, 3785, 3506}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_u8, 3802, 3506}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_f16, 3833, 3818}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_f32, 3852, 3818}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_s16, 3871, 3818}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_s32, 3890, 3818}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_s8, 3909, 3818}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_u16, 3927, 3818}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_u32, 3946, 3818}, |
| { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_u8, 3965, 3818}, |
| { ARM::BI__builtin_arm_mve_vclsq_m_s16, 3991, 3983}, |
| { ARM::BI__builtin_arm_mve_vclsq_m_s32, 4003, 3983}, |
| { ARM::BI__builtin_arm_mve_vclsq_m_s8, 4015, 3983}, |
| { ARM::BI__builtin_arm_mve_vclsq_s16, 4032, 4026}, |
| { ARM::BI__builtin_arm_mve_vclsq_s32, 4042, 4026}, |
| { ARM::BI__builtin_arm_mve_vclsq_s8, 4052, 4026}, |
| { ARM::BI__builtin_arm_mve_vclsq_x_s16, 4069, 4061}, |
| { ARM::BI__builtin_arm_mve_vclsq_x_s32, 4081, 4061}, |
| { ARM::BI__builtin_arm_mve_vclsq_x_s8, 4093, 4061}, |
| { ARM::BI__builtin_arm_mve_vclzq_m_s16, 4112, 4104}, |
| { ARM::BI__builtin_arm_mve_vclzq_m_s32, 4124, 4104}, |
| { ARM::BI__builtin_arm_mve_vclzq_m_s8, 4136, 4104}, |
| { ARM::BI__builtin_arm_mve_vclzq_m_u16, 4147, 4104}, |
| { ARM::BI__builtin_arm_mve_vclzq_m_u32, 4159, 4104}, |
| { ARM::BI__builtin_arm_mve_vclzq_m_u8, 4171, 4104}, |
| { ARM::BI__builtin_arm_mve_vclzq_s16, 4188, 4182}, |
| { ARM::BI__builtin_arm_mve_vclzq_s32, 4198, 4182}, |
| { ARM::BI__builtin_arm_mve_vclzq_s8, 4208, 4182}, |
| { ARM::BI__builtin_arm_mve_vclzq_u16, 4217, 4182}, |
| { ARM::BI__builtin_arm_mve_vclzq_u32, 4227, 4182}, |
| { ARM::BI__builtin_arm_mve_vclzq_u8, 4237, 4182}, |
| { ARM::BI__builtin_arm_mve_vclzq_x_s16, 4254, 4246}, |
| { ARM::BI__builtin_arm_mve_vclzq_x_s32, 4266, 4246}, |
| { ARM::BI__builtin_arm_mve_vclzq_x_s8, 4278, 4246}, |
| { ARM::BI__builtin_arm_mve_vclzq_x_u16, 4289, 4246}, |
| { ARM::BI__builtin_arm_mve_vclzq_x_u32, 4301, 4246}, |
| { ARM::BI__builtin_arm_mve_vclzq_x_u8, 4313, 4246}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_f16, 4331, 4324}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_f32, 4342, 4324}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_m_f16, 4362, 4353}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_m_f32, 4375, 4353}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_rot180_f16, 4402, 4388}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_rot180_f32, 4420, 4388}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_rot180_m_f16, 4454, 4438}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_rot180_m_f32, 4474, 4438}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_rot270_f16, 4508, 4494}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_rot270_f32, 4526, 4494}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_rot270_m_f16, 4560, 4544}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_rot270_m_f32, 4580, 4544}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_rot90_f16, 4613, 4600}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_rot90_f32, 4630, 4600}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_rot90_m_f16, 4662, 4647}, |
| { ARM::BI__builtin_arm_mve_vcmlaq_rot90_m_f32, 4681, 4647}, |
| { ARM::BI__builtin_arm_mve_vcmpcsq_m_n_u16, 4710, 4700}, |
| { ARM::BI__builtin_arm_mve_vcmpcsq_m_n_u32, 4726, 4700}, |
| { ARM::BI__builtin_arm_mve_vcmpcsq_m_n_u8, 4742, 4700}, |
| { ARM::BI__builtin_arm_mve_vcmpcsq_m_u16, 4757, 4700}, |
| { ARM::BI__builtin_arm_mve_vcmpcsq_m_u32, 4771, 4700}, |
| { ARM::BI__builtin_arm_mve_vcmpcsq_m_u8, 4785, 4700}, |
| { ARM::BI__builtin_arm_mve_vcmpcsq_n_u16, 4806, 4798}, |
| { ARM::BI__builtin_arm_mve_vcmpcsq_n_u32, 4820, 4798}, |
| { ARM::BI__builtin_arm_mve_vcmpcsq_n_u8, 4834, 4798}, |
| { ARM::BI__builtin_arm_mve_vcmpcsq_u16, 4847, 4798}, |
| { ARM::BI__builtin_arm_mve_vcmpcsq_u32, 4859, 4798}, |
| { ARM::BI__builtin_arm_mve_vcmpcsq_u8, 4871, 4798}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_f16, 4890, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_f32, 4902, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_f16, 4924, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_f32, 4938, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_f16, 4952, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_f32, 4968, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_s16, 4984, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_s32, 5000, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_s8, 5016, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_u16, 5031, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_u32, 5047, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_u8, 5063, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_s16, 5078, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_s32, 5092, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_s8, 5106, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_u16, 5119, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_u32, 5133, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_m_u8, 5147, 4914}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_n_f16, 5160, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_n_f32, 5174, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_n_s16, 5188, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_n_s32, 5202, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_n_s8, 5216, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_n_u16, 5229, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_n_u32, 5243, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_n_u8, 5257, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_s16, 5270, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_s32, 5282, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_s8, 5294, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_u16, 5305, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_u32, 5317, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpeqq_u8, 5329, 4882}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_f16, 5348, 5340}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_f32, 5360, 5340}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_m_f16, 5382, 5372}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_m_f32, 5396, 5372}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_m_n_f16, 5410, 5372}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_m_n_f32, 5426, 5372}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_m_n_s16, 5442, 5372}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_m_n_s32, 5458, 5372}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_m_n_s8, 5474, 5372}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_m_s16, 5489, 5372}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_m_s32, 5503, 5372}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_m_s8, 5517, 5372}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_n_f16, 5530, 5340}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_n_f32, 5544, 5340}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_n_s16, 5558, 5340}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_n_s32, 5572, 5340}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_n_s8, 5586, 5340}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_s16, 5599, 5340}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_s32, 5611, 5340}, |
| { ARM::BI__builtin_arm_mve_vcmpgeq_s8, 5623, 5340}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_f16, 5642, 5634}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_f32, 5654, 5634}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_m_f16, 5676, 5666}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_m_f32, 5690, 5666}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_m_n_f16, 5704, 5666}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_m_n_f32, 5720, 5666}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_m_n_s16, 5736, 5666}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_m_n_s32, 5752, 5666}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_m_n_s8, 5768, 5666}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_m_s16, 5783, 5666}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_m_s32, 5797, 5666}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_m_s8, 5811, 5666}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_n_f16, 5824, 5634}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_n_f32, 5838, 5634}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_n_s16, 5852, 5634}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_n_s32, 5866, 5634}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_n_s8, 5880, 5634}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_s16, 5893, 5634}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_s32, 5905, 5634}, |
| { ARM::BI__builtin_arm_mve_vcmpgtq_s8, 5917, 5634}, |
| { ARM::BI__builtin_arm_mve_vcmphiq_m_n_u16, 5938, 5928}, |
| { ARM::BI__builtin_arm_mve_vcmphiq_m_n_u32, 5954, 5928}, |
| { ARM::BI__builtin_arm_mve_vcmphiq_m_n_u8, 5970, 5928}, |
| { ARM::BI__builtin_arm_mve_vcmphiq_m_u16, 5985, 5928}, |
| { ARM::BI__builtin_arm_mve_vcmphiq_m_u32, 5999, 5928}, |
| { ARM::BI__builtin_arm_mve_vcmphiq_m_u8, 6013, 5928}, |
| { ARM::BI__builtin_arm_mve_vcmphiq_n_u16, 6034, 6026}, |
| { ARM::BI__builtin_arm_mve_vcmphiq_n_u32, 6048, 6026}, |
| { ARM::BI__builtin_arm_mve_vcmphiq_n_u8, 6062, 6026}, |
| { ARM::BI__builtin_arm_mve_vcmphiq_u16, 6075, 6026}, |
| { ARM::BI__builtin_arm_mve_vcmphiq_u32, 6087, 6026}, |
| { ARM::BI__builtin_arm_mve_vcmphiq_u8, 6099, 6026}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_f16, 6118, 6110}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_f32, 6130, 6110}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_m_f16, 6152, 6142}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_m_f32, 6166, 6142}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_m_n_f16, 6180, 6142}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_m_n_f32, 6196, 6142}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_m_n_s16, 6212, 6142}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_m_n_s32, 6228, 6142}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_m_n_s8, 6244, 6142}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_m_s16, 6259, 6142}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_m_s32, 6273, 6142}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_m_s8, 6287, 6142}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_n_f16, 6300, 6110}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_n_f32, 6314, 6110}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_n_s16, 6328, 6110}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_n_s32, 6342, 6110}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_n_s8, 6356, 6110}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_s16, 6369, 6110}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_s32, 6381, 6110}, |
| { ARM::BI__builtin_arm_mve_vcmpleq_s8, 6393, 6110}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_f16, 6412, 6404}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_f32, 6424, 6404}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_m_f16, 6446, 6436}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_m_f32, 6460, 6436}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_m_n_f16, 6474, 6436}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_m_n_f32, 6490, 6436}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_m_n_s16, 6506, 6436}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_m_n_s32, 6522, 6436}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_m_n_s8, 6538, 6436}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_m_s16, 6553, 6436}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_m_s32, 6567, 6436}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_m_s8, 6581, 6436}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_n_f16, 6594, 6404}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_n_f32, 6608, 6404}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_n_s16, 6622, 6404}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_n_s32, 6636, 6404}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_n_s8, 6650, 6404}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_s16, 6663, 6404}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_s32, 6675, 6404}, |
| { ARM::BI__builtin_arm_mve_vcmpltq_s8, 6687, 6404}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_f16, 6706, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_f32, 6718, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_f16, 6740, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_f32, 6754, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_n_f16, 6768, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_n_f32, 6784, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_n_s16, 6800, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_n_s32, 6816, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_n_s8, 6832, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_n_u16, 6847, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_n_u32, 6863, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_n_u8, 6879, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_s16, 6894, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_s32, 6908, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_s8, 6922, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_u16, 6935, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_u32, 6949, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_m_u8, 6963, 6730}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_n_f16, 6976, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_n_f32, 6990, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_n_s16, 7004, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_n_s32, 7018, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_n_s8, 7032, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_n_u16, 7045, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_n_u32, 7059, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_n_u8, 7073, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_s16, 7086, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_s32, 7098, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_s8, 7110, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_u16, 7121, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_u32, 7133, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmpneq_u8, 7145, 6698}, |
| { ARM::BI__builtin_arm_mve_vcmulq_f16, 7163, 7156}, |
| { ARM::BI__builtin_arm_mve_vcmulq_f32, 7174, 7156}, |
| { ARM::BI__builtin_arm_mve_vcmulq_m_f16, 7194, 7185}, |
| { ARM::BI__builtin_arm_mve_vcmulq_m_f32, 7207, 7185}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot180_f16, 7234, 7220}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot180_f32, 7252, 7220}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot180_m_f16, 7286, 7270}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot180_m_f32, 7306, 7270}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot180_x_f16, 7342, 7326}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot180_x_f32, 7362, 7326}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot270_f16, 7396, 7382}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot270_f32, 7414, 7382}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot270_m_f16, 7448, 7432}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot270_m_f32, 7468, 7432}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot270_x_f16, 7504, 7488}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot270_x_f32, 7524, 7488}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot90_f16, 7557, 7544}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot90_f32, 7574, 7544}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot90_m_f16, 7606, 7591}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot90_m_f32, 7625, 7591}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot90_x_f16, 7659, 7644}, |
| { ARM::BI__builtin_arm_mve_vcmulq_rot90_x_f32, 7678, 7644}, |
| { ARM::BI__builtin_arm_mve_vcmulq_x_f16, 7706, 7697}, |
| { ARM::BI__builtin_arm_mve_vcmulq_x_f32, 7719, 7697}, |
| { ARM::BI__builtin_arm_mve_vcreateq_f16, 7732, -1}, |
| { ARM::BI__builtin_arm_mve_vcreateq_f32, 7745, -1}, |
| { ARM::BI__builtin_arm_mve_vcreateq_s16, 7758, -1}, |
| { ARM::BI__builtin_arm_mve_vcreateq_s32, 7771, -1}, |
| { ARM::BI__builtin_arm_mve_vcreateq_s64, 7784, -1}, |
| { ARM::BI__builtin_arm_mve_vcreateq_s8, 7797, -1}, |
| { ARM::BI__builtin_arm_mve_vcreateq_u16, 7809, -1}, |
| { ARM::BI__builtin_arm_mve_vcreateq_u32, 7822, -1}, |
| { ARM::BI__builtin_arm_mve_vcreateq_u64, 7835, -1}, |
| { ARM::BI__builtin_arm_mve_vcreateq_u8, 7848, -1}, |
| { ARM::BI__builtin_arm_mve_vctp16q, 7860, -1}, |
| { ARM::BI__builtin_arm_mve_vctp16q_m, 7868, -1}, |
| { ARM::BI__builtin_arm_mve_vctp32q, 7878, -1}, |
| { ARM::BI__builtin_arm_mve_vctp32q_m, 7886, -1}, |
| { ARM::BI__builtin_arm_mve_vctp64q, 7896, -1}, |
| { ARM::BI__builtin_arm_mve_vctp64q_m, 7904, -1}, |
| { ARM::BI__builtin_arm_mve_vctp8q, 7914, -1}, |
| { ARM::BI__builtin_arm_mve_vctp8q_m, 7921, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtaq_m_s16_f16, 7939, 7930}, |
| { ARM::BI__builtin_arm_mve_vcvtaq_m_s32_f32, 7956, 7930}, |
| { ARM::BI__builtin_arm_mve_vcvtaq_m_u16_f16, 7973, 7930}, |
| { ARM::BI__builtin_arm_mve_vcvtaq_m_u32_f32, 7990, 7930}, |
| { ARM::BI__builtin_arm_mve_vcvtaq_s16_f16, 8007, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtaq_s32_f32, 8022, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtaq_u16_f16, 8037, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtaq_u32_f32, 8052, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtaq_x_s16_f16, 8067, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtaq_x_s32_f32, 8084, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtaq_x_u16_f16, 8101, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtaq_x_u32_f32, 8118, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtbq_f16_f32, 8135, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtbq_f32_f16, 8150, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtbq_m_f16_f32, 8165, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtbq_m_f32_f16, 8182, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtbq_x_f32_f16, 8199, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtmq_m_s16_f16, 8225, 8216}, |
| { ARM::BI__builtin_arm_mve_vcvtmq_m_s32_f32, 8242, 8216}, |
| { ARM::BI__builtin_arm_mve_vcvtmq_m_u16_f16, 8259, 8216}, |
| { ARM::BI__builtin_arm_mve_vcvtmq_m_u32_f32, 8276, 8216}, |
| { ARM::BI__builtin_arm_mve_vcvtmq_s16_f16, 8293, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtmq_s32_f32, 8308, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtmq_u16_f16, 8323, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtmq_u32_f32, 8338, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtmq_x_s16_f16, 8353, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtmq_x_s32_f32, 8370, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtmq_x_u16_f16, 8387, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtmq_x_u32_f32, 8404, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtnq_m_s16_f16, 8430, 8421}, |
| { ARM::BI__builtin_arm_mve_vcvtnq_m_s32_f32, 8447, 8421}, |
| { ARM::BI__builtin_arm_mve_vcvtnq_m_u16_f16, 8464, 8421}, |
| { ARM::BI__builtin_arm_mve_vcvtnq_m_u32_f32, 8481, 8421}, |
| { ARM::BI__builtin_arm_mve_vcvtnq_s16_f16, 8498, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtnq_s32_f32, 8513, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtnq_u16_f16, 8528, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtnq_u32_f32, 8543, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtnq_x_s16_f16, 8558, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtnq_x_s32_f32, 8575, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtnq_x_u16_f16, 8592, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtnq_x_u32_f32, 8609, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtpq_m_s16_f16, 8635, 8626}, |
| { ARM::BI__builtin_arm_mve_vcvtpq_m_s32_f32, 8652, 8626}, |
| { ARM::BI__builtin_arm_mve_vcvtpq_m_u16_f16, 8669, 8626}, |
| { ARM::BI__builtin_arm_mve_vcvtpq_m_u32_f32, 8686, 8626}, |
| { ARM::BI__builtin_arm_mve_vcvtpq_s16_f16, 8703, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtpq_s32_f32, 8718, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtpq_u16_f16, 8733, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtpq_u32_f32, 8748, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtpq_x_s16_f16, 8763, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtpq_x_s32_f32, 8780, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtpq_x_u16_f16, 8797, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtpq_x_u32_f32, 8814, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_f16_s16, 8837, 8831}, |
| { ARM::BI__builtin_arm_mve_vcvtq_f16_u16, 8851, 8831}, |
| { ARM::BI__builtin_arm_mve_vcvtq_f32_s32, 8865, 8831}, |
| { ARM::BI__builtin_arm_mve_vcvtq_f32_u32, 8879, 8831}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_f16_s16, 8901, 8893}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_f16_u16, 8917, 8893}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_f32_s32, 8933, 8893}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_f32_u32, 8949, 8893}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_n_f16_s16, 8975, 8965}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_n_f16_u16, 8993, 8965}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_n_f32_s32, 9011, 8965}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_n_f32_u32, 9029, 8965}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_n_s16_f16, 9047, 8965}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_n_s32_f32, 9065, 8965}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_n_u16_f16, 9083, 8965}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_n_u32_f32, 9101, 8965}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_s16_f16, 9119, 8893}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_s32_f32, 9135, 8893}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_u16_f16, 9151, 8893}, |
| { ARM::BI__builtin_arm_mve_vcvtq_m_u32_f32, 9167, 8893}, |
| { ARM::BI__builtin_arm_mve_vcvtq_n_f16_s16, 9191, 9183}, |
| { ARM::BI__builtin_arm_mve_vcvtq_n_f16_u16, 9207, 9183}, |
| { ARM::BI__builtin_arm_mve_vcvtq_n_f32_s32, 9223, 9183}, |
| { ARM::BI__builtin_arm_mve_vcvtq_n_f32_u32, 9239, 9183}, |
| { ARM::BI__builtin_arm_mve_vcvtq_n_s16_f16, 9255, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_n_s32_f32, 9271, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_n_u16_f16, 9287, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_n_u32_f32, 9303, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_s16_f16, 9319, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_s32_f32, 9333, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_u16_f16, 9347, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_u32_f32, 9361, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_f16_s16, 9383, 9375}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_f16_u16, 9399, 9375}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_f32_s32, 9415, 9375}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_f32_u32, 9431, 9375}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_n_f16_s16, 9457, 9447}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_n_f16_u16, 9475, 9447}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_n_f32_s32, 9493, 9447}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_n_f32_u32, 9511, 9447}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_n_s16_f16, 9529, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_n_s32_f32, 9547, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_n_u16_f16, 9565, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_n_u32_f32, 9583, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_s16_f16, 9601, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_s32_f32, 9617, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_u16_f16, 9633, -1}, |
| { ARM::BI__builtin_arm_mve_vcvtq_x_u32_f32, 9649, -1}, |
| { ARM::BI__builtin_arm_mve_vcvttq_f16_f32, 9665, -1}, |
| { ARM::BI__builtin_arm_mve_vcvttq_f32_f16, 9680, -1}, |
| { ARM::BI__builtin_arm_mve_vcvttq_m_f16_f32, 9695, -1}, |
| { ARM::BI__builtin_arm_mve_vcvttq_m_f32_f16, 9712, -1}, |
| { ARM::BI__builtin_arm_mve_vcvttq_x_f32_f16, 9729, -1}, |
| { ARM::BI__builtin_arm_mve_vddupq_m_n_u16, 9755, 9746}, |
| { ARM::BI__builtin_arm_mve_vddupq_m_n_u32, 9770, 9746}, |
| { ARM::BI__builtin_arm_mve_vddupq_m_n_u8, 9785, 9746}, |
| { ARM::BI__builtin_arm_mve_vddupq_m_wb_u16, 9799, 9746}, |
| { ARM::BI__builtin_arm_mve_vddupq_m_wb_u32, 9815, 9746}, |
| { ARM::BI__builtin_arm_mve_vddupq_m_wb_u8, 9831, 9746}, |
| { ARM::BI__builtin_arm_mve_vddupq_n_u16, 9857, 9846}, |
| { ARM::BI__builtin_arm_mve_vddupq_n_u32, 9881, 9870}, |
| { ARM::BI__builtin_arm_mve_vddupq_n_u8, 9904, 9894}, |
| { ARM::BI__builtin_arm_mve_vddupq_wb_u16, 9916, 9846}, |
| { ARM::BI__builtin_arm_mve_vddupq_wb_u32, 9930, 9870}, |
| { ARM::BI__builtin_arm_mve_vddupq_wb_u8, 9944, 9894}, |
| { ARM::BI__builtin_arm_mve_vddupq_x_n_u16, 9970, 9957}, |
| { ARM::BI__builtin_arm_mve_vddupq_x_n_u32, 9998, 9985}, |
| { ARM::BI__builtin_arm_mve_vddupq_x_n_u8, 10025, 10013}, |
| { ARM::BI__builtin_arm_mve_vddupq_x_wb_u16, 10039, 9957}, |
| { ARM::BI__builtin_arm_mve_vddupq_x_wb_u32, 10055, 9985}, |
| { ARM::BI__builtin_arm_mve_vddupq_x_wb_u8, 10071, 10013}, |
| { ARM::BI__builtin_arm_mve_vdupq_m_n_f16, 10094, 10086}, |
| { ARM::BI__builtin_arm_mve_vdupq_m_n_f32, 10108, 10086}, |
| { ARM::BI__builtin_arm_mve_vdupq_m_n_s16, 10122, 10086}, |
| { ARM::BI__builtin_arm_mve_vdupq_m_n_s32, 10136, 10086}, |
| { ARM::BI__builtin_arm_mve_vdupq_m_n_s8, 10150, 10086}, |
| { ARM::BI__builtin_arm_mve_vdupq_m_n_u16, 10163, 10086}, |
| { ARM::BI__builtin_arm_mve_vdupq_m_n_u32, 10177, 10086}, |
| { ARM::BI__builtin_arm_mve_vdupq_m_n_u8, 10191, 10086}, |
| { ARM::BI__builtin_arm_mve_vdupq_n_f16, 10204, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_n_f32, 10216, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_n_s16, 10228, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_n_s32, 10240, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_n_s8, 10252, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_n_u16, 10263, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_n_u32, 10275, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_n_u8, 10287, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_x_n_f16, 10298, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_x_n_f32, 10312, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_x_n_s16, 10326, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_x_n_s32, 10340, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_x_n_s8, 10354, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_x_n_u16, 10367, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_x_n_u32, 10381, -1}, |
| { ARM::BI__builtin_arm_mve_vdupq_x_n_u8, 10395, -1}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_m_n_u16, 10418, 10408}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_m_n_u32, 10434, 10408}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_m_n_u8, 10450, 10408}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_m_wb_u16, 10465, 10408}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_m_wb_u32, 10482, 10408}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_m_wb_u8, 10499, 10408}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_n_u16, 10527, 10515}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_n_u32, 10553, 10541}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_n_u8, 10578, 10567}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_wb_u16, 10591, 10515}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_wb_u32, 10606, 10541}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_wb_u8, 10621, 10567}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_x_n_u16, 10649, 10635}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_x_n_u32, 10679, 10665}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_x_n_u8, 10708, 10695}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_x_wb_u16, 10723, 10635}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_x_wb_u32, 10740, 10665}, |
| { ARM::BI__builtin_arm_mve_vdwdupq_x_wb_u8, 10757, 10695}, |
| { ARM::BI__builtin_arm_mve_veorq_f16, 10779, 10773}, |
| { ARM::BI__builtin_arm_mve_veorq_f32, 10789, 10773}, |
| { ARM::BI__builtin_arm_mve_veorq_m_f16, 10807, 10799}, |
| { ARM::BI__builtin_arm_mve_veorq_m_f32, 10819, 10799}, |
| { ARM::BI__builtin_arm_mve_veorq_m_s16, 10831, 10799}, |
| { ARM::BI__builtin_arm_mve_veorq_m_s32, 10843, 10799}, |
| { ARM::BI__builtin_arm_mve_veorq_m_s8, 10855, 10799}, |
| { ARM::BI__builtin_arm_mve_veorq_m_u16, 10866, 10799}, |
| { ARM::BI__builtin_arm_mve_veorq_m_u32, 10878, 10799}, |
| { ARM::BI__builtin_arm_mve_veorq_m_u8, 10890, 10799}, |
| { ARM::BI__builtin_arm_mve_veorq_s16, 10901, 10773}, |
| { ARM::BI__builtin_arm_mve_veorq_s32, 10911, 10773}, |
| { ARM::BI__builtin_arm_mve_veorq_s8, 10921, 10773}, |
| { ARM::BI__builtin_arm_mve_veorq_u16, 10930, 10773}, |
| { ARM::BI__builtin_arm_mve_veorq_u32, 10940, 10773}, |
| { ARM::BI__builtin_arm_mve_veorq_u8, 10950, 10773}, |
| { ARM::BI__builtin_arm_mve_veorq_x_f16, 10967, 10959}, |
| { ARM::BI__builtin_arm_mve_veorq_x_f32, 10979, 10959}, |
| { ARM::BI__builtin_arm_mve_veorq_x_s16, 10991, 10959}, |
| { ARM::BI__builtin_arm_mve_veorq_x_s32, 11003, 10959}, |
| { ARM::BI__builtin_arm_mve_veorq_x_s8, 11015, 10959}, |
| { ARM::BI__builtin_arm_mve_veorq_x_u16, 11026, 10959}, |
| { ARM::BI__builtin_arm_mve_veorq_x_u32, 11038, 10959}, |
| { ARM::BI__builtin_arm_mve_veorq_x_u8, 11050, 10959}, |
| { ARM::BI__builtin_arm_mve_vfmaq_f16, 11067, 11061}, |
| { ARM::BI__builtin_arm_mve_vfmaq_f32, 11077, 11061}, |
| { ARM::BI__builtin_arm_mve_vfmaq_m_f16, 11095, 11087}, |
| { ARM::BI__builtin_arm_mve_vfmaq_m_f32, 11107, 11087}, |
| { ARM::BI__builtin_arm_mve_vfmaq_m_n_f16, 11119, 11087}, |
| { ARM::BI__builtin_arm_mve_vfmaq_m_n_f32, 11133, 11087}, |
| { ARM::BI__builtin_arm_mve_vfmaq_n_f16, 11147, 11061}, |
| { ARM::BI__builtin_arm_mve_vfmaq_n_f32, 11159, 11061}, |
| { ARM::BI__builtin_arm_mve_vfmasq_m_n_f16, 11180, 11171}, |
| { ARM::BI__builtin_arm_mve_vfmasq_m_n_f32, 11195, 11171}, |
| { ARM::BI__builtin_arm_mve_vfmasq_n_f16, 11217, 11210}, |
| { ARM::BI__builtin_arm_mve_vfmasq_n_f32, 11230, 11210}, |
| { ARM::BI__builtin_arm_mve_vfmsq_f16, 11249, 11243}, |
| { ARM::BI__builtin_arm_mve_vfmsq_f32, 11259, 11243}, |
| { ARM::BI__builtin_arm_mve_vfmsq_m_f16, 11277, 11269}, |
| { ARM::BI__builtin_arm_mve_vfmsq_m_f32, 11289, 11269}, |
| { ARM::BI__builtin_arm_mve_vgetq_lane_f16, 11312, 11301}, |
| { ARM::BI__builtin_arm_mve_vgetq_lane_f32, 11327, 11301}, |
| { ARM::BI__builtin_arm_mve_vgetq_lane_s16, 11342, 11301}, |
| { ARM::BI__builtin_arm_mve_vgetq_lane_s32, 11357, 11301}, |
| { ARM::BI__builtin_arm_mve_vgetq_lane_s64, 11372, 11301}, |
| { ARM::BI__builtin_arm_mve_vgetq_lane_s8, 11387, 11301}, |
| { ARM::BI__builtin_arm_mve_vgetq_lane_u16, 11401, 11301}, |
| { ARM::BI__builtin_arm_mve_vgetq_lane_u32, 11416, 11301}, |
| { ARM::BI__builtin_arm_mve_vgetq_lane_u64, 11431, 11301}, |
| { ARM::BI__builtin_arm_mve_vgetq_lane_u8, 11446, 11301}, |
| { ARM::BI__builtin_arm_mve_vhaddq_m_n_s16, 11469, 11460}, |
| { ARM::BI__builtin_arm_mve_vhaddq_m_n_s32, 11484, 11460}, |
| { ARM::BI__builtin_arm_mve_vhaddq_m_n_s8, 11499, 11460}, |
| { ARM::BI__builtin_arm_mve_vhaddq_m_n_u16, 11513, 11460}, |
| { ARM::BI__builtin_arm_mve_vhaddq_m_n_u32, 11528, 11460}, |
| { ARM::BI__builtin_arm_mve_vhaddq_m_n_u8, 11543, 11460}, |
| { ARM::BI__builtin_arm_mve_vhaddq_m_s16, 11557, 11460}, |
| { ARM::BI__builtin_arm_mve_vhaddq_m_s32, 11570, 11460}, |
| { ARM::BI__builtin_arm_mve_vhaddq_m_s8, 11583, 11460}, |
| { ARM::BI__builtin_arm_mve_vhaddq_m_u16, 11595, 11460}, |
| { ARM::BI__builtin_arm_mve_vhaddq_m_u32, 11608, 11460}, |
| { ARM::BI__builtin_arm_mve_vhaddq_m_u8, 11621, 11460}, |
| { ARM::BI__builtin_arm_mve_vhaddq_n_s16, 11640, 11633}, |
| { ARM::BI__builtin_arm_mve_vhaddq_n_s32, 11653, 11633}, |
| { ARM::BI__builtin_arm_mve_vhaddq_n_s8, 11666, 11633}, |
| { ARM::BI__builtin_arm_mve_vhaddq_n_u16, 11678, 11633}, |
| { ARM::BI__builtin_arm_mve_vhaddq_n_u32, 11691, 11633}, |
| { ARM::BI__builtin_arm_mve_vhaddq_n_u8, 11704, 11633}, |
| { ARM::BI__builtin_arm_mve_vhaddq_s16, 11716, 11633}, |
| { ARM::BI__builtin_arm_mve_vhaddq_s32, 11727, 11633}, |
| { ARM::BI__builtin_arm_mve_vhaddq_s8, 11738, 11633}, |
| { ARM::BI__builtin_arm_mve_vhaddq_u16, 11748, 11633}, |
| { ARM::BI__builtin_arm_mve_vhaddq_u32, 11759, 11633}, |
| { ARM::BI__builtin_arm_mve_vhaddq_u8, 11770, 11633}, |
| { ARM::BI__builtin_arm_mve_vhaddq_x_n_s16, 11789, 11780}, |
| { ARM::BI__builtin_arm_mve_vhaddq_x_n_s32, 11804, 11780}, |
| { ARM::BI__builtin_arm_mve_vhaddq_x_n_s8, 11819, 11780}, |
| { ARM::BI__builtin_arm_mve_vhaddq_x_n_u16, 11833, 11780}, |
| { ARM::BI__builtin_arm_mve_vhaddq_x_n_u32, 11848, 11780}, |
| { ARM::BI__builtin_arm_mve_vhaddq_x_n_u8, 11863, 11780}, |
| { ARM::BI__builtin_arm_mve_vhaddq_x_s16, 11877, 11780}, |
| { ARM::BI__builtin_arm_mve_vhaddq_x_s32, 11890, 11780}, |
| { ARM::BI__builtin_arm_mve_vhaddq_x_s8, 11903, 11780}, |
| { ARM::BI__builtin_arm_mve_vhaddq_x_u16, 11915, 11780}, |
| { ARM::BI__builtin_arm_mve_vhaddq_x_u32, 11928, 11780}, |
| { ARM::BI__builtin_arm_mve_vhaddq_x_u8, 11941, 11780}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot270_m_s16, 11970, 11953}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot270_m_s32, 11991, 11953}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot270_m_s8, 12012, 11953}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot270_s16, 12047, 12032}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot270_s32, 12066, 12032}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot270_s8, 12085, 12032}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot270_x_s16, 12120, 12103}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot270_x_s32, 12141, 12103}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot270_x_s8, 12162, 12103}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot90_m_s16, 12198, 12182}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot90_m_s32, 12218, 12182}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot90_m_s8, 12238, 12182}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot90_s16, 12271, 12257}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot90_s32, 12289, 12257}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot90_s8, 12307, 12257}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot90_x_s16, 12340, 12324}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot90_x_s32, 12360, 12324}, |
| { ARM::BI__builtin_arm_mve_vhcaddq_rot90_x_s8, 12380, 12324}, |
| { ARM::BI__builtin_arm_mve_vhsubq_m_n_s16, 12408, 12399}, |
| { ARM::BI__builtin_arm_mve_vhsubq_m_n_s32, 12423, 12399}, |
| { ARM::BI__builtin_arm_mve_vhsubq_m_n_s8, 12438, 12399}, |
| { ARM::BI__builtin_arm_mve_vhsubq_m_n_u16, 12452, 12399}, |
| { ARM::BI__builtin_arm_mve_vhsubq_m_n_u32, 12467, 12399}, |
| { ARM::BI__builtin_arm_mve_vhsubq_m_n_u8, 12482, 12399}, |
| { ARM::BI__builtin_arm_mve_vhsubq_m_s16, 12496, 12399}, |
| { ARM::BI__builtin_arm_mve_vhsubq_m_s32, 12509, 12399}, |
| { ARM::BI__builtin_arm_mve_vhsubq_m_s8, 12522, 12399}, |
| { ARM::BI__builtin_arm_mve_vhsubq_m_u16, 12534, 12399}, |
| { ARM::BI__builtin_arm_mve_vhsubq_m_u32, 12547, 12399}, |
| { ARM::BI__builtin_arm_mve_vhsubq_m_u8, 12560, 12399}, |
| { ARM::BI__builtin_arm_mve_vhsubq_n_s16, 12579, 12572}, |
| { ARM::BI__builtin_arm_mve_vhsubq_n_s32, 12592, 12572}, |
| { ARM::BI__builtin_arm_mve_vhsubq_n_s8, 12605, 12572}, |
| { ARM::BI__builtin_arm_mve_vhsubq_n_u16, 12617, 12572}, |
| { ARM::BI__builtin_arm_mve_vhsubq_n_u32, 12630, 12572}, |
| { ARM::BI__builtin_arm_mve_vhsubq_n_u8, 12643, 12572}, |
| { ARM::BI__builtin_arm_mve_vhsubq_s16, 12655, 12572}, |
| { ARM::BI__builtin_arm_mve_vhsubq_s32, 12666, 12572}, |
| { ARM::BI__builtin_arm_mve_vhsubq_s8, 12677, 12572}, |
| { ARM::BI__builtin_arm_mve_vhsubq_u16, 12687, 12572}, |
| { ARM::BI__builtin_arm_mve_vhsubq_u32, 12698, 12572}, |
| { ARM::BI__builtin_arm_mve_vhsubq_u8, 12709, 12572}, |
| { ARM::BI__builtin_arm_mve_vhsubq_x_n_s16, 12728, 12719}, |
| { ARM::BI__builtin_arm_mve_vhsubq_x_n_s32, 12743, 12719}, |
| { ARM::BI__builtin_arm_mve_vhsubq_x_n_s8, 12758, 12719}, |
| { ARM::BI__builtin_arm_mve_vhsubq_x_n_u16, 12772, 12719}, |
| { ARM::BI__builtin_arm_mve_vhsubq_x_n_u32, 12787, 12719}, |
| { ARM::BI__builtin_arm_mve_vhsubq_x_n_u8, 12802, 12719}, |
| { ARM::BI__builtin_arm_mve_vhsubq_x_s16, 12816, 12719}, |
| { ARM::BI__builtin_arm_mve_vhsubq_x_s32, 12829, 12719}, |
| { ARM::BI__builtin_arm_mve_vhsubq_x_s8, 12842, 12719}, |
| { ARM::BI__builtin_arm_mve_vhsubq_x_u16, 12854, 12719}, |
| { ARM::BI__builtin_arm_mve_vhsubq_x_u32, 12867, 12719}, |
| { ARM::BI__builtin_arm_mve_vhsubq_x_u8, 12880, 12719}, |
| { ARM::BI__builtin_arm_mve_vidupq_m_n_u16, 12901, 12892}, |
| { ARM::BI__builtin_arm_mve_vidupq_m_n_u32, 12916, 12892}, |
| { ARM::BI__builtin_arm_mve_vidupq_m_n_u8, 12931, 12892}, |
| { ARM::BI__builtin_arm_mve_vidupq_m_wb_u16, 12945, 12892}, |
| { ARM::BI__builtin_arm_mve_vidupq_m_wb_u32, 12961, 12892}, |
| { ARM::BI__builtin_arm_mve_vidupq_m_wb_u8, 12977, 12892}, |
| { ARM::BI__builtin_arm_mve_vidupq_n_u16, 13003, 12992}, |
| { ARM::BI__builtin_arm_mve_vidupq_n_u32, 13027, 13016}, |
| { ARM::BI__builtin_arm_mve_vidupq_n_u8, 13050, 13040}, |
| { ARM::BI__builtin_arm_mve_vidupq_wb_u16, 13062, 12992}, |
| { ARM::BI__builtin_arm_mve_vidupq_wb_u32, 13076, 13016}, |
| { ARM::BI__builtin_arm_mve_vidupq_wb_u8, 13090, 13040}, |
| { ARM::BI__builtin_arm_mve_vidupq_x_n_u16, 13116, 13103}, |
| { ARM::BI__builtin_arm_mve_vidupq_x_n_u32, 13144, 13131}, |
| { ARM::BI__builtin_arm_mve_vidupq_x_n_u8, 13171, 13159}, |
| { ARM::BI__builtin_arm_mve_vidupq_x_wb_u16, 13185, 13103}, |
| { ARM::BI__builtin_arm_mve_vidupq_x_wb_u32, 13201, 13131}, |
| { ARM::BI__builtin_arm_mve_vidupq_x_wb_u8, 13217, 13159}, |
| { ARM::BI__builtin_arm_mve_viwdupq_m_n_u16, 13242, 13232}, |
| { ARM::BI__builtin_arm_mve_viwdupq_m_n_u32, 13258, 13232}, |
| { ARM::BI__builtin_arm_mve_viwdupq_m_n_u8, 13274, 13232}, |
| { ARM::BI__builtin_arm_mve_viwdupq_m_wb_u16, 13289, 13232}, |
| { ARM::BI__builtin_arm_mve_viwdupq_m_wb_u32, 13306, 13232}, |
| { ARM::BI__builtin_arm_mve_viwdupq_m_wb_u8, 13323, 13232}, |
| { ARM::BI__builtin_arm_mve_viwdupq_n_u16, 13351, 13339}, |
| { ARM::BI__builtin_arm_mve_viwdupq_n_u32, 13377, 13365}, |
| { ARM::BI__builtin_arm_mve_viwdupq_n_u8, 13402, 13391}, |
| { ARM::BI__builtin_arm_mve_viwdupq_wb_u16, 13415, 13339}, |
| { ARM::BI__builtin_arm_mve_viwdupq_wb_u32, 13430, 13365}, |
| { ARM::BI__builtin_arm_mve_viwdupq_wb_u8, 13445, 13391}, |
| { ARM::BI__builtin_arm_mve_viwdupq_x_n_u16, 13473, 13459}, |
| { ARM::BI__builtin_arm_mve_viwdupq_x_n_u32, 13503, 13489}, |
| { ARM::BI__builtin_arm_mve_viwdupq_x_n_u8, 13532, 13519}, |
| { ARM::BI__builtin_arm_mve_viwdupq_x_wb_u16, 13547, 13459}, |
| { ARM::BI__builtin_arm_mve_viwdupq_x_wb_u32, 13564, 13489}, |
| { ARM::BI__builtin_arm_mve_viwdupq_x_wb_u8, 13581, 13519}, |
| { ARM::BI__builtin_arm_mve_vld1q_f16, 13603, 13597}, |
| { ARM::BI__builtin_arm_mve_vld1q_f32, 13613, 13597}, |
| { ARM::BI__builtin_arm_mve_vld1q_s16, 13623, 13597}, |
| { ARM::BI__builtin_arm_mve_vld1q_s32, 13633, 13597}, |
| { ARM::BI__builtin_arm_mve_vld1q_s8, 13643, 13597}, |
| { ARM::BI__builtin_arm_mve_vld1q_u16, 13652, 13597}, |
| { ARM::BI__builtin_arm_mve_vld1q_u32, 13662, 13597}, |
| { ARM::BI__builtin_arm_mve_vld1q_u8, 13672, 13597}, |
| { ARM::BI__builtin_arm_mve_vld1q_z_f16, 13689, 13681}, |
| { ARM::BI__builtin_arm_mve_vld1q_z_f32, 13701, 13681}, |
| { ARM::BI__builtin_arm_mve_vld1q_z_s16, 13713, 13681}, |
| { ARM::BI__builtin_arm_mve_vld1q_z_s32, 13725, 13681}, |
| { ARM::BI__builtin_arm_mve_vld1q_z_s8, 13737, 13681}, |
| { ARM::BI__builtin_arm_mve_vld1q_z_u16, 13748, 13681}, |
| { ARM::BI__builtin_arm_mve_vld1q_z_u32, 13760, 13681}, |
| { ARM::BI__builtin_arm_mve_vld1q_z_u8, 13772, 13681}, |
| { ARM::BI__builtin_arm_mve_vld2q_f16, 13789, 13783}, |
| { ARM::BI__builtin_arm_mve_vld2q_f32, 13799, 13783}, |
| { ARM::BI__builtin_arm_mve_vld2q_s16, 13809, 13783}, |
| { ARM::BI__builtin_arm_mve_vld2q_s32, 13819, 13783}, |
| { ARM::BI__builtin_arm_mve_vld2q_s8, 13829, 13783}, |
| { ARM::BI__builtin_arm_mve_vld2q_u16, 13838, 13783}, |
| { ARM::BI__builtin_arm_mve_vld2q_u32, 13848, 13783}, |
| { ARM::BI__builtin_arm_mve_vld2q_u8, 13858, 13783}, |
| { ARM::BI__builtin_arm_mve_vld4q_f16, 13873, 13867}, |
| { ARM::BI__builtin_arm_mve_vld4q_f32, 13883, 13867}, |
| { ARM::BI__builtin_arm_mve_vld4q_s16, 13893, 13867}, |
| { ARM::BI__builtin_arm_mve_vld4q_s32, 13903, 13867}, |
| { ARM::BI__builtin_arm_mve_vld4q_s8, 13913, 13867}, |
| { ARM::BI__builtin_arm_mve_vld4q_u16, 13922, 13867}, |
| { ARM::BI__builtin_arm_mve_vld4q_u32, 13932, 13867}, |
| { ARM::BI__builtin_arm_mve_vld4q_u8, 13942, 13867}, |
| { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_s16, 13972, 13951}, |
| { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_s32, 13997, 13951}, |
| { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_s8, 14022, 13951}, |
| { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_u16, 14046, 13951}, |
| { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_u32, 14071, 13951}, |
| { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_u8, 14096, 13951}, |
| { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_z_s16, 14143, 14120}, |
| { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_z_s32, 14170, 14120}, |
| { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_z_s8, 14197, 14120}, |
| { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_z_u16, 14223, 14120}, |
| { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_z_u32, 14250, 14120}, |
| { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_z_u8, 14277, 14120}, |
| { ARM::BI__builtin_arm_mve_vldrbq_s16, 14303, -1}, |
| { ARM::BI__builtin_arm_mve_vldrbq_s32, 14314, -1}, |
| { ARM::BI__builtin_arm_mve_vldrbq_s8, 14325, -1}, |
| { ARM::BI__builtin_arm_mve_vldrbq_u16, 14335, -1}, |
| { ARM::BI__builtin_arm_mve_vldrbq_u32, 14346, -1}, |
| { ARM::BI__builtin_arm_mve_vldrbq_u8, 14357, -1}, |
| { ARM::BI__builtin_arm_mve_vldrbq_z_s16, 14367, -1}, |
| { ARM::BI__builtin_arm_mve_vldrbq_z_s32, 14380, -1}, |
| { ARM::BI__builtin_arm_mve_vldrbq_z_s8, 14393, -1}, |
| { ARM::BI__builtin_arm_mve_vldrbq_z_u16, 14405, -1}, |
| { ARM::BI__builtin_arm_mve_vldrbq_z_u32, 14418, -1}, |
| { ARM::BI__builtin_arm_mve_vldrbq_z_u8, 14431, -1}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_base_s64, 14443, -1}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_base_u64, 14466, -1}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_s64, 14489, -1}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_u64, 14515, -1}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_z_s64, 14541, -1}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_z_u64, 14569, -1}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_base_z_s64, 14597, -1}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_base_z_u64, 14622, -1}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_offset_s64, 14668, 14647}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_offset_u64, 14693, 14647}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_offset_z_s64, 14741, 14718}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_offset_z_u64, 14768, 14718}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_shifted_offset_s64, 14824, 14795}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_shifted_offset_u64, 14857, 14795}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_shifted_offset_z_s64, 14921, 14890}, |
| { ARM::BI__builtin_arm_mve_vldrdq_gather_shifted_offset_z_u64, 14956, 14890}, |
| { ARM::BI__builtin_arm_mve_vldrhq_f16, 14991, -1}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_f16, 15023, 15002}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_s16, 15048, 15002}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_s32, 15073, 15002}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_u16, 15098, 15002}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_u32, 15123, 15002}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_z_f16, 15171, 15148}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_z_s16, 15198, 15148}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_z_s32, 15225, 15148}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_z_u16, 15252, 15148}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_z_u32, 15279, 15148}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_f16, 15335, 15306}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_s16, 15368, 15306}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_s32, 15401, 15306}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_u16, 15434, 15306}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_u32, 15467, 15306}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_z_f16, 15531, 15500}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_z_s16, 15566, 15500}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_z_s32, 15601, 15500}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_z_u16, 15636, 15500}, |
| { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_z_u32, 15671, 15500}, |
| { ARM::BI__builtin_arm_mve_vldrhq_s16, 15706, -1}, |
| { ARM::BI__builtin_arm_mve_vldrhq_s32, 15717, -1}, |
| { ARM::BI__builtin_arm_mve_vldrhq_u16, 15728, -1}, |
| { ARM::BI__builtin_arm_mve_vldrhq_u32, 15739, -1}, |
| { ARM::BI__builtin_arm_mve_vldrhq_z_f16, 15750, -1}, |
| { ARM::BI__builtin_arm_mve_vldrhq_z_s16, 15763, -1}, |
| { ARM::BI__builtin_arm_mve_vldrhq_z_s32, 15776, -1}, |
| { ARM::BI__builtin_arm_mve_vldrhq_z_u16, 15789, -1}, |
| { ARM::BI__builtin_arm_mve_vldrhq_z_u32, 15802, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_f32, 15815, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_base_f32, 15826, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_base_s32, 15849, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_base_u32, 15872, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_f32, 15895, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_s32, 15921, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_u32, 15947, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_z_f32, 15973, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_z_s32, 16001, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_z_u32, 16029, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_base_z_f32, 16057, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_base_z_s32, 16082, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_base_z_u32, 16107, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_offset_f32, 16153, 16132}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_offset_s32, 16178, 16132}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_offset_u32, 16203, 16132}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_offset_z_f32, 16251, 16228}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_offset_z_s32, 16278, 16228}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_offset_z_u32, 16305, 16228}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_shifted_offset_f32, 16361, 16332}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_shifted_offset_s32, 16394, 16332}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_shifted_offset_u32, 16427, 16332}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_shifted_offset_z_f32, 16491, 16460}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_shifted_offset_z_s32, 16526, 16460}, |
| { ARM::BI__builtin_arm_mve_vldrwq_gather_shifted_offset_z_u32, 16561, 16460}, |
| { ARM::BI__builtin_arm_mve_vldrwq_s32, 16596, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_u32, 16607, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_z_f32, 16618, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_z_s32, 16631, -1}, |
| { ARM::BI__builtin_arm_mve_vldrwq_z_u32, 16644, -1}, |
| { ARM::BI__builtin_arm_mve_vmaxaq_m_s16, 16666, 16657}, |
| { ARM::BI__builtin_arm_mve_vmaxaq_m_s32, 16679, 16657}, |
| { ARM::BI__builtin_arm_mve_vmaxaq_m_s8, 16692, 16657}, |
| { ARM::BI__builtin_arm_mve_vmaxaq_s16, 16711, 16704}, |
| { ARM::BI__builtin_arm_mve_vmaxaq_s32, 16722, 16704}, |
| { ARM::BI__builtin_arm_mve_vmaxaq_s8, 16733, 16704}, |
| { ARM::BI__builtin_arm_mve_vmaxavq_p_s16, 16753, 16743}, |
| { ARM::BI__builtin_arm_mve_vmaxavq_p_s32, 16767, 16743}, |
| { ARM::BI__builtin_arm_mve_vmaxavq_p_s8, 16781, 16743}, |
| { ARM::BI__builtin_arm_mve_vmaxavq_s16, 16802, 16794}, |
| { ARM::BI__builtin_arm_mve_vmaxavq_s32, 16814, 16794}, |
| { ARM::BI__builtin_arm_mve_vmaxavq_s8, 16826, 16794}, |
| { ARM::BI__builtin_arm_mve_vmaxnmaq_f16, 16846, 16837}, |
| { ARM::BI__builtin_arm_mve_vmaxnmaq_f32, 16859, 16837}, |
| { ARM::BI__builtin_arm_mve_vmaxnmaq_m_f16, 16883, 16872}, |
| { ARM::BI__builtin_arm_mve_vmaxnmaq_m_f32, 16898, 16872}, |
| { ARM::BI__builtin_arm_mve_vmaxnmavq_f16, 16923, 16913}, |
| { ARM::BI__builtin_arm_mve_vmaxnmavq_f32, 16937, 16913}, |
| { ARM::BI__builtin_arm_mve_vmaxnmavq_p_f16, 16963, 16951}, |
| { ARM::BI__builtin_arm_mve_vmaxnmavq_p_f32, 16979, 16951}, |
| { ARM::BI__builtin_arm_mve_vmaxnmq_f16, 17003, 16995}, |
| { ARM::BI__builtin_arm_mve_vmaxnmq_f32, 17015, 16995}, |
| { ARM::BI__builtin_arm_mve_vmaxnmq_m_f16, 17037, 17027}, |
| { ARM::BI__builtin_arm_mve_vmaxnmq_m_f32, 17051, 17027}, |
| { ARM::BI__builtin_arm_mve_vmaxnmq_x_f16, 17075, 17065}, |
| { ARM::BI__builtin_arm_mve_vmaxnmq_x_f32, 17089, 17065}, |
| { ARM::BI__builtin_arm_mve_vmaxnmvq_f16, 17112, 17103}, |
| { ARM::BI__builtin_arm_mve_vmaxnmvq_f32, 17125, 17103}, |
| { ARM::BI__builtin_arm_mve_vmaxnmvq_p_f16, 17149, 17138}, |
| { ARM::BI__builtin_arm_mve_vmaxnmvq_p_f32, 17164, 17138}, |
| { ARM::BI__builtin_arm_mve_vmaxq_m_s16, 17187, 17179}, |
| { ARM::BI__builtin_arm_mve_vmaxq_m_s32, 17199, 17179}, |
| { ARM::BI__builtin_arm_mve_vmaxq_m_s8, 17211, 17179}, |
| { ARM::BI__builtin_arm_mve_vmaxq_m_u16, 17222, 17179}, |
| { ARM::BI__builtin_arm_mve_vmaxq_m_u32, 17234, 17179}, |
| { ARM::BI__builtin_arm_mve_vmaxq_m_u8, 17246, 17179}, |
| { ARM::BI__builtin_arm_mve_vmaxq_s16, 17263, 17257}, |
| { ARM::BI__builtin_arm_mve_vmaxq_s32, 17273, 17257}, |
| { ARM::BI__builtin_arm_mve_vmaxq_s8, 17283, 17257}, |
| { ARM::BI__builtin_arm_mve_vmaxq_u16, 17292, 17257}, |
| { ARM::BI__builtin_arm_mve_vmaxq_u32, 17302, 17257}, |
| { ARM::BI__builtin_arm_mve_vmaxq_u8, 17312, 17257}, |
| { ARM::BI__builtin_arm_mve_vmaxq_x_s16, 17329, 17321}, |
| { ARM::BI__builtin_arm_mve_vmaxq_x_s32, 17341, 17321}, |
| { ARM::BI__builtin_arm_mve_vmaxq_x_s8, 17353, 17321}, |
| { ARM::BI__builtin_arm_mve_vmaxq_x_u16, 17364, 17321}, |
| { ARM::BI__builtin_arm_mve_vmaxq_x_u32, 17376, 17321}, |
| { ARM::BI__builtin_arm_mve_vmaxq_x_u8, 17388, 17321}, |
| { ARM::BI__builtin_arm_mve_vmaxvq_p_s16, 17408, 17399}, |
| { ARM::BI__builtin_arm_mve_vmaxvq_p_s32, 17421, 17399}, |
| { ARM::BI__builtin_arm_mve_vmaxvq_p_s8, 17434, 17399}, |
| { ARM::BI__builtin_arm_mve_vmaxvq_p_u16, 17446, 17399}, |
| { ARM::BI__builtin_arm_mve_vmaxvq_p_u32, 17459, 17399}, |
| { ARM::BI__builtin_arm_mve_vmaxvq_p_u8, 17472, 17399}, |
| { ARM::BI__builtin_arm_mve_vmaxvq_s16, 17491, 17484}, |
| { ARM::BI__builtin_arm_mve_vmaxvq_s32, 17502, 17484}, |
| { ARM::BI__builtin_arm_mve_vmaxvq_s8, 17513, 17484}, |
| { ARM::BI__builtin_arm_mve_vmaxvq_u16, 17523, 17484}, |
| { ARM::BI__builtin_arm_mve_vmaxvq_u32, 17534, 17484}, |
| { ARM::BI__builtin_arm_mve_vmaxvq_u8, 17545, 17484}, |
| { ARM::BI__builtin_arm_mve_vminaq_m_s16, 17564, 17555}, |
| { ARM::BI__builtin_arm_mve_vminaq_m_s32, 17577, 17555}, |
| { ARM::BI__builtin_arm_mve_vminaq_m_s8, 17590, 17555}, |
| { ARM::BI__builtin_arm_mve_vminaq_s16, 17609, 17602}, |
| { ARM::BI__builtin_arm_mve_vminaq_s32, 17620, 17602}, |
| { ARM::BI__builtin_arm_mve_vminaq_s8, 17631, 17602}, |
| { ARM::BI__builtin_arm_mve_vminavq_p_s16, 17651, 17641}, |
| { ARM::BI__builtin_arm_mve_vminavq_p_s32, 17665, 17641}, |
| { ARM::BI__builtin_arm_mve_vminavq_p_s8, 17679, 17641}, |
| { ARM::BI__builtin_arm_mve_vminavq_s16, 17700, 17692}, |
| { ARM::BI__builtin_arm_mve_vminavq_s32, 17712, 17692}, |
| { ARM::BI__builtin_arm_mve_vminavq_s8, 17724, 17692}, |
| { ARM::BI__builtin_arm_mve_vminnmaq_f16, 17744, 17735}, |
| { ARM::BI__builtin_arm_mve_vminnmaq_f32, 17757, 17735}, |
| { ARM::BI__builtin_arm_mve_vminnmaq_m_f16, 17781, 17770}, |
| { ARM::BI__builtin_arm_mve_vminnmaq_m_f32, 17796, 17770}, |
| { ARM::BI__builtin_arm_mve_vminnmavq_f16, 17821, 17811}, |
| { ARM::BI__builtin_arm_mve_vminnmavq_f32, 17835, 17811}, |
| { ARM::BI__builtin_arm_mve_vminnmavq_p_f16, 17861, 17849}, |
| { ARM::BI__builtin_arm_mve_vminnmavq_p_f32, 17877, 17849}, |
| { ARM::BI__builtin_arm_mve_vminnmq_f16, 17901, 17893}, |
| { ARM::BI__builtin_arm_mve_vminnmq_f32, 17913, 17893}, |
| { ARM::BI__builtin_arm_mve_vminnmq_m_f16, 17935, 17925}, |
| { ARM::BI__builtin_arm_mve_vminnmq_m_f32, 17949, 17925}, |
| { ARM::BI__builtin_arm_mve_vminnmq_x_f16, 17973, 17963}, |
| { ARM::BI__builtin_arm_mve_vminnmq_x_f32, 17987, 17963}, |
| { ARM::BI__builtin_arm_mve_vminnmvq_f16, 18010, 18001}, |
| { ARM::BI__builtin_arm_mve_vminnmvq_f32, 18023, 18001}, |
| { ARM::BI__builtin_arm_mve_vminnmvq_p_f16, 18047, 18036}, |
| { ARM::BI__builtin_arm_mve_vminnmvq_p_f32, 18062, 18036}, |
| { ARM::BI__builtin_arm_mve_vminq_m_s16, 18085, 18077}, |
| { ARM::BI__builtin_arm_mve_vminq_m_s32, 18097, 18077}, |
| { ARM::BI__builtin_arm_mve_vminq_m_s8, 18109, 18077}, |
| { ARM::BI__builtin_arm_mve_vminq_m_u16, 18120, 18077}, |
| { ARM::BI__builtin_arm_mve_vminq_m_u32, 18132, 18077}, |
| { ARM::BI__builtin_arm_mve_vminq_m_u8, 18144, 18077}, |
| { ARM::BI__builtin_arm_mve_vminq_s16, 18161, 18155}, |
| { ARM::BI__builtin_arm_mve_vminq_s32, 18171, 18155}, |
| { ARM::BI__builtin_arm_mve_vminq_s8, 18181, 18155}, |
| { ARM::BI__builtin_arm_mve_vminq_u16, 18190, 18155}, |
| { ARM::BI__builtin_arm_mve_vminq_u32, 18200, 18155}, |
| { ARM::BI__builtin_arm_mve_vminq_u8, 18210, 18155}, |
| { ARM::BI__builtin_arm_mve_vminq_x_s16, 18227, 18219}, |
| { ARM::BI__builtin_arm_mve_vminq_x_s32, 18239, 18219}, |
| { ARM::BI__builtin_arm_mve_vminq_x_s8, 18251, 18219}, |
| { ARM::BI__builtin_arm_mve_vminq_x_u16, 18262, 18219}, |
| { ARM::BI__builtin_arm_mve_vminq_x_u32, 18274, 18219}, |
| { ARM::BI__builtin_arm_mve_vminq_x_u8, 18286, 18219}, |
| { ARM::BI__builtin_arm_mve_vminvq_p_s16, 18306, 18297}, |
| { ARM::BI__builtin_arm_mve_vminvq_p_s32, 18319, 18297}, |
| { ARM::BI__builtin_arm_mve_vminvq_p_s8, 18332, 18297}, |
| { ARM::BI__builtin_arm_mve_vminvq_p_u16, 18344, 18297}, |
| { ARM::BI__builtin_arm_mve_vminvq_p_u32, 18357, 18297}, |
| { ARM::BI__builtin_arm_mve_vminvq_p_u8, 18370, 18297}, |
| { ARM::BI__builtin_arm_mve_vminvq_s16, 18389, 18382}, |
| { ARM::BI__builtin_arm_mve_vminvq_s32, 18400, 18382}, |
| { ARM::BI__builtin_arm_mve_vminvq_s8, 18411, 18382}, |
| { ARM::BI__builtin_arm_mve_vminvq_u16, 18421, 18382}, |
| { ARM::BI__builtin_arm_mve_vminvq_u32, 18432, 18382}, |
| { ARM::BI__builtin_arm_mve_vminvq_u8, 18443, 18382}, |
| { ARM::BI__builtin_arm_mve_vmladavaq_p_s16, 18465, 18453}, |
| { ARM::BI__builtin_arm_mve_vmladavaq_p_s32, 18481, 18453}, |
| { ARM::BI__builtin_arm_mve_vmladavaq_p_s8, 18497, 18453}, |
| { ARM::BI__builtin_arm_mve_vmladavaq_p_u16, 18512, 18453}, |
| { ARM::BI__builtin_arm_mve_vmladavaq_p_u32, 18528, 18453}, |
| { ARM::BI__builtin_arm_mve_vmladavaq_p_u8, 18544, 18453}, |
| { ARM::BI__builtin_arm_mve_vmladavaq_s16, 18569, 18559}, |
| { ARM::BI__builtin_arm_mve_vmladavaq_s32, 18583, 18559}, |
| { ARM::BI__builtin_arm_mve_vmladavaq_s8, 18597, 18559}, |
| { ARM::BI__builtin_arm_mve_vmladavaq_u16, 18610, 18559}, |
| { ARM::BI__builtin_arm_mve_vmladavaq_u32, 18624, 18559}, |
| { ARM::BI__builtin_arm_mve_vmladavaq_u8, 18638, 18559}, |
| { ARM::BI__builtin_arm_mve_vmladavaxq_p_s16, 18664, 18651}, |
| { ARM::BI__builtin_arm_mve_vmladavaxq_p_s32, 18681, 18651}, |
| { ARM::BI__builtin_arm_mve_vmladavaxq_p_s8, 18698, 18651}, |
| { ARM::BI__builtin_arm_mve_vmladavaxq_s16, 18725, 18714}, |
| { ARM::BI__builtin_arm_mve_vmladavaxq_s32, 18740, 18714}, |
| { ARM::BI__builtin_arm_mve_vmladavaxq_s8, 18755, 18714}, |
| { ARM::BI__builtin_arm_mve_vmladavq_p_s16, 18780, 18769}, |
| { ARM::BI__builtin_arm_mve_vmladavq_p_s32, 18795, 18769}, |
| { ARM::BI__builtin_arm_mve_vmladavq_p_s8, 18810, 18769}, |
| { ARM::BI__builtin_arm_mve_vmladavq_p_u16, 18824, 18769}, |
| { ARM::BI__builtin_arm_mve_vmladavq_p_u32, 18839, 18769}, |
| { ARM::BI__builtin_arm_mve_vmladavq_p_u8, 18854, 18769}, |
| { ARM::BI__builtin_arm_mve_vmladavq_s16, 18877, 18868}, |
| { ARM::BI__builtin_arm_mve_vmladavq_s32, 18890, 18868}, |
| { ARM::BI__builtin_arm_mve_vmladavq_s8, 18903, 18868}, |
| { ARM::BI__builtin_arm_mve_vmladavq_u16, 18915, 18868}, |
| { ARM::BI__builtin_arm_mve_vmladavq_u32, 18928, 18868}, |
| { ARM::BI__builtin_arm_mve_vmladavq_u8, 18941, 18868}, |
| { ARM::BI__builtin_arm_mve_vmladavxq_p_s16, 18965, 18953}, |
| { ARM::BI__builtin_arm_mve_vmladavxq_p_s32, 18981, 18953}, |
| { ARM::BI__builtin_arm_mve_vmladavxq_p_s8, 18997, 18953}, |
| { ARM::BI__builtin_arm_mve_vmladavxq_s16, 19022, 19012}, |
| { ARM::BI__builtin_arm_mve_vmladavxq_s32, 19036, 19012}, |
| { ARM::BI__builtin_arm_mve_vmladavxq_s8, 19050, 19012}, |
| { ARM::BI__builtin_arm_mve_vmlaldavaq_p_s16, 19076, 19063}, |
| { ARM::BI__builtin_arm_mve_vmlaldavaq_p_s32, 19093, 19063}, |
| { ARM::BI__builtin_arm_mve_vmlaldavaq_p_u16, 19110, 19063}, |
| { ARM::BI__builtin_arm_mve_vmlaldavaq_p_u32, 19127, 19063}, |
| { ARM::BI__builtin_arm_mve_vmlaldavaq_s16, 19155, 19144}, |
| { ARM::BI__builtin_arm_mve_vmlaldavaq_s32, 19170, 19144}, |
| { ARM::BI__builtin_arm_mve_vmlaldavaq_u16, 19185, 19144}, |
| { ARM::BI__builtin_arm_mve_vmlaldavaq_u32, 19200, 19144}, |
| { ARM::BI__builtin_arm_mve_vmlaldavaxq_p_s16, 19229, 19215}, |
| { ARM::BI__builtin_arm_mve_vmlaldavaxq_p_s32, 19247, 19215}, |
| { ARM::BI__builtin_arm_mve_vmlaldavaxq_s16, 19277, 19265}, |
| { ARM::BI__builtin_arm_mve_vmlaldavaxq_s32, 19293, 19265}, |
| { ARM::BI__builtin_arm_mve_vmlaldavq_p_s16, 19321, 19309}, |
| { ARM::BI__builtin_arm_mve_vmlaldavq_p_s32, 19337, 19309}, |
| { ARM::BI__builtin_arm_mve_vmlaldavq_p_u16, 19353, 19309}, |
| { ARM::BI__builtin_arm_mve_vmlaldavq_p_u32, 19369, 19309}, |
| { ARM::BI__builtin_arm_mve_vmlaldavq_s16, 19395, 19385}, |
| { ARM::BI__builtin_arm_mve_vmlaldavq_s32, 19409, 19385}, |
| { ARM::BI__builtin_arm_mve_vmlaldavq_u16, 19423, 19385}, |
| { ARM::BI__builtin_arm_mve_vmlaldavq_u32, 19437, 19385}, |
| { ARM::BI__builtin_arm_mve_vmlaldavxq_p_s16, 19464, 19451}, |
| { ARM::BI__builtin_arm_mve_vmlaldavxq_p_s32, 19481, 19451}, |
| { ARM::BI__builtin_arm_mve_vmlaldavxq_s16, 19509, 19498}, |
| { ARM::BI__builtin_arm_mve_vmlaldavxq_s32, 19524, 19498}, |
| { ARM::BI__builtin_arm_mve_vmlaq_m_n_s16, 19547, 19539}, |
| { ARM::BI__builtin_arm_mve_vmlaq_m_n_s32, 19561, 19539}, |
| { ARM::BI__builtin_arm_mve_vmlaq_m_n_s8, 19575, 19539}, |
| { ARM::BI__builtin_arm_mve_vmlaq_m_n_u16, 19588, 19539}, |
| { ARM::BI__builtin_arm_mve_vmlaq_m_n_u32, 19602, 19539}, |
| { ARM::BI__builtin_arm_mve_vmlaq_m_n_u8, 19616, 19539}, |
| { ARM::BI__builtin_arm_mve_vmlaq_n_s16, 19635, 19629}, |
| { ARM::BI__builtin_arm_mve_vmlaq_n_s32, 19647, 19629}, |
| { ARM::BI__builtin_arm_mve_vmlaq_n_s8, 19659, 19629}, |
| { ARM::BI__builtin_arm_mve_vmlaq_n_u16, 19670, 19629}, |
| { ARM::BI__builtin_arm_mve_vmlaq_n_u32, 19682, 19629}, |
| { ARM::BI__builtin_arm_mve_vmlaq_n_u8, 19694, 19629}, |
| { ARM::BI__builtin_arm_mve_vmlasq_m_n_s16, 19714, 19705}, |
| { ARM::BI__builtin_arm_mve_vmlasq_m_n_s32, 19729, 19705}, |
| { ARM::BI__builtin_arm_mve_vmlasq_m_n_s8, 19744, 19705}, |
| { ARM::BI__builtin_arm_mve_vmlasq_m_n_u16, 19758, 19705}, |
| { ARM::BI__builtin_arm_mve_vmlasq_m_n_u32, 19773, 19705}, |
| { ARM::BI__builtin_arm_mve_vmlasq_m_n_u8, 19788, 19705}, |
| { ARM::BI__builtin_arm_mve_vmlasq_n_s16, 19809, 19802}, |
| { ARM::BI__builtin_arm_mve_vmlasq_n_s32, 19822, 19802}, |
| { ARM::BI__builtin_arm_mve_vmlasq_n_s8, 19835, 19802}, |
| { ARM::BI__builtin_arm_mve_vmlasq_n_u16, 19847, 19802}, |
| { ARM::BI__builtin_arm_mve_vmlasq_n_u32, 19860, 19802}, |
| { ARM::BI__builtin_arm_mve_vmlasq_n_u8, 19873, 19802}, |
| { ARM::BI__builtin_arm_mve_vmlsdavaq_p_s16, 19897, 19885}, |
| { ARM::BI__builtin_arm_mve_vmlsdavaq_p_s32, 19913, 19885}, |
| { ARM::BI__builtin_arm_mve_vmlsdavaq_p_s8, 19929, 19885}, |
| { ARM::BI__builtin_arm_mve_vmlsdavaq_s16, 19954, 19944}, |
| { ARM::BI__builtin_arm_mve_vmlsdavaq_s32, 19968, 19944}, |
| { ARM::BI__builtin_arm_mve_vmlsdavaq_s8, 19982, 19944}, |
| { ARM::BI__builtin_arm_mve_vmlsdavaxq_p_s16, 20008, 19995}, |
| { ARM::BI__builtin_arm_mve_vmlsdavaxq_p_s32, 20025, 19995}, |
| { ARM::BI__builtin_arm_mve_vmlsdavaxq_p_s8, 20042, 19995}, |
| { ARM::BI__builtin_arm_mve_vmlsdavaxq_s16, 20069, 20058}, |
| { ARM::BI__builtin_arm_mve_vmlsdavaxq_s32, 20084, 20058}, |
| { ARM::BI__builtin_arm_mve_vmlsdavaxq_s8, 20099, 20058}, |
| { ARM::BI__builtin_arm_mve_vmlsdavq_p_s16, 20124, 20113}, |
| { ARM::BI__builtin_arm_mve_vmlsdavq_p_s32, 20139, 20113}, |
| { ARM::BI__builtin_arm_mve_vmlsdavq_p_s8, 20154, 20113}, |
| { ARM::BI__builtin_arm_mve_vmlsdavq_s16, 20177, 20168}, |
| { ARM::BI__builtin_arm_mve_vmlsdavq_s32, 20190, 20168}, |
| { ARM::BI__builtin_arm_mve_vmlsdavq_s8, 20203, 20168}, |
| { ARM::BI__builtin_arm_mve_vmlsdavxq_p_s16, 20227, 20215}, |
| { ARM::BI__builtin_arm_mve_vmlsdavxq_p_s32, 20243, 20215}, |
| { ARM::BI__builtin_arm_mve_vmlsdavxq_p_s8, 20259, 20215}, |
| { ARM::BI__builtin_arm_mve_vmlsdavxq_s16, 20284, 20274}, |
| { ARM::BI__builtin_arm_mve_vmlsdavxq_s32, 20298, 20274}, |
| { ARM::BI__builtin_arm_mve_vmlsdavxq_s8, 20312, 20274}, |
| { ARM::BI__builtin_arm_mve_vmlsldavaq_p_s16, 20338, 20325}, |
| { ARM::BI__builtin_arm_mve_vmlsldavaq_p_s32, 20355, 20325}, |
| { ARM::BI__builtin_arm_mve_vmlsldavaq_s16, 20383, 20372}, |
| { ARM::BI__builtin_arm_mve_vmlsldavaq_s32, 20398, 20372}, |
| { ARM::BI__builtin_arm_mve_vmlsldavaxq_p_s16, 20427, 20413}, |
| { ARM::BI__builtin_arm_mve_vmlsldavaxq_p_s32, 20445, 20413}, |
| { ARM::BI__builtin_arm_mve_vmlsldavaxq_s16, 20475, 20463}, |
| { ARM::BI__builtin_arm_mve_vmlsldavaxq_s32, 20491, 20463}, |
| { ARM::BI__builtin_arm_mve_vmlsldavq_p_s16, 20519, 20507}, |
| { ARM::BI__builtin_arm_mve_vmlsldavq_p_s32, 20535, 20507}, |
| { ARM::BI__builtin_arm_mve_vmlsldavq_s16, 20561, 20551}, |
| { ARM::BI__builtin_arm_mve_vmlsldavq_s32, 20575, 20551}, |
| { ARM::BI__builtin_arm_mve_vmlsldavxq_p_s16, 20602, 20589}, |
| { ARM::BI__builtin_arm_mve_vmlsldavxq_p_s32, 20619, 20589}, |
| { ARM::BI__builtin_arm_mve_vmlsldavxq_s16, 20647, 20636}, |
| { ARM::BI__builtin_arm_mve_vmlsldavxq_s32, 20662, 20636}, |
| { ARM::BI__builtin_arm_mve_vmovlbq_m_s16, 20687, 20677}, |
| { ARM::BI__builtin_arm_mve_vmovlbq_m_s8, 20701, 20677}, |
| { ARM::BI__builtin_arm_mve_vmovlbq_m_u16, 20714, 20677}, |
| { ARM::BI__builtin_arm_mve_vmovlbq_m_u8, 20728, 20677}, |
| { ARM::BI__builtin_arm_mve_vmovlbq_s16, 20749, 20741}, |
| { ARM::BI__builtin_arm_mve_vmovlbq_s8, 20761, 20741}, |
| { ARM::BI__builtin_arm_mve_vmovlbq_u16, 20772, 20741}, |
| { ARM::BI__builtin_arm_mve_vmovlbq_u8, 20784, 20741}, |
| { ARM::BI__builtin_arm_mve_vmovlbq_x_s16, 20805, 20795}, |
| { ARM::BI__builtin_arm_mve_vmovlbq_x_s8, 20819, 20795}, |
| { ARM::BI__builtin_arm_mve_vmovlbq_x_u16, 20832, 20795}, |
| { ARM::BI__builtin_arm_mve_vmovlbq_x_u8, 20846, 20795}, |
| { ARM::BI__builtin_arm_mve_vmovltq_m_s16, 20869, 20859}, |
| { ARM::BI__builtin_arm_mve_vmovltq_m_s8, 20883, 20859}, |
| { ARM::BI__builtin_arm_mve_vmovltq_m_u16, 20896, 20859}, |
| { ARM::BI__builtin_arm_mve_vmovltq_m_u8, 20910, 20859}, |
| { ARM::BI__builtin_arm_mve_vmovltq_s16, 20931, 20923}, |
| { ARM::BI__builtin_arm_mve_vmovltq_s8, 20943, 20923}, |
| { ARM::BI__builtin_arm_mve_vmovltq_u16, 20954, 20923}, |
| { ARM::BI__builtin_arm_mve_vmovltq_u8, 20966, 20923}, |
| { ARM::BI__builtin_arm_mve_vmovltq_x_s16, 20987, 20977}, |
| { ARM::BI__builtin_arm_mve_vmovltq_x_s8, 21001, 20977}, |
| { ARM::BI__builtin_arm_mve_vmovltq_x_u16, 21014, 20977}, |
| { ARM::BI__builtin_arm_mve_vmovltq_x_u8, 21028, 20977}, |
| { ARM::BI__builtin_arm_mve_vmovnbq_m_s16, 21051, 21041}, |
| { ARM::BI__builtin_arm_mve_vmovnbq_m_s32, 21065, 21041}, |
| { ARM::BI__builtin_arm_mve_vmovnbq_m_u16, 21079, 21041}, |
| { ARM::BI__builtin_arm_mve_vmovnbq_m_u32, 21093, 21041}, |
| { ARM::BI__builtin_arm_mve_vmovnbq_s16, 21115, 21107}, |
| { ARM::BI__builtin_arm_mve_vmovnbq_s32, 21127, 21107}, |
| { ARM::BI__builtin_arm_mve_vmovnbq_u16, 21139, 21107}, |
| { ARM::BI__builtin_arm_mve_vmovnbq_u32, 21151, 21107}, |
| { ARM::BI__builtin_arm_mve_vmovntq_m_s16, 21173, 21163}, |
| { ARM::BI__builtin_arm_mve_vmovntq_m_s32, 21187, 21163}, |
| { ARM::BI__builtin_arm_mve_vmovntq_m_u16, 21201, 21163}, |
| { ARM::BI__builtin_arm_mve_vmovntq_m_u32, 21215, 21163}, |
| { ARM::BI__builtin_arm_mve_vmovntq_s16, 21237, 21229}, |
| { ARM::BI__builtin_arm_mve_vmovntq_s32, 21249, 21229}, |
| { ARM::BI__builtin_arm_mve_vmovntq_u16, 21261, 21229}, |
| { ARM::BI__builtin_arm_mve_vmovntq_u32, 21273, 21229}, |
| { ARM::BI__builtin_arm_mve_vmulhq_m_s16, 21294, 21285}, |
| { ARM::BI__builtin_arm_mve_vmulhq_m_s32, 21307, 21285}, |
| { ARM::BI__builtin_arm_mve_vmulhq_m_s8, 21320, 21285}, |
| { ARM::BI__builtin_arm_mve_vmulhq_m_u16, 21332, 21285}, |
| { ARM::BI__builtin_arm_mve_vmulhq_m_u32, 21345, 21285}, |
| { ARM::BI__builtin_arm_mve_vmulhq_m_u8, 21358, 21285}, |
| { ARM::BI__builtin_arm_mve_vmulhq_s16, 21377, 21370}, |
| { ARM::BI__builtin_arm_mve_vmulhq_s32, 21388, 21370}, |
| { ARM::BI__builtin_arm_mve_vmulhq_s8, 21399, 21370}, |
| { ARM::BI__builtin_arm_mve_vmulhq_u16, 21409, 21370}, |
| { ARM::BI__builtin_arm_mve_vmulhq_u32, 21420, 21370}, |
| { ARM::BI__builtin_arm_mve_vmulhq_u8, 21431, 21370}, |
| { ARM::BI__builtin_arm_mve_vmulhq_x_s16, 21450, 21441}, |
| { ARM::BI__builtin_arm_mve_vmulhq_x_s32, 21463, 21441}, |
| { ARM::BI__builtin_arm_mve_vmulhq_x_s8, 21476, 21441}, |
| { ARM::BI__builtin_arm_mve_vmulhq_x_u16, 21488, 21441}, |
| { ARM::BI__builtin_arm_mve_vmulhq_x_u32, 21501, 21441}, |
| { ARM::BI__builtin_arm_mve_vmulhq_x_u8, 21514, 21441}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_m_s16, 21540, 21526}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_m_s32, 21558, 21526}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_m_s8, 21576, 21526}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_m_u16, 21593, 21526}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_m_u32, 21611, 21526}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_m_u8, 21629, 21526}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_s16, 21658, 21646}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_s32, 21674, 21646}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_s8, 21690, 21646}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_u16, 21705, 21646}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_u32, 21721, 21646}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_u8, 21737, 21646}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_x_s16, 21766, 21752}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_x_s32, 21784, 21752}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_x_s8, 21802, 21752}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_x_u16, 21819, 21752}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_x_u32, 21837, 21752}, |
| { ARM::BI__builtin_arm_mve_vmullbq_int_x_u8, 21855, 21752}, |
| { ARM::BI__builtin_arm_mve_vmullbq_poly_m_p16, 21887, 21872}, |
| { ARM::BI__builtin_arm_mve_vmullbq_poly_m_p8, 21906, 21872}, |
| { ARM::BI__builtin_arm_mve_vmullbq_poly_p16, 21937, 21924}, |
| { ARM::BI__builtin_arm_mve_vmullbq_poly_p8, 21954, 21924}, |
| { ARM::BI__builtin_arm_mve_vmullbq_poly_x_p16, 21985, 21970}, |
| { ARM::BI__builtin_arm_mve_vmullbq_poly_x_p8, 22004, 21970}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_m_s16, 22036, 22022}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_m_s32, 22054, 22022}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_m_s8, 22072, 22022}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_m_u16, 22089, 22022}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_m_u32, 22107, 22022}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_m_u8, 22125, 22022}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_s16, 22154, 22142}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_s32, 22170, 22142}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_s8, 22186, 22142}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_u16, 22201, 22142}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_u32, 22217, 22142}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_u8, 22233, 22142}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_x_s16, 22262, 22248}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_x_s32, 22280, 22248}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_x_s8, 22298, 22248}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_x_u16, 22315, 22248}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_x_u32, 22333, 22248}, |
| { ARM::BI__builtin_arm_mve_vmulltq_int_x_u8, 22351, 22248}, |
| { ARM::BI__builtin_arm_mve_vmulltq_poly_m_p16, 22383, 22368}, |
| { ARM::BI__builtin_arm_mve_vmulltq_poly_m_p8, 22402, 22368}, |
| { ARM::BI__builtin_arm_mve_vmulltq_poly_p16, 22433, 22420}, |
| { ARM::BI__builtin_arm_mve_vmulltq_poly_p8, 22450, 22420}, |
| { ARM::BI__builtin_arm_mve_vmulltq_poly_x_p16, 22481, 22466}, |
| { ARM::BI__builtin_arm_mve_vmulltq_poly_x_p8, 22500, 22466}, |
| { ARM::BI__builtin_arm_mve_vmulq_f16, 22524, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_f32, 22534, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_f16, 22552, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_f32, 22564, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_n_f16, 22576, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_n_f32, 22590, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_n_s16, 22604, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_n_s32, 22618, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_n_s8, 22632, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_n_u16, 22645, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_n_u32, 22659, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_n_u8, 22673, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_s16, 22686, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_s32, 22698, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_s8, 22710, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_u16, 22721, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_u32, 22733, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_m_u8, 22745, 22544}, |
| { ARM::BI__builtin_arm_mve_vmulq_n_f16, 22756, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_n_f32, 22768, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_n_s16, 22780, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_n_s32, 22792, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_n_s8, 22804, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_n_u16, 22815, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_n_u32, 22827, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_n_u8, 22839, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_s16, 22850, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_s32, 22860, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_s8, 22870, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_u16, 22879, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_u32, 22889, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_u8, 22899, 22518}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_f16, 22916, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_f32, 22928, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_n_f16, 22940, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_n_f32, 22954, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_n_s16, 22968, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_n_s32, 22982, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_n_s8, 22996, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_n_u16, 23009, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_n_u32, 23023, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_n_u8, 23037, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_s16, 23050, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_s32, 23062, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_s8, 23074, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_u16, 23085, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_u32, 23097, 22908}, |
| { ARM::BI__builtin_arm_mve_vmulq_x_u8, 23109, 22908}, |
| { ARM::BI__builtin_arm_mve_vmvnq_m_n_s16, 23128, 23120}, |
| { ARM::BI__builtin_arm_mve_vmvnq_m_n_s32, 23142, 23120}, |
| { ARM::BI__builtin_arm_mve_vmvnq_m_n_u16, 23156, 23120}, |
| { ARM::BI__builtin_arm_mve_vmvnq_m_n_u32, 23170, 23120}, |
| { ARM::BI__builtin_arm_mve_vmvnq_m_s16, 23184, 23120}, |
| { ARM::BI__builtin_arm_mve_vmvnq_m_s32, 23196, 23120}, |
| { ARM::BI__builtin_arm_mve_vmvnq_m_s8, 23208, 23120}, |
| { ARM::BI__builtin_arm_mve_vmvnq_m_u16, 23219, 23120}, |
| { ARM::BI__builtin_arm_mve_vmvnq_m_u32, 23231, 23120}, |
| { ARM::BI__builtin_arm_mve_vmvnq_m_u8, 23243, 23120}, |
| { ARM::BI__builtin_arm_mve_vmvnq_n_s16, 23254, -1}, |
| { ARM::BI__builtin_arm_mve_vmvnq_n_s32, 23266, -1}, |
| { ARM::BI__builtin_arm_mve_vmvnq_n_u16, 23278, -1}, |
| { ARM::BI__builtin_arm_mve_vmvnq_n_u32, 23290, -1}, |
| { ARM::BI__builtin_arm_mve_vmvnq_s16, 23308, 23302}, |
| { ARM::BI__builtin_arm_mve_vmvnq_s32, 23318, 23302}, |
| { ARM::BI__builtin_arm_mve_vmvnq_s8, 23328, 23302}, |
| { ARM::BI__builtin_arm_mve_vmvnq_u16, 23337, 23302}, |
| { ARM::BI__builtin_arm_mve_vmvnq_u32, 23347, 23302}, |
| { ARM::BI__builtin_arm_mve_vmvnq_u8, 23357, 23302}, |
| { ARM::BI__builtin_arm_mve_vmvnq_x_n_s16, 23366, -1}, |
| { ARM::BI__builtin_arm_mve_vmvnq_x_n_s32, 23380, -1}, |
| { ARM::BI__builtin_arm_mve_vmvnq_x_n_u16, 23394, -1}, |
| { ARM::BI__builtin_arm_mve_vmvnq_x_n_u32, 23408, -1}, |
| { ARM::BI__builtin_arm_mve_vmvnq_x_s16, 23430, 23422}, |
| { ARM::BI__builtin_arm_mve_vmvnq_x_s32, 23442, 23422}, |
| { ARM::BI__builtin_arm_mve_vmvnq_x_s8, 23454, 23422}, |
| { ARM::BI__builtin_arm_mve_vmvnq_x_u16, 23465, 23422}, |
| { ARM::BI__builtin_arm_mve_vmvnq_x_u32, 23477, 23422}, |
| { ARM::BI__builtin_arm_mve_vmvnq_x_u8, 23489, 23422}, |
| { ARM::BI__builtin_arm_mve_vnegq_f16, 23506, 23500}, |
| { ARM::BI__builtin_arm_mve_vnegq_f32, 23516, 23500}, |
| { ARM::BI__builtin_arm_mve_vnegq_m_f16, 23534, 23526}, |
| { ARM::BI__builtin_arm_mve_vnegq_m_f32, 23546, 23526}, |
| { ARM::BI__builtin_arm_mve_vnegq_m_s16, 23558, 23526}, |
| { ARM::BI__builtin_arm_mve_vnegq_m_s32, 23570, 23526}, |
| { ARM::BI__builtin_arm_mve_vnegq_m_s8, 23582, 23526}, |
| { ARM::BI__builtin_arm_mve_vnegq_s16, 23593, 23500}, |
| { ARM::BI__builtin_arm_mve_vnegq_s32, 23603, 23500}, |
| { ARM::BI__builtin_arm_mve_vnegq_s8, 23613, 23500}, |
| { ARM::BI__builtin_arm_mve_vnegq_x_f16, 23630, 23622}, |
| { ARM::BI__builtin_arm_mve_vnegq_x_f32, 23642, 23622}, |
| { ARM::BI__builtin_arm_mve_vnegq_x_s16, 23654, 23622}, |
| { ARM::BI__builtin_arm_mve_vnegq_x_s32, 23666, 23622}, |
| { ARM::BI__builtin_arm_mve_vnegq_x_s8, 23678, 23622}, |
| { ARM::BI__builtin_arm_mve_vornq_f16, 23695, 23689}, |
| { ARM::BI__builtin_arm_mve_vornq_f32, 23705, 23689}, |
| { ARM::BI__builtin_arm_mve_vornq_m_f16, 23723, 23715}, |
| { ARM::BI__builtin_arm_mve_vornq_m_f32, 23735, 23715}, |
| { ARM::BI__builtin_arm_mve_vornq_m_s16, 23747, 23715}, |
| { ARM::BI__builtin_arm_mve_vornq_m_s32, 23759, 23715}, |
| { ARM::BI__builtin_arm_mve_vornq_m_s8, 23771, 23715}, |
| { ARM::BI__builtin_arm_mve_vornq_m_u16, 23782, 23715}, |
| { ARM::BI__builtin_arm_mve_vornq_m_u32, 23794, 23715}, |
| { ARM::BI__builtin_arm_mve_vornq_m_u8, 23806, 23715}, |
| { ARM::BI__builtin_arm_mve_vornq_s16, 23817, 23689}, |
| { ARM::BI__builtin_arm_mve_vornq_s32, 23827, 23689}, |
| { ARM::BI__builtin_arm_mve_vornq_s8, 23837, 23689}, |
| { ARM::BI__builtin_arm_mve_vornq_u16, 23846, 23689}, |
| { ARM::BI__builtin_arm_mve_vornq_u32, 23856, 23689}, |
| { ARM::BI__builtin_arm_mve_vornq_u8, 23866, 23689}, |
| { ARM::BI__builtin_arm_mve_vornq_x_f16, 23883, 23875}, |
| { ARM::BI__builtin_arm_mve_vornq_x_f32, 23895, 23875}, |
| { ARM::BI__builtin_arm_mve_vornq_x_s16, 23907, 23875}, |
| { ARM::BI__builtin_arm_mve_vornq_x_s32, 23919, 23875}, |
| { ARM::BI__builtin_arm_mve_vornq_x_s8, 23931, 23875}, |
| { ARM::BI__builtin_arm_mve_vornq_x_u16, 23942, 23875}, |
| { ARM::BI__builtin_arm_mve_vornq_x_u32, 23954, 23875}, |
| { ARM::BI__builtin_arm_mve_vornq_x_u8, 23966, 23875}, |
| { ARM::BI__builtin_arm_mve_vorrq_f16, 23983, 23977}, |
| { ARM::BI__builtin_arm_mve_vorrq_f32, 23993, 23977}, |
| { ARM::BI__builtin_arm_mve_vorrq_m_f16, 24011, 24003}, |
| { ARM::BI__builtin_arm_mve_vorrq_m_f32, 24023, 24003}, |
| { ARM::BI__builtin_arm_mve_vorrq_m_n_s16, 24045, 24035}, |
| { ARM::BI__builtin_arm_mve_vorrq_m_n_s32, 24059, 24035}, |
| { ARM::BI__builtin_arm_mve_vorrq_m_n_u16, 24073, 24035}, |
| { ARM::BI__builtin_arm_mve_vorrq_m_n_u32, 24087, 24035}, |
| { ARM::BI__builtin_arm_mve_vorrq_m_s16, 24101, 24003}, |
| { ARM::BI__builtin_arm_mve_vorrq_m_s32, 24113, 24003}, |
| { ARM::BI__builtin_arm_mve_vorrq_m_s8, 24125, 24003}, |
| { ARM::BI__builtin_arm_mve_vorrq_m_u16, 24136, 24003}, |
| { ARM::BI__builtin_arm_mve_vorrq_m_u32, 24148, 24003}, |
| { ARM::BI__builtin_arm_mve_vorrq_m_u8, 24160, 24003}, |
| { ARM::BI__builtin_arm_mve_vorrq_n_s16, 24171, 23977}, |
| { ARM::BI__builtin_arm_mve_vorrq_n_s32, 24183, 23977}, |
| { ARM::BI__builtin_arm_mve_vorrq_n_u16, 24195, 23977}, |
| { ARM::BI__builtin_arm_mve_vorrq_n_u32, 24207, 23977}, |
| { ARM::BI__builtin_arm_mve_vorrq_s16, 24219, 23977}, |
| { ARM::BI__builtin_arm_mve_vorrq_s32, 24229, 23977}, |
| { ARM::BI__builtin_arm_mve_vorrq_s8, 24239, 23977}, |
| { ARM::BI__builtin_arm_mve_vorrq_u16, 24248, 23977}, |
| { ARM::BI__builtin_arm_mve_vorrq_u32, 24258, 23977}, |
| { ARM::BI__builtin_arm_mve_vorrq_u8, 24268, 23977}, |
| { ARM::BI__builtin_arm_mve_vorrq_x_f16, 24285, 24277}, |
| { ARM::BI__builtin_arm_mve_vorrq_x_f32, 24297, 24277}, |
| { ARM::BI__builtin_arm_mve_vorrq_x_s16, 24309, 24277}, |
| { ARM::BI__builtin_arm_mve_vorrq_x_s32, 24321, 24277}, |
| { ARM::BI__builtin_arm_mve_vorrq_x_s8, 24333, 24277}, |
| { ARM::BI__builtin_arm_mve_vorrq_x_u16, 24344, 24277}, |
| { ARM::BI__builtin_arm_mve_vorrq_x_u32, 24356, 24277}, |
| { ARM::BI__builtin_arm_mve_vorrq_x_u8, 24368, 24277}, |
| { ARM::BI__builtin_arm_mve_vpnot, 24379, -1}, |
| { ARM::BI__builtin_arm_mve_vpselq_f16, 24392, 24385}, |
| { ARM::BI__builtin_arm_mve_vpselq_f32, 24403, 24385}, |
| { ARM::BI__builtin_arm_mve_vpselq_s16, 24414, 24385}, |
| { ARM::BI__builtin_arm_mve_vpselq_s32, 24425, 24385}, |
| { ARM::BI__builtin_arm_mve_vpselq_s64, 24436, 24385}, |
| { ARM::BI__builtin_arm_mve_vpselq_s8, 24447, 24385}, |
| { ARM::BI__builtin_arm_mve_vpselq_u16, 24457, 24385}, |
| { ARM::BI__builtin_arm_mve_vpselq_u32, 24468, 24385}, |
| { ARM::BI__builtin_arm_mve_vpselq_u64, 24479, 24385}, |
| { ARM::BI__builtin_arm_mve_vpselq_u8, 24490, 24385}, |
| { ARM::BI__builtin_arm_mve_vqabsq_m_s16, 24509, 24500}, |
| { ARM::BI__builtin_arm_mve_vqabsq_m_s32, 24522, 24500}, |
| { ARM::BI__builtin_arm_mve_vqabsq_m_s8, 24535, 24500}, |
| { ARM::BI__builtin_arm_mve_vqabsq_s16, 24554, 24547}, |
| { ARM::BI__builtin_arm_mve_vqabsq_s32, 24565, 24547}, |
| { ARM::BI__builtin_arm_mve_vqabsq_s8, 24576, 24547}, |
| { ARM::BI__builtin_arm_mve_vqaddq_m_n_s16, 24595, 24586}, |
| { ARM::BI__builtin_arm_mve_vqaddq_m_n_s32, 24610, 24586}, |
| { ARM::BI__builtin_arm_mve_vqaddq_m_n_s8, 24625, 24586}, |
| { ARM::BI__builtin_arm_mve_vqaddq_m_n_u16, 24639, 24586}, |
| { ARM::BI__builtin_arm_mve_vqaddq_m_n_u32, 24654, 24586}, |
| { ARM::BI__builtin_arm_mve_vqaddq_m_n_u8, 24669, 24586}, |
| { ARM::BI__builtin_arm_mve_vqaddq_m_s16, 24683, 24586}, |
| { ARM::BI__builtin_arm_mve_vqaddq_m_s32, 24696, 24586}, |
| { ARM::BI__builtin_arm_mve_vqaddq_m_s8, 24709, 24586}, |
| { ARM::BI__builtin_arm_mve_vqaddq_m_u16, 24721, 24586}, |
| { ARM::BI__builtin_arm_mve_vqaddq_m_u32, 24734, 24586}, |
| { ARM::BI__builtin_arm_mve_vqaddq_m_u8, 24747, 24586}, |
| { ARM::BI__builtin_arm_mve_vqaddq_n_s16, 24766, 24759}, |
| { ARM::BI__builtin_arm_mve_vqaddq_n_s32, 24779, 24759}, |
| { ARM::BI__builtin_arm_mve_vqaddq_n_s8, 24792, 24759}, |
| { ARM::BI__builtin_arm_mve_vqaddq_n_u16, 24804, 24759}, |
| { ARM::BI__builtin_arm_mve_vqaddq_n_u32, 24817, 24759}, |
| { ARM::BI__builtin_arm_mve_vqaddq_n_u8, 24830, 24759}, |
| { ARM::BI__builtin_arm_mve_vqaddq_s16, 24842, 24759}, |
| { ARM::BI__builtin_arm_mve_vqaddq_s32, 24853, 24759}, |
| { ARM::BI__builtin_arm_mve_vqaddq_s8, 24864, 24759}, |
| { ARM::BI__builtin_arm_mve_vqaddq_u16, 24874, 24759}, |
| { ARM::BI__builtin_arm_mve_vqaddq_u32, 24885, 24759}, |
| { ARM::BI__builtin_arm_mve_vqaddq_u8, 24896, 24759}, |
| { ARM::BI__builtin_arm_mve_vqdmladhq_m_s16, 24918, 24906}, |
| { ARM::BI__builtin_arm_mve_vqdmladhq_m_s32, 24934, 24906}, |
| { ARM::BI__builtin_arm_mve_vqdmladhq_m_s8, 24950, 24906}, |
| { ARM::BI__builtin_arm_mve_vqdmladhq_s16, 24975, 24965}, |
| { ARM::BI__builtin_arm_mve_vqdmladhq_s32, 24989, 24965}, |
| { ARM::BI__builtin_arm_mve_vqdmladhq_s8, 25003, 24965}, |
| { ARM::BI__builtin_arm_mve_vqdmladhxq_m_s16, 25029, 25016}, |
| { ARM::BI__builtin_arm_mve_vqdmladhxq_m_s32, 25046, 25016}, |
| { ARM::BI__builtin_arm_mve_vqdmladhxq_m_s8, 25063, 25016}, |
| { ARM::BI__builtin_arm_mve_vqdmladhxq_s16, 25090, 25079}, |
| { ARM::BI__builtin_arm_mve_vqdmladhxq_s32, 25105, 25079}, |
| { ARM::BI__builtin_arm_mve_vqdmladhxq_s8, 25120, 25079}, |
| { ARM::BI__builtin_arm_mve_vqdmlahq_m_n_s16, 25145, 25134}, |
| { ARM::BI__builtin_arm_mve_vqdmlahq_m_n_s32, 25162, 25134}, |
| { ARM::BI__builtin_arm_mve_vqdmlahq_m_n_s8, 25179, 25134}, |
| { ARM::BI__builtin_arm_mve_vqdmlahq_n_s16, 25204, 25195}, |
| { ARM::BI__builtin_arm_mve_vqdmlahq_n_s32, 25219, 25195}, |
| { ARM::BI__builtin_arm_mve_vqdmlahq_n_s8, 25234, 25195}, |
| { ARM::BI__builtin_arm_mve_vqdmlashq_m_n_s16, 25260, 25248}, |
| { ARM::BI__builtin_arm_mve_vqdmlashq_m_n_s32, 25278, 25248}, |
| { ARM::BI__builtin_arm_mve_vqdmlashq_m_n_s8, 25296, 25248}, |
| { ARM::BI__builtin_arm_mve_vqdmlashq_n_s16, 25323, 25313}, |
| { ARM::BI__builtin_arm_mve_vqdmlashq_n_s32, 25339, 25313}, |
| { ARM::BI__builtin_arm_mve_vqdmlashq_n_s8, 25355, 25313}, |
| { ARM::BI__builtin_arm_mve_vqdmlsdhq_m_s16, 25382, 25370}, |
| { ARM::BI__builtin_arm_mve_vqdmlsdhq_m_s32, 25398, 25370}, |
| { ARM::BI__builtin_arm_mve_vqdmlsdhq_m_s8, 25414, 25370}, |
| { ARM::BI__builtin_arm_mve_vqdmlsdhq_s16, 25439, 25429}, |
| { ARM::BI__builtin_arm_mve_vqdmlsdhq_s32, 25453, 25429}, |
| { ARM::BI__builtin_arm_mve_vqdmlsdhq_s8, 25467, 25429}, |
| { ARM::BI__builtin_arm_mve_vqdmlsdhxq_m_s16, 25493, 25480}, |
| { ARM::BI__builtin_arm_mve_vqdmlsdhxq_m_s32, 25510, 25480}, |
| { ARM::BI__builtin_arm_mve_vqdmlsdhxq_m_s8, 25527, 25480}, |
| { ARM::BI__builtin_arm_mve_vqdmlsdhxq_s16, 25554, 25543}, |
| { ARM::BI__builtin_arm_mve_vqdmlsdhxq_s32, 25569, 25543}, |
| { ARM::BI__builtin_arm_mve_vqdmlsdhxq_s8, 25584, 25543}, |
| { ARM::BI__builtin_arm_mve_vqdmulhq_m_n_s16, 25609, 25598}, |
| { ARM::BI__builtin_arm_mve_vqdmulhq_m_n_s32, 25626, 25598}, |
| { ARM::BI__builtin_arm_mve_vqdmulhq_m_n_s8, 25643, 25598}, |
| { ARM::BI__builtin_arm_mve_vqdmulhq_m_s16, 25659, 25598}, |
| { ARM::BI__builtin_arm_mve_vqdmulhq_m_s32, 25674, 25598}, |
| { ARM::BI__builtin_arm_mve_vqdmulhq_m_s8, 25689, 25598}, |
| { ARM::BI__builtin_arm_mve_vqdmulhq_n_s16, 25712, 25703}, |
| { ARM::BI__builtin_arm_mve_vqdmulhq_n_s32, 25727, 25703}, |
| { ARM::BI__builtin_arm_mve_vqdmulhq_n_s8, 25742, 25703}, |
| { ARM::BI__builtin_arm_mve_vqdmulhq_s16, 25756, 25703}, |
| { ARM::BI__builtin_arm_mve_vqdmulhq_s32, 25769, 25703}, |
| { ARM::BI__builtin_arm_mve_vqdmulhq_s8, 25782, 25703}, |
| { ARM::BI__builtin_arm_mve_vqdmullbq_m_n_s16, 25806, 25794}, |
| { ARM::BI__builtin_arm_mve_vqdmullbq_m_n_s32, 25824, 25794}, |
| { ARM::BI__builtin_arm_mve_vqdmullbq_m_s16, 25842, 25794}, |
| { ARM::BI__builtin_arm_mve_vqdmullbq_m_s32, 25858, 25794}, |
| { ARM::BI__builtin_arm_mve_vqdmullbq_n_s16, 25884, 25874}, |
| { ARM::BI__builtin_arm_mve_vqdmullbq_n_s32, 25900, 25874}, |
| { ARM::BI__builtin_arm_mve_vqdmullbq_s16, 25916, 25874}, |
| { ARM::BI__builtin_arm_mve_vqdmullbq_s32, 25930, 25874}, |
| { ARM::BI__builtin_arm_mve_vqdmulltq_m_n_s16, 25956, 25944}, |
| { ARM::BI__builtin_arm_mve_vqdmulltq_m_n_s32, 25974, 25944}, |
| { ARM::BI__builtin_arm_mve_vqdmulltq_m_s16, 25992, 25944}, |
| { ARM::BI__builtin_arm_mve_vqdmulltq_m_s32, 26008, 25944}, |
| { ARM::BI__builtin_arm_mve_vqdmulltq_n_s16, 26034, 26024}, |
| { ARM::BI__builtin_arm_mve_vqdmulltq_n_s32, 26050, 26024}, |
| { ARM::BI__builtin_arm_mve_vqdmulltq_s16, 26066, 26024}, |
| { ARM::BI__builtin_arm_mve_vqdmulltq_s32, 26080, 26024}, |
| { ARM::BI__builtin_arm_mve_vqmovnbq_m_s16, 26105, 26094}, |
| { ARM::BI__builtin_arm_mve_vqmovnbq_m_s32, 26120, 26094}, |
| { ARM::BI__builtin_arm_mve_vqmovnbq_m_u16, 26135, 26094}, |
| { ARM::BI__builtin_arm_mve_vqmovnbq_m_u32, 26150, 26094}, |
| { ARM::BI__builtin_arm_mve_vqmovnbq_s16, 26174, 26165}, |
| { ARM::BI__builtin_arm_mve_vqmovnbq_s32, 26187, 26165}, |
| { ARM::BI__builtin_arm_mve_vqmovnbq_u16, 26200, 26165}, |
| { ARM::BI__builtin_arm_mve_vqmovnbq_u32, 26213, 26165}, |
| { ARM::BI__builtin_arm_mve_vqmovntq_m_s16, 26237, 26226}, |
| { ARM::BI__builtin_arm_mve_vqmovntq_m_s32, 26252, 26226}, |
| { ARM::BI__builtin_arm_mve_vqmovntq_m_u16, 26267, 26226}, |
| { ARM::BI__builtin_arm_mve_vqmovntq_m_u32, 26282, 26226}, |
| { ARM::BI__builtin_arm_mve_vqmovntq_s16, 26306, 26297}, |
| { ARM::BI__builtin_arm_mve_vqmovntq_s32, 26319, 26297}, |
| { ARM::BI__builtin_arm_mve_vqmovntq_u16, 26332, 26297}, |
| { ARM::BI__builtin_arm_mve_vqmovntq_u32, 26345, 26297}, |
| { ARM::BI__builtin_arm_mve_vqmovunbq_m_s16, 26370, 26358}, |
| { ARM::BI__builtin_arm_mve_vqmovunbq_m_s32, 26386, 26358}, |
| { ARM::BI__builtin_arm_mve_vqmovunbq_s16, 26412, 26402}, |
| { ARM::BI__builtin_arm_mve_vqmovunbq_s32, 26426, 26402}, |
| { ARM::BI__builtin_arm_mve_vqmovuntq_m_s16, 26452, 26440}, |
| { ARM::BI__builtin_arm_mve_vqmovuntq_m_s32, 26468, 26440}, |
| { ARM::BI__builtin_arm_mve_vqmovuntq_s16, 26494, 26484}, |
| { ARM::BI__builtin_arm_mve_vqmovuntq_s32, 26508, 26484}, |
| { ARM::BI__builtin_arm_mve_vqnegq_m_s16, 26531, 26522}, |
| { ARM::BI__builtin_arm_mve_vqnegq_m_s32, 26544, 26522}, |
| { ARM::BI__builtin_arm_mve_vqnegq_m_s8, 26557, 26522}, |
| { ARM::BI__builtin_arm_mve_vqnegq_s16, 26576, 26569}, |
| { ARM::BI__builtin_arm_mve_vqnegq_s32, 26587, 26569}, |
| { ARM::BI__builtin_arm_mve_vqnegq_s8, 26598, 26569}, |
| { ARM::BI__builtin_arm_mve_vqrdmladhq_m_s16, 26621, 26608}, |
| { ARM::BI__builtin_arm_mve_vqrdmladhq_m_s32, 26638, 26608}, |
| { ARM::BI__builtin_arm_mve_vqrdmladhq_m_s8, 26655, 26608}, |
| { ARM::BI__builtin_arm_mve_vqrdmladhq_s16, 26682, 26671}, |
| { ARM::BI__builtin_arm_mve_vqrdmladhq_s32, 26697, 26671}, |
| { ARM::BI__builtin_arm_mve_vqrdmladhq_s8, 26712, 26671}, |
| { ARM::BI__builtin_arm_mve_vqrdmladhxq_m_s16, 26740, 26726}, |
| { ARM::BI__builtin_arm_mve_vqrdmladhxq_m_s32, 26758, 26726}, |
| { ARM::BI__builtin_arm_mve_vqrdmladhxq_m_s8, 26776, 26726}, |
| { ARM::BI__builtin_arm_mve_vqrdmladhxq_s16, 26805, 26793}, |
| { ARM::BI__builtin_arm_mve_vqrdmladhxq_s32, 26821, 26793}, |
| { ARM::BI__builtin_arm_mve_vqrdmladhxq_s8, 26837, 26793}, |
| { ARM::BI__builtin_arm_mve_vqrdmlahq_m_n_s16, 26864, 26852}, |
| { ARM::BI__builtin_arm_mve_vqrdmlahq_m_n_s32, 26882, 26852}, |
| { ARM::BI__builtin_arm_mve_vqrdmlahq_m_n_s8, 26900, 26852}, |
| { ARM::BI__builtin_arm_mve_vqrdmlahq_n_s16, 26927, 26917}, |
| { ARM::BI__builtin_arm_mve_vqrdmlahq_n_s32, 26943, 26917}, |
| { ARM::BI__builtin_arm_mve_vqrdmlahq_n_s8, 26959, 26917}, |
| { ARM::BI__builtin_arm_mve_vqrdmlashq_m_n_s16, 26987, 26974}, |
| { ARM::BI__builtin_arm_mve_vqrdmlashq_m_n_s32, 27006, 26974}, |
| { ARM::BI__builtin_arm_mve_vqrdmlashq_m_n_s8, 27025, 26974}, |
| { ARM::BI__builtin_arm_mve_vqrdmlashq_n_s16, 27054, 27043}, |
| { ARM::BI__builtin_arm_mve_vqrdmlashq_n_s32, 27071, 27043}, |
| { ARM::BI__builtin_arm_mve_vqrdmlashq_n_s8, 27088, 27043}, |
| { ARM::BI__builtin_arm_mve_vqrdmlsdhq_m_s16, 27117, 27104}, |
| { ARM::BI__builtin_arm_mve_vqrdmlsdhq_m_s32, 27134, 27104}, |
| { ARM::BI__builtin_arm_mve_vqrdmlsdhq_m_s8, 27151, 27104}, |
| { ARM::BI__builtin_arm_mve_vqrdmlsdhq_s16, 27178, 27167}, |
| { ARM::BI__builtin_arm_mve_vqrdmlsdhq_s32, 27193, 27167}, |
| { ARM::BI__builtin_arm_mve_vqrdmlsdhq_s8, 27208, 27167}, |
| { ARM::BI__builtin_arm_mve_vqrdmlsdhxq_m_s16, 27236, 27222}, |
| { ARM::BI__builtin_arm_mve_vqrdmlsdhxq_m_s32, 27254, 27222}, |
| { ARM::BI__builtin_arm_mve_vqrdmlsdhxq_m_s8, 27272, 27222}, |
| { ARM::BI__builtin_arm_mve_vqrdmlsdhxq_s16, 27301, 27289}, |
| { ARM::BI__builtin_arm_mve_vqrdmlsdhxq_s32, 27317, 27289}, |
| { ARM::BI__builtin_arm_mve_vqrdmlsdhxq_s8, 27333, 27289}, |
| { ARM::BI__builtin_arm_mve_vqrdmulhq_m_n_s16, 27360, 27348}, |
| { ARM::BI__builtin_arm_mve_vqrdmulhq_m_n_s32, 27378, 27348}, |
| { ARM::BI__builtin_arm_mve_vqrdmulhq_m_n_s8, 27396, 27348}, |
| { ARM::BI__builtin_arm_mve_vqrdmulhq_m_s16, 27413, 27348}, |
| { ARM::BI__builtin_arm_mve_vqrdmulhq_m_s32, 27429, 27348}, |
| { ARM::BI__builtin_arm_mve_vqrdmulhq_m_s8, 27445, 27348}, |
| { ARM::BI__builtin_arm_mve_vqrdmulhq_n_s16, 27470, 27460}, |
| { ARM::BI__builtin_arm_mve_vqrdmulhq_n_s32, 27486, 27460}, |
| { ARM::BI__builtin_arm_mve_vqrdmulhq_n_s8, 27502, 27460}, |
| { ARM::BI__builtin_arm_mve_vqrdmulhq_s16, 27517, 27460}, |
| { ARM::BI__builtin_arm_mve_vqrdmulhq_s32, 27531, 27460}, |
| { ARM::BI__builtin_arm_mve_vqrdmulhq_s8, 27545, 27460}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_m_n_s16, 27570, 27558}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_m_n_s32, 27586, 27558}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_m_n_s8, 27602, 27558}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_m_n_u16, 27617, 27558}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_m_n_u32, 27633, 27558}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_m_n_u8, 27649, 27558}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_m_s16, 27674, 27664}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_m_s32, 27688, 27664}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_m_s8, 27702, 27664}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_m_u16, 27715, 27664}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_m_u32, 27729, 27664}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_m_u8, 27743, 27664}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_n_s16, 27764, 27756}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_n_s32, 27778, 27756}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_n_s8, 27792, 27756}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_n_u16, 27805, 27756}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_n_u32, 27819, 27756}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_n_u8, 27833, 27756}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_s16, 27846, 27756}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_s32, 27858, 27756}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_s8, 27870, 27756}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_u16, 27881, 27756}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_u32, 27893, 27756}, |
| { ARM::BI__builtin_arm_mve_vqrshlq_u8, 27905, 27756}, |
| { ARM::BI__builtin_arm_mve_vqrshrnbq_m_n_s16, 27928, 27916}, |
| { ARM::BI__builtin_arm_mve_vqrshrnbq_m_n_s32, 27946, 27916}, |
| { ARM::BI__builtin_arm_mve_vqrshrnbq_m_n_u16, 27964, 27916}, |
| { ARM::BI__builtin_arm_mve_vqrshrnbq_m_n_u32, 27982, 27916}, |
| { ARM::BI__builtin_arm_mve_vqrshrnbq_n_s16, 28010, 28000}, |
| { ARM::BI__builtin_arm_mve_vqrshrnbq_n_s32, 28026, 28000}, |
| { ARM::BI__builtin_arm_mve_vqrshrnbq_n_u16, 28042, 28000}, |
| { ARM::BI__builtin_arm_mve_vqrshrnbq_n_u32, 28058, 28000}, |
| { ARM::BI__builtin_arm_mve_vqrshrntq_m_n_s16, 28086, 28074}, |
| { ARM::BI__builtin_arm_mve_vqrshrntq_m_n_s32, 28104, 28074}, |
| { ARM::BI__builtin_arm_mve_vqrshrntq_m_n_u16, 28122, 28074}, |
| { ARM::BI__builtin_arm_mve_vqrshrntq_m_n_u32, 28140, 28074}, |
| { ARM::BI__builtin_arm_mve_vqrshrntq_n_s16, 28168, 28158}, |
| { ARM::BI__builtin_arm_mve_vqrshrntq_n_s32, 28184, 28158}, |
| { ARM::BI__builtin_arm_mve_vqrshrntq_n_u16, 28200, 28158}, |
| { ARM::BI__builtin_arm_mve_vqrshrntq_n_u32, 28216, 28158}, |
| { ARM::BI__builtin_arm_mve_vqrshrunbq_m_n_s16, 28245, 28232}, |
| { ARM::BI__builtin_arm_mve_vqrshrunbq_m_n_s32, 28264, 28232}, |
| { ARM::BI__builtin_arm_mve_vqrshrunbq_n_s16, 28294, 28283}, |
| { ARM::BI__builtin_arm_mve_vqrshrunbq_n_s32, 28311, 28283}, |
| { ARM::BI__builtin_arm_mve_vqrshruntq_m_n_s16, 28341, 28328}, |
| { ARM::BI__builtin_arm_mve_vqrshruntq_m_n_s32, 28360, 28328}, |
| { ARM::BI__builtin_arm_mve_vqrshruntq_n_s16, 28390, 28379}, |
| { ARM::BI__builtin_arm_mve_vqrshruntq_n_s32, 28407, 28379}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_n_s16, 28435, 28424}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_n_s32, 28450, 28424}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_n_s8, 28465, 28424}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_n_u16, 28479, 28424}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_n_u32, 28494, 28424}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_n_u8, 28509, 28424}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_r_s16, 28534, 28523}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_r_s32, 28549, 28523}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_r_s8, 28564, 28523}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_r_u16, 28578, 28523}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_r_u32, 28593, 28523}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_r_u8, 28608, 28523}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_s16, 28631, 28622}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_s32, 28644, 28622}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_s8, 28657, 28622}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_u16, 28669, 28622}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_u32, 28682, 28622}, |
| { ARM::BI__builtin_arm_mve_vqshlq_m_u8, 28695, 28622}, |
| { ARM::BI__builtin_arm_mve_vqshlq_n_s16, 28716, 28707}, |
| { ARM::BI__builtin_arm_mve_vqshlq_n_s32, 28729, 28707}, |
| { ARM::BI__builtin_arm_mve_vqshlq_n_s8, 28742, 28707}, |
| { ARM::BI__builtin_arm_mve_vqshlq_n_u16, 28754, 28707}, |
| { ARM::BI__builtin_arm_mve_vqshlq_n_u32, 28767, 28707}, |
| { ARM::BI__builtin_arm_mve_vqshlq_n_u8, 28780, 28707}, |
| { ARM::BI__builtin_arm_mve_vqshlq_r_s16, 28801, 28792}, |
| { ARM::BI__builtin_arm_mve_vqshlq_r_s32, 28814, 28792}, |
| { ARM::BI__builtin_arm_mve_vqshlq_r_s8, 28827, 28792}, |
| { ARM::BI__builtin_arm_mve_vqshlq_r_u16, 28839, 28792}, |
| { ARM::BI__builtin_arm_mve_vqshlq_r_u32, 28852, 28792}, |
| { ARM::BI__builtin_arm_mve_vqshlq_r_u8, 28865, 28792}, |
| { ARM::BI__builtin_arm_mve_vqshlq_s16, 28884, 28877}, |
| { ARM::BI__builtin_arm_mve_vqshlq_s32, 28895, 28877}, |
| { ARM::BI__builtin_arm_mve_vqshlq_s8, 28906, 28877}, |
| { ARM::BI__builtin_arm_mve_vqshlq_u16, 28916, 28877}, |
| { ARM::BI__builtin_arm_mve_vqshlq_u32, 28927, 28877}, |
| { ARM::BI__builtin_arm_mve_vqshlq_u8, 28938, 28877}, |
| { ARM::BI__builtin_arm_mve_vqshluq_m_n_s16, 28958, 28948}, |
| { ARM::BI__builtin_arm_mve_vqshluq_m_n_s32, 28974, 28948}, |
| { ARM::BI__builtin_arm_mve_vqshluq_m_n_s8, 28990, 28948}, |
| { ARM::BI__builtin_arm_mve_vqshluq_n_s16, 29013, 29005}, |
| { ARM::BI__builtin_arm_mve_vqshluq_n_s32, 29027, 29005}, |
| { ARM::BI__builtin_arm_mve_vqshluq_n_s8, 29041, 29005}, |
| { ARM::BI__builtin_arm_mve_vqshrnbq_m_n_s16, 29065, 29054}, |
| { ARM::BI__builtin_arm_mve_vqshrnbq_m_n_s32, 29082, 29054}, |
| { ARM::BI__builtin_arm_mve_vqshrnbq_m_n_u16, 29099, 29054}, |
| { ARM::BI__builtin_arm_mve_vqshrnbq_m_n_u32, 29116, 29054}, |
| { ARM::BI__builtin_arm_mve_vqshrnbq_n_s16, 29142, 29133}, |
| { ARM::BI__builtin_arm_mve_vqshrnbq_n_s32, 29157, 29133}, |
| { ARM::BI__builtin_arm_mve_vqshrnbq_n_u16, 29172, 29133}, |
| { ARM::BI__builtin_arm_mve_vqshrnbq_n_u32, 29187, 29133}, |
| { ARM::BI__builtin_arm_mve_vqshrntq_m_n_s16, 29213, 29202}, |
| { ARM::BI__builtin_arm_mve_vqshrntq_m_n_s32, 29230, 29202}, |
| { ARM::BI__builtin_arm_mve_vqshrntq_m_n_u16, 29247, 29202}, |
| { ARM::BI__builtin_arm_mve_vqshrntq_m_n_u32, 29264, 29202}, |
| { ARM::BI__builtin_arm_mve_vqshrntq_n_s16, 29290, 29281}, |
| { ARM::BI__builtin_arm_mve_vqshrntq_n_s32, 29305, 29281}, |
| { ARM::BI__builtin_arm_mve_vqshrntq_n_u16, 29320, 29281}, |
| { ARM::BI__builtin_arm_mve_vqshrntq_n_u32, 29335, 29281}, |
| { ARM::BI__builtin_arm_mve_vqshrunbq_m_n_s16, 29362, 29350}, |
| { ARM::BI__builtin_arm_mve_vqshrunbq_m_n_s32, 29380, 29350}, |
| { ARM::BI__builtin_arm_mve_vqshrunbq_n_s16, 29408, 29398}, |
| { ARM::BI__builtin_arm_mve_vqshrunbq_n_s32, 29424, 29398}, |
| { ARM::BI__builtin_arm_mve_vqshruntq_m_n_s16, 29452, 29440}, |
| { ARM::BI__builtin_arm_mve_vqshruntq_m_n_s32, 29470, 29440}, |
| { ARM::BI__builtin_arm_mve_vqshruntq_n_s16, 29498, 29488}, |
| { ARM::BI__builtin_arm_mve_vqshruntq_n_s32, 29514, 29488}, |
| { ARM::BI__builtin_arm_mve_vqsubq_m_n_s16, 29539, 29530}, |
| { ARM::BI__builtin_arm_mve_vqsubq_m_n_s32, 29554, 29530}, |
| { ARM::BI__builtin_arm_mve_vqsubq_m_n_s8, 29569, 29530}, |
| { ARM::BI__builtin_arm_mve_vqsubq_m_n_u16, 29583, 29530}, |
| { ARM::BI__builtin_arm_mve_vqsubq_m_n_u32, 29598, 29530}, |
| { ARM::BI__builtin_arm_mve_vqsubq_m_n_u8, 29613, 29530}, |
| { ARM::BI__builtin_arm_mve_vqsubq_m_s16, 29627, 29530}, |
| { ARM::BI__builtin_arm_mve_vqsubq_m_s32, 29640, 29530}, |
| { ARM::BI__builtin_arm_mve_vqsubq_m_s8, 29653, 29530}, |
| { ARM::BI__builtin_arm_mve_vqsubq_m_u16, 29665, 29530}, |
| { ARM::BI__builtin_arm_mve_vqsubq_m_u32, 29678, 29530}, |
| { ARM::BI__builtin_arm_mve_vqsubq_m_u8, 29691, 29530}, |
| { ARM::BI__builtin_arm_mve_vqsubq_n_s16, 29710, 29703}, |
| { ARM::BI__builtin_arm_mve_vqsubq_n_s32, 29723, 29703}, |
| { ARM::BI__builtin_arm_mve_vqsubq_n_s8, 29736, 29703}, |
| { ARM::BI__builtin_arm_mve_vqsubq_n_u16, 29748, 29703}, |
| { ARM::BI__builtin_arm_mve_vqsubq_n_u32, 29761, 29703}, |
| { ARM::BI__builtin_arm_mve_vqsubq_n_u8, 29774, 29703}, |
| { ARM::BI__builtin_arm_mve_vqsubq_s16, 29786, 29703}, |
| { ARM::BI__builtin_arm_mve_vqsubq_s32, 29797, 29703}, |
| { ARM::BI__builtin_arm_mve_vqsubq_s8, 29808, 29703}, |
| { ARM::BI__builtin_arm_mve_vqsubq_u16, 29818, 29703}, |
| { ARM::BI__builtin_arm_mve_vqsubq_u32, 29829, 29703}, |
| { ARM::BI__builtin_arm_mve_vqsubq_u8, 29840, 29703}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f16_f32, 29868, 29850}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f16_s16, 29890, 29850}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f16_s32, 29912, 29850}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f16_s64, 29934, 29850}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f16_s8, 29956, 29850}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f16_u16, 29977, 29850}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f16_u32, 29999, 29850}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f16_u64, 30021, 29850}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f16_u8, 30043, 29850}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f32_f16, 30082, 30064}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f32_s16, 30104, 30064}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f32_s32, 30126, 30064}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f32_s64, 30148, 30064}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f32_s8, 30170, 30064}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f32_u16, 30191, 30064}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f32_u32, 30213, 30064}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f32_u64, 30235, 30064}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_f32_u8, 30257, 30064}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s16_f16, 30296, 30278}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s16_f32, 30318, 30278}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s16_s32, 30340, 30278}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s16_s64, 30362, 30278}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s16_s8, 30384, 30278}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s16_u16, 30405, 30278}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s16_u32, 30427, 30278}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s16_u64, 30449, 30278}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s16_u8, 30471, 30278}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s32_f16, 30510, 30492}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s32_f32, 30532, 30492}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s32_s16, 30554, 30492}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s32_s64, 30576, 30492}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s32_s8, 30598, 30492}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s32_u16, 30619, 30492}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s32_u32, 30641, 30492}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s32_u64, 30663, 30492}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s32_u8, 30685, 30492}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s64_f16, 30724, 30706}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s64_f32, 30746, 30706}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s64_s16, 30768, 30706}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s64_s32, 30790, 30706}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s64_s8, 30812, 30706}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s64_u16, 30833, 30706}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s64_u32, 30855, 30706}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s64_u64, 30877, 30706}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s64_u8, 30899, 30706}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s8_f16, 30937, 30920}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s8_f32, 30958, 30920}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s8_s16, 30979, 30920}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s8_s32, 31000, 30920}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s8_s64, 31021, 30920}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s8_u16, 31042, 30920}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s8_u32, 31063, 30920}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s8_u64, 31084, 30920}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_s8_u8, 31105, 30920}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u16_f16, 31143, 31125}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u16_f32, 31165, 31125}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u16_s16, 31187, 31125}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u16_s32, 31209, 31125}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u16_s64, 31231, 31125}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u16_s8, 31253, 31125}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u16_u32, 31274, 31125}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u16_u64, 31296, 31125}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u16_u8, 31318, 31125}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u32_f16, 31357, 31339}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u32_f32, 31379, 31339}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u32_s16, 31401, 31339}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u32_s32, 31423, 31339}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u32_s64, 31445, 31339}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u32_s8, 31467, 31339}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u32_u16, 31488, 31339}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u32_u64, 31510, 31339}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u32_u8, 31532, 31339}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u64_f16, 31571, 31553}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u64_f32, 31593, 31553}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u64_s16, 31615, 31553}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u64_s32, 31637, 31553}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u64_s64, 31659, 31553}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u64_s8, 31681, 31553}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u64_u16, 31702, 31553}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u64_u32, 31724, 31553}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u64_u8, 31746, 31553}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u8_f16, 31784, 31767}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u8_f32, 31805, 31767}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u8_s16, 31826, 31767}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u8_s32, 31847, 31767}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u8_s64, 31868, 31767}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u8_s8, 31889, 31767}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u8_u16, 31909, 31767}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u8_u32, 31930, 31767}, |
| { ARM::BI__builtin_arm_mve_vreinterpretq_u8_u64, 31951, 31767}, |
| { ARM::BI__builtin_arm_mve_vrev16q_m_s8, 31982, 31972}, |
| { ARM::BI__builtin_arm_mve_vrev16q_m_u8, 31995, 31972}, |
| { ARM::BI__builtin_arm_mve_vrev16q_s8, 32016, 32008}, |
| { ARM::BI__builtin_arm_mve_vrev16q_u8, 32027, 32008}, |
| { ARM::BI__builtin_arm_mve_vrev16q_x_s8, 32048, 32038}, |
| { ARM::BI__builtin_arm_mve_vrev16q_x_u8, 32061, 32038}, |
| { ARM::BI__builtin_arm_mve_vrev32q_f16, 32082, 32074}, |
| { ARM::BI__builtin_arm_mve_vrev32q_m_f16, 32104, 32094}, |
| { ARM::BI__builtin_arm_mve_vrev32q_m_s16, 32118, 32094}, |
| { ARM::BI__builtin_arm_mve_vrev32q_m_s8, 32132, 32094}, |
| { ARM::BI__builtin_arm_mve_vrev32q_m_u16, 32145, 32094}, |
| { ARM::BI__builtin_arm_mve_vrev32q_m_u8, 32159, 32094}, |
| { ARM::BI__builtin_arm_mve_vrev32q_s16, 32172, 32074}, |
| { ARM::BI__builtin_arm_mve_vrev32q_s8, 32184, 32074}, |
| { ARM::BI__builtin_arm_mve_vrev32q_u16, 32195, 32074}, |
| { ARM::BI__builtin_arm_mve_vrev32q_u8, 32207, 32074}, |
| { ARM::BI__builtin_arm_mve_vrev32q_x_f16, 32228, 32218}, |
| { ARM::BI__builtin_arm_mve_vrev32q_x_s16, 32242, 32218}, |
| { ARM::BI__builtin_arm_mve_vrev32q_x_s8, 32256, 32218}, |
| { ARM::BI__builtin_arm_mve_vrev32q_x_u16, 32269, 32218}, |
| { ARM::BI__builtin_arm_mve_vrev32q_x_u8, 32283, 32218}, |
| { ARM::BI__builtin_arm_mve_vrev64q_f16, 32304, 32296}, |
| { ARM::BI__builtin_arm_mve_vrev64q_f32, 32316, 32296}, |
| { ARM::BI__builtin_arm_mve_vrev64q_m_f16, 32338, 32328}, |
| { ARM::BI__builtin_arm_mve_vrev64q_m_f32, 32352, 32328}, |
| { ARM::BI__builtin_arm_mve_vrev64q_m_s16, 32366, 32328}, |
| { ARM::BI__builtin_arm_mve_vrev64q_m_s32, 32380, 32328}, |
| { ARM::BI__builtin_arm_mve_vrev64q_m_s8, 32394, 32328}, |
| { ARM::BI__builtin_arm_mve_vrev64q_m_u16, 32407, 32328}, |
| { ARM::BI__builtin_arm_mve_vrev64q_m_u32, 32421, 32328}, |
| { ARM::BI__builtin_arm_mve_vrev64q_m_u8, 32435, 32328}, |
| { ARM::BI__builtin_arm_mve_vrev64q_s16, 32448, 32296}, |
| { ARM::BI__builtin_arm_mve_vrev64q_s32, 32460, 32296}, |
| { ARM::BI__builtin_arm_mve_vrev64q_s8, 32472, 32296}, |
| { ARM::BI__builtin_arm_mve_vrev64q_u16, 32483, 32296}, |
| { ARM::BI__builtin_arm_mve_vrev64q_u32, 32495, 32296}, |
| { ARM::BI__builtin_arm_mve_vrev64q_u8, 32507, 32296}, |
| { ARM::BI__builtin_arm_mve_vrev64q_x_f16, 32528, 32518}, |
| { ARM::BI__builtin_arm_mve_vrev64q_x_f32, 32542, 32518}, |
| { ARM::BI__builtin_arm_mve_vrev64q_x_s16, 32556, 32518}, |
| { ARM::BI__builtin_arm_mve_vrev64q_x_s32, 32570, 32518}, |
| { ARM::BI__builtin_arm_mve_vrev64q_x_s8, 32584, 32518}, |
| { ARM::BI__builtin_arm_mve_vrev64q_x_u16, 32597, 32518}, |
| { ARM::BI__builtin_arm_mve_vrev64q_x_u32, 32611, 32518}, |
| { ARM::BI__builtin_arm_mve_vrev64q_x_u8, 32625, 32518}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_m_s16, 32648, 32638}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_m_s32, 32662, 32638}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_m_s8, 32676, 32638}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_m_u16, 32689, 32638}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_m_u32, 32703, 32638}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_m_u8, 32717, 32638}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_s16, 32738, 32730}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_s32, 32750, 32730}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_s8, 32762, 32730}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_u16, 32773, 32730}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_u32, 32785, 32730}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_u8, 32797, 32730}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_x_s16, 32818, 32808}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_x_s32, 32832, 32808}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_x_s8, 32846, 32808}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_x_u16, 32859, 32808}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_x_u32, 32873, 32808}, |
| { ARM::BI__builtin_arm_mve_vrhaddq_x_u8, 32887, 32808}, |
| { ARM::BI__builtin_arm_mve_vrmlaldavhaq_p_s32, 32915, 32900}, |
| { ARM::BI__builtin_arm_mve_vrmlaldavhaq_p_u32, 32934, 32900}, |
| { ARM::BI__builtin_arm_mve_vrmlaldavhaq_s32, 32966, 32953}, |
| { ARM::BI__builtin_arm_mve_vrmlaldavhaq_u32, 32983, 32953}, |
| { ARM::BI__builtin_arm_mve_vrmlaldavhaxq_p_s32, 33016, 33000}, |
| { ARM::BI__builtin_arm_mve_vrmlaldavhaxq_s32, 33050, 33036}, |
| { ARM::BI__builtin_arm_mve_vrmlaldavhq_p_s32, 33082, 33068}, |
| { ARM::BI__builtin_arm_mve_vrmlaldavhq_p_u32, 33100, 33068}, |
| { ARM::BI__builtin_arm_mve_vrmlaldavhq_s32, 33130, 33118}, |
| { ARM::BI__builtin_arm_mve_vrmlaldavhq_u32, 33146, 33118}, |
| { ARM::BI__builtin_arm_mve_vrmlaldavhxq_p_s32, 33177, 33162}, |
| { ARM::BI__builtin_arm_mve_vrmlaldavhxq_s32, 33209, 33196}, |
| { ARM::BI__builtin_arm_mve_vrmlsldavhaq_p_s32, 33241, 33226}, |
| { ARM::BI__builtin_arm_mve_vrmlsldavhaq_s32, 33273, 33260}, |
| { ARM::BI__builtin_arm_mve_vrmlsldavhaxq_p_s32, 33306, 33290}, |
| { ARM::BI__builtin_arm_mve_vrmlsldavhaxq_s32, 33340, 33326}, |
| { ARM::BI__builtin_arm_mve_vrmlsldavhq_p_s32, 33372, 33358}, |
| { ARM::BI__builtin_arm_mve_vrmlsldavhq_s32, 33402, 33390}, |
| { ARM::BI__builtin_arm_mve_vrmlsldavhxq_p_s32, 33433, 33418}, |
| { ARM::BI__builtin_arm_mve_vrmlsldavhxq_s32, 33465, 33452}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_m_s16, 33492, 33482}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_m_s32, 33506, 33482}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_m_s8, 33520, 33482}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_m_u16, 33533, 33482}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_m_u32, 33547, 33482}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_m_u8, 33561, 33482}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_s16, 33582, 33574}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_s32, 33594, 33574}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_s8, 33606, 33574}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_u16, 33617, 33574}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_u32, 33629, 33574}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_u8, 33641, 33574}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_x_s16, 33662, 33652}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_x_s32, 33676, 33652}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_x_s8, 33690, 33652}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_x_u16, 33703, 33652}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_x_u32, 33717, 33652}, |
| { ARM::BI__builtin_arm_mve_vrmulhq_x_u8, 33731, 33652}, |
| { ARM::BI__builtin_arm_mve_vrndaq_f16, 33751, 33744}, |
| { ARM::BI__builtin_arm_mve_vrndaq_f32, 33762, 33744}, |
| { ARM::BI__builtin_arm_mve_vrndaq_m_f16, 33782, 33773}, |
| { ARM::BI__builtin_arm_mve_vrndaq_m_f32, 33795, 33773}, |
| { ARM::BI__builtin_arm_mve_vrndaq_x_f16, 33817, 33808}, |
| { ARM::BI__builtin_arm_mve_vrndaq_x_f32, 33830, 33808}, |
| { ARM::BI__builtin_arm_mve_vrndmq_f16, 33850, 33843}, |
| { ARM::BI__builtin_arm_mve_vrndmq_f32, 33861, 33843}, |
| { ARM::BI__builtin_arm_mve_vrndmq_m_f16, 33881, 33872}, |
| { ARM::BI__builtin_arm_mve_vrndmq_m_f32, 33894, 33872}, |
| { ARM::BI__builtin_arm_mve_vrndmq_x_f16, 33916, 33907}, |
| { ARM::BI__builtin_arm_mve_vrndmq_x_f32, 33929, 33907}, |
| { ARM::BI__builtin_arm_mve_vrndnq_f16, 33949, 33942}, |
| { ARM::BI__builtin_arm_mve_vrndnq_f32, 33960, 33942}, |
| { ARM::BI__builtin_arm_mve_vrndnq_m_f16, 33980, 33971}, |
| { ARM::BI__builtin_arm_mve_vrndnq_m_f32, 33993, 33971}, |
| { ARM::BI__builtin_arm_mve_vrndnq_x_f16, 34015, 34006}, |
| { ARM::BI__builtin_arm_mve_vrndnq_x_f32, 34028, 34006}, |
| { ARM::BI__builtin_arm_mve_vrndpq_f16, 34048, 34041}, |
| { ARM::BI__builtin_arm_mve_vrndpq_f32, 34059, 34041}, |
| { ARM::BI__builtin_arm_mve_vrndpq_m_f16, 34079, 34070}, |
| { ARM::BI__builtin_arm_mve_vrndpq_m_f32, 34092, 34070}, |
| { ARM::BI__builtin_arm_mve_vrndpq_x_f16, 34114, 34105}, |
| { ARM::BI__builtin_arm_mve_vrndpq_x_f32, 34127, 34105}, |
| { ARM::BI__builtin_arm_mve_vrndq_f16, 34146, 34140}, |
| { ARM::BI__builtin_arm_mve_vrndq_f32, 34156, 34140}, |
| { ARM::BI__builtin_arm_mve_vrndq_m_f16, 34174, 34166}, |
| { ARM::BI__builtin_arm_mve_vrndq_m_f32, 34186, 34166}, |
| { ARM::BI__builtin_arm_mve_vrndq_x_f16, 34206, 34198}, |
| { ARM::BI__builtin_arm_mve_vrndq_x_f32, 34218, 34198}, |
| { ARM::BI__builtin_arm_mve_vrndxq_f16, 34237, 34230}, |
| { ARM::BI__builtin_arm_mve_vrndxq_f32, 34248, 34230}, |
| { ARM::BI__builtin_arm_mve_vrndxq_m_f16, 34268, 34259}, |
| { ARM::BI__builtin_arm_mve_vrndxq_m_f32, 34281, 34259}, |
| { ARM::BI__builtin_arm_mve_vrndxq_x_f16, 34303, 34294}, |
| { ARM::BI__builtin_arm_mve_vrndxq_x_f32, 34316, 34294}, |
| { ARM::BI__builtin_arm_mve_vrshlq_m_n_s16, 34340, 34329}, |
| { ARM::BI__builtin_arm_mve_vrshlq_m_n_s32, 34355, 34329}, |
| { ARM::BI__builtin_arm_mve_vrshlq_m_n_s8, 34370, 34329}, |
| { ARM::BI__builtin_arm_mve_vrshlq_m_n_u16, 34384, 34329}, |
| { ARM::BI__builtin_arm_mve_vrshlq_m_n_u32, 34399, 34329}, |
| { ARM::BI__builtin_arm_mve_vrshlq_m_n_u8, 34414, 34329}, |
| { ARM::BI__builtin_arm_mve_vrshlq_m_s16, 34437, 34428}, |
| { ARM::BI__builtin_arm_mve_vrshlq_m_s32, 34450, 34428}, |
| { ARM::BI__builtin_arm_mve_vrshlq_m_s8, 34463, 34428}, |
| { ARM::BI__builtin_arm_mve_vrshlq_m_u16, 34475, 34428}, |
| { ARM::BI__builtin_arm_mve_vrshlq_m_u32, 34488, 34428}, |
| { ARM::BI__builtin_arm_mve_vrshlq_m_u8, 34501, 34428}, |
| { ARM::BI__builtin_arm_mve_vrshlq_n_s16, 34520, 34513}, |
| { ARM::BI__builtin_arm_mve_vrshlq_n_s32, 34533, 34513}, |
| { ARM::BI__builtin_arm_mve_vrshlq_n_s8, 34546, 34513}, |
| { ARM::BI__builtin_arm_mve_vrshlq_n_u16, 34558, 34513}, |
| { ARM::BI__builtin_arm_mve_vrshlq_n_u32, 34571, 34513}, |
| { ARM::BI__builtin_arm_mve_vrshlq_n_u8, 34584, 34513}, |
| { ARM::BI__builtin_arm_mve_vrshlq_s16, 34596, 34513}, |
| { ARM::BI__builtin_arm_mve_vrshlq_s32, 34607, 34513}, |
| { ARM::BI__builtin_arm_mve_vrshlq_s8, 34618, 34513}, |
| { ARM::BI__builtin_arm_mve_vrshlq_u16, 34628, 34513}, |
| { ARM::BI__builtin_arm_mve_vrshlq_u32, 34639, 34513}, |
| { ARM::BI__builtin_arm_mve_vrshlq_u8, 34650, 34513}, |
| { ARM::BI__builtin_arm_mve_vrshlq_x_s16, 34669, 34660}, |
| { ARM::BI__builtin_arm_mve_vrshlq_x_s32, 34682, 34660}, |
| { ARM::BI__builtin_arm_mve_vrshlq_x_s8, 34695, 34660}, |
| { ARM::BI__builtin_arm_mve_vrshlq_x_u16, 34707, 34660}, |
| { ARM::BI__builtin_arm_mve_vrshlq_x_u32, 34720, 34660}, |
| { ARM::BI__builtin_arm_mve_vrshlq_x_u8, 34733, 34660}, |
| { ARM::BI__builtin_arm_mve_vrshrnbq_m_n_s16, 34756, 34745}, |
| { ARM::BI__builtin_arm_mve_vrshrnbq_m_n_s32, 34773, 34745}, |
| { ARM::BI__builtin_arm_mve_vrshrnbq_m_n_u16, 34790, 34745}, |
| { ARM::BI__builtin_arm_mve_vrshrnbq_m_n_u32, 34807, 34745}, |
| { ARM::BI__builtin_arm_mve_vrshrnbq_n_s16, 34833, 34824}, |
| { ARM::BI__builtin_arm_mve_vrshrnbq_n_s32, 34848, 34824}, |
| { ARM::BI__builtin_arm_mve_vrshrnbq_n_u16, 34863, 34824}, |
| { ARM::BI__builtin_arm_mve_vrshrnbq_n_u32, 34878, 34824}, |
| { ARM::BI__builtin_arm_mve_vrshrntq_m_n_s16, 34904, 34893}, |
| { ARM::BI__builtin_arm_mve_vrshrntq_m_n_s32, 34921, 34893}, |
| { ARM::BI__builtin_arm_mve_vrshrntq_m_n_u16, 34938, 34893}, |
| { ARM::BI__builtin_arm_mve_vrshrntq_m_n_u32, 34955, 34893}, |
| { ARM::BI__builtin_arm_mve_vrshrntq_n_s16, 34981, 34972}, |
| { ARM::BI__builtin_arm_mve_vrshrntq_n_s32, 34996, 34972}, |
| { ARM::BI__builtin_arm_mve_vrshrntq_n_u16, 35011, 34972}, |
| { ARM::BI__builtin_arm_mve_vrshrntq_n_u32, 35026, 34972}, |
| { ARM::BI__builtin_arm_mve_vrshrq_m_n_s16, 35050, 35041}, |
| { ARM::BI__builtin_arm_mve_vrshrq_m_n_s32, 35065, 35041}, |
| { ARM::BI__builtin_arm_mve_vrshrq_m_n_s8, 35080, 35041}, |
| { ARM::BI__builtin_arm_mve_vrshrq_m_n_u16, 35094, 35041}, |
| { ARM::BI__builtin_arm_mve_vrshrq_m_n_u32, 35109, 35041}, |
| { ARM::BI__builtin_arm_mve_vrshrq_m_n_u8, 35124, 35041}, |
| { ARM::BI__builtin_arm_mve_vrshrq_n_s16, 35145, 35138}, |
| { ARM::BI__builtin_arm_mve_vrshrq_n_s32, 35158, 35138}, |
| { ARM::BI__builtin_arm_mve_vrshrq_n_s8, 35171, 35138}, |
| { ARM::BI__builtin_arm_mve_vrshrq_n_u16, 35183, 35138}, |
| { ARM::BI__builtin_arm_mve_vrshrq_n_u32, 35196, 35138}, |
| { ARM::BI__builtin_arm_mve_vrshrq_n_u8, 35209, 35138}, |
| { ARM::BI__builtin_arm_mve_vrshrq_x_n_s16, 35230, 35221}, |
| { ARM::BI__builtin_arm_mve_vrshrq_x_n_s32, 35245, 35221}, |
| { ARM::BI__builtin_arm_mve_vrshrq_x_n_s8, 35260, 35221}, |
| { ARM::BI__builtin_arm_mve_vrshrq_x_n_u16, 35274, 35221}, |
| { ARM::BI__builtin_arm_mve_vrshrq_x_n_u32, 35289, 35221}, |
| { ARM::BI__builtin_arm_mve_vrshrq_x_n_u8, 35304, 35221}, |
| { ARM::BI__builtin_arm_mve_vsbciq_m_s32, 35327, 35318}, |
| { ARM::BI__builtin_arm_mve_vsbciq_m_u32, 35340, 35318}, |
| { ARM::BI__builtin_arm_mve_vsbciq_s32, 35360, 35353}, |
| { ARM::BI__builtin_arm_mve_vsbciq_u32, 35371, 35353}, |
| { ARM::BI__builtin_arm_mve_vsbcq_m_s32, 35390, 35382}, |
| { ARM::BI__builtin_arm_mve_vsbcq_m_u32, 35402, 35382}, |
| { ARM::BI__builtin_arm_mve_vsbcq_s32, 35420, 35414}, |
| { ARM::BI__builtin_arm_mve_vsbcq_u32, 35430, 35414}, |
| { ARM::BI__builtin_arm_mve_vsetq_lane_f16, 35451, 35440}, |
| { ARM::BI__builtin_arm_mve_vsetq_lane_f32, 35466, 35440}, |
| { ARM::BI__builtin_arm_mve_vsetq_lane_s16, 35481, 35440}, |
| { ARM::BI__builtin_arm_mve_vsetq_lane_s32, 35496, 35440}, |
| { ARM::BI__builtin_arm_mve_vsetq_lane_s64, 35511, 35440}, |
| { ARM::BI__builtin_arm_mve_vsetq_lane_s8, 35526, 35440}, |
| { ARM::BI__builtin_arm_mve_vsetq_lane_u16, 35540, 35440}, |
| { ARM::BI__builtin_arm_mve_vsetq_lane_u32, 35555, 35440}, |
| { ARM::BI__builtin_arm_mve_vsetq_lane_u64, 35570, 35440}, |
| { ARM::BI__builtin_arm_mve_vsetq_lane_u8, 35585, 35440}, |
| { ARM::BI__builtin_arm_mve_vshlcq_m_s16, 35608, 35599}, |
| { ARM::BI__builtin_arm_mve_vshlcq_m_s32, 35621, 35599}, |
| { ARM::BI__builtin_arm_mve_vshlcq_m_s8, 35634, 35599}, |
| { ARM::BI__builtin_arm_mve_vshlcq_m_u16, 35646, 35599}, |
| { ARM::BI__builtin_arm_mve_vshlcq_m_u32, 35659, 35599}, |
| { ARM::BI__builtin_arm_mve_vshlcq_m_u8, 35672, 35599}, |
| { ARM::BI__builtin_arm_mve_vshlcq_s16, 35691, 35684}, |
| { ARM::BI__builtin_arm_mve_vshlcq_s32, 35702, 35684}, |
| { ARM::BI__builtin_arm_mve_vshlcq_s8, 35713, 35684}, |
| { ARM::BI__builtin_arm_mve_vshlcq_u16, 35723, 35684}, |
| { ARM::BI__builtin_arm_mve_vshlcq_u32, 35734, 35684}, |
| { ARM::BI__builtin_arm_mve_vshlcq_u8, 35745, 35684}, |
| { ARM::BI__builtin_arm_mve_vshllbq_m_n_s16, 35765, 35755}, |
| { ARM::BI__builtin_arm_mve_vshllbq_m_n_s8, 35781, 35755}, |
| { ARM::BI__builtin_arm_mve_vshllbq_m_n_u16, 35796, 35755}, |
| { ARM::BI__builtin_arm_mve_vshllbq_m_n_u8, 35812, 35755}, |
| { ARM::BI__builtin_arm_mve_vshllbq_n_s16, 35835, 35827}, |
| { ARM::BI__builtin_arm_mve_vshllbq_n_s8, 35849, 35827}, |
| { ARM::BI__builtin_arm_mve_vshllbq_n_u16, 35862, 35827}, |
| { ARM::BI__builtin_arm_mve_vshllbq_n_u8, 35876, 35827}, |
| { ARM::BI__builtin_arm_mve_vshllbq_x_n_s16, 35899, 35889}, |
| { ARM::BI__builtin_arm_mve_vshllbq_x_n_s8, 35915, 35889}, |
| { ARM::BI__builtin_arm_mve_vshllbq_x_n_u16, 35930, 35889}, |
| { ARM::BI__builtin_arm_mve_vshllbq_x_n_u8, 35946, 35889}, |
| { ARM::BI__builtin_arm_mve_vshlltq_m_n_s16, 35971, 35961}, |
| { ARM::BI__builtin_arm_mve_vshlltq_m_n_s8, 35987, 35961}, |
| { ARM::BI__builtin_arm_mve_vshlltq_m_n_u16, 36002, 35961}, |
| { ARM::BI__builtin_arm_mve_vshlltq_m_n_u8, 36018, 35961}, |
| { ARM::BI__builtin_arm_mve_vshlltq_n_s16, 36041, 36033}, |
| { ARM::BI__builtin_arm_mve_vshlltq_n_s8, 36055, 36033}, |
| { ARM::BI__builtin_arm_mve_vshlltq_n_u16, 36068, 36033}, |
| { ARM::BI__builtin_arm_mve_vshlltq_n_u8, 36082, 36033}, |
| { ARM::BI__builtin_arm_mve_vshlltq_x_n_s16, 36105, 36095}, |
| { ARM::BI__builtin_arm_mve_vshlltq_x_n_s8, 36121, 36095}, |
| { ARM::BI__builtin_arm_mve_vshlltq_x_n_u16, 36136, 36095}, |
| { ARM::BI__builtin_arm_mve_vshlltq_x_n_u8, 36152, 36095}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_n_s16, 36177, 36167}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_n_s32, 36191, 36167}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_n_s8, 36205, 36167}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_n_u16, 36218, 36167}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_n_u32, 36232, 36167}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_n_u8, 36246, 36167}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_r_s16, 36269, 36259}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_r_s32, 36283, 36259}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_r_s8, 36297, 36259}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_r_u16, 36310, 36259}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_r_u32, 36324, 36259}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_r_u8, 36338, 36259}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_s16, 36359, 36351}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_s32, 36371, 36351}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_s8, 36383, 36351}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_u16, 36394, 36351}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_u32, 36406, 36351}, |
| { ARM::BI__builtin_arm_mve_vshlq_m_u8, 36418, 36351}, |
| { ARM::BI__builtin_arm_mve_vshlq_n_s16, 36437, 36429}, |
| { ARM::BI__builtin_arm_mve_vshlq_n_s32, 36449, 36429}, |
| { ARM::BI__builtin_arm_mve_vshlq_n_s8, 36461, 36429}, |
| { ARM::BI__builtin_arm_mve_vshlq_n_u16, 36472, 36429}, |
| { ARM::BI__builtin_arm_mve_vshlq_n_u32, 36484, 36429}, |
| { ARM::BI__builtin_arm_mve_vshlq_n_u8, 36496, 36429}, |
| { ARM::BI__builtin_arm_mve_vshlq_r_s16, 36515, 36507}, |
| { ARM::BI__builtin_arm_mve_vshlq_r_s32, 36527, 36507}, |
| { ARM::BI__builtin_arm_mve_vshlq_r_s8, 36539, 36507}, |
| { ARM::BI__builtin_arm_mve_vshlq_r_u16, 36550, 36507}, |
| { ARM::BI__builtin_arm_mve_vshlq_r_u32, 36562, 36507}, |
| { ARM::BI__builtin_arm_mve_vshlq_r_u8, 36574, 36507}, |
| { ARM::BI__builtin_arm_mve_vshlq_s16, 36591, 36585}, |
| { ARM::BI__builtin_arm_mve_vshlq_s32, 36601, 36585}, |
| { ARM::BI__builtin_arm_mve_vshlq_s8, 36611, 36585}, |
| { ARM::BI__builtin_arm_mve_vshlq_u16, 36620, 36585}, |
| { ARM::BI__builtin_arm_mve_vshlq_u32, 36630, 36585}, |
| { ARM::BI__builtin_arm_mve_vshlq_u8, 36640, 36585}, |
| { ARM::BI__builtin_arm_mve_vshlq_x_n_s16, 36659, 36649}, |
| { ARM::BI__builtin_arm_mve_vshlq_x_n_s32, 36673, 36649}, |
| { ARM::BI__builtin_arm_mve_vshlq_x_n_s8, 36687, 36649}, |
| { ARM::BI__builtin_arm_mve_vshlq_x_n_u16, 36700, 36649}, |
| { ARM::BI__builtin_arm_mve_vshlq_x_n_u32, 36714, 36649}, |
| { ARM::BI__builtin_arm_mve_vshlq_x_n_u8, 36728, 36649}, |
| { ARM::BI__builtin_arm_mve_vshlq_x_s16, 36749, 36741}, |
| { ARM::BI__builtin_arm_mve_vshlq_x_s32, 36761, 36741}, |
| { ARM::BI__builtin_arm_mve_vshlq_x_s8, 36773, 36741}, |
| { ARM::BI__builtin_arm_mve_vshlq_x_u16, 36784, 36741}, |
| { ARM::BI__builtin_arm_mve_vshlq_x_u32, 36796, 36741}, |
| { ARM::BI__builtin_arm_mve_vshlq_x_u8, 36808, 36741}, |
| { ARM::BI__builtin_arm_mve_vshrnbq_m_n_s16, 36829, 36819}, |
| { ARM::BI__builtin_arm_mve_vshrnbq_m_n_s32, 36845, 36819}, |
| { ARM::BI__builtin_arm_mve_vshrnbq_m_n_u16, 36861, 36819}, |
| { ARM::BI__builtin_arm_mve_vshrnbq_m_n_u32, 36877, 36819}, |
| { ARM::BI__builtin_arm_mve_vshrnbq_n_s16, 36901, 36893}, |
| { ARM::BI__builtin_arm_mve_vshrnbq_n_s32, 36915, 36893}, |
| { ARM::BI__builtin_arm_mve_vshrnbq_n_u16, 36929, 36893}, |
| { ARM::BI__builtin_arm_mve_vshrnbq_n_u32, 36943, 36893}, |
| { ARM::BI__builtin_arm_mve_vshrntq_m_n_s16, 36967, 36957}, |
| { ARM::BI__builtin_arm_mve_vshrntq_m_n_s32, 36983, 36957}, |
| { ARM::BI__builtin_arm_mve_vshrntq_m_n_u16, 36999, 36957}, |
| { ARM::BI__builtin_arm_mve_vshrntq_m_n_u32, 37015, 36957}, |
| { ARM::BI__builtin_arm_mve_vshrntq_n_s16, 37039, 37031}, |
| { ARM::BI__builtin_arm_mve_vshrntq_n_s32, 37053, 37031}, |
| { ARM::BI__builtin_arm_mve_vshrntq_n_u16, 37067, 37031}, |
| { ARM::BI__builtin_arm_mve_vshrntq_n_u32, 37081, 37031}, |
| { ARM::BI__builtin_arm_mve_vshrq_m_n_s16, 37103, 37095}, |
| { ARM::BI__builtin_arm_mve_vshrq_m_n_s32, 37117, 37095}, |
| { ARM::BI__builtin_arm_mve_vshrq_m_n_s8, 37131, 37095}, |
| { ARM::BI__builtin_arm_mve_vshrq_m_n_u16, 37144, 37095}, |
| { ARM::BI__builtin_arm_mve_vshrq_m_n_u32, 37158, 37095}, |
| { ARM::BI__builtin_arm_mve_vshrq_m_n_u8, 37172, 37095}, |
| { ARM::BI__builtin_arm_mve_vshrq_n_s16, 37191, 37185}, |
| { ARM::BI__builtin_arm_mve_vshrq_n_s32, 37203, 37185}, |
| { ARM::BI__builtin_arm_mve_vshrq_n_s8, 37215, 37185}, |
| { ARM::BI__builtin_arm_mve_vshrq_n_u16, 37226, 37185}, |
| { ARM::BI__builtin_arm_mve_vshrq_n_u32, 37238, 37185}, |
| { ARM::BI__builtin_arm_mve_vshrq_n_u8, 37250, 37185}, |
| { ARM::BI__builtin_arm_mve_vshrq_x_n_s16, 37269, 37261}, |
| { ARM::BI__builtin_arm_mve_vshrq_x_n_s32, 37283, 37261}, |
| { ARM::BI__builtin_arm_mve_vshrq_x_n_s8, 37297, 37261}, |
| { ARM::BI__builtin_arm_mve_vshrq_x_n_u16, 37310, 37261}, |
| { ARM::BI__builtin_arm_mve_vshrq_x_n_u32, 37324, 37261}, |
| { ARM::BI__builtin_arm_mve_vshrq_x_n_u8, 37338, 37261}, |
| { ARM::BI__builtin_arm_mve_vsliq_m_n_s16, 37359, 37351}, |
| { ARM::BI__builtin_arm_mve_vsliq_m_n_s32, 37373, 37351}, |
| { ARM::BI__builtin_arm_mve_vsliq_m_n_s8, 37387, 37351}, |
| { ARM::BI__builtin_arm_mve_vsliq_m_n_u16, 37400, 37351}, |
| { ARM::BI__builtin_arm_mve_vsliq_m_n_u32, 37414, 37351}, |
| { ARM::BI__builtin_arm_mve_vsliq_m_n_u8, 37428, 37351}, |
| { ARM::BI__builtin_arm_mve_vsliq_n_s16, 37447, 37441}, |
| { ARM::BI__builtin_arm_mve_vsliq_n_s32, 37459, 37441}, |
| { ARM::BI__builtin_arm_mve_vsliq_n_s8, 37471, 37441}, |
| { ARM::BI__builtin_arm_mve_vsliq_n_u16, 37482, 37441}, |
| { ARM::BI__builtin_arm_mve_vsliq_n_u32, 37494, 37441}, |
| { ARM::BI__builtin_arm_mve_vsliq_n_u8, 37506, 37441}, |
| { ARM::BI__builtin_arm_mve_vsriq_m_n_s16, 37525, 37517}, |
| { ARM::BI__builtin_arm_mve_vsriq_m_n_s32, 37539, 37517}, |
| { ARM::BI__builtin_arm_mve_vsriq_m_n_s8, 37553, 37517}, |
| { ARM::BI__builtin_arm_mve_vsriq_m_n_u16, 37566, 37517}, |
| { ARM::BI__builtin_arm_mve_vsriq_m_n_u32, 37580, 37517}, |
| { ARM::BI__builtin_arm_mve_vsriq_m_n_u8, 37594, 37517}, |
| { ARM::BI__builtin_arm_mve_vsriq_n_s16, 37613, 37607}, |
| { ARM::BI__builtin_arm_mve_vsriq_n_s32, 37625, 37607}, |
| { ARM::BI__builtin_arm_mve_vsriq_n_s8, 37637, 37607}, |
| { ARM::BI__builtin_arm_mve_vsriq_n_u16, 37648, 37607}, |
| { ARM::BI__builtin_arm_mve_vsriq_n_u32, 37660, 37607}, |
| { ARM::BI__builtin_arm_mve_vsriq_n_u8, 37672, 37607}, |
| { ARM::BI__builtin_arm_mve_vst1q_f16, 37689, 37683}, |
| { ARM::BI__builtin_arm_mve_vst1q_f32, 37699, 37683}, |
| { ARM::BI__builtin_arm_mve_vst1q_p_f16, 37717, 37709}, |
| { ARM::BI__builtin_arm_mve_vst1q_p_f32, 37729, 37709}, |
| { ARM::BI__builtin_arm_mve_vst1q_p_s16, 37741, 37709}, |
| { ARM::BI__builtin_arm_mve_vst1q_p_s32, 37753, 37709}, |
| { ARM::BI__builtin_arm_mve_vst1q_p_s8, 37765, 37709}, |
| { ARM::BI__builtin_arm_mve_vst1q_p_u16, 37776, 37709}, |
| { ARM::BI__builtin_arm_mve_vst1q_p_u32, 37788, 37709}, |
| { ARM::BI__builtin_arm_mve_vst1q_p_u8, 37800, 37709}, |
| { ARM::BI__builtin_arm_mve_vst1q_s16, 37811, 37683}, |
| { ARM::BI__builtin_arm_mve_vst1q_s32, 37821, 37683}, |
| { ARM::BI__builtin_arm_mve_vst1q_s8, 37831, 37683}, |
| { ARM::BI__builtin_arm_mve_vst1q_u16, 37840, 37683}, |
| { ARM::BI__builtin_arm_mve_vst1q_u32, 37850, 37683}, |
| { ARM::BI__builtin_arm_mve_vst1q_u8, 37860, 37683}, |
| { ARM::BI__builtin_arm_mve_vst2q_f16, 37875, 37869}, |
| { ARM::BI__builtin_arm_mve_vst2q_f32, 37885, 37869}, |
| { ARM::BI__builtin_arm_mve_vst2q_s16, 37895, 37869}, |
| { ARM::BI__builtin_arm_mve_vst2q_s32, 37905, 37869}, |
| { ARM::BI__builtin_arm_mve_vst2q_s8, 37915, 37869}, |
| { ARM::BI__builtin_arm_mve_vst2q_u16, 37924, 37869}, |
| { ARM::BI__builtin_arm_mve_vst2q_u32, 37934, 37869}, |
| { ARM::BI__builtin_arm_mve_vst2q_u8, 37944, 37869}, |
| { ARM::BI__builtin_arm_mve_vst4q_f16, 37959, 37953}, |
| { ARM::BI__builtin_arm_mve_vst4q_f32, 37969, 37953}, |
| { ARM::BI__builtin_arm_mve_vst4q_s16, 37979, 37953}, |
| { ARM::BI__builtin_arm_mve_vst4q_s32, 37989, 37953}, |
| { ARM::BI__builtin_arm_mve_vst4q_s8, 37999, 37953}, |
| { ARM::BI__builtin_arm_mve_vst4q_u16, 38008, 37953}, |
| { ARM::BI__builtin_arm_mve_vst4q_u32, 38018, 37953}, |
| { ARM::BI__builtin_arm_mve_vst4q_u8, 38028, 37953}, |
| { ARM::BI__builtin_arm_mve_vstrbq_p_s16, 38046, 38037}, |
| { ARM::BI__builtin_arm_mve_vstrbq_p_s32, 38059, 38037}, |
| { ARM::BI__builtin_arm_mve_vstrbq_p_s8, 38072, 38037}, |
| { ARM::BI__builtin_arm_mve_vstrbq_p_u16, 38084, 38037}, |
| { ARM::BI__builtin_arm_mve_vstrbq_p_u32, 38097, 38037}, |
| { ARM::BI__builtin_arm_mve_vstrbq_p_u8, 38110, 38037}, |
| { ARM::BI__builtin_arm_mve_vstrbq_s16, 38129, 38122}, |
| { ARM::BI__builtin_arm_mve_vstrbq_s32, 38140, 38122}, |
| { ARM::BI__builtin_arm_mve_vstrbq_s8, 38151, 38122}, |
| { ARM::BI__builtin_arm_mve_vstrbq_scatter_offset_p_s16, 38185, 38161}, |
| { ARM::BI__builtin_arm_mve_vstrbq_scatter_offset_p_s32, 38213, 38161}, |
| { ARM::BI__builtin_arm_mve_vstrbq_scatter_offset_p_s8, 38241, 38161}, |
| { ARM::BI__builtin_arm_mve_vstrbq_scatter_offset_p_u16, 38268, 38161}, |
| { ARM::BI__builtin_arm_mve_vstrbq_scatter_offset_p_u32, 38296, 38161}, |
| { ARM::BI__builtin_arm_mve_vstrbq_scatter_offset_p_u8, 38324, 38161}, |
| { ARM::BI__builtin_arm_mve_vstrbq_scatter_offset_s16, 38373, 38351}, |
| { ARM::BI__builtin_arm_mve_vstrbq_scatter_offset_s32, 38399, 38351}, |
| { ARM::BI__builtin_arm_mve_vstrbq_scatter_offset_s8, 38425, 38351}, |
| { ARM::BI__builtin_arm_mve_vstrbq_scatter_offset_u16, 38450, 38351}, |
| { ARM::BI__builtin_arm_mve_vstrbq_scatter_offset_u32, 38476, 38351}, |
| { ARM::BI__builtin_arm_mve_vstrbq_scatter_offset_u8, 38502, 38351}, |
| { ARM::BI__builtin_arm_mve_vstrbq_u16, 38527, 38122}, |
| { ARM::BI__builtin_arm_mve_vstrbq_u32, 38538, 38122}, |
| { ARM::BI__builtin_arm_mve_vstrbq_u8, 38549, 38122}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_base_p_s64, 38581, 38559}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_base_p_u64, 38607, 38559}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_base_s64, 38653, 38633}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_base_u64, 38677, 38633}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_base_wb_p_s64, 38726, 38701}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_base_wb_p_u64, 38755, 38701}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_base_wb_s64, 38807, 38784}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_base_wb_u64, 38834, 38784}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_offset_p_s64, 38885, 38861}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_offset_p_u64, 38913, 38861}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_offset_s64, 38963, 38941}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_offset_u64, 38989, 38941}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_shifted_offset_p_s64, 39047, 39015}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_shifted_offset_p_u64, 39083, 39015}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_shifted_offset_s64, 39149, 39119}, |
| { ARM::BI__builtin_arm_mve_vstrdq_scatter_shifted_offset_u64, 39183, 39119}, |
| { ARM::BI__builtin_arm_mve_vstrhq_f16, 39224, 39217}, |
| { ARM::BI__builtin_arm_mve_vstrhq_p_f16, 39244, 39235}, |
| { ARM::BI__builtin_arm_mve_vstrhq_p_s16, 39257, 39235}, |
| { ARM::BI__builtin_arm_mve_vstrhq_p_s32, 39270, 39235}, |
| { ARM::BI__builtin_arm_mve_vstrhq_p_u16, 39283, 39235}, |
| { ARM::BI__builtin_arm_mve_vstrhq_p_u32, 39296, 39235}, |
| { ARM::BI__builtin_arm_mve_vstrhq_s16, 39309, 39217}, |
| { ARM::BI__builtin_arm_mve_vstrhq_s32, 39320, 39217}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_offset_f16, 39353, 39331}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_offset_p_f16, 39403, 39379}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_offset_p_s16, 39431, 39379}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_offset_p_s32, 39459, 39379}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_offset_p_u16, 39487, 39379}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_offset_p_u32, 39515, 39379}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_offset_s16, 39543, 39331}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_offset_s32, 39569, 39331}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_offset_u16, 39595, 39331}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_offset_u32, 39621, 39331}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_shifted_offset_f16, 39677, 39647}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_shifted_offset_p_f16, 39743, 39711}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_shifted_offset_p_s16, 39779, 39711}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_shifted_offset_p_s32, 39815, 39711}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_shifted_offset_p_u16, 39851, 39711}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_shifted_offset_p_u32, 39887, 39711}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_shifted_offset_s16, 39923, 39647}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_shifted_offset_s32, 39957, 39647}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_shifted_offset_u16, 39991, 39647}, |
| { ARM::BI__builtin_arm_mve_vstrhq_scatter_shifted_offset_u32, 40025, 39647}, |
| { ARM::BI__builtin_arm_mve_vstrhq_u16, 40059, 39217}, |
| { ARM::BI__builtin_arm_mve_vstrhq_u32, 40070, 39217}, |
| { ARM::BI__builtin_arm_mve_vstrwq_f32, 40088, 40081}, |
| { ARM::BI__builtin_arm_mve_vstrwq_p_f32, 40108, 40099}, |
| { ARM::BI__builtin_arm_mve_vstrwq_p_s32, 40121, 40099}, |
| { ARM::BI__builtin_arm_mve_vstrwq_p_u32, 40134, 40099}, |
| { ARM::BI__builtin_arm_mve_vstrwq_s32, 40147, 40081}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_base_f32, 40178, 40158}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_base_p_f32, 40224, 40202}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_base_p_s32, 40250, 40202}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_base_p_u32, 40276, 40202}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_base_s32, 40302, 40158}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_base_u32, 40326, 40158}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_f32, 40373, 40350}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_p_f32, 40425, 40400}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_p_s32, 40454, 40400}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_p_u32, 40483, 40400}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_s32, 40512, 40350}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_u32, 40539, 40350}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_offset_f32, 40588, 40566}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_offset_p_f32, 40638, 40614}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_offset_p_s32, 40666, 40614}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_offset_p_u32, 40694, 40614}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_offset_s32, 40722, 40566}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_offset_u32, 40748, 40566}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_shifted_offset_f32, 40804, 40774}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_shifted_offset_p_f32, 40870, 40838}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_shifted_offset_p_s32, 40906, 40838}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_shifted_offset_p_u32, 40942, 40838}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_shifted_offset_s32, 40978, 40774}, |
| { ARM::BI__builtin_arm_mve_vstrwq_scatter_shifted_offset_u32, 41012, 40774}, |
| { ARM::BI__builtin_arm_mve_vstrwq_u32, 41046, 40081}, |
| { ARM::BI__builtin_arm_mve_vsubq_f16, 41063, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_f32, 41073, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_f16, 41091, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_f32, 41103, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_n_f16, 41115, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_n_f32, 41129, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_n_s16, 41143, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_n_s32, 41157, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_n_s8, 41171, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_n_u16, 41184, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_n_u32, 41198, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_n_u8, 41212, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_s16, 41225, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_s32, 41237, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_s8, 41249, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_u16, 41260, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_u32, 41272, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_m_u8, 41284, 41083}, |
| { ARM::BI__builtin_arm_mve_vsubq_n_f16, 41295, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_n_f32, 41307, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_n_s16, 41319, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_n_s32, 41331, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_n_s8, 41343, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_n_u16, 41354, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_n_u32, 41366, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_n_u8, 41378, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_s16, 41389, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_s32, 41399, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_s8, 41409, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_u16, 41418, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_u32, 41428, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_u8, 41438, 41057}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_f16, 41455, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_f32, 41467, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_n_f16, 41479, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_n_f32, 41493, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_n_s16, 41507, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_n_s32, 41521, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_n_s8, 41535, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_n_u16, 41548, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_n_u32, 41562, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_n_u8, 41576, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_s16, 41589, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_s32, 41601, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_s8, 41613, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_u16, 41624, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_u32, 41636, 41447}, |
| { ARM::BI__builtin_arm_mve_vsubq_x_u8, 41648, 41447}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_f16, 41659, -1}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_f32, 41679, -1}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_polymorphic_f16, 41715, 41699}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_polymorphic_f32, 41747, 41699}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_polymorphic_s16, 41779, 41699}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_polymorphic_s32, 41811, 41699}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_polymorphic_s64, 41843, 41699}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_polymorphic_s8, 41875, 41699}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_polymorphic_u16, 41906, 41699}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_polymorphic_u32, 41938, 41699}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_polymorphic_u64, 41970, 41699}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_polymorphic_u8, 42002, 41699}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_s16, 42033, -1}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_s32, 42053, -1}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_s64, 42073, -1}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_s8, 42093, -1}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_u16, 42112, -1}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_u32, 42132, -1}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_u64, 42152, -1}, |
| { ARM::BI__builtin_arm_mve_vuninitializedq_u8, 42172, -1}, |
| }; |
| |
| ArrayRef<IntrinToName> Map(MapData); |
| |
| static const char IntrinNames[] = { |
| "asrl\000lsll\000sqrshr\000sqrshrl\000sqrshrl_sat48\000sqshl\000sqshll\000" |
| "srshr\000srshrl\000uqrshl\000uqrshll\000uqrshll_sat48\000uqshl\000uqshl" |
| "l\000urshr\000urshrl\000vabavq_p\000vabavq_p_s16\000vabavq_p_s32\000vab" |
| "avq_p_s8\000vabavq_p_u16\000vabavq_p_u32\000vabavq_p_u8\000vabavq\000va" |
| "bavq_s16\000vabavq_s32\000vabavq_s8\000vabavq_u16\000vabavq_u32\000vaba" |
| "vq_u8\000vabdq\000vabdq_f16\000vabdq_f32\000vabdq_m\000vabdq_m_f16\000v" |
| "abdq_m_f32\000vabdq_m_s16\000vabdq_m_s32\000vabdq_m_s8\000vabdq_m_u16\000" |
| "vabdq_m_u32\000vabdq_m_u8\000vabdq_s16\000vabdq_s32\000vabdq_s8\000vabd" |
| "q_u16\000vabdq_u32\000vabdq_u8\000vabdq_x\000vabdq_x_f16\000vabdq_x_f32" |
| "\000vabdq_x_s16\000vabdq_x_s32\000vabdq_x_s8\000vabdq_x_u16\000vabdq_x_" |
| "u32\000vabdq_x_u8\000vabsq\000vabsq_f16\000vabsq_f32\000vabsq_m\000vabs" |
| "q_m_f16\000vabsq_m_f32\000vabsq_m_s16\000vabsq_m_s32\000vabsq_m_s8\000v" |
| "absq_s16\000vabsq_s32\000vabsq_s8\000vabsq_x\000vabsq_x_f16\000vabsq_x_" |
| "f32\000vabsq_x_s16\000vabsq_x_s32\000vabsq_x_s8\000vadciq_m\000vadciq_m" |
| "_s32\000vadciq_m_u32\000vadciq\000vadciq_s32\000vadciq_u32\000vadcq_m\000" |
| "vadcq_m_s32\000vadcq_m_u32\000vadcq\000vadcq_s32\000vadcq_u32\000vaddlv" |
| "aq_p\000vaddlvaq_p_s32\000vaddlvaq_p_u32\000vaddlvaq\000vaddlvaq_s32\000" |
| "vaddlvaq_u32\000vaddlvq_p\000vaddlvq_p_s32\000vaddlvq_p_u32\000vaddlvq\000" |
| "vaddlvq_s32\000vaddlvq_u32\000vaddq\000vaddq_f16\000vaddq_f32\000vaddq_" |
| "m\000vaddq_m_f16\000vaddq_m_f32\000vaddq_m_n_f16\000vaddq_m_n_f32\000va" |
| "ddq_m_n_s16\000vaddq_m_n_s32\000vaddq_m_n_s8\000vaddq_m_n_u16\000vaddq_" |
| "m_n_u32\000vaddq_m_n_u8\000vaddq_m_s16\000vaddq_m_s32\000vaddq_m_s8\000" |
| "vaddq_m_u16\000vaddq_m_u32\000vaddq_m_u8\000vaddq_n_f16\000vaddq_n_f32\000" |
| "vaddq_n_s16\000vaddq_n_s32\000vaddq_n_s8\000vaddq_n_u16\000vaddq_n_u32\000" |
| "vaddq_n_u8\000vaddq_s16\000vaddq_s32\000vaddq_s8\000vaddq_u16\000vaddq_" |
| "u32\000vaddq_u8\000vaddq_x\000vaddq_x_f16\000vaddq_x_f32\000vaddq_x_n_f" |
| "16\000vaddq_x_n_f32\000vaddq_x_n_s16\000vaddq_x_n_s32\000vaddq_x_n_s8\000" |
| "vaddq_x_n_u16\000vaddq_x_n_u32\000vaddq_x_n_u8\000vaddq_x_s16\000vaddq_" |
| "x_s32\000vaddq_x_s8\000vaddq_x_u16\000vaddq_x_u32\000vaddq_x_u8\000vadd" |
| "vaq_p\000vaddvaq_p_s16\000vaddvaq_p_s32\000vaddvaq_p_s8\000vaddvaq_p_u1" |
| "6\000vaddvaq_p_u32\000vaddvaq_p_u8\000vaddvaq\000vaddvaq_s16\000vaddvaq" |
| "_s32\000vaddvaq_s8\000vaddvaq_u16\000vaddvaq_u32\000vaddvaq_u8\000vaddv" |
| "q_p\000vaddvq_p_s16\000vaddvq_p_s32\000vaddvq_p_s8\000vaddvq_p_u16\000v" |
| "addvq_p_u32\000vaddvq_p_u8\000vaddvq\000vaddvq_s16\000vaddvq_s32\000vad" |
| "dvq_s8\000vaddvq_u16\000vaddvq_u32\000vaddvq_u8\000vandq\000vandq_f16\000" |
| "vandq_f32\000vandq_m\000vandq_m_f16\000vandq_m_f32\000vandq_m_s16\000va" |
| "ndq_m_s32\000vandq_m_s8\000vandq_m_u16\000vandq_m_u32\000vandq_m_u8\000" |
| "vandq_s16\000vandq_s32\000vandq_s8\000vandq_u16\000vandq_u32\000vandq_u" |
| "8\000vandq_x\000vandq_x_f16\000vandq_x_f32\000vandq_x_s16\000vandq_x_s3" |
| "2\000vandq_x_s8\000vandq_x_u16\000vandq_x_u32\000vandq_x_u8\000vbicq\000" |
| "vbicq_f16\000vbicq_f32\000vbicq_m\000vbicq_m_f16\000vbicq_m_f32\000vbic" |
| "q_m_n\000vbicq_m_n_s16\000vbicq_m_n_s32\000vbicq_m_n_u16\000vbicq_m_n_u" |
| "32\000vbicq_m_s16\000vbicq_m_s32\000vbicq_m_s8\000vbicq_m_u16\000vbicq_" |
| "m_u32\000vbicq_m_u8\000vbicq_n_s16\000vbicq_n_s32\000vbicq_n_u16\000vbi" |
| "cq_n_u32\000vbicq_s16\000vbicq_s32\000vbicq_s8\000vbicq_u16\000vbicq_u3" |
| "2\000vbicq_u8\000vbicq_x\000vbicq_x_f16\000vbicq_x_f32\000vbicq_x_s16\000" |
| "vbicq_x_s32\000vbicq_x_s8\000vbicq_x_u16\000vbicq_x_u32\000vbicq_x_u8\000" |
| "vbrsrq_m\000vbrsrq_m_n_f16\000vbrsrq_m_n_f32\000vbrsrq_m_n_s16\000vbrsr" |
| "q_m_n_s32\000vbrsrq_m_n_s8\000vbrsrq_m_n_u16\000vbrsrq_m_n_u32\000vbrsr" |
| "q_m_n_u8\000vbrsrq\000vbrsrq_n_f16\000vbrsrq_n_f32\000vbrsrq_n_s16\000v" |
| "brsrq_n_s32\000vbrsrq_n_s8\000vbrsrq_n_u16\000vbrsrq_n_u32\000vbrsrq_n_" |
| "u8\000vbrsrq_x\000vbrsrq_x_n_f16\000vbrsrq_x_n_f32\000vbrsrq_x_n_s16\000" |
| "vbrsrq_x_n_s32\000vbrsrq_x_n_s8\000vbrsrq_x_n_u16\000vbrsrq_x_n_u32\000" |
| "vbrsrq_x_n_u8\000vcaddq_rot270\000vcaddq_rot270_f16\000vcaddq_rot270_f3" |
| "2\000vcaddq_rot270_m\000vcaddq_rot270_m_f16\000vcaddq_rot270_m_f32\000v" |
| "caddq_rot270_m_s16\000vcaddq_rot270_m_s32\000vcaddq_rot270_m_s8\000vcad" |
| "dq_rot270_m_u16\000vcaddq_rot270_m_u32\000vcaddq_rot270_m_u8\000vcaddq_" |
| "rot270_s16\000vcaddq_rot270_s32\000vcaddq_rot270_s8\000vcaddq_rot270_u1" |
| "6\000vcaddq_rot270_u32\000vcaddq_rot270_u8\000vcaddq_rot270_x\000vcaddq" |
| "_rot270_x_f16\000vcaddq_rot270_x_f32\000vcaddq_rot270_x_s16\000vcaddq_r" |
| "ot270_x_s32\000vcaddq_rot270_x_s8\000vcaddq_rot270_x_u16\000vcaddq_rot2" |
| "70_x_u32\000vcaddq_rot270_x_u8\000vcaddq_rot90\000vcaddq_rot90_f16\000v" |
| "caddq_rot90_f32\000vcaddq_rot90_m\000vcaddq_rot90_m_f16\000vcaddq_rot90" |
| "_m_f32\000vcaddq_rot90_m_s16\000vcaddq_rot90_m_s32\000vcaddq_rot90_m_s8" |
| "\000vcaddq_rot90_m_u16\000vcaddq_rot90_m_u32\000vcaddq_rot90_m_u8\000vc" |
| "addq_rot90_s16\000vcaddq_rot90_s32\000vcaddq_rot90_s8\000vcaddq_rot90_u" |
| "16\000vcaddq_rot90_u32\000vcaddq_rot90_u8\000vcaddq_rot90_x\000vcaddq_r" |
| "ot90_x_f16\000vcaddq_rot90_x_f32\000vcaddq_rot90_x_s16\000vcaddq_rot90_" |
| "x_s32\000vcaddq_rot90_x_s8\000vcaddq_rot90_x_u16\000vcaddq_rot90_x_u32\000" |
| "vcaddq_rot90_x_u8\000vclsq_m\000vclsq_m_s16\000vclsq_m_s32\000vclsq_m_s" |
| "8\000vclsq\000vclsq_s16\000vclsq_s32\000vclsq_s8\000vclsq_x\000vclsq_x_" |
| "s16\000vclsq_x_s32\000vclsq_x_s8\000vclzq_m\000vclzq_m_s16\000vclzq_m_s" |
| "32\000vclzq_m_s8\000vclzq_m_u16\000vclzq_m_u32\000vclzq_m_u8\000vclzq\000" |
| "vclzq_s16\000vclzq_s32\000vclzq_s8\000vclzq_u16\000vclzq_u32\000vclzq_u" |
| "8\000vclzq_x\000vclzq_x_s16\000vclzq_x_s32\000vclzq_x_s8\000vclzq_x_u16" |
| "\000vclzq_x_u32\000vclzq_x_u8\000vcmlaq\000vcmlaq_f16\000vcmlaq_f32\000" |
| "vcmlaq_m\000vcmlaq_m_f16\000vcmlaq_m_f32\000vcmlaq_rot180\000vcmlaq_rot" |
| "180_f16\000vcmlaq_rot180_f32\000vcmlaq_rot180_m\000vcmlaq_rot180_m_f16\000" |
| "vcmlaq_rot180_m_f32\000vcmlaq_rot270\000vcmlaq_rot270_f16\000vcmlaq_rot" |
| "270_f32\000vcmlaq_rot270_m\000vcmlaq_rot270_m_f16\000vcmlaq_rot270_m_f3" |
| "2\000vcmlaq_rot90\000vcmlaq_rot90_f16\000vcmlaq_rot90_f32\000vcmlaq_rot" |
| "90_m\000vcmlaq_rot90_m_f16\000vcmlaq_rot90_m_f32\000vcmpcsq_m\000vcmpcs" |
| "q_m_n_u16\000vcmpcsq_m_n_u32\000vcmpcsq_m_n_u8\000vcmpcsq_m_u16\000vcmp" |
| "csq_m_u32\000vcmpcsq_m_u8\000vcmpcsq\000vcmpcsq_n_u16\000vcmpcsq_n_u32\000" |
| "vcmpcsq_n_u8\000vcmpcsq_u16\000vcmpcsq_u32\000vcmpcsq_u8\000vcmpeqq\000" |
| "vcmpeqq_f16\000vcmpeqq_f32\000vcmpeqq_m\000vcmpeqq_m_f16\000vcmpeqq_m_f" |
| "32\000vcmpeqq_m_n_f16\000vcmpeqq_m_n_f32\000vcmpeqq_m_n_s16\000vcmpeqq_" |
| "m_n_s32\000vcmpeqq_m_n_s8\000vcmpeqq_m_n_u16\000vcmpeqq_m_n_u32\000vcmp" |
| "eqq_m_n_u8\000vcmpeqq_m_s16\000vcmpeqq_m_s32\000vcmpeqq_m_s8\000vcmpeqq" |
| "_m_u16\000vcmpeqq_m_u32\000vcmpeqq_m_u8\000vcmpeqq_n_f16\000vcmpeqq_n_f" |
| "32\000vcmpeqq_n_s16\000vcmpeqq_n_s32\000vcmpeqq_n_s8\000vcmpeqq_n_u16\000" |
| "vcmpeqq_n_u32\000vcmpeqq_n_u8\000vcmpeqq_s16\000vcmpeqq_s32\000vcmpeqq_" |
| "s8\000vcmpeqq_u16\000vcmpeqq_u32\000vcmpeqq_u8\000vcmpgeq\000vcmpgeq_f1" |
| "6\000vcmpgeq_f32\000vcmpgeq_m\000vcmpgeq_m_f16\000vcmpgeq_m_f32\000vcmp" |
| "geq_m_n_f16\000vcmpgeq_m_n_f32\000vcmpgeq_m_n_s16\000vcmpgeq_m_n_s32\000" |
| "vcmpgeq_m_n_s8\000vcmpgeq_m_s16\000vcmpgeq_m_s32\000vcmpgeq_m_s8\000vcm" |
| "pgeq_n_f16\000vcmpgeq_n_f32\000vcmpgeq_n_s16\000vcmpgeq_n_s32\000vcmpge" |
| "q_n_s8\000vcmpgeq_s16\000vcmpgeq_s32\000vcmpgeq_s8\000vcmpgtq\000vcmpgt" |
| "q_f16\000vcmpgtq_f32\000vcmpgtq_m\000vcmpgtq_m_f16\000vcmpgtq_m_f32\000" |
| "vcmpgtq_m_n_f16\000vcmpgtq_m_n_f32\000vcmpgtq_m_n_s16\000vcmpgtq_m_n_s3" |
| "2\000vcmpgtq_m_n_s8\000vcmpgtq_m_s16\000vcmpgtq_m_s32\000vcmpgtq_m_s8\000" |
| "vcmpgtq_n_f16\000vcmpgtq_n_f32\000vcmpgtq_n_s16\000vcmpgtq_n_s32\000vcm" |
| "pgtq_n_s8\000vcmpgtq_s16\000vcmpgtq_s32\000vcmpgtq_s8\000vcmphiq_m\000v" |
| "cmphiq_m_n_u16\000vcmphiq_m_n_u32\000vcmphiq_m_n_u8\000vcmphiq_m_u16\000" |
| "vcmphiq_m_u32\000vcmphiq_m_u8\000vcmphiq\000vcmphiq_n_u16\000vcmphiq_n_" |
| "u32\000vcmphiq_n_u8\000vcmphiq_u16\000vcmphiq_u32\000vcmphiq_u8\000vcmp" |
| "leq\000vcmpleq_f16\000vcmpleq_f32\000vcmpleq_m\000vcmpleq_m_f16\000vcmp" |
| "leq_m_f32\000vcmpleq_m_n_f16\000vcmpleq_m_n_f32\000vcmpleq_m_n_s16\000v" |
| "cmpleq_m_n_s32\000vcmpleq_m_n_s8\000vcmpleq_m_s16\000vcmpleq_m_s32\000v" |
| "cmpleq_m_s8\000vcmpleq_n_f16\000vcmpleq_n_f32\000vcmpleq_n_s16\000vcmpl" |
| "eq_n_s32\000vcmpleq_n_s8\000vcmpleq_s16\000vcmpleq_s32\000vcmpleq_s8\000" |
| "vcmpltq\000vcmpltq_f16\000vcmpltq_f32\000vcmpltq_m\000vcmpltq_m_f16\000" |
| "vcmpltq_m_f32\000vcmpltq_m_n_f16\000vcmpltq_m_n_f32\000vcmpltq_m_n_s16\000" |
| "vcmpltq_m_n_s32\000vcmpltq_m_n_s8\000vcmpltq_m_s16\000vcmpltq_m_s32\000" |
| "vcmpltq_m_s8\000vcmpltq_n_f16\000vcmpltq_n_f32\000vcmpltq_n_s16\000vcmp" |
| "ltq_n_s32\000vcmpltq_n_s8\000vcmpltq_s16\000vcmpltq_s32\000vcmpltq_s8\000" |
| "vcmpneq\000vcmpneq_f16\000vcmpneq_f32\000vcmpneq_m\000vcmpneq_m_f16\000" |
| "vcmpneq_m_f32\000vcmpneq_m_n_f16\000vcmpneq_m_n_f32\000vcmpneq_m_n_s16\000" |
| "vcmpneq_m_n_s32\000vcmpneq_m_n_s8\000vcmpneq_m_n_u16\000vcmpneq_m_n_u32" |
| "\000vcmpneq_m_n_u8\000vcmpneq_m_s16\000vcmpneq_m_s32\000vcmpneq_m_s8\000" |
| "vcmpneq_m_u16\000vcmpneq_m_u32\000vcmpneq_m_u8\000vcmpneq_n_f16\000vcmp" |
| "neq_n_f32\000vcmpneq_n_s16\000vcmpneq_n_s32\000vcmpneq_n_s8\000vcmpneq_" |
| "n_u16\000vcmpneq_n_u32\000vcmpneq_n_u8\000vcmpneq_s16\000vcmpneq_s32\000" |
| "vcmpneq_s8\000vcmpneq_u16\000vcmpneq_u32\000vcmpneq_u8\000vcmulq\000vcm" |
| "ulq_f16\000vcmulq_f32\000vcmulq_m\000vcmulq_m_f16\000vcmulq_m_f32\000vc" |
| "mulq_rot180\000vcmulq_rot180_f16\000vcmulq_rot180_f32\000vcmulq_rot180_" |
| "m\000vcmulq_rot180_m_f16\000vcmulq_rot180_m_f32\000vcmulq_rot180_x\000v" |
| "cmulq_rot180_x_f16\000vcmulq_rot180_x_f32\000vcmulq_rot270\000vcmulq_ro" |
| "t270_f16\000vcmulq_rot270_f32\000vcmulq_rot270_m\000vcmulq_rot270_m_f16" |
| "\000vcmulq_rot270_m_f32\000vcmulq_rot270_x\000vcmulq_rot270_x_f16\000vc" |
| "mulq_rot270_x_f32\000vcmulq_rot90\000vcmulq_rot90_f16\000vcmulq_rot90_f" |
| "32\000vcmulq_rot90_m\000vcmulq_rot90_m_f16\000vcmulq_rot90_m_f32\000vcm" |
| "ulq_rot90_x\000vcmulq_rot90_x_f16\000vcmulq_rot90_x_f32\000vcmulq_x\000" |
| "vcmulq_x_f16\000vcmulq_x_f32\000vcreateq_f16\000vcreateq_f32\000vcreate" |
| "q_s16\000vcreateq_s32\000vcreateq_s64\000vcreateq_s8\000vcreateq_u16\000" |
| "vcreateq_u32\000vcreateq_u64\000vcreateq_u8\000vctp16q\000vctp16q_m\000" |
| "vctp32q\000vctp32q_m\000vctp64q\000vctp64q_m\000vctp8q\000vctp8q_m\000v" |
| "cvtaq_m\000vcvtaq_m_s16_f16\000vcvtaq_m_s32_f32\000vcvtaq_m_u16_f16\000" |
| "vcvtaq_m_u32_f32\000vcvtaq_s16_f16\000vcvtaq_s32_f32\000vcvtaq_u16_f16\000" |
| "vcvtaq_u32_f32\000vcvtaq_x_s16_f16\000vcvtaq_x_s32_f32\000vcvtaq_x_u16_" |
| "f16\000vcvtaq_x_u32_f32\000vcvtbq_f16_f32\000vcvtbq_f32_f16\000vcvtbq_m" |
| "_f16_f32\000vcvtbq_m_f32_f16\000vcvtbq_x_f32_f16\000vcvtmq_m\000vcvtmq_" |
| "m_s16_f16\000vcvtmq_m_s32_f32\000vcvtmq_m_u16_f16\000vcvtmq_m_u32_f32\000" |
| "vcvtmq_s16_f16\000vcvtmq_s32_f32\000vcvtmq_u16_f16\000vcvtmq_u32_f32\000" |
| "vcvtmq_x_s16_f16\000vcvtmq_x_s32_f32\000vcvtmq_x_u16_f16\000vcvtmq_x_u3" |
| "2_f32\000vcvtnq_m\000vcvtnq_m_s16_f16\000vcvtnq_m_s32_f32\000vcvtnq_m_u" |
| "16_f16\000vcvtnq_m_u32_f32\000vcvtnq_s16_f16\000vcvtnq_s32_f32\000vcvtn" |
| "q_u16_f16\000vcvtnq_u32_f32\000vcvtnq_x_s16_f16\000vcvtnq_x_s32_f32\000" |
| "vcvtnq_x_u16_f16\000vcvtnq_x_u32_f32\000vcvtpq_m\000vcvtpq_m_s16_f16\000" |
| "vcvtpq_m_s32_f32\000vcvtpq_m_u16_f16\000vcvtpq_m_u32_f32\000vcvtpq_s16_" |
| "f16\000vcvtpq_s32_f32\000vcvtpq_u16_f16\000vcvtpq_u32_f32\000vcvtpq_x_s" |
| "16_f16\000vcvtpq_x_s32_f32\000vcvtpq_x_u16_f16\000vcvtpq_x_u32_f32\000v" |
| "cvtq\000vcvtq_f16_s16\000vcvtq_f16_u16\000vcvtq_f32_s32\000vcvtq_f32_u3" |
| "2\000vcvtq_m\000vcvtq_m_f16_s16\000vcvtq_m_f16_u16\000vcvtq_m_f32_s32\000" |
| "vcvtq_m_f32_u32\000vcvtq_m_n\000vcvtq_m_n_f16_s16\000vcvtq_m_n_f16_u16\000" |
| "vcvtq_m_n_f32_s32\000vcvtq_m_n_f32_u32\000vcvtq_m_n_s16_f16\000vcvtq_m_" |
| "n_s32_f32\000vcvtq_m_n_u16_f16\000vcvtq_m_n_u32_f32\000vcvtq_m_s16_f16\000" |
| "vcvtq_m_s32_f32\000vcvtq_m_u16_f16\000vcvtq_m_u32_f32\000vcvtq_n\000vcv" |
| "tq_n_f16_s16\000vcvtq_n_f16_u16\000vcvtq_n_f32_s32\000vcvtq_n_f32_u32\000" |
| "vcvtq_n_s16_f16\000vcvtq_n_s32_f32\000vcvtq_n_u16_f16\000vcvtq_n_u32_f3" |
| "2\000vcvtq_s16_f16\000vcvtq_s32_f32\000vcvtq_u16_f16\000vcvtq_u32_f32\000" |
| "vcvtq_x\000vcvtq_x_f16_s16\000vcvtq_x_f16_u16\000vcvtq_x_f32_s32\000vcv" |
| "tq_x_f32_u32\000vcvtq_x_n\000vcvtq_x_n_f16_s16\000vcvtq_x_n_f16_u16\000" |
| "vcvtq_x_n_f32_s32\000vcvtq_x_n_f32_u32\000vcvtq_x_n_s16_f16\000vcvtq_x_" |
| "n_s32_f32\000vcvtq_x_n_u16_f16\000vcvtq_x_n_u32_f32\000vcvtq_x_s16_f16\000" |
| "vcvtq_x_s32_f32\000vcvtq_x_u16_f16\000vcvtq_x_u32_f32\000vcvttq_f16_f32" |
| "\000vcvttq_f32_f16\000vcvttq_m_f16_f32\000vcvttq_m_f32_f16\000vcvttq_x_" |
| "f32_f16\000vddupq_m\000vddupq_m_n_u16\000vddupq_m_n_u32\000vddupq_m_n_u" |
| "8\000vddupq_m_wb_u16\000vddupq_m_wb_u32\000vddupq_m_wb_u8\000vddupq_u16" |
| "\000vddupq_n_u16\000vddupq_u32\000vddupq_n_u32\000vddupq_u8\000vddupq_n" |
| "_u8\000vddupq_wb_u16\000vddupq_wb_u32\000vddupq_wb_u8\000vddupq_x_u16\000" |
| "vddupq_x_n_u16\000vddupq_x_u32\000vddupq_x_n_u32\000vddupq_x_u8\000vddu" |
| "pq_x_n_u8\000vddupq_x_wb_u16\000vddupq_x_wb_u32\000vddupq_x_wb_u8\000vd" |
| "upq_m\000vdupq_m_n_f16\000vdupq_m_n_f32\000vdupq_m_n_s16\000vdupq_m_n_s" |
| "32\000vdupq_m_n_s8\000vdupq_m_n_u16\000vdupq_m_n_u32\000vdupq_m_n_u8\000" |
| "vdupq_n_f16\000vdupq_n_f32\000vdupq_n_s16\000vdupq_n_s32\000vdupq_n_s8\000" |
| "vdupq_n_u16\000vdupq_n_u32\000vdupq_n_u8\000vdupq_x_n_f16\000vdupq_x_n_" |
| "f32\000vdupq_x_n_s16\000vdupq_x_n_s32\000vdupq_x_n_s8\000vdupq_x_n_u16\000" |
| "vdupq_x_n_u32\000vdupq_x_n_u8\000vdwdupq_m\000vdwdupq_m_n_u16\000vdwdup" |
| "q_m_n_u32\000vdwdupq_m_n_u8\000vdwdupq_m_wb_u16\000vdwdupq_m_wb_u32\000" |
| "vdwdupq_m_wb_u8\000vdwdupq_u16\000vdwdupq_n_u16\000vdwdupq_u32\000vdwdu" |
| "pq_n_u32\000vdwdupq_u8\000vdwdupq_n_u8\000vdwdupq_wb_u16\000vdwdupq_wb_" |
| "u32\000vdwdupq_wb_u8\000vdwdupq_x_u16\000vdwdupq_x_n_u16\000vdwdupq_x_u" |
| "32\000vdwdupq_x_n_u32\000vdwdupq_x_u8\000vdwdupq_x_n_u8\000vdwdupq_x_wb" |
| "_u16\000vdwdupq_x_wb_u32\000vdwdupq_x_wb_u8\000veorq\000veorq_f16\000ve" |
| "orq_f32\000veorq_m\000veorq_m_f16\000veorq_m_f32\000veorq_m_s16\000veor" |
| "q_m_s32\000veorq_m_s8\000veorq_m_u16\000veorq_m_u32\000veorq_m_u8\000ve" |
| "orq_s16\000veorq_s32\000veorq_s8\000veorq_u16\000veorq_u32\000veorq_u8\000" |
| "veorq_x\000veorq_x_f16\000veorq_x_f32\000veorq_x_s16\000veorq_x_s32\000" |
| "veorq_x_s8\000veorq_x_u16\000veorq_x_u32\000veorq_x_u8\000vfmaq\000vfma" |
| "q_f16\000vfmaq_f32\000vfmaq_m\000vfmaq_m_f16\000vfmaq_m_f32\000vfmaq_m_" |
| "n_f16\000vfmaq_m_n_f32\000vfmaq_n_f16\000vfmaq_n_f32\000vfmasq_m\000vfm" |
| "asq_m_n_f16\000vfmasq_m_n_f32\000vfmasq\000vfmasq_n_f16\000vfmasq_n_f32" |
| "\000vfmsq\000vfmsq_f16\000vfmsq_f32\000vfmsq_m\000vfmsq_m_f16\000vfmsq_" |
| "m_f32\000vgetq_lane\000vgetq_lane_f16\000vgetq_lane_f32\000vgetq_lane_s" |
| "16\000vgetq_lane_s32\000vgetq_lane_s64\000vgetq_lane_s8\000vgetq_lane_u" |
| "16\000vgetq_lane_u32\000vgetq_lane_u64\000vgetq_lane_u8\000vhaddq_m\000" |
| "vhaddq_m_n_s16\000vhaddq_m_n_s32\000vhaddq_m_n_s8\000vhaddq_m_n_u16\000" |
| "vhaddq_m_n_u32\000vhaddq_m_n_u8\000vhaddq_m_s16\000vhaddq_m_s32\000vhad" |
| "dq_m_s8\000vhaddq_m_u16\000vhaddq_m_u32\000vhaddq_m_u8\000vhaddq\000vha" |
| "ddq_n_s16\000vhaddq_n_s32\000vhaddq_n_s8\000vhaddq_n_u16\000vhaddq_n_u3" |
| "2\000vhaddq_n_u8\000vhaddq_s16\000vhaddq_s32\000vhaddq_s8\000vhaddq_u16" |
| "\000vhaddq_u32\000vhaddq_u8\000vhaddq_x\000vhaddq_x_n_s16\000vhaddq_x_n" |
| "_s32\000vhaddq_x_n_s8\000vhaddq_x_n_u16\000vhaddq_x_n_u32\000vhaddq_x_n" |
| "_u8\000vhaddq_x_s16\000vhaddq_x_s32\000vhaddq_x_s8\000vhaddq_x_u16\000v" |
| "haddq_x_u32\000vhaddq_x_u8\000vhcaddq_rot270_m\000vhcaddq_rot270_m_s16\000" |
| "vhcaddq_rot270_m_s32\000vhcaddq_rot270_m_s8\000vhcaddq_rot270\000vhcadd" |
| "q_rot270_s16\000vhcaddq_rot270_s32\000vhcaddq_rot270_s8\000vhcaddq_rot2" |
| "70_x\000vhcaddq_rot270_x_s16\000vhcaddq_rot270_x_s32\000vhcaddq_rot270_" |
| "x_s8\000vhcaddq_rot90_m\000vhcaddq_rot90_m_s16\000vhcaddq_rot90_m_s32\000" |
| "vhcaddq_rot90_m_s8\000vhcaddq_rot90\000vhcaddq_rot90_s16\000vhcaddq_rot" |
| "90_s32\000vhcaddq_rot90_s8\000vhcaddq_rot90_x\000vhcaddq_rot90_x_s16\000" |
| "vhcaddq_rot90_x_s32\000vhcaddq_rot90_x_s8\000vhsubq_m\000vhsubq_m_n_s16" |
| "\000vhsubq_m_n_s32\000vhsubq_m_n_s8\000vhsubq_m_n_u16\000vhsubq_m_n_u32" |
| "\000vhsubq_m_n_u8\000vhsubq_m_s16\000vhsubq_m_s32\000vhsubq_m_s8\000vhs" |
| "ubq_m_u16\000vhsubq_m_u32\000vhsubq_m_u8\000vhsubq\000vhsubq_n_s16\000v" |
| "hsubq_n_s32\000vhsubq_n_s8\000vhsubq_n_u16\000vhsubq_n_u32\000vhsubq_n_" |
| "u8\000vhsubq_s16\000vhsubq_s32\000vhsubq_s8\000vhsubq_u16\000vhsubq_u32" |
| "\000vhsubq_u8\000vhsubq_x\000vhsubq_x_n_s16\000vhsubq_x_n_s32\000vhsubq" |
| "_x_n_s8\000vhsubq_x_n_u16\000vhsubq_x_n_u32\000vhsubq_x_n_u8\000vhsubq_" |
| "x_s16\000vhsubq_x_s32\000vhsubq_x_s8\000vhsubq_x_u16\000vhsubq_x_u32\000" |
| "vhsubq_x_u8\000vidupq_m\000vidupq_m_n_u16\000vidupq_m_n_u32\000vidupq_m" |
| "_n_u8\000vidupq_m_wb_u16\000vidupq_m_wb_u32\000vidupq_m_wb_u8\000vidupq" |
| "_u16\000vidupq_n_u16\000vidupq_u32\000vidupq_n_u32\000vidupq_u8\000vidu" |
| "pq_n_u8\000vidupq_wb_u16\000vidupq_wb_u32\000vidupq_wb_u8\000vidupq_x_u" |
| "16\000vidupq_x_n_u16\000vidupq_x_u32\000vidupq_x_n_u32\000vidupq_x_u8\000" |
| "vidupq_x_n_u8\000vidupq_x_wb_u16\000vidupq_x_wb_u32\000vidupq_x_wb_u8\000" |
| "viwdupq_m\000viwdupq_m_n_u16\000viwdupq_m_n_u32\000viwdupq_m_n_u8\000vi" |
| "wdupq_m_wb_u16\000viwdupq_m_wb_u32\000viwdupq_m_wb_u8\000viwdupq_u16\000" |
| "viwdupq_n_u16\000viwdupq_u32\000viwdupq_n_u32\000viwdupq_u8\000viwdupq_" |
| "n_u8\000viwdupq_wb_u16\000viwdupq_wb_u32\000viwdupq_wb_u8\000viwdupq_x_" |
| "u16\000viwdupq_x_n_u16\000viwdupq_x_u32\000viwdupq_x_n_u32\000viwdupq_x" |
| "_u8\000viwdupq_x_n_u8\000viwdupq_x_wb_u16\000viwdupq_x_wb_u32\000viwdup" |
| "q_x_wb_u8\000vld1q\000vld1q_f16\000vld1q_f32\000vld1q_s16\000vld1q_s32\000" |
| "vld1q_s8\000vld1q_u16\000vld1q_u32\000vld1q_u8\000vld1q_z\000vld1q_z_f1" |
| "6\000vld1q_z_f32\000vld1q_z_s16\000vld1q_z_s32\000vld1q_z_s8\000vld1q_z" |
| "_u16\000vld1q_z_u32\000vld1q_z_u8\000vld2q\000vld2q_f16\000vld2q_f32\000" |
| "vld2q_s16\000vld2q_s32\000vld2q_s8\000vld2q_u16\000vld2q_u32\000vld2q_u" |
| "8\000vld4q\000vld4q_f16\000vld4q_f32\000vld4q_s16\000vld4q_s32\000vld4q" |
| "_s8\000vld4q_u16\000vld4q_u32\000vld4q_u8\000vldrbq_gather_offset\000vl" |
| "drbq_gather_offset_s16\000vldrbq_gather_offset_s32\000vldrbq_gather_off" |
| "set_s8\000vldrbq_gather_offset_u16\000vldrbq_gather_offset_u32\000vldrb" |
| "q_gather_offset_u8\000vldrbq_gather_offset_z\000vldrbq_gather_offset_z_" |
| "s16\000vldrbq_gather_offset_z_s32\000vldrbq_gather_offset_z_s8\000vldrb" |
| "q_gather_offset_z_u16\000vldrbq_gather_offset_z_u32\000vldrbq_gather_of" |
| "fset_z_u8\000vldrbq_s16\000vldrbq_s32\000vldrbq_s8\000vldrbq_u16\000vld" |
| "rbq_u32\000vldrbq_u8\000vldrbq_z_s16\000vldrbq_z_s32\000vldrbq_z_s8\000" |
| "vldrbq_z_u16\000vldrbq_z_u32\000vldrbq_z_u8\000vldrdq_gather_base_s64\000" |
| "vldrdq_gather_base_u64\000vldrdq_gather_base_wb_s64\000vldrdq_gather_ba" |
| "se_wb_u64\000vldrdq_gather_base_wb_z_s64\000vldrdq_gather_base_wb_z_u64" |
| "\000vldrdq_gather_base_z_s64\000vldrdq_gather_base_z_u64\000vldrdq_gath" |
| "er_offset\000vldrdq_gather_offset_s64\000vldrdq_gather_offset_u64\000vl" |
| "drdq_gather_offset_z\000vldrdq_gather_offset_z_s64\000vldrdq_gather_off" |
| "set_z_u64\000vldrdq_gather_shifted_offset\000vldrdq_gather_shifted_offs" |
| "et_s64\000vldrdq_gather_shifted_offset_u64\000vldrdq_gather_shifted_off" |
| "set_z\000vldrdq_gather_shifted_offset_z_s64\000vldrdq_gather_shifted_of" |
| "fset_z_u64\000vldrhq_f16\000vldrhq_gather_offset\000vldrhq_gather_offse" |
| "t_f16\000vldrhq_gather_offset_s16\000vldrhq_gather_offset_s32\000vldrhq" |
| "_gather_offset_u16\000vldrhq_gather_offset_u32\000vldrhq_gather_offset_" |
| "z\000vldrhq_gather_offset_z_f16\000vldrhq_gather_offset_z_s16\000vldrhq" |
| "_gather_offset_z_s32\000vldrhq_gather_offset_z_u16\000vldrhq_gather_off" |
| "set_z_u32\000vldrhq_gather_shifted_offset\000vldrhq_gather_shifted_offs" |
| "et_f16\000vldrhq_gather_shifted_offset_s16\000vldrhq_gather_shifted_off" |
| "set_s32\000vldrhq_gather_shifted_offset_u16\000vldrhq_gather_shifted_of" |
| "fset_u32\000vldrhq_gather_shifted_offset_z\000vldrhq_gather_shifted_off" |
| "set_z_f16\000vldrhq_gather_shifted_offset_z_s16\000vldrhq_gather_shifte" |
| "d_offset_z_s32\000vldrhq_gather_shifted_offset_z_u16\000vldrhq_gather_s" |
| "hifted_offset_z_u32\000vldrhq_s16\000vldrhq_s32\000vldrhq_u16\000vldrhq" |
| "_u32\000vldrhq_z_f16\000vldrhq_z_s16\000vldrhq_z_s32\000vldrhq_z_u16\000" |
| "vldrhq_z_u32\000vldrwq_f32\000vldrwq_gather_base_f32\000vldrwq_gather_b" |
| "ase_s32\000vldrwq_gather_base_u32\000vldrwq_gather_base_wb_f32\000vldrw" |
| "q_gather_base_wb_s32\000vldrwq_gather_base_wb_u32\000vldrwq_gather_base" |
| "_wb_z_f32\000vldrwq_gather_base_wb_z_s32\000vldrwq_gather_base_wb_z_u32" |
| "\000vldrwq_gather_base_z_f32\000vldrwq_gather_base_z_s32\000vldrwq_gath" |
| "er_base_z_u32\000vldrwq_gather_offset\000vldrwq_gather_offset_f32\000vl" |
| "drwq_gather_offset_s32\000vldrwq_gather_offset_u32\000vldrwq_gather_off" |
| "set_z\000vldrwq_gather_offset_z_f32\000vldrwq_gather_offset_z_s32\000vl" |
| "drwq_gather_offset_z_u32\000vldrwq_gather_shifted_offset\000vldrwq_gath" |
| "er_shifted_offset_f32\000vldrwq_gather_shifted_offset_s32\000vldrwq_gat" |
| "her_shifted_offset_u32\000vldrwq_gather_shifted_offset_z\000vldrwq_gath" |
| "er_shifted_offset_z_f32\000vldrwq_gather_shifted_offset_z_s32\000vldrwq" |
| "_gather_shifted_offset_z_u32\000vldrwq_s32\000vldrwq_u32\000vldrwq_z_f3" |
| "2\000vldrwq_z_s32\000vldrwq_z_u32\000vmaxaq_m\000vmaxaq_m_s16\000vmaxaq" |
| "_m_s32\000vmaxaq_m_s8\000vmaxaq\000vmaxaq_s16\000vmaxaq_s32\000vmaxaq_s" |
| "8\000vmaxavq_p\000vmaxavq_p_s16\000vmaxavq_p_s32\000vmaxavq_p_s8\000vma" |
| "xavq\000vmaxavq_s16\000vmaxavq_s32\000vmaxavq_s8\000vmaxnmaq\000vmaxnma" |
| "q_f16\000vmaxnmaq_f32\000vmaxnmaq_m\000vmaxnmaq_m_f16\000vmaxnmaq_m_f32" |
| "\000vmaxnmavq\000vmaxnmavq_f16\000vmaxnmavq_f32\000vmaxnmavq_p\000vmaxn" |
| "mavq_p_f16\000vmaxnmavq_p_f32\000vmaxnmq\000vmaxnmq_f16\000vmaxnmq_f32\000" |
| "vmaxnmq_m\000vmaxnmq_m_f16\000vmaxnmq_m_f32\000vmaxnmq_x\000vmaxnmq_x_f" |
| "16\000vmaxnmq_x_f32\000vmaxnmvq\000vmaxnmvq_f16\000vmaxnmvq_f32\000vmax" |
| "nmvq_p\000vmaxnmvq_p_f16\000vmaxnmvq_p_f32\000vmaxq_m\000vmaxq_m_s16\000" |
| "vmaxq_m_s32\000vmaxq_m_s8\000vmaxq_m_u16\000vmaxq_m_u32\000vmaxq_m_u8\000" |
| "vmaxq\000vmaxq_s16\000vmaxq_s32\000vmaxq_s8\000vmaxq_u16\000vmaxq_u32\000" |
| "vmaxq_u8\000vmaxq_x\000vmaxq_x_s16\000vmaxq_x_s32\000vmaxq_x_s8\000vmax" |
| "q_x_u16\000vmaxq_x_u32\000vmaxq_x_u8\000vmaxvq_p\000vmaxvq_p_s16\000vma" |
| "xvq_p_s32\000vmaxvq_p_s8\000vmaxvq_p_u16\000vmaxvq_p_u32\000vmaxvq_p_u8" |
| "\000vmaxvq\000vmaxvq_s16\000vmaxvq_s32\000vmaxvq_s8\000vmaxvq_u16\000vm" |
| "axvq_u32\000vmaxvq_u8\000vminaq_m\000vminaq_m_s16\000vminaq_m_s32\000vm" |
| "inaq_m_s8\000vminaq\000vminaq_s16\000vminaq_s32\000vminaq_s8\000vminavq" |
| "_p\000vminavq_p_s16\000vminavq_p_s32\000vminavq_p_s8\000vminavq\000vmin" |
| "avq_s16\000vminavq_s32\000vminavq_s8\000vminnmaq\000vminnmaq_f16\000vmi" |
| "nnmaq_f32\000vminnmaq_m\000vminnmaq_m_f16\000vminnmaq_m_f32\000vminnmav" |
| "q\000vminnmavq_f16\000vminnmavq_f32\000vminnmavq_p\000vminnmavq_p_f16\000" |
| "vminnmavq_p_f32\000vminnmq\000vminnmq_f16\000vminnmq_f32\000vminnmq_m\000" |
| "vminnmq_m_f16\000vminnmq_m_f32\000vminnmq_x\000vminnmq_x_f16\000vminnmq" |
| "_x_f32\000vminnmvq\000vminnmvq_f16\000vminnmvq_f32\000vminnmvq_p\000vmi" |
| "nnmvq_p_f16\000vminnmvq_p_f32\000vminq_m\000vminq_m_s16\000vminq_m_s32\000" |
| "vminq_m_s8\000vminq_m_u16\000vminq_m_u32\000vminq_m_u8\000vminq\000vmin" |
| "q_s16\000vminq_s32\000vminq_s8\000vminq_u16\000vminq_u32\000vminq_u8\000" |
| "vminq_x\000vminq_x_s16\000vminq_x_s32\000vminq_x_s8\000vminq_x_u16\000v" |
| "minq_x_u32\000vminq_x_u8\000vminvq_p\000vminvq_p_s16\000vminvq_p_s32\000" |
| "vminvq_p_s8\000vminvq_p_u16\000vminvq_p_u32\000vminvq_p_u8\000vminvq\000" |
| "vminvq_s16\000vminvq_s32\000vminvq_s8\000vminvq_u16\000vminvq_u32\000vm" |
| "invq_u8\000vmladavaq_p\000vmladavaq_p_s16\000vmladavaq_p_s32\000vmladav" |
| "aq_p_s8\000vmladavaq_p_u16\000vmladavaq_p_u32\000vmladavaq_p_u8\000vmla" |
| "davaq\000vmladavaq_s16\000vmladavaq_s32\000vmladavaq_s8\000vmladavaq_u1" |
| "6\000vmladavaq_u32\000vmladavaq_u8\000vmladavaxq_p\000vmladavaxq_p_s16\000" |
| "vmladavaxq_p_s32\000vmladavaxq_p_s8\000vmladavaxq\000vmladavaxq_s16\000" |
| "vmladavaxq_s32\000vmladavaxq_s8\000vmladavq_p\000vmladavq_p_s16\000vmla" |
| "davq_p_s32\000vmladavq_p_s8\000vmladavq_p_u16\000vmladavq_p_u32\000vmla" |
| "davq_p_u8\000vmladavq\000vmladavq_s16\000vmladavq_s32\000vmladavq_s8\000" |
| "vmladavq_u16\000vmladavq_u32\000vmladavq_u8\000vmladavxq_p\000vmladavxq" |
| "_p_s16\000vmladavxq_p_s32\000vmladavxq_p_s8\000vmladavxq\000vmladavxq_s" |
| "16\000vmladavxq_s32\000vmladavxq_s8\000vmlaldavaq_p\000vmlaldavaq_p_s16" |
| "\000vmlaldavaq_p_s32\000vmlaldavaq_p_u16\000vmlaldavaq_p_u32\000vmlalda" |
| "vaq\000vmlaldavaq_s16\000vmlaldavaq_s32\000vmlaldavaq_u16\000vmlaldavaq" |
| "_u32\000vmlaldavaxq_p\000vmlaldavaxq_p_s16\000vmlaldavaxq_p_s32\000vmla" |
| "ldavaxq\000vmlaldavaxq_s16\000vmlaldavaxq_s32\000vmlaldavq_p\000vmlalda" |
| "vq_p_s16\000vmlaldavq_p_s32\000vmlaldavq_p_u16\000vmlaldavq_p_u32\000vm" |
| "laldavq\000vmlaldavq_s16\000vmlaldavq_s32\000vmlaldavq_u16\000vmlaldavq" |
| "_u32\000vmlaldavxq_p\000vmlaldavxq_p_s16\000vmlaldavxq_p_s32\000vmlalda" |
| "vxq\000vmlaldavxq_s16\000vmlaldavxq_s32\000vmlaq_m\000vmlaq_m_n_s16\000" |
| "vmlaq_m_n_s32\000vmlaq_m_n_s8\000vmlaq_m_n_u16\000vmlaq_m_n_u32\000vmla" |
| "q_m_n_u8\000vmlaq\000vmlaq_n_s16\000vmlaq_n_s32\000vmlaq_n_s8\000vmlaq_" |
| "n_u16\000vmlaq_n_u32\000vmlaq_n_u8\000vmlasq_m\000vmlasq_m_n_s16\000vml" |
| "asq_m_n_s32\000vmlasq_m_n_s8\000vmlasq_m_n_u16\000vmlasq_m_n_u32\000vml" |
| "asq_m_n_u8\000vmlasq\000vmlasq_n_s16\000vmlasq_n_s32\000vmlasq_n_s8\000" |
| "vmlasq_n_u16\000vmlasq_n_u32\000vmlasq_n_u8\000vmlsdavaq_p\000vmlsdavaq" |
| "_p_s16\000vmlsdavaq_p_s32\000vmlsdavaq_p_s8\000vmlsdavaq\000vmlsdavaq_s" |
| "16\000vmlsdavaq_s32\000vmlsdavaq_s8\000vmlsdavaxq_p\000vmlsdavaxq_p_s16" |
| "\000vmlsdavaxq_p_s32\000vmlsdavaxq_p_s8\000vmlsdavaxq\000vmlsdavaxq_s16" |
| "\000vmlsdavaxq_s32\000vmlsdavaxq_s8\000vmlsdavq_p\000vmlsdavq_p_s16\000" |
| "vmlsdavq_p_s32\000vmlsdavq_p_s8\000vmlsdavq\000vmlsdavq_s16\000vmlsdavq" |
| "_s32\000vmlsdavq_s8\000vmlsdavxq_p\000vmlsdavxq_p_s16\000vmlsdavxq_p_s3" |
| "2\000vmlsdavxq_p_s8\000vmlsdavxq\000vmlsdavxq_s16\000vmlsdavxq_s32\000v" |
| "mlsdavxq_s8\000vmlsldavaq_p\000vmlsldavaq_p_s16\000vmlsldavaq_p_s32\000" |
| "vmlsldavaq\000vmlsldavaq_s16\000vmlsldavaq_s32\000vmlsldavaxq_p\000vmls" |
| "ldavaxq_p_s16\000vmlsldavaxq_p_s32\000vmlsldavaxq\000vmlsldavaxq_s16\000" |
| "vmlsldavaxq_s32\000vmlsldavq_p\000vmlsldavq_p_s16\000vmlsldavq_p_s32\000" |
| "vmlsldavq\000vmlsldavq_s16\000vmlsldavq_s32\000vmlsldavxq_p\000vmlsldav" |
| "xq_p_s16\000vmlsldavxq_p_s32\000vmlsldavxq\000vmlsldavxq_s16\000vmlslda" |
| "vxq_s32\000vmovlbq_m\000vmovlbq_m_s16\000vmovlbq_m_s8\000vmovlbq_m_u16\000" |
| "vmovlbq_m_u8\000vmovlbq\000vmovlbq_s16\000vmovlbq_s8\000vmovlbq_u16\000" |
| "vmovlbq_u8\000vmovlbq_x\000vmovlbq_x_s16\000vmovlbq_x_s8\000vmovlbq_x_u" |
| "16\000vmovlbq_x_u8\000vmovltq_m\000vmovltq_m_s16\000vmovltq_m_s8\000vmo" |
| "vltq_m_u16\000vmovltq_m_u8\000vmovltq\000vmovltq_s16\000vmovltq_s8\000v" |
| "movltq_u16\000vmovltq_u8\000vmovltq_x\000vmovltq_x_s16\000vmovltq_x_s8\000" |
| "vmovltq_x_u16\000vmovltq_x_u8\000vmovnbq_m\000vmovnbq_m_s16\000vmovnbq_" |
| "m_s32\000vmovnbq_m_u16\000vmovnbq_m_u32\000vmovnbq\000vmovnbq_s16\000vm" |
| "ovnbq_s32\000vmovnbq_u16\000vmovnbq_u32\000vmovntq_m\000vmovntq_m_s16\000" |
| "vmovntq_m_s32\000vmovntq_m_u16\000vmovntq_m_u32\000vmovntq\000vmovntq_s" |
| "16\000vmovntq_s32\000vmovntq_u16\000vmovntq_u32\000vmulhq_m\000vmulhq_m" |
| "_s16\000vmulhq_m_s32\000vmulhq_m_s8\000vmulhq_m_u16\000vmulhq_m_u32\000" |
| "vmulhq_m_u8\000vmulhq\000vmulhq_s16\000vmulhq_s32\000vmulhq_s8\000vmulh" |
| "q_u16\000vmulhq_u32\000vmulhq_u8\000vmulhq_x\000vmulhq_x_s16\000vmulhq_" |
| "x_s32\000vmulhq_x_s8\000vmulhq_x_u16\000vmulhq_x_u32\000vmulhq_x_u8\000" |
| "vmullbq_int_m\000vmullbq_int_m_s16\000vmullbq_int_m_s32\000vmullbq_int_" |
| "m_s8\000vmullbq_int_m_u16\000vmullbq_int_m_u32\000vmullbq_int_m_u8\000v" |
| "mullbq_int\000vmullbq_int_s16\000vmullbq_int_s32\000vmullbq_int_s8\000v" |
| "mullbq_int_u16\000vmullbq_int_u32\000vmullbq_int_u8\000vmullbq_int_x\000" |
| "vmullbq_int_x_s16\000vmullbq_int_x_s32\000vmullbq_int_x_s8\000vmullbq_i" |
| "nt_x_u16\000vmullbq_int_x_u32\000vmullbq_int_x_u8\000vmullbq_poly_m\000" |
| "vmullbq_poly_m_p16\000vmullbq_poly_m_p8\000vmullbq_poly\000vmullbq_poly" |
| "_p16\000vmullbq_poly_p8\000vmullbq_poly_x\000vmullbq_poly_x_p16\000vmul" |
| "lbq_poly_x_p8\000vmulltq_int_m\000vmulltq_int_m_s16\000vmulltq_int_m_s3" |
| "2\000vmulltq_int_m_s8\000vmulltq_int_m_u16\000vmulltq_int_m_u32\000vmul" |
| "ltq_int_m_u8\000vmulltq_int\000vmulltq_int_s16\000vmulltq_int_s32\000vm" |
| "ulltq_int_s8\000vmulltq_int_u16\000vmulltq_int_u32\000vmulltq_int_u8\000" |
| "vmulltq_int_x\000vmulltq_int_x_s16\000vmulltq_int_x_s32\000vmulltq_int_" |
| "x_s8\000vmulltq_int_x_u16\000vmulltq_int_x_u32\000vmulltq_int_x_u8\000v" |
| "mulltq_poly_m\000vmulltq_poly_m_p16\000vmulltq_poly_m_p8\000vmulltq_pol" |
| "y\000vmulltq_poly_p16\000vmulltq_poly_p8\000vmulltq_poly_x\000vmulltq_p" |
| "oly_x_p16\000vmulltq_poly_x_p8\000vmulq\000vmulq_f16\000vmulq_f32\000vm" |
| "ulq_m\000vmulq_m_f16\000vmulq_m_f32\000vmulq_m_n_f16\000vmulq_m_n_f32\000" |
| "vmulq_m_n_s16\000vmulq_m_n_s32\000vmulq_m_n_s8\000vmulq_m_n_u16\000vmul" |
| "q_m_n_u32\000vmulq_m_n_u8\000vmulq_m_s16\000vmulq_m_s32\000vmulq_m_s8\000" |
| "vmulq_m_u16\000vmulq_m_u32\000vmulq_m_u8\000vmulq_n_f16\000vmulq_n_f32\000" |
| "vmulq_n_s16\000vmulq_n_s32\000vmulq_n_s8\000vmulq_n_u16\000vmulq_n_u32\000" |
| "vmulq_n_u8\000vmulq_s16\000vmulq_s32\000vmulq_s8\000vmulq_u16\000vmulq_" |
| "u32\000vmulq_u8\000vmulq_x\000vmulq_x_f16\000vmulq_x_f32\000vmulq_x_n_f" |
| "16\000vmulq_x_n_f32\000vmulq_x_n_s16\000vmulq_x_n_s32\000vmulq_x_n_s8\000" |
| "vmulq_x_n_u16\000vmulq_x_n_u32\000vmulq_x_n_u8\000vmulq_x_s16\000vmulq_" |
| "x_s32\000vmulq_x_s8\000vmulq_x_u16\000vmulq_x_u32\000vmulq_x_u8\000vmvn" |
| "q_m\000vmvnq_m_n_s16\000vmvnq_m_n_s32\000vmvnq_m_n_u16\000vmvnq_m_n_u32" |
| "\000vmvnq_m_s16\000vmvnq_m_s32\000vmvnq_m_s8\000vmvnq_m_u16\000vmvnq_m_" |
| "u32\000vmvnq_m_u8\000vmvnq_n_s16\000vmvnq_n_s32\000vmvnq_n_u16\000vmvnq" |
| "_n_u32\000vmvnq\000vmvnq_s16\000vmvnq_s32\000vmvnq_s8\000vmvnq_u16\000v" |
| "mvnq_u32\000vmvnq_u8\000vmvnq_x_n_s16\000vmvnq_x_n_s32\000vmvnq_x_n_u16" |
| "\000vmvnq_x_n_u32\000vmvnq_x\000vmvnq_x_s16\000vmvnq_x_s32\000vmvnq_x_s" |
| "8\000vmvnq_x_u16\000vmvnq_x_u32\000vmvnq_x_u8\000vnegq\000vnegq_f16\000" |
| "vnegq_f32\000vnegq_m\000vnegq_m_f16\000vnegq_m_f32\000vnegq_m_s16\000vn" |
| "egq_m_s32\000vnegq_m_s8\000vnegq_s16\000vnegq_s32\000vnegq_s8\000vnegq_" |
| "x\000vnegq_x_f16\000vnegq_x_f32\000vnegq_x_s16\000vnegq_x_s32\000vnegq_" |
| "x_s8\000vornq\000vornq_f16\000vornq_f32\000vornq_m\000vornq_m_f16\000vo" |
| "rnq_m_f32\000vornq_m_s16\000vornq_m_s32\000vornq_m_s8\000vornq_m_u16\000" |
| "vornq_m_u32\000vornq_m_u8\000vornq_s16\000vornq_s32\000vornq_s8\000vorn" |
| "q_u16\000vornq_u32\000vornq_u8\000vornq_x\000vornq_x_f16\000vornq_x_f32" |
| "\000vornq_x_s16\000vornq_x_s32\000vornq_x_s8\000vornq_x_u16\000vornq_x_" |
| "u32\000vornq_x_u8\000vorrq\000vorrq_f16\000vorrq_f32\000vorrq_m\000vorr" |
| "q_m_f16\000vorrq_m_f32\000vorrq_m_n\000vorrq_m_n_s16\000vorrq_m_n_s32\000" |
| "vorrq_m_n_u16\000vorrq_m_n_u32\000vorrq_m_s16\000vorrq_m_s32\000vorrq_m" |
| "_s8\000vorrq_m_u16\000vorrq_m_u32\000vorrq_m_u8\000vorrq_n_s16\000vorrq" |
| "_n_s32\000vorrq_n_u16\000vorrq_n_u32\000vorrq_s16\000vorrq_s32\000vorrq" |
| "_s8\000vorrq_u16\000vorrq_u32\000vorrq_u8\000vorrq_x\000vorrq_x_f16\000" |
| "vorrq_x_f32\000vorrq_x_s16\000vorrq_x_s32\000vorrq_x_s8\000vorrq_x_u16\000" |
| "vorrq_x_u32\000vorrq_x_u8\000vpnot\000vpselq\000vpselq_f16\000vpselq_f3" |
| "2\000vpselq_s16\000vpselq_s32\000vpselq_s64\000vpselq_s8\000vpselq_u16\000" |
| "vpselq_u32\000vpselq_u64\000vpselq_u8\000vqabsq_m\000vqabsq_m_s16\000vq" |
| "absq_m_s32\000vqabsq_m_s8\000vqabsq\000vqabsq_s16\000vqabsq_s32\000vqab" |
| "sq_s8\000vqaddq_m\000vqaddq_m_n_s16\000vqaddq_m_n_s32\000vqaddq_m_n_s8\000" |
| "vqaddq_m_n_u16\000vqaddq_m_n_u32\000vqaddq_m_n_u8\000vqaddq_m_s16\000vq" |
| "addq_m_s32\000vqaddq_m_s8\000vqaddq_m_u16\000vqaddq_m_u32\000vqaddq_m_u" |
| "8\000vqaddq\000vqaddq_n_s16\000vqaddq_n_s32\000vqaddq_n_s8\000vqaddq_n_" |
| "u16\000vqaddq_n_u32\000vqaddq_n_u8\000vqaddq_s16\000vqaddq_s32\000vqadd" |
| "q_s8\000vqaddq_u16\000vqaddq_u32\000vqaddq_u8\000vqdmladhq_m\000vqdmlad" |
| "hq_m_s16\000vqdmladhq_m_s32\000vqdmladhq_m_s8\000vqdmladhq\000vqdmladhq" |
| "_s16\000vqdmladhq_s32\000vqdmladhq_s8\000vqdmladhxq_m\000vqdmladhxq_m_s" |
| "16\000vqdmladhxq_m_s32\000vqdmladhxq_m_s8\000vqdmladhxq\000vqdmladhxq_s" |
| "16\000vqdmladhxq_s32\000vqdmladhxq_s8\000vqdmlahq_m\000vqdmlahq_m_n_s16" |
| "\000vqdmlahq_m_n_s32\000vqdmlahq_m_n_s8\000vqdmlahq\000vqdmlahq_n_s16\000" |
| "vqdmlahq_n_s32\000vqdmlahq_n_s8\000vqdmlashq_m\000vqdmlashq_m_n_s16\000" |
| "vqdmlashq_m_n_s32\000vqdmlashq_m_n_s8\000vqdmlashq\000vqdmlashq_n_s16\000" |
| "vqdmlashq_n_s32\000vqdmlashq_n_s8\000vqdmlsdhq_m\000vqdmlsdhq_m_s16\000" |
| "vqdmlsdhq_m_s32\000vqdmlsdhq_m_s8\000vqdmlsdhq\000vqdmlsdhq_s16\000vqdm" |
| "lsdhq_s32\000vqdmlsdhq_s8\000vqdmlsdhxq_m\000vqdmlsdhxq_m_s16\000vqdmls" |
| "dhxq_m_s32\000vqdmlsdhxq_m_s8\000vqdmlsdhxq\000vqdmlsdhxq_s16\000vqdmls" |
| "dhxq_s32\000vqdmlsdhxq_s8\000vqdmulhq_m\000vqdmulhq_m_n_s16\000vqdmulhq" |
| "_m_n_s32\000vqdmulhq_m_n_s8\000vqdmulhq_m_s16\000vqdmulhq_m_s32\000vqdm" |
| "ulhq_m_s8\000vqdmulhq\000vqdmulhq_n_s16\000vqdmulhq_n_s32\000vqdmulhq_n" |
| "_s8\000vqdmulhq_s16\000vqdmulhq_s32\000vqdmulhq_s8\000vqdmullbq_m\000vq" |
| "dmullbq_m_n_s16\000vqdmullbq_m_n_s32\000vqdmullbq_m_s16\000vqdmullbq_m_" |
| "s32\000vqdmullbq\000vqdmullbq_n_s16\000vqdmullbq_n_s32\000vqdmullbq_s16" |
| "\000vqdmullbq_s32\000vqdmulltq_m\000vqdmulltq_m_n_s16\000vqdmulltq_m_n_" |
| "s32\000vqdmulltq_m_s16\000vqdmulltq_m_s32\000vqdmulltq\000vqdmulltq_n_s" |
| "16\000vqdmulltq_n_s32\000vqdmulltq_s16\000vqdmulltq_s32\000vqmovnbq_m\000" |
| "vqmovnbq_m_s16\000vqmovnbq_m_s32\000vqmovnbq_m_u16\000vqmovnbq_m_u32\000" |
| "vqmovnbq\000vqmovnbq_s16\000vqmovnbq_s32\000vqmovnbq_u16\000vqmovnbq_u3" |
| "2\000vqmovntq_m\000vqmovntq_m_s16\000vqmovntq_m_s32\000vqmovntq_m_u16\000" |
| "vqmovntq_m_u32\000vqmovntq\000vqmovntq_s16\000vqmovntq_s32\000vqmovntq_" |
| "u16\000vqmovntq_u32\000vqmovunbq_m\000vqmovunbq_m_s16\000vqmovunbq_m_s3" |
| "2\000vqmovunbq\000vqmovunbq_s16\000vqmovunbq_s32\000vqmovuntq_m\000vqmo" |
| "vuntq_m_s16\000vqmovuntq_m_s32\000vqmovuntq\000vqmovuntq_s16\000vqmovun" |
| "tq_s32\000vqnegq_m\000vqnegq_m_s16\000vqnegq_m_s32\000vqnegq_m_s8\000vq" |
| "negq\000vqnegq_s16\000vqnegq_s32\000vqnegq_s8\000vqrdmladhq_m\000vqrdml" |
| "adhq_m_s16\000vqrdmladhq_m_s32\000vqrdmladhq_m_s8\000vqrdmladhq\000vqrd" |
| "mladhq_s16\000vqrdmladhq_s32\000vqrdmladhq_s8\000vqrdmladhxq_m\000vqrdm" |
| "ladhxq_m_s16\000vqrdmladhxq_m_s32\000vqrdmladhxq_m_s8\000vqrdmladhxq\000" |
| "vqrdmladhxq_s16\000vqrdmladhxq_s32\000vqrdmladhxq_s8\000vqrdmlahq_m\000" |
| "vqrdmlahq_m_n_s16\000vqrdmlahq_m_n_s32\000vqrdmlahq_m_n_s8\000vqrdmlahq" |
| "\000vqrdmlahq_n_s16\000vqrdmlahq_n_s32\000vqrdmlahq_n_s8\000vqrdmlashq_" |
| "m\000vqrdmlashq_m_n_s16\000vqrdmlashq_m_n_s32\000vqrdmlashq_m_n_s8\000v" |
| "qrdmlashq\000vqrdmlashq_n_s16\000vqrdmlashq_n_s32\000vqrdmlashq_n_s8\000" |
| "vqrdmlsdhq_m\000vqrdmlsdhq_m_s16\000vqrdmlsdhq_m_s32\000vqrdmlsdhq_m_s8" |
| "\000vqrdmlsdhq\000vqrdmlsdhq_s16\000vqrdmlsdhq_s32\000vqrdmlsdhq_s8\000" |
| "vqrdmlsdhxq_m\000vqrdmlsdhxq_m_s16\000vqrdmlsdhxq_m_s32\000vqrdmlsdhxq_" |
| "m_s8\000vqrdmlsdhxq\000vqrdmlsdhxq_s16\000vqrdmlsdhxq_s32\000vqrdmlsdhx" |
| "q_s8\000vqrdmulhq_m\000vqrdmulhq_m_n_s16\000vqrdmulhq_m_n_s32\000vqrdmu" |
| "lhq_m_n_s8\000vqrdmulhq_m_s16\000vqrdmulhq_m_s32\000vqrdmulhq_m_s8\000v" |
| "qrdmulhq\000vqrdmulhq_n_s16\000vqrdmulhq_n_s32\000vqrdmulhq_n_s8\000vqr" |
| "dmulhq_s16\000vqrdmulhq_s32\000vqrdmulhq_s8\000vqrshlq_m_n\000vqrshlq_m" |
| "_n_s16\000vqrshlq_m_n_s32\000vqrshlq_m_n_s8\000vqrshlq_m_n_u16\000vqrsh" |
| "lq_m_n_u32\000vqrshlq_m_n_u8\000vqrshlq_m\000vqrshlq_m_s16\000vqrshlq_m" |
| "_s32\000vqrshlq_m_s8\000vqrshlq_m_u16\000vqrshlq_m_u32\000vqrshlq_m_u8\000" |
| "vqrshlq\000vqrshlq_n_s16\000vqrshlq_n_s32\000vqrshlq_n_s8\000vqrshlq_n_" |
| "u16\000vqrshlq_n_u32\000vqrshlq_n_u8\000vqrshlq_s16\000vqrshlq_s32\000v" |
| "qrshlq_s8\000vqrshlq_u16\000vqrshlq_u32\000vqrshlq_u8\000vqrshrnbq_m\000" |
| "vqrshrnbq_m_n_s16\000vqrshrnbq_m_n_s32\000vqrshrnbq_m_n_u16\000vqrshrnb" |
| "q_m_n_u32\000vqrshrnbq\000vqrshrnbq_n_s16\000vqrshrnbq_n_s32\000vqrshrn" |
| "bq_n_u16\000vqrshrnbq_n_u32\000vqrshrntq_m\000vqrshrntq_m_n_s16\000vqrs" |
| "hrntq_m_n_s32\000vqrshrntq_m_n_u16\000vqrshrntq_m_n_u32\000vqrshrntq\000" |
| "vqrshrntq_n_s16\000vqrshrntq_n_s32\000vqrshrntq_n_u16\000vqrshrntq_n_u3" |
| "2\000vqrshrunbq_m\000vqrshrunbq_m_n_s16\000vqrshrunbq_m_n_s32\000vqrshr" |
| "unbq\000vqrshrunbq_n_s16\000vqrshrunbq_n_s32\000vqrshruntq_m\000vqrshru" |
| "ntq_m_n_s16\000vqrshruntq_m_n_s32\000vqrshruntq\000vqrshruntq_n_s16\000" |
| "vqrshruntq_n_s32\000vqshlq_m_n\000vqshlq_m_n_s16\000vqshlq_m_n_s32\000v" |
| "qshlq_m_n_s8\000vqshlq_m_n_u16\000vqshlq_m_n_u32\000vqshlq_m_n_u8\000vq" |
| "shlq_m_r\000vqshlq_m_r_s16\000vqshlq_m_r_s32\000vqshlq_m_r_s8\000vqshlq" |
| "_m_r_u16\000vqshlq_m_r_u32\000vqshlq_m_r_u8\000vqshlq_m\000vqshlq_m_s16" |
| "\000vqshlq_m_s32\000vqshlq_m_s8\000vqshlq_m_u16\000vqshlq_m_u32\000vqsh" |
| "lq_m_u8\000vqshlq_n\000vqshlq_n_s16\000vqshlq_n_s32\000vqshlq_n_s8\000v" |
| "qshlq_n_u16\000vqshlq_n_u32\000vqshlq_n_u8\000vqshlq_r\000vqshlq_r_s16\000" |
| "vqshlq_r_s32\000vqshlq_r_s8\000vqshlq_r_u16\000vqshlq_r_u32\000vqshlq_r" |
| "_u8\000vqshlq\000vqshlq_s16\000vqshlq_s32\000vqshlq_s8\000vqshlq_u16\000" |
| "vqshlq_u32\000vqshlq_u8\000vqshluq_m\000vqshluq_m_n_s16\000vqshluq_m_n_" |
| "s32\000vqshluq_m_n_s8\000vqshluq\000vqshluq_n_s16\000vqshluq_n_s32\000v" |
| "qshluq_n_s8\000vqshrnbq_m\000vqshrnbq_m_n_s16\000vqshrnbq_m_n_s32\000vq" |
| "shrnbq_m_n_u16\000vqshrnbq_m_n_u32\000vqshrnbq\000vqshrnbq_n_s16\000vqs" |
| "hrnbq_n_s32\000vqshrnbq_n_u16\000vqshrnbq_n_u32\000vqshrntq_m\000vqshrn" |
| "tq_m_n_s16\000vqshrntq_m_n_s32\000vqshrntq_m_n_u16\000vqshrntq_m_n_u32\000" |
| "vqshrntq\000vqshrntq_n_s16\000vqshrntq_n_s32\000vqshrntq_n_u16\000vqshr" |
| "ntq_n_u32\000vqshrunbq_m\000vqshrunbq_m_n_s16\000vqshrunbq_m_n_s32\000v" |
| "qshrunbq\000vqshrunbq_n_s16\000vqshrunbq_n_s32\000vqshruntq_m\000vqshru" |
| "ntq_m_n_s16\000vqshruntq_m_n_s32\000vqshruntq\000vqshruntq_n_s16\000vqs" |
| "hruntq_n_s32\000vqsubq_m\000vqsubq_m_n_s16\000vqsubq_m_n_s32\000vqsubq_" |
| "m_n_s8\000vqsubq_m_n_u16\000vqsubq_m_n_u32\000vqsubq_m_n_u8\000vqsubq_m" |
| "_s16\000vqsubq_m_s32\000vqsubq_m_s8\000vqsubq_m_u16\000vqsubq_m_u32\000" |
| "vqsubq_m_u8\000vqsubq\000vqsubq_n_s16\000vqsubq_n_s32\000vqsubq_n_s8\000" |
| "vqsubq_n_u16\000vqsubq_n_u32\000vqsubq_n_u8\000vqsubq_s16\000vqsubq_s32" |
| "\000vqsubq_s8\000vqsubq_u16\000vqsubq_u32\000vqsubq_u8\000vreinterpretq" |
| "_f16\000vreinterpretq_f16_f32\000vreinterpretq_f16_s16\000vreinterpretq" |
| "_f16_s32\000vreinterpretq_f16_s64\000vreinterpretq_f16_s8\000vreinterpr" |
| "etq_f16_u16\000vreinterpretq_f16_u32\000vreinterpretq_f16_u64\000vreint" |
| "erpretq_f16_u8\000vreinterpretq_f32\000vreinterpretq_f32_f16\000vreinte" |
| "rpretq_f32_s16\000vreinterpretq_f32_s32\000vreinterpretq_f32_s64\000vre" |
| "interpretq_f32_s8\000vreinterpretq_f32_u16\000vreinterpretq_f32_u32\000" |
| "vreinterpretq_f32_u64\000vreinterpretq_f32_u8\000vreinterpretq_s16\000v" |
| "reinterpretq_s16_f16\000vreinterpretq_s16_f32\000vreinterpretq_s16_s32\000" |
| "vreinterpretq_s16_s64\000vreinterpretq_s16_s8\000vreinterpretq_s16_u16\000" |
| "vreinterpretq_s16_u32\000vreinterpretq_s16_u64\000vreinterpretq_s16_u8\000" |
| "vreinterpretq_s32\000vreinterpretq_s32_f16\000vreinterpretq_s32_f32\000" |
| "vreinterpretq_s32_s16\000vreinterpretq_s32_s64\000vreinterpretq_s32_s8\000" |
| "vreinterpretq_s32_u16\000vreinterpretq_s32_u32\000vreinterpretq_s32_u64" |
| "\000vreinterpretq_s32_u8\000vreinterpretq_s64\000vreinterpretq_s64_f16\000" |
| "vreinterpretq_s64_f32\000vreinterpretq_s64_s16\000vreinterpretq_s64_s32" |
| "\000vreinterpretq_s64_s8\000vreinterpretq_s64_u16\000vreinterpretq_s64_" |
| "u32\000vreinterpretq_s64_u64\000vreinterpretq_s64_u8\000vreinterpretq_s" |
| "8\000vreinterpretq_s8_f16\000vreinterpretq_s8_f32\000vreinterpretq_s8_s" |
| "16\000vreinterpretq_s8_s32\000vreinterpretq_s8_s64\000vreinterpretq_s8_" |
| "u16\000vreinterpretq_s8_u32\000vreinterpretq_s8_u64\000vreinterpretq_s8" |
| "_u8\000vreinterpretq_u16\000vreinterpretq_u16_f16\000vreinterpretq_u16_" |
| "f32\000vreinterpretq_u16_s16\000vreinterpretq_u16_s32\000vreinterpretq_" |
| "u16_s64\000vreinterpretq_u16_s8\000vreinterpretq_u16_u32\000vreinterpre" |
| "tq_u16_u64\000vreinterpretq_u16_u8\000vreinterpretq_u32\000vreinterpret" |
| "q_u32_f16\000vreinterpretq_u32_f32\000vreinterpretq_u32_s16\000vreinter" |
| "pretq_u32_s32\000vreinterpretq_u32_s64\000vreinterpretq_u32_s8\000vrein" |
| "terpretq_u32_u16\000vreinterpretq_u32_u64\000vreinterpretq_u32_u8\000vr" |
| "einterpretq_u64\000vreinterpretq_u64_f16\000vreinterpretq_u64_f32\000vr" |
| "einterpretq_u64_s16\000vreinterpretq_u64_s32\000vreinterpretq_u64_s64\000" |
| "vreinterpretq_u64_s8\000vreinterpretq_u64_u16\000vreinterpretq_u64_u32\000" |
| "vreinterpretq_u64_u8\000vreinterpretq_u8\000vreinterpretq_u8_f16\000vre" |
| "interpretq_u8_f32\000vreinterpretq_u8_s16\000vreinterpretq_u8_s32\000vr" |
| "einterpretq_u8_s64\000vreinterpretq_u8_s8\000vreinterpretq_u8_u16\000vr" |
| "einterpretq_u8_u32\000vreinterpretq_u8_u64\000vrev16q_m\000vrev16q_m_s8" |
| "\000vrev16q_m_u8\000vrev16q\000vrev16q_s8\000vrev16q_u8\000vrev16q_x\000" |
| "vrev16q_x_s8\000vrev16q_x_u8\000vrev32q\000vrev32q_f16\000vrev32q_m\000" |
| "vrev32q_m_f16\000vrev32q_m_s16\000vrev32q_m_s8\000vrev32q_m_u16\000vrev" |
| "32q_m_u8\000vrev32q_s16\000vrev32q_s8\000vrev32q_u16\000vrev32q_u8\000v" |
| "rev32q_x\000vrev32q_x_f16\000vrev32q_x_s16\000vrev32q_x_s8\000vrev32q_x" |
| "_u16\000vrev32q_x_u8\000vrev64q\000vrev64q_f16\000vrev64q_f32\000vrev64" |
| "q_m\000vrev64q_m_f16\000vrev64q_m_f32\000vrev64q_m_s16\000vrev64q_m_s32" |
| "\000vrev64q_m_s8\000vrev64q_m_u16\000vrev64q_m_u32\000vrev64q_m_u8\000v" |
| "rev64q_s16\000vrev64q_s32\000vrev64q_s8\000vrev64q_u16\000vrev64q_u32\000" |
| "vrev64q_u8\000vrev64q_x\000vrev64q_x_f16\000vrev64q_x_f32\000vrev64q_x_" |
| "s16\000vrev64q_x_s32\000vrev64q_x_s8\000vrev64q_x_u16\000vrev64q_x_u32\000" |
| "vrev64q_x_u8\000vrhaddq_m\000vrhaddq_m_s16\000vrhaddq_m_s32\000vrhaddq_" |
| "m_s8\000vrhaddq_m_u16\000vrhaddq_m_u32\000vrhaddq_m_u8\000vrhaddq\000vr" |
| "haddq_s16\000vrhaddq_s32\000vrhaddq_s8\000vrhaddq_u16\000vrhaddq_u32\000" |
| "vrhaddq_u8\000vrhaddq_x\000vrhaddq_x_s16\000vrhaddq_x_s32\000vrhaddq_x_" |
| "s8\000vrhaddq_x_u16\000vrhaddq_x_u32\000vrhaddq_x_u8\000vrmlaldavhaq_p\000" |
| "vrmlaldavhaq_p_s32\000vrmlaldavhaq_p_u32\000vrmlaldavhaq\000vrmlaldavha" |
| "q_s32\000vrmlaldavhaq_u32\000vrmlaldavhaxq_p\000vrmlaldavhaxq_p_s32\000" |
| "vrmlaldavhaxq\000vrmlaldavhaxq_s32\000vrmlaldavhq_p\000vrmlaldavhq_p_s3" |
| "2\000vrmlaldavhq_p_u32\000vrmlaldavhq\000vrmlaldavhq_s32\000vrmlaldavhq" |
| "_u32\000vrmlaldavhxq_p\000vrmlaldavhxq_p_s32\000vrmlaldavhxq\000vrmlald" |
| "avhxq_s32\000vrmlsldavhaq_p\000vrmlsldavhaq_p_s32\000vrmlsldavhaq\000vr" |
| "mlsldavhaq_s32\000vrmlsldavhaxq_p\000vrmlsldavhaxq_p_s32\000vrmlsldavha" |
| "xq\000vrmlsldavhaxq_s32\000vrmlsldavhq_p\000vrmlsldavhq_p_s32\000vrmlsl" |
| "davhq\000vrmlsldavhq_s32\000vrmlsldavhxq_p\000vrmlsldavhxq_p_s32\000vrm" |
| "lsldavhxq\000vrmlsldavhxq_s32\000vrmulhq_m\000vrmulhq_m_s16\000vrmulhq_" |
| "m_s32\000vrmulhq_m_s8\000vrmulhq_m_u16\000vrmulhq_m_u32\000vrmulhq_m_u8" |
| "\000vrmulhq\000vrmulhq_s16\000vrmulhq_s32\000vrmulhq_s8\000vrmulhq_u16\000" |
| "vrmulhq_u32\000vrmulhq_u8\000vrmulhq_x\000vrmulhq_x_s16\000vrmulhq_x_s3" |
| "2\000vrmulhq_x_s8\000vrmulhq_x_u16\000vrmulhq_x_u32\000vrmulhq_x_u8\000" |
| "vrndaq\000vrndaq_f16\000vrndaq_f32\000vrndaq_m\000vrndaq_m_f16\000vrnda" |
| "q_m_f32\000vrndaq_x\000vrndaq_x_f16\000vrndaq_x_f32\000vrndmq\000vrndmq" |
| "_f16\000vrndmq_f32\000vrndmq_m\000vrndmq_m_f16\000vrndmq_m_f32\000vrndm" |
| "q_x\000vrndmq_x_f16\000vrndmq_x_f32\000vrndnq\000vrndnq_f16\000vrndnq_f" |
| "32\000vrndnq_m\000vrndnq_m_f16\000vrndnq_m_f32\000vrndnq_x\000vrndnq_x_" |
| "f16\000vrndnq_x_f32\000vrndpq\000vrndpq_f16\000vrndpq_f32\000vrndpq_m\000" |
| "vrndpq_m_f16\000vrndpq_m_f32\000vrndpq_x\000vrndpq_x_f16\000vrndpq_x_f3" |
| "2\000vrndq\000vrndq_f16\000vrndq_f32\000vrndq_m\000vrndq_m_f16\000vrndq" |
| "_m_f32\000vrndq_x\000vrndq_x_f16\000vrndq_x_f32\000vrndxq\000vrndxq_f16" |
| "\000vrndxq_f32\000vrndxq_m\000vrndxq_m_f16\000vrndxq_m_f32\000vrndxq_x\000" |
| "vrndxq_x_f16\000vrndxq_x_f32\000vrshlq_m_n\000vrshlq_m_n_s16\000vrshlq_" |
| "m_n_s32\000vrshlq_m_n_s8\000vrshlq_m_n_u16\000vrshlq_m_n_u32\000vrshlq_" |
| "m_n_u8\000vrshlq_m\000vrshlq_m_s16\000vrshlq_m_s32\000vrshlq_m_s8\000vr" |
| "shlq_m_u16\000vrshlq_m_u32\000vrshlq_m_u8\000vrshlq\000vrshlq_n_s16\000" |
| "vrshlq_n_s32\000vrshlq_n_s8\000vrshlq_n_u16\000vrshlq_n_u32\000vrshlq_n" |
| "_u8\000vrshlq_s16\000vrshlq_s32\000vrshlq_s8\000vrshlq_u16\000vrshlq_u3" |
| "2\000vrshlq_u8\000vrshlq_x\000vrshlq_x_s16\000vrshlq_x_s32\000vrshlq_x_" |
| "s8\000vrshlq_x_u16\000vrshlq_x_u32\000vrshlq_x_u8\000vrshrnbq_m\000vrsh" |
| "rnbq_m_n_s16\000vrshrnbq_m_n_s32\000vrshrnbq_m_n_u16\000vrshrnbq_m_n_u3" |
| "2\000vrshrnbq\000vrshrnbq_n_s16\000vrshrnbq_n_s32\000vrshrnbq_n_u16\000" |
| "vrshrnbq_n_u32\000vrshrntq_m\000vrshrntq_m_n_s16\000vrshrntq_m_n_s32\000" |
| "vrshrntq_m_n_u16\000vrshrntq_m_n_u32\000vrshrntq\000vrshrntq_n_s16\000v" |
| "rshrntq_n_s32\000vrshrntq_n_u16\000vrshrntq_n_u32\000vrshrq_m\000vrshrq" |
| "_m_n_s16\000vrshrq_m_n_s32\000vrshrq_m_n_s8\000vrshrq_m_n_u16\000vrshrq" |
| "_m_n_u32\000vrshrq_m_n_u8\000vrshrq\000vrshrq_n_s16\000vrshrq_n_s32\000" |
| "vrshrq_n_s8\000vrshrq_n_u16\000vrshrq_n_u32\000vrshrq_n_u8\000vrshrq_x\000" |
| "vrshrq_x_n_s16\000vrshrq_x_n_s32\000vrshrq_x_n_s8\000vrshrq_x_n_u16\000" |
| "vrshrq_x_n_u32\000vrshrq_x_n_u8\000vsbciq_m\000vsbciq_m_s32\000vsbciq_m" |
| "_u32\000vsbciq\000vsbciq_s32\000vsbciq_u32\000vsbcq_m\000vsbcq_m_s32\000" |
| "vsbcq_m_u32\000vsbcq\000vsbcq_s32\000vsbcq_u32\000vsetq_lane\000vsetq_l" |
| "ane_f16\000vsetq_lane_f32\000vsetq_lane_s16\000vsetq_lane_s32\000vsetq_" |
| "lane_s64\000vsetq_lane_s8\000vsetq_lane_u16\000vsetq_lane_u32\000vsetq_" |
| "lane_u64\000vsetq_lane_u8\000vshlcq_m\000vshlcq_m_s16\000vshlcq_m_s32\000" |
| "vshlcq_m_s8\000vshlcq_m_u16\000vshlcq_m_u32\000vshlcq_m_u8\000vshlcq\000" |
| "vshlcq_s16\000vshlcq_s32\000vshlcq_s8\000vshlcq_u16\000vshlcq_u32\000vs" |
| "hlcq_u8\000vshllbq_m\000vshllbq_m_n_s16\000vshllbq_m_n_s8\000vshllbq_m_" |
| "n_u16\000vshllbq_m_n_u8\000vshllbq\000vshllbq_n_s16\000vshllbq_n_s8\000" |
| "vshllbq_n_u16\000vshllbq_n_u8\000vshllbq_x\000vshllbq_x_n_s16\000vshllb" |
| "q_x_n_s8\000vshllbq_x_n_u16\000vshllbq_x_n_u8\000vshlltq_m\000vshlltq_m" |
| "_n_s16\000vshlltq_m_n_s8\000vshlltq_m_n_u16\000vshlltq_m_n_u8\000vshllt" |
| "q\000vshlltq_n_s16\000vshlltq_n_s8\000vshlltq_n_u16\000vshlltq_n_u8\000" |
| "vshlltq_x\000vshlltq_x_n_s16\000vshlltq_x_n_s8\000vshlltq_x_n_u16\000vs" |
| "hlltq_x_n_u8\000vshlq_m_n\000vshlq_m_n_s16\000vshlq_m_n_s32\000vshlq_m_" |
| "n_s8\000vshlq_m_n_u16\000vshlq_m_n_u32\000vshlq_m_n_u8\000vshlq_m_r\000" |
| "vshlq_m_r_s16\000vshlq_m_r_s32\000vshlq_m_r_s8\000vshlq_m_r_u16\000vshl" |
| "q_m_r_u32\000vshlq_m_r_u8\000vshlq_m\000vshlq_m_s16\000vshlq_m_s32\000v" |
| "shlq_m_s8\000vshlq_m_u16\000vshlq_m_u32\000vshlq_m_u8\000vshlq_n\000vsh" |
| "lq_n_s16\000vshlq_n_s32\000vshlq_n_s8\000vshlq_n_u16\000vshlq_n_u32\000" |
| "vshlq_n_u8\000vshlq_r\000vshlq_r_s16\000vshlq_r_s32\000vshlq_r_s8\000vs" |
| "hlq_r_u16\000vshlq_r_u32\000vshlq_r_u8\000vshlq\000vshlq_s16\000vshlq_s" |
| "32\000vshlq_s8\000vshlq_u16\000vshlq_u32\000vshlq_u8\000vshlq_x_n\000vs" |
| "hlq_x_n_s16\000vshlq_x_n_s32\000vshlq_x_n_s8\000vshlq_x_n_u16\000vshlq_" |
| "x_n_u32\000vshlq_x_n_u8\000vshlq_x\000vshlq_x_s16\000vshlq_x_s32\000vsh" |
| "lq_x_s8\000vshlq_x_u16\000vshlq_x_u32\000vshlq_x_u8\000vshrnbq_m\000vsh" |
| "rnbq_m_n_s16\000vshrnbq_m_n_s32\000vshrnbq_m_n_u16\000vshrnbq_m_n_u32\000" |
| "vshrnbq\000vshrnbq_n_s16\000vshrnbq_n_s32\000vshrnbq_n_u16\000vshrnbq_n" |
| "_u32\000vshrntq_m\000vshrntq_m_n_s16\000vshrntq_m_n_s32\000vshrntq_m_n_" |
| "u16\000vshrntq_m_n_u32\000vshrntq\000vshrntq_n_s16\000vshrntq_n_s32\000" |
| "vshrntq_n_u16\000vshrntq_n_u32\000vshrq_m\000vshrq_m_n_s16\000vshrq_m_n" |
| "_s32\000vshrq_m_n_s8\000vshrq_m_n_u16\000vshrq_m_n_u32\000vshrq_m_n_u8\000" |
| "vshrq\000vshrq_n_s16\000vshrq_n_s32\000vshrq_n_s8\000vshrq_n_u16\000vsh" |
| "rq_n_u32\000vshrq_n_u8\000vshrq_x\000vshrq_x_n_s16\000vshrq_x_n_s32\000" |
| "vshrq_x_n_s8\000vshrq_x_n_u16\000vshrq_x_n_u32\000vshrq_x_n_u8\000vsliq" |
| "_m\000vsliq_m_n_s16\000vsliq_m_n_s32\000vsliq_m_n_s8\000vsliq_m_n_u16\000" |
| "vsliq_m_n_u32\000vsliq_m_n_u8\000vsliq\000vsliq_n_s16\000vsliq_n_s32\000" |
| "vsliq_n_s8\000vsliq_n_u16\000vsliq_n_u32\000vsliq_n_u8\000vsriq_m\000vs" |
| "riq_m_n_s16\000vsriq_m_n_s32\000vsriq_m_n_s8\000vsriq_m_n_u16\000vsriq_" |
| "m_n_u32\000vsriq_m_n_u8\000vsriq\000vsriq_n_s16\000vsriq_n_s32\000vsriq" |
| "_n_s8\000vsriq_n_u16\000vsriq_n_u32\000vsriq_n_u8\000vst1q\000vst1q_f16" |
| "\000vst1q_f32\000vst1q_p\000vst1q_p_f16\000vst1q_p_f32\000vst1q_p_s16\000" |
| "vst1q_p_s32\000vst1q_p_s8\000vst1q_p_u16\000vst1q_p_u32\000vst1q_p_u8\000" |
| "vst1q_s16\000vst1q_s32\000vst1q_s8\000vst1q_u16\000vst1q_u32\000vst1q_u" |
| "8\000vst2q\000vst2q_f16\000vst2q_f32\000vst2q_s16\000vst2q_s32\000vst2q" |
| "_s8\000vst2q_u16\000vst2q_u32\000vst2q_u8\000vst4q\000vst4q_f16\000vst4" |
| "q_f32\000vst4q_s16\000vst4q_s32\000vst4q_s8\000vst4q_u16\000vst4q_u32\000" |
| "vst4q_u8\000vstrbq_p\000vstrbq_p_s16\000vstrbq_p_s32\000vstrbq_p_s8\000" |
| "vstrbq_p_u16\000vstrbq_p_u32\000vstrbq_p_u8\000vstrbq\000vstrbq_s16\000" |
| "vstrbq_s32\000vstrbq_s8\000vstrbq_scatter_offset_p\000vstrbq_scatter_of" |
| "fset_p_s16\000vstrbq_scatter_offset_p_s32\000vstrbq_scatter_offset_p_s8" |
| "\000vstrbq_scatter_offset_p_u16\000vstrbq_scatter_offset_p_u32\000vstrb" |
| "q_scatter_offset_p_u8\000vstrbq_scatter_offset\000vstrbq_scatter_offset" |
| "_s16\000vstrbq_scatter_offset_s32\000vstrbq_scatter_offset_s8\000vstrbq" |
| "_scatter_offset_u16\000vstrbq_scatter_offset_u32\000vstrbq_scatter_offs" |
| "et_u8\000vstrbq_u16\000vstrbq_u32\000vstrbq_u8\000vstrdq_scatter_base_p" |
| "\000vstrdq_scatter_base_p_s64\000vstrdq_scatter_base_p_u64\000vstrdq_sc" |
| "atter_base\000vstrdq_scatter_base_s64\000vstrdq_scatter_base_u64\000vst" |
| "rdq_scatter_base_wb_p\000vstrdq_scatter_base_wb_p_s64\000vstrdq_scatter" |
| "_base_wb_p_u64\000vstrdq_scatter_base_wb\000vstrdq_scatter_base_wb_s64\000" |
| "vstrdq_scatter_base_wb_u64\000vstrdq_scatter_offset_p\000vstrdq_scatter" |
| "_offset_p_s64\000vstrdq_scatter_offset_p_u64\000vstrdq_scatter_offset\000" |
| "vstrdq_scatter_offset_s64\000vstrdq_scatter_offset_u64\000vstrdq_scatte" |
| "r_shifted_offset_p\000vstrdq_scatter_shifted_offset_p_s64\000vstrdq_sca" |
| "tter_shifted_offset_p_u64\000vstrdq_scatter_shifted_offset\000vstrdq_sc" |
| "atter_shifted_offset_s64\000vstrdq_scatter_shifted_offset_u64\000vstrhq" |
| "\000vstrhq_f16\000vstrhq_p\000vstrhq_p_f16\000vstrhq_p_s16\000vstrhq_p_" |
| "s32\000vstrhq_p_u16\000vstrhq_p_u32\000vstrhq_s16\000vstrhq_s32\000vstr" |
| "hq_scatter_offset\000vstrhq_scatter_offset_f16\000vstrhq_scatter_offset" |
| "_p\000vstrhq_scatter_offset_p_f16\000vstrhq_scatter_offset_p_s16\000vst" |
| "rhq_scatter_offset_p_s32\000vstrhq_scatter_offset_p_u16\000vstrhq_scatt" |
| "er_offset_p_u32\000vstrhq_scatter_offset_s16\000vstrhq_scatter_offset_s" |
| "32\000vstrhq_scatter_offset_u16\000vstrhq_scatter_offset_u32\000vstrhq_" |
| "scatter_shifted_offset\000vstrhq_scatter_shifted_offset_f16\000vstrhq_s" |
| "catter_shifted_offset_p\000vstrhq_scatter_shifted_offset_p_f16\000vstrh" |
| "q_scatter_shifted_offset_p_s16\000vstrhq_scatter_shifted_offset_p_s32\000" |
| "vstrhq_scatter_shifted_offset_p_u16\000vstrhq_scatter_shifted_offset_p_" |
| "u32\000vstrhq_scatter_shifted_offset_s16\000vstrhq_scatter_shifted_offs" |
| "et_s32\000vstrhq_scatter_shifted_offset_u16\000vstrhq_scatter_shifted_o" |
| "ffset_u32\000vstrhq_u16\000vstrhq_u32\000vstrwq\000vstrwq_f32\000vstrwq" |
| "_p\000vstrwq_p_f32\000vstrwq_p_s32\000vstrwq_p_u32\000vstrwq_s32\000vst" |
| "rwq_scatter_base\000vstrwq_scatter_base_f32\000vstrwq_scatter_base_p\000" |
| "vstrwq_scatter_base_p_f32\000vstrwq_scatter_base_p_s32\000vstrwq_scatte" |
| "r_base_p_u32\000vstrwq_scatter_base_s32\000vstrwq_scatter_base_u32\000v" |
| "strwq_scatter_base_wb\000vstrwq_scatter_base_wb_f32\000vstrwq_scatter_b" |
| "ase_wb_p\000vstrwq_scatter_base_wb_p_f32\000vstrwq_scatter_base_wb_p_s3" |
| "2\000vstrwq_scatter_base_wb_p_u32\000vstrwq_scatter_base_wb_s32\000vstr" |
| "wq_scatter_base_wb_u32\000vstrwq_scatter_offset\000vstrwq_scatter_offse" |
| "t_f32\000vstrwq_scatter_offset_p\000vstrwq_scatter_offset_p_f32\000vstr" |
| "wq_scatter_offset_p_s32\000vstrwq_scatter_offset_p_u32\000vstrwq_scatte" |
| "r_offset_s32\000vstrwq_scatter_offset_u32\000vstrwq_scatter_shifted_off" |
| "set\000vstrwq_scatter_shifted_offset_f32\000vstrwq_scatter_shifted_offs" |
| "et_p\000vstrwq_scatter_shifted_offset_p_f32\000vstrwq_scatter_shifted_o" |
| "ffset_p_s32\000vstrwq_scatter_shifted_offset_p_u32\000vstrwq_scatter_sh" |
| "ifted_offset_s32\000vstrwq_scatter_shifted_offset_u32\000vstrwq_u32\000" |
| "vsubq\000vsubq_f16\000vsubq_f32\000vsubq_m\000vsubq_m_f16\000vsubq_m_f3" |
| "2\000vsubq_m_n_f16\000vsubq_m_n_f32\000vsubq_m_n_s16\000vsubq_m_n_s32\000" |
| "vsubq_m_n_s8\000vsubq_m_n_u16\000vsubq_m_n_u32\000vsubq_m_n_u8\000vsubq" |
| "_m_s16\000vsubq_m_s32\000vsubq_m_s8\000vsubq_m_u16\000vsubq_m_u32\000vs" |
| "ubq_m_u8\000vsubq_n_f16\000vsubq_n_f32\000vsubq_n_s16\000vsubq_n_s32\000" |
| "vsubq_n_s8\000vsubq_n_u16\000vsubq_n_u32\000vsubq_n_u8\000vsubq_s16\000" |
| "vsubq_s32\000vsubq_s8\000vsubq_u16\000vsubq_u32\000vsubq_u8\000vsubq_x\000" |
| "vsubq_x_f16\000vsubq_x_f32\000vsubq_x_n_f16\000vsubq_x_n_f32\000vsubq_x" |
| "_n_s16\000vsubq_x_n_s32\000vsubq_x_n_s8\000vsubq_x_n_u16\000vsubq_x_n_u" |
| "32\000vsubq_x_n_u8\000vsubq_x_s16\000vsubq_x_s32\000vsubq_x_s8\000vsubq" |
| "_x_u16\000vsubq_x_u32\000vsubq_x_u8\000vuninitializedq_f16\000vuninitia" |
| "lizedq_f32\000vuninitializedq\000vuninitializedq_polymorphic_f16\000vun" |
| "initializedq_polymorphic_f32\000vuninitializedq_polymorphic_s16\000vuni" |
| "nitializedq_polymorphic_s32\000vuninitializedq_polymorphic_s64\000vunin" |
| "itializedq_polymorphic_s8\000vuninitializedq_polymorphic_u16\000vuninit" |
| "ializedq_polymorphic_u32\000vuninitializedq_polymorphic_u64\000vuniniti" |
| "alizedq_polymorphic_u8\000vuninitializedq_s16\000vuninitializedq_s32\000" |
| "vuninitializedq_s64\000vuninitializedq_s8\000vuninitializedq_u16\000vun" |
| "initializedq_u32\000vuninitializedq_u64\000vuninitializedq_u8\000"}; |
| |
