Snap for 10453563 from 9df12251ffa5aab3bf744c16004a0faffd796d41 to mainline-rkpd-release
Change-Id: Ic725b8656c231eecbb99ab17d1422557a83393fa
diff --git a/gralloc4/src/core/format_info.cpp b/gralloc4/src/core/format_info.cpp
index d27d204..14a1d84 100644
--- a/gralloc4/src/core/format_info.cpp
+++ b/gralloc4/src/core/format_info.cpp
@@ -128,7 +128,7 @@
/* BEGIN ALIGNED SECTION */
/* TODO(b/189467474) AFBC disabled on the GPU for RGB_565 due to color swap in Vulkan */
{ .id = MALI_GRALLOC_FORMAT_INTERNAL_RGB_565, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_NONE, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, },
- { .id = MALI_GRALLOC_FORMAT_INTERNAL_RGB_888, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_LIN, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, },
+ { .id = MALI_GRALLOC_FORMAT_INTERNAL_RGB_888, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_LIN, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_LIN, },
{ .id = MALI_GRALLOC_FORMAT_INTERNAL_RGBA_8888, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_LIN, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_LIN, .vpu_wr = F_NONE, .cam_wr = F_LIN, },
{ .id = MALI_GRALLOC_FORMAT_INTERNAL_BGRA_8888, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_wr = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_NONE, .cam_wr = F_NONE, },
{ .id = MALI_GRALLOC_FORMAT_INTERNAL_RGBX_8888, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, },
diff --git a/gralloc4/src/core/mali_gralloc_bufferallocation.cpp b/gralloc4/src/core/mali_gralloc_bufferallocation.cpp
index 7355930..289db0b 100644
--- a/gralloc4/src/core/mali_gralloc_bufferallocation.cpp
+++ b/gralloc4/src/core/mali_gralloc_bufferallocation.cpp
@@ -450,20 +450,14 @@
uint32_t stride_align,
uint32_t * byte_stride)
{
- if (plane == 0)
- {
- *byte_stride = GRALLOC_ALIGN(luma_stride, GRALLOC_ALIGN(stride_align, 32));
- }
- else
- {
- /*
- * Derive chroma stride from luma and verify it is:
- * 1. Aligned to "1/2*lcm(hw_align, cpu_align)"
- * 2. Multiple of 16px (16 bytes)
- */
- *byte_stride = luma_stride / 2;
- assert(*byte_stride == GRALLOC_ALIGN(*byte_stride, GRALLOC_ALIGN(stride_align / 2, 16)));
- assert(*byte_stride & 15 == 0);
+ // https://developer.android.com/reference/android/graphics/ImageFormat#YV12
+ if (plane == 0) {
+ // stride_align has to be honored as GPU alignment still requires the format to be
+ // 64 bytes aligned. Though that does not break the contract as long as the
+ // horizontal stride for chroma is half the luma stride and aligned to 16.
+ *byte_stride = GRALLOC_ALIGN(luma_stride, GRALLOC_ALIGN(stride_align, 16));
+ } else {
+ *byte_stride = GRALLOC_ALIGN(luma_stride / 2, 16);
}
}
#endif
@@ -647,10 +641,10 @@
/*
* Update YV12 stride with both CPU & HW usage due to constraint of chroma stride.
* Width is anyway aligned to 16px for luma and chroma (has_cpu_usage).
- *
- * Note: To prevent luma stride misalignment with GPU stride alignment.
- * The luma plane will maintain the same `stride` size, and the chroma plane
- * will align to `stride/2`.
+ *
+ * Note: To prevent luma stride misalignment with GPU stride alignment.
+ * The luma plane will maintain the same `stride` size, and the chroma plane
+ * will align to `stride/2`.
*/
if (format.id == MALI_GRALLOC_FORMAT_INTERNAL_YV12 && has_hw_usage && has_cpu_usage)
{
