| /* |
| * ALSA driver for RME Hammerfall DSP MADI audio interface(s) |
| * |
| * Copyright (c) 2003 Winfried Ritsch (IEM) |
| * code based on hdsp.c Paul Davis |
| * Marcus Andersson |
| * Thomas Charbonnel |
| * Modified 2006-06-01 for AES32 support by Remy Bruno |
| * <remy.bruno@trinnov.com> |
| * |
| * Modified 2009-04-13 for proper metering by Florian Faber |
| * <faber@faberman.de> |
| * |
| * Modified 2009-04-14 for native float support by Florian Faber |
| * <faber@faberman.de> |
| * |
| * Modified 2009-04-26 fixed bug in rms metering by Florian Faber |
| * <faber@faberman.de> |
| * |
| * Modified 2009-04-30 added hw serial number support by Florian Faber |
| * |
| * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth |
| * |
| * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; either version 2 of the License, or |
| * (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| * |
| */ |
| #include <linux/init.h> |
| #include <linux/delay.h> |
| #include <linux/interrupt.h> |
| #include <linux/module.h> |
| #include <linux/slab.h> |
| #include <linux/pci.h> |
| #include <linux/math64.h> |
| #include <asm/io.h> |
| |
| #include <sound/core.h> |
| #include <sound/control.h> |
| #include <sound/pcm.h> |
| #include <sound/pcm_params.h> |
| #include <sound/info.h> |
| #include <sound/asoundef.h> |
| #include <sound/rawmidi.h> |
| #include <sound/hwdep.h> |
| #include <sound/initval.h> |
| |
| #include <sound/hdspm.h> |
| |
| static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ |
| static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ |
| static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ |
| |
| module_param_array(index, int, NULL, 0444); |
| MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); |
| |
| module_param_array(id, charp, NULL, 0444); |
| MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); |
| |
| module_param_array(enable, bool, NULL, 0444); |
| MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); |
| |
| |
| MODULE_AUTHOR |
| ( |
| "Winfried Ritsch <ritsch_AT_iem.at>, " |
| "Paul Davis <paul@linuxaudiosystems.com>, " |
| "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " |
| "Remy Bruno <remy.bruno@trinnov.com>, " |
| "Florian Faber <faberman@linuxproaudio.org>, " |
| "Adrian Knoth <adi@drcomp.erfurt.thur.de>" |
| ); |
| MODULE_DESCRIPTION("RME HDSPM"); |
| MODULE_LICENSE("GPL"); |
| MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); |
| |
| /* --- Write registers. --- |
| These are defined as byte-offsets from the iobase value. */ |
| |
| #define HDSPM_WR_SETTINGS 0 |
| #define HDSPM_outputBufferAddress 32 |
| #define HDSPM_inputBufferAddress 36 |
| #define HDSPM_controlRegister 64 |
| #define HDSPM_interruptConfirmation 96 |
| #define HDSPM_control2Reg 256 /* not in specs ???????? */ |
| #define HDSPM_freqReg 256 /* for AES32 */ |
| #define HDSPM_midiDataOut0 352 /* just believe in old code */ |
| #define HDSPM_midiDataOut1 356 |
| #define HDSPM_eeprom_wr 384 /* for AES32 */ |
| |
| /* DMA enable for 64 channels, only Bit 0 is relevant */ |
| #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ |
| #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ |
| |
| /* 16 page addresses for each of the 64 channels DMA buffer in and out |
| (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ |
| #define HDSPM_pageAddressBufferOut 8192 |
| #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) |
| |
| #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ |
| |
| #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ |
| |
| /* --- Read registers. --- |
| These are defined as byte-offsets from the iobase value */ |
| #define HDSPM_statusRegister 0 |
| /*#define HDSPM_statusRegister2 96 */ |
| /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at |
| * offset 192, for AES32 *and* MADI |
| * => need to check that offset 192 is working on MADI */ |
| #define HDSPM_statusRegister2 192 |
| #define HDSPM_timecodeRegister 128 |
| |
| /* AIO, RayDAT */ |
| #define HDSPM_RD_STATUS_0 0 |
| #define HDSPM_RD_STATUS_1 64 |
| #define HDSPM_RD_STATUS_2 128 |
| #define HDSPM_RD_STATUS_3 192 |
| |
| #define HDSPM_RD_TCO 256 |
| #define HDSPM_RD_PLL_FREQ 512 |
| #define HDSPM_WR_TCO 128 |
| |
| #define HDSPM_TCO1_TCO_lock 0x00000001 |
| #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 |
| #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 |
| #define HDSPM_TCO1_LTC_Input_valid 0x00000008 |
| #define HDSPM_TCO1_WCK_Input_valid 0x00000010 |
| #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 |
| #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 |
| |
| #define HDSPM_TCO1_set_TC 0x00000100 |
| #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 |
| #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 |
| #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 |
| |
| #define HDSPM_TCO2_TC_run 0x00010000 |
| #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 |
| #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 |
| #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 |
| #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 |
| #define HDSPM_TCO2_set_jam_sync 0x00200000 |
| #define HDSPM_TCO2_set_flywheel 0x00400000 |
| |
| #define HDSPM_TCO2_set_01_4 0x01000000 |
| #define HDSPM_TCO2_set_pull_down 0x02000000 |
| #define HDSPM_TCO2_set_pull_up 0x04000000 |
| #define HDSPM_TCO2_set_freq 0x08000000 |
| #define HDSPM_TCO2_set_term_75R 0x10000000 |
| #define HDSPM_TCO2_set_input_LSB 0x20000000 |
| #define HDSPM_TCO2_set_input_MSB 0x40000000 |
| #define HDSPM_TCO2_set_freq_from_app 0x80000000 |
| |
| |
| #define HDSPM_midiDataOut0 352 |
| #define HDSPM_midiDataOut1 356 |
| #define HDSPM_midiDataOut2 368 |
| |
| #define HDSPM_midiDataIn0 360 |
| #define HDSPM_midiDataIn1 364 |
| #define HDSPM_midiDataIn2 372 |
| #define HDSPM_midiDataIn3 376 |
| |
| /* status is data bytes in MIDI-FIFO (0-128) */ |
| #define HDSPM_midiStatusOut0 384 |
| #define HDSPM_midiStatusOut1 388 |
| #define HDSPM_midiStatusOut2 400 |
| |
| #define HDSPM_midiStatusIn0 392 |
| #define HDSPM_midiStatusIn1 396 |
| #define HDSPM_midiStatusIn2 404 |
| #define HDSPM_midiStatusIn3 408 |
| |
| |
| /* the meters are regular i/o-mapped registers, but offset |
| considerably from the rest. the peak registers are reset |
| when read; the least-significant 4 bits are full-scale counters; |
| the actual peak value is in the most-significant 24 bits. |
| */ |
| |
| #define HDSPM_MADI_INPUT_PEAK 4096 |
| #define HDSPM_MADI_PLAYBACK_PEAK 4352 |
| #define HDSPM_MADI_OUTPUT_PEAK 4608 |
| |
| #define HDSPM_MADI_INPUT_RMS_L 6144 |
| #define HDSPM_MADI_PLAYBACK_RMS_L 6400 |
| #define HDSPM_MADI_OUTPUT_RMS_L 6656 |
| |
| #define HDSPM_MADI_INPUT_RMS_H 7168 |
| #define HDSPM_MADI_PLAYBACK_RMS_H 7424 |
| #define HDSPM_MADI_OUTPUT_RMS_H 7680 |
| |
| /* --- Control Register bits --------- */ |
| #define HDSPM_Start (1<<0) /* start engine */ |
| |
| #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ |
| #define HDSPM_Latency1 (1<<2) /* where n is defined */ |
| #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ |
| |
| #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ |
| #define HDSPM_c0Master 0x1 /* Master clock bit in settings |
| register [RayDAT, AIO] */ |
| |
| #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ |
| |
| #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ |
| #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ |
| #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ |
| #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ |
| |
| #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ |
| #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, |
| 56channelMODE=0 */ /* MADI ONLY*/ |
| #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ |
| |
| #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, |
| 0=off, 1=on */ /* MADI ONLY */ |
| #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ |
| |
| #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax |
| * -- MADI ONLY |
| */ |
| #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ |
| |
| #define HDSPM_SyncRef2 (1<<13) |
| #define HDSPM_SyncRef3 (1<<25) |
| |
| #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ |
| #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use |
| AES additional bits in |
| lower 5 Audiodatabits ??? */ |
| #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ |
| #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ |
| |
| #define HDSPM_Midi0InterruptEnable 0x0400000 |
| #define HDSPM_Midi1InterruptEnable 0x0800000 |
| #define HDSPM_Midi2InterruptEnable 0x0200000 |
| #define HDSPM_Midi3InterruptEnable 0x4000000 |
| |
| #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ |
| #define HDSPe_FLOAT_FORMAT 0x2000000 |
| |
| #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ |
| #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ |
| #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ |
| |
| #define HDSPM_wclk_sel (1<<30) |
| |
| /* --- bit helper defines */ |
| #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) |
| #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ |
| HDSPM_DoubleSpeed|HDSPM_QuadSpeed) |
| #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) |
| #define HDSPM_InputOptical 0 |
| #define HDSPM_InputCoaxial (HDSPM_InputSelect0) |
| #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ |
| HDSPM_SyncRef2|HDSPM_SyncRef3) |
| |
| #define HDSPM_c0_SyncRef0 0x2 |
| #define HDSPM_c0_SyncRef1 0x4 |
| #define HDSPM_c0_SyncRef2 0x8 |
| #define HDSPM_c0_SyncRef3 0x10 |
| #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ |
| HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) |
| |
| #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ |
| #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ |
| #define HDSPM_SYNC_FROM_TCO 2 |
| #define HDSPM_SYNC_FROM_SYNC_IN 3 |
| |
| #define HDSPM_Frequency32KHz HDSPM_Frequency0 |
| #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 |
| #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) |
| #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) |
| #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) |
| #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ |
| HDSPM_Frequency0) |
| #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) |
| #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) |
| #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ |
| HDSPM_Frequency0) |
| |
| |
| /* Synccheck Status */ |
| #define HDSPM_SYNC_CHECK_NO_LOCK 0 |
| #define HDSPM_SYNC_CHECK_LOCK 1 |
| #define HDSPM_SYNC_CHECK_SYNC 2 |
| |
| /* AutoSync References - used by "autosync_ref" control switch */ |
| #define HDSPM_AUTOSYNC_FROM_WORD 0 |
| #define HDSPM_AUTOSYNC_FROM_MADI 1 |
| #define HDSPM_AUTOSYNC_FROM_TCO 2 |
| #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 |
| #define HDSPM_AUTOSYNC_FROM_NONE 4 |
| |
| /* Possible sources of MADI input */ |
| #define HDSPM_OPTICAL 0 /* optical */ |
| #define HDSPM_COAXIAL 1 /* BNC */ |
| |
| #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) |
| #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) |
| |
| #define hdspm_encode_in(x) (((x)&0x3)<<14) |
| #define hdspm_decode_in(x) (((x)>>14)&0x3) |
| |
| /* --- control2 register bits --- */ |
| #define HDSPM_TMS (1<<0) |
| #define HDSPM_TCK (1<<1) |
| #define HDSPM_TDI (1<<2) |
| #define HDSPM_JTAG (1<<3) |
| #define HDSPM_PWDN (1<<4) |
| #define HDSPM_PROGRAM (1<<5) |
| #define HDSPM_CONFIG_MODE_0 (1<<6) |
| #define HDSPM_CONFIG_MODE_1 (1<<7) |
| /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ |
| #define HDSPM_BIGENDIAN_MODE (1<<9) |
| #define HDSPM_RD_MULTIPLE (1<<10) |
| |
| /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and |
| that do not conflict with specific bits for AES32 seem to be valid also |
| for the AES32 |
| */ |
| #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ |
| #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ |
| #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 |
| * (like inp0) |
| */ |
| |
| #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ |
| #define HDSPM_madiSync (1<<18) /* MADI is in sync */ |
| |
| #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */ |
| #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */ |
| |
| #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */ |
| #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */ |
| |
| #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ |
| /* since 64byte accurate, last 6 bits are not used */ |
| |
| |
| |
| #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ |
| |
| #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ |
| #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ |
| #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ |
| #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ |
| |
| #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with |
| * Interrupt |
| */ |
| #define HDSPM_tco_detect 0x08000000 |
| #define HDSPM_tco_lock 0x20000000 |
| |
| #define HDSPM_s2_tco_detect 0x00000040 |
| #define HDSPM_s2_AEBO_D 0x00000080 |
| #define HDSPM_s2_AEBI_D 0x00000100 |
| |
| |
| #define HDSPM_midi0IRQPending 0x40000000 |
| #define HDSPM_midi1IRQPending 0x80000000 |
| #define HDSPM_midi2IRQPending 0x20000000 |
| #define HDSPM_midi2IRQPendingAES 0x00000020 |
| #define HDSPM_midi3IRQPending 0x00200000 |
| |
| /* --- status bit helpers */ |
| #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ |
| HDSPM_madiFreq2|HDSPM_madiFreq3) |
| #define HDSPM_madiFreq32 (HDSPM_madiFreq0) |
| #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) |
| #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) |
| #define HDSPM_madiFreq64 (HDSPM_madiFreq2) |
| #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) |
| #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) |
| #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) |
| #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) |
| #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) |
| |
| /* Status2 Register bits */ /* MADI ONLY */ |
| |
| #define HDSPM_version0 (1<<0) /* not really defined but I guess */ |
| #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ |
| #define HDSPM_version2 (1<<2) |
| |
| #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ |
| #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ |
| |
| #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ |
| #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ |
| #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */ |
| /* missing Bit for 111=128, 1000=176.4, 1001=192 */ |
| |
| #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ |
| #define HDSPM_SyncRef1 0x20000 |
| |
| #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ |
| #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ |
| #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ |
| |
| #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) |
| |
| #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) |
| #define HDSPM_wcFreq32 (HDSPM_wc_freq0) |
| #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) |
| #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) |
| #define HDSPM_wcFreq64 (HDSPM_wc_freq2) |
| #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) |
| #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) |
| |
| #define HDSPM_status1_F_0 0x0400000 |
| #define HDSPM_status1_F_1 0x0800000 |
| #define HDSPM_status1_F_2 0x1000000 |
| #define HDSPM_status1_F_3 0x2000000 |
| #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) |
| |
| |
| #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ |
| HDSPM_SelSyncRef2) |
| #define HDSPM_SelSyncRef_WORD 0 |
| #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) |
| #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) |
| #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) |
| #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ |
| HDSPM_SelSyncRef2) |
| |
| /* |
| For AES32, bits for status, status2 and timecode are different |
| */ |
| /* status */ |
| #define HDSPM_AES32_wcLock 0x0200000 |
| #define HDSPM_AES32_wcSync 0x0100000 |
| #define HDSPM_AES32_wcFreq_bit 22 |
| /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function |
| HDSPM_bit2freq */ |
| #define HDSPM_AES32_syncref_bit 16 |
| /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ |
| |
| #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 |
| #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 |
| #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 |
| #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 |
| #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 |
| #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 |
| #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 |
| #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 |
| #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 |
| #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9 |
| |
| /* status2 */ |
| /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ |
| #define HDSPM_LockAES 0x80 |
| #define HDSPM_LockAES1 0x80 |
| #define HDSPM_LockAES2 0x40 |
| #define HDSPM_LockAES3 0x20 |
| #define HDSPM_LockAES4 0x10 |
| #define HDSPM_LockAES5 0x8 |
| #define HDSPM_LockAES6 0x4 |
| #define HDSPM_LockAES7 0x2 |
| #define HDSPM_LockAES8 0x1 |
| /* |
| Timecode |
| After windows driver sources, bits 4*i to 4*i+3 give the input frequency on |
| AES i+1 |
| bits 3210 |
| 0001 32kHz |
| 0010 44.1kHz |
| 0011 48kHz |
| 0100 64kHz |
| 0101 88.2kHz |
| 0110 96kHz |
| 0111 128kHz |
| 1000 176.4kHz |
| 1001 192kHz |
| NB: Timecode register doesn't seem to work on AES32 card revision 230 |
| */ |
| |
| /* Mixer Values */ |
| #define UNITY_GAIN 32768 /* = 65536/2 */ |
| #define MINUS_INFINITY_GAIN 0 |
| |
| /* Number of channels for different Speed Modes */ |
| #define MADI_SS_CHANNELS 64 |
| #define MADI_DS_CHANNELS 32 |
| #define MADI_QS_CHANNELS 16 |
| |
| #define RAYDAT_SS_CHANNELS 36 |
| #define RAYDAT_DS_CHANNELS 20 |
| #define RAYDAT_QS_CHANNELS 12 |
| |
| #define AIO_IN_SS_CHANNELS 14 |
| #define AIO_IN_DS_CHANNELS 10 |
| #define AIO_IN_QS_CHANNELS 8 |
| #define AIO_OUT_SS_CHANNELS 16 |
| #define AIO_OUT_DS_CHANNELS 12 |
| #define AIO_OUT_QS_CHANNELS 10 |
| |
| #define AES32_CHANNELS 16 |
| |
| /* the size of a substream (1 mono data stream) */ |
| #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) |
| #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) |
| |
| /* the size of the area we need to allocate for DMA transfers. the |
| size is the same regardless of the number of channels, and |
| also the latency to use. |
| for one direction !!! |
| */ |
| #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) |
| #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) |
| |
| #define HDSPM_RAYDAT_REV 211 |
| #define HDSPM_AIO_REV 212 |
| #define HDSPM_MADIFACE_REV 213 |
| |
| /* speed factor modes */ |
| #define HDSPM_SPEED_SINGLE 0 |
| #define HDSPM_SPEED_DOUBLE 1 |
| #define HDSPM_SPEED_QUAD 2 |
| |
| /* names for speed modes */ |
| static char *hdspm_speed_names[] = { "single", "double", "quad" }; |
| |
| static char *texts_autosync_aes_tco[] = { "Word Clock", |
| "AES1", "AES2", "AES3", "AES4", |
| "AES5", "AES6", "AES7", "AES8", |
| "TCO" }; |
| static char *texts_autosync_aes[] = { "Word Clock", |
| "AES1", "AES2", "AES3", "AES4", |
| "AES5", "AES6", "AES7", "AES8" }; |
| static char *texts_autosync_madi_tco[] = { "Word Clock", |
| "MADI", "TCO", "Sync In" }; |
| static char *texts_autosync_madi[] = { "Word Clock", |
| "MADI", "Sync In" }; |
| |
| static char *texts_autosync_raydat_tco[] = { |
| "Word Clock", |
| "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", |
| "AES", "SPDIF", "TCO", "Sync In" |
| }; |
| static char *texts_autosync_raydat[] = { |
| "Word Clock", |
| "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", |
| "AES", "SPDIF", "Sync In" |
| }; |
| static char *texts_autosync_aio_tco[] = { |
| "Word Clock", |
| "ADAT", "AES", "SPDIF", "TCO", "Sync In" |
| }; |
| static char *texts_autosync_aio[] = { "Word Clock", |
| "ADAT", "AES", "SPDIF", "Sync In" }; |
| |
| static char *texts_freq[] = { |
| "No Lock", |
| "32 kHz", |
| "44.1 kHz", |
| "48 kHz", |
| "64 kHz", |
| "88.2 kHz", |
| "96 kHz", |
| "128 kHz", |
| "176.4 kHz", |
| "192 kHz" |
| }; |
| |
| static char *texts_ports_madi[] = { |
| "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", |
| "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", |
| "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", |
| "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", |
| "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", |
| "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", |
| "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", |
| "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", |
| "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", |
| "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", |
| "MADI.61", "MADI.62", "MADI.63", "MADI.64", |
| }; |
| |
| |
| static char *texts_ports_raydat_ss[] = { |
| "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", |
| "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", |
| "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", |
| "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", |
| "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", |
| "ADAT4.7", "ADAT4.8", |
| "AES.L", "AES.R", |
| "SPDIF.L", "SPDIF.R" |
| }; |
| |
| static char *texts_ports_raydat_ds[] = { |
| "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", |
| "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", |
| "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", |
| "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", |
| "AES.L", "AES.R", |
| "SPDIF.L", "SPDIF.R" |
| }; |
| |
| static char *texts_ports_raydat_qs[] = { |
| "ADAT1.1", "ADAT1.2", |
| "ADAT2.1", "ADAT2.2", |
| "ADAT3.1", "ADAT3.2", |
| "ADAT4.1", "ADAT4.2", |
| "AES.L", "AES.R", |
| "SPDIF.L", "SPDIF.R" |
| }; |
| |
| |
| static char *texts_ports_aio_in_ss[] = { |
| "Analogue.L", "Analogue.R", |
| "AES.L", "AES.R", |
| "SPDIF.L", "SPDIF.R", |
| "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", |
| "ADAT.7", "ADAT.8" |
| }; |
| |
| static char *texts_ports_aio_out_ss[] = { |
| "Analogue.L", "Analogue.R", |
| "AES.L", "AES.R", |
| "SPDIF.L", "SPDIF.R", |
| "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", |
| "ADAT.7", "ADAT.8", |
| "Phone.L", "Phone.R" |
| }; |
| |
| static char *texts_ports_aio_in_ds[] = { |
| "Analogue.L", "Analogue.R", |
| "AES.L", "AES.R", |
| "SPDIF.L", "SPDIF.R", |
| "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" |
| }; |
| |
| static char *texts_ports_aio_out_ds[] = { |
| "Analogue.L", "Analogue.R", |
| "AES.L", "AES.R", |
| "SPDIF.L", "SPDIF.R", |
| "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", |
| "Phone.L", "Phone.R" |
| }; |
| |
| static char *texts_ports_aio_in_qs[] = { |
| "Analogue.L", "Analogue.R", |
| "AES.L", "AES.R", |
| "SPDIF.L", "SPDIF.R", |
| "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" |
| }; |
| |
| static char *texts_ports_aio_out_qs[] = { |
| "Analogue.L", "Analogue.R", |
| "AES.L", "AES.R", |
| "SPDIF.L", "SPDIF.R", |
| "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", |
| "Phone.L", "Phone.R" |
| }; |
| |
| static char *texts_ports_aes32[] = { |
| "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", |
| "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", |
| "AES.15", "AES.16" |
| }; |
| |
| /* These tables map the ALSA channels 1..N to the channels that we |
| need to use in order to find the relevant channel buffer. RME |
| refers to this kind of mapping as between "the ADAT channel and |
| the DMA channel." We index it using the logical audio channel, |
| and the value is the DMA channel (i.e. channel buffer number) |
| where the data for that channel can be read/written from/to. |
| */ |
| |
| static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { |
| 0, 1, 2, 3, 4, 5, 6, 7, |
| 8, 9, 10, 11, 12, 13, 14, 15, |
| 16, 17, 18, 19, 20, 21, 22, 23, |
| 24, 25, 26, 27, 28, 29, 30, 31, |
| 32, 33, 34, 35, 36, 37, 38, 39, |
| 40, 41, 42, 43, 44, 45, 46, 47, |
| 48, 49, 50, 51, 52, 53, 54, 55, |
| 56, 57, 58, 59, 60, 61, 62, 63 |
| }; |
| |
| static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { |
| 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ |
| 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ |
| 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ |
| 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ |
| 0, 1, /* AES */ |
| 2, 3, /* SPDIF */ |
| -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| }; |
| |
| static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { |
| 4, 5, 6, 7, /* ADAT 1 */ |
| 8, 9, 10, 11, /* ADAT 2 */ |
| 12, 13, 14, 15, /* ADAT 3 */ |
| 16, 17, 18, 19, /* ADAT 4 */ |
| 0, 1, /* AES */ |
| 2, 3, /* SPDIF */ |
| -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| }; |
| |
| static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { |
| 4, 5, /* ADAT 1 */ |
| 6, 7, /* ADAT 2 */ |
| 8, 9, /* ADAT 3 */ |
| 10, 11, /* ADAT 4 */ |
| 0, 1, /* AES */ |
| 2, 3, /* SPDIF */ |
| -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| }; |
| |
| static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { |
| 0, 1, /* line in */ |
| 8, 9, /* aes in, */ |
| 10, 11, /* spdif in */ |
| 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ |
| -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| }; |
| |
| static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { |
| 0, 1, /* line out */ |
| 8, 9, /* aes out */ |
| 10, 11, /* spdif out */ |
| 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ |
| 6, 7, /* phone out */ |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| }; |
| |
| static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { |
| 0, 1, /* line in */ |
| 8, 9, /* aes in */ |
| 10, 11, /* spdif in */ |
| 12, 14, 16, 18, /* adat in */ |
| -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1 |
| }; |
| |
| static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { |
| 0, 1, /* line out */ |
| 8, 9, /* aes out */ |
| 10, 11, /* spdif out */ |
| 12, 14, 16, 18, /* adat out */ |
| 6, 7, /* phone out */ |
| -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1 |
| }; |
| |
| static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { |
| 0, 1, /* line in */ |
| 8, 9, /* aes in */ |
| 10, 11, /* spdif in */ |
| 12, 16, /* adat in */ |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1 |
| }; |
| |
| static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { |
| 0, 1, /* line out */ |
| 8, 9, /* aes out */ |
| 10, 11, /* spdif out */ |
| 12, 16, /* adat out */ |
| 6, 7, /* phone out */ |
| -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1 |
| }; |
| |
| static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { |
| 0, 1, 2, 3, 4, 5, 6, 7, |
| 8, 9, 10, 11, 12, 13, 14, 15, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1 |
| }; |
| |
| struct hdspm_midi { |
| struct hdspm *hdspm; |
| int id; |
| struct snd_rawmidi *rmidi; |
| struct snd_rawmidi_substream *input; |
| struct snd_rawmidi_substream *output; |
| char istimer; /* timer in use */ |
| struct timer_list timer; |
| spinlock_t lock; |
| int pending; |
| int dataIn; |
| int statusIn; |
| int dataOut; |
| int statusOut; |
| int ie; |
| int irq; |
| }; |
| |
| struct hdspm_tco { |
| int input; |
| int framerate; |
| int wordclock; |
| int samplerate; |
| int pull; |
| int term; /* 0 = off, 1 = on */ |
| }; |
| |
| struct hdspm { |
| spinlock_t lock; |
| /* only one playback and/or capture stream */ |
| struct snd_pcm_substream *capture_substream; |
| struct snd_pcm_substream *playback_substream; |
| |
| char *card_name; /* for procinfo */ |
| unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ |
| |
| uint8_t io_type; |
| |
| int monitor_outs; /* set up monitoring outs init flag */ |
| |
| u32 control_register; /* cached value */ |
| u32 control2_register; /* cached value */ |
| u32 settings_register; |
| |
| struct hdspm_midi midi[4]; |
| struct tasklet_struct midi_tasklet; |
| |
| size_t period_bytes; |
| unsigned char ss_in_channels; |
| unsigned char ds_in_channels; |
| unsigned char qs_in_channels; |
| unsigned char ss_out_channels; |
| unsigned char ds_out_channels; |
| unsigned char qs_out_channels; |
| |
| unsigned char max_channels_in; |
| unsigned char max_channels_out; |
| |
| signed char *channel_map_in; |
| signed char *channel_map_out; |
| |
| signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; |
| signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; |
| |
| char **port_names_in; |
| char **port_names_out; |
| |
| char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; |
| char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; |
| |
| unsigned char *playback_buffer; /* suitably aligned address */ |
| unsigned char *capture_buffer; /* suitably aligned address */ |
| |
| pid_t capture_pid; /* process id which uses capture */ |
| pid_t playback_pid; /* process id which uses capture */ |
| int running; /* running status */ |
| |
| int last_external_sample_rate; /* samplerate mystic ... */ |
| int last_internal_sample_rate; |
| int system_sample_rate; |
| |
| int dev; /* Hardware vars... */ |
| int irq; |
| unsigned long port; |
| void __iomem *iobase; |
| |
| int irq_count; /* for debug */ |
| int midiPorts; |
| |
| struct snd_card *card; /* one card */ |
| struct snd_pcm *pcm; /* has one pcm */ |
| struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ |
| struct pci_dev *pci; /* and an pci info */ |
| |
| /* Mixer vars */ |
| /* fast alsa mixer */ |
| struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; |
| /* but input to much, so not used */ |
| struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; |
| /* full mixer accessible over mixer ioctl or hwdep-device */ |
| struct hdspm_mixer *mixer; |
| |
| struct hdspm_tco *tco; /* NULL if no TCO detected */ |
| |
| char **texts_autosync; |
| int texts_autosync_items; |
| |
| cycles_t last_interrupt; |
| |
| unsigned int serial; |
| |
| struct hdspm_peak_rms peak_rms; |
| }; |
| |
| |
| static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = { |
| { |
| .vendor = PCI_VENDOR_ID_XILINX, |
| .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, |
| .subvendor = PCI_ANY_ID, |
| .subdevice = PCI_ANY_ID, |
| .class = 0, |
| .class_mask = 0, |
| .driver_data = 0}, |
| {0,} |
| }; |
| |
| MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); |
| |
| /* prototypes */ |
| static int snd_hdspm_create_alsa_devices(struct snd_card *card, |
| struct hdspm *hdspm); |
| static int snd_hdspm_create_pcm(struct snd_card *card, |
| struct hdspm *hdspm); |
| |
| static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); |
| static inline int hdspm_get_pll_freq(struct hdspm *hdspm); |
| static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); |
| static int hdspm_autosync_ref(struct hdspm *hdspm); |
| static int snd_hdspm_set_defaults(struct hdspm *hdspm); |
| static int hdspm_system_clock_mode(struct hdspm *hdspm); |
| static void hdspm_set_sgbuf(struct hdspm *hdspm, |
| struct snd_pcm_substream *substream, |
| unsigned int reg, int channels); |
| |
| static inline int HDSPM_bit2freq(int n) |
| { |
| static const int bit2freq_tab[] = { |
| 0, 32000, 44100, 48000, 64000, 88200, |
| 96000, 128000, 176400, 192000 }; |
| if (n < 1 || n > 9) |
| return 0; |
| return bit2freq_tab[n]; |
| } |
| |
| /* Write/read to/from HDSPM with Adresses in Bytes |
| not words but only 32Bit writes are allowed */ |
| |
| static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, |
| unsigned int val) |
| { |
| writel(val, hdspm->iobase + reg); |
| } |
| |
| static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) |
| { |
| return readl(hdspm->iobase + reg); |
| } |
| |
| /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader |
| mixer is write only on hardware so we have to cache him for read |
| each fader is a u32, but uses only the first 16 bit */ |
| |
| static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, |
| unsigned int in) |
| { |
| if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) |
| return 0; |
| |
| return hdspm->mixer->ch[chan].in[in]; |
| } |
| |
| static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, |
| unsigned int pb) |
| { |
| if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) |
| return 0; |
| return hdspm->mixer->ch[chan].pb[pb]; |
| } |
| |
| static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, |
| unsigned int in, unsigned short data) |
| { |
| if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) |
| return -1; |
| |
| hdspm_write(hdspm, |
| HDSPM_MADI_mixerBase + |
| ((in + 128 * chan) * sizeof(u32)), |
| (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); |
| return 0; |
| } |
| |
| static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, |
| unsigned int pb, unsigned short data) |
| { |
| if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) |
| return -1; |
| |
| hdspm_write(hdspm, |
| HDSPM_MADI_mixerBase + |
| ((64 + pb + 128 * chan) * sizeof(u32)), |
| (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); |
| return 0; |
| } |
| |
| |
| /* enable DMA for specific channels, now available for DSP-MADI */ |
| static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) |
| { |
| hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); |
| } |
| |
| static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) |
| { |
| hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); |
| } |
| |
| /* check if same process is writing and reading */ |
| static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) |
| { |
| unsigned long flags; |
| int ret = 1; |
| |
| spin_lock_irqsave(&hdspm->lock, flags); |
| if ((hdspm->playback_pid != hdspm->capture_pid) && |
| (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { |
| ret = 0; |
| } |
| spin_unlock_irqrestore(&hdspm->lock, flags); |
| return ret; |
| } |
| |
| /* round arbitary sample rates to commonly known rates */ |
| static int hdspm_round_frequency(int rate) |
| { |
| if (rate < 38050) |
| return 32000; |
| if (rate < 46008) |
| return 44100; |
| else |
| return 48000; |
| } |
| |
| static int hdspm_tco_sync_check(struct hdspm *hdspm); |
| static int hdspm_sync_in_sync_check(struct hdspm *hdspm); |
| |
| /* check for external sample rate */ |
| static int hdspm_external_sample_rate(struct hdspm *hdspm) |
| { |
| unsigned int status, status2, timecode; |
| int syncref, rate = 0, rate_bits; |
| |
| switch (hdspm->io_type) { |
| case AES32: |
| status2 = hdspm_read(hdspm, HDSPM_statusRegister2); |
| status = hdspm_read(hdspm, HDSPM_statusRegister); |
| timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); |
| |
| syncref = hdspm_autosync_ref(hdspm); |
| |
| if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD && |
| status & HDSPM_AES32_wcLock) |
| return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF); |
| |
| if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 && |
| syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 && |
| status2 & (HDSPM_LockAES >> |
| (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))) |
| return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF); |
| return 0; |
| break; |
| |
| case MADIface: |
| status = hdspm_read(hdspm, HDSPM_statusRegister); |
| |
| if (!(status & HDSPM_madiLock)) { |
| rate = 0; /* no lock */ |
| } else { |
| switch (status & (HDSPM_status1_freqMask)) { |
| case HDSPM_status1_F_0*1: |
| rate = 32000; break; |
| case HDSPM_status1_F_0*2: |
| rate = 44100; break; |
| case HDSPM_status1_F_0*3: |
| rate = 48000; break; |
| case HDSPM_status1_F_0*4: |
| rate = 64000; break; |
| case HDSPM_status1_F_0*5: |
| rate = 88200; break; |
| case HDSPM_status1_F_0*6: |
| rate = 96000; break; |
| case HDSPM_status1_F_0*7: |
| rate = 128000; break; |
| case HDSPM_status1_F_0*8: |
| rate = 176400; break; |
| case HDSPM_status1_F_0*9: |
| rate = 192000; break; |
| default: |
| rate = 0; break; |
| } |
| } |
| |
| break; |
| |
| case MADI: |
| case AIO: |
| case RayDAT: |
| status2 = hdspm_read(hdspm, HDSPM_statusRegister2); |
| status = hdspm_read(hdspm, HDSPM_statusRegister); |
| rate = 0; |
| |
| /* if wordclock has synced freq and wordclock is valid */ |
| if ((status2 & HDSPM_wcLock) != 0 && |
| (status2 & HDSPM_SelSyncRef0) == 0) { |
| |
| rate_bits = status2 & HDSPM_wcFreqMask; |
| |
| |
| switch (rate_bits) { |
| case HDSPM_wcFreq32: |
| rate = 32000; |
| break; |
| case HDSPM_wcFreq44_1: |
| rate = 44100; |
| break; |
| case HDSPM_wcFreq48: |
| rate = 48000; |
| break; |
| case HDSPM_wcFreq64: |
| rate = 64000; |
| break; |
| case HDSPM_wcFreq88_2: |
| rate = 88200; |
| break; |
| case HDSPM_wcFreq96: |
| rate = 96000; |
| break; |
| default: |
| rate = 0; |
| break; |
| } |
| } |
| |
| /* if rate detected and Syncref is Word than have it, |
| * word has priority to MADI |
| */ |
| if (rate != 0 && |
| (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) |
| return rate; |
| |
| /* maybe a madi input (which is taken if sel sync is madi) */ |
| if (status & HDSPM_madiLock) { |
| rate_bits = status & HDSPM_madiFreqMask; |
| |
| switch (rate_bits) { |
| case HDSPM_madiFreq32: |
| rate = 32000; |
| break; |
| case HDSPM_madiFreq44_1: |
| rate = 44100; |
| break; |
| case HDSPM_madiFreq48: |
| rate = 48000; |
| break; |
| case HDSPM_madiFreq64: |
| rate = 64000; |
| break; |
| case HDSPM_madiFreq88_2: |
| rate = 88200; |
| break; |
| case HDSPM_madiFreq96: |
| rate = 96000; |
| break; |
| case HDSPM_madiFreq128: |
| rate = 128000; |
| break; |
| case HDSPM_madiFreq176_4: |
| rate = 176400; |
| break; |
| case HDSPM_madiFreq192: |
| rate = 192000; |
| break; |
| default: |
| rate = 0; |
| break; |
| } |
| |
| } /* endif HDSPM_madiLock */ |
| |
| /* check sample rate from TCO or SYNC_IN */ |
| { |
| bool is_valid_input = 0; |
| bool has_sync = 0; |
| |
| syncref = hdspm_autosync_ref(hdspm); |
| if (HDSPM_AUTOSYNC_FROM_TCO == syncref) { |
| is_valid_input = 1; |
| has_sync = (HDSPM_SYNC_CHECK_SYNC == |
| hdspm_tco_sync_check(hdspm)); |
| } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) { |
| is_valid_input = 1; |
| has_sync = (HDSPM_SYNC_CHECK_SYNC == |
| hdspm_sync_in_sync_check(hdspm)); |
| } |
| |
| if (is_valid_input && has_sync) { |
| rate = hdspm_round_frequency( |
| hdspm_get_pll_freq(hdspm)); |
| } |
| } |
| |
| /* QS and DS rates normally can not be detected |
| * automatically by the card. Only exception is MADI |
| * in 96k frame mode. |
| * |
| * So if we read SS values (32 .. 48k), check for |
| * user-provided DS/QS bits in the control register |
| * and multiply the base frequency accordingly. |
| */ |
| if (rate <= 48000) { |
| if (hdspm->control_register & HDSPM_QuadSpeed) |
| rate *= 4; |
| else if (hdspm->control_register & |
| HDSPM_DoubleSpeed) |
| rate *= 2; |
| } |
| break; |
| } |
| |
| return rate; |
| } |
| |
| /* return latency in samples per period */ |
| static int hdspm_get_latency(struct hdspm *hdspm) |
| { |
| int n; |
| |
| n = hdspm_decode_latency(hdspm->control_register); |
| |
| /* Special case for new RME cards with 32 samples period size. |
| * The three latency bits in the control register |
| * (HDSP_LatencyMask) encode latency values of 64 samples as |
| * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7 |
| * denotes 8192 samples, but on new cards like RayDAT or AIO, |
| * it corresponds to 32 samples. |
| */ |
| if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type)) |
| n = -1; |
| |
| return 1 << (n + 6); |
| } |
| |
| /* Latency function */ |
| static inline void hdspm_compute_period_size(struct hdspm *hdspm) |
| { |
| hdspm->period_bytes = 4 * hdspm_get_latency(hdspm); |
| } |
| |
| |
| static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) |
| { |
| int position; |
| |
| position = hdspm_read(hdspm, HDSPM_statusRegister); |
| |
| switch (hdspm->io_type) { |
| case RayDAT: |
| case AIO: |
| position &= HDSPM_BufferPositionMask; |
| position /= 4; /* Bytes per sample */ |
| break; |
| default: |
| position = (position & HDSPM_BufferID) ? |
| (hdspm->period_bytes / 4) : 0; |
| } |
| |
| return position; |
| } |
| |
| |
| static inline void hdspm_start_audio(struct hdspm * s) |
| { |
| s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); |
| hdspm_write(s, HDSPM_controlRegister, s->control_register); |
| } |
| |
| static inline void hdspm_stop_audio(struct hdspm * s) |
| { |
| s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); |
| hdspm_write(s, HDSPM_controlRegister, s->control_register); |
| } |
| |
| /* should I silence all or only opened ones ? doit all for first even is 4MB*/ |
| static void hdspm_silence_playback(struct hdspm *hdspm) |
| { |
| int i; |
| int n = hdspm->period_bytes; |
| void *buf = hdspm->playback_buffer; |
| |
| if (buf == NULL) |
| return; |
| |
| for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { |
| memset(buf, 0, n); |
| buf += HDSPM_CHANNEL_BUFFER_BYTES; |
| } |
| } |
| |
| static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) |
| { |
| int n; |
| |
| spin_lock_irq(&s->lock); |
| |
| if (32 == frames) { |
| /* Special case for new RME cards like RayDAT/AIO which |
| * support period sizes of 32 samples. Since latency is |
| * encoded in the three bits of HDSP_LatencyMask, we can only |
| * have values from 0 .. 7. While 0 still means 64 samples and |
| * 6 represents 4096 samples on all cards, 7 represents 8192 |
| * on older cards and 32 samples on new cards. |
| * |
| * In other words, period size in samples is calculated by |
| * 2^(n+6) with n ranging from 0 .. 7. |
| */ |
| n = 7; |
| } else { |
| frames >>= 7; |
| n = 0; |
| while (frames) { |
| n++; |
| frames >>= 1; |
| } |
| } |
| |
| s->control_register &= ~HDSPM_LatencyMask; |
| s->control_register |= hdspm_encode_latency(n); |
| |
| hdspm_write(s, HDSPM_controlRegister, s->control_register); |
| |
| hdspm_compute_period_size(s); |
| |
| spin_unlock_irq(&s->lock); |
| |
| return 0; |
| } |
| |
| static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) |
| { |
| u64 freq_const; |
| |
| if (period == 0) |
| return 0; |
| |
| switch (hdspm->io_type) { |
| case MADI: |
| case AES32: |
| freq_const = 110069313433624ULL; |
| break; |
| case RayDAT: |
| case AIO: |
| freq_const = 104857600000000ULL; |
| break; |
| case MADIface: |
| freq_const = 131072000000000ULL; |
| break; |
| default: |
| snd_BUG(); |
| return 0; |
| } |
| |
| return div_u64(freq_const, period); |
| } |
| |
| |
| static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) |
| { |
| u64 n; |
| |
| if (rate >= 112000) |
| rate /= 4; |
| else if (rate >= 56000) |
| rate /= 2; |
| |
| switch (hdspm->io_type) { |
| case MADIface: |
| n = 131072000000000ULL; /* 125 MHz */ |
| break; |
| case MADI: |
| case AES32: |
| n = 110069313433624ULL; /* 105 MHz */ |
| break; |
| case RayDAT: |
| case AIO: |
| n = 104857600000000ULL; /* 100 MHz */ |
| break; |
| default: |
| snd_BUG(); |
| return; |
| } |
| |
| n = div_u64(n, rate); |
| /* n should be less than 2^32 for being written to FREQ register */ |
| snd_BUG_ON(n >> 32); |
| hdspm_write(hdspm, HDSPM_freqReg, (u32)n); |
| } |
| |
| /* dummy set rate lets see what happens */ |
| static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) |
| { |
| int current_rate; |
| int rate_bits; |
| int not_set = 0; |
| int current_speed, target_speed; |
| |
| /* ASSUMPTION: hdspm->lock is either set, or there is no need for |
| it (e.g. during module initialization). |
| */ |
| |
| if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { |
| |
| /* SLAVE --- */ |
| if (called_internally) { |
| |
| /* request from ctl or card initialization |
| just make a warning an remember setting |
| for future master mode switching */ |
| |
| snd_printk(KERN_WARNING "HDSPM: " |
| "Warning: device is not running " |
| "as a clock master.\n"); |
| not_set = 1; |
| } else { |
| |
| /* hw_param request while in AutoSync mode */ |
| int external_freq = |
| hdspm_external_sample_rate(hdspm); |
| |
| if (hdspm_autosync_ref(hdspm) == |
| HDSPM_AUTOSYNC_FROM_NONE) { |
| |
| snd_printk(KERN_WARNING "HDSPM: " |
| "Detected no Externel Sync \n"); |
| not_set = 1; |
| |
| } else if (rate != external_freq) { |
| |
| snd_printk(KERN_WARNING "HDSPM: " |
| "Warning: No AutoSync source for " |
| "requested rate\n"); |
| not_set = 1; |
| } |
| } |
| } |
| |
| current_rate = hdspm->system_sample_rate; |
| |
| /* Changing between Singe, Double and Quad speed is not |
| allowed if any substreams are open. This is because such a change |
| causes a shift in the location of the DMA buffers and a reduction |
| in the number of available buffers. |
| |
| Note that a similar but essentially insoluble problem exists for |
| externally-driven rate changes. All we can do is to flag rate |
| changes in the read/write routines. |
| */ |
| |
| if (current_rate <= 48000) |
| current_speed = HDSPM_SPEED_SINGLE; |
| else if (current_rate <= 96000) |
| current_speed = HDSPM_SPEED_DOUBLE; |
| else |
| current_speed = HDSPM_SPEED_QUAD; |
| |
| if (rate <= 48000) |
| target_speed = HDSPM_SPEED_SINGLE; |
| else if (rate <= 96000) |
| target_speed = HDSPM_SPEED_DOUBLE; |
| else |
| target_speed = HDSPM_SPEED_QUAD; |
| |
| switch (rate) { |
| case 32000: |
| rate_bits = HDSPM_Frequency32KHz; |
| break; |
| case 44100: |
| rate_bits = HDSPM_Frequency44_1KHz; |
| break; |
| case 48000: |
| rate_bits = HDSPM_Frequency48KHz; |
| break; |
| case 64000: |
| rate_bits = HDSPM_Frequency64KHz; |
| break; |
| case 88200: |
| rate_bits = HDSPM_Frequency88_2KHz; |
| break; |
| case 96000: |
| rate_bits = HDSPM_Frequency96KHz; |
| break; |
| case 128000: |
| rate_bits = HDSPM_Frequency128KHz; |
| break; |
| case 176400: |
| rate_bits = HDSPM_Frequency176_4KHz; |
| break; |
| case 192000: |
| rate_bits = HDSPM_Frequency192KHz; |
| break; |
| default: |
| return -EINVAL; |
| } |
| |
| if (current_speed != target_speed |
| && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { |
| snd_printk |
| (KERN_ERR "HDSPM: " |
| "cannot change from %s speed to %s speed mode " |
| "(capture PID = %d, playback PID = %d)\n", |
| hdspm_speed_names[current_speed], |
| hdspm_speed_names[target_speed], |
| hdspm->capture_pid, hdspm->playback_pid); |
| return -EBUSY; |
| } |
| |
| hdspm->control_register &= ~HDSPM_FrequencyMask; |
| hdspm->control_register |= rate_bits; |
| hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); |
| |
| /* For AES32, need to set DDS value in FREQ register |
| For MADI, also apparently */ |
| hdspm_set_dds_value(hdspm, rate); |
| |
| if (AES32 == hdspm->io_type && rate != current_rate) |
| hdspm_write(hdspm, HDSPM_eeprom_wr, 0); |
| |
| hdspm->system_sample_rate = rate; |
| |
| if (rate <= 48000) { |
| hdspm->channel_map_in = hdspm->channel_map_in_ss; |
| hdspm->channel_map_out = hdspm->channel_map_out_ss; |
| hdspm->max_channels_in = hdspm->ss_in_channels; |
| hdspm->max_channels_out = hdspm->ss_out_channels; |
| hdspm->port_names_in = hdspm->port_names_in_ss; |
| hdspm->port_names_out = hdspm->port_names_out_ss; |
| } else if (rate <= 96000) { |
| hdspm->channel_map_in = hdspm->channel_map_in_ds; |
| hdspm->channel_map_out = hdspm->channel_map_out_ds; |
| hdspm->max_channels_in = hdspm->ds_in_channels; |
| hdspm->max_channels_out = hdspm->ds_out_channels; |
| hdspm->port_names_in = hdspm->port_names_in_ds; |
| hdspm->port_names_out = hdspm->port_names_out_ds; |
| } else { |
| hdspm->channel_map_in = hdspm->channel_map_in_qs; |
| hdspm->channel_map_out = hdspm->channel_map_out_qs; |
| hdspm->max_channels_in = hdspm->qs_in_channels; |
| hdspm->max_channels_out = hdspm->qs_out_channels; |
| hdspm->port_names_in = hdspm->port_names_in_qs; |
| hdspm->port_names_out = hdspm->port_names_out_qs; |
| } |
| |
| if (not_set != 0) |
| return -1; |
| |
| return 0; |
| } |
| |
| /* mainly for init to 0 on load */ |
| static void all_in_all_mixer(struct hdspm * hdspm, int sgain) |
| { |
| int i, j; |
| unsigned int gain; |
| |
| if (sgain > UNITY_GAIN) |
| gain = UNITY_GAIN; |
| else if (sgain < 0) |
| gain = 0; |
| else |
| gain = sgain; |
| |
| for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) |
| for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { |
| hdspm_write_in_gain(hdspm, i, j, gain); |
| hdspm_write_pb_gain(hdspm, i, j, gain); |
| } |
| } |
| |
| /*---------------------------------------------------------------------------- |
| MIDI |
| ----------------------------------------------------------------------------*/ |
| |
| static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, |
| int id) |
| { |
| /* the hardware already does the relevant bit-mask with 0xff */ |
| return hdspm_read(hdspm, hdspm->midi[id].dataIn); |
| } |
| |
| static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, |
| int val) |
| { |
| /* the hardware already does the relevant bit-mask with 0xff */ |
| return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); |
| } |
| |
| static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) |
| { |
| return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; |
| } |
| |
| static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) |
| { |
| int fifo_bytes_used; |
| |
| fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; |
| |
| if (fifo_bytes_used < 128) |
| return 128 - fifo_bytes_used; |
| else |
| return 0; |
| } |
| |
| static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) |
| { |
| while (snd_hdspm_midi_input_available (hdspm, id)) |
| snd_hdspm_midi_read_byte (hdspm, id); |
| } |
| |
| static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) |
| { |
| unsigned long flags; |
| int n_pending; |
| int to_write; |
| int i; |
| unsigned char buf[128]; |
| |
| /* Output is not interrupt driven */ |
| |
| spin_lock_irqsave (&hmidi->lock, flags); |
| if (hmidi->output && |
| !snd_rawmidi_transmit_empty (hmidi->output)) { |
| n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, |
| hmidi->id); |
| if (n_pending > 0) { |
| if (n_pending > (int)sizeof (buf)) |
| n_pending = sizeof (buf); |
| |
| to_write = snd_rawmidi_transmit (hmidi->output, buf, |
| n_pending); |
| if (to_write > 0) { |
| for (i = 0; i < to_write; ++i) |
| snd_hdspm_midi_write_byte (hmidi->hdspm, |
| hmidi->id, |
| buf[i]); |
| } |
| } |
| } |
| spin_unlock_irqrestore (&hmidi->lock, flags); |
| return 0; |
| } |
| |
| static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) |
| { |
| unsigned char buf[128]; /* this buffer is designed to match the MIDI |
| * input FIFO size |
| */ |
| unsigned long flags; |
| int n_pending; |
| int i; |
| |
| spin_lock_irqsave (&hmidi->lock, flags); |
| n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); |
| if (n_pending > 0) { |
| if (hmidi->input) { |
| if (n_pending > (int)sizeof (buf)) |
| n_pending = sizeof (buf); |
| for (i = 0; i < n_pending; ++i) |
| buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, |
| hmidi->id); |
| if (n_pending) |
| snd_rawmidi_receive (hmidi->input, buf, |
| n_pending); |
| } else { |
| /* flush the MIDI input FIFO */ |
| while (n_pending--) |
| snd_hdspm_midi_read_byte (hmidi->hdspm, |
| hmidi->id); |
| } |
| } |
| hmidi->pending = 0; |
| spin_unlock_irqrestore(&hmidi->lock, flags); |
| |
| spin_lock_irqsave(&hmidi->hdspm->lock, flags); |
| hmidi->hdspm->control_register |= hmidi->ie; |
| hdspm_write(hmidi->hdspm, HDSPM_controlRegister, |
| hmidi->hdspm->control_register); |
| spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); |
| |
| return snd_hdspm_midi_output_write (hmidi); |
| } |
| |
| static void |
| snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) |
| { |
| struct hdspm *hdspm; |
| struct hdspm_midi *hmidi; |
| unsigned long flags; |
| |
| hmidi = substream->rmidi->private_data; |
| hdspm = hmidi->hdspm; |
| |
| spin_lock_irqsave (&hdspm->lock, flags); |
| if (up) { |
| if (!(hdspm->control_register & hmidi->ie)) { |
| snd_hdspm_flush_midi_input (hdspm, hmidi->id); |
| hdspm->control_register |= hmidi->ie; |
| } |
| } else { |
| hdspm->control_register &= ~hmidi->ie; |
| } |
| |
| hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); |
| spin_unlock_irqrestore (&hdspm->lock, flags); |
| } |
| |
| static void snd_hdspm_midi_output_timer(unsigned long data) |
| { |
| struct hdspm_midi *hmidi = (struct hdspm_midi *) data; |
| unsigned long flags; |
| |
| snd_hdspm_midi_output_write(hmidi); |
| spin_lock_irqsave (&hmidi->lock, flags); |
| |
| /* this does not bump hmidi->istimer, because the |
| kernel automatically removed the timer when it |
| expired, and we are now adding it back, thus |
| leaving istimer wherever it was set before. |
| */ |
| |
| if (hmidi->istimer) { |
| hmidi->timer.expires = 1 + jiffies; |
| add_timer(&hmidi->timer); |
| } |
| |
| spin_unlock_irqrestore (&hmidi->lock, flags); |
| } |
| |
| static void |
| snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) |
| { |
| struct hdspm_midi *hmidi; |
| unsigned long flags; |
| |
| hmidi = substream->rmidi->private_data; |
| spin_lock_irqsave (&hmidi->lock, flags); |
| if (up) { |
| if (!hmidi->istimer) { |
| init_timer(&hmidi->timer); |
| hmidi->timer.function = snd_hdspm_midi_output_timer; |
| hmidi->timer.data = (unsigned long) hmidi; |
| hmidi->timer.expires = 1 + jiffies; |
| add_timer(&hmidi->timer); |
| hmidi->istimer++; |
| } |
| } else { |
| if (hmidi->istimer && --hmidi->istimer <= 0) |
| del_timer (&hmidi->timer); |
| } |
| spin_unlock_irqrestore (&hmidi->lock, flags); |
| if (up) |
| snd_hdspm_midi_output_write(hmidi); |
| } |
| |
| static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) |
| { |
| struct hdspm_midi *hmidi; |
| |
| hmidi = substream->rmidi->private_data; |
| spin_lock_irq (&hmidi->lock); |
| snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); |
| hmidi->input = substream; |
| spin_unlock_irq (&hmidi->lock); |
| |
| return 0; |
| } |
| |
| static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) |
| { |
| struct hdspm_midi *hmidi; |
| |
| hmidi = substream->rmidi->private_data; |
| spin_lock_irq (&hmidi->lock); |
| hmidi->output = substream; |
| spin_unlock_irq (&hmidi->lock); |
| |
| return 0; |
| } |
| |
| static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) |
| { |
| struct hdspm_midi *hmidi; |
| |
| snd_hdspm_midi_input_trigger (substream, 0); |
| |
| hmidi = substream->rmidi->private_data; |
| spin_lock_irq (&hmidi->lock); |
| hmidi->input = NULL; |
| spin_unlock_irq (&hmidi->lock); |
| |
| return 0; |
| } |
| |
| static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) |
| { |
| struct hdspm_midi *hmidi; |
| |
| snd_hdspm_midi_output_trigger (substream, 0); |
| |
| hmidi = substream->rmidi->private_data; |
| spin_lock_irq (&hmidi->lock); |
| hmidi->output = NULL; |
| spin_unlock_irq (&hmidi->lock); |
| |
| return 0; |
| } |
| |
| static struct snd_rawmidi_ops snd_hdspm_midi_output = |
| { |
| .open = snd_hdspm_midi_output_open, |
| .close = snd_hdspm_midi_output_close, |
| .trigger = snd_hdspm_midi_output_trigger, |
| }; |
| |
| static struct snd_rawmidi_ops snd_hdspm_midi_input = |
| { |
| .open = snd_hdspm_midi_input_open, |
| .close = snd_hdspm_midi_input_close, |
| .trigger = snd_hdspm_midi_input_trigger, |
| }; |
| |
| static int snd_hdspm_create_midi(struct snd_card *card, |
| struct hdspm *hdspm, int id) |
| { |
| int err; |
| char buf[32]; |
| |
| hdspm->midi[id].id = id; |
| hdspm->midi[id].hdspm = hdspm; |
| spin_lock_init (&hdspm->midi[id].lock); |
| |
| if (0 == id) { |
| if (MADIface == hdspm->io_type) { |
| /* MIDI-over-MADI on HDSPe MADIface */ |
| hdspm->midi[0].dataIn = HDSPM_midiDataIn2; |
| hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; |
| hdspm->midi[0].dataOut = HDSPM_midiDataOut2; |
| hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; |
| hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; |
| hdspm->midi[0].irq = HDSPM_midi2IRQPending; |
| } else { |
| hdspm->midi[0].dataIn = HDSPM_midiDataIn0; |
| hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; |
| hdspm->midi[0].dataOut = HDSPM_midiDataOut0; |
| hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; |
| hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; |
| hdspm->midi[0].irq = HDSPM_midi0IRQPending; |
| } |
| } else if (1 == id) { |
| hdspm->midi[1].dataIn = HDSPM_midiDataIn1; |
| hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; |
| hdspm->midi[1].dataOut = HDSPM_midiDataOut1; |
| hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; |
| hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; |
| hdspm->midi[1].irq = HDSPM_midi1IRQPending; |
| } else if ((2 == id) && (MADI == hdspm->io_type)) { |
| /* MIDI-over-MADI on HDSPe MADI */ |
| hdspm->midi[2].dataIn = HDSPM_midiDataIn2; |
| hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; |
| hdspm->midi[2].dataOut = HDSPM_midiDataOut2; |
| hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; |
| hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; |
| hdspm->midi[2].irq = HDSPM_midi2IRQPending; |
| } else if (2 == id) { |
| /* TCO MTC, read only */ |
| hdspm->midi[2].dataIn = HDSPM_midiDataIn2; |
| hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; |
| hdspm->midi[2].dataOut = -1; |
| hdspm->midi[2].statusOut = -1; |
| hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; |
| hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; |
| } else if (3 == id) { |
| /* TCO MTC on HDSPe MADI */ |
| hdspm->midi[3].dataIn = HDSPM_midiDataIn3; |
| hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; |
| hdspm->midi[3].dataOut = -1; |
| hdspm->midi[3].statusOut = -1; |
| hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; |
| hdspm->midi[3].irq = HDSPM_midi3IRQPending; |
| } |
| |
| if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || |
| (MADIface == hdspm->io_type)))) { |
| if ((id == 0) && (MADIface == hdspm->io_type)) { |
| sprintf(buf, "%s MIDIoverMADI", card->shortname); |
| } else if ((id == 2) && (MADI == hdspm->io_type)) { |
| sprintf(buf, "%s MIDIoverMADI", card->shortname); |
| } else { |
| sprintf(buf, "%s MIDI %d", card->shortname, id+1); |
| } |
| err = snd_rawmidi_new(card, buf, id, 1, 1, |
| &hdspm->midi[id].rmidi); |
| if (err < 0) |
| return err; |
| |
| sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d", |
| card->id, id+1); |
| hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; |
| |
| snd_rawmidi_set_ops(hdspm->midi[id].rmidi, |
| SNDRV_RAWMIDI_STREAM_OUTPUT, |
| &snd_hdspm_midi_output); |
| snd_rawmidi_set_ops(hdspm->midi[id].rmidi, |
| SNDRV_RAWMIDI_STREAM_INPUT, |
| &snd_hdspm_midi_input); |
| |
| hdspm->midi[id].rmidi->info_flags |= |
| SNDRV_RAWMIDI_INFO_OUTPUT | |
| SNDRV_RAWMIDI_INFO_INPUT | |
| SNDRV_RAWMIDI_INFO_DUPLEX; |
| } else { |
| /* TCO MTC, read only */ |
| sprintf(buf, "%s MTC %d", card->shortname, id+1); |
| err = snd_rawmidi_new(card, buf, id, 1, 1, |
| &hdspm->midi[id].rmidi); |
| if (err < 0) |
| return err; |
| |
| sprintf(hdspm->midi[id].rmidi->name, |
| "%s MTC %d", card->id, id+1); |
| hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; |
| |
| snd_rawmidi_set_ops(hdspm->midi[id].rmidi, |
| SNDRV_RAWMIDI_STREAM_INPUT, |
| &snd_hdspm_midi_input); |
| |
| hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; |
| } |
| |
| return 0; |
| } |
| |
| |
| static void hdspm_midi_tasklet(unsigned long arg) |
| { |
| struct hdspm *hdspm = (struct hdspm *)arg; |
| int i = 0; |
| |
| while (i < hdspm->midiPorts) { |
| if (hdspm->midi[i].pending) |
| snd_hdspm_midi_input_read(&hdspm->midi[i]); |
| |
| i++; |
| } |
| } |
| |
| |
| /*----------------------------------------------------------------------------- |
| Status Interface |
| ----------------------------------------------------------------------------*/ |
| |
| /* get the system sample rate which is set */ |
| |
| |
| static inline int hdspm_get_pll_freq(struct hdspm *hdspm) |
| { |
| unsigned int period, rate; |
| |
| period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); |
| rate = hdspm_calc_dds_value(hdspm, period); |
| |
| return rate; |
| } |
| |
| /** |
| * Calculate the real sample rate from the |
| * current DDS value. |
| **/ |
| static int hdspm_get_system_sample_rate(struct hdspm *hdspm) |
| { |
| unsigned int rate; |
| |
| rate = hdspm_get_pll_freq(hdspm); |
| |
| if (rate > 207000) { |
| /* Unreasonable high sample rate as seen on PCI MADI cards. */ |
| if (0 == hdspm_system_clock_mode(hdspm)) { |
| /* master mode, return internal sample rate */ |
| rate = hdspm->system_sample_rate; |
| } else { |
| /* slave mode, return external sample rate */ |
| rate = hdspm_external_sample_rate(hdspm); |
| } |
| } |
| |
| return rate; |
| } |
| |
| |
| #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ |
| { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
| .name = xname, \ |
| .index = xindex, \ |
| .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ |
| SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ |
| .info = snd_hdspm_info_system_sample_rate, \ |
| .put = snd_hdspm_put_system_sample_rate, \ |
| .get = snd_hdspm_get_system_sample_rate \ |
| } |
| |
| static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_info *uinfo) |
| { |
| uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
| uinfo->count = 1; |
| uinfo->value.integer.min = 27000; |
| uinfo->value.integer.max = 207000; |
| uinfo->value.integer.step = 1; |
| return 0; |
| } |
| |
| |
| static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_value * |
| ucontrol) |
| { |
| struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
| |
| ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); |
| return 0; |
| } |
| |
| static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_value * |
| ucontrol) |
| { |
| struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
| |
| hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]); |
| return 0; |
| } |
| |
| |
| /** |
| * Returns the WordClock sample rate class for the given card. |
| **/ |
| static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) |
| { |
| int status; |
| |
| switch (hdspm->io_type) { |
| case RayDAT: |
| case AIO: |
| status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); |
| return (status >> 16) & 0xF; |
| break; |
| default: |
| break; |
| } |
| |
| |
| return 0; |
| } |
| |
| |
| /** |
| * Returns the TCO sample rate class for the given card. |
| **/ |
| static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) |
| { |
| int status; |
| |
| if (hdspm->tco) { |
| switch (hdspm->io_type) { |
| case RayDAT: |
| case AIO: |
| status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); |
| return (status >> 20) & 0xF; |
| break; |
| default: |
| break; |
| } |
| } |
| |
| return 0; |
| } |
| |
| |
| /** |
| * Returns the SYNC_IN sample rate class for the given card. |
| **/ |
| static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) |
| { |
| int status; |
| |
| if (hdspm->tco) { |
| switch (hdspm->io_type) { |
| case RayDAT: |
| case AIO: |
| status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); |
| return (status >> 12) & 0xF; |
| break; |
| default: |
| break; |
| } |
| } |
| |
| return 0; |
| } |
| |
| |
| /** |
| * Returns the sample rate class for input source <idx> for |
| * 'new style' cards like the AIO and RayDAT. |
| **/ |
| static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) |
| { |
| int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); |
| |
| return (status >> (idx*4)) & 0xF; |
| } |
| |
| #define ENUMERATED_CTL_INFO(info, texts) \ |
| { \ |
| uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; \ |
| uinfo->count = 1; \ |
| uinfo->value.enumerated.items = ARRAY_SIZE(texts); \ |
| if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) \ |
| uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; \ |
| strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); \ |
| } |
| |
| |
| |
| #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ |
| { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
| .name = xname, \ |
| .private_value = xindex, \ |
| .access = SNDRV_CTL_ELEM_ACCESS_READ, \ |
| .info = snd_hdspm_info_autosync_sample_rate, \ |
| .get = snd_hdspm_get_autosync_sample_rate \ |
| } |
| |
| |
| static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_info *uinfo) |
| { |
| ENUMERATED_CTL_INFO(uinfo, texts_freq); |
| return 0; |
| } |
| |
| |
| static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_value * |
| ucontrol) |
| { |
| struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
| |
| switch (hdspm->io_type) { |
| case RayDAT: |
| switch (kcontrol->private_value) { |
| case 0: |
| ucontrol->value.enumerated.item[0] = |
| hdspm_get_wc_sample_rate(hdspm); |
| break; |
| case 7: |
| ucontrol->value.enumerated.item[0] = |
| hdspm_get_tco_sample_rate(hdspm); |
| break; |
| case 8: |
| ucontrol->value.enumerated.item[0] = |
| hdspm_get_sync_in_sample_rate(hdspm); |
| break; |
| default: |
| ucontrol->value.enumerated.item[0] = |
| hdspm_get_s1_sample_rate(hdspm, |
| kcontrol->private_value-1); |
| } |
| break; |
| |
| case AIO: |
| switch (kcontrol->private_value) { |
| case 0: /* WC */ |
| ucontrol->value.enumerated.item[0] = |
| hdspm_get_wc_sample_rate(hdspm); |
| break; |
| case 4: /* TCO */ |
| ucontrol->value.enumerated.item[0] = |
| hdspm_get_tco_sample_rate(hdspm); |
| break; |
| case 5: /* SYNC_IN */ |
| ucontrol->value.enumerated.item[0] = |
| hdspm_get_sync_in_sample_rate(hdspm); |
| break; |
| default: |
| ucontrol->value.enumerated.item[0] = |
| hdspm_get_s1_sample_rate(hdspm, |
| ucontrol->id.index-1); |
| } |
| break; |
| |
| case AES32: |
| |
| switch (kcontrol->private_value) { |
| case 0: /* WC */ |
| ucontrol->value.enumerated.item[0] = |
| hdspm_get_wc_sample_rate(hdspm); |
| break; |
| case 9: /* TCO */ |
| ucontrol->value.enumerated.item[0] = |
| hdspm_get_tco_sample_rate(hdspm); |
| break; |
| case 10: /* SYNC_IN */ |
| ucontrol->value.enumerated.item[0] = |
| hdspm_get_sync_in_sample_rate(hdspm); |
| break; |
| default: /* AES1 to AES8 */ |
| ucontrol->value.enumerated.item[0] = |
| hdspm_get_s1_sample_rate(hdspm, |
| kcontrol->private_value-1); |
| break; |
| } |
| break; |
| |
| case MADI: |
| case MADIface: |
| { |
| int rate = hdspm_external_sample_rate(hdspm); |
| int i, selected_rate = 0; |
| for (i = 1; i < 10; i++) |
| if (HDSPM_bit2freq(i) == rate) { |
| selected_rate = i; |
| break; |
| } |
| ucontrol->value.enumerated.item[0] = selected_rate; |
| } |
| break; |
| |
| default: |
| break; |
| } |
| |
| return 0; |
| } |
| |
| |
| #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ |
| { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
| .name = xname, \ |
| .index = xindex, \ |
| .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ |
| SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ |
| .info = snd_hdspm_info_system_clock_mode, \ |
| .get = snd_hdspm_get_system_clock_mode, \ |
| .put = snd_hdspm_put_system_clock_mode, \ |
| } |
| |
| |
| /** |
| * Returns the system clock mode for the given card. |
| * @returns 0 - master, 1 - slave |
| **/ |
| static int hdspm_system_clock_mode(struct hdspm *hdspm) |
| { |
| switch (hdspm->io_type) { |
| case AIO: |
| case RayDAT: |
| if (hdspm->settings_register & HDSPM_c0Master) |
| return 0; |
| break; |
| |
| default: |
| if (hdspm->control_register & HDSPM_ClockModeMaster) |
| return 0; |
| } |
| |
| return 1; |
| } |
| |
| |
| /** |
| * Sets the system clock mode. |
| * @param mode 0 - master, 1 - slave |
| **/ |
| static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) |
| { |
| switch (hdspm->io_type) { |
| case AIO: |
| case RayDAT: |
| if (0 == mode) |
| hdspm->settings_register |= HDSPM_c0Master; |
| else |
| hdspm->settings_register &= ~HDSPM_c0Master; |
| |
| hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); |
| break; |
| |
| default: |
| if (0 == mode) |
| hdspm->control_register |= HDSPM_ClockModeMaster; |
| else |
| hdspm->control_register &= ~HDSPM_ClockModeMaster; |
| |
| hdspm_write(hdspm, HDSPM_controlRegister, |
| hdspm->control_register); |
| } |
| } |
| |
| |
| static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_info *uinfo) |
| { |
| static char *texts[] = { "Master", "AutoSync" }; |
| ENUMERATED_CTL_INFO(uinfo, texts); |
| return 0; |
| } |
| |
| static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_value *ucontrol) |
| { |
| struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
| |
| ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); |
| return 0; |
| } |
| |
| static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_value *ucontrol) |
| { |
| struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
| int val; |
| |
| if (!snd_hdspm_use_is_exclusive(hdspm)) |
| return -EBUSY; |
| |
| val = ucontrol->value.enumerated.item[0]; |
| if (val < 0) |
| val = 0; |
| else if (val > 1) |
| val = 1; |
| |
| hdspm_set_system_clock_mode(hdspm, val); |
| |
| return 0; |
| } |
| |
| |
| #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ |
| { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
| .name = xname, \ |
| .index = xindex, \ |
| .info = snd_hdspm_info_clock_source, \ |
| .get = snd_hdspm_get_clock_source, \ |
| .put = snd_hdspm_put_clock_source \ |
| } |
| |
| |
| static int hdspm_clock_source(struct hdspm * hdspm) |
| { |
| switch (hdspm->system_sample_rate) { |
| case 32000: return 0; |
| case 44100: return 1; |
| case 48000: return 2; |
| case 64000: return 3; |
| case 88200: return 4; |
| case 96000: return 5; |
| case 128000: return 6; |
| case 176400: return 7; |
| case 192000: return 8; |
| } |
| |
| return -1; |
| } |
| |
| static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) |
| { |
| int rate; |
| switch (mode) { |
| case 0: |
| rate = 32000; break; |
| case 1: |
| rate = 44100; break; |
| case 2: |
| rate = 48000; break; |
| case 3: |
| rate = 64000; break; |
| case 4: |
| rate = 88200; break; |
| case 5: |
| rate = 96000; break; |
| case 6: |
| rate = 128000; break; |
| case 7: |
| rate = 176400; break; |
| case 8: |
| rate = 192000; break; |
| default: |
| rate = 48000; |
| } |
| hdspm_set_rate(hdspm, rate, 1); |
| return 0; |
| } |
| |
| static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_info *uinfo) |
| { |
| uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
| uinfo->count = 1; |
| uinfo->value.enumerated.items = 9; |
| |
| if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) |
| uinfo->value.enumerated.item = |
| uinfo->value.enumerated.items - 1; |
| |
| strcpy(uinfo->value.enumerated.name, |
| texts_freq[uinfo->value.enumerated.item+1]); |
| |
| return 0; |
| } |
| |
| static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_value *ucontrol) |
| { |
| struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
| |
| ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); |
| return 0; |
| } |
| |
| static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_value *ucontrol) |
| { |
| struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
| int change; |
| int val; |
| |
| if (!snd_hdspm_use_is_exclusive(hdspm)) |
| return -EBUSY; |
| val = ucontrol->value.enumerated.item[0]; |
| if (val < 0) |
| val = 0; |
| if (val > 9) |
| val = 9; |
| spin_lock_irq(&hdspm->lock); |
| if (val != hdspm_clock_source(hdspm)) |
| change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; |
| else |
| change = 0; |
| spin_unlock_irq(&hdspm->lock); |
| return change; |
| } |
| |
| |
| #define HDSPM_PREF_SYNC_REF(xname, xindex) \ |
| { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
| .name = xname, \ |
| .index = xindex, \ |
| .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ |
| SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ |
| .info = snd_hdspm_info_pref_sync_ref, \ |
| .get = snd_hdspm_get_pref_sync_ref, \ |
| .put = snd_hdspm_put_pref_sync_ref \ |
| } |
| |
| |
| /** |
| * Returns the current preferred sync reference setting. |
| * The semantics of the return value are depending on the |
| * card, please see the comments for clarification. |
| **/ |
| static int hdspm_pref_sync_ref(struct hdspm * hdspm) |
| { |
| switch (hdspm->io_type) { |
| case AES32: |
| switch (hdspm->control_register & HDSPM_SyncRefMask) { |
| case 0: return 0; /* WC */ |
| case HDSPM_SyncRef0: return 1; /* AES 1 */ |
| case HDSPM_SyncRef1: return 2; /* AES 2 */ |
| case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ |
| case HDSPM_SyncRef2: return 4; /* AES 4 */ |
| case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ |
| case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ |
| case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: |
| return 7; /* AES 7 */ |
| case HDSPM_SyncRef3: return 8; /* AES 8 */ |
| case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ |
| } |
| break; |
| |
| case MADI: |
| case MADIface: |
| if (hdspm->tco) { |
| switch (hdspm->control_register & HDSPM_SyncRefMask) { |
| case 0: return 0; /* WC */ |
| case HDSPM_SyncRef0: return 1; /* MADI */ |
| case HDSPM_SyncRef1: return 2; /* TCO */ |
| case HDSPM_SyncRef1+HDSPM_SyncRef0: |
| return 3; /* SYNC_IN */ |
| } |
| } else { |
| switch (hdspm->control_register & HDSPM_SyncRefMask) { |
| case 0: return 0; /* WC */ |
| case HDSPM_SyncRef0: return 1; /* MADI */ |
| case HDSPM_SyncRef1+HDSPM_SyncRef0: |
| return 2; /* SYNC_IN */ |
| } |
| } |
| break; |
| |
| case RayDAT: |
| if (hdspm->tco) { |
| switch ((hdspm->settings_register & |
| HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { |
| case 0: return 0; /* WC */ |
| case 3: return 1; /* ADAT 1 */ |
| case 4: return 2; /* ADAT 2 */ |
| case 5: return 3; /* ADAT 3 */ |
| case 6: return 4; /* ADAT 4 */ |
| case 1: return 5; /* AES */ |
| case 2: return 6; /* SPDIF */ |
| case 9: return 7; /* TCO */ |
| case 10: return 8; /* SYNC_IN */ |
| } |
| } else { |
| switch ((hdspm->settings_register & |
| HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { |
| case 0: return 0; /* WC */ |
| case 3: return 1; /* ADAT 1 */ |
| case 4: return 2; /* ADAT 2 */ |
| case 5: return 3; /* ADAT 3 */ |
| case 6: return 4; /* ADAT 4 */ |
| case 1: return 5; /* AES */ |
| case 2: return 6; /* SPDIF */ |
| case 10: return 7; /* SYNC_IN */ |
| } |
| } |
| |
| break; |
| |
| case AIO: |
| if (hdspm->tco) { |
| switch ((hdspm->settings_register & |
| HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { |
| case 0: return 0; /* WC */ |
| case 3: return 1; /* ADAT */ |
| case 1: return 2; /* AES */ |
| case 2: return 3; /* SPDIF */ |
| case 9: return 4; /* TCO */ |
| case 10: return 5; /* SYNC_IN */ |
| } |
| } else { |
| switch ((hdspm->settings_register & |
| HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { |
| case 0: return 0; /* WC */ |
| case 3: return 1; /* ADAT */ |
| case 1: return 2; /* AES */ |
| case 2: return 3; /* SPDIF */ |
| case 10: return 4; /* SYNC_IN */ |
| } |
| } |
| |
| break; |
| } |
| |
| return -1; |
| } |
| |
| |
| /** |
| * Set the preferred sync reference to <pref>. The semantics |
| * of <pref> are depending on the card type, see the comments |
| * for clarification. |
| **/ |
| static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) |
| { |
| int p = 0; |
| |
| switch (hdspm->io_type) { |
| case AES32: |
| hdspm->control_register &= ~HDSPM_SyncRefMask; |
| switch (pref) { |
| case 0: /* WC */ |
| break; |
| case 1: /* AES 1 */ |
| hdspm->control_register |= HDSPM_SyncRef0; |
| break; |
| case 2: /* AES 2 */ |
| hdspm->control_register |= HDSPM_SyncRef1; |
| break; |
| case 3: /* AES 3 */ |
| hdspm->control_register |= |
| HDSPM_SyncRef1+HDSPM_SyncRef0; |
| break; |
| case 4: /* AES 4 */ |
| hdspm->control_register |= HDSPM_SyncRef2; |
| break; |
| case 5: /* AES 5 */ |
| hdspm->control_register |= |
| HDSPM_SyncRef2+HDSPM_SyncRef0; |
| break; |
| case 6: /* AES 6 */ |
| hdspm->control_register |= |
| HDSPM_SyncRef2+HDSPM_SyncRef1; |
| break; |
| case 7: /* AES 7 */ |
| hdspm->control_register |= |
| HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; |
| break; |
| case 8: /* AES 8 */ |
| hdspm->control_register |= HDSPM_SyncRef3; |
| break; |
| case 9: /* TCO */ |
| hdspm->control_register |= |
| HDSPM_SyncRef3+HDSPM_SyncRef0; |
| break; |
| default: |
| return -1; |
| } |
| |
| break; |
| |
| case MADI: |
| case MADIface: |
| hdspm->control_register &= ~HDSPM_SyncRefMask; |
| if (hdspm->tco) { |
| switch (pref) { |
| case 0: /* WC */ |
| break; |
| case 1: /* MADI */ |
| hdspm->control_register |= HDSPM_SyncRef0; |
| break; |
| case 2: /* TCO */ |
| hdspm->control_register |= HDSPM_SyncRef1; |
| break; |
| case 3: /* SYNC_IN */ |
| hdspm->control_register |= |
| HDSPM_SyncRef0+HDSPM_SyncRef1; |
| break; |
| default: |
| return -1; |
| } |
| } else { |
| switch (pref) { |
| case 0: /* WC */ |
| break; |
| case 1: /* MADI */ |
| hdspm->control_register |= HDSPM_SyncRef0; |
| break; |
| case 2: /* SYNC_IN */ |
| hdspm->control_register |= |
| HDSPM_SyncRef0+HDSPM_SyncRef1; |
| break; |
| default: |
| return -1; |
| } |
| } |
| |
| break; |
| |
| case RayDAT: |
| if (hdspm->tco) { |
| switch (pref) { |
| case 0: p = 0; break; /* WC */ |
| case 1: p = 3; break; /* ADAT 1 */ |
| case 2: p = 4; break; /* ADAT 2 */ |
| case 3: p = 5; break; /* ADAT 3 */ |
| case 4: p = 6; break; /* ADAT 4 */ |
| case 5: p = 1; break; /* AES */ |
| case 6: p = 2; break; /* SPDIF */ |
| case 7: p = 9; break; /* TCO */ |
| case 8: p = 10; break; /* SYNC_IN */ |
| default: return -1; |
| } |
| } else { |
| switch (pref) { |
| case 0: p = 0; break; /* WC */ |
| case 1: p = 3; break; /* ADAT 1 */ |
| case 2: p = 4; break; /* ADAT 2 */ |
| case 3: p = 5; break; /* ADAT 3 */ |
| case 4: p = 6; break; /* ADAT 4 */ |
| case 5: p = 1; break; /* AES */ |
| case 6: p = 2; break; /* SPDIF */ |
| case 7: p = 10; break; /* SYNC_IN */ |
| default: return -1; |
| } |
| } |
| break; |
| |
| case AIO: |
| if (hdspm->tco) { |
| switch (pref) { |
| case 0: p = 0; break; /* WC */ |
| case 1: p = 3; break; /* ADAT */ |
| case 2: p = 1; break; /* AES */ |
| case 3: p = 2; break; /* SPDIF */ |
| case 4: p = 9; break; /* TCO */ |
| case 5: p = 10; break; /* SYNC_IN */ |
| default: return -1; |
| } |
| } else { |
| switch (pref) { |
| case 0: p = 0; break; /* WC */ |
| case 1: p = 3; break; /* ADAT */ |
| case 2: p = 1; break; /* AES */ |
| case 3: p = 2; break; /* SPDIF */ |
| case 4: p = 10; break; /* SYNC_IN */ |
| default: return -1; |
| } |
| } |
| break; |
| } |
| |
| switch (hdspm->io_type) { |
| case RayDAT: |
| case AIO: |
| hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; |
| hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; |
| hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); |
| break; |
| |
| case MADI: |
| case MADIface: |
| case AES32: |
| hdspm_write(hdspm, HDSPM_controlRegister, |
| hdspm->control_register); |
| } |
| |
| return 0; |
| } |
| |
| |
| static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_info *uinfo) |
| { |
| struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
| |
| uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
| uinfo->count = 1; |
| uinfo->value.enumerated.items = hdspm->texts_autosync_items; |
| |
| if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) |
| uinfo->value.enumerated.item = |
| uinfo->value.enumerated.items - 1; |
| |
| strcpy(uinfo->value.enumerated.name, |
| hdspm->texts_autosync[uinfo->value.enumerated.item]); |
| |
| return 0; |
| } |
| |
| static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_value *ucontrol) |
| { |
| struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
| int psf = hdspm_pref_sync_ref(hdspm); |
| |
| if (psf >= 0) { |
| ucontrol->value.enumerated.item[0] = psf; |
| return 0; |
| } |
| |
| return -1; |
| } |
| |
| static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_value *ucontrol) |
| { |
| struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
| int val, change = 0; |
| |
| if (!snd_hdspm_use_is_exclusive(hdspm)) |
| return -EBUSY; |
| |
| val = ucontrol->value.enumerated.item[0]; |
| |
| if (val < 0) |
| val = 0; |
| else if (val >= hdspm->texts_autosync_items) |
| val = hdspm->texts_autosync_items-1; |
| |
| spin_lock_irq(&hdspm->lock); |
| if (val != hdspm_pref_sync_ref(hdspm)) |
| change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; |
| |
| spin_unlock_irq(&hdspm->lock); |
| return change; |
| } |
| |
| |
| #define HDSPM_AUTOSYNC_REF(xname, xindex) \ |
| { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
| .name = xname, \ |
| .index = xindex, \ |
| .access = SNDRV_CTL_ELEM_ACCESS_READ, \ |
| .info = snd_hdspm_info_autosync_ref, \ |
| .get = snd_hdspm_get_autosync_ref, \ |
| } |
| |
| static int hdspm_autosync_ref(struct hdspm *hdspm) |
| { |
| if (AES32 == hdspm->io_type) { |
| unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); |
| unsigned int syncref = |
| (status >> HDSPM_AES32_syncref_bit) & 0xF; |
| if (syncref == 0) |
| return HDSPM_AES32_AUTOSYNC_FROM_WORD; |
| if (syncref <= 8) |
| return syncref; |
| return HDSPM_AES32_AUTOSYNC_FROM_NONE; |
| } else if (MADI == hdspm->io_type) { |
| /* This looks at the autosync selected sync reference */ |
| unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); |
| |
| switch (status2 & HDSPM_SelSyncRefMask) { |
| case HDSPM_SelSyncRef_WORD: |
| return HDSPM_AUTOSYNC_FROM_WORD; |
| case HDSPM_SelSyncRef_MADI: |
| return HDSPM_AUTOSYNC_FROM_MADI; |
| case HDSPM_SelSyncRef_TCO: |
| return HDSPM_AUTOSYNC_FROM_TCO; |
| case HDSPM_SelSyncRef_SyncIn: |
| return HDSPM_AUTOSYNC_FROM_SYNC_IN; |
| case HDSPM_SelSyncRef_NVALID: |
| return HDSPM_AUTOSYNC_FROM_NONE; |
| default: |
| return 0; |
| } |
| |
| } |
| return 0; |
| } |
| |
| |
| static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_info *uinfo) |
| { |
| struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
| |
| if (AES32 == hdspm->io_type) { |
| static char *texts[] = { "WordClock", "AES1", "AES2", "AES3", |
| "AES4", "AES5", "AES6", "AES7", "AES8", "None"}; |
|