Merge "xhci: xhci_configure_endpoint: use non-interruptible wait_for_completion" into edison-3.10
diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
index 808e53a..f686910 100644
--- a/drivers/spi/intel_mid_ssp_spi.c
+++ b/drivers/spi/intel_mid_ssp_spi.c
@@ -544,7 +544,7 @@
 
 		/* In Rx direction, TRAIL Bytes are handled by memcpy */
 		if (sspc->rx_dma &&
-			(sspc->len_dma_rx >
+			(sspc->len_dma_rx >=
 				sspc->rx_fifo_threshold * sspc->n_bytes))
 		{
 			sspc->len_dma_rx = TRUNCATE(sspc->len_dma_rx,
@@ -695,8 +695,8 @@
 		sspc->len = sspc->len - sspc->len_dma_rx;
 		sspc->cur_msg->actual_length = sspc->len_dma_rx;
 
-		while ((sspc->tx != sspc->tx_end) ||
-			(sspc->rx != sspc->rx_end)) {
+		while ((sspc->tx < sspc->tx_end) ||
+			(sspc->rx < sspc->rx_end)) {
 			sspc->read(sspc);
 			sspc->write(sspc);
 		}
@@ -749,9 +749,6 @@
 		sspc->cs_control(!sspc->cs_assert);
 
 	dev_dbg(dev, "End of transfer. SSSR:%08X\n", read_SSSR(reg));
-	msg = sspc->cur_msg;
-	if (likely(msg->complete))
-		msg->complete(msg->context);
 	complete(&sspc->msg_done);
 }
 
@@ -964,7 +961,6 @@
 	u32 mask = 0;
 	int bits_per_word, saved_bits_per_word;
 	unsigned long flags;
-	u8 normal_enabled = 0;
 
 	chip = spi_get_ctldata(msg->spi);
 
@@ -980,7 +976,13 @@
 	dma_enabled = chip->dma_enabled;
 	spin_unlock_irqrestore(&sspc->lock, flags);
 
+	/* multiple transfers must be serialized and this complete() is needed in order
+        to be able to process the transfers list in a generic way */
+	complete(&sspc->msg_done);
+
 	list_for_each_entry(transfer, &msg->transfers, transfer_list) {
+		wait_for_completion(&sspc->msg_done);
+		INIT_COMPLETION(sspc->msg_done);
 
 		/* Check transfer length */
 		if (unlikely((transfer->len > MAX_SPI_TRANSFER_SIZE) ||
@@ -1053,28 +1055,16 @@
 			sspc->n_bytes = 1;
 			sspc->read = u8_reader;
 			sspc->write = u8_writer;
-			/* It maybe has some unclear issue in dma mode, as workaround,
-			use normal mode to transfer when len equal 8 bytes */
-			if (transfer->len == 8)
-				normal_enabled = 1;
 		} else if (bits_per_word <= 16) {
 			sspc->n_bytes = 2;
 			sspc->read = u16_reader;
 			sspc->write = u16_writer;
-			/* It maybe has some unclear issue in dma mode, as workaround,
-			use normal mode to transfer when len equal 16 bytes */
-			if (transfer->len == 16)
-				normal_enabled = 1;
 		} else if (bits_per_word <= 32) {
 			if (!ssp_timing_wr)
 				cr0 |= SSCR0_EDSS;
 			sspc->n_bytes = 4;
 			sspc->read = u32_reader;
 			sspc->write = u32_writer;
-			/* It maybe has some unclear issue in dma mode, as workaround,
-			use normal mode to transfer when len equal 32 bytes */
-			if (transfer->len == 32)
-				normal_enabled = 1;
 		}
 
 		sspc->tx  = (void *)transfer->tx_buf;
@@ -1113,7 +1103,7 @@
 			/* value. The RX fifo threshold must be aligned with the DMA */
 			/* RX transfer size, which may be limited to a multiple of 4 */
 			/* bytes due to 32bits DDR access.                           */
-			if  (sspc->len / sspc->n_bytes <= sspc->rx_fifo_threshold) {
+			if  (sspc->len / sspc->n_bytes < sspc->rx_fifo_threshold) {
 				u32 rx_fifo_threshold;
 
 				rx_fifo_threshold = (sspc->len & ~(4 - 1)) /
@@ -1175,7 +1165,7 @@
 		if (sspc->cs_control)
 			sspc->cs_control(sspc->cs_assert);
 
-		if (likely(dma_enabled) && (!normal_enabled)) {
+		if (likely(dma_enabled)) {
 			if (unlikely(sspc->quirks & QUIRKS_USE_PM_QOS))
 				pm_qos_update_request(&sspc->pm_qos_req,
 						MIN_EXIT_LATENCY);
@@ -1184,6 +1174,8 @@
 			/* Do the transfer syncronously */
 			queue_work(sspc->wq_poll_write, &sspc->poll_write);
 			poll_transfer((unsigned long)sspc);
+			unmap_dma_buffers(sspc);
+			complete(&sspc->msg_done);
 		}
 
 		if (list_is_last(&transfer->transfer_list, &msg->transfers)
@@ -1194,13 +1186,11 @@
 
 	} /* end of list_for_each_entry */
 
+	wait_for_completion(&sspc->msg_done);
+
 	/* Now we are done with this entire message */
-	if ((!dma_enabled) || (normal_enabled)) {
-		unmap_dma_buffers(sspc);
-		if (likely(msg->complete))
-			msg->complete(msg->context);
-		complete(&sspc->msg_done);
-	}
+	if (likely(msg->complete))
+		msg->complete(msg->context);
 
 	return 0;
 }
@@ -1222,9 +1212,7 @@
 		list_del_init(&msg->queue);
 		sspc->cur_msg = msg;
 		spin_unlock_irqrestore(&sspc->lock, flags);
-		INIT_COMPLETION(sspc->msg_done);
 		handle_message(sspc);
-		wait_for_completion(&sspc->msg_done);
 		spin_lock_irqsave(&sspc->lock, flags);
 		sspc->cur_msg = NULL;
 	}
@@ -1254,10 +1242,11 @@
 	if (!spi->bits_per_word)
 		spi->bits_per_word = DFLT_BITS_PER_WORD;
 
-	if ((spi->bits_per_word < MIN_BITS_PER_WORD
-		|| spi->bits_per_word > MAX_BITS_PER_WORD)) {
-		ret = -EINVAL;
-		goto exit_setup;
+	if ((spi->bits_per_word != 8) && (spi->bits_per_word != 16)
+		&& (spi->bits_per_word != 32)) {
+		spin_unlock_irqrestore(&sspc->lock, flags);
+		dev_warn(&spi->dev, "invalid wordsize, system only support 8,16,32 bits per word.\n");
+		return -EINVAL;
 	}
 
 	chip = spi_get_ctldata(spi);
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index a08f923..12112a1 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -438,7 +438,8 @@
 		break;
 
 	default:
-		/* segmented and/or full-duplex I/O request */
+		/* segmented and/or full-duplex I/O request.
+		   Note: Maximum support 511 n_ioc at a time */
 		if (_IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0))
 				|| _IOC_DIR(cmd) != _IOC_WRITE) {
 			retval = -ENOTTY;
@@ -452,7 +453,10 @@
 		}
 		n_ioc = tmp / sizeof(struct spi_ioc_transfer);
 		if (n_ioc == 0)
+		{
+			dev_err(&spi->dev, "Value of n_ioc is out of range( 1 ~ 511 ).\n");
 			break;
+		}
 
 		/* copy into scratch area */
 		ioc = kmalloc(tmp, GFP_KERNEL);
diff --git a/sound/soc/intel/effects.c b/sound/soc/intel/effects.c
index 4de0ec3..d03cdfa 100644
--- a/sound/soc/intel/effects.c
+++ b/sound/soc/intel/effects.c
@@ -291,7 +291,7 @@
 					struct snd_effect_params *params)
 {
 	int ret = 0;
-	u8 pipe_id;
+	u8 pipe_id = 0;
 	u16 algo_id;
 	struct ipc_effect_payload dsp_payload;
 	struct sst_data *sst;
@@ -324,7 +324,7 @@
 					struct snd_effect_params *params)
 {
 	int ret = 0;
-	u8 pipe_id;
+	u8 pipe_id = 0;
 	u16 algo_id;
 	struct ipc_effect_payload dsp_payload;
 	struct sst_data *sst;