| /******************************************************************* |
| * (c) Copyright 2011-2012 Discretix Technologies Ltd. * |
| * This software is protected by copyright, international * |
| * treaties and patents, and distributed under multiple licenses. * |
| * Any use of this Software as part of the Discretix CryptoCell or * |
| * Packet Engine products requires a commercial license. * |
| * Copies of this Software that are distributed with the Discretix * |
| * CryptoCell or Packet Engine product drivers, may be used in * |
| * accordance with a commercial license, or at the user's option, * |
| * used and redistributed under the terms and conditions of the GNU * |
| * General Public License ("GPL") version 2, as published by the * |
| * Free Software Foundation. * |
| * This program is distributed in the hope that it will be useful, * |
| * but WITHOUT ANY LIABILITY AND WARRANTY; without even the implied * |
| * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * |
| * See the GNU General Public License version 2 for more details. * |
| * You should have received a copy of the GNU General Public * |
| * License version 2 along with this Software; if not, please write * |
| * to the Free Software Foundation, Inc., 59 Temple Place - Suite * |
| * 330, Boston, MA 02111-1307, USA. * |
| * Any copy or reproduction of this Software, as permitted under * |
| * the GNU General Public License version 2, must include this * |
| * Copyright Notice as well as any other notices provided under * |
| * the said license. * |
| ********************************************************************/ |
| #ifndef __DX_HOST_H__ |
| #define __DX_HOST_H__ |
| /* -------------------------------------- */ |
| /* BLOCK: HOST */ |
| /* -------------------------------------- */ |
| #define DX_HOST_IRR_REG_OFFSET 0xA00UL |
| #define DX_HOST_IRR_SEP_WATCHDOG_BIT_SHIFT 0x0UL |
| #define DX_HOST_IRR_SEP_WATCHDOG_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_DSCRPTR_DONE_LOW_INT_BIT_SHIFT 0x2UL |
| #define DX_HOST_IRR_DSCRPTR_DONE_LOW_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_HOST_SRAM_VIO_BIT_SHIFT 0x3UL |
| #define DX_HOST_IRR_HOST_SRAM_VIO_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_SRAM_TO_DIN_INT_BIT_SHIFT 0x4UL |
| #define DX_HOST_IRR_SRAM_TO_DIN_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_DOUT_TO_SRAM_INT_BIT_SHIFT 0x5UL |
| #define DX_HOST_IRR_DOUT_TO_SRAM_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_MEM_TO_DIN_INT_BIT_SHIFT 0x6UL |
| #define DX_HOST_IRR_MEM_TO_DIN_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_DOUT_TO_MEM_INT_BIT_SHIFT 0x7UL |
| #define DX_HOST_IRR_DOUT_TO_MEM_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT 0x8UL |
| #define DX_HOST_IRR_AXI_ERR_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_PKA_EXP_INT_BIT_SHIFT 0x9UL |
| #define DX_HOST_IRR_PKA_EXP_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_RNG_INT_BIT_SHIFT 0xAUL |
| #define DX_HOST_IRR_RNG_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_SEP_HOST_GPR0_INT_BIT_SHIFT 0xBUL |
| #define DX_HOST_IRR_SEP_HOST_GPR0_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_SEP_HOST_GPR1_INT_BIT_SHIFT 0xCUL |
| #define DX_HOST_IRR_SEP_HOST_GPR1_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_SEP_HOST_GPR2_INT_BIT_SHIFT 0xDUL |
| #define DX_HOST_IRR_SEP_HOST_GPR2_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_SEP_HOST_GPR3_INT_BIT_SHIFT 0xEUL |
| #define DX_HOST_IRR_SEP_HOST_GPR3_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_SEP_HOST_GPR4_INT_BIT_SHIFT 0xFUL |
| #define DX_HOST_IRR_SEP_HOST_GPR4_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_SEP_HOST_GPR5_INT_BIT_SHIFT 0x10UL |
| #define DX_HOST_IRR_SEP_HOST_GPR5_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_SEP_HOST_GPR6_INT_BIT_SHIFT 0x11UL |
| #define DX_HOST_IRR_SEP_HOST_GPR6_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_SEP_HOST_GPR7_INT_BIT_SHIFT 0x12UL |
| #define DX_HOST_IRR_SEP_HOST_GPR7_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT 0x13UL |
| #define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_REG_OFFSET 0xA04UL |
| #define DX_HOST_IMR_SEP_WATCHDOG_MASK_BIT_SHIFT 0x0UL |
| #define DX_HOST_IMR_SEP_WATCHDOG_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_NOT_USED_MASK_BIT_SHIFT 0x1UL |
| #define DX_HOST_IMR_NOT_USED_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT 0x2UL |
| #define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_HOST_SRAM_VIO_MASK_BIT_SHIFT 0x3UL |
| #define DX_HOST_IMR_HOST_SRAM_VIO_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_SRAM_TO_DIN_MASK_BIT_SHIFT 0x4UL |
| #define DX_HOST_IMR_SRAM_TO_DIN_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_DOUT_TO_SRAM_MASK_BIT_SHIFT 0x5UL |
| #define DX_HOST_IMR_DOUT_TO_SRAM_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_MEM_TO_DIN_MASK_BIT_SHIFT 0x6UL |
| #define DX_HOST_IMR_MEM_TO_DIN_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_DOUT_TO_MEM_MASK_BIT_SHIFT 0x7UL |
| #define DX_HOST_IMR_DOUT_TO_MEM_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL |
| #define DX_HOST_IMR_AXI_ERR_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_PKA_EXP_MASK_BIT_SHIFT 0x9UL |
| #define DX_HOST_IMR_PKA_EXP_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_RNG_INT_MASK_BIT_SHIFT 0xAUL |
| #define DX_HOST_IMR_RNG_INT_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_SEP_HOST_GPR0_MASK_BIT_SHIFT 0xBUL |
| #define DX_HOST_IMR_SEP_HOST_GPR0_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_SEP_HOST_GPR1_MASK_BIT_SHIFT 0xCUL |
| #define DX_HOST_IMR_SEP_HOST_GPR1_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_SEP_HOST_GPR2_MASK_BIT_SHIFT 0xDUL |
| #define DX_HOST_IMR_SEP_HOST_GPR2_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_SEP_HOST_GPR3_MASK_BIT_SHIFT 0xEUL |
| #define DX_HOST_IMR_SEP_HOST_GPR3_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_SEP_HOST_GPR4_MASK_BIT_SHIFT 0xFUL |
| #define DX_HOST_IMR_SEP_HOST_GPR4_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_SEP_HOST_GPR5_MASK_BIT_SHIFT 0x10UL |
| #define DX_HOST_IMR_SEP_HOST_GPR5_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_SEP_HOST_GPR6_MASK_BIT_SHIFT 0x11UL |
| #define DX_HOST_IMR_SEP_HOST_GPR6_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_SEP_HOST_GPR7_MASK_BIT_SHIFT 0x12UL |
| #define DX_HOST_IMR_SEP_HOST_GPR7_MASK_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT 0x13UL |
| #define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK1_BIT_SHIFT 0x14UL |
| #define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK1_BIT_SIZE 0x1UL |
| #define DX_HOST_IMR_CNTX_SWITCH_CNTR_EXPIRED_BIT_SHIFT 0x15UL |
| #define DX_HOST_IMR_CNTX_SWITCH_CNTR_EXPIRED_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_REG_OFFSET 0xA08UL |
| #define DX_HOST_ICR_SEP_WATCHDOG_CLEAR_BIT_SHIFT 0x0UL |
| #define DX_HOST_ICR_SEP_WATCHDOG_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT 0x2UL |
| #define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_HOST_SRAM_VIO_CLEAR_BIT_SHIFT 0x3UL |
| #define DX_HOST_ICR_HOST_SRAM_VIO_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_SRAM_TO_DIN_CLEAR_BIT_SHIFT 0x4UL |
| #define DX_HOST_ICR_SRAM_TO_DIN_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_DOUT_TO_SRAM_CLEAR_BIT_SHIFT 0x5UL |
| #define DX_HOST_ICR_DOUT_TO_SRAM_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_MEM_TO_DIN_CLEAR_BIT_SHIFT 0x6UL |
| #define DX_HOST_ICR_MEM_TO_DIN_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_DOUT_TO_MEM_CLEAR_BIT_SHIFT 0x7UL |
| #define DX_HOST_ICR_DOUT_TO_MEM_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL |
| #define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_PKA_EXP_CLEAR_BIT_SHIFT 0x9UL |
| #define DX_HOST_ICR_PKA_EXP_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_RNG_INT_CLEAR_BIT_SHIFT 0xAUL |
| #define DX_HOST_ICR_RNG_INT_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_SEP_HOST_GPR0_CLEAR_BIT_SHIFT 0xBUL |
| #define DX_HOST_ICR_SEP_HOST_GPR0_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_SEP_HOST_GPR1_CLEAR_BIT_SHIFT 0xCUL |
| #define DX_HOST_ICR_SEP_HOST_GPR1_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_SEP_HOST_GPR2_CLEAR_BIT_SHIFT 0xDUL |
| #define DX_HOST_ICR_SEP_HOST_GPR2_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_SEP_HOST_GPR3_CLEAR_BIT_SHIFT 0xEUL |
| #define DX_HOST_ICR_SEP_HOST_GPR3_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_SEP_HOST_GPR4_CLEAR_BIT_SHIFT 0xFUL |
| #define DX_HOST_ICR_SEP_HOST_GPR4_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_SEP_HOST_GPR5_CLEAR_BIT_SHIFT 0x10UL |
| #define DX_HOST_ICR_SEP_HOST_GPR5_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_SEP_HOST_GPR6_CLEAR_BIT_SHIFT 0x11UL |
| #define DX_HOST_ICR_SEP_HOST_GPR6_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_SEP_HOST_GPR7_CLEAR_BIT_SHIFT 0x12UL |
| #define DX_HOST_ICR_SEP_HOST_GPR7_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT 0x13UL |
| #define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL |
| #define DX_HOST_SEP_SRAM_THRESHOLD_REG_OFFSET 0xA10UL |
| #define DX_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SIZE 0x10UL |
| #define DX_HOST_SEP_BUSY_REG_OFFSET 0xA14UL |
| #define DX_HOST_SEP_BUSY_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_SEP_BUSY_VALUE_BIT_SIZE 0x1UL |
| #define DX_HOST_SEP_SW_MONITOR_REG_OFFSET 0xA20UL |
| #define DX_HOST_SEP_SW_MONITOR_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_SEP_SW_MONITOR_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_CC_SW_RST_REG_OFFSET 0xA40UL |
| #define DX_HOST_CC_SW_RST_CC_SW_RST_REQ_BIT_SHIFT 0x0UL |
| #define DX_HOST_CC_SW_RST_CC_SW_RST_REQ_BIT_SIZE 0x1UL |
| #define DX_HOST_CC_SW_RST_CC_SW_RST_FORCE_BIT_SHIFT 0x1UL |
| #define DX_HOST_CC_SW_RST_CC_SW_RST_FORCE_BIT_SIZE 0x1UL |
| #define DX_HOST_CC_SW_RST_AXIS_SYSREQ_BIT_SHIFT 0x2UL |
| #define DX_HOST_CC_SW_RST_AXIS_SYSREQ_BIT_SIZE 0x1UL |
| #define DX_HOST_CC_SW_RST_AXIM_SYSREQ_BIT_SHIFT 0x3UL |
| #define DX_HOST_CC_SW_RST_AXIM_SYSREQ_BIT_SIZE 0x1UL |
| #define DX_HOST_SEP_HOST_GPR0_REG_OFFSET 0xA80UL |
| #define DX_HOST_SEP_HOST_GPR0_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_SEP_HOST_GPR0_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_SEP_HOST_GPR1_REG_OFFSET 0xA88UL |
| #define DX_HOST_SEP_HOST_GPR1_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_SEP_HOST_GPR1_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_SEP_HOST_GPR2_REG_OFFSET 0xA90UL |
| #define DX_HOST_SEP_HOST_GPR2_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_SEP_HOST_GPR2_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_SEP_HOST_GPR3_REG_OFFSET 0xA98UL |
| #define DX_HOST_SEP_HOST_GPR3_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_SEP_HOST_GPR3_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_SEP_HOST_GPR4_REG_OFFSET 0xAA0UL |
| #define DX_HOST_SEP_HOST_GPR4_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_SEP_HOST_GPR4_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_SEP_HOST_GPR5_REG_OFFSET 0xAA8UL |
| #define DX_HOST_SEP_HOST_GPR5_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_SEP_HOST_GPR5_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_SEP_HOST_GPR6_REG_OFFSET 0xAB0UL |
| #define DX_HOST_SEP_HOST_GPR6_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_SEP_HOST_GPR6_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_SEP_HOST_GPR7_REG_OFFSET 0xAB8UL |
| #define DX_HOST_SEP_HOST_GPR7_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_SEP_HOST_GPR7_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_HOST_SEP_GPR0_REG_OFFSET 0xA84UL |
| #define DX_HOST_HOST_SEP_GPR0_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_HOST_SEP_GPR0_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_HOST_SEP_GPR1_REG_OFFSET 0xA8CUL |
| #define DX_HOST_HOST_SEP_GPR1_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_HOST_SEP_GPR1_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_HOST_SEP_GPR2_REG_OFFSET 0xA94UL |
| #define DX_HOST_HOST_SEP_GPR2_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_HOST_SEP_GPR2_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_HOST_SEP_GPR3_REG_OFFSET 0xA9CUL |
| #define DX_HOST_HOST_SEP_GPR3_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_HOST_SEP_GPR3_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_HOST_SEP_GPR4_REG_OFFSET 0xAA4UL |
| #define DX_HOST_HOST_SEP_GPR4_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_HOST_SEP_GPR4_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_HOST_SEP_GPR5_REG_OFFSET 0xAACUL |
| #define DX_HOST_HOST_SEP_GPR5_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_HOST_SEP_GPR5_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_HOST_SEP_GPR6_REG_OFFSET 0xAB4UL |
| #define DX_HOST_HOST_SEP_GPR6_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_HOST_SEP_GPR6_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_HOST_SEP_GPR7_REG_OFFSET 0xABCUL |
| #define DX_HOST_HOST_SEP_GPR7_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_HOST_SEP_GPR7_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_HOST_ENDIAN_REG_OFFSET 0xAD0UL |
| #define DX_HOST_HOST_ENDIAN_DIN_ICACHE_END_BIT_SHIFT 0x0UL |
| #define DX_HOST_HOST_ENDIAN_DIN_ICACHE_END_BIT_SIZE 0x1UL |
| #define DX_HOST_HOST_ENDIAN_DIN_DCAHE_END_BIT_SHIFT 0x1UL |
| #define DX_HOST_HOST_ENDIAN_DIN_DCAHE_END_BIT_SIZE 0x1UL |
| #define DX_HOST_HOST_ENDIAN_DIN_DD_END_BIT_SHIFT 0x2UL |
| #define DX_HOST_HOST_ENDIAN_DIN_DD_END_BIT_SIZE 0x1UL |
| #define DX_HOST_HOST_ENDIAN_DIN_DMA_END_BIT_SHIFT 0x3UL |
| #define DX_HOST_HOST_ENDIAN_DIN_DMA_END_BIT_SIZE 0x1UL |
| #define DX_HOST_HOST_ENDIAN_DOUT_ICACHE_END_BIT_SHIFT 0x4UL |
| #define DX_HOST_HOST_ENDIAN_DOUT_ICACHE_END_BIT_SIZE 0x1UL |
| #define DX_HOST_HOST_ENDIAN_DOUT_DCACHE_END_BIT_SHIFT 0x5UL |
| #define DX_HOST_HOST_ENDIAN_DOUT_DCACHE_END_BIT_SIZE 0x1UL |
| #define DX_HOST_HOST_ENDIAN_DOUT_DD_END_BIT_SHIFT 0x6UL |
| #define DX_HOST_HOST_ENDIAN_DOUT_DD_END_BIT_SIZE 0x1UL |
| #define DX_HOST_HOST_ENDIAN_DOUT_DMA_END_BIT_SHIFT 0x7UL |
| #define DX_HOST_HOST_ENDIAN_DOUT_DMA_END_BIT_SIZE 0x1UL |
| #define DX_HOST_HOST_ENDIAN_INTENAL_WORD_END_BIT_SHIFT 0x8UL |
| #define DX_HOST_HOST_ENDIAN_INTENAL_WORD_END_BIT_SIZE 0x8UL |
| #define DX_SRAM_DATA_REG_OFFSET 0xF00UL |
| #define DX_SRAM_DATA_VALUE_BIT_SHIFT 0x0UL |
| #define DX_SRAM_DATA_VALUE_BIT_SIZE 0x20UL |
| #define DX_SRAM_ADDR_REG_OFFSET 0xF04UL |
| #define DX_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL |
| #define DX_SRAM_ADDR_VALUE_BIT_SIZE 0xFUL |
| #define DX_SRAM_DATA_READY_REG_OFFSET 0xF08UL |
| #define DX_SRAM_DATA_READY_VALUE_BIT_SHIFT 0x0UL |
| #define DX_SRAM_DATA_READY_VALUE_BIT_SIZE 0x1UL |
| #define DX_HOST_RKEK1_0_REG_OFFSET 0xA00UL |
| #define DX_HOST_RKEK1_0_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK1_0_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK1_1_REG_OFFSET 0xA04UL |
| #define DX_HOST_RKEK1_1_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK1_1_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK1_2_REG_OFFSET 0xA08UL |
| #define DX_HOST_RKEK1_2_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK1_2_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK1_3_REG_OFFSET 0xA0CUL |
| #define DX_HOST_RKEK1_3_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK1_3_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK1_4_REG_OFFSET 0xA10UL |
| #define DX_HOST_RKEK1_4_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK1_4_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK1_5_REG_OFFSET 0xA14UL |
| #define DX_HOST_RKEK1_5_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK1_5_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK1_6_REG_OFFSET 0xA18UL |
| #define DX_HOST_RKEK1_6_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK1_6_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK1_7_REG_OFFSET 0xA1CUL |
| #define DX_HOST_RKEK1_7_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK1_7_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK1_ECC_REG_OFFSET 0xA20UL |
| #define DX_HOST_RKEK1_ECC_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK1_ECC_VALUE_BIT_SIZE 0x20UL |
| #define DX_LCS_REG_REG_OFFSET 0xA24UL |
| #define DX_LCS_REG_VALUE_BIT_SHIFT 0x0UL |
| #define DX_LCS_REG_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK2_0_REG_OFFSET 0xA2CUL |
| #define DX_HOST_RKEK2_0_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK2_0_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK2_1_REG_OFFSET 0xA30UL |
| #define DX_HOST_RKEK2_1_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK2_1_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK2_2_REG_OFFSET 0xA34UL |
| #define DX_HOST_RKEK2_2_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK2_2_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK2_3_REG_OFFSET 0xA38UL |
| #define DX_HOST_RKEK2_3_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK2_3_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK2_4_REG_OFFSET 0xA3CUL |
| #define DX_HOST_RKEK2_4_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK2_4_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK2_5_REG_OFFSET 0xA40UL |
| #define DX_HOST_RKEK2_5_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK2_5_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK2_6_REG_OFFSET 0xA44UL |
| #define DX_HOST_RKEK2_6_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK2_6_VALUE_BIT_SIZE 0x20UL |
| #define DX_HOST_RKEK2_7_REG_OFFSET 0xA48UL |
| #define DX_HOST_RKEK2_7_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_RKEK2_7_VALUE_BIT_SIZE 0x20UL |
| #define DX_NVM_CC_BOOT_REG_OFFSET 0xAA4UL |
| #define DX_NVM_CC_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT 0x1UL |
| #define DX_NVM_CC_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL |
| #define DX_NVM_CC_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT 0x2UL |
| #define DX_NVM_CC_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CNTR0_REG_OFFSET 0xA50UL |
| #define DX_PAU_HOST_CNTR0_VALUE_BIT_SHIFT 0x0UL |
| #define DX_PAU_HOST_CNTR0_VALUE_BIT_SIZE 0x20UL |
| #define DX_PAU_HOST_CNTR1_REG_OFFSET 0xA54UL |
| #define DX_PAU_HOST_CNTR1_VALUE_BIT_SHIFT 0x0UL |
| #define DX_PAU_HOST_CNTR1_VALUE_BIT_SIZE 0x20UL |
| #define DX_PAU_HOST_CNTR2_REG_OFFSET 0xA58UL |
| #define DX_PAU_HOST_CNTR2_VALUE_BIT_SHIFT 0x0UL |
| #define DX_PAU_HOST_CNTR2_VALUE_BIT_SIZE 0x20UL |
| #define DX_PAU_HOST_CNTR3_REG_OFFSET 0xA5CUL |
| #define DX_PAU_HOST_CNTR3_VALUE_BIT_SHIFT 0x0UL |
| #define DX_PAU_HOST_CNTR3_VALUE_BIT_SIZE 0x20UL |
| #define DX_PAU_HOST_CNTR4_REG_OFFSET 0xA60UL |
| #define DX_PAU_HOST_CNTR4_VALUE_BIT_SHIFT 0x0UL |
| #define DX_PAU_HOST_CNTR4_VALUE_BIT_SIZE 0x20UL |
| #define DX_PAU_HOST_XOR_REG_OFFSET 0xA64UL |
| #define DX_PAU_HOST_XOR_VALUE_BIT_SHIFT 0x0UL |
| #define DX_PAU_HOST_XOR_VALUE_BIT_SIZE 0x20UL |
| #define DX_PAU_HOST_MASK0_REG_OFFSET 0xA68UL |
| #define DX_PAU_HOST_MASK0_PAU_HOST_MASK0_BIT_SHIFT 0x0UL |
| #define DX_PAU_HOST_MASK0_PAU_HOST_MASK0_BIT_SIZE 0xDUL |
| #define DX_PAU_HOST_MASK0_UN_USED_BIT_SHIFT 0xDUL |
| #define DX_PAU_HOST_MASK0_UN_USED_BIT_SIZE 0x13UL |
| #define DX_PAU_HOST_MASK1_REG_OFFSET 0xA6CUL |
| #define DX_PAU_HOST_MASK1_PAU_HOST_MASK1_BIT_SHIFT 0x0UL |
| #define DX_PAU_HOST_MASK1_PAU_HOST_MASK1_BIT_SIZE 0x19UL |
| #define DX_PAU_HOST_MASK1_UN_USED_BIT_SHIFT 0x19UL |
| #define DX_PAU_HOST_MASK1_UN_USED_BIT_SIZE 0x7UL |
| #define DX_PAU_HOST_MASK2_REG_OFFSET 0xA70UL |
| #define DX_PAU_HOST_MASK2_PAU_HOST_MASK2_BIT_SHIFT 0x0UL |
| #define DX_PAU_HOST_MASK2_PAU_HOST_MASK2_BIT_SIZE 0x19UL |
| #define DX_PAU_HOST_MASK2_UN_USED_BIT_SHIFT 0x19UL |
| #define DX_PAU_HOST_MASK2_UN_USED_BIT_SIZE 0x7UL |
| #define DX_PAU_HOST_MASK3_REG_OFFSET 0xA74UL |
| #define DX_PAU_HOST_MASK3_PAU_HOST_MASK3_BIT_SHIFT 0x0UL |
| #define DX_PAU_HOST_MASK3_PAU_HOST_MASK3_BIT_SIZE 0x1EUL |
| #define DX_PAU_HOST_MASK3_UN_USED_BIT_SHIFT 0x1EUL |
| #define DX_PAU_HOST_MASK3_UN_USED_BIT_SIZE 0x2UL |
| #define DX_PAU_HOST_MASK4_REG_OFFSET 0xA78UL |
| #define DX_PAU_HOST_MASK4_PAU_HOST_MASK4_BIT_SHIFT 0x0UL |
| #define DX_PAU_HOST_MASK4_PAU_HOST_MASK4_BIT_SIZE 0x1EUL |
| #define DX_PAU_HOST_MASK4_UN_USED_BIT_SHIFT 0x1EUL |
| #define DX_PAU_HOST_MASK4_UN_USED_BIT_SIZE 0x2UL |
| #define DX_PAU_HOST_CONFIG_REG_OFFSET 0xA7CUL |
| #define DX_PAU_HOST_CONFIG_WRAPAROUND0_BIT_SHIFT 0x0UL |
| #define DX_PAU_HOST_CONFIG_WRAPAROUND0_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_WRAPAROUND1_BIT_SHIFT 0x1UL |
| #define DX_PAU_HOST_CONFIG_WRAPAROUND1_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_WRAPAROUND2_BIT_SHIFT 0x2UL |
| #define DX_PAU_HOST_CONFIG_WRAPAROUND2_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_WRAPAROUND3_BIT_SHIFT 0x3UL |
| #define DX_PAU_HOST_CONFIG_WRAPAROUND3_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_WRAPAROUND4_BIT_SHIFT 0x4UL |
| #define DX_PAU_HOST_CONFIG_WRAPAROUND4_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_OVERFLOW_SIGNAL0_BIT_SHIFT 0x5UL |
| #define DX_PAU_HOST_CONFIG_OVERFLOW_SIGNAL0_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_OVERFLOW_SIGNAL1_BIT_SHIFT 0x6UL |
| #define DX_PAU_HOST_CONFIG_OVERFLOW_SIGNAL1_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_OVERFLOW_SIGNAL2_BIT_SHIFT 0x7UL |
| #define DX_PAU_HOST_CONFIG_OVERFLOW_SIGNAL2_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_OVERFLOW_SIGNAL3_BIT_SHIFT 0x8UL |
| #define DX_PAU_HOST_CONFIG_OVERFLOW_SIGNAL3_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_OVERFLOW_SIGNAL4_BIT_SHIFT 0x9UL |
| #define DX_PAU_HOST_CONFIG_OVERFLOW_SIGNAL4_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_ENABLE_COUNTING_BIT_SHIFT 0xAUL |
| #define DX_PAU_HOST_CONFIG_ENABLE_COUNTING_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_AND_COUNETER_EVENT_BIT_SHIFT 0xBUL |
| #define DX_PAU_HOST_CONFIG_AND_COUNETER_EVENT_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_ENABLE_COUNTING0_BIT_SHIFT 0xCUL |
| #define DX_PAU_HOST_CONFIG_ENABLE_COUNTING0_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_ENABLE_COUNTING1_BIT_SHIFT 0xDUL |
| #define DX_PAU_HOST_CONFIG_ENABLE_COUNTING1_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_ENABLE_COUNTING2_BIT_SHIFT 0xEUL |
| #define DX_PAU_HOST_CONFIG_ENABLE_COUNTING2_BIT_SIZE 0x1UL |
| #define DX_PAU_HOST_CONFIG_ENABLE_COUNTING3_BIT_SHIFT 0xFUL |
| #define DX_PAU_HOST_CONFIG_ENABLE_COUNTING3_BIT_SIZE 0x1UL |
| #define DX_HOST_REGION_MASK_REG_OFFSET 0xAC4UL |
| #define DX_HOST_REGION_MASK_HOST_REGION_SECURED_MASK_BIT_SHIFT 0x0UL |
| #define DX_HOST_REGION_MASK_HOST_REGION_SECURED_MASK_BIT_SIZE 0x10UL |
| #define DX_HOST_REGION_MASK_HOST_REGION_NON_SECURED_MASK_BIT_SHIFT 0x10UL |
| #define DX_HOST_REGION_MASK_HOST_REGION_NON_SECURED_MASK_BIT_SIZE 0x10UL |
| #define DX_HOST_REGION_GPRS_MASK_REG_OFFSET 0xAC0UL |
| #define DX_HOST_REGION_GPRS_MASK_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_REGION_GPRS_MASK_VALUE_BIT_SIZE 0x8UL |
| #define DX_HOST_CC_SW_RESET_ALLOWED_REG_OFFSET 0xA48UL |
| #define DX_HOST_CC_SW_RESET_ALLOWED_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_CC_SW_RESET_ALLOWED_VALUE_BIT_SIZE 0x1UL |
| #define DX_HOST_CC_SIGNATURE_REG_OFFSET 0xAC8UL |
| #define DX_HOST_CC_SIGNATURE_VALUE_BIT_SHIFT 0x0UL |
| #define DX_HOST_CC_SIGNATURE_VALUE_BIT_SIZE 0x20UL |
| |
| #endif /*__DX_HOST_H__*/ |
