MLK-11722 mxc IPUv3: PRE: Correct block mode bad update window calculation
In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.
In non-small y resolution cases(>9 lines), we choose to check the STORE_BLOCK_Y
field of the register HW_PRE_STRORE_ENGINE_STATUS to determine the bad window
to update the SDW_UDPATE bit of the PRE_CTRL register. According to the
description of the STRORE_BLOCK_Y field in block mode, the field indicates the
Y coordinate of the block currently being rendered. Thus, we should round up
the real display y resolution to 4 lines to align with the block high(the out-
standing lines are cropped by PRG and IPU). To maximize the safe window, we
just need to avoid updating the shadow bit during the last block of lines.
To conclude, the bad window for block mode is (store_block_y == 0 ||
store_block_y >= DIV_ROUND_UP(y_resolution, 4) - 1).
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 1e21175555e4f35f87130a5f8839fac6a3e998b5)
1 file changed
