Merge remote-tracking branch 'goog/oc-mr1-iot-dev' into oc-mr1-iot-release

Change-Id: I4c08ebd4396fd5e5c81ece250831590e60171dcc
diff --git a/arch/arm/cpu/armv7/mx7ulp/scg.c b/arch/arm/cpu/armv7/mx7ulp/scg.c
index ce731eb..bb8326d 100644
--- a/arch/arm/cpu/armv7/mx7ulp/scg.c
+++ b/arch/arm/cpu/armv7/mx7ulp/scg.c
@@ -356,7 +356,7 @@
 
 static u32 scg_nic_get_rate(enum scg_clk clk)
 {
-	u32 reg, val, rate;
+	u32 reg, val, rate, nic0_rate;
 	u32 shift, mask;
 
 	reg = readl(&scg1_regs->niccsr);
@@ -374,6 +374,7 @@
 	val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT;
 
 	rate = rate / (val + 1);
+	nic0_rate = rate;
 
 	clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate);
 
@@ -415,6 +416,10 @@
 		return 0;
 	}
 
+	/* On RevB, the nic_bus and nic_ext dividers are parallel not chained with nic div */
+	if (soc_rev() >= CHIP_REV_2_0)
+		rate = nic0_rate;
+
 	val = (reg & mask) >> shift;
 	rate = rate / (val + 1);
 
diff --git a/arch/arm/cpu/armv8/imx8m/Kconfig b/arch/arm/cpu/armv8/imx8m/Kconfig
index 0c23db3..a6ffef2 100644
--- a/arch/arm/cpu/armv8/imx8m/Kconfig
+++ b/arch/arm/cpu/armv8/imx8m/Kconfig
@@ -12,6 +12,11 @@
 	select IMX8M
 	select SUPPORT_SPL
 
+config TARGET_IMX8MQ_PHANBELL
+	bool "imx8mq_phanbell"
+	select IMX8M
+	select SUPPORT_SPL
+
 config TARGET_IMX8MQ_DDR3L_ARM2
 	bool "imx8mq_ddr3l_arm2"
 	select IMX8M
@@ -27,6 +32,7 @@
 config SYS_SOC
 	default "imx8m"
 
+source "board/freescale/imx8mq_phanbell/Kconfig"
 source "board/freescale/imx8mq_evk/Kconfig"
 source "board/freescale/imx8mq_arm2/Kconfig"
 
diff --git a/arch/arm/cpu/armv8/imx8m/Makefile b/arch/arm/cpu/armv8/imx8m/Makefile
index ed90ebd..9569466 100644
--- a/arch/arm/cpu/armv8/imx8m/Makefile
+++ b/arch/arm/cpu/armv8/imx8m/Makefile
@@ -6,3 +6,5 @@
 
 obj-y	+= lowlevel_init.o
 obj-y	+= clock.o clock_slice.o soc.o
+obj-$(CONFIG_VIDEO_IMXDCSS) += video_common.o
+
diff --git a/arch/arm/cpu/armv8/imx8m/video_common.c b/arch/arm/cpu/armv8/imx8m/video_common.c
new file mode 100644
index 0000000..ee7c844
--- /dev/null
+++ b/arch/arm/cpu/armv8/imx8m/video_common.c
@@ -0,0 +1,736 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <i2c.h>
+#include <asm/arch/sys_proto.h>
+
+#include <video_fb.h>
+#include <asm/arch/video_common.h>
+#include <power-domain.h>
+#include <imx8_hdmi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* test congiurations */
+#undef IMXDCSS_LOAD_HDMI_FIRMWARE
+#undef IMXDCSS_SET_PIXEL_CLOCK
+
+static struct video_mode_settings gmode;
+static uint32_t gpixfmt;
+GraphicDevice panel;
+struct video_mode_settings *imx8m_get_gmode(void)
+{
+	return &gmode;
+}
+
+void imx8m_show_gmode(void)
+{
+	printf("gmode =\n"
+	       "pixelclock = %u\n"
+	       "xres       = %u\n"
+	       "yres       = %u\n"
+	       "hfp        = %u\n"
+	       "hbp        = %u\n"
+	       "vfp        = %u\n"
+	       "vbp        = %u\n"
+	       "hsync      = %u\n"
+	       "vsync      = %u\n"
+	       "hpol       = %u\n"
+	       "vpol       = %u\n",
+	       gmode.pixelclock,
+	       gmode.xres,
+	       gmode.yres,
+	       gmode.hfp,
+	       gmode.hbp,
+	       gmode.vfp,
+	       gmode.vbp, gmode.hsync, gmode.vsync, gmode.hpol, gmode.vpol);
+}
+
+GraphicDevice *imx8m_get_gd(void)
+{
+	return &panel;
+}
+
+#define REG_BASE_ADDR 0x32e00000UL
+
+/*#define DEBUGREG*/
+#ifdef DEBUGREG
+#define reg32_write(addr, val) \
+do { \
+	debug("%s():%d 0x%08x -> 0x%08x\n", __func__, __LINE__, \
+	(unsigned int)addr, (unsigned int)val); \
+	__raw_writel(val, addr); \
+} while (0)
+#else
+#define reg32_write(addr, val) __raw_writel(val, addr)
+#endif
+
+#define reg32_read(addr) __raw_readl(addr)
+
+#define reg32setbit(addr, bitpos) \
+	reg32_write((addr), (reg32_read((addr)) | (1<<(bitpos))))
+#define reg32clearbit(addr, bitpos) \
+	reg32_write((addr), (reg32_read((addr)) & ~(1<<(bitpos))))
+
+#define reg32_read_tst(addr, val, mask) \
+do { \
+	u32 temp = reg32_read((addr)); \
+	if ((temp & (mask)) == ((val) & (mask))) \
+		debug("%s():%d 0x%08x -> 0x%08x\n", \
+			__func__, __LINE__, addr, val); \
+	else  \
+		debug("%s():%d 0x%08x -> 0x%08x instead of 0x%08x\n", \
+			__func__, __LINE__, addr, temp, val); \
+} while (0)
+
+#define COLOR_LIST_SIZE 8
+static u32 color_list_argb32[COLOR_LIST_SIZE] = {
+	0xFFFFFFFF,		/* white */
+	0xFFFF0000,		/* red */
+	0xFF00FF00,		/* green */
+	0xFF0000FF,		/* blue */
+	0xFFFFFF00,		/* yellow */
+	0xFF00FFFF,		/* cyan */
+	0xFFFF00FF,		/* magenta */
+	0xFFC1C2C3,		/* silver */
+};				/*AARRGGBB */
+
+static unsigned int get_color_index(unsigned short px, unsigned short py,
+				    unsigned short width, unsigned short height,
+				    unsigned short bar_size)
+{
+	const int mw = 5;	/* margin width */
+	if ((py >= 0 && py < mw) || (py >= height - mw && py < height) ||
+	    (px >= 0 && px < mw) || (px >= width - mw && px < width)) {
+		return 1;
+	}
+
+	return py / bar_size;
+}
+
+void imx8m_create_color_bar(void *start_address,
+			   struct video_mode_settings *vms)
+{
+	/*struct video_mode_settings *vms = &vm_settings[g_vm]; */
+	uint32_t color_bar_size = vms->yres / COLOR_LIST_SIZE;
+	int i, j;
+	u32 *pointer;
+	int color_index = 0;
+	pointer = (u32 *)start_address;
+	uint32_t *color_map = &color_list_argb32[0];
+	debug("%s(), %d: start_address %p\n",
+	      __func__, __LINE__, start_address);
+	debug("%s(), %d: pointer %p\n", __func__, __LINE__, pointer);
+	debug("%s(), %d x %d\n", __func__, vms->xres, vms->yres);
+	for (i = 0; i < vms->yres; i++) {
+		for (j = 0; j < vms->xres; j++) {
+			color_index = get_color_index(j, i, vms->xres,
+						      vms->yres,
+						      color_bar_size);
+			*pointer = color_map[color_index];
+			pointer++;
+		}
+	}
+	invalidate_dcache_all();
+}
+
+static void imx8m_set_clocks(int apb_clk, int b_clk, int hdmi_core_clk,
+		      int p_clk, int rtr_clk)
+{
+	if (b_clk == 800) {
+		/* b_clk: bus_clk_root(4) sel 2nd input source and
+		   pre_div to 0; output should be 800M */
+		reg32_write(CCM_BUS_CLK_ROOT_GEN_TAGET_CLR(4),
+			    (0x7 << 24) | (0x7 << 16));
+		reg32_write(CCM_BUS_CLK_ROOT_GEN_TAGET_SET(4), (0x2 << 24));
+	} else {
+		printf("b_clk does not match a supported frequency");
+	}
+	if (rtr_clk == 400) {
+		/* rtr_clk: bus_clk_root(6) sel 1st input source
+		   and pre_div to 1; output should be 400M */
+		reg32_write(CCM_BUS_CLK_ROOT_GEN_TAGET_CLR(6),
+			    (0x7 << 24) | (0x7 << 16));
+		reg32_write(CCM_BUS_CLK_ROOT_GEN_TAGET_SET(6),
+			    (0x1 << 24) | (0x1 << 16));
+	} else {
+		debug("rtr_clk does not match a supported frequency");
+	}
+
+#ifdef IMXDCSS_LOAD_HDMI_FIRMWARE
+	/* If ROM is loading HDMI firmware then this clock should not be set */
+	if (hdmi_core_clk == 200) {
+		/* hdmi_core_clk: ip_clk_root(69) sel 1st input source and
+		   pre_div to 0 */
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(69),
+			    (0x7 << 24) | (0x7 << 16));
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(69), (0x1 << 24));
+		g_hdmi_core_clock = 200000000;
+	} else {
+		debug("hdmi_core_clk does not match a supported frequency");
+	}
+#endif
+
+#ifdef IMXDCSS_SET_PIXEL_CLOCK
+	/* This would be needed for MIPI-DSI DCSS display */
+	if (p_clk == 27) {
+		/* p_clk: ip_clk_root(9) sel 1st input source and
+		   pre_div to 1; post_div to 5, output 100M */
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9),
+			    (0x7 << 24) | (0x7 << 16));
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9),
+			    (0x1 << 24) | (29 << 16));
+	} else if (p_clk == 100) {
+		/* p_clk: ip_clk_root(9) sel 1st input source and
+		   pre_div to 1; post_div to 5, output 100M */
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9),
+			    (0x7 << 24) | (0x7 << 16));
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9),
+			    (0x1 << 24) | (0x5 << 16));
+	} else if (p_clk == 120) {
+		/* p_clk: ip_clk_root(9) sel 1st input source and
+		   pre_div to 1; post_div to 4, output 120M */
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9),
+			    (0x7 << 24) | (0x7 << 16));
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9),
+			    (0x1 << 24) | (0x4 << 16));
+	} else if (p_clk == 200) {
+		/* I added this to speed up the pixel clock and
+		   get frames out faster. may need to adjust this.
+		 */
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9),
+			    (0x7 << 24) | (0x7 << 16));
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9),
+			    (0x4 << 24) | (0x3 << 16)); /*for emu use 800 / 4 */
+	} else if (p_clk == 400) {
+		/* I added this to speed up the pixel clock and
+		   get frames out faster. may need to adjust this.
+		 */
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9),
+			    (0x7 << 24) | (0x7 << 16));
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9),
+			    (0x4 << 24) | (0x1 << 16)); /*for emu use 800 / 2 */
+	} else if (p_clk == 40) {	/* Do not reprogram, will get 40MHz */
+	} else {
+		debug("p_clk does not match a supported frequency");
+	}
+#endif
+}
+
+static int imx8m_power_init(uint32_t clock_control)
+{
+	u32 temp;
+	/*struct video_mode_settings *vms = &vm_settings[g_vm]; */
+
+	debug("\nenabling display clock...\n");
+	clock_enable(CCGR_DISPLAY, 1);
+
+	reg32_write(0x303A00EC, 0x0000ffff);	/*PGC_CPU_MAPPING */
+	reg32setbit(0x303A00F8, 10);	/*PU_PGC_SW_PUP_REQ : disp was 10 */
+#ifdef LOAD_HDMI_FIRMWARE
+	reg32setbit(0x303A00F8, 9);	/*PU_PGC_SW_PUP_REQ : hdmi was 9 */
+#endif
+	imx8m_set_clocks(133, 800, 200, 27, 400);
+
+	/* DCSS reset */
+	reg32_write(0x32e2f000, 0xffffffff);
+
+	/* DCSS clock selection */
+	reg32_write(0x32e2f010, clock_control);
+	temp = reg32_read(0x32e2f010);
+	debug("%s(): DCSS clock control 0x%08x\n", __func__, temp);
+
+	/* take DCSS out of reset - not needed OFB */
+	/*__raw_writel(0xffffffff, 0x32e2f004); */
+
+	return 0;
+}
+
+static void imx8m_display_init(u64 buffer, int encoding,
+			       struct video_mode_settings *vms)
+{
+	/*struct video_mode_settings *vms = &vm_settings[g_vm]; */
+
+	debug("entering %s() ...\n", __func__);
+	debug("%s() buffer ...\n", __func__);
+
+	/* DTRC-CHAN2/3 */
+	reg32_write(REG_BASE_ADDR + 0x160c8, 0x00000002);
+	reg32_write(REG_BASE_ADDR + 0x170c8, 0x00000002);
+
+	/* CHAN1_DPR */
+	reg32_write(REG_BASE_ADDR + 0x180c0, (unsigned int)buffer);
+	reg32_write(REG_BASE_ADDR + 0x18090, 0x00000002);
+	reg32_write(REG_BASE_ADDR + 0x180a0, vms->xres);
+	reg32_write(REG_BASE_ADDR + 0x180b0, vms->yres);
+	reg32_write(REG_BASE_ADDR + 0x18110,
+		    (unsigned int)buffer + vms->xres * vms->yres);
+	reg32_write(REG_BASE_ADDR + 0x180f0, 0x00000280);
+	reg32_write(REG_BASE_ADDR + 0x18100, 0x000000f0);
+	reg32_write(REG_BASE_ADDR + 0x18070, ((vms->xres * 4) << 16));
+	reg32_write(REG_BASE_ADDR + 0x18050, 0x000e4203);
+	reg32_write(REG_BASE_ADDR + 0x18050, 0x000e4203);
+	reg32_write(REG_BASE_ADDR + 0x18200, 0x00000038);
+	reg32_write(REG_BASE_ADDR + 0x18000, 0x00000004);
+	reg32_write(REG_BASE_ADDR + 0x18000, 0x00000005);
+
+	/* SCALER */
+	reg32_write(REG_BASE_ADDR + 0x1c008, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c00c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c010, 0x00000002);
+	reg32_write(REG_BASE_ADDR + 0x1c014, 0x00000002);
+	reg32_write(REG_BASE_ADDR + 0x1c018,
+		    ((vms->yres - 1) << 16 | (vms->xres - 1)));
+	reg32_write(REG_BASE_ADDR + 0x1c01c,
+		    ((vms->yres - 1) << 16 | (vms->xres - 1)));
+	reg32_write(REG_BASE_ADDR + 0x1c020,
+		    ((vms->yres - 1) << 16 | (vms->xres - 1)));
+	reg32_write(REG_BASE_ADDR + 0x1c024,
+		    ((vms->yres - 1) << 16 | (vms->xres - 1)));
+	reg32_write(REG_BASE_ADDR + 0x1c028, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c02c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c030, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c034, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c038, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c03c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c040, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c044, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c048, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c04c, 0x00002000);
+	reg32_write(REG_BASE_ADDR + 0x1c050, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c054, 0x00002000);
+	reg32_write(REG_BASE_ADDR + 0x1c058, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c05c, 0x00002000);
+	reg32_write(REG_BASE_ADDR + 0x1c060, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c064, 0x00002000);
+	reg32_write(REG_BASE_ADDR + 0x1c080, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0c0, 0x00040000);
+	reg32_write(REG_BASE_ADDR + 0x1c100, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c084, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0c4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c104, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c088, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0c8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c108, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c08c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0cc, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c10c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c090, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0d0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c110, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c094, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0d4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c114, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c098, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0d8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c118, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c09c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0dc, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c11c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0a0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0e0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c120, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0a4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0e4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c124, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0a8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0e8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c128, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0ac, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0ec, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c12c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0b0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0f0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c130, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0b4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0f4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c134, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0b8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0f8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c138, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0bc, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c0fc, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c13c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c140, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c180, 0x00040000);
+	reg32_write(REG_BASE_ADDR + 0x1c1c0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c144, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c184, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1c4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c148, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c188, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1c8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c14c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c18c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1cc, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c150, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c190, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1d0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c154, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c194, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1d4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c158, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c198, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1d8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c15c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c19c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1dc, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c160, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1a0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1e0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c164, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1a4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1e4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c168, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1a8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1e8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c16c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1ac, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1ec, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c170, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1b0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1f0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c174, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1b4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1f4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c178, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1b8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1f8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c17c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1bc, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c1fc, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c300, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c340, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c380, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c304, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c344, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c384, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c308, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c348, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c388, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c30c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c34c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c38c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c310, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c350, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c390, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c314, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c354, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c394, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c318, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c358, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c398, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c31c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c35c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c39c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c320, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c360, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c3a0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c324, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c364, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c3a4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c328, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c368, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c3a8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c32c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c36c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c3ac, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c330, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c370, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c3b0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c334, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c374, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c3b4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c338, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c378, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c3b8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c33c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c37c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c3bc, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c200, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c240, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c280, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c204, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c244, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c284, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c208, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c248, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c288, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c20c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c24c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c28c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c210, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c250, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c290, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c214, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c254, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c294, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c218, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c258, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c298, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c21c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c25c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c29c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c220, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c260, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c2a0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c224, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c264, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c2a4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c228, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c268, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c2a8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c22c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c26c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c2ac, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c230, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c270, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c2b0, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c234, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c274, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c2b4, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c238, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c278, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c2b8, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c23c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c27c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c2bc, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c2bc, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x1c000, 0x00000011);
+
+	/* SUBSAM */
+	reg32_write(REG_BASE_ADDR + 0x1b070, 0x21612161);
+	reg32_write(REG_BASE_ADDR + 0x1b080, 0x03ff0000);
+	reg32_write(REG_BASE_ADDR + 0x1b090, 0x03ff0000);
+
+	reg32_write(REG_BASE_ADDR + 0x1b010,
+		    (((vms->vfp + vms->vbp + vms->vsync + vms->yres -
+		       1) << 16) | (vms->hfp + vms->hbp + vms->hsync +
+				    vms->xres - 1)));
+	reg32_write(REG_BASE_ADDR + 0x1b020,
+		    (((vms->hsync - 1) << 16) | vms->hpol << 31 | (vms->hfp +
+								   vms->hbp +
+								   vms->hsync +
+								   vms->xres -
+								   1)));
+	reg32_write(REG_BASE_ADDR + 0x1b030,
+		    (((vms->vfp + vms->vsync -
+		       1) << 16) | vms->vpol << 31 | (vms->vfp - 1)));
+
+	reg32_write(REG_BASE_ADDR + 0x1b040,
+		    ((1 << 31) | ((vms->vsync + vms->vfp + vms->vbp) << 16) |
+		     (vms->hsync + vms->hbp - 1)));
+	reg32_write(REG_BASE_ADDR + 0x1b050,
+		    (((vms->vsync + vms->vfp + vms->vbp + vms->yres -
+		       1) << 16) | (vms->hsync + vms->hbp + vms->xres - 1)));
+
+	/* subsample mode 0 none, 1 422, 2 420 */
+	switch (encoding) {
+	case 4:
+		reg32_write(REG_BASE_ADDR + 0x1b060, 0x00000001);
+		break;
+
+	case 8:
+		reg32_write(REG_BASE_ADDR + 0x1b060, 0x00000002);
+		break;
+
+	case 2:
+	case 1:
+	default:
+		reg32_write(REG_BASE_ADDR + 0x1b060, 0x0000000);
+	}
+
+	reg32_write(REG_BASE_ADDR + 0x1b000, 0x00000001);
+#if 0
+	/* not needed for splash setup */
+	/* HDR10 Chan3 LUT */
+	reg32_write(REG_BASE_ADDR + 0x03874, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x03080, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x03000, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x03800, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x07874, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x07080, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x07000, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x07800, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0b874, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0b080, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0b000, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0b800, 0x00000000);
+
+	/* HDR10 Tables and Registers */
+	/*reg32_write(REG_BASE_ADDR+0x0f074, 0x00000003); */
+	/*reg32_write(REG_BASE_ADDR+0x0f000, 0x00000004); */
+
+	reg32_write(REG_BASE_ADDR + 0x0f004, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f008, 0x00000001);
+	reg32_write(REG_BASE_ADDR + 0x0f00c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f010, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f014, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f018, 0x00000001);
+	reg32_write(REG_BASE_ADDR + 0x0f01c, 0x00000001);
+	reg32_write(REG_BASE_ADDR + 0x0f020, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f024, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f028, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f02c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f030, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f034, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f038, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f03c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f040, 0xffffffff);
+	reg32_write(REG_BASE_ADDR + 0x0f044, 0xffffffff);
+	reg32_write(REG_BASE_ADDR + 0x0f048, 0xffffffff);
+	reg32_write(REG_BASE_ADDR + 0x0f04c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f050, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f054, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f058, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f05c, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f060, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f064, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f068, 0xffffffff);
+	reg32_write(REG_BASE_ADDR + 0x0f06c, 0xffffffff);
+	reg32_write(REG_BASE_ADDR + 0x0f070, 0xffffffff);
+	reg32_write(REG_BASE_ADDR + 0x0f074, 0x00000000);
+	reg32_write(REG_BASE_ADDR + 0x0f000, 0x00000003);
+#endif
+	/* DTG */
+	/*reg32_write(REG_BASE_ADDR + 0x20000, 0xff000484); */
+	/* disable local alpha */
+	reg32_write(REG_BASE_ADDR + 0x20000, 0xff005084);
+	reg32_write(REG_BASE_ADDR + 0x20004,
+		    (((vms->vfp + vms->vbp + vms->vsync + vms->yres -
+		       1) << 16) | (vms->hfp + vms->hbp + vms->hsync +
+				    vms->xres - 1)));
+	reg32_write(REG_BASE_ADDR + 0x20008,
+		    (((vms->vsync + vms->vfp + vms->vbp -
+		       1) << 16) | (vms->hsync + vms->hbp - 1)));
+	reg32_write(REG_BASE_ADDR + 0x2000c,
+		    (((vms->vsync + vms->vfp + vms->vbp + vms->yres -
+		       1) << 16) | (vms->hsync + vms->hbp + vms->xres - 1)));
+	reg32_write(REG_BASE_ADDR + 0x20010,
+		    (((vms->vsync + vms->vfp + vms->vbp -
+		       1) << 16) | (vms->hsync + vms->hbp - 1)));
+	reg32_write(REG_BASE_ADDR + 0x20014,
+		    (((vms->vsync + vms->vfp + vms->vbp + vms->yres -
+		       1) << 16) | (vms->hsync + vms->hbp + vms->xres - 1)));
+	reg32_write(REG_BASE_ADDR + 0x20028, 0x000b000a);
+
+	/* disable local alpha */
+	reg32_write(REG_BASE_ADDR + 0x20000, 0xff005184);
+
+	debug("leaving %s() ...\n", __func__);
+}
+
+void imx8m_display_shutdown(void)
+{
+	/* stop the DCSS modules in use */
+	/* dtg */
+	reg32_write(REG_BASE_ADDR + 0x20000, 0);
+	/* scaler */
+	reg32_write(REG_BASE_ADDR + 0x1c000, 0);
+	reg32_write(REG_BASE_ADDR + 0x1c400, 0);
+	reg32_write(REG_BASE_ADDR + 0x1c800, 0);
+	/* dpr */
+	reg32_write(REG_BASE_ADDR + 0x18000, 0);
+	reg32_write(REG_BASE_ADDR + 0x19000, 0);
+	reg32_write(REG_BASE_ADDR + 0x1a000, 0);
+	/* sub-sampler*/
+	reg32_write(REG_BASE_ADDR + 0x1b000, 0);
+#if 0
+	/* reset the DCSS */
+	reg32_write(0x32e2f000, 0xffffe8);
+	udelay(100);
+	reg32_write(0x32e2f000, 0xffffff);
+#endif
+
+}
+void *video_hw_init(void)
+{
+	void *fb;
+	int encoding = 1;
+
+	debug("%s()\n", __func__);
+
+	imx8m_power_init(0x1);
+
+	panel.winSizeX = gmode.xres;
+	panel.winSizeY = gmode.yres;
+	panel.plnSizeX = gmode.xres;
+	panel.plnSizeY = gmode.yres;
+	panel.gdfBytesPP = 4;
+	panel.gdfIndex = GDF_32BIT_X888RGB;
+	panel.memSize = gmode.xres * gmode.yres * panel.gdfBytesPP;
+
+	/* Allocate framebuffer */
+	fb = memalign(0x1000, roundup(panel.memSize, 0x1000));
+	debug("%s(): fb %p\n", __func__, fb);
+	if (!fb) {
+		printf("%s, %s(): Error allocating framebuffer!\n",
+		       __FILE__, __func__);
+		return NULL;
+	}
+
+	imx8m_create_color_bar((void *)((uint64_t) fb), &gmode);
+
+	imx8_hdmi_enable(encoding, &gmode); /* may change gmode */
+
+	/* start dccs */
+	imx8m_display_init((uint64_t) fb, encoding, &gmode);
+
+	panel.frameAdrs = (ulong) fb;
+	debug("IMXDCSS display started ...\n");
+
+	return &panel;
+}
+
+void imx8m_fb_disable(void)
+{
+	debug("%s()\n", __func__);
+	if (panel.frameAdrs) {
+#ifdef CONFIG_VIDEO_IMX8_HDMI
+		imx8_hdmi_disable();
+#endif
+		imx8m_display_shutdown();
+	}
+
+}
+
+int imx8m_fb_init(struct fb_videomode const *mode,
+		    uint8_t disp, uint32_t pixfmt)
+{
+	debug("entering %s()\n", __func__);
+
+	if (disp > 1) {
+		debug("Invalid disp parameter %d for imxdcss_fb_init()\n",
+		      disp);
+		return -EINVAL;
+	}
+
+	memset(&gmode, 0, sizeof(struct video_mode_settings));
+	gmode.pixelclock = PS2KHZ(mode->pixclock) * 1000;
+	gmode.xres = mode->xres;
+	gmode.hbp = mode->left_margin;
+	gmode.hfp = mode->right_margin;
+
+	gmode.yres = mode->yres;
+	gmode.vbp = mode->upper_margin;
+	gmode.vfp = mode->lower_margin;
+
+	gmode.hsync = mode->hsync_len;
+	gmode.vsync = mode->vsync_len;
+	gmode.hpol = (mode->flag & FB_SYNC_HOR_HIGH_ACT) ? 1 : 0;
+	gmode.vpol = (mode->flag & FB_SYNC_VERT_HIGH_ACT) ? 1 : 0;
+	gpixfmt = pixfmt;
+
+	debug("leaving %s()\n", __func__);
+
+	return 0;
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index afd1a5b..3b5d5d2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -388,6 +388,7 @@
 
 dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
 		fsl-imx8mq-ddr3l-arm2.dtb \
+		fsl-imx8mq-phanbell.dtb \
 		fsl-imx8mq-ddr4-arm2.dtb
 
 dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qm-lpddr4-arm2.dtb \
diff --git a/arch/arm/dts/fsl-imx8mq-phanbell.dts b/arch/arm/dts/fsl-imx8mq-phanbell.dts
new file mode 100644
index 0000000..c40931f
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mq-phanbell.dts
@@ -0,0 +1,746 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x40000000 0x00020000;
+
+#include "fsl-imx8mq.dtsi"
+
+/ {
+	model = "Freescale i.MX8MQ Phanbell";
+	compatible = "fsl,imx8mq-phanbell", "fsl,imx8mq";
+
+	bcmdhd_wlan_0: bcmdhd_wlan@0 {
+		compatible = "android,bcmdhd_wlan";
+		bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin";
+		bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal";
+	};
+
+	chosen {
+		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
+		stdout-path = &uart1;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VSD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+
+	modem_reset: modem-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <2000>;
+		reset-post-delay-ms = <40>;
+		#reset-cells = <0>;
+	};
+
+	wm8524: wm8524 {
+		compatible = "wlf,wm8524";
+		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
+		clock-names = "mclk";
+		wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+	};
+
+	sound-wm8524 {
+		compatible = "fsl,imx-audio-wm8524";
+		model = "wm8524-audio";
+		audio-cpu = <&sai2>;
+		audio-codec = <&wm8524>;
+		audio-routing =
+			"Line Out Jack", "LINEVOUTL",
+			"Line Out Jack", "LINEVOUTR";
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		ledpwm2 {
+			label = "PWM2";
+			pwms = <&pwm2 0 50000>;
+			max-brightness = <255>;
+		};
+	};
+	regulator-virtuals {
+		compatible = "simple-bus";
+
+		virt-buck1 {
+			compatible = "regulator-virtual";
+			virtual-supply = "buck1";
+		};
+		virt-buck2 {
+			compatible = "regulator-virtual";
+			virtual-supply = "buck2";
+		};
+		virt-buck3 {
+			compatible = "regulator-virtual";
+			virtual-supply = "buck3";
+		};
+		virt-buck4 {
+			compatible = "regulator-virtual";
+			virtual-supply = "buck4";
+		};
+		virt-buck5 {
+			compatible = "regulator-virtual";
+			virtual-supply = "buck5";
+		};
+		virt-buck6 {
+			compatible = "regulator-virtual";
+			virtual-supply = "buck6";
+		};
+		virt-buck7 {
+			compatible = "regulator-virtual";
+			virtual-supply = "buck7";
+		};
+		virt-buck8 {
+			compatible = "regulator-virtual";
+			virtual-supply = "buck8";
+		};
+		virt-ldo1 {
+			compatible = "regulator-virtual";
+			virtual-supply = "ldo1";
+		};
+		virt-ldo2 {
+			compatible = "regulator-virtual";
+			virtual-supply = "ldo2";
+		};
+		virt-ldo3 {
+			compatible = "regulator-virtual";
+			virtual-supply = "ldo3";
+		};
+		virt-ldo4 {
+			compatible = "regulator-virtual";
+			virtual-supply = "ldo4";
+		};
+		virt-ldo5 {
+			compatible = "regulator-virtual";
+			virtual-supply = "ldo5";
+		};
+		virt-ldo6 {
+			compatible = "regulator-virtual";
+			virtual-supply = "ldo6";
+		};
+		virt-ldo7 {
+			compatible = "regulator-virtual";
+			virtual-supply = "ldo7";
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	imx8mq-evk {
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+				MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
+				MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
+				MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
+				MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
+				MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
+				MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
+				MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
+				MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
+				MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
+				MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
+				MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
+				MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+				MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+				MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
+				MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
+				MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
+			>;
+		};
+
+
+		pinctrl_pcie0: pcie0grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20	0x16
+				MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29	0x16
+				MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28	0x16
+			>;
+		};
+
+		pinctrl_pcie1: pcie1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21	0x16
+				MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10	0x16
+				MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12	0x16
+			>;
+		};
+
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT	0x16
+			>;
+		};
+
+		pinctrl_qspi: qspigrp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
+				MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
+				MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
+				MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
+				MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
+				MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
+
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x79
+				MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x79
+			>;
+		};
+
+		pinctrl_uart3: uart3grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x79
+				MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x79
+				MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x79
+				MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x79
+				MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x19
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x83
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x85
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x87
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
+				MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+			>;
+		};
+
+		pinctrl_sai2: sai2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
+				MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
+				MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
+				MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
+				MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0xd6
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+			>;
+		};
+
+		pinctrl_pmic: pmicirq {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41 /*0x17059*/
+			>;
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,led-act-blind-workaround;
+			at803x,eee-disabled;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic: bd71837@4b {
+		reg = <0x4b>;
+		compatible = "rohm,bd71837";
+		/* PMIC BD71837 PMIC_nINT GPIO1_IO12 */
+		pinctrl-0 = <&pinctrl_pmic>;
+		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
+
+		bd71837,pmic-buck1-uses-i2c-dvs;
+		bd71837,pmic-buck1-dvs-voltage = <900000>, <850000>, <800000>; /* VDD_SOC: Run-Idle-Suspend */
+		bd71837,pmic-buck2-uses-i2c-dvs;
+		bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
+		bd71837,pmic-buck3-uses-i2c-dvs;
+		bd71837,pmic-buck3-dvs-voltage = <1000000>, <0>, <0>; /* VDD_GPU: Run */
+		bd71837,pmic-buck4-uses-i2c-dvs;
+		bd71837,pmic-buck4-dvs-voltage = <1000000>, <0>, <0>; /* VDD_VPU: Run */
+		
+		gpo {
+			rohm,drv = <0x0C>;	/* 0b0000_1100 all gpos with cmos output mode */
+		};
+
+		regulators {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			buck1_reg: regulator@0 {
+				reg = <0>;
+				regulator-compatible = "buck1";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+			};
+
+			buck2_reg: regulator@1 {
+				reg = <1>;
+				regulator-compatible = "buck2";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+			};
+
+			buck3_reg: regulator@2 {
+				reg = <2>;
+				regulator-compatible = "buck3";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck4_reg: regulator@3 {
+				reg = <3>;
+				regulator-compatible = "buck4";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5_reg: regulator@4 {
+				reg = <4>;
+				regulator-compatible = "buck5";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: regulator@5 {
+				reg = <5>;
+				regulator-compatible = "buck6";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			
+			buck7_reg: regulator@6 {
+				reg = <6>;
+				regulator-compatible = "buck7";
+				regulator-min-microvolt = <1605000>;
+				regulator-max-microvolt = <1995000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			
+			buck8_reg: regulator@7 {
+				reg = <7>;
+				regulator-compatible = "buck8";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			
+
+			ldo1_reg: regulator@8 {
+				reg = <8>;
+				regulator-compatible = "ldo1";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: regulator@9 {
+				reg = <9>;
+				regulator-compatible = "ldo2";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: regulator@10 {
+				reg = <10>;
+				regulator-compatible = "ldo3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: regulator@11 {
+				reg = <11>;
+				regulator-compatible = "ldo4";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5_reg: regulator@12 {
+				reg = <12>;
+				regulator-compatible = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo6_reg: regulator@13 {
+				reg = <13>;
+				regulator-compatible = "ldo6";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo7_reg: regulator@14 {
+				reg = <14>;
+				regulator-compatible = "ldo7";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+
+	adv7535: adv7535@3d {
+		compatible = "adi,adv7535";
+		reg = <0x3d>;		/* PD pin is low */
+		/* TODO: pin config & irq */
+		video-mode = <34>;	/* 1920x1080@30HZ */
+		dsi-traffic-mode = <0>;
+		bpp = <24>;
+		status = "okay";
+		port {
+			dsi_to_hdmi: endpoint {
+				remote-endpoint = <&mipi_dsi_ep>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "disabled";
+};
+
+&pcie0{
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>;
+	disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>;
+	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie1{
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie1>;
+	clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
+	disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>;
+	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "okay";
+};
+
+&uart1 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
+	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+	status = "okay";
+};
+
+&lcdif {
+	status = "okay";
+	disp-dev = "mipi_dsi_northwest";
+	display = <&display0>;
+
+	display0: display@0 {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+			clock-frequency = <9200000>;
+			hactive = <480>;
+			vactive = <272>;
+			hfront-porch = <8>;
+			hback-porch = <4>;
+			hsync-len = <41>;
+			vback-porch = <2>;
+			vfront-porch = <4>;
+			vsync-len = <10>;
+
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay";
+
+	flash0: n25q256a@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+	};
+};
+
+&mipi_dsi {
+	reset = <&src>;
+	mux-sel = <&gpr>;	/* lcdif or dcss */
+	status = "okay";
+	port {
+		mipi_dsi_ep: endpoint {
+			remote-endpoint = <&dsi_to_hdmi>;
+		};
+	};
+};
+
+&uart3 { /* BT */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
+	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+	fsl,uart-has-rtscts;
+	resets = <&modem_reset>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	status = "okay";
+	dr_mode = "peripheral";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2>;
+	assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>,
+			<&clk IMX8MQ_AUDIO_PLL1>,
+			<&clk IMX8MQ_CLK_SAI2_PRE_DIV>,
+			<&clk IMX8MQ_CLK_SAI2_DIV>;
+	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>;
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&vpu {
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts
index aed7fc1..6ad4050 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek.dts
+++ b/arch/arm/dts/fsl-imx8qxp-mek.dts
@@ -331,6 +331,7 @@
 	pca9646_switch: mux@71 {
 		compatible = "nxp,pca9544";
 		reg = <0x71>;
+		u-boot,i2c-offset-len = <0>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index ac5537d..6a1639d 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -14,6 +14,7 @@
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 obj-$(CONFIG_SECURE_BOOT) += hab.o
+obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 obj-y += cpu.o
 endif
 
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 1ef0c4c..e798ee6 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -18,6 +18,9 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#if defined(CONFIG_VIDEO_IMXDCSS)
+#include <asm/arch/video_common.h>
+#endif
 #include <imx_thermal.h>
 #include <ipu_pixfmt.h>
 #include <thermal.h>
@@ -325,6 +328,9 @@
 #if defined(CONFIG_VIDEO_MXS)
 	lcdif_power_down();
 #endif
+#if defined(CONFIG_VIDEO_IMXDCSS)
+	imx8m_fb_disable();
+#endif
 }
 
 #ifndef CONFIG_IMX8M
diff --git a/arch/arm/imx-common/video.c b/arch/arm/imx-common/video.c
index 7eed32c..a582487 100644
--- a/arch/arm/imx-common/video.c
+++ b/arch/arm/imx-common/video.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -42,6 +43,9 @@
 #elif defined(CONFIG_VIDEO_IMXDPUV1)
 		ret = imxdpuv1_fb_init(&displays[i].mode, displays[i].bus,
 					displays[i].pixfmt);
+#elif defined(CONFIG_VIDEO_IMXDCSS)
+		ret = imx8m_fb_init(&displays[i].mode, displays[i].bus,
+					displays[i].pixfmt);
 #elif defined(CONFIG_VIDEO_MXS)
 		ret = mxs_lcd_panel_setup(displays[i].mode,
 					displays[i].pixfmt,
diff --git a/arch/arm/include/asm/arch-imx8m/video_common.h b/arch/arm/include/asm/arch-imx8m/video_common.h
new file mode 100644
index 0000000..cdeec69
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/video_common.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_VIDEO_COMMON_H__
+#define __ASM_ARCH_VIDEO_COMMON_H__
+#include <linux/fb.h>
+#include <video_fb.h>
+
+struct video_mode_settings {
+	uint32_t pixelclock;	/* horizontal resolution	*/
+	uint16_t xres;		/* horizontal resolution	*/
+	uint16_t yres;		/* vertical resolution		*/
+	uint16_t hfp;		/* horizontal front porch	*/
+	uint16_t hbp;		/* horizontal back porch	*/
+	uint16_t vfp;		/* vertical front porch		*/
+	uint16_t vbp;		/* vertical back porch		*/
+	uint16_t hsync;		/* horizontal sync pulse width	*/
+	uint16_t vsync;		/* vertical sync pulse width	*/
+	bool hpol;		/* horizontal pulse polarity	*/
+	bool vpol;		/* vertical pulse polarity	*/
+};
+
+#define	PS2KHZ(ps)	(1000000000UL / (ps))
+struct video_mode_settings *imx8m_get_gmode(void);
+GraphicDevice *imx8m_get_gd(void);
+void imx8m_show_gmode(void);
+void imx8m_create_color_bar(
+	void *start_address,
+	struct video_mode_settings *vms);
+int imx8m_fb_init(
+	struct fb_videomode const *mode,
+	uint8_t disp,
+	uint32_t pixfmt);
+void imx8m_fb_disable(void);
+
+#endif /* __ASM_ARCH_VIDEO_COMMON_H__ */
diff --git a/arch/arm/include/asm/imx-common/sci/types.h b/arch/arm/include/asm/imx-common/sci/types.h
index 928023b..6e0520e 100644
--- a/arch/arm/include/asm/imx-common/sci/types.h
+++ b/arch/arm/include/asm/imx-common/sci/types.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
@@ -751,6 +751,8 @@
     SC_C_OFS_AUDIO          = 40,
     SC_C_OFS_PERIPH         = 41,
     SC_C_OFS_IRQ            = 42,
+    SC_C_RST0               = 43,
+    SC_C_RST1               = 44,
     SC_C_LAST
 } sc_ctrl_t;
 
diff --git a/arch/arm/include/asm/imx-common/video.h b/arch/arm/include/asm/imx-common/video.h
index 36147fe..ca626ce 100644
--- a/arch/arm/include/asm/imx-common/video.h
+++ b/arch/arm/include/asm/imx-common/video.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -15,6 +16,8 @@
 #include <asm/arch/video_common.h>
 #elif defined(CONFIG_VIDEO_MXS)
 #include <mxsfb.h>
+#elif defined(CONFIG_VIDEO_IMXDCSS)
+#include <asm/arch/video_common.h>
 #endif
 
 struct display_info_t {
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig
index f5190ac..49795d3 100644
--- a/board/freescale/common/Kconfig
+++ b/board/freescale/common/Kconfig
@@ -1,5 +1,15 @@
+if !ARCH_IMX8M && !ARCH_IMX8
+
 config CHAIN_OF_TRUST
 	depends on !FIT_SIGNATURE && SECURE_BOOT
 	select FSL_CAAM
 	bool
 	default y
+
+endif
+
+config USB_TCPC
+	bool "USB Typec port controller simple driver"
+	default n
+	help
+	  Enable USB type-c port controller (TCPC) driver
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index e391718..d54df99 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -85,5 +85,7 @@
 endif
 obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
 
-obj-$(CONFIG_USB_XHCI_IMX8) += tcpc.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_USB_TCPC) += tcpc.o
+endif
 endif
diff --git a/board/freescale/common/tcpc.c b/board/freescale/common/tcpc.c
index 5931cb1..a674717 100644
--- a/board/freescale/common/tcpc.c
+++ b/board/freescale/common/tcpc.c
@@ -8,30 +8,57 @@
 #include <time.h>
 #include "tcpc.h"
 
-int tcpc_set_cc_to_source(struct udevice *i2c_dev)
+#ifdef DEBUG
+#define tcpc_debug_log(port, fmt, args...) tcpc_log(port, fmt, ##args)
+#else
+#define tcpc_debug_log(port, fmt, args...)
+#endif
+
+static int tcpc_log(struct tcpc_port *port, const char *fmt, ...)
+{
+	va_list args;
+	int i;
+
+	va_start(args, fmt);
+	i = vscnprintf(port->log_p, port->log_size, fmt, args);
+	va_end(args);
+
+	port->log_size -= i;
+	port->log_p += i;
+
+	return i;
+}
+
+int tcpc_set_cc_to_source(struct tcpc_port *port)
 {
 	uint8_t valb;
 	int err;
 
+	if (port == NULL)
+		return -EINVAL;
+
 	valb = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
 			(TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) |
 			(TCPC_ROLE_CTRL_RP_VAL_DEF <<
 			 TCPC_ROLE_CTRL_RP_VAL_SHIFT);
 
-	err = dm_i2c_write(i2c_dev, TCPC_ROLE_CTRL, &valb, 1);
+	err = dm_i2c_write(port->i2c_dev, TCPC_ROLE_CTRL, &valb, 1);
 	if (err)
-		printf("%s dm_i2c_write failed, err %d\n", __func__, err);
+		tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err);
 	return err;
 }
 
-int tcpc_set_plug_orientation(struct udevice *i2c_dev, enum typec_cc_polarity polarity)
+int tcpc_set_plug_orientation(struct tcpc_port *port, enum typec_cc_polarity polarity)
 {
 	uint8_t valb;
 	int err;
 
-	err = dm_i2c_read(i2c_dev, TCPC_TCPC_CTRL, &valb, 1);
+	if (port == NULL)
+		return -EINVAL;
+
+	err = dm_i2c_read(port->i2c_dev, TCPC_TCPC_CTRL, &valb, 1);
 	if (err) {
-		printf("%s dm_i2c_read failed, err %d\n", __func__, err);
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
 		return -EIO;
 	}
 
@@ -40,74 +67,179 @@
 	else
 		valb &= ~TCPC_TCPC_CTRL_ORIENTATION;
 
-	err = dm_i2c_write(i2c_dev, TCPC_TCPC_CTRL, &valb, 1);
+	err = dm_i2c_write(port->i2c_dev, TCPC_TCPC_CTRL, &valb, 1);
 	if (err) {
-		printf("%s dm_i2c_write failed, err %d\n", __func__, err);
+		tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err);
 		return -EIO;
 	}
 
 	return 0;
 }
 
-int tcpc_get_cc_polarity(struct udevice *i2c_dev, enum typec_cc_polarity *polarity)
+int tcpc_get_cc_status(struct tcpc_port *port, enum typec_cc_polarity *polarity, enum typec_cc_state *state)
 {
 
-	uint8_t valb;
+	uint8_t valb_cc, cc2, cc1;
 	int err;
 
-	err = dm_i2c_read(i2c_dev, TCPC_CC_STATUS, &valb, 1);
+	if (port == NULL || polarity == NULL || state == NULL)
+		return -EINVAL;
+
+	err = dm_i2c_read(port->i2c_dev, TCPC_CC_STATUS, (uint8_t *)&valb_cc, 1);
 	if (err) {
-		printf("%s dm_i2c_read failed, err %d\n", __func__, err);
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
 		return -EIO;
 	}
 
-	debug("cc status 0x%x\n", valb);
+	tcpc_debug_log(port, "cc status 0x%x\n", valb_cc);
 
-	/* Set to Rp at default */
-	if (valb & TCPC_CC_STATUS_TERM)
-		return -EPERM;
+	cc2 = (valb_cc >> TCPC_CC_STATUS_CC2_SHIFT) & TCPC_CC_STATUS_CC2_MASK;
+	cc1 = (valb_cc >> TCPC_CC_STATUS_CC1_SHIFT) & TCPC_CC_STATUS_CC1_MASK;
 
-	if (((valb >> TCPC_CC_STATUS_CC1_SHIFT) & TCPC_CC_STATUS_CC1_MASK) == 0x2)
-		*polarity = TYPEC_POLARITY_CC1;
-	else if (((valb >> TCPC_CC_STATUS_CC2_SHIFT) & TCPC_CC_STATUS_CC2_MASK) == 0x2)
-		*polarity = TYPEC_POLARITY_CC2;
-	else
+	if (valb_cc & TCPC_CC_STATUS_LOOK4CONN)
 		return -EFAULT;
+
+	*state = TYPEC_STATE_OPEN;
+
+	if (valb_cc & TCPC_CC_STATUS_TERM) {
+		if (cc2) {
+			*polarity = TYPEC_POLARITY_CC2;
+
+			switch (cc2) {
+			case 0x1:
+				*state = TYPEC_STATE_SNK_DEFAULT;
+				tcpc_log(port, "SNK.Default on CC2\n");
+				break;
+			case 0x2:
+				*state = TYPEC_STATE_SNK_POWER15;
+				tcpc_log(port, "SNK.Power1.5 on CC2\n");
+				break;
+			case 0x3:
+				*state = TYPEC_STATE_SNK_POWER30;
+				tcpc_log(port, "SNK.Power3.0 on CC2\n");
+				break;
+			}
+		} else if (cc1) {
+			*polarity = TYPEC_POLARITY_CC1;
+
+			switch (cc1) {
+			case 0x1:
+				*state = TYPEC_STATE_SNK_DEFAULT;
+				tcpc_log(port, "SNK.Default on CC1\n");
+				break;
+			case 0x2:
+				*state = TYPEC_STATE_SNK_POWER15;
+				tcpc_log(port, "SNK.Power1.5 on CC1\n");
+				break;
+			case 0x3:
+				*state = TYPEC_STATE_SNK_POWER30;
+				tcpc_log(port, "SNK.Power3.0 on CC1\n");
+				break;
+			}
+		} else {
+			*state = TYPEC_STATE_OPEN;
+			return -EPERM;
+		}
+
+	} else {
+		if (cc2) {
+			*polarity = TYPEC_POLARITY_CC2;
+
+			switch (cc2) {
+			case 0x1:
+				if (cc1 == 0x1) {
+					*state = TYPEC_STATE_SRC_BOTH_RA;
+					tcpc_log(port, "SRC.Ra on both CC1 and CC2\n");
+				} else if (cc1 == 0x2) {
+					*state = TYPEC_STATE_SRC_RD_RA;
+					tcpc_log(port, "SRC.Ra on CC2, SRC.Rd on CC1\n");
+				} else if (cc1 == 0x0) {
+					tcpc_log(port, "SRC.Ra only on CC2\n");
+					return -EFAULT;
+				} else
+					return -EFAULT;
+				break;
+			case 0x2:
+				if (cc1 == 0x1) {
+					*state = TYPEC_STATE_SRC_RD_RA;
+					tcpc_log(port, "SRC.Ra on CC1, SRC.Rd on CC2\n");
+				} else if (cc1 == 0x0) {
+					*state = TYPEC_STATE_SRC_RD;
+					tcpc_log(port, "SRC.Rd on CC2\n");
+				} else
+					return -EFAULT;
+				break;
+			case 0x3:
+				*state = TYPEC_STATE_SRC_RESERVED;
+				return -EFAULT;
+			}
+		} else if (cc1) {
+			*polarity = TYPEC_POLARITY_CC1;
+
+			switch (cc1) {
+			case 0x1:
+				tcpc_log(port, "SRC.Ra only on CC1\n");
+				return -EFAULT;
+			case 0x2:
+				*state = TYPEC_STATE_SRC_RD;
+				tcpc_log(port, "SRC.Rd on CC1\n");
+				break;
+			case 0x3:
+				*state = TYPEC_STATE_SRC_RESERVED;
+				return -EFAULT;
+			}
+		} else {
+			*state = TYPEC_STATE_OPEN;
+			return -EPERM;
+		}
+	}
+
 	return 0;
 }
 
-int tcpc_clear_alert(struct udevice *i2c_dev, uint16_t clear_mask)
+int tcpc_clear_alert(struct tcpc_port *port, uint16_t clear_mask)
 {
 	int err;
-	err = dm_i2c_write(i2c_dev, TCPC_ALERT, (const uint8_t *)&clear_mask, 2);
+
+	if (port == NULL)
+		return -EINVAL;
+
+	err = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&clear_mask, 2);
 	if (err) {
-		printf("%s dm_i2c_write failed, err %d\n", __func__, err);
+		tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err);
 		return -EIO;
 	}
 
 	return 0;
 }
 
-int tcpc_send_command(struct udevice *i2c_dev, uint8_t command)
+int tcpc_send_command(struct tcpc_port *port, uint8_t command)
 {
 	int err;
-	err = dm_i2c_write(i2c_dev, TCPC_COMMAND, (const uint8_t *)&command, 1);
+
+	if (port == NULL)
+		return -EINVAL;
+
+	err = dm_i2c_write(port->i2c_dev, TCPC_COMMAND, (const uint8_t *)&command, 1);
 	if (err) {
-		printf("%s dm_i2c_write failed, err %d\n", __func__, err);
+		tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err);
 		return -EIO;
 	}
 
 	return 0;
 }
 
-int tcpc_polling_reg(struct udevice *i2c_dev, uint8_t reg,
+int tcpc_polling_reg(struct tcpc_port *port, uint8_t reg,
 	uint8_t reg_width, uint16_t mask, uint16_t value, ulong timeout_ms)
 {
 	uint16_t val = 0;
 	int err;
 	ulong start;
 
-	debug("%s reg 0x%x, mask 0x%x, value 0x%x\n", __func__, reg, mask, value);
+	if (port == NULL)
+		return -EINVAL;
+
+	tcpc_debug_log(port, "%s reg 0x%x, mask 0x%x, value 0x%x\n", __func__, reg, mask, value);
 
 	/* TCPC registers is 8 bits or 16 bits */
 	if (reg_width != 1 && reg_width != 2)
@@ -115,12 +247,10 @@
 
 	start = get_timer(0);	/* Get current timestamp */
 	do {
-		err = dm_i2c_read(i2c_dev, reg, (uint8_t *)&val, reg_width);
+		err = dm_i2c_read(port->i2c_dev, reg, (uint8_t *)&val, reg_width);
 		if (err)
 			return -EIO;
 
-		debug("val = 0x%x\n", val);
-
 		if ((val & mask) == value)
 			return 0;
 	} while (get_timer(0) < (start + timeout_ms));
@@ -128,31 +258,31 @@
 	return -ETIME;
 }
 
-int tcpc_init(struct udevice *i2c_dev)
+void tcpc_print_log(struct tcpc_port *port)
 {
-	int ret;
+	if (port == NULL)
+		return;
 
-	/* Check the Initialization Status bit in 1s */
-	ret = tcpc_polling_reg(i2c_dev, TCPC_POWER_STATUS, 1, TCPC_POWER_STATUS_UNINIT, 0, 1000);
-	if (ret) {
-		printf("%s: Polling TCPC POWER STATUS Initialization Status bit failed, ret = %d\n",
-			__func__, ret);
-		return ret;
-	}
+	if (port->log_print == port->log_p) /*nothing to output*/
+		return;
 
-	tcpc_clear_alert(i2c_dev, 0xffff);
+	printf("%s", port->log_print);
 
-	return 0;
+	port->log_print = port->log_p;
 }
 
-int tcpc_setup_dfp_mode(struct udevice *i2c_dev, ss_mux_sel ss_sel_func)
+int tcpc_setup_dfp_mode(struct tcpc_port *port)
 {
 	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
 	int ret;
 
-	tcpc_set_cc_to_source(i2c_dev);
+	if (port == NULL)
+		return -EINVAL;
 
-	ret = tcpc_send_command(i2c_dev, TCPC_CMD_LOOK4CONNECTION);
+	tcpc_set_cc_to_source(port);
+
+	ret = tcpc_send_command(port, TCPC_CMD_LOOK4CONNECTION);
 	if (ret)
 		return ret;
 
@@ -162,36 +292,35 @@
 	 */
 	mdelay(100);
 
-	ret = tcpc_polling_reg(i2c_dev, TCPC_ALERT, 2, TCPC_ALERT_CC_STATUS, TCPC_ALERT_CC_STATUS, 100);
+	ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_CC_STATUS, TCPC_ALERT_CC_STATUS, 100);
 	if (ret) {
-		printf("%s: Polling ALERT register, TCPC_ALERT_CC_STATUS bit failed, ret = %d\n",
+		tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_CC_STATUS bit failed, ret = %d\n",
 			__func__, ret);
 		return ret;
 	}
 
-	ret = tcpc_get_cc_polarity(i2c_dev, &pol);
-	tcpc_clear_alert(i2c_dev, TCPC_ALERT_CC_STATUS);
+	ret = tcpc_get_cc_status(port, &pol, &state);
+	tcpc_clear_alert(port, TCPC_ALERT_CC_STATUS);
 
 	if (!ret) {
+		/* If presenting as Rd/audio mode/open, return */
+		if (state != TYPEC_STATE_SRC_RD_RA && state != TYPEC_STATE_SRC_RD)
+			return -EPERM;
+
 		if (pol == TYPEC_POLARITY_CC1)
-			debug("polarity cc1\n");
+			tcpc_debug_log(port, "polarity cc1\n");
 		else
-			debug("polarity cc2\n");
+			tcpc_debug_log(port, "polarity cc2\n");
 
-		if (ss_sel_func)
-			ss_sel_func(pol);
+		if (port->ss_sel_func)
+			port->ss_sel_func(pol);
 
-		ret = tcpc_set_plug_orientation(i2c_dev, pol);
-		if (ret)
-			return ret;
-
-		/* Disable sink vbus */
-		ret = tcpc_send_command(i2c_dev, TCPC_CMD_DISABLE_SINK_VBUS);
+		ret = tcpc_set_plug_orientation(port, pol);
 		if (ret)
 			return ret;
 
 		/* Enable source vbus default voltage */
-		ret = tcpc_send_command(i2c_dev, TCPC_CMD_SRC_VBUS_DEFAULT);
+		ret = tcpc_send_command(port, TCPC_CMD_SRC_VBUS_DEFAULT);
 		if (ret)
 			return ret;
 
@@ -203,16 +332,15 @@
 	return 0;
 }
 
-int tcpc_disable_vbus(struct udevice *i2c_dev)
+int tcpc_disable_src_vbus(struct tcpc_port *port)
 {
 	int ret;
 
-	/* Disable VBUS*/
-	ret = tcpc_send_command(i2c_dev, TCPC_CMD_DISABLE_SINK_VBUS);
-	if (ret)
-		return ret;
+	if (port == NULL)
+		return -EINVAL;
 
-	ret = tcpc_send_command(i2c_dev, TCPC_CMD_DISABLE_SRC_VBUS);
+	/* Disable VBUS*/
+	ret = tcpc_send_command(port, TCPC_CMD_DISABLE_SRC_VBUS);
 	if (ret)
 		return ret;
 
@@ -221,3 +349,476 @@
 
 	return 0;
 }
+
+static int tcpc_pd_receive_message(struct tcpc_port *port, struct pd_message *msg)
+{
+	int ret;
+	uint8_t cnt;
+	uint16_t val;
+
+	if (port == NULL)
+		return -EINVAL;
+
+	/* Generally the max tSenderResponse is 30ms, max tTypeCSendSourceCap is 200ms, we set the timeout to 500ms */
+	ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_RX_STATUS, TCPC_ALERT_RX_STATUS, 500);
+	if (ret) {
+		tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_RX_STATUS bit failed, ret = %d\n",
+			__func__, ret);
+		return ret;
+	}
+
+	cnt = 0;
+	ret = dm_i2c_read(port->i2c_dev, TCPC_RX_BYTE_CNT, (uint8_t *)&cnt, 1);
+	if (ret)
+		return -EIO;
+
+	if (cnt > 0) {
+		ret = dm_i2c_read(port->i2c_dev, TCPC_RX_BUF_FRAME_TYPE, (uint8_t *)msg, cnt);
+		if (ret)
+			return -EIO;
+
+		/* Clear RX status alert bit */
+		val = TCPC_ALERT_RX_STATUS;
+		ret = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&val, 2);
+		if (ret)
+			return -EIO;
+	}
+
+	return cnt;
+}
+
+static int tcpc_pd_transmit_message(struct tcpc_port *port, struct pd_message *msg_p, uint8_t bytes)
+{
+	int ret;
+	uint8_t valb;
+	uint16_t val;
+
+	if (port == NULL)
+		return -EINVAL;
+
+	if (msg_p == NULL || bytes <= 0)
+		return -EINVAL;
+
+	ret = dm_i2c_write(port->i2c_dev, TCPC_TX_BYTE_CNT, (const uint8_t *)&bytes, 1);
+	if (ret)
+		return -EIO;
+
+	ret = dm_i2c_write(port->i2c_dev, TCPC_TX_HDR, (const uint8_t *)&(msg_p->header), bytes);
+	if (ret)
+		return -EIO;
+
+	valb = (3 << TCPC_TRANSMIT_RETRY_SHIFT) | (TCPC_TX_SOP << TCPC_TRANSMIT_TYPE_SHIFT);
+	ret = dm_i2c_write(port->i2c_dev, TCPC_TRANSMIT, (const uint8_t *)&valb, 1);
+	if (ret)
+		return -EIO;
+
+	/* Max tReceive is 1.1ms, we set to 5ms timeout */
+	ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_TX_SUCCESS, TCPC_ALERT_TX_SUCCESS, 5);
+	if (ret) {
+		if (ret == -ETIME) {
+			ret = dm_i2c_read(port->i2c_dev, TCPC_ALERT, (uint8_t *)&val, 2);
+			if (ret)
+				return -EIO;
+
+			if (val & TCPC_ALERT_TX_FAILED)
+				tcpc_log(port, "%s: PD TX FAILED, ALERT = 0x%x\n", __func__, val);
+
+			if (val & TCPC_ALERT_TX_DISCARDED)
+				tcpc_log(port, "%s: PD TX DISCARDED, ALERT = 0x%x\n", __func__, val);
+
+		} else {
+			tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_TX_SUCCESS bit failed, ret = %d\n",
+				__func__, ret);
+		}
+	} else {
+		port->tx_msg_id = (port->tx_msg_id + 1) & PD_HEADER_ID_MASK;
+	}
+
+	/* Clear ALERT status */
+	val &= (TCPC_ALERT_TX_FAILED | TCPC_ALERT_TX_DISCARDED | TCPC_ALERT_TX_SUCCESS);
+	ret = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&val, 2);
+	if (ret)
+		return -EIO;
+
+	return ret;
+}
+
+static void tcpc_log_source_caps(struct tcpc_port *port, uint32_t *caps, unsigned int capcount)
+{
+	int i;
+
+	for (i = 0; i < capcount; i++) {
+		u32 pdo = caps[i];
+		enum pd_pdo_type type = pdo_type(pdo);
+
+		tcpc_log(port, "PDO %d: type %d, ",
+			 i, type);
+
+		switch (type) {
+		case PDO_TYPE_FIXED:
+			tcpc_log(port, "%u mV, %u mA [%s%s%s%s%s%s]\n",
+				  pdo_fixed_voltage(pdo),
+				  pdo_max_current(pdo),
+				  (pdo & PDO_FIXED_DUAL_ROLE) ?
+							"R" : "",
+				  (pdo & PDO_FIXED_SUSPEND) ?
+							"S" : "",
+				  (pdo & PDO_FIXED_HIGHER_CAP) ?
+							"H" : "",
+				  (pdo & PDO_FIXED_USB_COMM) ?
+							"U" : "",
+				  (pdo & PDO_FIXED_DATA_SWAP) ?
+							"D" : "",
+				  (pdo & PDO_FIXED_EXTPOWER) ?
+							"E" : "");
+			break;
+		case PDO_TYPE_VAR:
+			tcpc_log(port, "%u-%u mV, %u mA\n",
+				  pdo_min_voltage(pdo),
+				  pdo_max_voltage(pdo),
+				  pdo_max_current(pdo));
+			break;
+		case PDO_TYPE_BATT:
+			tcpc_log(port, "%u-%u mV, %u mW\n",
+				  pdo_min_voltage(pdo),
+				  pdo_max_voltage(pdo),
+				  pdo_max_power(pdo));
+			break;
+		default:
+			tcpc_log(port, "undefined\n");
+			break;
+		}
+	}
+}
+
+static int tcpc_pd_select_pdo(uint32_t *caps, uint32_t capcount, uint32_t max_snk_mv, uint32_t max_snk_ma)
+{
+	unsigned int i, max_mw = 0, max_mv = 0;
+	int ret = -EINVAL;
+
+	/*
+	 * Select the source PDO providing the most power while staying within
+	 * the board's voltage limits. Prefer PDO providing exp
+	 */
+	for (i = 0; i < capcount; i++) {
+		u32 pdo = caps[i];
+		enum pd_pdo_type type = pdo_type(pdo);
+		unsigned int mv, ma, mw;
+
+		if (type == PDO_TYPE_FIXED)
+			mv = pdo_fixed_voltage(pdo);
+		else
+			mv = pdo_min_voltage(pdo);
+
+		if (type == PDO_TYPE_BATT) {
+			mw = pdo_max_power(pdo);
+		} else {
+			ma = min(pdo_max_current(pdo),
+				 max_snk_ma);
+			mw = ma * mv / 1000;
+		}
+
+		/* Perfer higher voltages if available */
+		if ((mw > max_mw || (mw == max_mw && mv > max_mv)) &&
+		    mv <= max_snk_mv) {
+			ret = i;
+			max_mw = mw;
+			max_mv = mv;
+		}
+	}
+
+	return ret;
+}
+
+static int tcpc_pd_build_request(struct tcpc_port *port,
+										uint32_t *caps,
+										uint32_t capcount,
+										uint32_t max_snk_mv,
+										uint32_t max_snk_ma,
+										uint32_t max_snk_mw,
+										uint32_t operating_snk_mw,
+										uint32_t *rdo)
+{
+	unsigned int mv, ma, mw, flags;
+	unsigned int max_ma, max_mw;
+	enum pd_pdo_type type;
+	int index;
+	u32 pdo;
+
+	index = tcpc_pd_select_pdo(caps, capcount, max_snk_mv, max_snk_ma);
+	if (index < 0)
+		return -EINVAL;
+
+	pdo = caps[index];
+	type = pdo_type(pdo);
+
+	if (type == PDO_TYPE_FIXED)
+		mv = pdo_fixed_voltage(pdo);
+	else
+		mv = pdo_min_voltage(pdo);
+
+	/* Select maximum available current within the board's power limit */
+	if (type == PDO_TYPE_BATT) {
+		mw = pdo_max_power(pdo);
+		ma = 1000 * min(mw, max_snk_mw) / mv;
+	} else {
+		ma = min(pdo_max_current(pdo),
+			 1000 * max_snk_mw / mv);
+	}
+	ma = min(ma, max_snk_ma);
+
+	/* XXX: Any other flags need to be set? */
+	flags = 0;
+
+	/* Set mismatch bit if offered power is less than operating power */
+	mw = ma * mv / 1000;
+	max_ma = ma;
+	max_mw = mw;
+	if (mw < operating_snk_mw) {
+		flags |= RDO_CAP_MISMATCH;
+		max_mw = operating_snk_mw;
+		max_ma = max_mw * 1000 / mv;
+	}
+
+	if (type == PDO_TYPE_BATT) {
+		*rdo = RDO_BATT(index + 1, mw, max_mw, flags);
+
+		tcpc_log(port, "Requesting PDO %d: %u mV, %u mW%s\n",
+			 index, mv, mw,
+			 flags & RDO_CAP_MISMATCH ? " [mismatch]" : "");
+	} else {
+		*rdo = RDO_FIXED(index + 1, ma, max_ma, flags);
+
+		tcpc_log(port, "Requesting PDO %d: %u mV, %u mA%s\n",
+			 index, mv, ma,
+			 flags & RDO_CAP_MISMATCH ? " [mismatch]" : "");
+	}
+
+	return 0;
+}
+
+static void tcpc_pd_sink_process(struct tcpc_port *port)
+{
+	int ret;
+	uint8_t msgtype;
+	uint32_t objcnt;
+	struct pd_message msg;
+	enum pd_sink_state pd_state = WAIT_SOURCE_CAP;
+
+	while (tcpc_pd_receive_message(port, &msg) > 0) {
+
+		msgtype = pd_header_type(msg.header);
+		objcnt = pd_header_cnt_le(msg.header);
+
+		tcpc_debug_log(port, "get msg, type %d, cnt %d\n", msgtype, objcnt);
+
+		switch (pd_state) {
+		case WAIT_SOURCE_CAP:
+		case SINK_READY:
+			if (msgtype != PD_DATA_SOURCE_CAP)
+				continue;
+
+			uint32_t *caps = (uint32_t *)&msg.payload;
+			uint32_t rdo = 0;
+
+			tcpc_log_source_caps(port, caps, objcnt);
+
+			tcpc_pd_build_request(port, caps, objcnt,
+				port->cfg.max_snk_mv, port->cfg.max_snk_ma,
+				port->cfg.max_snk_mw, port->cfg.op_snk_mv,
+				&rdo);
+
+			memset(&msg, 0, sizeof(msg));
+			msg.header = PD_HEADER(PD_DATA_REQUEST, 0, 0, port->tx_msg_id, 1);  /* power sink, data device, id 0, len 1 */
+			msg.payload[0] = rdo;
+
+			ret = tcpc_pd_transmit_message(port, &msg, 6);
+			if (ret)
+				tcpc_log(port, "send request failed\n");
+			else
+				pd_state = WAIT_SOURCE_ACCEPT;
+
+			break;
+		case WAIT_SOURCE_ACCEPT:
+			if (objcnt > 0) /* Should be ctrl message */
+				continue;
+
+			if (msgtype == PD_CTRL_ACCEPT) {
+				pd_state = WAIT_SOURCE_READY;
+				tcpc_log(port, "Source accept request\n");
+			} else if (msgtype == PD_CTRL_REJECT) {
+				tcpc_log(port, "Source reject request\n");
+				return;
+			}
+
+			break;
+		case WAIT_SOURCE_READY:
+			if (objcnt > 0) /* Should be ctrl message */
+				continue;
+
+			if (msgtype == PD_CTRL_PS_RDY) {
+				tcpc_log(port, "PD source ready!\n");
+				pd_state = SINK_READY;
+			}
+
+			break;
+		default:
+			tcpc_log(port, "unexpect status: %u\n", pd_state);
+			break;
+		}
+	}
+}
+
+static int tcpc_pd_sink_init(struct tcpc_port *port)
+{
+	uint8_t valb;
+	uint16_t val;
+	int err;
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+
+	if (port == NULL)
+		return -EINVAL;
+
+	port->pd_state = UNATTACH;
+
+	/* Check the VBUS PRES and SINK VBUS for dead battery */
+	err = dm_i2c_read(port->i2c_dev, TCPC_POWER_STATUS, &valb, 1);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	if (!(valb & TCPC_POWER_STATUS_VBUS_PRES)) {
+		tcpc_debug_log(port, "VBUS NOT PRES \n");
+		return -EPERM;
+	}
+
+	if (!(valb & TCPC_POWER_STATUS_SINKING_VBUS)) {
+		tcpc_debug_log(port, "SINK VBUS is not enabled for dead battery\n");
+		return -EPERM;
+	}
+
+	err = dm_i2c_read(port->i2c_dev, TCPC_ALERT, (uint8_t *)&val, 2);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	if (!(val & TCPC_ALERT_CC_STATUS)) {
+		tcpc_debug_log(port, "CC STATUS not detected for dead battery\n");
+		return -EPERM;
+	}
+
+	err = tcpc_get_cc_status(port, &pol, &state);
+	if (err || (state != TYPEC_STATE_SNK_POWER15
+		&& state != TYPEC_STATE_SNK_POWER30
+		&& state != TYPEC_STATE_SNK_DEFAULT)) {
+		tcpc_log(port, "TCPC wrong state for dead battery, err = %d, CC = 0x%x\n",
+			err, state);
+		return -EPERM;
+	} else
+		port->pd_state = ATTACHED;
+
+	dm_i2c_read(port->i2c_dev, TCPC_POWER_CTRL, (uint8_t *)&valb, 1);
+	valb &= ~TCPC_POWER_CTRL_AUTO_DISCH_DISCO; /* disable AutoDischargeDisconnect */
+	dm_i2c_write(port->i2c_dev, TCPC_POWER_CTRL, (const uint8_t *)&valb, 1);
+
+	/* As sink role */
+	valb = 0x00;
+	err = dm_i2c_write(port->i2c_dev, TCPC_MSG_HDR_INFO, (const uint8_t *)&valb, 1);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	/* Enable rx */
+	valb = TCPC_RX_DETECT_SOP | TCPC_RX_DETECT_HARD_RESET;
+	err = dm_i2c_write(port->i2c_dev, TCPC_RX_DETECT, (const uint8_t *)&valb, 1);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	tcpc_pd_sink_process(port);
+
+	return 0;
+}
+
+int tcpc_init(struct tcpc_port *port, struct tcpc_port_config config, ss_mux_sel ss_sel_func)
+{
+	int ret;
+	uint8_t valb;
+	uint16_t vid, pid;
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+
+	memset(port, 0, sizeof(struct tcpc_port));
+
+	if (port == NULL)
+		return -EINVAL;
+
+	port->cfg = config;
+	port->tx_msg_id = 0;
+	port->ss_sel_func = ss_sel_func;
+	port->log_p = (char *)&(port->logbuffer);
+	port->log_size = TCPC_LOG_BUFFER_SIZE;
+	port->log_print = port->log_p;
+	memset(&(port->logbuffer), 0, TCPC_LOG_BUFFER_SIZE);
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, port->cfg.i2c_bus, &bus);
+	if (ret) {
+		printf("%s: Can't find bus\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = dm_i2c_probe(bus, port->cfg.addr, 0, &i2c_dev);
+	if (ret) {
+		printf("%s: Can't find device id=0x%x\n",
+			__func__, config.addr);
+		return -ENODEV;
+	}
+
+	port->i2c_dev = i2c_dev;
+
+	/* Check the Initialization Status bit in 1s */
+	ret = tcpc_polling_reg(port, TCPC_POWER_STATUS, 1, TCPC_POWER_STATUS_UNINIT, 0, 1000);
+	if (ret) {
+		tcpc_log(port, "%s: Polling TCPC POWER STATUS Initialization Status bit failed, ret = %d\n",
+			__func__, ret);
+		return ret;
+	}
+
+	/* Clear AllRegistersResetToDefault */
+	valb = 0x80;
+	ret = dm_i2c_write(port->i2c_dev, TCPC_FAULT_STATUS, (const uint8_t *)&valb, 1);
+	if (ret) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	/* Read Vendor ID and Product ID */
+	ret = dm_i2c_read(port->i2c_dev, TCPC_VENDOR_ID, (uint8_t *)&vid, 2);
+	if (ret) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	ret = dm_i2c_read(port->i2c_dev, TCPC_PRODUCT_ID, (uint8_t *)&pid, 2);
+	if (ret) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	tcpc_log(port, "TCPC:  Vendor ID [0x%x], Product ID [0x%x]\n", vid, pid);
+
+	if (port->cfg.port_type == TYPEC_PORT_UFP
+		|| port->cfg.port_type == TYPEC_PORT_DRP)
+		tcpc_pd_sink_init(port);
+
+	tcpc_clear_alert(port, 0xffff);
+
+	tcpc_print_log(port);
+
+	return 0;
+}
diff --git a/board/freescale/common/tcpc.h b/board/freescale/common/tcpc.h
index ad981d1..c3bb9af 100644
--- a/board/freescale/common/tcpc.h
+++ b/board/freescale/common/tcpc.h
@@ -9,18 +9,29 @@
 
 #include <dm.h>
 
-#define TCPC_TCPC_CTRL			0x19
+#define TCPC_VENDOR_ID			0x0
+#define TCPC_PRODUCT_ID			0x2
+
+#define TCPC_ALERT					0x10
+#define TCPC_ALERT_VBUS_DISCNCT		BIT(11)
+#define TCPC_ALERT_RX_BUF_OVF		BIT(10)
+#define TCPC_ALERT_FAULT			BIT(9)
+#define TCPC_ALERT_V_ALARM_LO		BIT(8)
+#define TCPC_ALERT_V_ALARM_HI		BIT(7)
+#define TCPC_ALERT_TX_SUCCESS		BIT(6)
+#define TCPC_ALERT_TX_DISCARDED		BIT(5)
+#define TCPC_ALERT_TX_FAILED		BIT(4)
+#define TCPC_ALERT_RX_HARD_RST		BIT(3)
+#define TCPC_ALERT_RX_STATUS		BIT(2)
+#define TCPC_ALERT_POWER_STATUS		BIT(1)
+#define TCPC_ALERT_CC_STATUS		BIT(0)
+
+#define TCPC_TCPC_CTRL				0x19
+#define TCPC_TCPC_CTRL_BIST_MODE	BIT(1)
 #define TCPC_TCPC_CTRL_ORIENTATION	BIT(0)
 
-#define TCPC_CC_STATUS			0x1d
-#define TCPC_CC_STATUS_TERM		BIT(4)
-#define TCPC_CC_STATUS_CC2_SHIFT	2
-#define TCPC_CC_STATUS_CC2_MASK		0x3
-#define TCPC_CC_STATUS_CC1_SHIFT	0
-#define TCPC_CC_STATUS_CC1_MASK		0x3
-
-#define TCPC_ROLE_CTRL			0x1a
-#define TCPC_ROLE_CTRL_DRP		BIT(6)
+#define TCPC_ROLE_CTRL				0x1a
+#define TCPC_ROLE_CTRL_DRP			BIT(6)
 #define TCPC_ROLE_CTRL_RP_VAL_SHIFT	4
 #define TCPC_ROLE_CTRL_RP_VAL_MASK	0x3
 #define TCPC_ROLE_CTRL_RP_VAL_DEF	0x0
@@ -35,54 +46,401 @@
 #define TCPC_ROLE_CTRL_CC_RD		0x2
 #define TCPC_ROLE_CTRL_CC_OPEN		0x3
 
-#define TCPC_COMMAND			0x23
-#define TCPC_CMD_WAKE_I2C		0x11
+#define TCPC_POWER_CTRL						0x1c
+#define TCPC_POWER_CTRL_EN_VCONN			BIT(0)
+#define TCPC_POWER_CTRL_VCONN_POWER			BIT(1)
+#define TCPC_POWER_CTRL_FORCE_DISCH			BIT(2)
+#define TCPC_POWER_CTRL_EN_BLEED_CH			BIT(3)
+#define TCPC_POWER_CTRL_AUTO_DISCH_DISCO	BIT(4)
+#define TCPC_POWER_CTRL_DIS_V_ALARMS		BIT(5)
+#define TCPC_POWER_CTRL_VBUS_V_MONITOR		BIT(6)
+
+#define TCPC_CC_STATUS					0x1d
+#define TCPC_CC_STATUS_LOOK4CONN		BIT(5)
+#define TCPC_CC_STATUS_TERM				BIT(4)
+#define TCPC_CC_STATUS_CC2_SHIFT		2
+#define TCPC_CC_STATUS_CC2_MASK			0x3
+#define TCPC_CC_STATUS_CC1_SHIFT		0
+#define TCPC_CC_STATUS_CC1_MASK			0x3
+
+#define TCPC_POWER_STATUS				0x1e
+#define TCPC_POWER_STATUS_UNINIT		BIT(6)
+#define TCPC_POWER_STATUS_VBUS_DET		BIT(3)
+#define TCPC_POWER_STATUS_VBUS_PRES		BIT(2)
+#define TCPC_POWER_STATUS_SINKING_VBUS	BIT(0)
+
+#define TCPC_FAULT_STATUS               0x1f
+
+#define TCPC_COMMAND					0x23
+#define TCPC_CMD_WAKE_I2C				0x11
 #define TCPC_CMD_DISABLE_VBUS_DETECT	0x22
-#define TCPC_CMD_ENABLE_VBUS_DETECT	0x33
-#define TCPC_CMD_DISABLE_SINK_VBUS	0x44
-#define TCPC_CMD_SINK_VBUS		0x55
-#define TCPC_CMD_DISABLE_SRC_VBUS	0x66
-#define TCPC_CMD_SRC_VBUS_DEFAULT	0x77
-#define TCPC_CMD_SRC_VBUS_HIGH		0x88
-#define TCPC_CMD_LOOK4CONNECTION	0x99
-#define TCPC_CMD_RXONEMORE		0xAA
-#define TCPC_CMD_I2C_IDLE		0xFF
+#define TCPC_CMD_ENABLE_VBUS_DETECT		0x33
+#define TCPC_CMD_DISABLE_SINK_VBUS		0x44
+#define TCPC_CMD_SINK_VBUS				0x55
+#define TCPC_CMD_DISABLE_SRC_VBUS		0x66
+#define TCPC_CMD_SRC_VBUS_DEFAULT		0x77
+#define TCPC_CMD_SRC_VBUS_HIGH			0x88
+#define TCPC_CMD_LOOK4CONNECTION		0x99
+#define TCPC_CMD_RXONEMORE				0xAA
+#define TCPC_CMD_I2C_IDLE				0xFF
 
-#define TCPC_ALERT			0x10
-#define TCPC_ALERT_VBUS_DISCNCT		BIT(11)
-#define TCPC_ALERT_RX_BUF_OVF		BIT(10)
-#define TCPC_ALERT_FAULT		BIT(9)
-#define TCPC_ALERT_V_ALARM_LO		BIT(8)
-#define TCPC_ALERT_V_ALARM_HI		BIT(7)
-#define TCPC_ALERT_TX_SUCCESS		BIT(6)
-#define TCPC_ALERT_TX_DISCARDED		BIT(5)
-#define TCPC_ALERT_TX_FAILED		BIT(4)
-#define TCPC_ALERT_RX_HARD_RST		BIT(3)
-#define TCPC_ALERT_RX_STATUS		BIT(2)
-#define TCPC_ALERT_POWER_STATUS		BIT(1)
-#define TCPC_ALERT_CC_STATUS		BIT(0)
+#define TCPC_DEV_CAP_1					0x24
+#define TCPC_DEV_CAP_2					0x26
+#define TCPC_STD_INPUT_CAP				0x28
+#define TCPC_STD_OUTPUT_CAP				0x29
 
-#define TCPC_POWER_STATUS		0x1e
-#define TCPC_POWER_STATUS_UNINIT	BIT(6)
-#define TCPC_POWER_STATUS_VBUS_DET	BIT(3)
-#define TCPC_POWER_STATUS_VBUS_PRES	BIT(2)
+#define TCPC_MSG_HDR_INFO				0x2e
+#define TCPC_MSG_HDR_INFO_DATA_ROLE		BIT(3)
+#define TCPC_MSG_HDR_INFO_PWR_ROLE		BIT(0)
+#define TCPC_MSG_HDR_INFO_REV_SHIFT		1
+#define TCPC_MSG_HDR_INFO_REV_MASK		0x3
+
+#define TCPC_RX_DETECT					0x2f
+#define TCPC_RX_DETECT_HARD_RESET		BIT(5)
+#define TCPC_RX_DETECT_SOP				BIT(0)
+
+#define TCPC_RX_BYTE_CNT				0x30
+#define TCPC_RX_BUF_FRAME_TYPE			0x31
+#define TCPC_RX_HDR						0x32
+#define TCPC_RX_DATA					0x34 /* through 0x4f */
+
+#define TCPC_TRANSMIT					0x50
+#define TCPC_TRANSMIT_RETRY_SHIFT		4
+#define TCPC_TRANSMIT_RETRY_MASK		0x3
+#define TCPC_TRANSMIT_TYPE_SHIFT		0
+#define TCPC_TRANSMIT_TYPE_MASK			0x7
+
+#define TCPC_TX_BYTE_CNT				0x51
+#define TCPC_TX_HDR						0x52
+#define TCPC_TX_DATA					0x54 /* through 0x6f */
+
+#define TCPC_VBUS_VOLTAGE					0x70
+#define TCPC_VBUS_VOL_MASK					0x3ff
+#define TCPC_VBUS_VOL_SCALE_FACTOR_MASK		0xc00
+#define TCPC_VBUS_VOL_SCALE_FACTOR_SHIFT	10
+#define TCPC_VBUS_VOL_MV_UNIT				25
+
+#define TCPC_VBUS_SINK_DISCONNECT_THRESH	0x72
+#define TCPC_VBUS_STOP_DISCHARGE_THRESH		0x74
+#define TCPC_VBUS_VOLTAGE_ALARM_HI_CFG		0x76
+#define TCPC_VBUS_VOLTAGE_ALARM_LO_CFG		0x78
+
+enum typec_role {
+	TYPEC_SINK,
+	TYPEC_SOURCE,
+	TYPEC_ROLE_UNKNOWN,
+};
+
+enum typec_data_role {
+	TYPEC_DEVICE,
+	TYPEC_HOST,
+};
 
 enum typec_cc_polarity {
 	TYPEC_POLARITY_CC1,
 	TYPEC_POLARITY_CC2,
 };
 
+enum typec_cc_state {
+	TYPEC_STATE_OPEN,
+	TYPEC_STATE_SRC_BOTH_RA,
+	TYPEC_STATE_SRC_RD_RA,
+	TYPEC_STATE_SRC_RD,
+	TYPEC_STATE_SRC_RESERVED,
+	TYPEC_STATE_SNK_DEFAULT,
+	TYPEC_STATE_SNK_POWER15,
+	TYPEC_STATE_SNK_POWER30,
+};
+
+
+/* USB PD Messages */
+enum pd_ctrl_msg_type {
+	/* 0 Reserved */
+	PD_CTRL_GOOD_CRC = 1,
+	PD_CTRL_GOTO_MIN = 2,
+	PD_CTRL_ACCEPT = 3,
+	PD_CTRL_REJECT = 4,
+	PD_CTRL_PING = 5,
+	PD_CTRL_PS_RDY = 6,
+	PD_CTRL_GET_SOURCE_CAP = 7,
+	PD_CTRL_GET_SINK_CAP = 8,
+	PD_CTRL_DR_SWAP = 9,
+	PD_CTRL_PR_SWAP = 10,
+	PD_CTRL_VCONN_SWAP = 11,
+	PD_CTRL_WAIT = 12,
+	PD_CTRL_SOFT_RESET = 13,
+	/* 14-15 Reserved */
+};
+
+enum pd_data_msg_type {
+	/* 0 Reserved */
+	PD_DATA_SOURCE_CAP = 1,
+	PD_DATA_REQUEST = 2,
+	PD_DATA_BIST = 3,
+	PD_DATA_SINK_CAP = 4,
+	/* 5-14 Reserved */
+	PD_DATA_VENDOR_DEF = 15,
+};
+
+enum tcpc_transmit_type {
+	TCPC_TX_SOP = 0,
+	TCPC_TX_SOP_PRIME = 1,
+	TCPC_TX_SOP_PRIME_PRIME = 2,
+	TCPC_TX_SOP_DEBUG_PRIME = 3,
+	TCPC_TX_SOP_DEBUG_PRIME_PRIME = 4,
+	TCPC_TX_HARD_RESET = 5,
+	TCPC_TX_CABLE_RESET = 6,
+	TCPC_TX_BIST_MODE_2 = 7
+};
+
+enum pd_sink_state{
+	UNATTACH = 0,
+	ATTACHED,
+	WAIT_SOURCE_CAP,
+	WAIT_SOURCE_ACCEPT,
+	WAIT_SOURCE_READY,
+	SINK_READY,
+};
+
+
+#define PD_REV10        0x0
+#define PD_REV20        0x1
+
+#define PD_HEADER_CNT_SHIFT     12
+#define PD_HEADER_CNT_MASK      0x7
+#define PD_HEADER_ID_SHIFT      9
+#define PD_HEADER_ID_MASK       0x7
+#define PD_HEADER_PWR_ROLE      BIT(8)
+#define PD_HEADER_REV_SHIFT     6
+#define PD_HEADER_REV_MASK      0x3
+#define PD_HEADER_DATA_ROLE     BIT(5)
+#define PD_HEADER_TYPE_SHIFT    0
+#define PD_HEADER_TYPE_MASK     0xf
+
+#define PD_HEADER(type, pwr, data, id, cnt)                             \
+	((((type) & PD_HEADER_TYPE_MASK) << PD_HEADER_TYPE_SHIFT) |     \
+	 ((pwr) == TYPEC_SOURCE ? PD_HEADER_PWR_ROLE : 0) |             \
+	 ((data) == TYPEC_HOST ? PD_HEADER_DATA_ROLE : 0) |             \
+	 (PD_REV20 << PD_HEADER_REV_SHIFT) |                            \
+	 (((id) & PD_HEADER_ID_MASK) << PD_HEADER_ID_SHIFT) |           \
+	 (((cnt) & PD_HEADER_CNT_MASK) << PD_HEADER_CNT_SHIFT))
+
+
+static inline unsigned int pd_header_cnt(uint16_t header)
+{
+	return (header >> PD_HEADER_CNT_SHIFT) & PD_HEADER_CNT_MASK;
+}
+
+static inline unsigned int pd_header_cnt_le(__le16 header)
+{
+	return pd_header_cnt(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_type(uint16_t header)
+{
+	return (header >> PD_HEADER_TYPE_SHIFT) & PD_HEADER_TYPE_MASK;
+}
+
+static inline unsigned int pd_header_type_le(__le16 header)
+{
+	return pd_header_type(le16_to_cpu(header));
+}
+
+#define PD_MAX_PAYLOAD          7
+
+struct pd_message {
+	uint8_t   frametype;
+	uint16_t  header;
+	uint32_t  payload[PD_MAX_PAYLOAD];
+} __packed;
+
+enum pd_pdo_type {
+	PDO_TYPE_FIXED = 0,
+	PDO_TYPE_BATT = 1,
+	PDO_TYPE_VAR = 2,
+};
+
+
+#define PDO_TYPE_SHIFT          30
+#define PDO_TYPE_MASK           0x3
+
+#define PDO_TYPE(t)     ((t) << PDO_TYPE_SHIFT)
+
+#define PDO_VOLT_MASK           0x3ff
+#define PDO_CURR_MASK           0x3ff
+#define PDO_PWR_MASK            0x3ff
+
+#define PDO_FIXED_DUAL_ROLE     BIT(29) /* Power role swap supported */
+#define PDO_FIXED_SUSPEND       BIT(28) /* USB Suspend supported (Source) */
+#define PDO_FIXED_HIGHER_CAP    BIT(28) /* Requires more than vSafe5V (Sink) */
+#define PDO_FIXED_EXTPOWER      BIT(27) /* Externally powered */
+#define PDO_FIXED_USB_COMM      BIT(26) /* USB communications capable */
+#define PDO_FIXED_DATA_SWAP     BIT(25) /* Data role swap supported */
+#define PDO_FIXED_VOLT_SHIFT    10      /* 50mV units */
+#define PDO_FIXED_CURR_SHIFT    0       /* 10mA units */
+
+#define PDO_FIXED_VOLT(mv)      ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT)
+#define PDO_FIXED_CURR(ma)      ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT)
+
+#define PDO_FIXED(mv, ma, flags)                        \
+	(PDO_TYPE(PDO_TYPE_FIXED) | (flags) |           \
+	 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
+
+#define PDO_BATT_MAX_VOLT_SHIFT 20      /* 50mV units */
+#define PDO_BATT_MIN_VOLT_SHIFT 10      /* 50mV units */
+#define PDO_BATT_MAX_PWR_SHIFT  0       /* 250mW units */
+
+#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT)
+#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT)
+#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT)
+
+#define PDO_BATT(min_mv, max_mv, max_mw)                        \
+	(PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) |  \
+	 PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw))
+
+#define PDO_VAR_MAX_VOLT_SHIFT  20      /* 50mV units */
+#define PDO_VAR_MIN_VOLT_SHIFT  10      /* 50mV units */
+#define PDO_VAR_MAX_CURR_SHIFT  0       /* 10mA units */
+
+#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT)
+#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT)
+#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT)
+
+#define PDO_VAR(min_mv, max_mv, max_ma)                         \
+	(PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) |    \
+	 PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma))
+
+static inline enum pd_pdo_type pdo_type(uint32_t pdo)
+{
+	return (pdo >> PDO_TYPE_SHIFT) & PDO_TYPE_MASK;
+}
+
+static inline unsigned int pdo_fixed_voltage(uint32_t pdo)
+{
+	return ((pdo >> PDO_FIXED_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_min_voltage(uint32_t pdo)
+{
+	return ((pdo >> PDO_VAR_MIN_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_max_voltage(uint32_t pdo)
+{
+	return ((pdo >> PDO_VAR_MAX_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_max_current(uint32_t pdo)
+{
+	return ((pdo >> PDO_VAR_MAX_CURR_SHIFT) & PDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int pdo_max_power(uint32_t pdo)
+{
+	return ((pdo >> PDO_BATT_MAX_PWR_SHIFT) & PDO_PWR_MASK) * 250;
+}
+
+/* RDO: Request Data Object */
+#define RDO_OBJ_POS_SHIFT       28
+#define RDO_OBJ_POS_MASK        0x7
+#define RDO_GIVE_BACK           BIT(27) /* Supports reduced operating current */
+#define RDO_CAP_MISMATCH        BIT(26) /* Not satisfied by source caps */
+#define RDO_USB_COMM            BIT(25) /* USB communications capable */
+#define RDO_NO_SUSPEND          BIT(24) /* USB Suspend not supported */
+
+#define RDO_PWR_MASK                    0x3ff
+#define RDO_CURR_MASK                   0x3ff
+
+#define RDO_FIXED_OP_CURR_SHIFT         10
+#define RDO_FIXED_MAX_CURR_SHIFT        0
+
+#define RDO_OBJ(idx) (((idx) & RDO_OBJ_POS_MASK) << RDO_OBJ_POS_SHIFT)
+
+#define PDO_FIXED_OP_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_OP_CURR_SHIFT)
+#define PDO_FIXED_MAX_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_MAX_CURR_SHIFT)
+
+#define RDO_FIXED(idx, op_ma, max_ma, flags)                    \
+	(RDO_OBJ(idx) | (flags) |                               \
+	 PDO_FIXED_OP_CURR(op_ma) | PDO_FIXED_MAX_CURR(max_ma))
+
+#define RDO_BATT_OP_PWR_SHIFT           10      /* 250mW units */
+#define RDO_BATT_MAX_PWR_SHIFT          0       /* 250mW units */
+
+#define RDO_BATT_OP_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_OP_PWR_SHIFT)
+#define RDO_BATT_MAX_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_MAX_PWR_SHIFT)
+
+#define RDO_BATT(idx, op_mw, max_mw, flags)                     \
+	(RDO_OBJ(idx) | (flags) |                               \
+	 RDO_BATT_OP_PWR(op_mw) | RDO_BATT_MAX_PWR(max_mw))
+
+static inline unsigned int rdo_index(u32 rdo)
+{
+	return (rdo >> RDO_OBJ_POS_SHIFT) & RDO_OBJ_POS_MASK;
+}
+
+static inline unsigned int rdo_op_current(u32 rdo)
+{
+	return ((rdo >> RDO_FIXED_OP_CURR_SHIFT) & RDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int rdo_max_current(u32 rdo)
+{
+	return ((rdo >> RDO_FIXED_MAX_CURR_SHIFT) &
+			RDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int rdo_op_power(u32 rdo)
+{
+	return ((rdo >> RDO_BATT_OP_PWR_SHIFT) & RDO_PWR_MASK) * 250;
+}
+
+static inline unsigned int rdo_max_power(u32 rdo)
+{
+	return ((rdo >> RDO_BATT_MAX_PWR_SHIFT) & RDO_PWR_MASK) * 250;
+}
+
+#define TCPC_LOG_BUFFER_SIZE 1024
+
 typedef void (*ss_mux_sel)(enum typec_cc_polarity pol);
 
-int tcpc_set_cc_to_source(struct udevice *i2c_dev);
-int tcpc_set_plug_orientation(struct udevice *i2c_dev, enum typec_cc_polarity polarity);
-int tcpc_get_cc_polarity(struct udevice *i2c_dev, enum typec_cc_polarity *polarity);
-int tcpc_clear_alert(struct udevice *i2c_dev, uint16_t clear_mask);
-int tcpc_send_command(struct udevice *i2c_dev, uint8_t command);
-int tcpc_polling_reg(struct udevice *i2c_dev, uint8_t reg,
+enum tcpc_port_type {
+	TYPEC_PORT_DFP,
+	TYPEC_PORT_UFP,
+	TYPEC_PORT_DRP,
+};
+
+struct tcpc_port_config {
+	uint8_t i2c_bus;
+	uint8_t addr;
+	enum tcpc_port_type port_type;
+	uint32_t max_snk_mv;
+	uint32_t max_snk_ma;
+	uint32_t max_snk_mw;
+	uint32_t op_snk_mv;
+};
+
+struct tcpc_port {
+	struct tcpc_port_config cfg;
+	struct udevice *i2c_dev;
+	ss_mux_sel ss_sel_func;
+	enum pd_sink_state pd_state;
+	uint32_t tx_msg_id;
+	uint32_t log_size;
+	char logbuffer[TCPC_LOG_BUFFER_SIZE];
+	char *log_p;
+	char *log_print;
+};
+
+int tcpc_set_cc_to_source(struct tcpc_port *port);
+int tcpc_set_plug_orientation(struct tcpc_port *port, enum typec_cc_polarity polarity);
+int tcpc_get_cc_status(struct tcpc_port *port, enum typec_cc_polarity *polarity, enum typec_cc_state *state);
+int tcpc_clear_alert(struct tcpc_port *port, uint16_t clear_mask);
+int tcpc_send_command(struct tcpc_port *port, uint8_t command);
+int tcpc_polling_reg(struct tcpc_port *port, uint8_t reg,
 	uint8_t reg_width, uint16_t mask, uint16_t value, ulong timeout_ms);
-int tcpc_setup_dfp_mode(struct udevice *i2c_dev, ss_mux_sel ss_sel_func);
-int tcpc_disable_vbus(struct udevice *i2c_dev);
-int tcpc_init(struct udevice *i2c_dev);
+int tcpc_setup_dfp_mode(struct tcpc_port *port);
+int tcpc_disable_src_vbus(struct tcpc_port *port);
+int tcpc_init(struct tcpc_port *port, struct tcpc_port_config config, ss_mux_sel ss_sel_func);
+void tcpc_print_log(struct tcpc_port *port);
 
 #endif /* __TCPCI_H */
diff --git a/board/freescale/imx8mq_evk/Kconfig b/board/freescale/imx8mq_evk/Kconfig
index 421b081..3f3bddf 100644
--- a/board/freescale/imx8mq_evk/Kconfig
+++ b/board/freescale/imx8mq_evk/Kconfig
@@ -9,4 +9,6 @@
 config SYS_CONFIG_NAME
 	default "imx8mq_evk"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/imx8mq_evk/ddr/ddr_init.c b/board/freescale/imx8mq_evk/ddr/ddr_init.c
index 80971ec..b6d922f 100644
--- a/board/freescale/imx8mq_evk/ddr/ddr_init.c
+++ b/board/freescale/imx8mq_evk/ddr/ddr_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -25,64 +25,101 @@
 #define DDR_CSD1_BASE_ADDR 0x40000000
 #endif
 #define SILICON_TRAIN
+#define DDR_BOOT_P1	/* default DDR boot frequency point */
+#define WR_POST_EXT_3200
 
 volatile unsigned int tmp, tmp_t, i;
 void lpddr4_800MHz_cfg_umctl2(void)
 {
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000304, 0x00000001);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000030, 0x00000001);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000000, 0x83080020);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000064, 0x006180e0);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000d0, 0xc003061B);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000d4, 0x009D0000);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000d8, 0x0000fe05);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000dc, 0x00d4002d);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000e0, 0x00310008);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000e4, 0x00040009);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000e8, 0x0046004d);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000ec, 0x0005004d);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000f4, 0x00000979);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000100, 0x1a203522);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000104, 0x00060630);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000108, 0x070e1214);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000010c, 0x00b0c006);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000110, 0x0f04080f);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000114, 0x0d0d0c0c);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000118, 0x01010007);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000011c, 0x0000060a);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000120, 0x01010101);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000124, 0x40000008);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000128, 0x00050d01);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000012c, 0x01010008);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000130, 0x00020000);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000134, 0x18100002);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000138, 0x00000dc2);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000013c, 0x80000000);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000144, 0x00a00050);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000180, 0x53200018);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000184, 0x02800070);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000188, 0x00000000);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000190, 0x0397820a);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00002190, 0x0397820a);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00003190, 0x0397820a);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000194, 0x00020103);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001a0, 0xe0400018);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001a4, 0x00df00e4);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001a8, 0x00000000);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001b0, 0x00000011);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001b4, 0x0000170a);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001c0, 0x00000001);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001c4, 0x00000000);
+	/* Start to config, default 3200mbps */
+	/* dis_dq=1, indicates no reads or writes are issued to SDRAM */
+	 reg32_write(DDRC_DBG1(0), 0x00000001);
+	/* selfref_en=1, SDRAM enter self-refresh state */
+	reg32_write(DDRC_PWRCTL(0), 0x00000001);
+	reg32_write(DDRC_MSTR(0), 0xa3080020);
+	reg32_write(DDRC_MSTR2(0), 0x00000000);
+	reg32_write(DDRC_RFSHTMG(0), 0x006100E0);
+	reg32_write(DDRC_INIT0(0), 0xC003061B);
+	reg32_write(DDRC_INIT1(0), 0x009D0000);
+	reg32_write(DDRC_INIT3(0), 0x00D4002D);
+#ifdef WR_POST_EXT_3200  // recommened to define
+	reg32_write(DDRC_INIT4(0), 0x00330008);
+#else
+	reg32_write(DDRC_INIT4(0), 0x00310008);
+#endif
+	reg32_write(DDRC_INIT6(0), 0x0066004a);
+	reg32_write(DDRC_INIT7(0), 0x0006004a);
+
+	reg32_write(DDRC_DRAMTMG0(0), 0x1A201B22);
+	reg32_write(DDRC_DRAMTMG1(0), 0x00060633);
+	reg32_write(DDRC_DRAMTMG3(0), 0x00C0C000);
+	reg32_write(DDRC_DRAMTMG4(0), 0x0F04080F);
+	reg32_write(DDRC_DRAMTMG5(0), 0x02040C0C);
+	reg32_write(DDRC_DRAMTMG6(0), 0x01010007);
+	reg32_write(DDRC_DRAMTMG7(0), 0x00000401);
+	reg32_write(DDRC_DRAMTMG12(0), 0x00020600);
+	reg32_write(DDRC_DRAMTMG13(0), 0x0C100002);
+	reg32_write(DDRC_DRAMTMG14(0), 0x000000E6);
+	reg32_write(DDRC_DRAMTMG17(0), 0x00A00050);
+
+	reg32_write(DDRC_ZQCTL0(0), 0x03200018);
+	reg32_write(DDRC_ZQCTL1(0), 0x028061A8);
+	reg32_write(DDRC_ZQCTL2(0), 0x00000000);
+
+	reg32_write(DDRC_DFITMG0(0), 0x0497820A);
+	reg32_write(DDRC_DFITMG1(0), 0x00080303);
+	reg32_write(DDRC_DFIUPD0(0), 0xE0400018);
+	reg32_write(DDRC_DFIUPD1(0), 0x00DF00E4);
+	reg32_write(DDRC_DFIUPD2(0), 0x80000000);
+	reg32_write(DDRC_DFIMISC(0), 0x00000011);
+	reg32_write(DDRC_DFITMG2(0), 0x0000170A);
+
+	reg32_write(DDRC_DBICTL(0), 0x00000001);
+	reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001);
+
+	/* need be refined by ddrphy trained value */
+	reg32_write(DDRC_RANKCTL(0), 0x00000c99);
+	reg32_write(DDRC_DRAMTMG2(0), 0x070E171a);
+
+	/* address mapping */
 	/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
-	dwc_ddrphy_apb_wr(DDRC_ADDRMAP0(0), 0x00000015);
-	dwc_ddrphy_apb_wr(DDRC_ADDRMAP4(0), 0x00001F1F);
+	reg32_write(DDRC_ADDRMAP0(0), 0x00000015);
+	reg32_write(DDRC_ADDRMAP3(0), 0x00000000);
+	/* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
+	reg32_write(DDRC_ADDRMAP4(0), 0x00001F1F);
 	/* bank interleave */
-	dwc_ddrphy_apb_wr(DDRC_ADDRMAP1(0), 0x00080808);
-	dwc_ddrphy_apb_wr(DDRC_ADDRMAP5(0), 0x07070707);
-	dwc_ddrphy_apb_wr(DDRC_ADDRMAP6(0), 0x08080707);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000240, 0x020f0c54);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000244, 0x00000000);
-	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000490, 0x00000001);
+	/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
+	reg32_write(DDRC_ADDRMAP1(0), 0x00080808);
+	/* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
+	reg32_write(DDRC_ADDRMAP5(0), 0x07070707);
+	/* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
+	reg32_write(DDRC_ADDRMAP6(0), 0x08080707);
+
+	/* 667mts frequency setting */
+	reg32_write(DDRC_FREQ1_DERATEEN(0), 0x0000000);
+	reg32_write(DDRC_FREQ1_DERATEINT(0), 0x0800000);
+	reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0210000);
+	reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x014001E);
+	reg32_write(DDRC_FREQ1_INIT3(0), 0x0140009);
+	reg32_write(DDRC_FREQ1_INIT4(0), 0x00310008);
+	reg32_write(DDRC_FREQ1_INIT6(0), 0x0066004a);
+	reg32_write(DDRC_FREQ1_INIT7(0), 0x0006004a);
+	reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0xB070A07);
+	reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x003040A);
+	reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x305080C);
+	reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x0505000);
+	reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x3040203);
+	reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x2030303);
+	reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x2020004);
+	reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x0000302);
+	reg32_write(DDRC_FREQ1_DRAMTMG12(0), 0x0020310);
+	reg32_write(DDRC_FREQ1_DRAMTMG13(0), 0xA100002);
+	reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x0000020);
+	reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x0220011);
+	reg32_write(DDRC_FREQ1_ZQCTL0(0), 0x0A70005);
+	reg32_write(DDRC_FREQ1_DFITMG0(0), 0x3858202);
+	reg32_write(DDRC_FREQ1_DFITMG1(0), 0x0000404);
+	reg32_write(DDRC_FREQ1_DFITMG2(0), 0x0000502);
 
 	/* performance setting */
 	dwc_ddrphy_apb_wr(DDRC_ODTCFG(0), 0x0b060908);
@@ -111,67 +148,21 @@
 	dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHTMG(0), 0x00610090);
 }
 
-void lpddr4_100MHz_cfg_umctl2(void)
-{
-	reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c);
-	reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x00030410);
-	reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x0305090c);
-	reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x00505006);
-	reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x05040305);
-	reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504);
-	reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0a060004);
-	reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x0000090e);
-	reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x00000032);
-	reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x00000000);
-	reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x0036001b);
-	reg32_write(DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1);
-	reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0020d040);
-	reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03818200);
-	reg32_write(DDRC_FREQ1_ODTCFG(0), 0x0a1a096c);
-	reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000000);
-	reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x00038014);
-	reg32_write(DDRC_FREQ1_INIT3(0), 0x00840000);
-	reg32_write(DDRC_FREQ1_INIT6(0), 0x0000004d);
-	reg32_write(DDRC_FREQ1_INIT7(0), 0x0000004d);
-	reg32_write(DDRC_FREQ1_INIT4(0), 0x00310000);
-}
-
-void lpddr4_25MHz_cfg_umctl2(void)
-{
-	reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c);
-	reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x00030410);
-	reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x0305090c);
-	reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x00505006);
-	reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x05040305);
-	reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504);
-	reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x0a060004);
-	reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x0000090e);
-	reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x00000032);
-	reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000);
-	reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x0036001b);
-	reg32_write(DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1);
-	reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x0020d040);
-	reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03818200);
-	reg32_write(DDRC_FREQ2_ODTCFG(0), 0x0a1a096c);
-	reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000000);
-	reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x0003800c);
-	reg32_write(DDRC_FREQ2_INIT3(0), 0x00840000);
-	reg32_write(DDRC_FREQ2_INIT6(0), 0x0000004d);
-	reg32_write(DDRC_FREQ2_INIT7(0), 0x0000004d);
-	reg32_write(DDRC_FREQ2_INIT4(0), 0x00310000);
-}
-
 void ddr_init(void)
 {
-	/* change the clock source of dram_apb_clk_root  */
-	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
-	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16));
-
-	/* disable the clock gating */
-	reg32_write(0x303A00EC,0x0000ffff);
-	reg32setbit(0x303A00F8,5);
+	reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
+	mdelay(100);
 	reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
 
+	/* change the clock source of dram_apb_clk_root */
+	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7<<24)|(0x7<<16));
+	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4<<24)|(0x3<<16));
+
+	/* disable iso */
+	reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
+	reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
+
 	dram_pll_init(SSCG_PLL_OUT_800M);
 
 	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
@@ -179,46 +170,82 @@
 	/* Configure uMCTL2's registers */
 	lpddr4_800MHz_cfg_umctl2();
 
+#ifdef DDR_BOOT_P2
+	reg32_write(DDRC_MSTR2(0), 0x2);
+#else
+#ifdef DDR_BOOT_P1
+	reg32_write(DDRC_MSTR2(0), 0x1);
+#endif
+#endif
+	/* release [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n */
 	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
+
+	/* release [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n */
 	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
 
 	reg32_write(DDRC_DBG1(0), 0x00000000);
 	tmp = reg32_read(DDRC_PWRCTL(0));
 	reg32_write(DDRC_PWRCTL(0), 0x000000a8);
-	/* reg32_write(DDRC_PWRCTL(0), 0x0000018a); */
-	reg32_write(DDRC_SWCTL(0), 0x00000000);
-	reg32_write(DDRC_DDR_SS_GPR0, 0x01);
-	reg32_write(DDRC_DFIMISC(0), 0x00000010);
 
-	/* Configure LPDDR4 PHY's registers */
+	while ((reg32_read(DDRC_STAT(0)) & 0x33f) != 0x223)
+		;
+
+	reg32_write(DDRC_SWCTL(0), 0x00000000);
+
+	/* LPDDR4 mode */
+	reg32_write(DDRC_DDR_SS_GPR0, 0x01);
+
+#ifdef DDR_BOOT_P1
+	reg32_write(DDRC_DFIMISC(0), 0x00000110);
+#else
+	reg32_write(DDRC_DFIMISC(0), 0x00000010);
+#endif
+	/* LPDDR4 PHY config and training */
 	lpddr4_800M_cfg_phy();
 
 	reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+
 	reg32_write(DDRC_SWCTL(0), 0x0000);
-	/*
-	 * ------------------- 9 -------------------
-	 * Set DFIMISC.dfi_init_start to 1
-	 *  -----------------------------------------
-	 */
+
+	/* Set DFIMISC.dfi_init_start to 1 */
+#ifdef DDR_BOOT_P2
+	reg32_write(DDRC_DFIMISC(0), 0x00000230);
+#else
+#ifdef DDR_BOOT_P1
+	reg32_write(DDRC_DFIMISC(0), 0x00000130);
+#else
 	reg32_write(DDRC_DFIMISC(0), 0x00000030);
+#endif
+#endif
 	reg32_write(DDRC_SWCTL(0), 0x0001);
 
 	/* wait DFISTAT.dfi_init_complete to 1 */
-	tmp_t = 0;
-	while(tmp_t==0){
-		tmp  = reg32_read(DDRC_DFISTAT(0));
-		tmp_t = tmp & 0x01;
-		tmp  = reg32_read(DDRC_MRSTAT(0));
-	}
+	while ((reg32_read(DDRC_DFISTAT(0)) & 0x1) == 0x0)
+		;
 
 	reg32_write(DDRC_SWCTL(0), 0x0000);
 
+#ifdef DDR_BOOT_P2
+	reg32_write(DDRC_DFIMISC(0), 0x00000210);
+	/* set DFIMISC.dfi_init_complete_en again */
+	reg32_write(DDRC_DFIMISC(0), 0x00000211);
+#else
+#ifdef DDR_BOOT_P1
+	reg32_write(DDRC_DFIMISC(0), 0x00000110);
+	/* set DFIMISC.dfi_init_complete_en again */
+	reg32_write(DDRC_DFIMISC(0), 0x00000111);
+#else
 	/* clear DFIMISC.dfi_init_complete_en */
 	reg32_write(DDRC_DFIMISC(0), 0x00000010);
+	/* set DFIMISC.dfi_init_complete_en again */
 	reg32_write(DDRC_DFIMISC(0), 0x00000011);
+#endif
+#endif
+
 	reg32_write(DDRC_PWRCTL(0), 0x00000088);
 
 	tmp = reg32_read(DDRC_CRCPARSTAT(0));
+
 	/*
 	 * set SWCTL.sw_done to enable quasi-dynamic register
 	 * programming outside reset.
@@ -226,7 +253,7 @@
 	reg32_write(DDRC_SWCTL(0), 0x00000001);
 
 	/* wait SWSTAT.sw_done_ack to 1 */
-	while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
+	while ((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0x0)
 		;
 
 	/* wait STAT.operating_mode([1:0] for ddr3) to normal state */
@@ -234,23 +261,11 @@
 		;
 
 	reg32_write(DDRC_PWRCTL(0), 0x00000088);
-	/* reg32_write(DDRC_PWRCTL(0), 0x018a); */
+
 	tmp = reg32_read(DDRC_CRCPARSTAT(0));
 
-	/* enable port 0 */
 	reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+
 	tmp = reg32_read(DDRC_CRCPARSTAT(0));
 	reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
-
-	reg32_write(DDRC_SWCTL(0), 0x0);
-	lpddr4_100MHz_cfg_umctl2();
-	lpddr4_25MHz_cfg_umctl2();
-	reg32_write(DDRC_SWCTL(0), 0x1);
-
-	/* wait SWSTAT.sw_done_ack to 1 */
-	while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
-		;
-
-	reg32_write(DDRC_SWCTL(0), 0x0);
-
 }
diff --git a/board/freescale/imx8mq_evk/ddr/ddrphy_train.c b/board/freescale/imx8mq_evk/ddr/ddrphy_train.c
index c4e4378..a8a82b5 100644
--- a/board/freescale/imx8mq_evk/ddr/ddrphy_train.c
+++ b/board/freescale/imx8mq_evk/ddr/ddrphy_train.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -9,68 +9,92 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/ddr_memory_map.h>
 #include "ddr.h"
+#include "lpddr4_dvfs.h"
 
-void ddr_pll_bypass_100mts(void) {
-	/* change the clock source of dram_alt_clk_root to source 2 --100MHz */
-	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0),(0x7<<24)|(0x7<<16));
-	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0),(0x2<<24));
+extern void wait_ddrphy_training_complete(void);
 
-	/* change the clock source of dram_apb_clk_root to source 2 --40MHz */
-	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
-	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x2<<24)|(0x1<<16));
-
-	/* disable the clock gating */
-	reg32_write(0x303A00EC,0x0000ffff); /* PGC_CPU_MAPPING */
-	reg32setbit(0x303A00F8,5);          /* PU_PGC_SW_PUP_REQ */
-
-	/* configure pll bypass mode */
-	reg32_write(0x30389804, 1<<24);
-
-	printf("PLL bypass to 100MTS setting done \n");
-}
-
-void ddr_pll_bypass_400mts(void) {
-    /* change the clock source of dram_alt_clk_root to source 2 --400MHz */
-    reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0),(0x7<<24)|(0x7<<16));
-    reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0),(0x5<<24));
-
-    /* change the clock source of dram_apb_clk_root to source 2 --40MHz/2 */
-    reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
-    reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x2<<24)|(0x1<<16));
-
-    /* disable the clock gating */
-    reg32_write(0x303A00EC,0x0000ffff); /* PGC_CPU_MAPPING */
-    reg32setbit(0x303A00F8,5);          /* PU_PGC_SW_PUP_REQ */
-
-    /* configure pll bypass mode */
-    reg32_write(0x30389804, 1<<24);
-
-    printf("PLL bypass to 400MTS setting done \n");
-}
-
-
-void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate)
+void sscgpll_bypass_enable(unsigned int reg_addr)
 {
-	if (pstate == 2)
-		ddr_pll_bypass_100mts();
-	else if (pstate == 1)
-		ddr_pll_bypass_400mts();
-	else {
-		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16));
-		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4 << 24) | (0x3 << 16));
-		reg32_write(0x30389808, 1 << 24);
+	unsigned int read_data;
+	read_data = reg32_read(reg_addr);
+	reg32_write(reg_addr, read_data | 0x00000010);
+	read_data = reg32_read(reg_addr);
+	reg32_write(reg_addr, read_data | 0x00000020);
+}
+
+void sscgpll_bypass_disable(unsigned int reg_addr)
+{
+	unsigned int read_data;
+	read_data = reg32_read(reg_addr);
+	reg32_write(reg_addr, read_data & 0xffffffdf);
+	read_data = reg32_read(reg_addr);
+	reg32_write(reg_addr, read_data & 0xffffffef);
+}
+
+unsigned int wait_pll_lock(unsigned int reg_addr)
+{
+	unsigned int pll_lock;
+	pll_lock = reg32_read(reg_addr) >> 31;
+	return pll_lock;
+}
+
+void ddr_pll_config_freq(unsigned int freq)
+{
+	unsigned int ddr_pll_lock = 0x0;
+	sscgpll_bypass_enable(HW_DRAM_PLL_CFG0_ADDR);
+	switch (freq) {
+	case 800:
+		reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ece580);
+		break;
+	case 700:
+		reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ec4580);
+		break;
+	case 667:
+		reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ece480);
+		break;
+	case 400:
+		reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ec6984);
+		break;
+	case 167:
+		reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00f5a406);
+		break;
+	case 100:
+		reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x015dea96);
+		break;
+	default:
+		printf("Input freq=%d error.\n",freq);
+	}
+
+	sscgpll_bypass_disable(HW_DRAM_PLL_CFG0_ADDR);
+	while (ddr_pll_lock != 0x1) {
+		ddr_pll_lock = wait_pll_lock(HW_DRAM_PLL_CFG0_ADDR);
 	}
 }
 
-void lpddr4_800M_cfg_phy(void) {
-	unsigned int tmp, tmp_t;
+void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate)
+{
+	if (pstate == 0x1) {
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7<<24)|(0x7<<16));
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4<<24)|(0x4<<16)); /* to source 4 --800MHz/5 */
+		ddr_pll_config_freq(167);
+	} else {
+		ddr_pll_config_freq(800);
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7<<24)|(0x7<<16));
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4<<24)|(0x3<<16)); /* to source 4 --800MHz/4 */
+	}
+}
 
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20110, 0x02);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20111, 0x03);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20112, 0x04);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20113, 0x05);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20114, 0x00);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20115, 0x01);
+void lpddr4_800M_cfg_phy(void)
+{
+	printf("start to config phy: p0=3200mts, p1=667mts with 1D2D training\n");
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20110, 0x02); /* MapCAB0toDFI */
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20111, 0x03); /* MapCAB1toDFI */
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20112, 0x04); /* MapCAB2toDFI */
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20113, 0x05); /* MapCAB3toDFI */
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20114, 0x00); /* MapCAB4toDFI */
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20115, 0x01); /* MapCAB5toDFI */
+
+	/* Initialize PHY Configuration */
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1005f, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1015f, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1105f, 0x1ff);
@@ -79,6 +103,7 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1215f, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1305f, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1315f, 0x1ff);
+
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11005f, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11015f, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11105f, 0x1ff);
@@ -87,6 +112,7 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11215f, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11305f, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11315f, 0x1ff);
+
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21005f, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21015f, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21105f, 0x1ff);
@@ -95,6 +121,7 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21215f, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21305f, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21315f, 0x1ff);
+
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x55, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1055, 0x1ff);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2055, 0x1ff);
@@ -109,20 +136,23 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200c5, 0x7);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200c5, 0x7);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002e, 0x2);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002e, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002e, 0x1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002e, 0x2);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90204, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x190204, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x290204, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20024, 0xab);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120024, 0xab);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220024, 0xab);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
+
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20024, 0xe3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120024, 0xa3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220024, 0xa3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20056, 0x3);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120056, 0xa);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220056, 0xa);
+
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1004d, 0xe00);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1014d, 0xe00);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1104d, 0xe00);
@@ -147,48 +177,53 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21214d, 0xe00);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21304d, 0xe00);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21314d, 0xe00);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10049, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10149, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11049, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11149, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12049, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12149, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13049, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13149, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110049, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110149, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111049, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111149, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112049, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112149, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113049, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113149, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210049, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210149, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211049, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211149, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212049, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212149, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213049, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213149, 0xe38);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x43, 0x21);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1043, 0x21);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2043, 0x21);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3043, 0x21);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4043, 0x21);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5043, 0x21);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6043, 0x21);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7043, 0x21);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8043, 0x21);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9043, 0x21);
+
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10049, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10149, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11049, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11149, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12049, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12149, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13049, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13149, 0xfbe);
+
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110049, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110149, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111049, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111149, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112049, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112149, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113049, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113149, 0xfbe);
+
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210049, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210149, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211049, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211149, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212049, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212149, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213049, 0xfbe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213149, 0xfbe);
+
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x43, 0x63);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1043, 0x63);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2043, 0x63);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3043, 0x63);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4043, 0x63);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5043, 0x63);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6043, 0x63);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7043, 0x63);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8043, 0x63);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9043, 0x63);
+
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20018, 0x3);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20075, 0x4);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20050, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20008, 0x320);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120008, 0x64);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120008, 0xa7);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220008, 0x19);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x9);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200b2, 0x19c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200b2, 0x104);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10043, 0x5a1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10143, 0x5a1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11043, 0x5a1);
@@ -197,7 +232,7 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12143, 0x5a1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13043, 0x5a1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13143, 0x5a1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200b2, 0x19c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200b2, 0x104);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110043, 0x5a1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110143, 0x5a1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111043, 0x5a1);
@@ -206,7 +241,7 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112143, 0x5a1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113043, 0x5a1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113143, 0x5a1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200b2, 0x19c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200b2, 0x104);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210043, 0x5a1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210143, 0x5a1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211043, 0x5a1);
@@ -221,191 +256,29 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20019, 0x1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120019, 0x1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220019, 0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f0, 0x660);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f0, 0x600);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f1, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f2, 0x4444);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f3, 0x8888);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f4, 0x5555);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f4, 0x5655);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f5, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f6, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f7, 0xf000);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000b, 0x65);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000c, 0xc9);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000d, 0x7d1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000e, 0x2c);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000b, 0xd);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000c, 0x1a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000d, 0xfb);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000e, 0x10);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000b, 0x4);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000c, 0x7);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000d, 0x3f);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000e, 0x10);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20025, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002d, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002d, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002d, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20060, 0x2);
+
+	/* Load the 1D IMEM image */
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
-	/* load the 1D training image */
 	ddr_load_train_code(FW_1D_IMAGE);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
 
-	/* set the PHY input clock to the desired frequency for pstate 2 */
-	dwc_ddrphy_phyinit_userCustom_E_setDfiClk(2);
+	/* Set the PHY input clocks for pstate 0 */
+	dwc_ddrphy_phyinit_userCustom_E_setDfiClk (0);
+	/* Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x102);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x64);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x4);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x4);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x400);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x400);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
-extern void wait_ddrphy_training_complete(void);
-	wait_ddrphy_training_complete();
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
-
-	/* set the PHY input clock to the desired frequency for pstate 1 */
-	dwc_ddrphy_phyinit_userCustom_E_setDfiClk(1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x101);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x190);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x4);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x4);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x400);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x400);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x500);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
-extern void wait_ddrphy_training_complete(void);
-	wait_ddrphy_training_complete();
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
-
-	/* set the PHY input clock to the desired frequency for pstate 0 */
-	dwc_ddrphy_phyinit_userCustom_E_setDfiClk(0);
+	printf("config to do 3200 1d training.\n");
 
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
@@ -413,11 +286,194 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, 0x2828);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, 0x14);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, ((LPDDR4_PHY_RON<<8) | LPDDR4_PHY_RTT));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, LPDDR4_PHY_VREF_VALUE);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x131f);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, LPDDR4_HDT_CTL_3200_1D);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x3));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, LPDDR4_MR22_RANK0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, (((LPDDR4_RON) << 3) | 0x3));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, LPDDR4_MR22_RANK1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, (LPDDR4_MR22_RANK0 << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403f, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54040, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54041, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54042, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54043, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54044, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+
+	/* wait for train complete */
+	wait_ddrphy_training_complete();
+
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+	/* Load the 2D IMEM image */
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	ddr_load_train_code(FW_2D_IMAGE);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+	/* 3200 mts 2D training */
+	printf("config to do 3200 2d training.\n");
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, LPDDR4_PHY_VREF_VALUE);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x61);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, LPDDR4_HDT_CTL_2D);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, LPDDR4_2D_WEIGHT);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x3));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, LPDDR4_MR22_RANK0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, (((LPDDR4_RON) << 3) | 0x3));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, LPDDR4_MR22_RANK1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, (LPDDR4_MR22_RANK0 << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403f, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54040, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54041, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54042, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54043, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54044, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+
+	/* wait for train complete */
+	wait_ddrphy_training_complete();
+
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+	/* Step (E) Set the PHY input clocks for pstate 1 */
+	dwc_ddrphy_phyinit_userCustom_E_setDfiClk (1);
+
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	ddr_load_train_code(FW_1D_IMAGE);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+	printf("pstate=1: set dfi clk done done\n");
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0x29c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, LPDDR4_PHY_VREF_VALUE);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x121f);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0xc8);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
@@ -433,18 +489,17 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, 0x31);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, 0x4d46);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, 0x4d08);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x5);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, 0x31);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, 0x4d46);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, 0x4d08);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x914);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x1));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x6);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x914);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, (((LPDDR4_RON) << 3) | 0x1));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08));
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, LPDDR4_MR22_RANK1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
@@ -458,114 +513,40 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, 0x312d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, 0x4600);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, 0x84d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, 0x4d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x500);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, 0x312d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, 0x4600);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, 0x84d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0x1400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x600);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0x1400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8));
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403f, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54040, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54041, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54042, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54043, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
-extern void wait_ddrphy_training_complete(void);
-wait_ddrphy_training_complete();
+
+	/* wait for train complete */
+	wait_ddrphy_training_complete();
+
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
-	/* load the 2D training image */
-	ddr_load_train_code(FW_2D_IMAGE);
-
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0);
-
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x61);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x100);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x1f7f);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x084d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x084d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x500);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1);
-	/* Execute the Training Firmware */
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x9);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x0);
-	/* wait for 2D training complete */
-	extern void wait_ddrphy_training_complete(void);
-	wait_ddrphy_training_complete();
-
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1);
 
 	/* (I) Load PHY Init Engine Image */
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0);
+	printf("Load 201711 PIE\n");
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90000, 0x10);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90001, 0x400);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90002, 0x10e);
@@ -587,7 +568,7 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90035, 0x2);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90036, 0x10);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90037, 0x139);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90038, 0xf);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90038, 0xb);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90039, 0x7c0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003a, 0x139);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003b, 0x44);
@@ -695,14 +676,17 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a1, 0x5);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a2, 0x7c0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a3, 0x109);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a4, 0x10);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a5, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a4, 0xd);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a5, 0x7c0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a6, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a7, 0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a8, 0x7c0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a9, 0x109);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40000, 0x811);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40020, 0x880);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40040, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40060, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40001, 0x4016);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40001, 0x4008);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40021, 0x83);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40041, 0x4f);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40061, 0x0);
@@ -746,7 +730,7 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002b, 0x15);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004b, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006b, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000c, 0x4004);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000c, 0x4028);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002c, 0x80);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004c, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006c, 0x0);
@@ -806,234 +790,237 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4003a, 0x880);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4005a, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4007a, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a7, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a8, 0x790);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a9, 0x11a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900aa, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ab, 0x7aa);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ac, 0x2a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ad, 0x10);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ae, 0x7b2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900aa, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ab, 0x790);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ac, 0x11a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ad, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ae, 0x7aa);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900af, 0x2a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b0, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b1, 0x7c8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b2, 0x109);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b3, 0x10);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b4, 0x2a8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b5, 0x129);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b6, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b7, 0x370);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b8, 0x129);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b9, 0xa);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ba, 0x3c8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bb, 0x1a9);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bc, 0xc);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bd, 0x408);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900be, 0x199);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bf, 0x14);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c0, 0x790);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c1, 0x11a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c2, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c3, 0x4);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c4, 0x18);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c5, 0xc);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c6, 0x408);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c7, 0x199);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b0, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b1, 0x7b2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b2, 0x2a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b3, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b4, 0x7c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b5, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b6, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b7, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b8, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b9, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ba, 0x2a8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bb, 0x129);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bc, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bd, 0x370);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900be, 0x129);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bf, 0xa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c0, 0x3c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c1, 0x1a9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c2, 0xc);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c3, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c4, 0x199);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c5, 0x14);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c6, 0x790);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c7, 0x11a);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c8, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c9, 0x8568);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ca, 0x108);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cb, 0x18);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cc, 0x790);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cd, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c9, 0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ca, 0x18);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cb, 0xe);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cc, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cd, 0x199);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ce, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cf, 0x1d8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d0, 0x169);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d1, 0x10);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d2, 0x8558);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d3, 0x168);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d4, 0x70);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d5, 0x788);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d6, 0x16a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d7, 0x1ff8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d8, 0x85a8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d9, 0x1e8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900da, 0x50);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900db, 0x798);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cf, 0x8568);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d0, 0x108);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d1, 0x18);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d2, 0x790);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d3, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d4, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d5, 0x1d8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d6, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d7, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d8, 0x8558);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d9, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900da, 0x70);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900db, 0x788);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dc, 0x16a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dd, 0x60);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900de, 0x7a0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900df, 0x16a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e0, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e1, 0x8310);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e2, 0x168);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e3, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e4, 0xa310);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e5, 0x168);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e6, 0xa);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e7, 0x408);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e8, 0x169);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e9, 0x6e);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ea, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900eb, 0x68);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ec, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dd, 0x1ff8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900de, 0x85a8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900df, 0x1e8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e0, 0x50);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e1, 0x798);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e2, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e3, 0x60);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e4, 0x7a0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e5, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e6, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e7, 0x8310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e8, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e9, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ea, 0xa310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900eb, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ec, 0xa);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ed, 0x408);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ee, 0x169);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ef, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f0, 0x8310);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f1, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ef, 0x6e);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f0, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f1, 0x68);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f2, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f3, 0xa310);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f4, 0x168);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f5, 0x1ff8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f6, 0x85a8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f7, 0x1e8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f8, 0x68);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f9, 0x798);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fa, 0x16a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fb, 0x78);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fc, 0x7a0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fd, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f3, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f4, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f5, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f6, 0x8310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f7, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f8, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f9, 0xa310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fa, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fb, 0x1ff8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fc, 0x85a8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fd, 0x1e8);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fe, 0x68);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ff, 0x790);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ff, 0x798);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90100, 0x16a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90101, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90102, 0x8b10);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90103, 0x168);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90104, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90105, 0xab10);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90106, 0x168);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90107, 0xa);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90108, 0x408);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90109, 0x169);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010a, 0x58);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010b, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010c, 0x68);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90101, 0x78);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90102, 0x7a0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90103, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90104, 0x68);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90105, 0x790);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90106, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90107, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90108, 0x8b10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90109, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010a, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010b, 0xab10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010c, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010d, 0xa);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010e, 0x408);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010f, 0x169);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90110, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90111, 0x8b10);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90112, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90110, 0x58);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90111, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90112, 0x68);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90113, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90114, 0xab10);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90115, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90114, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90115, 0x169);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90116, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90117, 0x1d8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90118, 0x169);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90119, 0x80);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011a, 0x790);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011b, 0x16a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011c, 0x18);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011d, 0x7aa);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011e, 0x6a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011f, 0xa);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90120, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90121, 0x1e9);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90122, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90123, 0x8080);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90124, 0x108);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90125, 0xf);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90126, 0x408);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90127, 0x169);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90128, 0xc);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90129, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012a, 0x68);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012b, 0x9);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012c, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012d, 0x1a9);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012e, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012f, 0x408);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90130, 0x169);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90131, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90132, 0x8080);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90133, 0x108);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90134, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90135, 0x7aa);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90136, 0x6a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90117, 0x8b10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90118, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90119, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011a, 0xab10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011b, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011c, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011d, 0x1d8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011e, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011f, 0x80);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90120, 0x790);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90121, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90122, 0x18);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90123, 0x7aa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90124, 0x6a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90125, 0xa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90126, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90127, 0x1e9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90128, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90129, 0x8080);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012a, 0x108);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012b, 0xf);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012c, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012d, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012e, 0xc);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012f, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90130, 0x68);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90131, 0x9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90132, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90133, 0x1a9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90134, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90135, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90136, 0x169);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90137, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90138, 0x8568);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90138, 0x8080);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90139, 0x108);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013a, 0xb7);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013b, 0x790);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013c, 0x16a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013d, 0x1d);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013e, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013f, 0x68);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90140, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90141, 0x8558);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90142, 0x168);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90143, 0xf);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90144, 0x408);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90145, 0x169);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90146, 0xc);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90147, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90148, 0x68);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90149, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013a, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013b, 0x7aa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013c, 0x6a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013e, 0x8568);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013f, 0x108);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90140, 0xb7);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90141, 0x790);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90142, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90143, 0x1f);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90144, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90145, 0x68);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90146, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90147, 0x8558);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90148, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90149, 0xf);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014a, 0x408);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014b, 0x169);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014c, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014d, 0x8558);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014e, 0x168);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014f, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90150, 0x3c8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90151, 0x1a9);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90152, 0x3);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90153, 0x370);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90154, 0x129);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90155, 0x20);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90156, 0x2aa);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90157, 0x9);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90158, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90159, 0x400);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015a, 0x10e);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015b, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015c, 0xe8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015d, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014c, 0xc);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014e, 0x68);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014f, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90150, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90151, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90152, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90153, 0x8558);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90154, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90155, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90156, 0x3c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90157, 0x1a9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90158, 0x3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90159, 0x370);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015a, 0x129);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015b, 0x20);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015c, 0x2aa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015d, 0x9);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015e, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015f, 0x8140);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90160, 0x10c);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90161, 0x10);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90162, 0x8138);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90163, 0x10c);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90164, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90165, 0x7c8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90166, 0x101);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90167, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90168, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90169, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015f, 0x400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90160, 0x10e);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90161, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90162, 0xe8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90163, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90164, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90165, 0x8140);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90166, 0x10c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90167, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90168, 0x8138);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90169, 0x10c);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016a, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016b, 0x448);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016c, 0x109);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016d, 0xf);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016e, 0x7c0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016f, 0x109);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90170, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90171, 0xe8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016b, 0x7c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016c, 0x101);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016d, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016f, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90170, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90171, 0x448);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90172, 0x109);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90173, 0x47);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90174, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90173, 0xf);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90174, 0x7c0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90175, 0x109);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90176, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90177, 0x618);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90176, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90177, 0xe8);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90178, 0x109);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90179, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017a, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90179, 0x47);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017a, 0x630);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017b, 0x109);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017c, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017d, 0x7c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017c, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017d, 0x618);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017e, 0x109);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017f, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90180, 0x8140);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90181, 0x10c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90180, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90181, 0x109);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90182, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90183, 0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90184, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90183, 0x7c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90184, 0x109);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90185, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90186, 0x4);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90187, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90188, 0x8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90189, 0x7c8);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018a, 0x101);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90186, 0x8140);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90187, 0x10c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90188, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90189, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018a, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018b, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018c, 0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018d, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018e, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018f, 0x7c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90190, 0x101);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90006, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90007, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90008, 0x8);
@@ -1042,8 +1029,8 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000b, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd00e7, 0x400);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90017, 0x0);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9001f, 0x2a);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90026, 0x6a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9001f, 0x2b);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90026, 0x6c);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d0, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d1, 0x101);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d2, 0x105);
@@ -1053,6 +1040,18 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d6, 0x20a);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d7, 0x20b);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000b, 0x64);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000c, 0xc8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000d, 0x7d0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000e, 0x2c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000b, 0x14);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000c, 0x29);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000d, 0x1a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000e, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000b, 0x3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000c, 0x6);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000d, 0x3e);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000e, 0x10);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000c, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000d, 0x173);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000e, 0x60);
@@ -1069,6 +1068,18 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40083, 0x12);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40084, 0xe0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40085, 0x12);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140080, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140081, 0x12);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140082, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140083, 0x12);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140084, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140085, 0x12);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240080, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240081, 0x12);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240082, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240083, 0x12);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240084, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240085, 0x12);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400fd, 0xf);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10011, 0x1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10012, 0x1);
@@ -1126,23 +1137,8 @@
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x136b4, 0x1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x137b4, 0x1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x138b4, 0x1);
-	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20089, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x19);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xc0080, 0x2);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x000d0000, 0x00000000);
-	tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010, 0x0000006a);
-	tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d, 0x00000001);
-	/*
-	 * CalBusy.0 =1, indicates the calibrator is actively calibrating.
-	 * Wait Calibrating done.
-	 */
-	tmp_t = 1;
-	while(tmp_t) {
-		tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20097);
-		tmp_t = tmp & 0x01;
-	}
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0);
 }
diff --git a/board/freescale/imx8mq_evk/ddr/lpddr4_dvfs.h b/board/freescale/imx8mq_evk/ddr/lpddr4_dvfs.h
new file mode 100755
index 0000000..0ee2ea9
--- /dev/null
+++ b/board/freescale/imx8mq_evk/ddr/lpddr4_dvfs.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LPDDR4_DVFS_H__
+#define  __LPDDR4_DVFS_H__
+#include <asm/arch/ddr_memory_map.h>
+
+#define DFILP_SPT
+
+#define ANAMIX_PLL_BASE_ADDR	0x30360000
+#define HW_DRAM_PLL_CFG0_ADDR	(ANAMIX_PLL_BASE_ADDR + 0x60)
+#define HW_DRAM_PLL_CFG1_ADDR	(ANAMIX_PLL_BASE_ADDR + 0x64)
+#define HW_DRAM_PLL_CFG2_ADDR	(ANAMIX_PLL_BASE_ADDR + 0x68)
+
+#define LPDDR4_HDT_CTL_2D	0xC8  /* stage completion */
+#define LPDDR4_HDT_CTL_3200_1D	0xC8  /* stage completion */
+#define LPDDR4_HDT_CTL_400_1D	0xC8  /* stage completion */
+#define LPDDR4_HDT_CTL_100_1D	0xC8  /* stage completion */
+
+/* 2D share & weight */
+#define LPDDR4_2D_WEIGHT	0x1f7f
+#define LPDDR4_2D_SHARE		1
+#define LPDDR4_CATRAIN_3200_1d	0
+#define LPDDR4_CATRAIN_400	0
+#define LPDDR4_CATRAIN_100	0
+#define LPDDR4_CATRAIN_3200_2d	0
+
+#define WR_POST_EXT_3200  /* recommened to define */
+
+/* lpddr4 phy training config */
+/* for LPDDR4 Rtt */
+#define LPDDR4_RTT40	6
+#define LPDDR4_RTT48	5
+#define LPDDR4_RTT60	4
+#define LPDDR4_RTT80	3
+#define LPDDR4_RTT120	2
+#define LPDDR4_RTT240	1
+#define LPDDR4_RTT_DIS	0
+
+/* for LPDDR4 Ron */
+#define LPDDR4_RON34	7
+#define LPDDR4_RON40	6
+#define LPDDR4_RON48	5
+#define LPDDR4_RON60	4
+#define LPDDR4_RON80	3
+
+#define LPDDR4_PHY_ADDR_RON60	0x1
+#define LPDDR4_PHY_ADDR_RON40   0x3
+#define LPDDR4_PHY_ADDR_RON30   0x7
+#define LPDDR4_PHY_ADDR_RON24   0xf
+#define LPDDR4_PHY_ADDR_RON20   0x1f
+
+/* for read channel */
+#define LPDDR4_RON		LPDDR4_RON40 /* MR3[5:3] */
+#define LPDDR4_PHY_RTT		30
+#define LPDDR4_PHY_VREF_VALUE 	17
+
+/* for write channel */
+#define LPDDR4_PHY_RON		30
+#define LPDDR4_PHY_ADDR_RON	LPDDR4_PHY_ADDR_RON40
+#define LPDDR4_RTT_DQ		LPDDR4_RTT40 /* MR11[2:0] */
+#define LPDDR4_RTT_CA		LPDDR4_RTT40 /* MR11[6:4] */
+#define LPDDR4_RTT_CA_BANK0	LPDDR4_RTT40 /* MR11[6:4] */
+#define LPDDR4_RTT_CA_BANK1	LPDDR4_RTT40 /* LPDDR4_RTT_DIS//MR11[6:4] */
+#define LPDDR4_VREF_VALUE_CA		((1<<6)|(0xd)) /*((0<<6)|(0xe)) MR12 */
+#define LPDDR4_VREF_VALUE_DQ_RANK0	((1<<6)|(0xd)) /* MR14 */
+#define LPDDR4_VREF_VALUE_DQ_RANK1	((1<<6)|(0xd)) /* MR14 */
+#define LPDDR4_MR22_RANK0           	((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
+#define LPDDR4_MR22_RANK1		((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
+#define LPDDR4_MR3_PU_CAL		1 /* MR3[0] */
+
+#define LPDDR4_2D_WEIGHT 0x1f7f
+#define LPDDR4_2D_SHARE 1
+
+#endif  /*__LPDDR4_DVFS_H__ */
diff --git a/board/freescale/imx8mq_evk/imx8m_evk.c b/board/freescale/imx8mq_evk/imx8m_evk.c
index 618f77c..26191c4 100644
--- a/board/freescale/imx8mq_evk/imx8m_evk.c
+++ b/board/freescale/imx8mq_evk/imx8m_evk.c
@@ -1,6 +1,6 @@
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -20,9 +20,13 @@
 #include <asm/imx-common/gpio.h>
 #include <asm/imx-common/mxc_i2c.h>
 #include <asm/arch/clock.h>
+#include <asm/imx-common/video.h>
+#include <asm/arch/video_common.h>
 #include <spl.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
+#include <dm.h>
+#include "../common/tcpc.h"
 #include "../common/pfuze.h"
 #include <usb.h>
 #include <dwc3-uboot.h>
@@ -112,7 +116,8 @@
 
 static void setup_iomux_fec(void)
 {
-	imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, ARRAY_SIZE(fec1_rst_pads));
+	imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
+					 ARRAY_SIZE(fec1_rst_pads));
 
 	gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
 	gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
@@ -214,9 +219,8 @@
 
 int board_usb_cleanup(int index, enum usb_init_type init)
 {
-	if (index == 0 && init == USB_INIT_DEVICE) {
+	if (index == 0 && init == USB_INIT_DEVICE)
 		dwc3_uboot_exit(index);
-	}
 
 	imx8m_usb_power(index, false);
 
@@ -224,6 +228,32 @@
 }
 #endif
 
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port;
+struct tcpc_port_config port_config = {
+	.i2c_bus = 0,
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 20000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 15000,
+	.op_snk_mv = 9000,
+};
+
+static int setup_typec(void)
+{
+	int ret;
+
+	ret = tcpc_init(&port, port_config, NULL);
+	if (ret) {
+		printf("%s: tcpc init failed, err=%d\n",
+		       __func__, ret);
+	}
+
+	return ret;
+}
+#endif
+
 int board_init(void)
 {
 	board_qspi_init();
@@ -232,6 +262,9 @@
 	setup_fec();
 #endif
 
+#ifdef CONFIG_USB_TCPC
+	setup_typec();
+#endif
 	return 0;
 }
 
@@ -262,3 +295,50 @@
 }
 #endif /*CONFIG_ANDROID_RECOVERY*/
 #endif /*CONFIG_FSL_FASTBOOT*/
+
+#if defined(CONFIG_VIDEO_IMXDCSS)
+
+struct display_info_t const displays[] = {{
+	.bus	= 0, /* Unused */
+	.addr	= 0, /* Unused */
+	.pixfmt	= GDF_32BIT_X888RGB,
+	.detect	= NULL,
+	.enable	= NULL,
+#ifndef CONFIG_VIDEO_IMXDCSS_1080P
+	.mode	= {
+		.name           = "HDMI", /* 720P60 */
+		.refresh        = 60,
+		.xres           = 1280,
+		.yres           = 720,
+		.pixclock       = 13468, /* 74250  kHz */
+		.left_margin    = 110,
+		.right_margin   = 220,
+		.upper_margin   = 5,
+		.lower_margin   = 20,
+		.hsync_len      = 40,
+		.vsync_len      = 5,
+		.sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		.vmode          = FB_VMODE_NONINTERLACED
+	}
+#else
+	.mode	= {
+		.name           = "HDMI", /* 1080P60 */
+		.refresh        = 60,
+		.xres           = 1920,
+		.yres           = 1080,
+		.pixclock       = 6734, /* 148500 kHz */
+		.left_margin    = 148,
+		.right_margin   = 88,
+		.upper_margin   = 36,
+		.lower_margin   = 4,
+		.hsync_len      = 44,
+		.vsync_len      = 5,
+		.sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		.vmode          = FB_VMODE_NONINTERLACED
+	}
+#endif
+} };
+size_t display_count = ARRAY_SIZE(displays);
+
+#endif /* CONFIG_VIDEO_IMXDCSS */
+
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index fe2b88d..d51d5d3 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -175,6 +175,12 @@
 	if (ret < 0)
 		return ret;
 
+	/* set SW3A standby mode to off */
+	pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
+	reg &= ~0xf;
+	reg |= APS_OFF;
+	pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
+
 	return 0;
 }
 #endif
diff --git a/board/freescale/imx8mq_phanbell/Kconfig b/board/freescale/imx8mq_phanbell/Kconfig
new file mode 100644
index 0000000..6ead82d
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MQ_PHANBELL
+
+config SYS_BOARD
+	default "imx8mq_phanbell"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_phanbell"
+
+endif
diff --git a/board/freescale/imx8mq_phanbell/Makefile b/board/freescale/imx8mq_phanbell/Makefile
new file mode 100644
index 0000000..fc4b9f8
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2016 Freescale Semiconductor
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8m_phanbell.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o
+endif
diff --git a/board/freescale/imx8mq_phanbell/ddr/ddr.h b/board/freescale/imx8mq_phanbell/ddr/ddr.h
new file mode 100644
index 0000000..9acb29c
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/ddr/ddr.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+enum fw_type {
+	FW_1D_IMAGE,
+	FW_2D_IMAGE,
+};
+
+void ddr_init(void);
+void ddr_load_train_code(enum fw_type type);
+void lpddr4_800M_cfg_phy(void);
+
+static inline void reg32_write(unsigned long addr, u32 val)
+{
+	writel(val, addr);
+}
+
+static inline uint32_t reg32_read(unsigned long addr)
+{
+	return readl(addr);
+}
+
+static void inline dwc_ddrphy_apb_wr(unsigned long addr, u32 val)
+{
+    writel(val, addr);
+}
+
+static inline void reg32setbit(unsigned long addr, u32 bit)
+{
+	setbits_le32(addr, (1 << bit));
+}
diff --git a/board/freescale/imx8mq_phanbell/ddr/ddr_init.c b/board/freescale/imx8mq_phanbell/ddr/ddr_init.c
new file mode 100644
index 0000000..80971ec
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/ddr/ddr_init.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr_memory_map.h>
+#include <asm/arch/clock.h>
+#include "ddr.h"
+
+#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
+#define ddr_printf(args...) printf(args)
+#else
+#define ddr_printf(args...)
+#endif
+
+#include "wait_ddrphy_training_complete.c"
+#ifndef SRC_DDRC_RCR_ADDR
+#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
+#endif
+#ifndef DDR_CSD1_BASE_ADDR
+#define DDR_CSD1_BASE_ADDR 0x40000000
+#endif
+#define SILICON_TRAIN
+
+volatile unsigned int tmp, tmp_t, i;
+void lpddr4_800MHz_cfg_umctl2(void)
+{
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000304, 0x00000001);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000030, 0x00000001);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000000, 0x83080020);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000064, 0x006180e0);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000d0, 0xc003061B);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000d4, 0x009D0000);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000d8, 0x0000fe05);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000dc, 0x00d4002d);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000e0, 0x00310008);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000e4, 0x00040009);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000e8, 0x0046004d);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000ec, 0x0005004d);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000f4, 0x00000979);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000100, 0x1a203522);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000104, 0x00060630);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000108, 0x070e1214);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000010c, 0x00b0c006);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000110, 0x0f04080f);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000114, 0x0d0d0c0c);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000118, 0x01010007);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000011c, 0x0000060a);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000120, 0x01010101);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000124, 0x40000008);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000128, 0x00050d01);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000012c, 0x01010008);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000130, 0x00020000);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000134, 0x18100002);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000138, 0x00000dc2);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000013c, 0x80000000);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000144, 0x00a00050);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000180, 0x53200018);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000184, 0x02800070);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000188, 0x00000000);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000190, 0x0397820a);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00002190, 0x0397820a);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00003190, 0x0397820a);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000194, 0x00020103);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001a0, 0xe0400018);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001a4, 0x00df00e4);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001a8, 0x00000000);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001b0, 0x00000011);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001b4, 0x0000170a);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001c0, 0x00000001);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001c4, 0x00000000);
+	/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+	dwc_ddrphy_apb_wr(DDRC_ADDRMAP0(0), 0x00000015);
+	dwc_ddrphy_apb_wr(DDRC_ADDRMAP4(0), 0x00001F1F);
+	/* bank interleave */
+	dwc_ddrphy_apb_wr(DDRC_ADDRMAP1(0), 0x00080808);
+	dwc_ddrphy_apb_wr(DDRC_ADDRMAP5(0), 0x07070707);
+	dwc_ddrphy_apb_wr(DDRC_ADDRMAP6(0), 0x08080707);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000240, 0x020f0c54);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000244, 0x00000000);
+	dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000490, 0x00000001);
+
+	/* performance setting */
+	dwc_ddrphy_apb_wr(DDRC_ODTCFG(0), 0x0b060908);
+	dwc_ddrphy_apb_wr(DDRC_ODTMAP(0), 0x00000000);
+	dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505);
+	dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c);
+	dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b);
+	dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x00000009);
+	dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x02005574);
+	dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016);
+	dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000);
+	dwc_ddrphy_apb_wr(DDRC_DBGCMD(0), 0x00000000);
+	dwc_ddrphy_apb_wr(DDRC_SWCTL(0), 0x00000001);
+	dwc_ddrphy_apb_wr(DDRC_POISONCFG(0), 0x00000011);
+	dwc_ddrphy_apb_wr(DDRC_PCCFG(0), 0x00000111);
+	dwc_ddrphy_apb_wr(DDRC_PCFGR_0(0), 0x000010f3);
+	dwc_ddrphy_apb_wr(DDRC_PCFGW_0(0), 0x000072ff);
+	dwc_ddrphy_apb_wr(DDRC_PCTRL_0(0), 0x00000001);
+	dwc_ddrphy_apb_wr(DDRC_PCFGQOS0_0(0), 0x01110d00);
+	dwc_ddrphy_apb_wr(DDRC_PCFGQOS1_0(0), 0x00620790);
+	dwc_ddrphy_apb_wr(DDRC_PCFGWQOS0_0(0), 0x00100001);
+	dwc_ddrphy_apb_wr(DDRC_PCFGWQOS1_0(0), 0x0000041f);
+	dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEEN(0), 0x00000202);
+	dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5);
+	dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHCTL0(0), 0x00618040);
+	dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHTMG(0), 0x00610090);
+}
+
+void lpddr4_100MHz_cfg_umctl2(void)
+{
+	reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c);
+	reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x00030410);
+	reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x0305090c);
+	reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x00505006);
+	reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x05040305);
+	reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504);
+	reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0a060004);
+	reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x0000090e);
+	reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x00000032);
+	reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x00000000);
+	reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x0036001b);
+	reg32_write(DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1);
+	reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0020d040);
+	reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03818200);
+	reg32_write(DDRC_FREQ1_ODTCFG(0), 0x0a1a096c);
+	reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000000);
+	reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x00038014);
+	reg32_write(DDRC_FREQ1_INIT3(0), 0x00840000);
+	reg32_write(DDRC_FREQ1_INIT6(0), 0x0000004d);
+	reg32_write(DDRC_FREQ1_INIT7(0), 0x0000004d);
+	reg32_write(DDRC_FREQ1_INIT4(0), 0x00310000);
+}
+
+void lpddr4_25MHz_cfg_umctl2(void)
+{
+	reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c);
+	reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x00030410);
+	reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x0305090c);
+	reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x00505006);
+	reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x05040305);
+	reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504);
+	reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x0a060004);
+	reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x0000090e);
+	reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x00000032);
+	reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000);
+	reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x0036001b);
+	reg32_write(DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1);
+	reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x0020d040);
+	reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03818200);
+	reg32_write(DDRC_FREQ2_ODTCFG(0), 0x0a1a096c);
+	reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000000);
+	reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x0003800c);
+	reg32_write(DDRC_FREQ2_INIT3(0), 0x00840000);
+	reg32_write(DDRC_FREQ2_INIT6(0), 0x0000004d);
+	reg32_write(DDRC_FREQ2_INIT7(0), 0x0000004d);
+	reg32_write(DDRC_FREQ2_INIT4(0), 0x00310000);
+}
+
+void ddr_init(void)
+{
+	/* change the clock source of dram_apb_clk_root  */
+	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
+	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16));
+
+	/* disable the clock gating */
+	reg32_write(0x303A00EC,0x0000ffff);
+	reg32setbit(0x303A00F8,5);
+	reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
+
+	dram_pll_init(SSCG_PLL_OUT_800M);
+
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
+
+	/* Configure uMCTL2's registers */
+	lpddr4_800MHz_cfg_umctl2();
+
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
+
+	reg32_write(DDRC_DBG1(0), 0x00000000);
+	tmp = reg32_read(DDRC_PWRCTL(0));
+	reg32_write(DDRC_PWRCTL(0), 0x000000a8);
+	/* reg32_write(DDRC_PWRCTL(0), 0x0000018a); */
+	reg32_write(DDRC_SWCTL(0), 0x00000000);
+	reg32_write(DDRC_DDR_SS_GPR0, 0x01);
+	reg32_write(DDRC_DFIMISC(0), 0x00000010);
+
+	/* Configure LPDDR4 PHY's registers */
+	lpddr4_800M_cfg_phy();
+
+	reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+	reg32_write(DDRC_SWCTL(0), 0x0000);
+	/*
+	 * ------------------- 9 -------------------
+	 * Set DFIMISC.dfi_init_start to 1
+	 *  -----------------------------------------
+	 */
+	reg32_write(DDRC_DFIMISC(0), 0x00000030);
+	reg32_write(DDRC_SWCTL(0), 0x0001);
+
+	/* wait DFISTAT.dfi_init_complete to 1 */
+	tmp_t = 0;
+	while(tmp_t==0){
+		tmp  = reg32_read(DDRC_DFISTAT(0));
+		tmp_t = tmp & 0x01;
+		tmp  = reg32_read(DDRC_MRSTAT(0));
+	}
+
+	reg32_write(DDRC_SWCTL(0), 0x0000);
+
+	/* clear DFIMISC.dfi_init_complete_en */
+	reg32_write(DDRC_DFIMISC(0), 0x00000010);
+	reg32_write(DDRC_DFIMISC(0), 0x00000011);
+	reg32_write(DDRC_PWRCTL(0), 0x00000088);
+
+	tmp = reg32_read(DDRC_CRCPARSTAT(0));
+	/*
+	 * set SWCTL.sw_done to enable quasi-dynamic register
+	 * programming outside reset.
+	 */
+	reg32_write(DDRC_SWCTL(0), 0x00000001);
+
+	/* wait SWSTAT.sw_done_ack to 1 */
+	while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
+		;
+
+	/* wait STAT.operating_mode([1:0] for ddr3) to normal state */
+	while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
+		;
+
+	reg32_write(DDRC_PWRCTL(0), 0x00000088);
+	/* reg32_write(DDRC_PWRCTL(0), 0x018a); */
+	tmp = reg32_read(DDRC_CRCPARSTAT(0));
+
+	/* enable port 0 */
+	reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+	tmp = reg32_read(DDRC_CRCPARSTAT(0));
+	reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+
+	reg32_write(DDRC_SWCTL(0), 0x0);
+	lpddr4_100MHz_cfg_umctl2();
+	lpddr4_25MHz_cfg_umctl2();
+	reg32_write(DDRC_SWCTL(0), 0x1);
+
+	/* wait SWSTAT.sw_done_ack to 1 */
+	while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
+		;
+
+	reg32_write(DDRC_SWCTL(0), 0x0);
+
+}
diff --git a/board/freescale/imx8mq_phanbell/ddr/ddrphy_train.c b/board/freescale/imx8mq_phanbell/ddr/ddrphy_train.c
new file mode 100644
index 0000000..c4e4378
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/ddr/ddrphy_train.c
@@ -0,0 +1,1148 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr_memory_map.h>
+#include "ddr.h"
+
+void ddr_pll_bypass_100mts(void) {
+	/* change the clock source of dram_alt_clk_root to source 2 --100MHz */
+	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0),(0x7<<24)|(0x7<<16));
+	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0),(0x2<<24));
+
+	/* change the clock source of dram_apb_clk_root to source 2 --40MHz */
+	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
+	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x2<<24)|(0x1<<16));
+
+	/* disable the clock gating */
+	reg32_write(0x303A00EC,0x0000ffff); /* PGC_CPU_MAPPING */
+	reg32setbit(0x303A00F8,5);          /* PU_PGC_SW_PUP_REQ */
+
+	/* configure pll bypass mode */
+	reg32_write(0x30389804, 1<<24);
+
+	printf("PLL bypass to 100MTS setting done \n");
+}
+
+void ddr_pll_bypass_400mts(void) {
+    /* change the clock source of dram_alt_clk_root to source 2 --400MHz */
+    reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0),(0x7<<24)|(0x7<<16));
+    reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0),(0x5<<24));
+
+    /* change the clock source of dram_apb_clk_root to source 2 --40MHz/2 */
+    reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
+    reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x2<<24)|(0x1<<16));
+
+    /* disable the clock gating */
+    reg32_write(0x303A00EC,0x0000ffff); /* PGC_CPU_MAPPING */
+    reg32setbit(0x303A00F8,5);          /* PU_PGC_SW_PUP_REQ */
+
+    /* configure pll bypass mode */
+    reg32_write(0x30389804, 1<<24);
+
+    printf("PLL bypass to 400MTS setting done \n");
+}
+
+
+void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate)
+{
+	if (pstate == 2)
+		ddr_pll_bypass_100mts();
+	else if (pstate == 1)
+		ddr_pll_bypass_400mts();
+	else {
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16));
+		reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4 << 24) | (0x3 << 16));
+		reg32_write(0x30389808, 1 << 24);
+	}
+}
+
+void lpddr4_800M_cfg_phy(void) {
+	unsigned int tmp, tmp_t;
+
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20110, 0x02);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20111, 0x03);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20112, 0x04);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20113, 0x05);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20114, 0x00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20115, 0x01);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1005f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1015f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1105f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1115f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1205f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1215f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1305f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1315f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11005f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11015f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11105f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11115f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11205f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11215f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11305f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11315f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21005f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21015f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21105f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21115f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21205f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21215f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21305f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21315f, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x55, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1055, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2055, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3055, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4055, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5055, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6055, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7055, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8055, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9055, 0x1ff);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200c5, 0x19);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200c5, 0x7);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200c5, 0x7);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002e, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002e, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002e, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90204, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x190204, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x290204, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20024, 0xab);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120024, 0xab);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220024, 0xab);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20056, 0x3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120056, 0xa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220056, 0xa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1004d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1014d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1104d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1114d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1204d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1214d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1304d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1314d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11004d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11014d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11104d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11114d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11204d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11214d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11304d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11314d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21004d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21014d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21104d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21114d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21204d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21214d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21304d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21314d, 0xe00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10049, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10149, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11049, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11149, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12049, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12149, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13049, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13149, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110049, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110149, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111049, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111149, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112049, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112149, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113049, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113149, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210049, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210149, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211049, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211149, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212049, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212149, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213049, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213149, 0xe38);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x43, 0x21);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1043, 0x21);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2043, 0x21);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3043, 0x21);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4043, 0x21);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5043, 0x21);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6043, 0x21);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7043, 0x21);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8043, 0x21);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9043, 0x21);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20018, 0x3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20075, 0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20050, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20008, 0x320);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120008, 0x64);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220008, 0x19);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200b2, 0x19c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10043, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10143, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11043, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11143, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12043, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12143, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13043, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13143, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200b2, 0x19c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110043, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110143, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111043, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111143, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112043, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112143, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113043, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113143, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200b2, 0x19c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210043, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210143, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211043, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211143, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212043, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212143, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213043, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213143, 0x5a1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200fa, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200fa, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200fa, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20019, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120019, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220019, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f0, 0x660);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f1, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f2, 0x4444);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f3, 0x8888);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f4, 0x5555);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f5, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f6, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f7, 0xf000);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000b, 0x65);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000c, 0xc9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000d, 0x7d1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000e, 0x2c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000b, 0xd);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000c, 0x1a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000d, 0xfb);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000e, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000b, 0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000c, 0x7);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000d, 0x3f);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000e, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20025, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20060, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	/* load the 1D training image */
+	ddr_load_train_code(FW_1D_IMAGE);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+	/* set the PHY input clock to the desired frequency for pstate 2 */
+	dwc_ddrphy_phyinit_userCustom_E_setDfiClk(2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x102);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x64);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+extern void wait_ddrphy_training_complete(void);
+	wait_ddrphy_training_complete();
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+	/* set the PHY input clock to the desired frequency for pstate 1 */
+	dwc_ddrphy_phyinit_userCustom_E_setDfiClk(1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x101);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x190);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x500);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+extern void wait_ddrphy_training_complete(void);
+	wait_ddrphy_training_complete();
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+	/* set the PHY input clock to the desired frequency for pstate 0 */
+	dwc_ddrphy_phyinit_userCustom_E_setDfiClk(0);
+
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, 0x2828);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, 0x14);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x131f);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, 0x31);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, 0x4d46);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, 0x4d08);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, 0x31);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, 0x4d46);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, 0x4d08);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, 0x312d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, 0x4600);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, 0x84d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, 0x4d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x500);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, 0x312d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, 0x4600);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, 0x84d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+extern void wait_ddrphy_training_complete(void);
+wait_ddrphy_training_complete();
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	/* load the 2D training image */
+	ddr_load_train_code(FW_2D_IMAGE);
+
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0);
+
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x61);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x100);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x1f7f);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x084d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x084d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x500);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1);
+	/* Execute the Training Firmware */
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x0);
+	/* wait for 2D training complete */
+	extern void wait_ddrphy_training_complete(void);
+	wait_ddrphy_training_complete();
+
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1);
+
+	/* (I) Load PHY Init Engine Image */
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90000, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90001, 0x400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90002, 0x10e);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90003, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90004, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90005, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90029, 0xb);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002a, 0x480);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002b, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002c, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002d, 0x448);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002e, 0x139);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002f, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90030, 0x478);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90031, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90032, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90033, 0xe8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90034, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90035, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90036, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90037, 0x139);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90038, 0xf);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90039, 0x7c0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003a, 0x139);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003b, 0x44);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003c, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003d, 0x159);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003e, 0x14f);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003f, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90040, 0x159);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90041, 0x47);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90042, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90043, 0x149);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90044, 0x4f);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90045, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90046, 0x179);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90047, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90048, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90049, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004b, 0x7c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004c, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004e, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004f, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90050, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90051, 0x45a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90052, 0x9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90053, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90054, 0x448);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90055, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90056, 0x40);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90057, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90058, 0x179);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90059, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005a, 0x618);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005b, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005c, 0x40c0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005d, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005e, 0x149);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005f, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90060, 0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90061, 0x48);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90062, 0x4040);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90063, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90064, 0x149);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90065, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90066, 0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90067, 0x48);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90068, 0x40);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90069, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006a, 0x149);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006b, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006c, 0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006d, 0x18);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006f, 0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90070, 0x78);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90071, 0x549);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90072, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90073, 0x159);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90074, 0xd49);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90075, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90076, 0x159);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90077, 0x94a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90078, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90079, 0x159);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007a, 0x441);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007b, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007c, 0x149);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007d, 0x42);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007e, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007f, 0x149);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90080, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90081, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90082, 0x149);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90083, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90084, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90085, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90086, 0xa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90087, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90088, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90089, 0x9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008a, 0x3c0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008b, 0x149);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008c, 0x9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008d, 0x3c0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008e, 0x159);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008f, 0x18);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90090, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90091, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90092, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90093, 0x3c0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90094, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90095, 0x18);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90096, 0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90097, 0x48);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90098, 0x18);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90099, 0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009a, 0x58);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009b, 0xa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009c, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009d, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009e, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009f, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a0, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a1, 0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a2, 0x7c0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a3, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a4, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a5, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a6, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40000, 0x811);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40020, 0x880);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40040, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40060, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40001, 0x4016);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40021, 0x83);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40041, 0x4f);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40061, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40002, 0x4040);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40022, 0x83);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40042, 0x51);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40062, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40003, 0x811);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40023, 0x880);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40043, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40063, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40004, 0x720);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40024, 0xf);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40044, 0x1740);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40064, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40005, 0x16);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40025, 0x83);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40045, 0x4b);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40065, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40006, 0x716);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40026, 0xf);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40046, 0x2001);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40066, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40007, 0x716);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40027, 0xf);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40047, 0x2800);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40067, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40008, 0x716);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40028, 0xf);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40048, 0xf00);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40068, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40009, 0x720);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40029, 0xf);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40049, 0x1400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40069, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000a, 0xe08);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002a, 0xc15);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000b, 0x623);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002b, 0x15);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004b, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006b, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000c, 0x4004);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002c, 0x80);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004c, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006c, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000d, 0xe08);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002d, 0xc1a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000e, 0x623);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002e, 0x1a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000f, 0x4040);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002f, 0x80);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004f, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006f, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40010, 0x2604);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40030, 0x15);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40050, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40070, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40011, 0x708);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40031, 0x5);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40051, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40071, 0x2002);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40012, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40032, 0x80);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40052, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40072, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40013, 0x2604);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40033, 0x1a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40053, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40073, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40014, 0x708);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40034, 0xa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40054, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40074, 0x2002);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40015, 0x4040);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40035, 0x80);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40055, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40075, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40016, 0x60a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40036, 0x15);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40056, 0x1200);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40076, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40017, 0x61a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40037, 0x15);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40057, 0x1300);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40077, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40018, 0x60a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40038, 0x1a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40058, 0x1200);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40078, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40019, 0x642);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40039, 0x1a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40059, 0x1300);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40079, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4001a, 0x4808);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4003a, 0x880);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4005a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4007a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a7, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a8, 0x790);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a9, 0x11a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900aa, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ab, 0x7aa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ac, 0x2a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ad, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ae, 0x7b2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900af, 0x2a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b0, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b1, 0x7c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b2, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b3, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b4, 0x2a8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b5, 0x129);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b6, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b7, 0x370);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b8, 0x129);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b9, 0xa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ba, 0x3c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bb, 0x1a9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bc, 0xc);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bd, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900be, 0x199);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bf, 0x14);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c0, 0x790);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c1, 0x11a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c2, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c3, 0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c4, 0x18);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c5, 0xc);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c6, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c7, 0x199);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c8, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c9, 0x8568);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ca, 0x108);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cb, 0x18);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cc, 0x790);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cd, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ce, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cf, 0x1d8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d0, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d1, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d2, 0x8558);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d3, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d4, 0x70);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d5, 0x788);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d6, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d7, 0x1ff8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d8, 0x85a8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d9, 0x1e8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900da, 0x50);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900db, 0x798);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dc, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dd, 0x60);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900de, 0x7a0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900df, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e0, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e1, 0x8310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e2, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e3, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e4, 0xa310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e5, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e6, 0xa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e7, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e8, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e9, 0x6e);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ea, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900eb, 0x68);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ec, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ed, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ee, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ef, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f0, 0x8310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f1, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f2, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f3, 0xa310);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f4, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f5, 0x1ff8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f6, 0x85a8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f7, 0x1e8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f8, 0x68);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f9, 0x798);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fa, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fb, 0x78);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fc, 0x7a0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fd, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fe, 0x68);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ff, 0x790);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90100, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90101, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90102, 0x8b10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90103, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90104, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90105, 0xab10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90106, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90107, 0xa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90108, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90109, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010a, 0x58);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010b, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010c, 0x68);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010d, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010e, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010f, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90110, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90111, 0x8b10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90112, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90113, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90114, 0xab10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90115, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90116, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90117, 0x1d8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90118, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90119, 0x80);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011a, 0x790);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011b, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011c, 0x18);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011d, 0x7aa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011e, 0x6a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011f, 0xa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90120, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90121, 0x1e9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90122, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90123, 0x8080);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90124, 0x108);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90125, 0xf);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90126, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90127, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90128, 0xc);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90129, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012a, 0x68);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012b, 0x9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012c, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012d, 0x1a9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012f, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90130, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90131, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90132, 0x8080);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90133, 0x108);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90134, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90135, 0x7aa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90136, 0x6a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90137, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90138, 0x8568);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90139, 0x108);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013a, 0xb7);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013b, 0x790);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013c, 0x16a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013d, 0x1d);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013f, 0x68);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90140, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90141, 0x8558);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90142, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90143, 0xf);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90144, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90145, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90146, 0xc);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90147, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90148, 0x68);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90149, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014a, 0x408);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014b, 0x169);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014c, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014d, 0x8558);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014e, 0x168);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014f, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90150, 0x3c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90151, 0x1a9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90152, 0x3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90153, 0x370);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90154, 0x129);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90155, 0x20);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90156, 0x2aa);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90157, 0x9);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90158, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90159, 0x400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015a, 0x10e);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015b, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015c, 0xe8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015d, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015e, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015f, 0x8140);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90160, 0x10c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90161, 0x10);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90162, 0x8138);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90163, 0x10c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90164, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90165, 0x7c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90166, 0x101);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90167, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90168, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90169, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016a, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016b, 0x448);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016c, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016d, 0xf);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016e, 0x7c0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016f, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90170, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90171, 0xe8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90172, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90173, 0x47);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90174, 0x630);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90175, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90176, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90177, 0x618);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90178, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90179, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017a, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017b, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017c, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017d, 0x7c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017e, 0x109);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017f, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90180, 0x8140);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90181, 0x10c);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90182, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90183, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90184, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90185, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90186, 0x4);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90187, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90188, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90189, 0x7c8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018a, 0x101);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90006, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90007, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90008, 0x8);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90009, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000a, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000b, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd00e7, 0x400);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90017, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9001f, 0x2a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90026, 0x6a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d0, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d1, 0x101);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d2, 0x105);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d3, 0x107);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d4, 0x10f);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d5, 0x202);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d6, 0x20a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d7, 0x20b);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000c, 0x0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000d, 0x173);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000e, 0x60);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000f, 0x6110);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90010, 0x2152);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90011, 0xdfbd);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90012, 0x60);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90013, 0x6152);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20010, 0x5a);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20011, 0x3);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40080, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40081, 0x12);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40082, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40083, 0x12);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40084, 0xe0);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40085, 0x12);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400fd, 0xf);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10011, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10012, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10013, 0x180);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10018, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10002, 0x6209);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x100b2, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x101b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x102b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x103b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x104b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x105b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x106b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x107b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x108b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11011, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11012, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11013, 0x180);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11018, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11002, 0x6209);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110b2, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x114b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x115b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x116b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x117b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x118b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12011, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12012, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12013, 0x180);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12018, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002, 0x6209);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120b2, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x121b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x122b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x123b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x124b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x125b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x126b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x127b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x128b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13011, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13012, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13013, 0x180);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13018, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13002, 0x6209);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x130b2, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x131b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x132b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x133b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x134b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x135b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x136b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x137b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x138b4, 0x1);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xc0080, 0x2);
+	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x000d0000, 0x00000000);
+	tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010, 0x0000006a);
+	tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d, 0x00000001);
+	/*
+	 * CalBusy.0 =1, indicates the calibrator is actively calibrating.
+	 * Wait Calibrating done.
+	 */
+	tmp_t = 1;
+	while(tmp_t) {
+		tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20097);
+		tmp_t = tmp & 0x01;
+	}
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0);
+}
diff --git a/board/freescale/imx8mq_phanbell/ddr/helper.c b/board/freescale/imx8mq_phanbell/ddr/helper.c
new file mode 100644
index 0000000..782009e
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/ddr/helper.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr_memory_map.h>
+#include <asm/sections.h>
+
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMEM_LEN 32768//23400	//byte
+#define DMEM_LEN 16384//1720	//byte
+#define IMEM_2D_OFFSET 	49152
+
+#define IMEM_OFFSET_ADDR 0x00050000
+#define DMEM_OFFSET_ADDR 0x00054000
+#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+
+/* We need PHY iMEM PHY is 32KB padded */
+void ddr_load_train_code(enum fw_type type)
+{
+	u32 tmp32, i;
+	u32 error = 0;
+	unsigned long pr_to32, pr_from32;
+	unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
+	unsigned long imem_start = (unsigned long)&_end + fw_offset;
+	unsigned long dmem_start = imem_start + IMEM_LEN;
+
+	pr_from32 = imem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	for(i = 0x0; i < IMEM_LEN; ){
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	pr_from32 = dmem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	for(i = 0x0; i < DMEM_LEN;){
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	printf("check ddr4_pmu_train_imem code\n");
+	pr_from32 = imem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	for(i = 0x0; i < IMEM_LEN;){
+		tmp32 = (readw(pr_to32) & 0x0000ffff);
+		pr_to32 += 4;
+		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+
+		if(tmp32 != readl(pr_from32)){
+			printf("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 4;
+		i += 4;
+	}
+	if(error){
+		printf("check ddr4_pmu_train_imem code fail=%d\n",error);
+	}else{
+		printf("check ddr4_pmu_train_imem code pass\n");
+	}
+
+	printf("check ddr4_pmu_train_dmem code\n");
+	pr_from32 = dmem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	for(i = 0x0; i < DMEM_LEN;){
+		tmp32 = (readw(pr_to32) & 0x0000ffff);
+		pr_to32 += 4;
+		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+		if(tmp32 != readl(pr_from32)){
+			printf("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 4;
+		i += 4;
+	}
+
+	if(error){
+		printf("check ddr4_pmu_train_dmem code fail=%d",error);
+	}else{
+		printf("check ddr4_pmu_train_dmem code pass\n");
+	}
+}
diff --git a/board/freescale/imx8mq_phanbell/ddr/wait_ddrphy_training_complete.c b/board/freescale/imx8mq_phanbell/ddr/wait_ddrphy_training_complete.c
new file mode 100644
index 0000000..0b42e58
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/ddr/wait_ddrphy_training_complete.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+static inline void poll_pmu_message_ready(void)
+{
+	unsigned int reg;
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
+	} while (reg & 0x1);
+}
+
+static inline void ack_pmu_message_recieve(void)
+{
+	unsigned int reg;
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0);
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
+	} while (!(reg & 0x1));
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1);
+}
+
+static inline unsigned int get_mail(void)
+{
+	unsigned int reg;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
+
+	ack_pmu_message_recieve();
+
+	return reg;
+}
+
+static inline unsigned int get_stream_message(void)
+{
+	unsigned int reg, reg2;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
+
+	reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
+
+	reg2 = (reg2 << 16) | reg;
+
+	ack_pmu_message_recieve();
+
+	return reg2;
+}
+
+static inline void decode_major_message(unsigned int mail)
+{
+	ddr_printf("[PMU Major message = 0x%08x]\n", mail);
+}
+
+static inline void decode_streaming_message(void)
+{
+	unsigned int string_index, arg __maybe_unused;
+	int i = 0;
+
+	string_index = get_stream_message();
+	ddr_printf("	PMU String index = 0x%08x\n", string_index);
+	while (i < (string_index & 0xffff)){
+		arg = get_stream_message();
+		ddr_printf("	arg[%d] = 0x%08x\n", i, arg);
+		i++;
+	}
+
+	ddr_printf("\n");
+}
+
+void wait_ddrphy_training_complete(void)
+{
+	unsigned int mail;
+	while (1) {
+		mail = get_mail();
+		decode_major_message(mail);
+		if (mail == 0x08) {
+			decode_streaming_message();
+		} else if (mail == 0x07) {
+			printf("Training PASS\n");
+			break;
+		} else if (mail == 0xff) {
+			printf("Training FAILED\n");
+			break;
+		}
+	}
+}
diff --git a/board/freescale/imx8mq_phanbell/imx8m_phanbell.c b/board/freescale/imx8mq_phanbell/imx8m_phanbell.c
new file mode 100644
index 0000000..a1a1806
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/imx8m_phanbell.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <power/pmic.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define QSPI_PAD_CTRL	(PAD_CTL_DSE2 | PAD_CTL_HYS)
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_QSPI
+static iomux_v3_cfg_t const qspi_pads[] = {
+	IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+
+	IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+};
+
+int board_qspi_init(void)
+{
+	imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
+
+	set_clk_qspi();
+
+	return 0;
+}
+#endif
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+int board_postclk_init(void)
+{
+	/* TODO */
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	/* rom_pointer[1] contains the size of TEE occupies */
+	if (rom_pointer[1])
+		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+	else
+		gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
+static iomux_v3_cfg_t const fec1_rst_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, ARRAY_SIZE(fec1_rst_pads));
+
+	gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
+	gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
+	udelay(500);
+	gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
+}
+
+static int setup_fec(void)
+{
+	setup_iomux_fec();
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(IOMUXC_GPR1,
+			BIT(13) | BIT(17), 0);
+	return set_clk_enet(ENET_125MHz);
+}
+
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_DWC3
+
+#define USB_PHY_CTRL0			0xF0040
+#define USB_PHY_CTRL0_REF_SSP_EN	BIT(2)
+
+#define USB_PHY_CTRL1			0xF0044
+#define USB_PHY_CTRL1_RESET		BIT(0)
+#define USB_PHY_CTRL1_COMMONONN		BIT(1)
+#define USB_PHY_CTRL1_ATERESET		BIT(3)
+#define USB_PHY_CTRL1_VDATSRCENB0	BIT(19)
+#define USB_PHY_CTRL1_VDATDETENB0	BIT(20)
+
+#define USB_PHY_CTRL2			0xF0048
+#define USB_PHY_CTRL2_TXENABLEN0	BIT(8)
+
+static struct dwc3_device dwc3_device_data = {
+	.maximum_speed = USB_SPEED_SUPER,
+	.base = USB1_BASE_ADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+	.power_down_scale = 2,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+	dwc3_uboot_handle_interrupt(0);
+	return 0;
+}
+
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+	u32 RegData;
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+			USB_PHY_CTRL1_COMMONONN);
+	RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL0);
+	RegData |= USB_PHY_CTRL0_REF_SSP_EN;
+	writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL2);
+	RegData |= USB_PHY_CTRL2_TXENABLEN0;
+	writel(RegData, dwc3->base + USB_PHY_CTRL2);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+}
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+int board_usb_init(int index, enum usb_init_type init)
+{
+	imx8m_usb_power(index, true);
+
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		dwc3_nxp_usb_phy_init(&dwc3_device_data);
+		return dwc3_uboot_init(&dwc3_device_data);
+	}
+
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		dwc3_uboot_exit(index);
+	}
+
+	imx8m_usb_power(index, false);
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	board_qspi_init();
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	setenv("board_name", "Phanbell");
+	setenv("board_rev", "iMX8MQ");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+	return 0; /*TODO*/
+}
+#endif /*CONFIG_ANDROID_RECOVERY*/
+#endif /*CONFIG_FSL_FASTBOOT*/
diff --git a/board/freescale/imx8mq_phanbell/spl.c b/board/freescale/imx8mq_phanbell/spl.c
new file mode 100644
index 0000000..fe00d44
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/spl.c
@@ -0,0 +1,214 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/arch/ddr_memory_map.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <power/pmic.h>
+#include <power/bd71837.h>
+#include <asm/arch/clock.h>
+#include <asm/imx-common/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include "ddr/ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_dram_init(void)
+{
+	/* ddr init */
+	ddr_init();
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC	1
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_bd71837_init(I2C_PMIC);
+	if (ret)
+		printf("power init failed");
+
+	p = pmic_get("BD71837");
+	pmic_probe(p);
+
+	/* Set BUCK5 output for DRAM to 1.1V */
+	pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x5);
+	return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+	enable_tzc380();
+
+	/* Adjust pmic voltage to 1.0V for 800M */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Serial download mode */
+	if (is_usb_boot()) {
+		puts("Back to ROM, SDP\n");
+		restore_boot_params();
+	}
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/freescale/imx8qm_arm2/imx8qm_arm2.c b/board/freescale/imx8qm_arm2/imx8qm_arm2.c
index 61db268..c31e5d1 100644
--- a/board/freescale/imx8qm_arm2/imx8qm_arm2.c
+++ b/board/freescale/imx8qm_arm2/imx8qm_arm2.c
@@ -287,31 +287,34 @@
 
 static void enet_device_phy_reset(void)
 {
-	struct gpio_desc desc;
+	struct gpio_desc desc_enet0;
+	struct gpio_desc desc_enet1;
 	int ret;
 
-	if (0 == CONFIG_FEC_ENET_DEV) {
-		ret = dm_gpio_lookup_name("gpio@18_1", &desc);
-		if (ret)
-			return;
+	ret = dm_gpio_lookup_name("gpio@18_1", &desc_enet0);
+	if (ret)
+		return;
 
-		ret = dm_gpio_request(&desc, "enet0_reset");
-		if (ret)
-			return;
-	} else {
-		ret = dm_gpio_lookup_name("gpio@18_4", &desc);
-		if (ret)
-			return;
+	ret = dm_gpio_request(&desc_enet0, "enet0_reset");
+	if (ret)
+		return;
+	ret = dm_gpio_lookup_name("gpio@18_4", &desc_enet1);
+	if (ret)
+		return;
 
-		ret = dm_gpio_request(&desc, "enet1_reset");
-		if (ret)
-			return;
-	}
+	ret = dm_gpio_request(&desc_enet1, "enet1_reset");
+	if (ret)
+		return;
 
-	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
-	dm_gpio_set_value(&desc, 0);
+	dm_gpio_set_dir_flags(&desc_enet0, GPIOD_IS_OUT);
+	dm_gpio_set_value(&desc_enet0, 0);
 	udelay(50);
-	dm_gpio_set_value(&desc, 1);
+	dm_gpio_set_value(&desc_enet0, 1);
+
+	dm_gpio_set_dir_flags(&desc_enet1, GPIOD_IS_OUT);
+	dm_gpio_set_value(&desc_enet1, 0);
+	udelay(50);
+	dm_gpio_set_value(&desc_enet1, 1);
 
 	/* The board has a long delay for this reset to become stable */
 	mdelay(200);
diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig
index a44c8f7..93d7d5f 100644
--- a/board/freescale/imx8qm_mek/Kconfig
+++ b/board/freescale/imx8qm_mek/Kconfig
@@ -9,4 +9,6 @@
 config SYS_CONFIG_NAME
 	default "imx8qm_mek"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c
index 1d5648b..4546dac 100644
--- a/board/freescale/imx8qm_mek/imx8qm_mek.c
+++ b/board/freescale/imx8qm_mek/imx8qm_mek.c
@@ -288,35 +288,12 @@
 	SC_P_QSPI1A_SS0_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
 };
 
-struct udevice *tcpc_i2c_dev = NULL;
-
-static void setup_typec(void)
-{
-	struct udevice *bus;
-	uint8_t chip = 0x51;
-	int ret;
-
-	imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
-	gpio_request(USB_TYPEC_SEL, "typec_sel");
-	gpio_request(USB_TYPEC_EN, "typec_en");
-
-	gpio_direction_output(USB_TYPEC_EN, 1);
-
-	ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
-	if (ret) {
-		printf("%s: Can't find bus\n", __func__);
-		return;
-	}
-
-	ret = dm_i2c_probe(bus, chip, 0, &tcpc_i2c_dev);
-	if (ret) {
-		printf("%s: Can't find device id=0x%x\n",
-			__func__, chip);
-		return;
-	}
-
-	tcpc_init(tcpc_i2c_dev);
-}
+struct tcpc_port port;
+struct tcpc_port_config port_config = {
+	.i2c_bus = 0,
+	.addr = 0x51,
+	.port_type = TYPEC_PORT_DFP,
+};
 
 void ss_mux_select(enum typec_cc_polarity pol)
 {
@@ -326,12 +303,23 @@
 		gpio_direction_output(USB_TYPEC_SEL, 1);
 }
 
+static void setup_typec(void)
+{
+	imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
+	gpio_request(USB_TYPEC_SEL, "typec_sel");
+	gpio_request(USB_TYPEC_EN, "typec_en");
+
+	gpio_direction_output(USB_TYPEC_EN, 1);
+
+	tcpc_init(&port, port_config, &ss_mux_select);
+}
+
 int board_usb_init(int index, enum usb_init_type init)
 {
 	int ret = 0;
 
-	if (init == USB_INIT_HOST && tcpc_i2c_dev)
-		ret = tcpc_setup_dfp_mode(tcpc_i2c_dev, &ss_mux_select);
+	if (init == USB_INIT_HOST)
+		ret = tcpc_setup_dfp_mode(&port);
 
 	return ret;
 }
@@ -340,8 +328,8 @@
 {
 	int ret = 0;
 
-	if (init == USB_INIT_HOST && tcpc_i2c_dev)
-		ret = tcpc_disable_vbus(tcpc_i2c_dev);
+	if (init == USB_INIT_HOST)
+		ret = tcpc_disable_src_vbus(&port);
 
 	return ret;
 }
@@ -350,7 +338,7 @@
 int board_init(void)
 {
 	/* Power up base board */
-	sc_pm_set_resource_power_mode(gd->arch.ipc_channel_handle, 
+	sc_pm_set_resource_power_mode(gd->arch.ipc_channel_handle,
 		SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
 
 #ifdef CONFIG_MXC_GPIO
@@ -413,6 +401,7 @@
 	return dev_no;
 }
 
+extern uint32_t _end_ofs;
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -424,6 +413,18 @@
 	board_late_mmc_env_init();
 #endif
 
+#ifdef IMX_LOAD_HDMI_FIMRWARE
+	char *end_of_uboot;
+	char command[256];
+	end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob));
+	end_of_uboot += 9;
+
+	memcpy(IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot, IMX_HDMI_FIRMWARE_SIZE);
+
+	sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR);
+	run_command(command, 0);
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c
index 362957d..5eb61b0 100644
--- a/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c
+++ b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c
@@ -255,31 +255,35 @@
 
 static void enet_device_phy_reset(void)
 {
-	struct gpio_desc desc;
+	struct gpio_desc desc_enet0;
+	struct gpio_desc desc_enet1;
 	int ret;
 
-	if (0 == CONFIG_FEC_ENET_DEV) {
-		ret = dm_gpio_lookup_name("gpio@18_1", &desc);
-		if (ret)
-			return;
+	ret = dm_gpio_lookup_name("gpio@18_1", &desc_enet0);
+	if (ret)
+		return;
 
-		ret = dm_gpio_request(&desc, "enet0_reset");
-		if (ret)
-			return;
-	} else {
-		ret = dm_gpio_lookup_name("gpio@18_4", &desc);
-		if (ret)
-			return;
+	ret = dm_gpio_request(&desc_enet0, "enet0_reset");
+	if (ret)
+		return;
 
-		ret = dm_gpio_request(&desc, "enet1_reset");
-		if (ret)
-			return;
-	}
+	ret = dm_gpio_lookup_name("gpio@18_4", &desc_enet1);
+	if (ret)
+		return;
 
-	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
-	dm_gpio_set_value(&desc, 0);
+	ret = dm_gpio_request(&desc_enet1, "enet1_reset");
+	if (ret)
+		return;
+
+	dm_gpio_set_dir_flags(&desc_enet0, GPIOD_IS_OUT);
+	dm_gpio_set_value(&desc_enet0, 0);
 	udelay(50);
-	dm_gpio_set_value(&desc, 1);
+	dm_gpio_set_value(&desc_enet0, 1);
+
+	dm_gpio_set_dir_flags(&desc_enet1, GPIOD_IS_OUT);
+	dm_gpio_set_value(&desc_enet1, 0);
+	udelay(50);
+	dm_gpio_set_value(&desc_enet1, 1);
 
 	/* The board has a long delay for this reset to become stable */
 	mdelay(200);
diff --git a/board/freescale/imx8qxp_mek/Kconfig b/board/freescale/imx8qxp_mek/Kconfig
index 5ed457f..b67300d 100644
--- a/board/freescale/imx8qxp_mek/Kconfig
+++ b/board/freescale/imx8qxp_mek/Kconfig
@@ -9,4 +9,6 @@
 config SYS_CONFIG_NAME
 	default "imx8qxp_mek"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
index 7085809..24925a0 100644
--- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c
+++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
@@ -421,12 +421,23 @@
 	SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
 };
 
-struct udevice *tcpc_i2c_dev = NULL;
+struct tcpc_port port;
+struct tcpc_port_config port_config = {
+	.i2c_bus = 1,
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_DFP,
+};
+
+void ss_mux_select(enum typec_cc_polarity pol)
+{
+	if (pol == TYPEC_POLARITY_CC1)
+		gpio_direction_output(USB_TYPEC_SEL, 0);
+	else
+		gpio_direction_output(USB_TYPEC_SEL, 1);
+}
 
 static void setup_typec(void)
 {
-	struct udevice *bus;
-	uint8_t chip = 0x50;
 	int ret;
 	struct gpio_desc typec_en_desc;
 
@@ -448,36 +459,15 @@
 	/* Enable SS MUX */
 	dm_gpio_set_dir_flags(&typec_en_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 
-	ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
-	if (ret) {
-		printf("%s: Can't find bus\n", __func__);
-		return;
-	}
-
-	ret = dm_i2c_probe(bus, chip, 0, &tcpc_i2c_dev);
-	if (ret) {
-		printf("%s: Can't find device id=0x%x\n",
-			__func__, chip);
-		return;
-	}
-
-	tcpc_init(tcpc_i2c_dev);
-}
-
-void ss_mux_select(enum typec_cc_polarity pol)
-{
-	if (pol == TYPEC_POLARITY_CC1)
-		gpio_direction_output(USB_TYPEC_SEL, 0);
-	else
-		gpio_direction_output(USB_TYPEC_SEL, 1);
+	tcpc_init(&port, port_config, &ss_mux_select);
 }
 
 int board_usb_init(int index, enum usb_init_type init)
 {
 	int ret = 0;
 
-	if (init == USB_INIT_HOST && tcpc_i2c_dev)
-		ret = tcpc_setup_dfp_mode(tcpc_i2c_dev, &ss_mux_select);
+	if (init == USB_INIT_HOST)
+		ret = tcpc_setup_dfp_mode(&port);
 
 	return ret;
 
@@ -487,8 +477,8 @@
 {
 	int ret = 0;
 
-	if (init == USB_INIT_HOST && tcpc_i2c_dev)
-		ret = tcpc_disable_vbus(tcpc_i2c_dev);
+	if (init == USB_INIT_HOST)
+		ret = tcpc_disable_src_vbus(&port);
 
 	return ret;
 }
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index 6096e3c..e3b7516 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -624,6 +624,7 @@
 {
 	struct udevice *dev;
 	int ret, dev_id, rev_id;
+	u32 sw3mode;
 
 	ret = pmic_get("pfuze3000", &dev);
 	if (ret == -ENODEV)
@@ -637,6 +638,12 @@
 
 	pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
 
+	/* change sw3 mode to avoid DDR power off */
+	sw3mode = pmic_reg_read(dev, PFUZE3000_SW3MODE);
+	ret = pmic_reg_write(dev, PFUZE3000_SW3MODE, sw3mode | 0x20);
+	if (ret < 0)
+		printf("PMIC: PFUZE3000 change sw3 mode failed\n");
+
 	return 0;
 }
 #endif
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index f1ca4b2..36f7629 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -34,3 +34,7 @@
 CONFIG_FIT=y
 CONFIG_SPL_FIT=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB_TCPC=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index 9b1ee4c..e60b9fb 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -23,7 +23,7 @@
 CONFIG_CMD_USB=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-
+CONFIG_USB_TCPC=y
 
 # CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_USB_GADGET=y
diff --git a/configs/imx8qm_mek_fspi_defconfig b/configs/imx8qm_mek_fspi_defconfig
index c9ffb6a..36b5f4b 100644
--- a/configs/imx8qm_mek_fspi_defconfig
+++ b/configs/imx8qm_mek_fspi_defconfig
@@ -23,7 +23,7 @@
 CONFIG_CMD_USB=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-
+CONFIG_USB_TCPC=y
 
 # CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_USB_GADGET=y
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index ade0621..cd84875 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -26,6 +26,7 @@
 CONFIG_CMD_USB=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
 
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_USB_GADGET=y
diff --git a/configs/imx8qxp_mek_fspi_defconfig b/configs/imx8qxp_mek_fspi_defconfig
index 5aff415..b621a7f 100644
--- a/configs/imx8qxp_mek_fspi_defconfig
+++ b/configs/imx8qxp_mek_fspi_defconfig
@@ -26,6 +26,7 @@
 CONFIG_CMD_USB=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
 
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_USB_GADGET=y
diff --git a/configs/multa-imx7d_defconfig b/configs/multa-imx7d_defconfig
index de0e3ef..6b4324c 100644
--- a/configs/multa-imx7d_defconfig
+++ b/configs/multa-imx7d_defconfig
@@ -34,4 +34,3 @@
 CONFIG_FASTBOOT=y
 CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_CMD_FASTBOOT=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/mx8mq_phanbell_androidthings_defconfig b/configs/mx8mq_phanbell_androidthings_defconfig
new file mode 100644
index 0000000..dd0cf70
--- /dev/null
+++ b/configs/mx8mq_phanbell_androidthings_defconfig
@@ -0,0 +1,40 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_IMX8MQ_PHANBELL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ANDROID_THINGS_SUPPORT"
+CONFIG_EFI_PARTITION=y
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_BOOTDELAY=3
+CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-phanbell"
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+# CONFIG_BLK is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
diff --git a/configs/pico-imx7d-trusty_defconfig b/configs/pico-imx7d-trusty_defconfig
index d5bafe1..90b16c4 100644
--- a/configs/pico-imx7d-trusty_defconfig
+++ b/configs/pico-imx7d-trusty_defconfig
@@ -38,4 +38,4 @@
 CONFIG_OF_LIBFDT=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
-# CONFIG_EFI_LOADER is not set
\ No newline at end of file
+# CONFIG_EFI_LOADER is not set
diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c
index e159e33..018b2b6 100644
--- a/drivers/i2c/imx_lpi2c.c
+++ b/drivers/i2c/imx_lpi2c.c
@@ -20,6 +20,8 @@
 #define LPI2C_NACK_TOUT_MS 1
 #define LPI2C_TIMEOUT_MS 100
 
+static int bus_i2c_init(struct udevice *bus, int speed);
+
 /* Weak linked function for overridden by some SoC power function */
 int __weak init_i2c_power(unsigned i2c_num)
 {
@@ -168,7 +170,14 @@
 	result = imx_lpci2c_check_busy_bus(bus);
 	if (result) {
 		debug("i2c: start check busy bus: 0x%x\n", result);
-		return result;
+
+		/* Try to init the lpi2c then check the bus busy again */
+		bus_i2c_init(bus, 100000);
+		result = imx_lpci2c_check_busy_bus(bus);
+		if (result) {
+			printf("i2c: Error check busy bus: 0x%x\n", result);
+			return result;
+		}
 	}
 	/* clear all status flags */
 	writel(0x7f00, &regs->msr);
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 9adf0a8..42f2d39 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -356,13 +356,16 @@
 
 	/* Only bank 0 and 1 are redundancy mode, others are ECC mode */
 	if (bank != 0 && bank != 1) {
-		ret = fuse_sense(bank, word, &val);
-		if (ret)
-			return ret;
+		if ((soc_rev() < CHIP_REV_2_0) ||
+		    ((soc_rev() >= CHIP_REV_2_0) && bank != 9 && bank != 10 && bank != 28)) {
+			ret = fuse_sense(bank, word, &val);
+			if (ret)
+				return ret;
 
-		if (val != 0) {
-			printf("mxc_ocotp: The word has been programmed, no more write\n");
-			return -EPERM;
+			if (val != 0) {
+				printf("mxc_ocotp: The word has been programmed, no more write\n");
+				return -EPERM;
+			}
 		}
 	}
 #endif
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 179b1c0..5f68f4d 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -517,9 +517,9 @@
 
 	/* Workaround for ESDHC errata ENGcm03648 */
 	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
-		int timeout = 12000;
+		int timeout = 62000;
 
-		/* Poll on DATA0 line for cmd with busy signal for 1200 ms */
+		/* Poll on DATA0 line for cmd with busy signal for 6200 ms */
 		while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
 					PRSSTAT_DAT0)) {
 			udelay(100);
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 03fea07..01779d5 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -40,6 +40,13 @@
 	functions. It uses an I2C interface and is designed for use with
 	tablets and smartphones.
 
+config DM_PMIC_BD71837
+	bool "Enable Driver Model for PMIC BD71837"
+	depends on DM_PMIC
+	---help---
+	This config enables implementation of driver-model pmic uclass features
+	for PMIC BD71837. The driver implements read/write operations.
+
 config DM_PMIC_PFUZE100
 	bool "Enable Driver Model for PMIC PFUZE100"
 	depends on DM_PMIC
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index e54367a..5fce9fc 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -9,6 +9,7 @@
 obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
 obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
 obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o
 obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
 obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
 obj-$(CONFIG_PMIC_ACT8846) += act8846.o
@@ -27,6 +28,7 @@
 obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
 obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
 obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+obj-$(CONFIG_POWER_BD71837) += pmic_bd71837.o
 obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
 obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o
 obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c
new file mode 100644
index 0000000..1405e79
--- /dev/null
+++ b/drivers/power/pmic/bd71837.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2018 NXP  *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/bd71837.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+	/* buck */
+	{ .prefix = "b", .driver = BD71837_REGULATOR_DRIVER},
+	/* ldo */
+	{ .prefix = "l", .driver = BD71837_REGULATOR_DRIVER},
+	{ },
+};
+
+static int bd71837_reg_count(struct udevice *dev)
+{
+	return BD71837_REG_NUM;
+}
+
+static int bd71837_write(struct udevice *dev, uint reg, const uint8_t *buff,
+			  int len)
+{
+	if (dm_i2c_write(dev, reg, buff, len)) {
+		error("write error to device: %p register: %#x!", dev, reg);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int bd71837_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+	if (dm_i2c_read(dev, reg, buff, len)) {
+		error("read error from device: %p register: %#x!", dev, reg);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int bd71837_bind(struct udevice *dev)
+{
+	int children;
+	int regulators_node;
+	const void *blob = gd->fdt_blob;
+
+	regulators_node = fdt_subnode_offset(blob, dev_of_offset(dev),
+					     "regulators");
+	if (regulators_node <= 0) {
+		debug("%s: %s regulators subnode not found!", __func__,
+		      dev->name);
+		return -ENXIO;
+	}
+
+	debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+	children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+	if (!children)
+		debug("%s: %s - no child found\n", __func__, dev->name);
+
+	/* Always return success for this device */
+	return 0;
+}
+
+static struct dm_pmic_ops bd71837_ops = {
+	.reg_count = bd71837_reg_count,
+	.read = bd71837_read,
+	.write = bd71837_write,
+};
+
+static const struct udevice_id bd71837_ids[] = {
+	{ .compatible = "rohm,bd71837", .data = 0x4b, },
+	{ }
+};
+
+U_BOOT_DRIVER(pmic_bd71837) = {
+	.name = "bd71837 pmic",
+	.id = UCLASS_PMIC,
+	.of_match = bd71837_ids,
+	.bind = bd71837_bind,
+	.ops = &bd71837_ops,
+};
diff --git a/drivers/power/pmic/pmic_bd71837.c b/drivers/power/pmic/pmic_bd71837.c
new file mode 100644
index 0000000..74195cc
--- /dev/null
+++ b/drivers/power/pmic/pmic_bd71837.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/bd71837.h>
+
+static const char bd71837_name[] = "BD71837";
+int power_bd71837_init (unsigned char bus) {
+	struct pmic *p = pmic_alloc();
+
+	if (!p) {
+		printf("%s: POWER allocation error!\n", __func__);
+		return -ENOMEM;
+	}
+
+	p->name = bd71837_name;
+	p->interface = PMIC_I2C;
+	p->number_of_regs = BD71837_REG_NUM;
+	p->hw.i2c.addr = 0x4b;
+	p->hw.i2c.tx_num = 1;
+	p->bus = bus;
+
+	printf("power_bd71837_init\n");
+
+	return 0;
+}
diff --git a/drivers/power/power_core.c b/drivers/power/power_core.c
index b72286d..eecd0f7 100644
--- a/drivers/power/power_core.c
+++ b/drivers/power/power_core.c
@@ -99,6 +99,7 @@
 	struct pmic *p;
 
 	list_for_each_entry(p, &pmic_list, list) {
+	    	printf("pmic debug: name=%s\n", p->name);
 		if (strcmp(p->name, s) == 0) {
 			debug("%s: pmic %s -> 0x%p\n", __func__, p->name, p);
 			return p;
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 9153ae6..93c4502 100755
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -254,11 +254,7 @@
 #else
 #define ANDROID_BOOTLOADER_OFFSET   0x400
 #endif
-#define ANDROID_BOOTLOADER_SIZE	    0xFFC00
-#define ANDROID_KERNEL_OFFSET	    0x100000
-#define ANDROID_KERNEL_SIZE	    0x500000
-#define ANDROID_URAMDISK_OFFSET	    0x600000
-#define ANDROID_URAMDISK_SIZE	    0x100000
+#define ANDROID_BOOTLOADER_SIZE	    0x1FFC00
 
 #define MMC_SATA_BLOCK_SIZE 512
 #define FASTBOOT_FBPARTS_ENV_MAX_LEN 1024
@@ -1315,7 +1311,8 @@
 	.read_rollback_index = fsl_read_rollback_index_rpmb,
 	.write_rollback_index = fsl_write_rollback_index_rpmb,
 	.read_is_device_unlocked = fsl_read_is_device_unlocked,
-	.get_unique_guid_for_partition = fsl_get_unique_guid_for_partition
+	.get_unique_guid_for_partition = fsl_get_unique_guid_for_partition,
+	.get_size_of_partition = fsl_get_size_of_partition
 };
 #endif
 
@@ -1443,7 +1440,7 @@
 
 #ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT
 /* Setup booargs for taking the system parition as ramdisk */
-static void fastboot_setup_system_boot_args(const char *slot)
+static void fastboot_setup_system_boot_args(const char *slot, bool append_root)
 {
 	const char *system_part_name = NULL;
 	if(slot == NULL)
@@ -1458,10 +1455,14 @@
 	if(ptentry != NULL) {
 		char bootargs_3rd[ANDR_BOOT_ARGS_SIZE];
 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
-		u32 dev_no = mmc_map_to_kernel_blk(mmc_get_env_dev());
-		sprintf(bootargs_3rd, "skip_initramfs root=/dev/mmcblk%dp%d",
-				dev_no,
-				ptentry->partition_index);
+		if (append_root) {
+			u32 dev_no = mmc_map_to_kernel_blk(mmc_get_env_dev());
+			sprintf(bootargs_3rd, "skip_initramfs root=/dev/mmcblk%dp%d",
+					dev_no,
+					ptentry->partition_index);
+		} else {
+			sprintf(bootargs_3rd, "skip_initramfs");
+		}
 		setenv("bootargs_3rd", bootargs_3rd);
 #endif
 	}
@@ -1593,11 +1594,13 @@
 	bool allow_fail = (lock_status == FASTBOOT_UNLOCK ? true : false);
 	avb_metric = get_timer(0);
 	/* if in lock state, do avb verify */
-	avb_result = avb_ab_flow(&fsl_avb_ab_ops, requested_partitions, allow_fail, &avb_out_data);
+	avb_result = avb_ab_flow_fast(&fsl_avb_ab_ops, requested_partitions, allow_fail,
+			AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, &avb_out_data);
 	/* get the duration of avb */
 	metrics.avb = get_timer(avb_metric);
 
-	if (avb_result == AVB_AB_FLOW_RESULT_OK) {
+	if ((avb_result == AVB_AB_FLOW_RESULT_OK) ||
+			(avb_result == AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR)) {
 		assert(avb_out_data != NULL);
 		/* load the first partition */
 		avb_loadpart = avb_out_data->loaded_partitions;
@@ -1605,27 +1608,40 @@
 		/* we should use avb_part_data->data as boot image */
 		/* boot image is already read by avb */
 		hdr = (struct andr_img_hdr *)avb_loadpart->data;
-		if (android_image_check_header(hdr)) {
-			printf("boota: bad boot image magic\n");
-			goto fail;
-		}
 		slot = avb_out_data->ab_suffix;
-		printf(" verify OK, boot '%s%s'\n", avb_loadpart->partition_name, slot);
-		char bootargs_sec[2048];
-		sprintf(bootargs_sec, "androidboot.slot_suffix=%s %s",
-			slot, avb_out_data->cmdline);
+		if (avb_result == AVB_AB_FLOW_RESULT_OK)
+			printf(" verify OK, boot '%s%s'\n",
+					avb_loadpart->partition_name, avb_out_data->ab_suffix);
+		else {
+			printf(" verify FAIL, state: UNLOCK\n");
+			printf(" boot '%s%s' still\n",
+					avb_loadpart->partition_name, avb_out_data->ab_suffix);
+		}
+		char bootargs_sec[ANDR_BOOT_ARGS_SIZE];
+		if (lock_status == FASTBOOT_LOCK) {
+			sprintf(bootargs_sec,
+					"androidboot.verifiedbootstate=green androidboot.slot_suffix=%s %s",
+					avb_out_data->ab_suffix, avb_out_data->cmdline);
+		} else {
+			sprintf(bootargs_sec,
+					"androidboot.verifiedbootstate=orange androidboot.slot_suffix=%s %s",
+					avb_out_data->ab_suffix, avb_out_data->cmdline);
+		}
 		setenv("bootargs_sec", bootargs_sec);
 #ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT
-		if(!is_recovery_mode)
-			fastboot_setup_system_boot_args(slot);
+		if(!is_recovery_mode) {
+			if(avb_out_data->cmdline != NULL && strstr(avb_out_data->cmdline, "root="))
+				fastboot_setup_system_boot_args(avb_out_data->ab_suffix, false);
+			else
+				fastboot_setup_system_boot_args(avb_out_data->ab_suffix, true);
+		}
 #endif
 		image_size = avb_loadpart->data_size;
-		memcpy((void *)(ulong)(hdr->kernel_addr - hdr->page_size), (void *)hdr, image_size);
 	} else if (lock_status == FASTBOOT_LOCK) { /* && verify fail */
 		/* if in lock state, verify enforce fail */
 		printf(" verify FAIL, state: LOCK\n");
 		goto fail;
-	} else { /* lock_status == FASTBOOT_UNLOCK && verify fail */
+	} else { /* lock_status == FASTBOOT_UNLOCK && get unacceptable verify fail */
 		/* if in unlock state, log the verify state */
 		printf(" verify FAIL, state: UNLOCK\n");
 #endif
@@ -1666,7 +1682,7 @@
 		setenv("bootargs_sec", bootargs_sec);
 #ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT
 		if(!is_recovery_mode)
-			fastboot_setup_system_boot_args(slot);
+			fastboot_setup_system_boot_args(slot, true);
 #endif
 #ifdef CONFIG_FASTBOOT_LOCK
 	}
@@ -1676,8 +1692,14 @@
 	hdrload = (struct andr_img_hdr *)(ulong)(hdr->kernel_addr - hdr->page_size);
 	check_image_arm64  = image_arm64((void *)(ulong)hdrload->kernel_addr);
 
+#ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT
+	if (is_recovery_mode)
+		memcpy((void *)(ulong)hdrload->ramdisk_addr, (void *)(ulong)hdrload->kernel_addr
+				+ ALIGN(hdrload->kernel_size,hdrload->page_size), hdrload->ramdisk_size);
+#else
 	memcpy((void *)(ulong)hdrload->ramdisk_addr, (void *)(ulong)hdrload->kernel_addr
 			+ ALIGN(hdrload->kernel_size,hdrload->page_size), hdrload->ramdisk_size);
+#endif
 
 #ifdef CONFIG_OF_LIBFDT
 	bool fdt_loaded = false;
@@ -1718,8 +1740,14 @@
 	sprintf(ramdisk_addr, "0x%x:0x%x", hdrload->ramdisk_addr, hdrload->ramdisk_size);
 	sprintf(fdt_addr, "0x%x", hdrload->second_addr);
 
+/* no need to pass ramdisk addr for normal boot mode when enable CONFIG_SYSTEM_RAMDISK_SUPPORT*/
+#ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT
+	if (!is_recovery_mode)
+		boot_args[2] = NULL;
+#endif
+	/* we should free the avb_out_data but should not free the bootimage */
 	if (avb_out_data != NULL)
-		avb_slot_verify_data_free(avb_out_data);
+		avb_slot_verify_data_free_fast(avb_out_data);
 
 #ifdef CONFIG_IMX_TRUSTY_OS
 	/* put ql-tipc to release resource for Linux */
@@ -2733,7 +2761,6 @@
 	fastboot_tx_write_str("OKAY");
 }
 
-
 #ifdef CONFIG_FASTBOOT_LOCK
 
 int do_lock_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
@@ -2820,28 +2847,33 @@
 		    FASTBOOT_BOOTLOADER_VBOOT_KEY,
 		    strlen(FASTBOOT_BOOTLOADER_VBOOT_KEY))) {
 		strcpy(response, "OKAY");
-	} else if (!strncmp(cmd + len - 15, "unlock_critical", 15)) {
+	} else if (!strncmp(cmd + len - strlen("unlock_critical"),
+				"unlock_critical", strlen("unlock_critical"))) {
 #else
-	if (!strncmp(cmd + len - 15, "unlock_critical", 15)) {
+	if (!strncmp(cmd + len - strlen("unlock_critical"),
+				"unlock_critical", strlen("unlock_critical"))) {
 #endif
 		strcpy(response, "OKAY");
-	} else if (!strncmp(cmd + len - 13, "lock_critical", 13)) {
+	} else if (!strncmp(cmd + len - strlen("lock_critical"),
+				"lock_critical", strlen("lock_critical"))) {
 		strcpy(response, "OKAY");
-	} else if (!strncmp(cmd + len - 6, "unlock", 6)) {
+	} else if (!strncmp(cmd + len - strlen("unlock"),
+				"unlock", strlen("unlock"))) {
 		printf("flashing unlock.\n");
 		status = do_fastboot_unlock(false);
 		if (status != FASTBOOT_LOCK_ERROR)
 			strcpy(response, "OKAY");
 		else
 			strcpy(response, "FAIL unlock device failed.");
-	} else if (!strncmp(cmd + len - 4, "lock", 4)) {
+	} else if (!strncmp(cmd + len - strlen("lock"), "lock", strlen("lock"))) {
 		printf("flashing lock.\n");
 		status = do_fastboot_lock();
 		if (status != FASTBOOT_LOCK_ERROR)
 			strcpy(response, "OKAY");
 		else
 			strcpy(response, "FAIL lock device failed.");
-	} else if (!strncmp(cmd + len - 18, "get_unlock_ability", 18)) {
+	} else if (!strncmp(cmd + len - strlen("get_unlock_ability"),
+				"get_unlock_ability", strlen("get_unlock_ability"))) {
 		result = fastboot_lock_enable();
 		if (result == FASTBOOT_UL_ENABLE) {
 			fastboot_tx_write_more("INFO1");
@@ -3014,11 +3046,9 @@
 #ifdef CONFIG_FSL_FASTBOOT
 static void cb_reboot_bootloader(struct usb_ep *ep, struct usb_request *req)
 {
-	fastboot_tx_write_str("OKAY");
-
-	udelay(1000000);
 	enable_fastboot_command();
-	do_reset(NULL, 0, 0, NULL);
+        fastboot_func->in_req->complete = compl_do_reset;
+        fastboot_tx_write_str("OKAY");
 }
 #endif
 
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 2675a8f..fb93ea2 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -467,6 +467,29 @@
 	BUG();
 }
 
+static void reset_ep(struct usb_device *udev, int ep_index)
+{
+	struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
+	struct xhci_ring *ring =  ctrl->devs[udev->slot_id]->eps[ep_index].ring;
+	union xhci_trb *event;
+
+	xhci_queue_command(ctrl, NULL, udev->slot_id, ep_index, TRB_RESET_EP);
+
+	event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+	BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
+		!= udev->slot_id || GET_COMP_CODE(le32_to_cpu(
+		event->event_cmd.status)) != COMP_SUCCESS);
+	xhci_acknowledge_event(ctrl);
+
+	xhci_queue_command(ctrl, (void *)((uintptr_t)ring->enqueue |
+		ring->cycle_state), udev->slot_id, ep_index, TRB_SET_DEQ);
+	event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+	BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
+		!= udev->slot_id || GET_COMP_CODE(le32_to_cpu(
+		event->event_cmd.status)) != COMP_SUCCESS);
+	xhci_acknowledge_event(ctrl);
+}
+
 /*
  * Stops transfer processing for an endpoint and throws away all unprocessed
  * TRBs by setting the xHC's dequeue pointer to our enqueue pointer. The next
@@ -554,6 +577,7 @@
 	int start_cycle;
 	u32 field = 0;
 	u32 length_field = 0;
+	u32 ep_state;
 	struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
 	int slot_id = udev->slot_id;
 	int ep_index;
@@ -611,11 +635,15 @@
 	 * prepare_trasfer() as there in 'Linux' since we are not
 	 * maintaining multiple TDs/transfer at the same time.
 	 */
-	ret = prepare_ring(ctrl, ring,
-			   le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK);
+	ep_state = le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK;
+	ret = prepare_ring(ctrl, ring, ep_state);
 	if (ret < 0)
 		return ret;
 
+	/* For halted EP, reset it to stopped state and set TR Dequeue Pointer */
+	if (ep_state == EP_STATE_HALTED)
+		reset_ep(udev, ep_index);
+
 	/*
 	 * Don't give the first TRB to the hardware (by toggling the cycle bit)
 	 * until we've finished creating all the other TRBs.  The ring's cycle
@@ -746,6 +774,7 @@
 	int num_trbs;
 	u32 field;
 	u32 length_field;
+	u32 ep_state;
 	u64 buf_64 = 0;
 	struct xhci_generic_trb *start_trb;
 	struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
@@ -797,12 +826,16 @@
 	 * prepare_trasfer() as there in 'Linux' since we are not
 	 * maintaining multiple TDs/transfer at the same time.
 	 */
-	ret = prepare_ring(ctrl, ep_ring,
-				le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK);
 
+	ep_state = le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK;
+	ret = prepare_ring(ctrl, ep_ring, ep_state);
 	if (ret < 0)
 		return ret;
 
+	/* For halted EP, reset it to stopped state and set TR Dequeue Pointer */
+	if (ep_state == EP_STATE_HALTED)
+		reset_ep(udev, ep_index);
+
 	/*
 	 * Don't give the first TRB to the hardware (by toggling the cycle bit)
 	 * until we've finished creating all the other TRBs.  The ring's cycle
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index ade687f..43c68a5 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -457,6 +457,13 @@
 	help
 	  Support for IMXDPU V1 display controller for i.MX8 processors.
 
+config VIDEO_IMXDCSS
+	bool "i.MX8 DCSS display support"
+	default n
+	depends on VIDEO && IMX8M
+	help
+	  Support for DCSS display controller for i.MX8 processors.
+
 config VIDEO_IMX_HDP_LOAD
 	bool "i.MX8 HDMI/DP firmware loading"
 	default n
@@ -466,6 +473,13 @@
 	  firmware is copied from system memory to the HDMI/DP IRAM and
 	  DRAM memory.
 
+config VIDEO_IMX8_HDMI
+	bool "i.MX8 HDMI Splash screen"
+	default n
+	depends on VIDEO && IMX8M
+	help
+	  Support for HDMI i.MX8 processors.
+
 config MXC_EPDC
 	bool "i.MX EPDC support"
 	depends on LCD && (MX7 || MX6)
diff --git a/drivers/video/imx/Makefile b/drivers/video/imx/Makefile
index 0ec6e0e..5c243af 100644
--- a/drivers/video/imx/Makefile
+++ b/drivers/video/imx/Makefile
@@ -1,8 +1,9 @@
 #
-# Copyright 2017 NXP
+# Copyright 2017-2018 NXP
 #
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
 UBOOTINCLUDE += -I$(srctree)/drivers/video/imx/hdp
-obj-$(CONFIG_VIDEO_IMX_HDP_LOAD) += hdpload.o hdp/
+obj-$(CONFIG_VIDEO_IMX_HDP_LOAD) += hdp_load.o hdp/
+obj-$(CONFIG_VIDEO_IMX8_HDMI) += hdp.o imx8_hdmi.o hdp/
diff --git a/drivers/video/imx/hdp.c b/drivers/video/imx/hdp.c
new file mode 100644
index 0000000..b43d48a
--- /dev/null
+++ b/drivers/video/imx/hdp.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/imx-common/video.h>
+#include <asm/arch/video_common.h>
+#include <imx8_hdmi.h>
+
+int do_hdp(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	if (argc < 2)
+		return 0;
+
+	if (strncmp(argv[1], "colorbar", 8) == 0) {
+		GraphicDevice *gdev;
+		struct video_mode_settings *vm;
+
+		gdev = imx8m_get_gd();
+		vm = imx8m_get_gmode();
+		imx8m_show_gmode();
+
+		imx8m_create_color_bar(
+			(void *)((uint64_t)gdev->frameAdrs),
+			vm);
+		printf("colorbar test\n");
+	} else if (strncmp(argv[1], "stop", 4) == 0) {
+		imx8_hdmi_disable();
+		printf("stopping hdmi\n");
+	} else {
+		printf("test error argc %d\n", argc);
+	}
+
+	return 0;
+}
+/***************************************************/
+
+U_BOOT_CMD(
+	hdp,  CONFIG_SYS_MAXARGS, 1, do_hdp,
+	"hdmi/dp display test commands",
+	"[<command>] ...\n"
+	"colorbar - display a colorbar pattern\n"
+	);
diff --git a/drivers/video/imx/hdp/API_AFE.c b/drivers/video/imx/hdp/API_AFE.c
new file mode 100644
index 0000000..7b778cd
--- /dev/null
+++ b/drivers/video/imx/hdp/API_AFE.c
@@ -0,0 +1,115 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE.c
+ *
+ ******************************************************************************
+ */
+
+#include "address.h"
+#include "API_AFE.h"
+#include "util.h"
+#ifndef __UBOOT__
+#include <stdio.h>
+#endif
+
+void afe_write(unsigned int offset, unsigned short val)
+{
+#ifdef EXTERNAL_AFE
+	cdn_phapb_write(offset << 2, val);
+#else
+	CDN_API_STATUS sts;
+
+	sts = cdn_api_general_write_register_blocking(
+		ADDR_AFE + (offset << 2), val);
+
+	if (sts != CDN_OK) {
+		printf("CDN_API_General_Write_Register_blocking(0x%.8X, 0x%.8X) returned %d\n",
+		       offset,
+		       val,
+		       (int)sts);
+	}
+#endif
+}
+
+unsigned short afe_read(unsigned int offset)
+{
+	GENERAL_READ_REGISTER_RESPONSE resp;
+
+#ifdef EXTERNAL_AFE
+	cdn_phapb_read(offset << 2, &resp.val);
+#else
+	CDN_API_STATUS sts;
+
+	sts = cdn_api_general_read_register_blocking(
+		ADDR_AFE + (offset << 2), &resp);
+
+	if (sts != CDN_OK) {
+		printf("CDN_API_General_Read_Register_blocking(0x%.8X) returned %d\n",
+		       offset,
+		       (int)sts);
+	}
+#endif
+	return resp.val;
+}
+
+void set_field_value(reg_field_t *reg_field, u32 value)
+{
+	u8 length;
+	u32 max_value;
+	u32 trunc_val;
+	length = (reg_field->msb - reg_field->lsb + 1);
+
+	max_value = (1 << length) - 1;
+	if (value > max_value) {
+		trunc_val = value;
+		trunc_val &= (1 << length) - 1;
+		printf("set_field_value() Error! Specified value (0x%0X) exceeds field capacity - it will by truncated to 0x%0X (%0d-bit field - max value: %0d dec)\n",
+		       value, trunc_val, length, max_value);
+	} else {
+		reg_field->value = value;
+	}
+}
+
+int set_reg_value(reg_field_t reg_field)
+{
+	return reg_field.value << reg_field.lsb;
+}
diff --git a/drivers/video/imx/hdp/API_AFE.h b/drivers/video/imx/hdp/API_AFE.h
new file mode 100644
index 0000000..2ebdfb3
--- /dev/null
+++ b/drivers/video/imx/hdp/API_AFE.h
@@ -0,0 +1,99 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_AFE_H_
+#define API_AFE_H_
+#include "util.h"
+
+typedef enum {
+	AFE_LINK_RATE_1_6 = 0x6,  /* 1.62 Gb/s */
+	AFE_LINK_RATE_2_1 = 0x8,  /* 2.16 Gb/s */
+	AFE_LINK_RATE_2_4 = 0x9,  /* 2.43 Gb/s */
+	AFE_LINK_RATE_2_7 = 0xA,  /* 2.70 Gb/s */
+	AFE_LINK_RATE_3_2 = 0xC,  /* 3.24 Gb/s */
+	AFE_LINK_RATE_4_3 = 0x10, /* 4.32 Gb/s */
+	AFE_LINK_RATE_5_4 = 0x14, /* 5.40 Gb/s */
+	AFE_LINK_RATE_8_1 = 0x1E, /* 8.10 Gb/s */
+} ENUM_AFE_LINK_RATE;
+
+/* Some of the PHY programming sequences */
+/* depend on the reference clock frequency. */
+/* Variable of this type is used to control */
+/* the programming flow. */
+typedef enum {
+	REFCLK_24MHZ,
+	REFCLK_27MHZ
+} REFCLK_FREQ;
+
+typedef enum {
+	CLK_RATIO_1_1,
+	CLK_RATIO_5_4,
+	CLK_RATIO_3_2,
+	CLK_RATIO_2_1,
+	CLK_RATIO_1_2,
+	CLK_RATIO_5_8,
+	CLK_RATIO_3_4
+} clk_ratio_t;
+
+typedef struct {
+	u32 value;
+	u8 lsb;
+	u8 msb;
+} reg_field_t;
+
+unsigned char AFE_check_rate_supported(ENUM_AFE_LINK_RATE rate);
+void afe_write(unsigned int offset, unsigned short val);
+unsigned short afe_read(unsigned int offset);
+void AFE_init(int num_lanes, ENUM_AFE_LINK_RATE link_rate);
+void AFE_power(int num_lanes, ENUM_AFE_LINK_RATE link_rate);
+
+/*extern int cdn_phapb_read(unsigned int addr, unsigned int *value);*/
+/*extern int cdn_phapb_write(unsigned int addr, unsigned int value);*/
+void set_field_value(reg_field_t *reg_field, u32 value);
+int set_reg_value(reg_field_t reg_field);
+
+#endif
+
diff --git a/drivers/video/imx/hdp/API_AFE_t28hpc_hdmitx.c b/drivers/video/imx/hdp/API_AFE_t28hpc_hdmitx.c
new file mode 100644
index 0000000..933ecfa
--- /dev/null
+++ b/drivers/video/imx/hdp/API_AFE_t28hpc_hdmitx.c
@@ -0,0 +1,1863 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE_t28hpc_hdmitx.c
+ *
+ ******************************************************************************
+ */
+
+#include "API_AFE_t28hpc_hdmitx.h"
+#include "API_AFE.h"
+#include "externs.h"
+
+#ifndef DEBUG
+static inline void write16(uint32_t addr, uint16_t val)
+{
+	afe_write(addr, val);
+}
+
+static inline uint16_t read16(uint32_t addr)
+{
+	return afe_read(addr);
+}
+#else
+#define  write16(addr, val) __write16(addr, val, __LINE__)
+static inline void __write16(uint32_t addr, uint16_t val, int  line)
+{
+	afe_write(addr, val);
+	debug("write16():%4d Writting value 0x%04X at address 0x%05X (0x%04X)\n",
+	      line, val, (0x20000 * 4) + (addr << 2), addr);
+}
+#define  read16(addr) __read16(addr, __LINE__)
+static inline uint16_t __read16(uint32_t addr, int  line)
+{
+	debug("read16():%5d Reading from address 0x%05X (0x%04X)\n",
+	      line, (0x20000 * 4) + (addr << 2), addr);
+	return afe_read(addr);
+}
+
+#endif
+
+static char inside(u32 value, u32 left_sharp_corner,
+	u32 right_sharp_corner)
+{
+	if (value < left_sharp_corner)
+		return false;
+	if (value > right_sharp_corner)
+		return false;
+	return true;
+}
+
+void aux_cfg_t28hpc(void)
+{
+	write16(0x5025, 0x0001);
+
+	write16(0x5024, 36);
+
+	write16(0x5021, 0x0100);
+	write16(0x5021, 0x0300);
+	write16(0x5026, 0x0000);
+	write16(0x5020, 0x2008);
+	write16(0x5020, 0x2018);
+	write16(0x5020, 0xA018);
+	write16(0x5021, 0x030C);
+	write16(0x5029, 0x0000);
+	write16(0x5027, 0x4001);
+	write16(0x5020, 0xA098);
+	write16(0x5020, 0xA198);
+	write16(0x5021, 0x030D);
+	write16(0x5021, 0x030F);
+}
+
+int phy_cfg_t28hpc(int num_lanes, VIC_MODES vic_mode, int bpp,
+	VIC_PXL_ENCODING_FORMAT format, bool pixel_clk_from_phy)
+{
+	const int phy_reset_workaround = 1;
+	unsigned int vco_freq;
+	unsigned char k;
+	uint32_t reg_val;
+	uint32_t pixel_freq_khz = vic_table[vic_mode][PIXEL_FREQ_KHZ];
+	uint32_t character_clock_ratio_num = 1;
+	uint32_t character_clock_ratio_den = 1;
+	uint32_t character_freq_khz;
+	const unsigned int refclk_freq_khz = 27000;
+	unsigned int ftemp, ftemp2;
+
+	clk_ratio_t clk_ratio = 0;
+	reg_field_t cmnda_pll0_hs_sym_div_sel;
+	reg_field_t cmnda_pll0_ip_div;
+	reg_field_t cmnda_pll0_fb_div_low;
+	reg_field_t cmnda_pll0_fb_div_high;
+	reg_field_t cmn_ref_clk_dig_div;
+	reg_field_t divider_scaler;
+	reg_field_t cmnda_hs_clk_0_sel;
+	reg_field_t cmnda_hs_clk_1_sel;
+	reg_field_t tx_subrate;
+	reg_field_t voltage_to_current_coarse;
+	reg_field_t voltage_to_current;
+	reg_field_t ndac_ctrl;
+	reg_field_t pmos_ctrl;
+	reg_field_t ptat_ndac_ctrl;
+	reg_field_t charge_pump_gain;
+	reg_field_t vco_ring_select;
+	reg_field_t pll_feedback_divider_total;
+	reg_field_t cmnda_pll0_pxdiv_high;
+	reg_field_t cmnda_pll0_pxdiv_low;
+	reg_field_t coarse_code;
+	reg_field_t v2i_code;
+	reg_field_t vco_cal_code;
+
+	cmnda_pll0_fb_div_high.value = 0x00A;
+	ftemp = pixel_freq_khz;
+
+	debug(" VIC %d, pixel clock %u kHz\n", vic_mode, ftemp);
+
+	/* Set field position */
+	cmnda_pll0_hs_sym_div_sel.msb = 9;
+	cmnda_pll0_hs_sym_div_sel.lsb = 8;
+	cmnda_pll0_ip_div.msb = 7;
+	cmnda_pll0_ip_div.lsb = 0;
+	cmnda_pll0_fb_div_low.msb = 9;
+	cmnda_pll0_fb_div_low.lsb = 0;
+	cmnda_pll0_fb_div_high.msb = 9;
+	cmnda_pll0_fb_div_high.lsb = 0;
+	cmn_ref_clk_dig_div.msb = 13;
+	cmn_ref_clk_dig_div.lsb = 12;
+	divider_scaler.msb = 14;
+	divider_scaler.lsb = 12;
+	cmnda_hs_clk_0_sel.msb = 1;
+	cmnda_hs_clk_0_sel.lsb = 0;
+	cmnda_hs_clk_1_sel.msb = 1;
+	cmnda_hs_clk_1_sel.lsb = 0;
+	tx_subrate.msb = 2;
+	tx_subrate.lsb = 0;
+	voltage_to_current_coarse.msb = 2;
+	voltage_to_current_coarse.lsb = 0;
+	voltage_to_current.msb = 5;
+	voltage_to_current.lsb = 4;
+	ndac_ctrl.msb = 11;
+	ndac_ctrl.lsb = 8;
+	pmos_ctrl.msb = 7;
+	pmos_ctrl.lsb = 0;
+	ptat_ndac_ctrl.msb = 5;
+	ptat_ndac_ctrl.lsb = 0;
+	charge_pump_gain.msb = 8;
+	charge_pump_gain.lsb = 0;
+	vco_ring_select.msb = 12;
+	vco_ring_select.lsb = 12;
+	pll_feedback_divider_total.msb = 9;
+	pll_feedback_divider_total.lsb = 0;
+	cmnda_pll0_pxdiv_high.msb = 9;
+	cmnda_pll0_pxdiv_high.lsb = 0;
+	cmnda_pll0_pxdiv_low.msb = 9;
+	cmnda_pll0_pxdiv_low.lsb = 0;
+	coarse_code.msb = 7;
+	coarse_code.lsb = 0;
+	v2i_code.msb = 3;
+	v2i_code.lsb = 0;
+	vco_cal_code.msb = 8;
+	vco_cal_code.lsb = 0;
+
+	if (phy_reset_workaround) {
+		/* register PHY_PMA_ISOLATION_CTRL */
+		write16(0xC81F, 0xD000); /*  enable PHY iso mode only for CMN */
+		/* register PHY_PMA_ISO_PLL_CTRL1 */
+		reg_val = read16(0xC812);
+		reg_val &= 0xFF00;
+		reg_val |= 0x0012;
+		/* set pll0_clk_datart1_div/pll0_clk_datart0_div dividers */
+		write16(0xC812, reg_val);
+		/* register PHY_ISO_CMN_CTRL */
+		/* assert PHY reset from isolation register */
+		write16(0xC010, 0x0000);
+		/* register PHY_PMA_ISO_CMN_CTRL */
+		write16(0xC810, 0x0000);        /* assert PMA CMN reset */
+		/* register XCVR_DIAG_BIDI_CTRL */
+		for (k = 0; k < num_lanes; k++)
+			write16(0x40E8 | (k << 9), 0x00FF);
+	}
+	/*---------------------------------------------------------------
+	 * Describing Task phy_cfg_hdp
+	 * --------------------------------------------------------------*/
+	/* register PHY_PMA_CMN_CTRL1 */
+	reg_val = read16(0xC800);
+	reg_val &= 0xFFF7;
+	reg_val |= 0x0008;
+	write16(0xC800, reg_val);
+
+	/* register CMN_DIAG_PLL0_TEST_MODE */
+	write16(0x01C4, 0x0020);
+	/* register CMN_PSM_CLK_CTRL */
+	write16(0x0061, 0x0016);
+
+	switch (format) {
+	case YCBCR_4_2_2:
+		clk_ratio = CLK_RATIO_1_1;
+		character_clock_ratio_num = 1;
+		character_clock_ratio_den = 1;
+		break;
+	case YCBCR_4_2_0:
+		switch (bpp) {
+		case 8:
+			clk_ratio = CLK_RATIO_1_2;
+			character_clock_ratio_num = 1;
+			character_clock_ratio_den = 2;
+			break;
+		case 10:
+			clk_ratio = CLK_RATIO_5_8;
+			character_clock_ratio_num = 5;
+			character_clock_ratio_den = 8;
+			break;
+		case 12:
+			clk_ratio = CLK_RATIO_3_4;
+			character_clock_ratio_num = 3;
+			character_clock_ratio_den = 4;
+			break;
+		case 16:
+			clk_ratio = CLK_RATIO_1_1;
+			character_clock_ratio_num = 1;
+			character_clock_ratio_den = 1;
+			break;
+		default:
+			debug("Invalid ColorDepth\n");
+		}
+		break;
+
+	default:
+		switch (bpp) {
+			/* Assume RGB */
+		case 10:
+			clk_ratio = CLK_RATIO_5_4;
+			character_clock_ratio_num = 5;
+			character_clock_ratio_den = 4;
+			break;
+		case 12:
+			clk_ratio = CLK_RATIO_3_2;
+			character_clock_ratio_num = 3;
+			character_clock_ratio_den = 2;
+			break;
+		case 16:
+			clk_ratio = CLK_RATIO_2_1;
+			character_clock_ratio_num = 2;
+			character_clock_ratio_den = 1;
+			break;
+		default:
+			clk_ratio = CLK_RATIO_1_1;
+			character_clock_ratio_num = 1;
+			character_clock_ratio_den = 1;
+		}
+	}
+
+	character_freq_khz = pixel_freq_khz *
+		character_clock_ratio_num / character_clock_ratio_den;
+	ftemp = pixel_freq_khz;
+	ftemp2 = character_freq_khz;
+	debug("Pixel clock frequency: %u kHz, character clock frequency: %u, color depth is %0d-bit.\n",
+	       ftemp, ftemp2, bpp);
+	if (pixel_clk_from_phy == 0) {
+		/* -----------------------------------------------------------
+		 * Describing Task phy_cfg_hdmi_pll0_0pt5736 (Clock is input)
+		 * -----------------------------------------------------------*/
+
+		/* register CMN_PLL0_VCOCAL_INIT_TMR */
+		write16(0x0084, 0x0064);
+		/* register CMN_PLL0_VCOCAL_ITER_TMR */
+		write16(0x0085, 0x000A);
+		/* register PHY_HDP_CLK_CTL */
+		reg_val = read16(0xC009);
+		reg_val &= 0x00FF;
+		reg_val |= 0x1200;
+		write16(0xC009, reg_val);
+
+		switch (clk_ratio) {
+		case CLK_RATIO_1_1:
+			if (inside(pixel_freq_khz, 340000, 600000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x3C);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x24A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x06);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						600);
+			} else if (inside(pixel_freq_khz, 170000, 340000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x22);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x146);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x07);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						340);
+			} else if (inside(pixel_freq_khz, 85000, 170000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				set_field_value(&cmnda_pll0_ip_div, 0x11);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x146);
+				set_field_value(&cmn_ref_clk_dig_div, 0x00);
+				set_field_value(&divider_scaler, 0x07);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						340);
+			} else if (inside(pixel_freq_khz, 42500, 85000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				set_field_value(&cmnda_pll0_ip_div, 0x08);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x132);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						320);
+			} else if (inside(pixel_freq_khz, 25000, 42500)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				set_field_value(&cmnda_pll0_ip_div, 0x05);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x182);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						400);
+			} else {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			}
+			break;
+
+		case CLK_RATIO_5_4:
+			if (inside(pixel_freq_khz, 272000, 480000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x30);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x24A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x05);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						600);
+			} else if (inside(pixel_freq_khz, 136000, 272000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x1A);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x137);
+				set_field_value(&cmn_ref_clk_dig_div, 0x02);
+				set_field_value(&divider_scaler, 0x04);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						325);
+			} else if (inside(pixel_freq_khz, 68000, 136000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				set_field_value(&cmnda_pll0_ip_div, 0x0D);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x137);
+				set_field_value(&cmn_ref_clk_dig_div, 0x02);
+				set_field_value(&divider_scaler, 0x02);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						325);
+			} else if (inside(pixel_freq_khz, 34000, 68000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				set_field_value(&cmnda_pll0_ip_div, 0x06);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x11E);
+				set_field_value(&cmn_ref_clk_dig_div, 0x02);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						300);
+			} else if (inside(pixel_freq_khz, 25000, 34000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x182);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						400);
+			} else {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			}
+			break;
+		case CLK_RATIO_3_2:
+			if (inside(pixel_freq_khz, 226000, 400000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x28);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x24A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x04);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						600);
+			} else if (inside(pixel_freq_khz, 113000, 226000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x16);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x13C);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x05);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						330);
+			} else if (inside(pixel_freq_khz, 56000, 113000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				set_field_value(&cmnda_pll0_ip_div, 0x0B);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x13C);
+				set_field_value(&cmn_ref_clk_dig_div, 0x00);
+				set_field_value(&divider_scaler, 0x05);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						330);
+			} else if (inside(pixel_freq_khz, 28000, 56000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				set_field_value(&cmnda_pll0_ip_div, 0x06);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x15A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x02);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						360);
+			} else if (inside(pixel_freq_khz, 25000, 28000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x15A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						360);
+			} else {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			}
+			break;
+		case CLK_RATIO_2_1:
+			if (inside(pixel_freq_khz, 170000, 300000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x22);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x29A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x06);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						680);
+			} else if (inside(pixel_freq_khz, 85000, 170000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x11);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x146);
+				set_field_value(&cmn_ref_clk_dig_div, 0x00);
+				set_field_value(&divider_scaler, 0x07);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						340);
+			} else if (inside(pixel_freq_khz, 42500, 85000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				set_field_value(&cmnda_pll0_ip_div, 0x08);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x132);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						320);
+			} else if (inside(pixel_freq_khz, 25000, 42500)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				set_field_value(&cmnda_pll0_ip_div, 0x05);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x182);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						400);
+			} else {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			}
+			break;
+		case CLK_RATIO_1_2:
+			if (!(inside(pixel_freq_khz, 594000, 594000))) {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			} else {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				set_field_value(&cmnda_pll0_ip_div, 0x3C);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x24A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x06);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						600);
+			}
+			break;
+		case CLK_RATIO_5_8:
+			if (!(inside(pixel_freq_khz, 594000, 594000))) {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			} else {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x3C);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x169);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x06);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						375);
+			}
+			break;
+		case CLK_RATIO_3_4:
+			if (!(inside(pixel_freq_khz, 594000, 594000))) {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			} else {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x3C);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x1B4);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x06);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						450);
+			}
+			break;
+		}
+		vco_freq =
+			pixel_freq_khz * pll_feedback_divider_total.value /
+			cmnda_pll0_ip_div.value;
+		ftemp = vco_freq;
+		debug("VCO frequency is %u kHz\n", ftemp);
+
+		if (inside(vco_freq, 1700000, 2000000)) {
+			set_field_value(&voltage_to_current_coarse, 0x04);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x09);
+			set_field_value(&ptat_ndac_ctrl, 0x09);
+			switch (pll_feedback_divider_total.value) {
+			case 300:
+				set_field_value(&charge_pump_gain, 0x82);
+				break;
+			case 320:
+				set_field_value(&charge_pump_gain, 0x83);
+				break;
+			case 325:
+				set_field_value(&charge_pump_gain, 0x83);
+				break;
+			case 330:
+				set_field_value(&charge_pump_gain, 0x84);
+				break;
+			case 340:
+				set_field_value(&charge_pump_gain, 0x84);
+				break;
+			case 360:
+				set_field_value(&charge_pump_gain, 0x86);
+				break;
+			case 400:
+				set_field_value(&charge_pump_gain, 0xA2);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 2000000, 2400000)) {
+			set_field_value(&voltage_to_current_coarse, 0x04);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x09);
+			set_field_value(&ptat_ndac_ctrl, 0x09);
+			switch (pll_feedback_divider_total.value) {
+			case 300:
+				set_field_value(&charge_pump_gain, 0x47);
+				break;
+			case 320:
+				set_field_value(&charge_pump_gain, 0x4B);
+				break;
+			case 325:
+				set_field_value(&charge_pump_gain, 0x4C);
+				break;
+			case 330:
+				set_field_value(&charge_pump_gain, 0x80);
+				break;
+			case 340:
+				set_field_value(&charge_pump_gain, 0x81);
+				break;
+			case 360:
+				set_field_value(&charge_pump_gain, 0x82);
+				break;
+			case 400:
+				set_field_value(&charge_pump_gain, 0x84);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 2400000, 2800000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			switch (pll_feedback_divider_total.value) {
+			case 300:
+				set_field_value(&charge_pump_gain, 0x43);
+				break;
+			case 320:
+				set_field_value(&charge_pump_gain, 0x45);
+				break;
+			case 325:
+				set_field_value(&charge_pump_gain, 0x45);
+				break;
+			case 330:
+				set_field_value(&charge_pump_gain, 0x45);
+				break;
+			case 340:
+				set_field_value(&charge_pump_gain, 0x86);
+				break;
+			case 360:
+				set_field_value(&charge_pump_gain, 0x4A);
+				break;
+			case 400:
+				set_field_value(&charge_pump_gain, 0x81);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 2800000, 3400000)) {
+			set_field_value(&voltage_to_current_coarse, 0x06);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			switch (pll_feedback_divider_total.value) {
+			case 300:
+				set_field_value(&charge_pump_gain, 0x3D);
+				break;
+			case 320:
+				set_field_value(&charge_pump_gain, 0x41);
+				break;
+			case 325:
+				set_field_value(&charge_pump_gain, 0x41);
+				break;
+			case 330:
+				set_field_value(&charge_pump_gain, 0x41);
+				break;
+			case 340:
+				set_field_value(&charge_pump_gain, 0x42);
+				break;
+			case 360:
+				set_field_value(&charge_pump_gain, 0x43);
+				break;
+			case 400:
+				set_field_value(&charge_pump_gain, 0x46);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 3400000, 3900000)) {
+			set_field_value(&voltage_to_current_coarse, 0x04);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x07);
+			set_field_value(&ptat_ndac_ctrl, 0x0F);
+			switch (pll_feedback_divider_total.value) {
+			case 375:
+				set_field_value(&charge_pump_gain, 0x41);
+				break;
+			case 600:
+				set_field_value(&charge_pump_gain, 0x82);
+				break;
+			case 680:
+				set_field_value(&charge_pump_gain, 0x85);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 3900000, 4500000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x07);
+			set_field_value(&ptat_ndac_ctrl, 0x0F);
+			switch (pll_feedback_divider_total.value) {
+			case 450:
+				set_field_value(&charge_pump_gain, 0x41);
+				break;
+			case 600:
+				set_field_value(&charge_pump_gain, 0x4B);
+				break;
+			case 680:
+				set_field_value(&charge_pump_gain, 0x82);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 4500000, 5200000)) {
+			set_field_value(&voltage_to_current_coarse, 0x06);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			switch (pll_feedback_divider_total.value) {
+			case 600:
+				set_field_value(&charge_pump_gain, 0x45);
+				break;
+			case 680:
+				set_field_value(&charge_pump_gain, 0x4A);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 5200000, 6000000)) {
+			set_field_value(&voltage_to_current_coarse, 0x07);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			switch (pll_feedback_divider_total.value) {
+			case 600:
+				set_field_value(&charge_pump_gain, 0x42);
+				break;
+			case 680:
+				set_field_value(&charge_pump_gain, 0x45);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else
+			debug("VCO frequency %u kHz is outside of the supported range\n",
+			       ftemp);
+
+		/* register CMN_DIAG_PLL0_INCLK_CTRL */
+		reg_val = set_reg_value(cmnda_pll0_hs_sym_div_sel);
+		reg_val |= set_reg_value(cmnda_pll0_ip_div);
+		write16(0x01CA, reg_val);
+		/* register CMN_DIAG_PLL0_FBL_OVRD */
+		reg_val = set_reg_value(cmnda_pll0_fb_div_low);
+		reg_val |= (1 << 15);
+		write16(0x01C1, reg_val);
+		/* register PHY_PMA_CMN_CTRL1 */
+		reg_val = read16(0xC800);
+		reg_val &= 0xCFFF;
+		reg_val |= set_reg_value(cmn_ref_clk_dig_div);
+		write16(0xC800, reg_val);
+		/* register CMN_CDIAG_REFCLK_CTRL */
+		reg_val = read16(0x0062);
+		reg_val &= 0x8FFF;
+		reg_val |= set_reg_value(divider_scaler);
+		reg_val |= 0x00C0;
+		write16(0x0062, reg_val);
+		/* register CMN_DIAG_HSCLK_SEL */
+		reg_val = read16(0x01E0);
+		reg_val &= 0xFF00;
+		reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 0;
+		reg_val |= (cmnda_hs_clk_1_sel.value >> 1) << 4;
+		write16(0x01E0, reg_val);
+
+		/* register XCVR_DIAG_HSCLK_SEL */
+		for (k = 0; k < num_lanes; k++) {
+			reg_val = read16(0x40E1 | (k << 9));
+			reg_val &= 0xCFFF;
+			reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 12;
+			write16(0x40E1 | (k << 9), reg_val);
+		}
+
+		/* register TX_DIAG_TX_CTRL */
+		for (k = 0; k < num_lanes; k++) {
+			reg_val = read16(0x41E0 | (k << 9));
+			reg_val &= 0xFF3F;
+			reg_val |= (tx_subrate.value >> 1) << 6;
+			write16(0x41E0 | (k << 9), reg_val);
+		}
+
+		/* register CMN_PLLSM0_USER_DEF_CTRL */
+		reg_val = set_reg_value(vco_ring_select);
+		write16(0x002F, reg_val);
+		/* register CMN_DIAG_PLL0_OVRD */
+		write16(0x01C2, 0x0000);
+		/* register CMN_DIAG_PLL0_FBH_OVRD */
+		reg_val = set_reg_value(cmnda_pll0_fb_div_high);
+		reg_val |= (1 << 15);
+		write16(0x01C0, reg_val);
+		/* register CMN_DIAG_PLL0_V2I_TUNE */
+		reg_val = set_reg_value(voltage_to_current_coarse);
+		reg_val |= set_reg_value(voltage_to_current);
+		write16(0x01C5, reg_val);
+		/* register CMN_DIAG_PLL0_PTATIS_TUNE1 */
+		reg_val = set_reg_value(pmos_ctrl);
+		reg_val |= set_reg_value(ndac_ctrl);
+		write16(0x01C8, reg_val);
+		/* register CMN_DIAG_PLL0_PTATIS_TUNE2 */
+		reg_val = set_reg_value(ptat_ndac_ctrl);
+		write16(0x01C9, reg_val);
+		/* register CMN_DIAG_PLL0_CP_TUNE */
+		reg_val = set_reg_value(charge_pump_gain);
+		write16(0x01C6, reg_val);
+		/* register CMN_DIAG_PLL0_LF_PROG */
+		write16(0x01C7, 0x0008);
+
+		/* register XCVR_DIAG_PLLDRC_CTRL */
+		for (k = 0; k < num_lanes; k++) {
+			reg_val = read16(0x40E0 | (k << 9));
+			reg_val &= 0xBFFF;
+			write16(0x40E0 | (k << 9), reg_val);
+		}
+
+	} else {
+		/* Describing task phy_cfg_hdmi_pll0_0pt099_ver2
+		   (Clock is OUTPUT) */
+		if (inside(pixel_freq_khz, 27000, 27000)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						240);
+				set_field_value(&cmnda_pll0_fb_div_low, 0xBC);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x30);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x26);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x26);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				break;
+			case CLK_RATIO_5_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						300);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x0EC);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x03C);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x030);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x030);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						360);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x11C);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x048);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x03A);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x03A);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						240);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x0BC);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x030);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x026);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x026);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			default:
+				break;
+			}
+		} else if (inside(pixel_freq_khz, 54000, 54000)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						480);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x17C);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x060);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x026);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x026);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				break;
+			case CLK_RATIO_5_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						400);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x13C);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x050);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x017);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x017);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						480);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x17C);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x060);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x01C);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x01C);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						240);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x0bc);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x030);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			default:
+				break;
+			}
+		} else if (inside(pixel_freq_khz, 74250, 74250)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x026);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x026);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				break;
+			case CLK_RATIO_5_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						550);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x1b4);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x06e);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x017);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x017);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x01c);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x01c);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						330);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x104);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x042);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			default:
+				break;
+			}
+		} else if (inside(pixel_freq_khz, 99000, 99000)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						440);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x15c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x058);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			case CLK_RATIO_5_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						275);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x0d8);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x037);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x00b);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x00a);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						330);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x104);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x042);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x00d);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x00d);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						440);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x15c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x058);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			default:
+				break;
+			}
+		} else if (inside(pixel_freq_khz, 148500, 148500)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			case CLK_RATIO_5_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						550);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x1b4);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x06e);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x00b);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x00a);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						495);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x188);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x063);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x00d);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x00d);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			default:
+				break;
+			}
+		} else if (inside(pixel_freq_khz, 198000, 198000)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						220);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x0ac);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x02c);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			case CLK_RATIO_5_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						550);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x1b4);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x06e);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x00b);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x00a);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						330);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x104);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x042);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x006);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x005);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						440);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x15c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x058);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x008);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x008);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			default:
+				break;
+			}
+		} else if (inside(pixel_freq_khz, 297000, 297000)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						330);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x104);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x042);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						495);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x188);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x063);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x006);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x005);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x008);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x008);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			default:
+				ftemp = pixel_freq_khz;
+				debug("This pixel clock frequency (%u kHz) is not supported with this (%0d-bit) color depth.\n",
+				       ftemp, bpp);
+			}
+		} else if (inside(pixel_freq_khz, 594000, 594000)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			case CLK_RATIO_1_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			case CLK_RATIO_5_8:
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						550);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x1b4);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x06e);
+				/* does not matter - pixel clock delivered to
+				   controller from SoC */
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+				/* does not matter - pixel clock delivered to
+				   controller from SoC */
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			case CLK_RATIO_3_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						495);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x188);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x063);
+				/* does not matter - pixel clock delivered to
+				   controller from SoC */
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+				/* does not matter - pixel clock delivered to
+				   controller from SoC */
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			default:
+				debug("This pixel clock frequency (%d KHz) is not supported with this (%0d-bit) color depth.\n",
+				       pixel_freq_khz, bpp);
+			}
+		} else {
+			ftemp = pixel_freq_khz;
+			debug("This pixel clock frequency (%u kHz) is not supported.\n",
+			       ftemp);
+		}
+
+		vco_freq =
+			refclk_freq_khz * pll_feedback_divider_total.value /
+			cmnda_pll0_ip_div.value;
+		ftemp = vco_freq;
+		debug("VCO frequency is %u kHz\n", ftemp);
+
+		if (inside(vco_freq, 1980000, 1980000)) {
+			set_field_value(&voltage_to_current_coarse, 0x04);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x09);
+			set_field_value(&ptat_ndac_ctrl, 0x09);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 160);
+			set_field_value(&v2i_code, 5);
+			set_field_value(&vco_cal_code, 183);
+		} else if (inside(vco_freq, 2160000, 2160000)) {
+			set_field_value(&voltage_to_current_coarse, 0x04);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x09);
+			set_field_value(&ptat_ndac_ctrl, 0x09);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 166);
+			set_field_value(&v2i_code, 6);
+			set_field_value(&vco_cal_code, 208);
+		} else if (inside(vco_freq, 2475000, 2475000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 167);
+			set_field_value(&v2i_code, 6);
+			set_field_value(&vco_cal_code, 209);
+		} else if (inside(vco_freq, 2700000, 2700000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			switch (pll_feedback_divider_total.value) {
+			case 300:
+				set_field_value(&charge_pump_gain, 0x042);
+				break;
+			case 400:
+				set_field_value(&charge_pump_gain, 0x04c);
+				break;
+			}
+			set_field_value(&coarse_code, 188);
+			set_field_value(&v2i_code, 6);
+			set_field_value(&vco_cal_code, 225);
+		} else if (inside(vco_freq, 2970000, 2970000)) {
+			set_field_value(&voltage_to_current_coarse, 0x06);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 183);
+			set_field_value(&v2i_code, 6);
+			set_field_value(&vco_cal_code, 225);
+		} else if (inside(vco_freq, 3240000, 3240000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			switch (pll_feedback_divider_total.value) {
+			case 360:
+				set_field_value(&charge_pump_gain, 0x042);
+				break;
+			case 480:
+				set_field_value(&charge_pump_gain, 0x04c);
+				break;
+			}
+			set_field_value(&coarse_code, 203);
+			set_field_value(&v2i_code, 7);
+			set_field_value(&vco_cal_code, 256);
+		} else if (inside(vco_freq, 3712500, 3712500)) {
+			set_field_value(&voltage_to_current_coarse, 0x04);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x07);
+			set_field_value(&ptat_ndac_ctrl, 0x0F);
+			set_field_value(&charge_pump_gain, 0x04c);
+			set_field_value(&coarse_code, 212);
+			set_field_value(&v2i_code, 7);
+			set_field_value(&vco_cal_code, 257);
+		} else if (inside(vco_freq, 3960000, 3960000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x07);
+			set_field_value(&ptat_ndac_ctrl, 0x0F);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 184);
+			set_field_value(&v2i_code, 6);
+			set_field_value(&vco_cal_code, 226);
+		} else if (inside(vco_freq, 4320000, 4320000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x07);
+			set_field_value(&ptat_ndac_ctrl, 0x0F);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 205);
+			set_field_value(&v2i_code, 7);
+			set_field_value(&vco_cal_code, 258);
+		} else if (inside(vco_freq, 4455000, 4455000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x07);
+			set_field_value(&ptat_ndac_ctrl, 0x0F);
+			switch (pll_feedback_divider_total.value) {
+			case 495:
+				set_field_value(&charge_pump_gain, 0x042);
+				break;
+			case 660:
+				set_field_value(&charge_pump_gain, 0x04c);
+				break;
+			}
+			set_field_value(&coarse_code, 219);
+			set_field_value(&v2i_code, 7);
+			set_field_value(&vco_cal_code, 272);
+		} else if (inside(vco_freq, 4950000, 4950000)) {
+			set_field_value(&voltage_to_current_coarse, 0x06);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 213);
+			set_field_value(&v2i_code, 7);
+			set_field_value(&vco_cal_code, 258);
+		} else if (inside(vco_freq, 5940000, 5940000)) {
+			set_field_value(&voltage_to_current_coarse, 0x07);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 244);
+			set_field_value(&v2i_code, 8);
+			set_field_value(&vco_cal_code, 292);
+		} else {
+			ftemp = vco_freq;
+			debug("Current vco_freq (%u kHz) is not supported.\n",
+			       ftemp);
+		}
+
+		/* register CMN_PLL0_VCOCAL_INIT_TMR */
+		write16(0x0084, 0x0064);
+		/* register CMN_PLL0_VCOCAL_ITER_TMR */
+		write16(0x0085, 0x000A);
+		/* register PHY_HDP_CLK_CTL */
+		reg_val = read16(0xC009);
+		reg_val &= 0x00FF;
+		reg_val |= 0x2 << 8;
+		reg_val |= 0x1 << 12;
+		write16(0xC009, reg_val);
+		/* register CMN_DIAG_PLL0_INCLK_CTRL */
+		reg_val = set_reg_value(cmnda_pll0_ip_div);
+		reg_val |= set_reg_value(cmnda_pll0_hs_sym_div_sel);
+		write16(0x01CA, reg_val);
+		/* register CMN_DIAG_PLL0_FBH_OVRD */
+		reg_val = set_reg_value(cmnda_pll0_fb_div_high);
+		reg_val |= (1 << 15);
+		write16(0x01C0, reg_val);
+		/* register CMN_DIAG_PLL0_FBL_OVRD */
+		reg_val = set_reg_value(cmnda_pll0_fb_div_low);
+		reg_val |= (1 << 15);
+		write16(0x01C1, reg_val);
+		/* register CMN_DIAG_PLL0_PXL_DIVL */
+		reg_val = set_reg_value(cmnda_pll0_pxdiv_low);
+		write16(0x01CC, reg_val);
+		/* register CMN_DIAG_PLL0_PXL_DIVH */
+		reg_val = set_reg_value(cmnda_pll0_pxdiv_high);
+		reg_val |= (1 << 15);
+		write16(0x01CB, reg_val);
+
+		/* register TX_DIAG_TX_CTRL */
+		for (k = 0; k < num_lanes; k++) {
+			reg_val = read16(0x41E0 | (k << 9));
+			reg_val &= 0xFF3F;
+			reg_val |= (tx_subrate.value >> 1) << 6;
+			write16(0x41E0 | (k << 9), reg_val);
+		}
+
+		/* register PHY_PMA_CMN_CTRL1 */
+		reg_val = read16(0xC800);
+		reg_val &= 0xCFFF;
+		reg_val |= set_reg_value(cmn_ref_clk_dig_div);
+		write16(0xC800, reg_val);
+		/* register CMN_CDIAG_REFCLK_CTRL */
+		reg_val = read16(0x0062);
+		reg_val &= 0x8FFF;
+		reg_val |= set_reg_value(divider_scaler);
+		reg_val |= 0x00C0;
+		write16(0x0062, reg_val);
+		/* register CMN_DIAG_HSCLK_SEL */
+		reg_val = read16(0x01E0);
+		reg_val &= 0xFF00;
+		reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 0;
+		reg_val |= (cmnda_hs_clk_1_sel.value >> 1) << 4;
+		write16(0x01E0, reg_val);
+		/* register CMN_PLLSM0_USER_DEF_CTRL */
+		reg_val = set_reg_value(vco_ring_select);
+		write16(0x002F, reg_val);
+
+		/* register XCVR_DIAG_HSCLK_SEL */
+		for (k = 0; k < num_lanes; k++) {
+			reg_val = read16(0x40E1 | (k << 9));
+			reg_val &= 0xCFFF;
+			reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 12;
+			write16(0x40E1 | (k << 9), reg_val);
+		}
+
+		/* register CMN_DIAG_PLL0_OVRD */
+		write16(0x01C2, 0x0000);
+		/* register CMN_DIAG_PLL0_V2I_TUNE */
+		reg_val = set_reg_value(voltage_to_current_coarse);
+		reg_val |= set_reg_value(voltage_to_current);
+		write16(0x01C5, reg_val);
+		/* register CMN_DIAG_PLL0_PTATIS_TUNE1 */
+		reg_val = set_reg_value(pmos_ctrl);
+		reg_val |= set_reg_value(ndac_ctrl);
+		write16(0x01C8, reg_val);
+		/* register CMN_DIAG_PLL0_PTATIS_TUNE2 */
+		reg_val = set_reg_value(ptat_ndac_ctrl);
+		write16(0x01C9, reg_val);
+		/* register CMN_PLL0_VCOCAL_START */
+		reg_val = read16(0x0081);
+		reg_val &= 0xFE00;
+		reg_val |= set_reg_value(vco_cal_code);
+		write16(0x0081, reg_val);
+		/* register CMN_DIAG_PLL0_CP_TUNE */
+		reg_val = set_reg_value(charge_pump_gain);
+		write16(0x01C6, reg_val);
+		/* register CMN_DIAG_PLL0_LF_PROG */
+		write16(0x01C7, 0x0008);
+
+		/* register XCVR_DIAG_PLLDRC_CTRL */
+		for (k = 0; k < num_lanes; k++) {
+			reg_val = read16(0x40E0 | (k << 9));
+			reg_val &= 0xBFFF;
+			write16(0x40E0 | (k << 9), reg_val);
+		}
+	}
+
+	/* Back to task phy_cfg_hdp */
+
+	/* register PHY_PMA_CMN_CTRL1 */
+	reg_val = read16(0xC800);
+	reg_val &= 0xFF8F;
+	/* for differential clock on the refclk_p and refclk_m
+	 * off chip pins: PHY_PMA_CMN_CTRL1[6:4]=3'b000 */
+	reg_val |= 0x0000;
+	write16(0xC800, reg_val);
+
+	/* register CMN_DIAG_ACYA */
+	write16(0x01FF, 0x0100);
+
+	if (phy_reset_workaround) {
+		/* register PHY_ISO_CMN_CTRL */
+		write16(0xC010, 0x0001);        /* Deassert PHY reset */
+		/* register PHY_PMA_ISO_CMN_CTRL */
+		write16(0xC810, 0x0003);
+		for (k = 0; k < num_lanes; k++) {
+			/* register XCVR_PSM_RCTRL */
+			write16(0x4001 | (k << 9), 0xFEFC);
+		}
+		/* register PHY_PMA_ISO_CMN_CTRL
+		 * Assert cmn_macro_pwr_en*/
+		write16(0xC810, 0x0013);
+
+		/* PHY_PMA_ISO_CMN_CTRL
+		 * wait for cmn_macro_pwr_en_ack*/
+		while (!(read16(0xC810) & (1 << 5)))
+			;
+
+		/* PHY_PMA_CMN_CTRL1 wait for cmn_ready */
+		while (!(read16(0xC800) & (1 << 0)))
+			;
+	} else {
+		for (k = 0; k < num_lanes; k++) {
+			/* register XCVR_PSM_RCTRL */
+			write16(0x4001 | (k << 9), 0xBEFC);
+		}
+	}
+	for (k = 0; k < num_lanes; k++) {
+		/* register TX_PSC_A0 */
+		write16(0x4100 | (k << 9), 0x6791);
+		/* register TX_PSC_A1 */
+		write16(0x4101 | (k << 9), 0x6790);
+		/* register TX_PSC_A2 */
+		write16(0x4102 | (k << 9), 0x0090);
+		/* register TX_PSC_A3 */
+		write16(0x4103 | (k << 9), 0x0090);
+		/* register RX_PSC_CAL */
+		reg_val = read16(0x8006 | (k << 9));
+		reg_val &= 0xFFBB;
+		write16(0x8006 | (k << 9), reg_val);
+		reg_val = read16(0x8000 | (k << 9));
+		reg_val &= 0xFFBB;
+		write16(0x8000 | (k << 9), reg_val);
+	}
+
+	/* End of task phy_cfg_hdp */
+	/* register PHY_HDP_MODE_CTL */
+	write16(0xC008, 0x0004);
+
+	aux_cfg_t28hpc();
+	return character_freq_khz;
+}
+
+int hdmi_tx_t28hpc_power_config_seq(int num_lanes)
+{
+	unsigned char k;
+
+	/* Configure the power state.
+	 * register TX_DIAG_ACYA */
+	for (k = 0; k < num_lanes; k++) {
+		/* register XCVR_PSM_CAL_TMR */
+		write16(0x41FF | (k << 9), 0x0001);
+	}
+
+	/* register PHY_DP_MODE_CTL */
+	while (!(read16(0xC008) & (1 << 6)))
+		;
+
+	/* PHY_DP_MODE_CTL */
+	write16(0xC008, (((0x0F << num_lanes) & 0x0F) << 12) | 0x0101);
+
+	/* PHY_DP_MODE_CTL */
+	while (!(read16(0xC008) & (1 << 4)))
+		;
+
+	return 0;
+}
diff --git a/drivers/video/imx/hdp/API_AFE_t28hpc_hdmitx.h b/drivers/video/imx/hdp/API_AFE_t28hpc_hdmitx.h
new file mode 100644
index 0000000..756c1d5
--- /dev/null
+++ b/drivers/video/imx/hdp/API_AFE_t28hpc_hdmitx.h
@@ -0,0 +1,64 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE_t28hpc_hdmitx.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_AFE_T28HPC_HDMITX_H_
+#define API_AFE_T28HPC_HDMITX_H_
+
+#ifndef __UBOOT__
+#include <assert.h>
+#include <stdint.h>
+#else
+#include <common.h>
+#endif
+#include "vic_table.h"
+#include "API_AFE.h"
+#include "externs.h"
+
+int phy_cfg_t28hpc(int num_lanes, VIC_MODES vic_mode, int bpp,
+		VIC_PXL_ENCODING_FORMAT format, bool pixel_clk_from_phy);
+int hdmi_tx_t28hpc_power_config_seq(int num_lanes);
+
+#endif
diff --git a/drivers/video/imx/hdp/API_AVI.c b/drivers/video/imx/hdp/API_AVI.c
new file mode 100644
index 0000000..d9346f2
--- /dev/null
+++ b/drivers/video/imx/hdp/API_AVI.c
@@ -0,0 +1,191 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AVI.c
+ *
+ ******************************************************************************
+ */
+
+#include "API_AVI.h"
+#include "API_Infoframe.h"
+
+CDN_API_STATUS cdn_api_set_avi(VIC_MODES vic_mode,
+	VIC_PXL_ENCODING_FORMAT color_mode,
+	BT_TYPE itu_ver)
+{
+	unsigned int active_slot = vic_table[vic_mode][H_BLANK];
+	unsigned int line_width = vic_table[vic_mode][H_TOTAL];
+	unsigned int hactive = line_width - active_slot + 1;
+	unsigned int vactive = vic_table[vic_mode][V_ACTIVE] + 1;
+
+	unsigned int hactive_l = hactive - 256 * ((unsigned int)hactive / 256);
+	unsigned int hactive_h = hactive / 256;
+	unsigned int vactive_l = vactive - 256 * ((unsigned int)vactive / 256);
+	unsigned int vactive_h = vactive / 256;
+
+	/* unsigned int packet; */
+
+	unsigned int packet_type = 0x82;
+	unsigned int packet_version = 0x2;
+	unsigned int packet_len = 0xd;
+	unsigned int packet_y = 0;
+	unsigned int packet_c = 0;
+	unsigned int packet_r = 0;
+	unsigned int packet_vic = 0;
+	unsigned int packet_pr = 0;
+	unsigned int packet_buf[18 / sizeof(unsigned int)];
+	unsigned char *packet = (unsigned char *)&packet_buf[0];
+	unsigned int packet_hb0 = 0;
+	unsigned int packet_hb1 = 0;
+	unsigned int packet_hb2 = 0;
+	unsigned int packet_pb0 = 0;
+	unsigned int packet_pb1 = 0;
+	unsigned int packet_pb2 = 0;
+	unsigned int packet_pb3 = 0;
+	unsigned int packet_pb4 = 0;
+	unsigned int packet_pb5 = 0;
+	unsigned int packet_pb6 = 0;
+	unsigned int packet_pb7 = 0;
+	unsigned int packet_pb8 = 0;
+	unsigned int packet_pb9 = 0;
+	unsigned int packet_pb10 = 0;
+	unsigned int packet_pb11 = 0;
+	unsigned int packet_pb12 = 0;
+	unsigned int packet_pb13 = 0;
+	unsigned int pb1_13_chksum = 0;
+	unsigned int packet_chksum = 0;
+
+	if (color_mode == PXL_RGB)
+		packet_y = 0;
+	else if (color_mode == YCBCR_4_4_4)
+		packet_y = 2;
+	else if (color_mode == YCBCR_4_2_2)
+		packet_y = 1;
+	else if (color_mode == YCBCR_4_2_0)
+		packet_y = 3;
+
+	/* Colorimetry:  Nodata=0 IT601=1 ITU709=2 */
+	if (itu_ver == BT_601)
+		packet_c = 1;
+	else if (itu_ver == BT_709)
+		packet_c = 2;
+	else
+		packet_c = 0;
+
+	unsigned int packet_a0 = 1;
+	unsigned int packet_b = 0;
+	unsigned int packet_s = 0;
+	unsigned int packet_sc = 0; /* Picture Scaling */
+
+	/* Active Format Aspec Ratio: Same As Picture = 0x8 4:3(Center)=0x9
+	   16:9=0xA 14:9=0xB */
+	packet_r = vic_table[vic_mode][VIC_R3_0];
+	/* Aspect Ratio: Nodata=0 4:3=1 16:9=2 */
+	unsigned int packet_m = 0;
+	/* Quantization Range Default=0 Limited Range=0x1 FullRange=0x2
+	   Reserved 0x3 */
+	unsigned int packet_q = 0;
+	/* Quantization Range 0=Limited Range  FullRange=0x1 Reserved 0x3/2 */
+	unsigned int packet_yq = 0;
+	/* Extended Colorimetry xvYCC601=0x0 xvYCC709=1 All other Reserved */
+	unsigned int packet_ec = 0;
+	/*IT content nodata=0 ITcontent=1 */
+	unsigned int packet_it = 0;
+	/* Video Code (CEA) */
+	packet_vic = vic_table[vic_mode][VIC];
+	/* Pixel Repetition 0 ... 9 (1-10) */
+	packet_pr = vic_table[vic_mode][VIC_PR];
+	/* Content Type */
+	unsigned int packet_cn = 0;
+
+	packet_hb0 = packet_type;
+	packet_hb1 = packet_version;
+	packet_hb2 = packet_len;
+
+	packet_pb1 = 32 * packet_y + 16 * packet_a0 + 4 * packet_b + packet_s;
+	packet_pb2 = 64 * packet_c + 16 * packet_m + packet_r;
+	packet_pb3 =
+		128 * packet_it + 16 * packet_ec + 4 * packet_q + packet_sc;
+	packet_pb4 = packet_vic;
+	packet_pb5 = 64 * packet_yq + 16 * packet_cn + packet_pr;
+	packet_pb6 = 0;
+	packet_pb7 = 0;
+	packet_pb8 = vactive_l;
+	packet_pb9 = vactive_h;
+	packet_pb10 = 0;
+	packet_pb11 = 0;
+	packet_pb12 = hactive_l;
+	packet_pb13 = hactive_h;
+
+	pb1_13_chksum =
+		(packet_hb0 + packet_hb1 + packet_hb2 + packet_pb1 +
+		packet_pb2 + packet_pb3 + packet_pb4 + packet_pb5 +
+		packet_pb6 + packet_pb7 + packet_pb8 + packet_pb9 +
+		packet_pb10 + packet_pb11 + packet_pb12 + packet_pb13);
+	packet_chksum =
+		256 - (pb1_13_chksum -
+		256 * ((unsigned int)pb1_13_chksum / 256));
+	packet_pb0 = packet_chksum;
+
+	packet[0] = 0;
+	packet[1] = packet_hb0;
+	packet[2] = packet_hb1;
+	packet[3] = packet_hb2;
+	packet[4] = packet_pb0;
+	packet[5] = packet_pb1;
+	packet[6] = packet_pb2;
+	packet[7] = packet_pb3;
+	packet[8] = packet_pb4;
+	packet[9] = packet_pb5;
+	packet[10] = packet_pb6;
+	packet[11] = packet_pb7;
+	packet[12] = packet_pb8;
+	packet[13] = packet_pb9;
+	packet[14] = packet_pb10;
+	packet[15] = packet_pb11;
+	packet[16] = packet_pb12;
+	packet[17] = packet_pb13;
+
+	cdn_api_infoframeset(0, packet_len,
+			     (unsigned int *)&packet[0], packet_type);
+
+	return CDN_OK;
+} /* End API */
diff --git a/drivers/video/imx/hdp/API_AVI.h b/drivers/video/imx/hdp/API_AVI.h
new file mode 100644
index 0000000..435ba3f
--- /dev/null
+++ b/drivers/video/imx/hdp/API_AVI.h
@@ -0,0 +1,59 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AVI.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_AVI_H_
+#define API_AVI_H_
+
+#include "vic_table.h"
+#include "API_General.h"
+
+CDN_API_STATUS cdn_api_set_avi(
+	VIC_MODES vic_mode,
+	VIC_PXL_ENCODING_FORMAT color_mode,
+	BT_TYPE itu_ver);
+
+#endif /*API_AVI_H_ */
+
diff --git a/drivers/video/imx/hdp/API_General.c b/drivers/video/imx/hdp/API_General.c
index 83458d7..fb60655 100644
--- a/drivers/video/imx/hdp/API_General.c
+++ b/drivers/video/imx/hdp/API_General.c
@@ -35,7 +35,7 @@
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  ******************************************************************************
  *
diff --git a/drivers/video/imx/hdp/API_General.h b/drivers/video/imx/hdp/API_General.h
index 44e16e8..e631919 100644
--- a/drivers/video/imx/hdp/API_General.h
+++ b/drivers/video/imx/hdp/API_General.h
@@ -35,7 +35,7 @@
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  ******************************************************************************
  *
diff --git a/drivers/video/imx/hdp/API_HDMITX.c b/drivers/video/imx/hdp/API_HDMITX.c
new file mode 100644
index 0000000..b1b3061
--- /dev/null
+++ b/drivers/video/imx/hdp/API_HDMITX.c
@@ -0,0 +1,486 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_HDMITX.c
+ *
+ ******************************************************************************
+ */
+
+#include "API_HDMITX.h"
+#include "util.h"
+#include "opcodes.h"
+#ifndef __UBOOT__
+#include "string.h"
+#include "stdio.h"
+#endif
+#include "mhl_hdtx_top.h"
+#include "source_phy.h"
+#include "address.h"
+#include "source_car.h"
+#include "source_vif.h"
+#include "general_handler.h"
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_READ(HDMITX_TRANS_DATA *data_in,
+				       HDMITX_TRANS_DATA *data_out)
+{
+	internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_READ,
+				    CDN_BUS_TYPE_APB, 3,
+				    1, data_in->slave,
+				    1, data_in->offset,
+				    2, data_in->len
+				   );
+	internal_readmsg(5,
+			 1, &data_out->status,
+			 1, &data_out->slave,
+			 1, &data_out->offset,
+			 2, &data_out->len,
+			 0, &data_out->buff
+			);
+	return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_READ_blocking(HDMITX_TRANS_DATA *data_in,
+						HDMITX_TRANS_DATA *data_out)
+{
+	internal_block_function(CDN_API_HDMITX_DDC_READ(data_in, data_out));
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE(HDMITX_TRANS_DATA *data_in,
+					HDMITX_TRANS_DATA *data_out)
+{
+	printf("foo: %x\n", data_in->buff[0]);
+	internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_WRITE,
+				    CDN_BUS_TYPE_APB, 4,
+				    1, data_in->slave,
+				    1, data_in->offset,
+				    2, data_in->len,
+				    -data_in->len, data_in->buff
+				   );
+	internal_readmsg(4,
+			 1, &data_out->status,
+			 1, &data_out->slave,
+			 1, &data_out->offset,
+			 2, &data_out->len
+			);
+	return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE_blocking(HDMITX_TRANS_DATA *data_in,
+						 HDMITX_TRANS_DATA *data_out)
+{
+	internal_block_function(CDN_API_HDMITX_DDC_WRITE(data_in, data_out));
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ(HDMITX_TRANS_DATA *data_out)
+{
+	internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_UPDATE_READ,
+				    CDN_BUS_TYPE_APB, 0);
+	internal_readmsg(2,
+			 1, &data_out->status,
+			 0, &data_out->buff
+			);
+	return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ_blocking(HDMITX_TRANS_DATA
+						       *data_out)
+{
+	internal_block_function(CDN_API_HDMITX_DDC_UPDATE_READ(data_out));
+}
+
+CDN_API_STATUS CDN_API_HDMITX_READ_EDID(unsigned char block,
+					unsigned char segment,
+					HDMITX_TRANS_DATA *data_out)
+{
+	internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_EDID,
+				    CDN_BUS_TYPE_APB, 2,
+				    1, block,
+				    1, segment
+				   );
+	internal_readmsg(5,
+			 1, &data_out->status,
+			 1, &data_out->slave,
+			 1, &data_out->offset,
+			 2, &data_out->len,
+			 0, &data_out->buff
+			);
+	return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_READ_EDID_blocking(unsigned char block,
+						 unsigned char segment,
+						 HDMITX_TRANS_DATA *data_out)
+{
+	internal_block_function(CDN_API_HDMITX_READ_EDID(block, segment,
+							 data_out));
+}
+
+CDN_API_STATUS
+CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol,
+				 unsigned int character_rate)
+{
+	CDN_API_STATUS ret;
+	GENERAL_READ_REGISTER_RESPONSE resp;
+	HDMITX_TRANS_DATA data_in;
+	HDMITX_TRANS_DATA data_out;
+	unsigned char buff = 1;
+
+	/*enable/disable  scrambler; */
+	if (protocol == HDMI_TX_MODE_HDMI_2_0) {
+		if (character_rate > 340000)
+			buff = 3; /*enable scrambling + TMDS_Bit_Clock_Ratio */
+		else
+			buff = 1; /*enable scrambling */
+	} else {
+		buff = 0; /*disable scrambling */
+	}
+
+	data_in.buff = &buff;
+	data_in.len = 1;
+	data_in.slave = 0x54;
+	data_in.offset = 0x20; /*TMDS config */
+#if 1
+	if (protocol == HDMI_TX_MODE_HDMI_2_0)
+		ret =  CDN_API_HDMITX_DDC_WRITE_blocking(&data_in, &data_out);
+
+#endif
+	ret = cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD +
+						     (HDTX_CONTROLLER << 2),
+						     &resp);
+
+	/*remove data enable */
+	resp.val = resp.val & (~(F_DATA_EN(1)));
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      resp.val);
+
+	if (protocol == HDMI_TX_MODE_HDMI_2_0) {
+		if (character_rate > 3400000) {
+			/* Set TMDS clock ratio */
+			ret = cdn_api_general_write_register_blocking
+				(ADDR_SOURCE_MHL_HD +
+				 (HDTX_CLOCK_REG_0 << 2),
+				 F_DATA_REGISTER_VAL_0(0x00000));
+			ret = cdn_api_general_write_register_blocking
+				(ADDR_SOURCE_MHL_HD +
+				 (HDTX_CLOCK_REG_1 << 2),
+				 F_DATA_REGISTER_VAL_1(0xFFFFF));
+		}
+	}
+
+	/*set hdmi mode and preemble mode */
+	resp.val = resp.val & (~(F_HDMI_MODE(3)));
+	resp.val = resp.val & (~(F_HDMI2_PREAMBLE_EN(1)));
+
+	resp.val = (resp.val) | (F_HDMI_MODE(protocol)) |
+		(F_HDMI2_PREAMBLE_EN(1));
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      resp.val);
+
+	/*data enable */
+	resp.val |= F_DATA_EN(1);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      resp.val);
+
+	return ret;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_Init_blocking(void)
+{
+	CDN_API_STATUS ret;
+
+	/*init phy and CAR and HDMI TX */
+/*	ret = cdn_api_general_write_register_blocking
+		(ADDR_SOURCD_PHY + (LANES_CONFIG<<2),
+		F_SOURCE_PHY_LANE0_SWAP(0) |
+		F_SOURCE_PHY_LANE1_SWAP(1) |
+		F_SOURCE_PHY_LANE2_SWAP(2) |
+		F_SOURCE_PHY_LANE3_SWAP(3) |
+		F_SOURCE_PHY_COMB_BYPASS(0) |
+		F_SOURCE_PHY_20_10(1)); */
+
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCD_PHY +
+						      (PHY_DATA_SEL << 2),
+						      F_SOURCE_PHY_MHDP_SEL(1));
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_HPD << 2),
+						      F_HPD_VALID_WIDTH(4) |
+						      F_HPD_GLITCH_WIDTH(0));
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      F_HDMI_MODE(1) |
+						      F_AUTO_MODE(0) |
+						      F_GCP_EN(1) |
+						      F_DATA_EN(1) |
+						      F_CLEAR_AVMUTE(1) |
+						      F_HDMI2_PREAMBLE_EN(1) |
+						      F_HDMI2_CTRL_IL_MODE(1) |
+						      F_PIC_3D(0XF) |
+						      F_BCH_EN(1));
+	/* open CARS */
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_PHY_CAR << 2),
+						      0xF);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_HDTX_CAR << 2),
+						      0xFF);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_PKT_CAR << 2),
+						      0xF);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_AIF_CAR << 2),
+						      0xF);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_CIPHER_CAR << 2),
+						      0xF);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_CRYPTO_CAR << 2),
+						      0xF);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_CEC_CAR << 2), 3);
+
+	/*init vif */
+	/*ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_VIF
+	  +(HSYNC2VSYNC_POL_CTRL<<2), F_HPOL(0) | F_VPOL(0)); */
+
+	return ret;
+}
+
+
+CDN_API_STATUS CDN_API_HDMITX_SetVic_blocking(VIC_MODES vicMode, int bpp,
+					      VIC_PXL_ENCODING_FORMAT format)
+{
+	CDN_API_STATUS ret;
+	GENERAL_READ_REGISTER_RESPONSE resp;
+	unsigned int vsync_lines = vic_table[vicMode][VSYNC];
+	unsigned int eof_lines = vic_table[vicMode][TYPE_EOF];
+	unsigned int sof_lines = vic_table[vicMode][SOF];
+	unsigned int hblank = vic_table[vicMode][H_BLANK];
+	unsigned int hactive = vic_table[vicMode][H_TOTAL] - hblank;
+	unsigned int vblank = vsync_lines + eof_lines + sof_lines;
+	unsigned int vactive = vic_table[vicMode][V_TOTAL] - vblank;
+	unsigned int hfront = vic_table[vicMode][FRONT_PORCH];
+	unsigned int hback = vic_table[vicMode][BACK_PORCH];
+	unsigned int vfront = eof_lines;
+	unsigned int hsync = hblank - hfront - hback;
+	unsigned int vsync = vsync_lines;
+	unsigned int vback = sof_lines;
+	unsigned int v_h_polarity = ((vic_table[vicMode][HSYNC_POL] ==
+				      ACTIVE_LOW) ? 0 : 1) +
+		((vic_table[vicMode][VSYNC_POL] == ACTIVE_LOW) ? 0 : 2);
+
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (SCHEDULER_H_SIZE << 2),
+						      (hactive << 16) + hblank);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (SCHEDULER_V_SIZE << 2),
+						      (vactive << 16) + vblank);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_SIGNAL_FRONT_WIDTH
+						       << 2),
+						      (vfront << 16) + hfront);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_SIGNAL_SYNC_WIDTH
+						       << 2),
+						      (vsync << 16) + hsync);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_SIGNAL_BACK_WIDTH
+						       << 2),
+						      (vback << 16) + hback);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_VIF +
+						      (HSYNC2VSYNC_POL_CTRL
+						       << 2),
+						      v_h_polarity);
+
+	/*  Data Enable is 1 */
+
+	/*Reset Data Enable */
+	cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD +
+					       (HDTX_CONTROLLER << 2), &resp);
+
+	/*reset data enable */
+	resp.val = resp.val & (~(F_DATA_EN(1)));
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      resp.val);
+
+	/*set bpp */
+	resp.val = resp.val &  (~(F_VIF_DATA_WIDTH(3)));
+	switch (bpp) {
+	case 8:
+		resp.val = resp.val | (F_VIF_DATA_WIDTH(0));
+		break;
+
+	case 10:
+		resp.val = resp.val | (F_VIF_DATA_WIDTH(1));
+		break;
+
+	case 12:
+		resp.val = resp.val | (F_VIF_DATA_WIDTH(2));
+		break;
+
+	case 16:
+		resp.val = resp.val | (F_VIF_DATA_WIDTH(3));
+		break;
+	}
+
+	/*select color encoding */
+	resp.val = resp.val &  (~(F_HDMI_ENCODING(3)));
+	switch (format) {
+	case PXL_RGB:
+
+		resp.val = resp.val | (F_HDMI_ENCODING(0));
+		break;
+
+	case YCBCR_4_4_4:
+		resp.val = resp.val | (F_HDMI_ENCODING(2));
+		break;
+
+	case YCBCR_4_2_2:
+		resp.val = resp.val | (F_HDMI_ENCODING(1));
+		break;
+
+	case YCBCR_4_2_0:
+		resp.val = resp.val | (F_HDMI_ENCODING(3));
+		break;
+	case Y_ONLY:
+		/*not exist in hdmi */
+		break;
+	}
+
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      resp.val);
+
+	/*set data enable */
+	resp.val = resp.val  | (F_DATA_EN(1));
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      resp.val);
+
+	return ret;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_ForceColorDepth_blocking(unsigned char force,
+						       unsigned char val)
+{
+	unsigned int valToWrite = F_COLOR_DEPTH_VAL(val) |
+		F_COLOR_DEPTH_FORCE(force);
+
+	return cdn_api_general_write_register_blocking
+		(ADDR_SOURCE_MHL_HD +
+		 (GCP_FORCE_COLOR_DEPTH_CODING << 2),
+		 valToWrite);
+}
+
+CDN_API_STATUS CDN_API_HDMITX_ReadEvents(uint32_t *events)
+{
+	CDN_API_STATUS ret;
+
+	if (!state.running) {
+		if (!internal_apb_available())
+			return CDN_BSY;
+
+		internal_tx_mkfullmsg(MB_MODULE_ID_HDMI_TX, HDMI_TX_EVENTS, 0);
+		state.rxenable = 1;
+		state.bus_type = CDN_BUS_TYPE_APB;
+
+		return CDN_STARTED;
+	}
+
+	INTERNAL_PROCESS_MESSAGES;
+
+	ret = internal_test_rx_head(MB_MODULE_ID_HDMI_TX, HDMI_TX_EVENTS);
+
+	if (ret != CDN_OK)
+		return ret;
+
+	internal_readmsg(1, 4, events);
+
+	return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_ReadEvents_blocking(uint32_t *events)
+{
+	internal_block_function(CDN_API_HDMITX_ReadEvents(events));
+}
+
+CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus(uint8_t *hpd_sts)
+{
+	CDN_API_STATUS ret;
+
+	if (!state.running) {
+		if (!internal_apb_available())
+			return CDN_BSY;
+
+		/*
+		 * General Module is used here for obtaining HPD State because
+		 * HDMI TX Module is inactive in stand-by mode, thus cannot
+		 * return it.
+		 */
+		internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL,
+				      GENERAL_GET_HPD_STATE, 0);
+		state.rxenable = 1;
+		state.bus_type = CDN_BUS_TYPE_APB;
+
+		return CDN_STARTED;
+	}
+
+	INTERNAL_PROCESS_MESSAGES;
+
+	ret = internal_test_rx_head(MB_MODULE_ID_GENERAL,
+				    GENERAL_GET_HPD_STATE);
+
+	if (ret != CDN_OK)
+		return ret;
+
+	internal_readmsg(1, 1, hpd_sts);
+
+	return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus_blocking(uint8_t *hpd_sts)
+{
+	internal_block_function(CDN_API_HDMITX_GetHpdStatus(hpd_sts));
+}
+
diff --git a/drivers/video/imx/hdp/API_HDMITX.h b/drivers/video/imx/hdp/API_HDMITX.h
new file mode 100644
index 0000000..099fd11
--- /dev/null
+++ b/drivers/video/imx/hdp/API_HDMITX.h
@@ -0,0 +1,182 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_HDMITX.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef _API_HDMITX_H_
+# define _API_HDMITX_H_
+
+# include "API_General.h"
+# include "hdmi.h"
+# include "vic_table.h"
+
+/**
+ * \addtogroup HDMI_TX_API
+ * \{
+ */
+
+# define HDMI_TX_EVENT_CODE_HPD_HIGH                  0x01
+# define HDMI_TX_EVENT_CODE_HPD_LOW                   0x02
+# define HDMI_TX_EVENT_CODE_HPD_STATE_LOW             0x00
+# define HDMI_TX_EVENT_CODE_HPD_STATE_HIGH            0x08
+
+typedef struct {
+	/** if used to return data, this pointer is set (instead of being a
+	 *  destination to copy data to
+	 */
+	unsigned char *buff;
+	HDMI_I2C_STATUS status;
+	unsigned short len;
+	unsigned char slave;
+	unsigned char offset;
+} HDMITX_TRANS_DATA;
+
+
+typedef enum {
+	HDMI_TX_MODE_DVI,
+	HDMI_TX_MODE_HDMI_1_4,
+	HDMI_TX_MODE_HDMI_2_0,
+} HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE;
+
+/**
+ * \brief I2C read transaction
+ * \param [in]  data_in  - fields used: len, slave, offset
+ * \param [out] data_out - fields used: all
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_DDC_READ(HDMITX_TRANS_DATA *data_in,
+				       HDMITX_TRANS_DATA *data_out);
+CDN_API_STATUS CDN_API_HDMITX_DDC_READ_blocking(HDMITX_TRANS_DATA *data_in,
+						HDMITX_TRANS_DATA *data_out);
+
+/**
+ * \brief I2C write transaction
+ * \param [in]  data_in  - fields used: len, slave, offset, buff
+ * \param [out] data_out - fields used: status, len, slave, offset
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE(HDMITX_TRANS_DATA *data_in,
+					HDMITX_TRANS_DATA *data_out);
+CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE_blocking(HDMITX_TRANS_DATA *data_in,
+						 HDMITX_TRANS_DATA *data_out);
+
+/**
+ * \brief I2C update read
+ * \param [out] data_out - fields used: status, buff
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ(HDMITX_TRANS_DATA *data_out);
+CDN_API_STATUS
+CDN_API_HDMITX_DDC_UPDATE_READ_blocking(HDMITX_TRANS_DATA *data_out);
+
+/**
+ * \brief I2C read edid
+ * \param [in]  block    - EDID block
+ * \pram  [in]  segment  - EDID segment
+ * \param [out] data_out - fields used: status, buff, slave (as block),
+ * offset (as segment), len
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_READ_EDID(unsigned char block,
+					unsigned char segment,
+					HDMITX_TRANS_DATA *data_out);
+CDN_API_STATUS CDN_API_HDMITX_READ_EDID_blocking(unsigned char block,
+						 unsigned char segment,
+						 HDMITX_TRANS_DATA *data_out);
+
+/**
+ * \brief set hdmi protocol type (DVI,1.x,2.x) (send scrambler command over
+ * scdc and set bits in controller)
+ * \param [in]  protocol    - type
+ * \returns status
+ */
+/*CDN_API_STATUS
+CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol,
+				 float character_rate);*/
+CDN_API_STATUS
+CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol,
+				 unsigned int character_rate);
+/**
+ * \brief init hdmi registers
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_Init_blocking(void);
+
+/**
+ * \brief change to vid id vicMode
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_SetVic_blocking(VIC_MODES vicMode,
+					      int bpp,
+					      VIC_PXL_ENCODING_FORMAT format);
+
+/**
+ * \brief option to force color depth in the gcp or not force (HW mode)
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_ForceColorDepth_blocking(unsigned char force,
+						       unsigned char val);
+
+/**
+ * \brief send HDMI_TX_TX_READ_EVENTS command
+ */
+CDN_API_STATUS CDN_API_HDMITX_ReadEvents(uint32_t *events);
+
+/**
+ * blocking version of #CDN_API_HDMITX_ReadEvents
+ */
+CDN_API_STATUS CDN_API_HDMITX_ReadEvents_blocking(uint32_t *events);
+
+/**
+ * \brief get current HPD status
+ */
+CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus(uint8_t *hpd_sts);
+
+/**
+ * \brief blocking version of #CDN_API_HDMITX_GetHpdStatus
+ */
+CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus_blocking(uint8_t *hpd_sts);
+
+#endif
+
diff --git a/drivers/video/imx/hdp/API_Infoframe.c b/drivers/video/imx/hdp/API_Infoframe.c
new file mode 100644
index 0000000..acd9612
--- /dev/null
+++ b/drivers/video/imx/hdp/API_Infoframe.c
@@ -0,0 +1,157 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_Infoframe.c
+ *
+ ******************************************************************************
+ */
+
+#include "API_Infoframe.h"
+#include "address.h"
+#include "source_pif.h"
+#include "externs.h"
+#ifndef __UBOOT__
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#else
+#include <common.h>
+#include <asm/io.h>
+#endif
+#include "util.h"
+
+#define BANK_OFFSET 0x0
+
+/* Redefined because of compiler warnings about 32 bit shift left */
+#ifdef F_DATA_WR
+#undef F_DATA_WR
+#define F_DATA_WR(a_) ((uint32_t)(a_))
+#endif
+
+static CDN_API_STATUS infoframeSet(unsigned char entry_id,
+				   unsigned char packet_len,
+				   unsigned int *packet,
+				   unsigned char packet_type,
+				   unsigned char active_idle)
+{
+	unsigned int idx;
+	unsigned int activeIdleBit = (0 == active_idle) ? 0 : 0x20000;
+	/*invalidate entry */
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_PKT_ALLOC_REG << 2),
+			  activeIdleBit | F_PKT_ALLOC_ADDRESS(entry_id)))
+		return CDN_ERR;
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_PKT_ALLOC_WR_EN << 2),
+			  F_PKT_ALLOC_WR_EN(1)))
+		return CDN_ERR;
+
+	/*flush fifo 1 */
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_FIFO1_FLUSH << 2),
+			  F_FIFO1_FLUSH(1)))
+		return CDN_ERR;
+
+	/*write packet into memory */
+	for (idx = 0; idx < packet_len; idx++)
+		if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+				  (SOURCE_PIF_DATA_WR << 2),
+				  F_DATA_WR(packet[idx])))
+			return CDN_ERR;
+
+	/*write entry id */
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_WR_ADDR << 2),
+			  F_WR_ADDR(entry_id)))
+		return CDN_ERR;
+
+	/*write request */
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_WR_REQ << 2),
+			  F_HOST_WR(1)))
+		return CDN_ERR;
+
+	/*update entry */
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_PKT_ALLOC_REG << 2),
+			  activeIdleBit | F_TYPE_VALID(1) |
+			  F_PACKET_TYPE(packet_type) |
+			  F_PKT_ALLOC_ADDRESS(entry_id)))
+		return CDN_ERR;
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_PKT_ALLOC_WR_EN << 2),
+			  F_PKT_ALLOC_WR_EN(1)))
+		return CDN_ERR;
+
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_infoframeset(unsigned char entry_id,
+				    unsigned char packet_len,
+				    unsigned int *packet,
+				    unsigned char packet_type)
+{
+	return infoframeSet(entry_id, packet_len, packet, packet_type, 1);
+}
+
+CDN_API_STATUS cdn_api_infoframesetnoactiveidle(unsigned char entry_id,
+						unsigned char packet_len,
+						unsigned int *packet,
+						unsigned char packet_type)
+{
+	return infoframeSet(entry_id, packet_len, packet, packet_type, 0);
+}
+
+CDN_API_STATUS cdn_api_infoframeremove(unsigned char entry_id)
+{
+	/*invalidate entry */
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_PKT_ALLOC_REG << 2),
+			  0x20000 | F_PKT_ALLOC_ADDRESS(entry_id)))
+		return CDN_ERR;
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_PKT_ALLOC_WR_EN << 2),
+			  F_PKT_ALLOC_WR_EN(1)))
+		return CDN_ERR;
+
+	return CDN_OK;
+}
+
diff --git a/drivers/video/imx/hdp/API_Infoframe.h b/drivers/video/imx/hdp/API_Infoframe.h
new file mode 100644
index 0000000..a384bb2
--- /dev/null
+++ b/drivers/video/imx/hdp/API_Infoframe.h
@@ -0,0 +1,68 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_Infoframe.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_INFOFRAME_H
+# define API_INFOFRAME_H
+
+/**
+ * \addtogroup INFO_FRAME_API
+ * \{
+ */
+
+# include "API_General.h"
+
+CDN_API_STATUS cdn_api_infoframeset(unsigned char entry_id,
+				    unsigned char packet_len,
+				    unsigned int *packet,
+				    unsigned char packet_type);
+CDN_API_STATUS cdn_api_infoframesetnoactiveidle(unsigned char entry_id,
+						unsigned char packet_len,
+						unsigned int *packet,
+						unsigned char packet_type);
+CDN_API_STATUS cdn_api_infoframeremove(unsigned char entry_id);
+
+#endif
+
diff --git a/drivers/video/imx/hdp/Makefile b/drivers/video/imx/hdp/Makefile
index 13dcefd..d704b73 100644
--- a/drivers/video/imx/hdp/Makefile
+++ b/drivers/video/imx/hdp/Makefile
@@ -1 +1,49 @@
-obj-y += API_General.o util.o test_base_sw.o
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+obj-$(CONFIG_VIDEO_IMX_HDP_LOAD) += API_General.o util.o test_base_sw.o
+
+obj-$(CONFIG_VIDEO_IMX8_HDMI) += \
+	API_General.o \
+	test_base_sw.o \
+	API_AVI.o \
+	API_Infoframe.o \
+	util.o \
+	vic_table.o \
+	edid_parser.o \
+	API_AFE.o \
+	API_HDMITX.o \
+	API_AFE_t28hpc_hdmitx.o
+
+# common objects
+#obj-y += \
+#	API_General.o  API_AVI.o API_Infoframe.o \
+#	util.o vic_table.o test_base_sw.o \
+#	avgen_drv.o edid_parser.o \
+#	API_AFE.o
+
+#DP objects
+#	API_DPTX.o \
+#	API_AFE_mcu2_dp.o\
+#	mhdp_firmware.o
+
+#hdmi objects
+#obj-y += \
+#	API_HDMITX.o \
+#	API_HDCP.o \
+#	API_AFE_t28hpc_hdmitx.o
+#
+
+# USE for QM
+#	blob/API_AFE_mcu1_dp.o
+#	blob/API_AFE_ss28fdsoi_kiran_hdmitx.o
+#	blob/ss28fdsoi_hdmitx_table.o
+#	blob/hdmitx_firmware.o
+#	blob/mhdp_firmware.o
+
+# Use for mscale
+#	API_AFE_mcu2_dp.o ()
+#	API_AFE_t28hpc_hdmitx.c
+#
diff --git a/drivers/video/imx/hdp/apb_cfg.h b/drivers/video/imx/hdp/apb_cfg.h
index cdcbd76..572ab07 100644
--- a/drivers/video/imx/hdp/apb_cfg.h
+++ b/drivers/video/imx/hdp/apb_cfg.h
@@ -35,7 +35,7 @@
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  ******************************************************************************
  *
diff --git a/drivers/video/imx/hdp/avgen.h b/drivers/video/imx/hdp/avgen.h
new file mode 100644
index 0000000..669a101
--- /dev/null
+++ b/drivers/video/imx/hdp/avgen.h
@@ -0,0 +1,253 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * avgen.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef AVGEN_H_
+# define AVGEN_H_
+
+
+/* register HDMIPOL */
+# define HDMIPOL 0
+# define F_HDMI_V_H_POLARITY(x) (((x) & ((1 << 2) - 1)) << 0)
+# define F_HDMI_V_H_POLARITY_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+# define F_HDMI_BITWIDTH(x) (((x) & ((1 << 2) - 1)) << 2)
+# define F_HDMI_BITWIDTH_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2)
+
+/* register HDMI_FRONT_PORCHE_L */
+# define HDMI_FRONT_PORCHE_L 1
+# define F_HDMI_FRONT_PORCHE_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_FRONT_PORCHE_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDFP */
+# define HDFP 2
+# define F_HDMI_FRONT_PORCHE_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_FRONT_PORCHE_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDBP */
+# define HDBP 3
+# define F_HDMI_BACK_PORCHE_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_BACK_PORCHE_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_BACK_PORCHE_H */
+# define HDMI_BACK_PORCHE_H 4
+# define F_HDMI_BACK_PORCHE_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_BACK_PORCHE_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDAS */
+# define HDAS 5
+# define F_HDMI_ACTIVE_SLOT_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_ACTIVE_SLOT_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_ACTIVE_SLOT_H */
+# define HDMI_ACTIVE_SLOT_H 6
+# define F_HDMI_ACTIVE_SLOT_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_ACTIVE_SLOT_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDFL */
+# define HDFL 7
+# define F_HDMI_FRAME_LINES_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_FRAME_LINES_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_FRAME_LINES_H */
+# define HDMI_FRAME_LINES_H 8
+# define F_HDMI_FRAME_LINES_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_FRAME_LINES_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDLW */
+# define HDLW 9
+# define F_HDMI_LINE_WIDTH_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_LINE_WIDTH_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_LINE_WIDTH_H */
+# define HDMI_LINE_WIDTH_H 10
+# define F_HDMI_LINE_WIDTH_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_LINE_WIDTH_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDVL */
+# define HDVL 11
+# define F_HDMI_VSYNC_LINES(x) (((x) & ((1 << 7) - 1)) << 0)
+# define F_HDMI_VSYNC_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0)
+
+/* register HDEL */
+# define HDEL 12
+# define F_HDMI_EOF_LINES(x) (((x) & ((1 << 7) - 1)) << 0)
+# define F_HDMI_EOF_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0)
+
+/* register HDSL */
+# define HDSL 13
+# define F_HDMI_SOF_LINES(x) (((x) & ((1 << 7) - 1)) << 0)
+# define F_HDMI_SOF_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0)
+
+/* register HDCFUPDT */
+# define HDCFUPDT 14
+# define F_HDMI_CODE_FORMAT_UPDT(x) (((x) & ((1 << 6) - 1)) << 0)
+# define F_HDMI_CODE_FORMAT_UPDT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0)
+
+/* register HDCF */
+# define HDCF 15
+# define F_HDMI_CODE_FORMAT(x) (((x) & ((1 << 6) - 1)) << 0)
+# define F_HDMI_CODE_FORMAT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0)
+
+/* register HDASPACE */
+# define HDASPACE 16
+# define F_HDASPACE(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDASPACE_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_3D_MODE */
+# define HDMI_3D_MODE 17
+# define F_HDMI_3D_MODE(x) (((x) & ((1 << 3) - 1)) << 0)
+# define F_HDMI_3D_MODE_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0)
+
+/* register PTRNGENR */
+# define PTRNGENR 18
+# define F_PTRNGENR_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENR_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNGENR_H */
+# define PTRNGENR_H 19
+# define F_PTRNGENR_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENR_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNGENG */
+# define PTRNGENG 20
+# define F_PTRNGENG_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENG_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNEGENG_H */
+# define PTRNEGENG_H 21
+# define F_PTRNGENG_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENG_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNGENB */
+# define PTRNGENB 22
+# define F_PTRNGENB_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENB_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRGENB */
+# define PTRGENB 23
+# define F_PTRNGENB_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENB_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNGENFF */
+# define PTRNGENFF 30
+# define F_PTRNGENIP(x) (((x) & ((1 << 1) - 1)) << 1)
+# define F_PTRNGENIP_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+
+/* register PGENCTRL */
+# define PGENCTRL 32
+# define F_PGENCF(x) (((x) & ((1 << 6) - 1)) << 1)
+# define F_PGENCF_RD(x) (((x) & (((1 << 6) - 1) << 1)) >> 1)
+# define F_PTRNGENSTRT(x) (((x) & ((1 << 1) - 1)) << 7)
+# define F_PTRNGENSTRT_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+
+/* register PGENCTRL_H */
+# define PGENCTRL_H 33
+# define F_PTRNGENRST(x) (((x) & ((1 << 1) - 1)) << 0)
+# define F_PTRNGENRST_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+# define F_PIC_SEL(x) (((x) & ((1 << 3) - 1)) << 1)
+# define F_PIC_SEL_RD(x) (((x) & (((1 << 3) - 1) << 1)) >> 1)
+# define F_PIC_YCBCR_SEL(x) (((x) & ((1 << 2) - 1)) << 4)
+# define F_PIC_YCBCR_SEL_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4)
+
+/* register PGEN_COLOR_BAR_CTRL */
+# define PGEN_COLOR_BAR_CTRL 34
+# define F_PGEN_NUM_BAR(x) (((x) & ((1 << 3) - 1)) << 0)
+# define F_PGEN_NUM_BAR_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0)
+
+/* register PGEN_COLOR_BAR_CONTROL_H */
+# define PGEN_COLOR_BAR_CONTROL_H 35
+# define F_PGEN_COLOR_UPDT(x) (((x) & ((1 << 6) - 1)) << 0)
+# define F_PGEN_COLOR_UPDT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0)
+
+/* register GEN_AUDIO_CONTROL */
+# define GEN_AUDIO_CONTROL 36
+# define F_AUDIO_START(x) (((x) & ((1 << 1) - 1)) << 1)
+# define F_AUDIO_START_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+# define F_AUDIO_RESET(x) (((x) & ((1 << 1) - 1)) << 2)
+# define F_AUDIO_RESET_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+
+/* register SPDIF_CTRL_A */
+# define SPDIF_CTRL_A 37
+# define F_SPDIF_SOURCE_NUM(x) (((x) & ((1 << 4) - 1)) << 0)
+# define F_SPDIF_SOURCE_NUM_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+# define F_SPDIF_CH_NUM(x) (((x) & ((1 << 4) - 1)) << 4)
+# define F_SPDIF_CH_NUM_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4)
+
+/* register SPDIF_CTRL_A_H */
+# define SPDIF_CTRL_A_H 38
+# define F_SPDIF_SMP_FREQ(x) (((x) & ((1 << 4) - 1)) << 0)
+# define F_SPDIF_SMP_FREQ_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+# define F_SPDIF_CLK_ACCUR(x) (((x) & ((1 << 2) - 1)) << 4)
+# define F_SPDIF_CLK_ACCUR_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4)
+# define F_SPDIF_VALID(x) (((x) & ((1 << 1) - 1)) << 6)
+# define F_SPDIF_VALID_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+
+/* register SPDIF_CTRL_B */
+# define SPDIF_CTRL_B 39
+# define F_SPDIF_WORD_LENGTH(x) (((x) & ((1 << 4) - 1)) << 0)
+# define F_SPDIF_WORD_LENGTH_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+# define F_SPDIF_ORG_SMP_FREQ(x) (((x) & ((1 << 4) - 1)) << 4)
+# define F_SPDIF_ORG_SMP_FREQ_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4)
+
+/* register SPDIF_CTRL_B_H */
+# define SPDIF_CTRL_B_H 40
+# define F_CATEGORY_MODE(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_CATEGORY_MODE_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register AUDIO_DIV_EN */
+# define AUDIO_DIV_EN 45
+# define F_AGEN_60958_I2S(x) (((x) & ((1 << 1) - 1)) << 1)
+# define F_AGEN_60958_I2S_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+# define F_AGEN_PRL_SUBFRAME(x) (((x) & ((1 << 1) - 1)) << 2)
+# define F_AGEN_PRL_SUBFRAME_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+# define F_AGEN_SAMPLES_DATA(x) (((x) & ((1 << 1) - 1)) << 3)
+# define F_AGEN_SAMPLES_DATA_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+
+#endif /*AVGEN */
+
diff --git a/drivers/video/imx/hdp/avgen_drv.c b/drivers/video/imx/hdp/avgen_drv.c
new file mode 100644
index 0000000..89acafe
--- /dev/null
+++ b/drivers/video/imx/hdp/avgen_drv.c
@@ -0,0 +1,306 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * avgen_drv.c
+ *
+ ******************************************************************************
+ */
+
+#include "mhl_hdtx_top.h"
+#include "address.h"
+#include "avgen.h"
+#include "avgen_drv.h"
+#include "util.h"
+#include "externs.h"
+
+#define ADDR_AVGEN 0x80000
+
+CDN_API_STATUS CDN_API_AVGEN_Set(VIC_MODES vicMode, CDN_PROTOCOL_TYPE protocol,
+				 VIC_PXL_ENCODING_FORMAT format)
+{
+	/*CDN_API_STATUS ret; */
+	/*GENERAL_Read_Register_response resp; */
+	unsigned int pixelClockFreq = CDN_API_Get_PIXEL_FREQ_KHZ_ClosetVal
+		(vic_table[vicMode][PIXEL_FREQ_KHZ], protocol);
+	unsigned int v_h_polarity =
+		((vic_table[vicMode][HSYNC_POL] == ACTIVE_LOW) ? 0 : 1) +
+		((vic_table[vicMode][VSYNC_POL] == ACTIVE_LOW) ? 0 : 2);
+	unsigned int front_porche_l = vic_table[vicMode][FRONT_PORCH] - 256 *
+		((unsigned int)vic_table[vicMode][FRONT_PORCH] / 256);
+	unsigned int front_porche_h = vic_table[vicMode][FRONT_PORCH] / 256;
+	unsigned int back_porche_l = vic_table[vicMode][BACK_PORCH] - 256 *
+		((unsigned int)vic_table[vicMode][BACK_PORCH] / 256);
+	unsigned int back_porche_h = vic_table[vicMode][BACK_PORCH] / 256;
+	unsigned int active_slot_l = vic_table[vicMode][H_BLANK] - 256 *
+		((unsigned int)vic_table[vicMode][H_BLANK] / 256);
+	unsigned int active_slot_h = vic_table[vicMode][H_BLANK] / 256;
+	unsigned int frame_lines_l = vic_table[vicMode][V_TOTAL] - 256 *
+		((unsigned int)vic_table[vicMode][V_TOTAL] / 256);
+	unsigned int frame_lines_h = vic_table[vicMode][V_TOTAL] / 256;
+	unsigned int line_width_l = vic_table[vicMode][H_TOTAL] - 256 *
+		((unsigned int)vic_table[vicMode][H_TOTAL] / 256);
+	unsigned int line_width_h = vic_table[vicMode][H_TOTAL] / 256;
+	unsigned int vsync_lines = vic_table[vicMode][VSYNC];
+	unsigned int eof_lines = vic_table[vicMode][TYPE_EOF];
+	unsigned int sof_lines = vic_table[vicMode][SOF];
+	unsigned int interlace_progressive =
+		(vic_table[vicMode][I_P] == INTERLACED) ? 2 : 0;
+	unsigned int set_vif_clock = 0;
+
+	/*needed for HDMI /////////////////////////////// */
+	/*unsigned int hblank = vic_table[vicMode][H_BLANK]; */
+	/*unsigned int hactive = vic_table[vicMode][H_TOTAL]-hblank; */
+	/*unsigned int vblank = vsync_lines+eof_lines+sof_lines; */
+	/*unsigned int vactive = vic_table[vicMode][V_TOTAL]-vblank; */
+	/*unsigned int hfront = vic_table[vicMode][FRONT_PORCH]; */
+	/*unsigned int hback = vic_table[vicMode][BACK_PORCH]; */
+	/*unsigned int vfront = eof_lines; */
+	/*unsigned int hsync = hblank-hfront-hback; */
+	/*unsigned int vsync = vsync_lines; */
+	/*unsigned int vback = sof_lines; */
+	unsigned int set_CLK_SEL            = 0;
+	unsigned int set_REF_CLK_SEL        = 0;
+	unsigned int set_pll_CLK_IN            = 0;
+	unsigned int set_pll_clkfbout_l        = 0;
+	unsigned int set_pll_clkfbout_h        = 0;
+	unsigned int set_pll_CLKOUT5_L        = 0;
+	unsigned int set_pll_CLKOUT5_H        = 0;
+	unsigned int set_pll2_CLKIN            = 0;
+	unsigned int set_pll2_CLKFBOUT_L    = 0;
+	unsigned int set_pll2_CLKFBOUT_H    = 0;
+	unsigned int set_pll2_CLKOUT5_L        = 0;
+	unsigned int set_pll2_CLKOUT5_H        = 0;
+	/*///////////////////////////////////////////////// */
+
+	cdn_apb_write(0x1c00C6 << 2,
+		      (int)(vic_table[vicMode][PIXEL_FREQ_KHZ] * 1000));
+	cdn_apb_write(0x1c00C6 << 2, (int)(pixelClockFreq));
+
+	if ((int)(pixelClockFreq) == 25) {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL                = 4;
+			set_REF_CLK_SEL            = 0;
+			set_pll_CLK_IN            = 65;
+			set_pll_clkfbout_l        = 4292;
+			set_pll_clkfbout_h        = 128;
+			set_pll_CLKOUT5_L        = 4422;
+			set_pll_CLKOUT5_H        = 128;
+			set_pll2_CLKIN            = 12289;
+			set_pll2_CLKFBOUT_L        = 4356;
+			set_pll2_CLKFBOUT_H        = 0;
+			set_pll2_CLKOUT5_L        = 4552;
+			set_pll2_CLKOUT5_H        = 128;
+		} else {
+			set_vif_clock = 0x300;
+		}
+	} else if ((int)pixelClockFreq == 27000) {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL                = 5;
+			set_REF_CLK_SEL            = 0;
+			set_pll_CLK_IN            = 49217;
+			set_pll_clkfbout_l        = 4226;
+			set_pll_clkfbout_h        = 0;
+			set_pll_CLKOUT5_L        = 4422;
+			set_pll_CLKOUT5_H        = 128;
+		} else {
+			set_vif_clock = 0x301;
+		}
+	} else if ((int)pixelClockFreq == 54000) {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL             = 5;
+			set_REF_CLK_SEL         = 0;
+			set_pll_CLK_IN          = 4096;
+			set_pll_clkfbout_l      = 4226;
+			set_pll_clkfbout_h      = 0;
+			set_pll_CLKOUT5_L       = 4422;
+			set_pll_CLKOUT5_H       = 128;
+		} else {
+			set_vif_clock = 0x302;
+		}
+	} else if (pixelClockFreq == 74250) {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL          = 1;
+			set_pll_CLK_IN       = 74;
+		} else {
+			set_vif_clock = 0x303;
+		}
+	} else if (pixelClockFreq == 148500) {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL             = 0;
+			set_pll_CLK_IN       = 148;
+		} else {
+			set_vif_clock = 0x304;
+		}
+	} else if ((int)pixelClockFreq == 108000) {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL                = 5;
+			set_REF_CLK_SEL            = 2;
+			set_pll_CLK_IN            = 8258;
+			set_pll_clkfbout_l        = 4616;
+			set_pll_clkfbout_h        = 0;
+			set_pll_CLKOUT5_L        = 4422;
+			set_pll_CLKOUT5_H        = 128;
+		} else {
+			set_vif_clock = 0x305;
+		}
+	} else {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL             = 1;
+			set_pll_CLK_IN          = pixelClockFreq;
+		} else {
+			set_vif_clock = 0;
+		}
+	}
+	unsigned int start_pgen = 128;
+	/*unsigned int temp; */
+	if (protocol == CDN_HDMITX_TYPHOON) {
+		if (cdn_apb_write(0x0c0001 << 2,
+				  ((0) + (2 * set_CLK_SEL) + (16 * 0) +
+				   (32 * 0) + (64 * 3) + (65536 * 3) +
+				   (1048576 * set_REF_CLK_SEL))))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c00C6 << 2, set_pll_CLK_IN))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c00CC << 2, set_pll_clkfbout_l))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c00CD << 2, set_pll_clkfbout_h))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c00CE << 2, set_pll_CLKOUT5_L))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c00CF << 2, set_pll_CLKOUT5_H))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c0086 << 2, set_pll2_CLKIN))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c008C << 2, set_pll2_CLKFBOUT_L))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c008D << 2, set_pll2_CLKFBOUT_H))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c008E << 2, set_pll2_CLKOUT5_L))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c008F << 2, set_pll2_CLKOUT5_H))
+			return CDN_ERR;
+		if (cdn_apb_write(0x0c0001 << 2,
+				  ((1) + (2 * set_CLK_SEL) + (16 * 0) +
+				   (32 * 0) + (64 * 3) + (65536 * 3) +
+				   (1048576 * set_REF_CLK_SEL))))
+			return CDN_ERR;
+	}
+
+	if (cdn_apb_write((ADDR_AVGEN + HDMIPOL) << 2, v_h_polarity))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDMI_FRONT_PORCHE_L) << 2,
+			  front_porche_l))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDFP) << 2, front_porche_h))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDBP) << 2, back_porche_l))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDMI_BACK_PORCHE_H) << 2,
+			  back_porche_h))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDAS) << 2, active_slot_l))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDMI_ACTIVE_SLOT_H) << 2,
+			  active_slot_h))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDFL) << 2, frame_lines_l))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDMI_FRAME_LINES_H) << 2,
+			  frame_lines_h))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDLW) << 2, line_width_l))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDMI_LINE_WIDTH_H) << 2, line_width_h))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDVL) << 2, vsync_lines))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDEL) << 2, eof_lines))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDSL) << 2, sof_lines))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + PTRNGENFF) << 2, interlace_progressive))
+		return CDN_ERR;
+
+	if (protocol == CDN_HDMITX_TYPHOON) {
+		switch (format) {
+		case PXL_RGB:
+
+			if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2,
+					  F_PIC_SEL(1) | F_PIC_YCBCR_SEL(0)))
+				return CDN_ERR;
+			break;
+
+		case YCBCR_4_4_4:
+			if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2,
+					  F_PIC_SEL(2) | F_PIC_YCBCR_SEL(0)))
+				return CDN_ERR;
+
+			break;
+
+		case YCBCR_4_2_2:
+			if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2,
+					  F_PIC_SEL(2) | F_PIC_YCBCR_SEL(1)))
+				return CDN_ERR;
+
+			break;
+
+		case YCBCR_4_2_0:
+			if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2,
+					  F_PIC_SEL(2) | F_PIC_YCBCR_SEL(2)))
+				return CDN_ERR;
+
+			break;
+		case Y_ONLY:
+			/*not exist in hdmi */
+			break;
+		}
+	} else {
+		if (set_vif_clock != 0)
+			if (cdn_apb_write(0xC0006 << 2, set_vif_clock))
+				return CDN_ERR;
+	}
+
+	if (cdn_apb_write((ADDR_AVGEN + PGENCTRL) << 2, start_pgen))
+		return CDN_ERR;
+
+	return CDN_OK;
+}
+
diff --git a/drivers/video/imx/hdp/avgen_drv.h b/drivers/video/imx/hdp/avgen_drv.h
new file mode 100644
index 0000000..1f8c76b
--- /dev/null
+++ b/drivers/video/imx/hdp/avgen_drv.h
@@ -0,0 +1,69 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * avgen_drv.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef AVGEN_DRV_H_
+# define AVGEN_DRV_H_
+
+#ifndef __UBOOT__
+# include <stdint.h>
+#else
+#include <common.h>
+#endif
+
+# include "vic_table.h"
+# include "API_General.h"
+# include "defs.h"
+
+/**
+ * \brief set avgen according to mode and vic table, user that doesnt have
+ * cadence AVGEN, need to implement this function on user
+ * platform
+ */
+CDN_API_STATUS CDN_API_AVGEN_Set(VIC_MODES vicMode, CDN_PROTOCOL_TYPE protocol,
+				 VIC_PXL_ENCODING_FORMAT format);
+
+#endif
+
diff --git a/drivers/video/imx/hdp/defs.h b/drivers/video/imx/hdp/defs.h
new file mode 100644
index 0000000..4a6361e
--- /dev/null
+++ b/drivers/video/imx/hdp/defs.h
@@ -0,0 +1,57 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2015-2016 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * defs.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef _DEFS_H_
+#define _DEFS_H_
+
+typedef enum {
+	CDN_DPTX ,
+	CDN_HDMITX_TYPHOON,
+	CDN_HDMITX_KIRAN,
+} CDN_PROTOCOL_TYPE;
+
+#endif /*_DEFS_H_ */
+
diff --git a/drivers/video/imx/hdp/edid_parser.c b/drivers/video/imx/hdp/edid_parser.c
new file mode 100644
index 0000000..24aa739
--- /dev/null
+++ b/drivers/video/imx/hdp/edid_parser.c
@@ -0,0 +1,617 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2015-2016 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * edid_parser.c
+ *
+ ******************************************************************************
+ */
+
+#include "edid_parser.h"
+
+static EDID_PARSER_RESULT edid_parse_dtd(S_DTD_DATA *descriptor,
+					 unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_DTD;
+	descriptor->header.tag = 0;
+
+	descriptor->pixel_clock = raw_data[raw_data_index];
+	descriptor->pixel_clock +=
+		(unsigned short)raw_data[raw_data_index + 1] << 8;
+
+	descriptor->horizontal_addressable_video = raw_data[raw_data_index + 2];
+	descriptor->horizontal_addressable_video +=
+		((unsigned short)raw_data[raw_data_index + 4] & 0xF0) << 4;
+	descriptor->horizontal_blanking = raw_data[raw_data_index + 3];
+	descriptor->horizontal_blanking +=
+		((unsigned short)raw_data[raw_data_index + 4] & 0x0F) << 8;
+
+	descriptor->vertical_addressable_video = raw_data[raw_data_index + 5];
+	descriptor->vertical_addressable_video +=
+		((unsigned short)raw_data[raw_data_index + 7] & 0xF0) << 4;
+	descriptor->vertical_blanking = raw_data[raw_data_index + 6];
+	descriptor->vertical_blanking +=
+		((unsigned short)raw_data[raw_data_index + 7] & 0x0F) << 8;
+
+	descriptor->horizontal_front_porch = raw_data[raw_data_index + 8];
+	descriptor->horizontal_front_porch +=
+		((unsigned short)raw_data[raw_data_index + 11] & 0xC0) << 2;
+	descriptor->horizontal_sync_pulse_width = raw_data[raw_data_index + 9];
+	descriptor->horizontal_sync_pulse_width +=
+		((unsigned short)raw_data[raw_data_index + 11] & 0x30) << 4;
+
+	descriptor->vertical_front_porch =
+		(raw_data[raw_data_index + 10] & 0xF0) >> 4;
+	descriptor->vertical_front_porch +=
+		(raw_data[raw_data_index + 11] & 0x0C) << 2;
+	descriptor->vertical_sync_pulse_width =
+		raw_data[raw_data_index + 10] & 0x0F;
+	descriptor->vertical_sync_pulse_width +=
+		(raw_data[raw_data_index + 11] & 0x03) << 4;
+
+	descriptor->horizontal_addressable_video_image_size =
+		raw_data[raw_data_index + 12];
+	descriptor->horizontal_addressable_video_image_size +=
+		((unsigned short)raw_data[raw_data_index + 14] & 0xF0) << 4;
+	descriptor->vertical_addressable_video_image_size =
+		raw_data[raw_data_index + 13];
+	descriptor->vertical_addressable_video_image_size +=
+		((unsigned short)raw_data[raw_data_index + 14] & 0x0F) << 8;
+
+	descriptor->horizontal_border = raw_data[raw_data_index + 15];
+	descriptor->vertical_border = raw_data[raw_data_index + 16];
+
+	descriptor->signal_features = raw_data[raw_data_index + 17];
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_serial_number(S_SERIAL_NUMBER_DATA *
+						   descriptor,
+						   unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+	descriptor->header.type = DESCRIPTOR_TYPE_SERIAL_NUMBER;
+	descriptor->header.tag = 0xFF;
+
+	int idx;
+	for (idx = 0; idx < 13; idx++)
+		descriptor->serial_number[idx] =
+			raw_data[raw_data_index + 5 + idx];
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_data_string(S_DATA_STRING_DATA *
+						 descriptor,
+						 unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+	descriptor->header.type = DESCRIPTOR_TYPE_DATA_STRING;
+	descriptor->header.tag = 0xFE;
+	int idx;
+	for (idx = 0; idx < 13; idx++)
+		descriptor->data_string[idx] =
+			raw_data[raw_data_index + 5 + idx];
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_range_limits(S_RANGE_LIMITS_DATA *
+						  descriptor,
+						  unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_RANGE_LIMITS;
+	descriptor->header.tag = 0xFD;
+
+	descriptor->offset_flags = raw_data[raw_data_index + 4];
+	descriptor->min_vertical_rate = raw_data[raw_data_index + 5];
+	descriptor->max_vertical_rate = raw_data[raw_data_index + 6];
+	descriptor->min_horizontal_rate = raw_data[raw_data_index + 7];
+	descriptor->max_horizontal_rate = raw_data[raw_data_index + 8];
+	descriptor->max_pixel_clock = raw_data[raw_data_index + 9];
+
+	switch (raw_data[raw_data_index + 10]) {
+	case 0x00:
+		descriptor->type = VIDEO_TIMING_DEFAULT_GTF;
+		break;
+	case 0x01:
+		descriptor->type = VIDEO_TIMING_RANGE_LIMITS_ONLY;
+		break;
+	case 0x02:
+		descriptor->type = VIDEO_TIMING_SECONDARY_GTF;
+		S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF *timing_type_gtf =
+			(S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF *)
+			descriptor->suport_flags;
+		timing_type_gtf->start_break_frequency =
+			raw_data[raw_data_index + 12];
+		timing_type_gtf->c = raw_data[raw_data_index + 13];
+		timing_type_gtf->m = raw_data[raw_data_index + 14];
+		timing_type_gtf->m +=
+			(unsigned short)raw_data[raw_data_index + 15] << 8;
+		timing_type_gtf->k = raw_data[raw_data_index + 16];
+		timing_type_gtf->j = raw_data[raw_data_index + 17];
+		break;
+	case 0x04:
+		descriptor->type = VIDEO_TIMING_CVT;
+		S_RANGE_LIMITS_VIDEO_TIMING_CVT *timing_type_cvt =
+			(S_RANGE_LIMITS_VIDEO_TIMING_CVT *)descriptor->
+			suport_flags;
+		timing_type_cvt->cvt_version = raw_data[raw_data_index + 11];
+		timing_type_cvt->additional_pixel_clock_precision =
+			raw_data[raw_data_index + 12] >> 2;
+		timing_type_cvt->max_active_pixels =
+			raw_data[raw_data_index + 13];
+		timing_type_cvt->max_active_pixels +=
+			(unsigned short)(raw_data[raw_data_index + 12] & 0x03)
+			<< 8;
+		timing_type_cvt->supported_ar =
+			raw_data[raw_data_index + 14] >> 3;
+		timing_type_cvt->preferred_ar =
+			raw_data[raw_data_index + 15] >> 5;
+		timing_type_cvt->blanking_support =
+			(raw_data[raw_data_index + 15] & 0x18) >> 3;
+		timing_type_cvt->supported_scalling =
+			raw_data[raw_data_index + 16] >> 4;
+		timing_type_cvt->preferred_vertical_refresh_rate =
+			raw_data[raw_data_index + 17];
+		break;
+	}
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_product_name(S_PRODUCT_NAME_DATA *
+						  descriptor,
+						  unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_PRODUCT_NAME;
+	descriptor->header.tag = 0xFC;
+	int idx;
+	for (idx = 0; idx < 13; idx++)
+		descriptor->product_name[idx] =
+			raw_data[raw_data_index + 5 + idx];
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_color_point(S_COLOR_POINT_DATA *
+						 descriptor,
+						 unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_COLOR_POINT;
+	descriptor->header.tag = 0xFB;
+	descriptor->white_point_index_1 = raw_data[raw_data_index + 5];
+	descriptor->white_x_1 = (raw_data[raw_data_index + 6] & 0x0C) >> 2;
+	descriptor->white_x_1 +=
+		(unsigned short)raw_data[raw_data_index + 7] << 2;
+	descriptor->white_y_1 = raw_data[raw_data_index + 6] & 0x03;
+	descriptor->white_y_1 +=
+		(unsigned short)raw_data[raw_data_index + 8] << 2;
+	descriptor->gamma_1 = raw_data[raw_data_index + 9];
+
+	descriptor->white_point_index_2 = raw_data[raw_data_index + 10];
+	descriptor->white_x_2 = (raw_data[raw_data_index + 11] & 0x0C) >> 2;
+	descriptor->white_x_2 +=
+		(unsigned short)raw_data[raw_data_index + 12] << 2;
+	descriptor->white_y_2 = raw_data[raw_data_index + 11] & 0x03;
+	descriptor->white_y_2 +=
+		(unsigned short)raw_data[raw_data_index + 13] << 2;
+	descriptor->gamma_2 = raw_data[raw_data_index + 14];
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_standard_timing(S_STANDARD_TIMING_DATA *
+						     descriptor,
+						     unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_STANDARD_TIMING;
+	descriptor->header.tag = 0xFA;
+	int idx;
+	for (idx = 0; idx < 6; idx++) {
+		descriptor->standard_timings[idx] =
+			raw_data[raw_data_index + 5 + 2 * idx];
+		descriptor->standard_timings[idx] +=
+			(unsigned short)raw_data[raw_data_index + 5 + 2 * idx +
+			1];
+	}
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_color_management(S_COLOR_MANAGEMENT_DATA *
+						      descriptor,
+						      unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_COLOR_MANAGEMENT;
+	descriptor->header.tag = 0xF9;
+
+	descriptor->version = raw_data[raw_data_index + 5];
+
+	descriptor->red_a3 = raw_data[raw_data_index + 6];
+	descriptor->red_a3 += (unsigned short)raw_data[raw_data_index + 7] << 8;
+	descriptor->red_a2 = raw_data[raw_data_index + 8];
+	descriptor->red_a2 += (unsigned short)raw_data[raw_data_index + 9] << 8;
+
+	descriptor->green_a3 = raw_data[raw_data_index + 10];
+	descriptor->green_a3 +=
+		(unsigned short)raw_data[raw_data_index + 11] << 8;
+	descriptor->green_a2 = raw_data[raw_data_index + 12];
+	descriptor->green_a2 +=
+		(unsigned short)raw_data[raw_data_index + 13] << 8;
+
+	descriptor->blue_a3 = raw_data[raw_data_index + 14];
+	descriptor->blue_a3 +=
+		(unsigned short)raw_data[raw_data_index + 15] << 8;
+	descriptor->blue_a2 = raw_data[raw_data_index + 16];
+	descriptor->blue_a2 +=
+		(unsigned short)raw_data[raw_data_index + 17] << 8;
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_cvt_timing_codes(S_CVT_TIMING_CODES_DATA *
+						      descriptor,
+						      unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_CVT_TIMING_CODES;
+	descriptor->header.tag = 0xF8;
+	descriptor->version = raw_data[raw_data_index + 5];
+
+	int idx;
+	for (idx = 0; idx < 4; idx++) {
+		descriptor->addressable_lines[idx] =
+			raw_data[raw_data_index + 6 + idx * 3];
+		descriptor->addressable_lines[idx] +=
+			(unsigned short)(raw_data[raw_data_index + 7 + idx * 3]
+			& 0xF0) << 4;
+		descriptor->aspect_ratio[idx] =
+			(raw_data[raw_data_index + 7 + idx * 3] & 0x0C) >> 2;
+		descriptor->preferred_vertical_rate[idx] =
+			(raw_data[raw_data_index + 8 + idx * 3] & 0x60) >> 5;
+		descriptor->supported_vertical_rate_and_blanking[idx] =
+			raw_data[raw_data_index + 8 + idx * 3] & 0x1F;
+	}
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT
+edid_parse_established_timings_3(S_ESTABLISHED_TIMINGS_3_DATA *descriptor,
+				 unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_ESTABLISHED_TIMINGS_3;
+	descriptor->header.tag = 0xF7;
+	descriptor->version = raw_data[raw_data_index + 5];
+	int idx;
+	for (idx = 0; idx < 6; idx++) {
+		descriptor->established_timings[idx] =
+			raw_data[raw_data_index + 6 + idx];
+	}
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_dummy(S_DUMMY_DATA *descriptor,
+					   unsigned char *raw_data)
+{
+	descriptor->header.type = DESCRIPTOR_TYPE_DUMMY;
+	descriptor->header.tag = 0x10;
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT
+edid_parse_manufacturer_specific(S_MANUFACTURER_SPECIFIC_DATA *descriptor,
+				 unsigned char *raw_data, unsigned char tag)
+{
+	descriptor->header.type = DESCRIPTOR_TYPE_MANUFACTURER_SPECIFIC;
+	descriptor->header.tag = tag;
+
+	return EDID_PARSER_SUCCESS;
+}
+
+EDID_PARSER_RESULT edid_parse(S_EDID_DATA *edid, unsigned char *raw_data,
+			      unsigned int len)
+{
+	unsigned int raw_data_index = 0;
+	unsigned char sum = 0;
+	/*CHECK SUM OF BYTES IN BLOCK0 */
+	for (raw_data_index = 0; raw_data_index < EDID_LENGTH; raw_data_index++)
+		sum += raw_data[raw_data_index];
+
+	if (sum != 0)
+		return EDID_PARSER_ERROR;
+
+	/*READ HEADER */
+	for (raw_data_index = 0; raw_data_index < EDID_HEADER_LENGTH;
+		raw_data_index++)
+		edid->header[raw_data_index] = raw_data[raw_data_index];
+
+	/*READ VENDOR & PRODUCT IDENTIFICATION */
+	/*manufacturer name */
+	edid->manufacturer_name[0] = ((raw_data[8] & 0x7C) >> 2) + 0x40;
+	edid->manufacturer_name[1] =
+		((raw_data[8] & 0x03) << 3) + ((raw_data[9] & 0xE0) >> 5) +
+		0x40;
+	edid->manufacturer_name[2] = ((raw_data[9] & 0x1F)) + 0x40;
+	edid->manufacturer_name[3] = 0;
+
+	/*product code */
+	edid->product_code = (raw_data[10]);
+	edid->product_code += ((unsigned short)raw_data[11]) << 8;
+
+	/*serial number */
+	edid->serial_number = raw_data[12];
+	edid->serial_number += (unsigned int)raw_data[13] << 8;
+	edid->serial_number += (unsigned int)raw_data[14] << 16;
+	edid->serial_number += (unsigned int)raw_data[15] << 24;
+
+	/*week of manufacture */
+	edid->week = raw_data[16];
+
+	/*year of manufacture */
+	edid->year = raw_data[17];
+
+	/*EDID STRUCTURE VERSION & REVISION */
+	edid->edid_version = ((unsigned short)raw_data[18] << 8) + raw_data[19];
+
+	/*BASIC DISPLAY PARAMETERS AND FEATURES */
+	/*video input definition */
+	edid->video_input_definition = raw_data[20];
+
+	/*horizontal screen size */
+	edid->horizontal_size = raw_data[21];
+
+	/*vertical screen size */
+	edid->vertical_size = raw_data[22];
+
+	/*display transfer characteristic */
+	edid->gamma = raw_data[23];
+
+	/*feature support */
+	edid->feature_support = raw_data[24];
+
+	/*COLOR CHARACTERISTIC */
+	/*red */
+	edid->chromacity_coorditates_red_x = (raw_data[25] & 0xC0) >> 6;
+	edid->chromacity_coorditates_red_x += (unsigned short)raw_data[27] << 2;
+	edid->chromacity_coorditates_red_y = (raw_data[25] & 0x30) >> 4;
+	edid->chromacity_coorditates_red_y += (unsigned short)raw_data[28] << 2;
+
+	/*green */
+	edid->chromacity_coorditates_green_x = (raw_data[25] & 0x0C) >> 2;
+	edid->chromacity_coorditates_green_x +=
+		(unsigned short)raw_data[29] << 2;
+	edid->chromacity_coorditates_green_y = (raw_data[25] & 0x03);
+	edid->chromacity_coorditates_green_y +=
+		(unsigned short)raw_data[30] << 2;
+
+	/*blue */
+	edid->chromacity_coorditates_blue_x = (raw_data[26] & 0xC0) >> 6;
+	edid->chromacity_coorditates_blue_x +=
+		(unsigned short)raw_data[31] << 2;
+	edid->chromacity_coorditates_blue_y = (raw_data[26] & 0x30) >> 4;
+	edid->chromacity_coorditates_blue_y +=
+		(unsigned short)raw_data[32] << 2;
+
+	/*blue */
+	edid->chromacity_coorditates_white_x = (raw_data[26] & 0x0C) >> 2;
+	edid->chromacity_coorditates_white_x +=
+		(unsigned short)raw_data[33] << 2;
+	edid->chromacity_coorditates_white_y = (raw_data[26] & 0x03);
+	edid->chromacity_coorditates_white_y +=
+		(unsigned short)raw_data[34] << 2;
+
+	/*ESTABLISHED TIMINGS */
+	edid->established_timing_1 = raw_data[35];
+	edid->established_timing_2 = raw_data[36];
+	edid->manufacturer_timing = raw_data[37];
+
+	/*STANDARD TIMINGS */
+	for (raw_data_index = 0; raw_data_index < 8; raw_data_index++) {
+		edid->standard_timings[raw_data_index] =
+			raw_data[38 + (2 * raw_data_index)];
+		edid->standard_timings[raw_data_index] +=
+			(unsigned short)raw_data[38 + (2 * raw_data_index + 1)];
+	}
+	/*extensions */
+	edid->extensions = raw_data[126];
+
+	/*DESCRIPTORS */
+	unsigned int descriptor_index;
+	raw_data_index = 54;
+	for (descriptor_index = 0; descriptor_index < 4; descriptor_index++) {
+		if (raw_data[raw_data_index] == 0 &&
+		    raw_data[raw_data_index] == 0) {
+			/*display descriptor found */
+			unsigned char tag = raw_data[raw_data_index + 3];
+			if (tag == 0xFF) {
+				/*display product serial number */
+				S_SERIAL_NUMBER_DATA *descriptor =
+					(S_SERIAL_NUMBER_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_serial_number
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xFE) {
+				/*alphanumeric data string */
+				S_DATA_STRING_DATA *descriptor =
+					(S_DATA_STRING_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_data_string
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xFD) {
+				/*display range limits */
+				S_RANGE_LIMITS_DATA *descriptor =
+					(S_RANGE_LIMITS_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_range_limits
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xFC) {
+				/*display product name */
+				S_PRODUCT_NAME_DATA *descriptor =
+					(S_PRODUCT_NAME_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_product_name
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xFB) {
+				/*color point data */
+				S_COLOR_POINT_DATA *descriptor =
+					(S_COLOR_POINT_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_color_point
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xFA) {
+				/*standard timing identifications */
+				S_STANDARD_TIMING_DATA *descriptor =
+					(S_STANDARD_TIMING_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_standard_timing
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xF9) {
+				/*display color management (DCM) */
+				S_COLOR_MANAGEMENT_DATA *descriptor =
+					(S_COLOR_MANAGEMENT_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_color_management
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xF8) {
+				/*CVT 3 byte timing codes */
+				S_CVT_TIMING_CODES_DATA *descriptor =
+					(S_CVT_TIMING_CODES_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_cvt_timing_codes
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xF7) {
+				/*established timings III */
+				S_ESTABLISHED_TIMINGS_3_DATA *descriptor =
+					(S_ESTABLISHED_TIMINGS_3_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_established_timings_3
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0x10) {
+				/*dummy */
+				S_DUMMY_DATA *descriptor =
+					(S_DUMMY_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_dummy
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag <= 0x0F) {
+				/*manufacturer specific data */
+				S_MANUFACTURER_SPECIFIC_DATA *descriptor =
+					(S_MANUFACTURER_SPECIFIC_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_manufacturer_specific
+					(descriptor, raw_data + raw_data_index,
+					 tag) != EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+			}
+		} else {
+			/*detailed timing definition */
+			S_DTD_DATA *descriptor =
+				(S_DTD_DATA *)edid->
+				descriptors[descriptor_index];
+			if (edid_parse_dtd
+				(descriptor,
+				 raw_data + raw_data_index) !=
+				 EDID_PARSER_SUCCESS)
+				return EDID_PARSER_ERROR;
+		}
+		raw_data_index += 18;
+	}
+
+	return EDID_PARSER_SUCCESS;
+}
diff --git a/drivers/video/imx/hdp/edid_parser.h b/drivers/video/imx/hdp/edid_parser.h
new file mode 100644
index 0000000..13eb0b1
--- /dev/null
+++ b/drivers/video/imx/hdp/edid_parser.h
@@ -0,0 +1,297 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2015-2016 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * edid_parser.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef EDID_PARSER_H
+#define EDID_PARSER_H
+
+#define MAX_DESCRIPTOR_LENGTH 36
+#define MAX_RANGE_LIMITS_VIDEO_TIMING_LENGTH 12
+#define EDID_HEADER_LENGTH 8
+#define EDID_LENGTH 128
+
+typedef enum {
+	EDID_PARSER_SUCCESS,
+	EDID_PARSER_ERROR,
+} EDID_PARSER_RESULT;
+
+typedef enum {
+	DESCRIPTOR_TYPE_DTD,
+	DESCRIPTOR_TYPE_SERIAL_NUMBER,
+	DESCRIPTOR_TYPE_DATA_STRING,
+	DESCRIPTOR_TYPE_RANGE_LIMITS,
+	DESCRIPTOR_TYPE_PRODUCT_NAME,
+	DESCRIPTOR_TYPE_COLOR_POINT,
+	DESCRIPTOR_TYPE_STANDARD_TIMING,
+	DESCRIPTOR_TYPE_COLOR_MANAGEMENT,
+	DESCRIPTOR_TYPE_CVT_TIMING_CODES,
+	DESCRIPTOR_TYPE_ESTABLISHED_TIMINGS_3,
+	DESCRIPTOR_TYPE_DUMMY,
+	DESCRIPTOR_TYPE_MANUFACTURER_SPECIFIC
+} EDID_DESCRIPTOR_TYPE;
+
+typedef enum {
+	VIDEO_TIMING_DEFAULT_GTF,
+	VIDEO_TIMING_RANGE_LIMITS_ONLY,
+	VIDEO_TIMING_SECONDARY_GTF,
+	VIDEO_TIMING_CVT,
+} RANGE_LIMITS_VIDEO_TIMING_TYPE;
+
+/**
+ *  \brief Common descriptor header structure
+ */
+typedef struct {
+	EDID_DESCRIPTOR_TYPE type;
+	unsigned char tag;
+
+} S_DESCRIPTOR_HEADER_DATA;
+/**
+ *  \brief Detailed Timing Descriptor (DTD) structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned short pixel_clock;
+	unsigned short horizontal_addressable_video;
+	unsigned short horizontal_blanking;
+	unsigned short vertical_addressable_video;
+	unsigned short vertical_blanking;
+	unsigned short horizontal_front_porch;
+	unsigned short horizontal_sync_pulse_width;
+	unsigned short vertical_front_porch;
+	unsigned short vertical_sync_pulse_width;
+	unsigned short horizontal_addressable_video_image_size;
+	unsigned short vertical_addressable_video_image_size;
+	unsigned char horizontal_border;
+	unsigned char vertical_border;
+	unsigned char signal_features;
+} S_DTD_DATA;
+
+/**
+ *  \brief Serial Number Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char serial_number[13];
+
+} S_SERIAL_NUMBER_DATA;
+
+/**
+ *  \brief Data String Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	char data_string[13];
+
+} S_DATA_STRING_DATA;
+
+/**
+ *  \brief Range Limits Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char offset_flags;
+	unsigned char min_vertical_rate;
+	unsigned char max_vertical_rate;
+	unsigned char min_horizontal_rate;
+	unsigned char max_horizontal_rate;
+	unsigned char max_pixel_clock;
+	RANGE_LIMITS_VIDEO_TIMING_TYPE type;
+	unsigned char suport_flags[MAX_RANGE_LIMITS_VIDEO_TIMING_LENGTH];
+} S_RANGE_LIMITS_DATA;
+
+/**
+ *  \brief Range Limits Secondary GTF Flags structure
+ */
+typedef struct {
+	unsigned char start_break_frequency;
+	unsigned char c;
+	unsigned short m;
+	unsigned char k;
+	unsigned char j;
+
+} S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF;
+
+/**
+ *  \brief Range Limits CVT Flags structure
+ */
+typedef struct {
+	unsigned char cvt_version;
+	unsigned char additional_pixel_clock_precision;
+	unsigned short max_active_pixels;
+	unsigned char supported_ar;
+	unsigned char preferred_ar;
+	unsigned char blanking_support;
+	unsigned char supported_scalling;
+	unsigned char preferred_vertical_refresh_rate;
+} S_RANGE_LIMITS_VIDEO_TIMING_CVT;
+
+/**
+ *  \brief Product Name Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	char product_name[13];
+
+} S_PRODUCT_NAME_DATA;
+
+/**
+ *  \brief Color point Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char white_point_index_1;
+	unsigned short white_x_1;
+	unsigned short white_y_1;
+	unsigned char gamma_1;
+	unsigned char white_point_index_2;
+	unsigned short white_x_2;
+	unsigned short white_y_2;
+	unsigned char gamma_2;
+} S_COLOR_POINT_DATA;
+
+/**
+ *  \brief Standard Timing Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned short standard_timings[6];
+} S_STANDARD_TIMING_DATA;
+
+/**
+ *  \brief Color Management Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char version;
+	unsigned short red_a3;
+	unsigned short red_a2;
+	unsigned short green_a3;
+	unsigned short green_a2;
+	unsigned short blue_a3;
+	unsigned short blue_a2;
+} S_COLOR_MANAGEMENT_DATA;
+
+/**
+ *  \brief CVT 3 Byte Code Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char version;
+	unsigned short addressable_lines[4];
+	unsigned char aspect_ratio[4];
+	unsigned char preferred_vertical_rate[4];
+	unsigned char supported_vertical_rate_and_blanking[4];
+
+} S_CVT_TIMING_CODES_DATA;
+
+/**
+ *  \brief Established Timings 3 Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char version;
+	unsigned char established_timings[6];
+} S_ESTABLISHED_TIMINGS_3_DATA;
+
+/**
+ *  \brief Dummy Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+} S_DUMMY_DATA;
+
+/**
+ *  \brief Manufacturer Specific Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char desc_data[18];
+} S_MANUFACTURER_SPECIFIC_DATA;
+
+/**
+ *  \brief CEA-861 extension structure
+ */
+typedef struct {
+	unsigned char revision;
+	unsigned char underscan;
+	unsigned char audio;
+} S_CEA861_DATA;
+
+/**
+ *  \brief Extended Display Identification Data (EDID) structure
+ */
+typedef struct {
+	unsigned char header[8];
+	char manufacturer_name[4];
+	unsigned short product_code;
+	unsigned int serial_number;
+	unsigned char week;
+	unsigned short year;
+	unsigned short edid_version;
+	unsigned char video_input_definition;
+	unsigned char horizontal_size;
+	unsigned char vertical_size;
+	unsigned char gamma;
+	unsigned char feature_support;
+	unsigned short chromacity_coorditates_red_x;
+	unsigned short chromacity_coorditates_red_y;
+	unsigned short chromacity_coorditates_green_x;
+	unsigned short chromacity_coorditates_green_y;
+	unsigned short chromacity_coorditates_blue_x;
+	unsigned short chromacity_coorditates_blue_y;
+	unsigned short chromacity_coorditates_white_x;
+	unsigned short chromacity_coorditates_white_y;
+	unsigned char established_timing_1;
+	unsigned char established_timing_2;
+	unsigned char manufacturer_timing;
+	unsigned short standard_timings[8];
+	unsigned char descriptors[4][MAX_DESCRIPTOR_LENGTH];
+	unsigned char extensions;
+} S_EDID_DATA;
+
+EDID_PARSER_RESULT edid_parse(S_EDID_DATA *edid, unsigned char *raw_data,
+			      unsigned int len);
+
+#endif				/* EDID_PARSER_H */
diff --git a/drivers/video/imx/hdp/externs.h b/drivers/video/imx/hdp/externs.h
index 055f6ea..5be1192 100644
--- a/drivers/video/imx/hdp/externs.h
+++ b/drivers/video/imx/hdp/externs.h
@@ -35,7 +35,7 @@
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  ******************************************************************************
  *
diff --git a/drivers/video/imx/hdp/general_handler.h b/drivers/video/imx/hdp/general_handler.h
index 3656ef8..4a3132c 100644
--- a/drivers/video/imx/hdp/general_handler.h
+++ b/drivers/video/imx/hdp/general_handler.h
@@ -35,7 +35,7 @@
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  ******************************************************************************
  *
@@ -66,6 +66,7 @@
 #define GENERAL_WRITE_REGISTER          0x05
 #define GENERAL_WRITE_FIELD             0x06
 #define GENERAL_READ_REGISTER           0x07
+#define GENERAL_GET_HPD_STATE           0x11
 
 #define GENERAL_TEST_TRNG_SIMPLE        0xF0
 
diff --git a/drivers/video/imx/hdp/hdmi.h b/drivers/video/imx/hdp/hdmi.h
new file mode 100644
index 0000000..a898982
--- /dev/null
+++ b/drivers/video/imx/hdp/hdmi.h
@@ -0,0 +1,124 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2015-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * hdmi.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef _HDMI__
+#define _HDMI__
+/* ONLY ENUMS AND #DEFINES IN THIS FILE *
+ * THIS FILE WILL BE USED IN HOST'S API */
+
+#define EDID_SLAVE_ADDRESS                  0x50
+#define EDID_SEGMENT_SLAVE_ADDRESS          0x30
+#define SCDC_SLAVE_ADDRESS                  0x54
+
+typedef enum {
+	HDMI_TX_READ,
+	HDMI_TX_WRITE,
+	HDMI_TX_UPDATE_READ,
+	HDMI_TX_EDID,
+	HDMI_TX_EVENTS,
+	HDMI_TX_HPD_STATUS,
+	HDMI_TX_DEBUG_ECHO = 0xAA,
+	HDMI_TX_TEST = 0xBB,
+	HDMI_TX_EDID_INTERNAL = 0xF0,
+} HDMI_TX_OPCODE;
+
+typedef enum {
+	HDMI_I2C_ACK,
+	HDMI_I2C_NACK,
+	HDMI_I2C_TO,
+	HDMI_I2C_ARB_LOST,
+	HDMI_I2C_RRTO,
+	HDMI_I2C_RRT,
+    /** when i2c hardware didn't respond after some time */
+	HDMI_I2C_HW_TO,
+	HDMI_I2C_ERR		/*unspecified error */
+} HDMI_I2C_STATUS;
+
+typedef enum {
+	HDMI_RX_SET_EDID,
+	HDMI_RX_SCDC_SET,
+	HDMI_RX_SCDC_GET,
+	HDMI_RX_READ_EVENTS,
+	HDMI_RX_SET_HPD,
+
+	HDMI_RX_DEBUG_ECHO = 0xAA,
+	HDMI_RX_TEST = 0xBB,
+} HDMI_RX_OPCODE;
+
+typedef enum {
+	HDMI_SCDC_SINK_VER,
+	HDMI_SCDC_SOURCE_VER,
+} HDMI_SCDC_FIELD;
+
+/*/////////////////////////////////////// */
+/*/////////////////////////////////////// */
+typedef struct {
+	unsigned char sink_ver;
+	unsigned char manufacturer_oui_1;
+	unsigned char manufacturer_oui_2;
+	unsigned char manufacturer_oui_3;
+	unsigned char devId[8];
+	unsigned char hardware_major_rev;
+	unsigned char hardware_minor_rev;
+	unsigned char software_major_rev;
+	unsigned char software_minor_rev;
+	unsigned char manufacturerSpecific[34];
+} S_HDMI_SCDC_SET_MSG;
+
+typedef struct {
+	unsigned char source_ver;
+	unsigned char TMDS_Config;
+	unsigned char config_0;
+	unsigned char manufacturerSpecific[34];
+} S_HDMI_SCDC_GET_MSG;
+
+/*hpd events location */
+#define HDMI_RX_EVENT_5V_HIGH            0
+#define HDMI_RX_EVENT_5V_LOW             1
+#define HDMI_TX_EVENT_reserved           2
+#define HDMI_RX_EVENT_5V_VAL             3
+
+#endif /*_HDMI__ */
diff --git a/drivers/video/imx/hdp/mhl_hdtx_top.h b/drivers/video/imx/hdp/mhl_hdtx_top.h
new file mode 100644
index 0000000..ee105f8
--- /dev/null
+++ b/drivers/video/imx/hdp/mhl_hdtx_top.h
@@ -0,0 +1,220 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * mhl_hdtx_top.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef MHL_HDTX_TOP_H_
+#define MHL_HDTX_TOP_H_
+
+/* register SCHEDULER_H_SIZE */
+#define SCHEDULER_H_SIZE 0
+#define F_H_BLANK_SIZE(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_H_BLANK_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_H_ACTIVE_SIZE(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_H_ACTIVE_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register SCHEDULER_V_SIZE */
+#define SCHEDULER_V_SIZE 1
+#define F_V_BLANK_SIZE(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_V_BLANK_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_V_ACTIVE_SIZE(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_V_ACTIVE_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register SCHEDULER_KEEP_OUT */
+#define SCHEDULER_KEEP_OUT 2
+#define F_HKEEP_OUT(x) (((x) & ((1 << 9) - 1)) << 0)
+#define F_HKEEP_OUT_RD(x) (((x) & (((1 << 9) - 1) << 0)) >> 0)
+#define F_VKEEP_OUT_START(x) (((x) & ((1 << 11) - 1)) << 9)
+#define F_VKEEP_OUT_START_RD(x) (((x) & (((1 << 11) - 1) << 9)) >> 9)
+#define F_VKEEP_OUT_ZONE(x) (((x) & ((1 << 8) - 1)) << 20)
+#define F_VKEEP_OUT_ZONE_RD(x) (((x) & (((1 << 8) - 1) << 20)) >> 20)
+
+/* register HDTX_SIGNAL_FRONT_WIDTH */
+#define HDTX_SIGNAL_FRONT_WIDTH 3
+#define F_HFRONT(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_HFRONT_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_VFRONT(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_VFRONT_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register HDTX_SIGNAL_SYNC_WIDTH */
+#define HDTX_SIGNAL_SYNC_WIDTH 4
+#define F_HSYNC(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_HSYNC_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_VSYNC(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_VSYNC_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register HDTX_SIGNAL_BACK_WIDTH */
+#define HDTX_SIGNAL_BACK_WIDTH 5
+#define F_HBACK(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_HBACK_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_VBACK(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_VBACK_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register HDTX_CONTROLLER */
+#define HDTX_CONTROLLER 6
+#define F_HDMI_MODE(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_HDMI_MODE_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+#define F_VIF_DATA_WIDTH(x) (((x) & ((1 << 2) - 1)) << 2)
+#define F_VIF_DATA_WIDTH_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2)
+#define F_AUTO_MODE(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_AUTO_MODE_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_IL_PROG(x) (((x) & ((1 << 2) - 1)) << 5)
+#define F_IL_PROG_RD(x) (((x) & (((1 << 2) - 1) << 5)) >> 5)
+#define F_PIC_3D(x) (((x) & ((1 << 4) - 1)) << 7)
+#define F_PIC_3D_RD(x) (((x) & (((1 << 4) - 1) << 7)) >> 7)
+#define F_BCH_EN(x) (((x) & ((1 << 1) - 1)) << 11)
+#define F_BCH_EN_RD(x) (((x) & (((1 << 1) - 1) << 11)) >> 11)
+#define F_GCP_EN(x) (((x) & ((1 << 1) - 1)) << 12)
+#define F_GCP_EN_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12)
+#define F_SET_AVMUTE(x) (((x) & ((1 << 1) - 1)) << 13)
+#define F_SET_AVMUTE_RD(x) (((x) & (((1 << 1) - 1) << 13)) >> 13)
+#define F_CLEAR_AVMUTE(x) (((x) & ((1 << 1) - 1)) << 14)
+#define F_CLEAR_AVMUTE_RD(x) (((x) & (((1 << 1) - 1) << 14)) >> 14)
+#define F_DATA_EN(x) (((x) & ((1 << 1) - 1)) << 15)
+#define F_DATA_EN_RD(x) (((x) & (((1 << 1) - 1) << 15)) >> 15)
+#define F_HDMI_ENCODING(x) (((x) & ((1 << 2) - 1)) << 16)
+#define F_HDMI_ENCODING_RD(x) (((x) & (((1 << 2) - 1) << 16)) >> 16)
+#define F_HDMI2_PREAMBLE_EN(x) (((x) & ((1 << 1) - 1)) << 18)
+#define F_HDMI2_PREAMBLE_EN_RD(x) (((x) & (((1 << 1) - 1) << 18)) >> 18)
+#define F_HDMI2_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 19)
+#define F_HDMI2_CTRL_IL_MODE_RD(x) (((x) & (((1 << 1) - 1) << 19)) >> 19)
+
+/* register HDTX_HDCP */
+#define HDTX_HDCP 7
+#define F_HDTX_HDCP_SELECT(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_HDTX_HDCP_SELECT_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+#define F_ENC_BIT(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_ENC_BIT_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_HDCP_ENABLE_1P1_FEATURES(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_HDCP_ENABLE_1P1_FEATURES_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+#define F_HDCP_DELAY_FIFO_SW_RST(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_HDCP_DELAY_FIFO_SW_RST_RD(x) (((x)