| PRE lwl | |
| mem[0]: 0xaabbccdd | |
| mem[1]: 0x11223344 | |
| mem[2]: 0x1823194 | |
| mem[3]: 0x1823a08 | |
| mem[4]: 0x0 | |
| mem[5]: 0x77ff528c | |
| mem[6]: 0x77deb460 | |
| POST lwl | |
| mem[0]: 0xaabbccdd | |
| mem[1]: 0x11223344 | |
| mem[2]: 0x11223344 | |
| mem[3]: 0x223344dd | |
| mem[4]: 0x3344ccdd | |
| mem[5]: 0x44bbccdd | |
| mem[6]: 0x77deb460 | |
| PRE lwr | |
| mem[0]: 0xaabbccdd | |
| mem[1]: 0x11223344 | |
| mem[2]: 0x1823194 | |
| mem[3]: 0x1823a08 | |
| mem[4]: 0x0 | |
| mem[5]: 0x77ff528c | |
| mem[6]: 0x77deb460 | |
| POST lwr | |
| mem[0]: 0xaabbccdd | |
| mem[1]: 0x11223344 | |
| mem[2]: 0xaabbcc11 | |
| mem[3]: 0xaabb1122 | |
| mem[4]: 0xaa112233 | |
| mem[5]: 0x11223344 | |
| mem[6]: 0x77deb460 |