Add folding rules for: Sar64(x,0) and Sar32(x,0).  Immediate
shifts by zero seem to have a surprisingly large perf hit on
Intels, possibly due to the bizarre eflags/rflags semantics
involved.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2964 8f6e269a-dfd6-0310-a8e1-e2731360e62c
1 file changed