commit b597f20148cd99b9538334e4de27459a83c32e13
author zliu <zliu@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Wed Apr 15 01:15:31 2015 +0000
committer zliu <zliu@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Wed Apr 15 01:15:31 2015 +0000
tree 1c273213013159d9748762efd3bdcdce3070b8f4
parent 6faff00bed93ec774239ec0a67e4a21b7c06e11c

Fix the evCheck assertion for TileGX

Quote from Philippe's original email.
"When guest = amd64 and host = TILEGX, the
libvexmultiarch_test asserts in TILEGX code:
vex: priv/host_tilegx_defs.c:2361 (emit_TILEGXInstr):
Assertion `evCheckSzB_TILEGX() ==
(UChar*)p - (UChar*)p0' failed."

This patch make sure that evCheck always emits
exact 80 bytes instruction stream. 

By: Zhi-Gang Liu
zhg.liu@gmail.com




git-svn-id: svn://svn.valgrind.org/vex/trunk@3130 8f6e269a-dfd6-0310-a8e1-e2731360e62c

priv/host_tilegx_defs.c

diff --git a/priv/host_tilegx_defs.c b/priv/host_tilegx_defs.c
index 8bc88a9..d7eea6c 100644
--- a/priv/host_tilegx_defs.c
+++ b/priv/host_tilegx_defs.c
@@ -1348,11 +1348,10 @@
 
 static UChar *doAMode_IR ( UChar * p, UInt opc1, UInt rSD, TILEGXAMode * am )
 {
-  UInt rA; //, idx;
+  UInt rA;
   vassert(am->tag == GXam_IR);
 
   rA = iregNo(am->GXam.IR.base);
-  //idx = am->GXam.IR.index;
 
   if (opc1 == TILEGX_OPC_ST1 || opc1 == TILEGX_OPC_ST2 ||
       opc1 == TILEGX_OPC_ST4 || opc1 == TILEGX_OPC_ST) {
@@ -1381,19 +1380,29 @@
   return p;
 }
 
-/* Generate a machine-word sized load or store. Simplified version of
-   the GXin_Load and GXin_Store cases below. */
+/* Generate a machine-word sized load or store using exact 2 bundles.
+   Simplified version of the GXin_Load and GXin_Store cases below. */
 static UChar* do_load_or_store_machine_word ( UChar* p, Bool isLoad, UInt reg,
                                               TILEGXAMode* am )
 {
+  UInt rA = iregNo(am->GXam.IR.base);
+
   if (am->tag != GXam_IR)
     vpanic(__func__);
 
-  if (isLoad) /* load */
-    p = doAMode_IR(p, TILEGX_OPC_LD, reg, am);
-  else /* store */
-    p = doAMode_IR(p, TILEGX_OPC_ST, reg, am);
-
+  if (isLoad) /* load */ {
+     /* r51 is reserved scratch registers. */
+     p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
+				   51, rA, am->GXam.IR.index));
+     /* load from address in r51 to rSD. */
+     p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_LD, 2, reg, 51));
+  } else /* store */ {
+     /* r51 is reserved scratch registers. */
+     p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
+				   51, rA, am->GXam.IR.index));
+     /* store rSD to address in r51 */
+     p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ST, 2, 51, reg));
+  }
   return p;
 }