Improve front and back end support for SIMD instructions on Arm64.
Implement the following instructions -- some but not necessarily
all laneage combinations:
LD1 {vT.2d}, [Xn|SP]
ST1 {vT.2d}, [Xn|SP]
LD1 {vT.4s}, [Xn|SP]
ST1 {vT.4s}, [Xn|SP]
LD1 {vT.8h}, [Xn|SP]
ST1 {vT.8h}, [Xn|SP]
LD1 {vT.16b}, [Xn|SP]
ST1 {vT.16b}, [Xn|SP]
LD1 {vT.1d}, [Xn|SP]
ST1 {vT.1d}, [Xn|SP]
LD1 {vT.2s}, [Xn|SP]
ST1 {vT.2s}, [Xn|SP]
LD1 {vT.4h}, [Xn|SP]
ST1 {vT.4h}, [Xn|SP]
LD1 {vT.8b}, [Xn|SP]
ST1 {vT.8b}, [Xn|SP]
ST1 {vT.2d}, [xN|SP], #16
LD1 {vT.2d}, [xN|SP], #16
ST1 {vT.4s}, [xN|SP], #16
ST1 {vT.8h}, [xN|SP], #16
ST1 {vT.2s}, [xN|SP], #8
SCVTF Vd, Vn
UCVTF Vd, Vn
FADD Vd,Vn,Vm 1
FSUB Vd,Vn,Vm 2
FMUL Vd,Vn,Vm 3
FDIV Vd,Vn,Vm 4
FMLA Vd,Vn,Vm 5
FMLS Vd,Vn,Vm 6
ADD Vd.T, Vn.T, Vm.T
SUB Vd.T, Vn.T, Vm.T
XTN {,2}
DUP Vd.T, Vn.Ts[index]
git-svn-id: svn://svn.valgrind.org/vex/trunk@2810 8f6e269a-dfd6-0310-a8e1-e2731360e62c
6 files changed
