tree 0428e8b9daf0d67c5eab3020db6bc50ae3666e1d
parent a2cdc9f40d3bd7c3630b9cb51d2aba6556fb03f0
author sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> 1428331745 +0000
committer sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> 1428331745 +0000

arm64: add support for the following insns.  This completes support
for conversion instructions.

SCVTF d_d_imm, s_s_imm 
UCVTF d_d_imm, s_s_imm 
FCVTZS d_d_imm, s_s_imm 
FCVTZU d_d_imm, s_s_imm 
FCVTXN s_d 
SCVTF d_d, s_s 
UCVTF d_d, s_s 
SCVTF {2d_2d,4s_4s,2s_2s}_imm 
UCVTF {2d_2d,4s_4s,2s_2s}_imm 
FCVTZS {2d_2d,4s_4s,2s_2s}_imm 
FCVTZU {2d_2d,4s_4s,2s_2s}_imm 
FCVTXN 2s/4s_2d 
FCVTZ{S,U} {w,x}_{s,x}_#fbits 


git-svn-id: svn://svn.valgrind.org/vex/trunk@3119 8f6e269a-dfd6-0310-a8e1-e2731360e62c