No functional change.  Remove commented out code copied from the
arm32 port, which is never going to get used.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2925 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/priv/host_arm64_defs.c b/priv/host_arm64_defs.c
index 71135b9..c94ffbb 100644
--- a/priv/host_arm64_defs.c
+++ b/priv/host_arm64_defs.c
@@ -89,7 +89,6 @@
 HReg hregARM64_X5  ( void ) { return mkHReg(5,  HRcInt64, False); }
 HReg hregARM64_X6  ( void ) { return mkHReg(6,  HRcInt64, False); }
 HReg hregARM64_X7  ( void ) { return mkHReg(7,  HRcInt64, False); }
-//ZZ HReg hregARM_R8  ( void ) { return mkHReg(8,  HRcInt32, False); }
 HReg hregARM64_X9  ( void ) { return mkHReg(9,  HRcInt64, False); }
 HReg hregARM64_X10 ( void ) { return mkHReg(10, HRcInt64, False); }
 HReg hregARM64_X11 ( void ) { return mkHReg(11, HRcInt64, False); }
@@ -114,21 +113,11 @@
 HReg hregARM64_D11 ( void ) { return mkHReg(11, HRcFlt64, False); }
 HReg hregARM64_D12 ( void ) { return mkHReg(12, HRcFlt64, False); }
 HReg hregARM64_D13 ( void ) { return mkHReg(13, HRcFlt64, False); }
-//ZZ HReg hregARM_S26 ( void ) { return mkHReg(26, HRcFlt32, False); }
-//ZZ HReg hregARM_S27 ( void ) { return mkHReg(27, HRcFlt32, False); }
-//ZZ HReg hregARM_S28 ( void ) { return mkHReg(28, HRcFlt32, False); }
-//ZZ HReg hregARM_S29 ( void ) { return mkHReg(29, HRcFlt32, False); }
-//ZZ HReg hregARM_S30 ( void ) { return mkHReg(30, HRcFlt32, False); }
 HReg hregARM64_Q16 ( void ) { return mkHReg(16, HRcVec128, False); }
 HReg hregARM64_Q17 ( void ) { return mkHReg(17, HRcVec128, False); }
 HReg hregARM64_Q18 ( void ) { return mkHReg(18, HRcVec128, False); }
 HReg hregARM64_Q19 ( void ) { return mkHReg(19, HRcVec128, False); }
 HReg hregARM64_Q20 ( void ) { return mkHReg(20, HRcVec128, False); }
-//ZZ HReg hregARM_Q11 ( void ) { return mkHReg(11, HRcVec128, False); }
-//ZZ HReg hregARM_Q12 ( void ) { return mkHReg(12, HRcVec128, False); }
-//ZZ HReg hregARM_Q13 ( void ) { return mkHReg(13, HRcVec128, False); }
-//ZZ HReg hregARM_Q14 ( void ) { return mkHReg(14, HRcVec128, False); }
-//ZZ HReg hregARM_Q15 ( void ) { return mkHReg(15, HRcVec128, False); }
 
 void getAllocableRegs_ARM64 ( Int* nregs, HReg** arr )
 {
@@ -322,148 +311,6 @@
 }
 
 
-//ZZ /* --------- Mem AModes: Addressing Mode 2 --------- */
-//ZZ 
-//ZZ ARMAMode2* ARMAMode2_RI ( HReg reg, Int simm9 ) {
-//ZZ    ARMAMode2* am       = LibVEX_Alloc(sizeof(ARMAMode2));
-//ZZ    am->tag             = ARMam2_RI;
-//ZZ    am->ARMam2.RI.reg   = reg;
-//ZZ    am->ARMam2.RI.simm9 = simm9;
-//ZZ    vassert(-255 <= simm9 && simm9 <= 255);
-//ZZ    return am;
-//ZZ }
-//ZZ ARMAMode2* ARMAMode2_RR ( HReg base, HReg index ) {
-//ZZ    ARMAMode2* am       = LibVEX_Alloc(sizeof(ARMAMode2));
-//ZZ    am->tag             = ARMam2_RR;
-//ZZ    am->ARMam2.RR.base  = base;
-//ZZ    am->ARMam2.RR.index = index;
-//ZZ    return am;
-//ZZ }
-//ZZ 
-//ZZ void ppARMAMode2 ( ARMAMode2* am ) {
-//ZZ    switch (am->tag) {
-//ZZ       case ARMam2_RI:
-//ZZ          vex_printf("%d(", am->ARMam2.RI.simm9);
-//ZZ          ppHRegARM(am->ARMam2.RI.reg);
-//ZZ          vex_printf(")");
-//ZZ          break;
-//ZZ       case ARMam2_RR:
-//ZZ          vex_printf("(");
-//ZZ          ppHRegARM(am->ARMam2.RR.base);
-//ZZ          vex_printf(",");
-//ZZ          ppHRegARM(am->ARMam2.RR.index);
-//ZZ          vex_printf(")");
-//ZZ          break;
-//ZZ       default:
-//ZZ          vassert(0);
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ static void addRegUsage_ARMAMode2 ( HRegUsage* u, ARMAMode2* am ) {
-//ZZ    switch (am->tag) {
-//ZZ       case ARMam2_RI:
-//ZZ          addHRegUse(u, HRmRead, am->ARMam2.RI.reg);
-//ZZ          return;
-//ZZ       case ARMam2_RR:
-//ZZ          //    addHRegUse(u, HRmRead, am->ARMam2.RR.base);
-//ZZ          //    addHRegUse(u, HRmRead, am->ARMam2.RR.index);
-//ZZ          //   return;
-//ZZ       default:
-//ZZ          vpanic("addRegUsage_ARMAmode2");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ static void mapRegs_ARMAMode2 ( HRegRemap* m, ARMAMode2* am ) {
-//ZZ    switch (am->tag) {
-//ZZ       case ARMam2_RI:
-//ZZ          am->ARMam2.RI.reg = lookupHRegRemap(m, am->ARMam2.RI.reg);
-//ZZ          return;
-//ZZ       case ARMam2_RR:
-//ZZ          //am->ARMam2.RR.base =lookupHRegRemap(m, am->ARMam2.RR.base);
-//ZZ          //am->ARMam2.RR.index = lookupHRegRemap(m, am->ARMam2.RR.index);
-//ZZ          //return;
-//ZZ       default:
-//ZZ          vpanic("mapRegs_ARMAmode2");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ 
-//ZZ /* --------- Mem AModes: Addressing Mode VFP --------- */
-//ZZ 
-//ZZ ARMAModeV* mkARMAModeV ( HReg reg, Int simm11 ) {
-//ZZ    ARMAModeV* am = LibVEX_Alloc(sizeof(ARMAModeV));
-//ZZ    vassert(simm11 >= -1020 && simm11 <= 1020);
-//ZZ    vassert(0 == (simm11 & 3));
-//ZZ    am->reg    = reg;
-//ZZ    am->simm11 = simm11;
-//ZZ    return am;
-//ZZ }
-//ZZ 
-//ZZ void ppARMAModeV ( ARMAModeV* am ) {
-//ZZ    vex_printf("%d(", am->simm11);
-//ZZ    ppHRegARM(am->reg);
-//ZZ    vex_printf(")");
-//ZZ }
-//ZZ 
-//ZZ static void addRegUsage_ARMAModeV ( HRegUsage* u, ARMAModeV* am ) {
-//ZZ    addHRegUse(u, HRmRead, am->reg);
-//ZZ }
-//ZZ 
-//ZZ static void mapRegs_ARMAModeV ( HRegRemap* m, ARMAModeV* am ) {
-//ZZ    am->reg = lookupHRegRemap(m, am->reg);
-//ZZ }
-//ZZ 
-//ZZ 
-//ZZ /* --------- Mem AModes: Addressing Mode Neon ------- */
-//ZZ 
-//ZZ ARMAModeN *mkARMAModeN_RR ( HReg rN, HReg rM ) {
-//ZZ    ARMAModeN* am = LibVEX_Alloc(sizeof(ARMAModeN));
-//ZZ    am->tag = ARMamN_RR;
-//ZZ    am->ARMamN.RR.rN = rN;
-//ZZ    am->ARMamN.RR.rM = rM;
-//ZZ    return am;
-//ZZ }
-//ZZ 
-//ZZ ARMAModeN *mkARMAModeN_R ( HReg rN ) {
-//ZZ    ARMAModeN* am = LibVEX_Alloc(sizeof(ARMAModeN));
-//ZZ    am->tag = ARMamN_R;
-//ZZ    am->ARMamN.R.rN = rN;
-//ZZ    return am;
-//ZZ }
-//ZZ 
-//ZZ static void addRegUsage_ARMAModeN ( HRegUsage* u, ARMAModeN* am ) {
-//ZZ    if (am->tag == ARMamN_R) {
-//ZZ       addHRegUse(u, HRmRead, am->ARMamN.R.rN);
-//ZZ    } else {
-//ZZ       addHRegUse(u, HRmRead, am->ARMamN.RR.rN);
-//ZZ       addHRegUse(u, HRmRead, am->ARMamN.RR.rM);
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ static void mapRegs_ARMAModeN ( HRegRemap* m, ARMAModeN* am ) {
-//ZZ    if (am->tag == ARMamN_R) {
-//ZZ       am->ARMamN.R.rN = lookupHRegRemap(m, am->ARMamN.R.rN);
-//ZZ    } else {
-//ZZ       am->ARMamN.RR.rN = lookupHRegRemap(m, am->ARMamN.RR.rN);
-//ZZ       am->ARMamN.RR.rM = lookupHRegRemap(m, am->ARMamN.RR.rM);
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ void ppARMAModeN ( ARMAModeN* am ) {
-//ZZ    vex_printf("[");
-//ZZ    if (am->tag == ARMamN_R) {
-//ZZ       ppHRegARM(am->ARMamN.R.rN);
-//ZZ    } else {
-//ZZ       ppHRegARM(am->ARMamN.RR.rN);
-//ZZ    }
-//ZZ    vex_printf("]");
-//ZZ    if (am->tag == ARMamN_RR) {
-//ZZ       vex_printf(", ");
-//ZZ       ppHRegARM(am->ARMamN.RR.rM);
-//ZZ    }
-//ZZ }
-
-
 /* --------- Reg or uimm12<<{0,12} operands --------- */
 
 ARM64RIA* ARM64RIA_I12 ( UShort imm12, UChar shift ) {
@@ -636,138 +483,6 @@
 }
 
 
-//ZZ /* -------- Neon Immediate operatnd --------- */
-//ZZ 
-//ZZ ARMNImm* ARMNImm_TI ( UInt type, UInt imm8 ) {
-//ZZ    ARMNImm* i = LibVEX_Alloc(sizeof(ARMNImm));
-//ZZ    i->type = type;
-//ZZ    i->imm8 = imm8;
-//ZZ    return i;
-//ZZ }
-//ZZ 
-//ZZ ULong ARMNImm_to_Imm64 ( ARMNImm* imm ) {
-//ZZ    int i, j;
-//ZZ    ULong y, x = imm->imm8;
-//ZZ    switch (imm->type) {
-//ZZ       case 3:
-//ZZ          x = x << 8; /* fallthrough */
-//ZZ       case 2:
-//ZZ          x = x << 8; /* fallthrough */
-//ZZ       case 1:
-//ZZ          x = x << 8; /* fallthrough */
-//ZZ       case 0:
-//ZZ          return (x << 32) | x;
-//ZZ       case 5:
-//ZZ       case 6:
-//ZZ          if (imm->type == 5)
-//ZZ             x = x << 8;
-//ZZ          else
-//ZZ             x = (x << 8) | x;
-//ZZ          /* fallthrough */
-//ZZ       case 4:
-//ZZ          x = (x << 16) | x;
-//ZZ          return (x << 32) | x;
-//ZZ       case 8:
-//ZZ          x = (x << 8) | 0xFF;
-//ZZ          /* fallthrough */
-//ZZ       case 7:
-//ZZ          x = (x << 8) | 0xFF;
-//ZZ          return (x << 32) | x;
-//ZZ       case 9:
-//ZZ          x = 0;
-//ZZ          for (i = 7; i >= 0; i--) {
-//ZZ             y = ((ULong)imm->imm8 >> i) & 1;
-//ZZ             for (j = 0; j < 8; j++) {
-//ZZ                x = (x << 1) | y;
-//ZZ             }
-//ZZ          }
-//ZZ          return x;
-//ZZ       case 10:
-//ZZ          x |= (x & 0x80) << 5;
-//ZZ          x |= (~x & 0x40) << 5;
-//ZZ          x &= 0x187F; /* 0001 1000 0111 1111 */
-//ZZ          x |= (x & 0x40) << 4;
-//ZZ          x |= (x & 0x40) << 3;
-//ZZ          x |= (x & 0x40) << 2;
-//ZZ          x |= (x & 0x40) << 1;
-//ZZ          x = x << 19;
-//ZZ          x = (x << 32) | x;
-//ZZ          return x;
-//ZZ       default:
-//ZZ          vpanic("ARMNImm_to_Imm64");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ ARMNImm* Imm64_to_ARMNImm ( ULong x ) {
-//ZZ    ARMNImm tmp;
-//ZZ    if ((x & 0xFFFFFFFF) == (x >> 32)) {
-//ZZ       if ((x & 0xFFFFFF00) == 0)
-//ZZ          return ARMNImm_TI(0, x & 0xFF);
-//ZZ       if ((x & 0xFFFF00FF) == 0)
-//ZZ          return ARMNImm_TI(1, (x >> 8) & 0xFF);
-//ZZ       if ((x & 0xFF00FFFF) == 0)
-//ZZ          return ARMNImm_TI(2, (x >> 16) & 0xFF);
-//ZZ       if ((x & 0x00FFFFFF) == 0)
-//ZZ          return ARMNImm_TI(3, (x >> 24) & 0xFF);
-//ZZ       if ((x & 0xFFFF00FF) == 0xFF)
-//ZZ          return ARMNImm_TI(7, (x >> 8) & 0xFF);
-//ZZ       if ((x & 0xFF00FFFF) == 0xFFFF)
-//ZZ          return ARMNImm_TI(8, (x >> 16) & 0xFF);
-//ZZ       if ((x & 0xFFFF) == ((x >> 16) & 0xFFFF)) {
-//ZZ          if ((x & 0xFF00) == 0)
-//ZZ             return ARMNImm_TI(4, x & 0xFF);
-//ZZ          if ((x & 0x00FF) == 0)
-//ZZ             return ARMNImm_TI(5, (x >> 8) & 0xFF);
-//ZZ          if ((x & 0xFF) == ((x >> 8) & 0xFF))
-//ZZ             return ARMNImm_TI(6, x & 0xFF);
-//ZZ       }
-//ZZ       if ((x & 0x7FFFF) == 0) {
-//ZZ          tmp.type = 10;
-//ZZ          tmp.imm8 = ((x >> 19) & 0x7F) | ((x >> 24) & 0x80);
-//ZZ          if (ARMNImm_to_Imm64(&tmp) == x)
-//ZZ             return ARMNImm_TI(tmp.type, tmp.imm8);
-//ZZ       }
-//ZZ    } else {
-//ZZ       /* This can only be type 9. */
-//ZZ       tmp.imm8 = (((x >> 56) & 1) << 7)
-//ZZ                | (((x >> 48) & 1) << 6)
-//ZZ                | (((x >> 40) & 1) << 5)
-//ZZ                | (((x >> 32) & 1) << 4)
-//ZZ                | (((x >> 24) & 1) << 3)
-//ZZ                | (((x >> 16) & 1) << 2)
-//ZZ                | (((x >>  8) & 1) << 1)
-//ZZ                | (((x >>  0) & 1) << 0);
-//ZZ       tmp.type = 9;
-//ZZ       if (ARMNImm_to_Imm64 (&tmp) == x)
-//ZZ          return ARMNImm_TI(tmp.type, tmp.imm8);
-//ZZ    }
-//ZZ    return NULL;
-//ZZ }
-//ZZ 
-//ZZ void ppARMNImm (ARMNImm* i) {
-//ZZ    ULong x = ARMNImm_to_Imm64(i);
-//ZZ    vex_printf("0x%llX%llX", x, x);
-//ZZ }
-//ZZ 
-//ZZ /* -- Register or scalar operand --- */
-//ZZ 
-//ZZ ARMNRS* mkARMNRS(ARMNRS_tag tag, HReg reg, UInt index)
-//ZZ {
-//ZZ    ARMNRS *p = LibVEX_Alloc(sizeof(ARMNRS));
-//ZZ    p->tag = tag;
-//ZZ    p->reg = reg;
-//ZZ    p->index = index;
-//ZZ    return p;
-//ZZ }
-//ZZ 
-//ZZ void ppARMNRS(ARMNRS *p)
-//ZZ {
-//ZZ    ppHRegARM(p->reg);
-//ZZ    if (p->tag == ARMNRS_Scalar) {
-//ZZ       vex_printf("[%d]", p->index);
-//ZZ    }
-//ZZ }
-
 /* --------- Instructions. --------- */
 
 static const HChar* showARM64LogicOp ( ARM64LogicOp op ) {
@@ -1063,363 +778,6 @@
    }
 }
 
-//ZZ const HChar* showARMNeonBinOp ( ARMNeonBinOp op ) {
-//ZZ    switch (op) {
-//ZZ       case ARMneon_VAND: return "vand";
-//ZZ       case ARMneon_VORR: return "vorr";
-//ZZ       case ARMneon_VXOR: return "veor";
-//ZZ       case ARMneon_VADD: return "vadd";
-//ZZ       case ARMneon_VRHADDS: return "vrhadd";
-//ZZ       case ARMneon_VRHADDU: return "vrhadd";
-//ZZ       case ARMneon_VADDFP: return "vadd";
-//ZZ       case ARMneon_VPADDFP: return "vpadd";
-//ZZ       case ARMneon_VABDFP: return "vabd";
-//ZZ       case ARMneon_VSUB: return "vsub";
-//ZZ       case ARMneon_VSUBFP: return "vsub";
-//ZZ       case ARMneon_VMINU: return "vmin";
-//ZZ       case ARMneon_VMINS: return "vmin";
-//ZZ       case ARMneon_VMINF: return "vmin";
-//ZZ       case ARMneon_VMAXU: return "vmax";
-//ZZ       case ARMneon_VMAXS: return "vmax";
-//ZZ       case ARMneon_VMAXF: return "vmax";
-//ZZ       case ARMneon_VQADDU: return "vqadd";
-//ZZ       case ARMneon_VQADDS: return "vqadd";
-//ZZ       case ARMneon_VQSUBU: return "vqsub";
-//ZZ       case ARMneon_VQSUBS: return "vqsub";
-//ZZ       case ARMneon_VCGTU:  return "vcgt";
-//ZZ       case ARMneon_VCGTS:  return "vcgt";
-//ZZ       case ARMneon_VCGTF:  return "vcgt";
-//ZZ       case ARMneon_VCGEF:  return "vcgt";
-//ZZ       case ARMneon_VCGEU:  return "vcge";
-//ZZ       case ARMneon_VCGES:  return "vcge";
-//ZZ       case ARMneon_VCEQ:  return "vceq";
-//ZZ       case ARMneon_VCEQF:  return "vceq";
-//ZZ       case ARMneon_VPADD:   return "vpadd";
-//ZZ       case ARMneon_VPMINU:   return "vpmin";
-//ZZ       case ARMneon_VPMINS:   return "vpmin";
-//ZZ       case ARMneon_VPMINF:   return "vpmin";
-//ZZ       case ARMneon_VPMAXU:   return "vpmax";
-//ZZ       case ARMneon_VPMAXS:   return "vpmax";
-//ZZ       case ARMneon_VPMAXF:   return "vpmax";
-//ZZ       case ARMneon_VEXT:   return "vext";
-//ZZ       case ARMneon_VMUL:   return "vmuli";
-//ZZ       case ARMneon_VMULLU:   return "vmull";
-//ZZ       case ARMneon_VMULLS:   return "vmull";
-//ZZ       case ARMneon_VMULP:  return "vmul";
-//ZZ       case ARMneon_VMULFP:  return "vmul";
-//ZZ       case ARMneon_VMULLP:  return "vmul";
-//ZZ       case ARMneon_VQDMULH: return "vqdmulh";
-//ZZ       case ARMneon_VQRDMULH: return "vqrdmulh";
-//ZZ       case ARMneon_VQDMULL: return "vqdmull";
-//ZZ       case ARMneon_VTBL: return "vtbl";
-//ZZ       case ARMneon_VRECPS: return "vrecps";
-//ZZ       case ARMneon_VRSQRTS: return "vrecps";
-//ZZ       /* ... */
-//ZZ       default: vpanic("showARMNeonBinOp");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ const HChar* showARMNeonBinOpDataType ( ARMNeonBinOp op ) {
-//ZZ    switch (op) {
-//ZZ       case ARMneon_VAND:
-//ZZ       case ARMneon_VORR:
-//ZZ       case ARMneon_VXOR:
-//ZZ          return "";
-//ZZ       case ARMneon_VADD:
-//ZZ       case ARMneon_VSUB:
-//ZZ       case ARMneon_VEXT:
-//ZZ       case ARMneon_VMUL:
-//ZZ       case ARMneon_VPADD:
-//ZZ       case ARMneon_VTBL:
-//ZZ       case ARMneon_VCEQ:
-//ZZ          return ".i";
-//ZZ       case ARMneon_VRHADDU:
-//ZZ       case ARMneon_VMINU:
-//ZZ       case ARMneon_VMAXU:
-//ZZ       case ARMneon_VQADDU:
-//ZZ       case ARMneon_VQSUBU:
-//ZZ       case ARMneon_VCGTU:
-//ZZ       case ARMneon_VCGEU:
-//ZZ       case ARMneon_VMULLU:
-//ZZ       case ARMneon_VPMINU:
-//ZZ       case ARMneon_VPMAXU:
-//ZZ          return ".u";
-//ZZ       case ARMneon_VRHADDS:
-//ZZ       case ARMneon_VMINS:
-//ZZ       case ARMneon_VMAXS:
-//ZZ       case ARMneon_VQADDS:
-//ZZ       case ARMneon_VQSUBS:
-//ZZ       case ARMneon_VCGTS:
-//ZZ       case ARMneon_VCGES:
-//ZZ       case ARMneon_VQDMULL:
-//ZZ       case ARMneon_VMULLS:
-//ZZ       case ARMneon_VPMINS:
-//ZZ       case ARMneon_VPMAXS:
-//ZZ       case ARMneon_VQDMULH:
-//ZZ       case ARMneon_VQRDMULH:
-//ZZ          return ".s";
-//ZZ       case ARMneon_VMULP:
-//ZZ       case ARMneon_VMULLP:
-//ZZ          return ".p";
-//ZZ       case ARMneon_VADDFP:
-//ZZ       case ARMneon_VABDFP:
-//ZZ       case ARMneon_VPADDFP:
-//ZZ       case ARMneon_VSUBFP:
-//ZZ       case ARMneon_VMULFP:
-//ZZ       case ARMneon_VMINF:
-//ZZ       case ARMneon_VMAXF:
-//ZZ       case ARMneon_VPMINF:
-//ZZ       case ARMneon_VPMAXF:
-//ZZ       case ARMneon_VCGTF:
-//ZZ       case ARMneon_VCGEF:
-//ZZ       case ARMneon_VCEQF:
-//ZZ       case ARMneon_VRECPS:
-//ZZ       case ARMneon_VRSQRTS:
-//ZZ          return ".f";
-//ZZ       /* ... */
-//ZZ       default: vpanic("showARMNeonBinOpDataType");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ const HChar* showARMNeonUnOp ( ARMNeonUnOp op ) {
-//ZZ    switch (op) {
-//ZZ       case ARMneon_COPY: return "vmov";
-//ZZ       case ARMneon_COPYLS: return "vmov";
-//ZZ       case ARMneon_COPYLU: return "vmov";
-//ZZ       case ARMneon_COPYN: return "vmov";
-//ZZ       case ARMneon_COPYQNSS: return "vqmovn";
-//ZZ       case ARMneon_COPYQNUS: return "vqmovun";
-//ZZ       case ARMneon_COPYQNUU: return "vqmovn";
-//ZZ       case ARMneon_NOT: return "vmvn";
-//ZZ       case ARMneon_EQZ: return "vceq";
-//ZZ       case ARMneon_CNT: return "vcnt";
-//ZZ       case ARMneon_CLS: return "vcls";
-//ZZ       case ARMneon_CLZ: return "vclz";
-//ZZ       case ARMneon_DUP: return "vdup";
-//ZZ       case ARMneon_PADDLS: return "vpaddl";
-//ZZ       case ARMneon_PADDLU: return "vpaddl";
-//ZZ       case ARMneon_VQSHLNSS: return "vqshl";
-//ZZ       case ARMneon_VQSHLNUU: return "vqshl";
-//ZZ       case ARMneon_VQSHLNUS: return "vqshlu";
-//ZZ       case ARMneon_REV16: return "vrev16";
-//ZZ       case ARMneon_REV32: return "vrev32";
-//ZZ       case ARMneon_REV64: return "vrev64";
-//ZZ       case ARMneon_VCVTFtoU: return "vcvt";
-//ZZ       case ARMneon_VCVTFtoS: return "vcvt";
-//ZZ       case ARMneon_VCVTUtoF: return "vcvt";
-//ZZ       case ARMneon_VCVTStoF: return "vcvt";
-//ZZ       case ARMneon_VCVTFtoFixedU: return "vcvt";
-//ZZ       case ARMneon_VCVTFtoFixedS: return "vcvt";
-//ZZ       case ARMneon_VCVTFixedUtoF: return "vcvt";
-//ZZ       case ARMneon_VCVTFixedStoF: return "vcvt";
-//ZZ       case ARMneon_VCVTF32toF16: return "vcvt";
-//ZZ       case ARMneon_VCVTF16toF32: return "vcvt";
-//ZZ       case ARMneon_VRECIP: return "vrecip";
-//ZZ       case ARMneon_VRECIPF: return "vrecipf";
-//ZZ       case ARMneon_VNEGF: return "vneg";
-//ZZ       case ARMneon_ABS: return "vabs";
-//ZZ       case ARMneon_VABSFP: return "vabsfp";
-//ZZ       case ARMneon_VRSQRTEFP: return "vrsqrtefp";
-//ZZ       case ARMneon_VRSQRTE: return "vrsqrte";
-//ZZ       /* ... */
-//ZZ       default: vpanic("showARMNeonUnOp");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ const HChar* showARMNeonUnOpDataType ( ARMNeonUnOp op ) {
-//ZZ    switch (op) {
-//ZZ       case ARMneon_COPY:
-//ZZ       case ARMneon_NOT:
-//ZZ          return "";
-//ZZ       case ARMneon_COPYN:
-//ZZ       case ARMneon_EQZ:
-//ZZ       case ARMneon_CNT:
-//ZZ       case ARMneon_DUP:
-//ZZ       case ARMneon_REV16:
-//ZZ       case ARMneon_REV32:
-//ZZ       case ARMneon_REV64:
-//ZZ          return ".i";
-//ZZ       case ARMneon_COPYLU:
-//ZZ       case ARMneon_PADDLU:
-//ZZ       case ARMneon_COPYQNUU:
-//ZZ       case ARMneon_VQSHLNUU:
-//ZZ       case ARMneon_VRECIP:
-//ZZ       case ARMneon_VRSQRTE:
-//ZZ          return ".u";
-//ZZ       case ARMneon_CLS:
-//ZZ       case ARMneon_CLZ:
-//ZZ       case ARMneon_COPYLS:
-//ZZ       case ARMneon_PADDLS:
-//ZZ       case ARMneon_COPYQNSS:
-//ZZ       case ARMneon_COPYQNUS:
-//ZZ       case ARMneon_VQSHLNSS:
-//ZZ       case ARMneon_VQSHLNUS:
-//ZZ       case ARMneon_ABS:
-//ZZ          return ".s";
-//ZZ       case ARMneon_VRECIPF:
-//ZZ       case ARMneon_VNEGF:
-//ZZ       case ARMneon_VABSFP:
-//ZZ       case ARMneon_VRSQRTEFP:
-//ZZ          return ".f";
-//ZZ       case ARMneon_VCVTFtoU: return ".u32.f32";
-//ZZ       case ARMneon_VCVTFtoS: return ".s32.f32";
-//ZZ       case ARMneon_VCVTUtoF: return ".f32.u32";
-//ZZ       case ARMneon_VCVTStoF: return ".f32.s32";
-//ZZ       case ARMneon_VCVTF16toF32: return ".f32.f16";
-//ZZ       case ARMneon_VCVTF32toF16: return ".f16.f32";
-//ZZ       case ARMneon_VCVTFtoFixedU: return ".u32.f32";
-//ZZ       case ARMneon_VCVTFtoFixedS: return ".s32.f32";
-//ZZ       case ARMneon_VCVTFixedUtoF: return ".f32.u32";
-//ZZ       case ARMneon_VCVTFixedStoF: return ".f32.s32";
-//ZZ       /* ... */
-//ZZ       default: vpanic("showARMNeonUnOpDataType");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ const HChar* showARMNeonUnOpS ( ARMNeonUnOpS op ) {
-//ZZ    switch (op) {
-//ZZ       case ARMneon_SETELEM: return "vmov";
-//ZZ       case ARMneon_GETELEMU: return "vmov";
-//ZZ       case ARMneon_GETELEMS: return "vmov";
-//ZZ       case ARMneon_VDUP: return "vdup";
-//ZZ       /* ... */
-//ZZ       default: vpanic("showARMNeonUnarySOp");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ const HChar* showARMNeonUnOpSDataType ( ARMNeonUnOpS op ) {
-//ZZ    switch (op) {
-//ZZ       case ARMneon_SETELEM:
-//ZZ       case ARMneon_VDUP:
-//ZZ          return ".i";
-//ZZ       case ARMneon_GETELEMS:
-//ZZ          return ".s";
-//ZZ       case ARMneon_GETELEMU:
-//ZZ          return ".u";
-//ZZ       /* ... */
-//ZZ       default: vpanic("showARMNeonUnarySOp");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ const HChar* showARMNeonShiftOp ( ARMNeonShiftOp op ) {
-//ZZ    switch (op) {
-//ZZ       case ARMneon_VSHL: return "vshl";
-//ZZ       case ARMneon_VSAL: return "vshl";
-//ZZ       case ARMneon_VQSHL: return "vqshl";
-//ZZ       case ARMneon_VQSAL: return "vqshl";
-//ZZ       /* ... */
-//ZZ       default: vpanic("showARMNeonShiftOp");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ const HChar* showARMNeonShiftOpDataType ( ARMNeonShiftOp op ) {
-//ZZ    switch (op) {
-//ZZ       case ARMneon_VSHL:
-//ZZ       case ARMneon_VQSHL:
-//ZZ          return ".u";
-//ZZ       case ARMneon_VSAL:
-//ZZ       case ARMneon_VQSAL:
-//ZZ          return ".s";
-//ZZ       /* ... */
-//ZZ       default: vpanic("showARMNeonShiftOpDataType");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ const HChar* showARMNeonDualOp ( ARMNeonDualOp op ) {
-//ZZ    switch (op) {
-//ZZ       case ARMneon_TRN: return "vtrn";
-//ZZ       case ARMneon_ZIP: return "vzip";
-//ZZ       case ARMneon_UZP: return "vuzp";
-//ZZ       /* ... */
-//ZZ       default: vpanic("showARMNeonDualOp");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ const HChar* showARMNeonDualOpDataType ( ARMNeonDualOp op ) {
-//ZZ    switch (op) {
-//ZZ       case ARMneon_TRN:
-//ZZ       case ARMneon_ZIP:
-//ZZ       case ARMneon_UZP:
-//ZZ          return "i";
-//ZZ       /* ... */
-//ZZ       default: vpanic("showARMNeonDualOp");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ static const HChar* showARMNeonDataSize_wrk ( UInt size )
-//ZZ {
-//ZZ    switch (size) {
-//ZZ       case 0: return "8";
-//ZZ       case 1: return "16";
-//ZZ       case 2: return "32";
-//ZZ       case 3: return "64";
-//ZZ       default: vpanic("showARMNeonDataSize");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ static const HChar* showARMNeonDataSize ( ARMInstr* i )
-//ZZ {
-//ZZ    switch (i->tag) {
-//ZZ       case ARMin_NBinary:
-//ZZ          if (i->ARMin.NBinary.op == ARMneon_VEXT)
-//ZZ             return "8";
-//ZZ          if (i->ARMin.NBinary.op == ARMneon_VAND ||
-//ZZ              i->ARMin.NBinary.op == ARMneon_VORR ||
-//ZZ              i->ARMin.NBinary.op == ARMneon_VXOR)
-//ZZ             return "";
-//ZZ          return showARMNeonDataSize_wrk(i->ARMin.NBinary.size);
-//ZZ       case ARMin_NUnary:
-//ZZ          if (i->ARMin.NUnary.op == ARMneon_COPY ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_NOT ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VCVTF32toF16||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VCVTF16toF32||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedS ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedU ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VCVTFixedStoF ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VCVTFixedUtoF ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VCVTFtoS ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VCVTFtoU ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VCVTStoF ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VCVTUtoF)
-//ZZ             return "";
-//ZZ          if (i->ARMin.NUnary.op == ARMneon_VQSHLNSS ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VQSHLNUU ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VQSHLNUS) {
-//ZZ             UInt size;
-//ZZ             size = i->ARMin.NUnary.size;
-//ZZ             if (size & 0x40)
-//ZZ                return "64";
-//ZZ             if (size & 0x20)
-//ZZ                return "32";
-//ZZ             if (size & 0x10)
-//ZZ                return "16";
-//ZZ             if (size & 0x08)
-//ZZ                return "8";
-//ZZ             vpanic("showARMNeonDataSize");
-//ZZ          }
-//ZZ          return showARMNeonDataSize_wrk(i->ARMin.NUnary.size);
-//ZZ       case ARMin_NUnaryS:
-//ZZ          if (i->ARMin.NUnaryS.op == ARMneon_VDUP) {
-//ZZ             int size;
-//ZZ             size = i->ARMin.NUnaryS.size;
-//ZZ             if ((size & 1) == 1)
-//ZZ                return "8";
-//ZZ             if ((size & 3) == 2)
-//ZZ                return "16";
-//ZZ             if ((size & 7) == 4)
-//ZZ                return "32";
-//ZZ             vpanic("showARMNeonDataSize");
-//ZZ          }
-//ZZ          return showARMNeonDataSize_wrk(i->ARMin.NUnaryS.size);
-//ZZ       case ARMin_NShift:
-//ZZ          return showARMNeonDataSize_wrk(i->ARMin.NShift.size);
-//ZZ       case ARMin_NDual:
-//ZZ          return showARMNeonDataSize_wrk(i->ARMin.NDual.size);
-//ZZ       default:
-//ZZ          vpanic("showARMNeonDataSize");
-//ZZ    }
-//ZZ }
-
 ARM64Instr* ARM64Instr_Arith ( HReg dst,
                                HReg argL, ARM64RIA* argR, Bool isAdd ) {
    ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr));
@@ -1614,11 +972,6 @@
    i->tag        = ARM64in_MFence;
    return i;
 }
-//ZZ ARM64Instr* ARM64Instr_CLREX( void ) {
-//ZZ    ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr));
-//ZZ    i->tag        = ARM64in_CLREX;
-//ZZ    return i;
-//ZZ }
 ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) {
    ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr));
    i->tag                  = ARM64in_VLdStS;
@@ -1834,119 +1187,6 @@
    vassert(amtB >= 1 && amtB <= 15);
    return i;
 }
-//ZZ ARMInstr* ARMInstr_VAluS ( ARMVfpOp op, HReg dst, HReg argL, HReg argR ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag              = ARMin_VAluS;
-//ZZ    i->ARMin.VAluS.op   = op;
-//ZZ    i->ARMin.VAluS.dst  = dst;
-//ZZ    i->ARMin.VAluS.argL = argL;
-//ZZ    i->ARMin.VAluS.argR = argR;
-//ZZ    return i;
-//ZZ }
-//ZZ ARMInstr* ARMInstr_VCMovD ( ARMCondCode cond, HReg dst, HReg src ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag               = ARMin_VCMovD;
-//ZZ    i->ARMin.VCMovD.cond = cond;
-//ZZ    i->ARMin.VCMovD.dst  = dst;
-//ZZ    i->ARMin.VCMovD.src  = src;
-//ZZ    vassert(cond != ARMcc_AL);
-//ZZ    return i;
-//ZZ }
-//ZZ ARMInstr* ARMInstr_VCMovS ( ARMCondCode cond, HReg dst, HReg src ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag               = ARMin_VCMovS;
-//ZZ    i->ARMin.VCMovS.cond = cond;
-//ZZ    i->ARMin.VCMovS.dst  = dst;
-//ZZ    i->ARMin.VCMovS.src  = src;
-//ZZ    vassert(cond != ARMcc_AL);
-//ZZ    return i;
-//ZZ }
-//ZZ ARMInstr* ARMInstr_VXferD ( Bool toD, HReg dD, HReg rHi, HReg rLo ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag              = ARMin_VXferD;
-//ZZ    i->ARMin.VXferD.toD = toD;
-//ZZ    i->ARMin.VXferD.dD  = dD;
-//ZZ    i->ARMin.VXferD.rHi = rHi;
-//ZZ    i->ARMin.VXferD.rLo = rLo;
-//ZZ    return i;
-//ZZ }
-//ZZ ARMInstr* ARMInstr_VXferS ( Bool toS, HReg fD, HReg rLo ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag              = ARMin_VXferS;
-//ZZ    i->ARMin.VXferS.toS = toS;
-//ZZ    i->ARMin.VXferS.fD  = fD;
-//ZZ    i->ARMin.VXferS.rLo = rLo;
-//ZZ    return i;
-//ZZ }
-//ZZ ARMInstr* ARMInstr_VCvtID ( Bool iToD, Bool syned,
-//ZZ                             HReg dst, HReg src ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag                = ARMin_VCvtID;
-//ZZ    i->ARMin.VCvtID.iToD  = iToD;
-//ZZ    i->ARMin.VCvtID.syned = syned;
-//ZZ    i->ARMin.VCvtID.dst   = dst;
-//ZZ    i->ARMin.VCvtID.src   = src;
-//ZZ    return i;
-//ZZ }
-//ZZ ARMInstr* ARMInstr_NLdStD ( Bool isLoad, HReg dD, ARMAModeN *amode ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag                  = ARMin_NLdStD;
-//ZZ    i->ARMin.NLdStD.isLoad  = isLoad;
-//ZZ    i->ARMin.NLdStD.dD      = dD;
-//ZZ    i->ARMin.NLdStD.amode   = amode;
-//ZZ    return i;
-//ZZ }
-//ZZ 
-//ZZ ARMInstr* ARMInstr_NUnary ( ARMNeonUnOp op, HReg dQ, HReg nQ,
-//ZZ                             UInt size, Bool Q ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag                = ARMin_NUnary;
-//ZZ    i->ARMin.NUnary.op   = op;
-//ZZ    i->ARMin.NUnary.src  = nQ;
-//ZZ    i->ARMin.NUnary.dst  = dQ;
-//ZZ    i->ARMin.NUnary.size = size;
-//ZZ    i->ARMin.NUnary.Q    = Q;
-//ZZ    return i;
-//ZZ }
-//ZZ 
-//ZZ ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOpS op, ARMNRS* dst, ARMNRS* src,
-//ZZ                              UInt size, Bool Q ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag                = ARMin_NUnaryS;
-//ZZ    i->ARMin.NUnaryS.op   = op;
-//ZZ    i->ARMin.NUnaryS.src  = src;
-//ZZ    i->ARMin.NUnaryS.dst  = dst;
-//ZZ    i->ARMin.NUnaryS.size = size;
-//ZZ    i->ARMin.NUnaryS.Q    = Q;
-//ZZ    return i;
-//ZZ }
-//ZZ 
-//ZZ ARMInstr* ARMInstr_NDual ( ARMNeonDualOp op, HReg nQ, HReg mQ,
-//ZZ                            UInt size, Bool Q ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag                = ARMin_NDual;
-//ZZ    i->ARMin.NDual.op   = op;
-//ZZ    i->ARMin.NDual.arg1 = nQ;
-//ZZ    i->ARMin.NDual.arg2 = mQ;
-//ZZ    i->ARMin.NDual.size = size;
-//ZZ    i->ARMin.NDual.Q    = Q;
-//ZZ    return i;
-//ZZ }
-//ZZ 
-//ZZ ARMInstr* ARMInstr_NBinary ( ARMNeonBinOp op,
-//ZZ                              HReg dst, HReg argL, HReg argR,
-//ZZ                              UInt size, Bool Q ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag                = ARMin_NBinary;
-//ZZ    i->ARMin.NBinary.op   = op;
-//ZZ    i->ARMin.NBinary.argL = argL;
-//ZZ    i->ARMin.NBinary.argR = argR;
-//ZZ    i->ARMin.NBinary.dst  = dst;
-//ZZ    i->ARMin.NBinary.size = size;
-//ZZ    i->ARMin.NBinary.Q    = Q;
-//ZZ    return i;
-//ZZ }
-
 ARM64Instr* ARM64Instr_VImmQ (HReg rQ, UShort imm) {
    ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr));
    i->tag               = ARM64in_VImmQ;
@@ -2013,77 +1253,6 @@
    }
    return i;
 }
-
-//ZZ ARMInstr* ARMInstr_NCMovQ ( ARMCondCode cond, HReg dst, HReg src ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag               = ARMin_NCMovQ;
-//ZZ    i->ARMin.NCMovQ.cond = cond;
-//ZZ    i->ARMin.NCMovQ.dst  = dst;
-//ZZ    i->ARMin.NCMovQ.src  = src;
-//ZZ    vassert(cond != ARMcc_AL);
-//ZZ    return i;
-//ZZ }
-//ZZ 
-//ZZ ARMInstr* ARMInstr_NShift ( ARMNeonShiftOp op,
-//ZZ                             HReg dst, HReg argL, HReg argR,
-//ZZ                             UInt size, Bool Q ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag                = ARMin_NShift;
-//ZZ    i->ARMin.NShift.op   = op;
-//ZZ    i->ARMin.NShift.argL = argL;
-//ZZ    i->ARMin.NShift.argR = argR;
-//ZZ    i->ARMin.NShift.dst  = dst;
-//ZZ    i->ARMin.NShift.size = size;
-//ZZ    i->ARMin.NShift.Q    = Q;
-//ZZ    return i;
-//ZZ }
-//ZZ 
-//ZZ ARMInstr* ARMInstr_NShl64 ( HReg dst, HReg src, UInt amt )
-//ZZ {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag              = ARMin_NShl64;
-//ZZ    i->ARMin.NShl64.dst = dst;
-//ZZ    i->ARMin.NShl64.src = src;
-//ZZ    i->ARMin.NShl64.amt = amt;
-//ZZ    vassert(amt >= 1 && amt <= 63);
-//ZZ    return i;
-//ZZ }
-//ZZ 
-//ZZ /* Helper copy-pasted from isel.c */
-//ZZ static Bool fitsIn8x4 ( UInt* u8, UInt* u4, UInt u )
-//ZZ {
-//ZZ    UInt i;
-//ZZ    for (i = 0; i < 16; i++) {
-//ZZ       if (0 == (u & 0xFFFFFF00)) {
-//ZZ          *u8 = u;
-//ZZ          *u4 = i;
-//ZZ          return True;
-//ZZ       }
-//ZZ       u = ROR32(u, 30);
-//ZZ    }
-//ZZ    vassert(i == 16);
-//ZZ    return False;
-//ZZ }
-//ZZ 
-//ZZ ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) {
-//ZZ    UInt u8, u4;
-//ZZ    ARMInstr *i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    /* Try to generate single ADD if possible */
-//ZZ    if (fitsIn8x4(&u8, &u4, imm32)) {
-//ZZ       i->tag            = ARMin_Alu;
-//ZZ       i->ARMin.Alu.op   = ARMalu_ADD;
-//ZZ       i->ARMin.Alu.dst  = rD;
-//ZZ       i->ARMin.Alu.argL = rN;
-//ZZ       i->ARMin.Alu.argR = ARMRI84_I84(u8, u4);
-//ZZ    } else {
-//ZZ       i->tag               = ARMin_Add32;
-//ZZ       i->ARMin.Add32.rD    = rD;
-//ZZ       i->ARMin.Add32.rN    = rN;
-//ZZ       i->ARMin.Add32.imm32 = imm32;
-//ZZ    }
-//ZZ    return i;
-//ZZ }
-
 ARM64Instr* ARM64Instr_EvCheck ( ARM64AMode* amCounter,
                                  ARM64AMode* amFailAddr ) {
    ARM64Instr* i                 = LibVEX_Alloc(sizeof(ARM64Instr));
@@ -2093,12 +1262,6 @@
    return i;
 }
 
-//ZZ ARMInstr* ARMInstr_ProfInc ( void ) {
-//ZZ    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
-//ZZ    i->tag      = ARMin_ProfInc;
-//ZZ    return i;
-//ZZ }
-
 /* ... */
 
 void ppARM64Instr ( ARM64Instr* i ) {
@@ -2308,9 +1471,6 @@
       case ARM64in_MFence:
          vex_printf("(mfence) dsb sy; dmb sy; isb");
          return;
-//ZZ       case ARM64in_CLREX:
-//ZZ          vex_printf("clrex");
-//ZZ          return;
       case ARM64in_VLdStS:
          if (i->ARM64in.VLdStS.isLoad) {
             vex_printf("ldr    ");
@@ -2507,156 +1667,6 @@
          vex_printf(".16b, #%u", i->ARM64in.VExtV.amtB);
          return;
       }
-//ZZ       case ARMin_VAluS:
-//ZZ          vex_printf("f%-3ss ", showARMVfpOp(i->ARMin.VAluS.op));
-//ZZ          ppHRegARM(i->ARMin.VAluS.dst);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.VAluS.argL);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.VAluS.argR);
-//ZZ          return;
-//ZZ       case ARMin_VCMovD:
-//ZZ          vex_printf("fcpyd%s ", showARMCondCode(i->ARMin.VCMovD.cond));
-//ZZ          ppHRegARM(i->ARMin.VCMovD.dst);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.VCMovD.src);
-//ZZ          return;
-//ZZ       case ARMin_VCMovS:
-//ZZ          vex_printf("fcpys%s ", showARMCondCode(i->ARMin.VCMovS.cond));
-//ZZ          ppHRegARM(i->ARMin.VCMovS.dst);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.VCMovS.src);
-//ZZ          return;
-//ZZ       case ARMin_VXferD:
-//ZZ          vex_printf("vmov  ");
-//ZZ          if (i->ARMin.VXferD.toD) {
-//ZZ             ppHRegARM(i->ARMin.VXferD.dD);
-//ZZ             vex_printf(", ");
-//ZZ             ppHRegARM(i->ARMin.VXferD.rLo);
-//ZZ             vex_printf(", ");
-//ZZ             ppHRegARM(i->ARMin.VXferD.rHi);
-//ZZ          } else {
-//ZZ             ppHRegARM(i->ARMin.VXferD.rLo);
-//ZZ             vex_printf(", ");
-//ZZ             ppHRegARM(i->ARMin.VXferD.rHi);
-//ZZ             vex_printf(", ");
-//ZZ             ppHRegARM(i->ARMin.VXferD.dD);
-//ZZ          }
-//ZZ          return;
-//ZZ       case ARMin_VXferS:
-//ZZ          vex_printf("vmov  ");
-//ZZ          if (i->ARMin.VXferS.toS) {
-//ZZ             ppHRegARM(i->ARMin.VXferS.fD);
-//ZZ             vex_printf(", ");
-//ZZ             ppHRegARM(i->ARMin.VXferS.rLo);
-//ZZ          } else {
-//ZZ             ppHRegARM(i->ARMin.VXferS.rLo);
-//ZZ             vex_printf(", ");
-//ZZ             ppHRegARM(i->ARMin.VXferS.fD);
-//ZZ          }
-//ZZ          return;
-//ZZ       case ARMin_VCvtID: {
-//ZZ          const HChar* nm = "?";
-//ZZ          if (i->ARMin.VCvtID.iToD) {
-//ZZ             nm = i->ARMin.VCvtID.syned ? "fsitod" : "fuitod";
-//ZZ          } else {
-//ZZ             nm = i->ARMin.VCvtID.syned ? "ftosid" : "ftouid";
-//ZZ          }
-//ZZ          vex_printf("%s ", nm);
-//ZZ          ppHRegARM(i->ARMin.VCvtID.dst);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.VCvtID.src);
-//ZZ          return;
-//ZZ       }
-//ZZ       case ARMin_NLdStD:
-//ZZ          if (i->ARMin.NLdStD.isLoad)
-//ZZ             vex_printf("vld1.32 {");
-//ZZ          else
-//ZZ             vex_printf("vst1.32 {");
-//ZZ          ppHRegARM(i->ARMin.NLdStD.dD);
-//ZZ          vex_printf("} ");
-//ZZ          ppARMAModeN(i->ARMin.NLdStD.amode);
-//ZZ          return;
-//ZZ       case ARMin_NUnary:
-//ZZ          vex_printf("%s%s%s  ",
-//ZZ                     showARMNeonUnOp(i->ARMin.NUnary.op),
-//ZZ                     showARMNeonUnOpDataType(i->ARMin.NUnary.op),
-//ZZ                     showARMNeonDataSize(i));
-//ZZ          ppHRegARM(i->ARMin.NUnary.dst);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.NUnary.src);
-//ZZ          if (i->ARMin.NUnary.op == ARMneon_EQZ)
-//ZZ             vex_printf(", #0");
-//ZZ          if (i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedS ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedU ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VCVTFixedStoF ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VCVTFixedUtoF) {
-//ZZ             vex_printf(", #%d", i->ARMin.NUnary.size);
-//ZZ          }
-//ZZ          if (i->ARMin.NUnary.op == ARMneon_VQSHLNSS ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VQSHLNUU ||
-//ZZ              i->ARMin.NUnary.op == ARMneon_VQSHLNUS) {
-//ZZ             UInt size;
-//ZZ             size = i->ARMin.NUnary.size;
-//ZZ             if (size & 0x40) {
-//ZZ                vex_printf(", #%d", size - 64);
-//ZZ             } else if (size & 0x20) {
-//ZZ                vex_printf(", #%d", size - 32);
-//ZZ             } else if (size & 0x10) {
-//ZZ                vex_printf(", #%d", size - 16);
-//ZZ             } else if (size & 0x08) {
-//ZZ                vex_printf(", #%d", size - 8);
-//ZZ             }
-//ZZ          }
-//ZZ          return;
-//ZZ       case ARMin_NUnaryS:
-//ZZ          vex_printf("%s%s%s  ",
-//ZZ                     showARMNeonUnOpS(i->ARMin.NUnaryS.op),
-//ZZ                     showARMNeonUnOpSDataType(i->ARMin.NUnaryS.op),
-//ZZ                     showARMNeonDataSize(i));
-//ZZ          ppARMNRS(i->ARMin.NUnaryS.dst);
-//ZZ          vex_printf(", ");
-//ZZ          ppARMNRS(i->ARMin.NUnaryS.src);
-//ZZ          return;
-//ZZ       case ARMin_NShift:
-//ZZ          vex_printf("%s%s%s  ",
-//ZZ                     showARMNeonShiftOp(i->ARMin.NShift.op),
-//ZZ                     showARMNeonShiftOpDataType(i->ARMin.NShift.op),
-//ZZ                     showARMNeonDataSize(i));
-//ZZ          ppHRegARM(i->ARMin.NShift.dst);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.NShift.argL);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.NShift.argR);
-//ZZ          return;
-//ZZ       case ARMin_NShl64:
-//ZZ          vex_printf("vshl.i64 ");
-//ZZ          ppHRegARM(i->ARMin.NShl64.dst);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.NShl64.src);
-//ZZ          vex_printf(", #%u", i->ARMin.NShl64.amt);
-//ZZ          return;
-//ZZ       case ARMin_NDual:
-//ZZ          vex_printf("%s%s%s  ",
-//ZZ                     showARMNeonDualOp(i->ARMin.NDual.op),
-//ZZ                     showARMNeonDualOpDataType(i->ARMin.NDual.op),
-//ZZ                     showARMNeonDataSize(i));
-//ZZ          ppHRegARM(i->ARMin.NDual.arg1);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.NDual.arg2);
-//ZZ          return;
-//ZZ       case ARMin_NBinary:
-//ZZ          vex_printf("%s%s%s",
-//ZZ                     showARMNeonBinOp(i->ARMin.NBinary.op),
-//ZZ                     showARMNeonBinOpDataType(i->ARMin.NBinary.op),
-//ZZ                     showARMNeonDataSize(i));
-//ZZ          vex_printf("  ");
-//ZZ          ppHRegARM(i->ARMin.NBinary.dst);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.NBinary.argL);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.NBinary.argR);
-//ZZ          return;
       case ARM64in_VImmQ:
          vex_printf("qimm   ");
          ppHRegARM64(i->ARM64in.VImmQ.rQ);
@@ -2710,20 +1720,6 @@
          ppHRegARM64(i->ARM64in.VMov.src);
          return;
    }
-//ZZ        case ARMin_NCMovQ:
-//ZZ          vex_printf("vmov%s ", showARMCondCode(i->ARMin.NCMovQ.cond));
-//ZZ          ppHRegARM(i->ARMin.NCMovQ.dst);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.NCMovQ.src);
-//ZZ          return;
-//ZZ       case ARMin_Add32:
-//ZZ          vex_printf("add32 ");
-//ZZ          ppHRegARM(i->ARMin.Add32.rD);
-//ZZ          vex_printf(", ");
-//ZZ          ppHRegARM(i->ARMin.Add32.rN);
-//ZZ          vex_printf(", ");
-//ZZ          vex_printf("%d", i->ARMin.Add32.imm32);
-//ZZ          return;
       case ARM64in_EvCheck:
          vex_printf("(evCheck) ldr w9,");
          ppARM64AMode(i->ARM64in.EvCheck.amCounter);
@@ -2910,8 +1906,6 @@
          return;
       case ARM64in_MFence:
          return;
-//ZZ       case ARMin_CLREX:
-//ZZ          return;
       case ARM64in_VLdStS:
          addHRegUse(u, HRmRead, i->ARM64in.VLdStS.rN);
          if (i->ARM64in.VLdStS.isLoad) {
@@ -3006,79 +2000,6 @@
          addHRegUse(u, HRmWrite, i->ARM64in.VExtV.dst);
          addHRegUse(u, HRmRead, i->ARM64in.VExtV.srcLo);
          addHRegUse(u, HRmRead, i->ARM64in.VExtV.srcHi);
-//ZZ       case ARMin_VAluS:
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.VAluS.dst);
-//ZZ          addHRegUse(u, HRmRead, i->ARMin.VAluS.argL);
-//ZZ          addHRegUse(u, HRmRead, i->ARMin.VAluS.argR);
-//ZZ          return;
-//ZZ       case ARMin_VUnaryS:
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.VUnaryS.dst);
-//ZZ          addHRegUse(u, HRmRead, i->ARMin.VUnaryS.src);
-//ZZ          return;
-//ZZ       case ARMin_VCMovD:
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.VCMovD.dst);
-//ZZ          addHRegUse(u, HRmRead,  i->ARMin.VCMovD.dst);
-//ZZ          addHRegUse(u, HRmRead,  i->ARMin.VCMovD.src);
-//ZZ          return;
-//ZZ       case ARMin_VCMovS:
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.VCMovS.dst);
-//ZZ          addHRegUse(u, HRmRead,  i->ARMin.VCMovS.dst);
-//ZZ          addHRegUse(u, HRmRead,  i->ARMin.VCMovS.src);
-//ZZ          return;
-//ZZ       case ARMin_VXferD:
-//ZZ          if (i->ARMin.VXferD.toD) {
-//ZZ             addHRegUse(u, HRmWrite, i->ARMin.VXferD.dD);
-//ZZ             addHRegUse(u, HRmRead,  i->ARMin.VXferD.rHi);
-//ZZ             addHRegUse(u, HRmRead,  i->ARMin.VXferD.rLo);
-//ZZ          } else {
-//ZZ             addHRegUse(u, HRmRead,  i->ARMin.VXferD.dD);
-//ZZ             addHRegUse(u, HRmWrite, i->ARMin.VXferD.rHi);
-//ZZ             addHRegUse(u, HRmWrite, i->ARMin.VXferD.rLo);
-//ZZ          }
-//ZZ          return;
-//ZZ       case ARMin_VXferS:
-//ZZ          if (i->ARMin.VXferS.toS) {
-//ZZ             addHRegUse(u, HRmWrite, i->ARMin.VXferS.fD);
-//ZZ             addHRegUse(u, HRmRead,  i->ARMin.VXferS.rLo);
-//ZZ          } else {
-//ZZ             addHRegUse(u, HRmRead,  i->ARMin.VXferS.fD);
-//ZZ             addHRegUse(u, HRmWrite, i->ARMin.VXferS.rLo);
-//ZZ          }
-//ZZ          return;
-//ZZ       case ARMin_VCvtID:
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.VCvtID.dst);
-//ZZ          addHRegUse(u, HRmRead,  i->ARMin.VCvtID.src);
-//ZZ          return;
-//ZZ       case ARMin_NLdStD:
-//ZZ          if (i->ARMin.NLdStD.isLoad)
-//ZZ             addHRegUse(u, HRmWrite, i->ARMin.NLdStD.dD);
-//ZZ          else
-//ZZ             addHRegUse(u, HRmRead, i->ARMin.NLdStD.dD);
-//ZZ          addRegUsage_ARMAModeN(u, i->ARMin.NLdStD.amode);
-//ZZ          return;
-//ZZ       case ARMin_NUnary:
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.NUnary.dst);
-//ZZ          addHRegUse(u, HRmRead, i->ARMin.NUnary.src);
-//ZZ          return;
-//ZZ       case ARMin_NUnaryS:
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.NUnaryS.dst->reg);
-//ZZ          addHRegUse(u, HRmRead, i->ARMin.NUnaryS.src->reg);
-//ZZ          return;
-//ZZ       case ARMin_NShift:
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.NShift.dst);
-//ZZ          addHRegUse(u, HRmRead, i->ARMin.NShift.argL);
-//ZZ          addHRegUse(u, HRmRead, i->ARMin.NShift.argR);
-//ZZ          return;
-//ZZ       case ARMin_NShl64:
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.NShl64.dst);
-//ZZ          addHRegUse(u, HRmRead, i->ARMin.NShl64.src);
-//ZZ          return;
-//ZZ       case ARMin_NDual:
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.NDual.arg1);
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.NDual.arg2);
-//ZZ          addHRegUse(u, HRmRead, i->ARMin.NDual.arg1);
-//ZZ          addHRegUse(u, HRmRead, i->ARMin.NDual.arg2);
-//ZZ          return;
       case ARM64in_VImmQ:
          addHRegUse(u, HRmWrite, i->ARM64in.VImmQ.rQ);
          return;
@@ -3107,22 +2028,6 @@
          addHRegUse(u, HRmWrite, i->ARM64in.VMov.dst);
          addHRegUse(u, HRmRead,  i->ARM64in.VMov.src);
          return;
-//ZZ       case ARMin_NBinary:
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.NBinary.dst);
-//ZZ          /* TODO: sometimes dst is also being read! */
-//ZZ          // XXX fix this
-//ZZ          addHRegUse(u, HRmRead, i->ARMin.NBinary.argL);
-//ZZ          addHRegUse(u, HRmRead, i->ARMin.NBinary.argR);
-//ZZ          return;
-//ZZ       case ARMin_NCMovQ:
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.NCMovQ.dst);
-//ZZ          addHRegUse(u, HRmRead,  i->ARMin.NCMovQ.dst);
-//ZZ          addHRegUse(u, HRmRead,  i->ARMin.NCMovQ.src);
-//ZZ          return;
-//ZZ       case ARMin_Add32:
-//ZZ          addHRegUse(u, HRmWrite, i->ARMin.Add32.rD);
-//ZZ          addHRegUse(u, HRmRead, i->ARMin.Add32.rN);
-//ZZ          return;
       case ARM64in_EvCheck:
          /* We expect both amodes only to mention x21, so this is in
             fact pointless, since x21 isn't allocatable, but
@@ -3232,8 +2137,6 @@
          return;
       case ARM64in_MFence:
          return;
-//ZZ       case ARMin_CLREX:
-//ZZ          return;
       case ARM64in_VLdStS:
          i->ARM64in.VLdStS.sD = lookupHRegRemap(m, i->ARM64in.VLdStS.sD);
          i->ARM64in.VLdStS.rN = lookupHRegRemap(m, i->ARM64in.VLdStS.rN);
@@ -3314,60 +2217,6 @@
          i->ARM64in.VExtV.srcLo = lookupHRegRemap(m, i->ARM64in.VExtV.srcLo);
          i->ARM64in.VExtV.srcHi = lookupHRegRemap(m, i->ARM64in.VExtV.srcHi);
          return;
-
-//ZZ       case ARMin_VAluS:
-//ZZ          i->ARMin.VAluS.dst  = lookupHRegRemap(m, i->ARMin.VAluS.dst);
-//ZZ          i->ARMin.VAluS.argL = lookupHRegRemap(m, i->ARMin.VAluS.argL);
-//ZZ          i->ARMin.VAluS.argR = lookupHRegRemap(m, i->ARMin.VAluS.argR);
-//ZZ          return;
-//ZZ       case ARMin_VCMovD:
-//ZZ          i->ARMin.VCMovD.dst = lookupHRegRemap(m, i->ARMin.VCMovD.dst);
-//ZZ          i->ARMin.VCMovD.src = lookupHRegRemap(m, i->ARMin.VCMovD.src);
-//ZZ          return;
-//ZZ       case ARMin_VCMovS:
-//ZZ          i->ARMin.VCMovS.dst = lookupHRegRemap(m, i->ARMin.VCMovS.dst);
-//ZZ          i->ARMin.VCMovS.src = lookupHRegRemap(m, i->ARMin.VCMovS.src);
-//ZZ          return;
-//ZZ       case ARMin_VXferD:
-//ZZ          i->ARMin.VXferD.dD  = lookupHRegRemap(m, i->ARMin.VXferD.dD);
-//ZZ          i->ARMin.VXferD.rHi = lookupHRegRemap(m, i->ARMin.VXferD.rHi);
-//ZZ          i->ARMin.VXferD.rLo = lookupHRegRemap(m, i->ARMin.VXferD.rLo);
-//ZZ          return;
-//ZZ       case ARMin_VXferS:
-//ZZ          i->ARMin.VXferS.fD  = lookupHRegRemap(m, i->ARMin.VXferS.fD);
-//ZZ          i->ARMin.VXferS.rLo = lookupHRegRemap(m, i->ARMin.VXferS.rLo);
-//ZZ          return;
-//ZZ       case ARMin_VCvtID:
-//ZZ          i->ARMin.VCvtID.dst = lookupHRegRemap(m, i->ARMin.VCvtID.dst);
-//ZZ          i->ARMin.VCvtID.src = lookupHRegRemap(m, i->ARMin.VCvtID.src);
-//ZZ          return;
-//ZZ       case ARMin_NLdStD:
-//ZZ          i->ARMin.NLdStD.dD = lookupHRegRemap(m, i->ARMin.NLdStD.dD);
-//ZZ          mapRegs_ARMAModeN(m, i->ARMin.NLdStD.amode);
-//ZZ          return;
-//ZZ       case ARMin_NUnary:
-//ZZ          i->ARMin.NUnary.src = lookupHRegRemap(m, i->ARMin.NUnary.src);
-//ZZ          i->ARMin.NUnary.dst = lookupHRegRemap(m, i->ARMin.NUnary.dst);
-//ZZ          return;
-//ZZ       case ARMin_NUnaryS:
-//ZZ          i->ARMin.NUnaryS.src->reg
-//ZZ             = lookupHRegRemap(m, i->ARMin.NUnaryS.src->reg);
-//ZZ          i->ARMin.NUnaryS.dst->reg
-//ZZ             = lookupHRegRemap(m, i->ARMin.NUnaryS.dst->reg);
-//ZZ          return;
-//ZZ       case ARMin_NShift:
-//ZZ          i->ARMin.NShift.dst = lookupHRegRemap(m, i->ARMin.NShift.dst);
-//ZZ          i->ARMin.NShift.argL = lookupHRegRemap(m, i->ARMin.NShift.argL);
-//ZZ          i->ARMin.NShift.argR = lookupHRegRemap(m, i->ARMin.NShift.argR);
-//ZZ          return;
-//ZZ       case ARMin_NShl64:
-//ZZ          i->ARMin.NShl64.dst = lookupHRegRemap(m, i->ARMin.NShl64.dst);
-//ZZ          i->ARMin.NShl64.src = lookupHRegRemap(m, i->ARMin.NShl64.src);
-//ZZ          return;
-//ZZ       case ARMin_NDual:
-//ZZ          i->ARMin.NDual.arg1 = lookupHRegRemap(m, i->ARMin.NDual.arg1);
-//ZZ          i->ARMin.NDual.arg2 = lookupHRegRemap(m, i->ARMin.NDual.arg2);
-//ZZ          return;
       case ARM64in_VImmQ:
          i->ARM64in.VImmQ.rQ = lookupHRegRemap(m, i->ARM64in.VImmQ.rQ);
          return;
@@ -3407,20 +2256,6 @@
          i->ARM64in.VMov.dst = lookupHRegRemap(m, i->ARM64in.VMov.dst);
          i->ARM64in.VMov.src = lookupHRegRemap(m, i->ARM64in.VMov.src);
          return;
-
-//ZZ       case ARMin_NBinary:
-//ZZ          i->ARMin.NBinary.argL = lookupHRegRemap(m, i->ARMin.NBinary.argL);
-//ZZ          i->ARMin.NBinary.argR = lookupHRegRemap(m, i->ARMin.NBinary.argR);
-//ZZ          i->ARMin.NBinary.dst  = lookupHRegRemap(m, i->ARMin.NBinary.dst);
-//ZZ          return;
-//ZZ       case ARMin_NCMovQ:
-//ZZ          i->ARMin.NCMovQ.dst = lookupHRegRemap(m, i->ARMin.NCMovQ.dst);
-//ZZ          i->ARMin.NCMovQ.src = lookupHRegRemap(m, i->ARMin.NCMovQ.src);
-//ZZ          return;
-//ZZ       case ARMin_Add32:
-//ZZ          i->ARMin.Add32.rD = lookupHRegRemap(m, i->ARMin.Add32.rD);
-//ZZ          i->ARMin.Add32.rN = lookupHRegRemap(m, i->ARMin.Add32.rN);
-//ZZ          return;
       case ARM64in_EvCheck:
          /* We expect both amodes only to mention x21, so this is in
             fact pointless, since x21 isn't allocatable, but
@@ -3902,42 +2737,6 @@
 #define XX______(zzx7,zzx6) \
    ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24))
 */
-//ZZ /* Generate a skeletal insn that involves an a RI84 shifter operand.
-//ZZ    Returns a word which is all zeroes apart from bits 25 and 11..0,
-//ZZ    since it is those that encode the shifter operand (at least to the
-//ZZ    extent that we care about it.) */
-//ZZ static UInt skeletal_RI84 ( ARMRI84* ri )
-//ZZ {
-//ZZ    UInt instr;
-//ZZ    if (ri->tag == ARMri84_I84) {
-//ZZ       vassert(0 == (ri->ARMri84.I84.imm4 & ~0x0F));
-//ZZ       vassert(0 == (ri->ARMri84.I84.imm8 & ~0xFF));
-//ZZ       instr = 1 << 25;
-//ZZ       instr |= (ri->ARMri84.I84.imm4 << 8);
-//ZZ       instr |= ri->ARMri84.I84.imm8;
-//ZZ    } else {
-//ZZ       instr = 0 << 25;
-//ZZ       instr |= iregNo(ri->ARMri84.R.reg);
-//ZZ    }
-//ZZ    return instr;
-//ZZ }
-//ZZ 
-//ZZ /* Ditto for RI5.  Resulting word is zeroes apart from bit 4 and bits
-//ZZ    11..7. */
-//ZZ static UInt skeletal_RI5 ( ARMRI5* ri )
-//ZZ {
-//ZZ    UInt instr;
-//ZZ    if (ri->tag == ARMri5_I5) {
-//ZZ       UInt imm5 = ri->ARMri5.I5.imm5;
-//ZZ       vassert(imm5 >= 1 && imm5 <= 31);
-//ZZ       instr = 0 << 4;
-//ZZ       instr |= imm5 << 7;
-//ZZ    } else {
-//ZZ       instr = 1 << 4;
-//ZZ       instr |= iregNo(ri->ARMri5.R.reg) << 8;
-//ZZ    }
-//ZZ    return instr;
-//ZZ }
 
 
 /* Get an immediate into a register, using only that register. */
@@ -4483,126 +3282,6 @@
                                 i->ARM64in.LdSt8.amode );
          goto done;
       }
-//ZZ       case ARMin_LdSt32:
-//ZZ       case ARMin_LdSt8U: {
-//ZZ          UInt        bL, bB;
-//ZZ          HReg        rD;
-//ZZ          ARMAMode1*  am;
-//ZZ          ARMCondCode cc;
-//ZZ          if (i->tag == ARMin_LdSt32) {
-//ZZ             bB = 0;
-//ZZ             bL = i->ARMin.LdSt32.isLoad ? 1 : 0;
-//ZZ             am = i->ARMin.LdSt32.amode;
-//ZZ             rD = i->ARMin.LdSt32.rD;
-//ZZ             cc = i->ARMin.LdSt32.cc;
-//ZZ          } else {
-//ZZ             bB = 1;
-//ZZ             bL = i->ARMin.LdSt8U.isLoad ? 1 : 0;
-//ZZ             am = i->ARMin.LdSt8U.amode;
-//ZZ             rD = i->ARMin.LdSt8U.rD;
-//ZZ             cc = i->ARMin.LdSt8U.cc;
-//ZZ          }
-//ZZ          vassert(cc != ARMcc_NV);
-//ZZ          if (am->tag == ARMam1_RI) {
-//ZZ             Int  simm12;
-//ZZ             UInt instr, bP;
-//ZZ             if (am->ARMam1.RI.simm13 < 0) {
-//ZZ                bP = 0;
-//ZZ                simm12 = -am->ARMam1.RI.simm13;
-//ZZ             } else {
-//ZZ                bP = 1;
-//ZZ                simm12 = am->ARMam1.RI.simm13;
-//ZZ             }
-//ZZ             vassert(simm12 >= 0 && simm12 <= 4095);
-//ZZ             instr = XXXXX___(cc,X0101,BITS4(bP,bB,0,bL),
-//ZZ                              iregNo(am->ARMam1.RI.reg),
-//ZZ                              iregNo(rD));
-//ZZ             instr |= simm12;
-//ZZ             *p++ = instr;
-//ZZ             goto done;
-//ZZ          } else {
-//ZZ             // RR case
-//ZZ             goto bad;
-//ZZ          }
-//ZZ       }
-//ZZ       case ARMin_LdSt16: {
-//ZZ          HReg        rD = i->ARMin.LdSt16.rD;
-//ZZ          UInt        bS = i->ARMin.LdSt16.signedLoad ? 1 : 0;
-//ZZ          UInt        bL = i->ARMin.LdSt16.isLoad ? 1 : 0;
-//ZZ          ARMAMode2*  am = i->ARMin.LdSt16.amode;
-//ZZ          ARMCondCode cc = i->ARMin.LdSt16.cc;
-//ZZ          vassert(cc != ARMcc_NV);
-//ZZ          if (am->tag == ARMam2_RI) {
-//ZZ             HReg rN = am->ARMam2.RI.reg;
-//ZZ             Int  simm8;
-//ZZ             UInt bP, imm8hi, imm8lo, instr;
-//ZZ             if (am->ARMam2.RI.simm9 < 0) {
-//ZZ                bP = 0;
-//ZZ                simm8 = -am->ARMam2.RI.simm9;
-//ZZ             } else {
-//ZZ                bP = 1;
-//ZZ                simm8 = am->ARMam2.RI.simm9;
-//ZZ             }
-//ZZ             vassert(simm8 >= 0 && simm8 <= 255);
-//ZZ             imm8hi = (simm8 >> 4) & 0xF;
-//ZZ             imm8lo = simm8 & 0xF;
-//ZZ             vassert(!(bL == 0 && bS == 1)); // "! signed store"
-//ZZ             /**/ if (bL == 0 && bS == 0) {
-//ZZ                // strh
-//ZZ                instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,0), iregNo(rN),
-//ZZ                                 iregNo(rD), imm8hi, X1011, imm8lo);
-//ZZ                *p++ = instr;
-//ZZ                goto done;
-//ZZ             }
-//ZZ             else if (bL == 1 && bS == 0) {
-//ZZ                // ldrh
-//ZZ                instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregNo(rN),
-//ZZ                                 iregNo(rD), imm8hi, X1011, imm8lo);
-//ZZ                *p++ = instr;
-//ZZ                goto done;
-//ZZ             }
-//ZZ             else if (bL == 1 && bS == 1) {
-//ZZ                // ldrsh
-//ZZ                instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregNo(rN),
-//ZZ                                 iregNo(rD), imm8hi, X1111, imm8lo);
-//ZZ                *p++ = instr;
-//ZZ                goto done;
-//ZZ             }
-//ZZ             else vassert(0); // ill-constructed insn
-//ZZ          } else {
-//ZZ             // RR case
-//ZZ             goto bad;
-//ZZ          }
-//ZZ       }
-//ZZ       case ARMin_Ld8S: {
-//ZZ          HReg        rD = i->ARMin.Ld8S.rD;
-//ZZ          ARMAMode2*  am = i->ARMin.Ld8S.amode;
-//ZZ          ARMCondCode cc = i->ARMin.Ld8S.cc;
-//ZZ          vassert(cc != ARMcc_NV);
-//ZZ          if (am->tag == ARMam2_RI) {
-//ZZ             HReg rN = am->ARMam2.RI.reg;
-//ZZ             Int  simm8;
-//ZZ             UInt bP, imm8hi, imm8lo, instr;
-//ZZ             if (am->ARMam2.RI.simm9 < 0) {
-//ZZ                bP = 0;
-//ZZ                simm8 = -am->ARMam2.RI.simm9;
-//ZZ             } else {
-//ZZ                bP = 1;
-//ZZ                simm8 = am->ARMam2.RI.simm9;
-//ZZ             }
-//ZZ             vassert(simm8 >= 0 && simm8 <= 255);
-//ZZ             imm8hi = (simm8 >> 4) & 0xF;
-//ZZ             imm8lo = simm8 & 0xF;
-//ZZ             // ldrsb
-//ZZ             instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregNo(rN),
-//ZZ                              iregNo(rD), imm8hi, X1101, imm8lo);
-//ZZ             *p++ = instr;
-//ZZ             goto done;
-//ZZ          } else {
-//ZZ             // RR case
-//ZZ             goto bad;
-//ZZ          }
-//ZZ       }
 
       case ARM64in_XDirect: {
          /* NB: what goes on here has to be very closely coordinated
@@ -6074,878 +4753,6 @@
                               X000000 | (imm4 << 1), vN, vD);
          goto done;
       }
-//ZZ       case ARMin_VAluS: {
-//ZZ          UInt dN = fregNo(i->ARMin.VAluS.argL);
-//ZZ          UInt dD = fregNo(i->ARMin.VAluS.dst);
-//ZZ          UInt dM = fregNo(i->ARMin.VAluS.argR);
-//ZZ          UInt bN = dN & 1;
-//ZZ          UInt bD = dD & 1;
-//ZZ          UInt bM = dM & 1;
-//ZZ          UInt pqrs = X1111; /* undefined */
-//ZZ          switch (i->ARMin.VAluS.op) {
-//ZZ             case ARMvfp_ADD: pqrs = X0110; break;
-//ZZ             case ARMvfp_SUB: pqrs = X0111; break;
-//ZZ             case ARMvfp_MUL: pqrs = X0100; break;
-//ZZ             case ARMvfp_DIV: pqrs = X1000; break;
-//ZZ             default: goto bad;
-//ZZ          }
-//ZZ          vassert(pqrs != X1111);
-//ZZ          UInt bP  = (pqrs >> 3) & 1;
-//ZZ          UInt bQ  = (pqrs >> 2) & 1;
-//ZZ          UInt bR  = (pqrs >> 1) & 1;
-//ZZ          UInt bS  = (pqrs >> 0) & 1;
-//ZZ          UInt insn = XXXXXXXX(0xE, X1110, BITS4(bP,bD,bQ,bR),
-//ZZ                               (dN >> 1), (dD >> 1),
-//ZZ                               X1010, BITS4(bN,bS,bM,0), (dM >> 1));
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
-//ZZ       case ARMin_VUnaryS: {
-//ZZ          UInt fD   = fregNo(i->ARMin.VUnaryS.dst);
-//ZZ          UInt fM   = fregNo(i->ARMin.VUnaryS.src);
-//ZZ          UInt insn = 0;
-//ZZ          switch (i->ARMin.VUnaryS.op) {
-//ZZ             case ARMvfpu_COPY:
-//ZZ                insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0000,
-//ZZ                                (fD >> 1), X1010, BITS4(0,1,(fM & 1),0),
-//ZZ                                (fM >> 1));
-//ZZ                break;
-//ZZ             case ARMvfpu_ABS:
-//ZZ                insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0000,
-//ZZ                                (fD >> 1), X1010, BITS4(1,1,(fM & 1),0),
-//ZZ                                (fM >> 1));
-//ZZ                break;
-//ZZ             case ARMvfpu_NEG:
-//ZZ                insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0001,
-//ZZ                                (fD >> 1), X1010, BITS4(0,1,(fM & 1),0),
-//ZZ                                (fM >> 1));
-//ZZ                break;
-//ZZ             case ARMvfpu_SQRT:
-//ZZ                insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0001,
-//ZZ                                (fD >> 1), X1010, BITS4(1,1,(fM & 1),0),
-//ZZ                                (fM >> 1));
-//ZZ                break;
-//ZZ             default:
-//ZZ                goto bad;
-//ZZ          }
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
-//ZZ       case ARMin_VCMovD: {
-//ZZ          UInt cc = (UInt)i->ARMin.VCMovD.cond;
-//ZZ          UInt dD = dregNo(i->ARMin.VCMovD.dst);
-//ZZ          UInt dM = dregNo(i->ARMin.VCMovD.src);
-//ZZ          vassert(cc < 16 && cc != ARMcc_AL);
-//ZZ          UInt insn = XXXXXXXX(cc, X1110,X1011,X0000,dD,X1011,X0100,dM);
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
-//ZZ       case ARMin_VCMovS: {
-//ZZ          UInt cc = (UInt)i->ARMin.VCMovS.cond;
-//ZZ          UInt fD = fregNo(i->ARMin.VCMovS.dst);
-//ZZ          UInt fM = fregNo(i->ARMin.VCMovS.src);
-//ZZ          vassert(cc < 16 && cc != ARMcc_AL);
-//ZZ          UInt insn = XXXXXXXX(cc, X1110, BITS4(1,(fD & 1),1,1),
-//ZZ                               X0000,(fD >> 1),X1010,
-//ZZ                               BITS4(0,1,(fM & 1),0), (fM >> 1));
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
-//ZZ       case ARMin_VXferD: {
-//ZZ          UInt dD  = dregNo(i->ARMin.VXferD.dD);
-//ZZ          UInt rHi = iregNo(i->ARMin.VXferD.rHi);
-//ZZ          UInt rLo = iregNo(i->ARMin.VXferD.rLo);
-//ZZ          /* vmov dD, rLo, rHi is
-//ZZ             E C 4 rHi rLo B (0,0,dD[4],1) dD[3:0]
-//ZZ             vmov rLo, rHi, dD is
-//ZZ             E C 5 rHi rLo B (0,0,dD[4],1) dD[3:0]
-//ZZ          */
-//ZZ          UInt insn
-//ZZ             = XXXXXXXX(0xE, 0xC, i->ARMin.VXferD.toD ? 4 : 5,
-//ZZ                        rHi, rLo, 0xB,
-//ZZ                        BITS4(0,0, ((dD >> 4) & 1), 1), (dD & 0xF));
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
-//ZZ       case ARMin_VXferS: {
-//ZZ          UInt fD  = fregNo(i->ARMin.VXferS.fD);
-//ZZ          UInt rLo = iregNo(i->ARMin.VXferS.rLo);
-//ZZ          /* vmov fD, rLo is
-//ZZ             E E 0 fD[4:1] rLo A (fD[0],0,0,1) 0
-//ZZ             vmov rLo, fD is
-//ZZ             E E 1 fD[4:1] rLo A (fD[0],0,0,1) 0
-//ZZ          */
-//ZZ          UInt insn
-//ZZ             = XXXXXXXX(0xE, 0xE, i->ARMin.VXferS.toS ? 0 : 1,
-//ZZ                        (fD >> 1) & 0xF, rLo, 0xA, 
-//ZZ                        BITS4((fD & 1),0,0,1), 0);
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
-//ZZ       case ARMin_VCvtID: {
-//ZZ          Bool iToD = i->ARMin.VCvtID.iToD;
-//ZZ          Bool syned = i->ARMin.VCvtID.syned;
-//ZZ          if (iToD && syned) {
-//ZZ             // FSITOD: I32S-in-freg to F64-in-dreg
-//ZZ             UInt regF = fregNo(i->ARMin.VCvtID.src);
-//ZZ             UInt regD = dregNo(i->ARMin.VCvtID.dst);
-//ZZ             UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD,
-//ZZ                                  X1011, BITS4(1,1,(regF & 1),0),
-//ZZ                                  (regF >> 1) & 0xF);
-//ZZ             *p++ = insn;
-//ZZ             goto done;
-//ZZ          }
-//ZZ          if (iToD && (!syned)) {
-//ZZ             // FUITOD: I32U-in-freg to F64-in-dreg
-//ZZ             UInt regF = fregNo(i->ARMin.VCvtID.src);
-//ZZ             UInt regD = dregNo(i->ARMin.VCvtID.dst);
-//ZZ             UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD,
-//ZZ                                  X1011, BITS4(0,1,(regF & 1),0),
-//ZZ                                  (regF >> 1) & 0xF);
-//ZZ             *p++ = insn;
-//ZZ             goto done;
-//ZZ          }
-//ZZ          if ((!iToD) && syned) {
-//ZZ             // FTOSID: F64-in-dreg to I32S-in-freg
-//ZZ             UInt regD = dregNo(i->ARMin.VCvtID.src);
-//ZZ             UInt regF = fregNo(i->ARMin.VCvtID.dst);
-//ZZ             UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(regF & 1),1,1),
-//ZZ                                  X1101, (regF >> 1) & 0xF,
-//ZZ                                  X1011, X0100, regD);
-//ZZ             *p++ = insn;
-//ZZ             goto done;
-//ZZ          }
-//ZZ          if ((!iToD) && (!syned)) {
-//ZZ             // FTOUID: F64-in-dreg to I32U-in-freg
-//ZZ             UInt regD = dregNo(i->ARMin.VCvtID.src);
-//ZZ             UInt regF = fregNo(i->ARMin.VCvtID.dst);
-//ZZ             UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(regF & 1),1,1),
-//ZZ                                  X1100, (regF >> 1) & 0xF,
-//ZZ                                  X1011, X0100, regD);
-//ZZ             *p++ = insn;
-//ZZ             goto done;
-//ZZ          }
-//ZZ          /*UNREACHED*/
-//ZZ          vassert(0);
-//ZZ       }
-//ZZ       case ARMin_NLdStD: {
-//ZZ          UInt regD = dregNo(i->ARMin.NLdStD.dD);
-//ZZ          UInt regN, regM;
-//ZZ          UInt D = regD >> 4;
-//ZZ          UInt bL = i->ARMin.NLdStD.isLoad ? 1 : 0;
-//ZZ          UInt insn;
-//ZZ          vassert(hregClass(i->ARMin.NLdStD.dD) == HRcFlt64);
-//ZZ          regD &= 0xF;
-//ZZ          if (i->ARMin.NLdStD.amode->tag == ARMamN_RR) {
-//ZZ             regN = iregNo(i->ARMin.NLdStD.amode->ARMamN.RR.rN);
-//ZZ             regM = iregNo(i->ARMin.NLdStD.amode->ARMamN.RR.rM);
-//ZZ          } else {
-//ZZ             regN = iregNo(i->ARMin.NLdStD.amode->ARMamN.R.rN);
-//ZZ             regM = 15;
-//ZZ          }
-//ZZ          insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0),
-//ZZ                               regN, regD, X0111, X1000, regM);
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
-//ZZ       case ARMin_NUnaryS: {
-//ZZ          UInt Q = i->ARMin.NUnaryS.Q ? 1 : 0;
-//ZZ          UInt regD, D;
-//ZZ          UInt regM, M;
-//ZZ          UInt size = i->ARMin.NUnaryS.size;
-//ZZ          UInt insn;
-//ZZ          UInt opc, opc1, opc2;
-//ZZ          switch (i->ARMin.NUnaryS.op) {
-//ZZ 	    case ARMneon_VDUP:
-//ZZ                if (i->ARMin.NUnaryS.size >= 16)
-//ZZ                   goto bad;
-//ZZ                if (i->ARMin.NUnaryS.dst->tag != ARMNRS_Reg)
-//ZZ                   goto bad;
-//ZZ                if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar)
-//ZZ                   goto bad;
-//ZZ                regD = (hregClass(i->ARMin.NUnaryS.dst->reg) == HRcVec128)
-//ZZ                         ? (qregNo(i->ARMin.NUnaryS.dst->reg) << 1)
-//ZZ                         : dregNo(i->ARMin.NUnaryS.dst->reg);
-//ZZ                regM = (hregClass(i->ARMin.NUnaryS.src->reg) == HRcVec128)
-//ZZ                         ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1)
-//ZZ                         : dregNo(i->ARMin.NUnaryS.src->reg);
-//ZZ                D = regD >> 4;
-//ZZ                M = regM >> 4;
-//ZZ                regD &= 0xf;
-//ZZ                regM &= 0xf;
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1),
-//ZZ                                (i->ARMin.NUnaryS.size & 0xf), regD,
-//ZZ                                X1100, BITS4(0,Q,M,0), regM);
-//ZZ                *p++ = insn;
-//ZZ                goto done; 
-//ZZ             case ARMneon_SETELEM:
-//ZZ                regD = Q ? (qregNo(i->ARMin.NUnaryS.dst->reg) << 1) :
-//ZZ                                 dregNo(i->ARMin.NUnaryS.dst->reg);
-//ZZ                regM = iregNo(i->ARMin.NUnaryS.src->reg);
-//ZZ                M = regM >> 4;
-//ZZ                D = regD >> 4;
-//ZZ                regM &= 0xF;
-//ZZ                regD &= 0xF;
-//ZZ                if (i->ARMin.NUnaryS.dst->tag != ARMNRS_Scalar)
-//ZZ                   goto bad;
-//ZZ                switch (size) {
-//ZZ                   case 0:
-//ZZ                      if (i->ARMin.NUnaryS.dst->index > 7)
-//ZZ                         goto bad;
-//ZZ                      opc = X1000 | i->ARMin.NUnaryS.dst->index;
-//ZZ                      break;
-//ZZ                   case 1:
-//ZZ                      if (i->ARMin.NUnaryS.dst->index > 3)
-//ZZ                         goto bad;
-//ZZ                      opc = X0001 | (i->ARMin.NUnaryS.dst->index << 1);
-//ZZ                      break;
-//ZZ                   case 2:
-//ZZ                      if (i->ARMin.NUnaryS.dst->index > 1)
-//ZZ                         goto bad;
-//ZZ                      opc = X0000 | (i->ARMin.NUnaryS.dst->index << 2);
-//ZZ                      break;
-//ZZ                   default:
-//ZZ                      goto bad;
-//ZZ                }
-//ZZ                opc1 = (opc >> 2) & 3;
-//ZZ                opc2 = opc & 3;
-//ZZ                insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),0),
-//ZZ                                regD, regM, X1011,
-//ZZ                                BITS4(D,(opc2 >> 1),(opc2 & 1),1), X0000);
-//ZZ                *p++ = insn;
-//ZZ                goto done;
-//ZZ             case ARMneon_GETELEMU:
-//ZZ                regM = Q ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1) :
-//ZZ                                 dregNo(i->ARMin.NUnaryS.src->reg);
-//ZZ                regD = iregNo(i->ARMin.NUnaryS.dst->reg);
-//ZZ                M = regM >> 4;
-//ZZ                D = regD >> 4;
-//ZZ                regM &= 0xF;
-//ZZ                regD &= 0xF;
-//ZZ                if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar)
-//ZZ                   goto bad;
-//ZZ                switch (size) {
-//ZZ                   case 0:
-//ZZ                      if (Q && i->ARMin.NUnaryS.src->index > 7) {
-//ZZ                         regM++;
-//ZZ                         i->ARMin.NUnaryS.src->index -= 8;
-//ZZ                      }
-//ZZ                      if (i->ARMin.NUnaryS.src->index > 7)
-//ZZ                         goto bad;
-//ZZ                      opc = X1000 | i->ARMin.NUnaryS.src->index;
-//ZZ                      break;
-//ZZ                   case 1:
-//ZZ                      if (Q && i->ARMin.NUnaryS.src->index > 3) {
-//ZZ                         regM++;
-//ZZ                         i->ARMin.NUnaryS.src->index -= 4;
-//ZZ                      }
-//ZZ                      if (i->ARMin.NUnaryS.src->index > 3)
-//ZZ                         goto bad;
-//ZZ                      opc = X0001 | (i->ARMin.NUnaryS.src->index << 1);
-//ZZ                      break;
-//ZZ                   case 2:
-//ZZ                      goto bad;
-//ZZ                   default:
-//ZZ                      goto bad;
-//ZZ                }
-//ZZ                opc1 = (opc >> 2) & 3;
-//ZZ                opc2 = opc & 3;
-//ZZ                insn = XXXXXXXX(0xE, X1110, BITS4(1,(opc1 >> 1),(opc1 & 1),1),
-//ZZ                                regM, regD, X1011,
-//ZZ                                BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000);
-//ZZ                *p++ = insn;
-//ZZ                goto done;
-//ZZ             case ARMneon_GETELEMS:
-//ZZ                regM = Q ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1) :
-//ZZ                                 dregNo(i->ARMin.NUnaryS.src->reg);
-//ZZ                regD = iregNo(i->ARMin.NUnaryS.dst->reg);
-//ZZ                M = regM >> 4;
-//ZZ                D = regD >> 4;
-//ZZ                regM &= 0xF;
-//ZZ                regD &= 0xF;
-//ZZ                if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar)
-//ZZ                   goto bad;
-//ZZ                switch (size) {
-//ZZ                   case 0:
-//ZZ                      if (Q && i->ARMin.NUnaryS.src->index > 7) {
-//ZZ                         regM++;
-//ZZ                         i->ARMin.NUnaryS.src->index -= 8;
-//ZZ                      }
-//ZZ                      if (i->ARMin.NUnaryS.src->index > 7)
-//ZZ                         goto bad;
-//ZZ                      opc = X1000 | i->ARMin.NUnaryS.src->index;
-//ZZ                      break;
-//ZZ                   case 1:
-//ZZ                      if (Q && i->ARMin.NUnaryS.src->index > 3) {
-//ZZ                         regM++;
-//ZZ                         i->ARMin.NUnaryS.src->index -= 4;
-//ZZ                      }
-//ZZ                      if (i->ARMin.NUnaryS.src->index > 3)
-//ZZ                         goto bad;
-//ZZ                      opc = X0001 | (i->ARMin.NUnaryS.src->index << 1);
-//ZZ                      break;
-//ZZ                   case 2:
-//ZZ                      if (Q && i->ARMin.NUnaryS.src->index > 1) {
-//ZZ                         regM++;
-//ZZ                         i->ARMin.NUnaryS.src->index -= 2;
-//ZZ                      }
-//ZZ                      if (i->ARMin.NUnaryS.src->index > 1)
-//ZZ                         goto bad;
-//ZZ                      opc = X0000 | (i->ARMin.NUnaryS.src->index << 2);
-//ZZ                      break;
-//ZZ                   default:
-//ZZ                      goto bad;
-//ZZ                }
-//ZZ                opc1 = (opc >> 2) & 3;
-//ZZ                opc2 = opc & 3;
-//ZZ                insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),1),
-//ZZ                                regM, regD, X1011,
-//ZZ                                BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000);
-//ZZ                *p++ = insn;
-//ZZ                goto done;
-//ZZ             default:
-//ZZ                goto bad;
-//ZZ          }
-//ZZ       }
-//ZZ       case ARMin_NUnary: {
-//ZZ          UInt Q = i->ARMin.NUnary.Q ? 1 : 0;
-//ZZ          UInt regD = (hregClass(i->ARMin.NUnary.dst) == HRcVec128)
-//ZZ                        ? (qregNo(i->ARMin.NUnary.dst) << 1)
-//ZZ                        : dregNo(i->ARMin.NUnary.dst);
-//ZZ          UInt regM, M;
-//ZZ          UInt D = regD >> 4;
-//ZZ          UInt sz1 = i->ARMin.NUnary.size >> 1;
-//ZZ          UInt sz2 = i->ARMin.NUnary.size & 1;
-//ZZ          UInt sz = i->ARMin.NUnary.size;
-//ZZ          UInt insn;
-//ZZ          UInt F = 0; /* TODO: floating point EQZ ??? */
-//ZZ          if (i->ARMin.NUnary.op != ARMneon_DUP) {
-//ZZ             regM = (hregClass(i->ARMin.NUnary.src) == HRcVec128) 
-//ZZ                      ? (qregNo(i->ARMin.NUnary.src) << 1)
-//ZZ                      : dregNo(i->ARMin.NUnary.src);
-//ZZ             M = regM >> 4;
-//ZZ          } else {
-//ZZ             regM = iregNo(i->ARMin.NUnary.src);
-//ZZ             M = regM >> 4;
-//ZZ          }
-//ZZ          regD &= 0xF;
-//ZZ          regM &= 0xF;
-//ZZ          switch (i->ARMin.NUnary.op) {
-//ZZ             case ARMneon_COPY: /* VMOV reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regM, regD, X0001,
-//ZZ                                BITS4(M,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_COPYN: /* VMOVN regD, regQ */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
-//ZZ                                regD, X0010, BITS4(0,0,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_COPYQNSS: /* VQMOVN regD, regQ */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
-//ZZ                                regD, X0010, BITS4(1,0,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_COPYQNUS: /* VQMOVUN regD, regQ */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
-//ZZ                                regD, X0010, BITS4(0,1,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_COPYQNUU: /* VQMOVN regD, regQ */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
-//ZZ                                regD, X0010, BITS4(1,1,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_COPYLS: /* VMOVL regQ, regD */
-//ZZ                if (sz >= 3)
-//ZZ                   goto bad;
-//ZZ                insn = XXXXXXXX(0xF, X0010,
-//ZZ                                BITS4(1,D,(sz == 2) ? 1 : 0,(sz == 1) ? 1 : 0),
-//ZZ                                BITS4((sz == 0) ? 1 : 0,0,0,0),
-//ZZ                                regD, X1010, BITS4(0,0,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_COPYLU: /* VMOVL regQ, regD */
-//ZZ                if (sz >= 3)
-//ZZ                   goto bad;
-//ZZ                insn = XXXXXXXX(0xF, X0011,
-//ZZ                                BITS4(1,D,(sz == 2) ? 1 : 0,(sz == 1) ? 1 : 0),
-//ZZ                                BITS4((sz == 0) ? 1 : 0,0,0,0),
-//ZZ                                regD, X1010, BITS4(0,0,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_NOT: /* VMVN reg, reg*/
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0000, regD, X0101,
-//ZZ                                BITS4(1,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_EQZ:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,1),
-//ZZ                                regD, BITS4(0,F,0,1), BITS4(0,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_CNT:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0000, regD, X0101,
-//ZZ                                BITS4(0,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_CLZ:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
-//ZZ                                regD, X0100, BITS4(1,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_CLS:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
-//ZZ                                regD, X0100, BITS4(0,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_ABS:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,1),
-//ZZ                                regD, X0011, BITS4(0,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_DUP:
-//ZZ                sz1 = i->ARMin.NUnary.size == 0 ? 1 : 0;
-//ZZ                sz2 = i->ARMin.NUnary.size == 1 ? 1 : 0;
-//ZZ                vassert(sz1 + sz2 < 2);
-//ZZ                insn = XXXXXXXX(0xE, X1110, BITS4(1, sz1, Q, 0), regD, regM,
-//ZZ                                X1011, BITS4(D,0,sz2,1), X0000);
-//ZZ                break;
-//ZZ             case ARMneon_REV16:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
-//ZZ                                regD, BITS4(0,0,0,1), BITS4(0,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_REV32:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
-//ZZ                                regD, BITS4(0,0,0,0), BITS4(1,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_REV64:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
-//ZZ                                regD, BITS4(0,0,0,0), BITS4(0,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_PADDLU:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
-//ZZ                                regD, X0010, BITS4(1,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_PADDLS:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
-//ZZ                                regD, X0010, BITS4(0,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VQSHLNUU:
-//ZZ                insn = XXXXXXXX(0xF, X0011,
-//ZZ                                (1 << 3) | (D << 2) | ((sz >> 4) & 3),
-//ZZ                                sz & 0xf, regD, X0111,
-//ZZ                                BITS4(sz >> 6,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VQSHLNSS:
-//ZZ                insn = XXXXXXXX(0xF, X0010,
-//ZZ                                (1 << 3) | (D << 2) | ((sz >> 4) & 3),
-//ZZ                                sz & 0xf, regD, X0111,
-//ZZ                                BITS4(sz >> 6,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VQSHLNUS:
-//ZZ                insn = XXXXXXXX(0xF, X0011,
-//ZZ                                (1 << 3) | (D << 2) | ((sz >> 4) & 3),
-//ZZ                                sz & 0xf, regD, X0110,
-//ZZ                                BITS4(sz >> 6,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCVTFtoS:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0111,
-//ZZ                                BITS4(0,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCVTFtoU:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0111,
-//ZZ                                BITS4(1,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCVTStoF:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0110,
-//ZZ                                BITS4(0,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCVTUtoF:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0110,
-//ZZ                                BITS4(1,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCVTFtoFixedU:
-//ZZ                sz1 = (sz >> 5) & 1;
-//ZZ                sz2 = (sz >> 4) & 1;
-//ZZ                sz &= 0xf;
-//ZZ                insn = XXXXXXXX(0xF, X0011,
-//ZZ                                BITS4(1,D,sz1,sz2), sz, regD, X1111,
-//ZZ                                BITS4(0,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCVTFtoFixedS:
-//ZZ                sz1 = (sz >> 5) & 1;
-//ZZ                sz2 = (sz >> 4) & 1;
-//ZZ                sz &= 0xf;
-//ZZ                insn = XXXXXXXX(0xF, X0010,
-//ZZ                                BITS4(1,D,sz1,sz2), sz, regD, X1111,
-//ZZ                                BITS4(0,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCVTFixedUtoF:
-//ZZ                sz1 = (sz >> 5) & 1;
-//ZZ                sz2 = (sz >> 4) & 1;
-//ZZ                sz &= 0xf;
-//ZZ                insn = XXXXXXXX(0xF, X0011,
-//ZZ                                BITS4(1,D,sz1,sz2), sz, regD, X1110,
-//ZZ                                BITS4(0,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCVTFixedStoF:
-//ZZ                sz1 = (sz >> 5) & 1;
-//ZZ                sz2 = (sz >> 4) & 1;
-//ZZ                sz &= 0xf;
-//ZZ                insn = XXXXXXXX(0xF, X0010,
-//ZZ                                BITS4(1,D,sz1,sz2), sz, regD, X1110,
-//ZZ                                BITS4(0,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCVTF32toF16:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0110, regD, X0110,
-//ZZ                                BITS4(0,0,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCVTF16toF32:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0110, regD, X0111,
-//ZZ                                BITS4(0,0,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VRECIP:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100,
-//ZZ                                BITS4(0,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VRECIPF:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0101,
-//ZZ                                BITS4(0,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VABSFP:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1001, regD, X0111,
-//ZZ                                BITS4(0,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VRSQRTEFP:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0101,
-//ZZ                                BITS4(1,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VRSQRTE:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100,
-//ZZ                                BITS4(1,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VNEGF:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1001, regD, X0111,
-//ZZ                                BITS4(1,Q,M,0), regM);
-//ZZ                break;
-//ZZ 
-//ZZ             default:
-//ZZ                goto bad;
-//ZZ          }
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
-//ZZ       case ARMin_NDual: {
-//ZZ          UInt Q = i->ARMin.NDual.Q ? 1 : 0;
-//ZZ          UInt regD = (hregClass(i->ARMin.NDual.arg1) == HRcVec128)
-//ZZ                        ? (qregNo(i->ARMin.NDual.arg1) << 1)
-//ZZ                        : dregNo(i->ARMin.NDual.arg1);
-//ZZ          UInt regM = (hregClass(i->ARMin.NDual.arg2) == HRcVec128)
-//ZZ                        ? (qregNo(i->ARMin.NDual.arg2) << 1)
-//ZZ                        : dregNo(i->ARMin.NDual.arg2);
-//ZZ          UInt D = regD >> 4;
-//ZZ          UInt M = regM >> 4;
-//ZZ          UInt sz1 = i->ARMin.NDual.size >> 1;
-//ZZ          UInt sz2 = i->ARMin.NDual.size & 1;
-//ZZ          UInt insn;
-//ZZ          regD &= 0xF;
-//ZZ          regM &= 0xF;
-//ZZ          switch (i->ARMin.NDual.op) {
-//ZZ             case ARMneon_TRN: /* VTRN reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
-//ZZ                                regD, X0000, BITS4(1,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_ZIP: /* VZIP reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
-//ZZ                                regD, X0001, BITS4(1,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_UZP: /* VUZP reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
-//ZZ                                regD, X0001, BITS4(0,Q,M,0), regM);
-//ZZ                break;
-//ZZ             default:
-//ZZ                goto bad;
-//ZZ          }
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
-//ZZ       case ARMin_NBinary: {
-//ZZ          UInt Q = i->ARMin.NBinary.Q ? 1 : 0;
-//ZZ          UInt regD = (hregClass(i->ARMin.NBinary.dst) == HRcVec128)
-//ZZ                        ? (qregNo(i->ARMin.NBinary.dst) << 1)
-//ZZ                        : dregNo(i->ARMin.NBinary.dst);
-//ZZ          UInt regN = (hregClass(i->ARMin.NBinary.argL) == HRcVec128)
-//ZZ                        ? (qregNo(i->ARMin.NBinary.argL) << 1)
-//ZZ                        : dregNo(i->ARMin.NBinary.argL);
-//ZZ          UInt regM = (hregClass(i->ARMin.NBinary.argR) == HRcVec128)
-//ZZ                        ? (qregNo(i->ARMin.NBinary.argR) << 1)
-//ZZ                        : dregNo(i->ARMin.NBinary.argR);
-//ZZ          UInt sz1 = i->ARMin.NBinary.size >> 1;
-//ZZ          UInt sz2 = i->ARMin.NBinary.size & 1;
-//ZZ          UInt D = regD >> 4;
-//ZZ          UInt N = regN >> 4;
-//ZZ          UInt M = regM >> 4;
-//ZZ          UInt insn;
-//ZZ          regD &= 0xF;
-//ZZ          regM &= 0xF;
-//ZZ          regN &= 0xF;
-//ZZ          switch (i->ARMin.NBinary.op) {
-//ZZ             case ARMneon_VAND: /* VAND reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X0001,
-//ZZ                                BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VORR: /* VORR reg, reg, reg*/
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, X0001,
-//ZZ                                BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VXOR: /* VEOR reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, X0001,
-//ZZ                                BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VADD: /* VADD reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X1000, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VSUB: /* VSUB reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X1000, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VMINU: /* VMIN.Uxx reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0110, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VMINS: /* VMIN.Sxx reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0110, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VMAXU: /* VMAX.Uxx reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0110, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VMAXS: /* VMAX.Sxx reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0110, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VRHADDS: /* VRHADD.Sxx reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0001, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VRHADDU: /* VRHADD.Uxx reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0001, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VQADDU: /* VQADD unsigned reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0000, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VQADDS: /* VQADD signed reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0000, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VQSUBU: /* VQSUB unsigned reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0010, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VQSUBS: /* VQSUB signed reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0010, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCGTU: /* VCGT unsigned reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0011, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCGTS: /* VCGT signed reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0011, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCGEU: /* VCGE unsigned reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0011, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCGES: /* VCGE signed reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0011, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCEQ: /* VCEQ reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X1000, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VEXT: /* VEXT.8 reg, reg, #imm4*/
-//ZZ                if (i->ARMin.NBinary.size >= 16)
-//ZZ                   goto bad;
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(1,D,1,1), regN, regD,
-//ZZ                                i->ARMin.NBinary.size & 0xf, BITS4(N,Q,M,0),
-//ZZ                                regM);
-//ZZ                break;
-//ZZ             case ARMneon_VMUL:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X1001, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VMULLU:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,sz1,sz2), regN, regD,
-//ZZ                                X1100, BITS4(N,0,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VMULLS:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD,
-//ZZ                                X1100, BITS4(N,0,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VMULP:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X1001, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VMULFP:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD,
-//ZZ                                X1101, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VMULLP:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD,
-//ZZ                                X1110, BITS4(N,0,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VQDMULH:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X1011, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VQRDMULH:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X1011, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VQDMULL:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD,
-//ZZ                                X1101, BITS4(N,0,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VTBL:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), regN, regD,
-//ZZ                                X1000, BITS4(N,0,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VPADD:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X1011, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VPADDFP:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD,
-//ZZ                                X1101, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VPMINU:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X1010, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VPMINS:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X1010, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VPMAXU:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X1010, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VPMAXS:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X1010, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VADDFP: /* VADD reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD,
-//ZZ                                X1101, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VSUBFP: /* VADD reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD,
-//ZZ                                X1101, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VABDFP: /* VABD reg, reg, reg */
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD,
-//ZZ                                X1101, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VMINF:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD,
-//ZZ                                X1111, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VMAXF:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD,
-//ZZ                                X1111, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VPMINF:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD,
-//ZZ                                X1111, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VPMAXF:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD,
-//ZZ                                X1111, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VRECPS:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X1111,
-//ZZ                                BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCGTF:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD, X1110,
-//ZZ                                BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCGEF:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, X1110,
-//ZZ                                BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VCEQF:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X1110,
-//ZZ                                BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VRSQRTS:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, X1111,
-//ZZ                                BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             default:
-//ZZ                goto bad;
-//ZZ          }
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
-//ZZ       case ARMin_NShift: {
-//ZZ          UInt Q = i->ARMin.NShift.Q ? 1 : 0;
-//ZZ          UInt regD = (hregClass(i->ARMin.NShift.dst) == HRcVec128)
-//ZZ                        ? (qregNo(i->ARMin.NShift.dst) << 1)
-//ZZ                        : dregNo(i->ARMin.NShift.dst);
-//ZZ          UInt regM = (hregClass(i->ARMin.NShift.argL) == HRcVec128)
-//ZZ                        ? (qregNo(i->ARMin.NShift.argL) << 1)
-//ZZ                        : dregNo(i->ARMin.NShift.argL);
-//ZZ          UInt regN = (hregClass(i->ARMin.NShift.argR) == HRcVec128)
-//ZZ                        ? (qregNo(i->ARMin.NShift.argR) << 1)
-//ZZ                        : dregNo(i->ARMin.NShift.argR);
-//ZZ          UInt sz1 = i->ARMin.NShift.size >> 1;
-//ZZ          UInt sz2 = i->ARMin.NShift.size & 1;
-//ZZ          UInt D = regD >> 4;
-//ZZ          UInt N = regN >> 4;
-//ZZ          UInt M = regM >> 4;
-//ZZ          UInt insn;
-//ZZ          regD &= 0xF;
-//ZZ          regM &= 0xF;
-//ZZ          regN &= 0xF;
-//ZZ          switch (i->ARMin.NShift.op) {
-//ZZ             case ARMneon_VSHL:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0100, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VSAL:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0100, BITS4(N,Q,M,0), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VQSHL:
-//ZZ                insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0100, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             case ARMneon_VQSAL:
-//ZZ                insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
-//ZZ                                X0100, BITS4(N,Q,M,1), regM);
-//ZZ                break;
-//ZZ             default:
-//ZZ                goto bad;
-//ZZ          }
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
-//ZZ       case ARMin_NShl64: {
-//ZZ          HReg regDreg = i->ARMin.NShl64.dst;
-//ZZ          HReg regMreg = i->ARMin.NShl64.src;
-//ZZ          UInt amt     = i->ARMin.NShl64.amt;
-//ZZ          vassert(amt >= 1 && amt <= 63);
-//ZZ          vassert(hregClass(regDreg) == HRcFlt64);
-//ZZ          vassert(hregClass(regMreg) == HRcFlt64);
-//ZZ          UInt regD = dregNo(regDreg);
-//ZZ          UInt regM = dregNo(regMreg);
-//ZZ          UInt D    = (regD >> 4) & 1;
-//ZZ          UInt Vd   = regD & 0xF;
-//ZZ          UInt L    = 1;
-//ZZ          UInt Q    = 0; /* always 64-bit */
-//ZZ          UInt M    = (regM >> 4) & 1;
-//ZZ          UInt Vm   = regM & 0xF;
-//ZZ          UInt insn = XXXXXXXX(X1111,X0010, BITS4(1,D,(amt>>5)&1,(amt>>4)&1),
-//ZZ                               amt & 0xF, Vd, X0101, BITS4(L,Q,M,1), Vm);
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
       case ARM64in_VImmQ: {
          UInt   rQ  = qregNo(i->ARM64in.VImmQ.rQ);
          UShort imm = i->ARM64in.VImmQ.imm;
@@ -7081,84 +4888,6 @@
         }
         goto bad;
       }
-//ZZ       case ARMin_NeonImm: {
-//ZZ          UInt Q = (hregClass(i->ARMin.NeonImm.dst) == HRcVec128) ? 1 : 0;
-//ZZ          UInt regD = Q ? (qregNo(i->ARMin.NeonImm.dst) << 1) :
-//ZZ                           dregNo(i->ARMin.NeonImm.dst);
-//ZZ          UInt D = regD >> 4;
-//ZZ          UInt imm = i->ARMin.NeonImm.imm->imm8;
-//ZZ          UInt tp = i->ARMin.NeonImm.imm->type;
-//ZZ          UInt j = imm >> 7;
-//ZZ          UInt imm3 = (imm >> 4) & 0x7;
-//ZZ          UInt imm4 = imm & 0xF;
-//ZZ          UInt cmode, op;
-//ZZ          UInt insn;
-//ZZ          regD &= 0xF;
-//ZZ          if (tp == 9)
-//ZZ             op = 1;
-//ZZ          else
-//ZZ             op = 0;
-//ZZ          switch (tp) {
-//ZZ             case 0:
-//ZZ             case 1:
-//ZZ             case 2:
-//ZZ             case 3:
-//ZZ             case 4:
-//ZZ             case 5:
-//ZZ                cmode = tp << 1;
-//ZZ                break;
-//ZZ             case 9:
-//ZZ             case 6:
-//ZZ                cmode = 14;
-//ZZ                break;
-//ZZ             case 7:
-//ZZ                cmode = 12;
-//ZZ                break;
-//ZZ             case 8:
-//ZZ                cmode = 13;
-//ZZ                break;
-//ZZ             case 10:
-//ZZ                cmode = 15;
-//ZZ                break;
-//ZZ             default:
-//ZZ                vpanic("ARMin_NeonImm");
-//ZZ 
-//ZZ          }
-//ZZ          insn = XXXXXXXX(0xF, BITS4(0,0,1,j), BITS4(1,D,0,0), imm3, regD,
-//ZZ                          cmode, BITS4(0,Q,op,1), imm4);
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
-//ZZ       case ARMin_NCMovQ: {
-//ZZ          UInt cc = (UInt)i->ARMin.NCMovQ.cond;
-//ZZ          UInt qM = qregNo(i->ARMin.NCMovQ.src) << 1;
-//ZZ          UInt qD = qregNo(i->ARMin.NCMovQ.dst) << 1;
-//ZZ          UInt vM = qM & 0xF;
-//ZZ          UInt vD = qD & 0xF;
-//ZZ          UInt M  = (qM >> 4) & 1;
-//ZZ          UInt D  = (qD >> 4) & 1;
-//ZZ          vassert(cc < 16 && cc != ARMcc_AL && cc != ARMcc_NV);
-//ZZ          /* b!cc here+8: !cc A00 0000 */
-//ZZ          UInt insn = XXXXXXXX(cc ^ 1, 0xA, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0);
-//ZZ          *p++ = insn;
-//ZZ          /* vmov qD, qM */
-//ZZ          insn = XXXXXXXX(0xF, 0x2, BITS4(0,D,1,0),
-//ZZ                          vM, vD, BITS4(0,0,0,1), BITS4(M,1,M,1), vM);
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
-//ZZ       case ARMin_Add32: {
-//ZZ          UInt regD = iregNo(i->ARMin.Add32.rD);
-//ZZ          UInt regN = iregNo(i->ARMin.Add32.rN);
-//ZZ          UInt imm32 = i->ARMin.Add32.imm32;
-//ZZ          vassert(regD != regN);
-//ZZ          /* MOV regD, imm32 */
-//ZZ          p = imm32_to_iregNo((UInt *)p, regD, imm32);
-//ZZ          /* ADD regD, regN, regD */
-//ZZ          UInt insn = XXXXXXXX(0xE, 0, X1000, regN, regD, 0, 0, regD);
-//ZZ          *p++ = insn;
-//ZZ          goto done;
-//ZZ       }
 
       case ARM64in_EvCheck: {
          /* The sequence is fixed (canned) except for the two amodes
@@ -7353,31 +5082,6 @@
 //ZZ    VexInvalRange vir = {(HWord)p, 8};
 //ZZ    return vir;
 //ZZ }
-//ZZ 
-//ZZ 
-//ZZ #undef BITS4
-//ZZ #undef X0000
-//ZZ #undef X0001
-//ZZ #undef X0010
-//ZZ #undef X0011
-//ZZ #undef X0100
-//ZZ #undef X0101
-//ZZ #undef X0110
-//ZZ #undef X0111
-//ZZ #undef X1000
-//ZZ #undef X1001
-//ZZ #undef X1010
-//ZZ #undef X1011
-//ZZ #undef X1100
-//ZZ #undef X1101
-//ZZ #undef X1110
-//ZZ #undef X1111
-//ZZ #undef XXXXX___
-//ZZ #undef XXXXXX__
-//ZZ #undef XXX___XX
-//ZZ #undef XXXXX__X
-//ZZ #undef XXXXXXXX
-//ZZ #undef XX______
 
 /*---------------------------------------------------------------*/
 /*--- end                                   host_arm64_defs.c ---*/
diff --git a/priv/host_arm64_isel.c b/priv/host_arm64_isel.c
index 3915ae1..6a5c349 100644
--- a/priv/host_arm64_isel.c
+++ b/priv/host_arm64_isel.c
@@ -169,13 +169,6 @@
    return reg;
 }
 
-//ZZ static HReg newVRegF ( ISelEnv* env )
-//ZZ {
-//ZZ    HReg reg = mkHReg(env->vreg_ctr, HRcFlt32, True/*virtual reg*/);
-//ZZ    env->vreg_ctr++;
-//ZZ    return reg;
-//ZZ }
-
 static HReg newVRegV ( ISelEnv* env )
 {
    HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/);
@@ -183,22 +176,6 @@
    return reg;
 }
 
-//ZZ /* These are duplicated in guest_arm_toIR.c */
-//ZZ static IRExpr* unop ( IROp op, IRExpr* a )
-//ZZ {
-//ZZ    return IRExpr_Unop(op, a);
-//ZZ }
-//ZZ 
-//ZZ static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 )
-//ZZ {
-//ZZ    return IRExpr_Binop(op, a1, a2);
-//ZZ }
-//ZZ 
-//ZZ static IRExpr* bind ( Int binder )
-//ZZ {
-//ZZ    return IRExpr_Binder(binder);
-//ZZ }
-
 
 /*---------------------------------------------------------*/
 /*--- ISEL: Forward declarations                        ---*/
@@ -948,136 +925,6 @@
    return ARM64AMode_RI9(reg, 0);
 }
 
-//ZZ /* --------------------- AModeV --------------------- */
-//ZZ 
-//ZZ /* Return an AModeV which computes the value of the specified
-//ZZ    expression, possibly also adding insns to the code list as a
-//ZZ    result.  The expression may only be a 32-bit one.
-//ZZ */
-//ZZ 
-//ZZ static Bool sane_AModeV ( ARMAModeV* am )
-//ZZ {
-//ZZ   return toBool( hregClass(am->reg) == HRcInt32
-//ZZ                  && hregIsVirtual(am->reg)
-//ZZ                  && am->simm11 >= -1020 && am->simm11 <= 1020
-//ZZ                  && 0 == (am->simm11 & 3) );
-//ZZ }
-//ZZ 
-//ZZ static ARMAModeV* iselIntExpr_AModeV ( ISelEnv* env, IRExpr* e )
-//ZZ {
-//ZZ    ARMAModeV* am = iselIntExpr_AModeV_wrk(env, e);
-//ZZ    vassert(sane_AModeV(am));
-//ZZ    return am;
-//ZZ }
-//ZZ 
-//ZZ static ARMAModeV* iselIntExpr_AModeV_wrk ( ISelEnv* env, IRExpr* e )
-//ZZ {
-//ZZ    IRType ty = typeOfIRExpr(env->type_env,e);
-//ZZ    vassert(ty == Ity_I32);
-//ZZ 
-//ZZ    /* {Add32,Sub32}(expr, simm8 << 2) */
-//ZZ    if (e->tag == Iex_Binop
-//ZZ        && (e->Iex.Binop.op == Iop_Add32 || e->Iex.Binop.op == Iop_Sub32)
-//ZZ        && e->Iex.Binop.arg2->tag == Iex_Const
-//ZZ        && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U32) {
-//ZZ       Int simm = (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32;
-//ZZ       if (simm >= -1020 && simm <= 1020 && 0 == (simm & 3)) {
-//ZZ          HReg reg;
-//ZZ          if (e->Iex.Binop.op == Iop_Sub32)
-//ZZ             simm = -simm;
-//ZZ          reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
-//ZZ          return mkARMAModeV(reg, simm);
-//ZZ       }
-//ZZ    }
-//ZZ 
-//ZZ    /* Doesn't match anything in particular.  Generate it into
-//ZZ       a register and use that. */
-//ZZ    {
-//ZZ       HReg reg = iselIntExpr_R(env, e);
-//ZZ       return mkARMAModeV(reg, 0);
-//ZZ    }
-//ZZ 
-//ZZ }
-//ZZ 
-//ZZ /* -------------------- AModeN -------------------- */
-//ZZ 
-//ZZ static ARMAModeN* iselIntExpr_AModeN ( ISelEnv* env, IRExpr* e )
-//ZZ {
-//ZZ    return iselIntExpr_AModeN_wrk(env, e);
-//ZZ }
-//ZZ 
-//ZZ static ARMAModeN* iselIntExpr_AModeN_wrk ( ISelEnv* env, IRExpr* e )
-//ZZ {
-//ZZ    HReg reg = iselIntExpr_R(env, e);
-//ZZ    return mkARMAModeN_R(reg);
-//ZZ }
-//ZZ 
-//ZZ 
-//ZZ /* --------------------- RI84 --------------------- */
-//ZZ 
-//ZZ /* Select instructions to generate 'e' into a RI84.  If mayInv is
-//ZZ    true, then the caller will also accept an I84 form that denotes
-//ZZ    'not e'.  In this case didInv may not be NULL, and *didInv is set
-//ZZ    to True.  This complication is so as to allow generation of an RI84
-//ZZ    which is suitable for use in either an AND or BIC instruction,
-//ZZ    without knowing (before this call) which one.
-//ZZ */
-//ZZ static ARMRI84* iselIntExpr_RI84 ( /*OUT*/Bool* didInv, Bool mayInv,
-//ZZ                                    ISelEnv* env, IRExpr* e )
-//ZZ {
-//ZZ    ARMRI84* ri;
-//ZZ    if (mayInv)
-//ZZ       vassert(didInv != NULL);
-//ZZ    ri = iselIntExpr_RI84_wrk(didInv, mayInv, env, e);
-//ZZ    /* sanity checks ... */
-//ZZ    switch (ri->tag) {
-//ZZ       case ARMri84_I84:
-//ZZ          return ri;
-//ZZ       case ARMri84_R:
-//ZZ          vassert(hregClass(ri->ARMri84.R.reg) == HRcInt32);
-//ZZ          vassert(hregIsVirtual(ri->ARMri84.R.reg));
-//ZZ          return ri;
-//ZZ       default:
-//ZZ          vpanic("iselIntExpr_RI84: unknown arm RI84 tag");
-//ZZ    }
-//ZZ }
-//ZZ 
-//ZZ /* DO NOT CALL THIS DIRECTLY ! */
-//ZZ static ARMRI84* iselIntExpr_RI84_wrk ( /*OUT*/Bool* didInv, Bool mayInv,
-//ZZ                                        ISelEnv* env, IRExpr* e )
-//ZZ {
-//ZZ    IRType ty = typeOfIRExpr(env->type_env,e);
-//ZZ    vassert(ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8);
-//ZZ 
-//ZZ    if (didInv) *didInv = False;
-//ZZ 
-//ZZ    /* special case: immediate */
-//ZZ    if (e->tag == Iex_Const) {
-//ZZ       UInt u, u8 = 0x100, u4 = 0x10; /* both invalid */
-//ZZ       switch (e->Iex.Const.con->tag) {
-//ZZ          case Ico_U32: u = e->Iex.Const.con->Ico.U32; break;
-//ZZ          case Ico_U16: u = 0xFFFF & (e->Iex.Const.con->Ico.U16); break;
-//ZZ          case Ico_U8:  u = 0xFF   & (e->Iex.Const.con->Ico.U8); break;
-//ZZ          default: vpanic("iselIntExpr_RI84.Iex_Const(armh)");
-//ZZ       }
-//ZZ       if (fitsIn8x4(&u8, &u4, u)) {
-//ZZ          return ARMRI84_I84( (UShort)u8, (UShort)u4 );
-//ZZ       }
-//ZZ       if (mayInv && fitsIn8x4(&u8, &u4, ~u)) {
-//ZZ          vassert(didInv);
-//ZZ          *didInv = True;
-//ZZ          return ARMRI84_I84( (UShort)u8, (UShort)u4 );
-//ZZ       }
-//ZZ       /* else fail, fall through to default case */
-//ZZ    }
-//ZZ 
-//ZZ    /* default case: calculate into a register and return that */
-//ZZ    {
-//ZZ       HReg r = iselIntExpr_R ( env, e );
-//ZZ       return ARMRI84_R(r);
-//ZZ    }
-//ZZ }
-
 
 /* --------------------- RIA --------------------- */
 
@@ -1577,30 +1424,6 @@
       }
    }
 
-//ZZ    /* const */
-//ZZ    /* Constant 1:Bit */
-//ZZ    if (e->tag == Iex_Const) {
-//ZZ       HReg r;
-//ZZ       vassert(e->Iex.Const.con->tag == Ico_U1);
-//ZZ       vassert(e->Iex.Const.con->Ico.U1 == True 
-//ZZ               || e->Iex.Const.con->Ico.U1 == False);
-//ZZ       r = newVRegI(env);
-//ZZ       addInstr(env, ARMInstr_Imm32(r, 0));
-//ZZ       addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, r, ARMRI84_R(r)));
-//ZZ       return e->Iex.Const.con->Ico.U1 ? ARMcc_EQ : ARMcc_NE;
-//ZZ    }
-//ZZ 
-//ZZ    // JRS 2013-Jan-03: this seems completely nonsensical
-//ZZ    /* --- CasCmpEQ* --- */
-//ZZ    /* Ist_Cas has a dummy argument to compare with, so comparison is
-//ZZ       always true. */
-//ZZ    //if (e->tag == Iex_Binop
-//ZZ    //    && (e->Iex.Binop.op == Iop_CasCmpEQ32
-//ZZ    //        || e->Iex.Binop.op == Iop_CasCmpEQ16
-//ZZ    //        || e->Iex.Binop.op == Iop_CasCmpEQ8)) {
-//ZZ    //   return ARMcc_AL;
-//ZZ    //}
-
    ppIRExpr(e);
    vpanic("iselCondCode");
 }
@@ -1864,105 +1687,9 @@
         }
       } /* local scope */
 
-//ZZ       if (e->Iex.Binop.op == Iop_GetElem8x8
-//ZZ           || e->Iex.Binop.op == Iop_GetElem16x4
-//ZZ           || e->Iex.Binop.op == Iop_GetElem32x2) {
-//ZZ          HReg res = newVRegI(env);
-//ZZ          HReg arg = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ          UInt index, size;
-//ZZ          if (e->Iex.Binop.arg2->tag != Iex_Const ||
-//ZZ              typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
-//ZZ             vpanic("ARM target supports GetElem with constant "
-//ZZ                    "second argument only\n");
-//ZZ          }
-//ZZ          index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
-//ZZ          switch (e->Iex.Binop.op) {
-//ZZ             case Iop_GetElem8x8: vassert(index < 8); size = 0; break;
-//ZZ             case Iop_GetElem16x4: vassert(index < 4); size = 1; break;
-//ZZ             case Iop_GetElem32x2: vassert(index < 2); size = 2; break;
-//ZZ             default: vassert(0);
-//ZZ          }
-//ZZ          addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS,
-//ZZ                                         mkARMNRS(ARMNRS_Reg, res, 0),
-//ZZ                                         mkARMNRS(ARMNRS_Scalar, arg, index),
-//ZZ                                         size, False));
-//ZZ          return res;
-//ZZ       }
-//ZZ 
-//ZZ       if (e->Iex.Binop.op == Iop_GetElem8x16
-//ZZ           || e->Iex.Binop.op == Iop_GetElem16x8
-//ZZ           || e->Iex.Binop.op == Iop_GetElem32x4) {
-//ZZ          HReg res = newVRegI(env);
-//ZZ          HReg arg = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ          UInt index, size;
-//ZZ          if (e->Iex.Binop.arg2->tag != Iex_Const ||
-//ZZ              typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
-//ZZ             vpanic("ARM target supports GetElem with constant "
-//ZZ                    "second argument only\n");
-//ZZ          }
-//ZZ          index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
-//ZZ          switch (e->Iex.Binop.op) {
-//ZZ             case Iop_GetElem8x16: vassert(index < 16); size = 0; break;
-//ZZ             case Iop_GetElem16x8: vassert(index < 8); size = 1; break;
-//ZZ             case Iop_GetElem32x4: vassert(index < 4); size = 2; break;
-//ZZ             default: vassert(0);
-//ZZ          }
-//ZZ          addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS,
-//ZZ                                         mkARMNRS(ARMNRS_Reg, res, 0),
-//ZZ                                         mkARMNRS(ARMNRS_Scalar, arg, index),
-//ZZ                                         size, True));
-//ZZ          return res;
-//ZZ       }
-
       /* All cases involving host-side helper calls. */
       void* fn = NULL;
       switch (e->Iex.Binop.op) {
-//ZZ          case Iop_Add16x2:
-//ZZ             fn = &h_generic_calc_Add16x2; break;
-//ZZ          case Iop_Sub16x2:
-//ZZ             fn = &h_generic_calc_Sub16x2; break;
-//ZZ          case Iop_HAdd16Ux2:
-//ZZ             fn = &h_generic_calc_HAdd16Ux2; break;
-//ZZ          case Iop_HAdd16Sx2:
-//ZZ             fn = &h_generic_calc_HAdd16Sx2; break;
-//ZZ          case Iop_HSub16Ux2:
-//ZZ             fn = &h_generic_calc_HSub16Ux2; break;
-//ZZ          case Iop_HSub16Sx2:
-//ZZ             fn = &h_generic_calc_HSub16Sx2; break;
-//ZZ          case Iop_QAdd16Sx2:
-//ZZ             fn = &h_generic_calc_QAdd16Sx2; break;
-//ZZ          case Iop_QAdd16Ux2:
-//ZZ             fn = &h_generic_calc_QAdd16Ux2; break;
-//ZZ          case Iop_QSub16Sx2:
-//ZZ             fn = &h_generic_calc_QSub16Sx2; break;
-//ZZ          case Iop_Add8x4:
-//ZZ             fn = &h_generic_calc_Add8x4; break;
-//ZZ          case Iop_Sub8x4:
-//ZZ             fn = &h_generic_calc_Sub8x4; break;
-//ZZ          case Iop_HAdd8Ux4:
-//ZZ             fn = &h_generic_calc_HAdd8Ux4; break;
-//ZZ          case Iop_HAdd8Sx4:
-//ZZ             fn = &h_generic_calc_HAdd8Sx4; break;
-//ZZ          case Iop_HSub8Ux4:
-//ZZ             fn = &h_generic_calc_HSub8Ux4; break;
-//ZZ          case Iop_HSub8Sx4:
-//ZZ             fn = &h_generic_calc_HSub8Sx4; break;
-//ZZ          case Iop_QAdd8Sx4:
-//ZZ             fn = &h_generic_calc_QAdd8Sx4; break;
-//ZZ          case Iop_QAdd8Ux4:
-//ZZ             fn = &h_generic_calc_QAdd8Ux4; break;
-//ZZ          case Iop_QSub8Sx4:
-//ZZ             fn = &h_generic_calc_QSub8Sx4; break;
-//ZZ          case Iop_QSub8Ux4:
-//ZZ             fn = &h_generic_calc_QSub8Ux4; break;
-//ZZ          case Iop_Sad8Ux4:
-//ZZ             fn = &h_generic_calc_Sad8Ux4; break;
-//ZZ          case Iop_QAdd32S:
-//ZZ             fn = &h_generic_calc_QAdd32S; break;
-//ZZ          case Iop_QSub32S:
-//ZZ             fn = &h_generic_calc_QSub32S; break;
-//ZZ          case Iop_QSub16Ux2:
-//ZZ             fn = &h_generic_calc_QSub16Ux2; break;
          case Iop_DivU32:
             fn = &h_calc_udiv32_w_arm_semantics; break;
          case Iop_DivS32:
@@ -2194,31 +1921,6 @@
             addInstr(env, ARM64Instr_VXfromQ(dst, tmp, 0/*laneNo*/));
             return dst;
          }
-//ZZ          case Iop_64HIto32: {
-//ZZ             HReg rHi, rLo;
-//ZZ             iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
-//ZZ             return rHi; /* and abandon rLo .. poor wee thing :-) */
-//ZZ          }
-//ZZ          case Iop_64to32: {
-//ZZ             HReg rHi, rLo;
-//ZZ             iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
-//ZZ             return rLo; /* similar stupid comment to the above ... */
-//ZZ          }
-//ZZ          case Iop_64to8: {
-//ZZ             HReg rHi, rLo;
-//ZZ             if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
-//ZZ                HReg tHi = newVRegI(env);
-//ZZ                HReg tLo = newVRegI(env);
-//ZZ                HReg tmp = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ                addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo));
-//ZZ                rHi = tHi;
-//ZZ                rLo = tLo;
-//ZZ             } else {
-//ZZ                iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
-//ZZ             }
-//ZZ             return rLo;
-//ZZ          }
-
          case Iop_1Uto64: {
             /* 1Uto64(tmp). */
             HReg dst = newVRegI(env);
@@ -2238,52 +1940,6 @@
             }
             return dst;
          }
-//ZZ          case Iop_1Uto8: {
-//ZZ             HReg        dst  = newVRegI(env);
-//ZZ             ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0)));
-//ZZ             addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0)));
-//ZZ             return dst;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_1Sto32: {
-//ZZ             HReg        dst  = newVRegI(env);
-//ZZ             ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg);
-//ZZ             ARMRI5*     amt  = ARMRI5_I5(31);
-//ZZ             /* This is really rough.  We could do much better here;
-//ZZ                perhaps mvn{cond} dst, #0 as the second insn?
-//ZZ                (same applies to 1Sto64) */
-//ZZ             addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0)));
-//ZZ             addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0)));
-//ZZ             addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, dst, amt));
-//ZZ             addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt));
-//ZZ             return dst;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_Clz32: {
-//ZZ             /* Count leading zeroes; easy on ARM. */
-//ZZ             HReg dst = newVRegI(env);
-//ZZ             HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_Unary(ARMun_CLZ, dst, src));
-//ZZ             return dst;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_CmpwNEZ32: {
-//ZZ             HReg dst = newVRegI(env);
-//ZZ             HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_Unary(ARMun_NEG, dst, src));
-//ZZ             addInstr(env, ARMInstr_Alu(ARMalu_OR, dst, dst, ARMRI84_R(src)));
-//ZZ             addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, ARMRI5_I5(31)));
-//ZZ             return dst;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_ReinterpF32asI32: {
-//ZZ             HReg dst = newVRegI(env);
-//ZZ             HReg src = iselFltExpr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_VXferS(False/*!toS*/, src, dst));
-//ZZ             return dst;
-//ZZ          }
-
          case Iop_64to32:
          case Iop_64to16:
          case Iop_64to8:
@@ -2294,27 +1950,6 @@
             break;
       }
 
-//ZZ       /* All Unop cases involving host-side helper calls. */
-//ZZ       void* fn = NULL;
-//ZZ       switch (e->Iex.Unop.op) {
-//ZZ          case Iop_CmpNEZ16x2:
-//ZZ             fn = &h_generic_calc_CmpNEZ16x2; break;
-//ZZ          case Iop_CmpNEZ8x4:
-//ZZ             fn = &h_generic_calc_CmpNEZ8x4; break;
-//ZZ          default:
-//ZZ             break;
-//ZZ       }
-//ZZ 
-//ZZ       if (fn) {
-//ZZ          HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg);
-//ZZ          HReg res = newVRegI(env);
-//ZZ          addInstr(env, mk_iMOVds_RR(hregARM_R0(), arg));
-//ZZ          addInstr(env, ARMInstr_Call( ARMcc_AL, (HWord)Ptr_to_ULong(fn),
-//ZZ                                       1, RetLocInt ));
-//ZZ          addInstr(env, mk_iMOVds_RR(res, hregARM_R0()));
-//ZZ          return res;
-//ZZ       }
-
       break;
    }
 
@@ -2488,1888 +2123,6 @@
 }
 
 
-//ZZ /* -------------------- 64-bit -------------------- */
-//ZZ 
-//ZZ /* Compute a 64-bit value into a register pair, which is returned as
-//ZZ    the first two parameters.  As with iselIntExpr_R, these may be
-//ZZ    either real or virtual regs; in any case they must not be changed
-//ZZ    by subsequent code emitted by the caller.  */
-//ZZ 
-//ZZ static void iselInt64Expr ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
-//ZZ {
-//ZZ    iselInt64Expr_wrk(rHi, rLo, env, e);
-//ZZ #  if 0
-//ZZ    vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
-//ZZ #  endif
-//ZZ    vassert(hregClass(*rHi) == HRcInt32);
-//ZZ    vassert(hregIsVirtual(*rHi));
-//ZZ    vassert(hregClass(*rLo) == HRcInt32);
-//ZZ    vassert(hregIsVirtual(*rLo));
-//ZZ }
-//ZZ 
-//ZZ /* DO NOT CALL THIS DIRECTLY ! */
-//ZZ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
-//ZZ {
-//ZZ    vassert(e);
-//ZZ    vassert(typeOfIRExpr(env->type_env,e) == Ity_I64);
-//ZZ 
-//ZZ    /* 64-bit literal */
-//ZZ    if (e->tag == Iex_Const) {
-//ZZ       ULong   w64 = e->Iex.Const.con->Ico.U64;
-//ZZ       UInt    wHi = toUInt(w64 >> 32);
-//ZZ       UInt    wLo = toUInt(w64);
-//ZZ       HReg    tHi = newVRegI(env);
-//ZZ       HReg    tLo = newVRegI(env);
-//ZZ       vassert(e->Iex.Const.con->tag == Ico_U64);
-//ZZ       addInstr(env, ARMInstr_Imm32(tHi, wHi));
-//ZZ       addInstr(env, ARMInstr_Imm32(tLo, wLo));
-//ZZ       *rHi = tHi;
-//ZZ       *rLo = tLo;
-//ZZ       return;
-//ZZ    }
-//ZZ 
-//ZZ    /* read 64-bit IRTemp */
-//ZZ    if (e->tag == Iex_RdTmp) {
-//ZZ       if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
-//ZZ          HReg tHi = newVRegI(env);
-//ZZ          HReg tLo = newVRegI(env);
-//ZZ          HReg tmp = iselNeon64Expr(env, e);
-//ZZ          addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo));
-//ZZ          *rHi = tHi;
-//ZZ          *rLo = tLo;
-//ZZ       } else {
-//ZZ          lookupIRTemp64( rHi, rLo, env, e->Iex.RdTmp.tmp);
-//ZZ       }
-//ZZ       return;
-//ZZ    }
-//ZZ 
-//ZZ    /* 64-bit load */
-//ZZ    if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {
-//ZZ       HReg      tLo, tHi, rA;
-//ZZ       vassert(e->Iex.Load.ty == Ity_I64);
-//ZZ       rA  = iselIntExpr_R(env, e->Iex.Load.addr);
-//ZZ       tHi = newVRegI(env);
-//ZZ       tLo = newVRegI(env);
-//ZZ       addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/,
-//ZZ                                     tHi, ARMAMode1_RI(rA, 4)));
-//ZZ       addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/,
-//ZZ                                     tLo, ARMAMode1_RI(rA, 0)));
-//ZZ       *rHi = tHi;
-//ZZ       *rLo = tLo;
-//ZZ       return;
-//ZZ    }
-//ZZ 
-//ZZ    /* 64-bit GET */
-//ZZ    if (e->tag == Iex_Get) {
-//ZZ       ARMAMode1* am0 = ARMAMode1_RI(hregARM_R8(), e->Iex.Get.offset + 0);
-//ZZ       ARMAMode1* am4 = ARMAMode1_RI(hregARM_R8(), e->Iex.Get.offset + 4);
-//ZZ       HReg tHi = newVRegI(env);
-//ZZ       HReg tLo = newVRegI(env);
-//ZZ       addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, tHi, am4));
-//ZZ       addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, tLo, am0));
-//ZZ       *rHi = tHi;
-//ZZ       *rLo = tLo;
-//ZZ       return;
-//ZZ    }
-//ZZ 
-//ZZ    /* --------- BINARY ops --------- */
-//ZZ    if (e->tag == Iex_Binop) {
-//ZZ       switch (e->Iex.Binop.op) {
-//ZZ 
-//ZZ          /* 32 x 32 -> 64 multiply */
-//ZZ          case Iop_MullS32:
-//ZZ          case Iop_MullU32: {
-//ZZ             HReg     argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
-//ZZ             HReg     argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
-//ZZ             HReg     tHi  = newVRegI(env);
-//ZZ             HReg     tLo  = newVRegI(env);
-//ZZ             ARMMulOp mop  = e->Iex.Binop.op == Iop_MullS32
-//ZZ                                ? ARMmul_SX : ARMmul_ZX;
-//ZZ             addInstr(env, mk_iMOVds_RR(hregARM_R2(), argL));
-//ZZ             addInstr(env, mk_iMOVds_RR(hregARM_R3(), argR));
-//ZZ             addInstr(env, ARMInstr_Mul(mop));
-//ZZ             addInstr(env, mk_iMOVds_RR(tHi, hregARM_R1()));
-//ZZ             addInstr(env, mk_iMOVds_RR(tLo, hregARM_R0()));
-//ZZ             *rHi = tHi;
-//ZZ             *rLo = tLo;
-//ZZ             return;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_Or64: {
-//ZZ             HReg xLo, xHi, yLo, yHi;
-//ZZ             HReg tHi = newVRegI(env);
-//ZZ             HReg tLo = newVRegI(env);
-//ZZ             iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
-//ZZ             iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_Alu(ARMalu_OR, tHi, xHi, ARMRI84_R(yHi)));
-//ZZ             addInstr(env, ARMInstr_Alu(ARMalu_OR, tLo, xLo, ARMRI84_R(yLo)));
-//ZZ             *rHi = tHi;
-//ZZ             *rLo = tLo;
-//ZZ             return;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_Add64: {
-//ZZ             HReg xLo, xHi, yLo, yHi;
-//ZZ             HReg tHi = newVRegI(env);
-//ZZ             HReg tLo = newVRegI(env);
-//ZZ             iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
-//ZZ             iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_Alu(ARMalu_ADDS, tLo, xLo, ARMRI84_R(yLo)));
-//ZZ             addInstr(env, ARMInstr_Alu(ARMalu_ADC,  tHi, xHi, ARMRI84_R(yHi)));
-//ZZ             *rHi = tHi;
-//ZZ             *rLo = tLo;
-//ZZ             return;
-//ZZ          }
-//ZZ 
-//ZZ          /* 32HLto64(e1,e2) */
-//ZZ          case Iop_32HLto64: {
-//ZZ             *rHi = iselIntExpr_R(env, e->Iex.Binop.arg1);
-//ZZ             *rLo = iselIntExpr_R(env, e->Iex.Binop.arg2);
-//ZZ             return;
-//ZZ          }
-//ZZ 
-//ZZ          default:
-//ZZ             break;
-//ZZ       }
-//ZZ    }
-//ZZ 
-//ZZ    /* --------- UNARY ops --------- */
-//ZZ    if (e->tag == Iex_Unop) {
-//ZZ       switch (e->Iex.Unop.op) {
-//ZZ 
-//ZZ          /* ReinterpF64asI64 */
-//ZZ          case Iop_ReinterpF64asI64: {
-//ZZ             HReg dstHi = newVRegI(env);
-//ZZ             HReg dstLo = newVRegI(env);
-//ZZ             HReg src   = iselDblExpr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_VXferD(False/*!toD*/, src, dstHi, dstLo));
-//ZZ             *rHi = dstHi;
-//ZZ             *rLo = dstLo;
-//ZZ             return;
-//ZZ          }
-//ZZ 
-//ZZ          /* Left64(e) */
-//ZZ          case Iop_Left64: {
-//ZZ             HReg yLo, yHi;
-//ZZ             HReg tHi  = newVRegI(env);
-//ZZ             HReg tLo  = newVRegI(env);
-//ZZ             HReg zero = newVRegI(env);
-//ZZ             /* yHi:yLo = arg */
-//ZZ             iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg);
-//ZZ             /* zero = 0 */
-//ZZ             addInstr(env, ARMInstr_Imm32(zero, 0));
-//ZZ             /* tLo = 0 - yLo, and set carry */
-//ZZ             addInstr(env, ARMInstr_Alu(ARMalu_SUBS,
-//ZZ                                        tLo, zero, ARMRI84_R(yLo)));
-//ZZ             /* tHi = 0 - yHi - carry */
-//ZZ             addInstr(env, ARMInstr_Alu(ARMalu_SBC,
-//ZZ                                        tHi, zero, ARMRI84_R(yHi)));
-//ZZ             /* So now we have tHi:tLo = -arg.  To finish off, or 'arg'
-//ZZ                back in, so as to give the final result 
-//ZZ                tHi:tLo = arg | -arg. */
-//ZZ             addInstr(env, ARMInstr_Alu(ARMalu_OR, tHi, tHi, ARMRI84_R(yHi)));
-//ZZ             addInstr(env, ARMInstr_Alu(ARMalu_OR, tLo, tLo, ARMRI84_R(yLo)));
-//ZZ             *rHi = tHi;
-//ZZ             *rLo = tLo;
-//ZZ             return;
-//ZZ          }
-//ZZ 
-//ZZ          /* CmpwNEZ64(e) */
-//ZZ          case Iop_CmpwNEZ64: {
-//ZZ             HReg srcLo, srcHi;
-//ZZ             HReg tmp1 = newVRegI(env);
-//ZZ             HReg tmp2 = newVRegI(env);
-//ZZ             /* srcHi:srcLo = arg */
-//ZZ             iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg);
-//ZZ             /* tmp1 = srcHi | srcLo */
-//ZZ             addInstr(env, ARMInstr_Alu(ARMalu_OR,
-//ZZ                                        tmp1, srcHi, ARMRI84_R(srcLo)));
-//ZZ             /* tmp2 = (tmp1 | -tmp1) >>s 31 */
-//ZZ             addInstr(env, ARMInstr_Unary(ARMun_NEG, tmp2, tmp1));
-//ZZ             addInstr(env, ARMInstr_Alu(ARMalu_OR,
-//ZZ                                        tmp2, tmp2, ARMRI84_R(tmp1)));
-//ZZ             addInstr(env, ARMInstr_Shift(ARMsh_SAR,
-//ZZ                                          tmp2, tmp2, ARMRI5_I5(31)));
-//ZZ             *rHi = tmp2;
-//ZZ             *rLo = tmp2;
-//ZZ             return;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_1Sto64: {
-//ZZ             HReg        dst  = newVRegI(env);
-//ZZ             ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg);
-//ZZ             ARMRI5*     amt  = ARMRI5_I5(31);
-//ZZ             /* This is really rough.  We could do much better here;
-//ZZ                perhaps mvn{cond} dst, #0 as the second insn?
-//ZZ                (same applies to 1Sto32) */
-//ZZ             addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0)));
-//ZZ             addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0)));
-//ZZ             addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, dst, amt));
-//ZZ             addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt));
-//ZZ             *rHi = dst;
-//ZZ             *rLo = dst;
-//ZZ             return;
-//ZZ          }
-//ZZ 
-//ZZ          default: 
-//ZZ             break;
-//ZZ       }
-//ZZ    } /* if (e->tag == Iex_Unop) */
-//ZZ 
-//ZZ    /* --------- MULTIPLEX --------- */
-//ZZ    if (e->tag == Iex_ITE) { // VFD
-//ZZ       IRType tyC;
-//ZZ       HReg   r1hi, r1lo, r0hi, r0lo, dstHi, dstLo;
-//ZZ       ARMCondCode cc;
-//ZZ       tyC = typeOfIRExpr(env->type_env,e->Iex.ITE.cond);
-//ZZ       vassert(tyC == Ity_I1);
-//ZZ       iselInt64Expr(&r1hi, &r1lo, env, e->Iex.ITE.iftrue);
-//ZZ       iselInt64Expr(&r0hi, &r0lo, env, e->Iex.ITE.iffalse);
-//ZZ       dstHi = newVRegI(env);
-//ZZ       dstLo = newVRegI(env);
-//ZZ       addInstr(env, mk_iMOVds_RR(dstHi, r1hi));
-//ZZ       addInstr(env, mk_iMOVds_RR(dstLo, r1lo));
-//ZZ       cc = iselCondCode(env, e->Iex.ITE.cond);
-//ZZ       addInstr(env, ARMInstr_CMov(cc ^ 1, dstHi, ARMRI84_R(r0hi)));
-//ZZ       addInstr(env, ARMInstr_CMov(cc ^ 1, dstLo, ARMRI84_R(r0lo)));
-//ZZ       *rHi = dstHi;
-//ZZ       *rLo = dstLo;
-//ZZ       return;
-//ZZ    }
-//ZZ 
-//ZZ    /* It is convenient sometimes to call iselInt64Expr even when we
-//ZZ       have NEON support (e.g. in do_helper_call we need 64-bit
-//ZZ       arguments as 2 x 32 regs). */
-//ZZ    if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
-//ZZ       HReg tHi = newVRegI(env);
-//ZZ       HReg tLo = newVRegI(env);
-//ZZ       HReg tmp = iselNeon64Expr(env, e);
-//ZZ       addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo));
-//ZZ       *rHi = tHi;
-//ZZ       *rLo = tLo;
-//ZZ       return ;
-//ZZ    }
-//ZZ 
-//ZZ    ppIRExpr(e);
-//ZZ    vpanic("iselInt64Expr");
-//ZZ }
-//ZZ 
-//ZZ 
-//ZZ /*---------------------------------------------------------*/
-//ZZ /*--- ISEL: Vector (NEON) expressions (64 bit)          ---*/
-//ZZ /*---------------------------------------------------------*/
-//ZZ 
-//ZZ static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e )
-//ZZ {
-//ZZ    HReg r = iselNeon64Expr_wrk( env, e );
-//ZZ    vassert(hregClass(r) == HRcFlt64);
-//ZZ    vassert(hregIsVirtual(r));
-//ZZ    return r;
-//ZZ }
-//ZZ 
-//ZZ /* DO NOT CALL THIS DIRECTLY */
-//ZZ static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e )
-//ZZ {
-//ZZ    IRType ty = typeOfIRExpr(env->type_env, e);
-//ZZ    MatchInfo mi;
-//ZZ    vassert(e);
-//ZZ    vassert(ty == Ity_I64);
-//ZZ 
-//ZZ    if (e->tag == Iex_RdTmp) {
-//ZZ       return lookupIRTemp(env, e->Iex.RdTmp.tmp);
-//ZZ    }
-//ZZ 
-//ZZ    if (e->tag == Iex_Const) {
-//ZZ       HReg rLo, rHi;
-//ZZ       HReg res = newVRegD(env);
-//ZZ       iselInt64Expr(&rHi, &rLo, env, e);
-//ZZ       addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
-//ZZ       return res;
-//ZZ    }
-//ZZ 
-//ZZ    /* 64-bit load */
-//ZZ    if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {
-//ZZ       HReg res = newVRegD(env);
-//ZZ       ARMAModeN* am = iselIntExpr_AModeN(env, e->Iex.Load.addr);
-//ZZ       vassert(ty == Ity_I64);
-//ZZ       addInstr(env, ARMInstr_NLdStD(True, res, am));
-//ZZ       return res;
-//ZZ    }
-//ZZ 
-//ZZ    /* 64-bit GET */
-//ZZ    if (e->tag == Iex_Get) {
-//ZZ       HReg addr = newVRegI(env);
-//ZZ       HReg res = newVRegD(env);
-//ZZ       vassert(ty == Ity_I64);
-//ZZ       addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), e->Iex.Get.offset));
-//ZZ       addInstr(env, ARMInstr_NLdStD(True, res, mkARMAModeN_R(addr)));
-//ZZ       return res;
-//ZZ    }
-//ZZ 
-//ZZ    /* --------- BINARY ops --------- */
-//ZZ    if (e->tag == Iex_Binop) {
-//ZZ       switch (e->Iex.Binop.op) {
-//ZZ 
-//ZZ          /* 32 x 32 -> 64 multiply */
-//ZZ          case Iop_MullS32:
-//ZZ          case Iop_MullU32: {
-//ZZ             HReg rLo, rHi;
-//ZZ             HReg res = newVRegD(env);
-//ZZ             iselInt64Expr(&rHi, &rLo, env, e);
-//ZZ             addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_And64: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VAND,
-//ZZ                                            res, argL, argR, 4, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Or64: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
-//ZZ                                            res, argL, argR, 4, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Xor64: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VXOR,
-//ZZ                                            res, argL, argR, 4, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          /* 32HLto64(e1,e2) */
-//ZZ          case Iop_32HLto64: {
-//ZZ             HReg rHi = iselIntExpr_R(env, e->Iex.Binop.arg1);
-//ZZ             HReg rLo = iselIntExpr_R(env, e->Iex.Binop.arg2);
-//ZZ             HReg res = newVRegD(env);
-//ZZ             addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_Add8x8:
-//ZZ          case Iop_Add16x4:
-//ZZ          case Iop_Add32x2:
-//ZZ          case Iop_Add64: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Add8x8: size = 0; break;
-//ZZ                case Iop_Add16x4: size = 1; break;
-//ZZ                case Iop_Add32x2: size = 2; break;
-//ZZ                case Iop_Add64: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VADD,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Add32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Recps32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Rsqrts32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          // These 6 verified 18 Apr 2013
-//ZZ          case Iop_InterleaveHI32x2:
-//ZZ          case Iop_InterleaveLO32x2:
-//ZZ          case Iop_InterleaveOddLanes8x8:
-//ZZ          case Iop_InterleaveEvenLanes8x8:
-//ZZ          case Iop_InterleaveOddLanes16x4:
-//ZZ          case Iop_InterleaveEvenLanes16x4: {
-//ZZ             HReg rD   = newVRegD(env);
-//ZZ             HReg rM   = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             Bool resRd;  // is the result in rD or rM ?
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_InterleaveOddLanes8x8:   resRd = False; size = 0; break;
-//ZZ                case Iop_InterleaveEvenLanes8x8:  resRd = True;  size = 0; break;
-//ZZ                case Iop_InterleaveOddLanes16x4:  resRd = False; size = 1; break;
-//ZZ                case Iop_InterleaveEvenLanes16x4: resRd = True;  size = 1; break;
-//ZZ                case Iop_InterleaveHI32x2:        resRd = False; size = 2; break;
-//ZZ                case Iop_InterleaveLO32x2:        resRd = True;  size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False));
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False));
-//ZZ             addInstr(env, ARMInstr_NDual(ARMneon_TRN, rD, rM, size, False));
-//ZZ             return resRd ? rD : rM;
-//ZZ          }
-//ZZ 
-//ZZ          // These 4 verified 18 Apr 2013
-//ZZ          case Iop_InterleaveHI8x8:
-//ZZ          case Iop_InterleaveLO8x8:
-//ZZ          case Iop_InterleaveHI16x4:
-//ZZ          case Iop_InterleaveLO16x4: {
-//ZZ             HReg rD   = newVRegD(env);
-//ZZ             HReg rM   = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             Bool resRd;  // is the result in rD or rM ?
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_InterleaveHI8x8:  resRd = False; size = 0; break;
-//ZZ                case Iop_InterleaveLO8x8:  resRd = True;  size = 0; break;
-//ZZ                case Iop_InterleaveHI16x4: resRd = False; size = 1; break;
-//ZZ                case Iop_InterleaveLO16x4: resRd = True;  size = 1; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False));
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False));
-//ZZ             addInstr(env, ARMInstr_NDual(ARMneon_ZIP, rD, rM, size, False));
-//ZZ             return resRd ? rD : rM;
-//ZZ          }
-//ZZ 
-//ZZ          // These 4 verified 18 Apr 2013
-//ZZ          case Iop_CatOddLanes8x8:
-//ZZ          case Iop_CatEvenLanes8x8:
-//ZZ          case Iop_CatOddLanes16x4:
-//ZZ          case Iop_CatEvenLanes16x4: {
-//ZZ             HReg rD   = newVRegD(env);
-//ZZ             HReg rM   = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             Bool resRd;  // is the result in rD or rM ?
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_CatOddLanes8x8:   resRd = False; size = 0; break;
-//ZZ                case Iop_CatEvenLanes8x8:  resRd = True;  size = 0; break;
-//ZZ                case Iop_CatOddLanes16x4:  resRd = False; size = 1; break;
-//ZZ                case Iop_CatEvenLanes16x4: resRd = True;  size = 1; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False));
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False));
-//ZZ             addInstr(env, ARMInstr_NDual(ARMneon_UZP, rD, rM, size, False));
-//ZZ             return resRd ? rD : rM;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_QAdd8Ux8:
-//ZZ          case Iop_QAdd16Ux4:
-//ZZ          case Iop_QAdd32Ux2:
-//ZZ          case Iop_QAdd64Ux1: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QAdd8Ux8: size = 0; break;
-//ZZ                case Iop_QAdd16Ux4: size = 1; break;
-//ZZ                case Iop_QAdd32Ux2: size = 2; break;
-//ZZ                case Iop_QAdd64Ux1: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QAdd8Sx8:
-//ZZ          case Iop_QAdd16Sx4:
-//ZZ          case Iop_QAdd32Sx2:
-//ZZ          case Iop_QAdd64Sx1: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QAdd8Sx8: size = 0; break;
-//ZZ                case Iop_QAdd16Sx4: size = 1; break;
-//ZZ                case Iop_QAdd32Sx2: size = 2; break;
-//ZZ                case Iop_QAdd64Sx1: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Sub8x8:
-//ZZ          case Iop_Sub16x4:
-//ZZ          case Iop_Sub32x2:
-//ZZ          case Iop_Sub64: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Sub8x8: size = 0; break;
-//ZZ                case Iop_Sub16x4: size = 1; break;
-//ZZ                case Iop_Sub32x2: size = 2; break;
-//ZZ                case Iop_Sub64: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Sub32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QSub8Ux8:
-//ZZ          case Iop_QSub16Ux4:
-//ZZ          case Iop_QSub32Ux2:
-//ZZ          case Iop_QSub64Ux1: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QSub8Ux8: size = 0; break;
-//ZZ                case Iop_QSub16Ux4: size = 1; break;
-//ZZ                case Iop_QSub32Ux2: size = 2; break;
-//ZZ                case Iop_QSub64Ux1: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QSub8Sx8:
-//ZZ          case Iop_QSub16Sx4:
-//ZZ          case Iop_QSub32Sx2:
-//ZZ          case Iop_QSub64Sx1: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QSub8Sx8: size = 0; break;
-//ZZ                case Iop_QSub16Sx4: size = 1; break;
-//ZZ                case Iop_QSub32Sx2: size = 2; break;
-//ZZ                case Iop_QSub64Sx1: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Max8Ux8:
-//ZZ          case Iop_Max16Ux4:
-//ZZ          case Iop_Max32Ux2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Max8Ux8: size = 0; break;
-//ZZ                case Iop_Max16Ux4: size = 1; break;
-//ZZ                case Iop_Max32Ux2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Max8Sx8:
-//ZZ          case Iop_Max16Sx4:
-//ZZ          case Iop_Max32Sx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Max8Sx8: size = 0; break;
-//ZZ                case Iop_Max16Sx4: size = 1; break;
-//ZZ                case Iop_Max32Sx2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Min8Ux8:
-//ZZ          case Iop_Min16Ux4:
-//ZZ          case Iop_Min32Ux2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Min8Ux8: size = 0; break;
-//ZZ                case Iop_Min16Ux4: size = 1; break;
-//ZZ                case Iop_Min32Ux2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMINU,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Min8Sx8:
-//ZZ          case Iop_Min16Sx4:
-//ZZ          case Iop_Min32Sx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Min8Sx8: size = 0; break;
-//ZZ                case Iop_Min16Sx4: size = 1; break;
-//ZZ                case Iop_Min32Sx2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMINS,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Sar8x8:
-//ZZ          case Iop_Sar16x4:
-//ZZ          case Iop_Sar32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             HReg argR2 = newVRegD(env);
-//ZZ             HReg zero = newVRegD(env);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Sar8x8: size = 0; break;
-//ZZ                case Iop_Sar16x4: size = 1; break;
-//ZZ                case Iop_Sar32x2: size = 2; break;
-//ZZ                case Iop_Sar64: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
-//ZZ                                            argR2, zero, argR, size, False));
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
-//ZZ                                           res, argL, argR2, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Sal8x8:
-//ZZ          case Iop_Sal16x4:
-//ZZ          case Iop_Sal32x2:
-//ZZ          case Iop_Sal64x1: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Sal8x8: size = 0; break;
-//ZZ                case Iop_Sal16x4: size = 1; break;
-//ZZ                case Iop_Sal32x2: size = 2; break;
-//ZZ                case Iop_Sal64x1: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
-//ZZ                                           res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Shr8x8:
-//ZZ          case Iop_Shr16x4:
-//ZZ          case Iop_Shr32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             HReg argR2 = newVRegD(env);
-//ZZ             HReg zero = newVRegD(env);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Shr8x8: size = 0; break;
-//ZZ                case Iop_Shr16x4: size = 1; break;
-//ZZ                case Iop_Shr32x2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
-//ZZ                                            argR2, zero, argR, size, False));
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
-//ZZ                                           res, argL, argR2, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Shl8x8:
-//ZZ          case Iop_Shl16x4:
-//ZZ          case Iop_Shl32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Shl8x8: size = 0; break;
-//ZZ                case Iop_Shl16x4: size = 1; break;
-//ZZ                case Iop_Shl32x2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
-//ZZ                                           res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QShl8x8:
-//ZZ          case Iop_QShl16x4:
-//ZZ          case Iop_QShl32x2:
-//ZZ          case Iop_QShl64x1: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QShl8x8: size = 0; break;
-//ZZ                case Iop_QShl16x4: size = 1; break;
-//ZZ                case Iop_QShl32x2: size = 2; break;
-//ZZ                case Iop_QShl64x1: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VQSHL,
-//ZZ                                           res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QSal8x8:
-//ZZ          case Iop_QSal16x4:
-//ZZ          case Iop_QSal32x2:
-//ZZ          case Iop_QSal64x1: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QSal8x8: size = 0; break;
-//ZZ                case Iop_QSal16x4: size = 1; break;
-//ZZ                case Iop_QSal32x2: size = 2; break;
-//ZZ                case Iop_QSal64x1: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VQSAL,
-//ZZ                                           res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QShlN8x8:
-//ZZ          case Iop_QShlN16x4:
-//ZZ          case Iop_QShlN32x2:
-//ZZ          case Iop_QShlN64x1: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             UInt size, imm;
-//ZZ             if (e->Iex.Binop.arg2->tag != Iex_Const ||
-//ZZ                 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
-//ZZ                vpanic("ARM taget supports Iop_QShlNAxB with constant "
-//ZZ                       "second argument only\n");
-//ZZ             }
-//ZZ             imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QShlN8x8: size = 8 | imm; break;
-//ZZ                case Iop_QShlN16x4: size = 16 | imm; break;
-//ZZ                case Iop_QShlN32x2: size = 32 | imm; break;
-//ZZ                case Iop_QShlN64x1: size = 64 | imm; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU,
-//ZZ                                           res, argL, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QShlN8Sx8:
-//ZZ          case Iop_QShlN16Sx4:
-//ZZ          case Iop_QShlN32Sx2:
-//ZZ          case Iop_QShlN64Sx1: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             UInt size, imm;
-//ZZ             if (e->Iex.Binop.arg2->tag != Iex_Const ||
-//ZZ                 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
-//ZZ                vpanic("ARM taget supports Iop_QShlNAxB with constant "
-//ZZ                       "second argument only\n");
-//ZZ             }
-//ZZ             imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QShlN8Sx8: size = 8 | imm; break;
-//ZZ                case Iop_QShlN16Sx4: size = 16 | imm; break;
-//ZZ                case Iop_QShlN32Sx2: size = 32 | imm; break;
-//ZZ                case Iop_QShlN64Sx1: size = 64 | imm; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS,
-//ZZ                                           res, argL, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QShlNsatSS8x8:
-//ZZ          case Iop_QShlNsatSS16x4:
-//ZZ          case Iop_QShlNsatSS32x2:
-//ZZ          case Iop_QShlNsatSS64x1: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             UInt size, imm;
-//ZZ             if (e->Iex.Binop.arg2->tag != Iex_Const ||
-//ZZ                 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
-//ZZ                vpanic("ARM taget supports Iop_QShlNAxB with constant "
-//ZZ                       "second argument only\n");
-//ZZ             }
-//ZZ             imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QShlNsatSS8x8: size = 8 | imm; break;
-//ZZ                case Iop_QShlNsatSS16x4: size = 16 | imm; break;
-//ZZ                case Iop_QShlNsatSS32x2: size = 32 | imm; break;
-//ZZ                case Iop_QShlNsatSS64x1: size = 64 | imm; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS,
-//ZZ                                           res, argL, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_ShrN8x8:
-//ZZ          case Iop_ShrN16x4:
-//ZZ          case Iop_ShrN32x2:
-//ZZ          case Iop_Shr64: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg tmp = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
-//ZZ             HReg argR2 = newVRegI(env);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_ShrN8x8: size = 0; break;
-//ZZ                case Iop_ShrN16x4: size = 1; break;
-//ZZ                case Iop_ShrN32x2: size = 2; break;
-//ZZ                case Iop_Shr64: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False));
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
-//ZZ                                           res, argL, tmp, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_ShlN8x8:
-//ZZ          case Iop_ShlN16x4:
-//ZZ          case Iop_ShlN32x2:
-//ZZ          case Iop_Shl64: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg tmp = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             /* special-case Shl64(x, imm8) since the Neon front
-//ZZ                end produces a lot of those for V{LD,ST}{1,2,3,4}. */
-//ZZ             if (e->Iex.Binop.op == Iop_Shl64 
-//ZZ                 && e->Iex.Binop.arg2->tag == Iex_Const) {
-//ZZ                vassert(e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8);
-//ZZ                Int nshift = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
-//ZZ                if (nshift >= 1 && nshift <= 63) {
-//ZZ                   addInstr(env, ARMInstr_NShl64(res, argL, nshift));
-//ZZ                   return res;
-//ZZ                }
-//ZZ                /* else fall through to general case */
-//ZZ             }
-//ZZ             HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_ShlN8x8:  size = 0; break;
-//ZZ                case Iop_ShlN16x4: size = 1; break;
-//ZZ                case Iop_ShlN32x2: size = 2; break;
-//ZZ                case Iop_Shl64:    size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_DUP,
-//ZZ                                           tmp, argR, 0, False));
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
-//ZZ                                           res, argL, tmp, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_SarN8x8:
-//ZZ          case Iop_SarN16x4:
-//ZZ          case Iop_SarN32x2:
-//ZZ          case Iop_Sar64: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg tmp = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
-//ZZ             HReg argR2 = newVRegI(env);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_SarN8x8: size = 0; break;
-//ZZ                case Iop_SarN16x4: size = 1; break;
-//ZZ                case Iop_SarN32x2: size = 2; break;
-//ZZ                case Iop_Sar64: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False));
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
-//ZZ                                           res, argL, tmp, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpGT8Ux8:
-//ZZ          case Iop_CmpGT16Ux4:
-//ZZ          case Iop_CmpGT32Ux2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_CmpGT8Ux8: size = 0; break;
-//ZZ                case Iop_CmpGT16Ux4: size = 1; break;
-//ZZ                case Iop_CmpGT32Ux2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VCGTU,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpGT8Sx8:
-//ZZ          case Iop_CmpGT16Sx4:
-//ZZ          case Iop_CmpGT32Sx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_CmpGT8Sx8: size = 0; break;
-//ZZ                case Iop_CmpGT16Sx4: size = 1; break;
-//ZZ                case Iop_CmpGT32Sx2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpEQ8x8:
-//ZZ          case Iop_CmpEQ16x4:
-//ZZ          case Iop_CmpEQ32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_CmpEQ8x8: size = 0; break;
-//ZZ                case Iop_CmpEQ16x4: size = 1; break;
-//ZZ                case Iop_CmpEQ32x2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Mul8x8:
-//ZZ          case Iop_Mul16x4:
-//ZZ          case Iop_Mul32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Mul8x8: size = 0; break;
-//ZZ                case Iop_Mul16x4: size = 1; break;
-//ZZ                case Iop_Mul32x2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMUL,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Mul32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QDMulHi16Sx4:
-//ZZ          case Iop_QDMulHi32Sx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_QDMulHi16Sx4: size = 1; break;
-//ZZ                case Iop_QDMulHi32Sx2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_QRDMulHi16Sx4:
-//ZZ          case Iop_QRDMulHi32Sx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_QRDMulHi16Sx4: size = 1; break;
-//ZZ                case Iop_QRDMulHi32Sx2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_PwAdd8x8:
-//ZZ          case Iop_PwAdd16x4:
-//ZZ          case Iop_PwAdd32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_PwAdd8x8: size = 0; break;
-//ZZ                case Iop_PwAdd16x4: size = 1; break;
-//ZZ                case Iop_PwAdd32x2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VPADD,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PwAdd32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VPADDFP,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PwMin8Ux8:
-//ZZ          case Iop_PwMin16Ux4:
-//ZZ          case Iop_PwMin32Ux2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_PwMin8Ux8: size = 0; break;
-//ZZ                case Iop_PwMin16Ux4: size = 1; break;
-//ZZ                case Iop_PwMin32Ux2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VPMINU,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PwMin8Sx8:
-//ZZ          case Iop_PwMin16Sx4:
-//ZZ          case Iop_PwMin32Sx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_PwMin8Sx8: size = 0; break;
-//ZZ                case Iop_PwMin16Sx4: size = 1; break;
-//ZZ                case Iop_PwMin32Sx2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VPMINS,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PwMax8Ux8:
-//ZZ          case Iop_PwMax16Ux4:
-//ZZ          case Iop_PwMax32Ux2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_PwMax8Ux8: size = 0; break;
-//ZZ                case Iop_PwMax16Ux4: size = 1; break;
-//ZZ                case Iop_PwMax32Ux2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXU,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PwMax8Sx8:
-//ZZ          case Iop_PwMax16Sx4:
-//ZZ          case Iop_PwMax32Sx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_PwMax8Sx8: size = 0; break;
-//ZZ                case Iop_PwMax16Sx4: size = 1; break;
-//ZZ                case Iop_PwMax32Sx2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXS,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Perm8x8: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VTBL,
-//ZZ                                            res, argL, argR, 0, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PolynomialMul8x8: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMULP,
-//ZZ                                            res, argL, argR, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Max32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF,
-//ZZ                                            res, argL, argR, 2, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Min32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMINF,
-//ZZ                                            res, argL, argR, 2, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PwMax32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF,
-//ZZ                                            res, argL, argR, 2, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PwMin32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF,
-//ZZ                                            res, argL, argR, 2, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpGT32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF,
-//ZZ                                            res, argL, argR, 2, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpGE32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF,
-//ZZ                                            res, argL, argR, 2, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpEQ32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF,
-//ZZ                                            res, argL, argR, 2, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_F32ToFixed32Ux2_RZ:
-//ZZ          case Iop_F32ToFixed32Sx2_RZ:
-//ZZ          case Iop_Fixed32UToF32x2_RN:
-//ZZ          case Iop_Fixed32SToF32x2_RN: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             ARMNeonUnOp op;
-//ZZ             UInt imm6;
-//ZZ             if (e->Iex.Binop.arg2->tag != Iex_Const ||
-//ZZ                typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
-//ZZ                   vpanic("ARM supports FP <-> Fixed conversion with constant "
-//ZZ                          "second argument less than 33 only\n");
-//ZZ             }
-//ZZ             imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
-//ZZ             vassert(imm6 <= 32 && imm6 > 0);
-//ZZ             imm6 = 64 - imm6;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_F32ToFixed32Ux2_RZ: op = ARMneon_VCVTFtoFixedU; break;
-//ZZ                case Iop_F32ToFixed32Sx2_RZ: op = ARMneon_VCVTFtoFixedS; break;
-//ZZ                case Iop_Fixed32UToF32x2_RN: op = ARMneon_VCVTFixedUtoF; break;
-//ZZ                case Iop_Fixed32SToF32x2_RN: op = ARMneon_VCVTFixedStoF; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          /*
-//ZZ          FIXME: is this here or not?
-//ZZ          case Iop_VDup8x8:
-//ZZ          case Iop_VDup16x4:
-//ZZ          case Iop_VDup32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             UInt index;
-//ZZ             UInt imm4;
-//ZZ             UInt size = 0;
-//ZZ             if (e->Iex.Binop.arg2->tag != Iex_Const ||
-//ZZ                typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
-//ZZ                   vpanic("ARM supports Iop_VDup with constant "
-//ZZ                          "second argument less than 16 only\n");
-//ZZ             }
-//ZZ             index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_VDup8x8: imm4 = (index << 1) + 1; break;
-//ZZ                case Iop_VDup16x4: imm4 = (index << 2) + 2; break;
-//ZZ                case Iop_VDup32x2: imm4 = (index << 3) + 4; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             if (imm4 >= 16) {
-//ZZ                vpanic("ARM supports Iop_VDup with constant "
-//ZZ                       "second argument less than 16 only\n");
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VDUP,
-//ZZ                                           res, argL, imm4, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          */
-//ZZ          default:
-//ZZ             break;
-//ZZ       }
-//ZZ    }
-//ZZ 
-//ZZ    /* --------- UNARY ops --------- */
-//ZZ    if (e->tag == Iex_Unop) {
-//ZZ       switch (e->Iex.Unop.op) {
-//ZZ 
-//ZZ          /* 32Uto64 */
-//ZZ          case Iop_32Uto64: {
-//ZZ             HReg rLo = iselIntExpr_R(env, e->Iex.Unop.arg);
-//ZZ             HReg rHi = newVRegI(env);
-//ZZ             HReg res = newVRegD(env);
-//ZZ             addInstr(env, ARMInstr_Imm32(rHi, 0));
-//ZZ             addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          /* 32Sto64 */
-//ZZ          case Iop_32Sto64: {
-//ZZ             HReg rLo = iselIntExpr_R(env, e->Iex.Unop.arg);
-//ZZ             HReg rHi = newVRegI(env);
-//ZZ             addInstr(env, mk_iMOVds_RR(rHi, rLo));
-//ZZ             addInstr(env, ARMInstr_Shift(ARMsh_SAR, rHi, rHi, ARMRI5_I5(31)));
-//ZZ             HReg res = newVRegD(env);
-//ZZ             addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          /* The next 3 are pass-throughs */
-//ZZ          /* ReinterpF64asI64 */
-//ZZ          case Iop_ReinterpF64asI64:
-//ZZ          /* Left64(e) */
-//ZZ          case Iop_Left64:
-//ZZ          /* CmpwNEZ64(e) */
-//ZZ          case Iop_1Sto64: {
-//ZZ             HReg rLo, rHi;
-//ZZ             HReg res = newVRegD(env);
-//ZZ             iselInt64Expr(&rHi, &rLo, env, e);
-//ZZ             addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_Not64: {
-//ZZ             DECLARE_PATTERN(p_veqz_8x8);
-//ZZ             DECLARE_PATTERN(p_veqz_16x4);
-//ZZ             DECLARE_PATTERN(p_veqz_32x2);
-//ZZ             DECLARE_PATTERN(p_vcge_8sx8);
-//ZZ             DECLARE_PATTERN(p_vcge_16sx4);
-//ZZ             DECLARE_PATTERN(p_vcge_32sx2);
-//ZZ             DECLARE_PATTERN(p_vcge_8ux8);
-//ZZ             DECLARE_PATTERN(p_vcge_16ux4);
-//ZZ             DECLARE_PATTERN(p_vcge_32ux2);
-//ZZ             DEFINE_PATTERN(p_veqz_8x8,
-//ZZ                   unop(Iop_Not64, unop(Iop_CmpNEZ8x8, bind(0))));
-//ZZ             DEFINE_PATTERN(p_veqz_16x4,
-//ZZ                   unop(Iop_Not64, unop(Iop_CmpNEZ16x4, bind(0))));
-//ZZ             DEFINE_PATTERN(p_veqz_32x2,
-//ZZ                   unop(Iop_Not64, unop(Iop_CmpNEZ32x2, bind(0))));
-//ZZ             DEFINE_PATTERN(p_vcge_8sx8,
-//ZZ                   unop(Iop_Not64, binop(Iop_CmpGT8Sx8, bind(1), bind(0))));
-//ZZ             DEFINE_PATTERN(p_vcge_16sx4,
-//ZZ                   unop(Iop_Not64, binop(Iop_CmpGT16Sx4, bind(1), bind(0))));
-//ZZ             DEFINE_PATTERN(p_vcge_32sx2,
-//ZZ                   unop(Iop_Not64, binop(Iop_CmpGT32Sx2, bind(1), bind(0))));
-//ZZ             DEFINE_PATTERN(p_vcge_8ux8,
-//ZZ                   unop(Iop_Not64, binop(Iop_CmpGT8Ux8, bind(1), bind(0))));
-//ZZ             DEFINE_PATTERN(p_vcge_16ux4,
-//ZZ                   unop(Iop_Not64, binop(Iop_CmpGT16Ux4, bind(1), bind(0))));
-//ZZ             DEFINE_PATTERN(p_vcge_32ux2,
-//ZZ                   unop(Iop_Not64, binop(Iop_CmpGT32Ux2, bind(1), bind(0))));
-//ZZ             if (matchIRExpr(&mi, p_veqz_8x8, e)) {
-//ZZ                HReg res = newVRegD(env);
-//ZZ                HReg arg = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, False));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_veqz_16x4, e)) {
-//ZZ                HReg res = newVRegD(env);
-//ZZ                HReg arg = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, False));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_veqz_32x2, e)) {
-//ZZ                HReg res = newVRegD(env);
-//ZZ                HReg arg = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, False));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_vcge_8sx8, e)) {
-//ZZ                HReg res = newVRegD(env);
-//ZZ                HReg argL = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                HReg argR = iselNeon64Expr(env, mi.bindee[1]);
-//ZZ                addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
-//ZZ                                               res, argL, argR, 0, False));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_vcge_16sx4, e)) {
-//ZZ                HReg res = newVRegD(env);
-//ZZ                HReg argL = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                HReg argR = iselNeon64Expr(env, mi.bindee[1]);
-//ZZ                addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
-//ZZ                                               res, argL, argR, 1, False));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_vcge_32sx2, e)) {
-//ZZ                HReg res = newVRegD(env);
-//ZZ                HReg argL = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                HReg argR = iselNeon64Expr(env, mi.bindee[1]);
-//ZZ                addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
-//ZZ                                               res, argL, argR, 2, False));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_vcge_8ux8, e)) {
-//ZZ                HReg res = newVRegD(env);
-//ZZ                HReg argL = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                HReg argR = iselNeon64Expr(env, mi.bindee[1]);
-//ZZ                addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
-//ZZ                                               res, argL, argR, 0, False));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_vcge_16ux4, e)) {
-//ZZ                HReg res = newVRegD(env);
-//ZZ                HReg argL = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                HReg argR = iselNeon64Expr(env, mi.bindee[1]);
-//ZZ                addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
-//ZZ                                               res, argL, argR, 1, False));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_vcge_32ux2, e)) {
-//ZZ                HReg res = newVRegD(env);
-//ZZ                HReg argL = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                HReg argR = iselNeon64Expr(env, mi.bindee[1]);
-//ZZ                addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
-//ZZ                                               res, argL, argR, 2, False));
-//ZZ                return res;
-//ZZ             } else {
-//ZZ                HReg res = newVRegD(env);
-//ZZ                HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ                addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, False));
-//ZZ                return res;
-//ZZ             }
-//ZZ          }
-//ZZ          case Iop_Dup8x8:
-//ZZ          case Iop_Dup16x4:
-//ZZ          case Iop_Dup32x2: {
-//ZZ             HReg res, arg;
-//ZZ             UInt size;
-//ZZ             DECLARE_PATTERN(p_vdup_8x8);
-//ZZ             DECLARE_PATTERN(p_vdup_16x4);
-//ZZ             DECLARE_PATTERN(p_vdup_32x2);
-//ZZ             DEFINE_PATTERN(p_vdup_8x8,
-//ZZ                   unop(Iop_Dup8x8, binop(Iop_GetElem8x8, bind(0), bind(1))));
-//ZZ             DEFINE_PATTERN(p_vdup_16x4,
-//ZZ                   unop(Iop_Dup16x4, binop(Iop_GetElem16x4, bind(0), bind(1))));
-//ZZ             DEFINE_PATTERN(p_vdup_32x2,
-//ZZ                   unop(Iop_Dup32x2, binop(Iop_GetElem32x2, bind(0), bind(1))));
-//ZZ             if (matchIRExpr(&mi, p_vdup_8x8, e)) {
-//ZZ                UInt index;
-//ZZ                UInt imm4;
-//ZZ                if (mi.bindee[1]->tag == Iex_Const &&
-//ZZ                   typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
-//ZZ                   index = mi.bindee[1]->Iex.Const.con->Ico.U8;
-//ZZ                   imm4 = (index << 1) + 1;
-//ZZ                   if (index < 8) {
-//ZZ                      res = newVRegD(env);
-//ZZ                      arg = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                      addInstr(env, ARMInstr_NUnaryS(
-//ZZ                                       ARMneon_VDUP,
-//ZZ                                       mkARMNRS(ARMNRS_Reg, res, 0),
-//ZZ                                       mkARMNRS(ARMNRS_Scalar, arg, index),
-//ZZ                                       imm4, False
-//ZZ                              ));
-//ZZ                      return res;
-//ZZ                   }
-//ZZ                }
-//ZZ             } else if (matchIRExpr(&mi, p_vdup_16x4, e)) {
-//ZZ                UInt index;
-//ZZ                UInt imm4;
-//ZZ                if (mi.bindee[1]->tag == Iex_Const &&
-//ZZ                   typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
-//ZZ                   index = mi.bindee[1]->Iex.Const.con->Ico.U8;
-//ZZ                   imm4 = (index << 2) + 2;
-//ZZ                   if (index < 4) {
-//ZZ                      res = newVRegD(env);
-//ZZ                      arg = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                      addInstr(env, ARMInstr_NUnaryS(
-//ZZ                                       ARMneon_VDUP,
-//ZZ                                       mkARMNRS(ARMNRS_Reg, res, 0),
-//ZZ                                       mkARMNRS(ARMNRS_Scalar, arg, index),
-//ZZ                                       imm4, False
-//ZZ                              ));
-//ZZ                      return res;
-//ZZ                   }
-//ZZ                }
-//ZZ             } else if (matchIRExpr(&mi, p_vdup_32x2, e)) {
-//ZZ                UInt index;
-//ZZ                UInt imm4;
-//ZZ                if (mi.bindee[1]->tag == Iex_Const &&
-//ZZ                   typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
-//ZZ                   index = mi.bindee[1]->Iex.Const.con->Ico.U8;
-//ZZ                   imm4 = (index << 3) + 4;
-//ZZ                   if (index < 2) {
-//ZZ                      res = newVRegD(env);
-//ZZ                      arg = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                      addInstr(env, ARMInstr_NUnaryS(
-//ZZ                                       ARMneon_VDUP,
-//ZZ                                       mkARMNRS(ARMNRS_Reg, res, 0),
-//ZZ                                       mkARMNRS(ARMNRS_Scalar, arg, index),
-//ZZ                                       imm4, False
-//ZZ                              ));
-//ZZ                      return res;
-//ZZ                   }
-//ZZ                }
-//ZZ             }
-//ZZ             arg = iselIntExpr_R(env, e->Iex.Unop.arg);
-//ZZ             res = newVRegD(env);
-//ZZ             switch (e->Iex.Unop.op) {
-//ZZ                case Iop_Dup8x8: size = 0; break;
-//ZZ                case Iop_Dup16x4: size = 1; break;
-//ZZ                case Iop_Dup32x2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Abs8x8:
-//ZZ          case Iop_Abs16x4:
-//ZZ          case Iop_Abs32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Abs8x8: size = 0; break;
-//ZZ                case Iop_Abs16x4: size = 1; break;
-//ZZ                case Iop_Abs32x2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Reverse64_8x8:
-//ZZ          case Iop_Reverse64_16x4:
-//ZZ          case Iop_Reverse64_32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Reverse64_8x8: size = 0; break;
-//ZZ                case Iop_Reverse64_16x4: size = 1; break;
-//ZZ                case Iop_Reverse64_32x2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_REV64,
-//ZZ                                           res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Reverse32_8x8:
-//ZZ          case Iop_Reverse32_16x4: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Reverse32_8x8: size = 0; break;
-//ZZ                case Iop_Reverse32_16x4: size = 1; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_REV32,
-//ZZ                                           res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Reverse16_8x8: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_REV16,
-//ZZ                                           res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpwNEZ64: {
-//ZZ             HReg x_lsh = newVRegD(env);
-//ZZ             HReg x_rsh = newVRegD(env);
-//ZZ             HReg lsh_amt = newVRegD(env);
-//ZZ             HReg rsh_amt = newVRegD(env);
-//ZZ             HReg zero = newVRegD(env);
-//ZZ             HReg tmp = newVRegD(env);
-//ZZ             HReg tmp2 = newVRegD(env);
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg x = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, False));
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, False));
-//ZZ             addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32)));
-//ZZ             addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0)));
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
-//ZZ                                            rsh_amt, zero, lsh_amt, 2, False));
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
-//ZZ                                           x_lsh, x, lsh_amt, 3, False));
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
-//ZZ                                           x_rsh, x, rsh_amt, 3, False));
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
-//ZZ                                            tmp, x_lsh, x_rsh, 0, False));
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
-//ZZ                                            res, tmp, x, 0, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpNEZ8x8:
-//ZZ          case Iop_CmpNEZ16x4:
-//ZZ          case Iop_CmpNEZ32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg tmp = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Unop.op) {
-//ZZ                case Iop_CmpNEZ8x8: size = 0; break;
-//ZZ                case Iop_CmpNEZ16x4: size = 1; break;
-//ZZ                case Iop_CmpNEZ32x2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp, arg, size, False));
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_NarrowUn16to8x8:
-//ZZ          case Iop_NarrowUn32to16x4:
-//ZZ          case Iop_NarrowUn64to32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_NarrowUn16to8x8:  size = 0; break;
-//ZZ                case Iop_NarrowUn32to16x4: size = 1; break;
-//ZZ                case Iop_NarrowUn64to32x2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPYN,
-//ZZ                                           res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QNarrowUn16Sto8Sx8:
-//ZZ          case Iop_QNarrowUn32Sto16Sx4:
-//ZZ          case Iop_QNarrowUn64Sto32Sx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_QNarrowUn16Sto8Sx8:  size = 0; break;
-//ZZ                case Iop_QNarrowUn32Sto16Sx4: size = 1; break;
-//ZZ                case Iop_QNarrowUn64Sto32Sx2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNSS,
-//ZZ                                           res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QNarrowUn16Sto8Ux8:
-//ZZ          case Iop_QNarrowUn32Sto16Ux4:
-//ZZ          case Iop_QNarrowUn64Sto32Ux2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_QNarrowUn16Sto8Ux8:  size = 0; break;
-//ZZ                case Iop_QNarrowUn32Sto16Ux4: size = 1; break;
-//ZZ                case Iop_QNarrowUn64Sto32Ux2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUS,
-//ZZ                                           res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QNarrowUn16Uto8Ux8:
-//ZZ          case Iop_QNarrowUn32Uto16Ux4:
-//ZZ          case Iop_QNarrowUn64Uto32Ux2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_QNarrowUn16Uto8Ux8:  size = 0; break;
-//ZZ                case Iop_QNarrowUn32Uto16Ux4: size = 1; break;
-//ZZ                case Iop_QNarrowUn64Uto32Ux2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUU,
-//ZZ                                           res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PwAddL8Sx8:
-//ZZ          case Iop_PwAddL16Sx4:
-//ZZ          case Iop_PwAddL32Sx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_PwAddL8Sx8: size = 0; break;
-//ZZ                case Iop_PwAddL16Sx4: size = 1; break;
-//ZZ                case Iop_PwAddL32Sx2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS,
-//ZZ                                           res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PwAddL8Ux8:
-//ZZ          case Iop_PwAddL16Ux4:
-//ZZ          case Iop_PwAddL32Ux2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_PwAddL8Ux8: size = 0; break;
-//ZZ                case Iop_PwAddL16Ux4: size = 1; break;
-//ZZ                case Iop_PwAddL32Ux2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU,
-//ZZ                                           res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Cnt8x8: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_CNT,
-//ZZ                                           res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Clz8Sx8:
-//ZZ          case Iop_Clz16Sx4:
-//ZZ          case Iop_Clz32Sx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Clz8Sx8: size = 0; break;
-//ZZ                case Iop_Clz16Sx4: size = 1; break;
-//ZZ                case Iop_Clz32Sx2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_CLZ,
-//ZZ                                           res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Cls8Sx8:
-//ZZ          case Iop_Cls16Sx4:
-//ZZ          case Iop_Cls32Sx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Cls8Sx8: size = 0; break;
-//ZZ                case Iop_Cls16Sx4: size = 1; break;
-//ZZ                case Iop_Cls32Sx2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_CLS,
-//ZZ                                           res, arg, size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_FtoI32Sx2_RZ: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS,
-//ZZ                                           res, arg, 2, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_FtoI32Ux2_RZ: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU,
-//ZZ                                           res, arg, 2, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_I32StoFx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF,
-//ZZ                                           res, arg, 2, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_I32UtoFx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF,
-//ZZ                                           res, arg, 2, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_F32toF16x4: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF32toF16,
-//ZZ                                           res, arg, 2, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Recip32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF,
-//ZZ                                           res, argL, 0, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Recip32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP,
-//ZZ                                           res, argL, 0, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Abs32Fx2: {
-//ZZ             DECLARE_PATTERN(p_vabd_32fx2);
-//ZZ             DEFINE_PATTERN(p_vabd_32fx2,
-//ZZ                            unop(Iop_Abs32Fx2,
-//ZZ                                 binop(Iop_Sub32Fx2,
-//ZZ                                       bind(0),
-//ZZ                                       bind(1))));
-//ZZ             if (matchIRExpr(&mi, p_vabd_32fx2, e)) {
-//ZZ                HReg res = newVRegD(env);
-//ZZ                HReg argL = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                HReg argR = iselNeon64Expr(env, mi.bindee[1]);
-//ZZ                addInstr(env, ARMInstr_NBinary(ARMneon_VABDFP,
-//ZZ                                               res, argL, argR, 0, False));
-//ZZ                return res;
-//ZZ             } else {
-//ZZ                HReg res = newVRegD(env);
-//ZZ                HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ                addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP,
-//ZZ                                              res, arg, 0, False));
-//ZZ                return res;
-//ZZ             }
-//ZZ          }
-//ZZ          case Iop_Rsqrte32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP,
-//ZZ                                           res, arg, 0, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Rsqrte32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE,
-//ZZ                                           res, arg, 0, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Neg32Fx2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VNEGF,
-//ZZ                                           res, arg, 0, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          default:
-//ZZ             break;
-//ZZ       }
-//ZZ    } /* if (e->tag == Iex_Unop) */
-//ZZ 
-//ZZ    if (e->tag == Iex_Triop) {
-//ZZ       IRTriop *triop = e->Iex.Triop.details;
-//ZZ 
-//ZZ       switch (triop->op) {
-//ZZ          case Iop_Extract64: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg argL = iselNeon64Expr(env, triop->arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, triop->arg2);
-//ZZ             UInt imm4;
-//ZZ             if (triop->arg3->tag != Iex_Const ||
-//ZZ                 typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) {
-//ZZ                vpanic("ARM target supports Iop_Extract64 with constant "
-//ZZ                       "third argument less than 16 only\n");
-//ZZ             }
-//ZZ             imm4 = triop->arg3->Iex.Const.con->Ico.U8;
-//ZZ             if (imm4 >= 8) {
-//ZZ                vpanic("ARM target supports Iop_Extract64 with constant "
-//ZZ                       "third argument less than 16 only\n");
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VEXT,
-//ZZ                                            res, argL, argR, imm4, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_SetElem8x8:
-//ZZ          case Iop_SetElem16x4:
-//ZZ          case Iop_SetElem32x2: {
-//ZZ             HReg res = newVRegD(env);
-//ZZ             HReg dreg = iselNeon64Expr(env, triop->arg1);
-//ZZ             HReg arg = iselIntExpr_R(env, triop->arg3);
-//ZZ             UInt index, size;
-//ZZ             if (triop->arg2->tag != Iex_Const ||
-//ZZ                 typeOfIRExpr(env->type_env, triop->arg2) != Ity_I8) {
-//ZZ                vpanic("ARM target supports SetElem with constant "
-//ZZ                       "second argument only\n");
-//ZZ             }
-//ZZ             index = triop->arg2->Iex.Const.con->Ico.U8;
-//ZZ             switch (triop->op) {
-//ZZ                case Iop_SetElem8x8: vassert(index < 8); size = 0; break;
-//ZZ                case Iop_SetElem16x4: vassert(index < 4); size = 1; break;
-//ZZ                case Iop_SetElem32x2: vassert(index < 2); size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPY, res, dreg, 4, False));
-//ZZ             addInstr(env, ARMInstr_NUnaryS(ARMneon_SETELEM,
-//ZZ                                            mkARMNRS(ARMNRS_Scalar, res, index),
-//ZZ                                            mkARMNRS(ARMNRS_Reg, arg, 0),
-//ZZ                                            size, False));
-//ZZ             return res;
-//ZZ          }
-//ZZ          default:
-//ZZ             break;
-//ZZ       }
-//ZZ    }
-//ZZ 
-//ZZ    /* --------- MULTIPLEX --------- */
-//ZZ    if (e->tag == Iex_ITE) { // VFD
-//ZZ       HReg rLo, rHi;
-//ZZ       HReg res = newVRegD(env);
-//ZZ       iselInt64Expr(&rHi, &rLo, env, e);
-//ZZ       addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
-//ZZ       return res;
-//ZZ    }
-//ZZ 
-//ZZ    ppIRExpr(e);
-//ZZ    vpanic("iselNeon64Expr");
-//ZZ }
-
-
 /*---------------------------------------------------------*/
 /*--- ISEL: Vector expressions (128 bit)                ---*/
 /*---------------------------------------------------------*/
@@ -4528,426 +2281,6 @@
             addInstr(env, ARM64Instr_VQfromX(res, arg));
             return res;
          }
-
-//ZZ          case Iop_NotV128: {
-//ZZ             DECLARE_PATTERN(p_veqz_8x16);
-//ZZ             DECLARE_PATTERN(p_veqz_16x8);
-//ZZ             DECLARE_PATTERN(p_veqz_32x4);
-//ZZ             DECLARE_PATTERN(p_vcge_8sx16);
-//ZZ             DECLARE_PATTERN(p_vcge_16sx8);
-//ZZ             DECLARE_PATTERN(p_vcge_32sx4);
-//ZZ             DECLARE_PATTERN(p_vcge_8ux16);
-//ZZ             DECLARE_PATTERN(p_vcge_16ux8);
-//ZZ             DECLARE_PATTERN(p_vcge_32ux4);
-//ZZ             DEFINE_PATTERN(p_veqz_8x16,
-//ZZ                   unop(Iop_NotV128, unop(Iop_CmpNEZ8x16, bind(0))));
-//ZZ             DEFINE_PATTERN(p_veqz_16x8,
-//ZZ                   unop(Iop_NotV128, unop(Iop_CmpNEZ16x8, bind(0))));
-//ZZ             DEFINE_PATTERN(p_veqz_32x4,
-//ZZ                   unop(Iop_NotV128, unop(Iop_CmpNEZ32x4, bind(0))));
-//ZZ             DEFINE_PATTERN(p_vcge_8sx16,
-//ZZ                   unop(Iop_NotV128, binop(Iop_CmpGT8Sx16, bind(1), bind(0))));
-//ZZ             DEFINE_PATTERN(p_vcge_16sx8,
-//ZZ                   unop(Iop_NotV128, binop(Iop_CmpGT16Sx8, bind(1), bind(0))));
-//ZZ             DEFINE_PATTERN(p_vcge_32sx4,
-//ZZ                   unop(Iop_NotV128, binop(Iop_CmpGT32Sx4, bind(1), bind(0))));
-//ZZ             DEFINE_PATTERN(p_vcge_8ux16,
-//ZZ                   unop(Iop_NotV128, binop(Iop_CmpGT8Ux16, bind(1), bind(0))));
-//ZZ             DEFINE_PATTERN(p_vcge_16ux8,
-//ZZ                   unop(Iop_NotV128, binop(Iop_CmpGT16Ux8, bind(1), bind(0))));
-//ZZ             DEFINE_PATTERN(p_vcge_32ux4,
-//ZZ                   unop(Iop_NotV128, binop(Iop_CmpGT32Ux4, bind(1), bind(0))));
-//ZZ             if (matchIRExpr(&mi, p_veqz_8x16, e)) {
-//ZZ                HReg res = newVRegV(env);
-//ZZ                HReg arg = iselNeonExpr(env, mi.bindee[0]);
-//ZZ                addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, True));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_veqz_16x8, e)) {
-//ZZ                HReg res = newVRegV(env);
-//ZZ                HReg arg = iselNeonExpr(env, mi.bindee[0]);
-//ZZ                addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, True));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_veqz_32x4, e)) {
-//ZZ                HReg res = newVRegV(env);
-//ZZ                HReg arg = iselNeonExpr(env, mi.bindee[0]);
-//ZZ                addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, True));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_vcge_8sx16, e)) {
-//ZZ                HReg res = newVRegV(env);
-//ZZ                HReg argL = iselNeonExpr(env, mi.bindee[0]);
-//ZZ                HReg argR = iselNeonExpr(env, mi.bindee[1]);
-//ZZ                addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
-//ZZ                                               res, argL, argR, 0, True));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_vcge_16sx8, e)) {
-//ZZ                HReg res = newVRegV(env);
-//ZZ                HReg argL = iselNeonExpr(env, mi.bindee[0]);
-//ZZ                HReg argR = iselNeonExpr(env, mi.bindee[1]);
-//ZZ                addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
-//ZZ                                               res, argL, argR, 1, True));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_vcge_32sx4, e)) {
-//ZZ                HReg res = newVRegV(env);
-//ZZ                HReg argL = iselNeonExpr(env, mi.bindee[0]);
-//ZZ                HReg argR = iselNeonExpr(env, mi.bindee[1]);
-//ZZ                addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
-//ZZ                                               res, argL, argR, 2, True));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_vcge_8ux16, e)) {
-//ZZ                HReg res = newVRegV(env);
-//ZZ                HReg argL = iselNeonExpr(env, mi.bindee[0]);
-//ZZ                HReg argR = iselNeonExpr(env, mi.bindee[1]);
-//ZZ                addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
-//ZZ                                               res, argL, argR, 0, True));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_vcge_16ux8, e)) {
-//ZZ                HReg res = newVRegV(env);
-//ZZ                HReg argL = iselNeonExpr(env, mi.bindee[0]);
-//ZZ                HReg argR = iselNeonExpr(env, mi.bindee[1]);
-//ZZ                addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
-//ZZ                                               res, argL, argR, 1, True));
-//ZZ                return res;
-//ZZ             } else if (matchIRExpr(&mi, p_vcge_32ux4, e)) {
-//ZZ                HReg res = newVRegV(env);
-//ZZ                HReg argL = iselNeonExpr(env, mi.bindee[0]);
-//ZZ                HReg argR = iselNeonExpr(env, mi.bindee[1]);
-//ZZ                addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
-//ZZ                                               res, argL, argR, 2, True));
-//ZZ                return res;
-//ZZ             } else {
-//ZZ                HReg res = newVRegV(env);
-//ZZ                HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ                addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, True));
-//ZZ                return res;
-//ZZ             }
-//ZZ          }
-//ZZ          case Iop_Dup8x16:
-//ZZ          case Iop_Dup16x8:
-//ZZ          case Iop_Dup32x4: {
-//ZZ             HReg res, arg;
-//ZZ             UInt size;
-//ZZ             DECLARE_PATTERN(p_vdup_8x16);
-//ZZ             DECLARE_PATTERN(p_vdup_16x8);
-//ZZ             DECLARE_PATTERN(p_vdup_32x4);
-//ZZ             DEFINE_PATTERN(p_vdup_8x16,
-//ZZ                   unop(Iop_Dup8x16, binop(Iop_GetElem8x8, bind(0), bind(1))));
-//ZZ             DEFINE_PATTERN(p_vdup_16x8,
-//ZZ                   unop(Iop_Dup16x8, binop(Iop_GetElem16x4, bind(0), bind(1))));
-//ZZ             DEFINE_PATTERN(p_vdup_32x4,
-//ZZ                   unop(Iop_Dup32x4, binop(Iop_GetElem32x2, bind(0), bind(1))));
-//ZZ             if (matchIRExpr(&mi, p_vdup_8x16, e)) {
-//ZZ                UInt index;
-//ZZ                UInt imm4;
-//ZZ                if (mi.bindee[1]->tag == Iex_Const &&
-//ZZ                   typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
-//ZZ                   index = mi.bindee[1]->Iex.Const.con->Ico.U8;
-//ZZ                   imm4 = (index << 1) + 1;
-//ZZ                   if (index < 8) {
-//ZZ                      res = newVRegV(env);
-//ZZ                      arg = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                      addInstr(env, ARMInstr_NUnaryS(
-//ZZ                                       ARMneon_VDUP,
-//ZZ                                       mkARMNRS(ARMNRS_Reg, res, 0),
-//ZZ                                       mkARMNRS(ARMNRS_Scalar, arg, index),
-//ZZ                                       imm4, True
-//ZZ                              ));
-//ZZ                      return res;
-//ZZ                   }
-//ZZ                }
-//ZZ             } else if (matchIRExpr(&mi, p_vdup_16x8, e)) {
-//ZZ                UInt index;
-//ZZ                UInt imm4;
-//ZZ                if (mi.bindee[1]->tag == Iex_Const &&
-//ZZ                   typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
-//ZZ                   index = mi.bindee[1]->Iex.Const.con->Ico.U8;
-//ZZ                   imm4 = (index << 2) + 2;
-//ZZ                   if (index < 4) {
-//ZZ                      res = newVRegV(env);
-//ZZ                      arg = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                      addInstr(env, ARMInstr_NUnaryS(
-//ZZ                                       ARMneon_VDUP,
-//ZZ                                       mkARMNRS(ARMNRS_Reg, res, 0),
-//ZZ                                       mkARMNRS(ARMNRS_Scalar, arg, index),
-//ZZ                                       imm4, True
-//ZZ                              ));
-//ZZ                      return res;
-//ZZ                   }
-//ZZ                }
-//ZZ             } else if (matchIRExpr(&mi, p_vdup_32x4, e)) {
-//ZZ                UInt index;
-//ZZ                UInt imm4;
-//ZZ                if (mi.bindee[1]->tag == Iex_Const &&
-//ZZ                   typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
-//ZZ                   index = mi.bindee[1]->Iex.Const.con->Ico.U8;
-//ZZ                   imm4 = (index << 3) + 4;
-//ZZ                   if (index < 2) {
-//ZZ                      res = newVRegV(env);
-//ZZ                      arg = iselNeon64Expr(env, mi.bindee[0]);
-//ZZ                      addInstr(env, ARMInstr_NUnaryS(
-//ZZ                                       ARMneon_VDUP,
-//ZZ                                       mkARMNRS(ARMNRS_Reg, res, 0),
-//ZZ                                       mkARMNRS(ARMNRS_Scalar, arg, index),
-//ZZ                                       imm4, True
-//ZZ                              ));
-//ZZ                      return res;
-//ZZ                   }
-//ZZ                }
-//ZZ             }
-//ZZ             arg = iselIntExpr_R(env, e->Iex.Unop.arg);
-//ZZ             res = newVRegV(env);
-//ZZ             switch (e->Iex.Unop.op) {
-//ZZ                case Iop_Dup8x16: size = 0; break;
-//ZZ                case Iop_Dup16x8: size = 1; break;
-//ZZ                case Iop_Dup32x4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Abs8x16:
-//ZZ          case Iop_Abs16x8:
-//ZZ          case Iop_Abs32x4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Abs8x16: size = 0; break;
-//ZZ                case Iop_Abs16x8: size = 1; break;
-//ZZ                case Iop_Abs32x4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Reverse64_8x16:
-//ZZ          case Iop_Reverse64_16x8:
-//ZZ          case Iop_Reverse64_32x4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Reverse64_8x16: size = 0; break;
-//ZZ                case Iop_Reverse64_16x8: size = 1; break;
-//ZZ                case Iop_Reverse64_32x4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_REV64,
-//ZZ                                           res, arg, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Reverse32_8x16:
-//ZZ          case Iop_Reverse32_16x8: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Reverse32_8x16: size = 0; break;
-//ZZ                case Iop_Reverse32_16x8: size = 1; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_REV32,
-//ZZ                                           res, arg, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Reverse16_8x16: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_REV16,
-//ZZ                                           res, arg, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpNEZ64x2: {
-//ZZ             HReg x_lsh = newVRegV(env);
-//ZZ             HReg x_rsh = newVRegV(env);
-//ZZ             HReg lsh_amt = newVRegV(env);
-//ZZ             HReg rsh_amt = newVRegV(env);
-//ZZ             HReg zero = newVRegV(env);
-//ZZ             HReg tmp = newVRegV(env);
-//ZZ             HReg tmp2 = newVRegV(env);
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg x = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, True));
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, True));
-//ZZ             addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32)));
-//ZZ             addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0)));
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
-//ZZ                                            rsh_amt, zero, lsh_amt, 2, True));
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
-//ZZ                                           x_lsh, x, lsh_amt, 3, True));
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
-//ZZ                                           x_rsh, x, rsh_amt, 3, True));
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
-//ZZ                                            tmp, x_lsh, x_rsh, 0, True));
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
-//ZZ                                            res, tmp, x, 0, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Widen8Uto16x8:
-//ZZ          case Iop_Widen16Uto32x4:
-//ZZ          case Iop_Widen32Uto64x2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Unop.op) {
-//ZZ                case Iop_Widen8Uto16x8:  size = 0; break;
-//ZZ                case Iop_Widen16Uto32x4: size = 1; break;
-//ZZ                case Iop_Widen32Uto64x2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPYLU,
-//ZZ                                           res, arg, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Widen8Sto16x8:
-//ZZ          case Iop_Widen16Sto32x4:
-//ZZ          case Iop_Widen32Sto64x2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Unop.op) {
-//ZZ                case Iop_Widen8Sto16x8:  size = 0; break;
-//ZZ                case Iop_Widen16Sto32x4: size = 1; break;
-//ZZ                case Iop_Widen32Sto64x2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPYLS,
-//ZZ                                           res, arg, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PwAddL8Sx16:
-//ZZ          case Iop_PwAddL16Sx8:
-//ZZ          case Iop_PwAddL32Sx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_PwAddL8Sx16: size = 0; break;
-//ZZ                case Iop_PwAddL16Sx8: size = 1; break;
-//ZZ                case Iop_PwAddL32Sx4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS,
-//ZZ                                           res, arg, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PwAddL8Ux16:
-//ZZ          case Iop_PwAddL16Ux8:
-//ZZ          case Iop_PwAddL32Ux4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_PwAddL8Ux16: size = 0; break;
-//ZZ                case Iop_PwAddL16Ux8: size = 1; break;
-//ZZ                case Iop_PwAddL32Ux4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU,
-//ZZ                                           res, arg, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Cnt8x16: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_CNT, res, arg, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Clz8Sx16:
-//ZZ          case Iop_Clz16Sx8:
-//ZZ          case Iop_Clz32Sx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Clz8Sx16: size = 0; break;
-//ZZ                case Iop_Clz16Sx8: size = 1; break;
-//ZZ                case Iop_Clz32Sx4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_CLZ, res, arg, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Cls8Sx16:
-//ZZ          case Iop_Cls16Sx8:
-//ZZ          case Iop_Cls32Sx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Cls8Sx16: size = 0; break;
-//ZZ                case Iop_Cls16Sx8: size = 1; break;
-//ZZ                case Iop_Cls32Sx4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_CLS, res, arg, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_FtoI32Sx4_RZ: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS,
-//ZZ                                           res, arg, 2, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_FtoI32Ux4_RZ: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU,
-//ZZ                                           res, arg, 2, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_I32StoFx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF,
-//ZZ                                           res, arg, 2, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_I32UtoFx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF,
-//ZZ                                           res, arg, 2, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_F16toF32x4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF16toF32,
-//ZZ                                           res, arg, 2, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Recip32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF,
-//ZZ                                           res, argL, 0, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Recip32x4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP,
-//ZZ                                           res, argL, 0, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Rsqrte32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP,
-//ZZ                                           res, argL, 0, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Rsqrte32x4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE,
-//ZZ                                           res, argL, 0, True));
-//ZZ             return res;
-//ZZ          }
          /* ... */
          default:
             break;
@@ -5114,496 +2447,6 @@
             }
             return res;
          }
-//ZZ          case Iop_Add32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Recps32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Rsqrts32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          // These 6 verified 18 Apr 2013
-//ZZ          case Iop_InterleaveEvenLanes8x16:
-//ZZ          case Iop_InterleaveOddLanes8x16:
-//ZZ          case Iop_InterleaveEvenLanes16x8:
-//ZZ          case Iop_InterleaveOddLanes16x8:
-//ZZ          case Iop_InterleaveEvenLanes32x4:
-//ZZ          case Iop_InterleaveOddLanes32x4: {
-//ZZ             HReg rD   = newVRegV(env);
-//ZZ             HReg rM   = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             Bool resRd;  // is the result in rD or rM ?
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_InterleaveOddLanes8x16:  resRd = False; size = 0; break;
-//ZZ                case Iop_InterleaveEvenLanes8x16: resRd = True;  size = 0; break;
-//ZZ                case Iop_InterleaveOddLanes16x8:  resRd = False; size = 1; break;
-//ZZ                case Iop_InterleaveEvenLanes16x8: resRd = True;  size = 1; break;
-//ZZ                case Iop_InterleaveOddLanes32x4:  resRd = False; size = 2; break;
-//ZZ                case Iop_InterleaveEvenLanes32x4: resRd = True;  size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, True));
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, True));
-//ZZ             addInstr(env, ARMInstr_NDual(ARMneon_TRN, rD, rM, size, True));
-//ZZ             return resRd ? rD : rM;
-//ZZ          }
-//ZZ 
-//ZZ          // These 6 verified 18 Apr 2013
-//ZZ          case Iop_InterleaveHI8x16:
-//ZZ          case Iop_InterleaveLO8x16:
-//ZZ          case Iop_InterleaveHI16x8:
-//ZZ          case Iop_InterleaveLO16x8:
-//ZZ          case Iop_InterleaveHI32x4:
-//ZZ          case Iop_InterleaveLO32x4: {
-//ZZ             HReg rD   = newVRegV(env);
-//ZZ             HReg rM   = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             Bool resRd;  // is the result in rD or rM ?
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_InterleaveHI8x16: resRd = False; size = 0; break;
-//ZZ                case Iop_InterleaveLO8x16: resRd = True;  size = 0; break;
-//ZZ                case Iop_InterleaveHI16x8: resRd = False; size = 1; break;
-//ZZ                case Iop_InterleaveLO16x8: resRd = True;  size = 1; break;
-//ZZ                case Iop_InterleaveHI32x4: resRd = False; size = 2; break;
-//ZZ                case Iop_InterleaveLO32x4: resRd = True;  size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, True));
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, True));
-//ZZ             addInstr(env, ARMInstr_NDual(ARMneon_ZIP, rD, rM, size, True));
-//ZZ             return resRd ? rD : rM;
-//ZZ          }
-//ZZ 
-//ZZ          // These 6 verified 18 Apr 2013
-//ZZ          case Iop_CatOddLanes8x16:
-//ZZ          case Iop_CatEvenLanes8x16:
-//ZZ          case Iop_CatOddLanes16x8:
-//ZZ          case Iop_CatEvenLanes16x8:
-//ZZ          case Iop_CatOddLanes32x4:
-//ZZ          case Iop_CatEvenLanes32x4: {
-//ZZ             HReg rD   = newVRegV(env);
-//ZZ             HReg rM   = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             Bool resRd;  // is the result in rD or rM ?
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_CatOddLanes8x16:  resRd = False; size = 0; break;
-//ZZ                case Iop_CatEvenLanes8x16: resRd = True;  size = 0; break;
-//ZZ                case Iop_CatOddLanes16x8:  resRd = False; size = 1; break;
-//ZZ                case Iop_CatEvenLanes16x8: resRd = True;  size = 1; break;
-//ZZ                case Iop_CatOddLanes32x4:  resRd = False; size = 2; break;
-//ZZ                case Iop_CatEvenLanes32x4: resRd = True;  size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, True));
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, True));
-//ZZ             addInstr(env, ARMInstr_NDual(ARMneon_UZP, rD, rM, size, True));
-//ZZ             return resRd ? rD : rM;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_QAdd8Ux16:
-//ZZ          case Iop_QAdd16Ux8:
-//ZZ          case Iop_QAdd32Ux4:
-//ZZ          case Iop_QAdd64Ux2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QAdd8Ux16: size = 0; break;
-//ZZ                case Iop_QAdd16Ux8: size = 1; break;
-//ZZ                case Iop_QAdd32Ux4: size = 2; break;
-//ZZ                case Iop_QAdd64Ux2: size = 3; break;
-//ZZ                default:
-//ZZ                   ppIROp(e->Iex.Binop.op);
-//ZZ                   vpanic("Illegal element size in VQADDU");
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QAdd8Sx16:
-//ZZ          case Iop_QAdd16Sx8:
-//ZZ          case Iop_QAdd32Sx4:
-//ZZ          case Iop_QAdd64Sx2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QAdd8Sx16: size = 0; break;
-//ZZ                case Iop_QAdd16Sx8: size = 1; break;
-//ZZ                case Iop_QAdd32Sx4: size = 2; break;
-//ZZ                case Iop_QAdd64Sx2: size = 3; break;
-//ZZ                default:
-//ZZ                   ppIROp(e->Iex.Binop.op);
-//ZZ                   vpanic("Illegal element size in VQADDS");
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Sub8x16:
-//ZZ          case Iop_Sub16x8:
-//ZZ          case Iop_Sub32x4:
-//ZZ          case Iop_Sub64x2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Sub8x16: size = 0; break;
-//ZZ                case Iop_Sub16x8: size = 1; break;
-//ZZ                case Iop_Sub32x4: size = 2; break;
-//ZZ                case Iop_Sub64x2: size = 3; break;
-//ZZ                default:
-//ZZ                   ppIROp(e->Iex.Binop.op);
-//ZZ                   vpanic("Illegal element size in VSUB");
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Sub32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QSub8Ux16:
-//ZZ          case Iop_QSub16Ux8:
-//ZZ          case Iop_QSub32Ux4:
-//ZZ          case Iop_QSub64Ux2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QSub8Ux16: size = 0; break;
-//ZZ                case Iop_QSub16Ux8: size = 1; break;
-//ZZ                case Iop_QSub32Ux4: size = 2; break;
-//ZZ                case Iop_QSub64Ux2: size = 3; break;
-//ZZ                default:
-//ZZ                   ppIROp(e->Iex.Binop.op);
-//ZZ                   vpanic("Illegal element size in VQSUBU");
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QSub8Sx16:
-//ZZ          case Iop_QSub16Sx8:
-//ZZ          case Iop_QSub32Sx4:
-//ZZ          case Iop_QSub64Sx2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QSub8Sx16: size = 0; break;
-//ZZ                case Iop_QSub16Sx8: size = 1; break;
-//ZZ                case Iop_QSub32Sx4: size = 2; break;
-//ZZ                case Iop_QSub64Sx2: size = 3; break;
-//ZZ                default:
-//ZZ                   ppIROp(e->Iex.Binop.op);
-//ZZ                   vpanic("Illegal element size in VQSUBS");
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Max8Ux16:
-//ZZ          case Iop_Max16Ux8:
-//ZZ          case Iop_Max32Ux4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Max8Ux16: size = 0; break;
-//ZZ                case Iop_Max16Ux8: size = 1; break;
-//ZZ                case Iop_Max32Ux4: size = 2; break;
-//ZZ                default: vpanic("Illegal element size in VMAXU");
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Max8Sx16:
-//ZZ          case Iop_Max16Sx8:
-//ZZ          case Iop_Max32Sx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Max8Sx16: size = 0; break;
-//ZZ                case Iop_Max16Sx8: size = 1; break;
-//ZZ                case Iop_Max32Sx4: size = 2; break;
-//ZZ                default: vpanic("Illegal element size in VMAXU");
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Min8Ux16:
-//ZZ          case Iop_Min16Ux8:
-//ZZ          case Iop_Min32Ux4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Min8Ux16: size = 0; break;
-//ZZ                case Iop_Min16Ux8: size = 1; break;
-//ZZ                case Iop_Min32Ux4: size = 2; break;
-//ZZ                default: vpanic("Illegal element size in VMAXU");
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMINU,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Min8Sx16:
-//ZZ          case Iop_Min16Sx8:
-//ZZ          case Iop_Min32Sx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Min8Sx16: size = 0; break;
-//ZZ                case Iop_Min16Sx8: size = 1; break;
-//ZZ                case Iop_Min32Sx4: size = 2; break;
-//ZZ                default: vpanic("Illegal element size in VMAXU");
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMINS,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Sar8x16:
-//ZZ          case Iop_Sar16x8:
-//ZZ          case Iop_Sar32x4:
-//ZZ          case Iop_Sar64x2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             HReg argR2 = newVRegV(env);
-//ZZ             HReg zero = newVRegV(env);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Sar8x16: size = 0; break;
-//ZZ                case Iop_Sar16x8: size = 1; break;
-//ZZ                case Iop_Sar32x4: size = 2; break;
-//ZZ                case Iop_Sar64x2: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
-//ZZ                                            argR2, zero, argR, size, True));
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
-//ZZ                                           res, argL, argR2, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Sal8x16:
-//ZZ          case Iop_Sal16x8:
-//ZZ          case Iop_Sal32x4:
-//ZZ          case Iop_Sal64x2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Sal8x16: size = 0; break;
-//ZZ                case Iop_Sal16x8: size = 1; break;
-//ZZ                case Iop_Sal32x4: size = 2; break;
-//ZZ                case Iop_Sal64x2: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
-//ZZ                                           res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Shr8x16:
-//ZZ          case Iop_Shr16x8:
-//ZZ          case Iop_Shr32x4:
-//ZZ          case Iop_Shr64x2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             HReg argR2 = newVRegV(env);
-//ZZ             HReg zero = newVRegV(env);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Shr8x16: size = 0; break;
-//ZZ                case Iop_Shr16x8: size = 1; break;
-//ZZ                case Iop_Shr32x4: size = 2; break;
-//ZZ                case Iop_Shr64x2: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
-//ZZ                                            argR2, zero, argR, size, True));
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
-//ZZ                                           res, argL, argR2, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Shl8x16:
-//ZZ          case Iop_Shl16x8:
-//ZZ          case Iop_Shl32x4:
-//ZZ          case Iop_Shl64x2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_Shl8x16: size = 0; break;
-//ZZ                case Iop_Shl16x8: size = 1; break;
-//ZZ                case Iop_Shl32x4: size = 2; break;
-//ZZ                case Iop_Shl64x2: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
-//ZZ                                           res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QShl8x16:
-//ZZ          case Iop_QShl16x8:
-//ZZ          case Iop_QShl32x4:
-//ZZ          case Iop_QShl64x2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QShl8x16: size = 0; break;
-//ZZ                case Iop_QShl16x8: size = 1; break;
-//ZZ                case Iop_QShl32x4: size = 2; break;
-//ZZ                case Iop_QShl64x2: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VQSHL,
-//ZZ                                           res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QSal8x16:
-//ZZ          case Iop_QSal16x8:
-//ZZ          case Iop_QSal32x4:
-//ZZ          case Iop_QSal64x2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QSal8x16: size = 0; break;
-//ZZ                case Iop_QSal16x8: size = 1; break;
-//ZZ                case Iop_QSal32x4: size = 2; break;
-//ZZ                case Iop_QSal64x2: size = 3; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NShift(ARMneon_VQSAL,
-//ZZ                                           res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QShlN8x16:
-//ZZ          case Iop_QShlN16x8:
-//ZZ          case Iop_QShlN32x4:
-//ZZ          case Iop_QShlN64x2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             UInt size, imm;
-//ZZ             if (e->Iex.Binop.arg2->tag != Iex_Const ||
-//ZZ                 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
-//ZZ                vpanic("ARM taget supports Iop_QShlNAxB with constant "
-//ZZ                       "second argument only\n");
-//ZZ             }
-//ZZ             imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QShlN8x16: size = 8 | imm; break;
-//ZZ                case Iop_QShlN16x8: size = 16 | imm; break;
-//ZZ                case Iop_QShlN32x4: size = 32 | imm; break;
-//ZZ                case Iop_QShlN64x2: size = 64 | imm; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU,
-//ZZ                                           res, argL, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QShlN8Sx16:
-//ZZ          case Iop_QShlN16Sx8:
-//ZZ          case Iop_QShlN32Sx4:
-//ZZ          case Iop_QShlN64Sx2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             UInt size, imm;
-//ZZ             if (e->Iex.Binop.arg2->tag != Iex_Const ||
-//ZZ                 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
-//ZZ                vpanic("ARM taget supports Iop_QShlNASxB with constant "
-//ZZ                       "second argument only\n");
-//ZZ             }
-//ZZ             imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QShlN8Sx16: size = 8 | imm; break;
-//ZZ                case Iop_QShlN16Sx8: size = 16 | imm; break;
-//ZZ                case Iop_QShlN32Sx4: size = 32 | imm; break;
-//ZZ                case Iop_QShlN64Sx2: size = 64 | imm; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS,
-//ZZ                                           res, argL, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_QShlNsatSS8x16:
-//ZZ          case Iop_QShlNsatSS16x8:
-//ZZ          case Iop_QShlNsatSS32x4:
-//ZZ          case Iop_QShlNsatSS64x2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             UInt size, imm;
-//ZZ             if (e->Iex.Binop.arg2->tag != Iex_Const ||
-//ZZ                 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
-//ZZ                vpanic("ARM taget supports Iop_QShlNAxB with constant "
-//ZZ                       "second argument only\n");
-//ZZ             }
-//ZZ             imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_QShlNsatSS8x16: size = 8 | imm; break;
-//ZZ                case Iop_QShlNsatSS16x8: size = 16 | imm; break;
-//ZZ                case Iop_QShlNsatSS32x4: size = 32 | imm; break;
-//ZZ                case Iop_QShlNsatSS64x2: size = 64 | imm; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS,
-//ZZ                                           res, argL, size, True));
-//ZZ             return res;
-//ZZ          }
          case Iop_ShrN64x2: case Iop_ShrN32x4:
          case Iop_ShrN16x8: case Iop_ShrN8x16:
          case Iop_SarN64x2: case Iop_SarN32x4:
@@ -5896,314 +2739,6 @@
             return dst;
          }
 
-//ZZ          case Iop_CmpGT8Ux16:
-//ZZ          case Iop_CmpGT16Ux8:
-//ZZ          case Iop_CmpGT32Ux4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_CmpGT8Ux16: size = 0; break;
-//ZZ                case Iop_CmpGT16Ux8: size = 1; break;
-//ZZ                case Iop_CmpGT32Ux4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VCGTU,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpGT8Sx16:
-//ZZ          case Iop_CmpGT16Sx8:
-//ZZ          case Iop_CmpGT32Sx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_CmpGT8Sx16: size = 0; break;
-//ZZ                case Iop_CmpGT16Sx8: size = 1; break;
-//ZZ                case Iop_CmpGT32Sx4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpEQ8x16:
-//ZZ          case Iop_CmpEQ16x8:
-//ZZ          case Iop_CmpEQ32x4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size;
-//ZZ             switch (e->Iex.Binop.op) {
-//ZZ                case Iop_CmpEQ8x16: size = 0; break;
-//ZZ                case Iop_CmpEQ16x8: size = 1; break;
-//ZZ                case Iop_CmpEQ32x4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Mul8x16:
-//ZZ          case Iop_Mul16x8:
-//ZZ          case Iop_Mul32x4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Mul8x16: size = 0; break;
-//ZZ                case Iop_Mul16x8: size = 1; break;
-//ZZ                case Iop_Mul32x4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMUL,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Mul32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Mull8Ux8:
-//ZZ          case Iop_Mull16Ux4:
-//ZZ          case Iop_Mull32Ux2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Mull8Ux8: size = 0; break;
-//ZZ                case Iop_Mull16Ux4: size = 1; break;
-//ZZ                case Iop_Mull32Ux2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMULLU,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_Mull8Sx8:
-//ZZ          case Iop_Mull16Sx4:
-//ZZ          case Iop_Mull32Sx2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_Mull8Sx8: size = 0; break;
-//ZZ                case Iop_Mull16Sx4: size = 1; break;
-//ZZ                case Iop_Mull32Sx2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMULLS,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_QDMulHi16Sx8:
-//ZZ          case Iop_QDMulHi32Sx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_QDMulHi16Sx8: size = 1; break;
-//ZZ                case Iop_QDMulHi32Sx4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_QRDMulHi16Sx8:
-//ZZ          case Iop_QRDMulHi32Sx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_QRDMulHi16Sx8: size = 1; break;
-//ZZ                case Iop_QRDMulHi32Sx4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_QDMulLong16Sx4:
-//ZZ          case Iop_QDMulLong32Sx2: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_QDMulLong16Sx4: size = 1; break;
-//ZZ                case Iop_QDMulLong32Sx2: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULL,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PolynomialMul8x16: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMULP,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Max32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF,
-//ZZ                                            res, argL, argR, 2, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_Min32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMINF,
-//ZZ                                            res, argL, argR, 2, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PwMax32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF,
-//ZZ                                            res, argL, argR, 2, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_PwMin32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF,
-//ZZ                                            res, argL, argR, 2, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpGT32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF,
-//ZZ                                            res, argL, argR, 2, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpGE32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF,
-//ZZ                                            res, argL, argR, 2, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_CmpEQ32Fx4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF,
-//ZZ                                            res, argL, argR, 2, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ 
-//ZZ          case Iop_PolynomialMull8x8: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VMULLP,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          case Iop_F32ToFixed32Ux4_RZ:
-//ZZ          case Iop_F32ToFixed32Sx4_RZ:
-//ZZ          case Iop_Fixed32UToF32x4_RN:
-//ZZ          case Iop_Fixed32SToF32x4_RN: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg arg = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             ARMNeonUnOp op;
-//ZZ             UInt imm6;
-//ZZ             if (e->Iex.Binop.arg2->tag != Iex_Const ||
-//ZZ                typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
-//ZZ                   vpanic("ARM supports FP <-> Fixed conversion with constant "
-//ZZ                          "second argument less than 33 only\n");
-//ZZ             }
-//ZZ             imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
-//ZZ             vassert(imm6 <= 32 && imm6 > 0);
-//ZZ             imm6 = 64 - imm6;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_F32ToFixed32Ux4_RZ: op = ARMneon_VCVTFtoFixedU; break;
-//ZZ                case Iop_F32ToFixed32Sx4_RZ: op = ARMneon_VCVTFtoFixedS; break;
-//ZZ                case Iop_Fixed32UToF32x4_RN: op = ARMneon_VCVTFixedUtoF; break;
-//ZZ                case Iop_Fixed32SToF32x4_RN: op = ARMneon_VCVTFixedStoF; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          /*
-//ZZ          FIXME remove if not used
-//ZZ          case Iop_VDup8x16:
-//ZZ          case Iop_VDup16x8:
-//ZZ          case Iop_VDup32x4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
-//ZZ             UInt imm4;
-//ZZ             UInt index;
-//ZZ             if (e->Iex.Binop.arg2->tag != Iex_Const ||
-//ZZ                typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
-//ZZ                   vpanic("ARM supports Iop_VDup with constant "
-//ZZ                          "second argument less than 16 only\n");
-//ZZ             }
-//ZZ             index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_VDup8x16: imm4 = (index << 1) + 1; break;
-//ZZ                case Iop_VDup16x8: imm4 = (index << 2) + 2; break;
-//ZZ                case Iop_VDup32x4: imm4 = (index << 3) + 4; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             if (imm4 >= 16) {
-//ZZ                vpanic("ARM supports Iop_VDup with constant "
-//ZZ                       "second argument less than 16 only\n");
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NUnary(ARMneon_VDUP,
-//ZZ                                           res, argL, imm4, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          */
-//ZZ          case Iop_PwAdd8x16:
-//ZZ          case Iop_PwAdd16x8:
-//ZZ          case Iop_PwAdd32x4: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
-//ZZ             HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
-//ZZ             UInt size = 0;
-//ZZ             switch(e->Iex.Binop.op) {
-//ZZ                case Iop_PwAdd8x16: size = 0; break;
-//ZZ                case Iop_PwAdd16x8: size = 1; break;
-//ZZ                case Iop_PwAdd32x4: size = 2; break;
-//ZZ                default: vassert(0);
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VPADD,
-//ZZ                                            res, argL, argR, size, True));
-//ZZ             return res;
-//ZZ          }
          /* ... */
          default:
             break;
@@ -6232,43 +2767,8 @@
          addInstr(env, ARM64Instr_VBinV(vecbop, dst, argL, argR));
          return dst;
       }
-
-//ZZ       switch (triop->op) {
-//ZZ          case Iop_ExtractV128: {
-//ZZ             HReg res = newVRegV(env);
-//ZZ             HReg argL = iselNeonExpr(env, triop->arg1);
-//ZZ             HReg argR = iselNeonExpr(env, triop->arg2);
-//ZZ             UInt imm4;
-//ZZ             if (triop->arg3->tag != Iex_Const ||
-//ZZ                 typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) {
-//ZZ                vpanic("ARM target supports Iop_ExtractV128 with constant "
-//ZZ                       "third argument less than 16 only\n");
-//ZZ             }
-//ZZ             imm4 = triop->arg3->Iex.Const.con->Ico.U8;
-//ZZ             if (imm4 >= 16) {
-//ZZ                vpanic("ARM target supports Iop_ExtractV128 with constant "
-//ZZ                       "third argument less than 16 only\n");
-//ZZ             }
-//ZZ             addInstr(env, ARMInstr_NBinary(ARMneon_VEXT,
-//ZZ                                            res, argL, argR, imm4, True));
-//ZZ             return res;
-//ZZ          }
-//ZZ          default:
-//ZZ             break;
-//ZZ       }
    }
 
-//ZZ    if (e->tag == Iex_ITE) { // VFD
-//ZZ       ARMCondCode cc;
-//ZZ       HReg r1  = iselNeonExpr(env, e->Iex.ITE.iftrue);
-//ZZ       HReg r0  = iselNeonExpr(env, e->Iex.ITE.iffalse);
-//ZZ       HReg dst = newVRegV(env);
-//ZZ       addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, r1, 4, True));
-//ZZ       cc = iselCondCode(env, e->Iex.ITE.cond);
-//ZZ       addInstr(env, ARMInstr_NCMovQ(cc ^ 1, dst, r0));
-//ZZ       return dst;
-//ZZ    }
-
   v128_expr_bad:
    ppIRExpr(e);
    vpanic("iselV128Expr_wrk");
@@ -6337,17 +2837,6 @@
 
    if (e->tag == Iex_Unop) {
       switch (e->Iex.Unop.op) {
-//ZZ          case Iop_ReinterpI64asF64: {
-//ZZ             if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
-//ZZ                return iselNeon64Expr(env, e->Iex.Unop.arg);
-//ZZ             } else {
-//ZZ                HReg srcHi, srcLo;
-//ZZ                HReg dst = newVRegD(env);
-//ZZ                iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg);
-//ZZ                addInstr(env, ARMInstr_VXferD(True/*toD*/, dst, srcHi, srcLo));
-//ZZ                return dst;
-//ZZ             }
-//ZZ          }
          case Iop_NegF64: {
             HReg src = iselDblExpr(env, e->Iex.Unop.arg);
             HReg dst = newVRegD(env);
@@ -6434,19 +2923,6 @@
       }
    }
 
-//ZZ    if (e->tag == Iex_ITE) { // VFD
-//ZZ       if (ty == Ity_F64
-//ZZ           && typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) {
-//ZZ          HReg r1  = iselDblExpr(env, e->Iex.ITE.iftrue);
-//ZZ          HReg r0  = iselDblExpr(env, e->Iex.ITE.iffalse);
-//ZZ          HReg dst = newVRegD(env);
-//ZZ          addInstr(env, ARMInstr_VUnaryD(ARMvfpu_COPY, dst, r1));
-//ZZ          ARMCondCode cc = iselCondCode(env, e->Iex.ITE.cond);
-//ZZ          addInstr(env, ARMInstr_VCMovD(cc ^ 1, dst, r0));
-//ZZ          return dst;
-//ZZ       }
-//ZZ    }
-
    ppIRExpr(e);
    vpanic("iselDblExpr_wrk");
 }
@@ -6499,15 +2975,6 @@
       }
    }
 
-//ZZ    if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {
-//ZZ       ARMAModeV* am;
-//ZZ       HReg res = newVRegF(env);
-//ZZ       vassert(e->Iex.Load.ty == Ity_F32);
-//ZZ       am = iselIntExpr_AModeV(env, e->Iex.Load.addr);
-//ZZ       addInstr(env, ARMInstr_VLdStS(True/*isLoad*/, res, am));
-//ZZ       return res;
-//ZZ    }
-
    if (e->tag == Iex_Get) {
       Int offs = e->Iex.Get.offset;
       if (offs >= 0 && offs < 16384 && 0 == (offs & 3)) {
@@ -6520,12 +2987,6 @@
 
    if (e->tag == Iex_Unop) {
       switch (e->Iex.Unop.op) {
-//ZZ          case Iop_ReinterpI32asF32: {
-//ZZ             HReg dst = newVRegF(env);
-//ZZ             HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
-//ZZ             addInstr(env, ARMInstr_VXferS(True/*toS*/, dst, src));
-//ZZ             return dst;
-//ZZ          }
          case Iop_NegF32: {
             HReg src = iselFltExpr(env, e->Iex.Unop.arg);
             HReg dst = newVRegD(env);
@@ -6609,21 +3070,6 @@
       }
    }
 
-//ZZ 
-//ZZ    if (e->tag == Iex_ITE) { // VFD
-//ZZ       if (ty == Ity_F32
-//ZZ           && typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) {
-//ZZ          ARMCondCode cc;
-//ZZ          HReg r1  = iselFltExpr(env, e->Iex.ITE.iftrue);
-//ZZ          HReg r0  = iselFltExpr(env, e->Iex.ITE.iffalse);
-//ZZ          HReg dst = newVRegF(env);
-//ZZ          addInstr(env, ARMInstr_VUnaryS(ARMvfpu_COPY, dst, r1));
-//ZZ          cc = iselCondCode(env, e->Iex.ITE.cond);
-//ZZ          addInstr(env, ARMInstr_VCMovS(cc ^ 1, dst, r0));
-//ZZ          return dst;
-//ZZ       }
-//ZZ    }
-
    ppIRExpr(e);
    vpanic("iselFltExpr_wrk");
 }
@@ -6799,141 +3245,9 @@
          addInstr(env, ARM64Instr_VLdStS(False/*!isLoad*/, sD, addr, 0));
          return;
       }
-
-//ZZ       if (tyd == Ity_I16) {
-//ZZ          HReg       rD = iselIntExpr_R(env, stmt->Ist.Store.data);
-//ZZ          ARMAMode2* am = iselIntExpr_AMode2(env, stmt->Ist.Store.addr);
-//ZZ          addInstr(env, ARMInstr_LdSt16(ARMcc_AL,
-//ZZ                                        False/*!isLoad*/,
-//ZZ                                        False/*!isSignedLoad*/, rD, am));
-//ZZ          return;
-//ZZ       }
-//ZZ       if (tyd == Ity_I8) {
-//ZZ          HReg       rD = iselIntExpr_R(env, stmt->Ist.Store.data);
-//ZZ          ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.Store.addr);
-//ZZ          addInstr(env, ARMInstr_LdSt8U(ARMcc_AL, False/*!isLoad*/, rD, am));
-//ZZ          return;
-//ZZ       }
-//ZZ       if (tyd == Ity_I64) {
-//ZZ          if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
-//ZZ             HReg dD = iselNeon64Expr(env, stmt->Ist.Store.data);
-//ZZ             ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr);
-//ZZ             addInstr(env, ARMInstr_NLdStD(False, dD, am));
-//ZZ          } else {
-//ZZ             HReg rDhi, rDlo, rA;
-//ZZ             iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Store.data);
-//ZZ             rA = iselIntExpr_R(env, stmt->Ist.Store.addr);
-//ZZ             addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!load*/, rDhi,
-//ZZ                                           ARMAMode1_RI(rA,4)));
-//ZZ             addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!load*/, rDlo,
-//ZZ                                           ARMAMode1_RI(rA,0)));
-//ZZ          }
-//ZZ          return;
-//ZZ       }
-//ZZ       if (tyd == Ity_F64) {
-//ZZ          HReg       dD = iselDblExpr(env, stmt->Ist.Store.data);
-//ZZ          ARMAModeV* am = iselIntExpr_AModeV(env, stmt->Ist.Store.addr);
-//ZZ          addInstr(env, ARMInstr_VLdStD(False/*!isLoad*/, dD, am));
-//ZZ          return;
-//ZZ       }
-//ZZ       if (tyd == Ity_F32) {
-//ZZ          HReg       fD = iselFltExpr(env, stmt->Ist.Store.data);
-//ZZ          ARMAModeV* am = iselIntExpr_AModeV(env, stmt->Ist.Store.addr);
-//ZZ          addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, fD, am));
-//ZZ          return;
-//ZZ       }
-//ZZ       if (tyd == Ity_V128) {
-//ZZ          HReg       qD = iselNeonExpr(env, stmt->Ist.Store.data);
-//ZZ          ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr);
-//ZZ          addInstr(env, ARMInstr_NLdStQ(False, qD, am));
-//ZZ          return;
-//ZZ       }
-
       break;
    }
 
-//ZZ    /* --------- CONDITIONAL STORE --------- */
-//ZZ    /* conditional little-endian write to memory */
-//ZZ    case Ist_StoreG: {
-//ZZ       IRStoreG* sg   = stmt->Ist.StoreG.details;
-//ZZ       IRType    tya  = typeOfIRExpr(env->type_env, sg->addr);
-//ZZ       IRType    tyd  = typeOfIRExpr(env->type_env, sg->data);
-//ZZ       IREndness end  = sg->end;
-//ZZ 
-//ZZ       if (tya != Ity_I32 || end != Iend_LE) 
-//ZZ          goto stmt_fail;
-//ZZ 
-//ZZ       switch (tyd) {
-//ZZ          case Ity_I8:
-//ZZ          case Ity_I32: {
-//ZZ             HReg        rD = iselIntExpr_R(env, sg->data);
-//ZZ             ARMAMode1*  am = iselIntExpr_AMode1(env, sg->addr);
-//ZZ             ARMCondCode cc = iselCondCode(env, sg->guard);
-//ZZ             addInstr(env, (tyd == Ity_I32 ? ARMInstr_LdSt32 : ARMInstr_LdSt8U)
-//ZZ                              (cc, False/*!isLoad*/, rD, am));
-//ZZ             return;
-//ZZ          }
-//ZZ          case Ity_I16: {
-//ZZ             HReg        rD = iselIntExpr_R(env, sg->data);
-//ZZ             ARMAMode2*  am = iselIntExpr_AMode2(env, sg->addr);
-//ZZ             ARMCondCode cc = iselCondCode(env, sg->guard);
-//ZZ             addInstr(env, ARMInstr_LdSt16(cc, 
-//ZZ                                           False/*!isLoad*/,
-//ZZ                                           False/*!isSignedLoad*/, rD, am));
-//ZZ             return;
-//ZZ          }
-//ZZ          default:
-//ZZ             break;
-//ZZ       }
-//ZZ       break;
-//ZZ    }
-//ZZ 
-//ZZ    /* --------- CONDITIONAL LOAD --------- */
-//ZZ    /* conditional little-endian load from memory */
-//ZZ    case Ist_LoadG: {
-//ZZ       IRLoadG*  lg   = stmt->Ist.LoadG.details;
-//ZZ       IRType    tya  = typeOfIRExpr(env->type_env, lg->addr);
-//ZZ       IREndness end  = lg->end;
-//ZZ 
-//ZZ       if (tya != Ity_I32 || end != Iend_LE) 
-//ZZ          goto stmt_fail;
-//ZZ 
-//ZZ       switch (lg->cvt) {
-//ZZ          case ILGop_8Uto32:
-//ZZ          case ILGop_Ident32: {
-//ZZ             HReg        rAlt = iselIntExpr_R(env, lg->alt);
-//ZZ             ARMAMode1*  am   = iselIntExpr_AMode1(env, lg->addr);
-//ZZ             HReg        rD   = lookupIRTemp(env, lg->dst);
-//ZZ             addInstr(env, mk_iMOVds_RR(rD, rAlt));
-//ZZ             ARMCondCode cc   = iselCondCode(env, lg->guard);
-//ZZ             addInstr(env, (lg->cvt == ILGop_Ident32 ? ARMInstr_LdSt32
-//ZZ                                                     : ARMInstr_LdSt8U)
-//ZZ                              (cc, True/*isLoad*/, rD, am));
-//ZZ             return;
-//ZZ          }
-//ZZ          case ILGop_16Sto32:
-//ZZ          case ILGop_16Uto32:
-//ZZ          case ILGop_8Sto32: {
-//ZZ             HReg        rAlt = iselIntExpr_R(env, lg->alt);
-//ZZ             ARMAMode2*  am   = iselIntExpr_AMode2(env, lg->addr);
-//ZZ             HReg        rD   = lookupIRTemp(env, lg->dst);
-//ZZ             addInstr(env, mk_iMOVds_RR(rD, rAlt));
-//ZZ             ARMCondCode cc   = iselCondCode(env, lg->guard);
-//ZZ             if (lg->cvt == ILGop_8Sto32) {
-//ZZ                addInstr(env, ARMInstr_Ld8S(cc, rD, am));
-//ZZ             } else {
-//ZZ                vassert(lg->cvt == ILGop_16Sto32 || lg->cvt == ILGop_16Uto32);
-//ZZ                Bool sx = lg->cvt == ILGop_16Sto32;
-//ZZ                addInstr(env, ARMInstr_LdSt16(cc, True/*isLoad*/, sx, rD, am));
-//ZZ             }
-//ZZ             return;
-//ZZ          }
-//ZZ          default:
-//ZZ             break;
-//ZZ       }
-//ZZ       break;
-//ZZ    }
-
    /* --------- PUT --------- */
    /* write guest state, fixed offset */
    case Ist_Put: {
@@ -6982,43 +3296,6 @@
          return;
       }
 
-//ZZ        if (tyd == Ity_I64) {
-//ZZ           if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
-//ZZ              HReg addr = newVRegI(env);
-//ZZ              HReg qD = iselNeon64Expr(env, stmt->Ist.Put.data);
-//ZZ              addInstr(env, ARMInstr_Add32(addr, hregARM_R8(),
-//ZZ                                                 stmt->Ist.Put.offset));
-//ZZ              addInstr(env, ARMInstr_NLdStD(False, qD, mkARMAModeN_R(addr)));
-//ZZ           } else {
-//ZZ              HReg rDhi, rDlo;
-//ZZ              ARMAMode1* am0 = ARMAMode1_RI(hregARM_R8(),
-//ZZ                                            stmt->Ist.Put.offset + 0);
-//ZZ              ARMAMode1* am4 = ARMAMode1_RI(hregARM_R8(),
-//ZZ                                            stmt->Ist.Put.offset + 4);
-//ZZ              iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Put.data);
-//ZZ              addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/,
-//ZZ                                            rDhi, am4));
-//ZZ              addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/,
-//ZZ                                            rDlo, am0));
-//ZZ           }
-//ZZ           return;
-//ZZ        }
-//ZZ        if (tyd == Ity_F64) {
-//ZZ           // XXX This won't work if offset > 1020 or is not 0 % 4.
-//ZZ           // In which case we'll have to generate more longwinded code.
-//ZZ           ARMAModeV* am = mkARMAModeV(hregARM_R8(), stmt->Ist.Put.offset);
-//ZZ           HReg       rD = iselDblExpr(env, stmt->Ist.Put.data);
-//ZZ           addInstr(env, ARMInstr_VLdStD(False/*!isLoad*/, rD, am));
-//ZZ           return;
-//ZZ        }
-//ZZ        if (tyd == Ity_F32) {
-//ZZ           // XXX This won't work if offset > 1020 or is not 0 % 4.
-//ZZ           // In which case we'll have to generate more longwinded code.
-//ZZ           ARMAModeV* am = mkARMAModeV(hregARM_R8(), stmt->Ist.Put.offset);
-//ZZ           HReg       rD = iselFltExpr(env, stmt->Ist.Put.data);
-//ZZ           addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, rD, am));
-//ZZ           return;
-//ZZ        }
       break;
    }
 
@@ -7228,9 +3505,6 @@
          case Imbe_Fence:
             addInstr(env, ARM64Instr_MFence());
             return;
-//ZZ          case Imbe_CancelReservation:
-//ZZ             addInstr(env, ARMInstr_CLREX());
-//ZZ             return;
          default:
             break;
       }
@@ -7278,25 +3552,6 @@
          return;
       }
 
-//ZZ       /* Case: assisted transfer to arbitrary address */
-//ZZ       switch (stmt->Ist.Exit.jk) {
-//ZZ          /* Keep this list in sync with that in iselNext below */
-//ZZ          case Ijk_ClientReq:
-//ZZ          case Ijk_NoDecode:
-//ZZ          case Ijk_NoRedir:
-//ZZ          case Ijk_Sys_syscall:
-//ZZ          case Ijk_InvalICache:
-//ZZ          case Ijk_Yield:
-//ZZ          {
-//ZZ             HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
-//ZZ             addInstr(env, ARMInstr_XAssisted(r, amR15T, cc,
-//ZZ                                              stmt->Ist.Exit.jk));
-//ZZ             return;
-//ZZ          }
-//ZZ          default:
-//ZZ             break;
-//ZZ       }
-
       /* Do we ever expect to see any other kind? */
       goto stmt_fail;
    }
@@ -7379,7 +3634,6 @@
       case Ijk_Sys_syscall:
       case Ijk_InvalICache:
       case Ijk_FlushDCache:
-//ZZ       case Ijk_Yield:
       {
          HReg        r    = iselIntExpr_R(env, next);
          ARM64AMode* amPC = mk_baseblock_64bit_access_amode(offsIP);