drd/tests/unit_vc.stderr.exp

vc1: [ 3: 7, 5: 8 ]
vc2: [ 1: 4, 3: 9 ]
vc3: [ 1: 4, 3: 9, 5: 8 ]
vc_lte(vc1, vc2) = 0, vc_lte(vc1, vc3) = 1, vc_lte(vc2, vc3) = 1
vc_lte([ 1: 3, 2: 1 ], [ 1: 4 ]) = 0 sw 0