The following regression tests failures occur on PPC64 little endian only.

The regression test none/tests/jm_vec/isa_2_07 has failures on the lxsiwax and
lxsiwzx instructions. They are loads and the the results are correct for
big endian but not little endian. The little endian result matches the
expected big endian result. 

The regresssion test none/tests/test_isa_2_07_part2 has a failure with the
vbpermq instruction. The little endian result matches the expected result for
big endian. The upper and lower 64 bits of the result are not swapped correctly
for little endian.

This commit fixes these issues.

The bugzilla for the issue is 346270.

git-svn-id: svn://svn.valgrind.org/vex/trunk@3134 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/priv/guest_ppc_toIR.c b/priv/guest_ppc_toIR.c
index 3ee57da..a098f6f 100644
--- a/priv/guest_ppc_toIR.c
+++ b/priv/guest_ppc_toIR.c
@@ -15250,7 +15250,12 @@
    {
       IRExpr * exp;
       DIP("lxsiwzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
-      exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) );
+
+      if (host_endness == VexEndnessLE)
+         exp = unop( Iop_64to32, load( Ity_I64, mkexpr( EA ) ) );
+      else
+         exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) );
+
       putVSReg( XT, binop( Iop_64HLtoV128,
                            unop( Iop_32Uto64, exp),
                            mkU64(0) ) );
@@ -15260,7 +15265,12 @@
    {
       IRExpr * exp;
       DIP("lxsiwax %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
-      exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) );
+
+      if (host_endness == VexEndnessLE)
+         exp = unop( Iop_64to32, load( Ity_I64, mkexpr( EA ) ) );
+      else
+         exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) );
+
       putVSReg( XT, binop( Iop_64HLtoV128,
                            unop( Iop_32Sto64, exp),
                            mkU64(0) ) );
@@ -17844,11 +17854,18 @@
                                              mkexpr( vA ),
                                              mkexpr( idx ) ) ),
                                mkU8( 127 ) ) ) );
-         res = binop( Iop_OrV128,
-                      res,
-                      binop( Iop_ShlV128,
-                             mkexpr( perm_bit ),
-                             mkU8( i ) ) );
+         if (host_endness == VexEndnessLE)
+            res = binop( Iop_OrV128,
+                         res,
+                         binop( Iop_ShlV128,
+                                mkexpr( perm_bit ),
+                                mkU8( i + 64) ) );
+         else
+            res = binop( Iop_OrV128,
+                         res,
+                         binop( Iop_ShlV128,
+                                mkexpr( perm_bit ),
+                                mkU8( i ) ) );
          vB_expr = binop( Iop_ShrV128, vB_expr, mkU8( 8 ) );
       }
       putVReg( vRT_addr, res);