commit 0657e9a8533dc93d828fefe926ab4c3307fd27fd
author sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Thu Jul 03 11:01:38 2014 +0000
committer sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Thu Jul 03 11:01:38 2014 +0000
tree a43e8810001fd5bfe519876dbe6a9f3683ee09b5
parent a5a6b75098f4c9bc11d6d7e3e03d97636d73261e

arm32: support (ARM) PLDW [reg, #imm].  The non-W variant was already
accepted.  Fixes #323179.  (vasily.golubev@gmail.com)



git-svn-id: svn://svn.valgrind.org/vex/trunk@2896 8f6e269a-dfd6-0310-a8e1-e2731360e62c

priv/guest_arm_toIR.c

diff --git a/priv/guest_arm_toIR.c b/priv/guest_arm_toIR.c
index d1763d3..c993e4b 100644
--- a/priv/guest_arm_toIR.c
+++ b/priv/guest_arm_toIR.c
@@ -14400,13 +14400,14 @@
    // Should only be called for NV instructions
    vassert(BITS4(1,1,1,1) == INSN_COND);
 
-   /* ------------------------ pld ------------------------ */
-   if (BITS8(0,1,0,1, 0, 1,0,1) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,1))
+   /* ------------------------ pld{w} ------------------------ */
+   if (BITS8(0,1,0,1, 0,0, 0,1) == (INSN(27,20) & BITS8(1,1,1,1, 0,0, 1,1))
        && BITS4(1,1,1,1) == INSN(15,12)) {
       UInt rN    = INSN(19,16);
       UInt imm12 = INSN(11,0);
       UInt bU    = INSN(23,23);
-      DIP("pld [r%u, #%c%u]\n", rN, bU ? '+' : '-', imm12);
+      UInt bR    = INSN(22,22);
+      DIP("pld%c [r%u, #%c%u]\n", bR ? ' ' : 'w', rN, bU ? '+' : '-', imm12);
       return True;
    }